1 /* 2 * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "jvm.h" 27 #include "asm/assembler.hpp" 28 #include "asm/assembler.inline.hpp" 29 #include "compiler/compiler_globals.hpp" 30 #include "compiler/disassembler.hpp" 31 #include "gc/shared/barrierSet.hpp" 32 #include "gc/shared/barrierSetAssembler.hpp" 33 #include "gc/shared/collectedHeap.inline.hpp" 34 #include "gc/shared/tlab_globals.hpp" 35 #include "interpreter/bytecodeHistogram.hpp" 36 #include "interpreter/interpreter.hpp" 37 #include "logging/log.hpp" 38 #include "memory/resourceArea.hpp" 39 #include "memory/universe.hpp" 40 #include "oops/accessDecorators.hpp" 41 #include "oops/compressedKlass.inline.hpp" 42 #include "oops/compressedOops.inline.hpp" 43 #include "oops/klass.inline.hpp" 44 #include "prims/methodHandles.hpp" 45 #include "runtime/flags/flagSetting.hpp" 46 #include "runtime/interfaceSupport.inline.hpp" 47 #include "runtime/jniHandles.hpp" 48 #include "runtime/objectMonitor.hpp" 49 #include "runtime/os.hpp" 50 #include "runtime/safepoint.hpp" 51 #include "runtime/safepointMechanism.hpp" 52 #include "runtime/sharedRuntime.hpp" 53 #include "runtime/stubRoutines.hpp" 54 #include "runtime/thread.hpp" 55 #include "utilities/align.hpp" 56 #include "utilities/macros.hpp" 57 #include "crc32c.h" 58 59 #ifdef PRODUCT 60 #define BLOCK_COMMENT(str) /* nothing */ 61 #define STOP(error) stop(error) 62 #else 63 #define BLOCK_COMMENT(str) block_comment(str) 64 #define STOP(error) block_comment(error); stop(error) 65 #endif 66 67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 68 69 #ifdef ASSERT 70 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 71 #endif 72 73 static Assembler::Condition reverse[] = { 74 Assembler::noOverflow /* overflow = 0x0 */ , 75 Assembler::overflow /* noOverflow = 0x1 */ , 76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 78 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 79 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 80 Assembler::above /* belowEqual = 0x6 */ , 81 Assembler::belowEqual /* above = 0x7 */ , 82 Assembler::positive /* negative = 0x8 */ , 83 Assembler::negative /* positive = 0x9 */ , 84 Assembler::noParity /* parity = 0xa */ , 85 Assembler::parity /* noParity = 0xb */ , 86 Assembler::greaterEqual /* less = 0xc */ , 87 Assembler::less /* greaterEqual = 0xd */ , 88 Assembler::greater /* lessEqual = 0xe */ , 89 Assembler::lessEqual /* greater = 0xf, */ 90 91 }; 92 93 94 // Implementation of MacroAssembler 95 96 // First all the versions that have distinct versions depending on 32/64 bit 97 // Unless the difference is trivial (1 line or so). 98 99 #ifndef _LP64 100 101 // 32bit versions 102 103 Address MacroAssembler::as_Address(AddressLiteral adr) { 104 return Address(adr.target(), adr.rspec()); 105 } 106 107 Address MacroAssembler::as_Address(ArrayAddress adr) { 108 return Address::make_array(adr); 109 } 110 111 void MacroAssembler::call_VM_leaf_base(address entry_point, 112 int number_of_arguments) { 113 call(RuntimeAddress(entry_point)); 114 increment(rsp, number_of_arguments * wordSize); 115 } 116 117 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 118 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 119 } 120 121 122 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 123 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 124 } 125 126 void MacroAssembler::cmpoop(Address src1, jobject obj) { 127 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 128 } 129 130 void MacroAssembler::cmpoop(Register src1, jobject obj) { 131 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 132 } 133 134 void MacroAssembler::extend_sign(Register hi, Register lo) { 135 // According to Intel Doc. AP-526, "Integer Divide", p.18. 136 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 137 cdql(); 138 } else { 139 movl(hi, lo); 140 sarl(hi, 31); 141 } 142 } 143 144 void MacroAssembler::jC2(Register tmp, Label& L) { 145 // set parity bit if FPU flag C2 is set (via rax) 146 save_rax(tmp); 147 fwait(); fnstsw_ax(); 148 sahf(); 149 restore_rax(tmp); 150 // branch 151 jcc(Assembler::parity, L); 152 } 153 154 void MacroAssembler::jnC2(Register tmp, Label& L) { 155 // set parity bit if FPU flag C2 is set (via rax) 156 save_rax(tmp); 157 fwait(); fnstsw_ax(); 158 sahf(); 159 restore_rax(tmp); 160 // branch 161 jcc(Assembler::noParity, L); 162 } 163 164 // 32bit can do a case table jump in one instruction but we no longer allow the base 165 // to be installed in the Address class 166 void MacroAssembler::jump(ArrayAddress entry) { 167 jmp(as_Address(entry)); 168 } 169 170 // Note: y_lo will be destroyed 171 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 172 // Long compare for Java (semantics as described in JVM spec.) 173 Label high, low, done; 174 175 cmpl(x_hi, y_hi); 176 jcc(Assembler::less, low); 177 jcc(Assembler::greater, high); 178 // x_hi is the return register 179 xorl(x_hi, x_hi); 180 cmpl(x_lo, y_lo); 181 jcc(Assembler::below, low); 182 jcc(Assembler::equal, done); 183 184 bind(high); 185 xorl(x_hi, x_hi); 186 increment(x_hi); 187 jmp(done); 188 189 bind(low); 190 xorl(x_hi, x_hi); 191 decrementl(x_hi); 192 193 bind(done); 194 } 195 196 void MacroAssembler::lea(Register dst, AddressLiteral src) { 197 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 198 } 199 200 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 201 // leal(dst, as_Address(adr)); 202 // see note in movl as to why we must use a move 203 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 204 } 205 206 void MacroAssembler::leave() { 207 mov(rsp, rbp); 208 pop(rbp); 209 } 210 211 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 212 // Multiplication of two Java long values stored on the stack 213 // as illustrated below. Result is in rdx:rax. 214 // 215 // rsp ---> [ ?? ] \ \ 216 // .... | y_rsp_offset | 217 // [ y_lo ] / (in bytes) | x_rsp_offset 218 // [ y_hi ] | (in bytes) 219 // .... | 220 // [ x_lo ] / 221 // [ x_hi ] 222 // .... 223 // 224 // Basic idea: lo(result) = lo(x_lo * y_lo) 225 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 226 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 227 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 228 Label quick; 229 // load x_hi, y_hi and check if quick 230 // multiplication is possible 231 movl(rbx, x_hi); 232 movl(rcx, y_hi); 233 movl(rax, rbx); 234 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 235 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 236 // do full multiplication 237 // 1st step 238 mull(y_lo); // x_hi * y_lo 239 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 240 // 2nd step 241 movl(rax, x_lo); 242 mull(rcx); // x_lo * y_hi 243 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 244 // 3rd step 245 bind(quick); // note: rbx, = 0 if quick multiply! 246 movl(rax, x_lo); 247 mull(y_lo); // x_lo * y_lo 248 addl(rdx, rbx); // correct hi(x_lo * y_lo) 249 } 250 251 void MacroAssembler::lneg(Register hi, Register lo) { 252 negl(lo); 253 adcl(hi, 0); 254 negl(hi); 255 } 256 257 void MacroAssembler::lshl(Register hi, Register lo) { 258 // Java shift left long support (semantics as described in JVM spec., p.305) 259 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 260 // shift value is in rcx ! 261 assert(hi != rcx, "must not use rcx"); 262 assert(lo != rcx, "must not use rcx"); 263 const Register s = rcx; // shift count 264 const int n = BitsPerWord; 265 Label L; 266 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 267 cmpl(s, n); // if (s < n) 268 jcc(Assembler::less, L); // else (s >= n) 269 movl(hi, lo); // x := x << n 270 xorl(lo, lo); 271 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 272 bind(L); // s (mod n) < n 273 shldl(hi, lo); // x := x << s 274 shll(lo); 275 } 276 277 278 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 279 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 280 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 281 assert(hi != rcx, "must not use rcx"); 282 assert(lo != rcx, "must not use rcx"); 283 const Register s = rcx; // shift count 284 const int n = BitsPerWord; 285 Label L; 286 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 287 cmpl(s, n); // if (s < n) 288 jcc(Assembler::less, L); // else (s >= n) 289 movl(lo, hi); // x := x >> n 290 if (sign_extension) sarl(hi, 31); 291 else xorl(hi, hi); 292 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 293 bind(L); // s (mod n) < n 294 shrdl(lo, hi); // x := x >> s 295 if (sign_extension) sarl(hi); 296 else shrl(hi); 297 } 298 299 void MacroAssembler::movoop(Register dst, jobject obj) { 300 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 301 } 302 303 void MacroAssembler::movoop(Address dst, jobject obj) { 304 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 305 } 306 307 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 308 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 309 } 310 311 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 312 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 313 } 314 315 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 316 // scratch register is not used, 317 // it is defined to match parameters of 64-bit version of this method. 318 if (src.is_lval()) { 319 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 320 } else { 321 movl(dst, as_Address(src)); 322 } 323 } 324 325 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 326 movl(as_Address(dst), src); 327 } 328 329 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 330 movl(dst, as_Address(src)); 331 } 332 333 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 334 void MacroAssembler::movptr(Address dst, intptr_t src) { 335 movl(dst, src); 336 } 337 338 void MacroAssembler::pushoop(jobject obj) { 339 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 340 } 341 342 void MacroAssembler::pushklass(Metadata* obj) { 343 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 344 } 345 346 void MacroAssembler::pushptr(AddressLiteral src) { 347 if (src.is_lval()) { 348 push_literal32((int32_t)src.target(), src.rspec()); 349 } else { 350 pushl(as_Address(src)); 351 } 352 } 353 354 static void pass_arg0(MacroAssembler* masm, Register arg) { 355 masm->push(arg); 356 } 357 358 static void pass_arg1(MacroAssembler* masm, Register arg) { 359 masm->push(arg); 360 } 361 362 static void pass_arg2(MacroAssembler* masm, Register arg) { 363 masm->push(arg); 364 } 365 366 static void pass_arg3(MacroAssembler* masm, Register arg) { 367 masm->push(arg); 368 } 369 370 #ifndef PRODUCT 371 extern "C" void findpc(intptr_t x); 372 #endif 373 374 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 375 // In order to get locks to work, we need to fake a in_VM state 376 JavaThread* thread = JavaThread::current(); 377 JavaThreadState saved_state = thread->thread_state(); 378 thread->set_thread_state(_thread_in_vm); 379 if (ShowMessageBoxOnError) { 380 JavaThread* thread = JavaThread::current(); 381 JavaThreadState saved_state = thread->thread_state(); 382 thread->set_thread_state(_thread_in_vm); 383 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 384 ttyLocker ttyl; 385 BytecodeCounter::print(); 386 } 387 // To see where a verify_oop failed, get $ebx+40/X for this frame. 388 // This is the value of eip which points to where verify_oop will return. 389 if (os::message_box(msg, "Execution stopped, print registers?")) { 390 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 391 BREAKPOINT; 392 } 393 } 394 fatal("DEBUG MESSAGE: %s", msg); 395 } 396 397 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 398 ttyLocker ttyl; 399 FlagSetting fs(Debugging, true); 400 tty->print_cr("eip = 0x%08x", eip); 401 #ifndef PRODUCT 402 if ((WizardMode || Verbose) && PrintMiscellaneous) { 403 tty->cr(); 404 findpc(eip); 405 tty->cr(); 406 } 407 #endif 408 #define PRINT_REG(rax) \ 409 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 410 PRINT_REG(rax); 411 PRINT_REG(rbx); 412 PRINT_REG(rcx); 413 PRINT_REG(rdx); 414 PRINT_REG(rdi); 415 PRINT_REG(rsi); 416 PRINT_REG(rbp); 417 PRINT_REG(rsp); 418 #undef PRINT_REG 419 // Print some words near top of staack. 420 int* dump_sp = (int*) rsp; 421 for (int col1 = 0; col1 < 8; col1++) { 422 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 423 os::print_location(tty, *dump_sp++); 424 } 425 for (int row = 0; row < 16; row++) { 426 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 427 for (int col = 0; col < 8; col++) { 428 tty->print(" 0x%08x", *dump_sp++); 429 } 430 tty->cr(); 431 } 432 // Print some instructions around pc: 433 Disassembler::decode((address)eip-64, (address)eip); 434 tty->print_cr("--------"); 435 Disassembler::decode((address)eip, (address)eip+32); 436 } 437 438 void MacroAssembler::stop(const char* msg) { 439 ExternalAddress message((address)msg); 440 // push address of message 441 pushptr(message.addr()); 442 { Label L; call(L, relocInfo::none); bind(L); } // push eip 443 pusha(); // push registers 444 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 445 hlt(); 446 } 447 448 void MacroAssembler::warn(const char* msg) { 449 push_CPU_state(); 450 451 ExternalAddress message((address) msg); 452 // push address of message 453 pushptr(message.addr()); 454 455 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 456 addl(rsp, wordSize); // discard argument 457 pop_CPU_state(); 458 } 459 460 void MacroAssembler::print_state() { 461 { Label L; call(L, relocInfo::none); bind(L); } // push eip 462 pusha(); // push registers 463 464 push_CPU_state(); 465 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 466 pop_CPU_state(); 467 468 popa(); 469 addl(rsp, wordSize); 470 } 471 472 #else // _LP64 473 474 // 64 bit versions 475 476 Address MacroAssembler::as_Address(AddressLiteral adr) { 477 // amd64 always does this as a pc-rel 478 // we can be absolute or disp based on the instruction type 479 // jmp/call are displacements others are absolute 480 assert(!adr.is_lval(), "must be rval"); 481 assert(reachable(adr), "must be"); 482 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 483 484 } 485 486 Address MacroAssembler::as_Address(ArrayAddress adr) { 487 AddressLiteral base = adr.base(); 488 lea(rscratch1, base); 489 Address index = adr.index(); 490 assert(index._disp == 0, "must not have disp"); // maybe it can? 491 Address array(rscratch1, index._index, index._scale, index._disp); 492 return array; 493 } 494 495 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 496 Label L, E; 497 498 #ifdef _WIN64 499 // Windows always allocates space for it's register args 500 assert(num_args <= 4, "only register arguments supported"); 501 subq(rsp, frame::arg_reg_save_area_bytes); 502 #endif 503 504 // Align stack if necessary 505 testl(rsp, 15); 506 jcc(Assembler::zero, L); 507 508 subq(rsp, 8); 509 { 510 call(RuntimeAddress(entry_point)); 511 } 512 addq(rsp, 8); 513 jmp(E); 514 515 bind(L); 516 { 517 call(RuntimeAddress(entry_point)); 518 } 519 520 bind(E); 521 522 #ifdef _WIN64 523 // restore stack pointer 524 addq(rsp, frame::arg_reg_save_area_bytes); 525 #endif 526 527 } 528 529 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 530 assert(!src2.is_lval(), "should use cmpptr"); 531 532 if (reachable(src2)) { 533 cmpq(src1, as_Address(src2)); 534 } else { 535 lea(rscratch1, src2); 536 Assembler::cmpq(src1, Address(rscratch1, 0)); 537 } 538 } 539 540 int MacroAssembler::corrected_idivq(Register reg) { 541 // Full implementation of Java ldiv and lrem; checks for special 542 // case as described in JVM spec., p.243 & p.271. The function 543 // returns the (pc) offset of the idivl instruction - may be needed 544 // for implicit exceptions. 545 // 546 // normal case special case 547 // 548 // input : rax: dividend min_long 549 // reg: divisor (may not be eax/edx) -1 550 // 551 // output: rax: quotient (= rax idiv reg) min_long 552 // rdx: remainder (= rax irem reg) 0 553 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 554 static const int64_t min_long = 0x8000000000000000; 555 Label normal_case, special_case; 556 557 // check for special case 558 cmp64(rax, ExternalAddress((address) &min_long)); 559 jcc(Assembler::notEqual, normal_case); 560 xorl(rdx, rdx); // prepare rdx for possible special case (where 561 // remainder = 0) 562 cmpq(reg, -1); 563 jcc(Assembler::equal, special_case); 564 565 // handle normal case 566 bind(normal_case); 567 cdqq(); 568 int idivq_offset = offset(); 569 idivq(reg); 570 571 // normal and special case exit 572 bind(special_case); 573 574 return idivq_offset; 575 } 576 577 void MacroAssembler::decrementq(Register reg, int value) { 578 if (value == min_jint) { subq(reg, value); return; } 579 if (value < 0) { incrementq(reg, -value); return; } 580 if (value == 0) { ; return; } 581 if (value == 1 && UseIncDec) { decq(reg) ; return; } 582 /* else */ { subq(reg, value) ; return; } 583 } 584 585 void MacroAssembler::decrementq(Address dst, int value) { 586 if (value == min_jint) { subq(dst, value); return; } 587 if (value < 0) { incrementq(dst, -value); return; } 588 if (value == 0) { ; return; } 589 if (value == 1 && UseIncDec) { decq(dst) ; return; } 590 /* else */ { subq(dst, value) ; return; } 591 } 592 593 void MacroAssembler::incrementq(AddressLiteral dst) { 594 if (reachable(dst)) { 595 incrementq(as_Address(dst)); 596 } else { 597 lea(rscratch1, dst); 598 incrementq(Address(rscratch1, 0)); 599 } 600 } 601 602 void MacroAssembler::incrementq(Register reg, int value) { 603 if (value == min_jint) { addq(reg, value); return; } 604 if (value < 0) { decrementq(reg, -value); return; } 605 if (value == 0) { ; return; } 606 if (value == 1 && UseIncDec) { incq(reg) ; return; } 607 /* else */ { addq(reg, value) ; return; } 608 } 609 610 void MacroAssembler::incrementq(Address dst, int value) { 611 if (value == min_jint) { addq(dst, value); return; } 612 if (value < 0) { decrementq(dst, -value); return; } 613 if (value == 0) { ; return; } 614 if (value == 1 && UseIncDec) { incq(dst) ; return; } 615 /* else */ { addq(dst, value) ; return; } 616 } 617 618 // 32bit can do a case table jump in one instruction but we no longer allow the base 619 // to be installed in the Address class 620 void MacroAssembler::jump(ArrayAddress entry) { 621 lea(rscratch1, entry.base()); 622 Address dispatch = entry.index(); 623 assert(dispatch._base == noreg, "must be"); 624 dispatch._base = rscratch1; 625 jmp(dispatch); 626 } 627 628 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 629 ShouldNotReachHere(); // 64bit doesn't use two regs 630 cmpq(x_lo, y_lo); 631 } 632 633 void MacroAssembler::lea(Register dst, AddressLiteral src) { 634 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 635 } 636 637 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 638 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 639 movptr(dst, rscratch1); 640 } 641 642 void MacroAssembler::leave() { 643 // %%% is this really better? Why not on 32bit too? 644 emit_int8((unsigned char)0xC9); // LEAVE 645 } 646 647 void MacroAssembler::lneg(Register hi, Register lo) { 648 ShouldNotReachHere(); // 64bit doesn't use two regs 649 negq(lo); 650 } 651 652 void MacroAssembler::movoop(Register dst, jobject obj) { 653 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 654 } 655 656 void MacroAssembler::movoop(Address dst, jobject obj) { 657 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 658 movq(dst, rscratch1); 659 } 660 661 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 662 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 663 } 664 665 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 666 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 667 movq(dst, rscratch1); 668 } 669 670 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 671 if (src.is_lval()) { 672 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 673 } else { 674 if (reachable(src)) { 675 movq(dst, as_Address(src)); 676 } else { 677 lea(scratch, src); 678 movq(dst, Address(scratch, 0)); 679 } 680 } 681 } 682 683 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 684 movq(as_Address(dst), src); 685 } 686 687 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 688 movq(dst, as_Address(src)); 689 } 690 691 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 692 void MacroAssembler::movptr(Address dst, intptr_t src) { 693 if (is_simm32(src)) { 694 movptr(dst, checked_cast<int32_t>(src)); 695 } else { 696 mov64(rscratch1, src); 697 movq(dst, rscratch1); 698 } 699 } 700 701 // These are mostly for initializing NULL 702 void MacroAssembler::movptr(Address dst, int32_t src) { 703 movslq(dst, src); 704 } 705 706 void MacroAssembler::movptr(Register dst, int32_t src) { 707 mov64(dst, (intptr_t)src); 708 } 709 710 void MacroAssembler::pushoop(jobject obj) { 711 movoop(rscratch1, obj); 712 push(rscratch1); 713 } 714 715 void MacroAssembler::pushklass(Metadata* obj) { 716 mov_metadata(rscratch1, obj); 717 push(rscratch1); 718 } 719 720 void MacroAssembler::pushptr(AddressLiteral src) { 721 lea(rscratch1, src); 722 if (src.is_lval()) { 723 push(rscratch1); 724 } else { 725 pushq(Address(rscratch1, 0)); 726 } 727 } 728 729 void MacroAssembler::reset_last_Java_frame(bool clear_fp) { 730 reset_last_Java_frame(r15_thread, clear_fp); 731 } 732 733 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 734 Register last_java_fp, 735 address last_java_pc) { 736 vzeroupper(); 737 // determine last_java_sp register 738 if (!last_java_sp->is_valid()) { 739 last_java_sp = rsp; 740 } 741 742 // last_java_fp is optional 743 if (last_java_fp->is_valid()) { 744 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 745 last_java_fp); 746 } 747 748 // last_java_pc is optional 749 if (last_java_pc != NULL) { 750 Address java_pc(r15_thread, 751 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 752 lea(rscratch1, InternalAddress(last_java_pc)); 753 movptr(java_pc, rscratch1); 754 } 755 756 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 757 } 758 759 static void pass_arg0(MacroAssembler* masm, Register arg) { 760 if (c_rarg0 != arg ) { 761 masm->mov(c_rarg0, arg); 762 } 763 } 764 765 static void pass_arg1(MacroAssembler* masm, Register arg) { 766 if (c_rarg1 != arg ) { 767 masm->mov(c_rarg1, arg); 768 } 769 } 770 771 static void pass_arg2(MacroAssembler* masm, Register arg) { 772 if (c_rarg2 != arg ) { 773 masm->mov(c_rarg2, arg); 774 } 775 } 776 777 static void pass_arg3(MacroAssembler* masm, Register arg) { 778 if (c_rarg3 != arg ) { 779 masm->mov(c_rarg3, arg); 780 } 781 } 782 783 void MacroAssembler::stop(const char* msg) { 784 if (ShowMessageBoxOnError) { 785 address rip = pc(); 786 pusha(); // get regs on stack 787 lea(c_rarg1, InternalAddress(rip)); 788 movq(c_rarg2, rsp); // pass pointer to regs array 789 } 790 lea(c_rarg0, ExternalAddress((address) msg)); 791 andq(rsp, -16); // align stack as required by ABI 792 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 793 hlt(); 794 } 795 796 void MacroAssembler::warn(const char* msg) { 797 push(rbp); 798 movq(rbp, rsp); 799 andq(rsp, -16); // align stack as required by push_CPU_state and call 800 push_CPU_state(); // keeps alignment at 16 bytes 801 lea(c_rarg0, ExternalAddress((address) msg)); 802 lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning))); 803 call(rax); 804 pop_CPU_state(); 805 mov(rsp, rbp); 806 pop(rbp); 807 } 808 809 void MacroAssembler::print_state() { 810 address rip = pc(); 811 pusha(); // get regs on stack 812 push(rbp); 813 movq(rbp, rsp); 814 andq(rsp, -16); // align stack as required by push_CPU_state and call 815 push_CPU_state(); // keeps alignment at 16 bytes 816 817 lea(c_rarg0, InternalAddress(rip)); 818 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 819 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 820 821 pop_CPU_state(); 822 mov(rsp, rbp); 823 pop(rbp); 824 popa(); 825 } 826 827 #ifndef PRODUCT 828 extern "C" void findpc(intptr_t x); 829 #endif 830 831 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 832 // In order to get locks to work, we need to fake a in_VM state 833 if (ShowMessageBoxOnError) { 834 JavaThread* thread = JavaThread::current(); 835 JavaThreadState saved_state = thread->thread_state(); 836 thread->set_thread_state(_thread_in_vm); 837 #ifndef PRODUCT 838 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 839 ttyLocker ttyl; 840 BytecodeCounter::print(); 841 } 842 #endif 843 // To see where a verify_oop failed, get $ebx+40/X for this frame. 844 // XXX correct this offset for amd64 845 // This is the value of eip which points to where verify_oop will return. 846 if (os::message_box(msg, "Execution stopped, print registers?")) { 847 print_state64(pc, regs); 848 BREAKPOINT; 849 } 850 } 851 fatal("DEBUG MESSAGE: %s", msg); 852 } 853 854 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 855 ttyLocker ttyl; 856 FlagSetting fs(Debugging, true); 857 tty->print_cr("rip = 0x%016lx", (intptr_t)pc); 858 #ifndef PRODUCT 859 tty->cr(); 860 findpc(pc); 861 tty->cr(); 862 #endif 863 #define PRINT_REG(rax, value) \ 864 { tty->print("%s = ", #rax); os::print_location(tty, value); } 865 PRINT_REG(rax, regs[15]); 866 PRINT_REG(rbx, regs[12]); 867 PRINT_REG(rcx, regs[14]); 868 PRINT_REG(rdx, regs[13]); 869 PRINT_REG(rdi, regs[8]); 870 PRINT_REG(rsi, regs[9]); 871 PRINT_REG(rbp, regs[10]); 872 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp 873 PRINT_REG(rsp, (intptr_t)(®s[16])); 874 PRINT_REG(r8 , regs[7]); 875 PRINT_REG(r9 , regs[6]); 876 PRINT_REG(r10, regs[5]); 877 PRINT_REG(r11, regs[4]); 878 PRINT_REG(r12, regs[3]); 879 PRINT_REG(r13, regs[2]); 880 PRINT_REG(r14, regs[1]); 881 PRINT_REG(r15, regs[0]); 882 #undef PRINT_REG 883 // Print some words near the top of the stack. 884 int64_t* rsp = ®s[16]; 885 int64_t* dump_sp = rsp; 886 for (int col1 = 0; col1 < 8; col1++) { 887 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 888 os::print_location(tty, *dump_sp++); 889 } 890 for (int row = 0; row < 25; row++) { 891 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 892 for (int col = 0; col < 4; col++) { 893 tty->print(" 0x%016lx", (intptr_t)*dump_sp++); 894 } 895 tty->cr(); 896 } 897 // Print some instructions around pc: 898 Disassembler::decode((address)pc-64, (address)pc); 899 tty->print_cr("--------"); 900 Disassembler::decode((address)pc, (address)pc+32); 901 } 902 903 // The java_calling_convention describes stack locations as ideal slots on 904 // a frame with no abi restrictions. Since we must observe abi restrictions 905 // (like the placement of the register window) the slots must be biased by 906 // the following value. 907 static int reg2offset_in(VMReg r) { 908 // Account for saved rbp and return address 909 // This should really be in_preserve_stack_slots 910 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size; 911 } 912 913 static int reg2offset_out(VMReg r) { 914 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 915 } 916 917 // A long move 918 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) { 919 920 // The calling conventions assures us that each VMregpair is either 921 // all really one physical register or adjacent stack slots. 922 923 if (src.is_single_phys_reg() ) { 924 if (dst.is_single_phys_reg()) { 925 if (dst.first() != src.first()) { 926 mov(dst.first()->as_Register(), src.first()->as_Register()); 927 } 928 } else { 929 assert(dst.is_single_reg(), "not a stack pair"); 930 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 931 } 932 } else if (dst.is_single_phys_reg()) { 933 assert(src.is_single_reg(), "not a stack pair"); 934 movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first()))); 935 } else { 936 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 937 movq(rax, Address(rbp, reg2offset_in(src.first()))); 938 movq(Address(rsp, reg2offset_out(dst.first())), rax); 939 } 940 } 941 942 // A double move 943 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) { 944 945 // The calling conventions assures us that each VMregpair is either 946 // all really one physical register or adjacent stack slots. 947 948 if (src.is_single_phys_reg() ) { 949 if (dst.is_single_phys_reg()) { 950 // In theory these overlap but the ordering is such that this is likely a nop 951 if ( src.first() != dst.first()) { 952 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 953 } 954 } else { 955 assert(dst.is_single_reg(), "not a stack pair"); 956 movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 957 } 958 } else if (dst.is_single_phys_reg()) { 959 assert(src.is_single_reg(), "not a stack pair"); 960 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first()))); 961 } else { 962 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs"); 963 movq(rax, Address(rbp, reg2offset_in(src.first()))); 964 movq(Address(rsp, reg2offset_out(dst.first())), rax); 965 } 966 } 967 968 969 // A float arg may have to do float reg int reg conversion 970 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) { 971 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 972 973 // The calling conventions assures us that each VMregpair is either 974 // all really one physical register or adjacent stack slots. 975 976 if (src.first()->is_stack()) { 977 if (dst.first()->is_stack()) { 978 movl(rax, Address(rbp, reg2offset_in(src.first()))); 979 movptr(Address(rsp, reg2offset_out(dst.first())), rax); 980 } else { 981 // stack to reg 982 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 983 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()))); 984 } 985 } else if (dst.first()->is_stack()) { 986 // reg to stack 987 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters"); 988 movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister()); 989 } else { 990 // reg to reg 991 // In theory these overlap but the ordering is such that this is likely a nop 992 if ( src.first() != dst.first()) { 993 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister()); 994 } 995 } 996 } 997 998 // On 64 bit we will store integer like items to the stack as 999 // 64 bits items (x86_32/64 abi) even though java would only store 1000 // 32bits for a parameter. On 32bit it will simply be 32 bits 1001 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 1002 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) { 1003 if (src.first()->is_stack()) { 1004 if (dst.first()->is_stack()) { 1005 // stack to stack 1006 movslq(rax, Address(rbp, reg2offset_in(src.first()))); 1007 movq(Address(rsp, reg2offset_out(dst.first())), rax); 1008 } else { 1009 // stack to reg 1010 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1011 } 1012 } else if (dst.first()->is_stack()) { 1013 // reg to stack 1014 // Do we really have to sign extend??? 1015 // __ movslq(src.first()->as_Register(), src.first()->as_Register()); 1016 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1017 } else { 1018 // Do we really have to sign extend??? 1019 // __ movslq(dst.first()->as_Register(), src.first()->as_Register()); 1020 if (dst.first() != src.first()) { 1021 movq(dst.first()->as_Register(), src.first()->as_Register()); 1022 } 1023 } 1024 } 1025 1026 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) { 1027 if (src.first()->is_stack()) { 1028 if (dst.first()->is_stack()) { 1029 // stack to stack 1030 movq(rax, Address(rbp, reg2offset_in(src.first()))); 1031 movq(Address(rsp, reg2offset_out(dst.first())), rax); 1032 } else { 1033 // stack to reg 1034 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()))); 1035 } 1036 } else if (dst.first()->is_stack()) { 1037 // reg to stack 1038 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register()); 1039 } else { 1040 if (dst.first() != src.first()) { 1041 movq(dst.first()->as_Register(), src.first()->as_Register()); 1042 } 1043 } 1044 } 1045 1046 // An oop arg. Must pass a handle not the oop itself 1047 void MacroAssembler::object_move(OopMap* map, 1048 int oop_handle_offset, 1049 int framesize_in_slots, 1050 VMRegPair src, 1051 VMRegPair dst, 1052 bool is_receiver, 1053 int* receiver_offset) { 1054 1055 // must pass a handle. First figure out the location we use as a handle 1056 1057 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register(); 1058 1059 // See if oop is NULL if it is we need no handle 1060 1061 if (src.first()->is_stack()) { 1062 1063 // Oop is already on the stack as an argument 1064 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1065 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1066 if (is_receiver) { 1067 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1068 } 1069 1070 cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD); 1071 lea(rHandle, Address(rbp, reg2offset_in(src.first()))); 1072 // conditionally move a NULL 1073 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first()))); 1074 } else { 1075 1076 // Oop is in an a register we must store it to the space we reserve 1077 // on the stack for oop_handles and pass a handle if oop is non-NULL 1078 1079 const Register rOop = src.first()->as_Register(); 1080 int oop_slot; 1081 if (rOop == j_rarg0) 1082 oop_slot = 0; 1083 else if (rOop == j_rarg1) 1084 oop_slot = 1; 1085 else if (rOop == j_rarg2) 1086 oop_slot = 2; 1087 else if (rOop == j_rarg3) 1088 oop_slot = 3; 1089 else if (rOop == j_rarg4) 1090 oop_slot = 4; 1091 else { 1092 assert(rOop == j_rarg5, "wrong register"); 1093 oop_slot = 5; 1094 } 1095 1096 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset; 1097 int offset = oop_slot*VMRegImpl::stack_slot_size; 1098 1099 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1100 // Store oop in handle area, may be NULL 1101 movptr(Address(rsp, offset), rOop); 1102 if (is_receiver) { 1103 *receiver_offset = offset; 1104 } 1105 1106 cmpptr(rOop, (int32_t)NULL_WORD); 1107 lea(rHandle, Address(rsp, offset)); 1108 // conditionally move a NULL from the handle area where it was just stored 1109 cmovptr(Assembler::equal, rHandle, Address(rsp, offset)); 1110 } 1111 1112 // If arg is on the stack then place it otherwise it is already in correct reg. 1113 if (dst.first()->is_stack()) { 1114 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle); 1115 } 1116 } 1117 1118 #endif // _LP64 1119 1120 // Now versions that are common to 32/64 bit 1121 1122 void MacroAssembler::addptr(Register dst, int32_t imm32) { 1123 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 1124 } 1125 1126 void MacroAssembler::addptr(Register dst, Register src) { 1127 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 1128 } 1129 1130 void MacroAssembler::addptr(Address dst, Register src) { 1131 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 1132 } 1133 1134 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 1135 if (reachable(src)) { 1136 Assembler::addsd(dst, as_Address(src)); 1137 } else { 1138 lea(rscratch1, src); 1139 Assembler::addsd(dst, Address(rscratch1, 0)); 1140 } 1141 } 1142 1143 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 1144 if (reachable(src)) { 1145 addss(dst, as_Address(src)); 1146 } else { 1147 lea(rscratch1, src); 1148 addss(dst, Address(rscratch1, 0)); 1149 } 1150 } 1151 1152 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 1153 if (reachable(src)) { 1154 Assembler::addpd(dst, as_Address(src)); 1155 } else { 1156 lea(rscratch1, src); 1157 Assembler::addpd(dst, Address(rscratch1, 0)); 1158 } 1159 } 1160 1161 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only. 1162 // Stub code is generated once and never copied. 1163 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes. 1164 void MacroAssembler::align64() { 1165 align(64, (unsigned long long) pc()); 1166 } 1167 1168 void MacroAssembler::align32() { 1169 align(32, (unsigned long long) pc()); 1170 } 1171 1172 void MacroAssembler::align(int modulus) { 1173 // 8273459: Ensure alignment is possible with current segment alignment 1174 assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment"); 1175 align(modulus, offset()); 1176 } 1177 1178 void MacroAssembler::align(int modulus, int target) { 1179 if (target % modulus != 0) { 1180 nop(modulus - (target % modulus)); 1181 } 1182 } 1183 1184 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 1185 // Used in sign-masking with aligned address. 1186 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1187 if (reachable(src)) { 1188 Assembler::andpd(dst, as_Address(src)); 1189 } else { 1190 lea(scratch_reg, src); 1191 Assembler::andpd(dst, Address(scratch_reg, 0)); 1192 } 1193 } 1194 1195 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 1196 // Used in sign-masking with aligned address. 1197 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1198 if (reachable(src)) { 1199 Assembler::andps(dst, as_Address(src)); 1200 } else { 1201 lea(scratch_reg, src); 1202 Assembler::andps(dst, Address(scratch_reg, 0)); 1203 } 1204 } 1205 1206 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1207 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1208 } 1209 1210 void MacroAssembler::atomic_incl(Address counter_addr) { 1211 lock(); 1212 incrementl(counter_addr); 1213 } 1214 1215 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1216 if (reachable(counter_addr)) { 1217 atomic_incl(as_Address(counter_addr)); 1218 } else { 1219 lea(scr, counter_addr); 1220 atomic_incl(Address(scr, 0)); 1221 } 1222 } 1223 1224 #ifdef _LP64 1225 void MacroAssembler::atomic_incq(Address counter_addr) { 1226 lock(); 1227 incrementq(counter_addr); 1228 } 1229 1230 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1231 if (reachable(counter_addr)) { 1232 atomic_incq(as_Address(counter_addr)); 1233 } else { 1234 lea(scr, counter_addr); 1235 atomic_incq(Address(scr, 0)); 1236 } 1237 } 1238 #endif 1239 1240 // Writes to stack successive pages until offset reached to check for 1241 // stack overflow + shadow pages. This clobbers tmp. 1242 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1243 movptr(tmp, rsp); 1244 // Bang stack for total size given plus shadow page size. 1245 // Bang one page at a time because large size can bang beyond yellow and 1246 // red zones. 1247 Label loop; 1248 bind(loop); 1249 movl(Address(tmp, (-os::vm_page_size())), size ); 1250 subptr(tmp, os::vm_page_size()); 1251 subl(size, os::vm_page_size()); 1252 jcc(Assembler::greater, loop); 1253 1254 // Bang down shadow pages too. 1255 // At this point, (tmp-0) is the last address touched, so don't 1256 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1257 // was post-decremented.) Skip this address by starting at i=1, and 1258 // touch a few more pages below. N.B. It is important to touch all 1259 // the way down including all pages in the shadow zone. 1260 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1261 // this could be any sized move but this is can be a debugging crumb 1262 // so the bigger the better. 1263 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1264 } 1265 } 1266 1267 void MacroAssembler::reserved_stack_check() { 1268 // testing if reserved zone needs to be enabled 1269 Label no_reserved_zone_enabling; 1270 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1271 NOT_LP64(get_thread(rsi);) 1272 1273 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1274 jcc(Assembler::below, no_reserved_zone_enabling); 1275 1276 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1277 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1278 should_not_reach_here(); 1279 1280 bind(no_reserved_zone_enabling); 1281 } 1282 1283 void MacroAssembler::c2bool(Register x) { 1284 // implements x == 0 ? 0 : 1 1285 // note: must only look at least-significant byte of x 1286 // since C-style booleans are stored in one byte 1287 // only! (was bug) 1288 andl(x, 0xFF); 1289 setb(Assembler::notZero, x); 1290 } 1291 1292 // Wouldn't need if AddressLiteral version had new name 1293 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 1294 Assembler::call(L, rtype); 1295 } 1296 1297 void MacroAssembler::call(Register entry) { 1298 Assembler::call(entry); 1299 } 1300 1301 void MacroAssembler::call(AddressLiteral entry) { 1302 if (reachable(entry)) { 1303 Assembler::call_literal(entry.target(), entry.rspec()); 1304 } else { 1305 lea(rscratch1, entry); 1306 Assembler::call(rscratch1); 1307 } 1308 } 1309 1310 void MacroAssembler::ic_call(address entry, jint method_index) { 1311 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 1312 movptr(rax, (intptr_t)Universe::non_oop_word()); 1313 call(AddressLiteral(entry, rh)); 1314 } 1315 1316 // Implementation of call_VM versions 1317 1318 void MacroAssembler::call_VM(Register oop_result, 1319 address entry_point, 1320 bool check_exceptions) { 1321 Label C, E; 1322 call(C, relocInfo::none); 1323 jmp(E); 1324 1325 bind(C); 1326 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 1327 ret(0); 1328 1329 bind(E); 1330 } 1331 1332 void MacroAssembler::call_VM(Register oop_result, 1333 address entry_point, 1334 Register arg_1, 1335 bool check_exceptions) { 1336 Label C, E; 1337 call(C, relocInfo::none); 1338 jmp(E); 1339 1340 bind(C); 1341 pass_arg1(this, arg_1); 1342 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 1343 ret(0); 1344 1345 bind(E); 1346 } 1347 1348 void MacroAssembler::call_VM(Register oop_result, 1349 address entry_point, 1350 Register arg_1, 1351 Register arg_2, 1352 bool check_exceptions) { 1353 Label C, E; 1354 call(C, relocInfo::none); 1355 jmp(E); 1356 1357 bind(C); 1358 1359 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1360 1361 pass_arg2(this, arg_2); 1362 pass_arg1(this, arg_1); 1363 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 1364 ret(0); 1365 1366 bind(E); 1367 } 1368 1369 void MacroAssembler::call_VM(Register oop_result, 1370 address entry_point, 1371 Register arg_1, 1372 Register arg_2, 1373 Register arg_3, 1374 bool check_exceptions) { 1375 Label C, E; 1376 call(C, relocInfo::none); 1377 jmp(E); 1378 1379 bind(C); 1380 1381 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1382 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1383 pass_arg3(this, arg_3); 1384 1385 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1386 pass_arg2(this, arg_2); 1387 1388 pass_arg1(this, arg_1); 1389 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 1390 ret(0); 1391 1392 bind(E); 1393 } 1394 1395 void MacroAssembler::call_VM(Register oop_result, 1396 Register last_java_sp, 1397 address entry_point, 1398 int number_of_arguments, 1399 bool check_exceptions) { 1400 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1401 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1402 } 1403 1404 void MacroAssembler::call_VM(Register oop_result, 1405 Register last_java_sp, 1406 address entry_point, 1407 Register arg_1, 1408 bool check_exceptions) { 1409 pass_arg1(this, arg_1); 1410 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1411 } 1412 1413 void MacroAssembler::call_VM(Register oop_result, 1414 Register last_java_sp, 1415 address entry_point, 1416 Register arg_1, 1417 Register arg_2, 1418 bool check_exceptions) { 1419 1420 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1421 pass_arg2(this, arg_2); 1422 pass_arg1(this, arg_1); 1423 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1424 } 1425 1426 void MacroAssembler::call_VM(Register oop_result, 1427 Register last_java_sp, 1428 address entry_point, 1429 Register arg_1, 1430 Register arg_2, 1431 Register arg_3, 1432 bool check_exceptions) { 1433 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1434 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1435 pass_arg3(this, arg_3); 1436 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1437 pass_arg2(this, arg_2); 1438 pass_arg1(this, arg_1); 1439 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1440 } 1441 1442 void MacroAssembler::super_call_VM(Register oop_result, 1443 Register last_java_sp, 1444 address entry_point, 1445 int number_of_arguments, 1446 bool check_exceptions) { 1447 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 1448 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 1449 } 1450 1451 void MacroAssembler::super_call_VM(Register oop_result, 1452 Register last_java_sp, 1453 address entry_point, 1454 Register arg_1, 1455 bool check_exceptions) { 1456 pass_arg1(this, arg_1); 1457 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 1458 } 1459 1460 void MacroAssembler::super_call_VM(Register oop_result, 1461 Register last_java_sp, 1462 address entry_point, 1463 Register arg_1, 1464 Register arg_2, 1465 bool check_exceptions) { 1466 1467 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1468 pass_arg2(this, arg_2); 1469 pass_arg1(this, arg_1); 1470 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 1471 } 1472 1473 void MacroAssembler::super_call_VM(Register oop_result, 1474 Register last_java_sp, 1475 address entry_point, 1476 Register arg_1, 1477 Register arg_2, 1478 Register arg_3, 1479 bool check_exceptions) { 1480 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1481 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1482 pass_arg3(this, arg_3); 1483 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1484 pass_arg2(this, arg_2); 1485 pass_arg1(this, arg_1); 1486 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 1487 } 1488 1489 void MacroAssembler::call_VM_base(Register oop_result, 1490 Register java_thread, 1491 Register last_java_sp, 1492 address entry_point, 1493 int number_of_arguments, 1494 bool check_exceptions) { 1495 // determine java_thread register 1496 if (!java_thread->is_valid()) { 1497 #ifdef _LP64 1498 java_thread = r15_thread; 1499 #else 1500 java_thread = rdi; 1501 get_thread(java_thread); 1502 #endif // LP64 1503 } 1504 // determine last_java_sp register 1505 if (!last_java_sp->is_valid()) { 1506 last_java_sp = rsp; 1507 } 1508 // debugging support 1509 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 1510 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 1511 #ifdef ASSERT 1512 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 1513 // r12 is the heapbase. 1514 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 1515 #endif // ASSERT 1516 1517 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 1518 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 1519 1520 // push java thread (becomes first argument of C function) 1521 1522 NOT_LP64(push(java_thread); number_of_arguments++); 1523 LP64_ONLY(mov(c_rarg0, r15_thread)); 1524 1525 // set last Java frame before call 1526 assert(last_java_sp != rbp, "can't use ebp/rbp"); 1527 1528 // Only interpreter should have to set fp 1529 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 1530 1531 // do the call, remove parameters 1532 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 1533 1534 // restore the thread (cannot use the pushed argument since arguments 1535 // may be overwritten by C code generated by an optimizing compiler); 1536 // however can use the register value directly if it is callee saved. 1537 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 1538 // rdi & rsi (also r15) are callee saved -> nothing to do 1539 #ifdef ASSERT 1540 guarantee(java_thread != rax, "change this code"); 1541 push(rax); 1542 { Label L; 1543 get_thread(rax); 1544 cmpptr(java_thread, rax); 1545 jcc(Assembler::equal, L); 1546 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 1547 bind(L); 1548 } 1549 pop(rax); 1550 #endif 1551 } else { 1552 get_thread(java_thread); 1553 } 1554 // reset last Java frame 1555 // Only interpreter should have to clear fp 1556 reset_last_Java_frame(java_thread, true); 1557 1558 // C++ interp handles this in the interpreter 1559 check_and_handle_popframe(java_thread); 1560 check_and_handle_earlyret(java_thread); 1561 1562 if (check_exceptions) { 1563 // check for pending exceptions (java_thread is set upon return) 1564 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 1565 #ifndef _LP64 1566 jump_cc(Assembler::notEqual, 1567 RuntimeAddress(StubRoutines::forward_exception_entry())); 1568 #else 1569 // This used to conditionally jump to forward_exception however it is 1570 // possible if we relocate that the branch will not reach. So we must jump 1571 // around so we can always reach 1572 1573 Label ok; 1574 jcc(Assembler::equal, ok); 1575 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 1576 bind(ok); 1577 #endif // LP64 1578 } 1579 1580 // get oop result if there is one and reset the value in the thread 1581 if (oop_result->is_valid()) { 1582 get_vm_result(oop_result, java_thread); 1583 } 1584 } 1585 1586 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 1587 1588 // Calculate the value for last_Java_sp 1589 // somewhat subtle. call_VM does an intermediate call 1590 // which places a return address on the stack just under the 1591 // stack pointer as the user finished with it. This allows 1592 // use to retrieve last_Java_pc from last_Java_sp[-1]. 1593 // On 32bit we then have to push additional args on the stack to accomplish 1594 // the actual requested call. On 64bit call_VM only can use register args 1595 // so the only extra space is the return address that call_VM created. 1596 // This hopefully explains the calculations here. 1597 1598 #ifdef _LP64 1599 // We've pushed one address, correct last_Java_sp 1600 lea(rax, Address(rsp, wordSize)); 1601 #else 1602 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 1603 #endif // LP64 1604 1605 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 1606 1607 } 1608 1609 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter. 1610 void MacroAssembler::call_VM_leaf0(address entry_point) { 1611 MacroAssembler::call_VM_leaf_base(entry_point, 0); 1612 } 1613 1614 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 1615 call_VM_leaf_base(entry_point, number_of_arguments); 1616 } 1617 1618 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 1619 pass_arg0(this, arg_0); 1620 call_VM_leaf(entry_point, 1); 1621 } 1622 1623 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1624 1625 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1626 pass_arg1(this, arg_1); 1627 pass_arg0(this, arg_0); 1628 call_VM_leaf(entry_point, 2); 1629 } 1630 1631 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1632 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1633 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1634 pass_arg2(this, arg_2); 1635 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1636 pass_arg1(this, arg_1); 1637 pass_arg0(this, arg_0); 1638 call_VM_leaf(entry_point, 3); 1639 } 1640 1641 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 1642 pass_arg0(this, arg_0); 1643 MacroAssembler::call_VM_leaf_base(entry_point, 1); 1644 } 1645 1646 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 1647 1648 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1649 pass_arg1(this, arg_1); 1650 pass_arg0(this, arg_0); 1651 MacroAssembler::call_VM_leaf_base(entry_point, 2); 1652 } 1653 1654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 1655 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1656 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1657 pass_arg2(this, arg_2); 1658 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1659 pass_arg1(this, arg_1); 1660 pass_arg0(this, arg_0); 1661 MacroAssembler::call_VM_leaf_base(entry_point, 3); 1662 } 1663 1664 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 1665 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 1666 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 1667 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 1668 pass_arg3(this, arg_3); 1669 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 1670 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 1671 pass_arg2(this, arg_2); 1672 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 1673 pass_arg1(this, arg_1); 1674 pass_arg0(this, arg_0); 1675 MacroAssembler::call_VM_leaf_base(entry_point, 4); 1676 } 1677 1678 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 1679 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 1680 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 1681 verify_oop_msg(oop_result, "broken oop in call_VM_base"); 1682 } 1683 1684 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 1685 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 1686 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 1687 } 1688 1689 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 1690 } 1691 1692 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 1693 } 1694 1695 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 1696 if (reachable(src1)) { 1697 cmpl(as_Address(src1), imm); 1698 } else { 1699 lea(rscratch1, src1); 1700 cmpl(Address(rscratch1, 0), imm); 1701 } 1702 } 1703 1704 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 1705 assert(!src2.is_lval(), "use cmpptr"); 1706 if (reachable(src2)) { 1707 cmpl(src1, as_Address(src2)); 1708 } else { 1709 lea(rscratch1, src2); 1710 cmpl(src1, Address(rscratch1, 0)); 1711 } 1712 } 1713 1714 void MacroAssembler::cmp32(Register src1, int32_t imm) { 1715 Assembler::cmpl(src1, imm); 1716 } 1717 1718 void MacroAssembler::cmp32(Register src1, Address src2) { 1719 Assembler::cmpl(src1, src2); 1720 } 1721 1722 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1723 ucomisd(opr1, opr2); 1724 1725 Label L; 1726 if (unordered_is_less) { 1727 movl(dst, -1); 1728 jcc(Assembler::parity, L); 1729 jcc(Assembler::below , L); 1730 movl(dst, 0); 1731 jcc(Assembler::equal , L); 1732 increment(dst); 1733 } else { // unordered is greater 1734 movl(dst, 1); 1735 jcc(Assembler::parity, L); 1736 jcc(Assembler::above , L); 1737 movl(dst, 0); 1738 jcc(Assembler::equal , L); 1739 decrementl(dst); 1740 } 1741 bind(L); 1742 } 1743 1744 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 1745 ucomiss(opr1, opr2); 1746 1747 Label L; 1748 if (unordered_is_less) { 1749 movl(dst, -1); 1750 jcc(Assembler::parity, L); 1751 jcc(Assembler::below , L); 1752 movl(dst, 0); 1753 jcc(Assembler::equal , L); 1754 increment(dst); 1755 } else { // unordered is greater 1756 movl(dst, 1); 1757 jcc(Assembler::parity, L); 1758 jcc(Assembler::above , L); 1759 movl(dst, 0); 1760 jcc(Assembler::equal , L); 1761 decrementl(dst); 1762 } 1763 bind(L); 1764 } 1765 1766 1767 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 1768 if (reachable(src1)) { 1769 cmpb(as_Address(src1), imm); 1770 } else { 1771 lea(rscratch1, src1); 1772 cmpb(Address(rscratch1, 0), imm); 1773 } 1774 } 1775 1776 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 1777 #ifdef _LP64 1778 if (src2.is_lval()) { 1779 movptr(rscratch1, src2); 1780 Assembler::cmpq(src1, rscratch1); 1781 } else if (reachable(src2)) { 1782 cmpq(src1, as_Address(src2)); 1783 } else { 1784 lea(rscratch1, src2); 1785 Assembler::cmpq(src1, Address(rscratch1, 0)); 1786 } 1787 #else 1788 if (src2.is_lval()) { 1789 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 1790 } else { 1791 cmpl(src1, as_Address(src2)); 1792 } 1793 #endif // _LP64 1794 } 1795 1796 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 1797 assert(src2.is_lval(), "not a mem-mem compare"); 1798 #ifdef _LP64 1799 // moves src2's literal address 1800 movptr(rscratch1, src2); 1801 Assembler::cmpq(src1, rscratch1); 1802 #else 1803 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 1804 #endif // _LP64 1805 } 1806 1807 void MacroAssembler::cmpoop(Register src1, Register src2) { 1808 cmpptr(src1, src2); 1809 } 1810 1811 void MacroAssembler::cmpoop(Register src1, Address src2) { 1812 cmpptr(src1, src2); 1813 } 1814 1815 #ifdef _LP64 1816 void MacroAssembler::cmpoop(Register src1, jobject src2) { 1817 movoop(rscratch1, src2); 1818 cmpptr(src1, rscratch1); 1819 } 1820 #endif 1821 1822 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 1823 if (reachable(adr)) { 1824 lock(); 1825 cmpxchgptr(reg, as_Address(adr)); 1826 } else { 1827 lea(rscratch1, adr); 1828 lock(); 1829 cmpxchgptr(reg, Address(rscratch1, 0)); 1830 } 1831 } 1832 1833 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 1834 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 1835 } 1836 1837 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 1838 if (reachable(src)) { 1839 Assembler::comisd(dst, as_Address(src)); 1840 } else { 1841 lea(rscratch1, src); 1842 Assembler::comisd(dst, Address(rscratch1, 0)); 1843 } 1844 } 1845 1846 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 1847 if (reachable(src)) { 1848 Assembler::comiss(dst, as_Address(src)); 1849 } else { 1850 lea(rscratch1, src); 1851 Assembler::comiss(dst, Address(rscratch1, 0)); 1852 } 1853 } 1854 1855 1856 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 1857 Condition negated_cond = negate_condition(cond); 1858 Label L; 1859 jcc(negated_cond, L); 1860 pushf(); // Preserve flags 1861 atomic_incl(counter_addr); 1862 popf(); 1863 bind(L); 1864 } 1865 1866 int MacroAssembler::corrected_idivl(Register reg) { 1867 // Full implementation of Java idiv and irem; checks for 1868 // special case as described in JVM spec., p.243 & p.271. 1869 // The function returns the (pc) offset of the idivl 1870 // instruction - may be needed for implicit exceptions. 1871 // 1872 // normal case special case 1873 // 1874 // input : rax,: dividend min_int 1875 // reg: divisor (may not be rax,/rdx) -1 1876 // 1877 // output: rax,: quotient (= rax, idiv reg) min_int 1878 // rdx: remainder (= rax, irem reg) 0 1879 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 1880 const int min_int = 0x80000000; 1881 Label normal_case, special_case; 1882 1883 // check for special case 1884 cmpl(rax, min_int); 1885 jcc(Assembler::notEqual, normal_case); 1886 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 1887 cmpl(reg, -1); 1888 jcc(Assembler::equal, special_case); 1889 1890 // handle normal case 1891 bind(normal_case); 1892 cdql(); 1893 int idivl_offset = offset(); 1894 idivl(reg); 1895 1896 // normal and special case exit 1897 bind(special_case); 1898 1899 return idivl_offset; 1900 } 1901 1902 1903 1904 void MacroAssembler::decrementl(Register reg, int value) { 1905 if (value == min_jint) {subl(reg, value) ; return; } 1906 if (value < 0) { incrementl(reg, -value); return; } 1907 if (value == 0) { ; return; } 1908 if (value == 1 && UseIncDec) { decl(reg) ; return; } 1909 /* else */ { subl(reg, value) ; return; } 1910 } 1911 1912 void MacroAssembler::decrementl(Address dst, int value) { 1913 if (value == min_jint) {subl(dst, value) ; return; } 1914 if (value < 0) { incrementl(dst, -value); return; } 1915 if (value == 0) { ; return; } 1916 if (value == 1 && UseIncDec) { decl(dst) ; return; } 1917 /* else */ { subl(dst, value) ; return; } 1918 } 1919 1920 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 1921 assert (shift_value > 0, "illegal shift value"); 1922 Label _is_positive; 1923 testl (reg, reg); 1924 jcc (Assembler::positive, _is_positive); 1925 int offset = (1 << shift_value) - 1 ; 1926 1927 if (offset == 1) { 1928 incrementl(reg); 1929 } else { 1930 addl(reg, offset); 1931 } 1932 1933 bind (_is_positive); 1934 sarl(reg, shift_value); 1935 } 1936 1937 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 1938 if (reachable(src)) { 1939 Assembler::divsd(dst, as_Address(src)); 1940 } else { 1941 lea(rscratch1, src); 1942 Assembler::divsd(dst, Address(rscratch1, 0)); 1943 } 1944 } 1945 1946 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 1947 if (reachable(src)) { 1948 Assembler::divss(dst, as_Address(src)); 1949 } else { 1950 lea(rscratch1, src); 1951 Assembler::divss(dst, Address(rscratch1, 0)); 1952 } 1953 } 1954 1955 void MacroAssembler::enter() { 1956 push(rbp); 1957 mov(rbp, rsp); 1958 } 1959 1960 // A 5 byte nop that is safe for patching (see patch_verified_entry) 1961 void MacroAssembler::fat_nop() { 1962 if (UseAddressNop) { 1963 addr_nop_5(); 1964 } else { 1965 emit_int8(0x26); // es: 1966 emit_int8(0x2e); // cs: 1967 emit_int8(0x64); // fs: 1968 emit_int8(0x65); // gs: 1969 emit_int8((unsigned char)0x90); 1970 } 1971 } 1972 1973 #ifndef _LP64 1974 void MacroAssembler::fcmp(Register tmp) { 1975 fcmp(tmp, 1, true, true); 1976 } 1977 1978 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 1979 assert(!pop_right || pop_left, "usage error"); 1980 if (VM_Version::supports_cmov()) { 1981 assert(tmp == noreg, "unneeded temp"); 1982 if (pop_left) { 1983 fucomip(index); 1984 } else { 1985 fucomi(index); 1986 } 1987 if (pop_right) { 1988 fpop(); 1989 } 1990 } else { 1991 assert(tmp != noreg, "need temp"); 1992 if (pop_left) { 1993 if (pop_right) { 1994 fcompp(); 1995 } else { 1996 fcomp(index); 1997 } 1998 } else { 1999 fcom(index); 2000 } 2001 // convert FPU condition into eflags condition via rax, 2002 save_rax(tmp); 2003 fwait(); fnstsw_ax(); 2004 sahf(); 2005 restore_rax(tmp); 2006 } 2007 // condition codes set as follows: 2008 // 2009 // CF (corresponds to C0) if x < y 2010 // PF (corresponds to C2) if unordered 2011 // ZF (corresponds to C3) if x = y 2012 } 2013 2014 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 2015 fcmp2int(dst, unordered_is_less, 1, true, true); 2016 } 2017 2018 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 2019 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 2020 Label L; 2021 if (unordered_is_less) { 2022 movl(dst, -1); 2023 jcc(Assembler::parity, L); 2024 jcc(Assembler::below , L); 2025 movl(dst, 0); 2026 jcc(Assembler::equal , L); 2027 increment(dst); 2028 } else { // unordered is greater 2029 movl(dst, 1); 2030 jcc(Assembler::parity, L); 2031 jcc(Assembler::above , L); 2032 movl(dst, 0); 2033 jcc(Assembler::equal , L); 2034 decrementl(dst); 2035 } 2036 bind(L); 2037 } 2038 2039 void MacroAssembler::fld_d(AddressLiteral src) { 2040 fld_d(as_Address(src)); 2041 } 2042 2043 void MacroAssembler::fld_s(AddressLiteral src) { 2044 fld_s(as_Address(src)); 2045 } 2046 2047 void MacroAssembler::fldcw(AddressLiteral src) { 2048 Assembler::fldcw(as_Address(src)); 2049 } 2050 2051 void MacroAssembler::fpop() { 2052 ffree(); 2053 fincstp(); 2054 } 2055 2056 void MacroAssembler::fremr(Register tmp) { 2057 save_rax(tmp); 2058 { Label L; 2059 bind(L); 2060 fprem(); 2061 fwait(); fnstsw_ax(); 2062 sahf(); 2063 jcc(Assembler::parity, L); 2064 } 2065 restore_rax(tmp); 2066 // Result is in ST0. 2067 // Note: fxch & fpop to get rid of ST1 2068 // (otherwise FPU stack could overflow eventually) 2069 fxch(1); 2070 fpop(); 2071 } 2072 2073 void MacroAssembler::empty_FPU_stack() { 2074 if (VM_Version::supports_mmx()) { 2075 emms(); 2076 } else { 2077 for (int i = 8; i-- > 0; ) ffree(i); 2078 } 2079 } 2080 #endif // !LP64 2081 2082 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 2083 if (reachable(src)) { 2084 Assembler::mulpd(dst, as_Address(src)); 2085 } else { 2086 lea(rscratch1, src); 2087 Assembler::mulpd(dst, Address(rscratch1, 0)); 2088 } 2089 } 2090 2091 void MacroAssembler::load_float(Address src) { 2092 #ifdef _LP64 2093 movflt(xmm0, src); 2094 #else 2095 if (UseSSE >= 1) { 2096 movflt(xmm0, src); 2097 } else { 2098 fld_s(src); 2099 } 2100 #endif // LP64 2101 } 2102 2103 void MacroAssembler::store_float(Address dst) { 2104 #ifdef _LP64 2105 movflt(dst, xmm0); 2106 #else 2107 if (UseSSE >= 1) { 2108 movflt(dst, xmm0); 2109 } else { 2110 fstp_s(dst); 2111 } 2112 #endif // LP64 2113 } 2114 2115 void MacroAssembler::load_double(Address src) { 2116 #ifdef _LP64 2117 movdbl(xmm0, src); 2118 #else 2119 if (UseSSE >= 2) { 2120 movdbl(xmm0, src); 2121 } else { 2122 fld_d(src); 2123 } 2124 #endif // LP64 2125 } 2126 2127 void MacroAssembler::store_double(Address dst) { 2128 #ifdef _LP64 2129 movdbl(dst, xmm0); 2130 #else 2131 if (UseSSE >= 2) { 2132 movdbl(dst, xmm0); 2133 } else { 2134 fstp_d(dst); 2135 } 2136 #endif // LP64 2137 } 2138 2139 // dst = c = a * b + c 2140 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2141 Assembler::vfmadd231sd(c, a, b); 2142 if (dst != c) { 2143 movdbl(dst, c); 2144 } 2145 } 2146 2147 // dst = c = a * b + c 2148 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) { 2149 Assembler::vfmadd231ss(c, a, b); 2150 if (dst != c) { 2151 movflt(dst, c); 2152 } 2153 } 2154 2155 // dst = c = a * b + c 2156 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2157 Assembler::vfmadd231pd(c, a, b, vector_len); 2158 if (dst != c) { 2159 vmovdqu(dst, c); 2160 } 2161 } 2162 2163 // dst = c = a * b + c 2164 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) { 2165 Assembler::vfmadd231ps(c, a, b, vector_len); 2166 if (dst != c) { 2167 vmovdqu(dst, c); 2168 } 2169 } 2170 2171 // dst = c = a * b + c 2172 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2173 Assembler::vfmadd231pd(c, a, b, vector_len); 2174 if (dst != c) { 2175 vmovdqu(dst, c); 2176 } 2177 } 2178 2179 // dst = c = a * b + c 2180 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) { 2181 Assembler::vfmadd231ps(c, a, b, vector_len); 2182 if (dst != c) { 2183 vmovdqu(dst, c); 2184 } 2185 } 2186 2187 void MacroAssembler::incrementl(AddressLiteral dst) { 2188 if (reachable(dst)) { 2189 incrementl(as_Address(dst)); 2190 } else { 2191 lea(rscratch1, dst); 2192 incrementl(Address(rscratch1, 0)); 2193 } 2194 } 2195 2196 void MacroAssembler::incrementl(ArrayAddress dst) { 2197 incrementl(as_Address(dst)); 2198 } 2199 2200 void MacroAssembler::incrementl(Register reg, int value) { 2201 if (value == min_jint) {addl(reg, value) ; return; } 2202 if (value < 0) { decrementl(reg, -value); return; } 2203 if (value == 0) { ; return; } 2204 if (value == 1 && UseIncDec) { incl(reg) ; return; } 2205 /* else */ { addl(reg, value) ; return; } 2206 } 2207 2208 void MacroAssembler::incrementl(Address dst, int value) { 2209 if (value == min_jint) {addl(dst, value) ; return; } 2210 if (value < 0) { decrementl(dst, -value); return; } 2211 if (value == 0) { ; return; } 2212 if (value == 1 && UseIncDec) { incl(dst) ; return; } 2213 /* else */ { addl(dst, value) ; return; } 2214 } 2215 2216 void MacroAssembler::jump(AddressLiteral dst) { 2217 if (reachable(dst)) { 2218 jmp_literal(dst.target(), dst.rspec()); 2219 } else { 2220 lea(rscratch1, dst); 2221 jmp(rscratch1); 2222 } 2223 } 2224 2225 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 2226 if (reachable(dst)) { 2227 InstructionMark im(this); 2228 relocate(dst.reloc()); 2229 const int short_size = 2; 2230 const int long_size = 6; 2231 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 2232 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 2233 // 0111 tttn #8-bit disp 2234 emit_int8(0x70 | cc); 2235 emit_int8((offs - short_size) & 0xFF); 2236 } else { 2237 // 0000 1111 1000 tttn #32-bit disp 2238 emit_int8(0x0F); 2239 emit_int8((unsigned char)(0x80 | cc)); 2240 emit_int32(offs - long_size); 2241 } 2242 } else { 2243 #ifdef ASSERT 2244 warning("reversing conditional branch"); 2245 #endif /* ASSERT */ 2246 Label skip; 2247 jccb(reverse[cc], skip); 2248 lea(rscratch1, dst); 2249 Assembler::jmp(rscratch1); 2250 bind(skip); 2251 } 2252 } 2253 2254 void MacroAssembler::fld_x(AddressLiteral src) { 2255 Assembler::fld_x(as_Address(src)); 2256 } 2257 2258 void MacroAssembler::ldmxcsr(AddressLiteral src, Register scratchReg) { 2259 if (reachable(src)) { 2260 Assembler::ldmxcsr(as_Address(src)); 2261 } else { 2262 lea(scratchReg, src); 2263 Assembler::ldmxcsr(Address(scratchReg, 0)); 2264 } 2265 } 2266 2267 int MacroAssembler::load_signed_byte(Register dst, Address src) { 2268 int off; 2269 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2270 off = offset(); 2271 movsbl(dst, src); // movsxb 2272 } else { 2273 off = load_unsigned_byte(dst, src); 2274 shll(dst, 24); 2275 sarl(dst, 24); 2276 } 2277 return off; 2278 } 2279 2280 // Note: load_signed_short used to be called load_signed_word. 2281 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 2282 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 2283 // The term "word" in HotSpot means a 32- or 64-bit machine word. 2284 int MacroAssembler::load_signed_short(Register dst, Address src) { 2285 int off; 2286 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2287 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 2288 // version but this is what 64bit has always done. This seems to imply 2289 // that users are only using 32bits worth. 2290 off = offset(); 2291 movswl(dst, src); // movsxw 2292 } else { 2293 off = load_unsigned_short(dst, src); 2294 shll(dst, 16); 2295 sarl(dst, 16); 2296 } 2297 return off; 2298 } 2299 2300 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 2301 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2302 // and "3.9 Partial Register Penalties", p. 22). 2303 int off; 2304 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 2305 off = offset(); 2306 movzbl(dst, src); // movzxb 2307 } else { 2308 xorl(dst, dst); 2309 off = offset(); 2310 movb(dst, src); 2311 } 2312 return off; 2313 } 2314 2315 // Note: load_unsigned_short used to be called load_unsigned_word. 2316 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 2317 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 2318 // and "3.9 Partial Register Penalties", p. 22). 2319 int off; 2320 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 2321 off = offset(); 2322 movzwl(dst, src); // movzxw 2323 } else { 2324 xorl(dst, dst); 2325 off = offset(); 2326 movw(dst, src); 2327 } 2328 return off; 2329 } 2330 2331 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 2332 switch (size_in_bytes) { 2333 #ifndef _LP64 2334 case 8: 2335 assert(dst2 != noreg, "second dest register required"); 2336 movl(dst, src); 2337 movl(dst2, src.plus_disp(BytesPerInt)); 2338 break; 2339 #else 2340 case 8: movq(dst, src); break; 2341 #endif 2342 case 4: movl(dst, src); break; 2343 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 2344 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 2345 default: ShouldNotReachHere(); 2346 } 2347 } 2348 2349 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 2350 switch (size_in_bytes) { 2351 #ifndef _LP64 2352 case 8: 2353 assert(src2 != noreg, "second source register required"); 2354 movl(dst, src); 2355 movl(dst.plus_disp(BytesPerInt), src2); 2356 break; 2357 #else 2358 case 8: movq(dst, src); break; 2359 #endif 2360 case 4: movl(dst, src); break; 2361 case 2: movw(dst, src); break; 2362 case 1: movb(dst, src); break; 2363 default: ShouldNotReachHere(); 2364 } 2365 } 2366 2367 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 2368 if (reachable(dst)) { 2369 movl(as_Address(dst), src); 2370 } else { 2371 lea(rscratch1, dst); 2372 movl(Address(rscratch1, 0), src); 2373 } 2374 } 2375 2376 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 2377 if (reachable(src)) { 2378 movl(dst, as_Address(src)); 2379 } else { 2380 lea(rscratch1, src); 2381 movl(dst, Address(rscratch1, 0)); 2382 } 2383 } 2384 2385 // C++ bool manipulation 2386 2387 void MacroAssembler::movbool(Register dst, Address src) { 2388 if(sizeof(bool) == 1) 2389 movb(dst, src); 2390 else if(sizeof(bool) == 2) 2391 movw(dst, src); 2392 else if(sizeof(bool) == 4) 2393 movl(dst, src); 2394 else 2395 // unsupported 2396 ShouldNotReachHere(); 2397 } 2398 2399 void MacroAssembler::movbool(Address dst, bool boolconst) { 2400 if(sizeof(bool) == 1) 2401 movb(dst, (int) boolconst); 2402 else if(sizeof(bool) == 2) 2403 movw(dst, (int) boolconst); 2404 else if(sizeof(bool) == 4) 2405 movl(dst, (int) boolconst); 2406 else 2407 // unsupported 2408 ShouldNotReachHere(); 2409 } 2410 2411 void MacroAssembler::movbool(Address dst, Register src) { 2412 if(sizeof(bool) == 1) 2413 movb(dst, src); 2414 else if(sizeof(bool) == 2) 2415 movw(dst, src); 2416 else if(sizeof(bool) == 4) 2417 movl(dst, src); 2418 else 2419 // unsupported 2420 ShouldNotReachHere(); 2421 } 2422 2423 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 2424 movb(as_Address(dst), src); 2425 } 2426 2427 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 2428 if (reachable(src)) { 2429 movdl(dst, as_Address(src)); 2430 } else { 2431 lea(rscratch1, src); 2432 movdl(dst, Address(rscratch1, 0)); 2433 } 2434 } 2435 2436 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 2437 if (reachable(src)) { 2438 movq(dst, as_Address(src)); 2439 } else { 2440 lea(rscratch1, src); 2441 movq(dst, Address(rscratch1, 0)); 2442 } 2443 } 2444 2445 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 2446 if (reachable(src)) { 2447 if (UseXmmLoadAndClearUpper) { 2448 movsd (dst, as_Address(src)); 2449 } else { 2450 movlpd(dst, as_Address(src)); 2451 } 2452 } else { 2453 lea(rscratch1, src); 2454 if (UseXmmLoadAndClearUpper) { 2455 movsd (dst, Address(rscratch1, 0)); 2456 } else { 2457 movlpd(dst, Address(rscratch1, 0)); 2458 } 2459 } 2460 } 2461 2462 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 2463 if (reachable(src)) { 2464 movss(dst, as_Address(src)); 2465 } else { 2466 lea(rscratch1, src); 2467 movss(dst, Address(rscratch1, 0)); 2468 } 2469 } 2470 2471 void MacroAssembler::movptr(Register dst, Register src) { 2472 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2473 } 2474 2475 void MacroAssembler::movptr(Register dst, Address src) { 2476 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2477 } 2478 2479 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 2480 void MacroAssembler::movptr(Register dst, intptr_t src) { 2481 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 2482 } 2483 2484 void MacroAssembler::movptr(Address dst, Register src) { 2485 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 2486 } 2487 2488 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 2489 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2490 Assembler::movdqu(dst, src); 2491 } 2492 2493 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 2494 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2495 Assembler::movdqu(dst, src); 2496 } 2497 2498 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 2499 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2500 Assembler::movdqu(dst, src); 2501 } 2502 2503 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) { 2504 if (reachable(src)) { 2505 movdqu(dst, as_Address(src)); 2506 } else { 2507 lea(scratchReg, src); 2508 movdqu(dst, Address(scratchReg, 0)); 2509 } 2510 } 2511 2512 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 2513 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2514 Assembler::vmovdqu(dst, src); 2515 } 2516 2517 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 2518 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2519 Assembler::vmovdqu(dst, src); 2520 } 2521 2522 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 2523 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 2524 Assembler::vmovdqu(dst, src); 2525 } 2526 2527 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 2528 if (reachable(src)) { 2529 vmovdqu(dst, as_Address(src)); 2530 } 2531 else { 2532 lea(scratch_reg, src); 2533 vmovdqu(dst, Address(scratch_reg, 0)); 2534 } 2535 } 2536 2537 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg, int vector_len) { 2538 assert(vector_len <= AVX_256bit, "AVX2 vector length"); 2539 if (vector_len == AVX_256bit) { 2540 vmovdqu(dst, src, scratch_reg); 2541 } else { 2542 movdqu(dst, src, scratch_reg); 2543 } 2544 } 2545 2546 void MacroAssembler::kmov(KRegister dst, Address src) { 2547 if (VM_Version::supports_avx512bw()) { 2548 kmovql(dst, src); 2549 } else { 2550 assert(VM_Version::supports_evex(), ""); 2551 kmovwl(dst, src); 2552 } 2553 } 2554 2555 void MacroAssembler::kmov(Address dst, KRegister src) { 2556 if (VM_Version::supports_avx512bw()) { 2557 kmovql(dst, src); 2558 } else { 2559 assert(VM_Version::supports_evex(), ""); 2560 kmovwl(dst, src); 2561 } 2562 } 2563 2564 void MacroAssembler::kmov(KRegister dst, KRegister src) { 2565 if (VM_Version::supports_avx512bw()) { 2566 kmovql(dst, src); 2567 } else { 2568 assert(VM_Version::supports_evex(), ""); 2569 kmovwl(dst, src); 2570 } 2571 } 2572 2573 void MacroAssembler::kmov(Register dst, KRegister src) { 2574 if (VM_Version::supports_avx512bw()) { 2575 kmovql(dst, src); 2576 } else { 2577 assert(VM_Version::supports_evex(), ""); 2578 kmovwl(dst, src); 2579 } 2580 } 2581 2582 void MacroAssembler::kmov(KRegister dst, Register src) { 2583 if (VM_Version::supports_avx512bw()) { 2584 kmovql(dst, src); 2585 } else { 2586 assert(VM_Version::supports_evex(), ""); 2587 kmovwl(dst, src); 2588 } 2589 } 2590 2591 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) { 2592 if (reachable(src)) { 2593 kmovql(dst, as_Address(src)); 2594 } else { 2595 lea(scratch_reg, src); 2596 kmovql(dst, Address(scratch_reg, 0)); 2597 } 2598 } 2599 2600 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) { 2601 if (reachable(src)) { 2602 kmovwl(dst, as_Address(src)); 2603 } else { 2604 lea(scratch_reg, src); 2605 kmovwl(dst, Address(scratch_reg, 0)); 2606 } 2607 } 2608 2609 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2610 int vector_len, Register scratch_reg) { 2611 if (reachable(src)) { 2612 if (mask == k0) { 2613 Assembler::evmovdqub(dst, as_Address(src), merge, vector_len); 2614 } else { 2615 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len); 2616 } 2617 } else { 2618 lea(scratch_reg, src); 2619 if (mask == k0) { 2620 Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len); 2621 } else { 2622 Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2623 } 2624 } 2625 } 2626 2627 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2628 int vector_len, Register scratch_reg) { 2629 if (reachable(src)) { 2630 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len); 2631 } else { 2632 lea(scratch_reg, src); 2633 Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2634 } 2635 } 2636 2637 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2638 int vector_len, Register scratch_reg) { 2639 if (reachable(src)) { 2640 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len); 2641 } else { 2642 lea(scratch_reg, src); 2643 Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2644 } 2645 } 2646 2647 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, 2648 int vector_len, Register scratch_reg) { 2649 if (reachable(src)) { 2650 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len); 2651 } else { 2652 lea(scratch_reg, src); 2653 Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len); 2654 } 2655 } 2656 2657 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2658 if (reachable(src)) { 2659 Assembler::evmovdquq(dst, as_Address(src), vector_len); 2660 } else { 2661 lea(rscratch, src); 2662 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len); 2663 } 2664 } 2665 2666 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 2667 if (reachable(src)) { 2668 Assembler::movdqa(dst, as_Address(src)); 2669 } else { 2670 lea(rscratch1, src); 2671 Assembler::movdqa(dst, Address(rscratch1, 0)); 2672 } 2673 } 2674 2675 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 2676 if (reachable(src)) { 2677 Assembler::movsd(dst, as_Address(src)); 2678 } else { 2679 lea(rscratch1, src); 2680 Assembler::movsd(dst, Address(rscratch1, 0)); 2681 } 2682 } 2683 2684 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 2685 if (reachable(src)) { 2686 Assembler::movss(dst, as_Address(src)); 2687 } else { 2688 lea(rscratch1, src); 2689 Assembler::movss(dst, Address(rscratch1, 0)); 2690 } 2691 } 2692 2693 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 2694 if (reachable(src)) { 2695 Assembler::vmovddup(dst, as_Address(src), vector_len); 2696 } else { 2697 lea(rscratch, src); 2698 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len); 2699 } 2700 } 2701 2702 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 2703 if (reachable(src)) { 2704 Assembler::mulsd(dst, as_Address(src)); 2705 } else { 2706 lea(rscratch1, src); 2707 Assembler::mulsd(dst, Address(rscratch1, 0)); 2708 } 2709 } 2710 2711 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 2712 if (reachable(src)) { 2713 Assembler::mulss(dst, as_Address(src)); 2714 } else { 2715 lea(rscratch1, src); 2716 Assembler::mulss(dst, Address(rscratch1, 0)); 2717 } 2718 } 2719 2720 void MacroAssembler::null_check(Register reg, int offset) { 2721 if (needs_explicit_null_check(offset)) { 2722 // provoke OS NULL exception if reg = NULL by 2723 // accessing M[reg] w/o changing any (non-CC) registers 2724 // NOTE: cmpl is plenty here to provoke a segv 2725 cmpptr(rax, Address(reg, 0)); 2726 // Note: should probably use testl(rax, Address(reg, 0)); 2727 // may be shorter code (however, this version of 2728 // testl needs to be implemented first) 2729 } else { 2730 // nothing to do, (later) access of M[reg + offset] 2731 // will provoke OS NULL exception if reg = NULL 2732 } 2733 } 2734 2735 void MacroAssembler::os_breakpoint() { 2736 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 2737 // (e.g., MSVC can't call ps() otherwise) 2738 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 2739 } 2740 2741 void MacroAssembler::unimplemented(const char* what) { 2742 const char* buf = NULL; 2743 { 2744 ResourceMark rm; 2745 stringStream ss; 2746 ss.print("unimplemented: %s", what); 2747 buf = code_string(ss.as_string()); 2748 } 2749 stop(buf); 2750 } 2751 2752 #ifdef _LP64 2753 #define XSTATE_BV 0x200 2754 #endif 2755 2756 void MacroAssembler::pop_CPU_state() { 2757 pop_FPU_state(); 2758 pop_IU_state(); 2759 } 2760 2761 void MacroAssembler::pop_FPU_state() { 2762 #ifndef _LP64 2763 frstor(Address(rsp, 0)); 2764 #else 2765 fxrstor(Address(rsp, 0)); 2766 #endif 2767 addptr(rsp, FPUStateSizeInWords * wordSize); 2768 } 2769 2770 void MacroAssembler::pop_IU_state() { 2771 popa(); 2772 LP64_ONLY(addq(rsp, 8)); 2773 popf(); 2774 } 2775 2776 // Save Integer and Float state 2777 // Warning: Stack must be 16 byte aligned (64bit) 2778 void MacroAssembler::push_CPU_state() { 2779 push_IU_state(); 2780 push_FPU_state(); 2781 } 2782 2783 void MacroAssembler::push_FPU_state() { 2784 subptr(rsp, FPUStateSizeInWords * wordSize); 2785 #ifndef _LP64 2786 fnsave(Address(rsp, 0)); 2787 fwait(); 2788 #else 2789 fxsave(Address(rsp, 0)); 2790 #endif // LP64 2791 } 2792 2793 void MacroAssembler::push_IU_state() { 2794 // Push flags first because pusha kills them 2795 pushf(); 2796 // Make sure rsp stays 16-byte aligned 2797 LP64_ONLY(subq(rsp, 8)); 2798 pusha(); 2799 } 2800 2801 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register 2802 if (!java_thread->is_valid()) { 2803 java_thread = rdi; 2804 get_thread(java_thread); 2805 } 2806 // we must set sp to zero to clear frame 2807 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 2808 // must clear fp, so that compiled frames are not confused; it is 2809 // possible that we need it only for debugging 2810 if (clear_fp) { 2811 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 2812 } 2813 // Always clear the pc because it could have been set by make_walkable() 2814 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 2815 vzeroupper(); 2816 } 2817 2818 void MacroAssembler::restore_rax(Register tmp) { 2819 if (tmp == noreg) pop(rax); 2820 else if (tmp != rax) mov(rax, tmp); 2821 } 2822 2823 void MacroAssembler::round_to(Register reg, int modulus) { 2824 addptr(reg, modulus - 1); 2825 andptr(reg, -modulus); 2826 } 2827 2828 void MacroAssembler::save_rax(Register tmp) { 2829 if (tmp == noreg) push(rax); 2830 else if (tmp != rax) mov(tmp, rax); 2831 } 2832 2833 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) { 2834 if (at_return) { 2835 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore, 2836 // we may safely use rsp instead to perform the stack watermark check. 2837 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset())); 2838 jcc(Assembler::above, slow_path); 2839 return; 2840 } 2841 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit()); 2842 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll 2843 } 2844 2845 // Calls to C land 2846 // 2847 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 2848 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 2849 // has to be reset to 0. This is required to allow proper stack traversal. 2850 void MacroAssembler::set_last_Java_frame(Register java_thread, 2851 Register last_java_sp, 2852 Register last_java_fp, 2853 address last_java_pc) { 2854 vzeroupper(); 2855 // determine java_thread register 2856 if (!java_thread->is_valid()) { 2857 java_thread = rdi; 2858 get_thread(java_thread); 2859 } 2860 // determine last_java_sp register 2861 if (!last_java_sp->is_valid()) { 2862 last_java_sp = rsp; 2863 } 2864 2865 // last_java_fp is optional 2866 2867 if (last_java_fp->is_valid()) { 2868 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 2869 } 2870 2871 // last_java_pc is optional 2872 2873 if (last_java_pc != NULL) { 2874 lea(Address(java_thread, 2875 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 2876 InternalAddress(last_java_pc)); 2877 2878 } 2879 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 2880 } 2881 2882 void MacroAssembler::shlptr(Register dst, int imm8) { 2883 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 2884 } 2885 2886 void MacroAssembler::shrptr(Register dst, int imm8) { 2887 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 2888 } 2889 2890 void MacroAssembler::sign_extend_byte(Register reg) { 2891 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 2892 movsbl(reg, reg); // movsxb 2893 } else { 2894 shll(reg, 24); 2895 sarl(reg, 24); 2896 } 2897 } 2898 2899 void MacroAssembler::sign_extend_short(Register reg) { 2900 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 2901 movswl(reg, reg); // movsxw 2902 } else { 2903 shll(reg, 16); 2904 sarl(reg, 16); 2905 } 2906 } 2907 2908 void MacroAssembler::testl(Register dst, AddressLiteral src) { 2909 assert(reachable(src), "Address should be reachable"); 2910 testl(dst, as_Address(src)); 2911 } 2912 2913 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 2914 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2915 Assembler::pcmpeqb(dst, src); 2916 } 2917 2918 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 2919 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2920 Assembler::pcmpeqw(dst, src); 2921 } 2922 2923 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 2924 assert((dst->encoding() < 16),"XMM register should be 0-15"); 2925 Assembler::pcmpestri(dst, src, imm8); 2926 } 2927 2928 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 2929 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 2930 Assembler::pcmpestri(dst, src, imm8); 2931 } 2932 2933 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 2934 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2935 Assembler::pmovzxbw(dst, src); 2936 } 2937 2938 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 2939 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 2940 Assembler::pmovzxbw(dst, src); 2941 } 2942 2943 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 2944 assert((src->encoding() < 16),"XMM register should be 0-15"); 2945 Assembler::pmovmskb(dst, src); 2946 } 2947 2948 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 2949 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 2950 Assembler::ptest(dst, src); 2951 } 2952 2953 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 2954 if (reachable(src)) { 2955 Assembler::sqrtsd(dst, as_Address(src)); 2956 } else { 2957 lea(rscratch1, src); 2958 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 2959 } 2960 } 2961 2962 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 2963 if (reachable(src)) { 2964 Assembler::sqrtss(dst, as_Address(src)); 2965 } else { 2966 lea(rscratch1, src); 2967 Assembler::sqrtss(dst, Address(rscratch1, 0)); 2968 } 2969 } 2970 2971 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 2972 if (reachable(src)) { 2973 Assembler::subsd(dst, as_Address(src)); 2974 } else { 2975 lea(rscratch1, src); 2976 Assembler::subsd(dst, Address(rscratch1, 0)); 2977 } 2978 } 2979 2980 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) { 2981 if (reachable(src)) { 2982 Assembler::roundsd(dst, as_Address(src), rmode); 2983 } else { 2984 lea(scratch_reg, src); 2985 Assembler::roundsd(dst, Address(scratch_reg, 0), rmode); 2986 } 2987 } 2988 2989 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 2990 if (reachable(src)) { 2991 Assembler::subss(dst, as_Address(src)); 2992 } else { 2993 lea(rscratch1, src); 2994 Assembler::subss(dst, Address(rscratch1, 0)); 2995 } 2996 } 2997 2998 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 2999 if (reachable(src)) { 3000 Assembler::ucomisd(dst, as_Address(src)); 3001 } else { 3002 lea(rscratch1, src); 3003 Assembler::ucomisd(dst, Address(rscratch1, 0)); 3004 } 3005 } 3006 3007 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 3008 if (reachable(src)) { 3009 Assembler::ucomiss(dst, as_Address(src)); 3010 } else { 3011 lea(rscratch1, src); 3012 Assembler::ucomiss(dst, Address(rscratch1, 0)); 3013 } 3014 } 3015 3016 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 3017 // Used in sign-bit flipping with aligned address. 3018 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3019 if (reachable(src)) { 3020 Assembler::xorpd(dst, as_Address(src)); 3021 } else { 3022 lea(scratch_reg, src); 3023 Assembler::xorpd(dst, Address(scratch_reg, 0)); 3024 } 3025 } 3026 3027 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 3028 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 3029 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 3030 } 3031 else { 3032 Assembler::xorpd(dst, src); 3033 } 3034 } 3035 3036 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 3037 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 3038 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 3039 } else { 3040 Assembler::xorps(dst, src); 3041 } 3042 } 3043 3044 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) { 3045 // Used in sign-bit flipping with aligned address. 3046 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 3047 if (reachable(src)) { 3048 Assembler::xorps(dst, as_Address(src)); 3049 } else { 3050 lea(scratch_reg, src); 3051 Assembler::xorps(dst, Address(scratch_reg, 0)); 3052 } 3053 } 3054 3055 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 3056 // Used in sign-bit flipping with aligned address. 3057 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 3058 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 3059 if (reachable(src)) { 3060 Assembler::pshufb(dst, as_Address(src)); 3061 } else { 3062 lea(rscratch1, src); 3063 Assembler::pshufb(dst, Address(rscratch1, 0)); 3064 } 3065 } 3066 3067 // AVX 3-operands instructions 3068 3069 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3070 if (reachable(src)) { 3071 vaddsd(dst, nds, as_Address(src)); 3072 } else { 3073 lea(rscratch1, src); 3074 vaddsd(dst, nds, Address(rscratch1, 0)); 3075 } 3076 } 3077 3078 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3079 if (reachable(src)) { 3080 vaddss(dst, nds, as_Address(src)); 3081 } else { 3082 lea(rscratch1, src); 3083 vaddss(dst, nds, Address(rscratch1, 0)); 3084 } 3085 } 3086 3087 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3088 assert(UseAVX > 0, "requires some form of AVX"); 3089 if (reachable(src)) { 3090 Assembler::vpaddb(dst, nds, as_Address(src), vector_len); 3091 } else { 3092 lea(rscratch, src); 3093 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len); 3094 } 3095 } 3096 3097 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) { 3098 assert(UseAVX > 0, "requires some form of AVX"); 3099 if (reachable(src)) { 3100 Assembler::vpaddd(dst, nds, as_Address(src), vector_len); 3101 } else { 3102 lea(rscratch, src); 3103 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len); 3104 } 3105 } 3106 3107 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 3108 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3109 vandps(dst, nds, negate_field, vector_len); 3110 } 3111 3112 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 3113 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3114 vandpd(dst, nds, negate_field, vector_len); 3115 } 3116 3117 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3118 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3119 Assembler::vpaddb(dst, nds, src, vector_len); 3120 } 3121 3122 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3123 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3124 Assembler::vpaddb(dst, nds, src, vector_len); 3125 } 3126 3127 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3128 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3129 Assembler::vpaddw(dst, nds, src, vector_len); 3130 } 3131 3132 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3133 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3134 Assembler::vpaddw(dst, nds, src, vector_len); 3135 } 3136 3137 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3138 if (reachable(src)) { 3139 Assembler::vpand(dst, nds, as_Address(src), vector_len); 3140 } else { 3141 lea(scratch_reg, src); 3142 Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len); 3143 } 3144 } 3145 3146 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) { 3147 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3148 Assembler::vpbroadcastw(dst, src, vector_len); 3149 } 3150 3151 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) { 3152 if (reachable(src)) { 3153 Assembler::vbroadcastsd(dst, as_Address(src), vector_len); 3154 } else { 3155 lea(rscratch, src); 3156 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len); 3157 } 3158 } 3159 3160 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3161 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3162 Assembler::vpcmpeqb(dst, nds, src, vector_len); 3163 } 3164 3165 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3166 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3167 Assembler::vpcmpeqw(dst, nds, src, vector_len); 3168 } 3169 3170 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, 3171 AddressLiteral src, int vector_len, Register scratch_reg) { 3172 if (reachable(src)) { 3173 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len); 3174 } else { 3175 lea(scratch_reg, src); 3176 Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len); 3177 } 3178 } 3179 3180 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3181 int comparison, bool is_signed, int vector_len, Register scratch_reg) { 3182 if (reachable(src)) { 3183 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3184 } else { 3185 lea(scratch_reg, src); 3186 Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len); 3187 } 3188 } 3189 3190 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3191 int comparison, bool is_signed, int vector_len, Register scratch_reg) { 3192 if (reachable(src)) { 3193 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3194 } else { 3195 lea(scratch_reg, src); 3196 Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len); 3197 } 3198 } 3199 3200 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3201 int comparison, bool is_signed, int vector_len, Register scratch_reg) { 3202 if (reachable(src)) { 3203 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3204 } else { 3205 lea(scratch_reg, src); 3206 Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len); 3207 } 3208 } 3209 3210 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, 3211 int comparison, bool is_signed, int vector_len, Register scratch_reg) { 3212 if (reachable(src)) { 3213 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len); 3214 } else { 3215 lea(scratch_reg, src); 3216 Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len); 3217 } 3218 } 3219 3220 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) { 3221 if (width == Assembler::Q) { 3222 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len); 3223 } else { 3224 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len); 3225 } 3226 } 3227 3228 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) { 3229 int eq_cond_enc = 0x29; 3230 int gt_cond_enc = 0x37; 3231 if (width != Assembler::Q) { 3232 eq_cond_enc = 0x74 + width; 3233 gt_cond_enc = 0x64 + width; 3234 } 3235 switch (cond) { 3236 case eq: 3237 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3238 break; 3239 case neq: 3240 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len); 3241 vallones(xtmp, vector_len); 3242 vpxor(dst, xtmp, dst, vector_len); 3243 break; 3244 case le: 3245 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3246 vallones(xtmp, vector_len); 3247 vpxor(dst, xtmp, dst, vector_len); 3248 break; 3249 case nlt: 3250 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3251 vallones(xtmp, vector_len); 3252 vpxor(dst, xtmp, dst, vector_len); 3253 break; 3254 case lt: 3255 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len); 3256 break; 3257 case nle: 3258 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len); 3259 break; 3260 default: 3261 assert(false, "Should not reach here"); 3262 } 3263 } 3264 3265 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 3266 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3267 Assembler::vpmovzxbw(dst, src, vector_len); 3268 } 3269 3270 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) { 3271 assert((src->encoding() < 16),"XMM register should be 0-15"); 3272 Assembler::vpmovmskb(dst, src, vector_len); 3273 } 3274 3275 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3276 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3277 Assembler::vpmullw(dst, nds, src, vector_len); 3278 } 3279 3280 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3281 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3282 Assembler::vpmullw(dst, nds, src, vector_len); 3283 } 3284 3285 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3286 assert((UseAVX > 0), "AVX support is needed"); 3287 if (reachable(src)) { 3288 Assembler::vpmulld(dst, nds, as_Address(src), vector_len); 3289 } else { 3290 lea(scratch_reg, src); 3291 Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len); 3292 } 3293 } 3294 3295 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3296 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3297 Assembler::vpsubb(dst, nds, src, vector_len); 3298 } 3299 3300 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3301 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3302 Assembler::vpsubb(dst, nds, src, vector_len); 3303 } 3304 3305 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 3306 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3307 Assembler::vpsubw(dst, nds, src, vector_len); 3308 } 3309 3310 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 3311 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3312 Assembler::vpsubw(dst, nds, src, vector_len); 3313 } 3314 3315 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3316 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3317 Assembler::vpsraw(dst, nds, shift, vector_len); 3318 } 3319 3320 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3321 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3322 Assembler::vpsraw(dst, nds, shift, vector_len); 3323 } 3324 3325 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3326 assert(UseAVX > 2,""); 3327 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3328 vector_len = 2; 3329 } 3330 Assembler::evpsraq(dst, nds, shift, vector_len); 3331 } 3332 3333 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3334 assert(UseAVX > 2,""); 3335 if (!VM_Version::supports_avx512vl() && vector_len < 2) { 3336 vector_len = 2; 3337 } 3338 Assembler::evpsraq(dst, nds, shift, vector_len); 3339 } 3340 3341 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3342 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3343 Assembler::vpsrlw(dst, nds, shift, vector_len); 3344 } 3345 3346 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3347 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3348 Assembler::vpsrlw(dst, nds, shift, vector_len); 3349 } 3350 3351 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 3352 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3353 Assembler::vpsllw(dst, nds, shift, vector_len); 3354 } 3355 3356 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 3357 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3358 Assembler::vpsllw(dst, nds, shift, vector_len); 3359 } 3360 3361 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 3362 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15"); 3363 Assembler::vptest(dst, src); 3364 } 3365 3366 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 3367 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3368 Assembler::punpcklbw(dst, src); 3369 } 3370 3371 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) { 3372 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15"); 3373 Assembler::pshufd(dst, src, mode); 3374 } 3375 3376 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 3377 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15"); 3378 Assembler::pshuflw(dst, src, mode); 3379 } 3380 3381 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3382 if (reachable(src)) { 3383 vandpd(dst, nds, as_Address(src), vector_len); 3384 } else { 3385 lea(scratch_reg, src); 3386 vandpd(dst, nds, Address(scratch_reg, 0), vector_len); 3387 } 3388 } 3389 3390 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3391 if (reachable(src)) { 3392 vandps(dst, nds, as_Address(src), vector_len); 3393 } else { 3394 lea(scratch_reg, src); 3395 vandps(dst, nds, Address(scratch_reg, 0), vector_len); 3396 } 3397 } 3398 3399 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, 3400 bool merge, int vector_len, Register scratch_reg) { 3401 if (reachable(src)) { 3402 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len); 3403 } else { 3404 lea(scratch_reg, src); 3405 Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len); 3406 } 3407 } 3408 3409 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3410 if (reachable(src)) { 3411 vdivsd(dst, nds, as_Address(src)); 3412 } else { 3413 lea(rscratch1, src); 3414 vdivsd(dst, nds, Address(rscratch1, 0)); 3415 } 3416 } 3417 3418 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3419 if (reachable(src)) { 3420 vdivss(dst, nds, as_Address(src)); 3421 } else { 3422 lea(rscratch1, src); 3423 vdivss(dst, nds, Address(rscratch1, 0)); 3424 } 3425 } 3426 3427 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3428 if (reachable(src)) { 3429 vmulsd(dst, nds, as_Address(src)); 3430 } else { 3431 lea(rscratch1, src); 3432 vmulsd(dst, nds, Address(rscratch1, 0)); 3433 } 3434 } 3435 3436 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3437 if (reachable(src)) { 3438 vmulss(dst, nds, as_Address(src)); 3439 } else { 3440 lea(rscratch1, src); 3441 vmulss(dst, nds, Address(rscratch1, 0)); 3442 } 3443 } 3444 3445 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3446 if (reachable(src)) { 3447 vsubsd(dst, nds, as_Address(src)); 3448 } else { 3449 lea(rscratch1, src); 3450 vsubsd(dst, nds, Address(rscratch1, 0)); 3451 } 3452 } 3453 3454 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3455 if (reachable(src)) { 3456 vsubss(dst, nds, as_Address(src)); 3457 } else { 3458 lea(rscratch1, src); 3459 vsubss(dst, nds, Address(rscratch1, 0)); 3460 } 3461 } 3462 3463 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3464 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3465 vxorps(dst, nds, src, Assembler::AVX_128bit); 3466 } 3467 3468 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 3469 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15"); 3470 vxorpd(dst, nds, src, Assembler::AVX_128bit); 3471 } 3472 3473 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3474 if (reachable(src)) { 3475 vxorpd(dst, nds, as_Address(src), vector_len); 3476 } else { 3477 lea(scratch_reg, src); 3478 vxorpd(dst, nds, Address(scratch_reg, 0), vector_len); 3479 } 3480 } 3481 3482 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3483 if (reachable(src)) { 3484 vxorps(dst, nds, as_Address(src), vector_len); 3485 } else { 3486 lea(scratch_reg, src); 3487 vxorps(dst, nds, Address(scratch_reg, 0), vector_len); 3488 } 3489 } 3490 3491 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3492 if (UseAVX > 1 || (vector_len < 1)) { 3493 if (reachable(src)) { 3494 Assembler::vpxor(dst, nds, as_Address(src), vector_len); 3495 } else { 3496 lea(scratch_reg, src); 3497 Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len); 3498 } 3499 } 3500 else { 3501 MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg); 3502 } 3503 } 3504 3505 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) { 3506 if (reachable(src)) { 3507 Assembler::vpermd(dst, nds, as_Address(src), vector_len); 3508 } else { 3509 lea(scratch_reg, src); 3510 Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len); 3511 } 3512 } 3513 3514 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) { 3515 const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask); 3516 STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code 3517 // The inverted mask is sign-extended 3518 andptr(possibly_jweak, inverted_jweak_mask); 3519 } 3520 3521 void MacroAssembler::resolve_jobject(Register value, 3522 Register thread, 3523 Register tmp) { 3524 assert_different_registers(value, thread, tmp); 3525 Label done, not_weak; 3526 testptr(value, value); 3527 jcc(Assembler::zero, done); // Use NULL as-is. 3528 testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag. 3529 jcc(Assembler::zero, not_weak); 3530 // Resolve jweak. 3531 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 3532 value, Address(value, -JNIHandles::weak_tag_value), tmp, thread); 3533 verify_oop(value); 3534 jmp(done); 3535 bind(not_weak); 3536 // Resolve (untagged) jobject. 3537 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread); 3538 verify_oop(value); 3539 bind(done); 3540 } 3541 3542 void MacroAssembler::subptr(Register dst, int32_t imm32) { 3543 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 3544 } 3545 3546 // Force generation of a 4 byte immediate value even if it fits into 8bit 3547 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 3548 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 3549 } 3550 3551 void MacroAssembler::subptr(Register dst, Register src) { 3552 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 3553 } 3554 3555 // C++ bool manipulation 3556 void MacroAssembler::testbool(Register dst) { 3557 if(sizeof(bool) == 1) 3558 testb(dst, 0xff); 3559 else if(sizeof(bool) == 2) { 3560 // testw implementation needed for two byte bools 3561 ShouldNotReachHere(); 3562 } else if(sizeof(bool) == 4) 3563 testl(dst, dst); 3564 else 3565 // unsupported 3566 ShouldNotReachHere(); 3567 } 3568 3569 void MacroAssembler::testptr(Register dst, Register src) { 3570 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 3571 } 3572 3573 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 3574 void MacroAssembler::tlab_allocate(Register thread, Register obj, 3575 Register var_size_in_bytes, 3576 int con_size_in_bytes, 3577 Register t1, 3578 Register t2, 3579 Label& slow_case) { 3580 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3581 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case); 3582 } 3583 3584 RegSet MacroAssembler::call_clobbered_gp_registers() { 3585 RegSet regs; 3586 #ifdef _LP64 3587 regs += RegSet::of(rax, rcx, rdx); 3588 #ifndef WINDOWS 3589 regs += RegSet::of(rsi, rdi); 3590 #endif 3591 regs += RegSet::range(r8, r11); 3592 #else 3593 regs += RegSet::of(rax, rcx, rdx); 3594 #endif 3595 return regs; 3596 } 3597 3598 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() { 3599 int num_xmm_registers = XMMRegisterImpl::available_xmm_registers(); 3600 #if defined(WINDOWS) && defined(_LP64) 3601 XMMRegSet result = XMMRegSet::range(xmm0, xmm5); 3602 if (num_xmm_registers > 16) { 3603 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1)); 3604 } 3605 return result; 3606 #else 3607 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1)); 3608 #endif 3609 } 3610 3611 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor 3612 3613 #ifndef _LP64 3614 static bool use_x87_registers() { return UseSSE < 2; } 3615 #endif 3616 static bool use_xmm_registers() { return UseSSE >= 1; } 3617 3618 // C1 only ever uses the first double/float of the XMM register. 3619 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); } 3620 3621 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) { 3622 if (UseSSE == 1) { 3623 masm->movflt(Address(rsp, offset), reg); 3624 } else { 3625 masm->movdbl(Address(rsp, offset), reg); 3626 } 3627 } 3628 3629 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) { 3630 if (UseSSE == 1) { 3631 masm->movflt(reg, Address(rsp, offset)); 3632 } else { 3633 masm->movdbl(reg, Address(rsp, offset)); 3634 } 3635 } 3636 3637 int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers, bool save_fpu, 3638 int& gp_area_size, int& fp_area_size, int& xmm_area_size) { 3639 3640 gp_area_size = align_up(gp_registers.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size, 3641 StackAlignmentInBytes); 3642 #ifdef _LP64 3643 fp_area_size = 0; 3644 #else 3645 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0; 3646 #endif 3647 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0; 3648 3649 return gp_area_size + fp_area_size + xmm_area_size; 3650 } 3651 3652 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) { 3653 block_comment("push_call_clobbered_registers start"); 3654 // Regular registers 3655 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude; 3656 3657 int gp_area_size; 3658 int fp_area_size; 3659 int xmm_area_size; 3660 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu, 3661 gp_area_size, fp_area_size, xmm_area_size); 3662 subptr(rsp, total_save_size); 3663 3664 push_set(gp_registers_to_push, 0); 3665 3666 #ifndef _LP64 3667 if (save_fpu && use_x87_registers()) { 3668 fnsave(Address(rsp, gp_area_size)); 3669 fwait(); 3670 } 3671 #endif 3672 if (save_fpu && use_xmm_registers()) { 3673 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size); 3674 } 3675 3676 block_comment("push_call_clobbered_registers end"); 3677 } 3678 3679 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) { 3680 block_comment("pop_call_clobbered_registers start"); 3681 3682 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude; 3683 3684 int gp_area_size; 3685 int fp_area_size; 3686 int xmm_area_size; 3687 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu, 3688 gp_area_size, fp_area_size, xmm_area_size); 3689 3690 if (restore_fpu && use_xmm_registers()) { 3691 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size); 3692 } 3693 #ifndef _LP64 3694 if (restore_fpu && use_x87_registers()) { 3695 frstor(Address(rsp, gp_area_size)); 3696 } 3697 #endif 3698 3699 pop_set(gp_registers_to_pop, 0); 3700 3701 addptr(rsp, total_save_size); 3702 3703 vzeroupper(); 3704 3705 block_comment("pop_call_clobbered_registers end"); 3706 } 3707 3708 void MacroAssembler::push_set(XMMRegSet set, int offset) { 3709 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be"); 3710 int spill_offset = offset; 3711 3712 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) { 3713 save_xmm_register(this, spill_offset, *it); 3714 spill_offset += xmm_save_size(); 3715 } 3716 } 3717 3718 void MacroAssembler::pop_set(XMMRegSet set, int offset) { 3719 int restore_size = set.size() * xmm_save_size(); 3720 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be"); 3721 3722 int restore_offset = offset + restore_size - xmm_save_size(); 3723 3724 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) { 3725 restore_xmm_register(this, restore_offset, *it); 3726 restore_offset -= xmm_save_size(); 3727 } 3728 } 3729 3730 void MacroAssembler::push_set(RegSet set, int offset) { 3731 int spill_offset; 3732 if (offset == -1) { 3733 int register_push_size = set.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size; 3734 int aligned_size = align_up(register_push_size, StackAlignmentInBytes); 3735 subptr(rsp, aligned_size); 3736 spill_offset = 0; 3737 } else { 3738 spill_offset = offset; 3739 } 3740 3741 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) { 3742 movptr(Address(rsp, spill_offset), *it); 3743 spill_offset += RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size; 3744 } 3745 } 3746 3747 void MacroAssembler::pop_set(RegSet set, int offset) { 3748 3749 int gp_reg_size = RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size; 3750 int restore_size = set.size() * gp_reg_size; 3751 int aligned_size = align_up(restore_size, StackAlignmentInBytes); 3752 3753 int restore_offset; 3754 if (offset == -1) { 3755 restore_offset = restore_size - gp_reg_size; 3756 } else { 3757 restore_offset = offset + restore_size - gp_reg_size; 3758 } 3759 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) { 3760 movptr(*it, Address(rsp, restore_offset)); 3761 restore_offset -= gp_reg_size; 3762 } 3763 3764 if (offset == -1) { 3765 addptr(rsp, aligned_size); 3766 } 3767 } 3768 3769 // Defines obj, preserves var_size_in_bytes 3770 void MacroAssembler::eden_allocate(Register thread, Register obj, 3771 Register var_size_in_bytes, 3772 int con_size_in_bytes, 3773 Register t1, 3774 Label& slow_case) { 3775 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 3776 bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case); 3777 } 3778 3779 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 3780 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 3781 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 3782 assert((offset_in_bytes & (BytesPerInt - 1)) == 0, "offset must be a multiple of BytesPerInt"); 3783 Label done; 3784 3785 testptr(length_in_bytes, length_in_bytes); 3786 jcc(Assembler::zero, done); 3787 3788 // Emit single 32bit store to clear leading bytes, if necessary. 3789 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 3790 #ifdef _LP64 3791 if (!is_aligned(offset_in_bytes, BytesPerWord)) { 3792 movl(Address(address, offset_in_bytes), temp); 3793 offset_in_bytes += BytesPerInt; 3794 decrement(length_in_bytes, BytesPerInt); 3795 } 3796 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 3797 testptr(length_in_bytes, length_in_bytes); 3798 jcc(Assembler::zero, done); 3799 #endif 3800 3801 // initialize topmost word, divide index by 2, check if odd and test if zero 3802 // note: for the remaining code to work, index must be a multiple of BytesPerWord 3803 #ifdef ASSERT 3804 { 3805 Label L; 3806 testptr(length_in_bytes, BytesPerWord - 1); 3807 jcc(Assembler::zero, L); 3808 stop("length must be a multiple of BytesPerWord"); 3809 bind(L); 3810 } 3811 #endif 3812 Register index = length_in_bytes; 3813 if (UseIncDec) { 3814 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 3815 } else { 3816 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 3817 shrptr(index, 1); 3818 } 3819 #ifndef _LP64 3820 // index could have not been a multiple of 8 (i.e., bit 2 was set) 3821 { 3822 Label even; 3823 // note: if index was a multiple of 8, then it cannot 3824 // be 0 now otherwise it must have been 0 before 3825 // => if it is even, we don't need to check for 0 again 3826 jcc(Assembler::carryClear, even); 3827 // clear topmost word (no jump would be needed if conditional assignment worked here) 3828 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 3829 // index could be 0 now, must check again 3830 jcc(Assembler::zero, done); 3831 bind(even); 3832 } 3833 #endif // !_LP64 3834 // initialize remaining object fields: index is a multiple of 2 now 3835 { 3836 Label loop; 3837 bind(loop); 3838 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 3839 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 3840 decrement(index); 3841 jcc(Assembler::notZero, loop); 3842 } 3843 3844 bind(done); 3845 } 3846 3847 // Look up the method for a megamorphic invokeinterface call. 3848 // The target method is determined by <intf_klass, itable_index>. 3849 // The receiver klass is in recv_klass. 3850 // On success, the result will be in method_result, and execution falls through. 3851 // On failure, execution transfers to the given label. 3852 void MacroAssembler::lookup_interface_method(Register recv_klass, 3853 Register intf_klass, 3854 RegisterOrConstant itable_index, 3855 Register method_result, 3856 Register scan_temp, 3857 Label& L_no_such_interface, 3858 bool return_method) { 3859 assert_different_registers(recv_klass, intf_klass, scan_temp); 3860 assert_different_registers(method_result, intf_klass, scan_temp); 3861 assert(recv_klass != method_result || !return_method, 3862 "recv_klass can be destroyed when method isn't needed"); 3863 3864 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 3865 "caller must use same register for non-constant itable index as for method"); 3866 3867 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 3868 int vtable_base = in_bytes(Klass::vtable_start_offset()); 3869 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 3870 int scan_step = itableOffsetEntry::size() * wordSize; 3871 int vte_size = vtableEntry::size_in_bytes(); 3872 Address::ScaleFactor times_vte_scale = Address::times_ptr; 3873 assert(vte_size == wordSize, "else adjust times_vte_scale"); 3874 3875 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 3876 3877 // %%% Could store the aligned, prescaled offset in the klassoop. 3878 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 3879 3880 if (return_method) { 3881 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 3882 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 3883 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 3884 } 3885 3886 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 3887 // if (scan->interface() == intf) { 3888 // result = (klass + scan->offset() + itable_index); 3889 // } 3890 // } 3891 Label search, found_method; 3892 3893 for (int peel = 1; peel >= 0; peel--) { 3894 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 3895 cmpptr(intf_klass, method_result); 3896 3897 if (peel) { 3898 jccb(Assembler::equal, found_method); 3899 } else { 3900 jccb(Assembler::notEqual, search); 3901 // (invert the test to fall through to found_method...) 3902 } 3903 3904 if (!peel) break; 3905 3906 bind(search); 3907 3908 // Check that the previous entry is non-null. A null entry means that 3909 // the receiver class doesn't implement the interface, and wasn't the 3910 // same as when the caller was compiled. 3911 testptr(method_result, method_result); 3912 jcc(Assembler::zero, L_no_such_interface); 3913 addptr(scan_temp, scan_step); 3914 } 3915 3916 bind(found_method); 3917 3918 if (return_method) { 3919 // Got a hit. 3920 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 3921 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 3922 } 3923 } 3924 3925 3926 // virtual method calling 3927 void MacroAssembler::lookup_virtual_method(Register recv_klass, 3928 RegisterOrConstant vtable_index, 3929 Register method_result) { 3930 const int base = in_bytes(Klass::vtable_start_offset()); 3931 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 3932 Address vtable_entry_addr(recv_klass, 3933 vtable_index, Address::times_ptr, 3934 base + vtableEntry::method_offset_in_bytes()); 3935 movptr(method_result, vtable_entry_addr); 3936 } 3937 3938 3939 void MacroAssembler::check_klass_subtype(Register sub_klass, 3940 Register super_klass, 3941 Register temp_reg, 3942 Label& L_success) { 3943 Label L_failure; 3944 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 3945 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 3946 bind(L_failure); 3947 } 3948 3949 3950 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 3951 Register super_klass, 3952 Register temp_reg, 3953 Label* L_success, 3954 Label* L_failure, 3955 Label* L_slow_path, 3956 RegisterOrConstant super_check_offset) { 3957 assert_different_registers(sub_klass, super_klass, temp_reg); 3958 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 3959 if (super_check_offset.is_register()) { 3960 assert_different_registers(sub_klass, super_klass, 3961 super_check_offset.as_register()); 3962 } else if (must_load_sco) { 3963 assert(temp_reg != noreg, "supply either a temp or a register offset"); 3964 } 3965 3966 Label L_fallthrough; 3967 int label_nulls = 0; 3968 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 3969 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 3970 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 3971 assert(label_nulls <= 1, "at most one NULL in the batch"); 3972 3973 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 3974 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 3975 Address super_check_offset_addr(super_klass, sco_offset); 3976 3977 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 3978 // range of a jccb. If this routine grows larger, reconsider at 3979 // least some of these. 3980 #define local_jcc(assembler_cond, label) \ 3981 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 3982 else jcc( assembler_cond, label) /*omit semi*/ 3983 3984 // Hacked jmp, which may only be used just before L_fallthrough. 3985 #define final_jmp(label) \ 3986 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 3987 else jmp(label) /*omit semi*/ 3988 3989 // If the pointers are equal, we are done (e.g., String[] elements). 3990 // This self-check enables sharing of secondary supertype arrays among 3991 // non-primary types such as array-of-interface. Otherwise, each such 3992 // type would need its own customized SSA. 3993 // We move this check to the front of the fast path because many 3994 // type checks are in fact trivially successful in this manner, 3995 // so we get a nicely predicted branch right at the start of the check. 3996 cmpptr(sub_klass, super_klass); 3997 local_jcc(Assembler::equal, *L_success); 3998 3999 // Check the supertype display: 4000 if (must_load_sco) { 4001 // Positive movl does right thing on LP64. 4002 movl(temp_reg, super_check_offset_addr); 4003 super_check_offset = RegisterOrConstant(temp_reg); 4004 } 4005 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 4006 cmpptr(super_klass, super_check_addr); // load displayed supertype 4007 4008 // This check has worked decisively for primary supers. 4009 // Secondary supers are sought in the super_cache ('super_cache_addr'). 4010 // (Secondary supers are interfaces and very deeply nested subtypes.) 4011 // This works in the same check above because of a tricky aliasing 4012 // between the super_cache and the primary super display elements. 4013 // (The 'super_check_addr' can address either, as the case requires.) 4014 // Note that the cache is updated below if it does not help us find 4015 // what we need immediately. 4016 // So if it was a primary super, we can just fail immediately. 4017 // Otherwise, it's the slow path for us (no success at this point). 4018 4019 if (super_check_offset.is_register()) { 4020 local_jcc(Assembler::equal, *L_success); 4021 cmpl(super_check_offset.as_register(), sc_offset); 4022 if (L_failure == &L_fallthrough) { 4023 local_jcc(Assembler::equal, *L_slow_path); 4024 } else { 4025 local_jcc(Assembler::notEqual, *L_failure); 4026 final_jmp(*L_slow_path); 4027 } 4028 } else if (super_check_offset.as_constant() == sc_offset) { 4029 // Need a slow path; fast failure is impossible. 4030 if (L_slow_path == &L_fallthrough) { 4031 local_jcc(Assembler::equal, *L_success); 4032 } else { 4033 local_jcc(Assembler::notEqual, *L_slow_path); 4034 final_jmp(*L_success); 4035 } 4036 } else { 4037 // No slow path; it's a fast decision. 4038 if (L_failure == &L_fallthrough) { 4039 local_jcc(Assembler::equal, *L_success); 4040 } else { 4041 local_jcc(Assembler::notEqual, *L_failure); 4042 final_jmp(*L_success); 4043 } 4044 } 4045 4046 bind(L_fallthrough); 4047 4048 #undef local_jcc 4049 #undef final_jmp 4050 } 4051 4052 4053 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 4054 Register super_klass, 4055 Register temp_reg, 4056 Register temp2_reg, 4057 Label* L_success, 4058 Label* L_failure, 4059 bool set_cond_codes) { 4060 assert_different_registers(sub_klass, super_klass, temp_reg); 4061 if (temp2_reg != noreg) 4062 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 4063 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 4064 4065 Label L_fallthrough; 4066 int label_nulls = 0; 4067 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 4068 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 4069 assert(label_nulls <= 1, "at most one NULL in the batch"); 4070 4071 // a couple of useful fields in sub_klass: 4072 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 4073 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 4074 Address secondary_supers_addr(sub_klass, ss_offset); 4075 Address super_cache_addr( sub_klass, sc_offset); 4076 4077 // Do a linear scan of the secondary super-klass chain. 4078 // This code is rarely used, so simplicity is a virtue here. 4079 // The repne_scan instruction uses fixed registers, which we must spill. 4080 // Don't worry too much about pre-existing connections with the input regs. 4081 4082 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 4083 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 4084 4085 // Get super_klass value into rax (even if it was in rdi or rcx). 4086 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 4087 if (super_klass != rax || UseCompressedOops) { 4088 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 4089 mov(rax, super_klass); 4090 } 4091 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 4092 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 4093 4094 #ifndef PRODUCT 4095 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 4096 ExternalAddress pst_counter_addr((address) pst_counter); 4097 NOT_LP64( incrementl(pst_counter_addr) ); 4098 LP64_ONLY( lea(rcx, pst_counter_addr) ); 4099 LP64_ONLY( incrementl(Address(rcx, 0)) ); 4100 #endif //PRODUCT 4101 4102 // We will consult the secondary-super array. 4103 movptr(rdi, secondary_supers_addr); 4104 // Load the array length. (Positive movl does right thing on LP64.) 4105 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 4106 // Skip to start of data. 4107 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 4108 4109 // Scan RCX words at [RDI] for an occurrence of RAX. 4110 // Set NZ/Z based on last compare. 4111 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 4112 // not change flags (only scas instruction which is repeated sets flags). 4113 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 4114 4115 testptr(rax,rax); // Set Z = 0 4116 repne_scan(); 4117 4118 // Unspill the temp. registers: 4119 if (pushed_rdi) pop(rdi); 4120 if (pushed_rcx) pop(rcx); 4121 if (pushed_rax) pop(rax); 4122 4123 if (set_cond_codes) { 4124 // Special hack for the AD files: rdi is guaranteed non-zero. 4125 assert(!pushed_rdi, "rdi must be left non-NULL"); 4126 // Also, the condition codes are properly set Z/NZ on succeed/failure. 4127 } 4128 4129 if (L_failure == &L_fallthrough) 4130 jccb(Assembler::notEqual, *L_failure); 4131 else jcc(Assembler::notEqual, *L_failure); 4132 4133 // Success. Cache the super we found and proceed in triumph. 4134 movptr(super_cache_addr, super_klass); 4135 4136 if (L_success != &L_fallthrough) { 4137 jmp(*L_success); 4138 } 4139 4140 #undef IS_A_TEMP 4141 4142 bind(L_fallthrough); 4143 } 4144 4145 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) { 4146 assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required"); 4147 4148 Label L_fallthrough; 4149 if (L_fast_path == NULL) { 4150 L_fast_path = &L_fallthrough; 4151 } else if (L_slow_path == NULL) { 4152 L_slow_path = &L_fallthrough; 4153 } 4154 4155 // Fast path check: class is fully initialized 4156 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized); 4157 jcc(Assembler::equal, *L_fast_path); 4158 4159 // Fast path check: current thread is initializer thread 4160 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset())); 4161 if (L_slow_path == &L_fallthrough) { 4162 jcc(Assembler::equal, *L_fast_path); 4163 bind(*L_slow_path); 4164 } else if (L_fast_path == &L_fallthrough) { 4165 jcc(Assembler::notEqual, *L_slow_path); 4166 bind(*L_fast_path); 4167 } else { 4168 Unimplemented(); 4169 } 4170 } 4171 4172 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 4173 if (VM_Version::supports_cmov()) { 4174 cmovl(cc, dst, src); 4175 } else { 4176 Label L; 4177 jccb(negate_condition(cc), L); 4178 movl(dst, src); 4179 bind(L); 4180 } 4181 } 4182 4183 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 4184 if (VM_Version::supports_cmov()) { 4185 cmovl(cc, dst, src); 4186 } else { 4187 Label L; 4188 jccb(negate_condition(cc), L); 4189 movl(dst, src); 4190 bind(L); 4191 } 4192 } 4193 4194 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) { 4195 if (!VerifyOops) return; 4196 4197 // Pass register number to verify_oop_subroutine 4198 const char* b = NULL; 4199 { 4200 ResourceMark rm; 4201 stringStream ss; 4202 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line); 4203 b = code_string(ss.as_string()); 4204 } 4205 BLOCK_COMMENT("verify_oop {"); 4206 #ifdef _LP64 4207 push(rscratch1); // save r10, trashed by movptr() 4208 #endif 4209 push(rax); // save rax, 4210 push(reg); // pass register argument 4211 ExternalAddress buffer((address) b); 4212 // avoid using pushptr, as it modifies scratch registers 4213 // and our contract is not to modify anything 4214 movptr(rax, buffer.addr()); 4215 push(rax); 4216 // call indirectly to solve generation ordering problem 4217 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 4218 call(rax); 4219 // Caller pops the arguments (oop, message) and restores rax, r10 4220 BLOCK_COMMENT("} verify_oop"); 4221 } 4222 4223 void MacroAssembler::vallones(XMMRegister dst, int vector_len) { 4224 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) { 4225 vpternlogd(dst, 0xFF, dst, dst, vector_len); 4226 } else { 4227 assert(UseAVX > 0, ""); 4228 vpcmpeqb(dst, dst, dst, vector_len); 4229 } 4230 } 4231 4232 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 4233 int extra_slot_offset) { 4234 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 4235 int stackElementSize = Interpreter::stackElementSize; 4236 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 4237 #ifdef ASSERT 4238 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 4239 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 4240 #endif 4241 Register scale_reg = noreg; 4242 Address::ScaleFactor scale_factor = Address::no_scale; 4243 if (arg_slot.is_constant()) { 4244 offset += arg_slot.as_constant() * stackElementSize; 4245 } else { 4246 scale_reg = arg_slot.as_register(); 4247 scale_factor = Address::times(stackElementSize); 4248 } 4249 offset += wordSize; // return PC is on stack 4250 return Address(rsp, scale_reg, scale_factor, offset); 4251 } 4252 4253 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) { 4254 if (!VerifyOops) return; 4255 4256 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 4257 // Pass register number to verify_oop_subroutine 4258 const char* b = NULL; 4259 { 4260 ResourceMark rm; 4261 stringStream ss; 4262 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line); 4263 b = code_string(ss.as_string()); 4264 } 4265 #ifdef _LP64 4266 push(rscratch1); // save r10, trashed by movptr() 4267 #endif 4268 push(rax); // save rax, 4269 // addr may contain rsp so we will have to adjust it based on the push 4270 // we just did (and on 64 bit we do two pushes) 4271 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 4272 // stores rax into addr which is backwards of what was intended. 4273 if (addr.uses(rsp)) { 4274 lea(rax, addr); 4275 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 4276 } else { 4277 pushptr(addr); 4278 } 4279 4280 ExternalAddress buffer((address) b); 4281 // pass msg argument 4282 // avoid using pushptr, as it modifies scratch registers 4283 // and our contract is not to modify anything 4284 movptr(rax, buffer.addr()); 4285 push(rax); 4286 4287 // call indirectly to solve generation ordering problem 4288 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 4289 call(rax); 4290 // Caller pops the arguments (addr, message) and restores rax, r10. 4291 } 4292 4293 void MacroAssembler::verify_tlab() { 4294 #ifdef ASSERT 4295 if (UseTLAB && VerifyOops) { 4296 Label next, ok; 4297 Register t1 = rsi; 4298 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 4299 4300 push(t1); 4301 NOT_LP64(push(thread_reg)); 4302 NOT_LP64(get_thread(thread_reg)); 4303 4304 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4305 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 4306 jcc(Assembler::aboveEqual, next); 4307 STOP("assert(top >= start)"); 4308 should_not_reach_here(); 4309 4310 bind(next); 4311 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 4312 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 4313 jcc(Assembler::aboveEqual, ok); 4314 STOP("assert(top <= end)"); 4315 should_not_reach_here(); 4316 4317 bind(ok); 4318 NOT_LP64(pop(thread_reg)); 4319 pop(t1); 4320 } 4321 #endif 4322 } 4323 4324 class ControlWord { 4325 public: 4326 int32_t _value; 4327 4328 int rounding_control() const { return (_value >> 10) & 3 ; } 4329 int precision_control() const { return (_value >> 8) & 3 ; } 4330 bool precision() const { return ((_value >> 5) & 1) != 0; } 4331 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4332 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4333 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4334 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4335 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4336 4337 void print() const { 4338 // rounding control 4339 const char* rc; 4340 switch (rounding_control()) { 4341 case 0: rc = "round near"; break; 4342 case 1: rc = "round down"; break; 4343 case 2: rc = "round up "; break; 4344 case 3: rc = "chop "; break; 4345 default: 4346 rc = NULL; // silence compiler warnings 4347 fatal("Unknown rounding control: %d", rounding_control()); 4348 }; 4349 // precision control 4350 const char* pc; 4351 switch (precision_control()) { 4352 case 0: pc = "24 bits "; break; 4353 case 1: pc = "reserved"; break; 4354 case 2: pc = "53 bits "; break; 4355 case 3: pc = "64 bits "; break; 4356 default: 4357 pc = NULL; // silence compiler warnings 4358 fatal("Unknown precision control: %d", precision_control()); 4359 }; 4360 // flags 4361 char f[9]; 4362 f[0] = ' '; 4363 f[1] = ' '; 4364 f[2] = (precision ()) ? 'P' : 'p'; 4365 f[3] = (underflow ()) ? 'U' : 'u'; 4366 f[4] = (overflow ()) ? 'O' : 'o'; 4367 f[5] = (zero_divide ()) ? 'Z' : 'z'; 4368 f[6] = (denormalized()) ? 'D' : 'd'; 4369 f[7] = (invalid ()) ? 'I' : 'i'; 4370 f[8] = '\x0'; 4371 // output 4372 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 4373 } 4374 4375 }; 4376 4377 class StatusWord { 4378 public: 4379 int32_t _value; 4380 4381 bool busy() const { return ((_value >> 15) & 1) != 0; } 4382 bool C3() const { return ((_value >> 14) & 1) != 0; } 4383 bool C2() const { return ((_value >> 10) & 1) != 0; } 4384 bool C1() const { return ((_value >> 9) & 1) != 0; } 4385 bool C0() const { return ((_value >> 8) & 1) != 0; } 4386 int top() const { return (_value >> 11) & 7 ; } 4387 bool error_status() const { return ((_value >> 7) & 1) != 0; } 4388 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 4389 bool precision() const { return ((_value >> 5) & 1) != 0; } 4390 bool underflow() const { return ((_value >> 4) & 1) != 0; } 4391 bool overflow() const { return ((_value >> 3) & 1) != 0; } 4392 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 4393 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 4394 bool invalid() const { return ((_value >> 0) & 1) != 0; } 4395 4396 void print() const { 4397 // condition codes 4398 char c[5]; 4399 c[0] = (C3()) ? '3' : '-'; 4400 c[1] = (C2()) ? '2' : '-'; 4401 c[2] = (C1()) ? '1' : '-'; 4402 c[3] = (C0()) ? '0' : '-'; 4403 c[4] = '\x0'; 4404 // flags 4405 char f[9]; 4406 f[0] = (error_status()) ? 'E' : '-'; 4407 f[1] = (stack_fault ()) ? 'S' : '-'; 4408 f[2] = (precision ()) ? 'P' : '-'; 4409 f[3] = (underflow ()) ? 'U' : '-'; 4410 f[4] = (overflow ()) ? 'O' : '-'; 4411 f[5] = (zero_divide ()) ? 'Z' : '-'; 4412 f[6] = (denormalized()) ? 'D' : '-'; 4413 f[7] = (invalid ()) ? 'I' : '-'; 4414 f[8] = '\x0'; 4415 // output 4416 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 4417 } 4418 4419 }; 4420 4421 class TagWord { 4422 public: 4423 int32_t _value; 4424 4425 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 4426 4427 void print() const { 4428 printf("%04x", _value & 0xFFFF); 4429 } 4430 4431 }; 4432 4433 class FPU_Register { 4434 public: 4435 int32_t _m0; 4436 int32_t _m1; 4437 int16_t _ex; 4438 4439 bool is_indefinite() const { 4440 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 4441 } 4442 4443 void print() const { 4444 char sign = (_ex < 0) ? '-' : '+'; 4445 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 4446 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 4447 }; 4448 4449 }; 4450 4451 class FPU_State { 4452 public: 4453 enum { 4454 register_size = 10, 4455 number_of_registers = 8, 4456 register_mask = 7 4457 }; 4458 4459 ControlWord _control_word; 4460 StatusWord _status_word; 4461 TagWord _tag_word; 4462 int32_t _error_offset; 4463 int32_t _error_selector; 4464 int32_t _data_offset; 4465 int32_t _data_selector; 4466 int8_t _register[register_size * number_of_registers]; 4467 4468 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 4469 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 4470 4471 const char* tag_as_string(int tag) const { 4472 switch (tag) { 4473 case 0: return "valid"; 4474 case 1: return "zero"; 4475 case 2: return "special"; 4476 case 3: return "empty"; 4477 } 4478 ShouldNotReachHere(); 4479 return NULL; 4480 } 4481 4482 void print() const { 4483 // print computation registers 4484 { int t = _status_word.top(); 4485 for (int i = 0; i < number_of_registers; i++) { 4486 int j = (i - t) & register_mask; 4487 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 4488 st(j)->print(); 4489 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 4490 } 4491 } 4492 printf("\n"); 4493 // print control registers 4494 printf("ctrl = "); _control_word.print(); printf("\n"); 4495 printf("stat = "); _status_word .print(); printf("\n"); 4496 printf("tags = "); _tag_word .print(); printf("\n"); 4497 } 4498 4499 }; 4500 4501 class Flag_Register { 4502 public: 4503 int32_t _value; 4504 4505 bool overflow() const { return ((_value >> 11) & 1) != 0; } 4506 bool direction() const { return ((_value >> 10) & 1) != 0; } 4507 bool sign() const { return ((_value >> 7) & 1) != 0; } 4508 bool zero() const { return ((_value >> 6) & 1) != 0; } 4509 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 4510 bool parity() const { return ((_value >> 2) & 1) != 0; } 4511 bool carry() const { return ((_value >> 0) & 1) != 0; } 4512 4513 void print() const { 4514 // flags 4515 char f[8]; 4516 f[0] = (overflow ()) ? 'O' : '-'; 4517 f[1] = (direction ()) ? 'D' : '-'; 4518 f[2] = (sign ()) ? 'S' : '-'; 4519 f[3] = (zero ()) ? 'Z' : '-'; 4520 f[4] = (auxiliary_carry()) ? 'A' : '-'; 4521 f[5] = (parity ()) ? 'P' : '-'; 4522 f[6] = (carry ()) ? 'C' : '-'; 4523 f[7] = '\x0'; 4524 // output 4525 printf("%08x flags = %s", _value, f); 4526 } 4527 4528 }; 4529 4530 class IU_Register { 4531 public: 4532 int32_t _value; 4533 4534 void print() const { 4535 printf("%08x %11d", _value, _value); 4536 } 4537 4538 }; 4539 4540 class IU_State { 4541 public: 4542 Flag_Register _eflags; 4543 IU_Register _rdi; 4544 IU_Register _rsi; 4545 IU_Register _rbp; 4546 IU_Register _rsp; 4547 IU_Register _rbx; 4548 IU_Register _rdx; 4549 IU_Register _rcx; 4550 IU_Register _rax; 4551 4552 void print() const { 4553 // computation registers 4554 printf("rax, = "); _rax.print(); printf("\n"); 4555 printf("rbx, = "); _rbx.print(); printf("\n"); 4556 printf("rcx = "); _rcx.print(); printf("\n"); 4557 printf("rdx = "); _rdx.print(); printf("\n"); 4558 printf("rdi = "); _rdi.print(); printf("\n"); 4559 printf("rsi = "); _rsi.print(); printf("\n"); 4560 printf("rbp, = "); _rbp.print(); printf("\n"); 4561 printf("rsp = "); _rsp.print(); printf("\n"); 4562 printf("\n"); 4563 // control registers 4564 printf("flgs = "); _eflags.print(); printf("\n"); 4565 } 4566 }; 4567 4568 4569 class CPU_State { 4570 public: 4571 FPU_State _fpu_state; 4572 IU_State _iu_state; 4573 4574 void print() const { 4575 printf("--------------------------------------------------\n"); 4576 _iu_state .print(); 4577 printf("\n"); 4578 _fpu_state.print(); 4579 printf("--------------------------------------------------\n"); 4580 } 4581 4582 }; 4583 4584 4585 static void _print_CPU_state(CPU_State* state) { 4586 state->print(); 4587 }; 4588 4589 4590 void MacroAssembler::print_CPU_state() { 4591 push_CPU_state(); 4592 push(rsp); // pass CPU state 4593 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 4594 addptr(rsp, wordSize); // discard argument 4595 pop_CPU_state(); 4596 } 4597 4598 4599 #ifndef _LP64 4600 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 4601 static int counter = 0; 4602 FPU_State* fs = &state->_fpu_state; 4603 counter++; 4604 // For leaf calls, only verify that the top few elements remain empty. 4605 // We only need 1 empty at the top for C2 code. 4606 if( stack_depth < 0 ) { 4607 if( fs->tag_for_st(7) != 3 ) { 4608 printf("FPR7 not empty\n"); 4609 state->print(); 4610 assert(false, "error"); 4611 return false; 4612 } 4613 return true; // All other stack states do not matter 4614 } 4615 4616 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(), 4617 "bad FPU control word"); 4618 4619 // compute stack depth 4620 int i = 0; 4621 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 4622 int d = i; 4623 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 4624 // verify findings 4625 if (i != FPU_State::number_of_registers) { 4626 // stack not contiguous 4627 printf("%s: stack not contiguous at ST%d\n", s, i); 4628 state->print(); 4629 assert(false, "error"); 4630 return false; 4631 } 4632 // check if computed stack depth corresponds to expected stack depth 4633 if (stack_depth < 0) { 4634 // expected stack depth is -stack_depth or less 4635 if (d > -stack_depth) { 4636 // too many elements on the stack 4637 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 4638 state->print(); 4639 assert(false, "error"); 4640 return false; 4641 } 4642 } else { 4643 // expected stack depth is stack_depth 4644 if (d != stack_depth) { 4645 // wrong stack depth 4646 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 4647 state->print(); 4648 assert(false, "error"); 4649 return false; 4650 } 4651 } 4652 // everything is cool 4653 return true; 4654 } 4655 4656 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 4657 if (!VerifyFPU) return; 4658 push_CPU_state(); 4659 push(rsp); // pass CPU state 4660 ExternalAddress msg((address) s); 4661 // pass message string s 4662 pushptr(msg.addr()); 4663 push(stack_depth); // pass stack depth 4664 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 4665 addptr(rsp, 3 * wordSize); // discard arguments 4666 // check for error 4667 { Label L; 4668 testl(rax, rax); 4669 jcc(Assembler::notZero, L); 4670 int3(); // break if error condition 4671 bind(L); 4672 } 4673 pop_CPU_state(); 4674 } 4675 #endif // _LP64 4676 4677 void MacroAssembler::restore_cpu_control_state_after_jni() { 4678 // Either restore the MXCSR register after returning from the JNI Call 4679 // or verify that it wasn't changed (with -Xcheck:jni flag). 4680 if (VM_Version::supports_sse()) { 4681 if (RestoreMXCSROnJNICalls) { 4682 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std())); 4683 } else if (CheckJNICalls) { 4684 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 4685 } 4686 } 4687 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 4688 vzeroupper(); 4689 4690 #ifndef _LP64 4691 // Either restore the x87 floating pointer control word after returning 4692 // from the JNI call or verify that it wasn't changed. 4693 if (CheckJNICalls) { 4694 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 4695 } 4696 #endif // _LP64 4697 } 4698 4699 // ((OopHandle)result).resolve(); 4700 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) { 4701 assert_different_registers(result, tmp); 4702 4703 // Only 64 bit platforms support GCs that require a tmp register 4704 // Only IN_HEAP loads require a thread_tmp register 4705 // OopHandle::resolve is an indirection like jobject. 4706 access_load_at(T_OBJECT, IN_NATIVE, 4707 result, Address(result, 0), tmp, /*tmp_thread*/noreg); 4708 } 4709 4710 // ((WeakHandle)result).resolve(); 4711 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) { 4712 assert_different_registers(rresult, rtmp); 4713 Label resolved; 4714 4715 // A null weak handle resolves to null. 4716 cmpptr(rresult, 0); 4717 jcc(Assembler::equal, resolved); 4718 4719 // Only 64 bit platforms support GCs that require a tmp register 4720 // Only IN_HEAP loads require a thread_tmp register 4721 // WeakHandle::resolve is an indirection like jweak. 4722 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF, 4723 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg); 4724 bind(resolved); 4725 } 4726 4727 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) { 4728 // get mirror 4729 const int mirror_offset = in_bytes(Klass::java_mirror_offset()); 4730 load_method_holder(mirror, method); 4731 movptr(mirror, Address(mirror, mirror_offset)); 4732 resolve_oop_handle(mirror, tmp); 4733 } 4734 4735 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) { 4736 load_method_holder(rresult, rmethod); 4737 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset())); 4738 } 4739 4740 void MacroAssembler::load_method_holder(Register holder, Register method) { 4741 movptr(holder, Address(method, Method::const_offset())); // ConstMethod* 4742 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool* 4743 movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass* 4744 } 4745 4746 #ifdef _LP64 4747 void MacroAssembler::load_nklass(Register dst, Register src) { 4748 assert_different_registers(src, dst); 4749 assert(UseCompressedClassPointers, "expect compressed class pointers"); 4750 4751 Label slow, done; 4752 movq(dst, Address(src, oopDesc::mark_offset_in_bytes())); 4753 // NOTE: While it would seem nice to use xorb instead (for which we don't have an encoding in our assembler), 4754 // the encoding for xorq uses the signed version (0x81/6) of xor, which encodes as compact as xorb would, 4755 // and does't make a difference performance-wise. 4756 xorq(dst, markWord::unlocked_value); 4757 testb(dst, markWord::lock_mask_in_place); 4758 jccb(Assembler::notZero, slow); 4759 4760 shrq(dst, markWord::klass_shift); 4761 jmp(done); 4762 bind(slow); 4763 4764 if (dst != rax) { 4765 push(rax); 4766 } 4767 if (src != rax) { 4768 mov(rax, src); 4769 } 4770 call(RuntimeAddress(StubRoutines::load_nklass())); 4771 if (dst != rax) { 4772 mov(dst, rax); 4773 pop(rax); 4774 } 4775 4776 bind(done); 4777 } 4778 #endif 4779 4780 void MacroAssembler::load_klass(Register dst, Register src, Register tmp, bool null_check_src) { 4781 assert_different_registers(src, tmp); 4782 assert_different_registers(dst, tmp); 4783 #ifdef _LP64 4784 assert(UseCompressedClassPointers, "expect compressed class pointers"); 4785 Register d = dst; 4786 if (src == dst) { 4787 d = tmp; 4788 } 4789 if (null_check_src) { 4790 null_check(src, oopDesc::mark_offset_in_bytes()); 4791 } 4792 load_nklass(d, src); 4793 if (src == dst) { 4794 mov(dst, d); 4795 } 4796 decode_klass_not_null(dst, tmp); 4797 #else 4798 if (null_check_src) { 4799 null_check(src, oopDesc::klass_offset_in_bytes()); 4800 } 4801 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 4802 #endif 4803 } 4804 4805 #ifndef _LP64 4806 void MacroAssembler::store_klass(Register dst, Register src) { 4807 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 4808 } 4809 #endif 4810 4811 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src, 4812 Register tmp1, Register thread_tmp) { 4813 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4814 decorators = AccessInternal::decorator_fixup(decorators); 4815 bool as_raw = (decorators & AS_RAW) != 0; 4816 if (as_raw) { 4817 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4818 } else { 4819 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp); 4820 } 4821 } 4822 4823 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src, 4824 Register tmp1, Register tmp2, Register tmp3) { 4825 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 4826 decorators = AccessInternal::decorator_fixup(decorators); 4827 bool as_raw = (decorators & AS_RAW) != 0; 4828 if (as_raw) { 4829 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3); 4830 } else { 4831 bs->store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3); 4832 } 4833 } 4834 4835 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1, 4836 Register thread_tmp, DecoratorSet decorators) { 4837 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp); 4838 } 4839 4840 // Doesn't do verification, generates fixed size code 4841 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1, 4842 Register thread_tmp, DecoratorSet decorators) { 4843 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp); 4844 } 4845 4846 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1, 4847 Register tmp2, Register tmp3, DecoratorSet decorators) { 4848 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2, tmp3); 4849 } 4850 4851 // Used for storing NULLs. 4852 void MacroAssembler::store_heap_oop_null(Address dst) { 4853 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg); 4854 } 4855 4856 #ifdef _LP64 4857 #ifdef ASSERT 4858 void MacroAssembler::verify_heapbase(const char* msg) { 4859 assert (UseCompressedOops, "should be compressed"); 4860 assert (Universe::heap() != NULL, "java heap should be initialized"); 4861 if (CheckCompressedOops) { 4862 Label ok; 4863 const auto src2 = ExternalAddress((address)CompressedOops::ptrs_base_addr()); 4864 assert(!src2.is_lval(), "should not be lval"); 4865 const bool is_src2_reachable = reachable(src2); 4866 if (!is_src2_reachable) { 4867 push(rscratch1); // cmpptr trashes rscratch1 4868 } 4869 cmpptr(r12_heapbase, src2); 4870 jcc(Assembler::equal, ok); 4871 STOP(msg); 4872 bind(ok); 4873 if (!is_src2_reachable) { 4874 pop(rscratch1); 4875 } 4876 } 4877 } 4878 #endif 4879 4880 // Algorithm must match oop.inline.hpp encode_heap_oop. 4881 void MacroAssembler::encode_heap_oop(Register r) { 4882 #ifdef ASSERT 4883 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 4884 #endif 4885 verify_oop_msg(r, "broken oop in encode_heap_oop"); 4886 if (CompressedOops::base() == NULL) { 4887 if (CompressedOops::shift() != 0) { 4888 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4889 shrq(r, LogMinObjAlignmentInBytes); 4890 } 4891 return; 4892 } 4893 testq(r, r); 4894 cmovq(Assembler::equal, r, r12_heapbase); 4895 subq(r, r12_heapbase); 4896 shrq(r, LogMinObjAlignmentInBytes); 4897 } 4898 4899 void MacroAssembler::encode_heap_oop_not_null(Register r) { 4900 #ifdef ASSERT 4901 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 4902 if (CheckCompressedOops) { 4903 Label ok; 4904 testq(r, r); 4905 jcc(Assembler::notEqual, ok); 4906 STOP("null oop passed to encode_heap_oop_not_null"); 4907 bind(ok); 4908 } 4909 #endif 4910 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null"); 4911 if (CompressedOops::base() != NULL) { 4912 subq(r, r12_heapbase); 4913 } 4914 if (CompressedOops::shift() != 0) { 4915 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4916 shrq(r, LogMinObjAlignmentInBytes); 4917 } 4918 } 4919 4920 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 4921 #ifdef ASSERT 4922 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 4923 if (CheckCompressedOops) { 4924 Label ok; 4925 testq(src, src); 4926 jcc(Assembler::notEqual, ok); 4927 STOP("null oop passed to encode_heap_oop_not_null2"); 4928 bind(ok); 4929 } 4930 #endif 4931 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2"); 4932 if (dst != src) { 4933 movq(dst, src); 4934 } 4935 if (CompressedOops::base() != NULL) { 4936 subq(dst, r12_heapbase); 4937 } 4938 if (CompressedOops::shift() != 0) { 4939 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4940 shrq(dst, LogMinObjAlignmentInBytes); 4941 } 4942 } 4943 4944 void MacroAssembler::decode_heap_oop(Register r) { 4945 #ifdef ASSERT 4946 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 4947 #endif 4948 if (CompressedOops::base() == NULL) { 4949 if (CompressedOops::shift() != 0) { 4950 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4951 shlq(r, LogMinObjAlignmentInBytes); 4952 } 4953 } else { 4954 Label done; 4955 shlq(r, LogMinObjAlignmentInBytes); 4956 jccb(Assembler::equal, done); 4957 addq(r, r12_heapbase); 4958 bind(done); 4959 } 4960 verify_oop_msg(r, "broken oop in decode_heap_oop"); 4961 } 4962 4963 void MacroAssembler::decode_heap_oop_not_null(Register r) { 4964 // Note: it will change flags 4965 assert (UseCompressedOops, "should only be used for compressed headers"); 4966 assert (Universe::heap() != NULL, "java heap should be initialized"); 4967 // Cannot assert, unverified entry point counts instructions (see .ad file) 4968 // vtableStubs also counts instructions in pd_code_size_limit. 4969 // Also do not verify_oop as this is called by verify_oop. 4970 if (CompressedOops::shift() != 0) { 4971 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4972 shlq(r, LogMinObjAlignmentInBytes); 4973 if (CompressedOops::base() != NULL) { 4974 addq(r, r12_heapbase); 4975 } 4976 } else { 4977 assert (CompressedOops::base() == NULL, "sanity"); 4978 } 4979 } 4980 4981 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 4982 // Note: it will change flags 4983 assert (UseCompressedOops, "should only be used for compressed headers"); 4984 assert (Universe::heap() != NULL, "java heap should be initialized"); 4985 // Cannot assert, unverified entry point counts instructions (see .ad file) 4986 // vtableStubs also counts instructions in pd_code_size_limit. 4987 // Also do not verify_oop as this is called by verify_oop. 4988 if (CompressedOops::shift() != 0) { 4989 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong"); 4990 if (LogMinObjAlignmentInBytes == Address::times_8) { 4991 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 4992 } else { 4993 if (dst != src) { 4994 movq(dst, src); 4995 } 4996 shlq(dst, LogMinObjAlignmentInBytes); 4997 if (CompressedOops::base() != NULL) { 4998 addq(dst, r12_heapbase); 4999 } 5000 } 5001 } else { 5002 assert (CompressedOops::base() == NULL, "sanity"); 5003 if (dst != src) { 5004 movq(dst, src); 5005 } 5006 } 5007 } 5008 5009 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode = KlassDecodeNone; 5010 5011 // Returns a static string 5012 const char* MacroAssembler::describe_klass_decode_mode(MacroAssembler::KlassDecodeMode mode) { 5013 switch (mode) { 5014 case KlassDecodeNone: return "none"; 5015 case KlassDecodeZero: return "zero"; 5016 case KlassDecodeXor: return "xor"; 5017 case KlassDecodeAdd: return "add"; 5018 default: 5019 ShouldNotReachHere(); 5020 } 5021 return NULL; 5022 } 5023 5024 // Return the current narrow Klass pointer decode mode. 5025 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() { 5026 if (_klass_decode_mode == KlassDecodeNone) { 5027 // First time initialization 5028 assert(UseCompressedClassPointers, "not using compressed class pointers"); 5029 assert(Metaspace::initialized(), "metaspace not initialized yet"); 5030 5031 _klass_decode_mode = klass_decode_mode_for_base(CompressedKlassPointers::base()); 5032 guarantee(_klass_decode_mode != KlassDecodeNone, 5033 PTR_FORMAT " is not a valid encoding base on aarch64", 5034 p2i(CompressedKlassPointers::base())); 5035 log_info(metaspace)("klass decode mode initialized: %s", describe_klass_decode_mode(_klass_decode_mode)); 5036 } 5037 return _klass_decode_mode; 5038 } 5039 5040 // Given an arbitrary base address, return the KlassDecodeMode that would be used. Return KlassDecodeNone 5041 // if base address is not valid for encoding. 5042 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode_for_base(address base) { 5043 assert(CompressedKlassPointers::shift() != 0, "not lilliput?"); 5044 5045 const uint64_t base_u64 = (uint64_t) base; 5046 5047 if (base_u64 == 0) { 5048 return KlassDecodeZero; 5049 } 5050 5051 if ((base_u64 & (KlassEncodingMetaspaceMax - 1)) == 0) { 5052 return KlassDecodeXor; 5053 } 5054 5055 // Note that there is no point in optimizing for shift=3 since lilliput 5056 // will use larger shifts 5057 5058 // The add+shift mode for decode_and_move_klass_not_null() requires the base to be 5059 // shiftable-without-loss. So, this is the minimum restriction on x64 for a valid 5060 // encoding base. This does not matter in reality since the shift values we use for 5061 // Lilliput, while large, won't be larger than a page size. And the encoding base 5062 // will be quite likely page aligned since it usually falls to the beginning of 5063 // either CDS or CCS. 5064 if ((base_u64 & (KlassAlignmentInBytes - 1)) == 0) { 5065 return KlassDecodeAdd; 5066 } 5067 5068 return KlassDecodeNone; 5069 } 5070 5071 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) { 5072 assert_different_registers(r, tmp); 5073 switch (klass_decode_mode()) { 5074 case KlassDecodeZero: { 5075 shrq(r, CompressedKlassPointers::shift()); 5076 break; 5077 } 5078 case KlassDecodeXor: { 5079 mov64(tmp, (int64_t)CompressedKlassPointers::base()); 5080 xorq(r, tmp); 5081 shrq(r, CompressedKlassPointers::shift()); 5082 break; 5083 } 5084 case KlassDecodeAdd: { 5085 mov64(tmp, (int64_t)CompressedKlassPointers::base()); 5086 subq(r, tmp); 5087 shrq(r, CompressedKlassPointers::shift()); 5088 break; 5089 } 5090 default: 5091 ShouldNotReachHere(); 5092 } 5093 } 5094 5095 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) { 5096 assert_different_registers(src, dst); 5097 switch (klass_decode_mode()) { 5098 case KlassDecodeZero: { 5099 movptr(dst, src); 5100 shrq(dst, CompressedKlassPointers::shift()); 5101 break; 5102 } 5103 case KlassDecodeXor: { 5104 mov64(dst, (int64_t)CompressedKlassPointers::base()); 5105 xorq(dst, src); 5106 shrq(dst, CompressedKlassPointers::shift()); 5107 break; 5108 } 5109 case KlassDecodeAdd: { 5110 mov64(dst, -(int64_t)CompressedKlassPointers::base()); 5111 addq(dst, src); 5112 shrq(dst, CompressedKlassPointers::shift()); 5113 break; 5114 } 5115 default: 5116 ShouldNotReachHere(); 5117 } 5118 } 5119 5120 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) { 5121 assert_different_registers(r, tmp); 5122 const uint64_t base_u64 = (uint64_t)CompressedKlassPointers::base(); 5123 switch (klass_decode_mode()) { 5124 case KlassDecodeZero: { 5125 shlq(r, CompressedKlassPointers::shift()); 5126 break; 5127 } 5128 case KlassDecodeXor: { 5129 assert((base_u64 & (KlassEncodingMetaspaceMax - 1)) == 0, 5130 "base " UINT64_FORMAT_X " invalid for xor mode", base_u64); // should have been handled at VM init. 5131 shlq(r, CompressedKlassPointers::shift()); 5132 mov64(tmp, base_u64); 5133 xorq(r, tmp); 5134 break; 5135 } 5136 case KlassDecodeAdd: { 5137 shlq(r, CompressedKlassPointers::shift()); 5138 mov64(tmp, base_u64); 5139 addq(r, tmp); 5140 break; 5141 } 5142 default: 5143 ShouldNotReachHere(); 5144 } 5145 } 5146 5147 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) { 5148 assert_different_registers(src, dst); 5149 // Note: Cannot assert, unverified entry point counts instructions (see .ad file) 5150 // vtableStubs also counts instructions in pd_code_size_limit. 5151 // Also do not verify_oop as this is called by verify_oop. 5152 5153 const uint64_t base_u64 = (uint64_t)CompressedKlassPointers::base(); 5154 5155 switch (klass_decode_mode()) { 5156 case KlassDecodeZero: { 5157 movq(dst, src); 5158 shlq(dst, CompressedKlassPointers::shift()); 5159 break; 5160 } 5161 case KlassDecodeXor: { 5162 assert((base_u64 & (KlassEncodingMetaspaceMax - 1)) == 0, 5163 "base " UINT64_FORMAT_X " invalid for xor mode", base_u64); // should have been handled at VM init. 5164 const uint64_t base_right_shifted = base_u64 >> CompressedKlassPointers::shift(); 5165 mov64(dst, base_right_shifted); 5166 xorq(dst, src); 5167 shlq(dst, CompressedKlassPointers::shift()); 5168 break; 5169 } 5170 case KlassDecodeAdd: { 5171 assert((base_u64 & (KlassAlignmentInBytes - 1)) == 0, 5172 "base " UINT64_FORMAT_X " invalid for add mode", base_u64); // should have been handled at VM init. 5173 const uint64_t base_right_shifted = base_u64 >> CompressedKlassPointers::shift(); 5174 mov64(dst, base_right_shifted); 5175 addq(dst, src); 5176 shlq(dst, CompressedKlassPointers::shift()); 5177 break; 5178 } 5179 default: 5180 ShouldNotReachHere(); 5181 } 5182 } 5183 5184 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 5185 assert (UseCompressedOops, "should only be used for compressed headers"); 5186 assert (Universe::heap() != NULL, "java heap should be initialized"); 5187 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5188 int oop_index = oop_recorder()->find_index(obj); 5189 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5190 mov_narrow_oop(dst, oop_index, rspec); 5191 } 5192 5193 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 5194 assert (UseCompressedOops, "should only be used for compressed headers"); 5195 assert (Universe::heap() != NULL, "java heap should be initialized"); 5196 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5197 int oop_index = oop_recorder()->find_index(obj); 5198 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5199 mov_narrow_oop(dst, oop_index, rspec); 5200 } 5201 5202 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 5203 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5204 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5205 int klass_index = oop_recorder()->find_index(k); 5206 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5207 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5208 } 5209 5210 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 5211 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5212 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5213 int klass_index = oop_recorder()->find_index(k); 5214 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5215 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5216 } 5217 5218 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 5219 assert (UseCompressedOops, "should only be used for compressed headers"); 5220 assert (Universe::heap() != NULL, "java heap should be initialized"); 5221 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5222 int oop_index = oop_recorder()->find_index(obj); 5223 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5224 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 5225 } 5226 5227 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 5228 assert (UseCompressedOops, "should only be used for compressed headers"); 5229 assert (Universe::heap() != NULL, "java heap should be initialized"); 5230 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5231 int oop_index = oop_recorder()->find_index(obj); 5232 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5233 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 5234 } 5235 5236 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 5237 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5238 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5239 int klass_index = oop_recorder()->find_index(k); 5240 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5241 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5242 } 5243 5244 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 5245 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 5246 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5247 int klass_index = oop_recorder()->find_index(k); 5248 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 5249 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec); 5250 } 5251 5252 void MacroAssembler::reinit_heapbase() { 5253 if (UseCompressedOops) { 5254 if (Universe::heap() != NULL) { 5255 if (CompressedOops::base() == NULL) { 5256 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 5257 } else { 5258 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base()); 5259 } 5260 } else { 5261 movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr())); 5262 } 5263 } 5264 } 5265 5266 #endif // _LP64 5267 5268 // C2 compiled method's prolog code. 5269 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) { 5270 5271 // WARNING: Initial instruction MUST be 5 bytes or longer so that 5272 // NativeJump::patch_verified_entry will be able to patch out the entry 5273 // code safely. The push to verify stack depth is ok at 5 bytes, 5274 // the frame allocation can be either 3 or 6 bytes. So if we don't do 5275 // stack bang then we must use the 6 byte frame allocation even if 5276 // we have no frame. :-( 5277 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 5278 5279 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 5280 // Remove word for return addr 5281 framesize -= wordSize; 5282 stack_bang_size -= wordSize; 5283 5284 // Calls to C2R adapters often do not accept exceptional returns. 5285 // We require that their callers must bang for them. But be careful, because 5286 // some VM calls (such as call site linkage) can use several kilobytes of 5287 // stack. But the stack safety zone should account for that. 5288 // See bugs 4446381, 4468289, 4497237. 5289 if (stack_bang_size > 0) { 5290 generate_stack_overflow_check(stack_bang_size); 5291 5292 // We always push rbp, so that on return to interpreter rbp, will be 5293 // restored correctly and we can correct the stack. 5294 push(rbp); 5295 // Save caller's stack pointer into RBP if the frame pointer is preserved. 5296 if (PreserveFramePointer) { 5297 mov(rbp, rsp); 5298 } 5299 // Remove word for ebp 5300 framesize -= wordSize; 5301 5302 // Create frame 5303 if (framesize) { 5304 subptr(rsp, framesize); 5305 } 5306 } else { 5307 // Create frame (force generation of a 4 byte immediate value) 5308 subptr_imm32(rsp, framesize); 5309 5310 // Save RBP register now. 5311 framesize -= wordSize; 5312 movptr(Address(rsp, framesize), rbp); 5313 // Save caller's stack pointer into RBP if the frame pointer is preserved. 5314 if (PreserveFramePointer) { 5315 movptr(rbp, rsp); 5316 if (framesize > 0) { 5317 addptr(rbp, framesize); 5318 } 5319 } 5320 } 5321 5322 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 5323 framesize -= wordSize; 5324 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 5325 } 5326 5327 #ifndef _LP64 5328 // If method sets FPU control word do it now 5329 if (fp_mode_24b) { 5330 fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24())); 5331 } 5332 if (UseSSE >= 2 && VerifyFPU) { 5333 verify_FPU(0, "FPU stack must be clean on entry"); 5334 } 5335 #endif 5336 5337 #ifdef ASSERT 5338 if (VerifyStackAtCalls) { 5339 Label L; 5340 push(rax); 5341 mov(rax, rsp); 5342 andptr(rax, StackAlignmentInBytes-1); 5343 cmpptr(rax, StackAlignmentInBytes-wordSize); 5344 pop(rax); 5345 jcc(Assembler::equal, L); 5346 STOP("Stack is not properly aligned!"); 5347 bind(L); 5348 } 5349 #endif 5350 5351 if (!is_stub) { 5352 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler(); 5353 bs->nmethod_entry_barrier(this); 5354 } 5355 } 5356 5357 #if COMPILER2_OR_JVMCI 5358 5359 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers 5360 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) { 5361 // cnt - number of qwords (8-byte words). 5362 // base - start address, qword aligned. 5363 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end; 5364 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0); 5365 if (use64byteVector) { 5366 vpxor(xtmp, xtmp, xtmp, AVX_512bit); 5367 } else if (MaxVectorSize >= 32) { 5368 vpxor(xtmp, xtmp, xtmp, AVX_256bit); 5369 } else { 5370 pxor(xtmp, xtmp); 5371 } 5372 jmp(L_zero_64_bytes); 5373 5374 BIND(L_loop); 5375 if (MaxVectorSize >= 32) { 5376 fill64(base, 0, xtmp, use64byteVector); 5377 } else { 5378 movdqu(Address(base, 0), xtmp); 5379 movdqu(Address(base, 16), xtmp); 5380 movdqu(Address(base, 32), xtmp); 5381 movdqu(Address(base, 48), xtmp); 5382 } 5383 addptr(base, 64); 5384 5385 BIND(L_zero_64_bytes); 5386 subptr(cnt, 8); 5387 jccb(Assembler::greaterEqual, L_loop); 5388 5389 // Copy trailing 64 bytes 5390 if (use64byteVector) { 5391 addptr(cnt, 8); 5392 jccb(Assembler::equal, L_end); 5393 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true); 5394 jmp(L_end); 5395 } else { 5396 addptr(cnt, 4); 5397 jccb(Assembler::less, L_tail); 5398 if (MaxVectorSize >= 32) { 5399 vmovdqu(Address(base, 0), xtmp); 5400 } else { 5401 movdqu(Address(base, 0), xtmp); 5402 movdqu(Address(base, 16), xtmp); 5403 } 5404 } 5405 addptr(base, 32); 5406 subptr(cnt, 4); 5407 5408 BIND(L_tail); 5409 addptr(cnt, 4); 5410 jccb(Assembler::lessEqual, L_end); 5411 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) { 5412 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp); 5413 } else { 5414 decrement(cnt); 5415 5416 BIND(L_sloop); 5417 movq(Address(base, 0), xtmp); 5418 addptr(base, 8); 5419 decrement(cnt); 5420 jccb(Assembler::greaterEqual, L_sloop); 5421 } 5422 BIND(L_end); 5423 } 5424 5425 // Clearing constant sized memory using YMM/ZMM registers. 5426 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) { 5427 assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), ""); 5428 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0); 5429 5430 int vector64_count = (cnt & (~0x7)) >> 3; 5431 cnt = cnt & 0x7; 5432 5433 // 64 byte initialization loop. 5434 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit); 5435 for (int i = 0; i < vector64_count; i++) { 5436 fill64(base, i * 64, xtmp, use64byteVector); 5437 } 5438 5439 // Clear remaining 64 byte tail. 5440 int disp = vector64_count * 64; 5441 if (cnt) { 5442 switch (cnt) { 5443 case 1: 5444 movq(Address(base, disp), xtmp); 5445 break; 5446 case 2: 5447 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit); 5448 break; 5449 case 3: 5450 movl(rtmp, 0x7); 5451 kmovwl(mask, rtmp); 5452 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit); 5453 break; 5454 case 4: 5455 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit); 5456 break; 5457 case 5: 5458 if (use64byteVector) { 5459 movl(rtmp, 0x1F); 5460 kmovwl(mask, rtmp); 5461 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit); 5462 } else { 5463 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit); 5464 movq(Address(base, disp + 32), xtmp); 5465 } 5466 break; 5467 case 6: 5468 if (use64byteVector) { 5469 movl(rtmp, 0x3F); 5470 kmovwl(mask, rtmp); 5471 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit); 5472 } else { 5473 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit); 5474 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit); 5475 } 5476 break; 5477 case 7: 5478 if (use64byteVector) { 5479 movl(rtmp, 0x7F); 5480 kmovwl(mask, rtmp); 5481 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit); 5482 } else { 5483 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit); 5484 movl(rtmp, 0x7); 5485 kmovwl(mask, rtmp); 5486 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit); 5487 } 5488 break; 5489 default: 5490 fatal("Unexpected length : %d\n",cnt); 5491 break; 5492 } 5493 } 5494 } 5495 5496 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp, 5497 bool is_large, KRegister mask) { 5498 // cnt - number of qwords (8-byte words). 5499 // base - start address, qword aligned. 5500 // is_large - if optimizers know cnt is larger than InitArrayShortSize 5501 assert(base==rdi, "base register must be edi for rep stos"); 5502 assert(tmp==rax, "tmp register must be eax for rep stos"); 5503 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 5504 assert(InitArrayShortSize % BytesPerLong == 0, 5505 "InitArrayShortSize should be the multiple of BytesPerLong"); 5506 5507 Label DONE; 5508 if (!is_large || !UseXMMForObjInit) { 5509 xorptr(tmp, tmp); 5510 } 5511 5512 if (!is_large) { 5513 Label LOOP, LONG; 5514 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 5515 jccb(Assembler::greater, LONG); 5516 5517 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5518 5519 decrement(cnt); 5520 jccb(Assembler::negative, DONE); // Zero length 5521 5522 // Use individual pointer-sized stores for small counts: 5523 BIND(LOOP); 5524 movptr(Address(base, cnt, Address::times_ptr), tmp); 5525 decrement(cnt); 5526 jccb(Assembler::greaterEqual, LOOP); 5527 jmpb(DONE); 5528 5529 BIND(LONG); 5530 } 5531 5532 // Use longer rep-prefixed ops for non-small counts: 5533 if (UseFastStosb) { 5534 shlptr(cnt, 3); // convert to number of bytes 5535 rep_stosb(); 5536 } else if (UseXMMForObjInit) { 5537 xmm_clear_mem(base, cnt, tmp, xtmp, mask); 5538 } else { 5539 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 5540 rep_stos(); 5541 } 5542 5543 BIND(DONE); 5544 } 5545 5546 #endif //COMPILER2_OR_JVMCI 5547 5548 5549 void MacroAssembler::generate_fill(BasicType t, bool aligned, 5550 Register to, Register value, Register count, 5551 Register rtmp, XMMRegister xtmp) { 5552 ShortBranchVerifier sbv(this); 5553 assert_different_registers(to, value, count, rtmp); 5554 Label L_exit; 5555 Label L_fill_2_bytes, L_fill_4_bytes; 5556 5557 #if defined(COMPILER2) && defined(_LP64) 5558 if(MaxVectorSize >=32 && 5559 VM_Version::supports_avx512vlbw() && 5560 VM_Version::supports_bmi2()) { 5561 generate_fill_avx3(t, to, value, count, rtmp, xtmp); 5562 return; 5563 } 5564 #endif 5565 5566 int shift = -1; 5567 switch (t) { 5568 case T_BYTE: 5569 shift = 2; 5570 break; 5571 case T_SHORT: 5572 shift = 1; 5573 break; 5574 case T_INT: 5575 shift = 0; 5576 break; 5577 default: ShouldNotReachHere(); 5578 } 5579 5580 if (t == T_BYTE) { 5581 andl(value, 0xff); 5582 movl(rtmp, value); 5583 shll(rtmp, 8); 5584 orl(value, rtmp); 5585 } 5586 if (t == T_SHORT) { 5587 andl(value, 0xffff); 5588 } 5589 if (t == T_BYTE || t == T_SHORT) { 5590 movl(rtmp, value); 5591 shll(rtmp, 16); 5592 orl(value, rtmp); 5593 } 5594 5595 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 5596 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 5597 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 5598 Label L_skip_align2; 5599 // align source address at 4 bytes address boundary 5600 if (t == T_BYTE) { 5601 Label L_skip_align1; 5602 // One byte misalignment happens only for byte arrays 5603 testptr(to, 1); 5604 jccb(Assembler::zero, L_skip_align1); 5605 movb(Address(to, 0), value); 5606 increment(to); 5607 decrement(count); 5608 BIND(L_skip_align1); 5609 } 5610 // Two bytes misalignment happens only for byte and short (char) arrays 5611 testptr(to, 2); 5612 jccb(Assembler::zero, L_skip_align2); 5613 movw(Address(to, 0), value); 5614 addptr(to, 2); 5615 subl(count, 1<<(shift-1)); 5616 BIND(L_skip_align2); 5617 } 5618 if (UseSSE < 2) { 5619 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5620 // Fill 32-byte chunks 5621 subl(count, 8 << shift); 5622 jcc(Assembler::less, L_check_fill_8_bytes); 5623 align(16); 5624 5625 BIND(L_fill_32_bytes_loop); 5626 5627 for (int i = 0; i < 32; i += 4) { 5628 movl(Address(to, i), value); 5629 } 5630 5631 addptr(to, 32); 5632 subl(count, 8 << shift); 5633 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 5634 BIND(L_check_fill_8_bytes); 5635 addl(count, 8 << shift); 5636 jccb(Assembler::zero, L_exit); 5637 jmpb(L_fill_8_bytes); 5638 5639 // 5640 // length is too short, just fill qwords 5641 // 5642 BIND(L_fill_8_bytes_loop); 5643 movl(Address(to, 0), value); 5644 movl(Address(to, 4), value); 5645 addptr(to, 8); 5646 BIND(L_fill_8_bytes); 5647 subl(count, 1 << (shift + 1)); 5648 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 5649 // fall through to fill 4 bytes 5650 } else { 5651 Label L_fill_32_bytes; 5652 if (!UseUnalignedLoadStores) { 5653 // align to 8 bytes, we know we are 4 byte aligned to start 5654 testptr(to, 4); 5655 jccb(Assembler::zero, L_fill_32_bytes); 5656 movl(Address(to, 0), value); 5657 addptr(to, 4); 5658 subl(count, 1<<shift); 5659 } 5660 BIND(L_fill_32_bytes); 5661 { 5662 assert( UseSSE >= 2, "supported cpu only" ); 5663 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 5664 movdl(xtmp, value); 5665 if (UseAVX >= 2 && UseUnalignedLoadStores) { 5666 Label L_check_fill_32_bytes; 5667 if (UseAVX > 2) { 5668 // Fill 64-byte chunks 5669 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2; 5670 5671 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2 5672 cmpl(count, VM_Version::avx3_threshold()); 5673 jccb(Assembler::below, L_check_fill_64_bytes_avx2); 5674 5675 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 5676 5677 subl(count, 16 << shift); 5678 jccb(Assembler::less, L_check_fill_32_bytes); 5679 align(16); 5680 5681 BIND(L_fill_64_bytes_loop_avx3); 5682 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 5683 addptr(to, 64); 5684 subl(count, 16 << shift); 5685 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3); 5686 jmpb(L_check_fill_32_bytes); 5687 5688 BIND(L_check_fill_64_bytes_avx2); 5689 } 5690 // Fill 64-byte chunks 5691 Label L_fill_64_bytes_loop; 5692 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit); 5693 5694 subl(count, 16 << shift); 5695 jcc(Assembler::less, L_check_fill_32_bytes); 5696 align(16); 5697 5698 BIND(L_fill_64_bytes_loop); 5699 vmovdqu(Address(to, 0), xtmp); 5700 vmovdqu(Address(to, 32), xtmp); 5701 addptr(to, 64); 5702 subl(count, 16 << shift); 5703 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 5704 5705 BIND(L_check_fill_32_bytes); 5706 addl(count, 8 << shift); 5707 jccb(Assembler::less, L_check_fill_8_bytes); 5708 vmovdqu(Address(to, 0), xtmp); 5709 addptr(to, 32); 5710 subl(count, 8 << shift); 5711 5712 BIND(L_check_fill_8_bytes); 5713 // clean upper bits of YMM registers 5714 movdl(xtmp, value); 5715 pshufd(xtmp, xtmp, 0); 5716 } else { 5717 // Fill 32-byte chunks 5718 pshufd(xtmp, xtmp, 0); 5719 5720 subl(count, 8 << shift); 5721 jcc(Assembler::less, L_check_fill_8_bytes); 5722 align(16); 5723 5724 BIND(L_fill_32_bytes_loop); 5725 5726 if (UseUnalignedLoadStores) { 5727 movdqu(Address(to, 0), xtmp); 5728 movdqu(Address(to, 16), xtmp); 5729 } else { 5730 movq(Address(to, 0), xtmp); 5731 movq(Address(to, 8), xtmp); 5732 movq(Address(to, 16), xtmp); 5733 movq(Address(to, 24), xtmp); 5734 } 5735 5736 addptr(to, 32); 5737 subl(count, 8 << shift); 5738 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 5739 5740 BIND(L_check_fill_8_bytes); 5741 } 5742 addl(count, 8 << shift); 5743 jccb(Assembler::zero, L_exit); 5744 jmpb(L_fill_8_bytes); 5745 5746 // 5747 // length is too short, just fill qwords 5748 // 5749 BIND(L_fill_8_bytes_loop); 5750 movq(Address(to, 0), xtmp); 5751 addptr(to, 8); 5752 BIND(L_fill_8_bytes); 5753 subl(count, 1 << (shift + 1)); 5754 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 5755 } 5756 } 5757 // fill trailing 4 bytes 5758 BIND(L_fill_4_bytes); 5759 testl(count, 1<<shift); 5760 jccb(Assembler::zero, L_fill_2_bytes); 5761 movl(Address(to, 0), value); 5762 if (t == T_BYTE || t == T_SHORT) { 5763 Label L_fill_byte; 5764 addptr(to, 4); 5765 BIND(L_fill_2_bytes); 5766 // fill trailing 2 bytes 5767 testl(count, 1<<(shift-1)); 5768 jccb(Assembler::zero, L_fill_byte); 5769 movw(Address(to, 0), value); 5770 if (t == T_BYTE) { 5771 addptr(to, 2); 5772 BIND(L_fill_byte); 5773 // fill trailing byte 5774 testl(count, 1); 5775 jccb(Assembler::zero, L_exit); 5776 movb(Address(to, 0), value); 5777 } else { 5778 BIND(L_fill_byte); 5779 } 5780 } else { 5781 BIND(L_fill_2_bytes); 5782 } 5783 BIND(L_exit); 5784 } 5785 5786 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) { 5787 switch(type) { 5788 case T_BYTE: 5789 case T_BOOLEAN: 5790 evpbroadcastb(dst, src, vector_len); 5791 break; 5792 case T_SHORT: 5793 case T_CHAR: 5794 evpbroadcastw(dst, src, vector_len); 5795 break; 5796 case T_INT: 5797 case T_FLOAT: 5798 evpbroadcastd(dst, src, vector_len); 5799 break; 5800 case T_LONG: 5801 case T_DOUBLE: 5802 evpbroadcastq(dst, src, vector_len); 5803 break; 5804 default: 5805 fatal("Unhandled type : %s", type2name(type)); 5806 break; 5807 } 5808 } 5809 5810 // encode char[] to byte[] in ISO_8859_1 or ASCII 5811 //@IntrinsicCandidate 5812 //private static int implEncodeISOArray(byte[] sa, int sp, 5813 //byte[] da, int dp, int len) { 5814 // int i = 0; 5815 // for (; i < len; i++) { 5816 // char c = StringUTF16.getChar(sa, sp++); 5817 // if (c > '\u00FF') 5818 // break; 5819 // da[dp++] = (byte)c; 5820 // } 5821 // return i; 5822 //} 5823 // 5824 //@IntrinsicCandidate 5825 //private static int implEncodeAsciiArray(char[] sa, int sp, 5826 // byte[] da, int dp, int len) { 5827 // int i = 0; 5828 // for (; i < len; i++) { 5829 // char c = sa[sp++]; 5830 // if (c >= '\u0080') 5831 // break; 5832 // da[dp++] = (byte)c; 5833 // } 5834 // return i; 5835 //} 5836 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 5837 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 5838 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 5839 Register tmp5, Register result, bool ascii) { 5840 5841 // rsi: src 5842 // rdi: dst 5843 // rdx: len 5844 // rcx: tmp5 5845 // rax: result 5846 ShortBranchVerifier sbv(this); 5847 assert_different_registers(src, dst, len, tmp5, result); 5848 Label L_done, L_copy_1_char, L_copy_1_char_exit; 5849 5850 int mask = ascii ? 0xff80ff80 : 0xff00ff00; 5851 int short_mask = ascii ? 0xff80 : 0xff00; 5852 5853 // set result 5854 xorl(result, result); 5855 // check for zero length 5856 testl(len, len); 5857 jcc(Assembler::zero, L_done); 5858 5859 movl(result, len); 5860 5861 // Setup pointers 5862 lea(src, Address(src, len, Address::times_2)); // char[] 5863 lea(dst, Address(dst, len, Address::times_1)); // byte[] 5864 negptr(len); 5865 5866 if (UseSSE42Intrinsics || UseAVX >= 2) { 5867 Label L_copy_8_chars, L_copy_8_chars_exit; 5868 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 5869 5870 if (UseAVX >= 2) { 5871 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 5872 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector 5873 movdl(tmp1Reg, tmp5); 5874 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit); 5875 jmp(L_chars_32_check); 5876 5877 bind(L_copy_32_chars); 5878 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 5879 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 5880 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 5881 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector 5882 jccb(Assembler::notZero, L_copy_32_chars_exit); 5883 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 5884 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 5885 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 5886 5887 bind(L_chars_32_check); 5888 addptr(len, 32); 5889 jcc(Assembler::lessEqual, L_copy_32_chars); 5890 5891 bind(L_copy_32_chars_exit); 5892 subptr(len, 16); 5893 jccb(Assembler::greater, L_copy_16_chars_exit); 5894 5895 } else if (UseSSE42Intrinsics) { 5896 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector 5897 movdl(tmp1Reg, tmp5); 5898 pshufd(tmp1Reg, tmp1Reg, 0); 5899 jmpb(L_chars_16_check); 5900 } 5901 5902 bind(L_copy_16_chars); 5903 if (UseAVX >= 2) { 5904 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 5905 vptest(tmp2Reg, tmp1Reg); 5906 jcc(Assembler::notZero, L_copy_16_chars_exit); 5907 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 5908 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 5909 } else { 5910 if (UseAVX > 0) { 5911 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 5912 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 5913 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 5914 } else { 5915 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 5916 por(tmp2Reg, tmp3Reg); 5917 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 5918 por(tmp2Reg, tmp4Reg); 5919 } 5920 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector 5921 jccb(Assembler::notZero, L_copy_16_chars_exit); 5922 packuswb(tmp3Reg, tmp4Reg); 5923 } 5924 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 5925 5926 bind(L_chars_16_check); 5927 addptr(len, 16); 5928 jcc(Assembler::lessEqual, L_copy_16_chars); 5929 5930 bind(L_copy_16_chars_exit); 5931 if (UseAVX >= 2) { 5932 // clean upper bits of YMM registers 5933 vpxor(tmp2Reg, tmp2Reg); 5934 vpxor(tmp3Reg, tmp3Reg); 5935 vpxor(tmp4Reg, tmp4Reg); 5936 movdl(tmp1Reg, tmp5); 5937 pshufd(tmp1Reg, tmp1Reg, 0); 5938 } 5939 subptr(len, 8); 5940 jccb(Assembler::greater, L_copy_8_chars_exit); 5941 5942 bind(L_copy_8_chars); 5943 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 5944 ptest(tmp3Reg, tmp1Reg); 5945 jccb(Assembler::notZero, L_copy_8_chars_exit); 5946 packuswb(tmp3Reg, tmp1Reg); 5947 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 5948 addptr(len, 8); 5949 jccb(Assembler::lessEqual, L_copy_8_chars); 5950 5951 bind(L_copy_8_chars_exit); 5952 subptr(len, 8); 5953 jccb(Assembler::zero, L_done); 5954 } 5955 5956 bind(L_copy_1_char); 5957 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 5958 testl(tmp5, short_mask); // check if Unicode or non-ASCII char 5959 jccb(Assembler::notZero, L_copy_1_char_exit); 5960 movb(Address(dst, len, Address::times_1, 0), tmp5); 5961 addptr(len, 1); 5962 jccb(Assembler::less, L_copy_1_char); 5963 5964 bind(L_copy_1_char_exit); 5965 addptr(result, len); // len is negative count of not processed elements 5966 5967 bind(L_done); 5968 } 5969 5970 #ifdef _LP64 5971 /** 5972 * Helper for multiply_to_len(). 5973 */ 5974 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 5975 addq(dest_lo, src1); 5976 adcq(dest_hi, 0); 5977 addq(dest_lo, src2); 5978 adcq(dest_hi, 0); 5979 } 5980 5981 /** 5982 * Multiply 64 bit by 64 bit first loop. 5983 */ 5984 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 5985 Register y, Register y_idx, Register z, 5986 Register carry, Register product, 5987 Register idx, Register kdx) { 5988 // 5989 // jlong carry, x[], y[], z[]; 5990 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 5991 // huge_128 product = y[idx] * x[xstart] + carry; 5992 // z[kdx] = (jlong)product; 5993 // carry = (jlong)(product >>> 64); 5994 // } 5995 // z[xstart] = carry; 5996 // 5997 5998 Label L_first_loop, L_first_loop_exit; 5999 Label L_one_x, L_one_y, L_multiply; 6000 6001 decrementl(xstart); 6002 jcc(Assembler::negative, L_one_x); 6003 6004 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 6005 rorq(x_xstart, 32); // convert big-endian to little-endian 6006 6007 bind(L_first_loop); 6008 decrementl(idx); 6009 jcc(Assembler::negative, L_first_loop_exit); 6010 decrementl(idx); 6011 jcc(Assembler::negative, L_one_y); 6012 movq(y_idx, Address(y, idx, Address::times_4, 0)); 6013 rorq(y_idx, 32); // convert big-endian to little-endian 6014 bind(L_multiply); 6015 movq(product, x_xstart); 6016 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 6017 addq(product, carry); 6018 adcq(rdx, 0); 6019 subl(kdx, 2); 6020 movl(Address(z, kdx, Address::times_4, 4), product); 6021 shrq(product, 32); 6022 movl(Address(z, kdx, Address::times_4, 0), product); 6023 movq(carry, rdx); 6024 jmp(L_first_loop); 6025 6026 bind(L_one_y); 6027 movl(y_idx, Address(y, 0)); 6028 jmp(L_multiply); 6029 6030 bind(L_one_x); 6031 movl(x_xstart, Address(x, 0)); 6032 jmp(L_first_loop); 6033 6034 bind(L_first_loop_exit); 6035 } 6036 6037 /** 6038 * Multiply 64 bit by 64 bit and add 128 bit. 6039 */ 6040 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 6041 Register yz_idx, Register idx, 6042 Register carry, Register product, int offset) { 6043 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 6044 // z[kdx] = (jlong)product; 6045 6046 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 6047 rorq(yz_idx, 32); // convert big-endian to little-endian 6048 movq(product, x_xstart); 6049 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 6050 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 6051 rorq(yz_idx, 32); // convert big-endian to little-endian 6052 6053 add2_with_carry(rdx, product, carry, yz_idx); 6054 6055 movl(Address(z, idx, Address::times_4, offset+4), product); 6056 shrq(product, 32); 6057 movl(Address(z, idx, Address::times_4, offset), product); 6058 6059 } 6060 6061 /** 6062 * Multiply 128 bit by 128 bit. Unrolled inner loop. 6063 */ 6064 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 6065 Register yz_idx, Register idx, Register jdx, 6066 Register carry, Register product, 6067 Register carry2) { 6068 // jlong carry, x[], y[], z[]; 6069 // int kdx = ystart+1; 6070 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 6071 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 6072 // z[kdx+idx+1] = (jlong)product; 6073 // jlong carry2 = (jlong)(product >>> 64); 6074 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 6075 // z[kdx+idx] = (jlong)product; 6076 // carry = (jlong)(product >>> 64); 6077 // } 6078 // idx += 2; 6079 // if (idx > 0) { 6080 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 6081 // z[kdx+idx] = (jlong)product; 6082 // carry = (jlong)(product >>> 64); 6083 // } 6084 // 6085 6086 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 6087 6088 movl(jdx, idx); 6089 andl(jdx, 0xFFFFFFFC); 6090 shrl(jdx, 2); 6091 6092 bind(L_third_loop); 6093 subl(jdx, 1); 6094 jcc(Assembler::negative, L_third_loop_exit); 6095 subl(idx, 4); 6096 6097 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 6098 movq(carry2, rdx); 6099 6100 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 6101 movq(carry, rdx); 6102 jmp(L_third_loop); 6103 6104 bind (L_third_loop_exit); 6105 6106 andl (idx, 0x3); 6107 jcc(Assembler::zero, L_post_third_loop_done); 6108 6109 Label L_check_1; 6110 subl(idx, 2); 6111 jcc(Assembler::negative, L_check_1); 6112 6113 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 6114 movq(carry, rdx); 6115 6116 bind (L_check_1); 6117 addl (idx, 0x2); 6118 andl (idx, 0x1); 6119 subl(idx, 1); 6120 jcc(Assembler::negative, L_post_third_loop_done); 6121 6122 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 6123 movq(product, x_xstart); 6124 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 6125 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 6126 6127 add2_with_carry(rdx, product, yz_idx, carry); 6128 6129 movl(Address(z, idx, Address::times_4, 0), product); 6130 shrq(product, 32); 6131 6132 shlq(rdx, 32); 6133 orq(product, rdx); 6134 movq(carry, product); 6135 6136 bind(L_post_third_loop_done); 6137 } 6138 6139 /** 6140 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 6141 * 6142 */ 6143 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 6144 Register carry, Register carry2, 6145 Register idx, Register jdx, 6146 Register yz_idx1, Register yz_idx2, 6147 Register tmp, Register tmp3, Register tmp4) { 6148 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 6149 6150 // jlong carry, x[], y[], z[]; 6151 // int kdx = ystart+1; 6152 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 6153 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 6154 // jlong carry2 = (jlong)(tmp3 >>> 64); 6155 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 6156 // carry = (jlong)(tmp4 >>> 64); 6157 // z[kdx+idx+1] = (jlong)tmp3; 6158 // z[kdx+idx] = (jlong)tmp4; 6159 // } 6160 // idx += 2; 6161 // if (idx > 0) { 6162 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 6163 // z[kdx+idx] = (jlong)yz_idx1; 6164 // carry = (jlong)(yz_idx1 >>> 64); 6165 // } 6166 // 6167 6168 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 6169 6170 movl(jdx, idx); 6171 andl(jdx, 0xFFFFFFFC); 6172 shrl(jdx, 2); 6173 6174 bind(L_third_loop); 6175 subl(jdx, 1); 6176 jcc(Assembler::negative, L_third_loop_exit); 6177 subl(idx, 4); 6178 6179 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 6180 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 6181 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 6182 rorxq(yz_idx2, yz_idx2, 32); 6183 6184 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 6185 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 6186 6187 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 6188 rorxq(yz_idx1, yz_idx1, 32); 6189 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 6190 rorxq(yz_idx2, yz_idx2, 32); 6191 6192 if (VM_Version::supports_adx()) { 6193 adcxq(tmp3, carry); 6194 adoxq(tmp3, yz_idx1); 6195 6196 adcxq(tmp4, tmp); 6197 adoxq(tmp4, yz_idx2); 6198 6199 movl(carry, 0); // does not affect flags 6200 adcxq(carry2, carry); 6201 adoxq(carry2, carry); 6202 } else { 6203 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 6204 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 6205 } 6206 movq(carry, carry2); 6207 6208 movl(Address(z, idx, Address::times_4, 12), tmp3); 6209 shrq(tmp3, 32); 6210 movl(Address(z, idx, Address::times_4, 8), tmp3); 6211 6212 movl(Address(z, idx, Address::times_4, 4), tmp4); 6213 shrq(tmp4, 32); 6214 movl(Address(z, idx, Address::times_4, 0), tmp4); 6215 6216 jmp(L_third_loop); 6217 6218 bind (L_third_loop_exit); 6219 6220 andl (idx, 0x3); 6221 jcc(Assembler::zero, L_post_third_loop_done); 6222 6223 Label L_check_1; 6224 subl(idx, 2); 6225 jcc(Assembler::negative, L_check_1); 6226 6227 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 6228 rorxq(yz_idx1, yz_idx1, 32); 6229 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 6230 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 6231 rorxq(yz_idx2, yz_idx2, 32); 6232 6233 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 6234 6235 movl(Address(z, idx, Address::times_4, 4), tmp3); 6236 shrq(tmp3, 32); 6237 movl(Address(z, idx, Address::times_4, 0), tmp3); 6238 movq(carry, tmp4); 6239 6240 bind (L_check_1); 6241 addl (idx, 0x2); 6242 andl (idx, 0x1); 6243 subl(idx, 1); 6244 jcc(Assembler::negative, L_post_third_loop_done); 6245 movl(tmp4, Address(y, idx, Address::times_4, 0)); 6246 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 6247 movl(tmp4, Address(z, idx, Address::times_4, 0)); 6248 6249 add2_with_carry(carry2, tmp3, tmp4, carry); 6250 6251 movl(Address(z, idx, Address::times_4, 0), tmp3); 6252 shrq(tmp3, 32); 6253 6254 shlq(carry2, 32); 6255 orq(tmp3, carry2); 6256 movq(carry, tmp3); 6257 6258 bind(L_post_third_loop_done); 6259 } 6260 6261 /** 6262 * Code for BigInteger::multiplyToLen() intrinsic. 6263 * 6264 * rdi: x 6265 * rax: xlen 6266 * rsi: y 6267 * rcx: ylen 6268 * r8: z 6269 * r11: zlen 6270 * r12: tmp1 6271 * r13: tmp2 6272 * r14: tmp3 6273 * r15: tmp4 6274 * rbx: tmp5 6275 * 6276 */ 6277 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 6278 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 6279 ShortBranchVerifier sbv(this); 6280 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 6281 6282 push(tmp1); 6283 push(tmp2); 6284 push(tmp3); 6285 push(tmp4); 6286 push(tmp5); 6287 6288 push(xlen); 6289 push(zlen); 6290 6291 const Register idx = tmp1; 6292 const Register kdx = tmp2; 6293 const Register xstart = tmp3; 6294 6295 const Register y_idx = tmp4; 6296 const Register carry = tmp5; 6297 const Register product = xlen; 6298 const Register x_xstart = zlen; // reuse register 6299 6300 // First Loop. 6301 // 6302 // final static long LONG_MASK = 0xffffffffL; 6303 // int xstart = xlen - 1; 6304 // int ystart = ylen - 1; 6305 // long carry = 0; 6306 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 6307 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 6308 // z[kdx] = (int)product; 6309 // carry = product >>> 32; 6310 // } 6311 // z[xstart] = (int)carry; 6312 // 6313 6314 movl(idx, ylen); // idx = ylen; 6315 movl(kdx, zlen); // kdx = xlen+ylen; 6316 xorq(carry, carry); // carry = 0; 6317 6318 Label L_done; 6319 6320 movl(xstart, xlen); 6321 decrementl(xstart); 6322 jcc(Assembler::negative, L_done); 6323 6324 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 6325 6326 Label L_second_loop; 6327 testl(kdx, kdx); 6328 jcc(Assembler::zero, L_second_loop); 6329 6330 Label L_carry; 6331 subl(kdx, 1); 6332 jcc(Assembler::zero, L_carry); 6333 6334 movl(Address(z, kdx, Address::times_4, 0), carry); 6335 shrq(carry, 32); 6336 subl(kdx, 1); 6337 6338 bind(L_carry); 6339 movl(Address(z, kdx, Address::times_4, 0), carry); 6340 6341 // Second and third (nested) loops. 6342 // 6343 // for (int i = xstart-1; i >= 0; i--) { // Second loop 6344 // carry = 0; 6345 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 6346 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 6347 // (z[k] & LONG_MASK) + carry; 6348 // z[k] = (int)product; 6349 // carry = product >>> 32; 6350 // } 6351 // z[i] = (int)carry; 6352 // } 6353 // 6354 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 6355 6356 const Register jdx = tmp1; 6357 6358 bind(L_second_loop); 6359 xorl(carry, carry); // carry = 0; 6360 movl(jdx, ylen); // j = ystart+1 6361 6362 subl(xstart, 1); // i = xstart-1; 6363 jcc(Assembler::negative, L_done); 6364 6365 push (z); 6366 6367 Label L_last_x; 6368 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 6369 subl(xstart, 1); // i = xstart-1; 6370 jcc(Assembler::negative, L_last_x); 6371 6372 if (UseBMI2Instructions) { 6373 movq(rdx, Address(x, xstart, Address::times_4, 0)); 6374 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 6375 } else { 6376 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 6377 rorq(x_xstart, 32); // convert big-endian to little-endian 6378 } 6379 6380 Label L_third_loop_prologue; 6381 bind(L_third_loop_prologue); 6382 6383 push (x); 6384 push (xstart); 6385 push (ylen); 6386 6387 6388 if (UseBMI2Instructions) { 6389 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 6390 } else { // !UseBMI2Instructions 6391 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 6392 } 6393 6394 pop(ylen); 6395 pop(xlen); 6396 pop(x); 6397 pop(z); 6398 6399 movl(tmp3, xlen); 6400 addl(tmp3, 1); 6401 movl(Address(z, tmp3, Address::times_4, 0), carry); 6402 subl(tmp3, 1); 6403 jccb(Assembler::negative, L_done); 6404 6405 shrq(carry, 32); 6406 movl(Address(z, tmp3, Address::times_4, 0), carry); 6407 jmp(L_second_loop); 6408 6409 // Next infrequent code is moved outside loops. 6410 bind(L_last_x); 6411 if (UseBMI2Instructions) { 6412 movl(rdx, Address(x, 0)); 6413 } else { 6414 movl(x_xstart, Address(x, 0)); 6415 } 6416 jmp(L_third_loop_prologue); 6417 6418 bind(L_done); 6419 6420 pop(zlen); 6421 pop(xlen); 6422 6423 pop(tmp5); 6424 pop(tmp4); 6425 pop(tmp3); 6426 pop(tmp2); 6427 pop(tmp1); 6428 } 6429 6430 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 6431 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 6432 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 6433 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 6434 Label VECTOR8_TAIL, VECTOR4_TAIL; 6435 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 6436 Label SAME_TILL_END, DONE; 6437 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 6438 6439 //scale is in rcx in both Win64 and Unix 6440 ShortBranchVerifier sbv(this); 6441 6442 shlq(length); 6443 xorq(result, result); 6444 6445 if ((AVX3Threshold == 0) && (UseAVX > 2) && 6446 VM_Version::supports_avx512vlbw()) { 6447 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL; 6448 6449 cmpq(length, 64); 6450 jcc(Assembler::less, VECTOR32_TAIL); 6451 6452 movq(tmp1, length); 6453 andq(tmp1, 0x3F); // tail count 6454 andq(length, ~(0x3F)); //vector count 6455 6456 bind(VECTOR64_LOOP); 6457 // AVX512 code to compare 64 byte vectors. 6458 evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit); 6459 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit); 6460 kortestql(k7, k7); 6461 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch 6462 addq(result, 64); 6463 subq(length, 64); 6464 jccb(Assembler::notZero, VECTOR64_LOOP); 6465 6466 //bind(VECTOR64_TAIL); 6467 testq(tmp1, tmp1); 6468 jcc(Assembler::zero, SAME_TILL_END); 6469 6470 //bind(VECTOR64_TAIL); 6471 // AVX512 code to compare up to 63 byte vectors. 6472 mov64(tmp2, 0xFFFFFFFFFFFFFFFF); 6473 shlxq(tmp2, tmp2, tmp1); 6474 notq(tmp2); 6475 kmovql(k3, tmp2); 6476 6477 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit); 6478 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit); 6479 6480 ktestql(k7, k3); 6481 jcc(Assembler::below, SAME_TILL_END); // not mismatch 6482 6483 bind(VECTOR64_NOT_EQUAL); 6484 kmovql(tmp1, k7); 6485 notq(tmp1); 6486 tzcntq(tmp1, tmp1); 6487 addq(result, tmp1); 6488 shrq(result); 6489 jmp(DONE); 6490 bind(VECTOR32_TAIL); 6491 } 6492 6493 cmpq(length, 8); 6494 jcc(Assembler::equal, VECTOR8_LOOP); 6495 jcc(Assembler::less, VECTOR4_TAIL); 6496 6497 if (UseAVX >= 2) { 6498 Label VECTOR16_TAIL, VECTOR32_LOOP; 6499 6500 cmpq(length, 16); 6501 jcc(Assembler::equal, VECTOR16_LOOP); 6502 jcc(Assembler::less, VECTOR8_LOOP); 6503 6504 cmpq(length, 32); 6505 jccb(Assembler::less, VECTOR16_TAIL); 6506 6507 subq(length, 32); 6508 bind(VECTOR32_LOOP); 6509 vmovdqu(rymm0, Address(obja, result)); 6510 vmovdqu(rymm1, Address(objb, result)); 6511 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 6512 vptest(rymm2, rymm2); 6513 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 6514 addq(result, 32); 6515 subq(length, 32); 6516 jcc(Assembler::greaterEqual, VECTOR32_LOOP); 6517 addq(length, 32); 6518 jcc(Assembler::equal, SAME_TILL_END); 6519 //falling through if less than 32 bytes left //close the branch here. 6520 6521 bind(VECTOR16_TAIL); 6522 cmpq(length, 16); 6523 jccb(Assembler::less, VECTOR8_TAIL); 6524 bind(VECTOR16_LOOP); 6525 movdqu(rymm0, Address(obja, result)); 6526 movdqu(rymm1, Address(objb, result)); 6527 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 6528 ptest(rymm2, rymm2); 6529 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6530 addq(result, 16); 6531 subq(length, 16); 6532 jcc(Assembler::equal, SAME_TILL_END); 6533 //falling through if less than 16 bytes left 6534 } else {//regular intrinsics 6535 6536 cmpq(length, 16); 6537 jccb(Assembler::less, VECTOR8_TAIL); 6538 6539 subq(length, 16); 6540 bind(VECTOR16_LOOP); 6541 movdqu(rymm0, Address(obja, result)); 6542 movdqu(rymm1, Address(objb, result)); 6543 pxor(rymm0, rymm1); 6544 ptest(rymm0, rymm0); 6545 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 6546 addq(result, 16); 6547 subq(length, 16); 6548 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 6549 addq(length, 16); 6550 jcc(Assembler::equal, SAME_TILL_END); 6551 //falling through if less than 16 bytes left 6552 } 6553 6554 bind(VECTOR8_TAIL); 6555 cmpq(length, 8); 6556 jccb(Assembler::less, VECTOR4_TAIL); 6557 bind(VECTOR8_LOOP); 6558 movq(tmp1, Address(obja, result)); 6559 movq(tmp2, Address(objb, result)); 6560 xorq(tmp1, tmp2); 6561 testq(tmp1, tmp1); 6562 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 6563 addq(result, 8); 6564 subq(length, 8); 6565 jcc(Assembler::equal, SAME_TILL_END); 6566 //falling through if less than 8 bytes left 6567 6568 bind(VECTOR4_TAIL); 6569 cmpq(length, 4); 6570 jccb(Assembler::less, BYTES_TAIL); 6571 bind(VECTOR4_LOOP); 6572 movl(tmp1, Address(obja, result)); 6573 xorl(tmp1, Address(objb, result)); 6574 testl(tmp1, tmp1); 6575 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 6576 addq(result, 4); 6577 subq(length, 4); 6578 jcc(Assembler::equal, SAME_TILL_END); 6579 //falling through if less than 4 bytes left 6580 6581 bind(BYTES_TAIL); 6582 bind(BYTES_LOOP); 6583 load_unsigned_byte(tmp1, Address(obja, result)); 6584 load_unsigned_byte(tmp2, Address(objb, result)); 6585 xorl(tmp1, tmp2); 6586 testl(tmp1, tmp1); 6587 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6588 decq(length); 6589 jcc(Assembler::zero, SAME_TILL_END); 6590 incq(result); 6591 load_unsigned_byte(tmp1, Address(obja, result)); 6592 load_unsigned_byte(tmp2, Address(objb, result)); 6593 xorl(tmp1, tmp2); 6594 testl(tmp1, tmp1); 6595 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6596 decq(length); 6597 jcc(Assembler::zero, SAME_TILL_END); 6598 incq(result); 6599 load_unsigned_byte(tmp1, Address(obja, result)); 6600 load_unsigned_byte(tmp2, Address(objb, result)); 6601 xorl(tmp1, tmp2); 6602 testl(tmp1, tmp1); 6603 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 6604 jmp(SAME_TILL_END); 6605 6606 if (UseAVX >= 2) { 6607 bind(VECTOR32_NOT_EQUAL); 6608 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 6609 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 6610 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 6611 vpmovmskb(tmp1, rymm0); 6612 bsfq(tmp1, tmp1); 6613 addq(result, tmp1); 6614 shrq(result); 6615 jmp(DONE); 6616 } 6617 6618 bind(VECTOR16_NOT_EQUAL); 6619 if (UseAVX >= 2) { 6620 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 6621 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 6622 pxor(rymm0, rymm2); 6623 } else { 6624 pcmpeqb(rymm2, rymm2); 6625 pxor(rymm0, rymm1); 6626 pcmpeqb(rymm0, rymm1); 6627 pxor(rymm0, rymm2); 6628 } 6629 pmovmskb(tmp1, rymm0); 6630 bsfq(tmp1, tmp1); 6631 addq(result, tmp1); 6632 shrq(result); 6633 jmpb(DONE); 6634 6635 bind(VECTOR8_NOT_EQUAL); 6636 bind(VECTOR4_NOT_EQUAL); 6637 bsfq(tmp1, tmp1); 6638 shrq(tmp1, 3); 6639 addq(result, tmp1); 6640 bind(BYTES_NOT_EQUAL); 6641 shrq(result); 6642 jmpb(DONE); 6643 6644 bind(SAME_TILL_END); 6645 mov64(result, -1); 6646 6647 bind(DONE); 6648 } 6649 6650 //Helper functions for square_to_len() 6651 6652 /** 6653 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 6654 * Preserves x and z and modifies rest of the registers. 6655 */ 6656 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6657 // Perform square and right shift by 1 6658 // Handle odd xlen case first, then for even xlen do the following 6659 // jlong carry = 0; 6660 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 6661 // huge_128 product = x[j:j+1] * x[j:j+1]; 6662 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 6663 // z[i+2:i+3] = (jlong)(product >>> 1); 6664 // carry = (jlong)product; 6665 // } 6666 6667 xorq(tmp5, tmp5); // carry 6668 xorq(rdxReg, rdxReg); 6669 xorl(tmp1, tmp1); // index for x 6670 xorl(tmp4, tmp4); // index for z 6671 6672 Label L_first_loop, L_first_loop_exit; 6673 6674 testl(xlen, 1); 6675 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 6676 6677 // Square and right shift by 1 the odd element using 32 bit multiply 6678 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 6679 imulq(raxReg, raxReg); 6680 shrq(raxReg, 1); 6681 adcq(tmp5, 0); 6682 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 6683 incrementl(tmp1); 6684 addl(tmp4, 2); 6685 6686 // Square and right shift by 1 the rest using 64 bit multiply 6687 bind(L_first_loop); 6688 cmpptr(tmp1, xlen); 6689 jccb(Assembler::equal, L_first_loop_exit); 6690 6691 // Square 6692 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 6693 rorq(raxReg, 32); // convert big-endian to little-endian 6694 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 6695 6696 // Right shift by 1 and save carry 6697 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 6698 rcrq(rdxReg, 1); 6699 rcrq(raxReg, 1); 6700 adcq(tmp5, 0); 6701 6702 // Store result in z 6703 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 6704 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 6705 6706 // Update indices for x and z 6707 addl(tmp1, 2); 6708 addl(tmp4, 4); 6709 jmp(L_first_loop); 6710 6711 bind(L_first_loop_exit); 6712 } 6713 6714 6715 /** 6716 * Perform the following multiply add operation using BMI2 instructions 6717 * carry:sum = sum + op1*op2 + carry 6718 * op2 should be in rdx 6719 * op2 is preserved, all other registers are modified 6720 */ 6721 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 6722 // assert op2 is rdx 6723 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 6724 addq(sum, carry); 6725 adcq(tmp2, 0); 6726 addq(sum, op1); 6727 adcq(tmp2, 0); 6728 movq(carry, tmp2); 6729 } 6730 6731 /** 6732 * Perform the following multiply add operation: 6733 * carry:sum = sum + op1*op2 + carry 6734 * Preserves op1, op2 and modifies rest of registers 6735 */ 6736 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 6737 // rdx:rax = op1 * op2 6738 movq(raxReg, op2); 6739 mulq(op1); 6740 6741 // rdx:rax = sum + carry + rdx:rax 6742 addq(sum, carry); 6743 adcq(rdxReg, 0); 6744 addq(sum, raxReg); 6745 adcq(rdxReg, 0); 6746 6747 // carry:sum = rdx:sum 6748 movq(carry, rdxReg); 6749 } 6750 6751 /** 6752 * Add 64 bit long carry into z[] with carry propagation. 6753 * Preserves z and carry register values and modifies rest of registers. 6754 * 6755 */ 6756 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 6757 Label L_fourth_loop, L_fourth_loop_exit; 6758 6759 movl(tmp1, 1); 6760 subl(zlen, 2); 6761 addq(Address(z, zlen, Address::times_4, 0), carry); 6762 6763 bind(L_fourth_loop); 6764 jccb(Assembler::carryClear, L_fourth_loop_exit); 6765 subl(zlen, 2); 6766 jccb(Assembler::negative, L_fourth_loop_exit); 6767 addq(Address(z, zlen, Address::times_4, 0), tmp1); 6768 jmp(L_fourth_loop); 6769 bind(L_fourth_loop_exit); 6770 } 6771 6772 /** 6773 * Shift z[] left by 1 bit. 6774 * Preserves x, len, z and zlen registers and modifies rest of the registers. 6775 * 6776 */ 6777 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 6778 6779 Label L_fifth_loop, L_fifth_loop_exit; 6780 6781 // Fifth loop 6782 // Perform primitiveLeftShift(z, zlen, 1) 6783 6784 const Register prev_carry = tmp1; 6785 const Register new_carry = tmp4; 6786 const Register value = tmp2; 6787 const Register zidx = tmp3; 6788 6789 // int zidx, carry; 6790 // long value; 6791 // carry = 0; 6792 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 6793 // (carry:value) = (z[i] << 1) | carry ; 6794 // z[i] = value; 6795 // } 6796 6797 movl(zidx, zlen); 6798 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 6799 6800 bind(L_fifth_loop); 6801 decl(zidx); // Use decl to preserve carry flag 6802 decl(zidx); 6803 jccb(Assembler::negative, L_fifth_loop_exit); 6804 6805 if (UseBMI2Instructions) { 6806 movq(value, Address(z, zidx, Address::times_4, 0)); 6807 rclq(value, 1); 6808 rorxq(value, value, 32); 6809 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 6810 } 6811 else { 6812 // clear new_carry 6813 xorl(new_carry, new_carry); 6814 6815 // Shift z[i] by 1, or in previous carry and save new carry 6816 movq(value, Address(z, zidx, Address::times_4, 0)); 6817 shlq(value, 1); 6818 adcl(new_carry, 0); 6819 6820 orq(value, prev_carry); 6821 rorq(value, 0x20); 6822 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 6823 6824 // Set previous carry = new carry 6825 movl(prev_carry, new_carry); 6826 } 6827 jmp(L_fifth_loop); 6828 6829 bind(L_fifth_loop_exit); 6830 } 6831 6832 6833 /** 6834 * Code for BigInteger::squareToLen() intrinsic 6835 * 6836 * rdi: x 6837 * rsi: len 6838 * r8: z 6839 * rcx: zlen 6840 * r12: tmp1 6841 * r13: tmp2 6842 * r14: tmp3 6843 * r15: tmp4 6844 * rbx: tmp5 6845 * 6846 */ 6847 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6848 6849 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply; 6850 push(tmp1); 6851 push(tmp2); 6852 push(tmp3); 6853 push(tmp4); 6854 push(tmp5); 6855 6856 // First loop 6857 // Store the squares, right shifted one bit (i.e., divided by 2). 6858 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 6859 6860 // Add in off-diagonal sums. 6861 // 6862 // Second, third (nested) and fourth loops. 6863 // zlen +=2; 6864 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 6865 // carry = 0; 6866 // long op2 = x[xidx:xidx+1]; 6867 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 6868 // k -= 2; 6869 // long op1 = x[j:j+1]; 6870 // long sum = z[k:k+1]; 6871 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 6872 // z[k:k+1] = sum; 6873 // } 6874 // add_one_64(z, k, carry, tmp_regs); 6875 // } 6876 6877 const Register carry = tmp5; 6878 const Register sum = tmp3; 6879 const Register op1 = tmp4; 6880 Register op2 = tmp2; 6881 6882 push(zlen); 6883 push(len); 6884 addl(zlen,2); 6885 bind(L_second_loop); 6886 xorq(carry, carry); 6887 subl(zlen, 4); 6888 subl(len, 2); 6889 push(zlen); 6890 push(len); 6891 cmpl(len, 0); 6892 jccb(Assembler::lessEqual, L_second_loop_exit); 6893 6894 // Multiply an array by one 64 bit long. 6895 if (UseBMI2Instructions) { 6896 op2 = rdxReg; 6897 movq(op2, Address(x, len, Address::times_4, 0)); 6898 rorxq(op2, op2, 32); 6899 } 6900 else { 6901 movq(op2, Address(x, len, Address::times_4, 0)); 6902 rorq(op2, 32); 6903 } 6904 6905 bind(L_third_loop); 6906 decrementl(len); 6907 jccb(Assembler::negative, L_third_loop_exit); 6908 decrementl(len); 6909 jccb(Assembler::negative, L_last_x); 6910 6911 movq(op1, Address(x, len, Address::times_4, 0)); 6912 rorq(op1, 32); 6913 6914 bind(L_multiply); 6915 subl(zlen, 2); 6916 movq(sum, Address(z, zlen, Address::times_4, 0)); 6917 6918 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 6919 if (UseBMI2Instructions) { 6920 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 6921 } 6922 else { 6923 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 6924 } 6925 6926 movq(Address(z, zlen, Address::times_4, 0), sum); 6927 6928 jmp(L_third_loop); 6929 bind(L_third_loop_exit); 6930 6931 // Fourth loop 6932 // Add 64 bit long carry into z with carry propagation. 6933 // Uses offsetted zlen. 6934 add_one_64(z, zlen, carry, tmp1); 6935 6936 pop(len); 6937 pop(zlen); 6938 jmp(L_second_loop); 6939 6940 // Next infrequent code is moved outside loops. 6941 bind(L_last_x); 6942 movl(op1, Address(x, 0)); 6943 jmp(L_multiply); 6944 6945 bind(L_second_loop_exit); 6946 pop(len); 6947 pop(zlen); 6948 pop(len); 6949 pop(zlen); 6950 6951 // Fifth loop 6952 // Shift z left 1 bit. 6953 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 6954 6955 // z[zlen-1] |= x[len-1] & 1; 6956 movl(tmp3, Address(x, len, Address::times_4, -4)); 6957 andl(tmp3, 1); 6958 orl(Address(z, zlen, Address::times_4, -4), tmp3); 6959 6960 pop(tmp5); 6961 pop(tmp4); 6962 pop(tmp3); 6963 pop(tmp2); 6964 pop(tmp1); 6965 } 6966 6967 /** 6968 * Helper function for mul_add() 6969 * Multiply the in[] by int k and add to out[] starting at offset offs using 6970 * 128 bit by 32 bit multiply and return the carry in tmp5. 6971 * Only quad int aligned length of in[] is operated on in this function. 6972 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 6973 * This function preserves out, in and k registers. 6974 * len and offset point to the appropriate index in "in" & "out" correspondingly 6975 * tmp5 has the carry. 6976 * other registers are temporary and are modified. 6977 * 6978 */ 6979 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 6980 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 6981 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 6982 6983 Label L_first_loop, L_first_loop_exit; 6984 6985 movl(tmp1, len); 6986 shrl(tmp1, 2); 6987 6988 bind(L_first_loop); 6989 subl(tmp1, 1); 6990 jccb(Assembler::negative, L_first_loop_exit); 6991 6992 subl(len, 4); 6993 subl(offset, 4); 6994 6995 Register op2 = tmp2; 6996 const Register sum = tmp3; 6997 const Register op1 = tmp4; 6998 const Register carry = tmp5; 6999 7000 if (UseBMI2Instructions) { 7001 op2 = rdxReg; 7002 } 7003 7004 movq(op1, Address(in, len, Address::times_4, 8)); 7005 rorq(op1, 32); 7006 movq(sum, Address(out, offset, Address::times_4, 8)); 7007 rorq(sum, 32); 7008 if (UseBMI2Instructions) { 7009 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7010 } 7011 else { 7012 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7013 } 7014 // Store back in big endian from little endian 7015 rorq(sum, 0x20); 7016 movq(Address(out, offset, Address::times_4, 8), sum); 7017 7018 movq(op1, Address(in, len, Address::times_4, 0)); 7019 rorq(op1, 32); 7020 movq(sum, Address(out, offset, Address::times_4, 0)); 7021 rorq(sum, 32); 7022 if (UseBMI2Instructions) { 7023 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7024 } 7025 else { 7026 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7027 } 7028 // Store back in big endian from little endian 7029 rorq(sum, 0x20); 7030 movq(Address(out, offset, Address::times_4, 0), sum); 7031 7032 jmp(L_first_loop); 7033 bind(L_first_loop_exit); 7034 } 7035 7036 /** 7037 * Code for BigInteger::mulAdd() intrinsic 7038 * 7039 * rdi: out 7040 * rsi: in 7041 * r11: offs (out.length - offset) 7042 * rcx: len 7043 * r8: k 7044 * r12: tmp1 7045 * r13: tmp2 7046 * r14: tmp3 7047 * r15: tmp4 7048 * rbx: tmp5 7049 * Multiply the in[] by word k and add to out[], return the carry in rax 7050 */ 7051 void MacroAssembler::mul_add(Register out, Register in, Register offs, 7052 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 7053 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 7054 7055 Label L_carry, L_last_in, L_done; 7056 7057 // carry = 0; 7058 // for (int j=len-1; j >= 0; j--) { 7059 // long product = (in[j] & LONG_MASK) * kLong + 7060 // (out[offs] & LONG_MASK) + carry; 7061 // out[offs--] = (int)product; 7062 // carry = product >>> 32; 7063 // } 7064 // 7065 push(tmp1); 7066 push(tmp2); 7067 push(tmp3); 7068 push(tmp4); 7069 push(tmp5); 7070 7071 Register op2 = tmp2; 7072 const Register sum = tmp3; 7073 const Register op1 = tmp4; 7074 const Register carry = tmp5; 7075 7076 if (UseBMI2Instructions) { 7077 op2 = rdxReg; 7078 movl(op2, k); 7079 } 7080 else { 7081 movl(op2, k); 7082 } 7083 7084 xorq(carry, carry); 7085 7086 //First loop 7087 7088 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 7089 //The carry is in tmp5 7090 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 7091 7092 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 7093 decrementl(len); 7094 jccb(Assembler::negative, L_carry); 7095 decrementl(len); 7096 jccb(Assembler::negative, L_last_in); 7097 7098 movq(op1, Address(in, len, Address::times_4, 0)); 7099 rorq(op1, 32); 7100 7101 subl(offs, 2); 7102 movq(sum, Address(out, offs, Address::times_4, 0)); 7103 rorq(sum, 32); 7104 7105 if (UseBMI2Instructions) { 7106 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 7107 } 7108 else { 7109 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 7110 } 7111 7112 // Store back in big endian from little endian 7113 rorq(sum, 0x20); 7114 movq(Address(out, offs, Address::times_4, 0), sum); 7115 7116 testl(len, len); 7117 jccb(Assembler::zero, L_carry); 7118 7119 //Multiply the last in[] entry, if any 7120 bind(L_last_in); 7121 movl(op1, Address(in, 0)); 7122 movl(sum, Address(out, offs, Address::times_4, -4)); 7123 7124 movl(raxReg, k); 7125 mull(op1); //tmp4 * eax -> edx:eax 7126 addl(sum, carry); 7127 adcl(rdxReg, 0); 7128 addl(sum, raxReg); 7129 adcl(rdxReg, 0); 7130 movl(carry, rdxReg); 7131 7132 movl(Address(out, offs, Address::times_4, -4), sum); 7133 7134 bind(L_carry); 7135 //return tmp5/carry as carry in rax 7136 movl(rax, carry); 7137 7138 bind(L_done); 7139 pop(tmp5); 7140 pop(tmp4); 7141 pop(tmp3); 7142 pop(tmp2); 7143 pop(tmp1); 7144 } 7145 #endif 7146 7147 /** 7148 * Emits code to update CRC-32 with a byte value according to constants in table 7149 * 7150 * @param [in,out]crc Register containing the crc. 7151 * @param [in]val Register containing the byte to fold into the CRC. 7152 * @param [in]table Register containing the table of crc constants. 7153 * 7154 * uint32_t crc; 7155 * val = crc_table[(val ^ crc) & 0xFF]; 7156 * crc = val ^ (crc >> 8); 7157 * 7158 */ 7159 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 7160 xorl(val, crc); 7161 andl(val, 0xFF); 7162 shrl(crc, 8); // unsigned shift 7163 xorl(crc, Address(table, val, Address::times_4, 0)); 7164 } 7165 7166 /** 7167 * Fold 128-bit data chunk 7168 */ 7169 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 7170 if (UseAVX > 0) { 7171 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 7172 vpclmulldq(xcrc, xK, xcrc); // [63:0] 7173 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 7174 pxor(xcrc, xtmp); 7175 } else { 7176 movdqa(xtmp, xcrc); 7177 pclmulhdq(xtmp, xK); // [123:64] 7178 pclmulldq(xcrc, xK); // [63:0] 7179 pxor(xcrc, xtmp); 7180 movdqu(xtmp, Address(buf, offset)); 7181 pxor(xcrc, xtmp); 7182 } 7183 } 7184 7185 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 7186 if (UseAVX > 0) { 7187 vpclmulhdq(xtmp, xK, xcrc); 7188 vpclmulldq(xcrc, xK, xcrc); 7189 pxor(xcrc, xbuf); 7190 pxor(xcrc, xtmp); 7191 } else { 7192 movdqa(xtmp, xcrc); 7193 pclmulhdq(xtmp, xK); 7194 pclmulldq(xcrc, xK); 7195 pxor(xcrc, xbuf); 7196 pxor(xcrc, xtmp); 7197 } 7198 } 7199 7200 /** 7201 * 8-bit folds to compute 32-bit CRC 7202 * 7203 * uint64_t xcrc; 7204 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 7205 */ 7206 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 7207 movdl(tmp, xcrc); 7208 andl(tmp, 0xFF); 7209 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 7210 psrldq(xcrc, 1); // unsigned shift one byte 7211 pxor(xcrc, xtmp); 7212 } 7213 7214 /** 7215 * uint32_t crc; 7216 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 7217 */ 7218 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 7219 movl(tmp, crc); 7220 andl(tmp, 0xFF); 7221 shrl(crc, 8); 7222 xorl(crc, Address(table, tmp, Address::times_4, 0)); 7223 } 7224 7225 /** 7226 * @param crc register containing existing CRC (32-bit) 7227 * @param buf register pointing to input byte buffer (byte*) 7228 * @param len register containing number of bytes 7229 * @param table register that will contain address of CRC table 7230 * @param tmp scratch register 7231 */ 7232 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 7233 assert_different_registers(crc, buf, len, table, tmp, rax); 7234 7235 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 7236 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 7237 7238 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 7239 // context for the registers used, where all instructions below are using 128-bit mode 7240 // On EVEX without VL and BW, these instructions will all be AVX. 7241 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 7242 notl(crc); // ~crc 7243 cmpl(len, 16); 7244 jcc(Assembler::less, L_tail); 7245 7246 // Align buffer to 16 bytes 7247 movl(tmp, buf); 7248 andl(tmp, 0xF); 7249 jccb(Assembler::zero, L_aligned); 7250 subl(tmp, 16); 7251 addl(len, tmp); 7252 7253 align(4); 7254 BIND(L_align_loop); 7255 movsbl(rax, Address(buf, 0)); // load byte with sign extension 7256 update_byte_crc32(crc, rax, table); 7257 increment(buf); 7258 incrementl(tmp); 7259 jccb(Assembler::less, L_align_loop); 7260 7261 BIND(L_aligned); 7262 movl(tmp, len); // save 7263 shrl(len, 4); 7264 jcc(Assembler::zero, L_tail_restore); 7265 7266 // Fold crc into first bytes of vector 7267 movdqa(xmm1, Address(buf, 0)); 7268 movdl(rax, xmm1); 7269 xorl(crc, rax); 7270 if (VM_Version::supports_sse4_1()) { 7271 pinsrd(xmm1, crc, 0); 7272 } else { 7273 pinsrw(xmm1, crc, 0); 7274 shrl(crc, 16); 7275 pinsrw(xmm1, crc, 1); 7276 } 7277 addptr(buf, 16); 7278 subl(len, 4); // len > 0 7279 jcc(Assembler::less, L_fold_tail); 7280 7281 movdqa(xmm2, Address(buf, 0)); 7282 movdqa(xmm3, Address(buf, 16)); 7283 movdqa(xmm4, Address(buf, 32)); 7284 addptr(buf, 48); 7285 subl(len, 3); 7286 jcc(Assembler::lessEqual, L_fold_512b); 7287 7288 // Fold total 512 bits of polynomial on each iteration, 7289 // 128 bits per each of 4 parallel streams. 7290 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 7291 7292 align32(); 7293 BIND(L_fold_512b_loop); 7294 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 7295 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 7296 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 7297 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 7298 addptr(buf, 64); 7299 subl(len, 4); 7300 jcc(Assembler::greater, L_fold_512b_loop); 7301 7302 // Fold 512 bits to 128 bits. 7303 BIND(L_fold_512b); 7304 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 7305 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 7306 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 7307 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 7308 7309 // Fold the rest of 128 bits data chunks 7310 BIND(L_fold_tail); 7311 addl(len, 3); 7312 jccb(Assembler::lessEqual, L_fold_128b); 7313 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 7314 7315 BIND(L_fold_tail_loop); 7316 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 7317 addptr(buf, 16); 7318 decrementl(len); 7319 jccb(Assembler::greater, L_fold_tail_loop); 7320 7321 // Fold 128 bits in xmm1 down into 32 bits in crc register. 7322 BIND(L_fold_128b); 7323 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 7324 if (UseAVX > 0) { 7325 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 7326 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 7327 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 7328 } else { 7329 movdqa(xmm2, xmm0); 7330 pclmulqdq(xmm2, xmm1, 0x1); 7331 movdqa(xmm3, xmm0); 7332 pand(xmm3, xmm2); 7333 pclmulqdq(xmm0, xmm3, 0x1); 7334 } 7335 psrldq(xmm1, 8); 7336 psrldq(xmm2, 4); 7337 pxor(xmm0, xmm1); 7338 pxor(xmm0, xmm2); 7339 7340 // 8 8-bit folds to compute 32-bit CRC. 7341 for (int j = 0; j < 4; j++) { 7342 fold_8bit_crc32(xmm0, table, xmm1, rax); 7343 } 7344 movdl(crc, xmm0); // mov 32 bits to general register 7345 for (int j = 0; j < 4; j++) { 7346 fold_8bit_crc32(crc, table, rax); 7347 } 7348 7349 BIND(L_tail_restore); 7350 movl(len, tmp); // restore 7351 BIND(L_tail); 7352 andl(len, 0xf); 7353 jccb(Assembler::zero, L_exit); 7354 7355 // Fold the rest of bytes 7356 align(4); 7357 BIND(L_tail_loop); 7358 movsbl(rax, Address(buf, 0)); // load byte with sign extension 7359 update_byte_crc32(crc, rax, table); 7360 increment(buf); 7361 decrementl(len); 7362 jccb(Assembler::greater, L_tail_loop); 7363 7364 BIND(L_exit); 7365 notl(crc); // ~c 7366 } 7367 7368 #ifdef _LP64 7369 // Helper function for AVX 512 CRC32 7370 // Fold 512-bit data chunks 7371 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, 7372 Register pos, int offset) { 7373 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit); 7374 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64] 7375 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0] 7376 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */); 7377 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */); 7378 } 7379 7380 // Helper function for AVX 512 CRC32 7381 // Compute CRC32 for < 256B buffers 7382 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos, 7383 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop, 7384 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) { 7385 7386 Label L_less_than_32, L_exact_16_left, L_less_than_16_left; 7387 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left; 7388 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2; 7389 7390 // check if there is enough buffer to be able to fold 16B at a time 7391 cmpl(len, 32); 7392 jcc(Assembler::less, L_less_than_32); 7393 7394 // if there is, load the constants 7395 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10 7396 movdl(xmm0, crc); // get the initial crc value 7397 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext 7398 pxor(xmm7, xmm0); 7399 7400 // update the buffer pointer 7401 addl(pos, 16); 7402 //update the counter.subtract 32 instead of 16 to save one instruction from the loop 7403 subl(len, 32); 7404 jmp(L_16B_reduction_loop); 7405 7406 bind(L_less_than_32); 7407 //mov initial crc to the return value. this is necessary for zero - length buffers. 7408 movl(rax, crc); 7409 testl(len, len); 7410 jcc(Assembler::equal, L_cleanup); 7411 7412 movdl(xmm0, crc); //get the initial crc value 7413 7414 cmpl(len, 16); 7415 jcc(Assembler::equal, L_exact_16_left); 7416 jcc(Assembler::less, L_less_than_16_left); 7417 7418 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext 7419 pxor(xmm7, xmm0); //xor the initial crc value 7420 addl(pos, 16); 7421 subl(len, 16); 7422 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10 7423 jmp(L_get_last_two_xmms); 7424 7425 bind(L_less_than_16_left); 7426 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first. 7427 pxor(xmm1, xmm1); 7428 movptr(tmp1, rsp); 7429 movdqu(Address(tmp1, 0 * 16), xmm1); 7430 7431 cmpl(len, 4); 7432 jcc(Assembler::less, L_only_less_than_4); 7433 7434 //backup the counter value 7435 movl(tmp2, len); 7436 cmpl(len, 8); 7437 jcc(Assembler::less, L_less_than_8_left); 7438 7439 //load 8 Bytes 7440 movq(rax, Address(buf, pos, Address::times_1, 0 * 16)); 7441 movq(Address(tmp1, 0 * 16), rax); 7442 addptr(tmp1, 8); 7443 subl(len, 8); 7444 addl(pos, 8); 7445 7446 bind(L_less_than_8_left); 7447 cmpl(len, 4); 7448 jcc(Assembler::less, L_less_than_4_left); 7449 7450 //load 4 Bytes 7451 movl(rax, Address(buf, pos, Address::times_1, 0)); 7452 movl(Address(tmp1, 0 * 16), rax); 7453 addptr(tmp1, 4); 7454 subl(len, 4); 7455 addl(pos, 4); 7456 7457 bind(L_less_than_4_left); 7458 cmpl(len, 2); 7459 jcc(Assembler::less, L_less_than_2_left); 7460 7461 // load 2 Bytes 7462 movw(rax, Address(buf, pos, Address::times_1, 0)); 7463 movl(Address(tmp1, 0 * 16), rax); 7464 addptr(tmp1, 2); 7465 subl(len, 2); 7466 addl(pos, 2); 7467 7468 bind(L_less_than_2_left); 7469 cmpl(len, 1); 7470 jcc(Assembler::less, L_zero_left); 7471 7472 // load 1 Byte 7473 movb(rax, Address(buf, pos, Address::times_1, 0)); 7474 movb(Address(tmp1, 0 * 16), rax); 7475 7476 bind(L_zero_left); 7477 movdqu(xmm7, Address(rsp, 0)); 7478 pxor(xmm7, xmm0); //xor the initial crc value 7479 7480 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); 7481 movdqu(xmm0, Address(rax, tmp2)); 7482 pshufb(xmm7, xmm0); 7483 jmp(L_128_done); 7484 7485 bind(L_exact_16_left); 7486 movdqu(xmm7, Address(buf, pos, Address::times_1, 0)); 7487 pxor(xmm7, xmm0); //xor the initial crc value 7488 jmp(L_128_done); 7489 7490 bind(L_only_less_than_4); 7491 cmpl(len, 3); 7492 jcc(Assembler::less, L_only_less_than_3); 7493 7494 // load 3 Bytes 7495 movb(rax, Address(buf, pos, Address::times_1, 0)); 7496 movb(Address(tmp1, 0), rax); 7497 7498 movb(rax, Address(buf, pos, Address::times_1, 1)); 7499 movb(Address(tmp1, 1), rax); 7500 7501 movb(rax, Address(buf, pos, Address::times_1, 2)); 7502 movb(Address(tmp1, 2), rax); 7503 7504 movdqu(xmm7, Address(rsp, 0)); 7505 pxor(xmm7, xmm0); //xor the initial crc value 7506 7507 pslldq(xmm7, 0x5); 7508 jmp(L_barrett); 7509 bind(L_only_less_than_3); 7510 cmpl(len, 2); 7511 jcc(Assembler::less, L_only_less_than_2); 7512 7513 // load 2 Bytes 7514 movb(rax, Address(buf, pos, Address::times_1, 0)); 7515 movb(Address(tmp1, 0), rax); 7516 7517 movb(rax, Address(buf, pos, Address::times_1, 1)); 7518 movb(Address(tmp1, 1), rax); 7519 7520 movdqu(xmm7, Address(rsp, 0)); 7521 pxor(xmm7, xmm0); //xor the initial crc value 7522 7523 pslldq(xmm7, 0x6); 7524 jmp(L_barrett); 7525 7526 bind(L_only_less_than_2); 7527 //load 1 Byte 7528 movb(rax, Address(buf, pos, Address::times_1, 0)); 7529 movb(Address(tmp1, 0), rax); 7530 7531 movdqu(xmm7, Address(rsp, 0)); 7532 pxor(xmm7, xmm0); //xor the initial crc value 7533 7534 pslldq(xmm7, 0x7); 7535 } 7536 7537 /** 7538 * Compute CRC32 using AVX512 instructions 7539 * param crc register containing existing CRC (32-bit) 7540 * param buf register pointing to input byte buffer (byte*) 7541 * param len register containing number of bytes 7542 * param table address of crc or crc32c table 7543 * param tmp1 scratch register 7544 * param tmp2 scratch register 7545 * return rax result register 7546 * 7547 * This routine is identical for crc32c with the exception of the precomputed constant 7548 * table which will be passed as the table argument. The calculation steps are 7549 * the same for both variants. 7550 */ 7551 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) { 7552 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12); 7553 7554 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 7555 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 7556 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop; 7557 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop; 7558 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup; 7559 7560 const Register pos = r12; 7561 push(r12); 7562 subptr(rsp, 16 * 2 + 8); 7563 7564 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 7565 // context for the registers used, where all instructions below are using 128-bit mode 7566 // On EVEX without VL and BW, these instructions will all be AVX. 7567 movl(pos, 0); 7568 7569 // check if smaller than 256B 7570 cmpl(len, 256); 7571 jcc(Assembler::less, L_less_than_256); 7572 7573 // load the initial crc value 7574 movdl(xmm10, crc); 7575 7576 // receive the initial 64B data, xor the initial crc value 7577 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit); 7578 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit); 7579 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit); 7580 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4 7581 7582 subl(len, 256); 7583 cmpl(len, 256); 7584 jcc(Assembler::less, L_fold_128_B_loop); 7585 7586 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit); 7587 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit); 7588 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2 7589 subl(len, 256); 7590 7591 bind(L_fold_256_B_loop); 7592 addl(pos, 256); 7593 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64); 7594 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64); 7595 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64); 7596 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64); 7597 7598 subl(len, 256); 7599 jcc(Assembler::greaterEqual, L_fold_256_B_loop); 7600 7601 // Fold 256 into 128 7602 addl(pos, 256); 7603 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit); 7604 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit); 7605 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC 7606 7607 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit); 7608 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit); 7609 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC 7610 7611 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit); 7612 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit); 7613 7614 addl(len, 128); 7615 jmp(L_fold_128_B_register); 7616 7617 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop 7618 // loop will fold 128B at a time until we have 128 + y Bytes of buffer 7619 7620 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel 7621 bind(L_fold_128_B_loop); 7622 addl(pos, 128); 7623 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64); 7624 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64); 7625 7626 subl(len, 128); 7627 jcc(Assembler::greaterEqual, L_fold_128_B_loop); 7628 7629 addl(pos, 128); 7630 7631 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128 7632 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7 7633 bind(L_fold_128_B_register); 7634 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16 7635 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0 7636 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit); 7637 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit); 7638 // save last that has no multiplicand 7639 vextracti64x2(xmm7, xmm4, 3); 7640 7641 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit); 7642 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit); 7643 // Needed later in reduction loop 7644 movdqu(xmm10, Address(table, 1 * 16)); 7645 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC 7646 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC 7647 7648 // Swap 1,0,3,2 - 01 00 11 10 7649 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit); 7650 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit); 7651 vextracti128(xmm5, xmm8, 1); 7652 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit); 7653 7654 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop 7655 // instead of a cmp instruction, we use the negative flag with the jl instruction 7656 addl(len, 128 - 16); 7657 jcc(Assembler::less, L_final_reduction_for_128); 7658 7659 bind(L_16B_reduction_loop); 7660 vpclmulqdq(xmm8, xmm7, xmm10, 0x01); 7661 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7662 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); 7663 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16)); 7664 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7665 addl(pos, 16); 7666 subl(len, 16); 7667 jcc(Assembler::greaterEqual, L_16B_reduction_loop); 7668 7669 bind(L_final_reduction_for_128); 7670 addl(len, 16); 7671 jcc(Assembler::equal, L_128_done); 7672 7673 bind(L_get_last_two_xmms); 7674 movdqu(xmm2, xmm7); 7675 addl(pos, len); 7676 movdqu(xmm1, Address(buf, pos, Address::times_1, -16)); 7677 subl(pos, len); 7678 7679 // get rid of the extra data that was loaded before 7680 // load the shift constant 7681 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr())); 7682 movdqu(xmm0, Address(rax, len)); 7683 addl(rax, len); 7684 7685 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7686 //Change mask to 512 7687 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2); 7688 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit); 7689 7690 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit); 7691 vpclmulqdq(xmm8, xmm7, xmm10, 0x01); 7692 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7693 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit); 7694 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit); 7695 7696 bind(L_128_done); 7697 // compute crc of a 128-bit value 7698 movdqu(xmm10, Address(table, 3 * 16)); 7699 movdqu(xmm0, xmm7); 7700 7701 // 64b fold 7702 vpclmulqdq(xmm7, xmm7, xmm10, 0x0); 7703 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit); 7704 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7705 7706 // 32b fold 7707 movdqu(xmm0, xmm7); 7708 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit); 7709 vpclmulqdq(xmm7, xmm7, xmm10, 0x10); 7710 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit); 7711 jmp(L_barrett); 7712 7713 bind(L_less_than_256); 7714 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup); 7715 7716 //barrett reduction 7717 bind(L_barrett); 7718 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2); 7719 movdqu(xmm1, xmm7); 7720 movdqu(xmm2, xmm7); 7721 movdqu(xmm10, Address(table, 4 * 16)); 7722 7723 pclmulqdq(xmm7, xmm10, 0x0); 7724 pxor(xmm7, xmm2); 7725 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2); 7726 movdqu(xmm2, xmm7); 7727 pclmulqdq(xmm7, xmm10, 0x10); 7728 pxor(xmm7, xmm2); 7729 pxor(xmm7, xmm1); 7730 pextrd(crc, xmm7, 2); 7731 7732 bind(L_cleanup); 7733 addptr(rsp, 16 * 2 + 8); 7734 pop(r12); 7735 } 7736 7737 // S. Gueron / Information Processing Letters 112 (2012) 184 7738 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 7739 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 7740 // Output: the 64-bit carry-less product of B * CONST 7741 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 7742 Register tmp1, Register tmp2, Register tmp3) { 7743 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 7744 if (n > 0) { 7745 addq(tmp3, n * 256 * 8); 7746 } 7747 // Q1 = TABLEExt[n][B & 0xFF]; 7748 movl(tmp1, in); 7749 andl(tmp1, 0x000000FF); 7750 shll(tmp1, 3); 7751 addq(tmp1, tmp3); 7752 movq(tmp1, Address(tmp1, 0)); 7753 7754 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 7755 movl(tmp2, in); 7756 shrl(tmp2, 8); 7757 andl(tmp2, 0x000000FF); 7758 shll(tmp2, 3); 7759 addq(tmp2, tmp3); 7760 movq(tmp2, Address(tmp2, 0)); 7761 7762 shlq(tmp2, 8); 7763 xorq(tmp1, tmp2); 7764 7765 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 7766 movl(tmp2, in); 7767 shrl(tmp2, 16); 7768 andl(tmp2, 0x000000FF); 7769 shll(tmp2, 3); 7770 addq(tmp2, tmp3); 7771 movq(tmp2, Address(tmp2, 0)); 7772 7773 shlq(tmp2, 16); 7774 xorq(tmp1, tmp2); 7775 7776 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 7777 shrl(in, 24); 7778 andl(in, 0x000000FF); 7779 shll(in, 3); 7780 addq(in, tmp3); 7781 movq(in, Address(in, 0)); 7782 7783 shlq(in, 24); 7784 xorq(in, tmp1); 7785 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 7786 } 7787 7788 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 7789 Register in_out, 7790 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 7791 XMMRegister w_xtmp2, 7792 Register tmp1, 7793 Register n_tmp2, Register n_tmp3) { 7794 if (is_pclmulqdq_supported) { 7795 movdl(w_xtmp1, in_out); // modified blindly 7796 7797 movl(tmp1, const_or_pre_comp_const_index); 7798 movdl(w_xtmp2, tmp1); 7799 pclmulqdq(w_xtmp1, w_xtmp2, 0); 7800 7801 movdq(in_out, w_xtmp1); 7802 } else { 7803 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 7804 } 7805 } 7806 7807 // Recombination Alternative 2: No bit-reflections 7808 // T1 = (CRC_A * U1) << 1 7809 // T2 = (CRC_B * U2) << 1 7810 // C1 = T1 >> 32 7811 // C2 = T2 >> 32 7812 // T1 = T1 & 0xFFFFFFFF 7813 // T2 = T2 & 0xFFFFFFFF 7814 // T1 = CRC32(0, T1) 7815 // T2 = CRC32(0, T2) 7816 // C1 = C1 ^ T1 7817 // C2 = C2 ^ T2 7818 // CRC = C1 ^ C2 ^ CRC_C 7819 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 7820 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7821 Register tmp1, Register tmp2, 7822 Register n_tmp3) { 7823 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7824 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7825 shlq(in_out, 1); 7826 movl(tmp1, in_out); 7827 shrq(in_out, 32); 7828 xorl(tmp2, tmp2); 7829 crc32(tmp2, tmp1, 4); 7830 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 7831 shlq(in1, 1); 7832 movl(tmp1, in1); 7833 shrq(in1, 32); 7834 xorl(tmp2, tmp2); 7835 crc32(tmp2, tmp1, 4); 7836 xorl(in1, tmp2); 7837 xorl(in_out, in1); 7838 xorl(in_out, in2); 7839 } 7840 7841 // Set N to predefined value 7842 // Subtract from a length of a buffer 7843 // execute in a loop: 7844 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 7845 // for i = 1 to N do 7846 // CRC_A = CRC32(CRC_A, A[i]) 7847 // CRC_B = CRC32(CRC_B, B[i]) 7848 // CRC_C = CRC32(CRC_C, C[i]) 7849 // end for 7850 // Recombine 7851 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 7852 Register in_out1, Register in_out2, Register in_out3, 7853 Register tmp1, Register tmp2, Register tmp3, 7854 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7855 Register tmp4, Register tmp5, 7856 Register n_tmp6) { 7857 Label L_processPartitions; 7858 Label L_processPartition; 7859 Label L_exit; 7860 7861 bind(L_processPartitions); 7862 cmpl(in_out1, 3 * size); 7863 jcc(Assembler::less, L_exit); 7864 xorl(tmp1, tmp1); 7865 xorl(tmp2, tmp2); 7866 movq(tmp3, in_out2); 7867 addq(tmp3, size); 7868 7869 bind(L_processPartition); 7870 crc32(in_out3, Address(in_out2, 0), 8); 7871 crc32(tmp1, Address(in_out2, size), 8); 7872 crc32(tmp2, Address(in_out2, size * 2), 8); 7873 addq(in_out2, 8); 7874 cmpq(in_out2, tmp3); 7875 jcc(Assembler::less, L_processPartition); 7876 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 7877 w_xtmp1, w_xtmp2, w_xtmp3, 7878 tmp4, tmp5, 7879 n_tmp6); 7880 addq(in_out2, 2 * size); 7881 subl(in_out1, 3 * size); 7882 jmp(L_processPartitions); 7883 7884 bind(L_exit); 7885 } 7886 #else 7887 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 7888 Register tmp1, Register tmp2, Register tmp3, 7889 XMMRegister xtmp1, XMMRegister xtmp2) { 7890 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 7891 if (n > 0) { 7892 addl(tmp3, n * 256 * 8); 7893 } 7894 // Q1 = TABLEExt[n][B & 0xFF]; 7895 movl(tmp1, in_out); 7896 andl(tmp1, 0x000000FF); 7897 shll(tmp1, 3); 7898 addl(tmp1, tmp3); 7899 movq(xtmp1, Address(tmp1, 0)); 7900 7901 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 7902 movl(tmp2, in_out); 7903 shrl(tmp2, 8); 7904 andl(tmp2, 0x000000FF); 7905 shll(tmp2, 3); 7906 addl(tmp2, tmp3); 7907 movq(xtmp2, Address(tmp2, 0)); 7908 7909 psllq(xtmp2, 8); 7910 pxor(xtmp1, xtmp2); 7911 7912 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 7913 movl(tmp2, in_out); 7914 shrl(tmp2, 16); 7915 andl(tmp2, 0x000000FF); 7916 shll(tmp2, 3); 7917 addl(tmp2, tmp3); 7918 movq(xtmp2, Address(tmp2, 0)); 7919 7920 psllq(xtmp2, 16); 7921 pxor(xtmp1, xtmp2); 7922 7923 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 7924 shrl(in_out, 24); 7925 andl(in_out, 0x000000FF); 7926 shll(in_out, 3); 7927 addl(in_out, tmp3); 7928 movq(xtmp2, Address(in_out, 0)); 7929 7930 psllq(xtmp2, 24); 7931 pxor(xtmp1, xtmp2); // Result in CXMM 7932 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 7933 } 7934 7935 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 7936 Register in_out, 7937 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 7938 XMMRegister w_xtmp2, 7939 Register tmp1, 7940 Register n_tmp2, Register n_tmp3) { 7941 if (is_pclmulqdq_supported) { 7942 movdl(w_xtmp1, in_out); 7943 7944 movl(tmp1, const_or_pre_comp_const_index); 7945 movdl(w_xtmp2, tmp1); 7946 pclmulqdq(w_xtmp1, w_xtmp2, 0); 7947 // Keep result in XMM since GPR is 32 bit in length 7948 } else { 7949 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 7950 } 7951 } 7952 7953 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 7954 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7955 Register tmp1, Register tmp2, 7956 Register n_tmp3) { 7957 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7958 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 7959 7960 psllq(w_xtmp1, 1); 7961 movdl(tmp1, w_xtmp1); 7962 psrlq(w_xtmp1, 32); 7963 movdl(in_out, w_xtmp1); 7964 7965 xorl(tmp2, tmp2); 7966 crc32(tmp2, tmp1, 4); 7967 xorl(in_out, tmp2); 7968 7969 psllq(w_xtmp2, 1); 7970 movdl(tmp1, w_xtmp2); 7971 psrlq(w_xtmp2, 32); 7972 movdl(in1, w_xtmp2); 7973 7974 xorl(tmp2, tmp2); 7975 crc32(tmp2, tmp1, 4); 7976 xorl(in1, tmp2); 7977 xorl(in_out, in1); 7978 xorl(in_out, in2); 7979 } 7980 7981 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 7982 Register in_out1, Register in_out2, Register in_out3, 7983 Register tmp1, Register tmp2, Register tmp3, 7984 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 7985 Register tmp4, Register tmp5, 7986 Register n_tmp6) { 7987 Label L_processPartitions; 7988 Label L_processPartition; 7989 Label L_exit; 7990 7991 bind(L_processPartitions); 7992 cmpl(in_out1, 3 * size); 7993 jcc(Assembler::less, L_exit); 7994 xorl(tmp1, tmp1); 7995 xorl(tmp2, tmp2); 7996 movl(tmp3, in_out2); 7997 addl(tmp3, size); 7998 7999 bind(L_processPartition); 8000 crc32(in_out3, Address(in_out2, 0), 4); 8001 crc32(tmp1, Address(in_out2, size), 4); 8002 crc32(tmp2, Address(in_out2, size*2), 4); 8003 crc32(in_out3, Address(in_out2, 0+4), 4); 8004 crc32(tmp1, Address(in_out2, size+4), 4); 8005 crc32(tmp2, Address(in_out2, size*2+4), 4); 8006 addl(in_out2, 8); 8007 cmpl(in_out2, tmp3); 8008 jcc(Assembler::less, L_processPartition); 8009 8010 push(tmp3); 8011 push(in_out1); 8012 push(in_out2); 8013 tmp4 = tmp3; 8014 tmp5 = in_out1; 8015 n_tmp6 = in_out2; 8016 8017 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 8018 w_xtmp1, w_xtmp2, w_xtmp3, 8019 tmp4, tmp5, 8020 n_tmp6); 8021 8022 pop(in_out2); 8023 pop(in_out1); 8024 pop(tmp3); 8025 8026 addl(in_out2, 2 * size); 8027 subl(in_out1, 3 * size); 8028 jmp(L_processPartitions); 8029 8030 bind(L_exit); 8031 } 8032 #endif //LP64 8033 8034 #ifdef _LP64 8035 // Algorithm 2: Pipelined usage of the CRC32 instruction. 8036 // Input: A buffer I of L bytes. 8037 // Output: the CRC32C value of the buffer. 8038 // Notations: 8039 // Write L = 24N + r, with N = floor (L/24). 8040 // r = L mod 24 (0 <= r < 24). 8041 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 8042 // N quadwords, and R consists of r bytes. 8043 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 8044 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 8045 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 8046 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 8047 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8048 Register tmp1, Register tmp2, Register tmp3, 8049 Register tmp4, Register tmp5, Register tmp6, 8050 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8051 bool is_pclmulqdq_supported) { 8052 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 8053 Label L_wordByWord; 8054 Label L_byteByByteProlog; 8055 Label L_byteByByte; 8056 Label L_exit; 8057 8058 if (is_pclmulqdq_supported ) { 8059 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8060 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 8061 8062 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8063 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8064 8065 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8066 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8067 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 8068 } else { 8069 const_or_pre_comp_const_index[0] = 1; 8070 const_or_pre_comp_const_index[1] = 0; 8071 8072 const_or_pre_comp_const_index[2] = 3; 8073 const_or_pre_comp_const_index[3] = 2; 8074 8075 const_or_pre_comp_const_index[4] = 5; 8076 const_or_pre_comp_const_index[5] = 4; 8077 } 8078 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8079 in2, in1, in_out, 8080 tmp1, tmp2, tmp3, 8081 w_xtmp1, w_xtmp2, w_xtmp3, 8082 tmp4, tmp5, 8083 tmp6); 8084 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8085 in2, in1, in_out, 8086 tmp1, tmp2, tmp3, 8087 w_xtmp1, w_xtmp2, w_xtmp3, 8088 tmp4, tmp5, 8089 tmp6); 8090 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8091 in2, in1, in_out, 8092 tmp1, tmp2, tmp3, 8093 w_xtmp1, w_xtmp2, w_xtmp3, 8094 tmp4, tmp5, 8095 tmp6); 8096 movl(tmp1, in2); 8097 andl(tmp1, 0x00000007); 8098 negl(tmp1); 8099 addl(tmp1, in2); 8100 addq(tmp1, in1); 8101 8102 BIND(L_wordByWord); 8103 cmpq(in1, tmp1); 8104 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8105 crc32(in_out, Address(in1, 0), 4); 8106 addq(in1, 4); 8107 jmp(L_wordByWord); 8108 8109 BIND(L_byteByByteProlog); 8110 andl(in2, 0x00000007); 8111 movl(tmp2, 1); 8112 8113 BIND(L_byteByByte); 8114 cmpl(tmp2, in2); 8115 jccb(Assembler::greater, L_exit); 8116 crc32(in_out, Address(in1, 0), 1); 8117 incq(in1); 8118 incl(tmp2); 8119 jmp(L_byteByByte); 8120 8121 BIND(L_exit); 8122 } 8123 #else 8124 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 8125 Register tmp1, Register tmp2, Register tmp3, 8126 Register tmp4, Register tmp5, Register tmp6, 8127 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 8128 bool is_pclmulqdq_supported) { 8129 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 8130 Label L_wordByWord; 8131 Label L_byteByByteProlog; 8132 Label L_byteByByte; 8133 Label L_exit; 8134 8135 if (is_pclmulqdq_supported) { 8136 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 8137 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 8138 8139 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 8140 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 8141 8142 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 8143 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 8144 } else { 8145 const_or_pre_comp_const_index[0] = 1; 8146 const_or_pre_comp_const_index[1] = 0; 8147 8148 const_or_pre_comp_const_index[2] = 3; 8149 const_or_pre_comp_const_index[3] = 2; 8150 8151 const_or_pre_comp_const_index[4] = 5; 8152 const_or_pre_comp_const_index[5] = 4; 8153 } 8154 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 8155 in2, in1, in_out, 8156 tmp1, tmp2, tmp3, 8157 w_xtmp1, w_xtmp2, w_xtmp3, 8158 tmp4, tmp5, 8159 tmp6); 8160 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 8161 in2, in1, in_out, 8162 tmp1, tmp2, tmp3, 8163 w_xtmp1, w_xtmp2, w_xtmp3, 8164 tmp4, tmp5, 8165 tmp6); 8166 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 8167 in2, in1, in_out, 8168 tmp1, tmp2, tmp3, 8169 w_xtmp1, w_xtmp2, w_xtmp3, 8170 tmp4, tmp5, 8171 tmp6); 8172 movl(tmp1, in2); 8173 andl(tmp1, 0x00000007); 8174 negl(tmp1); 8175 addl(tmp1, in2); 8176 addl(tmp1, in1); 8177 8178 BIND(L_wordByWord); 8179 cmpl(in1, tmp1); 8180 jcc(Assembler::greaterEqual, L_byteByByteProlog); 8181 crc32(in_out, Address(in1,0), 4); 8182 addl(in1, 4); 8183 jmp(L_wordByWord); 8184 8185 BIND(L_byteByByteProlog); 8186 andl(in2, 0x00000007); 8187 movl(tmp2, 1); 8188 8189 BIND(L_byteByByte); 8190 cmpl(tmp2, in2); 8191 jccb(Assembler::greater, L_exit); 8192 movb(tmp1, Address(in1, 0)); 8193 crc32(in_out, tmp1, 1); 8194 incl(in1); 8195 incl(tmp2); 8196 jmp(L_byteByByte); 8197 8198 BIND(L_exit); 8199 } 8200 #endif // LP64 8201 #undef BIND 8202 #undef BLOCK_COMMENT 8203 8204 // Compress char[] array to byte[]. 8205 // ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java 8206 // @IntrinsicCandidate 8207 // private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) { 8208 // for (int i = 0; i < len; i++) { 8209 // int c = src[srcOff++]; 8210 // if (c >>> 8 != 0) { 8211 // return 0; 8212 // } 8213 // dst[dstOff++] = (byte)c; 8214 // } 8215 // return len; 8216 // } 8217 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 8218 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8219 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8220 Register tmp5, Register result, KRegister mask1, KRegister mask2) { 8221 Label copy_chars_loop, return_length, return_zero, done; 8222 8223 // rsi: src 8224 // rdi: dst 8225 // rdx: len 8226 // rcx: tmp5 8227 // rax: result 8228 8229 // rsi holds start addr of source char[] to be compressed 8230 // rdi holds start addr of destination byte[] 8231 // rdx holds length 8232 8233 assert(len != result, ""); 8234 8235 // save length for return 8236 push(len); 8237 8238 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512 8239 VM_Version::supports_avx512vlbw() && 8240 VM_Version::supports_bmi2()) { 8241 8242 Label copy_32_loop, copy_loop_tail, below_threshold; 8243 8244 // alignment 8245 Label post_alignment; 8246 8247 // if length of the string is less than 16, handle it in an old fashioned way 8248 testl(len, -32); 8249 jcc(Assembler::zero, below_threshold); 8250 8251 // First check whether a character is compressible ( <= 0xFF). 8252 // Create mask to test for Unicode chars inside zmm vector 8253 movl(result, 0x00FF); 8254 evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit); 8255 8256 testl(len, -64); 8257 jcc(Assembler::zero, post_alignment); 8258 8259 movl(tmp5, dst); 8260 andl(tmp5, (32 - 1)); 8261 negl(tmp5); 8262 andl(tmp5, (32 - 1)); 8263 8264 // bail out when there is nothing to be done 8265 testl(tmp5, 0xFFFFFFFF); 8266 jcc(Assembler::zero, post_alignment); 8267 8268 // ~(~0 << len), where len is the # of remaining elements to process 8269 movl(result, 0xFFFFFFFF); 8270 shlxl(result, result, tmp5); 8271 notl(result); 8272 kmovdl(mask2, result); 8273 8274 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 8275 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit); 8276 ktestd(mask1, mask2); 8277 jcc(Assembler::carryClear, return_zero); 8278 8279 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit); 8280 8281 addptr(src, tmp5); 8282 addptr(src, tmp5); 8283 addptr(dst, tmp5); 8284 subl(len, tmp5); 8285 8286 bind(post_alignment); 8287 // end of alignment 8288 8289 movl(tmp5, len); 8290 andl(tmp5, (32 - 1)); // tail count (in chars) 8291 andl(len, ~(32 - 1)); // vector count (in chars) 8292 jcc(Assembler::zero, copy_loop_tail); 8293 8294 lea(src, Address(src, len, Address::times_2)); 8295 lea(dst, Address(dst, len, Address::times_1)); 8296 negptr(len); 8297 8298 bind(copy_32_loop); 8299 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit); 8300 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit); 8301 kortestdl(mask1, mask1); 8302 jcc(Assembler::carryClear, return_zero); 8303 8304 // All elements in current processed chunk are valid candidates for 8305 // compression. Write a truncated byte elements to the memory. 8306 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit); 8307 addptr(len, 32); 8308 jcc(Assembler::notZero, copy_32_loop); 8309 8310 bind(copy_loop_tail); 8311 // bail out when there is nothing to be done 8312 testl(tmp5, 0xFFFFFFFF); 8313 jcc(Assembler::zero, return_length); 8314 8315 movl(len, tmp5); 8316 8317 // ~(~0 << len), where len is the # of remaining elements to process 8318 movl(result, 0xFFFFFFFF); 8319 shlxl(result, result, len); 8320 notl(result); 8321 8322 kmovdl(mask2, result); 8323 8324 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit); 8325 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit); 8326 ktestd(mask1, mask2); 8327 jcc(Assembler::carryClear, return_zero); 8328 8329 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit); 8330 jmp(return_length); 8331 8332 bind(below_threshold); 8333 } 8334 8335 if (UseSSE42Intrinsics) { 8336 Label copy_32_loop, copy_16, copy_tail; 8337 8338 movl(result, len); 8339 8340 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 8341 8342 // vectored compression 8343 andl(len, 0xfffffff0); // vector count (in chars) 8344 andl(result, 0x0000000f); // tail count (in chars) 8345 testl(len, len); 8346 jcc(Assembler::zero, copy_16); 8347 8348 // compress 16 chars per iter 8349 movdl(tmp1Reg, tmp5); 8350 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 8351 pxor(tmp4Reg, tmp4Reg); 8352 8353 lea(src, Address(src, len, Address::times_2)); 8354 lea(dst, Address(dst, len, Address::times_1)); 8355 negptr(len); 8356 8357 bind(copy_32_loop); 8358 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 8359 por(tmp4Reg, tmp2Reg); 8360 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 8361 por(tmp4Reg, tmp3Reg); 8362 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 8363 jcc(Assembler::notZero, return_zero); 8364 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 8365 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 8366 addptr(len, 16); 8367 jcc(Assembler::notZero, copy_32_loop); 8368 8369 // compress next vector of 8 chars (if any) 8370 bind(copy_16); 8371 movl(len, result); 8372 andl(len, 0xfffffff8); // vector count (in chars) 8373 andl(result, 0x00000007); // tail count (in chars) 8374 testl(len, len); 8375 jccb(Assembler::zero, copy_tail); 8376 8377 movdl(tmp1Reg, tmp5); 8378 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 8379 pxor(tmp3Reg, tmp3Reg); 8380 8381 movdqu(tmp2Reg, Address(src, 0)); 8382 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8383 jccb(Assembler::notZero, return_zero); 8384 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 8385 movq(Address(dst, 0), tmp2Reg); 8386 addptr(src, 16); 8387 addptr(dst, 8); 8388 8389 bind(copy_tail); 8390 movl(len, result); 8391 } 8392 // compress 1 char per iter 8393 testl(len, len); 8394 jccb(Assembler::zero, return_length); 8395 lea(src, Address(src, len, Address::times_2)); 8396 lea(dst, Address(dst, len, Address::times_1)); 8397 negptr(len); 8398 8399 bind(copy_chars_loop); 8400 load_unsigned_short(result, Address(src, len, Address::times_2)); 8401 testl(result, 0xff00); // check if Unicode char 8402 jccb(Assembler::notZero, return_zero); 8403 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 8404 increment(len); 8405 jcc(Assembler::notZero, copy_chars_loop); 8406 8407 // if compression succeeded, return length 8408 bind(return_length); 8409 pop(result); 8410 jmpb(done); 8411 8412 // if compression failed, return 0 8413 bind(return_zero); 8414 xorl(result, result); 8415 addptr(rsp, wordSize); 8416 8417 bind(done); 8418 } 8419 8420 // Inflate byte[] array to char[]. 8421 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java 8422 // @IntrinsicCandidate 8423 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) { 8424 // for (int i = 0; i < len; i++) { 8425 // dst[dstOff++] = (char)(src[srcOff++] & 0xff); 8426 // } 8427 // } 8428 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 8429 XMMRegister tmp1, Register tmp2, KRegister mask) { 8430 Label copy_chars_loop, done, below_threshold, avx3_threshold; 8431 // rsi: src 8432 // rdi: dst 8433 // rdx: len 8434 // rcx: tmp2 8435 8436 // rsi holds start addr of source byte[] to be inflated 8437 // rdi holds start addr of destination char[] 8438 // rdx holds length 8439 assert_different_registers(src, dst, len, tmp2); 8440 movl(tmp2, len); 8441 if ((UseAVX > 2) && // AVX512 8442 VM_Version::supports_avx512vlbw() && 8443 VM_Version::supports_bmi2()) { 8444 8445 Label copy_32_loop, copy_tail; 8446 Register tmp3_aliased = len; 8447 8448 // if length of the string is less than 16, handle it in an old fashioned way 8449 testl(len, -16); 8450 jcc(Assembler::zero, below_threshold); 8451 8452 testl(len, -1 * AVX3Threshold); 8453 jcc(Assembler::zero, avx3_threshold); 8454 8455 // In order to use only one arithmetic operation for the main loop we use 8456 // this pre-calculation 8457 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop 8458 andl(len, -32); // vector count 8459 jccb(Assembler::zero, copy_tail); 8460 8461 lea(src, Address(src, len, Address::times_1)); 8462 lea(dst, Address(dst, len, Address::times_2)); 8463 negptr(len); 8464 8465 8466 // inflate 32 chars per iter 8467 bind(copy_32_loop); 8468 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit); 8469 evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit); 8470 addptr(len, 32); 8471 jcc(Assembler::notZero, copy_32_loop); 8472 8473 bind(copy_tail); 8474 // bail out when there is nothing to be done 8475 testl(tmp2, -1); // we don't destroy the contents of tmp2 here 8476 jcc(Assembler::zero, done); 8477 8478 // ~(~0 << length), where length is the # of remaining elements to process 8479 movl(tmp3_aliased, -1); 8480 shlxl(tmp3_aliased, tmp3_aliased, tmp2); 8481 notl(tmp3_aliased); 8482 kmovdl(mask, tmp3_aliased); 8483 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit); 8484 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit); 8485 8486 jmp(done); 8487 bind(avx3_threshold); 8488 } 8489 if (UseSSE42Intrinsics) { 8490 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail; 8491 8492 if (UseAVX > 1) { 8493 andl(tmp2, (16 - 1)); 8494 andl(len, -16); 8495 jccb(Assembler::zero, copy_new_tail); 8496 } else { 8497 andl(tmp2, 0x00000007); // tail count (in chars) 8498 andl(len, 0xfffffff8); // vector count (in chars) 8499 jccb(Assembler::zero, copy_tail); 8500 } 8501 8502 // vectored inflation 8503 lea(src, Address(src, len, Address::times_1)); 8504 lea(dst, Address(dst, len, Address::times_2)); 8505 negptr(len); 8506 8507 if (UseAVX > 1) { 8508 bind(copy_16_loop); 8509 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit); 8510 vmovdqu(Address(dst, len, Address::times_2), tmp1); 8511 addptr(len, 16); 8512 jcc(Assembler::notZero, copy_16_loop); 8513 8514 bind(below_threshold); 8515 bind(copy_new_tail); 8516 movl(len, tmp2); 8517 andl(tmp2, 0x00000007); 8518 andl(len, 0xFFFFFFF8); 8519 jccb(Assembler::zero, copy_tail); 8520 8521 pmovzxbw(tmp1, Address(src, 0)); 8522 movdqu(Address(dst, 0), tmp1); 8523 addptr(src, 8); 8524 addptr(dst, 2 * 8); 8525 8526 jmp(copy_tail, true); 8527 } 8528 8529 // inflate 8 chars per iter 8530 bind(copy_8_loop); 8531 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 8532 movdqu(Address(dst, len, Address::times_2), tmp1); 8533 addptr(len, 8); 8534 jcc(Assembler::notZero, copy_8_loop); 8535 8536 bind(copy_tail); 8537 movl(len, tmp2); 8538 8539 cmpl(len, 4); 8540 jccb(Assembler::less, copy_bytes); 8541 8542 movdl(tmp1, Address(src, 0)); // load 4 byte chars 8543 pmovzxbw(tmp1, tmp1); 8544 movq(Address(dst, 0), tmp1); 8545 subptr(len, 4); 8546 addptr(src, 4); 8547 addptr(dst, 8); 8548 8549 bind(copy_bytes); 8550 } else { 8551 bind(below_threshold); 8552 } 8553 8554 testl(len, len); 8555 jccb(Assembler::zero, done); 8556 lea(src, Address(src, len, Address::times_1)); 8557 lea(dst, Address(dst, len, Address::times_2)); 8558 negptr(len); 8559 8560 // inflate 1 char per iter 8561 bind(copy_chars_loop); 8562 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 8563 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 8564 increment(len); 8565 jcc(Assembler::notZero, copy_chars_loop); 8566 8567 bind(done); 8568 } 8569 8570 8571 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) { 8572 switch(type) { 8573 case T_BYTE: 8574 case T_BOOLEAN: 8575 evmovdqub(dst, kmask, src, false, vector_len); 8576 break; 8577 case T_CHAR: 8578 case T_SHORT: 8579 evmovdquw(dst, kmask, src, false, vector_len); 8580 break; 8581 case T_INT: 8582 case T_FLOAT: 8583 evmovdqul(dst, kmask, src, false, vector_len); 8584 break; 8585 case T_LONG: 8586 case T_DOUBLE: 8587 evmovdquq(dst, kmask, src, false, vector_len); 8588 break; 8589 default: 8590 fatal("Unexpected type argument %s", type2name(type)); 8591 break; 8592 } 8593 } 8594 8595 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) { 8596 switch(type) { 8597 case T_BYTE: 8598 case T_BOOLEAN: 8599 evmovdqub(dst, kmask, src, true, vector_len); 8600 break; 8601 case T_CHAR: 8602 case T_SHORT: 8603 evmovdquw(dst, kmask, src, true, vector_len); 8604 break; 8605 case T_INT: 8606 case T_FLOAT: 8607 evmovdqul(dst, kmask, src, true, vector_len); 8608 break; 8609 case T_LONG: 8610 case T_DOUBLE: 8611 evmovdquq(dst, kmask, src, true, vector_len); 8612 break; 8613 default: 8614 fatal("Unexpected type argument %s", type2name(type)); 8615 break; 8616 } 8617 } 8618 8619 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) { 8620 switch(masklen) { 8621 case 2: 8622 knotbl(dst, src); 8623 movl(rtmp, 3); 8624 kmovbl(ktmp, rtmp); 8625 kandbl(dst, ktmp, dst); 8626 break; 8627 case 4: 8628 knotbl(dst, src); 8629 movl(rtmp, 15); 8630 kmovbl(ktmp, rtmp); 8631 kandbl(dst, ktmp, dst); 8632 break; 8633 case 8: 8634 knotbl(dst, src); 8635 break; 8636 case 16: 8637 knotwl(dst, src); 8638 break; 8639 case 32: 8640 knotdl(dst, src); 8641 break; 8642 case 64: 8643 knotql(dst, src); 8644 break; 8645 default: 8646 fatal("Unexpected vector length %d", masklen); 8647 break; 8648 } 8649 } 8650 8651 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8652 switch(type) { 8653 case T_BOOLEAN: 8654 case T_BYTE: 8655 kandbl(dst, src1, src2); 8656 break; 8657 case T_CHAR: 8658 case T_SHORT: 8659 kandwl(dst, src1, src2); 8660 break; 8661 case T_INT: 8662 case T_FLOAT: 8663 kanddl(dst, src1, src2); 8664 break; 8665 case T_LONG: 8666 case T_DOUBLE: 8667 kandql(dst, src1, src2); 8668 break; 8669 default: 8670 fatal("Unexpected type argument %s", type2name(type)); 8671 break; 8672 } 8673 } 8674 8675 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8676 switch(type) { 8677 case T_BOOLEAN: 8678 case T_BYTE: 8679 korbl(dst, src1, src2); 8680 break; 8681 case T_CHAR: 8682 case T_SHORT: 8683 korwl(dst, src1, src2); 8684 break; 8685 case T_INT: 8686 case T_FLOAT: 8687 kordl(dst, src1, src2); 8688 break; 8689 case T_LONG: 8690 case T_DOUBLE: 8691 korql(dst, src1, src2); 8692 break; 8693 default: 8694 fatal("Unexpected type argument %s", type2name(type)); 8695 break; 8696 } 8697 } 8698 8699 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) { 8700 switch(type) { 8701 case T_BOOLEAN: 8702 case T_BYTE: 8703 kxorbl(dst, src1, src2); 8704 break; 8705 case T_CHAR: 8706 case T_SHORT: 8707 kxorwl(dst, src1, src2); 8708 break; 8709 case T_INT: 8710 case T_FLOAT: 8711 kxordl(dst, src1, src2); 8712 break; 8713 case T_LONG: 8714 case T_DOUBLE: 8715 kxorql(dst, src1, src2); 8716 break; 8717 default: 8718 fatal("Unexpected type argument %s", type2name(type)); 8719 break; 8720 } 8721 } 8722 8723 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8724 switch(type) { 8725 case T_BOOLEAN: 8726 case T_BYTE: 8727 evpermb(dst, mask, nds, src, merge, vector_len); break; 8728 case T_CHAR: 8729 case T_SHORT: 8730 evpermw(dst, mask, nds, src, merge, vector_len); break; 8731 case T_INT: 8732 case T_FLOAT: 8733 evpermd(dst, mask, nds, src, merge, vector_len); break; 8734 case T_LONG: 8735 case T_DOUBLE: 8736 evpermq(dst, mask, nds, src, merge, vector_len); break; 8737 default: 8738 fatal("Unexpected type argument %s", type2name(type)); break; 8739 } 8740 } 8741 8742 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8743 switch(type) { 8744 case T_BOOLEAN: 8745 case T_BYTE: 8746 evpermb(dst, mask, nds, src, merge, vector_len); break; 8747 case T_CHAR: 8748 case T_SHORT: 8749 evpermw(dst, mask, nds, src, merge, vector_len); break; 8750 case T_INT: 8751 case T_FLOAT: 8752 evpermd(dst, mask, nds, src, merge, vector_len); break; 8753 case T_LONG: 8754 case T_DOUBLE: 8755 evpermq(dst, mask, nds, src, merge, vector_len); break; 8756 default: 8757 fatal("Unexpected type argument %s", type2name(type)); break; 8758 } 8759 } 8760 8761 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8762 switch(type) { 8763 case T_BYTE: 8764 evpminsb(dst, mask, nds, src, merge, vector_len); break; 8765 case T_SHORT: 8766 evpminsw(dst, mask, nds, src, merge, vector_len); break; 8767 case T_INT: 8768 evpminsd(dst, mask, nds, src, merge, vector_len); break; 8769 case T_LONG: 8770 evpminsq(dst, mask, nds, src, merge, vector_len); break; 8771 default: 8772 fatal("Unexpected type argument %s", type2name(type)); break; 8773 } 8774 } 8775 8776 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8777 switch(type) { 8778 case T_BYTE: 8779 evpmaxsb(dst, mask, nds, src, merge, vector_len); break; 8780 case T_SHORT: 8781 evpmaxsw(dst, mask, nds, src, merge, vector_len); break; 8782 case T_INT: 8783 evpmaxsd(dst, mask, nds, src, merge, vector_len); break; 8784 case T_LONG: 8785 evpmaxsq(dst, mask, nds, src, merge, vector_len); break; 8786 default: 8787 fatal("Unexpected type argument %s", type2name(type)); break; 8788 } 8789 } 8790 8791 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8792 switch(type) { 8793 case T_BYTE: 8794 evpminsb(dst, mask, nds, src, merge, vector_len); break; 8795 case T_SHORT: 8796 evpminsw(dst, mask, nds, src, merge, vector_len); break; 8797 case T_INT: 8798 evpminsd(dst, mask, nds, src, merge, vector_len); break; 8799 case T_LONG: 8800 evpminsq(dst, mask, nds, src, merge, vector_len); break; 8801 default: 8802 fatal("Unexpected type argument %s", type2name(type)); break; 8803 } 8804 } 8805 8806 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8807 switch(type) { 8808 case T_BYTE: 8809 evpmaxsb(dst, mask, nds, src, merge, vector_len); break; 8810 case T_SHORT: 8811 evpmaxsw(dst, mask, nds, src, merge, vector_len); break; 8812 case T_INT: 8813 evpmaxsd(dst, mask, nds, src, merge, vector_len); break; 8814 case T_LONG: 8815 evpmaxsq(dst, mask, nds, src, merge, vector_len); break; 8816 default: 8817 fatal("Unexpected type argument %s", type2name(type)); break; 8818 } 8819 } 8820 8821 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8822 switch(type) { 8823 case T_INT: 8824 evpxord(dst, mask, nds, src, merge, vector_len); break; 8825 case T_LONG: 8826 evpxorq(dst, mask, nds, src, merge, vector_len); break; 8827 default: 8828 fatal("Unexpected type argument %s", type2name(type)); break; 8829 } 8830 } 8831 8832 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8833 switch(type) { 8834 case T_INT: 8835 evpxord(dst, mask, nds, src, merge, vector_len); break; 8836 case T_LONG: 8837 evpxorq(dst, mask, nds, src, merge, vector_len); break; 8838 default: 8839 fatal("Unexpected type argument %s", type2name(type)); break; 8840 } 8841 } 8842 8843 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8844 switch(type) { 8845 case T_INT: 8846 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break; 8847 case T_LONG: 8848 evporq(dst, mask, nds, src, merge, vector_len); break; 8849 default: 8850 fatal("Unexpected type argument %s", type2name(type)); break; 8851 } 8852 } 8853 8854 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8855 switch(type) { 8856 case T_INT: 8857 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break; 8858 case T_LONG: 8859 evporq(dst, mask, nds, src, merge, vector_len); break; 8860 default: 8861 fatal("Unexpected type argument %s", type2name(type)); break; 8862 } 8863 } 8864 8865 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) { 8866 switch(type) { 8867 case T_INT: 8868 evpandd(dst, mask, nds, src, merge, vector_len); break; 8869 case T_LONG: 8870 evpandq(dst, mask, nds, src, merge, vector_len); break; 8871 default: 8872 fatal("Unexpected type argument %s", type2name(type)); break; 8873 } 8874 } 8875 8876 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) { 8877 switch(type) { 8878 case T_INT: 8879 evpandd(dst, mask, nds, src, merge, vector_len); break; 8880 case T_LONG: 8881 evpandq(dst, mask, nds, src, merge, vector_len); break; 8882 default: 8883 fatal("Unexpected type argument %s", type2name(type)); break; 8884 } 8885 } 8886 8887 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) { 8888 masklen = masklen < 8 ? 8 : masklen; 8889 ktest(masklen, src1, src2); 8890 setb(Assembler::notZero, dst); 8891 movzbl(dst, dst); 8892 } 8893 8894 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) { 8895 if (masklen < 8) { 8896 knotbl(kscratch, src2); 8897 kortestbl(src1, kscratch); 8898 setb(Assembler::carrySet, dst); 8899 movzbl(dst, dst); 8900 } else { 8901 ktest(masklen, src1, src2); 8902 setb(Assembler::carrySet, dst); 8903 movzbl(dst, dst); 8904 } 8905 } 8906 8907 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) { 8908 switch(masklen) { 8909 case 8: 8910 kortestbl(src1, src2); 8911 break; 8912 case 16: 8913 kortestwl(src1, src2); 8914 break; 8915 case 32: 8916 kortestdl(src1, src2); 8917 break; 8918 case 64: 8919 kortestql(src1, src2); 8920 break; 8921 default: 8922 fatal("Unexpected mask length %d", masklen); 8923 break; 8924 } 8925 } 8926 8927 8928 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) { 8929 switch(masklen) { 8930 case 8: 8931 ktestbl(src1, src2); 8932 break; 8933 case 16: 8934 ktestwl(src1, src2); 8935 break; 8936 case 32: 8937 ktestdl(src1, src2); 8938 break; 8939 case 64: 8940 ktestql(src1, src2); 8941 break; 8942 default: 8943 fatal("Unexpected mask length %d", masklen); 8944 break; 8945 } 8946 } 8947 8948 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) { 8949 switch(type) { 8950 case T_INT: 8951 evprold(dst, mask, src, shift, merge, vlen_enc); break; 8952 case T_LONG: 8953 evprolq(dst, mask, src, shift, merge, vlen_enc); break; 8954 default: 8955 fatal("Unexpected type argument %s", type2name(type)); break; 8956 break; 8957 } 8958 } 8959 8960 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) { 8961 switch(type) { 8962 case T_INT: 8963 evprord(dst, mask, src, shift, merge, vlen_enc); break; 8964 case T_LONG: 8965 evprorq(dst, mask, src, shift, merge, vlen_enc); break; 8966 default: 8967 fatal("Unexpected type argument %s", type2name(type)); break; 8968 } 8969 } 8970 8971 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) { 8972 switch(type) { 8973 case T_INT: 8974 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break; 8975 case T_LONG: 8976 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break; 8977 default: 8978 fatal("Unexpected type argument %s", type2name(type)); break; 8979 } 8980 } 8981 8982 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) { 8983 switch(type) { 8984 case T_INT: 8985 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break; 8986 case T_LONG: 8987 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break; 8988 default: 8989 fatal("Unexpected type argument %s", type2name(type)); break; 8990 } 8991 } 8992 #if COMPILER2_OR_JVMCI 8993 8994 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask, 8995 Register length, Register temp, int vec_enc) { 8996 // Computing mask for predicated vector store. 8997 movptr(temp, -1); 8998 bzhiq(temp, temp, length); 8999 kmov(mask, temp); 9000 evmovdqu(bt, mask, dst, xmm, vec_enc); 9001 } 9002 9003 // Set memory operation for length "less than" 64 bytes. 9004 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp, 9005 XMMRegister xmm, KRegister mask, Register length, 9006 Register temp, bool use64byteVector) { 9007 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9008 BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG}; 9009 if (!use64byteVector) { 9010 fill32(dst, disp, xmm); 9011 subptr(length, 32 >> shift); 9012 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp); 9013 } else { 9014 assert(MaxVectorSize == 64, "vector length != 64"); 9015 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit); 9016 } 9017 } 9018 9019 9020 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp, 9021 XMMRegister xmm, KRegister mask, Register length, 9022 Register temp) { 9023 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9024 BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG}; 9025 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit); 9026 } 9027 9028 9029 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) { 9030 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9031 vmovdqu(Address(dst, disp), xmm); 9032 } 9033 9034 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) { 9035 assert(MaxVectorSize >= 32, "vector length should be >= 32"); 9036 BasicType type[] = {T_BYTE, T_SHORT, T_INT, T_LONG}; 9037 if (!use64byteVector) { 9038 fill32(dst, disp, xmm); 9039 fill32(dst, disp + 32, xmm); 9040 } else { 9041 evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit); 9042 } 9043 } 9044 9045 #ifdef _LP64 9046 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value, 9047 Register count, Register rtmp, XMMRegister xtmp) { 9048 Label L_exit; 9049 Label L_fill_start; 9050 Label L_fill_64_bytes; 9051 Label L_fill_96_bytes; 9052 Label L_fill_128_bytes; 9053 Label L_fill_128_bytes_loop; 9054 Label L_fill_128_loop_header; 9055 Label L_fill_128_bytes_loop_header; 9056 Label L_fill_128_bytes_loop_pre_header; 9057 Label L_fill_zmm_sequence; 9058 9059 int shift = -1; 9060 int avx3threshold = VM_Version::avx3_threshold(); 9061 switch(type) { 9062 case T_BYTE: shift = 0; 9063 break; 9064 case T_SHORT: shift = 1; 9065 break; 9066 case T_INT: shift = 2; 9067 break; 9068 /* Uncomment when LONG fill stubs are supported. 9069 case T_LONG: shift = 3; 9070 break; 9071 */ 9072 default: 9073 fatal("Unhandled type: %s\n", type2name(type)); 9074 } 9075 9076 if ((avx3threshold != 0) || (MaxVectorSize == 32)) { 9077 9078 if (MaxVectorSize == 64) { 9079 cmpq(count, avx3threshold >> shift); 9080 jcc(Assembler::greater, L_fill_zmm_sequence); 9081 } 9082 9083 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit); 9084 9085 bind(L_fill_start); 9086 9087 cmpq(count, 32 >> shift); 9088 jccb(Assembler::greater, L_fill_64_bytes); 9089 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp); 9090 jmp(L_exit); 9091 9092 bind(L_fill_64_bytes); 9093 cmpq(count, 64 >> shift); 9094 jccb(Assembler::greater, L_fill_96_bytes); 9095 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp); 9096 jmp(L_exit); 9097 9098 bind(L_fill_96_bytes); 9099 cmpq(count, 96 >> shift); 9100 jccb(Assembler::greater, L_fill_128_bytes); 9101 fill64(to, 0, xtmp); 9102 subq(count, 64 >> shift); 9103 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp); 9104 jmp(L_exit); 9105 9106 bind(L_fill_128_bytes); 9107 cmpq(count, 128 >> shift); 9108 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header); 9109 fill64(to, 0, xtmp); 9110 fill32(to, 64, xtmp); 9111 subq(count, 96 >> shift); 9112 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp); 9113 jmp(L_exit); 9114 9115 bind(L_fill_128_bytes_loop_pre_header); 9116 { 9117 mov(rtmp, to); 9118 andq(rtmp, 31); 9119 jccb(Assembler::zero, L_fill_128_bytes_loop_header); 9120 negq(rtmp); 9121 addq(rtmp, 32); 9122 mov64(r8, -1L); 9123 bzhiq(r8, r8, rtmp); 9124 kmovql(k2, r8); 9125 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_256bit); 9126 addq(to, rtmp); 9127 shrq(rtmp, shift); 9128 subq(count, rtmp); 9129 } 9130 9131 cmpq(count, 128 >> shift); 9132 jcc(Assembler::less, L_fill_start); 9133 9134 bind(L_fill_128_bytes_loop_header); 9135 subq(count, 128 >> shift); 9136 9137 align32(); 9138 bind(L_fill_128_bytes_loop); 9139 fill64(to, 0, xtmp); 9140 fill64(to, 64, xtmp); 9141 addq(to, 128); 9142 subq(count, 128 >> shift); 9143 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop); 9144 9145 addq(count, 128 >> shift); 9146 jcc(Assembler::zero, L_exit); 9147 jmp(L_fill_start); 9148 } 9149 9150 if (MaxVectorSize == 64) { 9151 // Sequence using 64 byte ZMM register. 9152 Label L_fill_128_bytes_zmm; 9153 Label L_fill_192_bytes_zmm; 9154 Label L_fill_192_bytes_loop_zmm; 9155 Label L_fill_192_bytes_loop_header_zmm; 9156 Label L_fill_192_bytes_loop_pre_header_zmm; 9157 Label L_fill_start_zmm_sequence; 9158 9159 bind(L_fill_zmm_sequence); 9160 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit); 9161 9162 bind(L_fill_start_zmm_sequence); 9163 cmpq(count, 64 >> shift); 9164 jccb(Assembler::greater, L_fill_128_bytes_zmm); 9165 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true); 9166 jmp(L_exit); 9167 9168 bind(L_fill_128_bytes_zmm); 9169 cmpq(count, 128 >> shift); 9170 jccb(Assembler::greater, L_fill_192_bytes_zmm); 9171 fill64(to, 0, xtmp, true); 9172 subq(count, 64 >> shift); 9173 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true); 9174 jmp(L_exit); 9175 9176 bind(L_fill_192_bytes_zmm); 9177 cmpq(count, 192 >> shift); 9178 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm); 9179 fill64(to, 0, xtmp, true); 9180 fill64(to, 64, xtmp, true); 9181 subq(count, 128 >> shift); 9182 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true); 9183 jmp(L_exit); 9184 9185 bind(L_fill_192_bytes_loop_pre_header_zmm); 9186 { 9187 movq(rtmp, to); 9188 andq(rtmp, 63); 9189 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm); 9190 negq(rtmp); 9191 addq(rtmp, 64); 9192 mov64(r8, -1L); 9193 bzhiq(r8, r8, rtmp); 9194 kmovql(k2, r8); 9195 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_512bit); 9196 addq(to, rtmp); 9197 shrq(rtmp, shift); 9198 subq(count, rtmp); 9199 } 9200 9201 cmpq(count, 192 >> shift); 9202 jcc(Assembler::less, L_fill_start_zmm_sequence); 9203 9204 bind(L_fill_192_bytes_loop_header_zmm); 9205 subq(count, 192 >> shift); 9206 9207 align32(); 9208 bind(L_fill_192_bytes_loop_zmm); 9209 fill64(to, 0, xtmp, true); 9210 fill64(to, 64, xtmp, true); 9211 fill64(to, 128, xtmp, true); 9212 addq(to, 192); 9213 subq(count, 192 >> shift); 9214 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm); 9215 9216 addq(count, 192 >> shift); 9217 jcc(Assembler::zero, L_exit); 9218 jmp(L_fill_start_zmm_sequence); 9219 } 9220 bind(L_exit); 9221 } 9222 #endif 9223 #endif //COMPILER2_OR_JVMCI 9224 9225 9226 #ifdef _LP64 9227 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) { 9228 Label done; 9229 cvttss2sil(dst, src); 9230 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 9231 cmpl(dst, 0x80000000); // float_sign_flip 9232 jccb(Assembler::notEqual, done); 9233 subptr(rsp, 8); 9234 movflt(Address(rsp, 0), src); 9235 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup()))); 9236 pop(dst); 9237 bind(done); 9238 } 9239 9240 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) { 9241 Label done; 9242 cvttsd2sil(dst, src); 9243 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub 9244 cmpl(dst, 0x80000000); // float_sign_flip 9245 jccb(Assembler::notEqual, done); 9246 subptr(rsp, 8); 9247 movdbl(Address(rsp, 0), src); 9248 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup()))); 9249 pop(dst); 9250 bind(done); 9251 } 9252 9253 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) { 9254 Label done; 9255 cvttss2siq(dst, src); 9256 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 9257 jccb(Assembler::notEqual, done); 9258 subptr(rsp, 8); 9259 movflt(Address(rsp, 0), src); 9260 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup()))); 9261 pop(dst); 9262 bind(done); 9263 } 9264 9265 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) { 9266 // Following code is line by line assembly translation rounding algorithm. 9267 // Please refer to java.lang.Math.round(float) algorithm for details. 9268 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000; 9269 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24; 9270 const int32_t FloatConsts_EXP_BIAS = 127; 9271 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF; 9272 const int32_t MINUS_32 = 0xFFFFFFE0; 9273 Label L_special_case, L_block1, L_exit; 9274 movl(rtmp, FloatConsts_EXP_BIT_MASK); 9275 movdl(dst, src); 9276 andl(dst, rtmp); 9277 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1); 9278 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS); 9279 subl(rtmp, dst); 9280 movl(rcx, rtmp); 9281 movl(dst, MINUS_32); 9282 testl(rtmp, dst); 9283 jccb(Assembler::notEqual, L_special_case); 9284 movdl(dst, src); 9285 andl(dst, FloatConsts_SIGNIF_BIT_MASK); 9286 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1); 9287 movdl(rtmp, src); 9288 testl(rtmp, rtmp); 9289 jccb(Assembler::greaterEqual, L_block1); 9290 negl(dst); 9291 bind(L_block1); 9292 sarl(dst); 9293 addl(dst, 0x1); 9294 sarl(dst, 0x1); 9295 jmp(L_exit); 9296 bind(L_special_case); 9297 convert_f2i(dst, src); 9298 bind(L_exit); 9299 } 9300 9301 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) { 9302 // Following code is line by line assembly translation rounding algorithm. 9303 // Please refer to java.lang.Math.round(double) algorithm for details. 9304 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L; 9305 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53; 9306 const int64_t DoubleConsts_EXP_BIAS = 1023; 9307 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL; 9308 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L; 9309 Label L_special_case, L_block1, L_exit; 9310 mov64(rtmp, DoubleConsts_EXP_BIT_MASK); 9311 movq(dst, src); 9312 andq(dst, rtmp); 9313 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1); 9314 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS); 9315 subq(rtmp, dst); 9316 movq(rcx, rtmp); 9317 mov64(dst, MINUS_64); 9318 testq(rtmp, dst); 9319 jccb(Assembler::notEqual, L_special_case); 9320 movq(dst, src); 9321 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK); 9322 andq(dst, rtmp); 9323 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1); 9324 orq(dst, rtmp); 9325 movq(rtmp, src); 9326 testq(rtmp, rtmp); 9327 jccb(Assembler::greaterEqual, L_block1); 9328 negq(dst); 9329 bind(L_block1); 9330 sarq(dst); 9331 addq(dst, 0x1); 9332 sarq(dst, 0x1); 9333 jmp(L_exit); 9334 bind(L_special_case); 9335 convert_d2l(dst, src); 9336 bind(L_exit); 9337 } 9338 9339 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) { 9340 Label done; 9341 cvttsd2siq(dst, src); 9342 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip())); 9343 jccb(Assembler::notEqual, done); 9344 subptr(rsp, 8); 9345 movdbl(Address(rsp, 0), src); 9346 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup()))); 9347 pop(dst); 9348 bind(done); 9349 } 9350 9351 void MacroAssembler::cache_wb(Address line) 9352 { 9353 // 64 bit cpus always support clflush 9354 assert(VM_Version::supports_clflush(), "clflush should be available"); 9355 bool optimized = VM_Version::supports_clflushopt(); 9356 bool no_evict = VM_Version::supports_clwb(); 9357 9358 // prefer clwb (writeback without evict) otherwise 9359 // prefer clflushopt (potentially parallel writeback with evict) 9360 // otherwise fallback on clflush (serial writeback with evict) 9361 9362 if (optimized) { 9363 if (no_evict) { 9364 clwb(line); 9365 } else { 9366 clflushopt(line); 9367 } 9368 } else { 9369 // no need for fence when using CLFLUSH 9370 clflush(line); 9371 } 9372 } 9373 9374 void MacroAssembler::cache_wbsync(bool is_pre) 9375 { 9376 assert(VM_Version::supports_clflush(), "clflush should be available"); 9377 bool optimized = VM_Version::supports_clflushopt(); 9378 bool no_evict = VM_Version::supports_clwb(); 9379 9380 // pick the correct implementation 9381 9382 if (!is_pre && (optimized || no_evict)) { 9383 // need an sfence for post flush when using clflushopt or clwb 9384 // otherwise no no need for any synchroniaztion 9385 9386 sfence(); 9387 } 9388 } 9389 9390 #endif // _LP64 9391 9392 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 9393 switch (cond) { 9394 // Note some conditions are synonyms for others 9395 case Assembler::zero: return Assembler::notZero; 9396 case Assembler::notZero: return Assembler::zero; 9397 case Assembler::less: return Assembler::greaterEqual; 9398 case Assembler::lessEqual: return Assembler::greater; 9399 case Assembler::greater: return Assembler::lessEqual; 9400 case Assembler::greaterEqual: return Assembler::less; 9401 case Assembler::below: return Assembler::aboveEqual; 9402 case Assembler::belowEqual: return Assembler::above; 9403 case Assembler::above: return Assembler::belowEqual; 9404 case Assembler::aboveEqual: return Assembler::below; 9405 case Assembler::overflow: return Assembler::noOverflow; 9406 case Assembler::noOverflow: return Assembler::overflow; 9407 case Assembler::negative: return Assembler::positive; 9408 case Assembler::positive: return Assembler::negative; 9409 case Assembler::parity: return Assembler::noParity; 9410 case Assembler::noParity: return Assembler::parity; 9411 } 9412 ShouldNotReachHere(); return Assembler::overflow; 9413 } 9414 9415 SkipIfEqual::SkipIfEqual( 9416 MacroAssembler* masm, const bool* flag_addr, bool value) { 9417 _masm = masm; 9418 _masm->cmp8(ExternalAddress((address)flag_addr), value); 9419 _masm->jcc(Assembler::equal, _label); 9420 } 9421 9422 SkipIfEqual::~SkipIfEqual() { 9423 _masm->bind(_label); 9424 } 9425 9426 // 32-bit Windows has its own fast-path implementation 9427 // of get_thread 9428 #if !defined(WIN32) || defined(_LP64) 9429 9430 // This is simply a call to Thread::current() 9431 void MacroAssembler::get_thread(Register thread) { 9432 if (thread != rax) { 9433 push(rax); 9434 } 9435 LP64_ONLY(push(rdi);) 9436 LP64_ONLY(push(rsi);) 9437 push(rdx); 9438 push(rcx); 9439 #ifdef _LP64 9440 push(r8); 9441 push(r9); 9442 push(r10); 9443 push(r11); 9444 #endif 9445 9446 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 9447 9448 #ifdef _LP64 9449 pop(r11); 9450 pop(r10); 9451 pop(r9); 9452 pop(r8); 9453 #endif 9454 pop(rcx); 9455 pop(rdx); 9456 LP64_ONLY(pop(rsi);) 9457 LP64_ONLY(pop(rdi);) 9458 if (thread != rax) { 9459 mov(thread, rax); 9460 pop(rax); 9461 } 9462 } 9463 9464 9465 #endif // !WIN32 || _LP64