1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "asm/assembler.hpp"
26 #include "asm/assembler.inline.hpp"
27 #include "code/compiledIC.hpp"
28 #include "compiler/compiler_globals.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "crc32c.h"
31 #include "gc/shared/barrierSet.hpp"
32 #include "gc/shared/barrierSetAssembler.hpp"
33 #include "gc/shared/collectedHeap.inline.hpp"
34 #include "gc/shared/tlab_globals.hpp"
35 #include "interpreter/bytecodeHistogram.hpp"
36 #include "interpreter/interpreter.hpp"
37 #include "interpreter/interpreterRuntime.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
78 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
79 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
80 Assembler::above /* belowEqual = 0x6 */ ,
81 Assembler::belowEqual /* above = 0x7 */ ,
82 Assembler::positive /* negative = 0x8 */ ,
83 Assembler::negative /* positive = 0x9 */ ,
84 Assembler::noParity /* parity = 0xa */ ,
85 Assembler::parity /* noParity = 0xb */ ,
86 Assembler::greaterEqual /* less = 0xc */ ,
87 Assembler::less /* greaterEqual = 0xd */ ,
88 Assembler::greater /* lessEqual = 0xe */ ,
89 Assembler::lessEqual /* greater = 0xf, */
90
91 };
92
93
94 // Implementation of MacroAssembler
95
96 // First all the versions that have distinct versions depending on 32/64 bit
97 // Unless the difference is trivial (1 line or so).
98
99 #ifndef _LP64
100
101 // 32bit versions
102
103 Address MacroAssembler::as_Address(AddressLiteral adr) {
104 return Address(adr.target(), adr.rspec());
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 assert(rscratch == noreg, "");
109 return Address::make_array(adr);
110 }
111
112 void MacroAssembler::call_VM_leaf_base(address entry_point,
113 int number_of_arguments) {
114 call(RuntimeAddress(entry_point));
115 increment(rsp, number_of_arguments * wordSize);
116 }
117
118 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122
123 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
124 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Address src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
132 assert(rscratch == noreg, "redundant");
133 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
134 }
135
136 void MacroAssembler::extend_sign(Register hi, Register lo) {
137 // According to Intel Doc. AP-526, "Integer Divide", p.18.
138 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
139 cdql();
140 } else {
141 movl(hi, lo);
142 sarl(hi, 31);
143 }
144 }
145
146 void MacroAssembler::jC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::parity, L);
154 }
155
156 void MacroAssembler::jnC2(Register tmp, Label& L) {
157 // set parity bit if FPU flag C2 is set (via rax)
158 save_rax(tmp);
159 fwait(); fnstsw_ax();
160 sahf();
161 restore_rax(tmp);
162 // branch
163 jcc(Assembler::noParity, L);
164 }
165
166 // 32bit can do a case table jump in one instruction but we no longer allow the base
167 // to be installed in the Address class
168 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
169 assert(rscratch == noreg, "not needed");
170 jmp(as_Address(entry, noreg));
171 }
172
173 // Note: y_lo will be destroyed
174 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
175 // Long compare for Java (semantics as described in JVM spec.)
176 Label high, low, done;
177
178 cmpl(x_hi, y_hi);
179 jcc(Assembler::less, low);
180 jcc(Assembler::greater, high);
181 // x_hi is the return register
182 xorl(x_hi, x_hi);
183 cmpl(x_lo, y_lo);
184 jcc(Assembler::below, low);
185 jcc(Assembler::equal, done);
186
187 bind(high);
188 xorl(x_hi, x_hi);
189 increment(x_hi);
190 jmp(done);
191
192 bind(low);
193 xorl(x_hi, x_hi);
194 decrementl(x_hi);
195
196 bind(done);
197 }
198
199 void MacroAssembler::lea(Register dst, AddressLiteral src) {
200 mov_literal32(dst, (int32_t)src.target(), src.rspec());
201 }
202
203 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
204 assert(rscratch == noreg, "not needed");
205
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
309 assert(rscratch == noreg, "redundant");
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
318 assert(rscratch == noreg, "redundant");
319 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
320 }
321
322 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
331 assert(rscratch == noreg, "redundant");
332 movl(as_Address(dst, noreg), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src, noreg));
337 }
338
339 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
340 assert(rscratch == noreg, "redundant");
341 movl(dst, src);
342 }
343
344 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
345 assert(rscratch == noreg, "redundant");
346 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
347 }
348
349 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
350 assert(rscratch == noreg, "redundant");
351 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
352 }
353
354 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
355 assert(rscratch == noreg, "redundant");
356 if (src.is_lval()) {
357 push_literal32((int32_t)src.target(), src.rspec());
358 } else {
359 pushl(as_Address(src));
360 }
361 }
362
363 static void pass_arg0(MacroAssembler* masm, Register arg) {
364 masm->push(arg);
365 }
366
367 static void pass_arg1(MacroAssembler* masm, Register arg) {
368 masm->push(arg);
369 }
370
371 static void pass_arg2(MacroAssembler* masm, Register arg) {
372 masm->push(arg);
373 }
374
375 static void pass_arg3(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 #ifndef PRODUCT
380 extern "C" void findpc(intptr_t x);
381 #endif
382
383 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
384 // In order to get locks to work, we need to fake a in_VM state
385 JavaThread* thread = JavaThread::current();
386 JavaThreadState saved_state = thread->thread_state();
387 thread->set_thread_state(_thread_in_vm);
388 if (ShowMessageBoxOnError) {
389 JavaThread* thread = JavaThread::current();
390 JavaThreadState saved_state = thread->thread_state();
391 thread->set_thread_state(_thread_in_vm);
392 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
393 ttyLocker ttyl;
394 BytecodeCounter::print();
395 }
396 // To see where a verify_oop failed, get $ebx+40/X for this frame.
397 // This is the value of eip which points to where verify_oop will return.
398 if (os::message_box(msg, "Execution stopped, print registers?")) {
399 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
400 BREAKPOINT;
401 }
402 }
403 fatal("DEBUG MESSAGE: %s", msg);
404 }
405
406 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
407 ttyLocker ttyl;
408 DebuggingContext debugging{};
409 tty->print_cr("eip = 0x%08x", eip);
410 #ifndef PRODUCT
411 if ((WizardMode || Verbose) && PrintMiscellaneous) {
412 tty->cr();
413 findpc(eip);
414 tty->cr();
415 }
416 #endif
417 #define PRINT_REG(rax) \
418 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
419 PRINT_REG(rax);
420 PRINT_REG(rbx);
421 PRINT_REG(rcx);
422 PRINT_REG(rdx);
423 PRINT_REG(rdi);
424 PRINT_REG(rsi);
425 PRINT_REG(rbp);
426 PRINT_REG(rsp);
427 #undef PRINT_REG
428 // Print some words near top of staack.
429 int* dump_sp = (int*) rsp;
430 for (int col1 = 0; col1 < 8; col1++) {
431 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
432 os::print_location(tty, *dump_sp++);
433 }
434 for (int row = 0; row < 16; row++) {
435 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
436 for (int col = 0; col < 8; col++) {
437 tty->print(" 0x%08x", *dump_sp++);
438 }
439 tty->cr();
440 }
441 // Print some instructions around pc:
442 Disassembler::decode((address)eip-64, (address)eip);
443 tty->print_cr("--------");
444 Disassembler::decode((address)eip, (address)eip+32);
445 }
446
447 void MacroAssembler::stop(const char* msg) {
448 // push address of message
449 ExternalAddress message((address)msg);
450 pushptr(message.addr(), noreg);
451 { Label L; call(L, relocInfo::none); bind(L); } // push eip
452 pusha(); // push registers
453 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
454 hlt();
455 }
456
457 void MacroAssembler::warn(const char* msg) {
458 push_CPU_state();
459
460 // push address of message
461 ExternalAddress message((address)msg);
462 pushptr(message.addr(), noreg);
463
464 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
465 addl(rsp, wordSize); // discard argument
466 pop_CPU_state();
467 }
468
469 void MacroAssembler::print_state() {
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472
473 push_CPU_state();
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
475 pop_CPU_state();
476
477 popa();
478 addl(rsp, wordSize);
479 }
480
481 #else // _LP64
482
483 // 64 bit versions
484
485 Address MacroAssembler::as_Address(AddressLiteral adr) {
486 // amd64 always does this as a pc-rel
487 // we can be absolute or disp based on the instruction type
488 // jmp/call are displacements others are absolute
489 assert(!adr.is_lval(), "must be rval");
490 assert(reachable(adr), "must be");
491 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
492
493 }
494
495 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
496 AddressLiteral base = adr.base();
497 lea(rscratch, base);
498 Address index = adr.index();
499 assert(index._disp == 0, "must not have disp"); // maybe it can?
500 Address array(rscratch, index._index, index._scale, index._disp);
501 return array;
502 }
503
504 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
505 Label L, E;
506
507 #ifdef _WIN64
508 // Windows always allocates space for it's register args
509 assert(num_args <= 4, "only register arguments supported");
510 subq(rsp, frame::arg_reg_save_area_bytes);
511 #endif
512
513 // Align stack if necessary
514 testl(rsp, 15);
515 jcc(Assembler::zero, L);
516
517 subq(rsp, 8);
518 call(RuntimeAddress(entry_point));
519 addq(rsp, 8);
520 jmp(E);
521
522 bind(L);
523 call(RuntimeAddress(entry_point));
524
525 bind(E);
526
527 #ifdef _WIN64
528 // restore stack pointer
529 addq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531 }
532
533 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
534 assert(!src2.is_lval(), "should use cmpptr");
535 assert(rscratch != noreg || always_reachable(src2), "missing");
536
537 if (reachable(src2)) {
538 cmpq(src1, as_Address(src2));
539 } else {
540 lea(rscratch, src2);
541 Assembler::cmpq(src1, Address(rscratch, 0));
542 }
543 }
544
545 int MacroAssembler::corrected_idivq(Register reg) {
546 // Full implementation of Java ldiv and lrem; checks for special
547 // case as described in JVM spec., p.243 & p.271. The function
548 // returns the (pc) offset of the idivl instruction - may be needed
549 // for implicit exceptions.
550 //
551 // normal case special case
552 //
553 // input : rax: dividend min_long
554 // reg: divisor (may not be eax/edx) -1
555 //
556 // output: rax: quotient (= rax idiv reg) min_long
557 // rdx: remainder (= rax irem reg) 0
558 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
559 static const int64_t min_long = 0x8000000000000000;
560 Label normal_case, special_case;
561
562 // check for special case
563 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
564 jcc(Assembler::notEqual, normal_case);
565 xorl(rdx, rdx); // prepare rdx for possible special case (where
566 // remainder = 0)
567 cmpq(reg, -1);
568 jcc(Assembler::equal, special_case);
569
570 // handle normal case
571 bind(normal_case);
572 cdqq();
573 int idivq_offset = offset();
574 idivq(reg);
575
576 // normal and special case exit
577 bind(special_case);
578
579 return idivq_offset;
580 }
581
582 void MacroAssembler::decrementq(Register reg, int value) {
583 if (value == min_jint) { subq(reg, value); return; }
584 if (value < 0) { incrementq(reg, -value); return; }
585 if (value == 0) { ; return; }
586 if (value == 1 && UseIncDec) { decq(reg) ; return; }
587 /* else */ { subq(reg, value) ; return; }
588 }
589
590 void MacroAssembler::decrementq(Address dst, int value) {
591 if (value == min_jint) { subq(dst, value); return; }
592 if (value < 0) { incrementq(dst, -value); return; }
593 if (value == 0) { ; return; }
594 if (value == 1 && UseIncDec) { decq(dst) ; return; }
595 /* else */ { subq(dst, value) ; return; }
596 }
597
598 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
599 assert(rscratch != noreg || always_reachable(dst), "missing");
600
601 if (reachable(dst)) {
602 incrementq(as_Address(dst));
603 } else {
604 lea(rscratch, dst);
605 incrementq(Address(rscratch, 0));
606 }
607 }
608
609 void MacroAssembler::incrementq(Register reg, int value) {
610 if (value == min_jint) { addq(reg, value); return; }
611 if (value < 0) { decrementq(reg, -value); return; }
612 if (value == 0) { ; return; }
613 if (value == 1 && UseIncDec) { incq(reg) ; return; }
614 /* else */ { addq(reg, value) ; return; }
615 }
616
617 void MacroAssembler::incrementq(Address dst, int value) {
618 if (value == min_jint) { addq(dst, value); return; }
619 if (value < 0) { decrementq(dst, -value); return; }
620 if (value == 0) { ; return; }
621 if (value == 1 && UseIncDec) { incq(dst) ; return; }
622 /* else */ { addq(dst, value) ; return; }
623 }
624
625 // 32bit can do a case table jump in one instruction but we no longer allow the base
626 // to be installed in the Address class
627 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
628 lea(rscratch, entry.base());
629 Address dispatch = entry.index();
630 assert(dispatch._base == noreg, "must be");
631 dispatch._base = rscratch;
632 jmp(dispatch);
633 }
634
635 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
636 ShouldNotReachHere(); // 64bit doesn't use two regs
637 cmpq(x_lo, y_lo);
638 }
639
640 void MacroAssembler::lea(Register dst, AddressLiteral src) {
641 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
642 }
643
644 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
645 lea(rscratch, adr);
646 movptr(dst, rscratch);
647 }
648
649 void MacroAssembler::leave() {
650 // %%% is this really better? Why not on 32bit too?
651 emit_int8((unsigned char)0xC9); // LEAVE
652 }
653
654 void MacroAssembler::lneg(Register hi, Register lo) {
655 ShouldNotReachHere(); // 64bit doesn't use two regs
656 negq(lo);
657 }
658
659 void MacroAssembler::movoop(Register dst, jobject obj) {
660 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
661 }
662
663 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
664 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
665 movq(dst, rscratch);
666 }
667
668 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
669 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
670 }
671
672 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
673 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
674 movq(dst, rscratch);
675 }
676
677 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
678 if (src.is_lval()) {
679 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
680 } else {
681 if (reachable(src)) {
682 movq(dst, as_Address(src));
683 } else {
684 lea(dst, src);
685 movq(dst, Address(dst, 0));
686 }
687 }
688 }
689
690 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
691 movq(as_Address(dst, rscratch), src);
692 }
693
694 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
695 movq(dst, as_Address(src, dst /*rscratch*/));
696 }
697
698 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
699 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
700 if (is_simm32(src)) {
701 movptr(dst, checked_cast<int32_t>(src));
702 } else {
703 mov64(rscratch, src);
704 movq(dst, rscratch);
705 }
706 }
707
708 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
709 movoop(rscratch, obj);
710 push(rscratch);
711 }
712
713 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
714 mov_metadata(rscratch, obj);
715 push(rscratch);
716 }
717
718 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
719 lea(rscratch, src);
720 if (src.is_lval()) {
721 push(rscratch);
722 } else {
723 pushq(Address(rscratch, 0));
724 }
725 }
726
727 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
728 reset_last_Java_frame(r15_thread, clear_fp);
729 }
730
731 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
732 Register last_java_fp,
733 address last_java_pc,
734 Register rscratch) {
735 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
736 }
737
738 static void pass_arg0(MacroAssembler* masm, Register arg) {
739 if (c_rarg0 != arg ) {
740 masm->mov(c_rarg0, arg);
741 }
742 }
743
744 static void pass_arg1(MacroAssembler* masm, Register arg) {
745 if (c_rarg1 != arg ) {
746 masm->mov(c_rarg1, arg);
747 }
748 }
749
750 static void pass_arg2(MacroAssembler* masm, Register arg) {
751 if (c_rarg2 != arg ) {
752 masm->mov(c_rarg2, arg);
753 }
754 }
755
756 static void pass_arg3(MacroAssembler* masm, Register arg) {
757 if (c_rarg3 != arg ) {
758 masm->mov(c_rarg3, arg);
759 }
760 }
761
762 void MacroAssembler::stop(const char* msg) {
763 if (ShowMessageBoxOnError) {
764 address rip = pc();
765 pusha(); // get regs on stack
766 lea(c_rarg1, InternalAddress(rip));
767 movq(c_rarg2, rsp); // pass pointer to regs array
768 }
769 lea(c_rarg0, ExternalAddress((address) msg));
770 andq(rsp, -16); // align stack as required by ABI
771 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
772 hlt();
773 }
774
775 void MacroAssembler::warn(const char* msg) {
776 push(rbp);
777 movq(rbp, rsp);
778 andq(rsp, -16); // align stack as required by push_CPU_state and call
779 push_CPU_state(); // keeps alignment at 16 bytes
780
781 #ifdef _WIN64
782 // Windows always allocates space for its register args
783 subq(rsp, frame::arg_reg_save_area_bytes);
784 #endif
785 lea(c_rarg0, ExternalAddress((address) msg));
786 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
787
788 #ifdef _WIN64
789 // restore stack pointer
790 addq(rsp, frame::arg_reg_save_area_bytes);
791 #endif
792 pop_CPU_state();
793 mov(rsp, rbp);
794 pop(rbp);
795 }
796
797 void MacroAssembler::print_state() {
798 address rip = pc();
799 pusha(); // get regs on stack
800 push(rbp);
801 movq(rbp, rsp);
802 andq(rsp, -16); // align stack as required by push_CPU_state and call
803 push_CPU_state(); // keeps alignment at 16 bytes
804
805 lea(c_rarg0, InternalAddress(rip));
806 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
807 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
808
809 pop_CPU_state();
810 mov(rsp, rbp);
811 pop(rbp);
812 popa();
813 }
814
815 #ifndef PRODUCT
816 extern "C" void findpc(intptr_t x);
817 #endif
818
819 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
820 // In order to get locks to work, we need to fake a in_VM state
821 if (ShowMessageBoxOnError) {
822 JavaThread* thread = JavaThread::current();
823 JavaThreadState saved_state = thread->thread_state();
824 thread->set_thread_state(_thread_in_vm);
825 #ifndef PRODUCT
826 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
827 ttyLocker ttyl;
828 BytecodeCounter::print();
829 }
830 #endif
831 // To see where a verify_oop failed, get $ebx+40/X for this frame.
832 // XXX correct this offset for amd64
833 // This is the value of eip which points to where verify_oop will return.
834 if (os::message_box(msg, "Execution stopped, print registers?")) {
835 print_state64(pc, regs);
836 BREAKPOINT;
837 }
838 }
839 fatal("DEBUG MESSAGE: %s", msg);
840 }
841
842 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
843 ttyLocker ttyl;
844 DebuggingContext debugging{};
845 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
846 #ifndef PRODUCT
847 tty->cr();
848 findpc(pc);
849 tty->cr();
850 #endif
851 #define PRINT_REG(rax, value) \
852 { tty->print("%s = ", #rax); os::print_location(tty, value); }
853 PRINT_REG(rax, regs[15]);
854 PRINT_REG(rbx, regs[12]);
855 PRINT_REG(rcx, regs[14]);
856 PRINT_REG(rdx, regs[13]);
857 PRINT_REG(rdi, regs[8]);
858 PRINT_REG(rsi, regs[9]);
859 PRINT_REG(rbp, regs[10]);
860 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
861 PRINT_REG(rsp, (intptr_t)(®s[16]));
862 PRINT_REG(r8 , regs[7]);
863 PRINT_REG(r9 , regs[6]);
864 PRINT_REG(r10, regs[5]);
865 PRINT_REG(r11, regs[4]);
866 PRINT_REG(r12, regs[3]);
867 PRINT_REG(r13, regs[2]);
868 PRINT_REG(r14, regs[1]);
869 PRINT_REG(r15, regs[0]);
870 #undef PRINT_REG
871 // Print some words near the top of the stack.
872 int64_t* rsp = ®s[16];
873 int64_t* dump_sp = rsp;
874 for (int col1 = 0; col1 < 8; col1++) {
875 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
876 os::print_location(tty, *dump_sp++);
877 }
878 for (int row = 0; row < 25; row++) {
879 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
880 for (int col = 0; col < 4; col++) {
881 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
882 }
883 tty->cr();
884 }
885 // Print some instructions around pc:
886 Disassembler::decode((address)pc-64, (address)pc);
887 tty->print_cr("--------");
888 Disassembler::decode((address)pc, (address)pc+32);
889 }
890
891 // The java_calling_convention describes stack locations as ideal slots on
892 // a frame with no abi restrictions. Since we must observe abi restrictions
893 // (like the placement of the register window) the slots must be biased by
894 // the following value.
895 static int reg2offset_in(VMReg r) {
896 // Account for saved rbp and return address
897 // This should really be in_preserve_stack_slots
898 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
899 }
900
901 static int reg2offset_out(VMReg r) {
902 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
903 }
904
905 // A long move
906 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
907
908 // The calling conventions assures us that each VMregpair is either
909 // all really one physical register or adjacent stack slots.
910
911 if (src.is_single_phys_reg() ) {
912 if (dst.is_single_phys_reg()) {
913 if (dst.first() != src.first()) {
914 mov(dst.first()->as_Register(), src.first()->as_Register());
915 }
916 } else {
917 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
918 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
919 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
920 }
921 } else if (dst.is_single_phys_reg()) {
922 assert(src.is_single_reg(), "not a stack pair");
923 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
924 } else {
925 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
926 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
927 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
928 }
929 }
930
931 // A double move
932 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
933
934 // The calling conventions assures us that each VMregpair is either
935 // all really one physical register or adjacent stack slots.
936
937 if (src.is_single_phys_reg() ) {
938 if (dst.is_single_phys_reg()) {
939 // In theory these overlap but the ordering is such that this is likely a nop
940 if ( src.first() != dst.first()) {
941 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
942 }
943 } else {
944 assert(dst.is_single_reg(), "not a stack pair");
945 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
946 }
947 } else if (dst.is_single_phys_reg()) {
948 assert(src.is_single_reg(), "not a stack pair");
949 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
950 } else {
951 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
952 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
953 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
954 }
955 }
956
957
958 // A float arg may have to do float reg int reg conversion
959 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
960 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
961
962 // The calling conventions assures us that each VMregpair is either
963 // all really one physical register or adjacent stack slots.
964
965 if (src.first()->is_stack()) {
966 if (dst.first()->is_stack()) {
967 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
968 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
969 } else {
970 // stack to reg
971 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
972 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
973 }
974 } else if (dst.first()->is_stack()) {
975 // reg to stack
976 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
977 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
978 } else {
979 // reg to reg
980 // In theory these overlap but the ordering is such that this is likely a nop
981 if ( src.first() != dst.first()) {
982 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
983 }
984 }
985 }
986
987 // On 64 bit we will store integer like items to the stack as
988 // 64 bits items (x86_32/64 abi) even though java would only store
989 // 32bits for a parameter. On 32bit it will simply be 32 bits
990 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
991 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
992 if (src.first()->is_stack()) {
993 if (dst.first()->is_stack()) {
994 // stack to stack
995 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
996 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
997 } else {
998 // stack to reg
999 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1000 }
1001 } else if (dst.first()->is_stack()) {
1002 // reg to stack
1003 // Do we really have to sign extend???
1004 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1005 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1006 } else {
1007 // Do we really have to sign extend???
1008 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1009 if (dst.first() != src.first()) {
1010 movq(dst.first()->as_Register(), src.first()->as_Register());
1011 }
1012 }
1013 }
1014
1015 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1016 if (src.first()->is_stack()) {
1017 if (dst.first()->is_stack()) {
1018 // stack to stack
1019 movq(rax, Address(rbp, reg2offset_in(src.first())));
1020 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1021 } else {
1022 // stack to reg
1023 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1024 }
1025 } else if (dst.first()->is_stack()) {
1026 // reg to stack
1027 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1028 } else {
1029 if (dst.first() != src.first()) {
1030 movq(dst.first()->as_Register(), src.first()->as_Register());
1031 }
1032 }
1033 }
1034
1035 // An oop arg. Must pass a handle not the oop itself
1036 void MacroAssembler::object_move(OopMap* map,
1037 int oop_handle_offset,
1038 int framesize_in_slots,
1039 VMRegPair src,
1040 VMRegPair dst,
1041 bool is_receiver,
1042 int* receiver_offset) {
1043
1044 // must pass a handle. First figure out the location we use as a handle
1045
1046 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1047
1048 // See if oop is null if it is we need no handle
1049
1050 if (src.first()->is_stack()) {
1051
1052 // Oop is already on the stack as an argument
1053 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1054 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1055 if (is_receiver) {
1056 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1057 }
1058
1059 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1060 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1061 // conditionally move a null
1062 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1063 } else {
1064
1065 // Oop is in a register we must store it to the space we reserve
1066 // on the stack for oop_handles and pass a handle if oop is non-null
1067
1068 const Register rOop = src.first()->as_Register();
1069 int oop_slot;
1070 if (rOop == j_rarg0)
1071 oop_slot = 0;
1072 else if (rOop == j_rarg1)
1073 oop_slot = 1;
1074 else if (rOop == j_rarg2)
1075 oop_slot = 2;
1076 else if (rOop == j_rarg3)
1077 oop_slot = 3;
1078 else if (rOop == j_rarg4)
1079 oop_slot = 4;
1080 else {
1081 assert(rOop == j_rarg5, "wrong register");
1082 oop_slot = 5;
1083 }
1084
1085 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1086 int offset = oop_slot*VMRegImpl::stack_slot_size;
1087
1088 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1089 // Store oop in handle area, may be null
1090 movptr(Address(rsp, offset), rOop);
1091 if (is_receiver) {
1092 *receiver_offset = offset;
1093 }
1094
1095 cmpptr(rOop, NULL_WORD);
1096 lea(rHandle, Address(rsp, offset));
1097 // conditionally move a null from the handle area where it was just stored
1098 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1099 }
1100
1101 // If arg is on the stack then place it otherwise it is already in correct reg.
1102 if (dst.first()->is_stack()) {
1103 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1104 }
1105 }
1106
1107 #endif // _LP64
1108
1109 // Now versions that are common to 32/64 bit
1110
1111 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1112 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1113 }
1114
1115 void MacroAssembler::addptr(Register dst, Register src) {
1116 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1117 }
1118
1119 void MacroAssembler::addptr(Address dst, Register src) {
1120 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1121 }
1122
1123 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1124 assert(rscratch != noreg || always_reachable(src), "missing");
1125
1126 if (reachable(src)) {
1127 Assembler::addsd(dst, as_Address(src));
1128 } else {
1129 lea(rscratch, src);
1130 Assembler::addsd(dst, Address(rscratch, 0));
1131 }
1132 }
1133
1134 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1135 assert(rscratch != noreg || always_reachable(src), "missing");
1136
1137 if (reachable(src)) {
1138 addss(dst, as_Address(src));
1139 } else {
1140 lea(rscratch, src);
1141 addss(dst, Address(rscratch, 0));
1142 }
1143 }
1144
1145 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1146 assert(rscratch != noreg || always_reachable(src), "missing");
1147
1148 if (reachable(src)) {
1149 Assembler::addpd(dst, as_Address(src));
1150 } else {
1151 lea(rscratch, src);
1152 Assembler::addpd(dst, Address(rscratch, 0));
1153 }
1154 }
1155
1156 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1157 // Stub code is generated once and never copied.
1158 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1159 void MacroAssembler::align64() {
1160 align(64, (uint)(uintptr_t)pc());
1161 }
1162
1163 void MacroAssembler::align32() {
1164 align(32, (uint)(uintptr_t)pc());
1165 }
1166
1167 void MacroAssembler::align(uint modulus) {
1168 // 8273459: Ensure alignment is possible with current segment alignment
1169 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1170 align(modulus, offset());
1171 }
1172
1173 void MacroAssembler::align(uint modulus, uint target) {
1174 if (target % modulus != 0) {
1175 nop(modulus - (target % modulus));
1176 }
1177 }
1178
1179 void MacroAssembler::push_f(XMMRegister r) {
1180 subptr(rsp, wordSize);
1181 movflt(Address(rsp, 0), r);
1182 }
1183
1184 void MacroAssembler::pop_f(XMMRegister r) {
1185 movflt(r, Address(rsp, 0));
1186 addptr(rsp, wordSize);
1187 }
1188
1189 void MacroAssembler::push_d(XMMRegister r) {
1190 subptr(rsp, 2 * wordSize);
1191 movdbl(Address(rsp, 0), r);
1192 }
1193
1194 void MacroAssembler::pop_d(XMMRegister r) {
1195 movdbl(r, Address(rsp, 0));
1196 addptr(rsp, 2 * Interpreter::stackElementSize);
1197 }
1198
1199 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1200 // Used in sign-masking with aligned address.
1201 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1202 assert(rscratch != noreg || always_reachable(src), "missing");
1203
1204 if (UseAVX > 2 &&
1205 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
1206 (dst->encoding() >= 16)) {
1207 vpand(dst, dst, src, AVX_512bit, rscratch);
1208 } else if (reachable(src)) {
1209 Assembler::andpd(dst, as_Address(src));
1210 } else {
1211 lea(rscratch, src);
1212 Assembler::andpd(dst, Address(rscratch, 0));
1213 }
1214 }
1215
1216 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1217 // Used in sign-masking with aligned address.
1218 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1219 assert(rscratch != noreg || always_reachable(src), "missing");
1220
1221 if (reachable(src)) {
1222 Assembler::andps(dst, as_Address(src));
1223 } else {
1224 lea(rscratch, src);
1225 Assembler::andps(dst, Address(rscratch, 0));
1226 }
1227 }
1228
1229 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1230 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1231 }
1232
1233 #ifdef _LP64
1234 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1235 assert(rscratch != noreg || always_reachable(src), "missing");
1236
1237 if (reachable(src)) {
1238 andq(dst, as_Address(src));
1239 } else {
1240 lea(rscratch, src);
1241 andq(dst, Address(rscratch, 0));
1242 }
1243 }
1244 #endif
1245
1246 void MacroAssembler::atomic_incl(Address counter_addr) {
1247 lock();
1248 incrementl(counter_addr);
1249 }
1250
1251 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1252 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1253
1254 if (reachable(counter_addr)) {
1255 atomic_incl(as_Address(counter_addr));
1256 } else {
1257 lea(rscratch, counter_addr);
1258 atomic_incl(Address(rscratch, 0));
1259 }
1260 }
1261
1262 #ifdef _LP64
1263 void MacroAssembler::atomic_incq(Address counter_addr) {
1264 lock();
1265 incrementq(counter_addr);
1266 }
1267
1268 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1269 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1270
1271 if (reachable(counter_addr)) {
1272 atomic_incq(as_Address(counter_addr));
1273 } else {
1274 lea(rscratch, counter_addr);
1275 atomic_incq(Address(rscratch, 0));
1276 }
1277 }
1278 #endif
1279
1280 // Writes to stack successive pages until offset reached to check for
1281 // stack overflow + shadow pages. This clobbers tmp.
1282 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1283 movptr(tmp, rsp);
1284 // Bang stack for total size given plus shadow page size.
1285 // Bang one page at a time because large size can bang beyond yellow and
1286 // red zones.
1287 Label loop;
1288 bind(loop);
1289 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1290 subptr(tmp, (int)os::vm_page_size());
1291 subl(size, (int)os::vm_page_size());
1292 jcc(Assembler::greater, loop);
1293
1294 // Bang down shadow pages too.
1295 // At this point, (tmp-0) is the last address touched, so don't
1296 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1297 // was post-decremented.) Skip this address by starting at i=1, and
1298 // touch a few more pages below. N.B. It is important to touch all
1299 // the way down including all pages in the shadow zone.
1300 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1301 // this could be any sized move but this is can be a debugging crumb
1302 // so the bigger the better.
1303 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1304 }
1305 }
1306
1307 void MacroAssembler::reserved_stack_check() {
1308 // testing if reserved zone needs to be enabled
1309 Label no_reserved_zone_enabling;
1310 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1311 NOT_LP64(get_thread(rsi);)
1312
1313 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1314 jcc(Assembler::below, no_reserved_zone_enabling);
1315
1316 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1317 jump(RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
1318 should_not_reach_here();
1319
1320 bind(no_reserved_zone_enabling);
1321 }
1322
1323 void MacroAssembler::c2bool(Register x) {
1324 // implements x == 0 ? 0 : 1
1325 // note: must only look at least-significant byte of x
1326 // since C-style booleans are stored in one byte
1327 // only! (was bug)
1328 andl(x, 0xFF);
1329 setb(Assembler::notZero, x);
1330 }
1331
1332 // Wouldn't need if AddressLiteral version had new name
1333 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1334 Assembler::call(L, rtype);
1335 }
1336
1337 void MacroAssembler::call(Register entry) {
1338 Assembler::call(entry);
1339 }
1340
1341 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1342 assert(rscratch != noreg || always_reachable(entry), "missing");
1343
1344 if (reachable(entry)) {
1345 Assembler::call_literal(entry.target(), entry.rspec());
1346 } else {
1347 lea(rscratch, entry);
1348 Assembler::call(rscratch);
1349 }
1350 }
1351
1352 void MacroAssembler::ic_call(address entry, jint method_index) {
1353 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1354 #ifdef _LP64
1355 // Needs full 64-bit immediate for later patching.
1356 mov64(rax, (int64_t)Universe::non_oop_word());
1357 #else
1358 movptr(rax, (intptr_t)Universe::non_oop_word());
1359 #endif
1360 call(AddressLiteral(entry, rh));
1361 }
1362
1363 int MacroAssembler::ic_check_size() {
1364 return
1365 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1366 }
1367
1368 int MacroAssembler::ic_check(int end_alignment) {
1369 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1370 Register data = rax;
1371 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1372
1373 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1374 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1375 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1376 // before the inline cache check here, and not after
1377 align(end_alignment, offset() + ic_check_size());
1378
1379 int uep_offset = offset();
1380
1381 #ifdef _LP64
1382 if (UseCompactObjectHeaders) {
1383 load_narrow_klass_compact(temp, receiver);
1384 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1385 } else
1386 #endif
1387 if (UseCompressedClassPointers) {
1388 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1389 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1390 } else {
1391 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1392 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1393 }
1394
1395 // if inline cache check fails, then jump to runtime routine
1396 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1397 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1398
1399 return uep_offset;
1400 }
1401
1402 void MacroAssembler::emit_static_call_stub() {
1403 // Static stub relocation also tags the Method* in the code-stream.
1404 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1405 // This is recognized as unresolved by relocs/nativeinst/ic code.
1406 jump(RuntimeAddress(pc()));
1407 }
1408
1409 // Implementation of call_VM versions
1410
1411 void MacroAssembler::call_VM(Register oop_result,
1412 address entry_point,
1413 bool check_exceptions) {
1414 Label C, E;
1415 call(C, relocInfo::none);
1416 jmp(E);
1417
1418 bind(C);
1419 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1420 ret(0);
1421
1422 bind(E);
1423 }
1424
1425 void MacroAssembler::call_VM(Register oop_result,
1426 address entry_point,
1427 Register arg_1,
1428 bool check_exceptions) {
1429 Label C, E;
1430 call(C, relocInfo::none);
1431 jmp(E);
1432
1433 bind(C);
1434 pass_arg1(this, arg_1);
1435 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1436 ret(0);
1437
1438 bind(E);
1439 }
1440
1441 void MacroAssembler::call_VM(Register oop_result,
1442 address entry_point,
1443 Register arg_1,
1444 Register arg_2,
1445 bool check_exceptions) {
1446 Label C, E;
1447 call(C, relocInfo::none);
1448 jmp(E);
1449
1450 bind(C);
1451
1452 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1453
1454 pass_arg2(this, arg_2);
1455 pass_arg1(this, arg_1);
1456 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1457 ret(0);
1458
1459 bind(E);
1460 }
1461
1462 void MacroAssembler::call_VM(Register oop_result,
1463 address entry_point,
1464 Register arg_1,
1465 Register arg_2,
1466 Register arg_3,
1467 bool check_exceptions) {
1468 Label C, E;
1469 call(C, relocInfo::none);
1470 jmp(E);
1471
1472 bind(C);
1473
1474 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1475 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1476 pass_arg3(this, arg_3);
1477 pass_arg2(this, arg_2);
1478 pass_arg1(this, arg_1);
1479 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1480 ret(0);
1481
1482 bind(E);
1483 }
1484
1485 void MacroAssembler::call_VM(Register oop_result,
1486 Register last_java_sp,
1487 address entry_point,
1488 int number_of_arguments,
1489 bool check_exceptions) {
1490 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1491 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1492 }
1493
1494 void MacroAssembler::call_VM(Register oop_result,
1495 Register last_java_sp,
1496 address entry_point,
1497 Register arg_1,
1498 bool check_exceptions) {
1499 pass_arg1(this, arg_1);
1500 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1501 }
1502
1503 void MacroAssembler::call_VM(Register oop_result,
1504 Register last_java_sp,
1505 address entry_point,
1506 Register arg_1,
1507 Register arg_2,
1508 bool check_exceptions) {
1509
1510 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1511 pass_arg2(this, arg_2);
1512 pass_arg1(this, arg_1);
1513 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1514 }
1515
1516 void MacroAssembler::call_VM(Register oop_result,
1517 Register last_java_sp,
1518 address entry_point,
1519 Register arg_1,
1520 Register arg_2,
1521 Register arg_3,
1522 bool check_exceptions) {
1523 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1524 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1525 pass_arg3(this, arg_3);
1526 pass_arg2(this, arg_2);
1527 pass_arg1(this, arg_1);
1528 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1529 }
1530
1531 void MacroAssembler::super_call_VM(Register oop_result,
1532 Register last_java_sp,
1533 address entry_point,
1534 int number_of_arguments,
1535 bool check_exceptions) {
1536 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1537 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1538 }
1539
1540 void MacroAssembler::super_call_VM(Register oop_result,
1541 Register last_java_sp,
1542 address entry_point,
1543 Register arg_1,
1544 bool check_exceptions) {
1545 pass_arg1(this, arg_1);
1546 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1547 }
1548
1549 void MacroAssembler::super_call_VM(Register oop_result,
1550 Register last_java_sp,
1551 address entry_point,
1552 Register arg_1,
1553 Register arg_2,
1554 bool check_exceptions) {
1555
1556 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1557 pass_arg2(this, arg_2);
1558 pass_arg1(this, arg_1);
1559 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1560 }
1561
1562 void MacroAssembler::super_call_VM(Register oop_result,
1563 Register last_java_sp,
1564 address entry_point,
1565 Register arg_1,
1566 Register arg_2,
1567 Register arg_3,
1568 bool check_exceptions) {
1569 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1570 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1571 pass_arg3(this, arg_3);
1572 pass_arg2(this, arg_2);
1573 pass_arg1(this, arg_1);
1574 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1575 }
1576
1577 void MacroAssembler::call_VM_base(Register oop_result,
1578 Register java_thread,
1579 Register last_java_sp,
1580 address entry_point,
1581 int number_of_arguments,
1582 bool check_exceptions) {
1583 // determine java_thread register
1584 if (!java_thread->is_valid()) {
1585 #ifdef _LP64
1586 java_thread = r15_thread;
1587 #else
1588 java_thread = rdi;
1589 get_thread(java_thread);
1590 #endif // LP64
1591 }
1592 // determine last_java_sp register
1593 if (!last_java_sp->is_valid()) {
1594 last_java_sp = rsp;
1595 }
1596 // debugging support
1597 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1598 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1599 #ifdef ASSERT
1600 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1601 // r12 is the heapbase.
1602 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1603 #endif // ASSERT
1604
1605 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1606 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1607
1608 // push java thread (becomes first argument of C function)
1609
1610 NOT_LP64(push(java_thread); number_of_arguments++);
1611 LP64_ONLY(mov(c_rarg0, r15_thread));
1612
1613 // set last Java frame before call
1614 assert(last_java_sp != rbp, "can't use ebp/rbp");
1615
1616 // Only interpreter should have to set fp
1617 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1618
1619 // do the call, remove parameters
1620 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1621
1622 // restore the thread (cannot use the pushed argument since arguments
1623 // may be overwritten by C code generated by an optimizing compiler);
1624 // however can use the register value directly if it is callee saved.
1625 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1626 // rdi & rsi (also r15) are callee saved -> nothing to do
1627 #ifdef ASSERT
1628 guarantee(java_thread != rax, "change this code");
1629 push(rax);
1630 { Label L;
1631 get_thread(rax);
1632 cmpptr(java_thread, rax);
1633 jcc(Assembler::equal, L);
1634 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1635 bind(L);
1636 }
1637 pop(rax);
1638 #endif
1639 } else {
1640 get_thread(java_thread);
1641 }
1642 // reset last Java frame
1643 // Only interpreter should have to clear fp
1644 reset_last_Java_frame(java_thread, true);
1645
1646 // C++ interp handles this in the interpreter
1647 check_and_handle_popframe(java_thread);
1648 check_and_handle_earlyret(java_thread);
1649
1650 if (check_exceptions) {
1651 // check for pending exceptions (java_thread is set upon return)
1652 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1653 #ifndef _LP64
1654 jump_cc(Assembler::notEqual,
1655 RuntimeAddress(StubRoutines::forward_exception_entry()));
1656 #else
1657 // This used to conditionally jump to forward_exception however it is
1658 // possible if we relocate that the branch will not reach. So we must jump
1659 // around so we can always reach
1660
1661 Label ok;
1662 jcc(Assembler::equal, ok);
1663 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1664 bind(ok);
1665 #endif // LP64
1666 }
1667
1668 // get oop result if there is one and reset the value in the thread
1669 if (oop_result->is_valid()) {
1670 get_vm_result(oop_result, java_thread);
1671 }
1672 }
1673
1674 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1675
1676 // Calculate the value for last_Java_sp
1677 // somewhat subtle. call_VM does an intermediate call
1678 // which places a return address on the stack just under the
1679 // stack pointer as the user finished with it. This allows
1680 // use to retrieve last_Java_pc from last_Java_sp[-1].
1681 // On 32bit we then have to push additional args on the stack to accomplish
1682 // the actual requested call. On 64bit call_VM only can use register args
1683 // so the only extra space is the return address that call_VM created.
1684 // This hopefully explains the calculations here.
1685
1686 #ifdef _LP64
1687 // We've pushed one address, correct last_Java_sp
1688 lea(rax, Address(rsp, wordSize));
1689 #else
1690 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1691 #endif // LP64
1692
1693 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1694
1695 }
1696
1697 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1698 void MacroAssembler::call_VM_leaf0(address entry_point) {
1699 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1700 }
1701
1702 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1703 call_VM_leaf_base(entry_point, number_of_arguments);
1704 }
1705
1706 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1707 pass_arg0(this, arg_0);
1708 call_VM_leaf(entry_point, 1);
1709 }
1710
1711 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1712
1713 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1714 pass_arg1(this, arg_1);
1715 pass_arg0(this, arg_0);
1716 call_VM_leaf(entry_point, 2);
1717 }
1718
1719 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1720 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1721 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1729 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1730 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1731 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1732 pass_arg3(this, arg_3);
1733 pass_arg2(this, arg_2);
1734 pass_arg1(this, arg_1);
1735 pass_arg0(this, arg_0);
1736 call_VM_leaf(entry_point, 3);
1737 }
1738
1739 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1740 pass_arg0(this, arg_0);
1741 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1742 }
1743
1744 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1745 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1746 pass_arg1(this, arg_1);
1747 pass_arg0(this, arg_0);
1748 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1749 }
1750
1751 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1752 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1753 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1754 pass_arg2(this, arg_2);
1755 pass_arg1(this, arg_1);
1756 pass_arg0(this, arg_0);
1757 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1758 }
1759
1760 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1761 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1762 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1763 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1764 pass_arg3(this, arg_3);
1765 pass_arg2(this, arg_2);
1766 pass_arg1(this, arg_1);
1767 pass_arg0(this, arg_0);
1768 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1769 }
1770
1771 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1772 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1773 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1774 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1775 }
1776
1777 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1778 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1779 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1780 }
1781
1782 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1783 }
1784
1785 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1786 }
1787
1788 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1789 assert(rscratch != noreg || always_reachable(src1), "missing");
1790
1791 if (reachable(src1)) {
1792 cmpl(as_Address(src1), imm);
1793 } else {
1794 lea(rscratch, src1);
1795 cmpl(Address(rscratch, 0), imm);
1796 }
1797 }
1798
1799 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1800 assert(!src2.is_lval(), "use cmpptr");
1801 assert(rscratch != noreg || always_reachable(src2), "missing");
1802
1803 if (reachable(src2)) {
1804 cmpl(src1, as_Address(src2));
1805 } else {
1806 lea(rscratch, src2);
1807 cmpl(src1, Address(rscratch, 0));
1808 }
1809 }
1810
1811 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1812 Assembler::cmpl(src1, imm);
1813 }
1814
1815 void MacroAssembler::cmp32(Register src1, Address src2) {
1816 Assembler::cmpl(src1, src2);
1817 }
1818
1819 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1820 ucomisd(opr1, opr2);
1821
1822 Label L;
1823 if (unordered_is_less) {
1824 movl(dst, -1);
1825 jcc(Assembler::parity, L);
1826 jcc(Assembler::below , L);
1827 movl(dst, 0);
1828 jcc(Assembler::equal , L);
1829 increment(dst);
1830 } else { // unordered is greater
1831 movl(dst, 1);
1832 jcc(Assembler::parity, L);
1833 jcc(Assembler::above , L);
1834 movl(dst, 0);
1835 jcc(Assembler::equal , L);
1836 decrementl(dst);
1837 }
1838 bind(L);
1839 }
1840
1841 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1842 ucomiss(opr1, opr2);
1843
1844 Label L;
1845 if (unordered_is_less) {
1846 movl(dst, -1);
1847 jcc(Assembler::parity, L);
1848 jcc(Assembler::below , L);
1849 movl(dst, 0);
1850 jcc(Assembler::equal , L);
1851 increment(dst);
1852 } else { // unordered is greater
1853 movl(dst, 1);
1854 jcc(Assembler::parity, L);
1855 jcc(Assembler::above , L);
1856 movl(dst, 0);
1857 jcc(Assembler::equal , L);
1858 decrementl(dst);
1859 }
1860 bind(L);
1861 }
1862
1863
1864 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1865 assert(rscratch != noreg || always_reachable(src1), "missing");
1866
1867 if (reachable(src1)) {
1868 cmpb(as_Address(src1), imm);
1869 } else {
1870 lea(rscratch, src1);
1871 cmpb(Address(rscratch, 0), imm);
1872 }
1873 }
1874
1875 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1876 #ifdef _LP64
1877 assert(rscratch != noreg || always_reachable(src2), "missing");
1878
1879 if (src2.is_lval()) {
1880 movptr(rscratch, src2);
1881 Assembler::cmpq(src1, rscratch);
1882 } else if (reachable(src2)) {
1883 cmpq(src1, as_Address(src2));
1884 } else {
1885 lea(rscratch, src2);
1886 Assembler::cmpq(src1, Address(rscratch, 0));
1887 }
1888 #else
1889 assert(rscratch == noreg, "not needed");
1890 if (src2.is_lval()) {
1891 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1892 } else {
1893 cmpl(src1, as_Address(src2));
1894 }
1895 #endif // _LP64
1896 }
1897
1898 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1899 assert(src2.is_lval(), "not a mem-mem compare");
1900 #ifdef _LP64
1901 // moves src2's literal address
1902 movptr(rscratch, src2);
1903 Assembler::cmpq(src1, rscratch);
1904 #else
1905 assert(rscratch == noreg, "not needed");
1906 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1907 #endif // _LP64
1908 }
1909
1910 void MacroAssembler::cmpoop(Register src1, Register src2) {
1911 cmpptr(src1, src2);
1912 }
1913
1914 void MacroAssembler::cmpoop(Register src1, Address src2) {
1915 cmpptr(src1, src2);
1916 }
1917
1918 #ifdef _LP64
1919 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1920 movoop(rscratch, src2);
1921 cmpptr(src1, rscratch);
1922 }
1923 #endif
1924
1925 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1926 assert(rscratch != noreg || always_reachable(adr), "missing");
1927
1928 if (reachable(adr)) {
1929 lock();
1930 cmpxchgptr(reg, as_Address(adr));
1931 } else {
1932 lea(rscratch, adr);
1933 lock();
1934 cmpxchgptr(reg, Address(rscratch, 0));
1935 }
1936 }
1937
1938 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1939 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1940 }
1941
1942 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1943 assert(rscratch != noreg || always_reachable(src), "missing");
1944
1945 if (reachable(src)) {
1946 Assembler::comisd(dst, as_Address(src));
1947 } else {
1948 lea(rscratch, src);
1949 Assembler::comisd(dst, Address(rscratch, 0));
1950 }
1951 }
1952
1953 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1954 assert(rscratch != noreg || always_reachable(src), "missing");
1955
1956 if (reachable(src)) {
1957 Assembler::comiss(dst, as_Address(src));
1958 } else {
1959 lea(rscratch, src);
1960 Assembler::comiss(dst, Address(rscratch, 0));
1961 }
1962 }
1963
1964
1965 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1966 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1967
1968 Condition negated_cond = negate_condition(cond);
1969 Label L;
1970 jcc(negated_cond, L);
1971 pushf(); // Preserve flags
1972 atomic_incl(counter_addr, rscratch);
1973 popf();
1974 bind(L);
1975 }
1976
1977 int MacroAssembler::corrected_idivl(Register reg) {
1978 // Full implementation of Java idiv and irem; checks for
1979 // special case as described in JVM spec., p.243 & p.271.
1980 // The function returns the (pc) offset of the idivl
1981 // instruction - may be needed for implicit exceptions.
1982 //
1983 // normal case special case
1984 //
1985 // input : rax,: dividend min_int
1986 // reg: divisor (may not be rax,/rdx) -1
1987 //
1988 // output: rax,: quotient (= rax, idiv reg) min_int
1989 // rdx: remainder (= rax, irem reg) 0
1990 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1991 const int min_int = 0x80000000;
1992 Label normal_case, special_case;
1993
1994 // check for special case
1995 cmpl(rax, min_int);
1996 jcc(Assembler::notEqual, normal_case);
1997 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1998 cmpl(reg, -1);
1999 jcc(Assembler::equal, special_case);
2000
2001 // handle normal case
2002 bind(normal_case);
2003 cdql();
2004 int idivl_offset = offset();
2005 idivl(reg);
2006
2007 // normal and special case exit
2008 bind(special_case);
2009
2010 return idivl_offset;
2011 }
2012
2013
2014
2015 void MacroAssembler::decrementl(Register reg, int value) {
2016 if (value == min_jint) {subl(reg, value) ; return; }
2017 if (value < 0) { incrementl(reg, -value); return; }
2018 if (value == 0) { ; return; }
2019 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2020 /* else */ { subl(reg, value) ; return; }
2021 }
2022
2023 void MacroAssembler::decrementl(Address dst, int value) {
2024 if (value == min_jint) {subl(dst, value) ; return; }
2025 if (value < 0) { incrementl(dst, -value); return; }
2026 if (value == 0) { ; return; }
2027 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2028 /* else */ { subl(dst, value) ; return; }
2029 }
2030
2031 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2032 assert(shift_value > 0, "illegal shift value");
2033 Label _is_positive;
2034 testl (reg, reg);
2035 jcc (Assembler::positive, _is_positive);
2036 int offset = (1 << shift_value) - 1 ;
2037
2038 if (offset == 1) {
2039 incrementl(reg);
2040 } else {
2041 addl(reg, offset);
2042 }
2043
2044 bind (_is_positive);
2045 sarl(reg, shift_value);
2046 }
2047
2048 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2049 assert(rscratch != noreg || always_reachable(src), "missing");
2050
2051 if (reachable(src)) {
2052 Assembler::divsd(dst, as_Address(src));
2053 } else {
2054 lea(rscratch, src);
2055 Assembler::divsd(dst, Address(rscratch, 0));
2056 }
2057 }
2058
2059 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2060 assert(rscratch != noreg || always_reachable(src), "missing");
2061
2062 if (reachable(src)) {
2063 Assembler::divss(dst, as_Address(src));
2064 } else {
2065 lea(rscratch, src);
2066 Assembler::divss(dst, Address(rscratch, 0));
2067 }
2068 }
2069
2070 void MacroAssembler::enter() {
2071 push(rbp);
2072 mov(rbp, rsp);
2073 }
2074
2075 void MacroAssembler::post_call_nop() {
2076 if (!Continuations::enabled()) {
2077 return;
2078 }
2079 InstructionMark im(this);
2080 relocate(post_call_nop_Relocation::spec());
2081 InlineSkippedInstructionsCounter skipCounter(this);
2082 emit_int8((uint8_t)0x0f);
2083 emit_int8((uint8_t)0x1f);
2084 emit_int8((uint8_t)0x84);
2085 emit_int8((uint8_t)0x00);
2086 emit_int32(0x00);
2087 }
2088
2089 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2090 void MacroAssembler::fat_nop() {
2091 if (UseAddressNop) {
2092 addr_nop_5();
2093 } else {
2094 emit_int8((uint8_t)0x26); // es:
2095 emit_int8((uint8_t)0x2e); // cs:
2096 emit_int8((uint8_t)0x64); // fs:
2097 emit_int8((uint8_t)0x65); // gs:
2098 emit_int8((uint8_t)0x90);
2099 }
2100 }
2101
2102 #ifndef _LP64
2103 void MacroAssembler::fcmp(Register tmp) {
2104 fcmp(tmp, 1, true, true);
2105 }
2106
2107 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2108 assert(!pop_right || pop_left, "usage error");
2109 if (VM_Version::supports_cmov()) {
2110 assert(tmp == noreg, "unneeded temp");
2111 if (pop_left) {
2112 fucomip(index);
2113 } else {
2114 fucomi(index);
2115 }
2116 if (pop_right) {
2117 fpop();
2118 }
2119 } else {
2120 assert(tmp != noreg, "need temp");
2121 if (pop_left) {
2122 if (pop_right) {
2123 fcompp();
2124 } else {
2125 fcomp(index);
2126 }
2127 } else {
2128 fcom(index);
2129 }
2130 // convert FPU condition into eflags condition via rax,
2131 save_rax(tmp);
2132 fwait(); fnstsw_ax();
2133 sahf();
2134 restore_rax(tmp);
2135 }
2136 // condition codes set as follows:
2137 //
2138 // CF (corresponds to C0) if x < y
2139 // PF (corresponds to C2) if unordered
2140 // ZF (corresponds to C3) if x = y
2141 }
2142
2143 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2144 fcmp2int(dst, unordered_is_less, 1, true, true);
2145 }
2146
2147 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2148 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2149 Label L;
2150 if (unordered_is_less) {
2151 movl(dst, -1);
2152 jcc(Assembler::parity, L);
2153 jcc(Assembler::below , L);
2154 movl(dst, 0);
2155 jcc(Assembler::equal , L);
2156 increment(dst);
2157 } else { // unordered is greater
2158 movl(dst, 1);
2159 jcc(Assembler::parity, L);
2160 jcc(Assembler::above , L);
2161 movl(dst, 0);
2162 jcc(Assembler::equal , L);
2163 decrementl(dst);
2164 }
2165 bind(L);
2166 }
2167
2168 void MacroAssembler::fld_d(AddressLiteral src) {
2169 fld_d(as_Address(src));
2170 }
2171
2172 void MacroAssembler::fld_s(AddressLiteral src) {
2173 fld_s(as_Address(src));
2174 }
2175
2176 void MacroAssembler::fldcw(AddressLiteral src) {
2177 fldcw(as_Address(src));
2178 }
2179
2180 void MacroAssembler::fpop() {
2181 ffree();
2182 fincstp();
2183 }
2184
2185 void MacroAssembler::fremr(Register tmp) {
2186 save_rax(tmp);
2187 { Label L;
2188 bind(L);
2189 fprem();
2190 fwait(); fnstsw_ax();
2191 sahf();
2192 jcc(Assembler::parity, L);
2193 }
2194 restore_rax(tmp);
2195 // Result is in ST0.
2196 // Note: fxch & fpop to get rid of ST1
2197 // (otherwise FPU stack could overflow eventually)
2198 fxch(1);
2199 fpop();
2200 }
2201
2202 void MacroAssembler::empty_FPU_stack() {
2203 if (VM_Version::supports_mmx()) {
2204 emms();
2205 } else {
2206 for (int i = 8; i-- > 0; ) ffree(i);
2207 }
2208 }
2209 #endif // !LP64
2210
2211 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2212 assert(rscratch != noreg || always_reachable(src), "missing");
2213 if (reachable(src)) {
2214 Assembler::mulpd(dst, as_Address(src));
2215 } else {
2216 lea(rscratch, src);
2217 Assembler::mulpd(dst, Address(rscratch, 0));
2218 }
2219 }
2220
2221 void MacroAssembler::load_float(Address src) {
2222 #ifdef _LP64
2223 movflt(xmm0, src);
2224 #else
2225 if (UseSSE >= 1) {
2226 movflt(xmm0, src);
2227 } else {
2228 fld_s(src);
2229 }
2230 #endif // LP64
2231 }
2232
2233 void MacroAssembler::store_float(Address dst) {
2234 #ifdef _LP64
2235 movflt(dst, xmm0);
2236 #else
2237 if (UseSSE >= 1) {
2238 movflt(dst, xmm0);
2239 } else {
2240 fstp_s(dst);
2241 }
2242 #endif // LP64
2243 }
2244
2245 void MacroAssembler::load_double(Address src) {
2246 #ifdef _LP64
2247 movdbl(xmm0, src);
2248 #else
2249 if (UseSSE >= 2) {
2250 movdbl(xmm0, src);
2251 } else {
2252 fld_d(src);
2253 }
2254 #endif // LP64
2255 }
2256
2257 void MacroAssembler::store_double(Address dst) {
2258 #ifdef _LP64
2259 movdbl(dst, xmm0);
2260 #else
2261 if (UseSSE >= 2) {
2262 movdbl(dst, xmm0);
2263 } else {
2264 fstp_d(dst);
2265 }
2266 #endif // LP64
2267 }
2268
2269 // dst = c = a * b + c
2270 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2271 Assembler::vfmadd231sd(c, a, b);
2272 if (dst != c) {
2273 movdbl(dst, c);
2274 }
2275 }
2276
2277 // dst = c = a * b + c
2278 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2279 Assembler::vfmadd231ss(c, a, b);
2280 if (dst != c) {
2281 movflt(dst, c);
2282 }
2283 }
2284
2285 // dst = c = a * b + c
2286 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2287 Assembler::vfmadd231pd(c, a, b, vector_len);
2288 if (dst != c) {
2289 vmovdqu(dst, c);
2290 }
2291 }
2292
2293 // dst = c = a * b + c
2294 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2295 Assembler::vfmadd231ps(c, a, b, vector_len);
2296 if (dst != c) {
2297 vmovdqu(dst, c);
2298 }
2299 }
2300
2301 // dst = c = a * b + c
2302 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2303 Assembler::vfmadd231pd(c, a, b, vector_len);
2304 if (dst != c) {
2305 vmovdqu(dst, c);
2306 }
2307 }
2308
2309 // dst = c = a * b + c
2310 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2311 Assembler::vfmadd231ps(c, a, b, vector_len);
2312 if (dst != c) {
2313 vmovdqu(dst, c);
2314 }
2315 }
2316
2317 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2318 assert(rscratch != noreg || always_reachable(dst), "missing");
2319
2320 if (reachable(dst)) {
2321 incrementl(as_Address(dst));
2322 } else {
2323 lea(rscratch, dst);
2324 incrementl(Address(rscratch, 0));
2325 }
2326 }
2327
2328 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2329 incrementl(as_Address(dst, rscratch));
2330 }
2331
2332 void MacroAssembler::incrementl(Register reg, int value) {
2333 if (value == min_jint) {addl(reg, value) ; return; }
2334 if (value < 0) { decrementl(reg, -value); return; }
2335 if (value == 0) { ; return; }
2336 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2337 /* else */ { addl(reg, value) ; return; }
2338 }
2339
2340 void MacroAssembler::incrementl(Address dst, int value) {
2341 if (value == min_jint) {addl(dst, value) ; return; }
2342 if (value < 0) { decrementl(dst, -value); return; }
2343 if (value == 0) { ; return; }
2344 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2345 /* else */ { addl(dst, value) ; return; }
2346 }
2347
2348 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2349 assert(rscratch != noreg || always_reachable(dst), "missing");
2350 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump");
2351 if (reachable(dst)) {
2352 jmp_literal(dst.target(), dst.rspec());
2353 } else {
2354 lea(rscratch, dst);
2355 jmp(rscratch);
2356 }
2357 }
2358
2359 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2360 assert(rscratch != noreg || always_reachable(dst), "missing");
2361 assert(!dst.rspec().reloc()->is_data(), "should not use ExternalAddress for jump_cc");
2362 if (reachable(dst)) {
2363 InstructionMark im(this);
2364 relocate(dst.reloc());
2365 const int short_size = 2;
2366 const int long_size = 6;
2367 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2368 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2369 // 0111 tttn #8-bit disp
2370 emit_int8(0x70 | cc);
2371 emit_int8((offs - short_size) & 0xFF);
2372 } else {
2373 // 0000 1111 1000 tttn #32-bit disp
2374 emit_int8(0x0F);
2375 emit_int8((unsigned char)(0x80 | cc));
2376 emit_int32(offs - long_size);
2377 }
2378 } else {
2379 #ifdef ASSERT
2380 warning("reversing conditional branch");
2381 #endif /* ASSERT */
2382 Label skip;
2383 jccb(reverse[cc], skip);
2384 lea(rscratch, dst);
2385 Assembler::jmp(rscratch);
2386 bind(skip);
2387 }
2388 }
2389
2390 void MacroAssembler::cmp32_mxcsr_std(Address mxcsr_save, Register tmp, Register rscratch) {
2391 ExternalAddress mxcsr_std(StubRoutines::x86::addr_mxcsr_std());
2392 assert(rscratch != noreg || always_reachable(mxcsr_std), "missing");
2393
2394 stmxcsr(mxcsr_save);
2395 movl(tmp, mxcsr_save);
2396 if (EnableX86ECoreOpts) {
2397 // The mxcsr_std has status bits set for performance on ECore
2398 orl(tmp, 0x003f);
2399 } else {
2400 // Mask out status bits (only check control and mask bits)
2401 andl(tmp, 0xFFC0);
2402 }
2403 cmp32(tmp, mxcsr_std, rscratch);
2404 }
2405
2406 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2407 assert(rscratch != noreg || always_reachable(src), "missing");
2408
2409 if (reachable(src)) {
2410 Assembler::ldmxcsr(as_Address(src));
2411 } else {
2412 lea(rscratch, src);
2413 Assembler::ldmxcsr(Address(rscratch, 0));
2414 }
2415 }
2416
2417 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2418 int off;
2419 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2420 off = offset();
2421 movsbl(dst, src); // movsxb
2422 } else {
2423 off = load_unsigned_byte(dst, src);
2424 shll(dst, 24);
2425 sarl(dst, 24);
2426 }
2427 return off;
2428 }
2429
2430 // Note: load_signed_short used to be called load_signed_word.
2431 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2432 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2433 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2434 int MacroAssembler::load_signed_short(Register dst, Address src) {
2435 int off;
2436 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2437 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2438 // version but this is what 64bit has always done. This seems to imply
2439 // that users are only using 32bits worth.
2440 off = offset();
2441 movswl(dst, src); // movsxw
2442 } else {
2443 off = load_unsigned_short(dst, src);
2444 shll(dst, 16);
2445 sarl(dst, 16);
2446 }
2447 return off;
2448 }
2449
2450 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2451 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2452 // and "3.9 Partial Register Penalties", p. 22).
2453 int off;
2454 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2455 off = offset();
2456 movzbl(dst, src); // movzxb
2457 } else {
2458 xorl(dst, dst);
2459 off = offset();
2460 movb(dst, src);
2461 }
2462 return off;
2463 }
2464
2465 // Note: load_unsigned_short used to be called load_unsigned_word.
2466 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2467 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2468 // and "3.9 Partial Register Penalties", p. 22).
2469 int off;
2470 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2471 off = offset();
2472 movzwl(dst, src); // movzxw
2473 } else {
2474 xorl(dst, dst);
2475 off = offset();
2476 movw(dst, src);
2477 }
2478 return off;
2479 }
2480
2481 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2482 switch (size_in_bytes) {
2483 #ifndef _LP64
2484 case 8:
2485 assert(dst2 != noreg, "second dest register required");
2486 movl(dst, src);
2487 movl(dst2, src.plus_disp(BytesPerInt));
2488 break;
2489 #else
2490 case 8: movq(dst, src); break;
2491 #endif
2492 case 4: movl(dst, src); break;
2493 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2494 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2495 default: ShouldNotReachHere();
2496 }
2497 }
2498
2499 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2500 switch (size_in_bytes) {
2501 #ifndef _LP64
2502 case 8:
2503 assert(src2 != noreg, "second source register required");
2504 movl(dst, src);
2505 movl(dst.plus_disp(BytesPerInt), src2);
2506 break;
2507 #else
2508 case 8: movq(dst, src); break;
2509 #endif
2510 case 4: movl(dst, src); break;
2511 case 2: movw(dst, src); break;
2512 case 1: movb(dst, src); break;
2513 default: ShouldNotReachHere();
2514 }
2515 }
2516
2517 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2518 assert(rscratch != noreg || always_reachable(dst), "missing");
2519
2520 if (reachable(dst)) {
2521 movl(as_Address(dst), src);
2522 } else {
2523 lea(rscratch, dst);
2524 movl(Address(rscratch, 0), src);
2525 }
2526 }
2527
2528 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2529 if (reachable(src)) {
2530 movl(dst, as_Address(src));
2531 } else {
2532 lea(dst, src);
2533 movl(dst, Address(dst, 0));
2534 }
2535 }
2536
2537 // C++ bool manipulation
2538
2539 void MacroAssembler::movbool(Register dst, Address src) {
2540 if(sizeof(bool) == 1)
2541 movb(dst, src);
2542 else if(sizeof(bool) == 2)
2543 movw(dst, src);
2544 else if(sizeof(bool) == 4)
2545 movl(dst, src);
2546 else
2547 // unsupported
2548 ShouldNotReachHere();
2549 }
2550
2551 void MacroAssembler::movbool(Address dst, bool boolconst) {
2552 if(sizeof(bool) == 1)
2553 movb(dst, (int) boolconst);
2554 else if(sizeof(bool) == 2)
2555 movw(dst, (int) boolconst);
2556 else if(sizeof(bool) == 4)
2557 movl(dst, (int) boolconst);
2558 else
2559 // unsupported
2560 ShouldNotReachHere();
2561 }
2562
2563 void MacroAssembler::movbool(Address dst, Register src) {
2564 if(sizeof(bool) == 1)
2565 movb(dst, src);
2566 else if(sizeof(bool) == 2)
2567 movw(dst, src);
2568 else if(sizeof(bool) == 4)
2569 movl(dst, src);
2570 else
2571 // unsupported
2572 ShouldNotReachHere();
2573 }
2574
2575 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2576 assert(rscratch != noreg || always_reachable(src), "missing");
2577
2578 if (reachable(src)) {
2579 movdl(dst, as_Address(src));
2580 } else {
2581 lea(rscratch, src);
2582 movdl(dst, Address(rscratch, 0));
2583 }
2584 }
2585
2586 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2587 assert(rscratch != noreg || always_reachable(src), "missing");
2588
2589 if (reachable(src)) {
2590 movq(dst, as_Address(src));
2591 } else {
2592 lea(rscratch, src);
2593 movq(dst, Address(rscratch, 0));
2594 }
2595 }
2596
2597 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2598 assert(rscratch != noreg || always_reachable(src), "missing");
2599
2600 if (reachable(src)) {
2601 if (UseXmmLoadAndClearUpper) {
2602 movsd (dst, as_Address(src));
2603 } else {
2604 movlpd(dst, as_Address(src));
2605 }
2606 } else {
2607 lea(rscratch, src);
2608 if (UseXmmLoadAndClearUpper) {
2609 movsd (dst, Address(rscratch, 0));
2610 } else {
2611 movlpd(dst, Address(rscratch, 0));
2612 }
2613 }
2614 }
2615
2616 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2617 assert(rscratch != noreg || always_reachable(src), "missing");
2618
2619 if (reachable(src)) {
2620 movss(dst, as_Address(src));
2621 } else {
2622 lea(rscratch, src);
2623 movss(dst, Address(rscratch, 0));
2624 }
2625 }
2626
2627 void MacroAssembler::movptr(Register dst, Register src) {
2628 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movptr(Register dst, Address src) {
2632 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2633 }
2634
2635 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2636 void MacroAssembler::movptr(Register dst, intptr_t src) {
2637 #ifdef _LP64
2638 if (is_uimm32(src)) {
2639 movl(dst, checked_cast<uint32_t>(src));
2640 } else if (is_simm32(src)) {
2641 movq(dst, checked_cast<int32_t>(src));
2642 } else {
2643 mov64(dst, src);
2644 }
2645 #else
2646 movl(dst, src);
2647 #endif
2648 }
2649
2650 void MacroAssembler::movptr(Address dst, Register src) {
2651 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2652 }
2653
2654 void MacroAssembler::movptr(Address dst, int32_t src) {
2655 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2656 }
2657
2658 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2659 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2660 Assembler::movdqu(dst, src);
2661 }
2662
2663 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2664 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2665 Assembler::movdqu(dst, src);
2666 }
2667
2668 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2669 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2670 Assembler::movdqu(dst, src);
2671 }
2672
2673 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2674 assert(rscratch != noreg || always_reachable(src), "missing");
2675
2676 if (reachable(src)) {
2677 movdqu(dst, as_Address(src));
2678 } else {
2679 lea(rscratch, src);
2680 movdqu(dst, Address(rscratch, 0));
2681 }
2682 }
2683
2684 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2685 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2686 Assembler::vmovdqu(dst, src);
2687 }
2688
2689 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2690 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2691 Assembler::vmovdqu(dst, src);
2692 }
2693
2694 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2695 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2696 Assembler::vmovdqu(dst, src);
2697 }
2698
2699 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2700 assert(rscratch != noreg || always_reachable(src), "missing");
2701
2702 if (reachable(src)) {
2703 vmovdqu(dst, as_Address(src));
2704 }
2705 else {
2706 lea(rscratch, src);
2707 vmovdqu(dst, Address(rscratch, 0));
2708 }
2709 }
2710
2711 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2712 assert(rscratch != noreg || always_reachable(src), "missing");
2713
2714 if (vector_len == AVX_512bit) {
2715 evmovdquq(dst, src, AVX_512bit, rscratch);
2716 } else if (vector_len == AVX_256bit) {
2717 vmovdqu(dst, src, rscratch);
2718 } else {
2719 movdqu(dst, src, rscratch);
2720 }
2721 }
2722
2723 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src, int vector_len) {
2724 if (vector_len == AVX_512bit) {
2725 evmovdquq(dst, src, AVX_512bit);
2726 } else if (vector_len == AVX_256bit) {
2727 vmovdqu(dst, src);
2728 } else {
2729 movdqu(dst, src);
2730 }
2731 }
2732
2733 void MacroAssembler::vmovdqu(Address dst, XMMRegister src, int vector_len) {
2734 if (vector_len == AVX_512bit) {
2735 evmovdquq(dst, src, AVX_512bit);
2736 } else if (vector_len == AVX_256bit) {
2737 vmovdqu(dst, src);
2738 } else {
2739 movdqu(dst, src);
2740 }
2741 }
2742
2743 void MacroAssembler::vmovdqu(XMMRegister dst, Address src, int vector_len) {
2744 if (vector_len == AVX_512bit) {
2745 evmovdquq(dst, src, AVX_512bit);
2746 } else if (vector_len == AVX_256bit) {
2747 vmovdqu(dst, src);
2748 } else {
2749 movdqu(dst, src);
2750 }
2751 }
2752
2753 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2754 assert(rscratch != noreg || always_reachable(src), "missing");
2755
2756 if (reachable(src)) {
2757 vmovdqa(dst, as_Address(src));
2758 }
2759 else {
2760 lea(rscratch, src);
2761 vmovdqa(dst, Address(rscratch, 0));
2762 }
2763 }
2764
2765 void MacroAssembler::vmovdqa(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2766 assert(rscratch != noreg || always_reachable(src), "missing");
2767
2768 if (vector_len == AVX_512bit) {
2769 evmovdqaq(dst, src, AVX_512bit, rscratch);
2770 } else if (vector_len == AVX_256bit) {
2771 vmovdqa(dst, src, rscratch);
2772 } else {
2773 movdqa(dst, src, rscratch);
2774 }
2775 }
2776
2777 void MacroAssembler::kmov(KRegister dst, Address src) {
2778 if (VM_Version::supports_avx512bw()) {
2779 kmovql(dst, src);
2780 } else {
2781 assert(VM_Version::supports_evex(), "");
2782 kmovwl(dst, src);
2783 }
2784 }
2785
2786 void MacroAssembler::kmov(Address dst, KRegister src) {
2787 if (VM_Version::supports_avx512bw()) {
2788 kmovql(dst, src);
2789 } else {
2790 assert(VM_Version::supports_evex(), "");
2791 kmovwl(dst, src);
2792 }
2793 }
2794
2795 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2796 if (VM_Version::supports_avx512bw()) {
2797 kmovql(dst, src);
2798 } else {
2799 assert(VM_Version::supports_evex(), "");
2800 kmovwl(dst, src);
2801 }
2802 }
2803
2804 void MacroAssembler::kmov(Register dst, KRegister src) {
2805 if (VM_Version::supports_avx512bw()) {
2806 kmovql(dst, src);
2807 } else {
2808 assert(VM_Version::supports_evex(), "");
2809 kmovwl(dst, src);
2810 }
2811 }
2812
2813 void MacroAssembler::kmov(KRegister dst, Register src) {
2814 if (VM_Version::supports_avx512bw()) {
2815 kmovql(dst, src);
2816 } else {
2817 assert(VM_Version::supports_evex(), "");
2818 kmovwl(dst, src);
2819 }
2820 }
2821
2822 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2823 assert(rscratch != noreg || always_reachable(src), "missing");
2824
2825 if (reachable(src)) {
2826 kmovql(dst, as_Address(src));
2827 } else {
2828 lea(rscratch, src);
2829 kmovql(dst, Address(rscratch, 0));
2830 }
2831 }
2832
2833 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2834 assert(rscratch != noreg || always_reachable(src), "missing");
2835
2836 if (reachable(src)) {
2837 kmovwl(dst, as_Address(src));
2838 } else {
2839 lea(rscratch, src);
2840 kmovwl(dst, Address(rscratch, 0));
2841 }
2842 }
2843
2844 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2845 int vector_len, Register rscratch) {
2846 assert(rscratch != noreg || always_reachable(src), "missing");
2847
2848 if (reachable(src)) {
2849 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2850 } else {
2851 lea(rscratch, src);
2852 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2853 }
2854 }
2855
2856 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2857 int vector_len, Register rscratch) {
2858 assert(rscratch != noreg || always_reachable(src), "missing");
2859
2860 if (reachable(src)) {
2861 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2862 } else {
2863 lea(rscratch, src);
2864 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2865 }
2866 }
2867
2868 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2869 assert(rscratch != noreg || always_reachable(src), "missing");
2870
2871 if (reachable(src)) {
2872 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2873 } else {
2874 lea(rscratch, src);
2875 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2876 }
2877 }
2878
2879 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2880 assert(rscratch != noreg || always_reachable(src), "missing");
2881
2882 if (reachable(src)) {
2883 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2884 } else {
2885 lea(rscratch, src);
2886 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2887 }
2888 }
2889
2890 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2891 assert(rscratch != noreg || always_reachable(src), "missing");
2892
2893 if (reachable(src)) {
2894 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2895 } else {
2896 lea(rscratch, src);
2897 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2898 }
2899 }
2900
2901 void MacroAssembler::evmovdqaq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2902 assert(rscratch != noreg || always_reachable(src), "missing");
2903
2904 if (reachable(src)) {
2905 Assembler::evmovdqaq(dst, mask, as_Address(src), merge, vector_len);
2906 } else {
2907 lea(rscratch, src);
2908 Assembler::evmovdqaq(dst, mask, Address(rscratch, 0), merge, vector_len);
2909 }
2910 }
2911
2912 void MacroAssembler::evmovdqaq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2913 assert(rscratch != noreg || always_reachable(src), "missing");
2914
2915 if (reachable(src)) {
2916 Assembler::evmovdqaq(dst, as_Address(src), vector_len);
2917 } else {
2918 lea(rscratch, src);
2919 Assembler::evmovdqaq(dst, Address(rscratch, 0), vector_len);
2920 }
2921 }
2922
2923
2924 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2925 assert(rscratch != noreg || always_reachable(src), "missing");
2926
2927 if (reachable(src)) {
2928 Assembler::movdqa(dst, as_Address(src));
2929 } else {
2930 lea(rscratch, src);
2931 Assembler::movdqa(dst, Address(rscratch, 0));
2932 }
2933 }
2934
2935 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2936 assert(rscratch != noreg || always_reachable(src), "missing");
2937
2938 if (reachable(src)) {
2939 Assembler::movsd(dst, as_Address(src));
2940 } else {
2941 lea(rscratch, src);
2942 Assembler::movsd(dst, Address(rscratch, 0));
2943 }
2944 }
2945
2946 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2947 assert(rscratch != noreg || always_reachable(src), "missing");
2948
2949 if (reachable(src)) {
2950 Assembler::movss(dst, as_Address(src));
2951 } else {
2952 lea(rscratch, src);
2953 Assembler::movss(dst, Address(rscratch, 0));
2954 }
2955 }
2956
2957 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2958 assert(rscratch != noreg || always_reachable(src), "missing");
2959
2960 if (reachable(src)) {
2961 Assembler::movddup(dst, as_Address(src));
2962 } else {
2963 lea(rscratch, src);
2964 Assembler::movddup(dst, Address(rscratch, 0));
2965 }
2966 }
2967
2968 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2969 assert(rscratch != noreg || always_reachable(src), "missing");
2970
2971 if (reachable(src)) {
2972 Assembler::vmovddup(dst, as_Address(src), vector_len);
2973 } else {
2974 lea(rscratch, src);
2975 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2976 }
2977 }
2978
2979 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2980 assert(rscratch != noreg || always_reachable(src), "missing");
2981
2982 if (reachable(src)) {
2983 Assembler::mulsd(dst, as_Address(src));
2984 } else {
2985 lea(rscratch, src);
2986 Assembler::mulsd(dst, Address(rscratch, 0));
2987 }
2988 }
2989
2990 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2991 assert(rscratch != noreg || always_reachable(src), "missing");
2992
2993 if (reachable(src)) {
2994 Assembler::mulss(dst, as_Address(src));
2995 } else {
2996 lea(rscratch, src);
2997 Assembler::mulss(dst, Address(rscratch, 0));
2998 }
2999 }
3000
3001 void MacroAssembler::null_check(Register reg, int offset) {
3002 if (needs_explicit_null_check(offset)) {
3003 // provoke OS null exception if reg is null by
3004 // accessing M[reg] w/o changing any (non-CC) registers
3005 // NOTE: cmpl is plenty here to provoke a segv
3006 cmpptr(rax, Address(reg, 0));
3007 // Note: should probably use testl(rax, Address(reg, 0));
3008 // may be shorter code (however, this version of
3009 // testl needs to be implemented first)
3010 } else {
3011 // nothing to do, (later) access of M[reg + offset]
3012 // will provoke OS null exception if reg is null
3013 }
3014 }
3015
3016 void MacroAssembler::os_breakpoint() {
3017 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
3018 // (e.g., MSVC can't call ps() otherwise)
3019 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
3020 }
3021
3022 void MacroAssembler::unimplemented(const char* what) {
3023 const char* buf = nullptr;
3024 {
3025 ResourceMark rm;
3026 stringStream ss;
3027 ss.print("unimplemented: %s", what);
3028 buf = code_string(ss.as_string());
3029 }
3030 stop(buf);
3031 }
3032
3033 #ifdef _LP64
3034 #define XSTATE_BV 0x200
3035 #endif
3036
3037 void MacroAssembler::pop_CPU_state() {
3038 pop_FPU_state();
3039 pop_IU_state();
3040 }
3041
3042 void MacroAssembler::pop_FPU_state() {
3043 #ifndef _LP64
3044 frstor(Address(rsp, 0));
3045 #else
3046 fxrstor(Address(rsp, 0));
3047 #endif
3048 addptr(rsp, FPUStateSizeInWords * wordSize);
3049 }
3050
3051 void MacroAssembler::pop_IU_state() {
3052 popa();
3053 LP64_ONLY(addq(rsp, 8));
3054 popf();
3055 }
3056
3057 // Save Integer and Float state
3058 // Warning: Stack must be 16 byte aligned (64bit)
3059 void MacroAssembler::push_CPU_state() {
3060 push_IU_state();
3061 push_FPU_state();
3062 }
3063
3064 void MacroAssembler::push_FPU_state() {
3065 subptr(rsp, FPUStateSizeInWords * wordSize);
3066 #ifndef _LP64
3067 fnsave(Address(rsp, 0));
3068 fwait();
3069 #else
3070 fxsave(Address(rsp, 0));
3071 #endif // LP64
3072 }
3073
3074 void MacroAssembler::push_IU_state() {
3075 // Push flags first because pusha kills them
3076 pushf();
3077 // Make sure rsp stays 16-byte aligned
3078 LP64_ONLY(subq(rsp, 8));
3079 pusha();
3080 }
3081
3082 void MacroAssembler::push_cont_fastpath() {
3083 if (!Continuations::enabled()) return;
3084
3085 #ifndef _LP64
3086 Register rthread = rax;
3087 Register rrealsp = rbx;
3088 push(rthread);
3089 push(rrealsp);
3090
3091 get_thread(rthread);
3092
3093 // The code below wants the original RSP.
3094 // Move it back after the pushes above.
3095 movptr(rrealsp, rsp);
3096 addptr(rrealsp, 2*wordSize);
3097 #else
3098 Register rthread = r15_thread;
3099 Register rrealsp = rsp;
3100 #endif
3101
3102 Label done;
3103 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3104 jccb(Assembler::belowEqual, done);
3105 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3106 bind(done);
3107
3108 #ifndef _LP64
3109 pop(rrealsp);
3110 pop(rthread);
3111 #endif
3112 }
3113
3114 void MacroAssembler::pop_cont_fastpath() {
3115 if (!Continuations::enabled()) return;
3116
3117 #ifndef _LP64
3118 Register rthread = rax;
3119 Register rrealsp = rbx;
3120 push(rthread);
3121 push(rrealsp);
3122
3123 get_thread(rthread);
3124
3125 // The code below wants the original RSP.
3126 // Move it back after the pushes above.
3127 movptr(rrealsp, rsp);
3128 addptr(rrealsp, 2*wordSize);
3129 #else
3130 Register rthread = r15_thread;
3131 Register rrealsp = rsp;
3132 #endif
3133
3134 Label done;
3135 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3136 jccb(Assembler::below, done);
3137 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3138 bind(done);
3139
3140 #ifndef _LP64
3141 pop(rrealsp);
3142 pop(rthread);
3143 #endif
3144 }
3145
3146 void MacroAssembler::inc_held_monitor_count() {
3147 #ifdef _LP64
3148 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3149 #endif
3150 }
3151
3152 void MacroAssembler::dec_held_monitor_count() {
3153 #ifdef _LP64
3154 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3155 #endif
3156 }
3157
3158 #ifdef ASSERT
3159 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3160 #ifdef _LP64
3161 Label no_cont;
3162 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3163 testl(cont, cont);
3164 jcc(Assembler::zero, no_cont);
3165 stop(name);
3166 bind(no_cont);
3167 #else
3168 Unimplemented();
3169 #endif
3170 }
3171 #endif
3172
3173 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3174 if (!java_thread->is_valid()) {
3175 java_thread = rdi;
3176 get_thread(java_thread);
3177 }
3178 // we must set sp to zero to clear frame
3179 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3180 // must clear fp, so that compiled frames are not confused; it is
3181 // possible that we need it only for debugging
3182 if (clear_fp) {
3183 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3184 }
3185 // Always clear the pc because it could have been set by make_walkable()
3186 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3187 vzeroupper();
3188 }
3189
3190 void MacroAssembler::restore_rax(Register tmp) {
3191 if (tmp == noreg) pop(rax);
3192 else if (tmp != rax) mov(rax, tmp);
3193 }
3194
3195 void MacroAssembler::round_to(Register reg, int modulus) {
3196 addptr(reg, modulus - 1);
3197 andptr(reg, -modulus);
3198 }
3199
3200 void MacroAssembler::save_rax(Register tmp) {
3201 if (tmp == noreg) push(rax);
3202 else if (tmp != rax) mov(tmp, rax);
3203 }
3204
3205 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3206 if (at_return) {
3207 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3208 // we may safely use rsp instead to perform the stack watermark check.
3209 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3210 jcc(Assembler::above, slow_path);
3211 return;
3212 }
3213 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3214 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3215 }
3216
3217 // Calls to C land
3218 //
3219 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3220 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3221 // has to be reset to 0. This is required to allow proper stack traversal.
3222 void MacroAssembler::set_last_Java_frame(Register java_thread,
3223 Register last_java_sp,
3224 Register last_java_fp,
3225 address last_java_pc,
3226 Register rscratch) {
3227 vzeroupper();
3228 // determine java_thread register
3229 if (!java_thread->is_valid()) {
3230 java_thread = rdi;
3231 get_thread(java_thread);
3232 }
3233 // determine last_java_sp register
3234 if (!last_java_sp->is_valid()) {
3235 last_java_sp = rsp;
3236 }
3237 // last_java_fp is optional
3238 if (last_java_fp->is_valid()) {
3239 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3240 }
3241 // last_java_pc is optional
3242 if (last_java_pc != nullptr) {
3243 Address java_pc(java_thread,
3244 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3245 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3246 }
3247 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3248 }
3249
3250 #ifdef _LP64
3251 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
3252 Register last_java_fp,
3253 Label &L,
3254 Register scratch) {
3255 lea(scratch, L);
3256 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), scratch);
3257 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, nullptr, scratch);
3258 }
3259 #endif
3260
3261 void MacroAssembler::shlptr(Register dst, int imm8) {
3262 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3263 }
3264
3265 void MacroAssembler::shrptr(Register dst, int imm8) {
3266 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3267 }
3268
3269 void MacroAssembler::sign_extend_byte(Register reg) {
3270 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3271 movsbl(reg, reg); // movsxb
3272 } else {
3273 shll(reg, 24);
3274 sarl(reg, 24);
3275 }
3276 }
3277
3278 void MacroAssembler::sign_extend_short(Register reg) {
3279 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3280 movswl(reg, reg); // movsxw
3281 } else {
3282 shll(reg, 16);
3283 sarl(reg, 16);
3284 }
3285 }
3286
3287 void MacroAssembler::testl(Address dst, int32_t imm32) {
3288 if (imm32 >= 0 && is8bit(imm32)) {
3289 testb(dst, imm32);
3290 } else {
3291 Assembler::testl(dst, imm32);
3292 }
3293 }
3294
3295 void MacroAssembler::testl(Register dst, int32_t imm32) {
3296 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3297 testb(dst, imm32);
3298 } else {
3299 Assembler::testl(dst, imm32);
3300 }
3301 }
3302
3303 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3304 assert(always_reachable(src), "Address should be reachable");
3305 testl(dst, as_Address(src));
3306 }
3307
3308 #ifdef _LP64
3309
3310 void MacroAssembler::testq(Address dst, int32_t imm32) {
3311 if (imm32 >= 0) {
3312 testl(dst, imm32);
3313 } else {
3314 Assembler::testq(dst, imm32);
3315 }
3316 }
3317
3318 void MacroAssembler::testq(Register dst, int32_t imm32) {
3319 if (imm32 >= 0) {
3320 testl(dst, imm32);
3321 } else {
3322 Assembler::testq(dst, imm32);
3323 }
3324 }
3325
3326 #endif
3327
3328 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3329 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3330 Assembler::pcmpeqb(dst, src);
3331 }
3332
3333 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3334 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3335 Assembler::pcmpeqw(dst, src);
3336 }
3337
3338 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3339 assert((dst->encoding() < 16),"XMM register should be 0-15");
3340 Assembler::pcmpestri(dst, src, imm8);
3341 }
3342
3343 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3344 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3345 Assembler::pcmpestri(dst, src, imm8);
3346 }
3347
3348 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3349 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3350 Assembler::pmovzxbw(dst, src);
3351 }
3352
3353 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3354 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3355 Assembler::pmovzxbw(dst, src);
3356 }
3357
3358 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3359 assert((src->encoding() < 16),"XMM register should be 0-15");
3360 Assembler::pmovmskb(dst, src);
3361 }
3362
3363 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3364 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3365 Assembler::ptest(dst, src);
3366 }
3367
3368 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3369 assert(rscratch != noreg || always_reachable(src), "missing");
3370
3371 if (reachable(src)) {
3372 Assembler::sqrtss(dst, as_Address(src));
3373 } else {
3374 lea(rscratch, src);
3375 Assembler::sqrtss(dst, Address(rscratch, 0));
3376 }
3377 }
3378
3379 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3380 assert(rscratch != noreg || always_reachable(src), "missing");
3381
3382 if (reachable(src)) {
3383 Assembler::subsd(dst, as_Address(src));
3384 } else {
3385 lea(rscratch, src);
3386 Assembler::subsd(dst, Address(rscratch, 0));
3387 }
3388 }
3389
3390 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3391 assert(rscratch != noreg || always_reachable(src), "missing");
3392
3393 if (reachable(src)) {
3394 Assembler::roundsd(dst, as_Address(src), rmode);
3395 } else {
3396 lea(rscratch, src);
3397 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3398 }
3399 }
3400
3401 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3402 assert(rscratch != noreg || always_reachable(src), "missing");
3403
3404 if (reachable(src)) {
3405 Assembler::subss(dst, as_Address(src));
3406 } else {
3407 lea(rscratch, src);
3408 Assembler::subss(dst, Address(rscratch, 0));
3409 }
3410 }
3411
3412 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3413 assert(rscratch != noreg || always_reachable(src), "missing");
3414
3415 if (reachable(src)) {
3416 Assembler::ucomisd(dst, as_Address(src));
3417 } else {
3418 lea(rscratch, src);
3419 Assembler::ucomisd(dst, Address(rscratch, 0));
3420 }
3421 }
3422
3423 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3424 assert(rscratch != noreg || always_reachable(src), "missing");
3425
3426 if (reachable(src)) {
3427 Assembler::ucomiss(dst, as_Address(src));
3428 } else {
3429 lea(rscratch, src);
3430 Assembler::ucomiss(dst, Address(rscratch, 0));
3431 }
3432 }
3433
3434 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3435 assert(rscratch != noreg || always_reachable(src), "missing");
3436
3437 // Used in sign-bit flipping with aligned address.
3438 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3439
3440 if (UseAVX > 2 &&
3441 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3442 (dst->encoding() >= 16)) {
3443 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3444 } else if (reachable(src)) {
3445 Assembler::xorpd(dst, as_Address(src));
3446 } else {
3447 lea(rscratch, src);
3448 Assembler::xorpd(dst, Address(rscratch, 0));
3449 }
3450 }
3451
3452 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3453 if (UseAVX > 2 &&
3454 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3455 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3456 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3457 } else {
3458 Assembler::xorpd(dst, src);
3459 }
3460 }
3461
3462 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3463 if (UseAVX > 2 &&
3464 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3465 ((dst->encoding() >= 16) || (src->encoding() >= 16))) {
3466 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3467 } else {
3468 Assembler::xorps(dst, src);
3469 }
3470 }
3471
3472 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3473 assert(rscratch != noreg || always_reachable(src), "missing");
3474
3475 // Used in sign-bit flipping with aligned address.
3476 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3477
3478 if (UseAVX > 2 &&
3479 (!VM_Version::supports_avx512dq() || !VM_Version::supports_avx512vl()) &&
3480 (dst->encoding() >= 16)) {
3481 vpxor(dst, dst, src, Assembler::AVX_512bit, rscratch);
3482 } else if (reachable(src)) {
3483 Assembler::xorps(dst, as_Address(src));
3484 } else {
3485 lea(rscratch, src);
3486 Assembler::xorps(dst, Address(rscratch, 0));
3487 }
3488 }
3489
3490 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3491 assert(rscratch != noreg || always_reachable(src), "missing");
3492
3493 // Used in sign-bit flipping with aligned address.
3494 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3495 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3496 if (reachable(src)) {
3497 Assembler::pshufb(dst, as_Address(src));
3498 } else {
3499 lea(rscratch, src);
3500 Assembler::pshufb(dst, Address(rscratch, 0));
3501 }
3502 }
3503
3504 // AVX 3-operands instructions
3505
3506 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3507 assert(rscratch != noreg || always_reachable(src), "missing");
3508
3509 if (reachable(src)) {
3510 vaddsd(dst, nds, as_Address(src));
3511 } else {
3512 lea(rscratch, src);
3513 vaddsd(dst, nds, Address(rscratch, 0));
3514 }
3515 }
3516
3517 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3518 assert(rscratch != noreg || always_reachable(src), "missing");
3519
3520 if (reachable(src)) {
3521 vaddss(dst, nds, as_Address(src));
3522 } else {
3523 lea(rscratch, src);
3524 vaddss(dst, nds, Address(rscratch, 0));
3525 }
3526 }
3527
3528 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3529 assert(UseAVX > 0, "requires some form of AVX");
3530 assert(rscratch != noreg || always_reachable(src), "missing");
3531
3532 if (reachable(src)) {
3533 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3534 } else {
3535 lea(rscratch, src);
3536 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3537 }
3538 }
3539
3540 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3541 assert(UseAVX > 0, "requires some form of AVX");
3542 assert(rscratch != noreg || always_reachable(src), "missing");
3543
3544 if (reachable(src)) {
3545 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3546 } else {
3547 lea(rscratch, src);
3548 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3549 }
3550 }
3551
3552 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3553 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3554 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3555
3556 vandps(dst, nds, negate_field, vector_len, rscratch);
3557 }
3558
3559 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3560 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3561 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3562
3563 vandpd(dst, nds, negate_field, vector_len, rscratch);
3564 }
3565
3566 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3567 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3568 Assembler::vpaddb(dst, nds, src, vector_len);
3569 }
3570
3571 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3572 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3573 Assembler::vpaddb(dst, nds, src, vector_len);
3574 }
3575
3576 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3577 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3578 Assembler::vpaddw(dst, nds, src, vector_len);
3579 }
3580
3581 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3582 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3583 Assembler::vpaddw(dst, nds, src, vector_len);
3584 }
3585
3586 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3587 assert(rscratch != noreg || always_reachable(src), "missing");
3588
3589 if (reachable(src)) {
3590 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3591 } else {
3592 lea(rscratch, src);
3593 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3594 }
3595 }
3596
3597 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3598 assert(rscratch != noreg || always_reachable(src), "missing");
3599
3600 if (reachable(src)) {
3601 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3602 } else {
3603 lea(rscratch, src);
3604 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3605 }
3606 }
3607
3608 void MacroAssembler::vbroadcasti128(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3609 assert(rscratch != noreg || always_reachable(src), "missing");
3610
3611 if (reachable(src)) {
3612 Assembler::vbroadcasti128(dst, as_Address(src), vector_len);
3613 } else {
3614 lea(rscratch, src);
3615 Assembler::vbroadcasti128(dst, Address(rscratch, 0), vector_len);
3616 }
3617 }
3618
3619 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3620 assert(rscratch != noreg || always_reachable(src), "missing");
3621
3622 if (reachable(src)) {
3623 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3624 } else {
3625 lea(rscratch, src);
3626 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3627 }
3628 }
3629
3630 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3631 assert(rscratch != noreg || always_reachable(src), "missing");
3632
3633 if (reachable(src)) {
3634 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3635 } else {
3636 lea(rscratch, src);
3637 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3638 }
3639 }
3640
3641 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3642 assert(rscratch != noreg || always_reachable(src), "missing");
3643
3644 if (reachable(src)) {
3645 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3646 } else {
3647 lea(rscratch, src);
3648 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3649 }
3650 }
3651
3652 // Vector float blend
3653 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3654 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3655 // WARN: Allow dst == (src1|src2), mask == scratch
3656 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3657 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3658 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3659 if (blend_emulation && scratch_available && dst_available) {
3660 if (compute_mask) {
3661 vpsrad(scratch, mask, 32, vector_len);
3662 mask = scratch;
3663 }
3664 if (dst == src1) {
3665 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3666 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3667 } else {
3668 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3669 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3670 }
3671 vpor(dst, dst, scratch, vector_len);
3672 } else {
3673 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3674 }
3675 }
3676
3677 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3678 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3679 // WARN: Allow dst == (src1|src2), mask == scratch
3680 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3681 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3682 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3683 if (blend_emulation && scratch_available && dst_available) {
3684 if (compute_mask) {
3685 vpxor(scratch, scratch, scratch, vector_len);
3686 vpcmpgtq(scratch, scratch, mask, vector_len);
3687 mask = scratch;
3688 }
3689 if (dst == src1) {
3690 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3691 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3692 } else {
3693 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3694 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3695 }
3696 vpor(dst, dst, scratch, vector_len);
3697 } else {
3698 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3699 }
3700 }
3701
3702 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3703 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3704 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3705 }
3706
3707 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3708 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3709 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3710 }
3711
3712 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3713 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3714 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3715 }
3716
3717 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3718 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3719 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3720 }
3721
3722 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3723 assert(rscratch != noreg || always_reachable(src), "missing");
3724
3725 if (reachable(src)) {
3726 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3727 } else {
3728 lea(rscratch, src);
3729 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3730 }
3731 }
3732
3733 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3734 int comparison, bool is_signed, int vector_len, Register rscratch) {
3735 assert(rscratch != noreg || always_reachable(src), "missing");
3736
3737 if (reachable(src)) {
3738 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3739 } else {
3740 lea(rscratch, src);
3741 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3742 }
3743 }
3744
3745 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3746 int comparison, bool is_signed, int vector_len, Register rscratch) {
3747 assert(rscratch != noreg || always_reachable(src), "missing");
3748
3749 if (reachable(src)) {
3750 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3751 } else {
3752 lea(rscratch, src);
3753 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3754 }
3755 }
3756
3757 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3758 int comparison, bool is_signed, int vector_len, Register rscratch) {
3759 assert(rscratch != noreg || always_reachable(src), "missing");
3760
3761 if (reachable(src)) {
3762 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3763 } else {
3764 lea(rscratch, src);
3765 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3766 }
3767 }
3768
3769 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3770 int comparison, bool is_signed, int vector_len, Register rscratch) {
3771 assert(rscratch != noreg || always_reachable(src), "missing");
3772
3773 if (reachable(src)) {
3774 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3775 } else {
3776 lea(rscratch, src);
3777 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3778 }
3779 }
3780
3781 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3782 if (width == Assembler::Q) {
3783 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3784 } else {
3785 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3786 }
3787 }
3788
3789 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3790 int eq_cond_enc = 0x29;
3791 int gt_cond_enc = 0x37;
3792 if (width != Assembler::Q) {
3793 eq_cond_enc = 0x74 + width;
3794 gt_cond_enc = 0x64 + width;
3795 }
3796 switch (cond) {
3797 case eq:
3798 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3799 break;
3800 case neq:
3801 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3802 vallones(xtmp, vector_len);
3803 vpxor(dst, xtmp, dst, vector_len);
3804 break;
3805 case le:
3806 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3807 vallones(xtmp, vector_len);
3808 vpxor(dst, xtmp, dst, vector_len);
3809 break;
3810 case nlt:
3811 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3812 vallones(xtmp, vector_len);
3813 vpxor(dst, xtmp, dst, vector_len);
3814 break;
3815 case lt:
3816 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3817 break;
3818 case nle:
3819 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3820 break;
3821 default:
3822 assert(false, "Should not reach here");
3823 }
3824 }
3825
3826 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3827 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3828 Assembler::vpmovzxbw(dst, src, vector_len);
3829 }
3830
3831 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3832 assert((src->encoding() < 16),"XMM register should be 0-15");
3833 Assembler::vpmovmskb(dst, src, vector_len);
3834 }
3835
3836 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3837 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3838 Assembler::vpmullw(dst, nds, src, vector_len);
3839 }
3840
3841 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3842 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3843 Assembler::vpmullw(dst, nds, src, vector_len);
3844 }
3845
3846 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3847 assert((UseAVX > 0), "AVX support is needed");
3848 assert(rscratch != noreg || always_reachable(src), "missing");
3849
3850 if (reachable(src)) {
3851 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3852 } else {
3853 lea(rscratch, src);
3854 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3855 }
3856 }
3857
3858 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3859 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3860 Assembler::vpsubb(dst, nds, src, vector_len);
3861 }
3862
3863 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3864 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3865 Assembler::vpsubb(dst, nds, src, vector_len);
3866 }
3867
3868 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3869 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3870 Assembler::vpsubw(dst, nds, src, vector_len);
3871 }
3872
3873 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3874 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3875 Assembler::vpsubw(dst, nds, src, vector_len);
3876 }
3877
3878 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3879 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3880 Assembler::vpsraw(dst, nds, shift, vector_len);
3881 }
3882
3883 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3884 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3885 Assembler::vpsraw(dst, nds, shift, vector_len);
3886 }
3887
3888 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3889 assert(UseAVX > 2,"");
3890 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3891 vector_len = 2;
3892 }
3893 Assembler::evpsraq(dst, nds, shift, vector_len);
3894 }
3895
3896 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3897 assert(UseAVX > 2,"");
3898 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3899 vector_len = 2;
3900 }
3901 Assembler::evpsraq(dst, nds, shift, vector_len);
3902 }
3903
3904 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3905 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3906 Assembler::vpsrlw(dst, nds, shift, vector_len);
3907 }
3908
3909 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3910 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3911 Assembler::vpsrlw(dst, nds, shift, vector_len);
3912 }
3913
3914 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3915 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3916 Assembler::vpsllw(dst, nds, shift, vector_len);
3917 }
3918
3919 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3920 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3921 Assembler::vpsllw(dst, nds, shift, vector_len);
3922 }
3923
3924 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3925 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3926 Assembler::vptest(dst, src);
3927 }
3928
3929 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3930 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3931 Assembler::punpcklbw(dst, src);
3932 }
3933
3934 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3935 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3936 Assembler::pshufd(dst, src, mode);
3937 }
3938
3939 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3940 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3941 Assembler::pshuflw(dst, src, mode);
3942 }
3943
3944 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3945 assert(rscratch != noreg || always_reachable(src), "missing");
3946
3947 if (reachable(src)) {
3948 vandpd(dst, nds, as_Address(src), vector_len);
3949 } else {
3950 lea(rscratch, src);
3951 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3952 }
3953 }
3954
3955 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3956 assert(rscratch != noreg || always_reachable(src), "missing");
3957
3958 if (reachable(src)) {
3959 vandps(dst, nds, as_Address(src), vector_len);
3960 } else {
3961 lea(rscratch, src);
3962 vandps(dst, nds, Address(rscratch, 0), vector_len);
3963 }
3964 }
3965
3966 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3967 bool merge, int vector_len, Register rscratch) {
3968 assert(rscratch != noreg || always_reachable(src), "missing");
3969
3970 if (reachable(src)) {
3971 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3972 } else {
3973 lea(rscratch, src);
3974 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3975 }
3976 }
3977
3978 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3979 assert(rscratch != noreg || always_reachable(src), "missing");
3980
3981 if (reachable(src)) {
3982 vdivsd(dst, nds, as_Address(src));
3983 } else {
3984 lea(rscratch, src);
3985 vdivsd(dst, nds, Address(rscratch, 0));
3986 }
3987 }
3988
3989 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3990 assert(rscratch != noreg || always_reachable(src), "missing");
3991
3992 if (reachable(src)) {
3993 vdivss(dst, nds, as_Address(src));
3994 } else {
3995 lea(rscratch, src);
3996 vdivss(dst, nds, Address(rscratch, 0));
3997 }
3998 }
3999
4000 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4001 assert(rscratch != noreg || always_reachable(src), "missing");
4002
4003 if (reachable(src)) {
4004 vmulsd(dst, nds, as_Address(src));
4005 } else {
4006 lea(rscratch, src);
4007 vmulsd(dst, nds, Address(rscratch, 0));
4008 }
4009 }
4010
4011 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4012 assert(rscratch != noreg || always_reachable(src), "missing");
4013
4014 if (reachable(src)) {
4015 vmulss(dst, nds, as_Address(src));
4016 } else {
4017 lea(rscratch, src);
4018 vmulss(dst, nds, Address(rscratch, 0));
4019 }
4020 }
4021
4022 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4023 assert(rscratch != noreg || always_reachable(src), "missing");
4024
4025 if (reachable(src)) {
4026 vsubsd(dst, nds, as_Address(src));
4027 } else {
4028 lea(rscratch, src);
4029 vsubsd(dst, nds, Address(rscratch, 0));
4030 }
4031 }
4032
4033 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4034 assert(rscratch != noreg || always_reachable(src), "missing");
4035
4036 if (reachable(src)) {
4037 vsubss(dst, nds, as_Address(src));
4038 } else {
4039 lea(rscratch, src);
4040 vsubss(dst, nds, Address(rscratch, 0));
4041 }
4042 }
4043
4044 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4045 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4046 assert(rscratch != noreg || always_reachable(src), "missing");
4047
4048 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
4049 }
4050
4051 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
4052 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
4053 assert(rscratch != noreg || always_reachable(src), "missing");
4054
4055 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
4056 }
4057
4058 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4059 assert(rscratch != noreg || always_reachable(src), "missing");
4060
4061 if (reachable(src)) {
4062 vxorpd(dst, nds, as_Address(src), vector_len);
4063 } else {
4064 lea(rscratch, src);
4065 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
4066 }
4067 }
4068
4069 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4070 assert(rscratch != noreg || always_reachable(src), "missing");
4071
4072 if (reachable(src)) {
4073 vxorps(dst, nds, as_Address(src), vector_len);
4074 } else {
4075 lea(rscratch, src);
4076 vxorps(dst, nds, Address(rscratch, 0), vector_len);
4077 }
4078 }
4079
4080 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4081 assert(rscratch != noreg || always_reachable(src), "missing");
4082
4083 if (UseAVX > 1 || (vector_len < 1)) {
4084 if (reachable(src)) {
4085 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
4086 } else {
4087 lea(rscratch, src);
4088 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
4089 }
4090 } else {
4091 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
4092 }
4093 }
4094
4095 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
4096 assert(rscratch != noreg || always_reachable(src), "missing");
4097
4098 if (reachable(src)) {
4099 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
4100 } else {
4101 lea(rscratch, src);
4102 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
4103 }
4104 }
4105
4106 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
4107 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
4108 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
4109 // The inverted mask is sign-extended
4110 andptr(possibly_non_local, inverted_mask);
4111 }
4112
4113 void MacroAssembler::resolve_jobject(Register value,
4114 Register thread,
4115 Register tmp) {
4116 assert_different_registers(value, thread, tmp);
4117 Label done, tagged, weak_tagged;
4118 testptr(value, value);
4119 jcc(Assembler::zero, done); // Use null as-is.
4120 testptr(value, JNIHandles::tag_mask); // Test for tag.
4121 jcc(Assembler::notZero, tagged);
4122
4123 // Resolve local handle
4124 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
4125 verify_oop(value);
4126 jmp(done);
4127
4128 bind(tagged);
4129 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4130 jcc(Assembler::notZero, weak_tagged);
4131
4132 // Resolve global handle
4133 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4134 verify_oop(value);
4135 jmp(done);
4136
4137 bind(weak_tagged);
4138 // Resolve jweak.
4139 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4140 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4141 verify_oop(value);
4142
4143 bind(done);
4144 }
4145
4146 void MacroAssembler::resolve_global_jobject(Register value,
4147 Register thread,
4148 Register tmp) {
4149 assert_different_registers(value, thread, tmp);
4150 Label done;
4151
4152 testptr(value, value);
4153 jcc(Assembler::zero, done); // Use null as-is.
4154
4155 #ifdef ASSERT
4156 {
4157 Label valid_global_tag;
4158 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4159 jcc(Assembler::notZero, valid_global_tag);
4160 stop("non global jobject using resolve_global_jobject");
4161 bind(valid_global_tag);
4162 }
4163 #endif
4164
4165 // Resolve global handle
4166 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4167 verify_oop(value);
4168
4169 bind(done);
4170 }
4171
4172 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4173 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4174 }
4175
4176 // Force generation of a 4 byte immediate value even if it fits into 8bit
4177 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4178 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4179 }
4180
4181 void MacroAssembler::subptr(Register dst, Register src) {
4182 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4183 }
4184
4185 // C++ bool manipulation
4186 void MacroAssembler::testbool(Register dst) {
4187 if(sizeof(bool) == 1)
4188 testb(dst, 0xff);
4189 else if(sizeof(bool) == 2) {
4190 // testw implementation needed for two byte bools
4191 ShouldNotReachHere();
4192 } else if(sizeof(bool) == 4)
4193 testl(dst, dst);
4194 else
4195 // unsupported
4196 ShouldNotReachHere();
4197 }
4198
4199 void MacroAssembler::testptr(Register dst, Register src) {
4200 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4201 }
4202
4203 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4204 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4205 Register var_size_in_bytes,
4206 int con_size_in_bytes,
4207 Register t1,
4208 Register t2,
4209 Label& slow_case) {
4210 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4211 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4212 }
4213
4214 RegSet MacroAssembler::call_clobbered_gp_registers() {
4215 RegSet regs;
4216 #ifdef _LP64
4217 regs += RegSet::of(rax, rcx, rdx);
4218 #ifndef _WINDOWS
4219 regs += RegSet::of(rsi, rdi);
4220 #endif
4221 regs += RegSet::range(r8, r11);
4222 #else
4223 regs += RegSet::of(rax, rcx, rdx);
4224 #endif
4225 #ifdef _LP64
4226 if (UseAPX) {
4227 regs += RegSet::range(r16, as_Register(Register::number_of_registers - 1));
4228 }
4229 #endif
4230 return regs;
4231 }
4232
4233 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4234 int num_xmm_registers = XMMRegister::available_xmm_registers();
4235 #if defined(_WINDOWS)
4236 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4237 if (num_xmm_registers > 16) {
4238 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4239 }
4240 return result;
4241 #else
4242 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4243 #endif
4244 }
4245
4246 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4247
4248 #ifndef _LP64
4249 static bool use_x87_registers() { return UseSSE < 2; }
4250 #endif
4251 static bool use_xmm_registers() { return UseSSE >= 1; }
4252
4253 // C1 only ever uses the first double/float of the XMM register.
4254 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4255
4256 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4257 if (UseSSE == 1) {
4258 masm->movflt(Address(rsp, offset), reg);
4259 } else {
4260 masm->movdbl(Address(rsp, offset), reg);
4261 }
4262 }
4263
4264 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4265 if (UseSSE == 1) {
4266 masm->movflt(reg, Address(rsp, offset));
4267 } else {
4268 masm->movdbl(reg, Address(rsp, offset));
4269 }
4270 }
4271
4272 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4273 bool save_fpu, int& gp_area_size,
4274 int& fp_area_size, int& xmm_area_size) {
4275
4276 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4277 StackAlignmentInBytes);
4278 #ifdef _LP64
4279 fp_area_size = 0;
4280 #else
4281 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4282 #endif
4283 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4284
4285 return gp_area_size + fp_area_size + xmm_area_size;
4286 }
4287
4288 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4289 block_comment("push_call_clobbered_registers start");
4290 // Regular registers
4291 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4292
4293 int gp_area_size;
4294 int fp_area_size;
4295 int xmm_area_size;
4296 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4297 gp_area_size, fp_area_size, xmm_area_size);
4298 subptr(rsp, total_save_size);
4299
4300 push_set(gp_registers_to_push, 0);
4301
4302 #ifndef _LP64
4303 if (save_fpu && use_x87_registers()) {
4304 fnsave(Address(rsp, gp_area_size));
4305 fwait();
4306 }
4307 #endif
4308 if (save_fpu && use_xmm_registers()) {
4309 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4310 }
4311
4312 block_comment("push_call_clobbered_registers end");
4313 }
4314
4315 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4316 block_comment("pop_call_clobbered_registers start");
4317
4318 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4319
4320 int gp_area_size;
4321 int fp_area_size;
4322 int xmm_area_size;
4323 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4324 gp_area_size, fp_area_size, xmm_area_size);
4325
4326 if (restore_fpu && use_xmm_registers()) {
4327 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4328 }
4329 #ifndef _LP64
4330 if (restore_fpu && use_x87_registers()) {
4331 frstor(Address(rsp, gp_area_size));
4332 }
4333 #endif
4334
4335 pop_set(gp_registers_to_pop, 0);
4336
4337 addptr(rsp, total_save_size);
4338
4339 vzeroupper();
4340
4341 block_comment("pop_call_clobbered_registers end");
4342 }
4343
4344 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4345 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4346 int spill_offset = offset;
4347
4348 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4349 save_xmm_register(this, spill_offset, *it);
4350 spill_offset += xmm_save_size();
4351 }
4352 }
4353
4354 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4355 int restore_size = set.size() * xmm_save_size();
4356 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4357
4358 int restore_offset = offset + restore_size - xmm_save_size();
4359
4360 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4361 restore_xmm_register(this, restore_offset, *it);
4362 restore_offset -= xmm_save_size();
4363 }
4364 }
4365
4366 void MacroAssembler::push_set(RegSet set, int offset) {
4367 int spill_offset;
4368 if (offset == -1) {
4369 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4370 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4371 subptr(rsp, aligned_size);
4372 spill_offset = 0;
4373 } else {
4374 spill_offset = offset;
4375 }
4376
4377 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4378 movptr(Address(rsp, spill_offset), *it);
4379 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4380 }
4381 }
4382
4383 void MacroAssembler::pop_set(RegSet set, int offset) {
4384
4385 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4386 int restore_size = set.size() * gp_reg_size;
4387 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4388
4389 int restore_offset;
4390 if (offset == -1) {
4391 restore_offset = restore_size - gp_reg_size;
4392 } else {
4393 restore_offset = offset + restore_size - gp_reg_size;
4394 }
4395 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4396 movptr(*it, Address(rsp, restore_offset));
4397 restore_offset -= gp_reg_size;
4398 }
4399
4400 if (offset == -1) {
4401 addptr(rsp, aligned_size);
4402 }
4403 }
4404
4405 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4406 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4407 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4408 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4409 Label done;
4410
4411 testptr(length_in_bytes, length_in_bytes);
4412 jcc(Assembler::zero, done);
4413
4414 // initialize topmost word, divide index by 2, check if odd and test if zero
4415 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4416 #ifdef ASSERT
4417 {
4418 Label L;
4419 testptr(length_in_bytes, BytesPerWord - 1);
4420 jcc(Assembler::zero, L);
4421 stop("length must be a multiple of BytesPerWord");
4422 bind(L);
4423 }
4424 #endif
4425 Register index = length_in_bytes;
4426 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4427 if (UseIncDec) {
4428 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4429 } else {
4430 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4431 shrptr(index, 1);
4432 }
4433 #ifndef _LP64
4434 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4435 {
4436 Label even;
4437 // note: if index was a multiple of 8, then it cannot
4438 // be 0 now otherwise it must have been 0 before
4439 // => if it is even, we don't need to check for 0 again
4440 jcc(Assembler::carryClear, even);
4441 // clear topmost word (no jump would be needed if conditional assignment worked here)
4442 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4443 // index could be 0 now, must check again
4444 jcc(Assembler::zero, done);
4445 bind(even);
4446 }
4447 #endif // !_LP64
4448 // initialize remaining object fields: index is a multiple of 2 now
4449 {
4450 Label loop;
4451 bind(loop);
4452 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4453 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4454 decrement(index);
4455 jcc(Assembler::notZero, loop);
4456 }
4457
4458 bind(done);
4459 }
4460
4461 // Look up the method for a megamorphic invokeinterface call.
4462 // The target method is determined by <intf_klass, itable_index>.
4463 // The receiver klass is in recv_klass.
4464 // On success, the result will be in method_result, and execution falls through.
4465 // On failure, execution transfers to the given label.
4466 void MacroAssembler::lookup_interface_method(Register recv_klass,
4467 Register intf_klass,
4468 RegisterOrConstant itable_index,
4469 Register method_result,
4470 Register scan_temp,
4471 Label& L_no_such_interface,
4472 bool return_method) {
4473 assert_different_registers(recv_klass, intf_klass, scan_temp);
4474 assert_different_registers(method_result, intf_klass, scan_temp);
4475 assert(recv_klass != method_result || !return_method,
4476 "recv_klass can be destroyed when method isn't needed");
4477
4478 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4479 "caller must use same register for non-constant itable index as for method");
4480
4481 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4482 int vtable_base = in_bytes(Klass::vtable_start_offset());
4483 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4484 int scan_step = itableOffsetEntry::size() * wordSize;
4485 int vte_size = vtableEntry::size_in_bytes();
4486 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4487 assert(vte_size == wordSize, "else adjust times_vte_scale");
4488
4489 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4490
4491 // Could store the aligned, prescaled offset in the klass.
4492 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4493
4494 if (return_method) {
4495 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4496 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4497 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4498 }
4499
4500 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4501 // if (scan->interface() == intf) {
4502 // result = (klass + scan->offset() + itable_index);
4503 // }
4504 // }
4505 Label search, found_method;
4506
4507 for (int peel = 1; peel >= 0; peel--) {
4508 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4509 cmpptr(intf_klass, method_result);
4510
4511 if (peel) {
4512 jccb(Assembler::equal, found_method);
4513 } else {
4514 jccb(Assembler::notEqual, search);
4515 // (invert the test to fall through to found_method...)
4516 }
4517
4518 if (!peel) break;
4519
4520 bind(search);
4521
4522 // Check that the previous entry is non-null. A null entry means that
4523 // the receiver class doesn't implement the interface, and wasn't the
4524 // same as when the caller was compiled.
4525 testptr(method_result, method_result);
4526 jcc(Assembler::zero, L_no_such_interface);
4527 addptr(scan_temp, scan_step);
4528 }
4529
4530 bind(found_method);
4531
4532 if (return_method) {
4533 // Got a hit.
4534 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4535 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4536 }
4537 }
4538
4539 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4540 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4541 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4542 // The target method is determined by <holder_klass, itable_index>.
4543 // The receiver klass is in recv_klass.
4544 // On success, the result will be in method_result, and execution falls through.
4545 // On failure, execution transfers to the given label.
4546 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4547 Register holder_klass,
4548 Register resolved_klass,
4549 Register method_result,
4550 Register scan_temp,
4551 Register temp_reg2,
4552 Register receiver,
4553 int itable_index,
4554 Label& L_no_such_interface) {
4555 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4556 Register temp_itbl_klass = method_result;
4557 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4558
4559 int vtable_base = in_bytes(Klass::vtable_start_offset());
4560 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4561 int scan_step = itableOffsetEntry::size() * wordSize;
4562 int vte_size = vtableEntry::size_in_bytes();
4563 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4564 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4565 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4566 assert(vte_size == wordSize, "adjust times_vte_scale");
4567
4568 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4569
4570 // temp_itbl_klass = recv_klass.itable[0]
4571 // scan_temp = &recv_klass.itable[0] + step
4572 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4573 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4574 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4575 xorptr(temp_reg, temp_reg);
4576
4577 // Initial checks:
4578 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4579 // - if (itable[0] == 0), no such interface
4580 // - if (itable[0] == holder_klass), shortcut to "holder found"
4581 cmpptr(holder_klass, resolved_klass);
4582 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4583 testptr(temp_itbl_klass, temp_itbl_klass);
4584 jccb(Assembler::zero, L_no_such_interface);
4585 cmpptr(holder_klass, temp_itbl_klass);
4586 jccb(Assembler::equal, L_holder_found);
4587
4588 // Loop: Look for holder_klass record in itable
4589 // do {
4590 // tmp = itable[index];
4591 // index += step;
4592 // if (tmp == holder_klass) {
4593 // goto L_holder_found; // Found!
4594 // }
4595 // } while (tmp != 0);
4596 // goto L_no_such_interface // Not found.
4597 Label L_scan_holder;
4598 bind(L_scan_holder);
4599 movptr(temp_itbl_klass, Address(scan_temp, 0));
4600 addptr(scan_temp, scan_step);
4601 cmpptr(holder_klass, temp_itbl_klass);
4602 jccb(Assembler::equal, L_holder_found);
4603 testptr(temp_itbl_klass, temp_itbl_klass);
4604 jccb(Assembler::notZero, L_scan_holder);
4605
4606 jmpb(L_no_such_interface);
4607
4608 // Loop: Look for resolved_class record in itable
4609 // do {
4610 // tmp = itable[index];
4611 // index += step;
4612 // if (tmp == holder_klass) {
4613 // // Also check if we have met a holder klass
4614 // holder_tmp = itable[index-step-ioffset];
4615 // }
4616 // if (tmp == resolved_klass) {
4617 // goto L_resolved_found; // Found!
4618 // }
4619 // } while (tmp != 0);
4620 // goto L_no_such_interface // Not found.
4621 //
4622 Label L_loop_scan_resolved;
4623 bind(L_loop_scan_resolved);
4624 movptr(temp_itbl_klass, Address(scan_temp, 0));
4625 addptr(scan_temp, scan_step);
4626 bind(L_loop_scan_resolved_entry);
4627 cmpptr(holder_klass, temp_itbl_klass);
4628 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4629 cmpptr(resolved_klass, temp_itbl_klass);
4630 jccb(Assembler::equal, L_resolved_found);
4631 testptr(temp_itbl_klass, temp_itbl_klass);
4632 jccb(Assembler::notZero, L_loop_scan_resolved);
4633
4634 jmpb(L_no_such_interface);
4635
4636 Label L_ready;
4637
4638 // See if we already have a holder klass. If not, go and scan for it.
4639 bind(L_resolved_found);
4640 testptr(temp_reg, temp_reg);
4641 jccb(Assembler::zero, L_scan_holder);
4642 jmpb(L_ready);
4643
4644 bind(L_holder_found);
4645 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4646
4647 // Finally, temp_reg contains holder_klass vtable offset
4648 bind(L_ready);
4649 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4650 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4651 load_klass(scan_temp, receiver, noreg);
4652 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4653 } else {
4654 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4655 }
4656 }
4657
4658
4659 // virtual method calling
4660 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4661 RegisterOrConstant vtable_index,
4662 Register method_result) {
4663 const ByteSize base = Klass::vtable_start_offset();
4664 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4665 Address vtable_entry_addr(recv_klass,
4666 vtable_index, Address::times_ptr,
4667 base + vtableEntry::method_offset());
4668 movptr(method_result, vtable_entry_addr);
4669 }
4670
4671
4672 void MacroAssembler::check_klass_subtype(Register sub_klass,
4673 Register super_klass,
4674 Register temp_reg,
4675 Label& L_success) {
4676 Label L_failure;
4677 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4678 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4679 bind(L_failure);
4680 }
4681
4682
4683 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4684 Register super_klass,
4685 Register temp_reg,
4686 Label* L_success,
4687 Label* L_failure,
4688 Label* L_slow_path,
4689 RegisterOrConstant super_check_offset) {
4690 assert_different_registers(sub_klass, super_klass, temp_reg);
4691 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4692 if (super_check_offset.is_register()) {
4693 assert_different_registers(sub_klass, super_klass,
4694 super_check_offset.as_register());
4695 } else if (must_load_sco) {
4696 assert(temp_reg != noreg, "supply either a temp or a register offset");
4697 }
4698
4699 Label L_fallthrough;
4700 int label_nulls = 0;
4701 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4702 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4703 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4704 assert(label_nulls <= 1, "at most one null in the batch");
4705
4706 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4707 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4708 Address super_check_offset_addr(super_klass, sco_offset);
4709
4710 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4711 // range of a jccb. If this routine grows larger, reconsider at
4712 // least some of these.
4713 #define local_jcc(assembler_cond, label) \
4714 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4715 else jcc( assembler_cond, label) /*omit semi*/
4716
4717 // Hacked jmp, which may only be used just before L_fallthrough.
4718 #define final_jmp(label) \
4719 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4720 else jmp(label) /*omit semi*/
4721
4722 // If the pointers are equal, we are done (e.g., String[] elements).
4723 // This self-check enables sharing of secondary supertype arrays among
4724 // non-primary types such as array-of-interface. Otherwise, each such
4725 // type would need its own customized SSA.
4726 // We move this check to the front of the fast path because many
4727 // type checks are in fact trivially successful in this manner,
4728 // so we get a nicely predicted branch right at the start of the check.
4729 cmpptr(sub_klass, super_klass);
4730 local_jcc(Assembler::equal, *L_success);
4731
4732 // Check the supertype display:
4733 if (must_load_sco) {
4734 // Positive movl does right thing on LP64.
4735 movl(temp_reg, super_check_offset_addr);
4736 super_check_offset = RegisterOrConstant(temp_reg);
4737 }
4738 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4739 cmpptr(super_klass, super_check_addr); // load displayed supertype
4740
4741 // This check has worked decisively for primary supers.
4742 // Secondary supers are sought in the super_cache ('super_cache_addr').
4743 // (Secondary supers are interfaces and very deeply nested subtypes.)
4744 // This works in the same check above because of a tricky aliasing
4745 // between the super_cache and the primary super display elements.
4746 // (The 'super_check_addr' can address either, as the case requires.)
4747 // Note that the cache is updated below if it does not help us find
4748 // what we need immediately.
4749 // So if it was a primary super, we can just fail immediately.
4750 // Otherwise, it's the slow path for us (no success at this point).
4751
4752 if (super_check_offset.is_register()) {
4753 local_jcc(Assembler::equal, *L_success);
4754 cmpl(super_check_offset.as_register(), sc_offset);
4755 if (L_failure == &L_fallthrough) {
4756 local_jcc(Assembler::equal, *L_slow_path);
4757 } else {
4758 local_jcc(Assembler::notEqual, *L_failure);
4759 final_jmp(*L_slow_path);
4760 }
4761 } else if (super_check_offset.as_constant() == sc_offset) {
4762 // Need a slow path; fast failure is impossible.
4763 if (L_slow_path == &L_fallthrough) {
4764 local_jcc(Assembler::equal, *L_success);
4765 } else {
4766 local_jcc(Assembler::notEqual, *L_slow_path);
4767 final_jmp(*L_success);
4768 }
4769 } else {
4770 // No slow path; it's a fast decision.
4771 if (L_failure == &L_fallthrough) {
4772 local_jcc(Assembler::equal, *L_success);
4773 } else {
4774 local_jcc(Assembler::notEqual, *L_failure);
4775 final_jmp(*L_success);
4776 }
4777 }
4778
4779 bind(L_fallthrough);
4780
4781 #undef local_jcc
4782 #undef final_jmp
4783 }
4784
4785
4786 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
4787 Register super_klass,
4788 Register temp_reg,
4789 Register temp2_reg,
4790 Label* L_success,
4791 Label* L_failure,
4792 bool set_cond_codes) {
4793 assert_different_registers(sub_klass, super_klass, temp_reg);
4794 if (temp2_reg != noreg)
4795 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4796 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4797
4798 Label L_fallthrough;
4799 int label_nulls = 0;
4800 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4801 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4802 assert(label_nulls <= 1, "at most one null in the batch");
4803
4804 // a couple of useful fields in sub_klass:
4805 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4806 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4807 Address secondary_supers_addr(sub_klass, ss_offset);
4808 Address super_cache_addr( sub_klass, sc_offset);
4809
4810 // Do a linear scan of the secondary super-klass chain.
4811 // This code is rarely used, so simplicity is a virtue here.
4812 // The repne_scan instruction uses fixed registers, which we must spill.
4813 // Don't worry too much about pre-existing connections with the input regs.
4814
4815 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4816 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4817
4818 // Get super_klass value into rax (even if it was in rdi or rcx).
4819 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4820 if (super_klass != rax) {
4821 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4822 mov(rax, super_klass);
4823 }
4824 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4825 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4826
4827 #ifndef PRODUCT
4828 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4829 ExternalAddress pst_counter_addr((address) pst_counter);
4830 NOT_LP64( incrementl(pst_counter_addr) );
4831 LP64_ONLY( lea(rcx, pst_counter_addr) );
4832 LP64_ONLY( incrementl(Address(rcx, 0)) );
4833 #endif //PRODUCT
4834
4835 // We will consult the secondary-super array.
4836 movptr(rdi, secondary_supers_addr);
4837 // Load the array length. (Positive movl does right thing on LP64.)
4838 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4839 // Skip to start of data.
4840 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4841
4842 // Scan RCX words at [RDI] for an occurrence of RAX.
4843 // Set NZ/Z based on last compare.
4844 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4845 // not change flags (only scas instruction which is repeated sets flags).
4846 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4847
4848 testptr(rax,rax); // Set Z = 0
4849 repne_scan();
4850
4851 // Unspill the temp. registers:
4852 if (pushed_rdi) pop(rdi);
4853 if (pushed_rcx) pop(rcx);
4854 if (pushed_rax) pop(rax);
4855
4856 if (set_cond_codes) {
4857 // Special hack for the AD files: rdi is guaranteed non-zero.
4858 assert(!pushed_rdi, "rdi must be left non-null");
4859 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4860 }
4861
4862 if (L_failure == &L_fallthrough)
4863 jccb(Assembler::notEqual, *L_failure);
4864 else jcc(Assembler::notEqual, *L_failure);
4865
4866 // Success. Cache the super we found and proceed in triumph.
4867 movptr(super_cache_addr, super_klass);
4868
4869 if (L_success != &L_fallthrough) {
4870 jmp(*L_success);
4871 }
4872
4873 #undef IS_A_TEMP
4874
4875 bind(L_fallthrough);
4876 }
4877
4878 #ifndef _LP64
4879
4880 // 32-bit x86 only: always use the linear search.
4881 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4882 Register super_klass,
4883 Register temp_reg,
4884 Register temp2_reg,
4885 Label* L_success,
4886 Label* L_failure,
4887 bool set_cond_codes) {
4888 check_klass_subtype_slow_path_linear
4889 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
4890 }
4891
4892 #else // _LP64
4893
4894 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4895 Register super_klass,
4896 Register temp_reg,
4897 Register temp2_reg,
4898 Label* L_success,
4899 Label* L_failure,
4900 bool set_cond_codes) {
4901 assert(set_cond_codes == false, "must be false on 64-bit x86");
4902 check_klass_subtype_slow_path
4903 (sub_klass, super_klass, temp_reg, temp2_reg, noreg, noreg,
4904 L_success, L_failure);
4905 }
4906
4907 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4908 Register super_klass,
4909 Register temp_reg,
4910 Register temp2_reg,
4911 Register temp3_reg,
4912 Register temp4_reg,
4913 Label* L_success,
4914 Label* L_failure) {
4915 if (UseSecondarySupersTable) {
4916 check_klass_subtype_slow_path_table
4917 (sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, temp4_reg,
4918 L_success, L_failure);
4919 } else {
4920 check_klass_subtype_slow_path_linear
4921 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, /*set_cond_codes*/false);
4922 }
4923 }
4924
4925 Register MacroAssembler::allocate_if_noreg(Register r,
4926 RegSetIterator<Register> &available_regs,
4927 RegSet ®s_to_push) {
4928 if (!r->is_valid()) {
4929 r = *available_regs++;
4930 regs_to_push += r;
4931 }
4932 return r;
4933 }
4934
4935 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
4936 Register super_klass,
4937 Register temp_reg,
4938 Register temp2_reg,
4939 Register temp3_reg,
4940 Register result_reg,
4941 Label* L_success,
4942 Label* L_failure) {
4943 // NB! Callers may assume that, when temp2_reg is a valid register,
4944 // this code sets it to a nonzero value.
4945 bool temp2_reg_was_valid = temp2_reg->is_valid();
4946
4947 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
4948
4949 Label L_fallthrough;
4950 int label_nulls = 0;
4951 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4952 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4953 assert(label_nulls <= 1, "at most one null in the batch");
4954
4955 BLOCK_COMMENT("check_klass_subtype_slow_path_table");
4956
4957 RegSetIterator<Register> available_regs
4958 = (RegSet::of(rax, rcx, rdx, r8) + r9 + r10 + r11 + r12 - temps - sub_klass - super_klass).begin();
4959
4960 RegSet pushed_regs;
4961
4962 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
4963 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
4964 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
4965 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
4966 Register temp4_reg = allocate_if_noreg(noreg, available_regs, pushed_regs);
4967
4968 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, temp3_reg, result_reg);
4969
4970 {
4971
4972 int register_push_size = pushed_regs.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4973 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4974 subptr(rsp, aligned_size);
4975 push_set(pushed_regs, 0);
4976
4977 lookup_secondary_supers_table_var(sub_klass,
4978 super_klass,
4979 temp_reg, temp2_reg, temp3_reg, temp4_reg, result_reg);
4980 cmpq(result_reg, 0);
4981
4982 // Unspill the temp. registers:
4983 pop_set(pushed_regs, 0);
4984 // Increment SP but do not clobber flags.
4985 lea(rsp, Address(rsp, aligned_size));
4986 }
4987
4988 if (temp2_reg_was_valid) {
4989 movq(temp2_reg, 1);
4990 }
4991
4992 jcc(Assembler::notEqual, *L_failure);
4993
4994 if (L_success != &L_fallthrough) {
4995 jmp(*L_success);
4996 }
4997
4998 bind(L_fallthrough);
4999 }
5000
5001 // population_count variant for running without the POPCNT
5002 // instruction, which was introduced with SSE4.2 in 2008.
5003 void MacroAssembler::population_count(Register dst, Register src,
5004 Register scratch1, Register scratch2) {
5005 assert_different_registers(src, scratch1, scratch2);
5006 if (UsePopCountInstruction) {
5007 Assembler::popcntq(dst, src);
5008 } else {
5009 assert_different_registers(src, scratch1, scratch2);
5010 assert_different_registers(dst, scratch1, scratch2);
5011 Label loop, done;
5012
5013 mov(scratch1, src);
5014 // dst = 0;
5015 // while(scratch1 != 0) {
5016 // dst++;
5017 // scratch1 &= (scratch1 - 1);
5018 // }
5019 xorl(dst, dst);
5020 testq(scratch1, scratch1);
5021 jccb(Assembler::equal, done);
5022 {
5023 bind(loop);
5024 incq(dst);
5025 movq(scratch2, scratch1);
5026 decq(scratch2);
5027 andq(scratch1, scratch2);
5028 jccb(Assembler::notEqual, loop);
5029 }
5030 bind(done);
5031 }
5032 #ifdef ASSERT
5033 mov64(scratch1, 0xCafeBabeDeadBeef);
5034 movq(scratch2, scratch1);
5035 #endif
5036 }
5037
5038 // Ensure that the inline code and the stub are using the same registers.
5039 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
5040 do { \
5041 assert(r_super_klass == rax, "mismatch"); \
5042 assert(r_array_base == rbx, "mismatch"); \
5043 assert(r_array_length == rcx, "mismatch"); \
5044 assert(r_array_index == rdx, "mismatch"); \
5045 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
5046 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
5047 assert(result == rdi || result == noreg, "mismatch"); \
5048 } while(0)
5049
5050 // Versions of salq and rorq that don't need count to be in rcx
5051
5052 void MacroAssembler::salq(Register dest, Register count) {
5053 if (count == rcx) {
5054 Assembler::salq(dest);
5055 } else {
5056 assert_different_registers(rcx, dest);
5057 xchgq(rcx, count);
5058 Assembler::salq(dest);
5059 xchgq(rcx, count);
5060 }
5061 }
5062
5063 void MacroAssembler::rorq(Register dest, Register count) {
5064 if (count == rcx) {
5065 Assembler::rorq(dest);
5066 } else {
5067 assert_different_registers(rcx, dest);
5068 xchgq(rcx, count);
5069 Assembler::rorq(dest);
5070 xchgq(rcx, count);
5071 }
5072 }
5073
5074 // Return true: we succeeded in generating this code
5075 //
5076 // At runtime, return 0 in result if r_super_klass is a superclass of
5077 // r_sub_klass, otherwise return nonzero. Use this if you know the
5078 // super_klass_slot of the class you're looking for. This is always
5079 // the case for instanceof and checkcast.
5080 void MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
5081 Register r_super_klass,
5082 Register temp1,
5083 Register temp2,
5084 Register temp3,
5085 Register temp4,
5086 Register result,
5087 u1 super_klass_slot) {
5088 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5089
5090 Label L_fallthrough, L_success, L_failure;
5091
5092 BLOCK_COMMENT("lookup_secondary_supers_table {");
5093
5094 const Register
5095 r_array_index = temp1,
5096 r_array_length = temp2,
5097 r_array_base = temp3,
5098 r_bitmap = temp4;
5099
5100 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5101
5102 xorq(result, result); // = 0
5103
5104 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5105 movq(r_array_index, r_bitmap);
5106
5107 // First check the bitmap to see if super_klass might be present. If
5108 // the bit is zero, we are certain that super_klass is not one of
5109 // the secondary supers.
5110 u1 bit = super_klass_slot;
5111 {
5112 // NB: If the count in a x86 shift instruction is 0, the flags are
5113 // not affected, so we do a testq instead.
5114 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
5115 if (shift_count != 0) {
5116 salq(r_array_index, shift_count);
5117 } else {
5118 testq(r_array_index, r_array_index);
5119 }
5120 }
5121 // We test the MSB of r_array_index, i.e. its sign bit
5122 jcc(Assembler::positive, L_failure);
5123
5124 // Get the first array index that can contain super_klass into r_array_index.
5125 if (bit != 0) {
5126 population_count(r_array_index, r_array_index, temp2, temp3);
5127 } else {
5128 movl(r_array_index, 1);
5129 }
5130 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5131
5132 // We will consult the secondary-super array.
5133 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5134
5135 // We're asserting that the first word in an Array<Klass*> is the
5136 // length, and the second word is the first word of the data. If
5137 // that ever changes, r_array_base will have to be adjusted here.
5138 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5139 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5140
5141 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5142 jccb(Assembler::equal, L_success);
5143
5144 // Is there another entry to check? Consult the bitmap.
5145 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
5146 jccb(Assembler::carryClear, L_failure);
5147
5148 // Linear probe. Rotate the bitmap so that the next bit to test is
5149 // in Bit 1.
5150 if (bit != 0) {
5151 rorq(r_bitmap, bit);
5152 }
5153
5154 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5155 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5156 // Kills: r_array_length.
5157 // Returns: result.
5158 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
5159 // Result (0/1) is in rdi
5160 jmpb(L_fallthrough);
5161
5162 bind(L_failure);
5163 incq(result); // 0 => 1
5164
5165 bind(L_success);
5166 // result = 0;
5167
5168 bind(L_fallthrough);
5169 BLOCK_COMMENT("} lookup_secondary_supers_table");
5170
5171 if (VerifySecondarySupers) {
5172 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5173 temp1, temp2, temp3);
5174 }
5175 }
5176
5177 // At runtime, return 0 in result if r_super_klass is a superclass of
5178 // r_sub_klass, otherwise return nonzero. Use this version of
5179 // lookup_secondary_supers_table() if you don't know ahead of time
5180 // which superclass will be searched for. Used by interpreter and
5181 // runtime stubs. It is larger and has somewhat greater latency than
5182 // the version above, which takes a constant super_klass_slot.
5183 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
5184 Register r_super_klass,
5185 Register temp1,
5186 Register temp2,
5187 Register temp3,
5188 Register temp4,
5189 Register result) {
5190 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
5191 assert_different_registers(r_sub_klass, r_super_klass, rcx);
5192 RegSet temps = RegSet::of(temp1, temp2, temp3, temp4);
5193
5194 Label L_fallthrough, L_success, L_failure;
5195
5196 BLOCK_COMMENT("lookup_secondary_supers_table {");
5197
5198 RegSetIterator<Register> available_regs = (temps - rcx).begin();
5199
5200 // FIXME. Once we are sure that all paths reaching this point really
5201 // do pass rcx as one of our temps we can get rid of the following
5202 // workaround.
5203 assert(temps.contains(rcx), "fix this code");
5204
5205 // We prefer to have our shift count in rcx. If rcx is one of our
5206 // temps, use it for slot. If not, pick any of our temps.
5207 Register slot;
5208 if (!temps.contains(rcx)) {
5209 slot = *available_regs++;
5210 } else {
5211 slot = rcx;
5212 }
5213
5214 const Register r_array_index = *available_regs++;
5215 const Register r_bitmap = *available_regs++;
5216
5217 // The logic above guarantees this property, but we state it here.
5218 assert_different_registers(r_array_index, r_bitmap, rcx);
5219
5220 movq(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
5221 movq(r_array_index, r_bitmap);
5222
5223 // First check the bitmap to see if super_klass might be present. If
5224 // the bit is zero, we are certain that super_klass is not one of
5225 // the secondary supers.
5226 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5227 xorl(slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1)); // slot ^ 63 === 63 - slot (mod 64)
5228 salq(r_array_index, slot);
5229
5230 testq(r_array_index, r_array_index);
5231 // We test the MSB of r_array_index, i.e. its sign bit
5232 jcc(Assembler::positive, L_failure);
5233
5234 const Register r_array_base = *available_regs++;
5235
5236 // Get the first array index that can contain super_klass into r_array_index.
5237 // Note: Clobbers r_array_base and slot.
5238 population_count(r_array_index, r_array_index, /*temp2*/r_array_base, /*temp3*/slot);
5239
5240 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
5241
5242 // We will consult the secondary-super array.
5243 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5244
5245 // We're asserting that the first word in an Array<Klass*> is the
5246 // length, and the second word is the first word of the data. If
5247 // that ever changes, r_array_base will have to be adjusted here.
5248 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
5249 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
5250
5251 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5252 jccb(Assembler::equal, L_success);
5253
5254 // Restore slot to its true value
5255 movb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
5256
5257 // Linear probe. Rotate the bitmap so that the next bit to test is
5258 // in Bit 1.
5259 rorq(r_bitmap, slot);
5260
5261 // Is there another entry to check? Consult the bitmap.
5262 btq(r_bitmap, 1);
5263 jccb(Assembler::carryClear, L_failure);
5264
5265 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
5266 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
5267 // Kills: r_array_length.
5268 // Returns: result.
5269 lookup_secondary_supers_table_slow_path(r_super_klass,
5270 r_array_base,
5271 r_array_index,
5272 r_bitmap,
5273 /*temp1*/result,
5274 /*temp2*/slot,
5275 &L_success,
5276 nullptr);
5277
5278 bind(L_failure);
5279 movq(result, 1);
5280 jmpb(L_fallthrough);
5281
5282 bind(L_success);
5283 xorq(result, result); // = 0
5284
5285 bind(L_fallthrough);
5286 BLOCK_COMMENT("} lookup_secondary_supers_table");
5287
5288 if (VerifySecondarySupers) {
5289 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
5290 temp1, temp2, temp3);
5291 }
5292 }
5293
5294 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
5295 Label* L_success, Label* L_failure) {
5296 Label L_loop, L_fallthrough;
5297 {
5298 int label_nulls = 0;
5299 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5300 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5301 assert(label_nulls <= 1, "at most one null in the batch");
5302 }
5303 bind(L_loop);
5304 cmpq(value, Address(addr, count, Address::times_8));
5305 jcc(Assembler::equal, *L_success);
5306 addl(count, 1);
5307 cmpl(count, limit);
5308 jcc(Assembler::less, L_loop);
5309
5310 if (&L_fallthrough != L_failure) {
5311 jmp(*L_failure);
5312 }
5313 bind(L_fallthrough);
5314 }
5315
5316 // Called by code generated by check_klass_subtype_slow_path
5317 // above. This is called when there is a collision in the hashed
5318 // lookup in the secondary supers array.
5319 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
5320 Register r_array_base,
5321 Register r_array_index,
5322 Register r_bitmap,
5323 Register temp1,
5324 Register temp2,
5325 Label* L_success,
5326 Label* L_failure) {
5327 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
5328
5329 const Register
5330 r_array_length = temp1,
5331 r_sub_klass = noreg,
5332 result = noreg;
5333
5334 Label L_fallthrough;
5335 int label_nulls = 0;
5336 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
5337 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
5338 assert(label_nulls <= 1, "at most one null in the batch");
5339
5340 // Load the array length.
5341 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5342 // And adjust the array base to point to the data.
5343 // NB! Effectively increments current slot index by 1.
5344 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
5345 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5346
5347 // Linear probe
5348 Label L_huge;
5349
5350 // The bitmap is full to bursting.
5351 // Implicit invariant: BITMAP_FULL implies (length > 0)
5352 cmpl(r_array_length, (int32_t)Klass::SECONDARY_SUPERS_TABLE_SIZE - 2);
5353 jcc(Assembler::greater, L_huge);
5354
5355 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
5356 // current slot (at secondary_supers[r_array_index]) has not yet
5357 // been inspected, and r_array_index may be out of bounds if we
5358 // wrapped around the end of the array.
5359
5360 { // This is conventional linear probing, but instead of terminating
5361 // when a null entry is found in the table, we maintain a bitmap
5362 // in which a 0 indicates missing entries.
5363 // The check above guarantees there are 0s in the bitmap, so the loop
5364 // eventually terminates.
5365
5366 xorl(temp2, temp2); // = 0;
5367
5368 Label L_again;
5369 bind(L_again);
5370
5371 // Check for array wraparound.
5372 cmpl(r_array_index, r_array_length);
5373 cmovl(Assembler::greaterEqual, r_array_index, temp2);
5374
5375 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
5376 jcc(Assembler::equal, *L_success);
5377
5378 // If the next bit in bitmap is zero, we're done.
5379 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
5380 jcc(Assembler::carryClear, *L_failure);
5381
5382 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
5383 addl(r_array_index, 1);
5384
5385 jmp(L_again);
5386 }
5387
5388 { // Degenerate case: more than 64 secondary supers.
5389 // FIXME: We could do something smarter here, maybe a vectorized
5390 // comparison or a binary search, but is that worth any added
5391 // complexity?
5392 bind(L_huge);
5393 xorl(r_array_index, r_array_index); // = 0
5394 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
5395 L_success,
5396 (&L_fallthrough != L_failure ? L_failure : nullptr));
5397
5398 bind(L_fallthrough);
5399 }
5400 }
5401
5402 struct VerifyHelperArguments {
5403 Klass* _super;
5404 Klass* _sub;
5405 intptr_t _linear_result;
5406 intptr_t _table_result;
5407 };
5408
5409 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5410 Klass::on_secondary_supers_verification_failure(args->_super,
5411 args->_sub,
5412 args->_linear_result,
5413 args->_table_result,
5414 msg);
5415 }
5416
5417 // Make sure that the hashed lookup and a linear scan agree.
5418 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5419 Register r_super_klass,
5420 Register result,
5421 Register temp1,
5422 Register temp2,
5423 Register temp3) {
5424 const Register
5425 r_array_index = temp1,
5426 r_array_length = temp2,
5427 r_array_base = temp3,
5428 r_bitmap = noreg;
5429
5430 BLOCK_COMMENT("verify_secondary_supers_table {");
5431
5432 Label L_success, L_failure, L_check, L_done;
5433
5434 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5435 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5436 // And adjust the array base to point to the data.
5437 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5438
5439 testl(r_array_length, r_array_length); // array_length == 0?
5440 jcc(Assembler::zero, L_failure);
5441
5442 movl(r_array_index, 0);
5443 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5444 // fall through to L_failure
5445
5446 const Register linear_result = r_array_index; // reuse temp1
5447
5448 bind(L_failure); // not present
5449 movl(linear_result, 1);
5450 jmp(L_check);
5451
5452 bind(L_success); // present
5453 movl(linear_result, 0);
5454
5455 bind(L_check);
5456 cmpl(linear_result, result);
5457 jcc(Assembler::equal, L_done);
5458
5459 { // To avoid calling convention issues, build a record on the stack
5460 // and pass the pointer to that instead.
5461 push(result);
5462 push(linear_result);
5463 push(r_sub_klass);
5464 push(r_super_klass);
5465 movptr(c_rarg1, rsp);
5466 movptr(c_rarg0, (uintptr_t) "mismatch");
5467 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5468 should_not_reach_here();
5469 }
5470 bind(L_done);
5471
5472 BLOCK_COMMENT("} verify_secondary_supers_table");
5473 }
5474
5475 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5476
5477 #endif // LP64
5478
5479 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5480 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5481
5482 Label L_fallthrough;
5483 if (L_fast_path == nullptr) {
5484 L_fast_path = &L_fallthrough;
5485 } else if (L_slow_path == nullptr) {
5486 L_slow_path = &L_fallthrough;
5487 }
5488
5489 // Fast path check: class is fully initialized.
5490 // init_state needs acquire, but x86 is TSO, and so we are already good.
5491 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5492 jcc(Assembler::equal, *L_fast_path);
5493
5494 // Fast path check: current thread is initializer thread
5495 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5496 if (L_slow_path == &L_fallthrough) {
5497 jcc(Assembler::equal, *L_fast_path);
5498 bind(*L_slow_path);
5499 } else if (L_fast_path == &L_fallthrough) {
5500 jcc(Assembler::notEqual, *L_slow_path);
5501 bind(*L_fast_path);
5502 } else {
5503 Unimplemented();
5504 }
5505 }
5506
5507 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5508 if (VM_Version::supports_cmov()) {
5509 cmovl(cc, dst, src);
5510 } else {
5511 Label L;
5512 jccb(negate_condition(cc), L);
5513 movl(dst, src);
5514 bind(L);
5515 }
5516 }
5517
5518 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5519 if (VM_Version::supports_cmov()) {
5520 cmovl(cc, dst, src);
5521 } else {
5522 Label L;
5523 jccb(negate_condition(cc), L);
5524 movl(dst, src);
5525 bind(L);
5526 }
5527 }
5528
5529 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5530 if (!VerifyOops) return;
5531
5532 BLOCK_COMMENT("verify_oop {");
5533 #ifdef _LP64
5534 push(rscratch1);
5535 #endif
5536 push(rax); // save rax
5537 push(reg); // pass register argument
5538
5539 // Pass register number to verify_oop_subroutine
5540 const char* b = nullptr;
5541 {
5542 ResourceMark rm;
5543 stringStream ss;
5544 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5545 b = code_string(ss.as_string());
5546 }
5547 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5548 pushptr(buffer.addr(), rscratch1);
5549
5550 // call indirectly to solve generation ordering problem
5551 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5552 call(rax);
5553 // Caller pops the arguments (oop, message) and restores rax, r10
5554 BLOCK_COMMENT("} verify_oop");
5555 }
5556
5557 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5558 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5559 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5560 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5561 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5562 } else if (VM_Version::supports_avx()) {
5563 vpcmpeqd(dst, dst, dst, vector_len);
5564 } else {
5565 pcmpeqd(dst, dst);
5566 }
5567 }
5568
5569 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5570 int extra_slot_offset) {
5571 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5572 int stackElementSize = Interpreter::stackElementSize;
5573 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5574 #ifdef ASSERT
5575 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5576 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5577 #endif
5578 Register scale_reg = noreg;
5579 Address::ScaleFactor scale_factor = Address::no_scale;
5580 if (arg_slot.is_constant()) {
5581 offset += arg_slot.as_constant() * stackElementSize;
5582 } else {
5583 scale_reg = arg_slot.as_register();
5584 scale_factor = Address::times(stackElementSize);
5585 }
5586 offset += wordSize; // return PC is on stack
5587 return Address(rsp, scale_reg, scale_factor, offset);
5588 }
5589
5590 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5591 if (!VerifyOops) return;
5592
5593 #ifdef _LP64
5594 push(rscratch1);
5595 #endif
5596 push(rax); // save rax,
5597 // addr may contain rsp so we will have to adjust it based on the push
5598 // we just did (and on 64 bit we do two pushes)
5599 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5600 // stores rax into addr which is backwards of what was intended.
5601 if (addr.uses(rsp)) {
5602 lea(rax, addr);
5603 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5604 } else {
5605 pushptr(addr);
5606 }
5607
5608 // Pass register number to verify_oop_subroutine
5609 const char* b = nullptr;
5610 {
5611 ResourceMark rm;
5612 stringStream ss;
5613 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5614 b = code_string(ss.as_string());
5615 }
5616 AddressLiteral buffer((address) b, external_word_Relocation::spec_for_immediate());
5617 pushptr(buffer.addr(), rscratch1);
5618
5619 // call indirectly to solve generation ordering problem
5620 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5621 call(rax);
5622 // Caller pops the arguments (addr, message) and restores rax, r10.
5623 }
5624
5625 void MacroAssembler::verify_tlab() {
5626 #ifdef ASSERT
5627 if (UseTLAB && VerifyOops) {
5628 Label next, ok;
5629 Register t1 = rsi;
5630 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5631
5632 push(t1);
5633 NOT_LP64(push(thread_reg));
5634 NOT_LP64(get_thread(thread_reg));
5635
5636 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5637 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5638 jcc(Assembler::aboveEqual, next);
5639 STOP("assert(top >= start)");
5640 should_not_reach_here();
5641
5642 bind(next);
5643 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5644 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5645 jcc(Assembler::aboveEqual, ok);
5646 STOP("assert(top <= end)");
5647 should_not_reach_here();
5648
5649 bind(ok);
5650 NOT_LP64(pop(thread_reg));
5651 pop(t1);
5652 }
5653 #endif
5654 }
5655
5656 class ControlWord {
5657 public:
5658 int32_t _value;
5659
5660 int rounding_control() const { return (_value >> 10) & 3 ; }
5661 int precision_control() const { return (_value >> 8) & 3 ; }
5662 bool precision() const { return ((_value >> 5) & 1) != 0; }
5663 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5664 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5665 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5666 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5667 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5668
5669 void print() const {
5670 // rounding control
5671 const char* rc;
5672 switch (rounding_control()) {
5673 case 0: rc = "round near"; break;
5674 case 1: rc = "round down"; break;
5675 case 2: rc = "round up "; break;
5676 case 3: rc = "chop "; break;
5677 default:
5678 rc = nullptr; // silence compiler warnings
5679 fatal("Unknown rounding control: %d", rounding_control());
5680 };
5681 // precision control
5682 const char* pc;
5683 switch (precision_control()) {
5684 case 0: pc = "24 bits "; break;
5685 case 1: pc = "reserved"; break;
5686 case 2: pc = "53 bits "; break;
5687 case 3: pc = "64 bits "; break;
5688 default:
5689 pc = nullptr; // silence compiler warnings
5690 fatal("Unknown precision control: %d", precision_control());
5691 };
5692 // flags
5693 char f[9];
5694 f[0] = ' ';
5695 f[1] = ' ';
5696 f[2] = (precision ()) ? 'P' : 'p';
5697 f[3] = (underflow ()) ? 'U' : 'u';
5698 f[4] = (overflow ()) ? 'O' : 'o';
5699 f[5] = (zero_divide ()) ? 'Z' : 'z';
5700 f[6] = (denormalized()) ? 'D' : 'd';
5701 f[7] = (invalid ()) ? 'I' : 'i';
5702 f[8] = '\x0';
5703 // output
5704 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5705 }
5706
5707 };
5708
5709 class StatusWord {
5710 public:
5711 int32_t _value;
5712
5713 bool busy() const { return ((_value >> 15) & 1) != 0; }
5714 bool C3() const { return ((_value >> 14) & 1) != 0; }
5715 bool C2() const { return ((_value >> 10) & 1) != 0; }
5716 bool C1() const { return ((_value >> 9) & 1) != 0; }
5717 bool C0() const { return ((_value >> 8) & 1) != 0; }
5718 int top() const { return (_value >> 11) & 7 ; }
5719 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5720 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5721 bool precision() const { return ((_value >> 5) & 1) != 0; }
5722 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5723 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5724 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5725 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5726 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5727
5728 void print() const {
5729 // condition codes
5730 char c[5];
5731 c[0] = (C3()) ? '3' : '-';
5732 c[1] = (C2()) ? '2' : '-';
5733 c[2] = (C1()) ? '1' : '-';
5734 c[3] = (C0()) ? '0' : '-';
5735 c[4] = '\x0';
5736 // flags
5737 char f[9];
5738 f[0] = (error_status()) ? 'E' : '-';
5739 f[1] = (stack_fault ()) ? 'S' : '-';
5740 f[2] = (precision ()) ? 'P' : '-';
5741 f[3] = (underflow ()) ? 'U' : '-';
5742 f[4] = (overflow ()) ? 'O' : '-';
5743 f[5] = (zero_divide ()) ? 'Z' : '-';
5744 f[6] = (denormalized()) ? 'D' : '-';
5745 f[7] = (invalid ()) ? 'I' : '-';
5746 f[8] = '\x0';
5747 // output
5748 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5749 }
5750
5751 };
5752
5753 class TagWord {
5754 public:
5755 int32_t _value;
5756
5757 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5758
5759 void print() const {
5760 printf("%04x", _value & 0xFFFF);
5761 }
5762
5763 };
5764
5765 class FPU_Register {
5766 public:
5767 int32_t _m0;
5768 int32_t _m1;
5769 int16_t _ex;
5770
5771 bool is_indefinite() const {
5772 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5773 }
5774
5775 void print() const {
5776 char sign = (_ex < 0) ? '-' : '+';
5777 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5778 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5779 };
5780
5781 };
5782
5783 class FPU_State {
5784 public:
5785 enum {
5786 register_size = 10,
5787 number_of_registers = 8,
5788 register_mask = 7
5789 };
5790
5791 ControlWord _control_word;
5792 StatusWord _status_word;
5793 TagWord _tag_word;
5794 int32_t _error_offset;
5795 int32_t _error_selector;
5796 int32_t _data_offset;
5797 int32_t _data_selector;
5798 int8_t _register[register_size * number_of_registers];
5799
5800 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5801 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5802
5803 const char* tag_as_string(int tag) const {
5804 switch (tag) {
5805 case 0: return "valid";
5806 case 1: return "zero";
5807 case 2: return "special";
5808 case 3: return "empty";
5809 }
5810 ShouldNotReachHere();
5811 return nullptr;
5812 }
5813
5814 void print() const {
5815 // print computation registers
5816 { int t = _status_word.top();
5817 for (int i = 0; i < number_of_registers; i++) {
5818 int j = (i - t) & register_mask;
5819 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5820 st(j)->print();
5821 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5822 }
5823 }
5824 printf("\n");
5825 // print control registers
5826 printf("ctrl = "); _control_word.print(); printf("\n");
5827 printf("stat = "); _status_word .print(); printf("\n");
5828 printf("tags = "); _tag_word .print(); printf("\n");
5829 }
5830
5831 };
5832
5833 class Flag_Register {
5834 public:
5835 int32_t _value;
5836
5837 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5838 bool direction() const { return ((_value >> 10) & 1) != 0; }
5839 bool sign() const { return ((_value >> 7) & 1) != 0; }
5840 bool zero() const { return ((_value >> 6) & 1) != 0; }
5841 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5842 bool parity() const { return ((_value >> 2) & 1) != 0; }
5843 bool carry() const { return ((_value >> 0) & 1) != 0; }
5844
5845 void print() const {
5846 // flags
5847 char f[8];
5848 f[0] = (overflow ()) ? 'O' : '-';
5849 f[1] = (direction ()) ? 'D' : '-';
5850 f[2] = (sign ()) ? 'S' : '-';
5851 f[3] = (zero ()) ? 'Z' : '-';
5852 f[4] = (auxiliary_carry()) ? 'A' : '-';
5853 f[5] = (parity ()) ? 'P' : '-';
5854 f[6] = (carry ()) ? 'C' : '-';
5855 f[7] = '\x0';
5856 // output
5857 printf("%08x flags = %s", _value, f);
5858 }
5859
5860 };
5861
5862 class IU_Register {
5863 public:
5864 int32_t _value;
5865
5866 void print() const {
5867 printf("%08x %11d", _value, _value);
5868 }
5869
5870 };
5871
5872 class IU_State {
5873 public:
5874 Flag_Register _eflags;
5875 IU_Register _rdi;
5876 IU_Register _rsi;
5877 IU_Register _rbp;
5878 IU_Register _rsp;
5879 IU_Register _rbx;
5880 IU_Register _rdx;
5881 IU_Register _rcx;
5882 IU_Register _rax;
5883
5884 void print() const {
5885 // computation registers
5886 printf("rax, = "); _rax.print(); printf("\n");
5887 printf("rbx, = "); _rbx.print(); printf("\n");
5888 printf("rcx = "); _rcx.print(); printf("\n");
5889 printf("rdx = "); _rdx.print(); printf("\n");
5890 printf("rdi = "); _rdi.print(); printf("\n");
5891 printf("rsi = "); _rsi.print(); printf("\n");
5892 printf("rbp, = "); _rbp.print(); printf("\n");
5893 printf("rsp = "); _rsp.print(); printf("\n");
5894 printf("\n");
5895 // control registers
5896 printf("flgs = "); _eflags.print(); printf("\n");
5897 }
5898 };
5899
5900
5901 class CPU_State {
5902 public:
5903 FPU_State _fpu_state;
5904 IU_State _iu_state;
5905
5906 void print() const {
5907 printf("--------------------------------------------------\n");
5908 _iu_state .print();
5909 printf("\n");
5910 _fpu_state.print();
5911 printf("--------------------------------------------------\n");
5912 }
5913
5914 };
5915
5916
5917 static void _print_CPU_state(CPU_State* state) {
5918 state->print();
5919 };
5920
5921
5922 void MacroAssembler::print_CPU_state() {
5923 push_CPU_state();
5924 push(rsp); // pass CPU state
5925 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5926 addptr(rsp, wordSize); // discard argument
5927 pop_CPU_state();
5928 }
5929
5930
5931 #ifndef _LP64
5932 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5933 static int counter = 0;
5934 FPU_State* fs = &state->_fpu_state;
5935 counter++;
5936 // For leaf calls, only verify that the top few elements remain empty.
5937 // We only need 1 empty at the top for C2 code.
5938 if( stack_depth < 0 ) {
5939 if( fs->tag_for_st(7) != 3 ) {
5940 printf("FPR7 not empty\n");
5941 state->print();
5942 assert(false, "error");
5943 return false;
5944 }
5945 return true; // All other stack states do not matter
5946 }
5947
5948 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5949 "bad FPU control word");
5950
5951 // compute stack depth
5952 int i = 0;
5953 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5954 int d = i;
5955 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5956 // verify findings
5957 if (i != FPU_State::number_of_registers) {
5958 // stack not contiguous
5959 printf("%s: stack not contiguous at ST%d\n", s, i);
5960 state->print();
5961 assert(false, "error");
5962 return false;
5963 }
5964 // check if computed stack depth corresponds to expected stack depth
5965 if (stack_depth < 0) {
5966 // expected stack depth is -stack_depth or less
5967 if (d > -stack_depth) {
5968 // too many elements on the stack
5969 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5970 state->print();
5971 assert(false, "error");
5972 return false;
5973 }
5974 } else {
5975 // expected stack depth is stack_depth
5976 if (d != stack_depth) {
5977 // wrong stack depth
5978 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5979 state->print();
5980 assert(false, "error");
5981 return false;
5982 }
5983 }
5984 // everything is cool
5985 return true;
5986 }
5987
5988 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5989 if (!VerifyFPU) return;
5990 push_CPU_state();
5991 push(rsp); // pass CPU state
5992 ExternalAddress msg((address) s);
5993 // pass message string s
5994 pushptr(msg.addr(), noreg);
5995 push(stack_depth); // pass stack depth
5996 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5997 addptr(rsp, 3 * wordSize); // discard arguments
5998 // check for error
5999 { Label L;
6000 testl(rax, rax);
6001 jcc(Assembler::notZero, L);
6002 int3(); // break if error condition
6003 bind(L);
6004 }
6005 pop_CPU_state();
6006 }
6007 #endif // _LP64
6008
6009 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
6010 // Either restore the MXCSR register after returning from the JNI Call
6011 // or verify that it wasn't changed (with -Xcheck:jni flag).
6012 if (VM_Version::supports_sse()) {
6013 if (RestoreMXCSROnJNICalls) {
6014 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
6015 } else if (CheckJNICalls) {
6016 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
6017 }
6018 }
6019 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
6020 vzeroupper();
6021
6022 #ifndef _LP64
6023 // Either restore the x87 floating pointer control word after returning
6024 // from the JNI call or verify that it wasn't changed.
6025 if (CheckJNICalls) {
6026 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
6027 }
6028 #endif // _LP64
6029 }
6030
6031 // ((OopHandle)result).resolve();
6032 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
6033 assert_different_registers(result, tmp);
6034
6035 // Only 64 bit platforms support GCs that require a tmp register
6036 // Only IN_HEAP loads require a thread_tmp register
6037 // OopHandle::resolve is an indirection like jobject.
6038 access_load_at(T_OBJECT, IN_NATIVE,
6039 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
6040 }
6041
6042 // ((WeakHandle)result).resolve();
6043 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
6044 assert_different_registers(rresult, rtmp);
6045 Label resolved;
6046
6047 // A null weak handle resolves to null.
6048 cmpptr(rresult, 0);
6049 jcc(Assembler::equal, resolved);
6050
6051 // Only 64 bit platforms support GCs that require a tmp register
6052 // Only IN_HEAP loads require a thread_tmp register
6053 // WeakHandle::resolve is an indirection like jweak.
6054 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
6055 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
6056 bind(resolved);
6057 }
6058
6059 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
6060 // get mirror
6061 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
6062 load_method_holder(mirror, method);
6063 movptr(mirror, Address(mirror, mirror_offset));
6064 resolve_oop_handle(mirror, tmp);
6065 }
6066
6067 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
6068 load_method_holder(rresult, rmethod);
6069 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
6070 }
6071
6072 void MacroAssembler::load_method_holder(Register holder, Register method) {
6073 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
6074 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
6075 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
6076 }
6077
6078 #ifdef _LP64
6079 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
6080 assert(UseCompactObjectHeaders, "expect compact object headers");
6081 movl(dst, Address(src, oopDesc::mark_offset_in_bytes()));
6082 shrl(dst, markWord::klass_shift);
6083 }
6084 #endif
6085
6086 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
6087 assert_different_registers(src, tmp);
6088 assert_different_registers(dst, tmp);
6089 #ifdef _LP64
6090 if (UseCompactObjectHeaders) {
6091 load_narrow_klass_compact(dst, src);
6092 decode_klass_not_null(dst, tmp);
6093 } else if (UseCompressedClassPointers) {
6094 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6095 decode_klass_not_null(dst, tmp);
6096 } else
6097 #endif
6098 {
6099 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
6100 }
6101 }
6102
6103 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
6104 assert(!UseCompactObjectHeaders, "not with compact headers");
6105 assert_different_registers(src, tmp);
6106 assert_different_registers(dst, tmp);
6107 #ifdef _LP64
6108 if (UseCompressedClassPointers) {
6109 encode_klass_not_null(src, tmp);
6110 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6111 } else
6112 #endif
6113 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
6114 }
6115
6116 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
6117 #ifdef _LP64
6118 if (UseCompactObjectHeaders) {
6119 assert(tmp != noreg, "need tmp");
6120 assert_different_registers(klass, obj, tmp);
6121 load_narrow_klass_compact(tmp, obj);
6122 cmpl(klass, tmp);
6123 } else if (UseCompressedClassPointers) {
6124 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6125 } else
6126 #endif
6127 {
6128 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
6129 }
6130 }
6131
6132 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
6133 #ifdef _LP64
6134 if (UseCompactObjectHeaders) {
6135 assert(tmp2 != noreg, "need tmp2");
6136 assert_different_registers(obj1, obj2, tmp1, tmp2);
6137 load_narrow_klass_compact(tmp1, obj1);
6138 load_narrow_klass_compact(tmp2, obj2);
6139 cmpl(tmp1, tmp2);
6140 } else if (UseCompressedClassPointers) {
6141 movl(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6142 cmpl(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6143 } else
6144 #endif
6145 {
6146 movptr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
6147 cmpptr(tmp1, Address(obj2, oopDesc::klass_offset_in_bytes()));
6148 }
6149 }
6150
6151 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
6152 Register tmp1, Register thread_tmp) {
6153 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6154 decorators = AccessInternal::decorator_fixup(decorators, type);
6155 bool as_raw = (decorators & AS_RAW) != 0;
6156 if (as_raw) {
6157 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6158 } else {
6159 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
6160 }
6161 }
6162
6163 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
6164 Register tmp1, Register tmp2, Register tmp3) {
6165 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
6166 decorators = AccessInternal::decorator_fixup(decorators, type);
6167 bool as_raw = (decorators & AS_RAW) != 0;
6168 if (as_raw) {
6169 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6170 } else {
6171 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
6172 }
6173 }
6174
6175 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
6176 Register thread_tmp, DecoratorSet decorators) {
6177 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
6178 }
6179
6180 // Doesn't do verification, generates fixed size code
6181 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
6182 Register thread_tmp, DecoratorSet decorators) {
6183 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
6184 }
6185
6186 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
6187 Register tmp2, Register tmp3, DecoratorSet decorators) {
6188 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
6189 }
6190
6191 // Used for storing nulls.
6192 void MacroAssembler::store_heap_oop_null(Address dst) {
6193 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
6194 }
6195
6196 #ifdef _LP64
6197 void MacroAssembler::store_klass_gap(Register dst, Register src) {
6198 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
6199 if (UseCompressedClassPointers) {
6200 // Store to klass gap in destination
6201 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
6202 }
6203 }
6204
6205 #ifdef ASSERT
6206 void MacroAssembler::verify_heapbase(const char* msg) {
6207 assert (UseCompressedOops, "should be compressed");
6208 assert (Universe::heap() != nullptr, "java heap should be initialized");
6209 if (CheckCompressedOops) {
6210 Label ok;
6211 ExternalAddress src2(CompressedOops::base_addr());
6212 const bool is_src2_reachable = reachable(src2);
6213 if (!is_src2_reachable) {
6214 push(rscratch1); // cmpptr trashes rscratch1
6215 }
6216 cmpptr(r12_heapbase, src2, rscratch1);
6217 jcc(Assembler::equal, ok);
6218 STOP(msg);
6219 bind(ok);
6220 if (!is_src2_reachable) {
6221 pop(rscratch1);
6222 }
6223 }
6224 }
6225 #endif
6226
6227 // Algorithm must match oop.inline.hpp encode_heap_oop.
6228 void MacroAssembler::encode_heap_oop(Register r) {
6229 #ifdef ASSERT
6230 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
6231 #endif
6232 verify_oop_msg(r, "broken oop in encode_heap_oop");
6233 if (CompressedOops::base() == nullptr) {
6234 if (CompressedOops::shift() != 0) {
6235 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6236 shrq(r, LogMinObjAlignmentInBytes);
6237 }
6238 return;
6239 }
6240 testq(r, r);
6241 cmovq(Assembler::equal, r, r12_heapbase);
6242 subq(r, r12_heapbase);
6243 shrq(r, LogMinObjAlignmentInBytes);
6244 }
6245
6246 void MacroAssembler::encode_heap_oop_not_null(Register r) {
6247 #ifdef ASSERT
6248 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
6249 if (CheckCompressedOops) {
6250 Label ok;
6251 testq(r, r);
6252 jcc(Assembler::notEqual, ok);
6253 STOP("null oop passed to encode_heap_oop_not_null");
6254 bind(ok);
6255 }
6256 #endif
6257 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
6258 if (CompressedOops::base() != nullptr) {
6259 subq(r, r12_heapbase);
6260 }
6261 if (CompressedOops::shift() != 0) {
6262 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6263 shrq(r, LogMinObjAlignmentInBytes);
6264 }
6265 }
6266
6267 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
6268 #ifdef ASSERT
6269 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
6270 if (CheckCompressedOops) {
6271 Label ok;
6272 testq(src, src);
6273 jcc(Assembler::notEqual, ok);
6274 STOP("null oop passed to encode_heap_oop_not_null2");
6275 bind(ok);
6276 }
6277 #endif
6278 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
6279 if (dst != src) {
6280 movq(dst, src);
6281 }
6282 if (CompressedOops::base() != nullptr) {
6283 subq(dst, r12_heapbase);
6284 }
6285 if (CompressedOops::shift() != 0) {
6286 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6287 shrq(dst, LogMinObjAlignmentInBytes);
6288 }
6289 }
6290
6291 void MacroAssembler::decode_heap_oop(Register r) {
6292 #ifdef ASSERT
6293 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
6294 #endif
6295 if (CompressedOops::base() == nullptr) {
6296 if (CompressedOops::shift() != 0) {
6297 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6298 shlq(r, LogMinObjAlignmentInBytes);
6299 }
6300 } else {
6301 Label done;
6302 shlq(r, LogMinObjAlignmentInBytes);
6303 jccb(Assembler::equal, done);
6304 addq(r, r12_heapbase);
6305 bind(done);
6306 }
6307 verify_oop_msg(r, "broken oop in decode_heap_oop");
6308 }
6309
6310 void MacroAssembler::decode_heap_oop_not_null(Register r) {
6311 // Note: it will change flags
6312 assert (UseCompressedOops, "should only be used for compressed headers");
6313 assert (Universe::heap() != nullptr, "java heap should be initialized");
6314 // Cannot assert, unverified entry point counts instructions (see .ad file)
6315 // vtableStubs also counts instructions in pd_code_size_limit.
6316 // Also do not verify_oop as this is called by verify_oop.
6317 if (CompressedOops::shift() != 0) {
6318 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6319 shlq(r, LogMinObjAlignmentInBytes);
6320 if (CompressedOops::base() != nullptr) {
6321 addq(r, r12_heapbase);
6322 }
6323 } else {
6324 assert (CompressedOops::base() == nullptr, "sanity");
6325 }
6326 }
6327
6328 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
6329 // Note: it will change flags
6330 assert (UseCompressedOops, "should only be used for compressed headers");
6331 assert (Universe::heap() != nullptr, "java heap should be initialized");
6332 // Cannot assert, unverified entry point counts instructions (see .ad file)
6333 // vtableStubs also counts instructions in pd_code_size_limit.
6334 // Also do not verify_oop as this is called by verify_oop.
6335 if (CompressedOops::shift() != 0) {
6336 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
6337 if (LogMinObjAlignmentInBytes == Address::times_8) {
6338 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
6339 } else {
6340 if (dst != src) {
6341 movq(dst, src);
6342 }
6343 shlq(dst, LogMinObjAlignmentInBytes);
6344 if (CompressedOops::base() != nullptr) {
6345 addq(dst, r12_heapbase);
6346 }
6347 }
6348 } else {
6349 assert (CompressedOops::base() == nullptr, "sanity");
6350 if (dst != src) {
6351 movq(dst, src);
6352 }
6353 }
6354 }
6355
6356 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
6357 assert_different_registers(r, tmp);
6358 if (CompressedKlassPointers::base() != nullptr) {
6359 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6360 subq(r, tmp);
6361 }
6362 if (CompressedKlassPointers::shift() != 0) {
6363 shrq(r, CompressedKlassPointers::shift());
6364 }
6365 }
6366
6367 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
6368 assert_different_registers(src, dst);
6369 if (CompressedKlassPointers::base() != nullptr) {
6370 mov64(dst, -(int64_t)CompressedKlassPointers::base());
6371 addq(dst, src);
6372 } else {
6373 movptr(dst, src);
6374 }
6375 if (CompressedKlassPointers::shift() != 0) {
6376 shrq(dst, CompressedKlassPointers::shift());
6377 }
6378 }
6379
6380 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
6381 assert_different_registers(r, tmp);
6382 // Note: it will change flags
6383 assert(UseCompressedClassPointers, "should only be used for compressed headers");
6384 // Cannot assert, unverified entry point counts instructions (see .ad file)
6385 // vtableStubs also counts instructions in pd_code_size_limit.
6386 // Also do not verify_oop as this is called by verify_oop.
6387 if (CompressedKlassPointers::shift() != 0) {
6388 shlq(r, CompressedKlassPointers::shift());
6389 }
6390 if (CompressedKlassPointers::base() != nullptr) {
6391 mov64(tmp, (int64_t)CompressedKlassPointers::base());
6392 addq(r, tmp);
6393 }
6394 }
6395
6396 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
6397 assert_different_registers(src, dst);
6398 // Note: it will change flags
6399 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6400 // Cannot assert, unverified entry point counts instructions (see .ad file)
6401 // vtableStubs also counts instructions in pd_code_size_limit.
6402 // Also do not verify_oop as this is called by verify_oop.
6403
6404 if (CompressedKlassPointers::base() == nullptr &&
6405 CompressedKlassPointers::shift() == 0) {
6406 // The best case scenario is that there is no base or shift. Then it is already
6407 // a pointer that needs nothing but a register rename.
6408 movl(dst, src);
6409 } else {
6410 if (CompressedKlassPointers::shift() <= Address::times_8) {
6411 if (CompressedKlassPointers::base() != nullptr) {
6412 mov64(dst, (int64_t)CompressedKlassPointers::base());
6413 } else {
6414 xorq(dst, dst);
6415 }
6416 if (CompressedKlassPointers::shift() != 0) {
6417 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6418 leaq(dst, Address(dst, src, Address::times_8, 0));
6419 } else {
6420 addq(dst, src);
6421 }
6422 } else {
6423 if (CompressedKlassPointers::base() != nullptr) {
6424 const uint64_t base_right_shifted =
6425 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6426 mov64(dst, base_right_shifted);
6427 } else {
6428 xorq(dst, dst);
6429 }
6430 addq(dst, src);
6431 shlq(dst, CompressedKlassPointers::shift());
6432 }
6433 }
6434 }
6435
6436 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6437 assert (UseCompressedOops, "should only be used for compressed headers");
6438 assert (Universe::heap() != nullptr, "java heap should be initialized");
6439 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6440 int oop_index = oop_recorder()->find_index(obj);
6441 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6442 mov_narrow_oop(dst, oop_index, rspec);
6443 }
6444
6445 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6446 assert (UseCompressedOops, "should only be used for compressed headers");
6447 assert (Universe::heap() != nullptr, "java heap should be initialized");
6448 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6449 int oop_index = oop_recorder()->find_index(obj);
6450 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6451 mov_narrow_oop(dst, oop_index, rspec);
6452 }
6453
6454 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6455 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6456 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6457 int klass_index = oop_recorder()->find_index(k);
6458 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6459 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6460 }
6461
6462 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6463 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6464 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6465 int klass_index = oop_recorder()->find_index(k);
6466 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6467 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6468 }
6469
6470 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6471 assert (UseCompressedOops, "should only be used for compressed headers");
6472 assert (Universe::heap() != nullptr, "java heap should be initialized");
6473 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6474 int oop_index = oop_recorder()->find_index(obj);
6475 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6476 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6477 }
6478
6479 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6480 assert (UseCompressedOops, "should only be used for compressed headers");
6481 assert (Universe::heap() != nullptr, "java heap should be initialized");
6482 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6483 int oop_index = oop_recorder()->find_index(obj);
6484 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6485 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6486 }
6487
6488 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6489 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6490 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6491 int klass_index = oop_recorder()->find_index(k);
6492 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6493 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6494 }
6495
6496 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6497 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6498 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6499 int klass_index = oop_recorder()->find_index(k);
6500 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6501 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6502 }
6503
6504 void MacroAssembler::reinit_heapbase() {
6505 if (UseCompressedOops) {
6506 if (Universe::heap() != nullptr) {
6507 if (CompressedOops::base() == nullptr) {
6508 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6509 } else {
6510 mov64(r12_heapbase, (int64_t)CompressedOops::base());
6511 }
6512 } else {
6513 movptr(r12_heapbase, ExternalAddress(CompressedOops::base_addr()));
6514 }
6515 }
6516 }
6517
6518 #endif // _LP64
6519
6520 #if COMPILER2_OR_JVMCI
6521
6522 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6523 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6524 // cnt - number of qwords (8-byte words).
6525 // base - start address, qword aligned.
6526 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6527 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6528 if (use64byteVector) {
6529 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6530 } else if (MaxVectorSize >= 32) {
6531 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6532 } else {
6533 pxor(xtmp, xtmp);
6534 }
6535 jmp(L_zero_64_bytes);
6536
6537 BIND(L_loop);
6538 if (MaxVectorSize >= 32) {
6539 fill64(base, 0, xtmp, use64byteVector);
6540 } else {
6541 movdqu(Address(base, 0), xtmp);
6542 movdqu(Address(base, 16), xtmp);
6543 movdqu(Address(base, 32), xtmp);
6544 movdqu(Address(base, 48), xtmp);
6545 }
6546 addptr(base, 64);
6547
6548 BIND(L_zero_64_bytes);
6549 subptr(cnt, 8);
6550 jccb(Assembler::greaterEqual, L_loop);
6551
6552 // Copy trailing 64 bytes
6553 if (use64byteVector) {
6554 addptr(cnt, 8);
6555 jccb(Assembler::equal, L_end);
6556 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6557 jmp(L_end);
6558 } else {
6559 addptr(cnt, 4);
6560 jccb(Assembler::less, L_tail);
6561 if (MaxVectorSize >= 32) {
6562 vmovdqu(Address(base, 0), xtmp);
6563 } else {
6564 movdqu(Address(base, 0), xtmp);
6565 movdqu(Address(base, 16), xtmp);
6566 }
6567 }
6568 addptr(base, 32);
6569 subptr(cnt, 4);
6570
6571 BIND(L_tail);
6572 addptr(cnt, 4);
6573 jccb(Assembler::lessEqual, L_end);
6574 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6575 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6576 } else {
6577 decrement(cnt);
6578
6579 BIND(L_sloop);
6580 movq(Address(base, 0), xtmp);
6581 addptr(base, 8);
6582 decrement(cnt);
6583 jccb(Assembler::greaterEqual, L_sloop);
6584 }
6585 BIND(L_end);
6586 }
6587
6588 // Clearing constant sized memory using YMM/ZMM registers.
6589 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6590 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6591 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6592
6593 int vector64_count = (cnt & (~0x7)) >> 3;
6594 cnt = cnt & 0x7;
6595 const int fill64_per_loop = 4;
6596 const int max_unrolled_fill64 = 8;
6597
6598 // 64 byte initialization loop.
6599 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6600 int start64 = 0;
6601 if (vector64_count > max_unrolled_fill64) {
6602 Label LOOP;
6603 Register index = rtmp;
6604
6605 start64 = vector64_count - (vector64_count % fill64_per_loop);
6606
6607 movl(index, 0);
6608 BIND(LOOP);
6609 for (int i = 0; i < fill64_per_loop; i++) {
6610 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6611 }
6612 addl(index, fill64_per_loop * 64);
6613 cmpl(index, start64 * 64);
6614 jccb(Assembler::less, LOOP);
6615 }
6616 for (int i = start64; i < vector64_count; i++) {
6617 fill64(base, i * 64, xtmp, use64byteVector);
6618 }
6619
6620 // Clear remaining 64 byte tail.
6621 int disp = vector64_count * 64;
6622 if (cnt) {
6623 switch (cnt) {
6624 case 1:
6625 movq(Address(base, disp), xtmp);
6626 break;
6627 case 2:
6628 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6629 break;
6630 case 3:
6631 movl(rtmp, 0x7);
6632 kmovwl(mask, rtmp);
6633 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6634 break;
6635 case 4:
6636 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6637 break;
6638 case 5:
6639 if (use64byteVector) {
6640 movl(rtmp, 0x1F);
6641 kmovwl(mask, rtmp);
6642 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6643 } else {
6644 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6645 movq(Address(base, disp + 32), xtmp);
6646 }
6647 break;
6648 case 6:
6649 if (use64byteVector) {
6650 movl(rtmp, 0x3F);
6651 kmovwl(mask, rtmp);
6652 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6653 } else {
6654 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6655 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6656 }
6657 break;
6658 case 7:
6659 if (use64byteVector) {
6660 movl(rtmp, 0x7F);
6661 kmovwl(mask, rtmp);
6662 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6663 } else {
6664 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6665 movl(rtmp, 0x7);
6666 kmovwl(mask, rtmp);
6667 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6668 }
6669 break;
6670 default:
6671 fatal("Unexpected length : %d\n",cnt);
6672 break;
6673 }
6674 }
6675 }
6676
6677 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6678 bool is_large, KRegister mask) {
6679 // cnt - number of qwords (8-byte words).
6680 // base - start address, qword aligned.
6681 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6682 assert(base==rdi, "base register must be edi for rep stos");
6683 assert(tmp==rax, "tmp register must be eax for rep stos");
6684 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6685 assert(InitArrayShortSize % BytesPerLong == 0,
6686 "InitArrayShortSize should be the multiple of BytesPerLong");
6687
6688 Label DONE;
6689 if (!is_large || !UseXMMForObjInit) {
6690 xorptr(tmp, tmp);
6691 }
6692
6693 if (!is_large) {
6694 Label LOOP, LONG;
6695 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6696 jccb(Assembler::greater, LONG);
6697
6698 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6699
6700 decrement(cnt);
6701 jccb(Assembler::negative, DONE); // Zero length
6702
6703 // Use individual pointer-sized stores for small counts:
6704 BIND(LOOP);
6705 movptr(Address(base, cnt, Address::times_ptr), tmp);
6706 decrement(cnt);
6707 jccb(Assembler::greaterEqual, LOOP);
6708 jmpb(DONE);
6709
6710 BIND(LONG);
6711 }
6712
6713 // Use longer rep-prefixed ops for non-small counts:
6714 if (UseFastStosb) {
6715 shlptr(cnt, 3); // convert to number of bytes
6716 rep_stosb();
6717 } else if (UseXMMForObjInit) {
6718 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6719 } else {
6720 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6721 rep_stos();
6722 }
6723
6724 BIND(DONE);
6725 }
6726
6727 #endif //COMPILER2_OR_JVMCI
6728
6729
6730 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6731 Register to, Register value, Register count,
6732 Register rtmp, XMMRegister xtmp) {
6733 ShortBranchVerifier sbv(this);
6734 assert_different_registers(to, value, count, rtmp);
6735 Label L_exit;
6736 Label L_fill_2_bytes, L_fill_4_bytes;
6737
6738 #if defined(COMPILER2) && defined(_LP64)
6739 if(MaxVectorSize >=32 &&
6740 VM_Version::supports_avx512vlbw() &&
6741 VM_Version::supports_bmi2()) {
6742 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6743 return;
6744 }
6745 #endif
6746
6747 int shift = -1;
6748 switch (t) {
6749 case T_BYTE:
6750 shift = 2;
6751 break;
6752 case T_SHORT:
6753 shift = 1;
6754 break;
6755 case T_INT:
6756 shift = 0;
6757 break;
6758 default: ShouldNotReachHere();
6759 }
6760
6761 if (t == T_BYTE) {
6762 andl(value, 0xff);
6763 movl(rtmp, value);
6764 shll(rtmp, 8);
6765 orl(value, rtmp);
6766 }
6767 if (t == T_SHORT) {
6768 andl(value, 0xffff);
6769 }
6770 if (t == T_BYTE || t == T_SHORT) {
6771 movl(rtmp, value);
6772 shll(rtmp, 16);
6773 orl(value, rtmp);
6774 }
6775
6776 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6777 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6778 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6779 Label L_skip_align2;
6780 // align source address at 4 bytes address boundary
6781 if (t == T_BYTE) {
6782 Label L_skip_align1;
6783 // One byte misalignment happens only for byte arrays
6784 testptr(to, 1);
6785 jccb(Assembler::zero, L_skip_align1);
6786 movb(Address(to, 0), value);
6787 increment(to);
6788 decrement(count);
6789 BIND(L_skip_align1);
6790 }
6791 // Two bytes misalignment happens only for byte and short (char) arrays
6792 testptr(to, 2);
6793 jccb(Assembler::zero, L_skip_align2);
6794 movw(Address(to, 0), value);
6795 addptr(to, 2);
6796 subptr(count, 1<<(shift-1));
6797 BIND(L_skip_align2);
6798 }
6799 if (UseSSE < 2) {
6800 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6801 // Fill 32-byte chunks
6802 subptr(count, 8 << shift);
6803 jcc(Assembler::less, L_check_fill_8_bytes);
6804 align(16);
6805
6806 BIND(L_fill_32_bytes_loop);
6807
6808 for (int i = 0; i < 32; i += 4) {
6809 movl(Address(to, i), value);
6810 }
6811
6812 addptr(to, 32);
6813 subptr(count, 8 << shift);
6814 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6815 BIND(L_check_fill_8_bytes);
6816 addptr(count, 8 << shift);
6817 jccb(Assembler::zero, L_exit);
6818 jmpb(L_fill_8_bytes);
6819
6820 //
6821 // length is too short, just fill qwords
6822 //
6823 BIND(L_fill_8_bytes_loop);
6824 movl(Address(to, 0), value);
6825 movl(Address(to, 4), value);
6826 addptr(to, 8);
6827 BIND(L_fill_8_bytes);
6828 subptr(count, 1 << (shift + 1));
6829 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6830 // fall through to fill 4 bytes
6831 } else {
6832 Label L_fill_32_bytes;
6833 if (!UseUnalignedLoadStores) {
6834 // align to 8 bytes, we know we are 4 byte aligned to start
6835 testptr(to, 4);
6836 jccb(Assembler::zero, L_fill_32_bytes);
6837 movl(Address(to, 0), value);
6838 addptr(to, 4);
6839 subptr(count, 1<<shift);
6840 }
6841 BIND(L_fill_32_bytes);
6842 {
6843 assert( UseSSE >= 2, "supported cpu only" );
6844 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6845 movdl(xtmp, value);
6846 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6847 Label L_check_fill_32_bytes;
6848 if (UseAVX > 2) {
6849 // Fill 64-byte chunks
6850 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6851
6852 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6853 cmpptr(count, VM_Version::avx3_threshold());
6854 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6855
6856 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6857
6858 subptr(count, 16 << shift);
6859 jccb(Assembler::less, L_check_fill_32_bytes);
6860 align(16);
6861
6862 BIND(L_fill_64_bytes_loop_avx3);
6863 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6864 addptr(to, 64);
6865 subptr(count, 16 << shift);
6866 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6867 jmpb(L_check_fill_32_bytes);
6868
6869 BIND(L_check_fill_64_bytes_avx2);
6870 }
6871 // Fill 64-byte chunks
6872 Label L_fill_64_bytes_loop;
6873 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6874
6875 subptr(count, 16 << shift);
6876 jcc(Assembler::less, L_check_fill_32_bytes);
6877 align(16);
6878
6879 BIND(L_fill_64_bytes_loop);
6880 vmovdqu(Address(to, 0), xtmp);
6881 vmovdqu(Address(to, 32), xtmp);
6882 addptr(to, 64);
6883 subptr(count, 16 << shift);
6884 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6885
6886 BIND(L_check_fill_32_bytes);
6887 addptr(count, 8 << shift);
6888 jccb(Assembler::less, L_check_fill_8_bytes);
6889 vmovdqu(Address(to, 0), xtmp);
6890 addptr(to, 32);
6891 subptr(count, 8 << shift);
6892
6893 BIND(L_check_fill_8_bytes);
6894 // clean upper bits of YMM registers
6895 movdl(xtmp, value);
6896 pshufd(xtmp, xtmp, 0);
6897 } else {
6898 // Fill 32-byte chunks
6899 pshufd(xtmp, xtmp, 0);
6900
6901 subptr(count, 8 << shift);
6902 jcc(Assembler::less, L_check_fill_8_bytes);
6903 align(16);
6904
6905 BIND(L_fill_32_bytes_loop);
6906
6907 if (UseUnalignedLoadStores) {
6908 movdqu(Address(to, 0), xtmp);
6909 movdqu(Address(to, 16), xtmp);
6910 } else {
6911 movq(Address(to, 0), xtmp);
6912 movq(Address(to, 8), xtmp);
6913 movq(Address(to, 16), xtmp);
6914 movq(Address(to, 24), xtmp);
6915 }
6916
6917 addptr(to, 32);
6918 subptr(count, 8 << shift);
6919 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6920
6921 BIND(L_check_fill_8_bytes);
6922 }
6923 addptr(count, 8 << shift);
6924 jccb(Assembler::zero, L_exit);
6925 jmpb(L_fill_8_bytes);
6926
6927 //
6928 // length is too short, just fill qwords
6929 //
6930 BIND(L_fill_8_bytes_loop);
6931 movq(Address(to, 0), xtmp);
6932 addptr(to, 8);
6933 BIND(L_fill_8_bytes);
6934 subptr(count, 1 << (shift + 1));
6935 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6936 }
6937 }
6938 // fill trailing 4 bytes
6939 BIND(L_fill_4_bytes);
6940 testl(count, 1<<shift);
6941 jccb(Assembler::zero, L_fill_2_bytes);
6942 movl(Address(to, 0), value);
6943 if (t == T_BYTE || t == T_SHORT) {
6944 Label L_fill_byte;
6945 addptr(to, 4);
6946 BIND(L_fill_2_bytes);
6947 // fill trailing 2 bytes
6948 testl(count, 1<<(shift-1));
6949 jccb(Assembler::zero, L_fill_byte);
6950 movw(Address(to, 0), value);
6951 if (t == T_BYTE) {
6952 addptr(to, 2);
6953 BIND(L_fill_byte);
6954 // fill trailing byte
6955 testl(count, 1);
6956 jccb(Assembler::zero, L_exit);
6957 movb(Address(to, 0), value);
6958 } else {
6959 BIND(L_fill_byte);
6960 }
6961 } else {
6962 BIND(L_fill_2_bytes);
6963 }
6964 BIND(L_exit);
6965 }
6966
6967 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6968 switch(type) {
6969 case T_BYTE:
6970 case T_BOOLEAN:
6971 evpbroadcastb(dst, src, vector_len);
6972 break;
6973 case T_SHORT:
6974 case T_CHAR:
6975 evpbroadcastw(dst, src, vector_len);
6976 break;
6977 case T_INT:
6978 case T_FLOAT:
6979 evpbroadcastd(dst, src, vector_len);
6980 break;
6981 case T_LONG:
6982 case T_DOUBLE:
6983 evpbroadcastq(dst, src, vector_len);
6984 break;
6985 default:
6986 fatal("Unhandled type : %s", type2name(type));
6987 break;
6988 }
6989 }
6990
6991 // encode char[] to byte[] in ISO_8859_1 or ASCII
6992 //@IntrinsicCandidate
6993 //private static int implEncodeISOArray(byte[] sa, int sp,
6994 //byte[] da, int dp, int len) {
6995 // int i = 0;
6996 // for (; i < len; i++) {
6997 // char c = StringUTF16.getChar(sa, sp++);
6998 // if (c > '\u00FF')
6999 // break;
7000 // da[dp++] = (byte)c;
7001 // }
7002 // return i;
7003 //}
7004 //
7005 //@IntrinsicCandidate
7006 //private static int implEncodeAsciiArray(char[] sa, int sp,
7007 // byte[] da, int dp, int len) {
7008 // int i = 0;
7009 // for (; i < len; i++) {
7010 // char c = sa[sp++];
7011 // if (c >= '\u0080')
7012 // break;
7013 // da[dp++] = (byte)c;
7014 // }
7015 // return i;
7016 //}
7017 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
7018 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7019 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7020 Register tmp5, Register result, bool ascii) {
7021
7022 // rsi: src
7023 // rdi: dst
7024 // rdx: len
7025 // rcx: tmp5
7026 // rax: result
7027 ShortBranchVerifier sbv(this);
7028 assert_different_registers(src, dst, len, tmp5, result);
7029 Label L_done, L_copy_1_char, L_copy_1_char_exit;
7030
7031 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
7032 int short_mask = ascii ? 0xff80 : 0xff00;
7033
7034 // set result
7035 xorl(result, result);
7036 // check for zero length
7037 testl(len, len);
7038 jcc(Assembler::zero, L_done);
7039
7040 movl(result, len);
7041
7042 // Setup pointers
7043 lea(src, Address(src, len, Address::times_2)); // char[]
7044 lea(dst, Address(dst, len, Address::times_1)); // byte[]
7045 negptr(len);
7046
7047 if (UseSSE42Intrinsics || UseAVX >= 2) {
7048 Label L_copy_8_chars, L_copy_8_chars_exit;
7049 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
7050
7051 if (UseAVX >= 2) {
7052 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
7053 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7054 movdl(tmp1Reg, tmp5);
7055 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
7056 jmp(L_chars_32_check);
7057
7058 bind(L_copy_32_chars);
7059 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
7060 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
7061 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7062 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7063 jccb(Assembler::notZero, L_copy_32_chars_exit);
7064 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
7065 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
7066 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
7067
7068 bind(L_chars_32_check);
7069 addptr(len, 32);
7070 jcc(Assembler::lessEqual, L_copy_32_chars);
7071
7072 bind(L_copy_32_chars_exit);
7073 subptr(len, 16);
7074 jccb(Assembler::greater, L_copy_16_chars_exit);
7075
7076 } else if (UseSSE42Intrinsics) {
7077 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
7078 movdl(tmp1Reg, tmp5);
7079 pshufd(tmp1Reg, tmp1Reg, 0);
7080 jmpb(L_chars_16_check);
7081 }
7082
7083 bind(L_copy_16_chars);
7084 if (UseAVX >= 2) {
7085 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
7086 vptest(tmp2Reg, tmp1Reg);
7087 jcc(Assembler::notZero, L_copy_16_chars_exit);
7088 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
7089 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
7090 } else {
7091 if (UseAVX > 0) {
7092 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7093 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7094 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
7095 } else {
7096 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
7097 por(tmp2Reg, tmp3Reg);
7098 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
7099 por(tmp2Reg, tmp4Reg);
7100 }
7101 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
7102 jccb(Assembler::notZero, L_copy_16_chars_exit);
7103 packuswb(tmp3Reg, tmp4Reg);
7104 }
7105 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
7106
7107 bind(L_chars_16_check);
7108 addptr(len, 16);
7109 jcc(Assembler::lessEqual, L_copy_16_chars);
7110
7111 bind(L_copy_16_chars_exit);
7112 if (UseAVX >= 2) {
7113 // clean upper bits of YMM registers
7114 vpxor(tmp2Reg, tmp2Reg);
7115 vpxor(tmp3Reg, tmp3Reg);
7116 vpxor(tmp4Reg, tmp4Reg);
7117 movdl(tmp1Reg, tmp5);
7118 pshufd(tmp1Reg, tmp1Reg, 0);
7119 }
7120 subptr(len, 8);
7121 jccb(Assembler::greater, L_copy_8_chars_exit);
7122
7123 bind(L_copy_8_chars);
7124 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
7125 ptest(tmp3Reg, tmp1Reg);
7126 jccb(Assembler::notZero, L_copy_8_chars_exit);
7127 packuswb(tmp3Reg, tmp1Reg);
7128 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
7129 addptr(len, 8);
7130 jccb(Assembler::lessEqual, L_copy_8_chars);
7131
7132 bind(L_copy_8_chars_exit);
7133 subptr(len, 8);
7134 jccb(Assembler::zero, L_done);
7135 }
7136
7137 bind(L_copy_1_char);
7138 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
7139 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
7140 jccb(Assembler::notZero, L_copy_1_char_exit);
7141 movb(Address(dst, len, Address::times_1, 0), tmp5);
7142 addptr(len, 1);
7143 jccb(Assembler::less, L_copy_1_char);
7144
7145 bind(L_copy_1_char_exit);
7146 addptr(result, len); // len is negative count of not processed elements
7147
7148 bind(L_done);
7149 }
7150
7151 #ifdef _LP64
7152 /**
7153 * Helper for multiply_to_len().
7154 */
7155 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
7156 addq(dest_lo, src1);
7157 adcq(dest_hi, 0);
7158 addq(dest_lo, src2);
7159 adcq(dest_hi, 0);
7160 }
7161
7162 /**
7163 * Multiply 64 bit by 64 bit first loop.
7164 */
7165 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
7166 Register y, Register y_idx, Register z,
7167 Register carry, Register product,
7168 Register idx, Register kdx) {
7169 //
7170 // jlong carry, x[], y[], z[];
7171 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7172 // huge_128 product = y[idx] * x[xstart] + carry;
7173 // z[kdx] = (jlong)product;
7174 // carry = (jlong)(product >>> 64);
7175 // }
7176 // z[xstart] = carry;
7177 //
7178
7179 Label L_first_loop, L_first_loop_exit;
7180 Label L_one_x, L_one_y, L_multiply;
7181
7182 decrementl(xstart);
7183 jcc(Assembler::negative, L_one_x);
7184
7185 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7186 rorq(x_xstart, 32); // convert big-endian to little-endian
7187
7188 bind(L_first_loop);
7189 decrementl(idx);
7190 jcc(Assembler::negative, L_first_loop_exit);
7191 decrementl(idx);
7192 jcc(Assembler::negative, L_one_y);
7193 movq(y_idx, Address(y, idx, Address::times_4, 0));
7194 rorq(y_idx, 32); // convert big-endian to little-endian
7195 bind(L_multiply);
7196 movq(product, x_xstart);
7197 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
7198 addq(product, carry);
7199 adcq(rdx, 0);
7200 subl(kdx, 2);
7201 movl(Address(z, kdx, Address::times_4, 4), product);
7202 shrq(product, 32);
7203 movl(Address(z, kdx, Address::times_4, 0), product);
7204 movq(carry, rdx);
7205 jmp(L_first_loop);
7206
7207 bind(L_one_y);
7208 movl(y_idx, Address(y, 0));
7209 jmp(L_multiply);
7210
7211 bind(L_one_x);
7212 movl(x_xstart, Address(x, 0));
7213 jmp(L_first_loop);
7214
7215 bind(L_first_loop_exit);
7216 }
7217
7218 /**
7219 * Multiply 64 bit by 64 bit and add 128 bit.
7220 */
7221 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
7222 Register yz_idx, Register idx,
7223 Register carry, Register product, int offset) {
7224 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
7225 // z[kdx] = (jlong)product;
7226
7227 movq(yz_idx, Address(y, idx, Address::times_4, offset));
7228 rorq(yz_idx, 32); // convert big-endian to little-endian
7229 movq(product, x_xstart);
7230 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7231 movq(yz_idx, Address(z, idx, Address::times_4, offset));
7232 rorq(yz_idx, 32); // convert big-endian to little-endian
7233
7234 add2_with_carry(rdx, product, carry, yz_idx);
7235
7236 movl(Address(z, idx, Address::times_4, offset+4), product);
7237 shrq(product, 32);
7238 movl(Address(z, idx, Address::times_4, offset), product);
7239
7240 }
7241
7242 /**
7243 * Multiply 128 bit by 128 bit. Unrolled inner loop.
7244 */
7245 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
7246 Register yz_idx, Register idx, Register jdx,
7247 Register carry, Register product,
7248 Register carry2) {
7249 // jlong carry, x[], y[], z[];
7250 // int kdx = ystart+1;
7251 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7252 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
7253 // z[kdx+idx+1] = (jlong)product;
7254 // jlong carry2 = (jlong)(product >>> 64);
7255 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
7256 // z[kdx+idx] = (jlong)product;
7257 // carry = (jlong)(product >>> 64);
7258 // }
7259 // idx += 2;
7260 // if (idx > 0) {
7261 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
7262 // z[kdx+idx] = (jlong)product;
7263 // carry = (jlong)(product >>> 64);
7264 // }
7265 //
7266
7267 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7268
7269 movl(jdx, idx);
7270 andl(jdx, 0xFFFFFFFC);
7271 shrl(jdx, 2);
7272
7273 bind(L_third_loop);
7274 subl(jdx, 1);
7275 jcc(Assembler::negative, L_third_loop_exit);
7276 subl(idx, 4);
7277
7278 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
7279 movq(carry2, rdx);
7280
7281 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
7282 movq(carry, rdx);
7283 jmp(L_third_loop);
7284
7285 bind (L_third_loop_exit);
7286
7287 andl (idx, 0x3);
7288 jcc(Assembler::zero, L_post_third_loop_done);
7289
7290 Label L_check_1;
7291 subl(idx, 2);
7292 jcc(Assembler::negative, L_check_1);
7293
7294 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
7295 movq(carry, rdx);
7296
7297 bind (L_check_1);
7298 addl (idx, 0x2);
7299 andl (idx, 0x1);
7300 subl(idx, 1);
7301 jcc(Assembler::negative, L_post_third_loop_done);
7302
7303 movl(yz_idx, Address(y, idx, Address::times_4, 0));
7304 movq(product, x_xstart);
7305 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
7306 movl(yz_idx, Address(z, idx, Address::times_4, 0));
7307
7308 add2_with_carry(rdx, product, yz_idx, carry);
7309
7310 movl(Address(z, idx, Address::times_4, 0), product);
7311 shrq(product, 32);
7312
7313 shlq(rdx, 32);
7314 orq(product, rdx);
7315 movq(carry, product);
7316
7317 bind(L_post_third_loop_done);
7318 }
7319
7320 /**
7321 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
7322 *
7323 */
7324 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
7325 Register carry, Register carry2,
7326 Register idx, Register jdx,
7327 Register yz_idx1, Register yz_idx2,
7328 Register tmp, Register tmp3, Register tmp4) {
7329 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
7330
7331 // jlong carry, x[], y[], z[];
7332 // int kdx = ystart+1;
7333 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
7334 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
7335 // jlong carry2 = (jlong)(tmp3 >>> 64);
7336 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
7337 // carry = (jlong)(tmp4 >>> 64);
7338 // z[kdx+idx+1] = (jlong)tmp3;
7339 // z[kdx+idx] = (jlong)tmp4;
7340 // }
7341 // idx += 2;
7342 // if (idx > 0) {
7343 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
7344 // z[kdx+idx] = (jlong)yz_idx1;
7345 // carry = (jlong)(yz_idx1 >>> 64);
7346 // }
7347 //
7348
7349 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
7350
7351 movl(jdx, idx);
7352 andl(jdx, 0xFFFFFFFC);
7353 shrl(jdx, 2);
7354
7355 bind(L_third_loop);
7356 subl(jdx, 1);
7357 jcc(Assembler::negative, L_third_loop_exit);
7358 subl(idx, 4);
7359
7360 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
7361 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
7362 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
7363 rorxq(yz_idx2, yz_idx2, 32);
7364
7365 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7366 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
7367
7368 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
7369 rorxq(yz_idx1, yz_idx1, 32);
7370 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7371 rorxq(yz_idx2, yz_idx2, 32);
7372
7373 if (VM_Version::supports_adx()) {
7374 adcxq(tmp3, carry);
7375 adoxq(tmp3, yz_idx1);
7376
7377 adcxq(tmp4, tmp);
7378 adoxq(tmp4, yz_idx2);
7379
7380 movl(carry, 0); // does not affect flags
7381 adcxq(carry2, carry);
7382 adoxq(carry2, carry);
7383 } else {
7384 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
7385 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
7386 }
7387 movq(carry, carry2);
7388
7389 movl(Address(z, idx, Address::times_4, 12), tmp3);
7390 shrq(tmp3, 32);
7391 movl(Address(z, idx, Address::times_4, 8), tmp3);
7392
7393 movl(Address(z, idx, Address::times_4, 4), tmp4);
7394 shrq(tmp4, 32);
7395 movl(Address(z, idx, Address::times_4, 0), tmp4);
7396
7397 jmp(L_third_loop);
7398
7399 bind (L_third_loop_exit);
7400
7401 andl (idx, 0x3);
7402 jcc(Assembler::zero, L_post_third_loop_done);
7403
7404 Label L_check_1;
7405 subl(idx, 2);
7406 jcc(Assembler::negative, L_check_1);
7407
7408 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7409 rorxq(yz_idx1, yz_idx1, 32);
7410 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7411 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7412 rorxq(yz_idx2, yz_idx2, 32);
7413
7414 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7415
7416 movl(Address(z, idx, Address::times_4, 4), tmp3);
7417 shrq(tmp3, 32);
7418 movl(Address(z, idx, Address::times_4, 0), tmp3);
7419 movq(carry, tmp4);
7420
7421 bind (L_check_1);
7422 addl (idx, 0x2);
7423 andl (idx, 0x1);
7424 subl(idx, 1);
7425 jcc(Assembler::negative, L_post_third_loop_done);
7426 movl(tmp4, Address(y, idx, Address::times_4, 0));
7427 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7428 movl(tmp4, Address(z, idx, Address::times_4, 0));
7429
7430 add2_with_carry(carry2, tmp3, tmp4, carry);
7431
7432 movl(Address(z, idx, Address::times_4, 0), tmp3);
7433 shrq(tmp3, 32);
7434
7435 shlq(carry2, 32);
7436 orq(tmp3, carry2);
7437 movq(carry, tmp3);
7438
7439 bind(L_post_third_loop_done);
7440 }
7441
7442 /**
7443 * Code for BigInteger::multiplyToLen() intrinsic.
7444 *
7445 * rdi: x
7446 * rax: xlen
7447 * rsi: y
7448 * rcx: ylen
7449 * r8: z
7450 * r11: tmp0
7451 * r12: tmp1
7452 * r13: tmp2
7453 * r14: tmp3
7454 * r15: tmp4
7455 * rbx: tmp5
7456 *
7457 */
7458 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7459 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7460 ShortBranchVerifier sbv(this);
7461 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7462
7463 push(tmp0);
7464 push(tmp1);
7465 push(tmp2);
7466 push(tmp3);
7467 push(tmp4);
7468 push(tmp5);
7469
7470 push(xlen);
7471
7472 const Register idx = tmp1;
7473 const Register kdx = tmp2;
7474 const Register xstart = tmp3;
7475
7476 const Register y_idx = tmp4;
7477 const Register carry = tmp5;
7478 const Register product = xlen;
7479 const Register x_xstart = tmp0;
7480
7481 // First Loop.
7482 //
7483 // final static long LONG_MASK = 0xffffffffL;
7484 // int xstart = xlen - 1;
7485 // int ystart = ylen - 1;
7486 // long carry = 0;
7487 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7488 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7489 // z[kdx] = (int)product;
7490 // carry = product >>> 32;
7491 // }
7492 // z[xstart] = (int)carry;
7493 //
7494
7495 movl(idx, ylen); // idx = ylen;
7496 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7497 xorq(carry, carry); // carry = 0;
7498
7499 Label L_done;
7500
7501 movl(xstart, xlen);
7502 decrementl(xstart);
7503 jcc(Assembler::negative, L_done);
7504
7505 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7506
7507 Label L_second_loop;
7508 testl(kdx, kdx);
7509 jcc(Assembler::zero, L_second_loop);
7510
7511 Label L_carry;
7512 subl(kdx, 1);
7513 jcc(Assembler::zero, L_carry);
7514
7515 movl(Address(z, kdx, Address::times_4, 0), carry);
7516 shrq(carry, 32);
7517 subl(kdx, 1);
7518
7519 bind(L_carry);
7520 movl(Address(z, kdx, Address::times_4, 0), carry);
7521
7522 // Second and third (nested) loops.
7523 //
7524 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7525 // carry = 0;
7526 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7527 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7528 // (z[k] & LONG_MASK) + carry;
7529 // z[k] = (int)product;
7530 // carry = product >>> 32;
7531 // }
7532 // z[i] = (int)carry;
7533 // }
7534 //
7535 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7536
7537 const Register jdx = tmp1;
7538
7539 bind(L_second_loop);
7540 xorl(carry, carry); // carry = 0;
7541 movl(jdx, ylen); // j = ystart+1
7542
7543 subl(xstart, 1); // i = xstart-1;
7544 jcc(Assembler::negative, L_done);
7545
7546 push (z);
7547
7548 Label L_last_x;
7549 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7550 subl(xstart, 1); // i = xstart-1;
7551 jcc(Assembler::negative, L_last_x);
7552
7553 if (UseBMI2Instructions) {
7554 movq(rdx, Address(x, xstart, Address::times_4, 0));
7555 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7556 } else {
7557 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7558 rorq(x_xstart, 32); // convert big-endian to little-endian
7559 }
7560
7561 Label L_third_loop_prologue;
7562 bind(L_third_loop_prologue);
7563
7564 push (x);
7565 push (xstart);
7566 push (ylen);
7567
7568
7569 if (UseBMI2Instructions) {
7570 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7571 } else { // !UseBMI2Instructions
7572 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7573 }
7574
7575 pop(ylen);
7576 pop(xlen);
7577 pop(x);
7578 pop(z);
7579
7580 movl(tmp3, xlen);
7581 addl(tmp3, 1);
7582 movl(Address(z, tmp3, Address::times_4, 0), carry);
7583 subl(tmp3, 1);
7584 jccb(Assembler::negative, L_done);
7585
7586 shrq(carry, 32);
7587 movl(Address(z, tmp3, Address::times_4, 0), carry);
7588 jmp(L_second_loop);
7589
7590 // Next infrequent code is moved outside loops.
7591 bind(L_last_x);
7592 if (UseBMI2Instructions) {
7593 movl(rdx, Address(x, 0));
7594 } else {
7595 movl(x_xstart, Address(x, 0));
7596 }
7597 jmp(L_third_loop_prologue);
7598
7599 bind(L_done);
7600
7601 pop(xlen);
7602
7603 pop(tmp5);
7604 pop(tmp4);
7605 pop(tmp3);
7606 pop(tmp2);
7607 pop(tmp1);
7608 pop(tmp0);
7609 }
7610
7611 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7612 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7613 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7614 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7615 Label VECTOR8_TAIL, VECTOR4_TAIL;
7616 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7617 Label SAME_TILL_END, DONE;
7618 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7619
7620 //scale is in rcx in both Win64 and Unix
7621 ShortBranchVerifier sbv(this);
7622
7623 shlq(length);
7624 xorq(result, result);
7625
7626 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7627 VM_Version::supports_avx512vlbw()) {
7628 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7629
7630 cmpq(length, 64);
7631 jcc(Assembler::less, VECTOR32_TAIL);
7632
7633 movq(tmp1, length);
7634 andq(tmp1, 0x3F); // tail count
7635 andq(length, ~(0x3F)); //vector count
7636
7637 bind(VECTOR64_LOOP);
7638 // AVX512 code to compare 64 byte vectors.
7639 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7640 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7641 kortestql(k7, k7);
7642 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7643 addq(result, 64);
7644 subq(length, 64);
7645 jccb(Assembler::notZero, VECTOR64_LOOP);
7646
7647 //bind(VECTOR64_TAIL);
7648 testq(tmp1, tmp1);
7649 jcc(Assembler::zero, SAME_TILL_END);
7650
7651 //bind(VECTOR64_TAIL);
7652 // AVX512 code to compare up to 63 byte vectors.
7653 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7654 shlxq(tmp2, tmp2, tmp1);
7655 notq(tmp2);
7656 kmovql(k3, tmp2);
7657
7658 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7659 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7660
7661 ktestql(k7, k3);
7662 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7663
7664 bind(VECTOR64_NOT_EQUAL);
7665 kmovql(tmp1, k7);
7666 notq(tmp1);
7667 tzcntq(tmp1, tmp1);
7668 addq(result, tmp1);
7669 shrq(result);
7670 jmp(DONE);
7671 bind(VECTOR32_TAIL);
7672 }
7673
7674 cmpq(length, 8);
7675 jcc(Assembler::equal, VECTOR8_LOOP);
7676 jcc(Assembler::less, VECTOR4_TAIL);
7677
7678 if (UseAVX >= 2) {
7679 Label VECTOR16_TAIL, VECTOR32_LOOP;
7680
7681 cmpq(length, 16);
7682 jcc(Assembler::equal, VECTOR16_LOOP);
7683 jcc(Assembler::less, VECTOR8_LOOP);
7684
7685 cmpq(length, 32);
7686 jccb(Assembler::less, VECTOR16_TAIL);
7687
7688 subq(length, 32);
7689 bind(VECTOR32_LOOP);
7690 vmovdqu(rymm0, Address(obja, result));
7691 vmovdqu(rymm1, Address(objb, result));
7692 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7693 vptest(rymm2, rymm2);
7694 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7695 addq(result, 32);
7696 subq(length, 32);
7697 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7698 addq(length, 32);
7699 jcc(Assembler::equal, SAME_TILL_END);
7700 //falling through if less than 32 bytes left //close the branch here.
7701
7702 bind(VECTOR16_TAIL);
7703 cmpq(length, 16);
7704 jccb(Assembler::less, VECTOR8_TAIL);
7705 bind(VECTOR16_LOOP);
7706 movdqu(rymm0, Address(obja, result));
7707 movdqu(rymm1, Address(objb, result));
7708 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7709 ptest(rymm2, rymm2);
7710 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7711 addq(result, 16);
7712 subq(length, 16);
7713 jcc(Assembler::equal, SAME_TILL_END);
7714 //falling through if less than 16 bytes left
7715 } else {//regular intrinsics
7716
7717 cmpq(length, 16);
7718 jccb(Assembler::less, VECTOR8_TAIL);
7719
7720 subq(length, 16);
7721 bind(VECTOR16_LOOP);
7722 movdqu(rymm0, Address(obja, result));
7723 movdqu(rymm1, Address(objb, result));
7724 pxor(rymm0, rymm1);
7725 ptest(rymm0, rymm0);
7726 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7727 addq(result, 16);
7728 subq(length, 16);
7729 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7730 addq(length, 16);
7731 jcc(Assembler::equal, SAME_TILL_END);
7732 //falling through if less than 16 bytes left
7733 }
7734
7735 bind(VECTOR8_TAIL);
7736 cmpq(length, 8);
7737 jccb(Assembler::less, VECTOR4_TAIL);
7738 bind(VECTOR8_LOOP);
7739 movq(tmp1, Address(obja, result));
7740 movq(tmp2, Address(objb, result));
7741 xorq(tmp1, tmp2);
7742 testq(tmp1, tmp1);
7743 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7744 addq(result, 8);
7745 subq(length, 8);
7746 jcc(Assembler::equal, SAME_TILL_END);
7747 //falling through if less than 8 bytes left
7748
7749 bind(VECTOR4_TAIL);
7750 cmpq(length, 4);
7751 jccb(Assembler::less, BYTES_TAIL);
7752 bind(VECTOR4_LOOP);
7753 movl(tmp1, Address(obja, result));
7754 xorl(tmp1, Address(objb, result));
7755 testl(tmp1, tmp1);
7756 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7757 addq(result, 4);
7758 subq(length, 4);
7759 jcc(Assembler::equal, SAME_TILL_END);
7760 //falling through if less than 4 bytes left
7761
7762 bind(BYTES_TAIL);
7763 bind(BYTES_LOOP);
7764 load_unsigned_byte(tmp1, Address(obja, result));
7765 load_unsigned_byte(tmp2, Address(objb, result));
7766 xorl(tmp1, tmp2);
7767 testl(tmp1, tmp1);
7768 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7769 decq(length);
7770 jcc(Assembler::zero, SAME_TILL_END);
7771 incq(result);
7772 load_unsigned_byte(tmp1, Address(obja, result));
7773 load_unsigned_byte(tmp2, Address(objb, result));
7774 xorl(tmp1, tmp2);
7775 testl(tmp1, tmp1);
7776 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7777 decq(length);
7778 jcc(Assembler::zero, SAME_TILL_END);
7779 incq(result);
7780 load_unsigned_byte(tmp1, Address(obja, result));
7781 load_unsigned_byte(tmp2, Address(objb, result));
7782 xorl(tmp1, tmp2);
7783 testl(tmp1, tmp1);
7784 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7785 jmp(SAME_TILL_END);
7786
7787 if (UseAVX >= 2) {
7788 bind(VECTOR32_NOT_EQUAL);
7789 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7790 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7791 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7792 vpmovmskb(tmp1, rymm0);
7793 bsfq(tmp1, tmp1);
7794 addq(result, tmp1);
7795 shrq(result);
7796 jmp(DONE);
7797 }
7798
7799 bind(VECTOR16_NOT_EQUAL);
7800 if (UseAVX >= 2) {
7801 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7802 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7803 pxor(rymm0, rymm2);
7804 } else {
7805 pcmpeqb(rymm2, rymm2);
7806 pxor(rymm0, rymm1);
7807 pcmpeqb(rymm0, rymm1);
7808 pxor(rymm0, rymm2);
7809 }
7810 pmovmskb(tmp1, rymm0);
7811 bsfq(tmp1, tmp1);
7812 addq(result, tmp1);
7813 shrq(result);
7814 jmpb(DONE);
7815
7816 bind(VECTOR8_NOT_EQUAL);
7817 bind(VECTOR4_NOT_EQUAL);
7818 bsfq(tmp1, tmp1);
7819 shrq(tmp1, 3);
7820 addq(result, tmp1);
7821 bind(BYTES_NOT_EQUAL);
7822 shrq(result);
7823 jmpb(DONE);
7824
7825 bind(SAME_TILL_END);
7826 mov64(result, -1);
7827
7828 bind(DONE);
7829 }
7830
7831 //Helper functions for square_to_len()
7832
7833 /**
7834 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7835 * Preserves x and z and modifies rest of the registers.
7836 */
7837 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7838 // Perform square and right shift by 1
7839 // Handle odd xlen case first, then for even xlen do the following
7840 // jlong carry = 0;
7841 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7842 // huge_128 product = x[j:j+1] * x[j:j+1];
7843 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7844 // z[i+2:i+3] = (jlong)(product >>> 1);
7845 // carry = (jlong)product;
7846 // }
7847
7848 xorq(tmp5, tmp5); // carry
7849 xorq(rdxReg, rdxReg);
7850 xorl(tmp1, tmp1); // index for x
7851 xorl(tmp4, tmp4); // index for z
7852
7853 Label L_first_loop, L_first_loop_exit;
7854
7855 testl(xlen, 1);
7856 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7857
7858 // Square and right shift by 1 the odd element using 32 bit multiply
7859 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7860 imulq(raxReg, raxReg);
7861 shrq(raxReg, 1);
7862 adcq(tmp5, 0);
7863 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7864 incrementl(tmp1);
7865 addl(tmp4, 2);
7866
7867 // Square and right shift by 1 the rest using 64 bit multiply
7868 bind(L_first_loop);
7869 cmpptr(tmp1, xlen);
7870 jccb(Assembler::equal, L_first_loop_exit);
7871
7872 // Square
7873 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7874 rorq(raxReg, 32); // convert big-endian to little-endian
7875 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7876
7877 // Right shift by 1 and save carry
7878 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7879 rcrq(rdxReg, 1);
7880 rcrq(raxReg, 1);
7881 adcq(tmp5, 0);
7882
7883 // Store result in z
7884 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7885 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7886
7887 // Update indices for x and z
7888 addl(tmp1, 2);
7889 addl(tmp4, 4);
7890 jmp(L_first_loop);
7891
7892 bind(L_first_loop_exit);
7893 }
7894
7895
7896 /**
7897 * Perform the following multiply add operation using BMI2 instructions
7898 * carry:sum = sum + op1*op2 + carry
7899 * op2 should be in rdx
7900 * op2 is preserved, all other registers are modified
7901 */
7902 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7903 // assert op2 is rdx
7904 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7905 addq(sum, carry);
7906 adcq(tmp2, 0);
7907 addq(sum, op1);
7908 adcq(tmp2, 0);
7909 movq(carry, tmp2);
7910 }
7911
7912 /**
7913 * Perform the following multiply add operation:
7914 * carry:sum = sum + op1*op2 + carry
7915 * Preserves op1, op2 and modifies rest of registers
7916 */
7917 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7918 // rdx:rax = op1 * op2
7919 movq(raxReg, op2);
7920 mulq(op1);
7921
7922 // rdx:rax = sum + carry + rdx:rax
7923 addq(sum, carry);
7924 adcq(rdxReg, 0);
7925 addq(sum, raxReg);
7926 adcq(rdxReg, 0);
7927
7928 // carry:sum = rdx:sum
7929 movq(carry, rdxReg);
7930 }
7931
7932 /**
7933 * Add 64 bit long carry into z[] with carry propagation.
7934 * Preserves z and carry register values and modifies rest of registers.
7935 *
7936 */
7937 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7938 Label L_fourth_loop, L_fourth_loop_exit;
7939
7940 movl(tmp1, 1);
7941 subl(zlen, 2);
7942 addq(Address(z, zlen, Address::times_4, 0), carry);
7943
7944 bind(L_fourth_loop);
7945 jccb(Assembler::carryClear, L_fourth_loop_exit);
7946 subl(zlen, 2);
7947 jccb(Assembler::negative, L_fourth_loop_exit);
7948 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7949 jmp(L_fourth_loop);
7950 bind(L_fourth_loop_exit);
7951 }
7952
7953 /**
7954 * Shift z[] left by 1 bit.
7955 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7956 *
7957 */
7958 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7959
7960 Label L_fifth_loop, L_fifth_loop_exit;
7961
7962 // Fifth loop
7963 // Perform primitiveLeftShift(z, zlen, 1)
7964
7965 const Register prev_carry = tmp1;
7966 const Register new_carry = tmp4;
7967 const Register value = tmp2;
7968 const Register zidx = tmp3;
7969
7970 // int zidx, carry;
7971 // long value;
7972 // carry = 0;
7973 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7974 // (carry:value) = (z[i] << 1) | carry ;
7975 // z[i] = value;
7976 // }
7977
7978 movl(zidx, zlen);
7979 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7980
7981 bind(L_fifth_loop);
7982 decl(zidx); // Use decl to preserve carry flag
7983 decl(zidx);
7984 jccb(Assembler::negative, L_fifth_loop_exit);
7985
7986 if (UseBMI2Instructions) {
7987 movq(value, Address(z, zidx, Address::times_4, 0));
7988 rclq(value, 1);
7989 rorxq(value, value, 32);
7990 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7991 }
7992 else {
7993 // clear new_carry
7994 xorl(new_carry, new_carry);
7995
7996 // Shift z[i] by 1, or in previous carry and save new carry
7997 movq(value, Address(z, zidx, Address::times_4, 0));
7998 shlq(value, 1);
7999 adcl(new_carry, 0);
8000
8001 orq(value, prev_carry);
8002 rorq(value, 0x20);
8003 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
8004
8005 // Set previous carry = new carry
8006 movl(prev_carry, new_carry);
8007 }
8008 jmp(L_fifth_loop);
8009
8010 bind(L_fifth_loop_exit);
8011 }
8012
8013
8014 /**
8015 * Code for BigInteger::squareToLen() intrinsic
8016 *
8017 * rdi: x
8018 * rsi: len
8019 * r8: z
8020 * rcx: zlen
8021 * r12: tmp1
8022 * r13: tmp2
8023 * r14: tmp3
8024 * r15: tmp4
8025 * rbx: tmp5
8026 *
8027 */
8028 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8029
8030 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
8031 push(tmp1);
8032 push(tmp2);
8033 push(tmp3);
8034 push(tmp4);
8035 push(tmp5);
8036
8037 // First loop
8038 // Store the squares, right shifted one bit (i.e., divided by 2).
8039 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
8040
8041 // Add in off-diagonal sums.
8042 //
8043 // Second, third (nested) and fourth loops.
8044 // zlen +=2;
8045 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
8046 // carry = 0;
8047 // long op2 = x[xidx:xidx+1];
8048 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
8049 // k -= 2;
8050 // long op1 = x[j:j+1];
8051 // long sum = z[k:k+1];
8052 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
8053 // z[k:k+1] = sum;
8054 // }
8055 // add_one_64(z, k, carry, tmp_regs);
8056 // }
8057
8058 const Register carry = tmp5;
8059 const Register sum = tmp3;
8060 const Register op1 = tmp4;
8061 Register op2 = tmp2;
8062
8063 push(zlen);
8064 push(len);
8065 addl(zlen,2);
8066 bind(L_second_loop);
8067 xorq(carry, carry);
8068 subl(zlen, 4);
8069 subl(len, 2);
8070 push(zlen);
8071 push(len);
8072 cmpl(len, 0);
8073 jccb(Assembler::lessEqual, L_second_loop_exit);
8074
8075 // Multiply an array by one 64 bit long.
8076 if (UseBMI2Instructions) {
8077 op2 = rdxReg;
8078 movq(op2, Address(x, len, Address::times_4, 0));
8079 rorxq(op2, op2, 32);
8080 }
8081 else {
8082 movq(op2, Address(x, len, Address::times_4, 0));
8083 rorq(op2, 32);
8084 }
8085
8086 bind(L_third_loop);
8087 decrementl(len);
8088 jccb(Assembler::negative, L_third_loop_exit);
8089 decrementl(len);
8090 jccb(Assembler::negative, L_last_x);
8091
8092 movq(op1, Address(x, len, Address::times_4, 0));
8093 rorq(op1, 32);
8094
8095 bind(L_multiply);
8096 subl(zlen, 2);
8097 movq(sum, Address(z, zlen, Address::times_4, 0));
8098
8099 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
8100 if (UseBMI2Instructions) {
8101 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
8102 }
8103 else {
8104 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8105 }
8106
8107 movq(Address(z, zlen, Address::times_4, 0), sum);
8108
8109 jmp(L_third_loop);
8110 bind(L_third_loop_exit);
8111
8112 // Fourth loop
8113 // Add 64 bit long carry into z with carry propagation.
8114 // Uses offsetted zlen.
8115 add_one_64(z, zlen, carry, tmp1);
8116
8117 pop(len);
8118 pop(zlen);
8119 jmp(L_second_loop);
8120
8121 // Next infrequent code is moved outside loops.
8122 bind(L_last_x);
8123 movl(op1, Address(x, 0));
8124 jmp(L_multiply);
8125
8126 bind(L_second_loop_exit);
8127 pop(len);
8128 pop(zlen);
8129 pop(len);
8130 pop(zlen);
8131
8132 // Fifth loop
8133 // Shift z left 1 bit.
8134 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
8135
8136 // z[zlen-1] |= x[len-1] & 1;
8137 movl(tmp3, Address(x, len, Address::times_4, -4));
8138 andl(tmp3, 1);
8139 orl(Address(z, zlen, Address::times_4, -4), tmp3);
8140
8141 pop(tmp5);
8142 pop(tmp4);
8143 pop(tmp3);
8144 pop(tmp2);
8145 pop(tmp1);
8146 }
8147
8148 /**
8149 * Helper function for mul_add()
8150 * Multiply the in[] by int k and add to out[] starting at offset offs using
8151 * 128 bit by 32 bit multiply and return the carry in tmp5.
8152 * Only quad int aligned length of in[] is operated on in this function.
8153 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
8154 * This function preserves out, in and k registers.
8155 * len and offset point to the appropriate index in "in" & "out" correspondingly
8156 * tmp5 has the carry.
8157 * other registers are temporary and are modified.
8158 *
8159 */
8160 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
8161 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
8162 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8163
8164 Label L_first_loop, L_first_loop_exit;
8165
8166 movl(tmp1, len);
8167 shrl(tmp1, 2);
8168
8169 bind(L_first_loop);
8170 subl(tmp1, 1);
8171 jccb(Assembler::negative, L_first_loop_exit);
8172
8173 subl(len, 4);
8174 subl(offset, 4);
8175
8176 Register op2 = tmp2;
8177 const Register sum = tmp3;
8178 const Register op1 = tmp4;
8179 const Register carry = tmp5;
8180
8181 if (UseBMI2Instructions) {
8182 op2 = rdxReg;
8183 }
8184
8185 movq(op1, Address(in, len, Address::times_4, 8));
8186 rorq(op1, 32);
8187 movq(sum, Address(out, offset, Address::times_4, 8));
8188 rorq(sum, 32);
8189 if (UseBMI2Instructions) {
8190 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8191 }
8192 else {
8193 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8194 }
8195 // Store back in big endian from little endian
8196 rorq(sum, 0x20);
8197 movq(Address(out, offset, Address::times_4, 8), sum);
8198
8199 movq(op1, Address(in, len, Address::times_4, 0));
8200 rorq(op1, 32);
8201 movq(sum, Address(out, offset, Address::times_4, 0));
8202 rorq(sum, 32);
8203 if (UseBMI2Instructions) {
8204 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8205 }
8206 else {
8207 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8208 }
8209 // Store back in big endian from little endian
8210 rorq(sum, 0x20);
8211 movq(Address(out, offset, Address::times_4, 0), sum);
8212
8213 jmp(L_first_loop);
8214 bind(L_first_loop_exit);
8215 }
8216
8217 /**
8218 * Code for BigInteger::mulAdd() intrinsic
8219 *
8220 * rdi: out
8221 * rsi: in
8222 * r11: offs (out.length - offset)
8223 * rcx: len
8224 * r8: k
8225 * r12: tmp1
8226 * r13: tmp2
8227 * r14: tmp3
8228 * r15: tmp4
8229 * rbx: tmp5
8230 * Multiply the in[] by word k and add to out[], return the carry in rax
8231 */
8232 void MacroAssembler::mul_add(Register out, Register in, Register offs,
8233 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
8234 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
8235
8236 Label L_carry, L_last_in, L_done;
8237
8238 // carry = 0;
8239 // for (int j=len-1; j >= 0; j--) {
8240 // long product = (in[j] & LONG_MASK) * kLong +
8241 // (out[offs] & LONG_MASK) + carry;
8242 // out[offs--] = (int)product;
8243 // carry = product >>> 32;
8244 // }
8245 //
8246 push(tmp1);
8247 push(tmp2);
8248 push(tmp3);
8249 push(tmp4);
8250 push(tmp5);
8251
8252 Register op2 = tmp2;
8253 const Register sum = tmp3;
8254 const Register op1 = tmp4;
8255 const Register carry = tmp5;
8256
8257 if (UseBMI2Instructions) {
8258 op2 = rdxReg;
8259 movl(op2, k);
8260 }
8261 else {
8262 movl(op2, k);
8263 }
8264
8265 xorq(carry, carry);
8266
8267 //First loop
8268
8269 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
8270 //The carry is in tmp5
8271 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
8272
8273 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
8274 decrementl(len);
8275 jccb(Assembler::negative, L_carry);
8276 decrementl(len);
8277 jccb(Assembler::negative, L_last_in);
8278
8279 movq(op1, Address(in, len, Address::times_4, 0));
8280 rorq(op1, 32);
8281
8282 subl(offs, 2);
8283 movq(sum, Address(out, offs, Address::times_4, 0));
8284 rorq(sum, 32);
8285
8286 if (UseBMI2Instructions) {
8287 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
8288 }
8289 else {
8290 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
8291 }
8292
8293 // Store back in big endian from little endian
8294 rorq(sum, 0x20);
8295 movq(Address(out, offs, Address::times_4, 0), sum);
8296
8297 testl(len, len);
8298 jccb(Assembler::zero, L_carry);
8299
8300 //Multiply the last in[] entry, if any
8301 bind(L_last_in);
8302 movl(op1, Address(in, 0));
8303 movl(sum, Address(out, offs, Address::times_4, -4));
8304
8305 movl(raxReg, k);
8306 mull(op1); //tmp4 * eax -> edx:eax
8307 addl(sum, carry);
8308 adcl(rdxReg, 0);
8309 addl(sum, raxReg);
8310 adcl(rdxReg, 0);
8311 movl(carry, rdxReg);
8312
8313 movl(Address(out, offs, Address::times_4, -4), sum);
8314
8315 bind(L_carry);
8316 //return tmp5/carry as carry in rax
8317 movl(rax, carry);
8318
8319 bind(L_done);
8320 pop(tmp5);
8321 pop(tmp4);
8322 pop(tmp3);
8323 pop(tmp2);
8324 pop(tmp1);
8325 }
8326 #endif
8327
8328 /**
8329 * Emits code to update CRC-32 with a byte value according to constants in table
8330 *
8331 * @param [in,out]crc Register containing the crc.
8332 * @param [in]val Register containing the byte to fold into the CRC.
8333 * @param [in]table Register containing the table of crc constants.
8334 *
8335 * uint32_t crc;
8336 * val = crc_table[(val ^ crc) & 0xFF];
8337 * crc = val ^ (crc >> 8);
8338 *
8339 */
8340 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
8341 xorl(val, crc);
8342 andl(val, 0xFF);
8343 shrl(crc, 8); // unsigned shift
8344 xorl(crc, Address(table, val, Address::times_4, 0));
8345 }
8346
8347 /**
8348 * Fold 128-bit data chunk
8349 */
8350 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
8351 if (UseAVX > 0) {
8352 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
8353 vpclmulldq(xcrc, xK, xcrc); // [63:0]
8354 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
8355 pxor(xcrc, xtmp);
8356 } else {
8357 movdqa(xtmp, xcrc);
8358 pclmulhdq(xtmp, xK); // [123:64]
8359 pclmulldq(xcrc, xK); // [63:0]
8360 pxor(xcrc, xtmp);
8361 movdqu(xtmp, Address(buf, offset));
8362 pxor(xcrc, xtmp);
8363 }
8364 }
8365
8366 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
8367 if (UseAVX > 0) {
8368 vpclmulhdq(xtmp, xK, xcrc);
8369 vpclmulldq(xcrc, xK, xcrc);
8370 pxor(xcrc, xbuf);
8371 pxor(xcrc, xtmp);
8372 } else {
8373 movdqa(xtmp, xcrc);
8374 pclmulhdq(xtmp, xK);
8375 pclmulldq(xcrc, xK);
8376 pxor(xcrc, xbuf);
8377 pxor(xcrc, xtmp);
8378 }
8379 }
8380
8381 /**
8382 * 8-bit folds to compute 32-bit CRC
8383 *
8384 * uint64_t xcrc;
8385 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
8386 */
8387 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
8388 movdl(tmp, xcrc);
8389 andl(tmp, 0xFF);
8390 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
8391 psrldq(xcrc, 1); // unsigned shift one byte
8392 pxor(xcrc, xtmp);
8393 }
8394
8395 /**
8396 * uint32_t crc;
8397 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8398 */
8399 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8400 movl(tmp, crc);
8401 andl(tmp, 0xFF);
8402 shrl(crc, 8);
8403 xorl(crc, Address(table, tmp, Address::times_4, 0));
8404 }
8405
8406 /**
8407 * @param crc register containing existing CRC (32-bit)
8408 * @param buf register pointing to input byte buffer (byte*)
8409 * @param len register containing number of bytes
8410 * @param table register that will contain address of CRC table
8411 * @param tmp scratch register
8412 */
8413 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8414 assert_different_registers(crc, buf, len, table, tmp, rax);
8415
8416 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8417 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8418
8419 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8420 // context for the registers used, where all instructions below are using 128-bit mode
8421 // On EVEX without VL and BW, these instructions will all be AVX.
8422 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8423 notl(crc); // ~crc
8424 cmpl(len, 16);
8425 jcc(Assembler::less, L_tail);
8426
8427 // Align buffer to 16 bytes
8428 movl(tmp, buf);
8429 andl(tmp, 0xF);
8430 jccb(Assembler::zero, L_aligned);
8431 subl(tmp, 16);
8432 addl(len, tmp);
8433
8434 align(4);
8435 BIND(L_align_loop);
8436 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8437 update_byte_crc32(crc, rax, table);
8438 increment(buf);
8439 incrementl(tmp);
8440 jccb(Assembler::less, L_align_loop);
8441
8442 BIND(L_aligned);
8443 movl(tmp, len); // save
8444 shrl(len, 4);
8445 jcc(Assembler::zero, L_tail_restore);
8446
8447 // Fold crc into first bytes of vector
8448 movdqa(xmm1, Address(buf, 0));
8449 movdl(rax, xmm1);
8450 xorl(crc, rax);
8451 if (VM_Version::supports_sse4_1()) {
8452 pinsrd(xmm1, crc, 0);
8453 } else {
8454 pinsrw(xmm1, crc, 0);
8455 shrl(crc, 16);
8456 pinsrw(xmm1, crc, 1);
8457 }
8458 addptr(buf, 16);
8459 subl(len, 4); // len > 0
8460 jcc(Assembler::less, L_fold_tail);
8461
8462 movdqa(xmm2, Address(buf, 0));
8463 movdqa(xmm3, Address(buf, 16));
8464 movdqa(xmm4, Address(buf, 32));
8465 addptr(buf, 48);
8466 subl(len, 3);
8467 jcc(Assembler::lessEqual, L_fold_512b);
8468
8469 // Fold total 512 bits of polynomial on each iteration,
8470 // 128 bits per each of 4 parallel streams.
8471 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8472
8473 align32();
8474 BIND(L_fold_512b_loop);
8475 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8476 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8477 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8478 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8479 addptr(buf, 64);
8480 subl(len, 4);
8481 jcc(Assembler::greater, L_fold_512b_loop);
8482
8483 // Fold 512 bits to 128 bits.
8484 BIND(L_fold_512b);
8485 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8486 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8487 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8488 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8489
8490 // Fold the rest of 128 bits data chunks
8491 BIND(L_fold_tail);
8492 addl(len, 3);
8493 jccb(Assembler::lessEqual, L_fold_128b);
8494 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8495
8496 BIND(L_fold_tail_loop);
8497 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8498 addptr(buf, 16);
8499 decrementl(len);
8500 jccb(Assembler::greater, L_fold_tail_loop);
8501
8502 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8503 BIND(L_fold_128b);
8504 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8505 if (UseAVX > 0) {
8506 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8507 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8508 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8509 } else {
8510 movdqa(xmm2, xmm0);
8511 pclmulqdq(xmm2, xmm1, 0x1);
8512 movdqa(xmm3, xmm0);
8513 pand(xmm3, xmm2);
8514 pclmulqdq(xmm0, xmm3, 0x1);
8515 }
8516 psrldq(xmm1, 8);
8517 psrldq(xmm2, 4);
8518 pxor(xmm0, xmm1);
8519 pxor(xmm0, xmm2);
8520
8521 // 8 8-bit folds to compute 32-bit CRC.
8522 for (int j = 0; j < 4; j++) {
8523 fold_8bit_crc32(xmm0, table, xmm1, rax);
8524 }
8525 movdl(crc, xmm0); // mov 32 bits to general register
8526 for (int j = 0; j < 4; j++) {
8527 fold_8bit_crc32(crc, table, rax);
8528 }
8529
8530 BIND(L_tail_restore);
8531 movl(len, tmp); // restore
8532 BIND(L_tail);
8533 andl(len, 0xf);
8534 jccb(Assembler::zero, L_exit);
8535
8536 // Fold the rest of bytes
8537 align(4);
8538 BIND(L_tail_loop);
8539 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8540 update_byte_crc32(crc, rax, table);
8541 increment(buf);
8542 decrementl(len);
8543 jccb(Assembler::greater, L_tail_loop);
8544
8545 BIND(L_exit);
8546 notl(crc); // ~c
8547 }
8548
8549 #ifdef _LP64
8550 // Helper function for AVX 512 CRC32
8551 // Fold 512-bit data chunks
8552 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8553 Register pos, int offset) {
8554 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8555 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8556 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8557 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8558 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8559 }
8560
8561 // Helper function for AVX 512 CRC32
8562 // Compute CRC32 for < 256B buffers
8563 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8564 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8565 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8566
8567 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8568 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8569 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8570
8571 // check if there is enough buffer to be able to fold 16B at a time
8572 cmpl(len, 32);
8573 jcc(Assembler::less, L_less_than_32);
8574
8575 // if there is, load the constants
8576 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8577 movdl(xmm0, crc); // get the initial crc value
8578 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8579 pxor(xmm7, xmm0);
8580
8581 // update the buffer pointer
8582 addl(pos, 16);
8583 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8584 subl(len, 32);
8585 jmp(L_16B_reduction_loop);
8586
8587 bind(L_less_than_32);
8588 //mov initial crc to the return value. this is necessary for zero - length buffers.
8589 movl(rax, crc);
8590 testl(len, len);
8591 jcc(Assembler::equal, L_cleanup);
8592
8593 movdl(xmm0, crc); //get the initial crc value
8594
8595 cmpl(len, 16);
8596 jcc(Assembler::equal, L_exact_16_left);
8597 jcc(Assembler::less, L_less_than_16_left);
8598
8599 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8600 pxor(xmm7, xmm0); //xor the initial crc value
8601 addl(pos, 16);
8602 subl(len, 16);
8603 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8604 jmp(L_get_last_two_xmms);
8605
8606 bind(L_less_than_16_left);
8607 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8608 pxor(xmm1, xmm1);
8609 movptr(tmp1, rsp);
8610 movdqu(Address(tmp1, 0 * 16), xmm1);
8611
8612 cmpl(len, 4);
8613 jcc(Assembler::less, L_only_less_than_4);
8614
8615 //backup the counter value
8616 movl(tmp2, len);
8617 cmpl(len, 8);
8618 jcc(Assembler::less, L_less_than_8_left);
8619
8620 //load 8 Bytes
8621 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8622 movq(Address(tmp1, 0 * 16), rax);
8623 addptr(tmp1, 8);
8624 subl(len, 8);
8625 addl(pos, 8);
8626
8627 bind(L_less_than_8_left);
8628 cmpl(len, 4);
8629 jcc(Assembler::less, L_less_than_4_left);
8630
8631 //load 4 Bytes
8632 movl(rax, Address(buf, pos, Address::times_1, 0));
8633 movl(Address(tmp1, 0 * 16), rax);
8634 addptr(tmp1, 4);
8635 subl(len, 4);
8636 addl(pos, 4);
8637
8638 bind(L_less_than_4_left);
8639 cmpl(len, 2);
8640 jcc(Assembler::less, L_less_than_2_left);
8641
8642 // load 2 Bytes
8643 movw(rax, Address(buf, pos, Address::times_1, 0));
8644 movl(Address(tmp1, 0 * 16), rax);
8645 addptr(tmp1, 2);
8646 subl(len, 2);
8647 addl(pos, 2);
8648
8649 bind(L_less_than_2_left);
8650 cmpl(len, 1);
8651 jcc(Assembler::less, L_zero_left);
8652
8653 // load 1 Byte
8654 movb(rax, Address(buf, pos, Address::times_1, 0));
8655 movb(Address(tmp1, 0 * 16), rax);
8656
8657 bind(L_zero_left);
8658 movdqu(xmm7, Address(rsp, 0));
8659 pxor(xmm7, xmm0); //xor the initial crc value
8660
8661 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8662 movdqu(xmm0, Address(rax, tmp2));
8663 pshufb(xmm7, xmm0);
8664 jmp(L_128_done);
8665
8666 bind(L_exact_16_left);
8667 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8668 pxor(xmm7, xmm0); //xor the initial crc value
8669 jmp(L_128_done);
8670
8671 bind(L_only_less_than_4);
8672 cmpl(len, 3);
8673 jcc(Assembler::less, L_only_less_than_3);
8674
8675 // load 3 Bytes
8676 movb(rax, Address(buf, pos, Address::times_1, 0));
8677 movb(Address(tmp1, 0), rax);
8678
8679 movb(rax, Address(buf, pos, Address::times_1, 1));
8680 movb(Address(tmp1, 1), rax);
8681
8682 movb(rax, Address(buf, pos, Address::times_1, 2));
8683 movb(Address(tmp1, 2), rax);
8684
8685 movdqu(xmm7, Address(rsp, 0));
8686 pxor(xmm7, xmm0); //xor the initial crc value
8687
8688 pslldq(xmm7, 0x5);
8689 jmp(L_barrett);
8690 bind(L_only_less_than_3);
8691 cmpl(len, 2);
8692 jcc(Assembler::less, L_only_less_than_2);
8693
8694 // load 2 Bytes
8695 movb(rax, Address(buf, pos, Address::times_1, 0));
8696 movb(Address(tmp1, 0), rax);
8697
8698 movb(rax, Address(buf, pos, Address::times_1, 1));
8699 movb(Address(tmp1, 1), rax);
8700
8701 movdqu(xmm7, Address(rsp, 0));
8702 pxor(xmm7, xmm0); //xor the initial crc value
8703
8704 pslldq(xmm7, 0x6);
8705 jmp(L_barrett);
8706
8707 bind(L_only_less_than_2);
8708 //load 1 Byte
8709 movb(rax, Address(buf, pos, Address::times_1, 0));
8710 movb(Address(tmp1, 0), rax);
8711
8712 movdqu(xmm7, Address(rsp, 0));
8713 pxor(xmm7, xmm0); //xor the initial crc value
8714
8715 pslldq(xmm7, 0x7);
8716 }
8717
8718 /**
8719 * Compute CRC32 using AVX512 instructions
8720 * param crc register containing existing CRC (32-bit)
8721 * param buf register pointing to input byte buffer (byte*)
8722 * param len register containing number of bytes
8723 * param table address of crc or crc32c table
8724 * param tmp1 scratch register
8725 * param tmp2 scratch register
8726 * return rax result register
8727 *
8728 * This routine is identical for crc32c with the exception of the precomputed constant
8729 * table which will be passed as the table argument. The calculation steps are
8730 * the same for both variants.
8731 */
8732 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8733 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8734
8735 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8736 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8737 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8738 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8739 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8740
8741 const Register pos = r12;
8742 push(r12);
8743 subptr(rsp, 16 * 2 + 8);
8744
8745 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8746 // context for the registers used, where all instructions below are using 128-bit mode
8747 // On EVEX without VL and BW, these instructions will all be AVX.
8748 movl(pos, 0);
8749
8750 // check if smaller than 256B
8751 cmpl(len, 256);
8752 jcc(Assembler::less, L_less_than_256);
8753
8754 // load the initial crc value
8755 movdl(xmm10, crc);
8756
8757 // receive the initial 64B data, xor the initial crc value
8758 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8759 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8760 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8761 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8762
8763 subl(len, 256);
8764 cmpl(len, 256);
8765 jcc(Assembler::less, L_fold_128_B_loop);
8766
8767 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8768 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8769 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8770 subl(len, 256);
8771
8772 bind(L_fold_256_B_loop);
8773 addl(pos, 256);
8774 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8775 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8776 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8777 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8778
8779 subl(len, 256);
8780 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8781
8782 // Fold 256 into 128
8783 addl(pos, 256);
8784 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8785 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8786 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8787
8788 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8789 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8790 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8791
8792 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8793 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8794
8795 addl(len, 128);
8796 jmp(L_fold_128_B_register);
8797
8798 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8799 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8800
8801 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8802 bind(L_fold_128_B_loop);
8803 addl(pos, 128);
8804 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8805 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8806
8807 subl(len, 128);
8808 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8809
8810 addl(pos, 128);
8811
8812 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8813 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8814 bind(L_fold_128_B_register);
8815 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8816 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8817 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8818 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8819 // save last that has no multiplicand
8820 vextracti64x2(xmm7, xmm4, 3);
8821
8822 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8823 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8824 // Needed later in reduction loop
8825 movdqu(xmm10, Address(table, 1 * 16));
8826 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8827 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8828
8829 // Swap 1,0,3,2 - 01 00 11 10
8830 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8831 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8832 vextracti128(xmm5, xmm8, 1);
8833 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8834
8835 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8836 // instead of a cmp instruction, we use the negative flag with the jl instruction
8837 addl(len, 128 - 16);
8838 jcc(Assembler::less, L_final_reduction_for_128);
8839
8840 bind(L_16B_reduction_loop);
8841 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8842 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8843 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8844 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8845 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8846 addl(pos, 16);
8847 subl(len, 16);
8848 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8849
8850 bind(L_final_reduction_for_128);
8851 addl(len, 16);
8852 jcc(Assembler::equal, L_128_done);
8853
8854 bind(L_get_last_two_xmms);
8855 movdqu(xmm2, xmm7);
8856 addl(pos, len);
8857 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8858 subl(pos, len);
8859
8860 // get rid of the extra data that was loaded before
8861 // load the shift constant
8862 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8863 movdqu(xmm0, Address(rax, len));
8864 addl(rax, len);
8865
8866 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8867 //Change mask to 512
8868 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8869 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8870
8871 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8872 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8873 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8874 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8875 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8876
8877 bind(L_128_done);
8878 // compute crc of a 128-bit value
8879 movdqu(xmm10, Address(table, 3 * 16));
8880 movdqu(xmm0, xmm7);
8881
8882 // 64b fold
8883 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8884 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8885 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8886
8887 // 32b fold
8888 movdqu(xmm0, xmm7);
8889 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8890 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8891 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8892 jmp(L_barrett);
8893
8894 bind(L_less_than_256);
8895 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8896
8897 //barrett reduction
8898 bind(L_barrett);
8899 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8900 movdqu(xmm1, xmm7);
8901 movdqu(xmm2, xmm7);
8902 movdqu(xmm10, Address(table, 4 * 16));
8903
8904 pclmulqdq(xmm7, xmm10, 0x0);
8905 pxor(xmm7, xmm2);
8906 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8907 movdqu(xmm2, xmm7);
8908 pclmulqdq(xmm7, xmm10, 0x10);
8909 pxor(xmm7, xmm2);
8910 pxor(xmm7, xmm1);
8911 pextrd(crc, xmm7, 2);
8912
8913 bind(L_cleanup);
8914 addptr(rsp, 16 * 2 + 8);
8915 pop(r12);
8916 }
8917
8918 // S. Gueron / Information Processing Letters 112 (2012) 184
8919 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8920 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8921 // Output: the 64-bit carry-less product of B * CONST
8922 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8923 Register tmp1, Register tmp2, Register tmp3) {
8924 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8925 if (n > 0) {
8926 addq(tmp3, n * 256 * 8);
8927 }
8928 // Q1 = TABLEExt[n][B & 0xFF];
8929 movl(tmp1, in);
8930 andl(tmp1, 0x000000FF);
8931 shll(tmp1, 3);
8932 addq(tmp1, tmp3);
8933 movq(tmp1, Address(tmp1, 0));
8934
8935 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8936 movl(tmp2, in);
8937 shrl(tmp2, 8);
8938 andl(tmp2, 0x000000FF);
8939 shll(tmp2, 3);
8940 addq(tmp2, tmp3);
8941 movq(tmp2, Address(tmp2, 0));
8942
8943 shlq(tmp2, 8);
8944 xorq(tmp1, tmp2);
8945
8946 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8947 movl(tmp2, in);
8948 shrl(tmp2, 16);
8949 andl(tmp2, 0x000000FF);
8950 shll(tmp2, 3);
8951 addq(tmp2, tmp3);
8952 movq(tmp2, Address(tmp2, 0));
8953
8954 shlq(tmp2, 16);
8955 xorq(tmp1, tmp2);
8956
8957 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8958 shrl(in, 24);
8959 andl(in, 0x000000FF);
8960 shll(in, 3);
8961 addq(in, tmp3);
8962 movq(in, Address(in, 0));
8963
8964 shlq(in, 24);
8965 xorq(in, tmp1);
8966 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8967 }
8968
8969 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8970 Register in_out,
8971 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8972 XMMRegister w_xtmp2,
8973 Register tmp1,
8974 Register n_tmp2, Register n_tmp3) {
8975 if (is_pclmulqdq_supported) {
8976 movdl(w_xtmp1, in_out); // modified blindly
8977
8978 movl(tmp1, const_or_pre_comp_const_index);
8979 movdl(w_xtmp2, tmp1);
8980 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8981
8982 movdq(in_out, w_xtmp1);
8983 } else {
8984 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8985 }
8986 }
8987
8988 // Recombination Alternative 2: No bit-reflections
8989 // T1 = (CRC_A * U1) << 1
8990 // T2 = (CRC_B * U2) << 1
8991 // C1 = T1 >> 32
8992 // C2 = T2 >> 32
8993 // T1 = T1 & 0xFFFFFFFF
8994 // T2 = T2 & 0xFFFFFFFF
8995 // T1 = CRC32(0, T1)
8996 // T2 = CRC32(0, T2)
8997 // C1 = C1 ^ T1
8998 // C2 = C2 ^ T2
8999 // CRC = C1 ^ C2 ^ CRC_C
9000 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9001 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9002 Register tmp1, Register tmp2,
9003 Register n_tmp3) {
9004 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9005 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9006 shlq(in_out, 1);
9007 movl(tmp1, in_out);
9008 shrq(in_out, 32);
9009 xorl(tmp2, tmp2);
9010 crc32(tmp2, tmp1, 4);
9011 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
9012 shlq(in1, 1);
9013 movl(tmp1, in1);
9014 shrq(in1, 32);
9015 xorl(tmp2, tmp2);
9016 crc32(tmp2, tmp1, 4);
9017 xorl(in1, tmp2);
9018 xorl(in_out, in1);
9019 xorl(in_out, in2);
9020 }
9021
9022 // Set N to predefined value
9023 // Subtract from a length of a buffer
9024 // execute in a loop:
9025 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
9026 // for i = 1 to N do
9027 // CRC_A = CRC32(CRC_A, A[i])
9028 // CRC_B = CRC32(CRC_B, B[i])
9029 // CRC_C = CRC32(CRC_C, C[i])
9030 // end for
9031 // Recombine
9032 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9033 Register in_out1, Register in_out2, Register in_out3,
9034 Register tmp1, Register tmp2, Register tmp3,
9035 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9036 Register tmp4, Register tmp5,
9037 Register n_tmp6) {
9038 Label L_processPartitions;
9039 Label L_processPartition;
9040 Label L_exit;
9041
9042 bind(L_processPartitions);
9043 cmpl(in_out1, 3 * size);
9044 jcc(Assembler::less, L_exit);
9045 xorl(tmp1, tmp1);
9046 xorl(tmp2, tmp2);
9047 movq(tmp3, in_out2);
9048 addq(tmp3, size);
9049
9050 bind(L_processPartition);
9051 crc32(in_out3, Address(in_out2, 0), 8);
9052 crc32(tmp1, Address(in_out2, size), 8);
9053 crc32(tmp2, Address(in_out2, size * 2), 8);
9054 addq(in_out2, 8);
9055 cmpq(in_out2, tmp3);
9056 jcc(Assembler::less, L_processPartition);
9057 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9058 w_xtmp1, w_xtmp2, w_xtmp3,
9059 tmp4, tmp5,
9060 n_tmp6);
9061 addq(in_out2, 2 * size);
9062 subl(in_out1, 3 * size);
9063 jmp(L_processPartitions);
9064
9065 bind(L_exit);
9066 }
9067 #else
9068 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
9069 Register tmp1, Register tmp2, Register tmp3,
9070 XMMRegister xtmp1, XMMRegister xtmp2) {
9071 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
9072 if (n > 0) {
9073 addl(tmp3, n * 256 * 8);
9074 }
9075 // Q1 = TABLEExt[n][B & 0xFF];
9076 movl(tmp1, in_out);
9077 andl(tmp1, 0x000000FF);
9078 shll(tmp1, 3);
9079 addl(tmp1, tmp3);
9080 movq(xtmp1, Address(tmp1, 0));
9081
9082 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
9083 movl(tmp2, in_out);
9084 shrl(tmp2, 8);
9085 andl(tmp2, 0x000000FF);
9086 shll(tmp2, 3);
9087 addl(tmp2, tmp3);
9088 movq(xtmp2, Address(tmp2, 0));
9089
9090 psllq(xtmp2, 8);
9091 pxor(xtmp1, xtmp2);
9092
9093 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
9094 movl(tmp2, in_out);
9095 shrl(tmp2, 16);
9096 andl(tmp2, 0x000000FF);
9097 shll(tmp2, 3);
9098 addl(tmp2, tmp3);
9099 movq(xtmp2, Address(tmp2, 0));
9100
9101 psllq(xtmp2, 16);
9102 pxor(xtmp1, xtmp2);
9103
9104 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
9105 shrl(in_out, 24);
9106 andl(in_out, 0x000000FF);
9107 shll(in_out, 3);
9108 addl(in_out, tmp3);
9109 movq(xtmp2, Address(in_out, 0));
9110
9111 psllq(xtmp2, 24);
9112 pxor(xtmp1, xtmp2); // Result in CXMM
9113 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
9114 }
9115
9116 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
9117 Register in_out,
9118 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
9119 XMMRegister w_xtmp2,
9120 Register tmp1,
9121 Register n_tmp2, Register n_tmp3) {
9122 if (is_pclmulqdq_supported) {
9123 movdl(w_xtmp1, in_out);
9124
9125 movl(tmp1, const_or_pre_comp_const_index);
9126 movdl(w_xtmp2, tmp1);
9127 pclmulqdq(w_xtmp1, w_xtmp2, 0);
9128 // Keep result in XMM since GPR is 32 bit in length
9129 } else {
9130 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
9131 }
9132 }
9133
9134 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
9135 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9136 Register tmp1, Register tmp2,
9137 Register n_tmp3) {
9138 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9139 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
9140
9141 psllq(w_xtmp1, 1);
9142 movdl(tmp1, w_xtmp1);
9143 psrlq(w_xtmp1, 32);
9144 movdl(in_out, w_xtmp1);
9145
9146 xorl(tmp2, tmp2);
9147 crc32(tmp2, tmp1, 4);
9148 xorl(in_out, tmp2);
9149
9150 psllq(w_xtmp2, 1);
9151 movdl(tmp1, w_xtmp2);
9152 psrlq(w_xtmp2, 32);
9153 movdl(in1, w_xtmp2);
9154
9155 xorl(tmp2, tmp2);
9156 crc32(tmp2, tmp1, 4);
9157 xorl(in1, tmp2);
9158 xorl(in_out, in1);
9159 xorl(in_out, in2);
9160 }
9161
9162 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
9163 Register in_out1, Register in_out2, Register in_out3,
9164 Register tmp1, Register tmp2, Register tmp3,
9165 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9166 Register tmp4, Register tmp5,
9167 Register n_tmp6) {
9168 Label L_processPartitions;
9169 Label L_processPartition;
9170 Label L_exit;
9171
9172 bind(L_processPartitions);
9173 cmpl(in_out1, 3 * size);
9174 jcc(Assembler::less, L_exit);
9175 xorl(tmp1, tmp1);
9176 xorl(tmp2, tmp2);
9177 movl(tmp3, in_out2);
9178 addl(tmp3, size);
9179
9180 bind(L_processPartition);
9181 crc32(in_out3, Address(in_out2, 0), 4);
9182 crc32(tmp1, Address(in_out2, size), 4);
9183 crc32(tmp2, Address(in_out2, size*2), 4);
9184 crc32(in_out3, Address(in_out2, 0+4), 4);
9185 crc32(tmp1, Address(in_out2, size+4), 4);
9186 crc32(tmp2, Address(in_out2, size*2+4), 4);
9187 addl(in_out2, 8);
9188 cmpl(in_out2, tmp3);
9189 jcc(Assembler::less, L_processPartition);
9190
9191 push(tmp3);
9192 push(in_out1);
9193 push(in_out2);
9194 tmp4 = tmp3;
9195 tmp5 = in_out1;
9196 n_tmp6 = in_out2;
9197
9198 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
9199 w_xtmp1, w_xtmp2, w_xtmp3,
9200 tmp4, tmp5,
9201 n_tmp6);
9202
9203 pop(in_out2);
9204 pop(in_out1);
9205 pop(tmp3);
9206
9207 addl(in_out2, 2 * size);
9208 subl(in_out1, 3 * size);
9209 jmp(L_processPartitions);
9210
9211 bind(L_exit);
9212 }
9213 #endif //LP64
9214
9215 #ifdef _LP64
9216 // Algorithm 2: Pipelined usage of the CRC32 instruction.
9217 // Input: A buffer I of L bytes.
9218 // Output: the CRC32C value of the buffer.
9219 // Notations:
9220 // Write L = 24N + r, with N = floor (L/24).
9221 // r = L mod 24 (0 <= r < 24).
9222 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
9223 // N quadwords, and R consists of r bytes.
9224 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
9225 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
9226 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
9227 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
9228 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9229 Register tmp1, Register tmp2, Register tmp3,
9230 Register tmp4, Register tmp5, Register tmp6,
9231 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9232 bool is_pclmulqdq_supported) {
9233 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9234 Label L_wordByWord;
9235 Label L_byteByByteProlog;
9236 Label L_byteByByte;
9237 Label L_exit;
9238
9239 if (is_pclmulqdq_supported ) {
9240 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9241 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9242
9243 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9244 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9245
9246 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9247 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9248 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
9249 } else {
9250 const_or_pre_comp_const_index[0] = 1;
9251 const_or_pre_comp_const_index[1] = 0;
9252
9253 const_or_pre_comp_const_index[2] = 3;
9254 const_or_pre_comp_const_index[3] = 2;
9255
9256 const_or_pre_comp_const_index[4] = 5;
9257 const_or_pre_comp_const_index[5] = 4;
9258 }
9259 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9260 in2, in1, in_out,
9261 tmp1, tmp2, tmp3,
9262 w_xtmp1, w_xtmp2, w_xtmp3,
9263 tmp4, tmp5,
9264 tmp6);
9265 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9266 in2, in1, in_out,
9267 tmp1, tmp2, tmp3,
9268 w_xtmp1, w_xtmp2, w_xtmp3,
9269 tmp4, tmp5,
9270 tmp6);
9271 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9272 in2, in1, in_out,
9273 tmp1, tmp2, tmp3,
9274 w_xtmp1, w_xtmp2, w_xtmp3,
9275 tmp4, tmp5,
9276 tmp6);
9277 movl(tmp1, in2);
9278 andl(tmp1, 0x00000007);
9279 negl(tmp1);
9280 addl(tmp1, in2);
9281 addq(tmp1, in1);
9282
9283 cmpq(in1, tmp1);
9284 jccb(Assembler::greaterEqual, L_byteByByteProlog);
9285 align(16);
9286 BIND(L_wordByWord);
9287 crc32(in_out, Address(in1, 0), 8);
9288 addq(in1, 8);
9289 cmpq(in1, tmp1);
9290 jcc(Assembler::less, L_wordByWord);
9291
9292 BIND(L_byteByByteProlog);
9293 andl(in2, 0x00000007);
9294 movl(tmp2, 1);
9295
9296 cmpl(tmp2, in2);
9297 jccb(Assembler::greater, L_exit);
9298 BIND(L_byteByByte);
9299 crc32(in_out, Address(in1, 0), 1);
9300 incq(in1);
9301 incl(tmp2);
9302 cmpl(tmp2, in2);
9303 jcc(Assembler::lessEqual, L_byteByByte);
9304
9305 BIND(L_exit);
9306 }
9307 #else
9308 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
9309 Register tmp1, Register tmp2, Register tmp3,
9310 Register tmp4, Register tmp5, Register tmp6,
9311 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
9312 bool is_pclmulqdq_supported) {
9313 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
9314 Label L_wordByWord;
9315 Label L_byteByByteProlog;
9316 Label L_byteByByte;
9317 Label L_exit;
9318
9319 if (is_pclmulqdq_supported) {
9320 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::crc32c_table_addr();
9321 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 1);
9322
9323 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 2);
9324 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 3);
9325
9326 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 4);
9327 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::crc32c_table_addr() + 5);
9328 } else {
9329 const_or_pre_comp_const_index[0] = 1;
9330 const_or_pre_comp_const_index[1] = 0;
9331
9332 const_or_pre_comp_const_index[2] = 3;
9333 const_or_pre_comp_const_index[3] = 2;
9334
9335 const_or_pre_comp_const_index[4] = 5;
9336 const_or_pre_comp_const_index[5] = 4;
9337 }
9338 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
9339 in2, in1, in_out,
9340 tmp1, tmp2, tmp3,
9341 w_xtmp1, w_xtmp2, w_xtmp3,
9342 tmp4, tmp5,
9343 tmp6);
9344 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
9345 in2, in1, in_out,
9346 tmp1, tmp2, tmp3,
9347 w_xtmp1, w_xtmp2, w_xtmp3,
9348 tmp4, tmp5,
9349 tmp6);
9350 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
9351 in2, in1, in_out,
9352 tmp1, tmp2, tmp3,
9353 w_xtmp1, w_xtmp2, w_xtmp3,
9354 tmp4, tmp5,
9355 tmp6);
9356 movl(tmp1, in2);
9357 andl(tmp1, 0x00000007);
9358 negl(tmp1);
9359 addl(tmp1, in2);
9360 addl(tmp1, in1);
9361
9362 BIND(L_wordByWord);
9363 cmpl(in1, tmp1);
9364 jcc(Assembler::greaterEqual, L_byteByByteProlog);
9365 crc32(in_out, Address(in1,0), 4);
9366 addl(in1, 4);
9367 jmp(L_wordByWord);
9368
9369 BIND(L_byteByByteProlog);
9370 andl(in2, 0x00000007);
9371 movl(tmp2, 1);
9372
9373 BIND(L_byteByByte);
9374 cmpl(tmp2, in2);
9375 jccb(Assembler::greater, L_exit);
9376 movb(tmp1, Address(in1, 0));
9377 crc32(in_out, tmp1, 1);
9378 incl(in1);
9379 incl(tmp2);
9380 jmp(L_byteByByte);
9381
9382 BIND(L_exit);
9383 }
9384 #endif // LP64
9385 #undef BIND
9386 #undef BLOCK_COMMENT
9387
9388 // Compress char[] array to byte[].
9389 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
9390 // Return the array length if every element in array can be encoded,
9391 // otherwise, the index of first non-latin1 (> 0xff) character.
9392 // @IntrinsicCandidate
9393 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
9394 // for (int i = 0; i < len; i++) {
9395 // char c = src[srcOff];
9396 // if (c > 0xff) {
9397 // return i; // return index of non-latin1 char
9398 // }
9399 // dst[dstOff] = (byte)c;
9400 // srcOff++;
9401 // dstOff++;
9402 // }
9403 // return len;
9404 // }
9405 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9406 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9407 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9408 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9409 Label copy_chars_loop, done, reset_sp, copy_tail;
9410
9411 // rsi: src
9412 // rdi: dst
9413 // rdx: len
9414 // rcx: tmp5
9415 // rax: result
9416
9417 // rsi holds start addr of source char[] to be compressed
9418 // rdi holds start addr of destination byte[]
9419 // rdx holds length
9420
9421 assert(len != result, "");
9422
9423 // save length for return
9424 movl(result, len);
9425
9426 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9427 VM_Version::supports_avx512vlbw() &&
9428 VM_Version::supports_bmi2()) {
9429
9430 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9431
9432 // alignment
9433 Label post_alignment;
9434
9435 // if length of the string is less than 32, handle it the old fashioned way
9436 testl(len, -32);
9437 jcc(Assembler::zero, below_threshold);
9438
9439 // First check whether a character is compressible ( <= 0xFF).
9440 // Create mask to test for Unicode chars inside zmm vector
9441 movl(tmp5, 0x00FF);
9442 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9443
9444 testl(len, -64);
9445 jccb(Assembler::zero, post_alignment);
9446
9447 movl(tmp5, dst);
9448 andl(tmp5, (32 - 1));
9449 negl(tmp5);
9450 andl(tmp5, (32 - 1));
9451
9452 // bail out when there is nothing to be done
9453 testl(tmp5, 0xFFFFFFFF);
9454 jccb(Assembler::zero, post_alignment);
9455
9456 // ~(~0 << len), where len is the # of remaining elements to process
9457 movl(len, 0xFFFFFFFF);
9458 shlxl(len, len, tmp5);
9459 notl(len);
9460 kmovdl(mask2, len);
9461 movl(len, result);
9462
9463 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9464 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9465 ktestd(mask1, mask2);
9466 jcc(Assembler::carryClear, copy_tail);
9467
9468 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9469
9470 addptr(src, tmp5);
9471 addptr(src, tmp5);
9472 addptr(dst, tmp5);
9473 subl(len, tmp5);
9474
9475 bind(post_alignment);
9476 // end of alignment
9477
9478 movl(tmp5, len);
9479 andl(tmp5, (32 - 1)); // tail count (in chars)
9480 andl(len, ~(32 - 1)); // vector count (in chars)
9481 jccb(Assembler::zero, copy_loop_tail);
9482
9483 lea(src, Address(src, len, Address::times_2));
9484 lea(dst, Address(dst, len, Address::times_1));
9485 negptr(len);
9486
9487 bind(copy_32_loop);
9488 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9489 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9490 kortestdl(mask1, mask1);
9491 jccb(Assembler::carryClear, reset_for_copy_tail);
9492
9493 // All elements in current processed chunk are valid candidates for
9494 // compression. Write a truncated byte elements to the memory.
9495 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9496 addptr(len, 32);
9497 jccb(Assembler::notZero, copy_32_loop);
9498
9499 bind(copy_loop_tail);
9500 // bail out when there is nothing to be done
9501 testl(tmp5, 0xFFFFFFFF);
9502 jcc(Assembler::zero, done);
9503
9504 movl(len, tmp5);
9505
9506 // ~(~0 << len), where len is the # of remaining elements to process
9507 movl(tmp5, 0xFFFFFFFF);
9508 shlxl(tmp5, tmp5, len);
9509 notl(tmp5);
9510
9511 kmovdl(mask2, tmp5);
9512
9513 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9514 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9515 ktestd(mask1, mask2);
9516 jcc(Assembler::carryClear, copy_tail);
9517
9518 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9519 jmp(done);
9520
9521 bind(reset_for_copy_tail);
9522 lea(src, Address(src, tmp5, Address::times_2));
9523 lea(dst, Address(dst, tmp5, Address::times_1));
9524 subptr(len, tmp5);
9525 jmp(copy_chars_loop);
9526
9527 bind(below_threshold);
9528 }
9529
9530 if (UseSSE42Intrinsics) {
9531 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9532
9533 // vectored compression
9534 testl(len, 0xfffffff8);
9535 jcc(Assembler::zero, copy_tail);
9536
9537 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9538 movdl(tmp1Reg, tmp5);
9539 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9540
9541 andl(len, 0xfffffff0);
9542 jccb(Assembler::zero, copy_16);
9543
9544 // compress 16 chars per iter
9545 pxor(tmp4Reg, tmp4Reg);
9546
9547 lea(src, Address(src, len, Address::times_2));
9548 lea(dst, Address(dst, len, Address::times_1));
9549 negptr(len);
9550
9551 bind(copy_32_loop);
9552 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9553 por(tmp4Reg, tmp2Reg);
9554 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9555 por(tmp4Reg, tmp3Reg);
9556 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9557 jccb(Assembler::notZero, reset_for_copy_tail);
9558 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9559 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9560 addptr(len, 16);
9561 jccb(Assembler::notZero, copy_32_loop);
9562
9563 // compress next vector of 8 chars (if any)
9564 bind(copy_16);
9565 // len = 0
9566 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9567 jccb(Assembler::zero, copy_tail_sse);
9568
9569 pxor(tmp3Reg, tmp3Reg);
9570
9571 movdqu(tmp2Reg, Address(src, 0));
9572 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9573 jccb(Assembler::notZero, reset_for_copy_tail);
9574 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9575 movq(Address(dst, 0), tmp2Reg);
9576 addptr(src, 16);
9577 addptr(dst, 8);
9578 jmpb(copy_tail_sse);
9579
9580 bind(reset_for_copy_tail);
9581 movl(tmp5, result);
9582 andl(tmp5, 0x0000000f);
9583 lea(src, Address(src, tmp5, Address::times_2));
9584 lea(dst, Address(dst, tmp5, Address::times_1));
9585 subptr(len, tmp5);
9586 jmpb(copy_chars_loop);
9587
9588 bind(copy_tail_sse);
9589 movl(len, result);
9590 andl(len, 0x00000007); // tail count (in chars)
9591 }
9592 // compress 1 char per iter
9593 bind(copy_tail);
9594 testl(len, len);
9595 jccb(Assembler::zero, done);
9596 lea(src, Address(src, len, Address::times_2));
9597 lea(dst, Address(dst, len, Address::times_1));
9598 negptr(len);
9599
9600 bind(copy_chars_loop);
9601 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9602 testl(tmp5, 0xff00); // check if Unicode char
9603 jccb(Assembler::notZero, reset_sp);
9604 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9605 increment(len);
9606 jccb(Assembler::notZero, copy_chars_loop);
9607
9608 // add len then return (len will be zero if compress succeeded, otherwise negative)
9609 bind(reset_sp);
9610 addl(result, len);
9611
9612 bind(done);
9613 }
9614
9615 // Inflate byte[] array to char[].
9616 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9617 // @IntrinsicCandidate
9618 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9619 // for (int i = 0; i < len; i++) {
9620 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9621 // }
9622 // }
9623 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9624 XMMRegister tmp1, Register tmp2, KRegister mask) {
9625 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9626 // rsi: src
9627 // rdi: dst
9628 // rdx: len
9629 // rcx: tmp2
9630
9631 // rsi holds start addr of source byte[] to be inflated
9632 // rdi holds start addr of destination char[]
9633 // rdx holds length
9634 assert_different_registers(src, dst, len, tmp2);
9635 movl(tmp2, len);
9636 if ((UseAVX > 2) && // AVX512
9637 VM_Version::supports_avx512vlbw() &&
9638 VM_Version::supports_bmi2()) {
9639
9640 Label copy_32_loop, copy_tail;
9641 Register tmp3_aliased = len;
9642
9643 // if length of the string is less than 16, handle it in an old fashioned way
9644 testl(len, -16);
9645 jcc(Assembler::zero, below_threshold);
9646
9647 testl(len, -1 * AVX3Threshold);
9648 jcc(Assembler::zero, avx3_threshold);
9649
9650 // In order to use only one arithmetic operation for the main loop we use
9651 // this pre-calculation
9652 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9653 andl(len, -32); // vector count
9654 jccb(Assembler::zero, copy_tail);
9655
9656 lea(src, Address(src, len, Address::times_1));
9657 lea(dst, Address(dst, len, Address::times_2));
9658 negptr(len);
9659
9660
9661 // inflate 32 chars per iter
9662 bind(copy_32_loop);
9663 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9664 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9665 addptr(len, 32);
9666 jcc(Assembler::notZero, copy_32_loop);
9667
9668 bind(copy_tail);
9669 // bail out when there is nothing to be done
9670 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9671 jcc(Assembler::zero, done);
9672
9673 // ~(~0 << length), where length is the # of remaining elements to process
9674 movl(tmp3_aliased, -1);
9675 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9676 notl(tmp3_aliased);
9677 kmovdl(mask, tmp3_aliased);
9678 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9679 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9680
9681 jmp(done);
9682 bind(avx3_threshold);
9683 }
9684 if (UseSSE42Intrinsics) {
9685 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9686
9687 if (UseAVX > 1) {
9688 andl(tmp2, (16 - 1));
9689 andl(len, -16);
9690 jccb(Assembler::zero, copy_new_tail);
9691 } else {
9692 andl(tmp2, 0x00000007); // tail count (in chars)
9693 andl(len, 0xfffffff8); // vector count (in chars)
9694 jccb(Assembler::zero, copy_tail);
9695 }
9696
9697 // vectored inflation
9698 lea(src, Address(src, len, Address::times_1));
9699 lea(dst, Address(dst, len, Address::times_2));
9700 negptr(len);
9701
9702 if (UseAVX > 1) {
9703 bind(copy_16_loop);
9704 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9705 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9706 addptr(len, 16);
9707 jcc(Assembler::notZero, copy_16_loop);
9708
9709 bind(below_threshold);
9710 bind(copy_new_tail);
9711 movl(len, tmp2);
9712 andl(tmp2, 0x00000007);
9713 andl(len, 0xFFFFFFF8);
9714 jccb(Assembler::zero, copy_tail);
9715
9716 pmovzxbw(tmp1, Address(src, 0));
9717 movdqu(Address(dst, 0), tmp1);
9718 addptr(src, 8);
9719 addptr(dst, 2 * 8);
9720
9721 jmp(copy_tail, true);
9722 }
9723
9724 // inflate 8 chars per iter
9725 bind(copy_8_loop);
9726 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9727 movdqu(Address(dst, len, Address::times_2), tmp1);
9728 addptr(len, 8);
9729 jcc(Assembler::notZero, copy_8_loop);
9730
9731 bind(copy_tail);
9732 movl(len, tmp2);
9733
9734 cmpl(len, 4);
9735 jccb(Assembler::less, copy_bytes);
9736
9737 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9738 pmovzxbw(tmp1, tmp1);
9739 movq(Address(dst, 0), tmp1);
9740 subptr(len, 4);
9741 addptr(src, 4);
9742 addptr(dst, 8);
9743
9744 bind(copy_bytes);
9745 } else {
9746 bind(below_threshold);
9747 }
9748
9749 testl(len, len);
9750 jccb(Assembler::zero, done);
9751 lea(src, Address(src, len, Address::times_1));
9752 lea(dst, Address(dst, len, Address::times_2));
9753 negptr(len);
9754
9755 // inflate 1 char per iter
9756 bind(copy_chars_loop);
9757 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9758 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9759 increment(len);
9760 jcc(Assembler::notZero, copy_chars_loop);
9761
9762 bind(done);
9763 }
9764
9765 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
9766 switch(type) {
9767 case T_BYTE:
9768 case T_BOOLEAN:
9769 evmovdqub(dst, kmask, src, merge, vector_len);
9770 break;
9771 case T_CHAR:
9772 case T_SHORT:
9773 evmovdquw(dst, kmask, src, merge, vector_len);
9774 break;
9775 case T_INT:
9776 case T_FLOAT:
9777 evmovdqul(dst, kmask, src, merge, vector_len);
9778 break;
9779 case T_LONG:
9780 case T_DOUBLE:
9781 evmovdquq(dst, kmask, src, merge, vector_len);
9782 break;
9783 default:
9784 fatal("Unexpected type argument %s", type2name(type));
9785 break;
9786 }
9787 }
9788
9789
9790 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9791 switch(type) {
9792 case T_BYTE:
9793 case T_BOOLEAN:
9794 evmovdqub(dst, kmask, src, merge, vector_len);
9795 break;
9796 case T_CHAR:
9797 case T_SHORT:
9798 evmovdquw(dst, kmask, src, merge, vector_len);
9799 break;
9800 case T_INT:
9801 case T_FLOAT:
9802 evmovdqul(dst, kmask, src, merge, vector_len);
9803 break;
9804 case T_LONG:
9805 case T_DOUBLE:
9806 evmovdquq(dst, kmask, src, merge, vector_len);
9807 break;
9808 default:
9809 fatal("Unexpected type argument %s", type2name(type));
9810 break;
9811 }
9812 }
9813
9814 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9815 switch(type) {
9816 case T_BYTE:
9817 case T_BOOLEAN:
9818 evmovdqub(dst, kmask, src, merge, vector_len);
9819 break;
9820 case T_CHAR:
9821 case T_SHORT:
9822 evmovdquw(dst, kmask, src, merge, vector_len);
9823 break;
9824 case T_INT:
9825 case T_FLOAT:
9826 evmovdqul(dst, kmask, src, merge, vector_len);
9827 break;
9828 case T_LONG:
9829 case T_DOUBLE:
9830 evmovdquq(dst, kmask, src, merge, vector_len);
9831 break;
9832 default:
9833 fatal("Unexpected type argument %s", type2name(type));
9834 break;
9835 }
9836 }
9837
9838 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9839 switch(masklen) {
9840 case 2:
9841 knotbl(dst, src);
9842 movl(rtmp, 3);
9843 kmovbl(ktmp, rtmp);
9844 kandbl(dst, ktmp, dst);
9845 break;
9846 case 4:
9847 knotbl(dst, src);
9848 movl(rtmp, 15);
9849 kmovbl(ktmp, rtmp);
9850 kandbl(dst, ktmp, dst);
9851 break;
9852 case 8:
9853 knotbl(dst, src);
9854 break;
9855 case 16:
9856 knotwl(dst, src);
9857 break;
9858 case 32:
9859 knotdl(dst, src);
9860 break;
9861 case 64:
9862 knotql(dst, src);
9863 break;
9864 default:
9865 fatal("Unexpected vector length %d", masklen);
9866 break;
9867 }
9868 }
9869
9870 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9871 switch(type) {
9872 case T_BOOLEAN:
9873 case T_BYTE:
9874 kandbl(dst, src1, src2);
9875 break;
9876 case T_CHAR:
9877 case T_SHORT:
9878 kandwl(dst, src1, src2);
9879 break;
9880 case T_INT:
9881 case T_FLOAT:
9882 kanddl(dst, src1, src2);
9883 break;
9884 case T_LONG:
9885 case T_DOUBLE:
9886 kandql(dst, src1, src2);
9887 break;
9888 default:
9889 fatal("Unexpected type argument %s", type2name(type));
9890 break;
9891 }
9892 }
9893
9894 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9895 switch(type) {
9896 case T_BOOLEAN:
9897 case T_BYTE:
9898 korbl(dst, src1, src2);
9899 break;
9900 case T_CHAR:
9901 case T_SHORT:
9902 korwl(dst, src1, src2);
9903 break;
9904 case T_INT:
9905 case T_FLOAT:
9906 kordl(dst, src1, src2);
9907 break;
9908 case T_LONG:
9909 case T_DOUBLE:
9910 korql(dst, src1, src2);
9911 break;
9912 default:
9913 fatal("Unexpected type argument %s", type2name(type));
9914 break;
9915 }
9916 }
9917
9918 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9919 switch(type) {
9920 case T_BOOLEAN:
9921 case T_BYTE:
9922 kxorbl(dst, src1, src2);
9923 break;
9924 case T_CHAR:
9925 case T_SHORT:
9926 kxorwl(dst, src1, src2);
9927 break;
9928 case T_INT:
9929 case T_FLOAT:
9930 kxordl(dst, src1, src2);
9931 break;
9932 case T_LONG:
9933 case T_DOUBLE:
9934 kxorql(dst, src1, src2);
9935 break;
9936 default:
9937 fatal("Unexpected type argument %s", type2name(type));
9938 break;
9939 }
9940 }
9941
9942 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9943 switch(type) {
9944 case T_BOOLEAN:
9945 case T_BYTE:
9946 evpermb(dst, mask, nds, src, merge, vector_len); break;
9947 case T_CHAR:
9948 case T_SHORT:
9949 evpermw(dst, mask, nds, src, merge, vector_len); break;
9950 case T_INT:
9951 case T_FLOAT:
9952 evpermd(dst, mask, nds, src, merge, vector_len); break;
9953 case T_LONG:
9954 case T_DOUBLE:
9955 evpermq(dst, mask, nds, src, merge, vector_len); break;
9956 default:
9957 fatal("Unexpected type argument %s", type2name(type)); break;
9958 }
9959 }
9960
9961 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9962 switch(type) {
9963 case T_BOOLEAN:
9964 case T_BYTE:
9965 evpermb(dst, mask, nds, src, merge, vector_len); break;
9966 case T_CHAR:
9967 case T_SHORT:
9968 evpermw(dst, mask, nds, src, merge, vector_len); break;
9969 case T_INT:
9970 case T_FLOAT:
9971 evpermd(dst, mask, nds, src, merge, vector_len); break;
9972 case T_LONG:
9973 case T_DOUBLE:
9974 evpermq(dst, mask, nds, src, merge, vector_len); break;
9975 default:
9976 fatal("Unexpected type argument %s", type2name(type)); break;
9977 }
9978 }
9979
9980 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9981 switch(type) {
9982 case T_BYTE:
9983 evpminub(dst, mask, nds, src, merge, vector_len); break;
9984 case T_SHORT:
9985 evpminuw(dst, mask, nds, src, merge, vector_len); break;
9986 case T_INT:
9987 evpminud(dst, mask, nds, src, merge, vector_len); break;
9988 case T_LONG:
9989 evpminuq(dst, mask, nds, src, merge, vector_len); break;
9990 default:
9991 fatal("Unexpected type argument %s", type2name(type)); break;
9992 }
9993 }
9994
9995 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9996 switch(type) {
9997 case T_BYTE:
9998 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
9999 case T_SHORT:
10000 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
10001 case T_INT:
10002 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
10003 case T_LONG:
10004 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
10005 default:
10006 fatal("Unexpected type argument %s", type2name(type)); break;
10007 }
10008 }
10009
10010 void MacroAssembler::evpminu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10011 switch(type) {
10012 case T_BYTE:
10013 evpminub(dst, mask, nds, src, merge, vector_len); break;
10014 case T_SHORT:
10015 evpminuw(dst, mask, nds, src, merge, vector_len); break;
10016 case T_INT:
10017 evpminud(dst, mask, nds, src, merge, vector_len); break;
10018 case T_LONG:
10019 evpminuq(dst, mask, nds, src, merge, vector_len); break;
10020 default:
10021 fatal("Unexpected type argument %s", type2name(type)); break;
10022 }
10023 }
10024
10025 void MacroAssembler::evpmaxu(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10026 switch(type) {
10027 case T_BYTE:
10028 evpmaxub(dst, mask, nds, src, merge, vector_len); break;
10029 case T_SHORT:
10030 evpmaxuw(dst, mask, nds, src, merge, vector_len); break;
10031 case T_INT:
10032 evpmaxud(dst, mask, nds, src, merge, vector_len); break;
10033 case T_LONG:
10034 evpmaxuq(dst, mask, nds, src, merge, vector_len); break;
10035 default:
10036 fatal("Unexpected type argument %s", type2name(type)); break;
10037 }
10038 }
10039
10040 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10041 switch(type) {
10042 case T_BYTE:
10043 evpminsb(dst, mask, nds, src, merge, vector_len); break;
10044 case T_SHORT:
10045 evpminsw(dst, mask, nds, src, merge, vector_len); break;
10046 case T_INT:
10047 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10048 case T_LONG:
10049 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10050 default:
10051 fatal("Unexpected type argument %s", type2name(type)); break;
10052 }
10053 }
10054
10055 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10056 switch(type) {
10057 case T_BYTE:
10058 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10059 case T_SHORT:
10060 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10061 case T_INT:
10062 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10063 case T_LONG:
10064 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10065 default:
10066 fatal("Unexpected type argument %s", type2name(type)); break;
10067 }
10068 }
10069
10070 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10071 switch(type) {
10072 case T_BYTE:
10073 evpminsb(dst, mask, nds, src, merge, vector_len); break;
10074 case T_SHORT:
10075 evpminsw(dst, mask, nds, src, merge, vector_len); break;
10076 case T_INT:
10077 evpminsd(dst, mask, nds, src, merge, vector_len); break;
10078 case T_LONG:
10079 evpminsq(dst, mask, nds, src, merge, vector_len); break;
10080 default:
10081 fatal("Unexpected type argument %s", type2name(type)); break;
10082 }
10083 }
10084
10085 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10086 switch(type) {
10087 case T_BYTE:
10088 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
10089 case T_SHORT:
10090 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
10091 case T_INT:
10092 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
10093 case T_LONG:
10094 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
10095 default:
10096 fatal("Unexpected type argument %s", type2name(type)); break;
10097 }
10098 }
10099
10100 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10101 switch(type) {
10102 case T_INT:
10103 evpxord(dst, mask, nds, src, merge, vector_len); break;
10104 case T_LONG:
10105 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10106 default:
10107 fatal("Unexpected type argument %s", type2name(type)); break;
10108 }
10109 }
10110
10111 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10112 switch(type) {
10113 case T_INT:
10114 evpxord(dst, mask, nds, src, merge, vector_len); break;
10115 case T_LONG:
10116 evpxorq(dst, mask, nds, src, merge, vector_len); break;
10117 default:
10118 fatal("Unexpected type argument %s", type2name(type)); break;
10119 }
10120 }
10121
10122 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10123 switch(type) {
10124 case T_INT:
10125 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10126 case T_LONG:
10127 evporq(dst, mask, nds, src, merge, vector_len); break;
10128 default:
10129 fatal("Unexpected type argument %s", type2name(type)); break;
10130 }
10131 }
10132
10133 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10134 switch(type) {
10135 case T_INT:
10136 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
10137 case T_LONG:
10138 evporq(dst, mask, nds, src, merge, vector_len); break;
10139 default:
10140 fatal("Unexpected type argument %s", type2name(type)); break;
10141 }
10142 }
10143
10144 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10145 switch(type) {
10146 case T_INT:
10147 evpandd(dst, mask, nds, src, merge, vector_len); break;
10148 case T_LONG:
10149 evpandq(dst, mask, nds, src, merge, vector_len); break;
10150 default:
10151 fatal("Unexpected type argument %s", type2name(type)); break;
10152 }
10153 }
10154
10155 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10156 switch(type) {
10157 case T_INT:
10158 evpandd(dst, mask, nds, src, merge, vector_len); break;
10159 case T_LONG:
10160 evpandq(dst, mask, nds, src, merge, vector_len); break;
10161 default:
10162 fatal("Unexpected type argument %s", type2name(type)); break;
10163 }
10164 }
10165
10166 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
10167 switch(masklen) {
10168 case 8:
10169 kortestbl(src1, src2);
10170 break;
10171 case 16:
10172 kortestwl(src1, src2);
10173 break;
10174 case 32:
10175 kortestdl(src1, src2);
10176 break;
10177 case 64:
10178 kortestql(src1, src2);
10179 break;
10180 default:
10181 fatal("Unexpected mask length %d", masklen);
10182 break;
10183 }
10184 }
10185
10186
10187 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
10188 switch(masklen) {
10189 case 8:
10190 ktestbl(src1, src2);
10191 break;
10192 case 16:
10193 ktestwl(src1, src2);
10194 break;
10195 case 32:
10196 ktestdl(src1, src2);
10197 break;
10198 case 64:
10199 ktestql(src1, src2);
10200 break;
10201 default:
10202 fatal("Unexpected mask length %d", masklen);
10203 break;
10204 }
10205 }
10206
10207 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10208 switch(type) {
10209 case T_INT:
10210 evprold(dst, mask, src, shift, merge, vlen_enc); break;
10211 case T_LONG:
10212 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
10213 default:
10214 fatal("Unexpected type argument %s", type2name(type)); break;
10215 break;
10216 }
10217 }
10218
10219 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
10220 switch(type) {
10221 case T_INT:
10222 evprord(dst, mask, src, shift, merge, vlen_enc); break;
10223 case T_LONG:
10224 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
10225 default:
10226 fatal("Unexpected type argument %s", type2name(type)); break;
10227 }
10228 }
10229
10230 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10231 switch(type) {
10232 case T_INT:
10233 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
10234 case T_LONG:
10235 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
10236 default:
10237 fatal("Unexpected type argument %s", type2name(type)); break;
10238 }
10239 }
10240
10241 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
10242 switch(type) {
10243 case T_INT:
10244 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
10245 case T_LONG:
10246 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
10247 default:
10248 fatal("Unexpected type argument %s", type2name(type)); break;
10249 }
10250 }
10251
10252 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10253 assert(rscratch != noreg || always_reachable(src), "missing");
10254
10255 if (reachable(src)) {
10256 evpandq(dst, nds, as_Address(src), vector_len);
10257 } else {
10258 lea(rscratch, src);
10259 evpandq(dst, nds, Address(rscratch, 0), vector_len);
10260 }
10261 }
10262
10263 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
10264 assert(rscratch != noreg || always_reachable(src), "missing");
10265
10266 if (reachable(src)) {
10267 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
10268 } else {
10269 lea(rscratch, src);
10270 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
10271 }
10272 }
10273
10274 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10275 assert(rscratch != noreg || always_reachable(src), "missing");
10276
10277 if (reachable(src)) {
10278 evporq(dst, nds, as_Address(src), vector_len);
10279 } else {
10280 lea(rscratch, src);
10281 evporq(dst, nds, Address(rscratch, 0), vector_len);
10282 }
10283 }
10284
10285 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10286 assert(rscratch != noreg || always_reachable(src), "missing");
10287
10288 if (reachable(src)) {
10289 vpshufb(dst, nds, as_Address(src), vector_len);
10290 } else {
10291 lea(rscratch, src);
10292 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
10293 }
10294 }
10295
10296 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
10297 assert(rscratch != noreg || always_reachable(src), "missing");
10298
10299 if (reachable(src)) {
10300 Assembler::vpor(dst, nds, as_Address(src), vector_len);
10301 } else {
10302 lea(rscratch, src);
10303 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
10304 }
10305 }
10306
10307 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
10308 assert(rscratch != noreg || always_reachable(src3), "missing");
10309
10310 if (reachable(src3)) {
10311 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
10312 } else {
10313 lea(rscratch, src3);
10314 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
10315 }
10316 }
10317
10318 #if COMPILER2_OR_JVMCI
10319
10320 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
10321 Register length, Register temp, int vec_enc) {
10322 // Computing mask for predicated vector store.
10323 movptr(temp, -1);
10324 bzhiq(temp, temp, length);
10325 kmov(mask, temp);
10326 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
10327 }
10328
10329 // Set memory operation for length "less than" 64 bytes.
10330 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
10331 XMMRegister xmm, KRegister mask, Register length,
10332 Register temp, bool use64byteVector) {
10333 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10334 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10335 if (!use64byteVector) {
10336 fill32(dst, disp, xmm);
10337 subptr(length, 32 >> shift);
10338 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
10339 } else {
10340 assert(MaxVectorSize == 64, "vector length != 64");
10341 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
10342 }
10343 }
10344
10345
10346 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
10347 XMMRegister xmm, KRegister mask, Register length,
10348 Register temp) {
10349 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10350 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
10351 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
10352 }
10353
10354
10355 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
10356 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10357 vmovdqu(dst, xmm);
10358 }
10359
10360 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
10361 fill32(Address(dst, disp), xmm);
10362 }
10363
10364 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
10365 assert(MaxVectorSize >= 32, "vector length should be >= 32");
10366 if (!use64byteVector) {
10367 fill32(dst, xmm);
10368 fill32(dst.plus_disp(32), xmm);
10369 } else {
10370 evmovdquq(dst, xmm, Assembler::AVX_512bit);
10371 }
10372 }
10373
10374 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
10375 fill64(Address(dst, disp), xmm, use64byteVector);
10376 }
10377
10378 #ifdef _LP64
10379 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
10380 Register count, Register rtmp, XMMRegister xtmp) {
10381 Label L_exit;
10382 Label L_fill_start;
10383 Label L_fill_64_bytes;
10384 Label L_fill_96_bytes;
10385 Label L_fill_128_bytes;
10386 Label L_fill_128_bytes_loop;
10387 Label L_fill_128_loop_header;
10388 Label L_fill_128_bytes_loop_header;
10389 Label L_fill_128_bytes_loop_pre_header;
10390 Label L_fill_zmm_sequence;
10391
10392 int shift = -1;
10393 int avx3threshold = VM_Version::avx3_threshold();
10394 switch(type) {
10395 case T_BYTE: shift = 0;
10396 break;
10397 case T_SHORT: shift = 1;
10398 break;
10399 case T_INT: shift = 2;
10400 break;
10401 /* Uncomment when LONG fill stubs are supported.
10402 case T_LONG: shift = 3;
10403 break;
10404 */
10405 default:
10406 fatal("Unhandled type: %s\n", type2name(type));
10407 }
10408
10409 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
10410
10411 if (MaxVectorSize == 64) {
10412 cmpq(count, avx3threshold >> shift);
10413 jcc(Assembler::greater, L_fill_zmm_sequence);
10414 }
10415
10416 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
10417
10418 bind(L_fill_start);
10419
10420 cmpq(count, 32 >> shift);
10421 jccb(Assembler::greater, L_fill_64_bytes);
10422 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
10423 jmp(L_exit);
10424
10425 bind(L_fill_64_bytes);
10426 cmpq(count, 64 >> shift);
10427 jccb(Assembler::greater, L_fill_96_bytes);
10428 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
10429 jmp(L_exit);
10430
10431 bind(L_fill_96_bytes);
10432 cmpq(count, 96 >> shift);
10433 jccb(Assembler::greater, L_fill_128_bytes);
10434 fill64(to, 0, xtmp);
10435 subq(count, 64 >> shift);
10436 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
10437 jmp(L_exit);
10438
10439 bind(L_fill_128_bytes);
10440 cmpq(count, 128 >> shift);
10441 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
10442 fill64(to, 0, xtmp);
10443 fill32(to, 64, xtmp);
10444 subq(count, 96 >> shift);
10445 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
10446 jmp(L_exit);
10447
10448 bind(L_fill_128_bytes_loop_pre_header);
10449 {
10450 mov(rtmp, to);
10451 andq(rtmp, 31);
10452 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
10453 negq(rtmp);
10454 addq(rtmp, 32);
10455 mov64(r8, -1L);
10456 bzhiq(r8, r8, rtmp);
10457 kmovql(k2, r8);
10458 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
10459 addq(to, rtmp);
10460 shrq(rtmp, shift);
10461 subq(count, rtmp);
10462 }
10463
10464 cmpq(count, 128 >> shift);
10465 jcc(Assembler::less, L_fill_start);
10466
10467 bind(L_fill_128_bytes_loop_header);
10468 subq(count, 128 >> shift);
10469
10470 align32();
10471 bind(L_fill_128_bytes_loop);
10472 fill64(to, 0, xtmp);
10473 fill64(to, 64, xtmp);
10474 addq(to, 128);
10475 subq(count, 128 >> shift);
10476 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
10477
10478 addq(count, 128 >> shift);
10479 jcc(Assembler::zero, L_exit);
10480 jmp(L_fill_start);
10481 }
10482
10483 if (MaxVectorSize == 64) {
10484 // Sequence using 64 byte ZMM register.
10485 Label L_fill_128_bytes_zmm;
10486 Label L_fill_192_bytes_zmm;
10487 Label L_fill_192_bytes_loop_zmm;
10488 Label L_fill_192_bytes_loop_header_zmm;
10489 Label L_fill_192_bytes_loop_pre_header_zmm;
10490 Label L_fill_start_zmm_sequence;
10491
10492 bind(L_fill_zmm_sequence);
10493 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10494
10495 bind(L_fill_start_zmm_sequence);
10496 cmpq(count, 64 >> shift);
10497 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10498 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10499 jmp(L_exit);
10500
10501 bind(L_fill_128_bytes_zmm);
10502 cmpq(count, 128 >> shift);
10503 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10504 fill64(to, 0, xtmp, true);
10505 subq(count, 64 >> shift);
10506 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10507 jmp(L_exit);
10508
10509 bind(L_fill_192_bytes_zmm);
10510 cmpq(count, 192 >> shift);
10511 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10512 fill64(to, 0, xtmp, true);
10513 fill64(to, 64, xtmp, true);
10514 subq(count, 128 >> shift);
10515 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10516 jmp(L_exit);
10517
10518 bind(L_fill_192_bytes_loop_pre_header_zmm);
10519 {
10520 movq(rtmp, to);
10521 andq(rtmp, 63);
10522 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10523 negq(rtmp);
10524 addq(rtmp, 64);
10525 mov64(r8, -1L);
10526 bzhiq(r8, r8, rtmp);
10527 kmovql(k2, r8);
10528 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10529 addq(to, rtmp);
10530 shrq(rtmp, shift);
10531 subq(count, rtmp);
10532 }
10533
10534 cmpq(count, 192 >> shift);
10535 jcc(Assembler::less, L_fill_start_zmm_sequence);
10536
10537 bind(L_fill_192_bytes_loop_header_zmm);
10538 subq(count, 192 >> shift);
10539
10540 align32();
10541 bind(L_fill_192_bytes_loop_zmm);
10542 fill64(to, 0, xtmp, true);
10543 fill64(to, 64, xtmp, true);
10544 fill64(to, 128, xtmp, true);
10545 addq(to, 192);
10546 subq(count, 192 >> shift);
10547 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10548
10549 addq(count, 192 >> shift);
10550 jcc(Assembler::zero, L_exit);
10551 jmp(L_fill_start_zmm_sequence);
10552 }
10553 bind(L_exit);
10554 }
10555 #endif
10556 #endif //COMPILER2_OR_JVMCI
10557
10558
10559 #ifdef _LP64
10560 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10561 Label done;
10562 cvttss2sil(dst, src);
10563 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10564 cmpl(dst, 0x80000000); // float_sign_flip
10565 jccb(Assembler::notEqual, done);
10566 subptr(rsp, 8);
10567 movflt(Address(rsp, 0), src);
10568 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10569 pop(dst);
10570 bind(done);
10571 }
10572
10573 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10574 Label done;
10575 cvttsd2sil(dst, src);
10576 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10577 cmpl(dst, 0x80000000); // float_sign_flip
10578 jccb(Assembler::notEqual, done);
10579 subptr(rsp, 8);
10580 movdbl(Address(rsp, 0), src);
10581 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10582 pop(dst);
10583 bind(done);
10584 }
10585
10586 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10587 Label done;
10588 cvttss2siq(dst, src);
10589 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10590 jccb(Assembler::notEqual, done);
10591 subptr(rsp, 8);
10592 movflt(Address(rsp, 0), src);
10593 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10594 pop(dst);
10595 bind(done);
10596 }
10597
10598 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10599 // Following code is line by line assembly translation rounding algorithm.
10600 // Please refer to java.lang.Math.round(float) algorithm for details.
10601 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10602 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10603 const int32_t FloatConsts_EXP_BIAS = 127;
10604 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10605 const int32_t MINUS_32 = 0xFFFFFFE0;
10606 Label L_special_case, L_block1, L_exit;
10607 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10608 movdl(dst, src);
10609 andl(dst, rtmp);
10610 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10611 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10612 subl(rtmp, dst);
10613 movl(rcx, rtmp);
10614 movl(dst, MINUS_32);
10615 testl(rtmp, dst);
10616 jccb(Assembler::notEqual, L_special_case);
10617 movdl(dst, src);
10618 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10619 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10620 movdl(rtmp, src);
10621 testl(rtmp, rtmp);
10622 jccb(Assembler::greaterEqual, L_block1);
10623 negl(dst);
10624 bind(L_block1);
10625 sarl(dst);
10626 addl(dst, 0x1);
10627 sarl(dst, 0x1);
10628 jmp(L_exit);
10629 bind(L_special_case);
10630 convert_f2i(dst, src);
10631 bind(L_exit);
10632 }
10633
10634 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10635 // Following code is line by line assembly translation rounding algorithm.
10636 // Please refer to java.lang.Math.round(double) algorithm for details.
10637 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10638 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10639 const int64_t DoubleConsts_EXP_BIAS = 1023;
10640 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10641 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10642 Label L_special_case, L_block1, L_exit;
10643 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10644 movq(dst, src);
10645 andq(dst, rtmp);
10646 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10647 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10648 subq(rtmp, dst);
10649 movq(rcx, rtmp);
10650 mov64(dst, MINUS_64);
10651 testq(rtmp, dst);
10652 jccb(Assembler::notEqual, L_special_case);
10653 movq(dst, src);
10654 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10655 andq(dst, rtmp);
10656 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10657 orq(dst, rtmp);
10658 movq(rtmp, src);
10659 testq(rtmp, rtmp);
10660 jccb(Assembler::greaterEqual, L_block1);
10661 negq(dst);
10662 bind(L_block1);
10663 sarq(dst);
10664 addq(dst, 0x1);
10665 sarq(dst, 0x1);
10666 jmp(L_exit);
10667 bind(L_special_case);
10668 convert_d2l(dst, src);
10669 bind(L_exit);
10670 }
10671
10672 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10673 Label done;
10674 cvttsd2siq(dst, src);
10675 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10676 jccb(Assembler::notEqual, done);
10677 subptr(rsp, 8);
10678 movdbl(Address(rsp, 0), src);
10679 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10680 pop(dst);
10681 bind(done);
10682 }
10683
10684 void MacroAssembler::cache_wb(Address line)
10685 {
10686 // 64 bit cpus always support clflush
10687 assert(VM_Version::supports_clflush(), "clflush should be available");
10688 bool optimized = VM_Version::supports_clflushopt();
10689 bool no_evict = VM_Version::supports_clwb();
10690
10691 // prefer clwb (writeback without evict) otherwise
10692 // prefer clflushopt (potentially parallel writeback with evict)
10693 // otherwise fallback on clflush (serial writeback with evict)
10694
10695 if (optimized) {
10696 if (no_evict) {
10697 clwb(line);
10698 } else {
10699 clflushopt(line);
10700 }
10701 } else {
10702 // no need for fence when using CLFLUSH
10703 clflush(line);
10704 }
10705 }
10706
10707 void MacroAssembler::cache_wbsync(bool is_pre)
10708 {
10709 assert(VM_Version::supports_clflush(), "clflush should be available");
10710 bool optimized = VM_Version::supports_clflushopt();
10711 bool no_evict = VM_Version::supports_clwb();
10712
10713 // pick the correct implementation
10714
10715 if (!is_pre && (optimized || no_evict)) {
10716 // need an sfence for post flush when using clflushopt or clwb
10717 // otherwise no no need for any synchroniaztion
10718
10719 sfence();
10720 }
10721 }
10722
10723 #endif // _LP64
10724
10725 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10726 switch (cond) {
10727 // Note some conditions are synonyms for others
10728 case Assembler::zero: return Assembler::notZero;
10729 case Assembler::notZero: return Assembler::zero;
10730 case Assembler::less: return Assembler::greaterEqual;
10731 case Assembler::lessEqual: return Assembler::greater;
10732 case Assembler::greater: return Assembler::lessEqual;
10733 case Assembler::greaterEqual: return Assembler::less;
10734 case Assembler::below: return Assembler::aboveEqual;
10735 case Assembler::belowEqual: return Assembler::above;
10736 case Assembler::above: return Assembler::belowEqual;
10737 case Assembler::aboveEqual: return Assembler::below;
10738 case Assembler::overflow: return Assembler::noOverflow;
10739 case Assembler::noOverflow: return Assembler::overflow;
10740 case Assembler::negative: return Assembler::positive;
10741 case Assembler::positive: return Assembler::negative;
10742 case Assembler::parity: return Assembler::noParity;
10743 case Assembler::noParity: return Assembler::parity;
10744 }
10745 ShouldNotReachHere(); return Assembler::overflow;
10746 }
10747
10748 // This is simply a call to Thread::current()
10749 void MacroAssembler::get_thread(Register thread) {
10750 if (thread != rax) {
10751 push(rax);
10752 }
10753 LP64_ONLY(push(rdi);)
10754 LP64_ONLY(push(rsi);)
10755 push(rdx);
10756 push(rcx);
10757 #ifdef _LP64
10758 push(r8);
10759 push(r9);
10760 push(r10);
10761 push(r11);
10762 #endif
10763
10764 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10765
10766 #ifdef _LP64
10767 pop(r11);
10768 pop(r10);
10769 pop(r9);
10770 pop(r8);
10771 #endif
10772 pop(rcx);
10773 pop(rdx);
10774 LP64_ONLY(pop(rsi);)
10775 LP64_ONLY(pop(rdi);)
10776 if (thread != rax) {
10777 mov(thread, rax);
10778 pop(rax);
10779 }
10780 }
10781
10782 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10783 Label L_stack_ok;
10784 if (bias == 0) {
10785 testptr(sp, 2 * wordSize - 1);
10786 } else {
10787 // lea(tmp, Address(rsp, bias);
10788 mov(tmp, sp);
10789 addptr(tmp, bias);
10790 testptr(tmp, 2 * wordSize - 1);
10791 }
10792 jcc(Assembler::equal, L_stack_ok);
10793 block_comment(msg);
10794 stop(msg);
10795 bind(L_stack_ok);
10796 }
10797
10798 // Implements lightweight-locking.
10799 //
10800 // obj: the object to be locked
10801 // reg_rax: rax
10802 // thread: the thread which attempts to lock obj
10803 // tmp: a temporary register
10804 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10805 assert(reg_rax == rax, "");
10806 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10807
10808 Label push;
10809 const Register top = tmp;
10810
10811 // Preload the markWord. It is important that this is the first
10812 // instruction emitted as it is part of C1's null check semantics.
10813 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10814
10815 if (UseObjectMonitorTable) {
10816 // Clear cache in case fast locking succeeds.
10817 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10818 }
10819
10820 // Load top.
10821 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10822
10823 // Check if the lock-stack is full.
10824 cmpl(top, LockStack::end_offset());
10825 jcc(Assembler::greaterEqual, slow);
10826
10827 // Check for recursion.
10828 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10829 jcc(Assembler::equal, push);
10830
10831 // Check header for monitor (0b10).
10832 testptr(reg_rax, markWord::monitor_value);
10833 jcc(Assembler::notZero, slow);
10834
10835 // Try to lock. Transition lock bits 0b01 => 0b00
10836 movptr(tmp, reg_rax);
10837 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10838 orptr(reg_rax, markWord::unlocked_value);
10839 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10840 jcc(Assembler::notEqual, slow);
10841
10842 // Restore top, CAS clobbers register.
10843 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10844
10845 bind(push);
10846 // After successful lock, push object on lock-stack.
10847 movptr(Address(thread, top), obj);
10848 incrementl(top, oopSize);
10849 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10850 }
10851
10852 // Implements lightweight-unlocking.
10853 //
10854 // obj: the object to be unlocked
10855 // reg_rax: rax
10856 // thread: the thread
10857 // tmp: a temporary register
10858 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10859 assert(reg_rax == rax, "");
10860 assert_different_registers(obj, reg_rax, thread, tmp);
10861
10862 Label unlocked, push_and_slow;
10863 const Register top = tmp;
10864
10865 // Check if obj is top of lock-stack.
10866 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10867 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10868 jcc(Assembler::notEqual, slow);
10869
10870 // Pop lock-stack.
10871 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10872 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10873
10874 // Check if recursive.
10875 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10876 jcc(Assembler::equal, unlocked);
10877
10878 // Not recursive. Check header for monitor (0b10).
10879 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10880 testptr(reg_rax, markWord::monitor_value);
10881 jcc(Assembler::notZero, push_and_slow);
10882
10883 #ifdef ASSERT
10884 // Check header not unlocked (0b01).
10885 Label not_unlocked;
10886 testptr(reg_rax, markWord::unlocked_value);
10887 jcc(Assembler::zero, not_unlocked);
10888 stop("lightweight_unlock already unlocked");
10889 bind(not_unlocked);
10890 #endif
10891
10892 // Try to unlock. Transition lock bits 0b00 => 0b01
10893 movptr(tmp, reg_rax);
10894 orptr(tmp, markWord::unlocked_value);
10895 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10896 jcc(Assembler::equal, unlocked);
10897
10898 bind(push_and_slow);
10899 // Restore lock-stack and handle the unlock in runtime.
10900 #ifdef ASSERT
10901 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10902 movptr(Address(thread, top), obj);
10903 #endif
10904 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10905 jmp(slow);
10906
10907 bind(unlocked);
10908 }
10909
10910 #ifdef _LP64
10911 // Saves legacy GPRs state on stack.
10912 void MacroAssembler::save_legacy_gprs() {
10913 subq(rsp, 16 * wordSize);
10914 movq(Address(rsp, 15 * wordSize), rax);
10915 movq(Address(rsp, 14 * wordSize), rcx);
10916 movq(Address(rsp, 13 * wordSize), rdx);
10917 movq(Address(rsp, 12 * wordSize), rbx);
10918 movq(Address(rsp, 10 * wordSize), rbp);
10919 movq(Address(rsp, 9 * wordSize), rsi);
10920 movq(Address(rsp, 8 * wordSize), rdi);
10921 movq(Address(rsp, 7 * wordSize), r8);
10922 movq(Address(rsp, 6 * wordSize), r9);
10923 movq(Address(rsp, 5 * wordSize), r10);
10924 movq(Address(rsp, 4 * wordSize), r11);
10925 movq(Address(rsp, 3 * wordSize), r12);
10926 movq(Address(rsp, 2 * wordSize), r13);
10927 movq(Address(rsp, wordSize), r14);
10928 movq(Address(rsp, 0), r15);
10929 }
10930
10931 // Resotres back legacy GPRs state from stack.
10932 void MacroAssembler::restore_legacy_gprs() {
10933 movq(r15, Address(rsp, 0));
10934 movq(r14, Address(rsp, wordSize));
10935 movq(r13, Address(rsp, 2 * wordSize));
10936 movq(r12, Address(rsp, 3 * wordSize));
10937 movq(r11, Address(rsp, 4 * wordSize));
10938 movq(r10, Address(rsp, 5 * wordSize));
10939 movq(r9, Address(rsp, 6 * wordSize));
10940 movq(r8, Address(rsp, 7 * wordSize));
10941 movq(rdi, Address(rsp, 8 * wordSize));
10942 movq(rsi, Address(rsp, 9 * wordSize));
10943 movq(rbp, Address(rsp, 10 * wordSize));
10944 movq(rbx, Address(rsp, 12 * wordSize));
10945 movq(rdx, Address(rsp, 13 * wordSize));
10946 movq(rcx, Address(rsp, 14 * wordSize));
10947 movq(rax, Address(rsp, 15 * wordSize));
10948 addq(rsp, 16 * wordSize);
10949 }
10950
10951 void MacroAssembler::setcc(Assembler::Condition comparison, Register dst) {
10952 if (VM_Version::supports_apx_f()) {
10953 esetzucc(comparison, dst);
10954 } else {
10955 setb(comparison, dst);
10956 movzbl(dst, dst);
10957 }
10958 }
10959 #endif