1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "code/compiledIC.hpp"
29 #include "compiler/compiler_globals.hpp"
30 #include "compiler/disassembler.hpp"
31 #include "crc32c.h"
32 #include "gc/shared/barrierSet.hpp"
33 #include "gc/shared/barrierSetAssembler.hpp"
34 #include "gc/shared/collectedHeap.inline.hpp"
35 #include "gc/shared/tlab_globals.hpp"
36 #include "interpreter/bytecodeHistogram.hpp"
37 #include "interpreter/interpreter.hpp"
38 #include "jvm.h"
39 #include "memory/resourceArea.hpp"
40 #include "memory/universe.hpp"
41 #include "oops/accessDecorators.hpp"
42 #include "oops/compressedKlass.inline.hpp"
43 #include "oops/compressedOops.inline.hpp"
44 #include "oops/klass.inline.hpp"
45 #include "prims/methodHandles.hpp"
46 #include "runtime/continuation.hpp"
47 #include "runtime/interfaceSupport.inline.hpp"
48 #include "runtime/javaThread.hpp"
49 #include "runtime/jniHandles.hpp"
50 #include "runtime/objectMonitor.hpp"
51 #include "runtime/os.hpp"
52 #include "runtime/safepoint.hpp"
53 #include "runtime/safepointMechanism.hpp"
54 #include "runtime/sharedRuntime.hpp"
55 #include "runtime/stubRoutines.hpp"
56 #include "utilities/checkedCast.hpp"
57 #include "utilities/macros.hpp"
58
59 #ifdef PRODUCT
60 #define BLOCK_COMMENT(str) /* nothing */
61 #define STOP(error) stop(error)
62 #else
63 #define BLOCK_COMMENT(str) block_comment(str)
64 #define STOP(error) block_comment(error); stop(error)
65 #endif
66
67 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
68
69 #ifdef ASSERT
70 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
71 #endif
72
73 static const Assembler::Condition reverse[] = {
74 Assembler::noOverflow /* overflow = 0x0 */ ,
75 Assembler::overflow /* noOverflow = 0x1 */ ,
76 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ ,
77 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ ,
78 Assembler::notZero /* zero = 0x4, equal = 0x4 */ ,
79 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ ,
80 Assembler::above /* belowEqual = 0x6 */ ,
81 Assembler::belowEqual /* above = 0x7 */ ,
82 Assembler::positive /* negative = 0x8 */ ,
83 Assembler::negative /* positive = 0x9 */ ,
84 Assembler::noParity /* parity = 0xa */ ,
85 Assembler::parity /* noParity = 0xb */ ,
86 Assembler::greaterEqual /* less = 0xc */ ,
87 Assembler::less /* greaterEqual = 0xd */ ,
88 Assembler::greater /* lessEqual = 0xe */ ,
89 Assembler::lessEqual /* greater = 0xf, */
90
91 };
92
93
94 // Implementation of MacroAssembler
95
96 // First all the versions that have distinct versions depending on 32/64 bit
97 // Unless the difference is trivial (1 line or so).
98
99 #ifndef _LP64
100
101 // 32bit versions
102
103 Address MacroAssembler::as_Address(AddressLiteral adr) {
104 return Address(adr.target(), adr.rspec());
105 }
106
107 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
108 assert(rscratch == noreg, "");
109 return Address::make_array(adr);
110 }
111
112 void MacroAssembler::call_VM_leaf_base(address entry_point,
113 int number_of_arguments) {
114 call(RuntimeAddress(entry_point));
115 increment(rsp, number_of_arguments * wordSize);
116 }
117
118 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
119 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
120 }
121
122
123 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
124 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
125 }
126
127 void MacroAssembler::cmpoop(Address src1, jobject obj) {
128 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
129 }
130
131 void MacroAssembler::cmpoop(Register src1, jobject obj, Register rscratch) {
132 assert(rscratch == noreg, "redundant");
133 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
134 }
135
136 void MacroAssembler::extend_sign(Register hi, Register lo) {
137 // According to Intel Doc. AP-526, "Integer Divide", p.18.
138 if (VM_Version::is_P6() && hi == rdx && lo == rax) {
139 cdql();
140 } else {
141 movl(hi, lo);
142 sarl(hi, 31);
143 }
144 }
145
146 void MacroAssembler::jC2(Register tmp, Label& L) {
147 // set parity bit if FPU flag C2 is set (via rax)
148 save_rax(tmp);
149 fwait(); fnstsw_ax();
150 sahf();
151 restore_rax(tmp);
152 // branch
153 jcc(Assembler::parity, L);
154 }
155
156 void MacroAssembler::jnC2(Register tmp, Label& L) {
157 // set parity bit if FPU flag C2 is set (via rax)
158 save_rax(tmp);
159 fwait(); fnstsw_ax();
160 sahf();
161 restore_rax(tmp);
162 // branch
163 jcc(Assembler::noParity, L);
164 }
165
166 // 32bit can do a case table jump in one instruction but we no longer allow the base
167 // to be installed in the Address class
168 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
169 assert(rscratch == noreg, "not needed");
170 jmp(as_Address(entry, noreg));
171 }
172
173 // Note: y_lo will be destroyed
174 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
175 // Long compare for Java (semantics as described in JVM spec.)
176 Label high, low, done;
177
178 cmpl(x_hi, y_hi);
179 jcc(Assembler::less, low);
180 jcc(Assembler::greater, high);
181 // x_hi is the return register
182 xorl(x_hi, x_hi);
183 cmpl(x_lo, y_lo);
184 jcc(Assembler::below, low);
185 jcc(Assembler::equal, done);
186
187 bind(high);
188 xorl(x_hi, x_hi);
189 increment(x_hi);
190 jmp(done);
191
192 bind(low);
193 xorl(x_hi, x_hi);
194 decrementl(x_hi);
195
196 bind(done);
197 }
198
199 void MacroAssembler::lea(Register dst, AddressLiteral src) {
200 mov_literal32(dst, (int32_t)src.target(), src.rspec());
201 }
202
203 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
204 assert(rscratch == noreg, "not needed");
205
206 // leal(dst, as_Address(adr));
207 // see note in movl as to why we must use a move
208 mov_literal32(dst, (int32_t)adr.target(), adr.rspec());
209 }
210
211 void MacroAssembler::leave() {
212 mov(rsp, rbp);
213 pop(rbp);
214 }
215
216 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
217 // Multiplication of two Java long values stored on the stack
218 // as illustrated below. Result is in rdx:rax.
219 //
220 // rsp ---> [ ?? ] \ \
221 // .... | y_rsp_offset |
222 // [ y_lo ] / (in bytes) | x_rsp_offset
223 // [ y_hi ] | (in bytes)
224 // .... |
225 // [ x_lo ] /
226 // [ x_hi ]
227 // ....
228 //
229 // Basic idea: lo(result) = lo(x_lo * y_lo)
230 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
231 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
232 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
233 Label quick;
234 // load x_hi, y_hi and check if quick
235 // multiplication is possible
236 movl(rbx, x_hi);
237 movl(rcx, y_hi);
238 movl(rax, rbx);
239 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0
240 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply
241 // do full multiplication
242 // 1st step
243 mull(y_lo); // x_hi * y_lo
244 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx,
245 // 2nd step
246 movl(rax, x_lo);
247 mull(rcx); // x_lo * y_hi
248 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx,
249 // 3rd step
250 bind(quick); // note: rbx, = 0 if quick multiply!
251 movl(rax, x_lo);
252 mull(y_lo); // x_lo * y_lo
253 addl(rdx, rbx); // correct hi(x_lo * y_lo)
254 }
255
256 void MacroAssembler::lneg(Register hi, Register lo) {
257 negl(lo);
258 adcl(hi, 0);
259 negl(hi);
260 }
261
262 void MacroAssembler::lshl(Register hi, Register lo) {
263 // Java shift left long support (semantics as described in JVM spec., p.305)
264 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
265 // shift value is in rcx !
266 assert(hi != rcx, "must not use rcx");
267 assert(lo != rcx, "must not use rcx");
268 const Register s = rcx; // shift count
269 const int n = BitsPerWord;
270 Label L;
271 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
272 cmpl(s, n); // if (s < n)
273 jcc(Assembler::less, L); // else (s >= n)
274 movl(hi, lo); // x := x << n
275 xorl(lo, lo);
276 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
277 bind(L); // s (mod n) < n
278 shldl(hi, lo); // x := x << s
279 shll(lo);
280 }
281
282
283 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
284 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
285 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
286 assert(hi != rcx, "must not use rcx");
287 assert(lo != rcx, "must not use rcx");
288 const Register s = rcx; // shift count
289 const int n = BitsPerWord;
290 Label L;
291 andl(s, 0x3f); // s := s & 0x3f (s < 0x40)
292 cmpl(s, n); // if (s < n)
293 jcc(Assembler::less, L); // else (s >= n)
294 movl(lo, hi); // x := x >> n
295 if (sign_extension) sarl(hi, 31);
296 else xorl(hi, hi);
297 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
298 bind(L); // s (mod n) < n
299 shrdl(lo, hi); // x := x >> s
300 if (sign_extension) sarl(hi);
301 else shrl(hi);
302 }
303
304 void MacroAssembler::movoop(Register dst, jobject obj) {
305 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
306 }
307
308 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
309 assert(rscratch == noreg, "redundant");
310 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
311 }
312
313 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
314 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
315 }
316
317 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
318 assert(rscratch == noreg, "redundant");
319 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
320 }
321
322 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
323 if (src.is_lval()) {
324 mov_literal32(dst, (intptr_t)src.target(), src.rspec());
325 } else {
326 movl(dst, as_Address(src));
327 }
328 }
329
330 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
331 assert(rscratch == noreg, "redundant");
332 movl(as_Address(dst, noreg), src);
333 }
334
335 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
336 movl(dst, as_Address(src, noreg));
337 }
338
339 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
340 assert(rscratch == noreg, "redundant");
341 movl(dst, src);
342 }
343
344 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
345 assert(rscratch == noreg, "redundant");
346 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
347 }
348
349 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
350 assert(rscratch == noreg, "redundant");
351 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
352 }
353
354 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
355 assert(rscratch == noreg, "redundant");
356 if (src.is_lval()) {
357 push_literal32((int32_t)src.target(), src.rspec());
358 } else {
359 pushl(as_Address(src));
360 }
361 }
362
363 static void pass_arg0(MacroAssembler* masm, Register arg) {
364 masm->push(arg);
365 }
366
367 static void pass_arg1(MacroAssembler* masm, Register arg) {
368 masm->push(arg);
369 }
370
371 static void pass_arg2(MacroAssembler* masm, Register arg) {
372 masm->push(arg);
373 }
374
375 static void pass_arg3(MacroAssembler* masm, Register arg) {
376 masm->push(arg);
377 }
378
379 #ifndef PRODUCT
380 extern "C" void findpc(intptr_t x);
381 #endif
382
383 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
384 // In order to get locks to work, we need to fake a in_VM state
385 JavaThread* thread = JavaThread::current();
386 JavaThreadState saved_state = thread->thread_state();
387 thread->set_thread_state(_thread_in_vm);
388 if (ShowMessageBoxOnError) {
389 JavaThread* thread = JavaThread::current();
390 JavaThreadState saved_state = thread->thread_state();
391 thread->set_thread_state(_thread_in_vm);
392 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
393 ttyLocker ttyl;
394 BytecodeCounter::print();
395 }
396 // To see where a verify_oop failed, get $ebx+40/X for this frame.
397 // This is the value of eip which points to where verify_oop will return.
398 if (os::message_box(msg, "Execution stopped, print registers?")) {
399 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
400 BREAKPOINT;
401 }
402 }
403 fatal("DEBUG MESSAGE: %s", msg);
404 }
405
406 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
407 ttyLocker ttyl;
408 DebuggingContext debugging{};
409 tty->print_cr("eip = 0x%08x", eip);
410 #ifndef PRODUCT
411 if ((WizardMode || Verbose) && PrintMiscellaneous) {
412 tty->cr();
413 findpc(eip);
414 tty->cr();
415 }
416 #endif
417 #define PRINT_REG(rax) \
418 { tty->print("%s = ", #rax); os::print_location(tty, rax); }
419 PRINT_REG(rax);
420 PRINT_REG(rbx);
421 PRINT_REG(rcx);
422 PRINT_REG(rdx);
423 PRINT_REG(rdi);
424 PRINT_REG(rsi);
425 PRINT_REG(rbp);
426 PRINT_REG(rsp);
427 #undef PRINT_REG
428 // Print some words near top of staack.
429 int* dump_sp = (int*) rsp;
430 for (int col1 = 0; col1 < 8; col1++) {
431 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
432 os::print_location(tty, *dump_sp++);
433 }
434 for (int row = 0; row < 16; row++) {
435 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
436 for (int col = 0; col < 8; col++) {
437 tty->print(" 0x%08x", *dump_sp++);
438 }
439 tty->cr();
440 }
441 // Print some instructions around pc:
442 Disassembler::decode((address)eip-64, (address)eip);
443 tty->print_cr("--------");
444 Disassembler::decode((address)eip, (address)eip+32);
445 }
446
447 void MacroAssembler::stop(const char* msg) {
448 // push address of message
449 ExternalAddress message((address)msg);
450 pushptr(message.addr(), noreg);
451 { Label L; call(L, relocInfo::none); bind(L); } // push eip
452 pusha(); // push registers
453 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
454 hlt();
455 }
456
457 void MacroAssembler::warn(const char* msg) {
458 push_CPU_state();
459
460 // push address of message
461 ExternalAddress message((address)msg);
462 pushptr(message.addr(), noreg);
463
464 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
465 addl(rsp, wordSize); // discard argument
466 pop_CPU_state();
467 }
468
469 void MacroAssembler::print_state() {
470 { Label L; call(L, relocInfo::none); bind(L); } // push eip
471 pusha(); // push registers
472
473 push_CPU_state();
474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
475 pop_CPU_state();
476
477 popa();
478 addl(rsp, wordSize);
479 }
480
481 #else // _LP64
482
483 // 64 bit versions
484
485 Address MacroAssembler::as_Address(AddressLiteral adr) {
486 // amd64 always does this as a pc-rel
487 // we can be absolute or disp based on the instruction type
488 // jmp/call are displacements others are absolute
489 assert(!adr.is_lval(), "must be rval");
490 assert(reachable(adr), "must be");
491 return Address(checked_cast<int32_t>(adr.target() - pc()), adr.target(), adr.reloc());
492
493 }
494
495 Address MacroAssembler::as_Address(ArrayAddress adr, Register rscratch) {
496 AddressLiteral base = adr.base();
497 lea(rscratch, base);
498 Address index = adr.index();
499 assert(index._disp == 0, "must not have disp"); // maybe it can?
500 Address array(rscratch, index._index, index._scale, index._disp);
501 return array;
502 }
503
504 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
505 Label L, E;
506
507 #ifdef _WIN64
508 // Windows always allocates space for it's register args
509 assert(num_args <= 4, "only register arguments supported");
510 subq(rsp, frame::arg_reg_save_area_bytes);
511 #endif
512
513 // Align stack if necessary
514 testl(rsp, 15);
515 jcc(Assembler::zero, L);
516
517 subq(rsp, 8);
518 call(RuntimeAddress(entry_point));
519 addq(rsp, 8);
520 jmp(E);
521
522 bind(L);
523 call(RuntimeAddress(entry_point));
524
525 bind(E);
526
527 #ifdef _WIN64
528 // restore stack pointer
529 addq(rsp, frame::arg_reg_save_area_bytes);
530 #endif
531
532 }
533
534 void MacroAssembler::cmp64(Register src1, AddressLiteral src2, Register rscratch) {
535 assert(!src2.is_lval(), "should use cmpptr");
536 assert(rscratch != noreg || always_reachable(src2), "missing");
537
538 if (reachable(src2)) {
539 cmpq(src1, as_Address(src2));
540 } else {
541 lea(rscratch, src2);
542 Assembler::cmpq(src1, Address(rscratch, 0));
543 }
544 }
545
546 int MacroAssembler::corrected_idivq(Register reg) {
547 // Full implementation of Java ldiv and lrem; checks for special
548 // case as described in JVM spec., p.243 & p.271. The function
549 // returns the (pc) offset of the idivl instruction - may be needed
550 // for implicit exceptions.
551 //
552 // normal case special case
553 //
554 // input : rax: dividend min_long
555 // reg: divisor (may not be eax/edx) -1
556 //
557 // output: rax: quotient (= rax idiv reg) min_long
558 // rdx: remainder (= rax irem reg) 0
559 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
560 static const int64_t min_long = 0x8000000000000000;
561 Label normal_case, special_case;
562
563 // check for special case
564 cmp64(rax, ExternalAddress((address) &min_long), rdx /*rscratch*/);
565 jcc(Assembler::notEqual, normal_case);
566 xorl(rdx, rdx); // prepare rdx for possible special case (where
567 // remainder = 0)
568 cmpq(reg, -1);
569 jcc(Assembler::equal, special_case);
570
571 // handle normal case
572 bind(normal_case);
573 cdqq();
574 int idivq_offset = offset();
575 idivq(reg);
576
577 // normal and special case exit
578 bind(special_case);
579
580 return idivq_offset;
581 }
582
583 void MacroAssembler::decrementq(Register reg, int value) {
584 if (value == min_jint) { subq(reg, value); return; }
585 if (value < 0) { incrementq(reg, -value); return; }
586 if (value == 0) { ; return; }
587 if (value == 1 && UseIncDec) { decq(reg) ; return; }
588 /* else */ { subq(reg, value) ; return; }
589 }
590
591 void MacroAssembler::decrementq(Address dst, int value) {
592 if (value == min_jint) { subq(dst, value); return; }
593 if (value < 0) { incrementq(dst, -value); return; }
594 if (value == 0) { ; return; }
595 if (value == 1 && UseIncDec) { decq(dst) ; return; }
596 /* else */ { subq(dst, value) ; return; }
597 }
598
599 void MacroAssembler::incrementq(AddressLiteral dst, Register rscratch) {
600 assert(rscratch != noreg || always_reachable(dst), "missing");
601
602 if (reachable(dst)) {
603 incrementq(as_Address(dst));
604 } else {
605 lea(rscratch, dst);
606 incrementq(Address(rscratch, 0));
607 }
608 }
609
610 void MacroAssembler::incrementq(Register reg, int value) {
611 if (value == min_jint) { addq(reg, value); return; }
612 if (value < 0) { decrementq(reg, -value); return; }
613 if (value == 0) { ; return; }
614 if (value == 1 && UseIncDec) { incq(reg) ; return; }
615 /* else */ { addq(reg, value) ; return; }
616 }
617
618 void MacroAssembler::incrementq(Address dst, int value) {
619 if (value == min_jint) { addq(dst, value); return; }
620 if (value < 0) { decrementq(dst, -value); return; }
621 if (value == 0) { ; return; }
622 if (value == 1 && UseIncDec) { incq(dst) ; return; }
623 /* else */ { addq(dst, value) ; return; }
624 }
625
626 // 32bit can do a case table jump in one instruction but we no longer allow the base
627 // to be installed in the Address class
628 void MacroAssembler::jump(ArrayAddress entry, Register rscratch) {
629 lea(rscratch, entry.base());
630 Address dispatch = entry.index();
631 assert(dispatch._base == noreg, "must be");
632 dispatch._base = rscratch;
633 jmp(dispatch);
634 }
635
636 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
637 ShouldNotReachHere(); // 64bit doesn't use two regs
638 cmpq(x_lo, y_lo);
639 }
640
641 void MacroAssembler::lea(Register dst, AddressLiteral src) {
642 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
643 }
644
645 void MacroAssembler::lea(Address dst, AddressLiteral adr, Register rscratch) {
646 lea(rscratch, adr);
647 movptr(dst, rscratch);
648 }
649
650 void MacroAssembler::leave() {
651 // %%% is this really better? Why not on 32bit too?
652 emit_int8((unsigned char)0xC9); // LEAVE
653 }
654
655 void MacroAssembler::lneg(Register hi, Register lo) {
656 ShouldNotReachHere(); // 64bit doesn't use two regs
657 negq(lo);
658 }
659
660 void MacroAssembler::movoop(Register dst, jobject obj) {
661 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
662 }
663
664 void MacroAssembler::movoop(Address dst, jobject obj, Register rscratch) {
665 mov_literal64(rscratch, (intptr_t)obj, oop_Relocation::spec_for_immediate());
666 movq(dst, rscratch);
667 }
668
669 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
670 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
671 }
672
673 void MacroAssembler::mov_metadata(Address dst, Metadata* obj, Register rscratch) {
674 mov_literal64(rscratch, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
675 movq(dst, rscratch);
676 }
677
678 void MacroAssembler::movptr(Register dst, AddressLiteral src) {
679 if (src.is_lval()) {
680 mov_literal64(dst, (intptr_t)src.target(), src.rspec());
681 } else {
682 if (reachable(src)) {
683 movq(dst, as_Address(src));
684 } else {
685 lea(dst, src);
686 movq(dst, Address(dst, 0));
687 }
688 }
689 }
690
691 void MacroAssembler::movptr(ArrayAddress dst, Register src, Register rscratch) {
692 movq(as_Address(dst, rscratch), src);
693 }
694
695 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
696 movq(dst, as_Address(src, dst /*rscratch*/));
697 }
698
699 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
700 void MacroAssembler::movptr(Address dst, intptr_t src, Register rscratch) {
701 if (is_simm32(src)) {
702 movptr(dst, checked_cast<int32_t>(src));
703 } else {
704 mov64(rscratch, src);
705 movq(dst, rscratch);
706 }
707 }
708
709 void MacroAssembler::pushoop(jobject obj, Register rscratch) {
710 movoop(rscratch, obj);
711 push(rscratch);
712 }
713
714 void MacroAssembler::pushklass(Metadata* obj, Register rscratch) {
715 mov_metadata(rscratch, obj);
716 push(rscratch);
717 }
718
719 void MacroAssembler::pushptr(AddressLiteral src, Register rscratch) {
720 lea(rscratch, src);
721 if (src.is_lval()) {
722 push(rscratch);
723 } else {
724 pushq(Address(rscratch, 0));
725 }
726 }
727
728 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
729 reset_last_Java_frame(r15_thread, clear_fp);
730 }
731
732 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
733 Register last_java_fp,
734 address last_java_pc,
735 Register rscratch) {
736 set_last_Java_frame(r15_thread, last_java_sp, last_java_fp, last_java_pc, rscratch);
737 }
738
739 static void pass_arg0(MacroAssembler* masm, Register arg) {
740 if (c_rarg0 != arg ) {
741 masm->mov(c_rarg0, arg);
742 }
743 }
744
745 static void pass_arg1(MacroAssembler* masm, Register arg) {
746 if (c_rarg1 != arg ) {
747 masm->mov(c_rarg1, arg);
748 }
749 }
750
751 static void pass_arg2(MacroAssembler* masm, Register arg) {
752 if (c_rarg2 != arg ) {
753 masm->mov(c_rarg2, arg);
754 }
755 }
756
757 static void pass_arg3(MacroAssembler* masm, Register arg) {
758 if (c_rarg3 != arg ) {
759 masm->mov(c_rarg3, arg);
760 }
761 }
762
763 void MacroAssembler::stop(const char* msg) {
764 if (ShowMessageBoxOnError) {
765 address rip = pc();
766 pusha(); // get regs on stack
767 lea(c_rarg1, InternalAddress(rip));
768 movq(c_rarg2, rsp); // pass pointer to regs array
769 }
770 lea(c_rarg0, ExternalAddress((address) msg));
771 andq(rsp, -16); // align stack as required by ABI
772 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
773 hlt();
774 }
775
776 void MacroAssembler::warn(const char* msg) {
777 push(rbp);
778 movq(rbp, rsp);
779 andq(rsp, -16); // align stack as required by push_CPU_state and call
780 push_CPU_state(); // keeps alignment at 16 bytes
781
782 lea(c_rarg0, ExternalAddress((address) msg));
783 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
784
785 pop_CPU_state();
786 mov(rsp, rbp);
787 pop(rbp);
788 }
789
790 void MacroAssembler::print_state() {
791 address rip = pc();
792 pusha(); // get regs on stack
793 push(rbp);
794 movq(rbp, rsp);
795 andq(rsp, -16); // align stack as required by push_CPU_state and call
796 push_CPU_state(); // keeps alignment at 16 bytes
797
798 lea(c_rarg0, InternalAddress(rip));
799 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
800 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
801
802 pop_CPU_state();
803 mov(rsp, rbp);
804 pop(rbp);
805 popa();
806 }
807
808 #ifndef PRODUCT
809 extern "C" void findpc(intptr_t x);
810 #endif
811
812 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
813 // In order to get locks to work, we need to fake a in_VM state
814 if (ShowMessageBoxOnError) {
815 JavaThread* thread = JavaThread::current();
816 JavaThreadState saved_state = thread->thread_state();
817 thread->set_thread_state(_thread_in_vm);
818 #ifndef PRODUCT
819 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
820 ttyLocker ttyl;
821 BytecodeCounter::print();
822 }
823 #endif
824 // To see where a verify_oop failed, get $ebx+40/X for this frame.
825 // XXX correct this offset for amd64
826 // This is the value of eip which points to where verify_oop will return.
827 if (os::message_box(msg, "Execution stopped, print registers?")) {
828 print_state64(pc, regs);
829 BREAKPOINT;
830 }
831 }
832 fatal("DEBUG MESSAGE: %s", msg);
833 }
834
835 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
836 ttyLocker ttyl;
837 DebuggingContext debugging{};
838 tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
839 #ifndef PRODUCT
840 tty->cr();
841 findpc(pc);
842 tty->cr();
843 #endif
844 #define PRINT_REG(rax, value) \
845 { tty->print("%s = ", #rax); os::print_location(tty, value); }
846 PRINT_REG(rax, regs[15]);
847 PRINT_REG(rbx, regs[12]);
848 PRINT_REG(rcx, regs[14]);
849 PRINT_REG(rdx, regs[13]);
850 PRINT_REG(rdi, regs[8]);
851 PRINT_REG(rsi, regs[9]);
852 PRINT_REG(rbp, regs[10]);
853 // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
854 PRINT_REG(rsp, (intptr_t)(®s[16]));
855 PRINT_REG(r8 , regs[7]);
856 PRINT_REG(r9 , regs[6]);
857 PRINT_REG(r10, regs[5]);
858 PRINT_REG(r11, regs[4]);
859 PRINT_REG(r12, regs[3]);
860 PRINT_REG(r13, regs[2]);
861 PRINT_REG(r14, regs[1]);
862 PRINT_REG(r15, regs[0]);
863 #undef PRINT_REG
864 // Print some words near the top of the stack.
865 int64_t* rsp = ®s[16];
866 int64_t* dump_sp = rsp;
867 for (int col1 = 0; col1 < 8; col1++) {
868 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
869 os::print_location(tty, *dump_sp++);
870 }
871 for (int row = 0; row < 25; row++) {
872 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
873 for (int col = 0; col < 4; col++) {
874 tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
875 }
876 tty->cr();
877 }
878 // Print some instructions around pc:
879 Disassembler::decode((address)pc-64, (address)pc);
880 tty->print_cr("--------");
881 Disassembler::decode((address)pc, (address)pc+32);
882 }
883
884 // The java_calling_convention describes stack locations as ideal slots on
885 // a frame with no abi restrictions. Since we must observe abi restrictions
886 // (like the placement of the register window) the slots must be biased by
887 // the following value.
888 static int reg2offset_in(VMReg r) {
889 // Account for saved rbp and return address
890 // This should really be in_preserve_stack_slots
891 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
892 }
893
894 static int reg2offset_out(VMReg r) {
895 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
896 }
897
898 // A long move
899 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
900
901 // The calling conventions assures us that each VMregpair is either
902 // all really one physical register or adjacent stack slots.
903
904 if (src.is_single_phys_reg() ) {
905 if (dst.is_single_phys_reg()) {
906 if (dst.first() != src.first()) {
907 mov(dst.first()->as_Register(), src.first()->as_Register());
908 }
909 } else {
910 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
911 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
912 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
913 }
914 } else if (dst.is_single_phys_reg()) {
915 assert(src.is_single_reg(), "not a stack pair");
916 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
917 } else {
918 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
919 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
920 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
921 }
922 }
923
924 // A double move
925 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
926
927 // The calling conventions assures us that each VMregpair is either
928 // all really one physical register or adjacent stack slots.
929
930 if (src.is_single_phys_reg() ) {
931 if (dst.is_single_phys_reg()) {
932 // In theory these overlap but the ordering is such that this is likely a nop
933 if ( src.first() != dst.first()) {
934 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
935 }
936 } else {
937 assert(dst.is_single_reg(), "not a stack pair");
938 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
939 }
940 } else if (dst.is_single_phys_reg()) {
941 assert(src.is_single_reg(), "not a stack pair");
942 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
943 } else {
944 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
945 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
946 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
947 }
948 }
949
950
951 // A float arg may have to do float reg int reg conversion
952 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
953 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
954
955 // The calling conventions assures us that each VMregpair is either
956 // all really one physical register or adjacent stack slots.
957
958 if (src.first()->is_stack()) {
959 if (dst.first()->is_stack()) {
960 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
961 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
962 } else {
963 // stack to reg
964 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
965 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
966 }
967 } else if (dst.first()->is_stack()) {
968 // reg to stack
969 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
970 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
971 } else {
972 // reg to reg
973 // In theory these overlap but the ordering is such that this is likely a nop
974 if ( src.first() != dst.first()) {
975 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
976 }
977 }
978 }
979
980 // On 64 bit we will store integer like items to the stack as
981 // 64 bits items (x86_32/64 abi) even though java would only store
982 // 32bits for a parameter. On 32bit it will simply be 32 bits
983 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
984 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
985 if (src.first()->is_stack()) {
986 if (dst.first()->is_stack()) {
987 // stack to stack
988 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
989 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
990 } else {
991 // stack to reg
992 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
993 }
994 } else if (dst.first()->is_stack()) {
995 // reg to stack
996 // Do we really have to sign extend???
997 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
998 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
999 } else {
1000 // Do we really have to sign extend???
1001 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1002 if (dst.first() != src.first()) {
1003 movq(dst.first()->as_Register(), src.first()->as_Register());
1004 }
1005 }
1006 }
1007
1008 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1009 if (src.first()->is_stack()) {
1010 if (dst.first()->is_stack()) {
1011 // stack to stack
1012 movq(rax, Address(rbp, reg2offset_in(src.first())));
1013 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1014 } else {
1015 // stack to reg
1016 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1017 }
1018 } else if (dst.first()->is_stack()) {
1019 // reg to stack
1020 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1021 } else {
1022 if (dst.first() != src.first()) {
1023 movq(dst.first()->as_Register(), src.first()->as_Register());
1024 }
1025 }
1026 }
1027
1028 // An oop arg. Must pass a handle not the oop itself
1029 void MacroAssembler::object_move(OopMap* map,
1030 int oop_handle_offset,
1031 int framesize_in_slots,
1032 VMRegPair src,
1033 VMRegPair dst,
1034 bool is_receiver,
1035 int* receiver_offset) {
1036
1037 // must pass a handle. First figure out the location we use as a handle
1038
1039 Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1040
1041 // See if oop is null if it is we need no handle
1042
1043 if (src.first()->is_stack()) {
1044
1045 // Oop is already on the stack as an argument
1046 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1047 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1048 if (is_receiver) {
1049 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1050 }
1051
1052 cmpptr(Address(rbp, reg2offset_in(src.first())), NULL_WORD);
1053 lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1054 // conditionally move a null
1055 cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1056 } else {
1057
1058 // Oop is in a register we must store it to the space we reserve
1059 // on the stack for oop_handles and pass a handle if oop is non-null
1060
1061 const Register rOop = src.first()->as_Register();
1062 int oop_slot;
1063 if (rOop == j_rarg0)
1064 oop_slot = 0;
1065 else if (rOop == j_rarg1)
1066 oop_slot = 1;
1067 else if (rOop == j_rarg2)
1068 oop_slot = 2;
1069 else if (rOop == j_rarg3)
1070 oop_slot = 3;
1071 else if (rOop == j_rarg4)
1072 oop_slot = 4;
1073 else {
1074 assert(rOop == j_rarg5, "wrong register");
1075 oop_slot = 5;
1076 }
1077
1078 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1079 int offset = oop_slot*VMRegImpl::stack_slot_size;
1080
1081 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1082 // Store oop in handle area, may be null
1083 movptr(Address(rsp, offset), rOop);
1084 if (is_receiver) {
1085 *receiver_offset = offset;
1086 }
1087
1088 cmpptr(rOop, NULL_WORD);
1089 lea(rHandle, Address(rsp, offset));
1090 // conditionally move a null from the handle area where it was just stored
1091 cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1092 }
1093
1094 // If arg is on the stack then place it otherwise it is already in correct reg.
1095 if (dst.first()->is_stack()) {
1096 movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1097 }
1098 }
1099
1100 #endif // _LP64
1101
1102 // Now versions that are common to 32/64 bit
1103
1104 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1105 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1106 }
1107
1108 void MacroAssembler::addptr(Register dst, Register src) {
1109 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1110 }
1111
1112 void MacroAssembler::addptr(Address dst, Register src) {
1113 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1114 }
1115
1116 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1117 assert(rscratch != noreg || always_reachable(src), "missing");
1118
1119 if (reachable(src)) {
1120 Assembler::addsd(dst, as_Address(src));
1121 } else {
1122 lea(rscratch, src);
1123 Assembler::addsd(dst, Address(rscratch, 0));
1124 }
1125 }
1126
1127 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1128 assert(rscratch != noreg || always_reachable(src), "missing");
1129
1130 if (reachable(src)) {
1131 addss(dst, as_Address(src));
1132 } else {
1133 lea(rscratch, src);
1134 addss(dst, Address(rscratch, 0));
1135 }
1136 }
1137
1138 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1139 assert(rscratch != noreg || always_reachable(src), "missing");
1140
1141 if (reachable(src)) {
1142 Assembler::addpd(dst, as_Address(src));
1143 } else {
1144 lea(rscratch, src);
1145 Assembler::addpd(dst, Address(rscratch, 0));
1146 }
1147 }
1148
1149 // See 8273459. Function for ensuring 64-byte alignment, intended for stubs only.
1150 // Stub code is generated once and never copied.
1151 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1152 void MacroAssembler::align64() {
1153 align(64, (uint)(uintptr_t)pc());
1154 }
1155
1156 void MacroAssembler::align32() {
1157 align(32, (uint)(uintptr_t)pc());
1158 }
1159
1160 void MacroAssembler::align(uint modulus) {
1161 // 8273459: Ensure alignment is possible with current segment alignment
1162 assert(modulus <= (uintx)CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1163 align(modulus, offset());
1164 }
1165
1166 void MacroAssembler::align(uint modulus, uint target) {
1167 if (target % modulus != 0) {
1168 nop(modulus - (target % modulus));
1169 }
1170 }
1171
1172 void MacroAssembler::push_f(XMMRegister r) {
1173 subptr(rsp, wordSize);
1174 movflt(Address(rsp, 0), r);
1175 }
1176
1177 void MacroAssembler::pop_f(XMMRegister r) {
1178 movflt(r, Address(rsp, 0));
1179 addptr(rsp, wordSize);
1180 }
1181
1182 void MacroAssembler::push_d(XMMRegister r) {
1183 subptr(rsp, 2 * wordSize);
1184 movdbl(Address(rsp, 0), r);
1185 }
1186
1187 void MacroAssembler::pop_d(XMMRegister r) {
1188 movdbl(r, Address(rsp, 0));
1189 addptr(rsp, 2 * Interpreter::stackElementSize);
1190 }
1191
1192 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1193 // Used in sign-masking with aligned address.
1194 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195 assert(rscratch != noreg || always_reachable(src), "missing");
1196
1197 if (reachable(src)) {
1198 Assembler::andpd(dst, as_Address(src));
1199 } else {
1200 lea(rscratch, src);
1201 Assembler::andpd(dst, Address(rscratch, 0));
1202 }
1203 }
1204
1205 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register rscratch) {
1206 // Used in sign-masking with aligned address.
1207 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1208 assert(rscratch != noreg || always_reachable(src), "missing");
1209
1210 if (reachable(src)) {
1211 Assembler::andps(dst, as_Address(src));
1212 } else {
1213 lea(rscratch, src);
1214 Assembler::andps(dst, Address(rscratch, 0));
1215 }
1216 }
1217
1218 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1219 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1220 }
1221
1222 #ifdef _LP64
1223 void MacroAssembler::andq(Register dst, AddressLiteral src, Register rscratch) {
1224 assert(rscratch != noreg || always_reachable(src), "missing");
1225
1226 if (reachable(src)) {
1227 andq(dst, as_Address(src));
1228 } else {
1229 lea(rscratch, src);
1230 andq(dst, Address(rscratch, 0));
1231 }
1232 }
1233 #endif
1234
1235 void MacroAssembler::atomic_incl(Address counter_addr) {
1236 lock();
1237 incrementl(counter_addr);
1238 }
1239
1240 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register rscratch) {
1241 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1242
1243 if (reachable(counter_addr)) {
1244 atomic_incl(as_Address(counter_addr));
1245 } else {
1246 lea(rscratch, counter_addr);
1247 atomic_incl(Address(rscratch, 0));
1248 }
1249 }
1250
1251 #ifdef _LP64
1252 void MacroAssembler::atomic_incq(Address counter_addr) {
1253 lock();
1254 incrementq(counter_addr);
1255 }
1256
1257 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register rscratch) {
1258 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1259
1260 if (reachable(counter_addr)) {
1261 atomic_incq(as_Address(counter_addr));
1262 } else {
1263 lea(rscratch, counter_addr);
1264 atomic_incq(Address(rscratch, 0));
1265 }
1266 }
1267 #endif
1268
1269 // Writes to stack successive pages until offset reached to check for
1270 // stack overflow + shadow pages. This clobbers tmp.
1271 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1272 movptr(tmp, rsp);
1273 // Bang stack for total size given plus shadow page size.
1274 // Bang one page at a time because large size can bang beyond yellow and
1275 // red zones.
1276 Label loop;
1277 bind(loop);
1278 movl(Address(tmp, (-(int)os::vm_page_size())), size );
1279 subptr(tmp, (int)os::vm_page_size());
1280 subl(size, (int)os::vm_page_size());
1281 jcc(Assembler::greater, loop);
1282
1283 // Bang down shadow pages too.
1284 // At this point, (tmp-0) is the last address touched, so don't
1285 // touch it again. (It was touched as (tmp-pagesize) but then tmp
1286 // was post-decremented.) Skip this address by starting at i=1, and
1287 // touch a few more pages below. N.B. It is important to touch all
1288 // the way down including all pages in the shadow zone.
1289 for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()); i++) {
1290 // this could be any sized move but this is can be a debugging crumb
1291 // so the bigger the better.
1292 movptr(Address(tmp, (-i*(int)os::vm_page_size())), size );
1293 }
1294 }
1295
1296 void MacroAssembler::reserved_stack_check() {
1297 // testing if reserved zone needs to be enabled
1298 Label no_reserved_zone_enabling;
1299 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1300 NOT_LP64(get_thread(rsi);)
1301
1302 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1303 jcc(Assembler::below, no_reserved_zone_enabling);
1304
1305 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1306 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1307 should_not_reach_here();
1308
1309 bind(no_reserved_zone_enabling);
1310 }
1311
1312 void MacroAssembler::c2bool(Register x) {
1313 // implements x == 0 ? 0 : 1
1314 // note: must only look at least-significant byte of x
1315 // since C-style booleans are stored in one byte
1316 // only! (was bug)
1317 andl(x, 0xFF);
1318 setb(Assembler::notZero, x);
1319 }
1320
1321 // Wouldn't need if AddressLiteral version had new name
1322 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1323 Assembler::call(L, rtype);
1324 }
1325
1326 void MacroAssembler::call(Register entry) {
1327 Assembler::call(entry);
1328 }
1329
1330 void MacroAssembler::call(AddressLiteral entry, Register rscratch) {
1331 assert(rscratch != noreg || always_reachable(entry), "missing");
1332
1333 if (reachable(entry)) {
1334 Assembler::call_literal(entry.target(), entry.rspec());
1335 } else {
1336 lea(rscratch, entry);
1337 Assembler::call(rscratch);
1338 }
1339 }
1340
1341 void MacroAssembler::ic_call(address entry, jint method_index) {
1342 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1343 #ifdef _LP64
1344 // Needs full 64-bit immediate for later patching.
1345 mov64(rax, (int64_t)Universe::non_oop_word());
1346 #else
1347 movptr(rax, (intptr_t)Universe::non_oop_word());
1348 #endif
1349 call(AddressLiteral(entry, rh));
1350 }
1351
1352 int MacroAssembler::ic_check_size() {
1353 return
1354 LP64_ONLY(UseCompactObjectHeaders ? 17 : 14) NOT_LP64(12);
1355 }
1356
1357 int MacroAssembler::ic_check(int end_alignment) {
1358 Register receiver = LP64_ONLY(j_rarg0) NOT_LP64(rcx);
1359 Register data = rax;
1360 Register temp = LP64_ONLY(rscratch1) NOT_LP64(rbx);
1361
1362 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1363 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1364 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1365 // before the inline cache check here, and not after
1366 align(end_alignment, offset() + ic_check_size());
1367
1368 int uep_offset = offset();
1369
1370 #ifdef _LP64
1371 if (UseCompactObjectHeaders) {
1372 load_nklass_compact(temp, receiver);
1373 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1374 } else
1375 #endif
1376 if (UseCompressedClassPointers) {
1377 movl(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1378 cmpl(temp, Address(data, CompiledICData::speculated_klass_offset()));
1379 } else {
1380 movptr(temp, Address(receiver, oopDesc::klass_offset_in_bytes()));
1381 cmpptr(temp, Address(data, CompiledICData::speculated_klass_offset()));
1382 }
1383
1384 // if inline cache check fails, then jump to runtime routine
1385 jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1386 assert((offset() % end_alignment) == 0, "Misaligned verified entry point (%d, %d, %d)", uep_offset, offset(), end_alignment);
1387
1388 return uep_offset;
1389 }
1390
1391 void MacroAssembler::emit_static_call_stub() {
1392 // Static stub relocation also tags the Method* in the code-stream.
1393 mov_metadata(rbx, (Metadata*) nullptr); // Method is zapped till fixup time.
1394 // This is recognized as unresolved by relocs/nativeinst/ic code.
1395 jump(RuntimeAddress(pc()));
1396 }
1397
1398 // Implementation of call_VM versions
1399
1400 void MacroAssembler::call_VM(Register oop_result,
1401 address entry_point,
1402 bool check_exceptions) {
1403 Label C, E;
1404 call(C, relocInfo::none);
1405 jmp(E);
1406
1407 bind(C);
1408 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1409 ret(0);
1410
1411 bind(E);
1412 }
1413
1414 void MacroAssembler::call_VM(Register oop_result,
1415 address entry_point,
1416 Register arg_1,
1417 bool check_exceptions) {
1418 Label C, E;
1419 call(C, relocInfo::none);
1420 jmp(E);
1421
1422 bind(C);
1423 pass_arg1(this, arg_1);
1424 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1425 ret(0);
1426
1427 bind(E);
1428 }
1429
1430 void MacroAssembler::call_VM(Register oop_result,
1431 address entry_point,
1432 Register arg_1,
1433 Register arg_2,
1434 bool check_exceptions) {
1435 Label C, E;
1436 call(C, relocInfo::none);
1437 jmp(E);
1438
1439 bind(C);
1440
1441 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1442
1443 pass_arg2(this, arg_2);
1444 pass_arg1(this, arg_1);
1445 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1446 ret(0);
1447
1448 bind(E);
1449 }
1450
1451 void MacroAssembler::call_VM(Register oop_result,
1452 address entry_point,
1453 Register arg_1,
1454 Register arg_2,
1455 Register arg_3,
1456 bool check_exceptions) {
1457 Label C, E;
1458 call(C, relocInfo::none);
1459 jmp(E);
1460
1461 bind(C);
1462
1463 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1464 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1465 pass_arg3(this, arg_3);
1466 pass_arg2(this, arg_2);
1467 pass_arg1(this, arg_1);
1468 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1469 ret(0);
1470
1471 bind(E);
1472 }
1473
1474 void MacroAssembler::call_VM(Register oop_result,
1475 Register last_java_sp,
1476 address entry_point,
1477 int number_of_arguments,
1478 bool check_exceptions) {
1479 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1480 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1481 }
1482
1483 void MacroAssembler::call_VM(Register oop_result,
1484 Register last_java_sp,
1485 address entry_point,
1486 Register arg_1,
1487 bool check_exceptions) {
1488 pass_arg1(this, arg_1);
1489 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1490 }
1491
1492 void MacroAssembler::call_VM(Register oop_result,
1493 Register last_java_sp,
1494 address entry_point,
1495 Register arg_1,
1496 Register arg_2,
1497 bool check_exceptions) {
1498
1499 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1500 pass_arg2(this, arg_2);
1501 pass_arg1(this, arg_1);
1502 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1503 }
1504
1505 void MacroAssembler::call_VM(Register oop_result,
1506 Register last_java_sp,
1507 address entry_point,
1508 Register arg_1,
1509 Register arg_2,
1510 Register arg_3,
1511 bool check_exceptions) {
1512 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1513 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1514 pass_arg3(this, arg_3);
1515 pass_arg2(this, arg_2);
1516 pass_arg1(this, arg_1);
1517 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1518 }
1519
1520 void MacroAssembler::super_call_VM(Register oop_result,
1521 Register last_java_sp,
1522 address entry_point,
1523 int number_of_arguments,
1524 bool check_exceptions) {
1525 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1526 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1527 }
1528
1529 void MacroAssembler::super_call_VM(Register oop_result,
1530 Register last_java_sp,
1531 address entry_point,
1532 Register arg_1,
1533 bool check_exceptions) {
1534 pass_arg1(this, arg_1);
1535 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1536 }
1537
1538 void MacroAssembler::super_call_VM(Register oop_result,
1539 Register last_java_sp,
1540 address entry_point,
1541 Register arg_1,
1542 Register arg_2,
1543 bool check_exceptions) {
1544
1545 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1546 pass_arg2(this, arg_2);
1547 pass_arg1(this, arg_1);
1548 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1549 }
1550
1551 void MacroAssembler::super_call_VM(Register oop_result,
1552 Register last_java_sp,
1553 address entry_point,
1554 Register arg_1,
1555 Register arg_2,
1556 Register arg_3,
1557 bool check_exceptions) {
1558 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1559 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1560 pass_arg3(this, arg_3);
1561 pass_arg2(this, arg_2);
1562 pass_arg1(this, arg_1);
1563 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1564 }
1565
1566 void MacroAssembler::call_VM_base(Register oop_result,
1567 Register java_thread,
1568 Register last_java_sp,
1569 address entry_point,
1570 int number_of_arguments,
1571 bool check_exceptions) {
1572 // determine java_thread register
1573 if (!java_thread->is_valid()) {
1574 #ifdef _LP64
1575 java_thread = r15_thread;
1576 #else
1577 java_thread = rdi;
1578 get_thread(java_thread);
1579 #endif // LP64
1580 }
1581 // determine last_java_sp register
1582 if (!last_java_sp->is_valid()) {
1583 last_java_sp = rsp;
1584 }
1585 // debugging support
1586 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
1587 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1588 #ifdef ASSERT
1589 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1590 // r12 is the heapbase.
1591 LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1592 #endif // ASSERT
1593
1594 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
1595 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1596
1597 // push java thread (becomes first argument of C function)
1598
1599 NOT_LP64(push(java_thread); number_of_arguments++);
1600 LP64_ONLY(mov(c_rarg0, r15_thread));
1601
1602 // set last Java frame before call
1603 assert(last_java_sp != rbp, "can't use ebp/rbp");
1604
1605 // Only interpreter should have to set fp
1606 set_last_Java_frame(java_thread, last_java_sp, rbp, nullptr, rscratch1);
1607
1608 // do the call, remove parameters
1609 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1610
1611 // restore the thread (cannot use the pushed argument since arguments
1612 // may be overwritten by C code generated by an optimizing compiler);
1613 // however can use the register value directly if it is callee saved.
1614 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1615 // rdi & rsi (also r15) are callee saved -> nothing to do
1616 #ifdef ASSERT
1617 guarantee(java_thread != rax, "change this code");
1618 push(rax);
1619 { Label L;
1620 get_thread(rax);
1621 cmpptr(java_thread, rax);
1622 jcc(Assembler::equal, L);
1623 STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1624 bind(L);
1625 }
1626 pop(rax);
1627 #endif
1628 } else {
1629 get_thread(java_thread);
1630 }
1631 // reset last Java frame
1632 // Only interpreter should have to clear fp
1633 reset_last_Java_frame(java_thread, true);
1634
1635 // C++ interp handles this in the interpreter
1636 check_and_handle_popframe(java_thread);
1637 check_and_handle_earlyret(java_thread);
1638
1639 if (check_exceptions) {
1640 // check for pending exceptions (java_thread is set upon return)
1641 cmpptr(Address(java_thread, Thread::pending_exception_offset()), NULL_WORD);
1642 #ifndef _LP64
1643 jump_cc(Assembler::notEqual,
1644 RuntimeAddress(StubRoutines::forward_exception_entry()));
1645 #else
1646 // This used to conditionally jump to forward_exception however it is
1647 // possible if we relocate that the branch will not reach. So we must jump
1648 // around so we can always reach
1649
1650 Label ok;
1651 jcc(Assembler::equal, ok);
1652 jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1653 bind(ok);
1654 #endif // LP64
1655 }
1656
1657 // get oop result if there is one and reset the value in the thread
1658 if (oop_result->is_valid()) {
1659 get_vm_result(oop_result, java_thread);
1660 }
1661 }
1662
1663 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1664
1665 // Calculate the value for last_Java_sp
1666 // somewhat subtle. call_VM does an intermediate call
1667 // which places a return address on the stack just under the
1668 // stack pointer as the user finished with it. This allows
1669 // use to retrieve last_Java_pc from last_Java_sp[-1].
1670 // On 32bit we then have to push additional args on the stack to accomplish
1671 // the actual requested call. On 64bit call_VM only can use register args
1672 // so the only extra space is the return address that call_VM created.
1673 // This hopefully explains the calculations here.
1674
1675 #ifdef _LP64
1676 // We've pushed one address, correct last_Java_sp
1677 lea(rax, Address(rsp, wordSize));
1678 #else
1679 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1680 #endif // LP64
1681
1682 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1683
1684 }
1685
1686 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1687 void MacroAssembler::call_VM_leaf0(address entry_point) {
1688 MacroAssembler::call_VM_leaf_base(entry_point, 0);
1689 }
1690
1691 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1692 call_VM_leaf_base(entry_point, number_of_arguments);
1693 }
1694
1695 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1696 pass_arg0(this, arg_0);
1697 call_VM_leaf(entry_point, 1);
1698 }
1699
1700 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1701
1702 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1703 pass_arg1(this, arg_1);
1704 pass_arg0(this, arg_0);
1705 call_VM_leaf(entry_point, 2);
1706 }
1707
1708 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1709 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1710 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1711 pass_arg2(this, arg_2);
1712 pass_arg1(this, arg_1);
1713 pass_arg0(this, arg_0);
1714 call_VM_leaf(entry_point, 3);
1715 }
1716
1717 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1718 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1719 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1720 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1721 pass_arg3(this, arg_3);
1722 pass_arg2(this, arg_2);
1723 pass_arg1(this, arg_1);
1724 pass_arg0(this, arg_0);
1725 call_VM_leaf(entry_point, 3);
1726 }
1727
1728 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1729 pass_arg0(this, arg_0);
1730 MacroAssembler::call_VM_leaf_base(entry_point, 1);
1731 }
1732
1733 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1734 LP64_ONLY(assert_different_registers(arg_0, c_rarg1));
1735 pass_arg1(this, arg_1);
1736 pass_arg0(this, arg_0);
1737 MacroAssembler::call_VM_leaf_base(entry_point, 2);
1738 }
1739
1740 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1741 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2));
1742 LP64_ONLY(assert_different_registers(arg_1, c_rarg2));
1743 pass_arg2(this, arg_2);
1744 pass_arg1(this, arg_1);
1745 pass_arg0(this, arg_0);
1746 MacroAssembler::call_VM_leaf_base(entry_point, 3);
1747 }
1748
1749 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1750 LP64_ONLY(assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3));
1751 LP64_ONLY(assert_different_registers(arg_1, c_rarg2, c_rarg3));
1752 LP64_ONLY(assert_different_registers(arg_2, c_rarg3));
1753 pass_arg3(this, arg_3);
1754 pass_arg2(this, arg_2);
1755 pass_arg1(this, arg_1);
1756 pass_arg0(this, arg_0);
1757 MacroAssembler::call_VM_leaf_base(entry_point, 4);
1758 }
1759
1760 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1761 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1762 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1763 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1764 }
1765
1766 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1767 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1768 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1769 }
1770
1771 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1772 }
1773
1774 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1775 }
1776
1777 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm, Register rscratch) {
1778 assert(rscratch != noreg || always_reachable(src1), "missing");
1779
1780 if (reachable(src1)) {
1781 cmpl(as_Address(src1), imm);
1782 } else {
1783 lea(rscratch, src1);
1784 cmpl(Address(rscratch, 0), imm);
1785 }
1786 }
1787
1788 void MacroAssembler::cmp32(Register src1, AddressLiteral src2, Register rscratch) {
1789 assert(!src2.is_lval(), "use cmpptr");
1790 assert(rscratch != noreg || always_reachable(src2), "missing");
1791
1792 if (reachable(src2)) {
1793 cmpl(src1, as_Address(src2));
1794 } else {
1795 lea(rscratch, src2);
1796 cmpl(src1, Address(rscratch, 0));
1797 }
1798 }
1799
1800 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1801 Assembler::cmpl(src1, imm);
1802 }
1803
1804 void MacroAssembler::cmp32(Register src1, Address src2) {
1805 Assembler::cmpl(src1, src2);
1806 }
1807
1808 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1809 ucomisd(opr1, opr2);
1810
1811 Label L;
1812 if (unordered_is_less) {
1813 movl(dst, -1);
1814 jcc(Assembler::parity, L);
1815 jcc(Assembler::below , L);
1816 movl(dst, 0);
1817 jcc(Assembler::equal , L);
1818 increment(dst);
1819 } else { // unordered is greater
1820 movl(dst, 1);
1821 jcc(Assembler::parity, L);
1822 jcc(Assembler::above , L);
1823 movl(dst, 0);
1824 jcc(Assembler::equal , L);
1825 decrementl(dst);
1826 }
1827 bind(L);
1828 }
1829
1830 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1831 ucomiss(opr1, opr2);
1832
1833 Label L;
1834 if (unordered_is_less) {
1835 movl(dst, -1);
1836 jcc(Assembler::parity, L);
1837 jcc(Assembler::below , L);
1838 movl(dst, 0);
1839 jcc(Assembler::equal , L);
1840 increment(dst);
1841 } else { // unordered is greater
1842 movl(dst, 1);
1843 jcc(Assembler::parity, L);
1844 jcc(Assembler::above , L);
1845 movl(dst, 0);
1846 jcc(Assembler::equal , L);
1847 decrementl(dst);
1848 }
1849 bind(L);
1850 }
1851
1852
1853 void MacroAssembler::cmp8(AddressLiteral src1, int imm, Register rscratch) {
1854 assert(rscratch != noreg || always_reachable(src1), "missing");
1855
1856 if (reachable(src1)) {
1857 cmpb(as_Address(src1), imm);
1858 } else {
1859 lea(rscratch, src1);
1860 cmpb(Address(rscratch, 0), imm);
1861 }
1862 }
1863
1864 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2, Register rscratch) {
1865 #ifdef _LP64
1866 assert(rscratch != noreg || always_reachable(src2), "missing");
1867
1868 if (src2.is_lval()) {
1869 movptr(rscratch, src2);
1870 Assembler::cmpq(src1, rscratch);
1871 } else if (reachable(src2)) {
1872 cmpq(src1, as_Address(src2));
1873 } else {
1874 lea(rscratch, src2);
1875 Assembler::cmpq(src1, Address(rscratch, 0));
1876 }
1877 #else
1878 assert(rscratch == noreg, "not needed");
1879 if (src2.is_lval()) {
1880 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1881 } else {
1882 cmpl(src1, as_Address(src2));
1883 }
1884 #endif // _LP64
1885 }
1886
1887 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2, Register rscratch) {
1888 assert(src2.is_lval(), "not a mem-mem compare");
1889 #ifdef _LP64
1890 // moves src2's literal address
1891 movptr(rscratch, src2);
1892 Assembler::cmpq(src1, rscratch);
1893 #else
1894 assert(rscratch == noreg, "not needed");
1895 cmp_literal32(src1, (int32_t)src2.target(), src2.rspec());
1896 #endif // _LP64
1897 }
1898
1899 void MacroAssembler::cmpoop(Register src1, Register src2) {
1900 cmpptr(src1, src2);
1901 }
1902
1903 void MacroAssembler::cmpoop(Register src1, Address src2) {
1904 cmpptr(src1, src2);
1905 }
1906
1907 #ifdef _LP64
1908 void MacroAssembler::cmpoop(Register src1, jobject src2, Register rscratch) {
1909 movoop(rscratch, src2);
1910 cmpptr(src1, rscratch);
1911 }
1912 #endif
1913
1914 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch) {
1915 assert(rscratch != noreg || always_reachable(adr), "missing");
1916
1917 if (reachable(adr)) {
1918 lock();
1919 cmpxchgptr(reg, as_Address(adr));
1920 } else {
1921 lea(rscratch, adr);
1922 lock();
1923 cmpxchgptr(reg, Address(rscratch, 0));
1924 }
1925 }
1926
1927 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1928 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1929 }
1930
1931 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
1932 assert(rscratch != noreg || always_reachable(src), "missing");
1933
1934 if (reachable(src)) {
1935 Assembler::comisd(dst, as_Address(src));
1936 } else {
1937 lea(rscratch, src);
1938 Assembler::comisd(dst, Address(rscratch, 0));
1939 }
1940 }
1941
1942 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
1943 assert(rscratch != noreg || always_reachable(src), "missing");
1944
1945 if (reachable(src)) {
1946 Assembler::comiss(dst, as_Address(src));
1947 } else {
1948 lea(rscratch, src);
1949 Assembler::comiss(dst, Address(rscratch, 0));
1950 }
1951 }
1952
1953
1954 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch) {
1955 assert(rscratch != noreg || always_reachable(counter_addr), "missing");
1956
1957 Condition negated_cond = negate_condition(cond);
1958 Label L;
1959 jcc(negated_cond, L);
1960 pushf(); // Preserve flags
1961 atomic_incl(counter_addr, rscratch);
1962 popf();
1963 bind(L);
1964 }
1965
1966 int MacroAssembler::corrected_idivl(Register reg) {
1967 // Full implementation of Java idiv and irem; checks for
1968 // special case as described in JVM spec., p.243 & p.271.
1969 // The function returns the (pc) offset of the idivl
1970 // instruction - may be needed for implicit exceptions.
1971 //
1972 // normal case special case
1973 //
1974 // input : rax,: dividend min_int
1975 // reg: divisor (may not be rax,/rdx) -1
1976 //
1977 // output: rax,: quotient (= rax, idiv reg) min_int
1978 // rdx: remainder (= rax, irem reg) 0
1979 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1980 const int min_int = 0x80000000;
1981 Label normal_case, special_case;
1982
1983 // check for special case
1984 cmpl(rax, min_int);
1985 jcc(Assembler::notEqual, normal_case);
1986 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1987 cmpl(reg, -1);
1988 jcc(Assembler::equal, special_case);
1989
1990 // handle normal case
1991 bind(normal_case);
1992 cdql();
1993 int idivl_offset = offset();
1994 idivl(reg);
1995
1996 // normal and special case exit
1997 bind(special_case);
1998
1999 return idivl_offset;
2000 }
2001
2002
2003
2004 void MacroAssembler::decrementl(Register reg, int value) {
2005 if (value == min_jint) {subl(reg, value) ; return; }
2006 if (value < 0) { incrementl(reg, -value); return; }
2007 if (value == 0) { ; return; }
2008 if (value == 1 && UseIncDec) { decl(reg) ; return; }
2009 /* else */ { subl(reg, value) ; return; }
2010 }
2011
2012 void MacroAssembler::decrementl(Address dst, int value) {
2013 if (value == min_jint) {subl(dst, value) ; return; }
2014 if (value < 0) { incrementl(dst, -value); return; }
2015 if (value == 0) { ; return; }
2016 if (value == 1 && UseIncDec) { decl(dst) ; return; }
2017 /* else */ { subl(dst, value) ; return; }
2018 }
2019
2020 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
2021 assert(shift_value > 0, "illegal shift value");
2022 Label _is_positive;
2023 testl (reg, reg);
2024 jcc (Assembler::positive, _is_positive);
2025 int offset = (1 << shift_value) - 1 ;
2026
2027 if (offset == 1) {
2028 incrementl(reg);
2029 } else {
2030 addl(reg, offset);
2031 }
2032
2033 bind (_is_positive);
2034 sarl(reg, shift_value);
2035 }
2036
2037 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2038 assert(rscratch != noreg || always_reachable(src), "missing");
2039
2040 if (reachable(src)) {
2041 Assembler::divsd(dst, as_Address(src));
2042 } else {
2043 lea(rscratch, src);
2044 Assembler::divsd(dst, Address(rscratch, 0));
2045 }
2046 }
2047
2048 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2049 assert(rscratch != noreg || always_reachable(src), "missing");
2050
2051 if (reachable(src)) {
2052 Assembler::divss(dst, as_Address(src));
2053 } else {
2054 lea(rscratch, src);
2055 Assembler::divss(dst, Address(rscratch, 0));
2056 }
2057 }
2058
2059 void MacroAssembler::enter() {
2060 push(rbp);
2061 mov(rbp, rsp);
2062 }
2063
2064 void MacroAssembler::post_call_nop() {
2065 if (!Continuations::enabled()) {
2066 return;
2067 }
2068 InstructionMark im(this);
2069 relocate(post_call_nop_Relocation::spec());
2070 InlineSkippedInstructionsCounter skipCounter(this);
2071 emit_int8((uint8_t)0x0f);
2072 emit_int8((uint8_t)0x1f);
2073 emit_int8((uint8_t)0x84);
2074 emit_int8((uint8_t)0x00);
2075 emit_int32(0x00);
2076 }
2077
2078 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2079 void MacroAssembler::fat_nop() {
2080 if (UseAddressNop) {
2081 addr_nop_5();
2082 } else {
2083 emit_int8((uint8_t)0x26); // es:
2084 emit_int8((uint8_t)0x2e); // cs:
2085 emit_int8((uint8_t)0x64); // fs:
2086 emit_int8((uint8_t)0x65); // gs:
2087 emit_int8((uint8_t)0x90);
2088 }
2089 }
2090
2091 #ifndef _LP64
2092 void MacroAssembler::fcmp(Register tmp) {
2093 fcmp(tmp, 1, true, true);
2094 }
2095
2096 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2097 assert(!pop_right || pop_left, "usage error");
2098 if (VM_Version::supports_cmov()) {
2099 assert(tmp == noreg, "unneeded temp");
2100 if (pop_left) {
2101 fucomip(index);
2102 } else {
2103 fucomi(index);
2104 }
2105 if (pop_right) {
2106 fpop();
2107 }
2108 } else {
2109 assert(tmp != noreg, "need temp");
2110 if (pop_left) {
2111 if (pop_right) {
2112 fcompp();
2113 } else {
2114 fcomp(index);
2115 }
2116 } else {
2117 fcom(index);
2118 }
2119 // convert FPU condition into eflags condition via rax,
2120 save_rax(tmp);
2121 fwait(); fnstsw_ax();
2122 sahf();
2123 restore_rax(tmp);
2124 }
2125 // condition codes set as follows:
2126 //
2127 // CF (corresponds to C0) if x < y
2128 // PF (corresponds to C2) if unordered
2129 // ZF (corresponds to C3) if x = y
2130 }
2131
2132 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2133 fcmp2int(dst, unordered_is_less, 1, true, true);
2134 }
2135
2136 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2137 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2138 Label L;
2139 if (unordered_is_less) {
2140 movl(dst, -1);
2141 jcc(Assembler::parity, L);
2142 jcc(Assembler::below , L);
2143 movl(dst, 0);
2144 jcc(Assembler::equal , L);
2145 increment(dst);
2146 } else { // unordered is greater
2147 movl(dst, 1);
2148 jcc(Assembler::parity, L);
2149 jcc(Assembler::above , L);
2150 movl(dst, 0);
2151 jcc(Assembler::equal , L);
2152 decrementl(dst);
2153 }
2154 bind(L);
2155 }
2156
2157 void MacroAssembler::fld_d(AddressLiteral src) {
2158 fld_d(as_Address(src));
2159 }
2160
2161 void MacroAssembler::fld_s(AddressLiteral src) {
2162 fld_s(as_Address(src));
2163 }
2164
2165 void MacroAssembler::fldcw(AddressLiteral src) {
2166 fldcw(as_Address(src));
2167 }
2168
2169 void MacroAssembler::fpop() {
2170 ffree();
2171 fincstp();
2172 }
2173
2174 void MacroAssembler::fremr(Register tmp) {
2175 save_rax(tmp);
2176 { Label L;
2177 bind(L);
2178 fprem();
2179 fwait(); fnstsw_ax();
2180 sahf();
2181 jcc(Assembler::parity, L);
2182 }
2183 restore_rax(tmp);
2184 // Result is in ST0.
2185 // Note: fxch & fpop to get rid of ST1
2186 // (otherwise FPU stack could overflow eventually)
2187 fxch(1);
2188 fpop();
2189 }
2190
2191 void MacroAssembler::empty_FPU_stack() {
2192 if (VM_Version::supports_mmx()) {
2193 emms();
2194 } else {
2195 for (int i = 8; i-- > 0; ) ffree(i);
2196 }
2197 }
2198 #endif // !LP64
2199
2200 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2201 assert(rscratch != noreg || always_reachable(src), "missing");
2202 if (reachable(src)) {
2203 Assembler::mulpd(dst, as_Address(src));
2204 } else {
2205 lea(rscratch, src);
2206 Assembler::mulpd(dst, Address(rscratch, 0));
2207 }
2208 }
2209
2210 void MacroAssembler::load_float(Address src) {
2211 #ifdef _LP64
2212 movflt(xmm0, src);
2213 #else
2214 if (UseSSE >= 1) {
2215 movflt(xmm0, src);
2216 } else {
2217 fld_s(src);
2218 }
2219 #endif // LP64
2220 }
2221
2222 void MacroAssembler::store_float(Address dst) {
2223 #ifdef _LP64
2224 movflt(dst, xmm0);
2225 #else
2226 if (UseSSE >= 1) {
2227 movflt(dst, xmm0);
2228 } else {
2229 fstp_s(dst);
2230 }
2231 #endif // LP64
2232 }
2233
2234 void MacroAssembler::load_double(Address src) {
2235 #ifdef _LP64
2236 movdbl(xmm0, src);
2237 #else
2238 if (UseSSE >= 2) {
2239 movdbl(xmm0, src);
2240 } else {
2241 fld_d(src);
2242 }
2243 #endif // LP64
2244 }
2245
2246 void MacroAssembler::store_double(Address dst) {
2247 #ifdef _LP64
2248 movdbl(dst, xmm0);
2249 #else
2250 if (UseSSE >= 2) {
2251 movdbl(dst, xmm0);
2252 } else {
2253 fstp_d(dst);
2254 }
2255 #endif // LP64
2256 }
2257
2258 // dst = c = a * b + c
2259 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2260 Assembler::vfmadd231sd(c, a, b);
2261 if (dst != c) {
2262 movdbl(dst, c);
2263 }
2264 }
2265
2266 // dst = c = a * b + c
2267 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2268 Assembler::vfmadd231ss(c, a, b);
2269 if (dst != c) {
2270 movflt(dst, c);
2271 }
2272 }
2273
2274 // dst = c = a * b + c
2275 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2276 Assembler::vfmadd231pd(c, a, b, vector_len);
2277 if (dst != c) {
2278 vmovdqu(dst, c);
2279 }
2280 }
2281
2282 // dst = c = a * b + c
2283 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2284 Assembler::vfmadd231ps(c, a, b, vector_len);
2285 if (dst != c) {
2286 vmovdqu(dst, c);
2287 }
2288 }
2289
2290 // dst = c = a * b + c
2291 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2292 Assembler::vfmadd231pd(c, a, b, vector_len);
2293 if (dst != c) {
2294 vmovdqu(dst, c);
2295 }
2296 }
2297
2298 // dst = c = a * b + c
2299 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2300 Assembler::vfmadd231ps(c, a, b, vector_len);
2301 if (dst != c) {
2302 vmovdqu(dst, c);
2303 }
2304 }
2305
2306 void MacroAssembler::incrementl(AddressLiteral dst, Register rscratch) {
2307 assert(rscratch != noreg || always_reachable(dst), "missing");
2308
2309 if (reachable(dst)) {
2310 incrementl(as_Address(dst));
2311 } else {
2312 lea(rscratch, dst);
2313 incrementl(Address(rscratch, 0));
2314 }
2315 }
2316
2317 void MacroAssembler::incrementl(ArrayAddress dst, Register rscratch) {
2318 incrementl(as_Address(dst, rscratch));
2319 }
2320
2321 void MacroAssembler::incrementl(Register reg, int value) {
2322 if (value == min_jint) {addl(reg, value) ; return; }
2323 if (value < 0) { decrementl(reg, -value); return; }
2324 if (value == 0) { ; return; }
2325 if (value == 1 && UseIncDec) { incl(reg) ; return; }
2326 /* else */ { addl(reg, value) ; return; }
2327 }
2328
2329 void MacroAssembler::incrementl(Address dst, int value) {
2330 if (value == min_jint) {addl(dst, value) ; return; }
2331 if (value < 0) { decrementl(dst, -value); return; }
2332 if (value == 0) { ; return; }
2333 if (value == 1 && UseIncDec) { incl(dst) ; return; }
2334 /* else */ { addl(dst, value) ; return; }
2335 }
2336
2337 void MacroAssembler::jump(AddressLiteral dst, Register rscratch) {
2338 assert(rscratch != noreg || always_reachable(dst), "missing");
2339
2340 if (reachable(dst)) {
2341 jmp_literal(dst.target(), dst.rspec());
2342 } else {
2343 lea(rscratch, dst);
2344 jmp(rscratch);
2345 }
2346 }
2347
2348 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst, Register rscratch) {
2349 assert(rscratch != noreg || always_reachable(dst), "missing");
2350
2351 if (reachable(dst)) {
2352 InstructionMark im(this);
2353 relocate(dst.reloc());
2354 const int short_size = 2;
2355 const int long_size = 6;
2356 int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2357 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2358 // 0111 tttn #8-bit disp
2359 emit_int8(0x70 | cc);
2360 emit_int8((offs - short_size) & 0xFF);
2361 } else {
2362 // 0000 1111 1000 tttn #32-bit disp
2363 emit_int8(0x0F);
2364 emit_int8((unsigned char)(0x80 | cc));
2365 emit_int32(offs - long_size);
2366 }
2367 } else {
2368 #ifdef ASSERT
2369 warning("reversing conditional branch");
2370 #endif /* ASSERT */
2371 Label skip;
2372 jccb(reverse[cc], skip);
2373 lea(rscratch, dst);
2374 Assembler::jmp(rscratch);
2375 bind(skip);
2376 }
2377 }
2378
2379 void MacroAssembler::ldmxcsr(AddressLiteral src, Register rscratch) {
2380 assert(rscratch != noreg || always_reachable(src), "missing");
2381
2382 if (reachable(src)) {
2383 Assembler::ldmxcsr(as_Address(src));
2384 } else {
2385 lea(rscratch, src);
2386 Assembler::ldmxcsr(Address(rscratch, 0));
2387 }
2388 }
2389
2390 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2391 int off;
2392 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2393 off = offset();
2394 movsbl(dst, src); // movsxb
2395 } else {
2396 off = load_unsigned_byte(dst, src);
2397 shll(dst, 24);
2398 sarl(dst, 24);
2399 }
2400 return off;
2401 }
2402
2403 // Note: load_signed_short used to be called load_signed_word.
2404 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2405 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2406 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2407 int MacroAssembler::load_signed_short(Register dst, Address src) {
2408 int off;
2409 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2410 // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2411 // version but this is what 64bit has always done. This seems to imply
2412 // that users are only using 32bits worth.
2413 off = offset();
2414 movswl(dst, src); // movsxw
2415 } else {
2416 off = load_unsigned_short(dst, src);
2417 shll(dst, 16);
2418 sarl(dst, 16);
2419 }
2420 return off;
2421 }
2422
2423 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2424 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2425 // and "3.9 Partial Register Penalties", p. 22).
2426 int off;
2427 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2428 off = offset();
2429 movzbl(dst, src); // movzxb
2430 } else {
2431 xorl(dst, dst);
2432 off = offset();
2433 movb(dst, src);
2434 }
2435 return off;
2436 }
2437
2438 // Note: load_unsigned_short used to be called load_unsigned_word.
2439 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2440 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2441 // and "3.9 Partial Register Penalties", p. 22).
2442 int off;
2443 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2444 off = offset();
2445 movzwl(dst, src); // movzxw
2446 } else {
2447 xorl(dst, dst);
2448 off = offset();
2449 movw(dst, src);
2450 }
2451 return off;
2452 }
2453
2454 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2455 switch (size_in_bytes) {
2456 #ifndef _LP64
2457 case 8:
2458 assert(dst2 != noreg, "second dest register required");
2459 movl(dst, src);
2460 movl(dst2, src.plus_disp(BytesPerInt));
2461 break;
2462 #else
2463 case 8: movq(dst, src); break;
2464 #endif
2465 case 4: movl(dst, src); break;
2466 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2467 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2468 default: ShouldNotReachHere();
2469 }
2470 }
2471
2472 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2473 switch (size_in_bytes) {
2474 #ifndef _LP64
2475 case 8:
2476 assert(src2 != noreg, "second source register required");
2477 movl(dst, src);
2478 movl(dst.plus_disp(BytesPerInt), src2);
2479 break;
2480 #else
2481 case 8: movq(dst, src); break;
2482 #endif
2483 case 4: movl(dst, src); break;
2484 case 2: movw(dst, src); break;
2485 case 1: movb(dst, src); break;
2486 default: ShouldNotReachHere();
2487 }
2488 }
2489
2490 void MacroAssembler::mov32(AddressLiteral dst, Register src, Register rscratch) {
2491 assert(rscratch != noreg || always_reachable(dst), "missing");
2492
2493 if (reachable(dst)) {
2494 movl(as_Address(dst), src);
2495 } else {
2496 lea(rscratch, dst);
2497 movl(Address(rscratch, 0), src);
2498 }
2499 }
2500
2501 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2502 if (reachable(src)) {
2503 movl(dst, as_Address(src));
2504 } else {
2505 lea(dst, src);
2506 movl(dst, Address(dst, 0));
2507 }
2508 }
2509
2510 // C++ bool manipulation
2511
2512 void MacroAssembler::movbool(Register dst, Address src) {
2513 if(sizeof(bool) == 1)
2514 movb(dst, src);
2515 else if(sizeof(bool) == 2)
2516 movw(dst, src);
2517 else if(sizeof(bool) == 4)
2518 movl(dst, src);
2519 else
2520 // unsupported
2521 ShouldNotReachHere();
2522 }
2523
2524 void MacroAssembler::movbool(Address dst, bool boolconst) {
2525 if(sizeof(bool) == 1)
2526 movb(dst, (int) boolconst);
2527 else if(sizeof(bool) == 2)
2528 movw(dst, (int) boolconst);
2529 else if(sizeof(bool) == 4)
2530 movl(dst, (int) boolconst);
2531 else
2532 // unsupported
2533 ShouldNotReachHere();
2534 }
2535
2536 void MacroAssembler::movbool(Address dst, Register src) {
2537 if(sizeof(bool) == 1)
2538 movb(dst, src);
2539 else if(sizeof(bool) == 2)
2540 movw(dst, src);
2541 else if(sizeof(bool) == 4)
2542 movl(dst, src);
2543 else
2544 // unsupported
2545 ShouldNotReachHere();
2546 }
2547
2548 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2549 assert(rscratch != noreg || always_reachable(src), "missing");
2550
2551 if (reachable(src)) {
2552 movdl(dst, as_Address(src));
2553 } else {
2554 lea(rscratch, src);
2555 movdl(dst, Address(rscratch, 0));
2556 }
2557 }
2558
2559 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src, Register rscratch) {
2560 assert(rscratch != noreg || always_reachable(src), "missing");
2561
2562 if (reachable(src)) {
2563 movq(dst, as_Address(src));
2564 } else {
2565 lea(rscratch, src);
2566 movq(dst, Address(rscratch, 0));
2567 }
2568 }
2569
2570 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src, Register rscratch) {
2571 assert(rscratch != noreg || always_reachable(src), "missing");
2572
2573 if (reachable(src)) {
2574 if (UseXmmLoadAndClearUpper) {
2575 movsd (dst, as_Address(src));
2576 } else {
2577 movlpd(dst, as_Address(src));
2578 }
2579 } else {
2580 lea(rscratch, src);
2581 if (UseXmmLoadAndClearUpper) {
2582 movsd (dst, Address(rscratch, 0));
2583 } else {
2584 movlpd(dst, Address(rscratch, 0));
2585 }
2586 }
2587 }
2588
2589 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src, Register rscratch) {
2590 assert(rscratch != noreg || always_reachable(src), "missing");
2591
2592 if (reachable(src)) {
2593 movss(dst, as_Address(src));
2594 } else {
2595 lea(rscratch, src);
2596 movss(dst, Address(rscratch, 0));
2597 }
2598 }
2599
2600 void MacroAssembler::movptr(Register dst, Register src) {
2601 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2602 }
2603
2604 void MacroAssembler::movptr(Register dst, Address src) {
2605 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2606 }
2607
2608 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2609 void MacroAssembler::movptr(Register dst, intptr_t src) {
2610 #ifdef _LP64
2611 if (is_uimm32(src)) {
2612 movl(dst, checked_cast<uint32_t>(src));
2613 } else if (is_simm32(src)) {
2614 movq(dst, checked_cast<int32_t>(src));
2615 } else {
2616 mov64(dst, src);
2617 }
2618 #else
2619 movl(dst, src);
2620 #endif
2621 }
2622
2623 void MacroAssembler::movptr(Address dst, Register src) {
2624 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2625 }
2626
2627 void MacroAssembler::movptr(Address dst, int32_t src) {
2628 LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src));
2629 }
2630
2631 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2632 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2633 Assembler::movdqu(dst, src);
2634 }
2635
2636 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2637 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2638 Assembler::movdqu(dst, src);
2639 }
2640
2641 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2642 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2643 Assembler::movdqu(dst, src);
2644 }
2645
2646 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2647 assert(rscratch != noreg || always_reachable(src), "missing");
2648
2649 if (reachable(src)) {
2650 movdqu(dst, as_Address(src));
2651 } else {
2652 lea(rscratch, src);
2653 movdqu(dst, Address(rscratch, 0));
2654 }
2655 }
2656
2657 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2658 assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2659 Assembler::vmovdqu(dst, src);
2660 }
2661
2662 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2663 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2664 Assembler::vmovdqu(dst, src);
2665 }
2666
2667 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2668 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2669 Assembler::vmovdqu(dst, src);
2670 }
2671
2672 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register rscratch) {
2673 assert(rscratch != noreg || always_reachable(src), "missing");
2674
2675 if (reachable(src)) {
2676 vmovdqu(dst, as_Address(src));
2677 }
2678 else {
2679 lea(rscratch, src);
2680 vmovdqu(dst, Address(rscratch, 0));
2681 }
2682 }
2683
2684 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2685 assert(rscratch != noreg || always_reachable(src), "missing");
2686
2687 if (vector_len == AVX_512bit) {
2688 evmovdquq(dst, src, AVX_512bit, rscratch);
2689 } else if (vector_len == AVX_256bit) {
2690 vmovdqu(dst, src, rscratch);
2691 } else {
2692 movdqu(dst, src, rscratch);
2693 }
2694 }
2695
2696 void MacroAssembler::kmov(KRegister dst, Address src) {
2697 if (VM_Version::supports_avx512bw()) {
2698 kmovql(dst, src);
2699 } else {
2700 assert(VM_Version::supports_evex(), "");
2701 kmovwl(dst, src);
2702 }
2703 }
2704
2705 void MacroAssembler::kmov(Address dst, KRegister src) {
2706 if (VM_Version::supports_avx512bw()) {
2707 kmovql(dst, src);
2708 } else {
2709 assert(VM_Version::supports_evex(), "");
2710 kmovwl(dst, src);
2711 }
2712 }
2713
2714 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2715 if (VM_Version::supports_avx512bw()) {
2716 kmovql(dst, src);
2717 } else {
2718 assert(VM_Version::supports_evex(), "");
2719 kmovwl(dst, src);
2720 }
2721 }
2722
2723 void MacroAssembler::kmov(Register dst, KRegister src) {
2724 if (VM_Version::supports_avx512bw()) {
2725 kmovql(dst, src);
2726 } else {
2727 assert(VM_Version::supports_evex(), "");
2728 kmovwl(dst, src);
2729 }
2730 }
2731
2732 void MacroAssembler::kmov(KRegister dst, Register src) {
2733 if (VM_Version::supports_avx512bw()) {
2734 kmovql(dst, src);
2735 } else {
2736 assert(VM_Version::supports_evex(), "");
2737 kmovwl(dst, src);
2738 }
2739 }
2740
2741 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register rscratch) {
2742 assert(rscratch != noreg || always_reachable(src), "missing");
2743
2744 if (reachable(src)) {
2745 kmovql(dst, as_Address(src));
2746 } else {
2747 lea(rscratch, src);
2748 kmovql(dst, Address(rscratch, 0));
2749 }
2750 }
2751
2752 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register rscratch) {
2753 assert(rscratch != noreg || always_reachable(src), "missing");
2754
2755 if (reachable(src)) {
2756 kmovwl(dst, as_Address(src));
2757 } else {
2758 lea(rscratch, src);
2759 kmovwl(dst, Address(rscratch, 0));
2760 }
2761 }
2762
2763 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2764 int vector_len, Register rscratch) {
2765 assert(rscratch != noreg || always_reachable(src), "missing");
2766
2767 if (reachable(src)) {
2768 Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2769 } else {
2770 lea(rscratch, src);
2771 Assembler::evmovdqub(dst, mask, Address(rscratch, 0), merge, vector_len);
2772 }
2773 }
2774
2775 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2776 int vector_len, Register rscratch) {
2777 assert(rscratch != noreg || always_reachable(src), "missing");
2778
2779 if (reachable(src)) {
2780 Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2781 } else {
2782 lea(rscratch, src);
2783 Assembler::evmovdquw(dst, mask, Address(rscratch, 0), merge, vector_len);
2784 }
2785 }
2786
2787 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2788 assert(rscratch != noreg || always_reachable(src), "missing");
2789
2790 if (reachable(src)) {
2791 Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2792 } else {
2793 lea(rscratch, src);
2794 Assembler::evmovdqul(dst, mask, Address(rscratch, 0), merge, vector_len);
2795 }
2796 }
2797
2798 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
2799 assert(rscratch != noreg || always_reachable(src), "missing");
2800
2801 if (reachable(src)) {
2802 Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2803 } else {
2804 lea(rscratch, src);
2805 Assembler::evmovdquq(dst, mask, Address(rscratch, 0), merge, vector_len);
2806 }
2807 }
2808
2809 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2810 assert(rscratch != noreg || always_reachable(src), "missing");
2811
2812 if (reachable(src)) {
2813 Assembler::evmovdquq(dst, as_Address(src), vector_len);
2814 } else {
2815 lea(rscratch, src);
2816 Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2817 }
2818 }
2819
2820 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src, Register rscratch) {
2821 assert(rscratch != noreg || always_reachable(src), "missing");
2822
2823 if (reachable(src)) {
2824 Assembler::movdqa(dst, as_Address(src));
2825 } else {
2826 lea(rscratch, src);
2827 Assembler::movdqa(dst, Address(rscratch, 0));
2828 }
2829 }
2830
2831 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2832 assert(rscratch != noreg || always_reachable(src), "missing");
2833
2834 if (reachable(src)) {
2835 Assembler::movsd(dst, as_Address(src));
2836 } else {
2837 lea(rscratch, src);
2838 Assembler::movsd(dst, Address(rscratch, 0));
2839 }
2840 }
2841
2842 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2843 assert(rscratch != noreg || always_reachable(src), "missing");
2844
2845 if (reachable(src)) {
2846 Assembler::movss(dst, as_Address(src));
2847 } else {
2848 lea(rscratch, src);
2849 Assembler::movss(dst, Address(rscratch, 0));
2850 }
2851 }
2852
2853 void MacroAssembler::movddup(XMMRegister dst, AddressLiteral src, Register rscratch) {
2854 assert(rscratch != noreg || always_reachable(src), "missing");
2855
2856 if (reachable(src)) {
2857 Assembler::movddup(dst, as_Address(src));
2858 } else {
2859 lea(rscratch, src);
2860 Assembler::movddup(dst, Address(rscratch, 0));
2861 }
2862 }
2863
2864 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2865 assert(rscratch != noreg || always_reachable(src), "missing");
2866
2867 if (reachable(src)) {
2868 Assembler::vmovddup(dst, as_Address(src), vector_len);
2869 } else {
2870 lea(rscratch, src);
2871 Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2872 }
2873 }
2874
2875 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
2876 assert(rscratch != noreg || always_reachable(src), "missing");
2877
2878 if (reachable(src)) {
2879 Assembler::mulsd(dst, as_Address(src));
2880 } else {
2881 lea(rscratch, src);
2882 Assembler::mulsd(dst, Address(rscratch, 0));
2883 }
2884 }
2885
2886 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src, Register rscratch) {
2887 assert(rscratch != noreg || always_reachable(src), "missing");
2888
2889 if (reachable(src)) {
2890 Assembler::mulss(dst, as_Address(src));
2891 } else {
2892 lea(rscratch, src);
2893 Assembler::mulss(dst, Address(rscratch, 0));
2894 }
2895 }
2896
2897 void MacroAssembler::null_check(Register reg, int offset) {
2898 if (needs_explicit_null_check(offset)) {
2899 // provoke OS null exception if reg is null by
2900 // accessing M[reg] w/o changing any (non-CC) registers
2901 // NOTE: cmpl is plenty here to provoke a segv
2902 cmpptr(rax, Address(reg, 0));
2903 // Note: should probably use testl(rax, Address(reg, 0));
2904 // may be shorter code (however, this version of
2905 // testl needs to be implemented first)
2906 } else {
2907 // nothing to do, (later) access of M[reg + offset]
2908 // will provoke OS null exception if reg is null
2909 }
2910 }
2911
2912 void MacroAssembler::os_breakpoint() {
2913 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2914 // (e.g., MSVC can't call ps() otherwise)
2915 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2916 }
2917
2918 void MacroAssembler::unimplemented(const char* what) {
2919 const char* buf = nullptr;
2920 {
2921 ResourceMark rm;
2922 stringStream ss;
2923 ss.print("unimplemented: %s", what);
2924 buf = code_string(ss.as_string());
2925 }
2926 stop(buf);
2927 }
2928
2929 #ifdef _LP64
2930 #define XSTATE_BV 0x200
2931 #endif
2932
2933 void MacroAssembler::pop_CPU_state() {
2934 pop_FPU_state();
2935 pop_IU_state();
2936 }
2937
2938 void MacroAssembler::pop_FPU_state() {
2939 #ifndef _LP64
2940 frstor(Address(rsp, 0));
2941 #else
2942 fxrstor(Address(rsp, 0));
2943 #endif
2944 addptr(rsp, FPUStateSizeInWords * wordSize);
2945 }
2946
2947 void MacroAssembler::pop_IU_state() {
2948 popa();
2949 LP64_ONLY(addq(rsp, 8));
2950 popf();
2951 }
2952
2953 // Save Integer and Float state
2954 // Warning: Stack must be 16 byte aligned (64bit)
2955 void MacroAssembler::push_CPU_state() {
2956 push_IU_state();
2957 push_FPU_state();
2958 }
2959
2960 void MacroAssembler::push_FPU_state() {
2961 subptr(rsp, FPUStateSizeInWords * wordSize);
2962 #ifndef _LP64
2963 fnsave(Address(rsp, 0));
2964 fwait();
2965 #else
2966 fxsave(Address(rsp, 0));
2967 #endif // LP64
2968 }
2969
2970 void MacroAssembler::push_IU_state() {
2971 // Push flags first because pusha kills them
2972 pushf();
2973 // Make sure rsp stays 16-byte aligned
2974 LP64_ONLY(subq(rsp, 8));
2975 pusha();
2976 }
2977
2978 void MacroAssembler::push_cont_fastpath() {
2979 if (!Continuations::enabled()) return;
2980
2981 #ifndef _LP64
2982 Register rthread = rax;
2983 Register rrealsp = rbx;
2984 push(rthread);
2985 push(rrealsp);
2986
2987 get_thread(rthread);
2988
2989 // The code below wants the original RSP.
2990 // Move it back after the pushes above.
2991 movptr(rrealsp, rsp);
2992 addptr(rrealsp, 2*wordSize);
2993 #else
2994 Register rthread = r15_thread;
2995 Register rrealsp = rsp;
2996 #endif
2997
2998 Label done;
2999 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3000 jccb(Assembler::belowEqual, done);
3001 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), rrealsp);
3002 bind(done);
3003
3004 #ifndef _LP64
3005 pop(rrealsp);
3006 pop(rthread);
3007 #endif
3008 }
3009
3010 void MacroAssembler::pop_cont_fastpath() {
3011 if (!Continuations::enabled()) return;
3012
3013 #ifndef _LP64
3014 Register rthread = rax;
3015 Register rrealsp = rbx;
3016 push(rthread);
3017 push(rrealsp);
3018
3019 get_thread(rthread);
3020
3021 // The code below wants the original RSP.
3022 // Move it back after the pushes above.
3023 movptr(rrealsp, rsp);
3024 addptr(rrealsp, 2*wordSize);
3025 #else
3026 Register rthread = r15_thread;
3027 Register rrealsp = rsp;
3028 #endif
3029
3030 Label done;
3031 cmpptr(rrealsp, Address(rthread, JavaThread::cont_fastpath_offset()));
3032 jccb(Assembler::below, done);
3033 movptr(Address(rthread, JavaThread::cont_fastpath_offset()), 0);
3034 bind(done);
3035
3036 #ifndef _LP64
3037 pop(rrealsp);
3038 pop(rthread);
3039 #endif
3040 }
3041
3042 void MacroAssembler::inc_held_monitor_count() {
3043 #ifndef _LP64
3044 Register thread = rax;
3045 push(thread);
3046 get_thread(thread);
3047 incrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3048 pop(thread);
3049 #else // LP64
3050 incrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3051 #endif
3052 }
3053
3054 void MacroAssembler::dec_held_monitor_count() {
3055 #ifndef _LP64
3056 Register thread = rax;
3057 push(thread);
3058 get_thread(thread);
3059 decrementl(Address(thread, JavaThread::held_monitor_count_offset()));
3060 pop(thread);
3061 #else // LP64
3062 decrementq(Address(r15_thread, JavaThread::held_monitor_count_offset()));
3063 #endif
3064 }
3065
3066 #ifdef ASSERT
3067 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
3068 #ifdef _LP64
3069 Label no_cont;
3070 movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
3071 testl(cont, cont);
3072 jcc(Assembler::zero, no_cont);
3073 stop(name);
3074 bind(no_cont);
3075 #else
3076 Unimplemented();
3077 #endif
3078 }
3079 #endif
3080
3081 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
3082 if (!java_thread->is_valid()) {
3083 java_thread = rdi;
3084 get_thread(java_thread);
3085 }
3086 // we must set sp to zero to clear frame
3087 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
3088 // must clear fp, so that compiled frames are not confused; it is
3089 // possible that we need it only for debugging
3090 if (clear_fp) {
3091 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
3092 }
3093 // Always clear the pc because it could have been set by make_walkable()
3094 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
3095 vzeroupper();
3096 }
3097
3098 void MacroAssembler::restore_rax(Register tmp) {
3099 if (tmp == noreg) pop(rax);
3100 else if (tmp != rax) mov(rax, tmp);
3101 }
3102
3103 void MacroAssembler::round_to(Register reg, int modulus) {
3104 addptr(reg, modulus - 1);
3105 andptr(reg, -modulus);
3106 }
3107
3108 void MacroAssembler::save_rax(Register tmp) {
3109 if (tmp == noreg) push(rax);
3110 else if (tmp != rax) mov(tmp, rax);
3111 }
3112
3113 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
3114 if (at_return) {
3115 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
3116 // we may safely use rsp instead to perform the stack watermark check.
3117 cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
3118 jcc(Assembler::above, slow_path);
3119 return;
3120 }
3121 testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
3122 jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
3123 }
3124
3125 // Calls to C land
3126 //
3127 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
3128 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
3129 // has to be reset to 0. This is required to allow proper stack traversal.
3130 void MacroAssembler::set_last_Java_frame(Register java_thread,
3131 Register last_java_sp,
3132 Register last_java_fp,
3133 address last_java_pc,
3134 Register rscratch) {
3135 vzeroupper();
3136 // determine java_thread register
3137 if (!java_thread->is_valid()) {
3138 java_thread = rdi;
3139 get_thread(java_thread);
3140 }
3141 // determine last_java_sp register
3142 if (!last_java_sp->is_valid()) {
3143 last_java_sp = rsp;
3144 }
3145 // last_java_fp is optional
3146 if (last_java_fp->is_valid()) {
3147 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3148 }
3149 // last_java_pc is optional
3150 if (last_java_pc != nullptr) {
3151 Address java_pc(java_thread,
3152 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
3153 lea(java_pc, InternalAddress(last_java_pc), rscratch);
3154 }
3155 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3156 }
3157
3158 void MacroAssembler::shlptr(Register dst, int imm8) {
3159 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3160 }
3161
3162 void MacroAssembler::shrptr(Register dst, int imm8) {
3163 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3164 }
3165
3166 void MacroAssembler::sign_extend_byte(Register reg) {
3167 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3168 movsbl(reg, reg); // movsxb
3169 } else {
3170 shll(reg, 24);
3171 sarl(reg, 24);
3172 }
3173 }
3174
3175 void MacroAssembler::sign_extend_short(Register reg) {
3176 if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3177 movswl(reg, reg); // movsxw
3178 } else {
3179 shll(reg, 16);
3180 sarl(reg, 16);
3181 }
3182 }
3183
3184 void MacroAssembler::testl(Address dst, int32_t imm32) {
3185 if (imm32 >= 0 && is8bit(imm32)) {
3186 testb(dst, imm32);
3187 } else {
3188 Assembler::testl(dst, imm32);
3189 }
3190 }
3191
3192 void MacroAssembler::testl(Register dst, int32_t imm32) {
3193 if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
3194 testb(dst, imm32);
3195 } else {
3196 Assembler::testl(dst, imm32);
3197 }
3198 }
3199
3200 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3201 assert(always_reachable(src), "Address should be reachable");
3202 testl(dst, as_Address(src));
3203 }
3204
3205 #ifdef _LP64
3206
3207 void MacroAssembler::testq(Address dst, int32_t imm32) {
3208 if (imm32 >= 0) {
3209 testl(dst, imm32);
3210 } else {
3211 Assembler::testq(dst, imm32);
3212 }
3213 }
3214
3215 void MacroAssembler::testq(Register dst, int32_t imm32) {
3216 if (imm32 >= 0) {
3217 testl(dst, imm32);
3218 } else {
3219 Assembler::testq(dst, imm32);
3220 }
3221 }
3222
3223 #endif
3224
3225 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3226 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3227 Assembler::pcmpeqb(dst, src);
3228 }
3229
3230 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3231 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3232 Assembler::pcmpeqw(dst, src);
3233 }
3234
3235 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3236 assert((dst->encoding() < 16),"XMM register should be 0-15");
3237 Assembler::pcmpestri(dst, src, imm8);
3238 }
3239
3240 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3241 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3242 Assembler::pcmpestri(dst, src, imm8);
3243 }
3244
3245 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3246 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3247 Assembler::pmovzxbw(dst, src);
3248 }
3249
3250 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3251 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3252 Assembler::pmovzxbw(dst, src);
3253 }
3254
3255 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3256 assert((src->encoding() < 16),"XMM register should be 0-15");
3257 Assembler::pmovmskb(dst, src);
3258 }
3259
3260 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3261 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3262 Assembler::ptest(dst, src);
3263 }
3264
3265 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3266 assert(rscratch != noreg || always_reachable(src), "missing");
3267
3268 if (reachable(src)) {
3269 Assembler::sqrtss(dst, as_Address(src));
3270 } else {
3271 lea(rscratch, src);
3272 Assembler::sqrtss(dst, Address(rscratch, 0));
3273 }
3274 }
3275
3276 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3277 assert(rscratch != noreg || always_reachable(src), "missing");
3278
3279 if (reachable(src)) {
3280 Assembler::subsd(dst, as_Address(src));
3281 } else {
3282 lea(rscratch, src);
3283 Assembler::subsd(dst, Address(rscratch, 0));
3284 }
3285 }
3286
3287 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch) {
3288 assert(rscratch != noreg || always_reachable(src), "missing");
3289
3290 if (reachable(src)) {
3291 Assembler::roundsd(dst, as_Address(src), rmode);
3292 } else {
3293 lea(rscratch, src);
3294 Assembler::roundsd(dst, Address(rscratch, 0), rmode);
3295 }
3296 }
3297
3298 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3299 assert(rscratch != noreg || always_reachable(src), "missing");
3300
3301 if (reachable(src)) {
3302 Assembler::subss(dst, as_Address(src));
3303 } else {
3304 lea(rscratch, src);
3305 Assembler::subss(dst, Address(rscratch, 0));
3306 }
3307 }
3308
3309 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3310 assert(rscratch != noreg || always_reachable(src), "missing");
3311
3312 if (reachable(src)) {
3313 Assembler::ucomisd(dst, as_Address(src));
3314 } else {
3315 lea(rscratch, src);
3316 Assembler::ucomisd(dst, Address(rscratch, 0));
3317 }
3318 }
3319
3320 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch) {
3321 assert(rscratch != noreg || always_reachable(src), "missing");
3322
3323 if (reachable(src)) {
3324 Assembler::ucomiss(dst, as_Address(src));
3325 } else {
3326 lea(rscratch, src);
3327 Assembler::ucomiss(dst, Address(rscratch, 0));
3328 }
3329 }
3330
3331 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register rscratch) {
3332 assert(rscratch != noreg || always_reachable(src), "missing");
3333
3334 // Used in sign-bit flipping with aligned address.
3335 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3336 if (reachable(src)) {
3337 Assembler::xorpd(dst, as_Address(src));
3338 } else {
3339 lea(rscratch, src);
3340 Assembler::xorpd(dst, Address(rscratch, 0));
3341 }
3342 }
3343
3344 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3345 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3346 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3347 }
3348 else {
3349 Assembler::xorpd(dst, src);
3350 }
3351 }
3352
3353 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3354 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3355 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3356 } else {
3357 Assembler::xorps(dst, src);
3358 }
3359 }
3360
3361 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register rscratch) {
3362 assert(rscratch != noreg || always_reachable(src), "missing");
3363
3364 // Used in sign-bit flipping with aligned address.
3365 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3366 if (reachable(src)) {
3367 Assembler::xorps(dst, as_Address(src));
3368 } else {
3369 lea(rscratch, src);
3370 Assembler::xorps(dst, Address(rscratch, 0));
3371 }
3372 }
3373
3374 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src, Register rscratch) {
3375 assert(rscratch != noreg || always_reachable(src), "missing");
3376
3377 // Used in sign-bit flipping with aligned address.
3378 bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3379 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3380 if (reachable(src)) {
3381 Assembler::pshufb(dst, as_Address(src));
3382 } else {
3383 lea(rscratch, src);
3384 Assembler::pshufb(dst, Address(rscratch, 0));
3385 }
3386 }
3387
3388 // AVX 3-operands instructions
3389
3390 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3391 assert(rscratch != noreg || always_reachable(src), "missing");
3392
3393 if (reachable(src)) {
3394 vaddsd(dst, nds, as_Address(src));
3395 } else {
3396 lea(rscratch, src);
3397 vaddsd(dst, nds, Address(rscratch, 0));
3398 }
3399 }
3400
3401 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3402 assert(rscratch != noreg || always_reachable(src), "missing");
3403
3404 if (reachable(src)) {
3405 vaddss(dst, nds, as_Address(src));
3406 } else {
3407 lea(rscratch, src);
3408 vaddss(dst, nds, Address(rscratch, 0));
3409 }
3410 }
3411
3412 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3413 assert(UseAVX > 0, "requires some form of AVX");
3414 assert(rscratch != noreg || always_reachable(src), "missing");
3415
3416 if (reachable(src)) {
3417 Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3418 } else {
3419 lea(rscratch, src);
3420 Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3421 }
3422 }
3423
3424 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3425 assert(UseAVX > 0, "requires some form of AVX");
3426 assert(rscratch != noreg || always_reachable(src), "missing");
3427
3428 if (reachable(src)) {
3429 Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3430 } else {
3431 lea(rscratch, src);
3432 Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3433 }
3434 }
3435
3436 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3437 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3438 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3439
3440 vandps(dst, nds, negate_field, vector_len, rscratch);
3441 }
3442
3443 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch) {
3444 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3445 assert(rscratch != noreg || always_reachable(negate_field), "missing");
3446
3447 vandpd(dst, nds, negate_field, vector_len, rscratch);
3448 }
3449
3450 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3451 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3452 Assembler::vpaddb(dst, nds, src, vector_len);
3453 }
3454
3455 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3456 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3457 Assembler::vpaddb(dst, nds, src, vector_len);
3458 }
3459
3460 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3461 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3462 Assembler::vpaddw(dst, nds, src, vector_len);
3463 }
3464
3465 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3466 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3467 Assembler::vpaddw(dst, nds, src, vector_len);
3468 }
3469
3470 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3471 assert(rscratch != noreg || always_reachable(src), "missing");
3472
3473 if (reachable(src)) {
3474 Assembler::vpand(dst, nds, as_Address(src), vector_len);
3475 } else {
3476 lea(rscratch, src);
3477 Assembler::vpand(dst, nds, Address(rscratch, 0), vector_len);
3478 }
3479 }
3480
3481 void MacroAssembler::vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3482 assert(rscratch != noreg || always_reachable(src), "missing");
3483
3484 if (reachable(src)) {
3485 Assembler::vpbroadcastd(dst, as_Address(src), vector_len);
3486 } else {
3487 lea(rscratch, src);
3488 Assembler::vpbroadcastd(dst, Address(rscratch, 0), vector_len);
3489 }
3490 }
3491
3492 void MacroAssembler::vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3493 assert(rscratch != noreg || always_reachable(src), "missing");
3494
3495 if (reachable(src)) {
3496 Assembler::vpbroadcastq(dst, as_Address(src), vector_len);
3497 } else {
3498 lea(rscratch, src);
3499 Assembler::vpbroadcastq(dst, Address(rscratch, 0), vector_len);
3500 }
3501 }
3502
3503 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3504 assert(rscratch != noreg || always_reachable(src), "missing");
3505
3506 if (reachable(src)) {
3507 Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3508 } else {
3509 lea(rscratch, src);
3510 Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3511 }
3512 }
3513
3514 void MacroAssembler::vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3515 assert(rscratch != noreg || always_reachable(src), "missing");
3516
3517 if (reachable(src)) {
3518 Assembler::vbroadcastss(dst, as_Address(src), vector_len);
3519 } else {
3520 lea(rscratch, src);
3521 Assembler::vbroadcastss(dst, Address(rscratch, 0), vector_len);
3522 }
3523 }
3524
3525 // Vector float blend
3526 // vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3527 void MacroAssembler::vblendvps(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3528 // WARN: Allow dst == (src1|src2), mask == scratch
3529 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3530 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst;
3531 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3532 if (blend_emulation && scratch_available && dst_available) {
3533 if (compute_mask) {
3534 vpsrad(scratch, mask, 32, vector_len);
3535 mask = scratch;
3536 }
3537 if (dst == src1) {
3538 vpandn(dst, mask, src1, vector_len); // if mask == 0, src1
3539 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3540 } else {
3541 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3542 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src1
3543 }
3544 vpor(dst, dst, scratch, vector_len);
3545 } else {
3546 Assembler::vblendvps(dst, src1, src2, mask, vector_len);
3547 }
3548 }
3549
3550 // vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len, bool compute_mask = true, XMMRegister scratch = xnoreg)
3551 void MacroAssembler::vblendvpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, XMMRegister mask, int vector_len, bool compute_mask, XMMRegister scratch) {
3552 // WARN: Allow dst == (src1|src2), mask == scratch
3553 bool blend_emulation = EnableX86ECoreOpts && UseAVX > 1;
3554 bool scratch_available = scratch != xnoreg && scratch != src1 && scratch != src2 && scratch != dst && (!compute_mask || scratch != mask);
3555 bool dst_available = dst != mask && (dst != src1 || dst != src2);
3556 if (blend_emulation && scratch_available && dst_available) {
3557 if (compute_mask) {
3558 vpxor(scratch, scratch, scratch, vector_len);
3559 vpcmpgtq(scratch, scratch, mask, vector_len);
3560 mask = scratch;
3561 }
3562 if (dst == src1) {
3563 vpandn(dst, mask, src1, vector_len); // if mask == 0, src
3564 vpand (scratch, mask, src2, vector_len); // if mask == 1, src2
3565 } else {
3566 vpand (dst, mask, src2, vector_len); // if mask == 1, src2
3567 vpandn(scratch, mask, src1, vector_len); // if mask == 0, src
3568 }
3569 vpor(dst, dst, scratch, vector_len);
3570 } else {
3571 Assembler::vblendvpd(dst, src1, src2, mask, vector_len);
3572 }
3573 }
3574
3575 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3576 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3577 Assembler::vpcmpeqb(dst, nds, src, vector_len);
3578 }
3579
3580 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
3581 assert(((dst->encoding() < 16 && src1->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3582 Assembler::vpcmpeqb(dst, src1, src2, vector_len);
3583 }
3584
3585 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3586 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3587 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3588 }
3589
3590 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3591 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3592 Assembler::vpcmpeqw(dst, nds, src, vector_len);
3593 }
3594
3595 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3596 assert(rscratch != noreg || always_reachable(src), "missing");
3597
3598 if (reachable(src)) {
3599 Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3600 } else {
3601 lea(rscratch, src);
3602 Assembler::evpcmpeqd(kdst, mask, nds, Address(rscratch, 0), vector_len);
3603 }
3604 }
3605
3606 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3607 int comparison, bool is_signed, int vector_len, Register rscratch) {
3608 assert(rscratch != noreg || always_reachable(src), "missing");
3609
3610 if (reachable(src)) {
3611 Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3612 } else {
3613 lea(rscratch, src);
3614 Assembler::evpcmpd(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3615 }
3616 }
3617
3618 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3619 int comparison, bool is_signed, int vector_len, Register rscratch) {
3620 assert(rscratch != noreg || always_reachable(src), "missing");
3621
3622 if (reachable(src)) {
3623 Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3624 } else {
3625 lea(rscratch, src);
3626 Assembler::evpcmpq(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3627 }
3628 }
3629
3630 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3631 int comparison, bool is_signed, int vector_len, Register rscratch) {
3632 assert(rscratch != noreg || always_reachable(src), "missing");
3633
3634 if (reachable(src)) {
3635 Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3636 } else {
3637 lea(rscratch, src);
3638 Assembler::evpcmpb(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3639 }
3640 }
3641
3642 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3643 int comparison, bool is_signed, int vector_len, Register rscratch) {
3644 assert(rscratch != noreg || always_reachable(src), "missing");
3645
3646 if (reachable(src)) {
3647 Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3648 } else {
3649 lea(rscratch, src);
3650 Assembler::evpcmpw(kdst, mask, nds, Address(rscratch, 0), comparison, is_signed, vector_len);
3651 }
3652 }
3653
3654 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3655 if (width == Assembler::Q) {
3656 Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3657 } else {
3658 Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3659 }
3660 }
3661
3662 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3663 int eq_cond_enc = 0x29;
3664 int gt_cond_enc = 0x37;
3665 if (width != Assembler::Q) {
3666 eq_cond_enc = 0x74 + width;
3667 gt_cond_enc = 0x64 + width;
3668 }
3669 switch (cond) {
3670 case eq:
3671 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3672 break;
3673 case neq:
3674 vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3675 vallones(xtmp, vector_len);
3676 vpxor(dst, xtmp, dst, vector_len);
3677 break;
3678 case le:
3679 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3680 vallones(xtmp, vector_len);
3681 vpxor(dst, xtmp, dst, vector_len);
3682 break;
3683 case nlt:
3684 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3685 vallones(xtmp, vector_len);
3686 vpxor(dst, xtmp, dst, vector_len);
3687 break;
3688 case lt:
3689 vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3690 break;
3691 case nle:
3692 vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3693 break;
3694 default:
3695 assert(false, "Should not reach here");
3696 }
3697 }
3698
3699 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3700 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3701 Assembler::vpmovzxbw(dst, src, vector_len);
3702 }
3703
3704 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3705 assert((src->encoding() < 16),"XMM register should be 0-15");
3706 Assembler::vpmovmskb(dst, src, vector_len);
3707 }
3708
3709 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3710 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3711 Assembler::vpmullw(dst, nds, src, vector_len);
3712 }
3713
3714 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3715 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3716 Assembler::vpmullw(dst, nds, src, vector_len);
3717 }
3718
3719 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3720 assert((UseAVX > 0), "AVX support is needed");
3721 assert(rscratch != noreg || always_reachable(src), "missing");
3722
3723 if (reachable(src)) {
3724 Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3725 } else {
3726 lea(rscratch, src);
3727 Assembler::vpmulld(dst, nds, Address(rscratch, 0), vector_len);
3728 }
3729 }
3730
3731 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3732 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3733 Assembler::vpsubb(dst, nds, src, vector_len);
3734 }
3735
3736 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3737 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3738 Assembler::vpsubb(dst, nds, src, vector_len);
3739 }
3740
3741 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3742 assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3743 Assembler::vpsubw(dst, nds, src, vector_len);
3744 }
3745
3746 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3747 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3748 Assembler::vpsubw(dst, nds, src, vector_len);
3749 }
3750
3751 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3752 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3753 Assembler::vpsraw(dst, nds, shift, vector_len);
3754 }
3755
3756 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3757 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3758 Assembler::vpsraw(dst, nds, shift, vector_len);
3759 }
3760
3761 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3762 assert(UseAVX > 2,"");
3763 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3764 vector_len = 2;
3765 }
3766 Assembler::evpsraq(dst, nds, shift, vector_len);
3767 }
3768
3769 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3770 assert(UseAVX > 2,"");
3771 if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3772 vector_len = 2;
3773 }
3774 Assembler::evpsraq(dst, nds, shift, vector_len);
3775 }
3776
3777 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3778 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3779 Assembler::vpsrlw(dst, nds, shift, vector_len);
3780 }
3781
3782 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3783 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3784 Assembler::vpsrlw(dst, nds, shift, vector_len);
3785 }
3786
3787 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3788 assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3789 Assembler::vpsllw(dst, nds, shift, vector_len);
3790 }
3791
3792 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3793 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3794 Assembler::vpsllw(dst, nds, shift, vector_len);
3795 }
3796
3797 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3798 assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3799 Assembler::vptest(dst, src);
3800 }
3801
3802 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3803 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3804 Assembler::punpcklbw(dst, src);
3805 }
3806
3807 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3808 assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3809 Assembler::pshufd(dst, src, mode);
3810 }
3811
3812 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3813 assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3814 Assembler::pshuflw(dst, src, mode);
3815 }
3816
3817 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3818 assert(rscratch != noreg || always_reachable(src), "missing");
3819
3820 if (reachable(src)) {
3821 vandpd(dst, nds, as_Address(src), vector_len);
3822 } else {
3823 lea(rscratch, src);
3824 vandpd(dst, nds, Address(rscratch, 0), vector_len);
3825 }
3826 }
3827
3828 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3829 assert(rscratch != noreg || always_reachable(src), "missing");
3830
3831 if (reachable(src)) {
3832 vandps(dst, nds, as_Address(src), vector_len);
3833 } else {
3834 lea(rscratch, src);
3835 vandps(dst, nds, Address(rscratch, 0), vector_len);
3836 }
3837 }
3838
3839 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3840 bool merge, int vector_len, Register rscratch) {
3841 assert(rscratch != noreg || always_reachable(src), "missing");
3842
3843 if (reachable(src)) {
3844 Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3845 } else {
3846 lea(rscratch, src);
3847 Assembler::evpord(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
3848 }
3849 }
3850
3851 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3852 assert(rscratch != noreg || always_reachable(src), "missing");
3853
3854 if (reachable(src)) {
3855 vdivsd(dst, nds, as_Address(src));
3856 } else {
3857 lea(rscratch, src);
3858 vdivsd(dst, nds, Address(rscratch, 0));
3859 }
3860 }
3861
3862 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3863 assert(rscratch != noreg || always_reachable(src), "missing");
3864
3865 if (reachable(src)) {
3866 vdivss(dst, nds, as_Address(src));
3867 } else {
3868 lea(rscratch, src);
3869 vdivss(dst, nds, Address(rscratch, 0));
3870 }
3871 }
3872
3873 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3874 assert(rscratch != noreg || always_reachable(src), "missing");
3875
3876 if (reachable(src)) {
3877 vmulsd(dst, nds, as_Address(src));
3878 } else {
3879 lea(rscratch, src);
3880 vmulsd(dst, nds, Address(rscratch, 0));
3881 }
3882 }
3883
3884 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3885 assert(rscratch != noreg || always_reachable(src), "missing");
3886
3887 if (reachable(src)) {
3888 vmulss(dst, nds, as_Address(src));
3889 } else {
3890 lea(rscratch, src);
3891 vmulss(dst, nds, Address(rscratch, 0));
3892 }
3893 }
3894
3895 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3896 assert(rscratch != noreg || always_reachable(src), "missing");
3897
3898 if (reachable(src)) {
3899 vsubsd(dst, nds, as_Address(src));
3900 } else {
3901 lea(rscratch, src);
3902 vsubsd(dst, nds, Address(rscratch, 0));
3903 }
3904 }
3905
3906 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3907 assert(rscratch != noreg || always_reachable(src), "missing");
3908
3909 if (reachable(src)) {
3910 vsubss(dst, nds, as_Address(src));
3911 } else {
3912 lea(rscratch, src);
3913 vsubss(dst, nds, Address(rscratch, 0));
3914 }
3915 }
3916
3917 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3918 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3919 assert(rscratch != noreg || always_reachable(src), "missing");
3920
3921 vxorps(dst, nds, src, Assembler::AVX_128bit, rscratch);
3922 }
3923
3924 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch) {
3925 assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3926 assert(rscratch != noreg || always_reachable(src), "missing");
3927
3928 vxorpd(dst, nds, src, Assembler::AVX_128bit, rscratch);
3929 }
3930
3931 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3932 assert(rscratch != noreg || always_reachable(src), "missing");
3933
3934 if (reachable(src)) {
3935 vxorpd(dst, nds, as_Address(src), vector_len);
3936 } else {
3937 lea(rscratch, src);
3938 vxorpd(dst, nds, Address(rscratch, 0), vector_len);
3939 }
3940 }
3941
3942 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3943 assert(rscratch != noreg || always_reachable(src), "missing");
3944
3945 if (reachable(src)) {
3946 vxorps(dst, nds, as_Address(src), vector_len);
3947 } else {
3948 lea(rscratch, src);
3949 vxorps(dst, nds, Address(rscratch, 0), vector_len);
3950 }
3951 }
3952
3953 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3954 assert(rscratch != noreg || always_reachable(src), "missing");
3955
3956 if (UseAVX > 1 || (vector_len < 1)) {
3957 if (reachable(src)) {
3958 Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3959 } else {
3960 lea(rscratch, src);
3961 Assembler::vpxor(dst, nds, Address(rscratch, 0), vector_len);
3962 }
3963 } else {
3964 MacroAssembler::vxorpd(dst, nds, src, vector_len, rscratch);
3965 }
3966 }
3967
3968 void MacroAssembler::vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3969 assert(rscratch != noreg || always_reachable(src), "missing");
3970
3971 if (reachable(src)) {
3972 Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3973 } else {
3974 lea(rscratch, src);
3975 Assembler::vpermd(dst, nds, Address(rscratch, 0), vector_len);
3976 }
3977 }
3978
3979 void MacroAssembler::clear_jobject_tag(Register possibly_non_local) {
3980 const int32_t inverted_mask = ~static_cast<int32_t>(JNIHandles::tag_mask);
3981 STATIC_ASSERT(inverted_mask == -4); // otherwise check this code
3982 // The inverted mask is sign-extended
3983 andptr(possibly_non_local, inverted_mask);
3984 }
3985
3986 void MacroAssembler::resolve_jobject(Register value,
3987 Register thread,
3988 Register tmp) {
3989 assert_different_registers(value, thread, tmp);
3990 Label done, tagged, weak_tagged;
3991 testptr(value, value);
3992 jcc(Assembler::zero, done); // Use null as-is.
3993 testptr(value, JNIHandles::tag_mask); // Test for tag.
3994 jcc(Assembler::notZero, tagged);
3995
3996 // Resolve local handle
3997 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp, thread);
3998 verify_oop(value);
3999 jmp(done);
4000
4001 bind(tagged);
4002 testptr(value, JNIHandles::TypeTag::weak_global); // Test for weak tag.
4003 jcc(Assembler::notZero, weak_tagged);
4004
4005 // Resolve global handle
4006 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4007 verify_oop(value);
4008 jmp(done);
4009
4010 bind(weak_tagged);
4011 // Resolve jweak.
4012 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4013 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp, thread);
4014 verify_oop(value);
4015
4016 bind(done);
4017 }
4018
4019 void MacroAssembler::resolve_global_jobject(Register value,
4020 Register thread,
4021 Register tmp) {
4022 assert_different_registers(value, thread, tmp);
4023 Label done;
4024
4025 testptr(value, value);
4026 jcc(Assembler::zero, done); // Use null as-is.
4027
4028 #ifdef ASSERT
4029 {
4030 Label valid_global_tag;
4031 testptr(value, JNIHandles::TypeTag::global); // Test for global tag.
4032 jcc(Assembler::notZero, valid_global_tag);
4033 stop("non global jobject using resolve_global_jobject");
4034 bind(valid_global_tag);
4035 }
4036 #endif
4037
4038 // Resolve global handle
4039 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp, thread);
4040 verify_oop(value);
4041
4042 bind(done);
4043 }
4044
4045 void MacroAssembler::subptr(Register dst, int32_t imm32) {
4046 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
4047 }
4048
4049 // Force generation of a 4 byte immediate value even if it fits into 8bit
4050 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
4051 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
4052 }
4053
4054 void MacroAssembler::subptr(Register dst, Register src) {
4055 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
4056 }
4057
4058 // C++ bool manipulation
4059 void MacroAssembler::testbool(Register dst) {
4060 if(sizeof(bool) == 1)
4061 testb(dst, 0xff);
4062 else if(sizeof(bool) == 2) {
4063 // testw implementation needed for two byte bools
4064 ShouldNotReachHere();
4065 } else if(sizeof(bool) == 4)
4066 testl(dst, dst);
4067 else
4068 // unsupported
4069 ShouldNotReachHere();
4070 }
4071
4072 void MacroAssembler::testptr(Register dst, Register src) {
4073 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
4074 }
4075
4076 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
4077 void MacroAssembler::tlab_allocate(Register thread, Register obj,
4078 Register var_size_in_bytes,
4079 int con_size_in_bytes,
4080 Register t1,
4081 Register t2,
4082 Label& slow_case) {
4083 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4084 bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
4085 }
4086
4087 RegSet MacroAssembler::call_clobbered_gp_registers() {
4088 RegSet regs;
4089 #ifdef _LP64
4090 regs += RegSet::of(rax, rcx, rdx);
4091 #ifndef WINDOWS
4092 regs += RegSet::of(rsi, rdi);
4093 #endif
4094 regs += RegSet::range(r8, r11);
4095 #else
4096 regs += RegSet::of(rax, rcx, rdx);
4097 #endif
4098 return regs;
4099 }
4100
4101 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
4102 int num_xmm_registers = XMMRegister::available_xmm_registers();
4103 #if defined(WINDOWS) && defined(_LP64)
4104 XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
4105 if (num_xmm_registers > 16) {
4106 result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
4107 }
4108 return result;
4109 #else
4110 return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
4111 #endif
4112 }
4113
4114 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
4115
4116 #ifndef _LP64
4117 static bool use_x87_registers() { return UseSSE < 2; }
4118 #endif
4119 static bool use_xmm_registers() { return UseSSE >= 1; }
4120
4121 // C1 only ever uses the first double/float of the XMM register.
4122 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
4123
4124 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4125 if (UseSSE == 1) {
4126 masm->movflt(Address(rsp, offset), reg);
4127 } else {
4128 masm->movdbl(Address(rsp, offset), reg);
4129 }
4130 }
4131
4132 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
4133 if (UseSSE == 1) {
4134 masm->movflt(reg, Address(rsp, offset));
4135 } else {
4136 masm->movdbl(reg, Address(rsp, offset));
4137 }
4138 }
4139
4140 static int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers,
4141 bool save_fpu, int& gp_area_size,
4142 int& fp_area_size, int& xmm_area_size) {
4143
4144 gp_area_size = align_up(gp_registers.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size,
4145 StackAlignmentInBytes);
4146 #ifdef _LP64
4147 fp_area_size = 0;
4148 #else
4149 fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
4150 #endif
4151 xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
4152
4153 return gp_area_size + fp_area_size + xmm_area_size;
4154 }
4155
4156 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
4157 block_comment("push_call_clobbered_registers start");
4158 // Regular registers
4159 RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
4160
4161 int gp_area_size;
4162 int fp_area_size;
4163 int xmm_area_size;
4164 int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
4165 gp_area_size, fp_area_size, xmm_area_size);
4166 subptr(rsp, total_save_size);
4167
4168 push_set(gp_registers_to_push, 0);
4169
4170 #ifndef _LP64
4171 if (save_fpu && use_x87_registers()) {
4172 fnsave(Address(rsp, gp_area_size));
4173 fwait();
4174 }
4175 #endif
4176 if (save_fpu && use_xmm_registers()) {
4177 push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4178 }
4179
4180 block_comment("push_call_clobbered_registers end");
4181 }
4182
4183 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
4184 block_comment("pop_call_clobbered_registers start");
4185
4186 RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
4187
4188 int gp_area_size;
4189 int fp_area_size;
4190 int xmm_area_size;
4191 int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
4192 gp_area_size, fp_area_size, xmm_area_size);
4193
4194 if (restore_fpu && use_xmm_registers()) {
4195 pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
4196 }
4197 #ifndef _LP64
4198 if (restore_fpu && use_x87_registers()) {
4199 frstor(Address(rsp, gp_area_size));
4200 }
4201 #endif
4202
4203 pop_set(gp_registers_to_pop, 0);
4204
4205 addptr(rsp, total_save_size);
4206
4207 vzeroupper();
4208
4209 block_comment("pop_call_clobbered_registers end");
4210 }
4211
4212 void MacroAssembler::push_set(XMMRegSet set, int offset) {
4213 assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
4214 int spill_offset = offset;
4215
4216 for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
4217 save_xmm_register(this, spill_offset, *it);
4218 spill_offset += xmm_save_size();
4219 }
4220 }
4221
4222 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
4223 int restore_size = set.size() * xmm_save_size();
4224 assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
4225
4226 int restore_offset = offset + restore_size - xmm_save_size();
4227
4228 for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
4229 restore_xmm_register(this, restore_offset, *it);
4230 restore_offset -= xmm_save_size();
4231 }
4232 }
4233
4234 void MacroAssembler::push_set(RegSet set, int offset) {
4235 int spill_offset;
4236 if (offset == -1) {
4237 int register_push_size = set.size() * Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4238 int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
4239 subptr(rsp, aligned_size);
4240 spill_offset = 0;
4241 } else {
4242 spill_offset = offset;
4243 }
4244
4245 for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
4246 movptr(Address(rsp, spill_offset), *it);
4247 spill_offset += Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4248 }
4249 }
4250
4251 void MacroAssembler::pop_set(RegSet set, int offset) {
4252
4253 int gp_reg_size = Register::max_slots_per_register * VMRegImpl::stack_slot_size;
4254 int restore_size = set.size() * gp_reg_size;
4255 int aligned_size = align_up(restore_size, StackAlignmentInBytes);
4256
4257 int restore_offset;
4258 if (offset == -1) {
4259 restore_offset = restore_size - gp_reg_size;
4260 } else {
4261 restore_offset = offset + restore_size - gp_reg_size;
4262 }
4263 for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
4264 movptr(*it, Address(rsp, restore_offset));
4265 restore_offset -= gp_reg_size;
4266 }
4267
4268 if (offset == -1) {
4269 addptr(rsp, aligned_size);
4270 }
4271 }
4272
4273 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
4274 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
4275 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
4276 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
4277 Label done;
4278
4279 testptr(length_in_bytes, length_in_bytes);
4280 jcc(Assembler::zero, done);
4281
4282 // initialize topmost word, divide index by 2, check if odd and test if zero
4283 // note: for the remaining code to work, index must be a multiple of BytesPerWord
4284 #ifdef ASSERT
4285 {
4286 Label L;
4287 testptr(length_in_bytes, BytesPerWord - 1);
4288 jcc(Assembler::zero, L);
4289 stop("length must be a multiple of BytesPerWord");
4290 bind(L);
4291 }
4292 #endif
4293 Register index = length_in_bytes;
4294 xorptr(temp, temp); // use _zero reg to clear memory (shorter code)
4295 if (UseIncDec) {
4296 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set
4297 } else {
4298 shrptr(index, 2); // use 2 instructions to avoid partial flag stall
4299 shrptr(index, 1);
4300 }
4301 #ifndef _LP64
4302 // index could have not been a multiple of 8 (i.e., bit 2 was set)
4303 {
4304 Label even;
4305 // note: if index was a multiple of 8, then it cannot
4306 // be 0 now otherwise it must have been 0 before
4307 // => if it is even, we don't need to check for 0 again
4308 jcc(Assembler::carryClear, even);
4309 // clear topmost word (no jump would be needed if conditional assignment worked here)
4310 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
4311 // index could be 0 now, must check again
4312 jcc(Assembler::zero, done);
4313 bind(even);
4314 }
4315 #endif // !_LP64
4316 // initialize remaining object fields: index is a multiple of 2 now
4317 {
4318 Label loop;
4319 bind(loop);
4320 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
4321 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
4322 decrement(index);
4323 jcc(Assembler::notZero, loop);
4324 }
4325
4326 bind(done);
4327 }
4328
4329 // Look up the method for a megamorphic invokeinterface call.
4330 // The target method is determined by <intf_klass, itable_index>.
4331 // The receiver klass is in recv_klass.
4332 // On success, the result will be in method_result, and execution falls through.
4333 // On failure, execution transfers to the given label.
4334 void MacroAssembler::lookup_interface_method(Register recv_klass,
4335 Register intf_klass,
4336 RegisterOrConstant itable_index,
4337 Register method_result,
4338 Register scan_temp,
4339 Label& L_no_such_interface,
4340 bool return_method) {
4341 assert_different_registers(recv_klass, intf_klass, scan_temp);
4342 assert_different_registers(method_result, intf_klass, scan_temp);
4343 assert(recv_klass != method_result || !return_method,
4344 "recv_klass can be destroyed when method isn't needed");
4345
4346 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
4347 "caller must use same register for non-constant itable index as for method");
4348
4349 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
4350 int vtable_base = in_bytes(Klass::vtable_start_offset());
4351 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4352 int scan_step = itableOffsetEntry::size() * wordSize;
4353 int vte_size = vtableEntry::size_in_bytes();
4354 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4355 assert(vte_size == wordSize, "else adjust times_vte_scale");
4356
4357 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4358
4359 // Could store the aligned, prescaled offset in the klass.
4360 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
4361
4362 if (return_method) {
4363 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
4364 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4365 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
4366 }
4367
4368 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
4369 // if (scan->interface() == intf) {
4370 // result = (klass + scan->offset() + itable_index);
4371 // }
4372 // }
4373 Label search, found_method;
4374
4375 for (int peel = 1; peel >= 0; peel--) {
4376 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
4377 cmpptr(intf_klass, method_result);
4378
4379 if (peel) {
4380 jccb(Assembler::equal, found_method);
4381 } else {
4382 jccb(Assembler::notEqual, search);
4383 // (invert the test to fall through to found_method...)
4384 }
4385
4386 if (!peel) break;
4387
4388 bind(search);
4389
4390 // Check that the previous entry is non-null. A null entry means that
4391 // the receiver class doesn't implement the interface, and wasn't the
4392 // same as when the caller was compiled.
4393 testptr(method_result, method_result);
4394 jcc(Assembler::zero, L_no_such_interface);
4395 addptr(scan_temp, scan_step);
4396 }
4397
4398 bind(found_method);
4399
4400 if (return_method) {
4401 // Got a hit.
4402 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
4403 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
4404 }
4405 }
4406
4407 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
4408 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
4409 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
4410 // The target method is determined by <holder_klass, itable_index>.
4411 // The receiver klass is in recv_klass.
4412 // On success, the result will be in method_result, and execution falls through.
4413 // On failure, execution transfers to the given label.
4414 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
4415 Register holder_klass,
4416 Register resolved_klass,
4417 Register method_result,
4418 Register scan_temp,
4419 Register temp_reg2,
4420 Register receiver,
4421 int itable_index,
4422 Label& L_no_such_interface) {
4423 assert_different_registers(recv_klass, method_result, holder_klass, resolved_klass, scan_temp, temp_reg2, receiver);
4424 Register temp_itbl_klass = method_result;
4425 Register temp_reg = (temp_reg2 == noreg ? recv_klass : temp_reg2); // reuse recv_klass register on 32-bit x86 impl
4426
4427 int vtable_base = in_bytes(Klass::vtable_start_offset());
4428 int itentry_off = in_bytes(itableMethodEntry::method_offset());
4429 int scan_step = itableOffsetEntry::size() * wordSize;
4430 int vte_size = vtableEntry::size_in_bytes();
4431 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
4432 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
4433 Address::ScaleFactor times_vte_scale = Address::times_ptr;
4434 assert(vte_size == wordSize, "adjust times_vte_scale");
4435
4436 Label L_loop_scan_resolved_entry, L_resolved_found, L_holder_found;
4437
4438 // temp_itbl_klass = recv_klass.itable[0]
4439 // scan_temp = &recv_klass.itable[0] + step
4440 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
4441 movptr(temp_itbl_klass, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset));
4442 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base + ioffset + scan_step));
4443 xorptr(temp_reg, temp_reg);
4444
4445 // Initial checks:
4446 // - if (holder_klass != resolved_klass), go to "scan for resolved"
4447 // - if (itable[0] == 0), no such interface
4448 // - if (itable[0] == holder_klass), shortcut to "holder found"
4449 cmpptr(holder_klass, resolved_klass);
4450 jccb(Assembler::notEqual, L_loop_scan_resolved_entry);
4451 testptr(temp_itbl_klass, temp_itbl_klass);
4452 jccb(Assembler::zero, L_no_such_interface);
4453 cmpptr(holder_klass, temp_itbl_klass);
4454 jccb(Assembler::equal, L_holder_found);
4455
4456 // Loop: Look for holder_klass record in itable
4457 // do {
4458 // tmp = itable[index];
4459 // index += step;
4460 // if (tmp == holder_klass) {
4461 // goto L_holder_found; // Found!
4462 // }
4463 // } while (tmp != 0);
4464 // goto L_no_such_interface // Not found.
4465 Label L_scan_holder;
4466 bind(L_scan_holder);
4467 movptr(temp_itbl_klass, Address(scan_temp, 0));
4468 addptr(scan_temp, scan_step);
4469 cmpptr(holder_klass, temp_itbl_klass);
4470 jccb(Assembler::equal, L_holder_found);
4471 testptr(temp_itbl_klass, temp_itbl_klass);
4472 jccb(Assembler::notZero, L_scan_holder);
4473
4474 jmpb(L_no_such_interface);
4475
4476 // Loop: Look for resolved_class record in itable
4477 // do {
4478 // tmp = itable[index];
4479 // index += step;
4480 // if (tmp == holder_klass) {
4481 // // Also check if we have met a holder klass
4482 // holder_tmp = itable[index-step-ioffset];
4483 // }
4484 // if (tmp == resolved_klass) {
4485 // goto L_resolved_found; // Found!
4486 // }
4487 // } while (tmp != 0);
4488 // goto L_no_such_interface // Not found.
4489 //
4490 Label L_loop_scan_resolved;
4491 bind(L_loop_scan_resolved);
4492 movptr(temp_itbl_klass, Address(scan_temp, 0));
4493 addptr(scan_temp, scan_step);
4494 bind(L_loop_scan_resolved_entry);
4495 cmpptr(holder_klass, temp_itbl_klass);
4496 cmovl(Assembler::equal, temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4497 cmpptr(resolved_klass, temp_itbl_klass);
4498 jccb(Assembler::equal, L_resolved_found);
4499 testptr(temp_itbl_klass, temp_itbl_klass);
4500 jccb(Assembler::notZero, L_loop_scan_resolved);
4501
4502 jmpb(L_no_such_interface);
4503
4504 Label L_ready;
4505
4506 // See if we already have a holder klass. If not, go and scan for it.
4507 bind(L_resolved_found);
4508 testptr(temp_reg, temp_reg);
4509 jccb(Assembler::zero, L_scan_holder);
4510 jmpb(L_ready);
4511
4512 bind(L_holder_found);
4513 movl(temp_reg, Address(scan_temp, ooffset - ioffset - scan_step));
4514
4515 // Finally, temp_reg contains holder_klass vtable offset
4516 bind(L_ready);
4517 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
4518 if (temp_reg2 == noreg) { // recv_klass register is clobbered for 32-bit x86 impl
4519 load_klass(scan_temp, receiver, noreg);
4520 movptr(method_result, Address(scan_temp, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4521 } else {
4522 movptr(method_result, Address(recv_klass, temp_reg, Address::times_1, itable_index * wordSize + itentry_off));
4523 }
4524 }
4525
4526
4527 // virtual method calling
4528 void MacroAssembler::lookup_virtual_method(Register recv_klass,
4529 RegisterOrConstant vtable_index,
4530 Register method_result) {
4531 const ByteSize base = Klass::vtable_start_offset();
4532 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
4533 Address vtable_entry_addr(recv_klass,
4534 vtable_index, Address::times_ptr,
4535 base + vtableEntry::method_offset());
4536 movptr(method_result, vtable_entry_addr);
4537 }
4538
4539
4540 void MacroAssembler::check_klass_subtype(Register sub_klass,
4541 Register super_klass,
4542 Register temp_reg,
4543 Label& L_success) {
4544 Label L_failure;
4545 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
4546 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
4547 bind(L_failure);
4548 }
4549
4550
4551 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
4552 Register super_klass,
4553 Register temp_reg,
4554 Label* L_success,
4555 Label* L_failure,
4556 Label* L_slow_path,
4557 RegisterOrConstant super_check_offset) {
4558 assert_different_registers(sub_klass, super_klass, temp_reg);
4559 bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
4560 if (super_check_offset.is_register()) {
4561 assert_different_registers(sub_klass, super_klass,
4562 super_check_offset.as_register());
4563 } else if (must_load_sco) {
4564 assert(temp_reg != noreg, "supply either a temp or a register offset");
4565 }
4566
4567 Label L_fallthrough;
4568 int label_nulls = 0;
4569 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4570 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4571 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
4572 assert(label_nulls <= 1, "at most one null in the batch");
4573
4574 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4575 int sco_offset = in_bytes(Klass::super_check_offset_offset());
4576 Address super_check_offset_addr(super_klass, sco_offset);
4577
4578 // Hacked jcc, which "knows" that L_fallthrough, at least, is in
4579 // range of a jccb. If this routine grows larger, reconsider at
4580 // least some of these.
4581 #define local_jcc(assembler_cond, label) \
4582 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \
4583 else jcc( assembler_cond, label) /*omit semi*/
4584
4585 // Hacked jmp, which may only be used just before L_fallthrough.
4586 #define final_jmp(label) \
4587 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
4588 else jmp(label) /*omit semi*/
4589
4590 // If the pointers are equal, we are done (e.g., String[] elements).
4591 // This self-check enables sharing of secondary supertype arrays among
4592 // non-primary types such as array-of-interface. Otherwise, each such
4593 // type would need its own customized SSA.
4594 // We move this check to the front of the fast path because many
4595 // type checks are in fact trivially successful in this manner,
4596 // so we get a nicely predicted branch right at the start of the check.
4597 cmpptr(sub_klass, super_klass);
4598 local_jcc(Assembler::equal, *L_success);
4599
4600 // Check the supertype display:
4601 if (must_load_sco) {
4602 // Positive movl does right thing on LP64.
4603 movl(temp_reg, super_check_offset_addr);
4604 super_check_offset = RegisterOrConstant(temp_reg);
4605 }
4606 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
4607 cmpptr(super_klass, super_check_addr); // load displayed supertype
4608
4609 // This check has worked decisively for primary supers.
4610 // Secondary supers are sought in the super_cache ('super_cache_addr').
4611 // (Secondary supers are interfaces and very deeply nested subtypes.)
4612 // This works in the same check above because of a tricky aliasing
4613 // between the super_cache and the primary super display elements.
4614 // (The 'super_check_addr' can address either, as the case requires.)
4615 // Note that the cache is updated below if it does not help us find
4616 // what we need immediately.
4617 // So if it was a primary super, we can just fail immediately.
4618 // Otherwise, it's the slow path for us (no success at this point).
4619
4620 if (super_check_offset.is_register()) {
4621 local_jcc(Assembler::equal, *L_success);
4622 cmpl(super_check_offset.as_register(), sc_offset);
4623 if (L_failure == &L_fallthrough) {
4624 local_jcc(Assembler::equal, *L_slow_path);
4625 } else {
4626 local_jcc(Assembler::notEqual, *L_failure);
4627 final_jmp(*L_slow_path);
4628 }
4629 } else if (super_check_offset.as_constant() == sc_offset) {
4630 // Need a slow path; fast failure is impossible.
4631 if (L_slow_path == &L_fallthrough) {
4632 local_jcc(Assembler::equal, *L_success);
4633 } else {
4634 local_jcc(Assembler::notEqual, *L_slow_path);
4635 final_jmp(*L_success);
4636 }
4637 } else {
4638 // No slow path; it's a fast decision.
4639 if (L_failure == &L_fallthrough) {
4640 local_jcc(Assembler::equal, *L_success);
4641 } else {
4642 local_jcc(Assembler::notEqual, *L_failure);
4643 final_jmp(*L_success);
4644 }
4645 }
4646
4647 bind(L_fallthrough);
4648
4649 #undef local_jcc
4650 #undef final_jmp
4651 }
4652
4653
4654 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4655 Register super_klass,
4656 Register temp_reg,
4657 Register temp2_reg,
4658 Label* L_success,
4659 Label* L_failure,
4660 bool set_cond_codes) {
4661 assert_different_registers(sub_klass, super_klass, temp_reg);
4662 if (temp2_reg != noreg)
4663 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4664 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4665
4666 Label L_fallthrough;
4667 int label_nulls = 0;
4668 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4669 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4670 assert(label_nulls <= 1, "at most one null in the batch");
4671
4672 // a couple of useful fields in sub_klass:
4673 int ss_offset = in_bytes(Klass::secondary_supers_offset());
4674 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4675 Address secondary_supers_addr(sub_klass, ss_offset);
4676 Address super_cache_addr( sub_klass, sc_offset);
4677
4678 // Do a linear scan of the secondary super-klass chain.
4679 // This code is rarely used, so simplicity is a virtue here.
4680 // The repne_scan instruction uses fixed registers, which we must spill.
4681 // Don't worry too much about pre-existing connections with the input regs.
4682
4683 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4684 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4685
4686 // Get super_klass value into rax (even if it was in rdi or rcx).
4687 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4688 if (super_klass != rax) {
4689 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4690 mov(rax, super_klass);
4691 }
4692 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4693 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4694
4695 #ifndef PRODUCT
4696 uint* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4697 ExternalAddress pst_counter_addr((address) pst_counter);
4698 NOT_LP64( incrementl(pst_counter_addr) );
4699 LP64_ONLY( lea(rcx, pst_counter_addr) );
4700 LP64_ONLY( incrementl(Address(rcx, 0)) );
4701 #endif //PRODUCT
4702
4703 // We will consult the secondary-super array.
4704 movptr(rdi, secondary_supers_addr);
4705 // Load the array length. (Positive movl does right thing on LP64.)
4706 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4707 // Skip to start of data.
4708 addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4709
4710 // Scan RCX words at [RDI] for an occurrence of RAX.
4711 // Set NZ/Z based on last compare.
4712 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4713 // not change flags (only scas instruction which is repeated sets flags).
4714 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4715
4716 testptr(rax,rax); // Set Z = 0
4717 repne_scan();
4718
4719 // Unspill the temp. registers:
4720 if (pushed_rdi) pop(rdi);
4721 if (pushed_rcx) pop(rcx);
4722 if (pushed_rax) pop(rax);
4723
4724 if (set_cond_codes) {
4725 // Special hack for the AD files: rdi is guaranteed non-zero.
4726 assert(!pushed_rdi, "rdi must be left non-null");
4727 // Also, the condition codes are properly set Z/NZ on succeed/failure.
4728 }
4729
4730 if (L_failure == &L_fallthrough)
4731 jccb(Assembler::notEqual, *L_failure);
4732 else jcc(Assembler::notEqual, *L_failure);
4733
4734 // Success. Cache the super we found and proceed in triumph.
4735 movptr(super_cache_addr, super_klass);
4736
4737 if (L_success != &L_fallthrough) {
4738 jmp(*L_success);
4739 }
4740
4741 #undef IS_A_TEMP
4742
4743 bind(L_fallthrough);
4744 }
4745
4746 #ifdef _LP64
4747
4748 // population_count variant for running without the POPCNT
4749 // instruction, which was introduced with SSE4.2 in 2008.
4750 void MacroAssembler::population_count(Register dst, Register src,
4751 Register scratch1, Register scratch2) {
4752 assert_different_registers(src, scratch1, scratch2);
4753 if (UsePopCountInstruction) {
4754 Assembler::popcntq(dst, src);
4755 } else {
4756 assert_different_registers(src, scratch1, scratch2);
4757 assert_different_registers(dst, scratch1, scratch2);
4758 Label loop, done;
4759
4760 mov(scratch1, src);
4761 // dst = 0;
4762 // while(scratch1 != 0) {
4763 // dst++;
4764 // scratch1 &= (scratch1 - 1);
4765 // }
4766 xorl(dst, dst);
4767 testq(scratch1, scratch1);
4768 jccb(Assembler::equal, done);
4769 {
4770 bind(loop);
4771 incq(dst);
4772 movq(scratch2, scratch1);
4773 decq(scratch2);
4774 andq(scratch1, scratch2);
4775 jccb(Assembler::notEqual, loop);
4776 }
4777 bind(done);
4778 }
4779 }
4780
4781 // Ensure that the inline code and the stub are using the same registers.
4782 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
4783 do { \
4784 assert(r_super_klass == rax, "mismatch"); \
4785 assert(r_array_base == rbx, "mismatch"); \
4786 assert(r_array_length == rcx, "mismatch"); \
4787 assert(r_array_index == rdx, "mismatch"); \
4788 assert(r_sub_klass == rsi || r_sub_klass == noreg, "mismatch"); \
4789 assert(r_bitmap == r11 || r_bitmap == noreg, "mismatch"); \
4790 assert(result == rdi || result == noreg, "mismatch"); \
4791 } while(0)
4792
4793 void MacroAssembler::lookup_secondary_supers_table(Register r_sub_klass,
4794 Register r_super_klass,
4795 Register temp1,
4796 Register temp2,
4797 Register temp3,
4798 Register temp4,
4799 Register result,
4800 u1 super_klass_slot) {
4801 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, temp3, temp4, result);
4802
4803 Label L_fallthrough, L_success, L_failure;
4804
4805 BLOCK_COMMENT("lookup_secondary_supers_table {");
4806
4807 const Register
4808 r_array_index = temp1,
4809 r_array_length = temp2,
4810 r_array_base = temp3,
4811 r_bitmap = temp4;
4812
4813 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4814
4815 xorq(result, result); // = 0
4816
4817 movq(r_bitmap, Address(r_sub_klass, Klass::bitmap_offset()));
4818 movq(r_array_index, r_bitmap);
4819
4820 // First check the bitmap to see if super_klass might be present. If
4821 // the bit is zero, we are certain that super_klass is not one of
4822 // the secondary supers.
4823 u1 bit = super_klass_slot;
4824 {
4825 // NB: If the count in a x86 shift instruction is 0, the flags are
4826 // not affected, so we do a testq instead.
4827 int shift_count = Klass::SECONDARY_SUPERS_TABLE_MASK - bit;
4828 if (shift_count != 0) {
4829 salq(r_array_index, shift_count);
4830 } else {
4831 testq(r_array_index, r_array_index);
4832 }
4833 }
4834 // We test the MSB of r_array_index, i.e. its sign bit
4835 jcc(Assembler::positive, L_failure);
4836
4837 // Get the first array index that can contain super_klass into r_array_index.
4838 if (bit != 0) {
4839 population_count(r_array_index, r_array_index, temp2, temp3);
4840 } else {
4841 movl(r_array_index, 1);
4842 }
4843 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
4844
4845 // We will consult the secondary-super array.
4846 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
4847
4848 // We're asserting that the first word in an Array<Klass*> is the
4849 // length, and the second word is the first word of the data. If
4850 // that ever changes, r_array_base will have to be adjusted here.
4851 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
4852 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
4853
4854 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4855 jccb(Assembler::equal, L_success);
4856
4857 // Is there another entry to check? Consult the bitmap.
4858 btq(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK);
4859 jccb(Assembler::carryClear, L_failure);
4860
4861 // Linear probe. Rotate the bitmap so that the next bit to test is
4862 // in Bit 1.
4863 if (bit != 0) {
4864 rorq(r_bitmap, bit);
4865 }
4866
4867 // Calls into the stub generated by lookup_secondary_supers_table_slow_path.
4868 // Arguments: r_super_klass, r_array_base, r_array_index, r_bitmap.
4869 // Kills: r_array_length.
4870 // Returns: result.
4871 call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub()));
4872 // Result (0/1) is in rdi
4873 jmpb(L_fallthrough);
4874
4875 bind(L_failure);
4876 incq(result); // 0 => 1
4877
4878 bind(L_success);
4879 // result = 0;
4880
4881 bind(L_fallthrough);
4882 BLOCK_COMMENT("} lookup_secondary_supers_table");
4883
4884 if (VerifySecondarySupers) {
4885 verify_secondary_supers_table(r_sub_klass, r_super_klass, result,
4886 temp1, temp2, temp3);
4887 }
4888 }
4889
4890 void MacroAssembler::repne_scanq(Register addr, Register value, Register count, Register limit,
4891 Label* L_success, Label* L_failure) {
4892 Label L_loop, L_fallthrough;
4893 {
4894 int label_nulls = 0;
4895 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4896 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4897 assert(label_nulls <= 1, "at most one null in the batch");
4898 }
4899 bind(L_loop);
4900 cmpq(value, Address(addr, count, Address::times_8));
4901 jcc(Assembler::equal, *L_success);
4902 addl(count, 1);
4903 cmpl(count, limit);
4904 jcc(Assembler::less, L_loop);
4905
4906 if (&L_fallthrough != L_failure) {
4907 jmp(*L_failure);
4908 }
4909 bind(L_fallthrough);
4910 }
4911
4912 // Called by code generated by check_klass_subtype_slow_path
4913 // above. This is called when there is a collision in the hashed
4914 // lookup in the secondary supers array.
4915 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
4916 Register r_array_base,
4917 Register r_array_index,
4918 Register r_bitmap,
4919 Register temp1,
4920 Register temp2,
4921 Label* L_success,
4922 Label* L_failure) {
4923 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, temp2);
4924
4925 const Register
4926 r_array_length = temp1,
4927 r_sub_klass = noreg,
4928 result = noreg;
4929
4930 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
4931
4932 Label L_fallthrough;
4933 int label_nulls = 0;
4934 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
4935 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
4936 assert(label_nulls <= 1, "at most one null in the batch");
4937
4938 // Load the array length.
4939 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
4940 // And adjust the array base to point to the data.
4941 // NB! Effectively increments current slot index by 1.
4942 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
4943 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
4944
4945 // Linear probe
4946 Label L_huge;
4947
4948 // The bitmap is full to bursting.
4949 // Implicit invariant: BITMAP_FULL implies (length > 0)
4950 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
4951 cmpq(r_bitmap, (int32_t)-1); // sign-extends immediate to 64-bit value
4952 jcc(Assembler::equal, L_huge);
4953
4954 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
4955 // current slot (at secondary_supers[r_array_index]) has not yet
4956 // been inspected, and r_array_index may be out of bounds if we
4957 // wrapped around the end of the array.
4958
4959 { // This is conventional linear probing, but instead of terminating
4960 // when a null entry is found in the table, we maintain a bitmap
4961 // in which a 0 indicates missing entries.
4962 // The check above guarantees there are 0s in the bitmap, so the loop
4963 // eventually terminates.
4964
4965 xorl(temp2, temp2); // = 0;
4966
4967 Label L_again;
4968 bind(L_again);
4969
4970 // Check for array wraparound.
4971 cmpl(r_array_index, r_array_length);
4972 cmovl(Assembler::greaterEqual, r_array_index, temp2);
4973
4974 cmpq(r_super_klass, Address(r_array_base, r_array_index, Address::times_8));
4975 jcc(Assembler::equal, *L_success);
4976
4977 // If the next bit in bitmap is zero, we're done.
4978 btq(r_bitmap, 2); // look-ahead check (Bit 2); Bits 0 and 1 are tested by now
4979 jcc(Assembler::carryClear, *L_failure);
4980
4981 rorq(r_bitmap, 1); // Bits 1/2 => 0/1
4982 addl(r_array_index, 1);
4983
4984 jmp(L_again);
4985 }
4986
4987 { // Degenerate case: more than 64 secondary supers.
4988 // FIXME: We could do something smarter here, maybe a vectorized
4989 // comparison or a binary search, but is that worth any added
4990 // complexity?
4991 bind(L_huge);
4992 xorl(r_array_index, r_array_index); // = 0
4993 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length,
4994 L_success,
4995 (&L_fallthrough != L_failure ? L_failure : nullptr));
4996
4997 bind(L_fallthrough);
4998 }
4999 }
5000
5001 struct VerifyHelperArguments {
5002 Klass* _super;
5003 Klass* _sub;
5004 intptr_t _linear_result;
5005 intptr_t _table_result;
5006 };
5007
5008 static void verify_secondary_supers_table_helper(const char* msg, VerifyHelperArguments* args) {
5009 Klass::on_secondary_supers_verification_failure(args->_super,
5010 args->_sub,
5011 args->_linear_result,
5012 args->_table_result,
5013 msg);
5014 }
5015
5016 // Make sure that the hashed lookup and a linear scan agree.
5017 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
5018 Register r_super_klass,
5019 Register result,
5020 Register temp1,
5021 Register temp2,
5022 Register temp3) {
5023 const Register
5024 r_array_index = temp1,
5025 r_array_length = temp2,
5026 r_array_base = temp3,
5027 r_bitmap = noreg;
5028
5029 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
5030
5031 BLOCK_COMMENT("verify_secondary_supers_table {");
5032
5033 Label L_success, L_failure, L_check, L_done;
5034
5035 movptr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
5036 movl(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
5037 // And adjust the array base to point to the data.
5038 addptr(r_array_base, Array<Klass*>::base_offset_in_bytes());
5039
5040 testl(r_array_length, r_array_length); // array_length == 0?
5041 jcc(Assembler::zero, L_failure);
5042
5043 movl(r_array_index, 0);
5044 repne_scanq(r_array_base, r_super_klass, r_array_index, r_array_length, &L_success);
5045 // fall through to L_failure
5046
5047 const Register linear_result = r_array_index; // reuse temp1
5048
5049 bind(L_failure); // not present
5050 movl(linear_result, 1);
5051 jmp(L_check);
5052
5053 bind(L_success); // present
5054 movl(linear_result, 0);
5055
5056 bind(L_check);
5057 cmpl(linear_result, result);
5058 jcc(Assembler::equal, L_done);
5059
5060 { // To avoid calling convention issues, build a record on the stack
5061 // and pass the pointer to that instead.
5062 push(result);
5063 push(linear_result);
5064 push(r_sub_klass);
5065 push(r_super_klass);
5066 movptr(c_rarg1, rsp);
5067 movptr(c_rarg0, (uintptr_t) "mismatch");
5068 call(RuntimeAddress(CAST_FROM_FN_PTR(address, verify_secondary_supers_table_helper)));
5069 should_not_reach_here();
5070 }
5071 bind(L_done);
5072
5073 BLOCK_COMMENT("} verify_secondary_supers_table");
5074 }
5075
5076 #undef LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS
5077
5078 #endif // LP64
5079
5080 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
5081 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
5082
5083 Label L_fallthrough;
5084 if (L_fast_path == nullptr) {
5085 L_fast_path = &L_fallthrough;
5086 } else if (L_slow_path == nullptr) {
5087 L_slow_path = &L_fallthrough;
5088 }
5089
5090 // Fast path check: class is fully initialized
5091 cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
5092 jcc(Assembler::equal, *L_fast_path);
5093
5094 // Fast path check: current thread is initializer thread
5095 cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
5096 if (L_slow_path == &L_fallthrough) {
5097 jcc(Assembler::equal, *L_fast_path);
5098 bind(*L_slow_path);
5099 } else if (L_fast_path == &L_fallthrough) {
5100 jcc(Assembler::notEqual, *L_slow_path);
5101 bind(*L_fast_path);
5102 } else {
5103 Unimplemented();
5104 }
5105 }
5106
5107 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
5108 if (VM_Version::supports_cmov()) {
5109 cmovl(cc, dst, src);
5110 } else {
5111 Label L;
5112 jccb(negate_condition(cc), L);
5113 movl(dst, src);
5114 bind(L);
5115 }
5116 }
5117
5118 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
5119 if (VM_Version::supports_cmov()) {
5120 cmovl(cc, dst, src);
5121 } else {
5122 Label L;
5123 jccb(negate_condition(cc), L);
5124 movl(dst, src);
5125 bind(L);
5126 }
5127 }
5128
5129 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
5130 if (!VerifyOops) return;
5131
5132 BLOCK_COMMENT("verify_oop {");
5133 #ifdef _LP64
5134 push(rscratch1);
5135 #endif
5136 push(rax); // save rax
5137 push(reg); // pass register argument
5138
5139 // Pass register number to verify_oop_subroutine
5140 const char* b = nullptr;
5141 {
5142 ResourceMark rm;
5143 stringStream ss;
5144 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
5145 b = code_string(ss.as_string());
5146 }
5147 ExternalAddress buffer((address) b);
5148 pushptr(buffer.addr(), rscratch1);
5149
5150 // call indirectly to solve generation ordering problem
5151 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5152 call(rax);
5153 // Caller pops the arguments (oop, message) and restores rax, r10
5154 BLOCK_COMMENT("} verify_oop");
5155 }
5156
5157 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
5158 if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
5159 // Only pcmpeq has dependency breaking treatment (i.e the execution can begin without
5160 // waiting for the previous result on dst), not vpcmpeqd, so just use vpternlog
5161 vpternlogd(dst, 0xFF, dst, dst, vector_len);
5162 } else if (VM_Version::supports_avx()) {
5163 vpcmpeqd(dst, dst, dst, vector_len);
5164 } else {
5165 assert(VM_Version::supports_sse2(), "");
5166 pcmpeqd(dst, dst);
5167 }
5168 }
5169
5170 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
5171 int extra_slot_offset) {
5172 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
5173 int stackElementSize = Interpreter::stackElementSize;
5174 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
5175 #ifdef ASSERT
5176 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
5177 assert(offset1 - offset == stackElementSize, "correct arithmetic");
5178 #endif
5179 Register scale_reg = noreg;
5180 Address::ScaleFactor scale_factor = Address::no_scale;
5181 if (arg_slot.is_constant()) {
5182 offset += arg_slot.as_constant() * stackElementSize;
5183 } else {
5184 scale_reg = arg_slot.as_register();
5185 scale_factor = Address::times(stackElementSize);
5186 }
5187 offset += wordSize; // return PC is on stack
5188 return Address(rsp, scale_reg, scale_factor, offset);
5189 }
5190
5191 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
5192 if (!VerifyOops) return;
5193
5194 #ifdef _LP64
5195 push(rscratch1);
5196 #endif
5197 push(rax); // save rax,
5198 // addr may contain rsp so we will have to adjust it based on the push
5199 // we just did (and on 64 bit we do two pushes)
5200 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
5201 // stores rax into addr which is backwards of what was intended.
5202 if (addr.uses(rsp)) {
5203 lea(rax, addr);
5204 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
5205 } else {
5206 pushptr(addr);
5207 }
5208
5209 // Pass register number to verify_oop_subroutine
5210 const char* b = nullptr;
5211 {
5212 ResourceMark rm;
5213 stringStream ss;
5214 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
5215 b = code_string(ss.as_string());
5216 }
5217 ExternalAddress buffer((address) b);
5218 pushptr(buffer.addr(), rscratch1);
5219
5220 // call indirectly to solve generation ordering problem
5221 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
5222 call(rax);
5223 // Caller pops the arguments (addr, message) and restores rax, r10.
5224 }
5225
5226 void MacroAssembler::verify_tlab() {
5227 #ifdef ASSERT
5228 if (UseTLAB && VerifyOops) {
5229 Label next, ok;
5230 Register t1 = rsi;
5231 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
5232
5233 push(t1);
5234 NOT_LP64(push(thread_reg));
5235 NOT_LP64(get_thread(thread_reg));
5236
5237 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5238 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
5239 jcc(Assembler::aboveEqual, next);
5240 STOP("assert(top >= start)");
5241 should_not_reach_here();
5242
5243 bind(next);
5244 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
5245 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
5246 jcc(Assembler::aboveEqual, ok);
5247 STOP("assert(top <= end)");
5248 should_not_reach_here();
5249
5250 bind(ok);
5251 NOT_LP64(pop(thread_reg));
5252 pop(t1);
5253 }
5254 #endif
5255 }
5256
5257 class ControlWord {
5258 public:
5259 int32_t _value;
5260
5261 int rounding_control() const { return (_value >> 10) & 3 ; }
5262 int precision_control() const { return (_value >> 8) & 3 ; }
5263 bool precision() const { return ((_value >> 5) & 1) != 0; }
5264 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5265 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5266 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5267 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5268 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5269
5270 void print() const {
5271 // rounding control
5272 const char* rc;
5273 switch (rounding_control()) {
5274 case 0: rc = "round near"; break;
5275 case 1: rc = "round down"; break;
5276 case 2: rc = "round up "; break;
5277 case 3: rc = "chop "; break;
5278 default:
5279 rc = nullptr; // silence compiler warnings
5280 fatal("Unknown rounding control: %d", rounding_control());
5281 };
5282 // precision control
5283 const char* pc;
5284 switch (precision_control()) {
5285 case 0: pc = "24 bits "; break;
5286 case 1: pc = "reserved"; break;
5287 case 2: pc = "53 bits "; break;
5288 case 3: pc = "64 bits "; break;
5289 default:
5290 pc = nullptr; // silence compiler warnings
5291 fatal("Unknown precision control: %d", precision_control());
5292 };
5293 // flags
5294 char f[9];
5295 f[0] = ' ';
5296 f[1] = ' ';
5297 f[2] = (precision ()) ? 'P' : 'p';
5298 f[3] = (underflow ()) ? 'U' : 'u';
5299 f[4] = (overflow ()) ? 'O' : 'o';
5300 f[5] = (zero_divide ()) ? 'Z' : 'z';
5301 f[6] = (denormalized()) ? 'D' : 'd';
5302 f[7] = (invalid ()) ? 'I' : 'i';
5303 f[8] = '\x0';
5304 // output
5305 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
5306 }
5307
5308 };
5309
5310 class StatusWord {
5311 public:
5312 int32_t _value;
5313
5314 bool busy() const { return ((_value >> 15) & 1) != 0; }
5315 bool C3() const { return ((_value >> 14) & 1) != 0; }
5316 bool C2() const { return ((_value >> 10) & 1) != 0; }
5317 bool C1() const { return ((_value >> 9) & 1) != 0; }
5318 bool C0() const { return ((_value >> 8) & 1) != 0; }
5319 int top() const { return (_value >> 11) & 7 ; }
5320 bool error_status() const { return ((_value >> 7) & 1) != 0; }
5321 bool stack_fault() const { return ((_value >> 6) & 1) != 0; }
5322 bool precision() const { return ((_value >> 5) & 1) != 0; }
5323 bool underflow() const { return ((_value >> 4) & 1) != 0; }
5324 bool overflow() const { return ((_value >> 3) & 1) != 0; }
5325 bool zero_divide() const { return ((_value >> 2) & 1) != 0; }
5326 bool denormalized() const { return ((_value >> 1) & 1) != 0; }
5327 bool invalid() const { return ((_value >> 0) & 1) != 0; }
5328
5329 void print() const {
5330 // condition codes
5331 char c[5];
5332 c[0] = (C3()) ? '3' : '-';
5333 c[1] = (C2()) ? '2' : '-';
5334 c[2] = (C1()) ? '1' : '-';
5335 c[3] = (C0()) ? '0' : '-';
5336 c[4] = '\x0';
5337 // flags
5338 char f[9];
5339 f[0] = (error_status()) ? 'E' : '-';
5340 f[1] = (stack_fault ()) ? 'S' : '-';
5341 f[2] = (precision ()) ? 'P' : '-';
5342 f[3] = (underflow ()) ? 'U' : '-';
5343 f[4] = (overflow ()) ? 'O' : '-';
5344 f[5] = (zero_divide ()) ? 'Z' : '-';
5345 f[6] = (denormalized()) ? 'D' : '-';
5346 f[7] = (invalid ()) ? 'I' : '-';
5347 f[8] = '\x0';
5348 // output
5349 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top());
5350 }
5351
5352 };
5353
5354 class TagWord {
5355 public:
5356 int32_t _value;
5357
5358 int tag_at(int i) const { return (_value >> (i*2)) & 3; }
5359
5360 void print() const {
5361 printf("%04x", _value & 0xFFFF);
5362 }
5363
5364 };
5365
5366 class FPU_Register {
5367 public:
5368 int32_t _m0;
5369 int32_t _m1;
5370 int16_t _ex;
5371
5372 bool is_indefinite() const {
5373 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
5374 }
5375
5376 void print() const {
5377 char sign = (_ex < 0) ? '-' : '+';
5378 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " ";
5379 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind);
5380 };
5381
5382 };
5383
5384 class FPU_State {
5385 public:
5386 enum {
5387 register_size = 10,
5388 number_of_registers = 8,
5389 register_mask = 7
5390 };
5391
5392 ControlWord _control_word;
5393 StatusWord _status_word;
5394 TagWord _tag_word;
5395 int32_t _error_offset;
5396 int32_t _error_selector;
5397 int32_t _data_offset;
5398 int32_t _data_selector;
5399 int8_t _register[register_size * number_of_registers];
5400
5401 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
5402 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; }
5403
5404 const char* tag_as_string(int tag) const {
5405 switch (tag) {
5406 case 0: return "valid";
5407 case 1: return "zero";
5408 case 2: return "special";
5409 case 3: return "empty";
5410 }
5411 ShouldNotReachHere();
5412 return nullptr;
5413 }
5414
5415 void print() const {
5416 // print computation registers
5417 { int t = _status_word.top();
5418 for (int i = 0; i < number_of_registers; i++) {
5419 int j = (i - t) & register_mask;
5420 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
5421 st(j)->print();
5422 printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
5423 }
5424 }
5425 printf("\n");
5426 // print control registers
5427 printf("ctrl = "); _control_word.print(); printf("\n");
5428 printf("stat = "); _status_word .print(); printf("\n");
5429 printf("tags = "); _tag_word .print(); printf("\n");
5430 }
5431
5432 };
5433
5434 class Flag_Register {
5435 public:
5436 int32_t _value;
5437
5438 bool overflow() const { return ((_value >> 11) & 1) != 0; }
5439 bool direction() const { return ((_value >> 10) & 1) != 0; }
5440 bool sign() const { return ((_value >> 7) & 1) != 0; }
5441 bool zero() const { return ((_value >> 6) & 1) != 0; }
5442 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; }
5443 bool parity() const { return ((_value >> 2) & 1) != 0; }
5444 bool carry() const { return ((_value >> 0) & 1) != 0; }
5445
5446 void print() const {
5447 // flags
5448 char f[8];
5449 f[0] = (overflow ()) ? 'O' : '-';
5450 f[1] = (direction ()) ? 'D' : '-';
5451 f[2] = (sign ()) ? 'S' : '-';
5452 f[3] = (zero ()) ? 'Z' : '-';
5453 f[4] = (auxiliary_carry()) ? 'A' : '-';
5454 f[5] = (parity ()) ? 'P' : '-';
5455 f[6] = (carry ()) ? 'C' : '-';
5456 f[7] = '\x0';
5457 // output
5458 printf("%08x flags = %s", _value, f);
5459 }
5460
5461 };
5462
5463 class IU_Register {
5464 public:
5465 int32_t _value;
5466
5467 void print() const {
5468 printf("%08x %11d", _value, _value);
5469 }
5470
5471 };
5472
5473 class IU_State {
5474 public:
5475 Flag_Register _eflags;
5476 IU_Register _rdi;
5477 IU_Register _rsi;
5478 IU_Register _rbp;
5479 IU_Register _rsp;
5480 IU_Register _rbx;
5481 IU_Register _rdx;
5482 IU_Register _rcx;
5483 IU_Register _rax;
5484
5485 void print() const {
5486 // computation registers
5487 printf("rax, = "); _rax.print(); printf("\n");
5488 printf("rbx, = "); _rbx.print(); printf("\n");
5489 printf("rcx = "); _rcx.print(); printf("\n");
5490 printf("rdx = "); _rdx.print(); printf("\n");
5491 printf("rdi = "); _rdi.print(); printf("\n");
5492 printf("rsi = "); _rsi.print(); printf("\n");
5493 printf("rbp, = "); _rbp.print(); printf("\n");
5494 printf("rsp = "); _rsp.print(); printf("\n");
5495 printf("\n");
5496 // control registers
5497 printf("flgs = "); _eflags.print(); printf("\n");
5498 }
5499 };
5500
5501
5502 class CPU_State {
5503 public:
5504 FPU_State _fpu_state;
5505 IU_State _iu_state;
5506
5507 void print() const {
5508 printf("--------------------------------------------------\n");
5509 _iu_state .print();
5510 printf("\n");
5511 _fpu_state.print();
5512 printf("--------------------------------------------------\n");
5513 }
5514
5515 };
5516
5517
5518 static void _print_CPU_state(CPU_State* state) {
5519 state->print();
5520 };
5521
5522
5523 void MacroAssembler::print_CPU_state() {
5524 push_CPU_state();
5525 push(rsp); // pass CPU state
5526 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
5527 addptr(rsp, wordSize); // discard argument
5528 pop_CPU_state();
5529 }
5530
5531
5532 #ifndef _LP64
5533 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
5534 static int counter = 0;
5535 FPU_State* fs = &state->_fpu_state;
5536 counter++;
5537 // For leaf calls, only verify that the top few elements remain empty.
5538 // We only need 1 empty at the top for C2 code.
5539 if( stack_depth < 0 ) {
5540 if( fs->tag_for_st(7) != 3 ) {
5541 printf("FPR7 not empty\n");
5542 state->print();
5543 assert(false, "error");
5544 return false;
5545 }
5546 return true; // All other stack states do not matter
5547 }
5548
5549 assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
5550 "bad FPU control word");
5551
5552 // compute stack depth
5553 int i = 0;
5554 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++;
5555 int d = i;
5556 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
5557 // verify findings
5558 if (i != FPU_State::number_of_registers) {
5559 // stack not contiguous
5560 printf("%s: stack not contiguous at ST%d\n", s, i);
5561 state->print();
5562 assert(false, "error");
5563 return false;
5564 }
5565 // check if computed stack depth corresponds to expected stack depth
5566 if (stack_depth < 0) {
5567 // expected stack depth is -stack_depth or less
5568 if (d > -stack_depth) {
5569 // too many elements on the stack
5570 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
5571 state->print();
5572 assert(false, "error");
5573 return false;
5574 }
5575 } else {
5576 // expected stack depth is stack_depth
5577 if (d != stack_depth) {
5578 // wrong stack depth
5579 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
5580 state->print();
5581 assert(false, "error");
5582 return false;
5583 }
5584 }
5585 // everything is cool
5586 return true;
5587 }
5588
5589 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
5590 if (!VerifyFPU) return;
5591 push_CPU_state();
5592 push(rsp); // pass CPU state
5593 ExternalAddress msg((address) s);
5594 // pass message string s
5595 pushptr(msg.addr(), noreg);
5596 push(stack_depth); // pass stack depth
5597 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
5598 addptr(rsp, 3 * wordSize); // discard arguments
5599 // check for error
5600 { Label L;
5601 testl(rax, rax);
5602 jcc(Assembler::notZero, L);
5603 int3(); // break if error condition
5604 bind(L);
5605 }
5606 pop_CPU_state();
5607 }
5608 #endif // _LP64
5609
5610 void MacroAssembler::restore_cpu_control_state_after_jni(Register rscratch) {
5611 // Either restore the MXCSR register after returning from the JNI Call
5612 // or verify that it wasn't changed (with -Xcheck:jni flag).
5613 if (VM_Version::supports_sse()) {
5614 if (RestoreMXCSROnJNICalls) {
5615 ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()), rscratch);
5616 } else if (CheckJNICalls) {
5617 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
5618 }
5619 }
5620 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
5621 vzeroupper();
5622
5623 #ifndef _LP64
5624 // Either restore the x87 floating pointer control word after returning
5625 // from the JNI call or verify that it wasn't changed.
5626 if (CheckJNICalls) {
5627 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
5628 }
5629 #endif // _LP64
5630 }
5631
5632 // ((OopHandle)result).resolve();
5633 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
5634 assert_different_registers(result, tmp);
5635
5636 // Only 64 bit platforms support GCs that require a tmp register
5637 // Only IN_HEAP loads require a thread_tmp register
5638 // OopHandle::resolve is an indirection like jobject.
5639 access_load_at(T_OBJECT, IN_NATIVE,
5640 result, Address(result, 0), tmp, /*tmp_thread*/noreg);
5641 }
5642
5643 // ((WeakHandle)result).resolve();
5644 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
5645 assert_different_registers(rresult, rtmp);
5646 Label resolved;
5647
5648 // A null weak handle resolves to null.
5649 cmpptr(rresult, 0);
5650 jcc(Assembler::equal, resolved);
5651
5652 // Only 64 bit platforms support GCs that require a tmp register
5653 // Only IN_HEAP loads require a thread_tmp register
5654 // WeakHandle::resolve is an indirection like jweak.
5655 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5656 rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
5657 bind(resolved);
5658 }
5659
5660 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
5661 // get mirror
5662 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5663 load_method_holder(mirror, method);
5664 movptr(mirror, Address(mirror, mirror_offset));
5665 resolve_oop_handle(mirror, tmp);
5666 }
5667
5668 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5669 load_method_holder(rresult, rmethod);
5670 movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5671 }
5672
5673 void MacroAssembler::load_method_holder(Register holder, Register method) {
5674 movptr(holder, Address(method, Method::const_offset())); // ConstMethod*
5675 movptr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5676 movptr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5677 }
5678
5679 #ifdef _LP64
5680 void MacroAssembler::load_nklass_compact(Register dst, Register src) {
5681 assert(UseCompactObjectHeaders, "expect compact object headers");
5682 movq(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5683 shrq(dst, markWord::klass_shift);
5684 }
5685 #endif
5686
5687 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
5688 BLOCK_COMMENT("load_klass");
5689 assert_different_registers(src, tmp);
5690 assert_different_registers(dst, tmp);
5691 #ifdef _LP64
5692 if (UseCompactObjectHeaders) {
5693 load_nklass_compact(dst, src);
5694 decode_klass_not_null(dst, tmp);
5695 } else if (UseCompressedClassPointers) {
5696 movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5697 decode_klass_not_null(dst, tmp);
5698 } else
5699 #endif
5700 {
5701 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5702 }
5703 }
5704
5705 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
5706 assert(!UseCompactObjectHeaders, "not with compact headers");
5707 assert_different_registers(src, tmp);
5708 assert_different_registers(dst, tmp);
5709 #ifdef _LP64
5710 if (UseCompressedClassPointers) {
5711 encode_klass_not_null(src, tmp);
5712 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5713 } else
5714 #endif
5715 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
5716 }
5717
5718 void MacroAssembler::cmp_klass(Register klass, Register obj, Register tmp) {
5719 BLOCK_COMMENT("cmp_klass 1");
5720 #ifdef _LP64
5721 if (UseCompactObjectHeaders) {
5722 load_nklass_compact(tmp, obj);
5723 cmpl(klass, tmp);
5724 } else if (UseCompressedClassPointers) {
5725 cmpl(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5726 } else
5727 #endif
5728 {
5729 cmpptr(klass, Address(obj, oopDesc::klass_offset_in_bytes()));
5730 }
5731 }
5732
5733 void MacroAssembler::cmp_klass(Register src, Register dst, Register tmp1, Register tmp2) {
5734 BLOCK_COMMENT("cmp_klass 2");
5735 #ifdef _LP64
5736 if (UseCompactObjectHeaders) {
5737 assert(tmp2 != noreg, "need tmp2");
5738 assert_different_registers(src, dst, tmp1, tmp2);
5739 load_nklass_compact(tmp1, src);
5740 load_nklass_compact(tmp2, dst);
5741 cmpl(tmp1, tmp2);
5742 } else if (UseCompressedClassPointers) {
5743 movl(tmp1, Address(src, oopDesc::klass_offset_in_bytes()));
5744 cmpl(tmp1, Address(dst, oopDesc::klass_offset_in_bytes()));
5745 } else
5746 #endif
5747 {
5748 movptr(tmp1, Address(src, oopDesc::klass_offset_in_bytes()));
5749 cmpptr(tmp1, Address(dst, oopDesc::klass_offset_in_bytes()));
5750 }
5751 }
5752
5753 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
5754 Register tmp1, Register thread_tmp) {
5755 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5756 decorators = AccessInternal::decorator_fixup(decorators, type);
5757 bool as_raw = (decorators & AS_RAW) != 0;
5758 if (as_raw) {
5759 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5760 } else {
5761 bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
5762 }
5763 }
5764
5765 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
5766 Register tmp1, Register tmp2, Register tmp3) {
5767 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5768 decorators = AccessInternal::decorator_fixup(decorators, type);
5769 bool as_raw = (decorators & AS_RAW) != 0;
5770 if (as_raw) {
5771 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5772 } else {
5773 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5774 }
5775 }
5776
5777 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5778 Register thread_tmp, DecoratorSet decorators) {
5779 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
5780 }
5781
5782 // Doesn't do verification, generates fixed size code
5783 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5784 Register thread_tmp, DecoratorSet decorators) {
5785 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
5786 }
5787
5788 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5789 Register tmp2, Register tmp3, DecoratorSet decorators) {
5790 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5791 }
5792
5793 // Used for storing nulls.
5794 void MacroAssembler::store_heap_oop_null(Address dst) {
5795 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5796 }
5797
5798 #ifdef _LP64
5799 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5800 assert(!UseCompactObjectHeaders, "Don't use with compact headers");
5801 if (UseCompressedClassPointers) {
5802 // Store to klass gap in destination
5803 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
5804 }
5805 }
5806
5807 #ifdef ASSERT
5808 void MacroAssembler::verify_heapbase(const char* msg) {
5809 assert (UseCompressedOops, "should be compressed");
5810 assert (Universe::heap() != nullptr, "java heap should be initialized");
5811 if (CheckCompressedOops) {
5812 Label ok;
5813 ExternalAddress src2(CompressedOops::ptrs_base_addr());
5814 const bool is_src2_reachable = reachable(src2);
5815 if (!is_src2_reachable) {
5816 push(rscratch1); // cmpptr trashes rscratch1
5817 }
5818 cmpptr(r12_heapbase, src2, rscratch1);
5819 jcc(Assembler::equal, ok);
5820 STOP(msg);
5821 bind(ok);
5822 if (!is_src2_reachable) {
5823 pop(rscratch1);
5824 }
5825 }
5826 }
5827 #endif
5828
5829 // Algorithm must match oop.inline.hpp encode_heap_oop.
5830 void MacroAssembler::encode_heap_oop(Register r) {
5831 #ifdef ASSERT
5832 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5833 #endif
5834 verify_oop_msg(r, "broken oop in encode_heap_oop");
5835 if (CompressedOops::base() == nullptr) {
5836 if (CompressedOops::shift() != 0) {
5837 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5838 shrq(r, LogMinObjAlignmentInBytes);
5839 }
5840 return;
5841 }
5842 testq(r, r);
5843 cmovq(Assembler::equal, r, r12_heapbase);
5844 subq(r, r12_heapbase);
5845 shrq(r, LogMinObjAlignmentInBytes);
5846 }
5847
5848 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5849 #ifdef ASSERT
5850 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5851 if (CheckCompressedOops) {
5852 Label ok;
5853 testq(r, r);
5854 jcc(Assembler::notEqual, ok);
5855 STOP("null oop passed to encode_heap_oop_not_null");
5856 bind(ok);
5857 }
5858 #endif
5859 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5860 if (CompressedOops::base() != nullptr) {
5861 subq(r, r12_heapbase);
5862 }
5863 if (CompressedOops::shift() != 0) {
5864 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5865 shrq(r, LogMinObjAlignmentInBytes);
5866 }
5867 }
5868
5869 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5870 #ifdef ASSERT
5871 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5872 if (CheckCompressedOops) {
5873 Label ok;
5874 testq(src, src);
5875 jcc(Assembler::notEqual, ok);
5876 STOP("null oop passed to encode_heap_oop_not_null2");
5877 bind(ok);
5878 }
5879 #endif
5880 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5881 if (dst != src) {
5882 movq(dst, src);
5883 }
5884 if (CompressedOops::base() != nullptr) {
5885 subq(dst, r12_heapbase);
5886 }
5887 if (CompressedOops::shift() != 0) {
5888 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5889 shrq(dst, LogMinObjAlignmentInBytes);
5890 }
5891 }
5892
5893 void MacroAssembler::decode_heap_oop(Register r) {
5894 #ifdef ASSERT
5895 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5896 #endif
5897 if (CompressedOops::base() == nullptr) {
5898 if (CompressedOops::shift() != 0) {
5899 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5900 shlq(r, LogMinObjAlignmentInBytes);
5901 }
5902 } else {
5903 Label done;
5904 shlq(r, LogMinObjAlignmentInBytes);
5905 jccb(Assembler::equal, done);
5906 addq(r, r12_heapbase);
5907 bind(done);
5908 }
5909 verify_oop_msg(r, "broken oop in decode_heap_oop");
5910 }
5911
5912 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5913 // Note: it will change flags
5914 assert (UseCompressedOops, "should only be used for compressed headers");
5915 assert (Universe::heap() != nullptr, "java heap should be initialized");
5916 // Cannot assert, unverified entry point counts instructions (see .ad file)
5917 // vtableStubs also counts instructions in pd_code_size_limit.
5918 // Also do not verify_oop as this is called by verify_oop.
5919 if (CompressedOops::shift() != 0) {
5920 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5921 shlq(r, LogMinObjAlignmentInBytes);
5922 if (CompressedOops::base() != nullptr) {
5923 addq(r, r12_heapbase);
5924 }
5925 } else {
5926 assert (CompressedOops::base() == nullptr, "sanity");
5927 }
5928 }
5929
5930 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5931 // Note: it will change flags
5932 assert (UseCompressedOops, "should only be used for compressed headers");
5933 assert (Universe::heap() != nullptr, "java heap should be initialized");
5934 // Cannot assert, unverified entry point counts instructions (see .ad file)
5935 // vtableStubs also counts instructions in pd_code_size_limit.
5936 // Also do not verify_oop as this is called by verify_oop.
5937 if (CompressedOops::shift() != 0) {
5938 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5939 if (LogMinObjAlignmentInBytes == Address::times_8) {
5940 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
5941 } else {
5942 if (dst != src) {
5943 movq(dst, src);
5944 }
5945 shlq(dst, LogMinObjAlignmentInBytes);
5946 if (CompressedOops::base() != nullptr) {
5947 addq(dst, r12_heapbase);
5948 }
5949 }
5950 } else {
5951 assert (CompressedOops::base() == nullptr, "sanity");
5952 if (dst != src) {
5953 movq(dst, src);
5954 }
5955 }
5956 }
5957
5958 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
5959 assert_different_registers(r, tmp);
5960 if (CompressedKlassPointers::base() != nullptr) {
5961 mov64(tmp, (int64_t)CompressedKlassPointers::base());
5962 subq(r, tmp);
5963 }
5964 if (CompressedKlassPointers::shift() != 0) {
5965 shrq(r, CompressedKlassPointers::shift());
5966 }
5967 }
5968
5969 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
5970 assert_different_registers(src, dst);
5971 if (CompressedKlassPointers::base() != nullptr) {
5972 mov64(dst, -(int64_t)CompressedKlassPointers::base());
5973 addq(dst, src);
5974 } else {
5975 movptr(dst, src);
5976 }
5977 if (CompressedKlassPointers::shift() != 0) {
5978 shrq(dst, CompressedKlassPointers::shift());
5979 }
5980 }
5981
5982 void MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
5983 assert_different_registers(r, tmp);
5984 // Note: it will change flags
5985 assert(UseCompressedClassPointers, "should only be used for compressed headers");
5986 // Cannot assert, unverified entry point counts instructions (see .ad file)
5987 // vtableStubs also counts instructions in pd_code_size_limit.
5988 // Also do not verify_oop as this is called by verify_oop.
5989 if (CompressedKlassPointers::shift() != 0) {
5990 shlq(r, CompressedKlassPointers::shift());
5991 }
5992 if (CompressedKlassPointers::base() != nullptr) {
5993 mov64(tmp, (int64_t)CompressedKlassPointers::base());
5994 addq(r, tmp);
5995 }
5996 }
5997
5998 void MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5999 assert_different_registers(src, dst);
6000 // Note: it will change flags
6001 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6002 // Cannot assert, unverified entry point counts instructions (see .ad file)
6003 // vtableStubs also counts instructions in pd_code_size_limit.
6004 // Also do not verify_oop as this is called by verify_oop.
6005
6006 if (CompressedKlassPointers::base() == nullptr &&
6007 CompressedKlassPointers::shift() == 0) {
6008 // The best case scenario is that there is no base or shift. Then it is already
6009 // a pointer that needs nothing but a register rename.
6010 movl(dst, src);
6011 } else {
6012 if (CompressedKlassPointers::shift() <= Address::times_8) {
6013 if (CompressedKlassPointers::base() != nullptr) {
6014 mov64(dst, (int64_t)CompressedKlassPointers::base());
6015 } else {
6016 xorq(dst, dst);
6017 }
6018 if (CompressedKlassPointers::shift() != 0) {
6019 assert(CompressedKlassPointers::shift() == Address::times_8, "klass not aligned on 64bits?");
6020 leaq(dst, Address(dst, src, Address::times_8, 0));
6021 } else {
6022 addq(dst, src);
6023 }
6024 } else {
6025 if (CompressedKlassPointers::base() != nullptr) {
6026 const uint64_t base_right_shifted =
6027 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
6028 mov64(dst, base_right_shifted);
6029 } else {
6030 xorq(dst, dst);
6031 }
6032 addq(dst, src);
6033 shlq(dst, CompressedKlassPointers::shift());
6034 }
6035 }
6036 }
6037
6038 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
6039 assert (UseCompressedOops, "should only be used for compressed headers");
6040 assert (Universe::heap() != nullptr, "java heap should be initialized");
6041 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6042 int oop_index = oop_recorder()->find_index(obj);
6043 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6044 mov_narrow_oop(dst, oop_index, rspec);
6045 }
6046
6047 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
6048 assert (UseCompressedOops, "should only be used for compressed headers");
6049 assert (Universe::heap() != nullptr, "java heap should be initialized");
6050 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6051 int oop_index = oop_recorder()->find_index(obj);
6052 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6053 mov_narrow_oop(dst, oop_index, rspec);
6054 }
6055
6056 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
6057 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6058 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6059 int klass_index = oop_recorder()->find_index(k);
6060 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6061 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6062 }
6063
6064 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
6065 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6066 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6067 int klass_index = oop_recorder()->find_index(k);
6068 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6069 mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6070 }
6071
6072 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
6073 assert (UseCompressedOops, "should only be used for compressed headers");
6074 assert (Universe::heap() != nullptr, "java heap should be initialized");
6075 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6076 int oop_index = oop_recorder()->find_index(obj);
6077 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6078 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6079 }
6080
6081 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
6082 assert (UseCompressedOops, "should only be used for compressed headers");
6083 assert (Universe::heap() != nullptr, "java heap should be initialized");
6084 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6085 int oop_index = oop_recorder()->find_index(obj);
6086 RelocationHolder rspec = oop_Relocation::spec(oop_index);
6087 Assembler::cmp_narrow_oop(dst, oop_index, rspec);
6088 }
6089
6090 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
6091 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6092 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6093 int klass_index = oop_recorder()->find_index(k);
6094 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6095 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6096 }
6097
6098 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
6099 assert (UseCompressedClassPointers, "should only be used for compressed headers");
6100 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
6101 int klass_index = oop_recorder()->find_index(k);
6102 RelocationHolder rspec = metadata_Relocation::spec(klass_index);
6103 Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
6104 }
6105
6106 void MacroAssembler::reinit_heapbase() {
6107 if (UseCompressedOops) {
6108 if (Universe::heap() != nullptr) {
6109 if (CompressedOops::base() == nullptr) {
6110 MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
6111 } else {
6112 mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
6113 }
6114 } else {
6115 movptr(r12_heapbase, ExternalAddress(CompressedOops::ptrs_base_addr()));
6116 }
6117 }
6118 }
6119
6120 #endif // _LP64
6121
6122 #if COMPILER2_OR_JVMCI
6123
6124 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
6125 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6126 // cnt - number of qwords (8-byte words).
6127 // base - start address, qword aligned.
6128 Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
6129 bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
6130 if (use64byteVector) {
6131 vpxor(xtmp, xtmp, xtmp, AVX_512bit);
6132 } else if (MaxVectorSize >= 32) {
6133 vpxor(xtmp, xtmp, xtmp, AVX_256bit);
6134 } else {
6135 pxor(xtmp, xtmp);
6136 }
6137 jmp(L_zero_64_bytes);
6138
6139 BIND(L_loop);
6140 if (MaxVectorSize >= 32) {
6141 fill64(base, 0, xtmp, use64byteVector);
6142 } else {
6143 movdqu(Address(base, 0), xtmp);
6144 movdqu(Address(base, 16), xtmp);
6145 movdqu(Address(base, 32), xtmp);
6146 movdqu(Address(base, 48), xtmp);
6147 }
6148 addptr(base, 64);
6149
6150 BIND(L_zero_64_bytes);
6151 subptr(cnt, 8);
6152 jccb(Assembler::greaterEqual, L_loop);
6153
6154 // Copy trailing 64 bytes
6155 if (use64byteVector) {
6156 addptr(cnt, 8);
6157 jccb(Assembler::equal, L_end);
6158 fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
6159 jmp(L_end);
6160 } else {
6161 addptr(cnt, 4);
6162 jccb(Assembler::less, L_tail);
6163 if (MaxVectorSize >= 32) {
6164 vmovdqu(Address(base, 0), xtmp);
6165 } else {
6166 movdqu(Address(base, 0), xtmp);
6167 movdqu(Address(base, 16), xtmp);
6168 }
6169 }
6170 addptr(base, 32);
6171 subptr(cnt, 4);
6172
6173 BIND(L_tail);
6174 addptr(cnt, 4);
6175 jccb(Assembler::lessEqual, L_end);
6176 if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
6177 fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
6178 } else {
6179 decrement(cnt);
6180
6181 BIND(L_sloop);
6182 movq(Address(base, 0), xtmp);
6183 addptr(base, 8);
6184 decrement(cnt);
6185 jccb(Assembler::greaterEqual, L_sloop);
6186 }
6187 BIND(L_end);
6188 }
6189
6190 // Clearing constant sized memory using YMM/ZMM registers.
6191 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
6192 assert(UseAVX > 2 && VM_Version::supports_avx512vl(), "");
6193 bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
6194
6195 int vector64_count = (cnt & (~0x7)) >> 3;
6196 cnt = cnt & 0x7;
6197 const int fill64_per_loop = 4;
6198 const int max_unrolled_fill64 = 8;
6199
6200 // 64 byte initialization loop.
6201 vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
6202 int start64 = 0;
6203 if (vector64_count > max_unrolled_fill64) {
6204 Label LOOP;
6205 Register index = rtmp;
6206
6207 start64 = vector64_count - (vector64_count % fill64_per_loop);
6208
6209 movl(index, 0);
6210 BIND(LOOP);
6211 for (int i = 0; i < fill64_per_loop; i++) {
6212 fill64(Address(base, index, Address::times_1, i * 64), xtmp, use64byteVector);
6213 }
6214 addl(index, fill64_per_loop * 64);
6215 cmpl(index, start64 * 64);
6216 jccb(Assembler::less, LOOP);
6217 }
6218 for (int i = start64; i < vector64_count; i++) {
6219 fill64(base, i * 64, xtmp, use64byteVector);
6220 }
6221
6222 // Clear remaining 64 byte tail.
6223 int disp = vector64_count * 64;
6224 if (cnt) {
6225 switch (cnt) {
6226 case 1:
6227 movq(Address(base, disp), xtmp);
6228 break;
6229 case 2:
6230 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_128bit);
6231 break;
6232 case 3:
6233 movl(rtmp, 0x7);
6234 kmovwl(mask, rtmp);
6235 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_256bit);
6236 break;
6237 case 4:
6238 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6239 break;
6240 case 5:
6241 if (use64byteVector) {
6242 movl(rtmp, 0x1F);
6243 kmovwl(mask, rtmp);
6244 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6245 } else {
6246 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6247 movq(Address(base, disp + 32), xtmp);
6248 }
6249 break;
6250 case 6:
6251 if (use64byteVector) {
6252 movl(rtmp, 0x3F);
6253 kmovwl(mask, rtmp);
6254 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6255 } else {
6256 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6257 evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, false, Assembler::AVX_128bit);
6258 }
6259 break;
6260 case 7:
6261 if (use64byteVector) {
6262 movl(rtmp, 0x7F);
6263 kmovwl(mask, rtmp);
6264 evmovdqu(T_LONG, mask, Address(base, disp), xtmp, true, Assembler::AVX_512bit);
6265 } else {
6266 evmovdqu(T_LONG, k0, Address(base, disp), xtmp, false, Assembler::AVX_256bit);
6267 movl(rtmp, 0x7);
6268 kmovwl(mask, rtmp);
6269 evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, true, Assembler::AVX_256bit);
6270 }
6271 break;
6272 default:
6273 fatal("Unexpected length : %d\n",cnt);
6274 break;
6275 }
6276 }
6277 }
6278
6279 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
6280 bool is_large, KRegister mask) {
6281 // cnt - number of qwords (8-byte words).
6282 // base - start address, qword aligned.
6283 // is_large - if optimizers know cnt is larger than InitArrayShortSize
6284 assert(base==rdi, "base register must be edi for rep stos");
6285 assert(tmp==rax, "tmp register must be eax for rep stos");
6286 assert(cnt==rcx, "cnt register must be ecx for rep stos");
6287 assert(InitArrayShortSize % BytesPerLong == 0,
6288 "InitArrayShortSize should be the multiple of BytesPerLong");
6289
6290 Label DONE;
6291 if (!is_large || !UseXMMForObjInit) {
6292 xorptr(tmp, tmp);
6293 }
6294
6295 if (!is_large) {
6296 Label LOOP, LONG;
6297 cmpptr(cnt, InitArrayShortSize/BytesPerLong);
6298 jccb(Assembler::greater, LONG);
6299
6300 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6301
6302 decrement(cnt);
6303 jccb(Assembler::negative, DONE); // Zero length
6304
6305 // Use individual pointer-sized stores for small counts:
6306 BIND(LOOP);
6307 movptr(Address(base, cnt, Address::times_ptr), tmp);
6308 decrement(cnt);
6309 jccb(Assembler::greaterEqual, LOOP);
6310 jmpb(DONE);
6311
6312 BIND(LONG);
6313 }
6314
6315 // Use longer rep-prefixed ops for non-small counts:
6316 if (UseFastStosb) {
6317 shlptr(cnt, 3); // convert to number of bytes
6318 rep_stosb();
6319 } else if (UseXMMForObjInit) {
6320 xmm_clear_mem(base, cnt, tmp, xtmp, mask);
6321 } else {
6322 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
6323 rep_stos();
6324 }
6325
6326 BIND(DONE);
6327 }
6328
6329 #endif //COMPILER2_OR_JVMCI
6330
6331
6332 void MacroAssembler::generate_fill(BasicType t, bool aligned,
6333 Register to, Register value, Register count,
6334 Register rtmp, XMMRegister xtmp) {
6335 ShortBranchVerifier sbv(this);
6336 assert_different_registers(to, value, count, rtmp);
6337 Label L_exit;
6338 Label L_fill_2_bytes, L_fill_4_bytes;
6339
6340 #if defined(COMPILER2) && defined(_LP64)
6341 if(MaxVectorSize >=32 &&
6342 VM_Version::supports_avx512vlbw() &&
6343 VM_Version::supports_bmi2()) {
6344 generate_fill_avx3(t, to, value, count, rtmp, xtmp);
6345 return;
6346 }
6347 #endif
6348
6349 int shift = -1;
6350 switch (t) {
6351 case T_BYTE:
6352 shift = 2;
6353 break;
6354 case T_SHORT:
6355 shift = 1;
6356 break;
6357 case T_INT:
6358 shift = 0;
6359 break;
6360 default: ShouldNotReachHere();
6361 }
6362
6363 if (t == T_BYTE) {
6364 andl(value, 0xff);
6365 movl(rtmp, value);
6366 shll(rtmp, 8);
6367 orl(value, rtmp);
6368 }
6369 if (t == T_SHORT) {
6370 andl(value, 0xffff);
6371 }
6372 if (t == T_BYTE || t == T_SHORT) {
6373 movl(rtmp, value);
6374 shll(rtmp, 16);
6375 orl(value, rtmp);
6376 }
6377
6378 cmpptr(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
6379 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
6380 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
6381 Label L_skip_align2;
6382 // align source address at 4 bytes address boundary
6383 if (t == T_BYTE) {
6384 Label L_skip_align1;
6385 // One byte misalignment happens only for byte arrays
6386 testptr(to, 1);
6387 jccb(Assembler::zero, L_skip_align1);
6388 movb(Address(to, 0), value);
6389 increment(to);
6390 decrement(count);
6391 BIND(L_skip_align1);
6392 }
6393 // Two bytes misalignment happens only for byte and short (char) arrays
6394 testptr(to, 2);
6395 jccb(Assembler::zero, L_skip_align2);
6396 movw(Address(to, 0), value);
6397 addptr(to, 2);
6398 subptr(count, 1<<(shift-1));
6399 BIND(L_skip_align2);
6400 }
6401 if (UseSSE < 2) {
6402 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6403 // Fill 32-byte chunks
6404 subptr(count, 8 << shift);
6405 jcc(Assembler::less, L_check_fill_8_bytes);
6406 align(16);
6407
6408 BIND(L_fill_32_bytes_loop);
6409
6410 for (int i = 0; i < 32; i += 4) {
6411 movl(Address(to, i), value);
6412 }
6413
6414 addptr(to, 32);
6415 subptr(count, 8 << shift);
6416 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6417 BIND(L_check_fill_8_bytes);
6418 addptr(count, 8 << shift);
6419 jccb(Assembler::zero, L_exit);
6420 jmpb(L_fill_8_bytes);
6421
6422 //
6423 // length is too short, just fill qwords
6424 //
6425 BIND(L_fill_8_bytes_loop);
6426 movl(Address(to, 0), value);
6427 movl(Address(to, 4), value);
6428 addptr(to, 8);
6429 BIND(L_fill_8_bytes);
6430 subptr(count, 1 << (shift + 1));
6431 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6432 // fall through to fill 4 bytes
6433 } else {
6434 Label L_fill_32_bytes;
6435 if (!UseUnalignedLoadStores) {
6436 // align to 8 bytes, we know we are 4 byte aligned to start
6437 testptr(to, 4);
6438 jccb(Assembler::zero, L_fill_32_bytes);
6439 movl(Address(to, 0), value);
6440 addptr(to, 4);
6441 subptr(count, 1<<shift);
6442 }
6443 BIND(L_fill_32_bytes);
6444 {
6445 assert( UseSSE >= 2, "supported cpu only" );
6446 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
6447 movdl(xtmp, value);
6448 if (UseAVX >= 2 && UseUnalignedLoadStores) {
6449 Label L_check_fill_32_bytes;
6450 if (UseAVX > 2) {
6451 // Fill 64-byte chunks
6452 Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
6453
6454 // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
6455 cmpptr(count, VM_Version::avx3_threshold());
6456 jccb(Assembler::below, L_check_fill_64_bytes_avx2);
6457
6458 vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
6459
6460 subptr(count, 16 << shift);
6461 jccb(Assembler::less, L_check_fill_32_bytes);
6462 align(16);
6463
6464 BIND(L_fill_64_bytes_loop_avx3);
6465 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
6466 addptr(to, 64);
6467 subptr(count, 16 << shift);
6468 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
6469 jmpb(L_check_fill_32_bytes);
6470
6471 BIND(L_check_fill_64_bytes_avx2);
6472 }
6473 // Fill 64-byte chunks
6474 Label L_fill_64_bytes_loop;
6475 vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
6476
6477 subptr(count, 16 << shift);
6478 jcc(Assembler::less, L_check_fill_32_bytes);
6479 align(16);
6480
6481 BIND(L_fill_64_bytes_loop);
6482 vmovdqu(Address(to, 0), xtmp);
6483 vmovdqu(Address(to, 32), xtmp);
6484 addptr(to, 64);
6485 subptr(count, 16 << shift);
6486 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
6487
6488 BIND(L_check_fill_32_bytes);
6489 addptr(count, 8 << shift);
6490 jccb(Assembler::less, L_check_fill_8_bytes);
6491 vmovdqu(Address(to, 0), xtmp);
6492 addptr(to, 32);
6493 subptr(count, 8 << shift);
6494
6495 BIND(L_check_fill_8_bytes);
6496 // clean upper bits of YMM registers
6497 movdl(xtmp, value);
6498 pshufd(xtmp, xtmp, 0);
6499 } else {
6500 // Fill 32-byte chunks
6501 pshufd(xtmp, xtmp, 0);
6502
6503 subptr(count, 8 << shift);
6504 jcc(Assembler::less, L_check_fill_8_bytes);
6505 align(16);
6506
6507 BIND(L_fill_32_bytes_loop);
6508
6509 if (UseUnalignedLoadStores) {
6510 movdqu(Address(to, 0), xtmp);
6511 movdqu(Address(to, 16), xtmp);
6512 } else {
6513 movq(Address(to, 0), xtmp);
6514 movq(Address(to, 8), xtmp);
6515 movq(Address(to, 16), xtmp);
6516 movq(Address(to, 24), xtmp);
6517 }
6518
6519 addptr(to, 32);
6520 subptr(count, 8 << shift);
6521 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
6522
6523 BIND(L_check_fill_8_bytes);
6524 }
6525 addptr(count, 8 << shift);
6526 jccb(Assembler::zero, L_exit);
6527 jmpb(L_fill_8_bytes);
6528
6529 //
6530 // length is too short, just fill qwords
6531 //
6532 BIND(L_fill_8_bytes_loop);
6533 movq(Address(to, 0), xtmp);
6534 addptr(to, 8);
6535 BIND(L_fill_8_bytes);
6536 subptr(count, 1 << (shift + 1));
6537 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
6538 }
6539 }
6540 // fill trailing 4 bytes
6541 BIND(L_fill_4_bytes);
6542 testl(count, 1<<shift);
6543 jccb(Assembler::zero, L_fill_2_bytes);
6544 movl(Address(to, 0), value);
6545 if (t == T_BYTE || t == T_SHORT) {
6546 Label L_fill_byte;
6547 addptr(to, 4);
6548 BIND(L_fill_2_bytes);
6549 // fill trailing 2 bytes
6550 testl(count, 1<<(shift-1));
6551 jccb(Assembler::zero, L_fill_byte);
6552 movw(Address(to, 0), value);
6553 if (t == T_BYTE) {
6554 addptr(to, 2);
6555 BIND(L_fill_byte);
6556 // fill trailing byte
6557 testl(count, 1);
6558 jccb(Assembler::zero, L_exit);
6559 movb(Address(to, 0), value);
6560 } else {
6561 BIND(L_fill_byte);
6562 }
6563 } else {
6564 BIND(L_fill_2_bytes);
6565 }
6566 BIND(L_exit);
6567 }
6568
6569 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
6570 switch(type) {
6571 case T_BYTE:
6572 case T_BOOLEAN:
6573 evpbroadcastb(dst, src, vector_len);
6574 break;
6575 case T_SHORT:
6576 case T_CHAR:
6577 evpbroadcastw(dst, src, vector_len);
6578 break;
6579 case T_INT:
6580 case T_FLOAT:
6581 evpbroadcastd(dst, src, vector_len);
6582 break;
6583 case T_LONG:
6584 case T_DOUBLE:
6585 evpbroadcastq(dst, src, vector_len);
6586 break;
6587 default:
6588 fatal("Unhandled type : %s", type2name(type));
6589 break;
6590 }
6591 }
6592
6593 // encode char[] to byte[] in ISO_8859_1 or ASCII
6594 //@IntrinsicCandidate
6595 //private static int implEncodeISOArray(byte[] sa, int sp,
6596 //byte[] da, int dp, int len) {
6597 // int i = 0;
6598 // for (; i < len; i++) {
6599 // char c = StringUTF16.getChar(sa, sp++);
6600 // if (c > '\u00FF')
6601 // break;
6602 // da[dp++] = (byte)c;
6603 // }
6604 // return i;
6605 //}
6606 //
6607 //@IntrinsicCandidate
6608 //private static int implEncodeAsciiArray(char[] sa, int sp,
6609 // byte[] da, int dp, int len) {
6610 // int i = 0;
6611 // for (; i < len; i++) {
6612 // char c = sa[sp++];
6613 // if (c >= '\u0080')
6614 // break;
6615 // da[dp++] = (byte)c;
6616 // }
6617 // return i;
6618 //}
6619 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
6620 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
6621 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
6622 Register tmp5, Register result, bool ascii) {
6623
6624 // rsi: src
6625 // rdi: dst
6626 // rdx: len
6627 // rcx: tmp5
6628 // rax: result
6629 ShortBranchVerifier sbv(this);
6630 assert_different_registers(src, dst, len, tmp5, result);
6631 Label L_done, L_copy_1_char, L_copy_1_char_exit;
6632
6633 int mask = ascii ? 0xff80ff80 : 0xff00ff00;
6634 int short_mask = ascii ? 0xff80 : 0xff00;
6635
6636 // set result
6637 xorl(result, result);
6638 // check for zero length
6639 testl(len, len);
6640 jcc(Assembler::zero, L_done);
6641
6642 movl(result, len);
6643
6644 // Setup pointers
6645 lea(src, Address(src, len, Address::times_2)); // char[]
6646 lea(dst, Address(dst, len, Address::times_1)); // byte[]
6647 negptr(len);
6648
6649 if (UseSSE42Intrinsics || UseAVX >= 2) {
6650 Label L_copy_8_chars, L_copy_8_chars_exit;
6651 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
6652
6653 if (UseAVX >= 2) {
6654 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
6655 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6656 movdl(tmp1Reg, tmp5);
6657 vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
6658 jmp(L_chars_32_check);
6659
6660 bind(L_copy_32_chars);
6661 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
6662 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
6663 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6664 vptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6665 jccb(Assembler::notZero, L_copy_32_chars_exit);
6666 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
6667 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
6668 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
6669
6670 bind(L_chars_32_check);
6671 addptr(len, 32);
6672 jcc(Assembler::lessEqual, L_copy_32_chars);
6673
6674 bind(L_copy_32_chars_exit);
6675 subptr(len, 16);
6676 jccb(Assembler::greater, L_copy_16_chars_exit);
6677
6678 } else if (UseSSE42Intrinsics) {
6679 movl(tmp5, mask); // create mask to test for Unicode or non-ASCII chars in vector
6680 movdl(tmp1Reg, tmp5);
6681 pshufd(tmp1Reg, tmp1Reg, 0);
6682 jmpb(L_chars_16_check);
6683 }
6684
6685 bind(L_copy_16_chars);
6686 if (UseAVX >= 2) {
6687 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
6688 vptest(tmp2Reg, tmp1Reg);
6689 jcc(Assembler::notZero, L_copy_16_chars_exit);
6690 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
6691 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
6692 } else {
6693 if (UseAVX > 0) {
6694 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6695 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6696 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
6697 } else {
6698 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
6699 por(tmp2Reg, tmp3Reg);
6700 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
6701 por(tmp2Reg, tmp4Reg);
6702 }
6703 ptest(tmp2Reg, tmp1Reg); // check for Unicode or non-ASCII chars in vector
6704 jccb(Assembler::notZero, L_copy_16_chars_exit);
6705 packuswb(tmp3Reg, tmp4Reg);
6706 }
6707 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
6708
6709 bind(L_chars_16_check);
6710 addptr(len, 16);
6711 jcc(Assembler::lessEqual, L_copy_16_chars);
6712
6713 bind(L_copy_16_chars_exit);
6714 if (UseAVX >= 2) {
6715 // clean upper bits of YMM registers
6716 vpxor(tmp2Reg, tmp2Reg);
6717 vpxor(tmp3Reg, tmp3Reg);
6718 vpxor(tmp4Reg, tmp4Reg);
6719 movdl(tmp1Reg, tmp5);
6720 pshufd(tmp1Reg, tmp1Reg, 0);
6721 }
6722 subptr(len, 8);
6723 jccb(Assembler::greater, L_copy_8_chars_exit);
6724
6725 bind(L_copy_8_chars);
6726 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
6727 ptest(tmp3Reg, tmp1Reg);
6728 jccb(Assembler::notZero, L_copy_8_chars_exit);
6729 packuswb(tmp3Reg, tmp1Reg);
6730 movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
6731 addptr(len, 8);
6732 jccb(Assembler::lessEqual, L_copy_8_chars);
6733
6734 bind(L_copy_8_chars_exit);
6735 subptr(len, 8);
6736 jccb(Assembler::zero, L_done);
6737 }
6738
6739 bind(L_copy_1_char);
6740 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
6741 testl(tmp5, short_mask); // check if Unicode or non-ASCII char
6742 jccb(Assembler::notZero, L_copy_1_char_exit);
6743 movb(Address(dst, len, Address::times_1, 0), tmp5);
6744 addptr(len, 1);
6745 jccb(Assembler::less, L_copy_1_char);
6746
6747 bind(L_copy_1_char_exit);
6748 addptr(result, len); // len is negative count of not processed elements
6749
6750 bind(L_done);
6751 }
6752
6753 #ifdef _LP64
6754 /**
6755 * Helper for multiply_to_len().
6756 */
6757 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
6758 addq(dest_lo, src1);
6759 adcq(dest_hi, 0);
6760 addq(dest_lo, src2);
6761 adcq(dest_hi, 0);
6762 }
6763
6764 /**
6765 * Multiply 64 bit by 64 bit first loop.
6766 */
6767 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
6768 Register y, Register y_idx, Register z,
6769 Register carry, Register product,
6770 Register idx, Register kdx) {
6771 //
6772 // jlong carry, x[], y[], z[];
6773 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6774 // huge_128 product = y[idx] * x[xstart] + carry;
6775 // z[kdx] = (jlong)product;
6776 // carry = (jlong)(product >>> 64);
6777 // }
6778 // z[xstart] = carry;
6779 //
6780
6781 Label L_first_loop, L_first_loop_exit;
6782 Label L_one_x, L_one_y, L_multiply;
6783
6784 decrementl(xstart);
6785 jcc(Assembler::negative, L_one_x);
6786
6787 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
6788 rorq(x_xstart, 32); // convert big-endian to little-endian
6789
6790 bind(L_first_loop);
6791 decrementl(idx);
6792 jcc(Assembler::negative, L_first_loop_exit);
6793 decrementl(idx);
6794 jcc(Assembler::negative, L_one_y);
6795 movq(y_idx, Address(y, idx, Address::times_4, 0));
6796 rorq(y_idx, 32); // convert big-endian to little-endian
6797 bind(L_multiply);
6798 movq(product, x_xstart);
6799 mulq(y_idx); // product(rax) * y_idx -> rdx:rax
6800 addq(product, carry);
6801 adcq(rdx, 0);
6802 subl(kdx, 2);
6803 movl(Address(z, kdx, Address::times_4, 4), product);
6804 shrq(product, 32);
6805 movl(Address(z, kdx, Address::times_4, 0), product);
6806 movq(carry, rdx);
6807 jmp(L_first_loop);
6808
6809 bind(L_one_y);
6810 movl(y_idx, Address(y, 0));
6811 jmp(L_multiply);
6812
6813 bind(L_one_x);
6814 movl(x_xstart, Address(x, 0));
6815 jmp(L_first_loop);
6816
6817 bind(L_first_loop_exit);
6818 }
6819
6820 /**
6821 * Multiply 64 bit by 64 bit and add 128 bit.
6822 */
6823 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
6824 Register yz_idx, Register idx,
6825 Register carry, Register product, int offset) {
6826 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6827 // z[kdx] = (jlong)product;
6828
6829 movq(yz_idx, Address(y, idx, Address::times_4, offset));
6830 rorq(yz_idx, 32); // convert big-endian to little-endian
6831 movq(product, x_xstart);
6832 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6833 movq(yz_idx, Address(z, idx, Address::times_4, offset));
6834 rorq(yz_idx, 32); // convert big-endian to little-endian
6835
6836 add2_with_carry(rdx, product, carry, yz_idx);
6837
6838 movl(Address(z, idx, Address::times_4, offset+4), product);
6839 shrq(product, 32);
6840 movl(Address(z, idx, Address::times_4, offset), product);
6841
6842 }
6843
6844 /**
6845 * Multiply 128 bit by 128 bit. Unrolled inner loop.
6846 */
6847 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
6848 Register yz_idx, Register idx, Register jdx,
6849 Register carry, Register product,
6850 Register carry2) {
6851 // jlong carry, x[], y[], z[];
6852 // int kdx = ystart+1;
6853 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6854 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6855 // z[kdx+idx+1] = (jlong)product;
6856 // jlong carry2 = (jlong)(product >>> 64);
6857 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6858 // z[kdx+idx] = (jlong)product;
6859 // carry = (jlong)(product >>> 64);
6860 // }
6861 // idx += 2;
6862 // if (idx > 0) {
6863 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6864 // z[kdx+idx] = (jlong)product;
6865 // carry = (jlong)(product >>> 64);
6866 // }
6867 //
6868
6869 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6870
6871 movl(jdx, idx);
6872 andl(jdx, 0xFFFFFFFC);
6873 shrl(jdx, 2);
6874
6875 bind(L_third_loop);
6876 subl(jdx, 1);
6877 jcc(Assembler::negative, L_third_loop_exit);
6878 subl(idx, 4);
6879
6880 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6881 movq(carry2, rdx);
6882
6883 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6884 movq(carry, rdx);
6885 jmp(L_third_loop);
6886
6887 bind (L_third_loop_exit);
6888
6889 andl (idx, 0x3);
6890 jcc(Assembler::zero, L_post_third_loop_done);
6891
6892 Label L_check_1;
6893 subl(idx, 2);
6894 jcc(Assembler::negative, L_check_1);
6895
6896 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6897 movq(carry, rdx);
6898
6899 bind (L_check_1);
6900 addl (idx, 0x2);
6901 andl (idx, 0x1);
6902 subl(idx, 1);
6903 jcc(Assembler::negative, L_post_third_loop_done);
6904
6905 movl(yz_idx, Address(y, idx, Address::times_4, 0));
6906 movq(product, x_xstart);
6907 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
6908 movl(yz_idx, Address(z, idx, Address::times_4, 0));
6909
6910 add2_with_carry(rdx, product, yz_idx, carry);
6911
6912 movl(Address(z, idx, Address::times_4, 0), product);
6913 shrq(product, 32);
6914
6915 shlq(rdx, 32);
6916 orq(product, rdx);
6917 movq(carry, product);
6918
6919 bind(L_post_third_loop_done);
6920 }
6921
6922 /**
6923 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
6924 *
6925 */
6926 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
6927 Register carry, Register carry2,
6928 Register idx, Register jdx,
6929 Register yz_idx1, Register yz_idx2,
6930 Register tmp, Register tmp3, Register tmp4) {
6931 assert(UseBMI2Instructions, "should be used only when BMI2 is available");
6932
6933 // jlong carry, x[], y[], z[];
6934 // int kdx = ystart+1;
6935 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6936 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6937 // jlong carry2 = (jlong)(tmp3 >>> 64);
6938 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2;
6939 // carry = (jlong)(tmp4 >>> 64);
6940 // z[kdx+idx+1] = (jlong)tmp3;
6941 // z[kdx+idx] = (jlong)tmp4;
6942 // }
6943 // idx += 2;
6944 // if (idx > 0) {
6945 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6946 // z[kdx+idx] = (jlong)yz_idx1;
6947 // carry = (jlong)(yz_idx1 >>> 64);
6948 // }
6949 //
6950
6951 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6952
6953 movl(jdx, idx);
6954 andl(jdx, 0xFFFFFFFC);
6955 shrl(jdx, 2);
6956
6957 bind(L_third_loop);
6958 subl(jdx, 1);
6959 jcc(Assembler::negative, L_third_loop_exit);
6960 subl(idx, 4);
6961
6962 movq(yz_idx1, Address(y, idx, Address::times_4, 8));
6963 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6964 movq(yz_idx2, Address(y, idx, Address::times_4, 0));
6965 rorxq(yz_idx2, yz_idx2, 32);
6966
6967 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
6968 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp
6969
6970 movq(yz_idx1, Address(z, idx, Address::times_4, 8));
6971 rorxq(yz_idx1, yz_idx1, 32);
6972 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
6973 rorxq(yz_idx2, yz_idx2, 32);
6974
6975 if (VM_Version::supports_adx()) {
6976 adcxq(tmp3, carry);
6977 adoxq(tmp3, yz_idx1);
6978
6979 adcxq(tmp4, tmp);
6980 adoxq(tmp4, yz_idx2);
6981
6982 movl(carry, 0); // does not affect flags
6983 adcxq(carry2, carry);
6984 adoxq(carry2, carry);
6985 } else {
6986 add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6987 add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6988 }
6989 movq(carry, carry2);
6990
6991 movl(Address(z, idx, Address::times_4, 12), tmp3);
6992 shrq(tmp3, 32);
6993 movl(Address(z, idx, Address::times_4, 8), tmp3);
6994
6995 movl(Address(z, idx, Address::times_4, 4), tmp4);
6996 shrq(tmp4, 32);
6997 movl(Address(z, idx, Address::times_4, 0), tmp4);
6998
6999 jmp(L_third_loop);
7000
7001 bind (L_third_loop_exit);
7002
7003 andl (idx, 0x3);
7004 jcc(Assembler::zero, L_post_third_loop_done);
7005
7006 Label L_check_1;
7007 subl(idx, 2);
7008 jcc(Assembler::negative, L_check_1);
7009
7010 movq(yz_idx1, Address(y, idx, Address::times_4, 0));
7011 rorxq(yz_idx1, yz_idx1, 32);
7012 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3
7013 movq(yz_idx2, Address(z, idx, Address::times_4, 0));
7014 rorxq(yz_idx2, yz_idx2, 32);
7015
7016 add2_with_carry(tmp4, tmp3, carry, yz_idx2);
7017
7018 movl(Address(z, idx, Address::times_4, 4), tmp3);
7019 shrq(tmp3, 32);
7020 movl(Address(z, idx, Address::times_4, 0), tmp3);
7021 movq(carry, tmp4);
7022
7023 bind (L_check_1);
7024 addl (idx, 0x2);
7025 andl (idx, 0x1);
7026 subl(idx, 1);
7027 jcc(Assembler::negative, L_post_third_loop_done);
7028 movl(tmp4, Address(y, idx, Address::times_4, 0));
7029 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3
7030 movl(tmp4, Address(z, idx, Address::times_4, 0));
7031
7032 add2_with_carry(carry2, tmp3, tmp4, carry);
7033
7034 movl(Address(z, idx, Address::times_4, 0), tmp3);
7035 shrq(tmp3, 32);
7036
7037 shlq(carry2, 32);
7038 orq(tmp3, carry2);
7039 movq(carry, tmp3);
7040
7041 bind(L_post_third_loop_done);
7042 }
7043
7044 /**
7045 * Code for BigInteger::multiplyToLen() intrinsic.
7046 *
7047 * rdi: x
7048 * rax: xlen
7049 * rsi: y
7050 * rcx: ylen
7051 * r8: z
7052 * r11: tmp0
7053 * r12: tmp1
7054 * r13: tmp2
7055 * r14: tmp3
7056 * r15: tmp4
7057 * rbx: tmp5
7058 *
7059 */
7060 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register tmp0,
7061 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
7062 ShortBranchVerifier sbv(this);
7063 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
7064
7065 push(tmp0);
7066 push(tmp1);
7067 push(tmp2);
7068 push(tmp3);
7069 push(tmp4);
7070 push(tmp5);
7071
7072 push(xlen);
7073
7074 const Register idx = tmp1;
7075 const Register kdx = tmp2;
7076 const Register xstart = tmp3;
7077
7078 const Register y_idx = tmp4;
7079 const Register carry = tmp5;
7080 const Register product = xlen;
7081 const Register x_xstart = tmp0;
7082
7083 // First Loop.
7084 //
7085 // final static long LONG_MASK = 0xffffffffL;
7086 // int xstart = xlen - 1;
7087 // int ystart = ylen - 1;
7088 // long carry = 0;
7089 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
7090 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
7091 // z[kdx] = (int)product;
7092 // carry = product >>> 32;
7093 // }
7094 // z[xstart] = (int)carry;
7095 //
7096
7097 movl(idx, ylen); // idx = ylen;
7098 lea(kdx, Address(xlen, ylen)); // kdx = xlen+ylen;
7099 xorq(carry, carry); // carry = 0;
7100
7101 Label L_done;
7102
7103 movl(xstart, xlen);
7104 decrementl(xstart);
7105 jcc(Assembler::negative, L_done);
7106
7107 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
7108
7109 Label L_second_loop;
7110 testl(kdx, kdx);
7111 jcc(Assembler::zero, L_second_loop);
7112
7113 Label L_carry;
7114 subl(kdx, 1);
7115 jcc(Assembler::zero, L_carry);
7116
7117 movl(Address(z, kdx, Address::times_4, 0), carry);
7118 shrq(carry, 32);
7119 subl(kdx, 1);
7120
7121 bind(L_carry);
7122 movl(Address(z, kdx, Address::times_4, 0), carry);
7123
7124 // Second and third (nested) loops.
7125 //
7126 // for (int i = xstart-1; i >= 0; i--) { // Second loop
7127 // carry = 0;
7128 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
7129 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
7130 // (z[k] & LONG_MASK) + carry;
7131 // z[k] = (int)product;
7132 // carry = product >>> 32;
7133 // }
7134 // z[i] = (int)carry;
7135 // }
7136 //
7137 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
7138
7139 const Register jdx = tmp1;
7140
7141 bind(L_second_loop);
7142 xorl(carry, carry); // carry = 0;
7143 movl(jdx, ylen); // j = ystart+1
7144
7145 subl(xstart, 1); // i = xstart-1;
7146 jcc(Assembler::negative, L_done);
7147
7148 push (z);
7149
7150 Label L_last_x;
7151 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
7152 subl(xstart, 1); // i = xstart-1;
7153 jcc(Assembler::negative, L_last_x);
7154
7155 if (UseBMI2Instructions) {
7156 movq(rdx, Address(x, xstart, Address::times_4, 0));
7157 rorxq(rdx, rdx, 32); // convert big-endian to little-endian
7158 } else {
7159 movq(x_xstart, Address(x, xstart, Address::times_4, 0));
7160 rorq(x_xstart, 32); // convert big-endian to little-endian
7161 }
7162
7163 Label L_third_loop_prologue;
7164 bind(L_third_loop_prologue);
7165
7166 push (x);
7167 push (xstart);
7168 push (ylen);
7169
7170
7171 if (UseBMI2Instructions) {
7172 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
7173 } else { // !UseBMI2Instructions
7174 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
7175 }
7176
7177 pop(ylen);
7178 pop(xlen);
7179 pop(x);
7180 pop(z);
7181
7182 movl(tmp3, xlen);
7183 addl(tmp3, 1);
7184 movl(Address(z, tmp3, Address::times_4, 0), carry);
7185 subl(tmp3, 1);
7186 jccb(Assembler::negative, L_done);
7187
7188 shrq(carry, 32);
7189 movl(Address(z, tmp3, Address::times_4, 0), carry);
7190 jmp(L_second_loop);
7191
7192 // Next infrequent code is moved outside loops.
7193 bind(L_last_x);
7194 if (UseBMI2Instructions) {
7195 movl(rdx, Address(x, 0));
7196 } else {
7197 movl(x_xstart, Address(x, 0));
7198 }
7199 jmp(L_third_loop_prologue);
7200
7201 bind(L_done);
7202
7203 pop(xlen);
7204
7205 pop(tmp5);
7206 pop(tmp4);
7207 pop(tmp3);
7208 pop(tmp2);
7209 pop(tmp1);
7210 pop(tmp0);
7211 }
7212
7213 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
7214 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
7215 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
7216 Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
7217 Label VECTOR8_TAIL, VECTOR4_TAIL;
7218 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
7219 Label SAME_TILL_END, DONE;
7220 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
7221
7222 //scale is in rcx in both Win64 and Unix
7223 ShortBranchVerifier sbv(this);
7224
7225 shlq(length);
7226 xorq(result, result);
7227
7228 if ((AVX3Threshold == 0) && (UseAVX > 2) &&
7229 VM_Version::supports_avx512vlbw()) {
7230 Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
7231
7232 cmpq(length, 64);
7233 jcc(Assembler::less, VECTOR32_TAIL);
7234
7235 movq(tmp1, length);
7236 andq(tmp1, 0x3F); // tail count
7237 andq(length, ~(0x3F)); //vector count
7238
7239 bind(VECTOR64_LOOP);
7240 // AVX512 code to compare 64 byte vectors.
7241 evmovdqub(rymm0, Address(obja, result), Assembler::AVX_512bit);
7242 evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
7243 kortestql(k7, k7);
7244 jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL); // mismatch
7245 addq(result, 64);
7246 subq(length, 64);
7247 jccb(Assembler::notZero, VECTOR64_LOOP);
7248
7249 //bind(VECTOR64_TAIL);
7250 testq(tmp1, tmp1);
7251 jcc(Assembler::zero, SAME_TILL_END);
7252
7253 //bind(VECTOR64_TAIL);
7254 // AVX512 code to compare up to 63 byte vectors.
7255 mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
7256 shlxq(tmp2, tmp2, tmp1);
7257 notq(tmp2);
7258 kmovql(k3, tmp2);
7259
7260 evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
7261 evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
7262
7263 ktestql(k7, k3);
7264 jcc(Assembler::below, SAME_TILL_END); // not mismatch
7265
7266 bind(VECTOR64_NOT_EQUAL);
7267 kmovql(tmp1, k7);
7268 notq(tmp1);
7269 tzcntq(tmp1, tmp1);
7270 addq(result, tmp1);
7271 shrq(result);
7272 jmp(DONE);
7273 bind(VECTOR32_TAIL);
7274 }
7275
7276 cmpq(length, 8);
7277 jcc(Assembler::equal, VECTOR8_LOOP);
7278 jcc(Assembler::less, VECTOR4_TAIL);
7279
7280 if (UseAVX >= 2) {
7281 Label VECTOR16_TAIL, VECTOR32_LOOP;
7282
7283 cmpq(length, 16);
7284 jcc(Assembler::equal, VECTOR16_LOOP);
7285 jcc(Assembler::less, VECTOR8_LOOP);
7286
7287 cmpq(length, 32);
7288 jccb(Assembler::less, VECTOR16_TAIL);
7289
7290 subq(length, 32);
7291 bind(VECTOR32_LOOP);
7292 vmovdqu(rymm0, Address(obja, result));
7293 vmovdqu(rymm1, Address(objb, result));
7294 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
7295 vptest(rymm2, rymm2);
7296 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
7297 addq(result, 32);
7298 subq(length, 32);
7299 jcc(Assembler::greaterEqual, VECTOR32_LOOP);
7300 addq(length, 32);
7301 jcc(Assembler::equal, SAME_TILL_END);
7302 //falling through if less than 32 bytes left //close the branch here.
7303
7304 bind(VECTOR16_TAIL);
7305 cmpq(length, 16);
7306 jccb(Assembler::less, VECTOR8_TAIL);
7307 bind(VECTOR16_LOOP);
7308 movdqu(rymm0, Address(obja, result));
7309 movdqu(rymm1, Address(objb, result));
7310 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
7311 ptest(rymm2, rymm2);
7312 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7313 addq(result, 16);
7314 subq(length, 16);
7315 jcc(Assembler::equal, SAME_TILL_END);
7316 //falling through if less than 16 bytes left
7317 } else {//regular intrinsics
7318
7319 cmpq(length, 16);
7320 jccb(Assembler::less, VECTOR8_TAIL);
7321
7322 subq(length, 16);
7323 bind(VECTOR16_LOOP);
7324 movdqu(rymm0, Address(obja, result));
7325 movdqu(rymm1, Address(objb, result));
7326 pxor(rymm0, rymm1);
7327 ptest(rymm0, rymm0);
7328 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
7329 addq(result, 16);
7330 subq(length, 16);
7331 jccb(Assembler::greaterEqual, VECTOR16_LOOP);
7332 addq(length, 16);
7333 jcc(Assembler::equal, SAME_TILL_END);
7334 //falling through if less than 16 bytes left
7335 }
7336
7337 bind(VECTOR8_TAIL);
7338 cmpq(length, 8);
7339 jccb(Assembler::less, VECTOR4_TAIL);
7340 bind(VECTOR8_LOOP);
7341 movq(tmp1, Address(obja, result));
7342 movq(tmp2, Address(objb, result));
7343 xorq(tmp1, tmp2);
7344 testq(tmp1, tmp1);
7345 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
7346 addq(result, 8);
7347 subq(length, 8);
7348 jcc(Assembler::equal, SAME_TILL_END);
7349 //falling through if less than 8 bytes left
7350
7351 bind(VECTOR4_TAIL);
7352 cmpq(length, 4);
7353 jccb(Assembler::less, BYTES_TAIL);
7354 bind(VECTOR4_LOOP);
7355 movl(tmp1, Address(obja, result));
7356 xorl(tmp1, Address(objb, result));
7357 testl(tmp1, tmp1);
7358 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
7359 addq(result, 4);
7360 subq(length, 4);
7361 jcc(Assembler::equal, SAME_TILL_END);
7362 //falling through if less than 4 bytes left
7363
7364 bind(BYTES_TAIL);
7365 bind(BYTES_LOOP);
7366 load_unsigned_byte(tmp1, Address(obja, result));
7367 load_unsigned_byte(tmp2, Address(objb, result));
7368 xorl(tmp1, tmp2);
7369 testl(tmp1, tmp1);
7370 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7371 decq(length);
7372 jcc(Assembler::zero, SAME_TILL_END);
7373 incq(result);
7374 load_unsigned_byte(tmp1, Address(obja, result));
7375 load_unsigned_byte(tmp2, Address(objb, result));
7376 xorl(tmp1, tmp2);
7377 testl(tmp1, tmp1);
7378 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7379 decq(length);
7380 jcc(Assembler::zero, SAME_TILL_END);
7381 incq(result);
7382 load_unsigned_byte(tmp1, Address(obja, result));
7383 load_unsigned_byte(tmp2, Address(objb, result));
7384 xorl(tmp1, tmp2);
7385 testl(tmp1, tmp1);
7386 jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
7387 jmp(SAME_TILL_END);
7388
7389 if (UseAVX >= 2) {
7390 bind(VECTOR32_NOT_EQUAL);
7391 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
7392 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
7393 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
7394 vpmovmskb(tmp1, rymm0);
7395 bsfq(tmp1, tmp1);
7396 addq(result, tmp1);
7397 shrq(result);
7398 jmp(DONE);
7399 }
7400
7401 bind(VECTOR16_NOT_EQUAL);
7402 if (UseAVX >= 2) {
7403 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
7404 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
7405 pxor(rymm0, rymm2);
7406 } else {
7407 pcmpeqb(rymm2, rymm2);
7408 pxor(rymm0, rymm1);
7409 pcmpeqb(rymm0, rymm1);
7410 pxor(rymm0, rymm2);
7411 }
7412 pmovmskb(tmp1, rymm0);
7413 bsfq(tmp1, tmp1);
7414 addq(result, tmp1);
7415 shrq(result);
7416 jmpb(DONE);
7417
7418 bind(VECTOR8_NOT_EQUAL);
7419 bind(VECTOR4_NOT_EQUAL);
7420 bsfq(tmp1, tmp1);
7421 shrq(tmp1, 3);
7422 addq(result, tmp1);
7423 bind(BYTES_NOT_EQUAL);
7424 shrq(result);
7425 jmpb(DONE);
7426
7427 bind(SAME_TILL_END);
7428 mov64(result, -1);
7429
7430 bind(DONE);
7431 }
7432
7433 //Helper functions for square_to_len()
7434
7435 /**
7436 * Store the squares of x[], right shifted one bit (divided by 2) into z[]
7437 * Preserves x and z and modifies rest of the registers.
7438 */
7439 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7440 // Perform square and right shift by 1
7441 // Handle odd xlen case first, then for even xlen do the following
7442 // jlong carry = 0;
7443 // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
7444 // huge_128 product = x[j:j+1] * x[j:j+1];
7445 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
7446 // z[i+2:i+3] = (jlong)(product >>> 1);
7447 // carry = (jlong)product;
7448 // }
7449
7450 xorq(tmp5, tmp5); // carry
7451 xorq(rdxReg, rdxReg);
7452 xorl(tmp1, tmp1); // index for x
7453 xorl(tmp4, tmp4); // index for z
7454
7455 Label L_first_loop, L_first_loop_exit;
7456
7457 testl(xlen, 1);
7458 jccb(Assembler::zero, L_first_loop); //jump if xlen is even
7459
7460 // Square and right shift by 1 the odd element using 32 bit multiply
7461 movl(raxReg, Address(x, tmp1, Address::times_4, 0));
7462 imulq(raxReg, raxReg);
7463 shrq(raxReg, 1);
7464 adcq(tmp5, 0);
7465 movq(Address(z, tmp4, Address::times_4, 0), raxReg);
7466 incrementl(tmp1);
7467 addl(tmp4, 2);
7468
7469 // Square and right shift by 1 the rest using 64 bit multiply
7470 bind(L_first_loop);
7471 cmpptr(tmp1, xlen);
7472 jccb(Assembler::equal, L_first_loop_exit);
7473
7474 // Square
7475 movq(raxReg, Address(x, tmp1, Address::times_4, 0));
7476 rorq(raxReg, 32); // convert big-endian to little-endian
7477 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax
7478
7479 // Right shift by 1 and save carry
7480 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
7481 rcrq(rdxReg, 1);
7482 rcrq(raxReg, 1);
7483 adcq(tmp5, 0);
7484
7485 // Store result in z
7486 movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
7487 movq(Address(z, tmp4, Address::times_4, 8), raxReg);
7488
7489 // Update indices for x and z
7490 addl(tmp1, 2);
7491 addl(tmp4, 4);
7492 jmp(L_first_loop);
7493
7494 bind(L_first_loop_exit);
7495 }
7496
7497
7498 /**
7499 * Perform the following multiply add operation using BMI2 instructions
7500 * carry:sum = sum + op1*op2 + carry
7501 * op2 should be in rdx
7502 * op2 is preserved, all other registers are modified
7503 */
7504 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
7505 // assert op2 is rdx
7506 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1
7507 addq(sum, carry);
7508 adcq(tmp2, 0);
7509 addq(sum, op1);
7510 adcq(tmp2, 0);
7511 movq(carry, tmp2);
7512 }
7513
7514 /**
7515 * Perform the following multiply add operation:
7516 * carry:sum = sum + op1*op2 + carry
7517 * Preserves op1, op2 and modifies rest of registers
7518 */
7519 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
7520 // rdx:rax = op1 * op2
7521 movq(raxReg, op2);
7522 mulq(op1);
7523
7524 // rdx:rax = sum + carry + rdx:rax
7525 addq(sum, carry);
7526 adcq(rdxReg, 0);
7527 addq(sum, raxReg);
7528 adcq(rdxReg, 0);
7529
7530 // carry:sum = rdx:sum
7531 movq(carry, rdxReg);
7532 }
7533
7534 /**
7535 * Add 64 bit long carry into z[] with carry propagation.
7536 * Preserves z and carry register values and modifies rest of registers.
7537 *
7538 */
7539 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
7540 Label L_fourth_loop, L_fourth_loop_exit;
7541
7542 movl(tmp1, 1);
7543 subl(zlen, 2);
7544 addq(Address(z, zlen, Address::times_4, 0), carry);
7545
7546 bind(L_fourth_loop);
7547 jccb(Assembler::carryClear, L_fourth_loop_exit);
7548 subl(zlen, 2);
7549 jccb(Assembler::negative, L_fourth_loop_exit);
7550 addq(Address(z, zlen, Address::times_4, 0), tmp1);
7551 jmp(L_fourth_loop);
7552 bind(L_fourth_loop_exit);
7553 }
7554
7555 /**
7556 * Shift z[] left by 1 bit.
7557 * Preserves x, len, z and zlen registers and modifies rest of the registers.
7558 *
7559 */
7560 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
7561
7562 Label L_fifth_loop, L_fifth_loop_exit;
7563
7564 // Fifth loop
7565 // Perform primitiveLeftShift(z, zlen, 1)
7566
7567 const Register prev_carry = tmp1;
7568 const Register new_carry = tmp4;
7569 const Register value = tmp2;
7570 const Register zidx = tmp3;
7571
7572 // int zidx, carry;
7573 // long value;
7574 // carry = 0;
7575 // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
7576 // (carry:value) = (z[i] << 1) | carry ;
7577 // z[i] = value;
7578 // }
7579
7580 movl(zidx, zlen);
7581 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
7582
7583 bind(L_fifth_loop);
7584 decl(zidx); // Use decl to preserve carry flag
7585 decl(zidx);
7586 jccb(Assembler::negative, L_fifth_loop_exit);
7587
7588 if (UseBMI2Instructions) {
7589 movq(value, Address(z, zidx, Address::times_4, 0));
7590 rclq(value, 1);
7591 rorxq(value, value, 32);
7592 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7593 }
7594 else {
7595 // clear new_carry
7596 xorl(new_carry, new_carry);
7597
7598 // Shift z[i] by 1, or in previous carry and save new carry
7599 movq(value, Address(z, zidx, Address::times_4, 0));
7600 shlq(value, 1);
7601 adcl(new_carry, 0);
7602
7603 orq(value, prev_carry);
7604 rorq(value, 0x20);
7605 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form
7606
7607 // Set previous carry = new carry
7608 movl(prev_carry, new_carry);
7609 }
7610 jmp(L_fifth_loop);
7611
7612 bind(L_fifth_loop_exit);
7613 }
7614
7615
7616 /**
7617 * Code for BigInteger::squareToLen() intrinsic
7618 *
7619 * rdi: x
7620 * rsi: len
7621 * r8: z
7622 * rcx: zlen
7623 * r12: tmp1
7624 * r13: tmp2
7625 * r14: tmp3
7626 * r15: tmp4
7627 * rbx: tmp5
7628 *
7629 */
7630 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7631
7632 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
7633 push(tmp1);
7634 push(tmp2);
7635 push(tmp3);
7636 push(tmp4);
7637 push(tmp5);
7638
7639 // First loop
7640 // Store the squares, right shifted one bit (i.e., divided by 2).
7641 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
7642
7643 // Add in off-diagonal sums.
7644 //
7645 // Second, third (nested) and fourth loops.
7646 // zlen +=2;
7647 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
7648 // carry = 0;
7649 // long op2 = x[xidx:xidx+1];
7650 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
7651 // k -= 2;
7652 // long op1 = x[j:j+1];
7653 // long sum = z[k:k+1];
7654 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
7655 // z[k:k+1] = sum;
7656 // }
7657 // add_one_64(z, k, carry, tmp_regs);
7658 // }
7659
7660 const Register carry = tmp5;
7661 const Register sum = tmp3;
7662 const Register op1 = tmp4;
7663 Register op2 = tmp2;
7664
7665 push(zlen);
7666 push(len);
7667 addl(zlen,2);
7668 bind(L_second_loop);
7669 xorq(carry, carry);
7670 subl(zlen, 4);
7671 subl(len, 2);
7672 push(zlen);
7673 push(len);
7674 cmpl(len, 0);
7675 jccb(Assembler::lessEqual, L_second_loop_exit);
7676
7677 // Multiply an array by one 64 bit long.
7678 if (UseBMI2Instructions) {
7679 op2 = rdxReg;
7680 movq(op2, Address(x, len, Address::times_4, 0));
7681 rorxq(op2, op2, 32);
7682 }
7683 else {
7684 movq(op2, Address(x, len, Address::times_4, 0));
7685 rorq(op2, 32);
7686 }
7687
7688 bind(L_third_loop);
7689 decrementl(len);
7690 jccb(Assembler::negative, L_third_loop_exit);
7691 decrementl(len);
7692 jccb(Assembler::negative, L_last_x);
7693
7694 movq(op1, Address(x, len, Address::times_4, 0));
7695 rorq(op1, 32);
7696
7697 bind(L_multiply);
7698 subl(zlen, 2);
7699 movq(sum, Address(z, zlen, Address::times_4, 0));
7700
7701 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
7702 if (UseBMI2Instructions) {
7703 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
7704 }
7705 else {
7706 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7707 }
7708
7709 movq(Address(z, zlen, Address::times_4, 0), sum);
7710
7711 jmp(L_third_loop);
7712 bind(L_third_loop_exit);
7713
7714 // Fourth loop
7715 // Add 64 bit long carry into z with carry propagation.
7716 // Uses offsetted zlen.
7717 add_one_64(z, zlen, carry, tmp1);
7718
7719 pop(len);
7720 pop(zlen);
7721 jmp(L_second_loop);
7722
7723 // Next infrequent code is moved outside loops.
7724 bind(L_last_x);
7725 movl(op1, Address(x, 0));
7726 jmp(L_multiply);
7727
7728 bind(L_second_loop_exit);
7729 pop(len);
7730 pop(zlen);
7731 pop(len);
7732 pop(zlen);
7733
7734 // Fifth loop
7735 // Shift z left 1 bit.
7736 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
7737
7738 // z[zlen-1] |= x[len-1] & 1;
7739 movl(tmp3, Address(x, len, Address::times_4, -4));
7740 andl(tmp3, 1);
7741 orl(Address(z, zlen, Address::times_4, -4), tmp3);
7742
7743 pop(tmp5);
7744 pop(tmp4);
7745 pop(tmp3);
7746 pop(tmp2);
7747 pop(tmp1);
7748 }
7749
7750 /**
7751 * Helper function for mul_add()
7752 * Multiply the in[] by int k and add to out[] starting at offset offs using
7753 * 128 bit by 32 bit multiply and return the carry in tmp5.
7754 * Only quad int aligned length of in[] is operated on in this function.
7755 * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
7756 * This function preserves out, in and k registers.
7757 * len and offset point to the appropriate index in "in" & "out" correspondingly
7758 * tmp5 has the carry.
7759 * other registers are temporary and are modified.
7760 *
7761 */
7762 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
7763 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
7764 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7765
7766 Label L_first_loop, L_first_loop_exit;
7767
7768 movl(tmp1, len);
7769 shrl(tmp1, 2);
7770
7771 bind(L_first_loop);
7772 subl(tmp1, 1);
7773 jccb(Assembler::negative, L_first_loop_exit);
7774
7775 subl(len, 4);
7776 subl(offset, 4);
7777
7778 Register op2 = tmp2;
7779 const Register sum = tmp3;
7780 const Register op1 = tmp4;
7781 const Register carry = tmp5;
7782
7783 if (UseBMI2Instructions) {
7784 op2 = rdxReg;
7785 }
7786
7787 movq(op1, Address(in, len, Address::times_4, 8));
7788 rorq(op1, 32);
7789 movq(sum, Address(out, offset, Address::times_4, 8));
7790 rorq(sum, 32);
7791 if (UseBMI2Instructions) {
7792 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7793 }
7794 else {
7795 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7796 }
7797 // Store back in big endian from little endian
7798 rorq(sum, 0x20);
7799 movq(Address(out, offset, Address::times_4, 8), sum);
7800
7801 movq(op1, Address(in, len, Address::times_4, 0));
7802 rorq(op1, 32);
7803 movq(sum, Address(out, offset, Address::times_4, 0));
7804 rorq(sum, 32);
7805 if (UseBMI2Instructions) {
7806 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7807 }
7808 else {
7809 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7810 }
7811 // Store back in big endian from little endian
7812 rorq(sum, 0x20);
7813 movq(Address(out, offset, Address::times_4, 0), sum);
7814
7815 jmp(L_first_loop);
7816 bind(L_first_loop_exit);
7817 }
7818
7819 /**
7820 * Code for BigInteger::mulAdd() intrinsic
7821 *
7822 * rdi: out
7823 * rsi: in
7824 * r11: offs (out.length - offset)
7825 * rcx: len
7826 * r8: k
7827 * r12: tmp1
7828 * r13: tmp2
7829 * r14: tmp3
7830 * r15: tmp4
7831 * rbx: tmp5
7832 * Multiply the in[] by word k and add to out[], return the carry in rax
7833 */
7834 void MacroAssembler::mul_add(Register out, Register in, Register offs,
7835 Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
7836 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
7837
7838 Label L_carry, L_last_in, L_done;
7839
7840 // carry = 0;
7841 // for (int j=len-1; j >= 0; j--) {
7842 // long product = (in[j] & LONG_MASK) * kLong +
7843 // (out[offs] & LONG_MASK) + carry;
7844 // out[offs--] = (int)product;
7845 // carry = product >>> 32;
7846 // }
7847 //
7848 push(tmp1);
7849 push(tmp2);
7850 push(tmp3);
7851 push(tmp4);
7852 push(tmp5);
7853
7854 Register op2 = tmp2;
7855 const Register sum = tmp3;
7856 const Register op1 = tmp4;
7857 const Register carry = tmp5;
7858
7859 if (UseBMI2Instructions) {
7860 op2 = rdxReg;
7861 movl(op2, k);
7862 }
7863 else {
7864 movl(op2, k);
7865 }
7866
7867 xorq(carry, carry);
7868
7869 //First loop
7870
7871 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
7872 //The carry is in tmp5
7873 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
7874
7875 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
7876 decrementl(len);
7877 jccb(Assembler::negative, L_carry);
7878 decrementl(len);
7879 jccb(Assembler::negative, L_last_in);
7880
7881 movq(op1, Address(in, len, Address::times_4, 0));
7882 rorq(op1, 32);
7883
7884 subl(offs, 2);
7885 movq(sum, Address(out, offs, Address::times_4, 0));
7886 rorq(sum, 32);
7887
7888 if (UseBMI2Instructions) {
7889 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
7890 }
7891 else {
7892 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
7893 }
7894
7895 // Store back in big endian from little endian
7896 rorq(sum, 0x20);
7897 movq(Address(out, offs, Address::times_4, 0), sum);
7898
7899 testl(len, len);
7900 jccb(Assembler::zero, L_carry);
7901
7902 //Multiply the last in[] entry, if any
7903 bind(L_last_in);
7904 movl(op1, Address(in, 0));
7905 movl(sum, Address(out, offs, Address::times_4, -4));
7906
7907 movl(raxReg, k);
7908 mull(op1); //tmp4 * eax -> edx:eax
7909 addl(sum, carry);
7910 adcl(rdxReg, 0);
7911 addl(sum, raxReg);
7912 adcl(rdxReg, 0);
7913 movl(carry, rdxReg);
7914
7915 movl(Address(out, offs, Address::times_4, -4), sum);
7916
7917 bind(L_carry);
7918 //return tmp5/carry as carry in rax
7919 movl(rax, carry);
7920
7921 bind(L_done);
7922 pop(tmp5);
7923 pop(tmp4);
7924 pop(tmp3);
7925 pop(tmp2);
7926 pop(tmp1);
7927 }
7928 #endif
7929
7930 /**
7931 * Emits code to update CRC-32 with a byte value according to constants in table
7932 *
7933 * @param [in,out]crc Register containing the crc.
7934 * @param [in]val Register containing the byte to fold into the CRC.
7935 * @param [in]table Register containing the table of crc constants.
7936 *
7937 * uint32_t crc;
7938 * val = crc_table[(val ^ crc) & 0xFF];
7939 * crc = val ^ (crc >> 8);
7940 *
7941 */
7942 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7943 xorl(val, crc);
7944 andl(val, 0xFF);
7945 shrl(crc, 8); // unsigned shift
7946 xorl(crc, Address(table, val, Address::times_4, 0));
7947 }
7948
7949 /**
7950 * Fold 128-bit data chunk
7951 */
7952 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7953 if (UseAVX > 0) {
7954 vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7955 vpclmulldq(xcrc, xK, xcrc); // [63:0]
7956 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7957 pxor(xcrc, xtmp);
7958 } else {
7959 movdqa(xtmp, xcrc);
7960 pclmulhdq(xtmp, xK); // [123:64]
7961 pclmulldq(xcrc, xK); // [63:0]
7962 pxor(xcrc, xtmp);
7963 movdqu(xtmp, Address(buf, offset));
7964 pxor(xcrc, xtmp);
7965 }
7966 }
7967
7968 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7969 if (UseAVX > 0) {
7970 vpclmulhdq(xtmp, xK, xcrc);
7971 vpclmulldq(xcrc, xK, xcrc);
7972 pxor(xcrc, xbuf);
7973 pxor(xcrc, xtmp);
7974 } else {
7975 movdqa(xtmp, xcrc);
7976 pclmulhdq(xtmp, xK);
7977 pclmulldq(xcrc, xK);
7978 pxor(xcrc, xbuf);
7979 pxor(xcrc, xtmp);
7980 }
7981 }
7982
7983 /**
7984 * 8-bit folds to compute 32-bit CRC
7985 *
7986 * uint64_t xcrc;
7987 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7988 */
7989 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7990 movdl(tmp, xcrc);
7991 andl(tmp, 0xFF);
7992 movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7993 psrldq(xcrc, 1); // unsigned shift one byte
7994 pxor(xcrc, xtmp);
7995 }
7996
7997 /**
7998 * uint32_t crc;
7999 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
8000 */
8001 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
8002 movl(tmp, crc);
8003 andl(tmp, 0xFF);
8004 shrl(crc, 8);
8005 xorl(crc, Address(table, tmp, Address::times_4, 0));
8006 }
8007
8008 /**
8009 * @param crc register containing existing CRC (32-bit)
8010 * @param buf register pointing to input byte buffer (byte*)
8011 * @param len register containing number of bytes
8012 * @param table register that will contain address of CRC table
8013 * @param tmp scratch register
8014 */
8015 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
8016 assert_different_registers(crc, buf, len, table, tmp, rax);
8017
8018 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8019 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8020
8021 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8022 // context for the registers used, where all instructions below are using 128-bit mode
8023 // On EVEX without VL and BW, these instructions will all be AVX.
8024 lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
8025 notl(crc); // ~crc
8026 cmpl(len, 16);
8027 jcc(Assembler::less, L_tail);
8028
8029 // Align buffer to 16 bytes
8030 movl(tmp, buf);
8031 andl(tmp, 0xF);
8032 jccb(Assembler::zero, L_aligned);
8033 subl(tmp, 16);
8034 addl(len, tmp);
8035
8036 align(4);
8037 BIND(L_align_loop);
8038 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8039 update_byte_crc32(crc, rax, table);
8040 increment(buf);
8041 incrementl(tmp);
8042 jccb(Assembler::less, L_align_loop);
8043
8044 BIND(L_aligned);
8045 movl(tmp, len); // save
8046 shrl(len, 4);
8047 jcc(Assembler::zero, L_tail_restore);
8048
8049 // Fold crc into first bytes of vector
8050 movdqa(xmm1, Address(buf, 0));
8051 movdl(rax, xmm1);
8052 xorl(crc, rax);
8053 if (VM_Version::supports_sse4_1()) {
8054 pinsrd(xmm1, crc, 0);
8055 } else {
8056 pinsrw(xmm1, crc, 0);
8057 shrl(crc, 16);
8058 pinsrw(xmm1, crc, 1);
8059 }
8060 addptr(buf, 16);
8061 subl(len, 4); // len > 0
8062 jcc(Assembler::less, L_fold_tail);
8063
8064 movdqa(xmm2, Address(buf, 0));
8065 movdqa(xmm3, Address(buf, 16));
8066 movdqa(xmm4, Address(buf, 32));
8067 addptr(buf, 48);
8068 subl(len, 3);
8069 jcc(Assembler::lessEqual, L_fold_512b);
8070
8071 // Fold total 512 bits of polynomial on each iteration,
8072 // 128 bits per each of 4 parallel streams.
8073 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32), rscratch1);
8074
8075 align32();
8076 BIND(L_fold_512b_loop);
8077 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8078 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
8079 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
8080 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
8081 addptr(buf, 64);
8082 subl(len, 4);
8083 jcc(Assembler::greater, L_fold_512b_loop);
8084
8085 // Fold 512 bits to 128 bits.
8086 BIND(L_fold_512b);
8087 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8088 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
8089 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
8090 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
8091
8092 // Fold the rest of 128 bits data chunks
8093 BIND(L_fold_tail);
8094 addl(len, 3);
8095 jccb(Assembler::lessEqual, L_fold_128b);
8096 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16), rscratch1);
8097
8098 BIND(L_fold_tail_loop);
8099 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0);
8100 addptr(buf, 16);
8101 decrementl(len);
8102 jccb(Assembler::greater, L_fold_tail_loop);
8103
8104 // Fold 128 bits in xmm1 down into 32 bits in crc register.
8105 BIND(L_fold_128b);
8106 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()), rscratch1);
8107 if (UseAVX > 0) {
8108 vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
8109 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
8110 vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
8111 } else {
8112 movdqa(xmm2, xmm0);
8113 pclmulqdq(xmm2, xmm1, 0x1);
8114 movdqa(xmm3, xmm0);
8115 pand(xmm3, xmm2);
8116 pclmulqdq(xmm0, xmm3, 0x1);
8117 }
8118 psrldq(xmm1, 8);
8119 psrldq(xmm2, 4);
8120 pxor(xmm0, xmm1);
8121 pxor(xmm0, xmm2);
8122
8123 // 8 8-bit folds to compute 32-bit CRC.
8124 for (int j = 0; j < 4; j++) {
8125 fold_8bit_crc32(xmm0, table, xmm1, rax);
8126 }
8127 movdl(crc, xmm0); // mov 32 bits to general register
8128 for (int j = 0; j < 4; j++) {
8129 fold_8bit_crc32(crc, table, rax);
8130 }
8131
8132 BIND(L_tail_restore);
8133 movl(len, tmp); // restore
8134 BIND(L_tail);
8135 andl(len, 0xf);
8136 jccb(Assembler::zero, L_exit);
8137
8138 // Fold the rest of bytes
8139 align(4);
8140 BIND(L_tail_loop);
8141 movsbl(rax, Address(buf, 0)); // load byte with sign extension
8142 update_byte_crc32(crc, rax, table);
8143 increment(buf);
8144 decrementl(len);
8145 jccb(Assembler::greater, L_tail_loop);
8146
8147 BIND(L_exit);
8148 notl(crc); // ~c
8149 }
8150
8151 #ifdef _LP64
8152 // Helper function for AVX 512 CRC32
8153 // Fold 512-bit data chunks
8154 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
8155 Register pos, int offset) {
8156 evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
8157 evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
8158 evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
8159 evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
8160 evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
8161 }
8162
8163 // Helper function for AVX 512 CRC32
8164 // Compute CRC32 for < 256B buffers
8165 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
8166 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
8167 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
8168
8169 Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
8170 Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
8171 Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
8172
8173 // check if there is enough buffer to be able to fold 16B at a time
8174 cmpl(len, 32);
8175 jcc(Assembler::less, L_less_than_32);
8176
8177 // if there is, load the constants
8178 movdqu(xmm10, Address(table, 1 * 16)); //rk1 and rk2 in xmm10
8179 movdl(xmm0, crc); // get the initial crc value
8180 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8181 pxor(xmm7, xmm0);
8182
8183 // update the buffer pointer
8184 addl(pos, 16);
8185 //update the counter.subtract 32 instead of 16 to save one instruction from the loop
8186 subl(len, 32);
8187 jmp(L_16B_reduction_loop);
8188
8189 bind(L_less_than_32);
8190 //mov initial crc to the return value. this is necessary for zero - length buffers.
8191 movl(rax, crc);
8192 testl(len, len);
8193 jcc(Assembler::equal, L_cleanup);
8194
8195 movdl(xmm0, crc); //get the initial crc value
8196
8197 cmpl(len, 16);
8198 jcc(Assembler::equal, L_exact_16_left);
8199 jcc(Assembler::less, L_less_than_16_left);
8200
8201 movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
8202 pxor(xmm7, xmm0); //xor the initial crc value
8203 addl(pos, 16);
8204 subl(len, 16);
8205 movdqu(xmm10, Address(table, 1 * 16)); // rk1 and rk2 in xmm10
8206 jmp(L_get_last_two_xmms);
8207
8208 bind(L_less_than_16_left);
8209 //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
8210 pxor(xmm1, xmm1);
8211 movptr(tmp1, rsp);
8212 movdqu(Address(tmp1, 0 * 16), xmm1);
8213
8214 cmpl(len, 4);
8215 jcc(Assembler::less, L_only_less_than_4);
8216
8217 //backup the counter value
8218 movl(tmp2, len);
8219 cmpl(len, 8);
8220 jcc(Assembler::less, L_less_than_8_left);
8221
8222 //load 8 Bytes
8223 movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
8224 movq(Address(tmp1, 0 * 16), rax);
8225 addptr(tmp1, 8);
8226 subl(len, 8);
8227 addl(pos, 8);
8228
8229 bind(L_less_than_8_left);
8230 cmpl(len, 4);
8231 jcc(Assembler::less, L_less_than_4_left);
8232
8233 //load 4 Bytes
8234 movl(rax, Address(buf, pos, Address::times_1, 0));
8235 movl(Address(tmp1, 0 * 16), rax);
8236 addptr(tmp1, 4);
8237 subl(len, 4);
8238 addl(pos, 4);
8239
8240 bind(L_less_than_4_left);
8241 cmpl(len, 2);
8242 jcc(Assembler::less, L_less_than_2_left);
8243
8244 // load 2 Bytes
8245 movw(rax, Address(buf, pos, Address::times_1, 0));
8246 movl(Address(tmp1, 0 * 16), rax);
8247 addptr(tmp1, 2);
8248 subl(len, 2);
8249 addl(pos, 2);
8250
8251 bind(L_less_than_2_left);
8252 cmpl(len, 1);
8253 jcc(Assembler::less, L_zero_left);
8254
8255 // load 1 Byte
8256 movb(rax, Address(buf, pos, Address::times_1, 0));
8257 movb(Address(tmp1, 0 * 16), rax);
8258
8259 bind(L_zero_left);
8260 movdqu(xmm7, Address(rsp, 0));
8261 pxor(xmm7, xmm0); //xor the initial crc value
8262
8263 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8264 movdqu(xmm0, Address(rax, tmp2));
8265 pshufb(xmm7, xmm0);
8266 jmp(L_128_done);
8267
8268 bind(L_exact_16_left);
8269 movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
8270 pxor(xmm7, xmm0); //xor the initial crc value
8271 jmp(L_128_done);
8272
8273 bind(L_only_less_than_4);
8274 cmpl(len, 3);
8275 jcc(Assembler::less, L_only_less_than_3);
8276
8277 // load 3 Bytes
8278 movb(rax, Address(buf, pos, Address::times_1, 0));
8279 movb(Address(tmp1, 0), rax);
8280
8281 movb(rax, Address(buf, pos, Address::times_1, 1));
8282 movb(Address(tmp1, 1), rax);
8283
8284 movb(rax, Address(buf, pos, Address::times_1, 2));
8285 movb(Address(tmp1, 2), rax);
8286
8287 movdqu(xmm7, Address(rsp, 0));
8288 pxor(xmm7, xmm0); //xor the initial crc value
8289
8290 pslldq(xmm7, 0x5);
8291 jmp(L_barrett);
8292 bind(L_only_less_than_3);
8293 cmpl(len, 2);
8294 jcc(Assembler::less, L_only_less_than_2);
8295
8296 // load 2 Bytes
8297 movb(rax, Address(buf, pos, Address::times_1, 0));
8298 movb(Address(tmp1, 0), rax);
8299
8300 movb(rax, Address(buf, pos, Address::times_1, 1));
8301 movb(Address(tmp1, 1), rax);
8302
8303 movdqu(xmm7, Address(rsp, 0));
8304 pxor(xmm7, xmm0); //xor the initial crc value
8305
8306 pslldq(xmm7, 0x6);
8307 jmp(L_barrett);
8308
8309 bind(L_only_less_than_2);
8310 //load 1 Byte
8311 movb(rax, Address(buf, pos, Address::times_1, 0));
8312 movb(Address(tmp1, 0), rax);
8313
8314 movdqu(xmm7, Address(rsp, 0));
8315 pxor(xmm7, xmm0); //xor the initial crc value
8316
8317 pslldq(xmm7, 0x7);
8318 }
8319
8320 /**
8321 * Compute CRC32 using AVX512 instructions
8322 * param crc register containing existing CRC (32-bit)
8323 * param buf register pointing to input byte buffer (byte*)
8324 * param len register containing number of bytes
8325 * param table address of crc or crc32c table
8326 * param tmp1 scratch register
8327 * param tmp2 scratch register
8328 * return rax result register
8329 *
8330 * This routine is identical for crc32c with the exception of the precomputed constant
8331 * table which will be passed as the table argument. The calculation steps are
8332 * the same for both variants.
8333 */
8334 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
8335 assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
8336
8337 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
8338 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
8339 Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
8340 Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
8341 Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
8342
8343 const Register pos = r12;
8344 push(r12);
8345 subptr(rsp, 16 * 2 + 8);
8346
8347 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
8348 // context for the registers used, where all instructions below are using 128-bit mode
8349 // On EVEX without VL and BW, these instructions will all be AVX.
8350 movl(pos, 0);
8351
8352 // check if smaller than 256B
8353 cmpl(len, 256);
8354 jcc(Assembler::less, L_less_than_256);
8355
8356 // load the initial crc value
8357 movdl(xmm10, crc);
8358
8359 // receive the initial 64B data, xor the initial crc value
8360 evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
8361 evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
8362 evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
8363 evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
8364
8365 subl(len, 256);
8366 cmpl(len, 256);
8367 jcc(Assembler::less, L_fold_128_B_loop);
8368
8369 evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
8370 evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
8371 evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
8372 subl(len, 256);
8373
8374 bind(L_fold_256_B_loop);
8375 addl(pos, 256);
8376 fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
8377 fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
8378 fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
8379 fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
8380
8381 subl(len, 256);
8382 jcc(Assembler::greaterEqual, L_fold_256_B_loop);
8383
8384 // Fold 256 into 128
8385 addl(pos, 256);
8386 evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
8387 evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
8388 vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
8389
8390 evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
8391 evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
8392 vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
8393
8394 evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
8395 evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
8396
8397 addl(len, 128);
8398 jmp(L_fold_128_B_register);
8399
8400 // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
8401 // loop will fold 128B at a time until we have 128 + y Bytes of buffer
8402
8403 // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
8404 bind(L_fold_128_B_loop);
8405 addl(pos, 128);
8406 fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
8407 fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
8408
8409 subl(len, 128);
8410 jcc(Assembler::greaterEqual, L_fold_128_B_loop);
8411
8412 addl(pos, 128);
8413
8414 // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
8415 // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
8416 bind(L_fold_128_B_register);
8417 evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
8418 evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
8419 evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
8420 evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
8421 // save last that has no multiplicand
8422 vextracti64x2(xmm7, xmm4, 3);
8423
8424 evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
8425 evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
8426 // Needed later in reduction loop
8427 movdqu(xmm10, Address(table, 1 * 16));
8428 vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
8429 vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
8430
8431 // Swap 1,0,3,2 - 01 00 11 10
8432 evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
8433 evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
8434 vextracti128(xmm5, xmm8, 1);
8435 evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
8436
8437 // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
8438 // instead of a cmp instruction, we use the negative flag with the jl instruction
8439 addl(len, 128 - 16);
8440 jcc(Assembler::less, L_final_reduction_for_128);
8441
8442 bind(L_16B_reduction_loop);
8443 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8444 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8445 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8446 movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
8447 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8448 addl(pos, 16);
8449 subl(len, 16);
8450 jcc(Assembler::greaterEqual, L_16B_reduction_loop);
8451
8452 bind(L_final_reduction_for_128);
8453 addl(len, 16);
8454 jcc(Assembler::equal, L_128_done);
8455
8456 bind(L_get_last_two_xmms);
8457 movdqu(xmm2, xmm7);
8458 addl(pos, len);
8459 movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
8460 subl(pos, len);
8461
8462 // get rid of the extra data that was loaded before
8463 // load the shift constant
8464 lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
8465 movdqu(xmm0, Address(rax, len));
8466 addl(rax, len);
8467
8468 vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8469 //Change mask to 512
8470 vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
8471 vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
8472
8473 blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
8474 vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
8475 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8476 vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
8477 vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
8478
8479 bind(L_128_done);
8480 // compute crc of a 128-bit value
8481 movdqu(xmm10, Address(table, 3 * 16));
8482 movdqu(xmm0, xmm7);
8483
8484 // 64b fold
8485 vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
8486 vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
8487 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8488
8489 // 32b fold
8490 movdqu(xmm0, xmm7);
8491 vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
8492 vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
8493 vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
8494 jmp(L_barrett);
8495
8496 bind(L_less_than_256);
8497 kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
8498
8499 //barrett reduction
8500 bind(L_barrett);
8501 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
8502 movdqu(xmm1, xmm7);
8503 movdqu(xmm2, xmm7);
8504 movdqu(xmm10, Address(table, 4 * 16));
8505
8506 pclmulqdq(xmm7, xmm10, 0x0);
8507 pxor(xmm7, xmm2);
8508 vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
8509 movdqu(xmm2, xmm7);
8510 pclmulqdq(xmm7, xmm10, 0x10);
8511 pxor(xmm7, xmm2);
8512 pxor(xmm7, xmm1);
8513 pextrd(crc, xmm7, 2);
8514
8515 bind(L_cleanup);
8516 addptr(rsp, 16 * 2 + 8);
8517 pop(r12);
8518 }
8519
8520 // S. Gueron / Information Processing Letters 112 (2012) 184
8521 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
8522 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
8523 // Output: the 64-bit carry-less product of B * CONST
8524 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
8525 Register tmp1, Register tmp2, Register tmp3) {
8526 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8527 if (n > 0) {
8528 addq(tmp3, n * 256 * 8);
8529 }
8530 // Q1 = TABLEExt[n][B & 0xFF];
8531 movl(tmp1, in);
8532 andl(tmp1, 0x000000FF);
8533 shll(tmp1, 3);
8534 addq(tmp1, tmp3);
8535 movq(tmp1, Address(tmp1, 0));
8536
8537 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8538 movl(tmp2, in);
8539 shrl(tmp2, 8);
8540 andl(tmp2, 0x000000FF);
8541 shll(tmp2, 3);
8542 addq(tmp2, tmp3);
8543 movq(tmp2, Address(tmp2, 0));
8544
8545 shlq(tmp2, 8);
8546 xorq(tmp1, tmp2);
8547
8548 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8549 movl(tmp2, in);
8550 shrl(tmp2, 16);
8551 andl(tmp2, 0x000000FF);
8552 shll(tmp2, 3);
8553 addq(tmp2, tmp3);
8554 movq(tmp2, Address(tmp2, 0));
8555
8556 shlq(tmp2, 16);
8557 xorq(tmp1, tmp2);
8558
8559 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8560 shrl(in, 24);
8561 andl(in, 0x000000FF);
8562 shll(in, 3);
8563 addq(in, tmp3);
8564 movq(in, Address(in, 0));
8565
8566 shlq(in, 24);
8567 xorq(in, tmp1);
8568 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8569 }
8570
8571 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8572 Register in_out,
8573 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8574 XMMRegister w_xtmp2,
8575 Register tmp1,
8576 Register n_tmp2, Register n_tmp3) {
8577 if (is_pclmulqdq_supported) {
8578 movdl(w_xtmp1, in_out); // modified blindly
8579
8580 movl(tmp1, const_or_pre_comp_const_index);
8581 movdl(w_xtmp2, tmp1);
8582 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8583
8584 movdq(in_out, w_xtmp1);
8585 } else {
8586 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
8587 }
8588 }
8589
8590 // Recombination Alternative 2: No bit-reflections
8591 // T1 = (CRC_A * U1) << 1
8592 // T2 = (CRC_B * U2) << 1
8593 // C1 = T1 >> 32
8594 // C2 = T2 >> 32
8595 // T1 = T1 & 0xFFFFFFFF
8596 // T2 = T2 & 0xFFFFFFFF
8597 // T1 = CRC32(0, T1)
8598 // T2 = CRC32(0, T2)
8599 // C1 = C1 ^ T1
8600 // C2 = C2 ^ T2
8601 // CRC = C1 ^ C2 ^ CRC_C
8602 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8603 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8604 Register tmp1, Register tmp2,
8605 Register n_tmp3) {
8606 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8607 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8608 shlq(in_out, 1);
8609 movl(tmp1, in_out);
8610 shrq(in_out, 32);
8611 xorl(tmp2, tmp2);
8612 crc32(tmp2, tmp1, 4);
8613 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
8614 shlq(in1, 1);
8615 movl(tmp1, in1);
8616 shrq(in1, 32);
8617 xorl(tmp2, tmp2);
8618 crc32(tmp2, tmp1, 4);
8619 xorl(in1, tmp2);
8620 xorl(in_out, in1);
8621 xorl(in_out, in2);
8622 }
8623
8624 // Set N to predefined value
8625 // Subtract from a length of a buffer
8626 // execute in a loop:
8627 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
8628 // for i = 1 to N do
8629 // CRC_A = CRC32(CRC_A, A[i])
8630 // CRC_B = CRC32(CRC_B, B[i])
8631 // CRC_C = CRC32(CRC_C, C[i])
8632 // end for
8633 // Recombine
8634 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8635 Register in_out1, Register in_out2, Register in_out3,
8636 Register tmp1, Register tmp2, Register tmp3,
8637 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8638 Register tmp4, Register tmp5,
8639 Register n_tmp6) {
8640 Label L_processPartitions;
8641 Label L_processPartition;
8642 Label L_exit;
8643
8644 bind(L_processPartitions);
8645 cmpl(in_out1, 3 * size);
8646 jcc(Assembler::less, L_exit);
8647 xorl(tmp1, tmp1);
8648 xorl(tmp2, tmp2);
8649 movq(tmp3, in_out2);
8650 addq(tmp3, size);
8651
8652 bind(L_processPartition);
8653 crc32(in_out3, Address(in_out2, 0), 8);
8654 crc32(tmp1, Address(in_out2, size), 8);
8655 crc32(tmp2, Address(in_out2, size * 2), 8);
8656 addq(in_out2, 8);
8657 cmpq(in_out2, tmp3);
8658 jcc(Assembler::less, L_processPartition);
8659 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8660 w_xtmp1, w_xtmp2, w_xtmp3,
8661 tmp4, tmp5,
8662 n_tmp6);
8663 addq(in_out2, 2 * size);
8664 subl(in_out1, 3 * size);
8665 jmp(L_processPartitions);
8666
8667 bind(L_exit);
8668 }
8669 #else
8670 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
8671 Register tmp1, Register tmp2, Register tmp3,
8672 XMMRegister xtmp1, XMMRegister xtmp2) {
8673 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
8674 if (n > 0) {
8675 addl(tmp3, n * 256 * 8);
8676 }
8677 // Q1 = TABLEExt[n][B & 0xFF];
8678 movl(tmp1, in_out);
8679 andl(tmp1, 0x000000FF);
8680 shll(tmp1, 3);
8681 addl(tmp1, tmp3);
8682 movq(xtmp1, Address(tmp1, 0));
8683
8684 // Q2 = TABLEExt[n][B >> 8 & 0xFF];
8685 movl(tmp2, in_out);
8686 shrl(tmp2, 8);
8687 andl(tmp2, 0x000000FF);
8688 shll(tmp2, 3);
8689 addl(tmp2, tmp3);
8690 movq(xtmp2, Address(tmp2, 0));
8691
8692 psllq(xtmp2, 8);
8693 pxor(xtmp1, xtmp2);
8694
8695 // Q3 = TABLEExt[n][B >> 16 & 0xFF];
8696 movl(tmp2, in_out);
8697 shrl(tmp2, 16);
8698 andl(tmp2, 0x000000FF);
8699 shll(tmp2, 3);
8700 addl(tmp2, tmp3);
8701 movq(xtmp2, Address(tmp2, 0));
8702
8703 psllq(xtmp2, 16);
8704 pxor(xtmp1, xtmp2);
8705
8706 // Q4 = TABLEExt[n][B >> 24 & 0xFF];
8707 shrl(in_out, 24);
8708 andl(in_out, 0x000000FF);
8709 shll(in_out, 3);
8710 addl(in_out, tmp3);
8711 movq(xtmp2, Address(in_out, 0));
8712
8713 psllq(xtmp2, 24);
8714 pxor(xtmp1, xtmp2); // Result in CXMM
8715 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
8716 }
8717
8718 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
8719 Register in_out,
8720 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
8721 XMMRegister w_xtmp2,
8722 Register tmp1,
8723 Register n_tmp2, Register n_tmp3) {
8724 if (is_pclmulqdq_supported) {
8725 movdl(w_xtmp1, in_out);
8726
8727 movl(tmp1, const_or_pre_comp_const_index);
8728 movdl(w_xtmp2, tmp1);
8729 pclmulqdq(w_xtmp1, w_xtmp2, 0);
8730 // Keep result in XMM since GPR is 32 bit in length
8731 } else {
8732 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
8733 }
8734 }
8735
8736 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
8737 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8738 Register tmp1, Register tmp2,
8739 Register n_tmp3) {
8740 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8741 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
8742
8743 psllq(w_xtmp1, 1);
8744 movdl(tmp1, w_xtmp1);
8745 psrlq(w_xtmp1, 32);
8746 movdl(in_out, w_xtmp1);
8747
8748 xorl(tmp2, tmp2);
8749 crc32(tmp2, tmp1, 4);
8750 xorl(in_out, tmp2);
8751
8752 psllq(w_xtmp2, 1);
8753 movdl(tmp1, w_xtmp2);
8754 psrlq(w_xtmp2, 32);
8755 movdl(in1, w_xtmp2);
8756
8757 xorl(tmp2, tmp2);
8758 crc32(tmp2, tmp1, 4);
8759 xorl(in1, tmp2);
8760 xorl(in_out, in1);
8761 xorl(in_out, in2);
8762 }
8763
8764 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
8765 Register in_out1, Register in_out2, Register in_out3,
8766 Register tmp1, Register tmp2, Register tmp3,
8767 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8768 Register tmp4, Register tmp5,
8769 Register n_tmp6) {
8770 Label L_processPartitions;
8771 Label L_processPartition;
8772 Label L_exit;
8773
8774 bind(L_processPartitions);
8775 cmpl(in_out1, 3 * size);
8776 jcc(Assembler::less, L_exit);
8777 xorl(tmp1, tmp1);
8778 xorl(tmp2, tmp2);
8779 movl(tmp3, in_out2);
8780 addl(tmp3, size);
8781
8782 bind(L_processPartition);
8783 crc32(in_out3, Address(in_out2, 0), 4);
8784 crc32(tmp1, Address(in_out2, size), 4);
8785 crc32(tmp2, Address(in_out2, size*2), 4);
8786 crc32(in_out3, Address(in_out2, 0+4), 4);
8787 crc32(tmp1, Address(in_out2, size+4), 4);
8788 crc32(tmp2, Address(in_out2, size*2+4), 4);
8789 addl(in_out2, 8);
8790 cmpl(in_out2, tmp3);
8791 jcc(Assembler::less, L_processPartition);
8792
8793 push(tmp3);
8794 push(in_out1);
8795 push(in_out2);
8796 tmp4 = tmp3;
8797 tmp5 = in_out1;
8798 n_tmp6 = in_out2;
8799
8800 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
8801 w_xtmp1, w_xtmp2, w_xtmp3,
8802 tmp4, tmp5,
8803 n_tmp6);
8804
8805 pop(in_out2);
8806 pop(in_out1);
8807 pop(tmp3);
8808
8809 addl(in_out2, 2 * size);
8810 subl(in_out1, 3 * size);
8811 jmp(L_processPartitions);
8812
8813 bind(L_exit);
8814 }
8815 #endif //LP64
8816
8817 #ifdef _LP64
8818 // Algorithm 2: Pipelined usage of the CRC32 instruction.
8819 // Input: A buffer I of L bytes.
8820 // Output: the CRC32C value of the buffer.
8821 // Notations:
8822 // Write L = 24N + r, with N = floor (L/24).
8823 // r = L mod 24 (0 <= r < 24).
8824 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
8825 // N quadwords, and R consists of r bytes.
8826 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
8827 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
8828 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
8829 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
8830 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8831 Register tmp1, Register tmp2, Register tmp3,
8832 Register tmp4, Register tmp5, Register tmp6,
8833 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8834 bool is_pclmulqdq_supported) {
8835 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8836 Label L_wordByWord;
8837 Label L_byteByByteProlog;
8838 Label L_byteByByte;
8839 Label L_exit;
8840
8841 if (is_pclmulqdq_supported ) {
8842 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8843 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
8844
8845 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8846 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8847
8848 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8849 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8850 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
8851 } else {
8852 const_or_pre_comp_const_index[0] = 1;
8853 const_or_pre_comp_const_index[1] = 0;
8854
8855 const_or_pre_comp_const_index[2] = 3;
8856 const_or_pre_comp_const_index[3] = 2;
8857
8858 const_or_pre_comp_const_index[4] = 5;
8859 const_or_pre_comp_const_index[5] = 4;
8860 }
8861 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8862 in2, in1, in_out,
8863 tmp1, tmp2, tmp3,
8864 w_xtmp1, w_xtmp2, w_xtmp3,
8865 tmp4, tmp5,
8866 tmp6);
8867 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8868 in2, in1, in_out,
8869 tmp1, tmp2, tmp3,
8870 w_xtmp1, w_xtmp2, w_xtmp3,
8871 tmp4, tmp5,
8872 tmp6);
8873 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8874 in2, in1, in_out,
8875 tmp1, tmp2, tmp3,
8876 w_xtmp1, w_xtmp2, w_xtmp3,
8877 tmp4, tmp5,
8878 tmp6);
8879 movl(tmp1, in2);
8880 andl(tmp1, 0x00000007);
8881 negl(tmp1);
8882 addl(tmp1, in2);
8883 addq(tmp1, in1);
8884
8885 cmpq(in1, tmp1);
8886 jccb(Assembler::greaterEqual, L_byteByByteProlog);
8887 align(16);
8888 BIND(L_wordByWord);
8889 crc32(in_out, Address(in1, 0), 8);
8890 addq(in1, 8);
8891 cmpq(in1, tmp1);
8892 jcc(Assembler::less, L_wordByWord);
8893
8894 BIND(L_byteByByteProlog);
8895 andl(in2, 0x00000007);
8896 movl(tmp2, 1);
8897
8898 cmpl(tmp2, in2);
8899 jccb(Assembler::greater, L_exit);
8900 BIND(L_byteByByte);
8901 crc32(in_out, Address(in1, 0), 1);
8902 incq(in1);
8903 incl(tmp2);
8904 cmpl(tmp2, in2);
8905 jcc(Assembler::lessEqual, L_byteByByte);
8906
8907 BIND(L_exit);
8908 }
8909 #else
8910 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
8911 Register tmp1, Register tmp2, Register tmp3,
8912 Register tmp4, Register tmp5, Register tmp6,
8913 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
8914 bool is_pclmulqdq_supported) {
8915 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
8916 Label L_wordByWord;
8917 Label L_byteByByteProlog;
8918 Label L_byteByByte;
8919 Label L_exit;
8920
8921 if (is_pclmulqdq_supported) {
8922 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
8923 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
8924
8925 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
8926 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
8927
8928 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
8929 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
8930 } else {
8931 const_or_pre_comp_const_index[0] = 1;
8932 const_or_pre_comp_const_index[1] = 0;
8933
8934 const_or_pre_comp_const_index[2] = 3;
8935 const_or_pre_comp_const_index[3] = 2;
8936
8937 const_or_pre_comp_const_index[4] = 5;
8938 const_or_pre_comp_const_index[5] = 4;
8939 }
8940 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8941 in2, in1, in_out,
8942 tmp1, tmp2, tmp3,
8943 w_xtmp1, w_xtmp2, w_xtmp3,
8944 tmp4, tmp5,
8945 tmp6);
8946 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8947 in2, in1, in_out,
8948 tmp1, tmp2, tmp3,
8949 w_xtmp1, w_xtmp2, w_xtmp3,
8950 tmp4, tmp5,
8951 tmp6);
8952 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8953 in2, in1, in_out,
8954 tmp1, tmp2, tmp3,
8955 w_xtmp1, w_xtmp2, w_xtmp3,
8956 tmp4, tmp5,
8957 tmp6);
8958 movl(tmp1, in2);
8959 andl(tmp1, 0x00000007);
8960 negl(tmp1);
8961 addl(tmp1, in2);
8962 addl(tmp1, in1);
8963
8964 BIND(L_wordByWord);
8965 cmpl(in1, tmp1);
8966 jcc(Assembler::greaterEqual, L_byteByByteProlog);
8967 crc32(in_out, Address(in1,0), 4);
8968 addl(in1, 4);
8969 jmp(L_wordByWord);
8970
8971 BIND(L_byteByByteProlog);
8972 andl(in2, 0x00000007);
8973 movl(tmp2, 1);
8974
8975 BIND(L_byteByByte);
8976 cmpl(tmp2, in2);
8977 jccb(Assembler::greater, L_exit);
8978 movb(tmp1, Address(in1, 0));
8979 crc32(in_out, tmp1, 1);
8980 incl(in1);
8981 incl(tmp2);
8982 jmp(L_byteByByte);
8983
8984 BIND(L_exit);
8985 }
8986 #endif // LP64
8987 #undef BIND
8988 #undef BLOCK_COMMENT
8989
8990 // Compress char[] array to byte[].
8991 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
8992 // Return the array length if every element in array can be encoded,
8993 // otherwise, the index of first non-latin1 (> 0xff) character.
8994 // @IntrinsicCandidate
8995 // public static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8996 // for (int i = 0; i < len; i++) {
8997 // char c = src[srcOff];
8998 // if (c > 0xff) {
8999 // return i; // return index of non-latin1 char
9000 // }
9001 // dst[dstOff] = (byte)c;
9002 // srcOff++;
9003 // dstOff++;
9004 // }
9005 // return len;
9006 // }
9007 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
9008 XMMRegister tmp1Reg, XMMRegister tmp2Reg,
9009 XMMRegister tmp3Reg, XMMRegister tmp4Reg,
9010 Register tmp5, Register result, KRegister mask1, KRegister mask2) {
9011 Label copy_chars_loop, done, reset_sp, copy_tail;
9012
9013 // rsi: src
9014 // rdi: dst
9015 // rdx: len
9016 // rcx: tmp5
9017 // rax: result
9018
9019 // rsi holds start addr of source char[] to be compressed
9020 // rdi holds start addr of destination byte[]
9021 // rdx holds length
9022
9023 assert(len != result, "");
9024
9025 // save length for return
9026 movl(result, len);
9027
9028 if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
9029 VM_Version::supports_avx512vlbw() &&
9030 VM_Version::supports_bmi2()) {
9031
9032 Label copy_32_loop, copy_loop_tail, below_threshold, reset_for_copy_tail;
9033
9034 // alignment
9035 Label post_alignment;
9036
9037 // if length of the string is less than 32, handle it the old fashioned way
9038 testl(len, -32);
9039 jcc(Assembler::zero, below_threshold);
9040
9041 // First check whether a character is compressible ( <= 0xFF).
9042 // Create mask to test for Unicode chars inside zmm vector
9043 movl(tmp5, 0x00FF);
9044 evpbroadcastw(tmp2Reg, tmp5, Assembler::AVX_512bit);
9045
9046 testl(len, -64);
9047 jccb(Assembler::zero, post_alignment);
9048
9049 movl(tmp5, dst);
9050 andl(tmp5, (32 - 1));
9051 negl(tmp5);
9052 andl(tmp5, (32 - 1));
9053
9054 // bail out when there is nothing to be done
9055 testl(tmp5, 0xFFFFFFFF);
9056 jccb(Assembler::zero, post_alignment);
9057
9058 // ~(~0 << len), where len is the # of remaining elements to process
9059 movl(len, 0xFFFFFFFF);
9060 shlxl(len, len, tmp5);
9061 notl(len);
9062 kmovdl(mask2, len);
9063 movl(len, result);
9064
9065 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9066 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9067 ktestd(mask1, mask2);
9068 jcc(Assembler::carryClear, copy_tail);
9069
9070 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9071
9072 addptr(src, tmp5);
9073 addptr(src, tmp5);
9074 addptr(dst, tmp5);
9075 subl(len, tmp5);
9076
9077 bind(post_alignment);
9078 // end of alignment
9079
9080 movl(tmp5, len);
9081 andl(tmp5, (32 - 1)); // tail count (in chars)
9082 andl(len, ~(32 - 1)); // vector count (in chars)
9083 jccb(Assembler::zero, copy_loop_tail);
9084
9085 lea(src, Address(src, len, Address::times_2));
9086 lea(dst, Address(dst, len, Address::times_1));
9087 negptr(len);
9088
9089 bind(copy_32_loop);
9090 evmovdquw(tmp1Reg, Address(src, len, Address::times_2), Assembler::AVX_512bit);
9091 evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
9092 kortestdl(mask1, mask1);
9093 jccb(Assembler::carryClear, reset_for_copy_tail);
9094
9095 // All elements in current processed chunk are valid candidates for
9096 // compression. Write a truncated byte elements to the memory.
9097 evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
9098 addptr(len, 32);
9099 jccb(Assembler::notZero, copy_32_loop);
9100
9101 bind(copy_loop_tail);
9102 // bail out when there is nothing to be done
9103 testl(tmp5, 0xFFFFFFFF);
9104 jcc(Assembler::zero, done);
9105
9106 movl(len, tmp5);
9107
9108 // ~(~0 << len), where len is the # of remaining elements to process
9109 movl(tmp5, 0xFFFFFFFF);
9110 shlxl(tmp5, tmp5, len);
9111 notl(tmp5);
9112
9113 kmovdl(mask2, tmp5);
9114
9115 evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
9116 evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
9117 ktestd(mask1, mask2);
9118 jcc(Assembler::carryClear, copy_tail);
9119
9120 evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
9121 jmp(done);
9122
9123 bind(reset_for_copy_tail);
9124 lea(src, Address(src, tmp5, Address::times_2));
9125 lea(dst, Address(dst, tmp5, Address::times_1));
9126 subptr(len, tmp5);
9127 jmp(copy_chars_loop);
9128
9129 bind(below_threshold);
9130 }
9131
9132 if (UseSSE42Intrinsics) {
9133 Label copy_32_loop, copy_16, copy_tail_sse, reset_for_copy_tail;
9134
9135 // vectored compression
9136 testl(len, 0xfffffff8);
9137 jcc(Assembler::zero, copy_tail);
9138
9139 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors
9140 movdl(tmp1Reg, tmp5);
9141 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg
9142
9143 andl(len, 0xfffffff0);
9144 jccb(Assembler::zero, copy_16);
9145
9146 // compress 16 chars per iter
9147 pxor(tmp4Reg, tmp4Reg);
9148
9149 lea(src, Address(src, len, Address::times_2));
9150 lea(dst, Address(dst, len, Address::times_1));
9151 negptr(len);
9152
9153 bind(copy_32_loop);
9154 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters
9155 por(tmp4Reg, tmp2Reg);
9156 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
9157 por(tmp4Reg, tmp3Reg);
9158 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector
9159 jccb(Assembler::notZero, reset_for_copy_tail);
9160 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte
9161 movdqu(Address(dst, len, Address::times_1), tmp2Reg);
9162 addptr(len, 16);
9163 jccb(Assembler::notZero, copy_32_loop);
9164
9165 // compress next vector of 8 chars (if any)
9166 bind(copy_16);
9167 // len = 0
9168 testl(result, 0x00000008); // check if there's a block of 8 chars to compress
9169 jccb(Assembler::zero, copy_tail_sse);
9170
9171 pxor(tmp3Reg, tmp3Reg);
9172
9173 movdqu(tmp2Reg, Address(src, 0));
9174 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector
9175 jccb(Assembler::notZero, reset_for_copy_tail);
9176 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte
9177 movq(Address(dst, 0), tmp2Reg);
9178 addptr(src, 16);
9179 addptr(dst, 8);
9180 jmpb(copy_tail_sse);
9181
9182 bind(reset_for_copy_tail);
9183 movl(tmp5, result);
9184 andl(tmp5, 0x0000000f);
9185 lea(src, Address(src, tmp5, Address::times_2));
9186 lea(dst, Address(dst, tmp5, Address::times_1));
9187 subptr(len, tmp5);
9188 jmpb(copy_chars_loop);
9189
9190 bind(copy_tail_sse);
9191 movl(len, result);
9192 andl(len, 0x00000007); // tail count (in chars)
9193 }
9194 // compress 1 char per iter
9195 bind(copy_tail);
9196 testl(len, len);
9197 jccb(Assembler::zero, done);
9198 lea(src, Address(src, len, Address::times_2));
9199 lea(dst, Address(dst, len, Address::times_1));
9200 negptr(len);
9201
9202 bind(copy_chars_loop);
9203 load_unsigned_short(tmp5, Address(src, len, Address::times_2));
9204 testl(tmp5, 0xff00); // check if Unicode char
9205 jccb(Assembler::notZero, reset_sp);
9206 movb(Address(dst, len, Address::times_1), tmp5); // ASCII char; compress to 1 byte
9207 increment(len);
9208 jccb(Assembler::notZero, copy_chars_loop);
9209
9210 // add len then return (len will be zero if compress succeeded, otherwise negative)
9211 bind(reset_sp);
9212 addl(result, len);
9213
9214 bind(done);
9215 }
9216
9217 // Inflate byte[] array to char[].
9218 // ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
9219 // @IntrinsicCandidate
9220 // private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
9221 // for (int i = 0; i < len; i++) {
9222 // dst[dstOff++] = (char)(src[srcOff++] & 0xff);
9223 // }
9224 // }
9225 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
9226 XMMRegister tmp1, Register tmp2, KRegister mask) {
9227 Label copy_chars_loop, done, below_threshold, avx3_threshold;
9228 // rsi: src
9229 // rdi: dst
9230 // rdx: len
9231 // rcx: tmp2
9232
9233 // rsi holds start addr of source byte[] to be inflated
9234 // rdi holds start addr of destination char[]
9235 // rdx holds length
9236 assert_different_registers(src, dst, len, tmp2);
9237 movl(tmp2, len);
9238 if ((UseAVX > 2) && // AVX512
9239 VM_Version::supports_avx512vlbw() &&
9240 VM_Version::supports_bmi2()) {
9241
9242 Label copy_32_loop, copy_tail;
9243 Register tmp3_aliased = len;
9244
9245 // if length of the string is less than 16, handle it in an old fashioned way
9246 testl(len, -16);
9247 jcc(Assembler::zero, below_threshold);
9248
9249 testl(len, -1 * AVX3Threshold);
9250 jcc(Assembler::zero, avx3_threshold);
9251
9252 // In order to use only one arithmetic operation for the main loop we use
9253 // this pre-calculation
9254 andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
9255 andl(len, -32); // vector count
9256 jccb(Assembler::zero, copy_tail);
9257
9258 lea(src, Address(src, len, Address::times_1));
9259 lea(dst, Address(dst, len, Address::times_2));
9260 negptr(len);
9261
9262
9263 // inflate 32 chars per iter
9264 bind(copy_32_loop);
9265 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
9266 evmovdquw(Address(dst, len, Address::times_2), tmp1, Assembler::AVX_512bit);
9267 addptr(len, 32);
9268 jcc(Assembler::notZero, copy_32_loop);
9269
9270 bind(copy_tail);
9271 // bail out when there is nothing to be done
9272 testl(tmp2, -1); // we don't destroy the contents of tmp2 here
9273 jcc(Assembler::zero, done);
9274
9275 // ~(~0 << length), where length is the # of remaining elements to process
9276 movl(tmp3_aliased, -1);
9277 shlxl(tmp3_aliased, tmp3_aliased, tmp2);
9278 notl(tmp3_aliased);
9279 kmovdl(mask, tmp3_aliased);
9280 evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
9281 evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
9282
9283 jmp(done);
9284 bind(avx3_threshold);
9285 }
9286 if (UseSSE42Intrinsics) {
9287 Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
9288
9289 if (UseAVX > 1) {
9290 andl(tmp2, (16 - 1));
9291 andl(len, -16);
9292 jccb(Assembler::zero, copy_new_tail);
9293 } else {
9294 andl(tmp2, 0x00000007); // tail count (in chars)
9295 andl(len, 0xfffffff8); // vector count (in chars)
9296 jccb(Assembler::zero, copy_tail);
9297 }
9298
9299 // vectored inflation
9300 lea(src, Address(src, len, Address::times_1));
9301 lea(dst, Address(dst, len, Address::times_2));
9302 negptr(len);
9303
9304 if (UseAVX > 1) {
9305 bind(copy_16_loop);
9306 vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
9307 vmovdqu(Address(dst, len, Address::times_2), tmp1);
9308 addptr(len, 16);
9309 jcc(Assembler::notZero, copy_16_loop);
9310
9311 bind(below_threshold);
9312 bind(copy_new_tail);
9313 movl(len, tmp2);
9314 andl(tmp2, 0x00000007);
9315 andl(len, 0xFFFFFFF8);
9316 jccb(Assembler::zero, copy_tail);
9317
9318 pmovzxbw(tmp1, Address(src, 0));
9319 movdqu(Address(dst, 0), tmp1);
9320 addptr(src, 8);
9321 addptr(dst, 2 * 8);
9322
9323 jmp(copy_tail, true);
9324 }
9325
9326 // inflate 8 chars per iter
9327 bind(copy_8_loop);
9328 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words
9329 movdqu(Address(dst, len, Address::times_2), tmp1);
9330 addptr(len, 8);
9331 jcc(Assembler::notZero, copy_8_loop);
9332
9333 bind(copy_tail);
9334 movl(len, tmp2);
9335
9336 cmpl(len, 4);
9337 jccb(Assembler::less, copy_bytes);
9338
9339 movdl(tmp1, Address(src, 0)); // load 4 byte chars
9340 pmovzxbw(tmp1, tmp1);
9341 movq(Address(dst, 0), tmp1);
9342 subptr(len, 4);
9343 addptr(src, 4);
9344 addptr(dst, 8);
9345
9346 bind(copy_bytes);
9347 } else {
9348 bind(below_threshold);
9349 }
9350
9351 testl(len, len);
9352 jccb(Assembler::zero, done);
9353 lea(src, Address(src, len, Address::times_1));
9354 lea(dst, Address(dst, len, Address::times_2));
9355 negptr(len);
9356
9357 // inflate 1 char per iter
9358 bind(copy_chars_loop);
9359 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char
9360 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word
9361 increment(len);
9362 jcc(Assembler::notZero, copy_chars_loop);
9363
9364 bind(done);
9365 }
9366
9367
9368 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, bool merge, int vector_len) {
9369 switch(type) {
9370 case T_BYTE:
9371 case T_BOOLEAN:
9372 evmovdqub(dst, kmask, src, merge, vector_len);
9373 break;
9374 case T_CHAR:
9375 case T_SHORT:
9376 evmovdquw(dst, kmask, src, merge, vector_len);
9377 break;
9378 case T_INT:
9379 case T_FLOAT:
9380 evmovdqul(dst, kmask, src, merge, vector_len);
9381 break;
9382 case T_LONG:
9383 case T_DOUBLE:
9384 evmovdquq(dst, kmask, src, merge, vector_len);
9385 break;
9386 default:
9387 fatal("Unexpected type argument %s", type2name(type));
9388 break;
9389 }
9390 }
9391
9392 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, bool merge, int vector_len) {
9393 switch(type) {
9394 case T_BYTE:
9395 case T_BOOLEAN:
9396 evmovdqub(dst, kmask, src, merge, vector_len);
9397 break;
9398 case T_CHAR:
9399 case T_SHORT:
9400 evmovdquw(dst, kmask, src, merge, vector_len);
9401 break;
9402 case T_INT:
9403 case T_FLOAT:
9404 evmovdqul(dst, kmask, src, merge, vector_len);
9405 break;
9406 case T_LONG:
9407 case T_DOUBLE:
9408 evmovdquq(dst, kmask, src, merge, vector_len);
9409 break;
9410 default:
9411 fatal("Unexpected type argument %s", type2name(type));
9412 break;
9413 }
9414 }
9415
9416 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
9417 switch(masklen) {
9418 case 2:
9419 knotbl(dst, src);
9420 movl(rtmp, 3);
9421 kmovbl(ktmp, rtmp);
9422 kandbl(dst, ktmp, dst);
9423 break;
9424 case 4:
9425 knotbl(dst, src);
9426 movl(rtmp, 15);
9427 kmovbl(ktmp, rtmp);
9428 kandbl(dst, ktmp, dst);
9429 break;
9430 case 8:
9431 knotbl(dst, src);
9432 break;
9433 case 16:
9434 knotwl(dst, src);
9435 break;
9436 case 32:
9437 knotdl(dst, src);
9438 break;
9439 case 64:
9440 knotql(dst, src);
9441 break;
9442 default:
9443 fatal("Unexpected vector length %d", masklen);
9444 break;
9445 }
9446 }
9447
9448 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9449 switch(type) {
9450 case T_BOOLEAN:
9451 case T_BYTE:
9452 kandbl(dst, src1, src2);
9453 break;
9454 case T_CHAR:
9455 case T_SHORT:
9456 kandwl(dst, src1, src2);
9457 break;
9458 case T_INT:
9459 case T_FLOAT:
9460 kanddl(dst, src1, src2);
9461 break;
9462 case T_LONG:
9463 case T_DOUBLE:
9464 kandql(dst, src1, src2);
9465 break;
9466 default:
9467 fatal("Unexpected type argument %s", type2name(type));
9468 break;
9469 }
9470 }
9471
9472 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9473 switch(type) {
9474 case T_BOOLEAN:
9475 case T_BYTE:
9476 korbl(dst, src1, src2);
9477 break;
9478 case T_CHAR:
9479 case T_SHORT:
9480 korwl(dst, src1, src2);
9481 break;
9482 case T_INT:
9483 case T_FLOAT:
9484 kordl(dst, src1, src2);
9485 break;
9486 case T_LONG:
9487 case T_DOUBLE:
9488 korql(dst, src1, src2);
9489 break;
9490 default:
9491 fatal("Unexpected type argument %s", type2name(type));
9492 break;
9493 }
9494 }
9495
9496 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
9497 switch(type) {
9498 case T_BOOLEAN:
9499 case T_BYTE:
9500 kxorbl(dst, src1, src2);
9501 break;
9502 case T_CHAR:
9503 case T_SHORT:
9504 kxorwl(dst, src1, src2);
9505 break;
9506 case T_INT:
9507 case T_FLOAT:
9508 kxordl(dst, src1, src2);
9509 break;
9510 case T_LONG:
9511 case T_DOUBLE:
9512 kxorql(dst, src1, src2);
9513 break;
9514 default:
9515 fatal("Unexpected type argument %s", type2name(type));
9516 break;
9517 }
9518 }
9519
9520 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9521 switch(type) {
9522 case T_BOOLEAN:
9523 case T_BYTE:
9524 evpermb(dst, mask, nds, src, merge, vector_len); break;
9525 case T_CHAR:
9526 case T_SHORT:
9527 evpermw(dst, mask, nds, src, merge, vector_len); break;
9528 case T_INT:
9529 case T_FLOAT:
9530 evpermd(dst, mask, nds, src, merge, vector_len); break;
9531 case T_LONG:
9532 case T_DOUBLE:
9533 evpermq(dst, mask, nds, src, merge, vector_len); break;
9534 default:
9535 fatal("Unexpected type argument %s", type2name(type)); break;
9536 }
9537 }
9538
9539 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9540 switch(type) {
9541 case T_BOOLEAN:
9542 case T_BYTE:
9543 evpermb(dst, mask, nds, src, merge, vector_len); break;
9544 case T_CHAR:
9545 case T_SHORT:
9546 evpermw(dst, mask, nds, src, merge, vector_len); break;
9547 case T_INT:
9548 case T_FLOAT:
9549 evpermd(dst, mask, nds, src, merge, vector_len); break;
9550 case T_LONG:
9551 case T_DOUBLE:
9552 evpermq(dst, mask, nds, src, merge, vector_len); break;
9553 default:
9554 fatal("Unexpected type argument %s", type2name(type)); break;
9555 }
9556 }
9557
9558 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9559 switch(type) {
9560 case T_BYTE:
9561 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9562 case T_SHORT:
9563 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9564 case T_INT:
9565 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9566 case T_LONG:
9567 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9568 default:
9569 fatal("Unexpected type argument %s", type2name(type)); break;
9570 }
9571 }
9572
9573 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9574 switch(type) {
9575 case T_BYTE:
9576 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9577 case T_SHORT:
9578 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9579 case T_INT:
9580 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9581 case T_LONG:
9582 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9583 default:
9584 fatal("Unexpected type argument %s", type2name(type)); break;
9585 }
9586 }
9587
9588 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9589 switch(type) {
9590 case T_BYTE:
9591 evpminsb(dst, mask, nds, src, merge, vector_len); break;
9592 case T_SHORT:
9593 evpminsw(dst, mask, nds, src, merge, vector_len); break;
9594 case T_INT:
9595 evpminsd(dst, mask, nds, src, merge, vector_len); break;
9596 case T_LONG:
9597 evpminsq(dst, mask, nds, src, merge, vector_len); break;
9598 default:
9599 fatal("Unexpected type argument %s", type2name(type)); break;
9600 }
9601 }
9602
9603 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9604 switch(type) {
9605 case T_BYTE:
9606 evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
9607 case T_SHORT:
9608 evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
9609 case T_INT:
9610 evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
9611 case T_LONG:
9612 evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
9613 default:
9614 fatal("Unexpected type argument %s", type2name(type)); break;
9615 }
9616 }
9617
9618 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9619 switch(type) {
9620 case T_INT:
9621 evpxord(dst, mask, nds, src, merge, vector_len); break;
9622 case T_LONG:
9623 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9624 default:
9625 fatal("Unexpected type argument %s", type2name(type)); break;
9626 }
9627 }
9628
9629 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9630 switch(type) {
9631 case T_INT:
9632 evpxord(dst, mask, nds, src, merge, vector_len); break;
9633 case T_LONG:
9634 evpxorq(dst, mask, nds, src, merge, vector_len); break;
9635 default:
9636 fatal("Unexpected type argument %s", type2name(type)); break;
9637 }
9638 }
9639
9640 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9641 switch(type) {
9642 case T_INT:
9643 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9644 case T_LONG:
9645 evporq(dst, mask, nds, src, merge, vector_len); break;
9646 default:
9647 fatal("Unexpected type argument %s", type2name(type)); break;
9648 }
9649 }
9650
9651 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9652 switch(type) {
9653 case T_INT:
9654 Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
9655 case T_LONG:
9656 evporq(dst, mask, nds, src, merge, vector_len); break;
9657 default:
9658 fatal("Unexpected type argument %s", type2name(type)); break;
9659 }
9660 }
9661
9662 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9663 switch(type) {
9664 case T_INT:
9665 evpandd(dst, mask, nds, src, merge, vector_len); break;
9666 case T_LONG:
9667 evpandq(dst, mask, nds, src, merge, vector_len); break;
9668 default:
9669 fatal("Unexpected type argument %s", type2name(type)); break;
9670 }
9671 }
9672
9673 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9674 switch(type) {
9675 case T_INT:
9676 evpandd(dst, mask, nds, src, merge, vector_len); break;
9677 case T_LONG:
9678 evpandq(dst, mask, nds, src, merge, vector_len); break;
9679 default:
9680 fatal("Unexpected type argument %s", type2name(type)); break;
9681 }
9682 }
9683
9684 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
9685 switch(masklen) {
9686 case 8:
9687 kortestbl(src1, src2);
9688 break;
9689 case 16:
9690 kortestwl(src1, src2);
9691 break;
9692 case 32:
9693 kortestdl(src1, src2);
9694 break;
9695 case 64:
9696 kortestql(src1, src2);
9697 break;
9698 default:
9699 fatal("Unexpected mask length %d", masklen);
9700 break;
9701 }
9702 }
9703
9704
9705 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
9706 switch(masklen) {
9707 case 8:
9708 ktestbl(src1, src2);
9709 break;
9710 case 16:
9711 ktestwl(src1, src2);
9712 break;
9713 case 32:
9714 ktestdl(src1, src2);
9715 break;
9716 case 64:
9717 ktestql(src1, src2);
9718 break;
9719 default:
9720 fatal("Unexpected mask length %d", masklen);
9721 break;
9722 }
9723 }
9724
9725 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9726 switch(type) {
9727 case T_INT:
9728 evprold(dst, mask, src, shift, merge, vlen_enc); break;
9729 case T_LONG:
9730 evprolq(dst, mask, src, shift, merge, vlen_enc); break;
9731 default:
9732 fatal("Unexpected type argument %s", type2name(type)); break;
9733 break;
9734 }
9735 }
9736
9737 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
9738 switch(type) {
9739 case T_INT:
9740 evprord(dst, mask, src, shift, merge, vlen_enc); break;
9741 case T_LONG:
9742 evprorq(dst, mask, src, shift, merge, vlen_enc); break;
9743 default:
9744 fatal("Unexpected type argument %s", type2name(type)); break;
9745 }
9746 }
9747
9748 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9749 switch(type) {
9750 case T_INT:
9751 evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
9752 case T_LONG:
9753 evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
9754 default:
9755 fatal("Unexpected type argument %s", type2name(type)); break;
9756 }
9757 }
9758
9759 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
9760 switch(type) {
9761 case T_INT:
9762 evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
9763 case T_LONG:
9764 evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
9765 default:
9766 fatal("Unexpected type argument %s", type2name(type)); break;
9767 }
9768 }
9769
9770 void MacroAssembler::evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9771 assert(rscratch != noreg || always_reachable(src), "missing");
9772
9773 if (reachable(src)) {
9774 evpandq(dst, nds, as_Address(src), vector_len);
9775 } else {
9776 lea(rscratch, src);
9777 evpandq(dst, nds, Address(rscratch, 0), vector_len);
9778 }
9779 }
9780
9781 void MacroAssembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch) {
9782 assert(rscratch != noreg || always_reachable(src), "missing");
9783
9784 if (reachable(src)) {
9785 Assembler::evpaddq(dst, mask, nds, as_Address(src), merge, vector_len);
9786 } else {
9787 lea(rscratch, src);
9788 Assembler::evpaddq(dst, mask, nds, Address(rscratch, 0), merge, vector_len);
9789 }
9790 }
9791
9792 void MacroAssembler::evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9793 assert(rscratch != noreg || always_reachable(src), "missing");
9794
9795 if (reachable(src)) {
9796 evporq(dst, nds, as_Address(src), vector_len);
9797 } else {
9798 lea(rscratch, src);
9799 evporq(dst, nds, Address(rscratch, 0), vector_len);
9800 }
9801 }
9802
9803 void MacroAssembler::vpshufb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9804 assert(rscratch != noreg || always_reachable(src), "missing");
9805
9806 if (reachable(src)) {
9807 vpshufb(dst, nds, as_Address(src), vector_len);
9808 } else {
9809 lea(rscratch, src);
9810 vpshufb(dst, nds, Address(rscratch, 0), vector_len);
9811 }
9812 }
9813
9814 void MacroAssembler::vpor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
9815 assert(rscratch != noreg || always_reachable(src), "missing");
9816
9817 if (reachable(src)) {
9818 Assembler::vpor(dst, nds, as_Address(src), vector_len);
9819 } else {
9820 lea(rscratch, src);
9821 Assembler::vpor(dst, nds, Address(rscratch, 0), vector_len);
9822 }
9823 }
9824
9825 void MacroAssembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch) {
9826 assert(rscratch != noreg || always_reachable(src3), "missing");
9827
9828 if (reachable(src3)) {
9829 vpternlogq(dst, imm8, src2, as_Address(src3), vector_len);
9830 } else {
9831 lea(rscratch, src3);
9832 vpternlogq(dst, imm8, src2, Address(rscratch, 0), vector_len);
9833 }
9834 }
9835
9836 #if COMPILER2_OR_JVMCI
9837
9838 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
9839 Register length, Register temp, int vec_enc) {
9840 // Computing mask for predicated vector store.
9841 movptr(temp, -1);
9842 bzhiq(temp, temp, length);
9843 kmov(mask, temp);
9844 evmovdqu(bt, mask, dst, xmm, true, vec_enc);
9845 }
9846
9847 // Set memory operation for length "less than" 64 bytes.
9848 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
9849 XMMRegister xmm, KRegister mask, Register length,
9850 Register temp, bool use64byteVector) {
9851 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9852 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9853 if (!use64byteVector) {
9854 fill32(dst, disp, xmm);
9855 subptr(length, 32 >> shift);
9856 fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
9857 } else {
9858 assert(MaxVectorSize == 64, "vector length != 64");
9859 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
9860 }
9861 }
9862
9863
9864 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
9865 XMMRegister xmm, KRegister mask, Register length,
9866 Register temp) {
9867 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9868 const BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
9869 fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
9870 }
9871
9872
9873 void MacroAssembler::fill32(Address dst, XMMRegister xmm) {
9874 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9875 vmovdqu(dst, xmm);
9876 }
9877
9878 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
9879 fill32(Address(dst, disp), xmm);
9880 }
9881
9882 void MacroAssembler::fill64(Address dst, XMMRegister xmm, bool use64byteVector) {
9883 assert(MaxVectorSize >= 32, "vector length should be >= 32");
9884 if (!use64byteVector) {
9885 fill32(dst, xmm);
9886 fill32(dst.plus_disp(32), xmm);
9887 } else {
9888 evmovdquq(dst, xmm, Assembler::AVX_512bit);
9889 }
9890 }
9891
9892 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
9893 fill64(Address(dst, disp), xmm, use64byteVector);
9894 }
9895
9896 #ifdef _LP64
9897 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
9898 Register count, Register rtmp, XMMRegister xtmp) {
9899 Label L_exit;
9900 Label L_fill_start;
9901 Label L_fill_64_bytes;
9902 Label L_fill_96_bytes;
9903 Label L_fill_128_bytes;
9904 Label L_fill_128_bytes_loop;
9905 Label L_fill_128_loop_header;
9906 Label L_fill_128_bytes_loop_header;
9907 Label L_fill_128_bytes_loop_pre_header;
9908 Label L_fill_zmm_sequence;
9909
9910 int shift = -1;
9911 int avx3threshold = VM_Version::avx3_threshold();
9912 switch(type) {
9913 case T_BYTE: shift = 0;
9914 break;
9915 case T_SHORT: shift = 1;
9916 break;
9917 case T_INT: shift = 2;
9918 break;
9919 /* Uncomment when LONG fill stubs are supported.
9920 case T_LONG: shift = 3;
9921 break;
9922 */
9923 default:
9924 fatal("Unhandled type: %s\n", type2name(type));
9925 }
9926
9927 if ((avx3threshold != 0) || (MaxVectorSize == 32)) {
9928
9929 if (MaxVectorSize == 64) {
9930 cmpq(count, avx3threshold >> shift);
9931 jcc(Assembler::greater, L_fill_zmm_sequence);
9932 }
9933
9934 evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
9935
9936 bind(L_fill_start);
9937
9938 cmpq(count, 32 >> shift);
9939 jccb(Assembler::greater, L_fill_64_bytes);
9940 fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
9941 jmp(L_exit);
9942
9943 bind(L_fill_64_bytes);
9944 cmpq(count, 64 >> shift);
9945 jccb(Assembler::greater, L_fill_96_bytes);
9946 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
9947 jmp(L_exit);
9948
9949 bind(L_fill_96_bytes);
9950 cmpq(count, 96 >> shift);
9951 jccb(Assembler::greater, L_fill_128_bytes);
9952 fill64(to, 0, xtmp);
9953 subq(count, 64 >> shift);
9954 fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
9955 jmp(L_exit);
9956
9957 bind(L_fill_128_bytes);
9958 cmpq(count, 128 >> shift);
9959 jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
9960 fill64(to, 0, xtmp);
9961 fill32(to, 64, xtmp);
9962 subq(count, 96 >> shift);
9963 fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
9964 jmp(L_exit);
9965
9966 bind(L_fill_128_bytes_loop_pre_header);
9967 {
9968 mov(rtmp, to);
9969 andq(rtmp, 31);
9970 jccb(Assembler::zero, L_fill_128_bytes_loop_header);
9971 negq(rtmp);
9972 addq(rtmp, 32);
9973 mov64(r8, -1L);
9974 bzhiq(r8, r8, rtmp);
9975 kmovql(k2, r8);
9976 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_256bit);
9977 addq(to, rtmp);
9978 shrq(rtmp, shift);
9979 subq(count, rtmp);
9980 }
9981
9982 cmpq(count, 128 >> shift);
9983 jcc(Assembler::less, L_fill_start);
9984
9985 bind(L_fill_128_bytes_loop_header);
9986 subq(count, 128 >> shift);
9987
9988 align32();
9989 bind(L_fill_128_bytes_loop);
9990 fill64(to, 0, xtmp);
9991 fill64(to, 64, xtmp);
9992 addq(to, 128);
9993 subq(count, 128 >> shift);
9994 jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
9995
9996 addq(count, 128 >> shift);
9997 jcc(Assembler::zero, L_exit);
9998 jmp(L_fill_start);
9999 }
10000
10001 if (MaxVectorSize == 64) {
10002 // Sequence using 64 byte ZMM register.
10003 Label L_fill_128_bytes_zmm;
10004 Label L_fill_192_bytes_zmm;
10005 Label L_fill_192_bytes_loop_zmm;
10006 Label L_fill_192_bytes_loop_header_zmm;
10007 Label L_fill_192_bytes_loop_pre_header_zmm;
10008 Label L_fill_start_zmm_sequence;
10009
10010 bind(L_fill_zmm_sequence);
10011 evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
10012
10013 bind(L_fill_start_zmm_sequence);
10014 cmpq(count, 64 >> shift);
10015 jccb(Assembler::greater, L_fill_128_bytes_zmm);
10016 fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
10017 jmp(L_exit);
10018
10019 bind(L_fill_128_bytes_zmm);
10020 cmpq(count, 128 >> shift);
10021 jccb(Assembler::greater, L_fill_192_bytes_zmm);
10022 fill64(to, 0, xtmp, true);
10023 subq(count, 64 >> shift);
10024 fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
10025 jmp(L_exit);
10026
10027 bind(L_fill_192_bytes_zmm);
10028 cmpq(count, 192 >> shift);
10029 jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
10030 fill64(to, 0, xtmp, true);
10031 fill64(to, 64, xtmp, true);
10032 subq(count, 128 >> shift);
10033 fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
10034 jmp(L_exit);
10035
10036 bind(L_fill_192_bytes_loop_pre_header_zmm);
10037 {
10038 movq(rtmp, to);
10039 andq(rtmp, 63);
10040 jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
10041 negq(rtmp);
10042 addq(rtmp, 64);
10043 mov64(r8, -1L);
10044 bzhiq(r8, r8, rtmp);
10045 kmovql(k2, r8);
10046 evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, true, Assembler::AVX_512bit);
10047 addq(to, rtmp);
10048 shrq(rtmp, shift);
10049 subq(count, rtmp);
10050 }
10051
10052 cmpq(count, 192 >> shift);
10053 jcc(Assembler::less, L_fill_start_zmm_sequence);
10054
10055 bind(L_fill_192_bytes_loop_header_zmm);
10056 subq(count, 192 >> shift);
10057
10058 align32();
10059 bind(L_fill_192_bytes_loop_zmm);
10060 fill64(to, 0, xtmp, true);
10061 fill64(to, 64, xtmp, true);
10062 fill64(to, 128, xtmp, true);
10063 addq(to, 192);
10064 subq(count, 192 >> shift);
10065 jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
10066
10067 addq(count, 192 >> shift);
10068 jcc(Assembler::zero, L_exit);
10069 jmp(L_fill_start_zmm_sequence);
10070 }
10071 bind(L_exit);
10072 }
10073 #endif
10074 #endif //COMPILER2_OR_JVMCI
10075
10076
10077 #ifdef _LP64
10078 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
10079 Label done;
10080 cvttss2sil(dst, src);
10081 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10082 cmpl(dst, 0x80000000); // float_sign_flip
10083 jccb(Assembler::notEqual, done);
10084 subptr(rsp, 8);
10085 movflt(Address(rsp, 0), src);
10086 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10087 pop(dst);
10088 bind(done);
10089 }
10090
10091 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
10092 Label done;
10093 cvttsd2sil(dst, src);
10094 // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
10095 cmpl(dst, 0x80000000); // float_sign_flip
10096 jccb(Assembler::notEqual, done);
10097 subptr(rsp, 8);
10098 movdbl(Address(rsp, 0), src);
10099 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10100 pop(dst);
10101 bind(done);
10102 }
10103
10104 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
10105 Label done;
10106 cvttss2siq(dst, src);
10107 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10108 jccb(Assembler::notEqual, done);
10109 subptr(rsp, 8);
10110 movflt(Address(rsp, 0), src);
10111 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10112 pop(dst);
10113 bind(done);
10114 }
10115
10116 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10117 // Following code is line by line assembly translation rounding algorithm.
10118 // Please refer to java.lang.Math.round(float) algorithm for details.
10119 const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
10120 const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
10121 const int32_t FloatConsts_EXP_BIAS = 127;
10122 const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
10123 const int32_t MINUS_32 = 0xFFFFFFE0;
10124 Label L_special_case, L_block1, L_exit;
10125 movl(rtmp, FloatConsts_EXP_BIT_MASK);
10126 movdl(dst, src);
10127 andl(dst, rtmp);
10128 sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
10129 movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
10130 subl(rtmp, dst);
10131 movl(rcx, rtmp);
10132 movl(dst, MINUS_32);
10133 testl(rtmp, dst);
10134 jccb(Assembler::notEqual, L_special_case);
10135 movdl(dst, src);
10136 andl(dst, FloatConsts_SIGNIF_BIT_MASK);
10137 orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
10138 movdl(rtmp, src);
10139 testl(rtmp, rtmp);
10140 jccb(Assembler::greaterEqual, L_block1);
10141 negl(dst);
10142 bind(L_block1);
10143 sarl(dst);
10144 addl(dst, 0x1);
10145 sarl(dst, 0x1);
10146 jmp(L_exit);
10147 bind(L_special_case);
10148 convert_f2i(dst, src);
10149 bind(L_exit);
10150 }
10151
10152 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
10153 // Following code is line by line assembly translation rounding algorithm.
10154 // Please refer to java.lang.Math.round(double) algorithm for details.
10155 const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
10156 const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
10157 const int64_t DoubleConsts_EXP_BIAS = 1023;
10158 const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
10159 const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
10160 Label L_special_case, L_block1, L_exit;
10161 mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
10162 movq(dst, src);
10163 andq(dst, rtmp);
10164 sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
10165 mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
10166 subq(rtmp, dst);
10167 movq(rcx, rtmp);
10168 mov64(dst, MINUS_64);
10169 testq(rtmp, dst);
10170 jccb(Assembler::notEqual, L_special_case);
10171 movq(dst, src);
10172 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
10173 andq(dst, rtmp);
10174 mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
10175 orq(dst, rtmp);
10176 movq(rtmp, src);
10177 testq(rtmp, rtmp);
10178 jccb(Assembler::greaterEqual, L_block1);
10179 negq(dst);
10180 bind(L_block1);
10181 sarq(dst);
10182 addq(dst, 0x1);
10183 sarq(dst, 0x1);
10184 jmp(L_exit);
10185 bind(L_special_case);
10186 convert_d2l(dst, src);
10187 bind(L_exit);
10188 }
10189
10190 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
10191 Label done;
10192 cvttsd2siq(dst, src);
10193 cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10194 jccb(Assembler::notEqual, done);
10195 subptr(rsp, 8);
10196 movdbl(Address(rsp, 0), src);
10197 call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10198 pop(dst);
10199 bind(done);
10200 }
10201
10202 void MacroAssembler::cache_wb(Address line)
10203 {
10204 // 64 bit cpus always support clflush
10205 assert(VM_Version::supports_clflush(), "clflush should be available");
10206 bool optimized = VM_Version::supports_clflushopt();
10207 bool no_evict = VM_Version::supports_clwb();
10208
10209 // prefer clwb (writeback without evict) otherwise
10210 // prefer clflushopt (potentially parallel writeback with evict)
10211 // otherwise fallback on clflush (serial writeback with evict)
10212
10213 if (optimized) {
10214 if (no_evict) {
10215 clwb(line);
10216 } else {
10217 clflushopt(line);
10218 }
10219 } else {
10220 // no need for fence when using CLFLUSH
10221 clflush(line);
10222 }
10223 }
10224
10225 void MacroAssembler::cache_wbsync(bool is_pre)
10226 {
10227 assert(VM_Version::supports_clflush(), "clflush should be available");
10228 bool optimized = VM_Version::supports_clflushopt();
10229 bool no_evict = VM_Version::supports_clwb();
10230
10231 // pick the correct implementation
10232
10233 if (!is_pre && (optimized || no_evict)) {
10234 // need an sfence for post flush when using clflushopt or clwb
10235 // otherwise no no need for any synchroniaztion
10236
10237 sfence();
10238 }
10239 }
10240
10241 #endif // _LP64
10242
10243 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
10244 switch (cond) {
10245 // Note some conditions are synonyms for others
10246 case Assembler::zero: return Assembler::notZero;
10247 case Assembler::notZero: return Assembler::zero;
10248 case Assembler::less: return Assembler::greaterEqual;
10249 case Assembler::lessEqual: return Assembler::greater;
10250 case Assembler::greater: return Assembler::lessEqual;
10251 case Assembler::greaterEqual: return Assembler::less;
10252 case Assembler::below: return Assembler::aboveEqual;
10253 case Assembler::belowEqual: return Assembler::above;
10254 case Assembler::above: return Assembler::belowEqual;
10255 case Assembler::aboveEqual: return Assembler::below;
10256 case Assembler::overflow: return Assembler::noOverflow;
10257 case Assembler::noOverflow: return Assembler::overflow;
10258 case Assembler::negative: return Assembler::positive;
10259 case Assembler::positive: return Assembler::negative;
10260 case Assembler::parity: return Assembler::noParity;
10261 case Assembler::noParity: return Assembler::parity;
10262 }
10263 ShouldNotReachHere(); return Assembler::overflow;
10264 }
10265
10266 SkipIfEqual::SkipIfEqual(
10267 MacroAssembler* masm, const bool* flag_addr, bool value, Register rscratch) {
10268 _masm = masm;
10269 _masm->cmp8(ExternalAddress((address)flag_addr), value, rscratch);
10270 _masm->jcc(Assembler::equal, _label);
10271 }
10272
10273 SkipIfEqual::~SkipIfEqual() {
10274 _masm->bind(_label);
10275 }
10276
10277 // 32-bit Windows has its own fast-path implementation
10278 // of get_thread
10279 #if !defined(WIN32) || defined(_LP64)
10280
10281 // This is simply a call to Thread::current()
10282 void MacroAssembler::get_thread(Register thread) {
10283 if (thread != rax) {
10284 push(rax);
10285 }
10286 LP64_ONLY(push(rdi);)
10287 LP64_ONLY(push(rsi);)
10288 push(rdx);
10289 push(rcx);
10290 #ifdef _LP64
10291 push(r8);
10292 push(r9);
10293 push(r10);
10294 push(r11);
10295 #endif
10296
10297 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
10298
10299 #ifdef _LP64
10300 pop(r11);
10301 pop(r10);
10302 pop(r9);
10303 pop(r8);
10304 #endif
10305 pop(rcx);
10306 pop(rdx);
10307 LP64_ONLY(pop(rsi);)
10308 LP64_ONLY(pop(rdi);)
10309 if (thread != rax) {
10310 mov(thread, rax);
10311 pop(rax);
10312 }
10313 }
10314
10315
10316 #endif // !WIN32 || _LP64
10317
10318 void MacroAssembler::check_stack_alignment(Register sp, const char* msg, unsigned bias, Register tmp) {
10319 Label L_stack_ok;
10320 if (bias == 0) {
10321 testptr(sp, 2 * wordSize - 1);
10322 } else {
10323 // lea(tmp, Address(rsp, bias);
10324 mov(tmp, sp);
10325 addptr(tmp, bias);
10326 testptr(tmp, 2 * wordSize - 1);
10327 }
10328 jcc(Assembler::equal, L_stack_ok);
10329 block_comment(msg);
10330 stop(msg);
10331 bind(L_stack_ok);
10332 }
10333
10334 // Implements lightweight-locking.
10335 //
10336 // obj: the object to be locked
10337 // reg_rax: rax
10338 // thread: the thread which attempts to lock obj
10339 // tmp: a temporary register
10340 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10341 assert(reg_rax == rax, "");
10342 assert_different_registers(basic_lock, obj, reg_rax, thread, tmp);
10343
10344 Label push;
10345 const Register top = tmp;
10346
10347 // Preload the markWord. It is important that this is the first
10348 // instruction emitted as it is part of C1's null check semantics.
10349 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10350
10351 if (UseObjectMonitorTable) {
10352 // Clear cache in case fast locking succeeds.
10353 movptr(Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))), 0);
10354 }
10355
10356 // Load top.
10357 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10358
10359 // Check if the lock-stack is full.
10360 cmpl(top, LockStack::end_offset());
10361 jcc(Assembler::greaterEqual, slow);
10362
10363 // Check for recursion.
10364 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10365 jcc(Assembler::equal, push);
10366
10367 // Check header for monitor (0b10).
10368 testptr(reg_rax, markWord::monitor_value);
10369 jcc(Assembler::notZero, slow);
10370
10371 // Try to lock. Transition lock bits 0b01 => 0b00
10372 movptr(tmp, reg_rax);
10373 andptr(tmp, ~(int32_t)markWord::unlocked_value);
10374 orptr(reg_rax, markWord::unlocked_value);
10375 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10376 jcc(Assembler::notEqual, slow);
10377
10378 // Restore top, CAS clobbers register.
10379 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10380
10381 bind(push);
10382 // After successful lock, push object on lock-stack.
10383 movptr(Address(thread, top), obj);
10384 incrementl(top, oopSize);
10385 movl(Address(thread, JavaThread::lock_stack_top_offset()), top);
10386 }
10387
10388 // Implements lightweight-unlocking.
10389 //
10390 // obj: the object to be unlocked
10391 // reg_rax: rax
10392 // thread: the thread
10393 // tmp: a temporary register
10394 void MacroAssembler::lightweight_unlock(Register obj, Register reg_rax, Register thread, Register tmp, Label& slow) {
10395 assert(reg_rax == rax, "");
10396 assert_different_registers(obj, reg_rax, thread, tmp);
10397
10398 Label unlocked, push_and_slow;
10399 const Register top = tmp;
10400
10401 // Check if obj is top of lock-stack.
10402 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10403 cmpptr(obj, Address(thread, top, Address::times_1, -oopSize));
10404 jcc(Assembler::notEqual, slow);
10405
10406 // Pop lock-stack.
10407 DEBUG_ONLY(movptr(Address(thread, top, Address::times_1, -oopSize), 0);)
10408 subl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10409
10410 // Check if recursive.
10411 cmpptr(obj, Address(thread, top, Address::times_1, -2 * oopSize));
10412 jcc(Assembler::equal, unlocked);
10413
10414 // Not recursive. Check header for monitor (0b10).
10415 movptr(reg_rax, Address(obj, oopDesc::mark_offset_in_bytes()));
10416 testptr(reg_rax, markWord::monitor_value);
10417 jcc(Assembler::notZero, push_and_slow);
10418
10419 #ifdef ASSERT
10420 // Check header not unlocked (0b01).
10421 Label not_unlocked;
10422 testptr(reg_rax, markWord::unlocked_value);
10423 jcc(Assembler::zero, not_unlocked);
10424 stop("lightweight_unlock already unlocked");
10425 bind(not_unlocked);
10426 #endif
10427
10428 // Try to unlock. Transition lock bits 0b00 => 0b01
10429 movptr(tmp, reg_rax);
10430 orptr(tmp, markWord::unlocked_value);
10431 lock(); cmpxchgptr(tmp, Address(obj, oopDesc::mark_offset_in_bytes()));
10432 jcc(Assembler::equal, unlocked);
10433
10434 bind(push_and_slow);
10435 // Restore lock-stack and handle the unlock in runtime.
10436 #ifdef ASSERT
10437 movl(top, Address(thread, JavaThread::lock_stack_top_offset()));
10438 movptr(Address(thread, top), obj);
10439 #endif
10440 addl(Address(thread, JavaThread::lock_stack_top_offset()), oopSize);
10441 jmp(slow);
10442
10443 bind(unlocked);
10444 }