1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "asm/register.hpp"
  30 #include "code/vmreg.inline.hpp"
  31 #include "compiler/oopMap.hpp"
  32 #include "utilities/macros.hpp"
  33 #include "runtime/rtmLocking.hpp"
  34 #include "runtime/vm_version.hpp"
  35 
  36 // MacroAssembler extends Assembler by frequently used macros.
  37 //
  38 // Instructions for which a 'better' code sequence exists depending
  39 // on arguments should also go in here.
  40 
  41 class MacroAssembler: public Assembler {
  42   friend class LIR_Assembler;
  43   friend class Runtime1;      // as_Address()
  44 
  45  public:
  46   // Support for VM calls
  47   //
  48   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  49   // may customize this version by overriding it for its purposes (e.g., to save/restore
  50   // additional registers when doing a VM call).
  51 
  52   virtual void call_VM_leaf_base(
  53     address entry_point,               // the entry point
  54     int     number_of_arguments        // the number of arguments to pop after the call
  55   );
  56 
  57  protected:
  58   // This is the base routine called by the different versions of call_VM. The interpreter
  59   // may customize this version by overriding it for its purposes (e.g., to save/restore
  60   // additional registers when doing a VM call).
  61   //
  62   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  63   // returns the register which contains the thread upon return. If a thread register has been
  64   // specified, the return value will correspond to that register. If no last_java_sp is specified
  65   // (noreg) than rsp will be used instead.
  66   virtual void call_VM_base(           // returns the register containing the thread upon return
  67     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  68     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  69     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  70     address  entry_point,              // the entry point
  71     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  72     bool     check_exceptions          // whether to check for pending exceptions after return
  73   );
  74 
  75   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  76 
  77   // helpers for FPU flag access
  78   // tmp is a temporary register, if none is available use noreg
  79   void save_rax   (Register tmp);
  80   void restore_rax(Register tmp);
  81 
  82  public:
  83   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  84 
  85  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  86  // The implementation is only non-empty for the InterpreterMacroAssembler,
  87  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  88  virtual void check_and_handle_popframe(Register java_thread);
  89  virtual void check_and_handle_earlyret(Register java_thread);
  90 
  91   Address as_Address(AddressLiteral adr);
  92   Address as_Address(ArrayAddress adr, Register rscratch);
  93 
  94   // Support for NULL-checks
  95   //
  96   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  97   // If the accessed location is M[reg + offset] and the offset is known, provide the
  98   // offset. No explicit code generation is needed if the offset is within a certain
  99   // range (0 <= offset <= page_size).
 100 
 101   void null_check(Register reg, int offset = -1);
 102   static bool needs_explicit_null_check(intptr_t offset);
 103   static bool uses_implicit_null_check(void* address);
 104 
 105   // Required platform-specific helpers for Label::patch_instructions.
 106   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 107   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 108     unsigned char op = branch[0];
 109     assert(op == 0xE8 /* call */ ||
 110         op == 0xE9 /* jmp */ ||
 111         op == 0xEB /* short jmp */ ||
 112         (op & 0xF0) == 0x70 /* short jcc */ ||
 113         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 114         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 115         "Invalid opcode at patch point");
 116 
 117     if (op == 0xEB || (op & 0xF0) == 0x70) {
 118       // short offset operators (jmp and jcc)
 119       char* disp = (char*) &branch[1];
 120       int imm8 = target - (address) &disp[1];
 121       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
 122                 file == NULL ? "<NULL>" : file, line);
 123       *disp = imm8;
 124     } else {
 125       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 126       int imm32 = target - (address) &disp[1];
 127       *disp = imm32;
 128     }
 129   }
 130 
 131   // The following 4 methods return the offset of the appropriate move instruction
 132 
 133   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 134   int load_unsigned_byte(Register dst, Address src);
 135   int load_unsigned_short(Register dst, Address src);
 136 
 137   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 138   int load_signed_byte(Register dst, Address src);
 139   int load_signed_short(Register dst, Address src);
 140 
 141   // Support for sign-extension (hi:lo = extend_sign(lo))
 142   void extend_sign(Register hi, Register lo);
 143 
 144   // Load and store values by size and signed-ness
 145   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 146   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 147 
 148   // Support for inc/dec with optimal instruction selection depending on value
 149 
 150   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 151   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 152 
 153   void decrementl(Address dst, int value = 1);
 154   void decrementl(Register reg, int value = 1);
 155 
 156   void decrementq(Register reg, int value = 1);
 157   void decrementq(Address dst, int value = 1);
 158 
 159   void incrementl(Address dst, int value = 1);
 160   void incrementl(Register reg, int value = 1);
 161 
 162   void incrementq(Register reg, int value = 1);
 163   void incrementq(Address dst, int value = 1);
 164 
 165   // Support optimal SSE move instructions.
 166   void movflt(XMMRegister dst, XMMRegister src) {
 167     if (dst-> encoding() == src->encoding()) return;
 168     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 169     else                       { movss (dst, src); return; }
 170   }
 171   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 172   void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 173   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 174 
 175   // Move with zero extension
 176   void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
 177 
 178   void movdbl(XMMRegister dst, XMMRegister src) {
 179     if (dst-> encoding() == src->encoding()) return;
 180     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 181     else                       { movsd (dst, src); return; }
 182   }
 183 
 184   void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 185 
 186   void movdbl(XMMRegister dst, Address src) {
 187     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 188     else                         { movlpd(dst, src); return; }
 189   }
 190   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 191 
 192   void incrementl(AddressLiteral dst, Register rscratch = noreg);
 193   void incrementl(ArrayAddress   dst, Register rscratch);
 194 
 195   void incrementq(AddressLiteral dst, Register rscratch = noreg);
 196 
 197   // Alignment
 198   void align32();
 199   void align64();
 200   void align(int modulus);
 201   void align(int modulus, int target);
 202 
 203   void post_call_nop();
 204   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 205   void fat_nop();
 206 
 207   // Stack frame creation/removal
 208   void enter();
 209   void leave();
 210 
 211   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 212   // The pointer will be loaded into the thread register.
 213   void get_thread(Register thread);
 214 
 215 #ifdef _LP64
 216   // Support for argument shuffling
 217 
 218   // bias in bytes
 219   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 220   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 221   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 222   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 223   void move_ptr(VMRegPair src, VMRegPair dst);
 224   void object_move(OopMap* map,
 225                    int oop_handle_offset,
 226                    int framesize_in_slots,
 227                    VMRegPair src,
 228                    VMRegPair dst,
 229                    bool is_receiver,
 230                    int* receiver_offset);
 231 #endif // _LP64
 232 
 233   // Support for VM calls
 234   //
 235   // It is imperative that all calls into the VM are handled via the call_VM macros.
 236   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 237   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 238 
 239 
 240   void call_VM(Register oop_result,
 241                address entry_point,
 242                bool check_exceptions = true);
 243   void call_VM(Register oop_result,
 244                address entry_point,
 245                Register arg_1,
 246                bool check_exceptions = true);
 247   void call_VM(Register oop_result,
 248                address entry_point,
 249                Register arg_1, Register arg_2,
 250                bool check_exceptions = true);
 251   void call_VM(Register oop_result,
 252                address entry_point,
 253                Register arg_1, Register arg_2, Register arg_3,
 254                bool check_exceptions = true);
 255 
 256   // Overloadings with last_Java_sp
 257   void call_VM(Register oop_result,
 258                Register last_java_sp,
 259                address entry_point,
 260                int number_of_arguments = 0,
 261                bool check_exceptions = true);
 262   void call_VM(Register oop_result,
 263                Register last_java_sp,
 264                address entry_point,
 265                Register arg_1, bool
 266                check_exceptions = true);
 267   void call_VM(Register oop_result,
 268                Register last_java_sp,
 269                address entry_point,
 270                Register arg_1, Register arg_2,
 271                bool check_exceptions = true);
 272   void call_VM(Register oop_result,
 273                Register last_java_sp,
 274                address entry_point,
 275                Register arg_1, Register arg_2, Register arg_3,
 276                bool check_exceptions = true);
 277 
 278   void get_vm_result  (Register oop_result, Register thread);
 279   void get_vm_result_2(Register metadata_result, Register thread);
 280 
 281   // These always tightly bind to MacroAssembler::call_VM_base
 282   // bypassing the virtual implementation
 283   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 284   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 285   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 286   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 287   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 288 
 289   void call_VM_leaf0(address entry_point);
 290   void call_VM_leaf(address entry_point,
 291                     int number_of_arguments = 0);
 292   void call_VM_leaf(address entry_point,
 293                     Register arg_1);
 294   void call_VM_leaf(address entry_point,
 295                     Register arg_1, Register arg_2);
 296   void call_VM_leaf(address entry_point,
 297                     Register arg_1, Register arg_2, Register arg_3);
 298 
 299   void call_VM_leaf(address entry_point,
 300                     Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 301 
 302   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 303   // bypassing the virtual implementation
 304   void super_call_VM_leaf(address entry_point);
 305   void super_call_VM_leaf(address entry_point, Register arg_1);
 306   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 307   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 308   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 309 
 310   // last Java Frame (fills frame anchor)
 311   void set_last_Java_frame(Register thread,
 312                            Register last_java_sp,
 313                            Register last_java_fp,
 314                            address  last_java_pc,
 315                            Register rscratch);
 316 
 317   // thread in the default location (r15_thread on 64bit)
 318   void set_last_Java_frame(Register last_java_sp,
 319                            Register last_java_fp,
 320                            address  last_java_pc,
 321                            Register rscratch);
 322 
 323   void reset_last_Java_frame(Register thread, bool clear_fp);
 324 
 325   // thread in the default location (r15_thread on 64bit)
 326   void reset_last_Java_frame(bool clear_fp);
 327 
 328   // jobjects
 329   void clear_jweak_tag(Register possibly_jweak);
 330   void resolve_jobject(Register value, Register thread, Register tmp);
 331 
 332   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 333   void c2bool(Register x);
 334 
 335   // C++ bool manipulation
 336 
 337   void movbool(Register dst, Address src);
 338   void movbool(Address dst, bool boolconst);
 339   void movbool(Address dst, Register src);
 340   void testbool(Register dst);
 341 
 342   void resolve_oop_handle(Register result, Register tmp);
 343   void resolve_weak_handle(Register result, Register tmp);
 344   void load_mirror(Register mirror, Register method, Register tmp);
 345   void load_method_holder_cld(Register rresult, Register rmethod);
 346 
 347   void load_method_holder(Register holder, Register method);
 348 
 349   // oop manipulations
 350   void load_klass(Register dst, Register src, Register tmp);
 351   void store_klass(Register dst, Register src, Register tmp);
 352 
 353   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 354                       Register tmp1, Register thread_tmp);
 355   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 356                        Register tmp1, Register tmp2, Register tmp3);
 357 
 358   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 359                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 360   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 361                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 362   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 363                       Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 364 
 365   // Used for storing NULL. All other oop constants should be
 366   // stored using routines that take a jobject.
 367   void store_heap_oop_null(Address dst);
 368 
 369 #ifdef _LP64
 370   void store_klass_gap(Register dst, Register src);
 371 
 372   // This dummy is to prevent a call to store_heap_oop from
 373   // converting a zero (like NULL) into a Register by giving
 374   // the compiler two choices it can't resolve
 375 
 376   void store_heap_oop(Address dst, void* dummy);
 377 
 378   void encode_heap_oop(Register r);
 379   void decode_heap_oop(Register r);
 380   void encode_heap_oop_not_null(Register r);
 381   void decode_heap_oop_not_null(Register r);
 382   void encode_heap_oop_not_null(Register dst, Register src);
 383   void decode_heap_oop_not_null(Register dst, Register src);
 384 
 385   void set_narrow_oop(Register dst, jobject obj);
 386   void set_narrow_oop(Address dst, jobject obj);
 387   void cmp_narrow_oop(Register dst, jobject obj);
 388   void cmp_narrow_oop(Address dst, jobject obj);
 389 
 390   void encode_klass_not_null(Register r, Register tmp);
 391   void decode_klass_not_null(Register r, Register tmp);
 392   void encode_and_move_klass_not_null(Register dst, Register src);
 393   void decode_and_move_klass_not_null(Register dst, Register src);
 394   void set_narrow_klass(Register dst, Klass* k);
 395   void set_narrow_klass(Address dst, Klass* k);
 396   void cmp_narrow_klass(Register dst, Klass* k);
 397   void cmp_narrow_klass(Address dst, Klass* k);
 398 
 399   // if heap base register is used - reinit it with the correct value
 400   void reinit_heapbase();
 401 
 402   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 403 
 404 #endif // _LP64
 405 
 406   // Int division/remainder for Java
 407   // (as idivl, but checks for special case as described in JVM spec.)
 408   // returns idivl instruction offset for implicit exception handling
 409   int corrected_idivl(Register reg);
 410 
 411   // Long division/remainder for Java
 412   // (as idivq, but checks for special case as described in JVM spec.)
 413   // returns idivq instruction offset for implicit exception handling
 414   int corrected_idivq(Register reg);
 415 
 416   void int3();
 417 
 418   // Long operation macros for a 32bit cpu
 419   // Long negation for Java
 420   void lneg(Register hi, Register lo);
 421 
 422   // Long multiplication for Java
 423   // (destroys contents of eax, ebx, ecx and edx)
 424   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 425 
 426   // Long shifts for Java
 427   // (semantics as described in JVM spec.)
 428   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 429   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 430 
 431   // Long compare for Java
 432   // (semantics as described in JVM spec.)
 433   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 434 
 435 
 436   // misc
 437 
 438   // Sign extension
 439   void sign_extend_short(Register reg);
 440   void sign_extend_byte(Register reg);
 441 
 442   // Division by power of 2, rounding towards 0
 443   void division_with_shift(Register reg, int shift_value);
 444 
 445 #ifndef _LP64
 446   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 447   //
 448   // CF (corresponds to C0) if x < y
 449   // PF (corresponds to C2) if unordered
 450   // ZF (corresponds to C3) if x = y
 451   //
 452   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 453   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 454   void fcmp(Register tmp);
 455   // Variant of the above which allows y to be further down the stack
 456   // and which only pops x and y if specified. If pop_right is
 457   // specified then pop_left must also be specified.
 458   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 459 
 460   // Floating-point comparison for Java
 461   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 462   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 463   // (semantics as described in JVM spec.)
 464   void fcmp2int(Register dst, bool unordered_is_less);
 465   // Variant of the above which allows y to be further down the stack
 466   // and which only pops x and y if specified. If pop_right is
 467   // specified then pop_left must also be specified.
 468   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 469 
 470   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 471   // tmp is a temporary register, if none is available use noreg
 472   void fremr(Register tmp);
 473 
 474   // only if +VerifyFPU
 475   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 476 #endif // !LP64
 477 
 478   // dst = c = a * b + c
 479   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 480   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 481 
 482   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 483   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 484   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 485   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 486 
 487 
 488   // same as fcmp2int, but using SSE2
 489   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 490   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 491 
 492   // branch to L if FPU flag C2 is set/not set
 493   // tmp is a temporary register, if none is available use noreg
 494   void jC2 (Register tmp, Label& L);
 495   void jnC2(Register tmp, Label& L);
 496 
 497   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 498   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 499   void load_float(Address src);
 500 
 501   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 502   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 503   void store_float(Address dst);
 504 
 505   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 506   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 507   void load_double(Address src);
 508 
 509   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 510   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 511   void store_double(Address dst);
 512 
 513 #ifndef _LP64
 514   // Pop ST (ffree & fincstp combined)
 515   void fpop();
 516 
 517   void empty_FPU_stack();
 518 #endif // !_LP64
 519 
 520   void push_IU_state();
 521   void pop_IU_state();
 522 
 523   void push_FPU_state();
 524   void pop_FPU_state();
 525 
 526   void push_CPU_state();
 527   void pop_CPU_state();
 528 
 529   void push_cont_fastpath();
 530   void pop_cont_fastpath();
 531 
 532   void inc_held_monitor_count();
 533   void dec_held_monitor_count();
 534 
 535   DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
 536 
 537   // Round up to a power of two
 538   void round_to(Register reg, int modulus);
 539 
 540 private:
 541   // General purpose and XMM registers potentially clobbered by native code; there
 542   // is no need for FPU or AVX opmask related methods because C1/interpreter
 543   // - we save/restore FPU state as a whole always
 544   // - do not care about AVX-512 opmask
 545   static RegSet call_clobbered_gp_registers();
 546   static XMMRegSet call_clobbered_xmm_registers();
 547 
 548   void push_set(XMMRegSet set, int offset);
 549   void pop_set(XMMRegSet set, int offset);
 550 
 551 public:
 552   void push_set(RegSet set, int offset = -1);
 553   void pop_set(RegSet set, int offset = -1);
 554 
 555   // Push and pop everything that might be clobbered by a native
 556   // runtime call.
 557   // Only save the lower 64 bits of each vector register.
 558   // Additional registers can be excluded in a passed RegSet.
 559   void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
 560   void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
 561 
 562   void push_call_clobbered_registers(bool save_fpu = true) {
 563     push_call_clobbered_registers_except(RegSet(), save_fpu);
 564   }
 565   void pop_call_clobbered_registers(bool restore_fpu = true) {
 566     pop_call_clobbered_registers_except(RegSet(), restore_fpu);
 567   }
 568 
 569   // allocation
 570   void tlab_allocate(
 571     Register thread,                   // Current thread
 572     Register obj,                      // result: pointer to object after successful allocation
 573     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 574     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 575     Register t1,                       // temp register
 576     Register t2,                       // temp register
 577     Label&   slow_case                 // continuation point if fast allocation fails
 578   );
 579   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 580 
 581   // interface method calling
 582   void lookup_interface_method(Register recv_klass,
 583                                Register intf_klass,
 584                                RegisterOrConstant itable_index,
 585                                Register method_result,
 586                                Register scan_temp,
 587                                Label& no_such_interface,
 588                                bool return_method = true);
 589 
 590   // virtual method calling
 591   void lookup_virtual_method(Register recv_klass,
 592                              RegisterOrConstant vtable_index,
 593                              Register method_result);
 594 
 595   // Test sub_klass against super_klass, with fast and slow paths.
 596 
 597   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 598   // One of the three labels can be NULL, meaning take the fall-through.
 599   // If super_check_offset is -1, the value is loaded up from super_klass.
 600   // No registers are killed, except temp_reg.
 601   void check_klass_subtype_fast_path(Register sub_klass,
 602                                      Register super_klass,
 603                                      Register temp_reg,
 604                                      Label* L_success,
 605                                      Label* L_failure,
 606                                      Label* L_slow_path,
 607                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 608 
 609   // The rest of the type check; must be wired to a corresponding fast path.
 610   // It does not repeat the fast path logic, so don't use it standalone.
 611   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 612   // Updates the sub's secondary super cache as necessary.
 613   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 614   void check_klass_subtype_slow_path(Register sub_klass,
 615                                      Register super_klass,
 616                                      Register temp_reg,
 617                                      Register temp2_reg,
 618                                      Label* L_success,
 619                                      Label* L_failure,
 620                                      bool set_cond_codes = false);
 621 
 622   // Simplified, combined version, good for typical uses.
 623   // Falls through on failure.
 624   void check_klass_subtype(Register sub_klass,
 625                            Register super_klass,
 626                            Register temp_reg,
 627                            Label& L_success);
 628 
 629   void clinit_barrier(Register klass,
 630                       Register thread,
 631                       Label* L_fast_path = NULL,
 632                       Label* L_slow_path = NULL);
 633 
 634   // method handles (JSR 292)
 635   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 636 
 637   // Debugging
 638 
 639   // only if +VerifyOops
 640   void _verify_oop(Register reg, const char* s, const char* file, int line);
 641   void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
 642 
 643   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
 644     if (VerifyOops) {
 645       _verify_oop(reg, s, file, line);
 646     }
 647   }
 648   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
 649     if (VerifyOops) {
 650       _verify_oop_addr(reg, s, file, line);
 651     }
 652   }
 653 
 654   // TODO: verify method and klass metadata (compare against vptr?)
 655   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 656   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 657 
 658 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
 659 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
 660 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
 661 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 662 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 663 
 664   // Verify or restore cpu control state after JNI call
 665   void restore_cpu_control_state_after_jni(Register rscratch);
 666 
 667   // prints msg, dumps registers and stops execution
 668   void stop(const char* msg);
 669 
 670   // prints msg and continues
 671   void warn(const char* msg);
 672 
 673   // dumps registers and other state
 674   void print_state();
 675 
 676   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 677   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 678   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 679   static void print_state64(int64_t pc, int64_t regs[]);
 680 
 681   void os_breakpoint();
 682 
 683   void untested()                                { stop("untested"); }
 684 
 685   void unimplemented(const char* what = "");
 686 
 687   void should_not_reach_here()                   { stop("should not reach here"); }
 688 
 689   void print_CPU_state();
 690 
 691   // Stack overflow checking
 692   void bang_stack_with_offset(int offset) {
 693     // stack grows down, caller passes positive offset
 694     assert(offset > 0, "must bang with negative offset");
 695     movl(Address(rsp, (-offset)), rax);
 696   }
 697 
 698   // Writes to stack successive pages until offset reached to check for
 699   // stack overflow + shadow pages.  Also, clobbers tmp
 700   void bang_stack_size(Register size, Register tmp);
 701 
 702   // Check for reserved stack access in method being exited (for JIT)
 703   void reserved_stack_check();
 704 
 705   void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
 706 
 707   void verify_tlab();
 708 
 709   static Condition negate_condition(Condition cond);
 710 
 711   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 712   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 713   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 714   // here in MacroAssembler. The major exception to this rule is call
 715 
 716   // Arithmetics
 717 
 718 
 719   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 720   void addptr(Address dst, Register src);
 721 
 722   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 723   void addptr(Register dst, int32_t src);
 724   void addptr(Register dst, Register src);
 725   void addptr(Register dst, RegisterOrConstant src) {
 726     if (src.is_constant()) addptr(dst, src.as_constant());
 727     else                   addptr(dst, src.as_register());
 728   }
 729 
 730   void andptr(Register dst, int32_t src);
 731   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 732 
 733   void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
 734 
 735   // renamed to drag out the casting of address to int32_t/intptr_t
 736   void cmp32(Register src1, int32_t imm);
 737 
 738   void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
 739   // compare reg - mem, or reg - &mem
 740   void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
 741 
 742   void cmp32(Register src1, Address src2);
 743 
 744 #ifndef _LP64
 745   void cmpklass(Address dst, Metadata* obj);
 746   void cmpklass(Register dst, Metadata* obj);
 747   void cmpoop(Address dst, jobject obj);
 748 #endif // _LP64
 749 
 750   void cmpoop(Register src1, Register src2);
 751   void cmpoop(Register src1, Address src2);
 752   void cmpoop(Register dst, jobject obj, Register rscratch);
 753 
 754   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 755   void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
 756 
 757   void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
 758 
 759   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 760   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 761   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 762 
 763   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 764   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 765 
 766   // cmp64 to avoild hiding cmpq
 767   void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
 768 
 769   void cmpxchgptr(Register reg, Address adr);
 770 
 771   void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
 772 
 773   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 774   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 775 
 776 
 777   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 778 
 779   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 780 
 781   void shlptr(Register dst, int32_t shift);
 782   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 783 
 784   void shrptr(Register dst, int32_t shift);
 785   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 786 
 787   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 788   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 789 
 790   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 791 
 792   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 793   void subptr(Register dst, int32_t src);
 794   // Force generation of a 4 byte immediate value even if it fits into 8bit
 795   void subptr_imm32(Register dst, int32_t src);
 796   void subptr(Register dst, Register src);
 797   void subptr(Register dst, RegisterOrConstant src) {
 798     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 799     else                   subptr(dst,       src.as_register());
 800   }
 801 
 802   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 803   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 804 
 805   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 806   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 807 
 808   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 809 
 810 
 811 
 812   // Helper functions for statistics gathering.
 813   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 814   void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
 815   // Unconditional atomic increment.
 816   void atomic_incl(Address counter_addr);
 817   void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
 818 #ifdef _LP64
 819   void atomic_incq(Address counter_addr);
 820   void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
 821 #endif
 822   void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { LP64_ONLY(atomic_incq(counter_addr, rscratch)) NOT_LP64(atomic_incl(counter_addr, rscratch)) ; }
 823   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 824 
 825   void lea(Register dst, Address        adr) { Assembler::lea(dst, adr); }
 826   void lea(Register dst, AddressLiteral adr);
 827   void lea(Address  dst, AddressLiteral adr, Register rscratch);
 828 
 829   void leal32(Register dst, Address src) { leal(dst, src); }
 830 
 831   // Import other testl() methods from the parent class or else
 832   // they will be hidden by the following overriding declaration.
 833   using Assembler::testl;
 834   void testl(Address dst, int32_t imm32);
 835   void testl(Register dst, int32_t imm32);
 836   void testl(Register dst, AddressLiteral src); // requires reachable address
 837   using Assembler::testq;
 838   void testq(Address dst, int32_t imm32);
 839   void testq(Register dst, int32_t imm32);
 840 
 841   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 842   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 843   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 844   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 845 
 846   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 847   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 848   void testptr(Register src1, Register src2);
 849 
 850   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 851   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 852 
 853   // Calls
 854 
 855   void call(Label& L, relocInfo::relocType rtype);
 856   void call(Register entry);
 857   void call(Address addr) { Assembler::call(addr); }
 858 
 859   // NOTE: this call transfers to the effective address of entry NOT
 860   // the address contained by entry. This is because this is more natural
 861   // for jumps/calls.
 862   void call(AddressLiteral entry, Register rscratch = rax);
 863 
 864   // Emit the CompiledIC call idiom
 865   void ic_call(address entry, jint method_index = 0);
 866 
 867   void emit_static_call_stub();
 868 
 869   // Jumps
 870 
 871   // NOTE: these jumps transfer to the effective address of dst NOT
 872   // the address contained by dst. This is because this is more natural
 873   // for jumps/calls.
 874   void jump(AddressLiteral dst, Register rscratch = noreg);
 875 
 876   void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
 877 
 878   // 32bit can do a case table jump in one instruction but we no longer allow the base
 879   // to be installed in the Address class. This jump will transfer to the address
 880   // contained in the location described by entry (not the address of entry)
 881   void jump(ArrayAddress entry, Register rscratch);
 882 
 883   // Floating
 884 
 885   void push_f(XMMRegister r);
 886   void pop_f(XMMRegister r);
 887   void push_d(XMMRegister r);
 888   void pop_d(XMMRegister r);
 889 
 890   void andpd(XMMRegister dst, XMMRegister    src) { Assembler::andpd(dst, src); }
 891   void andpd(XMMRegister dst, Address        src) { Assembler::andpd(dst, src); }
 892   void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 893 
 894   void andps(XMMRegister dst, XMMRegister    src) { Assembler::andps(dst, src); }
 895   void andps(XMMRegister dst, Address        src) { Assembler::andps(dst, src); }
 896   void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 897 
 898   void comiss(XMMRegister dst, XMMRegister    src) { Assembler::comiss(dst, src); }
 899   void comiss(XMMRegister dst, Address        src) { Assembler::comiss(dst, src); }
 900   void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 901 
 902   void comisd(XMMRegister dst, XMMRegister    src) { Assembler::comisd(dst, src); }
 903   void comisd(XMMRegister dst, Address        src) { Assembler::comisd(dst, src); }
 904   void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 905 
 906 #ifndef _LP64
 907   void fadd_s(Address        src) { Assembler::fadd_s(src); }
 908   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 909 
 910   void fldcw(Address        src) { Assembler::fldcw(src); }
 911   void fldcw(AddressLiteral src);
 912 
 913   void fld_s(int index)          { Assembler::fld_s(index); }
 914   void fld_s(Address        src) { Assembler::fld_s(src); }
 915   void fld_s(AddressLiteral src);
 916 
 917   void fld_d(Address        src) { Assembler::fld_d(src); }
 918   void fld_d(AddressLiteral src);
 919 
 920   void fld_x(Address        src) { Assembler::fld_x(src); }
 921   void fld_x(AddressLiteral src) { Assembler::fld_x(as_Address(src)); }
 922 
 923   void fmul_s(Address        src) { Assembler::fmul_s(src); }
 924   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 925 #endif // !_LP64
 926 
 927   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 928   void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
 929 
 930 #ifdef _LP64
 931  private:
 932   void sha256_AVX2_one_round_compute(
 933     Register  reg_old_h,
 934     Register  reg_a,
 935     Register  reg_b,
 936     Register  reg_c,
 937     Register  reg_d,
 938     Register  reg_e,
 939     Register  reg_f,
 940     Register  reg_g,
 941     Register  reg_h,
 942     int iter);
 943   void sha256_AVX2_four_rounds_compute_first(int start);
 944   void sha256_AVX2_four_rounds_compute_last(int start);
 945   void sha256_AVX2_one_round_and_sched(
 946         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 947         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 948         XMMRegister xmm_2,     /* ymm6 */
 949         XMMRegister xmm_3,     /* ymm7 */
 950         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 951         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 952         Register    reg_c,      /* edi */
 953         Register    reg_d,      /* esi */
 954         Register    reg_e,      /* r8d */
 955         Register    reg_f,      /* r9d */
 956         Register    reg_g,      /* r10d */
 957         Register    reg_h,      /* r11d */
 958         int iter);
 959 
 960   void addm(int disp, Register r1, Register r2);
 961 
 962   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 963                                      Register e, Register f, Register g, Register h, int iteration);
 964 
 965   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 966                                           Register a, Register b, Register c, Register d, Register e, Register f,
 967                                           Register g, Register h, int iteration);
 968 
 969   void addmq(int disp, Register r1, Register r2);
 970  public:
 971   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 972                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 973                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 974                    bool multi_block, XMMRegister shuf_mask);
 975   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 976                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 977                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 978                    XMMRegister shuf_mask);
 979 #endif // _LP64
 980 
 981   void fast_md5(Register buf, Address state, Address ofs, Address limit,
 982                 bool multi_block);
 983 
 984   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
 985                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
 986                  Register buf, Register state, Register ofs, Register limit, Register rsp,
 987                  bool multi_block);
 988 
 989 #ifdef _LP64
 990   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 991                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 992                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 993                    bool multi_block, XMMRegister shuf_mask);
 994 #else
 995   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 996                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 997                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 998                    bool multi_block);
 999 #endif
1000 
1001   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1002                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1003                 Register rax, Register rcx, Register rdx, Register tmp);
1004 
1005 #ifndef _LP64
1006  private:
1007   // Initialized in macroAssembler_x86_constants.cpp
1008   static address ONES;
1009   static address L_2IL0FLOATPACKET_0;
1010   static address PI4_INV;
1011   static address PI4X3;
1012   static address PI4X4;
1013 
1014  public:
1015   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1016                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1017                 Register rax, Register rcx, Register rdx, Register tmp1);
1018 
1019   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1020                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1021                 Register rax, Register rcx, Register rdx, Register tmp);
1022 
1023   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1024                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1025                 Register rdx, Register tmp);
1026 
1027   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1028                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1029                 Register rax, Register rbx, Register rdx);
1030 
1031   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1032                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1033                 Register rax, Register rcx, Register rdx, Register tmp);
1034 
1035   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1036                         Register edx, Register ebx, Register esi, Register edi,
1037                         Register ebp, Register esp);
1038 
1039   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1040                          Register esi, Register edi, Register ebp, Register esp);
1041 
1042   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1043                         Register edx, Register ebx, Register esi, Register edi,
1044                         Register ebp, Register esp);
1045 
1046   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1047                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1048                 Register rax, Register rcx, Register rdx, Register tmp);
1049 #endif // !_LP64
1050 
1051 private:
1052 
1053   // these are private because users should be doing movflt/movdbl
1054 
1055   void movss(Address     dst, XMMRegister    src) { Assembler::movss(dst, src); }
1056   void movss(XMMRegister dst, XMMRegister    src) { Assembler::movss(dst, src); }
1057   void movss(XMMRegister dst, Address        src) { Assembler::movss(dst, src); }
1058   void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1059 
1060   void movlpd(XMMRegister dst, Address        src) {Assembler::movlpd(dst, src); }
1061   void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1062 
1063 public:
1064 
1065   void addsd(XMMRegister dst, XMMRegister    src) { Assembler::addsd(dst, src); }
1066   void addsd(XMMRegister dst, Address        src) { Assembler::addsd(dst, src); }
1067   void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1068 
1069   void addss(XMMRegister dst, XMMRegister    src) { Assembler::addss(dst, src); }
1070   void addss(XMMRegister dst, Address        src) { Assembler::addss(dst, src); }
1071   void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1072 
1073   void addpd(XMMRegister dst, XMMRegister    src) { Assembler::addpd(dst, src); }
1074   void addpd(XMMRegister dst, Address        src) { Assembler::addpd(dst, src); }
1075   void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1076 
1077   using Assembler::vbroadcastsd;
1078   void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1079 
1080   using Assembler::vbroadcastss;
1081   void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1082 
1083   void divsd(XMMRegister dst, XMMRegister    src) { Assembler::divsd(dst, src); }
1084   void divsd(XMMRegister dst, Address        src) { Assembler::divsd(dst, src); }
1085   void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1086 
1087   void divss(XMMRegister dst, XMMRegister    src) { Assembler::divss(dst, src); }
1088   void divss(XMMRegister dst, Address        src) { Assembler::divss(dst, src); }
1089   void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1090 
1091   // Move Unaligned Double Quadword
1092   void movdqu(Address     dst, XMMRegister    src);
1093   void movdqu(XMMRegister dst, XMMRegister    src);
1094   void movdqu(XMMRegister dst, Address        src);
1095   void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1096 
1097   void kmovwl(Register  dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1098   void kmovwl(Address   dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1099   void kmovwl(KRegister dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1100   void kmovwl(KRegister dst, Register       src) { Assembler::kmovwl(dst, src); }
1101   void kmovwl(KRegister dst, Address        src) { Assembler::kmovwl(dst, src); }
1102   void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1103 
1104   void kmovql(KRegister dst, KRegister      src) { Assembler::kmovql(dst, src); }
1105   void kmovql(KRegister dst, Register       src) { Assembler::kmovql(dst, src); }
1106   void kmovql(Register  dst, KRegister      src) { Assembler::kmovql(dst, src); }
1107   void kmovql(KRegister dst, Address        src) { Assembler::kmovql(dst, src); }
1108   void kmovql(Address   dst, KRegister      src) { Assembler::kmovql(dst, src); }
1109   void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1110 
1111   // Safe move operation, lowers down to 16bit moves for targets supporting
1112   // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1113   void kmov(Address  dst, KRegister src);
1114   void kmov(KRegister dst, Address src);
1115   void kmov(KRegister dst, KRegister src);
1116   void kmov(Register dst, KRegister src);
1117   void kmov(KRegister dst, Register src);
1118 
1119   using Assembler::movddup;
1120   void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1121 
1122   using Assembler::vmovddup;
1123   void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1124 
1125   // AVX Unaligned forms
1126   void vmovdqu(Address     dst, XMMRegister    src);
1127   void vmovdqu(XMMRegister dst, Address        src);
1128   void vmovdqu(XMMRegister dst, XMMRegister    src);
1129   void vmovdqu(XMMRegister dst, AddressLiteral src,                 Register rscratch = noreg);
1130   void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1131 
1132   // AVX512 Unaligned
1133   void evmovdqu(BasicType type, KRegister kmask, Address     dst, XMMRegister src, bool merge, int vector_len);
1134   void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address     src, bool merge, int vector_len);
1135 
1136   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1137   void evmovdqub(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1138 
1139   void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1140     if (dst->encoding() != src->encoding() || mask != k0)  {
1141       Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1142     }
1143   }
1144   void evmovdqub(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1145   void evmovdqub(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1146   void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1147 
1148   void evmovdquw(Address     dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1149   void evmovdquw(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1150 
1151   void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1152     if (dst->encoding() != src->encoding() || mask != k0) {
1153       Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1154     }
1155   }
1156   void evmovdquw(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1157   void evmovdquw(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1158   void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1159 
1160   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1161      if (dst->encoding() != src->encoding()) {
1162        Assembler::evmovdqul(dst, src, vector_len);
1163      }
1164   }
1165   void evmovdqul(Address     dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1166   void evmovdqul(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1167 
1168   void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1169     if (dst->encoding() != src->encoding() || mask != k0)  {
1170       Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1171     }
1172   }
1173   void evmovdqul(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1174   void evmovdqul(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1175   void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1176 
1177   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1178     if (dst->encoding() != src->encoding()) {
1179       Assembler::evmovdquq(dst, src, vector_len);
1180     }
1181   }
1182   void evmovdquq(XMMRegister dst, Address        src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1183   void evmovdquq(Address     dst, XMMRegister    src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1184   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1185 
1186   void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1187     if (dst->encoding() != src->encoding() || mask != k0) {
1188       Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1189     }
1190   }
1191   void evmovdquq(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1192   void evmovdquq(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1193   void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1194 
1195   // Move Aligned Double Quadword
1196   void movdqa(XMMRegister dst, XMMRegister    src) { Assembler::movdqa(dst, src); }
1197   void movdqa(XMMRegister dst, Address        src) { Assembler::movdqa(dst, src); }
1198   void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1199 
1200   void movsd(Address     dst, XMMRegister    src) { Assembler::movsd(dst, src); }
1201   void movsd(XMMRegister dst, XMMRegister    src) { Assembler::movsd(dst, src); }
1202   void movsd(XMMRegister dst, Address        src) { Assembler::movsd(dst, src); }
1203   void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1204 
1205   void mulpd(XMMRegister dst, XMMRegister    src) { Assembler::mulpd(dst, src); }
1206   void mulpd(XMMRegister dst, Address        src) { Assembler::mulpd(dst, src); }
1207   void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1208 
1209   void mulsd(XMMRegister dst, XMMRegister    src) { Assembler::mulsd(dst, src); }
1210   void mulsd(XMMRegister dst, Address        src) { Assembler::mulsd(dst, src); }
1211   void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1212 
1213   void mulss(XMMRegister dst, XMMRegister    src) { Assembler::mulss(dst, src); }
1214   void mulss(XMMRegister dst, Address        src) { Assembler::mulss(dst, src); }
1215   void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1216 
1217   // Carry-Less Multiplication Quadword
1218   void pclmulldq(XMMRegister dst, XMMRegister src) {
1219     // 0x00 - multiply lower 64 bits [0:63]
1220     Assembler::pclmulqdq(dst, src, 0x00);
1221   }
1222   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1223     // 0x11 - multiply upper 64 bits [64:127]
1224     Assembler::pclmulqdq(dst, src, 0x11);
1225   }
1226 
1227   void pcmpeqb(XMMRegister dst, XMMRegister src);
1228   void pcmpeqw(XMMRegister dst, XMMRegister src);
1229 
1230   void pcmpestri(XMMRegister dst, Address src, int imm8);
1231   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1232 
1233   void pmovzxbw(XMMRegister dst, XMMRegister src);
1234   void pmovzxbw(XMMRegister dst, Address src);
1235 
1236   void pmovmskb(Register dst, XMMRegister src);
1237 
1238   void ptest(XMMRegister dst, XMMRegister src);
1239 
1240   void roundsd(XMMRegister dst, XMMRegister    src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1241   void roundsd(XMMRegister dst, Address        src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1242   void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1243 
1244   void sqrtss(XMMRegister dst, XMMRegister     src) { Assembler::sqrtss(dst, src); }
1245   void sqrtss(XMMRegister dst, Address         src) { Assembler::sqrtss(dst, src); }
1246   void sqrtss(XMMRegister dst, AddressLiteral  src, Register rscratch = noreg);
1247 
1248   void subsd(XMMRegister dst, XMMRegister    src) { Assembler::subsd(dst, src); }
1249   void subsd(XMMRegister dst, Address        src) { Assembler::subsd(dst, src); }
1250   void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1251 
1252   void subss(XMMRegister dst, XMMRegister    src) { Assembler::subss(dst, src); }
1253   void subss(XMMRegister dst, Address        src) { Assembler::subss(dst, src); }
1254   void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1255 
1256   void ucomiss(XMMRegister dst, XMMRegister    src) { Assembler::ucomiss(dst, src); }
1257   void ucomiss(XMMRegister dst, Address        src) { Assembler::ucomiss(dst, src); }
1258   void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1259 
1260   void ucomisd(XMMRegister dst, XMMRegister    src) { Assembler::ucomisd(dst, src); }
1261   void ucomisd(XMMRegister dst, Address        src) { Assembler::ucomisd(dst, src); }
1262   void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1263 
1264   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1265   void xorpd(XMMRegister dst, XMMRegister    src);
1266   void xorpd(XMMRegister dst, Address        src) { Assembler::xorpd(dst, src); }
1267   void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1268 
1269   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1270   void xorps(XMMRegister dst, XMMRegister    src);
1271   void xorps(XMMRegister dst, Address        src) { Assembler::xorps(dst, src); }
1272   void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1273 
1274   // Shuffle Bytes
1275   void pshufb(XMMRegister dst, XMMRegister    src) { Assembler::pshufb(dst, src); }
1276   void pshufb(XMMRegister dst, Address        src) { Assembler::pshufb(dst, src); }
1277   void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1278   // AVX 3-operands instructions
1279 
1280   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vaddsd(dst, nds, src); }
1281   void vaddsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vaddsd(dst, nds, src); }
1282   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1283 
1284   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vaddss(dst, nds, src); }
1285   void vaddss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vaddss(dst, nds, src); }
1286   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1287 
1288   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1289   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1290 
1291   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len);
1292   void vpaddb(XMMRegister dst, XMMRegister nds, Address        src, int vector_len);
1293   void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1294 
1295   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1296   void vpaddw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1297 
1298   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1299   void vpaddd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1300   void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1301 
1302   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1303   void vpand(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1304   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1305 
1306   using Assembler::vpbroadcastd;
1307   void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1308 
1309   using Assembler::vpbroadcastq;
1310   void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1311 
1312   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1313 
1314   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1315   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1316 
1317   // Vector compares
1318   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1319     Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1320   }
1321   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1322 
1323   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1324     Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1325   }
1326   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1327 
1328   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1329     Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1330   }
1331   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1332 
1333   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1334     Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1335   }
1336   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1337 
1338   void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1339 
1340   // Emit comparison instruction for the specified comparison predicate.
1341   void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1342   void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1343 
1344   void vpmovzxbw(XMMRegister dst, Address     src, int vector_len);
1345   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1346 
1347   void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1348 
1349   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1350   void vpmullw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1351 
1352   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1353   void vpmulld(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1354   void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1355 
1356   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1357   void vpsubb(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1358 
1359   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1360   void vpsubw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1361 
1362   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1363   void vpsraw(XMMRegister dst, XMMRegister nds, int         shift, int vector_len);
1364 
1365   void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1366   void evpsraq(XMMRegister dst, XMMRegister nds, int         shift, int vector_len);
1367 
1368   void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1369     if (!is_varshift) {
1370       Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1371     } else {
1372       Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1373     }
1374   }
1375   void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1376     if (!is_varshift) {
1377       Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1378     } else {
1379       Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1380     }
1381   }
1382   void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1383     if (!is_varshift) {
1384       Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1385     } else {
1386       Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1387     }
1388   }
1389   void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1390     if (!is_varshift) {
1391       Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1392     } else {
1393       Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1394     }
1395   }
1396   void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1397     if (!is_varshift) {
1398       Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1399     } else {
1400       Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1401     }
1402   }
1403   void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1404     if (!is_varshift) {
1405       Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1406     } else {
1407       Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1408     }
1409   }
1410   void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1411     if (!is_varshift) {
1412       Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1413     } else {
1414       Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1415     }
1416   }
1417   void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1418     if (!is_varshift) {
1419       Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1420     } else {
1421       Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1422     }
1423   }
1424   void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1425     if (!is_varshift) {
1426       Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1427     } else {
1428       Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1429     }
1430   }
1431 
1432   void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1433   void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1434   void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1435   void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1436 
1437   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1438   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1439 
1440   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1441   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1442 
1443   void vptest(XMMRegister dst, XMMRegister src);
1444   void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1445 
1446   void punpcklbw(XMMRegister dst, XMMRegister src);
1447   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1448 
1449   void pshufd(XMMRegister dst, Address src, int mode);
1450   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1451 
1452   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1453   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1454 
1455   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1456   void vandpd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1457   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1458 
1459   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1460   void vandps(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1461   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1462 
1463   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1464 
1465   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vdivsd(dst, nds, src); }
1466   void vdivsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vdivsd(dst, nds, src); }
1467   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1468 
1469   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vdivss(dst, nds, src); }
1470   void vdivss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vdivss(dst, nds, src); }
1471   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1472 
1473   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vmulsd(dst, nds, src); }
1474   void vmulsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vmulsd(dst, nds, src); }
1475   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1476 
1477   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vmulss(dst, nds, src); }
1478   void vmulss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vmulss(dst, nds, src); }
1479   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1480 
1481   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vsubsd(dst, nds, src); }
1482   void vsubsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vsubsd(dst, nds, src); }
1483   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1484 
1485   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vsubss(dst, nds, src); }
1486   void vsubss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vsubss(dst, nds, src); }
1487   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1488 
1489   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1490   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1491 
1492   // AVX Vector instructions
1493 
1494   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1495   void vxorpd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1496   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1497 
1498   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1499   void vxorps(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1500   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1501 
1502   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1503     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1504       Assembler::vpxor(dst, nds, src, vector_len);
1505     else
1506       Assembler::vxorpd(dst, nds, src, vector_len);
1507   }
1508   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1509     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1510       Assembler::vpxor(dst, nds, src, vector_len);
1511     else
1512       Assembler::vxorpd(dst, nds, src, vector_len);
1513   }
1514   void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1515 
1516   // Simple version for AVX2 256bit vectors
1517   void vpxor(XMMRegister dst, XMMRegister src) {
1518     assert(UseAVX >= 2, "Should be at least AVX2");
1519     Assembler::vpxor(dst, dst, src, AVX_256bit);
1520   }
1521   void vpxor(XMMRegister dst, Address src) {
1522     assert(UseAVX >= 2, "Should be at least AVX2");
1523     Assembler::vpxor(dst, dst, src, AVX_256bit);
1524   }
1525 
1526   void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1527   void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1528 
1529   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1530     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1531       Assembler::vinserti32x4(dst, nds, src, imm8);
1532     } else if (UseAVX > 1) {
1533       // vinserti128 is available only in AVX2
1534       Assembler::vinserti128(dst, nds, src, imm8);
1535     } else {
1536       Assembler::vinsertf128(dst, nds, src, imm8);
1537     }
1538   }
1539 
1540   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1541     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1542       Assembler::vinserti32x4(dst, nds, src, imm8);
1543     } else if (UseAVX > 1) {
1544       // vinserti128 is available only in AVX2
1545       Assembler::vinserti128(dst, nds, src, imm8);
1546     } else {
1547       Assembler::vinsertf128(dst, nds, src, imm8);
1548     }
1549   }
1550 
1551   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1552     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1553       Assembler::vextracti32x4(dst, src, imm8);
1554     } else if (UseAVX > 1) {
1555       // vextracti128 is available only in AVX2
1556       Assembler::vextracti128(dst, src, imm8);
1557     } else {
1558       Assembler::vextractf128(dst, src, imm8);
1559     }
1560   }
1561 
1562   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1563     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1564       Assembler::vextracti32x4(dst, src, imm8);
1565     } else if (UseAVX > 1) {
1566       // vextracti128 is available only in AVX2
1567       Assembler::vextracti128(dst, src, imm8);
1568     } else {
1569       Assembler::vextractf128(dst, src, imm8);
1570     }
1571   }
1572 
1573   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1574   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1575     vinserti128(dst, dst, src, 1);
1576   }
1577   void vinserti128_high(XMMRegister dst, Address src) {
1578     vinserti128(dst, dst, src, 1);
1579   }
1580   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1581     vextracti128(dst, src, 1);
1582   }
1583   void vextracti128_high(Address dst, XMMRegister src) {
1584     vextracti128(dst, src, 1);
1585   }
1586 
1587   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1588     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1589       Assembler::vinsertf32x4(dst, dst, src, 1);
1590     } else {
1591       Assembler::vinsertf128(dst, dst, src, 1);
1592     }
1593   }
1594 
1595   void vinsertf128_high(XMMRegister dst, Address src) {
1596     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1597       Assembler::vinsertf32x4(dst, dst, src, 1);
1598     } else {
1599       Assembler::vinsertf128(dst, dst, src, 1);
1600     }
1601   }
1602 
1603   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1604     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1605       Assembler::vextractf32x4(dst, src, 1);
1606     } else {
1607       Assembler::vextractf128(dst, src, 1);
1608     }
1609   }
1610 
1611   void vextractf128_high(Address dst, XMMRegister src) {
1612     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1613       Assembler::vextractf32x4(dst, src, 1);
1614     } else {
1615       Assembler::vextractf128(dst, src, 1);
1616     }
1617   }
1618 
1619   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1620   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1621     Assembler::vinserti64x4(dst, dst, src, 1);
1622   }
1623   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1624     Assembler::vinsertf64x4(dst, dst, src, 1);
1625   }
1626   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1627     Assembler::vextracti64x4(dst, src, 1);
1628   }
1629   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1630     Assembler::vextractf64x4(dst, src, 1);
1631   }
1632   void vextractf64x4_high(Address dst, XMMRegister src) {
1633     Assembler::vextractf64x4(dst, src, 1);
1634   }
1635   void vinsertf64x4_high(XMMRegister dst, Address src) {
1636     Assembler::vinsertf64x4(dst, dst, src, 1);
1637   }
1638 
1639   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1640   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1641     vinserti128(dst, dst, src, 0);
1642   }
1643   void vinserti128_low(XMMRegister dst, Address src) {
1644     vinserti128(dst, dst, src, 0);
1645   }
1646   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1647     vextracti128(dst, src, 0);
1648   }
1649   void vextracti128_low(Address dst, XMMRegister src) {
1650     vextracti128(dst, src, 0);
1651   }
1652 
1653   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1654     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1655       Assembler::vinsertf32x4(dst, dst, src, 0);
1656     } else {
1657       Assembler::vinsertf128(dst, dst, src, 0);
1658     }
1659   }
1660 
1661   void vinsertf128_low(XMMRegister dst, Address src) {
1662     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1663       Assembler::vinsertf32x4(dst, dst, src, 0);
1664     } else {
1665       Assembler::vinsertf128(dst, dst, src, 0);
1666     }
1667   }
1668 
1669   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1670     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1671       Assembler::vextractf32x4(dst, src, 0);
1672     } else {
1673       Assembler::vextractf128(dst, src, 0);
1674     }
1675   }
1676 
1677   void vextractf128_low(Address dst, XMMRegister src) {
1678     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1679       Assembler::vextractf32x4(dst, src, 0);
1680     } else {
1681       Assembler::vextractf128(dst, src, 0);
1682     }
1683   }
1684 
1685   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1686   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1687     Assembler::vinserti64x4(dst, dst, src, 0);
1688   }
1689   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1690     Assembler::vinsertf64x4(dst, dst, src, 0);
1691   }
1692   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1693     Assembler::vextracti64x4(dst, src, 0);
1694   }
1695   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1696     Assembler::vextractf64x4(dst, src, 0);
1697   }
1698   void vextractf64x4_low(Address dst, XMMRegister src) {
1699     Assembler::vextractf64x4(dst, src, 0);
1700   }
1701   void vinsertf64x4_low(XMMRegister dst, Address src) {
1702     Assembler::vinsertf64x4(dst, dst, src, 0);
1703   }
1704 
1705   // Carry-Less Multiplication Quadword
1706   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1707     // 0x00 - multiply lower 64 bits [0:63]
1708     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1709   }
1710   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1711     // 0x11 - multiply upper 64 bits [64:127]
1712     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1713   }
1714   void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1715     // 0x10 - multiply nds[0:63] and src[64:127]
1716     Assembler::vpclmulqdq(dst, nds, src, 0x10);
1717   }
1718   void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1719     //0x01 - multiply nds[64:127] and src[0:63]
1720     Assembler::vpclmulqdq(dst, nds, src, 0x01);
1721   }
1722 
1723   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1724     // 0x00 - multiply lower 64 bits [0:63]
1725     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1726   }
1727   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1728     // 0x11 - multiply upper 64 bits [64:127]
1729     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1730   }
1731 
1732   // AVX-512 mask operations.
1733   void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1734   void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1735   void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1736   void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1737   void kortest(uint masklen, KRegister src1, KRegister src2);
1738   void ktest(uint masklen, KRegister src1, KRegister src2);
1739 
1740   void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1741   void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1742 
1743   void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1744   void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1745 
1746   void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1747   void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1748 
1749   void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1750   void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1751 
1752   void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1753   void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1754   void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1755   void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1756 
1757   void alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch);
1758   void anytrue(Register dst, uint masklen, KRegister src, KRegister kscratch);
1759 
1760   void cmov32( Condition cc, Register dst, Address  src);
1761   void cmov32( Condition cc, Register dst, Register src);
1762 
1763   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1764 
1765   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1766   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1767 
1768   void movoop(Register dst, jobject obj);
1769   void movoop(Address  dst, jobject obj, Register rscratch);
1770 
1771   void mov_metadata(Register dst, Metadata* obj);
1772   void mov_metadata(Address  dst, Metadata* obj, Register rscratch);
1773 
1774   void movptr(Register     dst, Register       src);
1775   void movptr(Register     dst, Address        src);
1776   void movptr(Register     dst, AddressLiteral src);
1777   void movptr(Register     dst, ArrayAddress   src);
1778   void movptr(Register     dst, intptr_t       src);
1779   void movptr(Address      dst, Register       src);
1780   void movptr(Address      dst, int32_t        imm);
1781   void movptr(Address      dst, intptr_t       src, Register rscratch);
1782   void movptr(ArrayAddress dst, Register       src, Register rscratch);
1783 
1784   void movptr(Register dst, RegisterOrConstant src) {
1785     if (src.is_constant()) movptr(dst, src.as_constant());
1786     else                   movptr(dst, src.as_register());
1787   }
1788 
1789 
1790   // to avoid hiding movl
1791   void mov32(Register       dst, AddressLiteral src);
1792   void mov32(AddressLiteral dst, Register        src, Register rscratch = noreg);
1793 
1794   // Import other mov() methods from the parent class or else
1795   // they will be hidden by the following overriding declaration.
1796   using Assembler::movdl;
1797   void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1798 
1799   using Assembler::movq;
1800   void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1801 
1802   // Can push value or effective address
1803   void pushptr(AddressLiteral src, Register rscratch);
1804 
1805   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1806   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1807 
1808   void pushoop(jobject obj, Register rscratch);
1809   void pushklass(Metadata* obj, Register rscratch);
1810 
1811   // sign extend as need a l to ptr sized element
1812   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1813   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1814 
1815 
1816  public:
1817   // clear memory of size 'cnt' qwords, starting at 'base';
1818   // if 'is_large' is set, do not try to produce short loop
1819   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1820 
1821   // clear memory initialization sequence for constant size;
1822   void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1823 
1824   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1825   void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1826 
1827   // Fill primitive arrays
1828   void generate_fill(BasicType t, bool aligned,
1829                      Register to, Register value, Register count,
1830                      Register rtmp, XMMRegister xtmp);
1831 
1832   void encode_iso_array(Register src, Register dst, Register len,
1833                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1834                         XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1835 
1836 #ifdef _LP64
1837   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1838   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1839                              Register y, Register y_idx, Register z,
1840                              Register carry, Register product,
1841                              Register idx, Register kdx);
1842   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1843                               Register yz_idx, Register idx,
1844                               Register carry, Register product, int offset);
1845   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1846                                     Register carry, Register carry2,
1847                                     Register idx, Register jdx,
1848                                     Register yz_idx1, Register yz_idx2,
1849                                     Register tmp, Register tmp3, Register tmp4);
1850   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1851                                Register yz_idx, Register idx, Register jdx,
1852                                Register carry, Register product,
1853                                Register carry2);
1854   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1855                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1856   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1857                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1858   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1859                             Register tmp2);
1860   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1861                        Register rdxReg, Register raxReg);
1862   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1863   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1864                        Register tmp3, Register tmp4);
1865   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1866                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1867 
1868   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1869                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1870                Register raxReg);
1871   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1872                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1873                Register raxReg);
1874   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1875                            Register result, Register tmp1, Register tmp2,
1876                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1877 #endif
1878 
1879   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1880   void update_byte_crc32(Register crc, Register val, Register table);
1881   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1882 
1883 
1884 #ifdef _LP64
1885   void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1886   void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1887                                 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1888                                 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1889 #endif // _LP64
1890 
1891   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1892   // Note on a naming convention:
1893   // Prefix w = register only used on a Westmere+ architecture
1894   // Prefix n = register only used on a Nehalem architecture
1895 #ifdef _LP64
1896   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1897                        Register tmp1, Register tmp2, Register tmp3);
1898 #else
1899   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1900                        Register tmp1, Register tmp2, Register tmp3,
1901                        XMMRegister xtmp1, XMMRegister xtmp2);
1902 #endif
1903   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1904                         Register in_out,
1905                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1906                         XMMRegister w_xtmp2,
1907                         Register tmp1,
1908                         Register n_tmp2, Register n_tmp3);
1909   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1910                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1911                        Register tmp1, Register tmp2,
1912                        Register n_tmp3);
1913   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1914                          Register in_out1, Register in_out2, Register in_out3,
1915                          Register tmp1, Register tmp2, Register tmp3,
1916                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1917                          Register tmp4, Register tmp5,
1918                          Register n_tmp6);
1919   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1920                             Register tmp1, Register tmp2, Register tmp3,
1921                             Register tmp4, Register tmp5, Register tmp6,
1922                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1923                             bool is_pclmulqdq_supported);
1924   // Fold 128-bit data chunk
1925   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1926   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1927 #ifdef _LP64
1928   // Fold 512-bit data chunk
1929   void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
1930 #endif // _LP64
1931   // Fold 8-bit data
1932   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1933   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1934 
1935   // Compress char[] array to byte[].
1936   void char_array_compress(Register src, Register dst, Register len,
1937                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1938                            XMMRegister tmp4, Register tmp5, Register result,
1939                            KRegister mask1 = knoreg, KRegister mask2 = knoreg);
1940 
1941   // Inflate byte[] array to char[].
1942   void byte_array_inflate(Register src, Register dst, Register len,
1943                           XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
1944 
1945   void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
1946                    Register length, Register temp, int vec_enc);
1947 
1948   void fill64_masked(uint shift, Register dst, int disp,
1949                          XMMRegister xmm, KRegister mask, Register length,
1950                          Register temp, bool use64byteVector = false);
1951 
1952   void fill32_masked(uint shift, Register dst, int disp,
1953                          XMMRegister xmm, KRegister mask, Register length,
1954                          Register temp);
1955 
1956   void fill32(Address dst, XMMRegister xmm);
1957 
1958   void fill32(Register dst, int disp, XMMRegister xmm);
1959 
1960   void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
1961 
1962   void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
1963 
1964 #ifdef _LP64
1965   void convert_f2i(Register dst, XMMRegister src);
1966   void convert_d2i(Register dst, XMMRegister src);
1967   void convert_f2l(Register dst, XMMRegister src);
1968   void convert_d2l(Register dst, XMMRegister src);
1969   void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
1970   void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
1971 
1972   void cache_wb(Address line);
1973   void cache_wbsync(bool is_pre);
1974 
1975 #ifdef COMPILER2_OR_JVMCI
1976   void generate_fill_avx3(BasicType type, Register to, Register value,
1977                           Register count, Register rtmp, XMMRegister xtmp);
1978 #endif // COMPILER2_OR_JVMCI
1979 
1980   OopMap* continuation_enter_setup(int& stack_slots);
1981   void fill_continuation_entry(Register reg_cont_obj, Register reg_flags);
1982   void continuation_enter_cleanup();
1983 #endif // _LP64
1984 
1985   void vallones(XMMRegister dst, int vector_len);
1986 
1987   void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
1988 
1989 };
1990 
1991 /**
1992  * class SkipIfEqual:
1993  *
1994  * Instantiating this class will result in assembly code being output that will
1995  * jump around any code emitted between the creation of the instance and it's
1996  * automatic destruction at the end of a scope block, depending on the value of
1997  * the flag passed to the constructor, which will be checked at run-time.
1998  */
1999 class SkipIfEqual {
2000  private:
2001   MacroAssembler* _masm;
2002   Label _label;
2003 
2004  public:
2005    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value, Register rscratch);
2006    ~SkipIfEqual();
2007 };
2008 
2009 #endif // CPU_X86_MACROASSEMBLER_X86_HPP