1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
26 #define CPU_X86_MACROASSEMBLER_X86_HPP
27
28 #include "asm/assembler.hpp"
29 #include "code/vmreg.inline.hpp"
30 #include "compiler/oopMap.hpp"
31 #include "utilities/macros.hpp"
32 #include "runtime/rtmLocking.hpp"
33 #include "runtime/vm_version.hpp"
34
35 // MacroAssembler extends Assembler by frequently used macros.
36 //
37 // Instructions for which a 'better' code sequence exists depending
38 // on arguments should also go in here.
39
40 class MacroAssembler: public Assembler {
41 friend class LIR_Assembler;
42 friend class Runtime1; // as_Address()
43
44 public:
45 // Support for VM calls
46 //
47 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
48 // may customize this version by overriding it for its purposes (e.g., to save/restore
49 // additional registers when doing a VM call).
50
51 virtual void call_VM_leaf_base(
52 address entry_point, // the entry point
53 int number_of_arguments // the number of arguments to pop after the call
54 );
55
56 protected:
57 // This is the base routine called by the different versions of call_VM. The interpreter
58 // may customize this version by overriding it for its purposes (e.g., to save/restore
59 // additional registers when doing a VM call).
60 //
61 // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
62 // returns the register which contains the thread upon return. If a thread register has been
63 // specified, the return value will correspond to that register. If no last_java_sp is specified
64 // (noreg) than rsp will be used instead.
65 virtual void call_VM_base( // returns the register containing the thread upon return
66 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
67 Register java_thread, // the thread if computed before ; use noreg otherwise
68 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
69 address entry_point, // the entry point
70 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
71 bool check_exceptions // whether to check for pending exceptions after return
72 );
73
74 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
75
76 // helpers for FPU flag access
77 // tmp is a temporary register, if none is available use noreg
78 void save_rax (Register tmp);
79 void restore_rax(Register tmp);
80
81 public:
82 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
83
84 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
85 // The implementation is only non-empty for the InterpreterMacroAssembler,
86 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
87 virtual void check_and_handle_popframe(Register java_thread);
88 virtual void check_and_handle_earlyret(Register java_thread);
89
90 Address as_Address(AddressLiteral adr);
91 Address as_Address(ArrayAddress adr);
92
93 // Support for NULL-checks
94 //
95 // Generates code that causes a NULL OS exception if the content of reg is NULL.
96 // If the accessed location is M[reg + offset] and the offset is known, provide the
97 // offset. No explicit code generation is needed if the offset is within a certain
98 // range (0 <= offset <= page_size).
99
100 void null_check(Register reg, int offset = -1);
101 static bool needs_explicit_null_check(intptr_t offset);
102 static bool uses_implicit_null_check(void* address);
103
104 // Required platform-specific helpers for Label::patch_instructions.
105 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
106 void pd_patch_instruction(address branch, address target, const char* file, int line) {
107 unsigned char op = branch[0];
108 assert(op == 0xE8 /* call */ ||
109 op == 0xE9 /* jmp */ ||
110 op == 0xEB /* short jmp */ ||
111 (op & 0xF0) == 0x70 /* short jcc */ ||
112 op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
113 op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
114 "Invalid opcode at patch point");
115
116 if (op == 0xEB || (op & 0xF0) == 0x70) {
117 // short offset operators (jmp and jcc)
118 char* disp = (char*) &branch[1];
119 int imm8 = target - (address) &disp[1];
120 guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
121 file == NULL ? "<NULL>" : file, line);
122 *disp = imm8;
123 } else {
124 int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
125 int imm32 = target - (address) &disp[1];
126 *disp = imm32;
127 }
128 }
129
130 // The following 4 methods return the offset of the appropriate move instruction
131
132 // Support for fast byte/short loading with zero extension (depending on particular CPU)
133 int load_unsigned_byte(Register dst, Address src);
134 int load_unsigned_short(Register dst, Address src);
135
136 // Support for fast byte/short loading with sign extension (depending on particular CPU)
137 int load_signed_byte(Register dst, Address src);
138 int load_signed_short(Register dst, Address src);
139
140 // Support for sign-extension (hi:lo = extend_sign(lo))
141 void extend_sign(Register hi, Register lo);
142
143 // Load and store values by size and signed-ness
144 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
145 void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
146
147 // Support for inc/dec with optimal instruction selection depending on value
148
149 void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
150 void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
151
152 void decrementl(Address dst, int value = 1);
153 void decrementl(Register reg, int value = 1);
154
155 void decrementq(Register reg, int value = 1);
156 void decrementq(Address dst, int value = 1);
157
158 void incrementl(Address dst, int value = 1);
159 void incrementl(Register reg, int value = 1);
160
161 void incrementq(Register reg, int value = 1);
162 void incrementq(Address dst, int value = 1);
163
164 // Support optimal SSE move instructions.
165 void movflt(XMMRegister dst, XMMRegister src) {
166 if (dst-> encoding() == src->encoding()) return;
167 if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
168 else { movss (dst, src); return; }
169 }
170 void movflt(XMMRegister dst, Address src) { movss(dst, src); }
171 void movflt(XMMRegister dst, AddressLiteral src);
172 void movflt(Address dst, XMMRegister src) { movss(dst, src); }
173
174 // Move with zero extension
175 void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
176
177 void movdbl(XMMRegister dst, XMMRegister src) {
178 if (dst-> encoding() == src->encoding()) return;
179 if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
180 else { movsd (dst, src); return; }
181 }
182
183 void movdbl(XMMRegister dst, AddressLiteral src);
184
185 void movdbl(XMMRegister dst, Address src) {
186 if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
187 else { movlpd(dst, src); return; }
188 }
189 void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
190
191 void incrementl(AddressLiteral dst);
192 void incrementl(ArrayAddress dst);
193
194 void incrementq(AddressLiteral dst);
195
196 // Alignment
197 void align32();
198 void align64();
199 void align(int modulus);
200 void align(int modulus, int target);
201
202 // A 5 byte nop that is safe for patching (see patch_verified_entry)
203 void fat_nop();
204
205 // Stack frame creation/removal
206 void enter();
207 void leave();
208
209 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
210 // The pointer will be loaded into the thread register.
211 void get_thread(Register thread);
212
213 #ifdef _LP64
214 // Support for argument shuffling
215
216 void move32_64(VMRegPair src, VMRegPair dst);
217 void long_move(VMRegPair src, VMRegPair dst);
218 void float_move(VMRegPair src, VMRegPair dst);
219 void double_move(VMRegPair src, VMRegPair dst);
220 void move_ptr(VMRegPair src, VMRegPair dst);
221 void object_move(OopMap* map,
222 int oop_handle_offset,
223 int framesize_in_slots,
224 VMRegPair src,
225 VMRegPair dst,
226 bool is_receiver,
227 int* receiver_offset);
228 #endif // _LP64
229
230 // Support for VM calls
231 //
232 // It is imperative that all calls into the VM are handled via the call_VM macros.
233 // They make sure that the stack linkage is setup correctly. call_VM's correspond
234 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
235
236
237 void call_VM(Register oop_result,
238 address entry_point,
239 bool check_exceptions = true);
240 void call_VM(Register oop_result,
241 address entry_point,
242 Register arg_1,
243 bool check_exceptions = true);
244 void call_VM(Register oop_result,
245 address entry_point,
246 Register arg_1, Register arg_2,
247 bool check_exceptions = true);
248 void call_VM(Register oop_result,
249 address entry_point,
250 Register arg_1, Register arg_2, Register arg_3,
251 bool check_exceptions = true);
252
253 // Overloadings with last_Java_sp
254 void call_VM(Register oop_result,
255 Register last_java_sp,
256 address entry_point,
257 int number_of_arguments = 0,
258 bool check_exceptions = true);
259 void call_VM(Register oop_result,
260 Register last_java_sp,
261 address entry_point,
262 Register arg_1, bool
263 check_exceptions = true);
264 void call_VM(Register oop_result,
265 Register last_java_sp,
266 address entry_point,
267 Register arg_1, Register arg_2,
268 bool check_exceptions = true);
269 void call_VM(Register oop_result,
270 Register last_java_sp,
271 address entry_point,
272 Register arg_1, Register arg_2, Register arg_3,
273 bool check_exceptions = true);
274
275 void get_vm_result (Register oop_result, Register thread);
276 void get_vm_result_2(Register metadata_result, Register thread);
277
278 // These always tightly bind to MacroAssembler::call_VM_base
279 // bypassing the virtual implementation
280 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
281 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
282 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
283 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
284 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
285
286 void call_VM_leaf0(address entry_point);
287 void call_VM_leaf(address entry_point,
288 int number_of_arguments = 0);
289 void call_VM_leaf(address entry_point,
290 Register arg_1);
291 void call_VM_leaf(address entry_point,
292 Register arg_1, Register arg_2);
293 void call_VM_leaf(address entry_point,
294 Register arg_1, Register arg_2, Register arg_3);
295
296 // These always tightly bind to MacroAssembler::call_VM_leaf_base
297 // bypassing the virtual implementation
298 void super_call_VM_leaf(address entry_point);
299 void super_call_VM_leaf(address entry_point, Register arg_1);
300 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
301 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
302 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
303
304 // last Java Frame (fills frame anchor)
305 void set_last_Java_frame(Register thread,
306 Register last_java_sp,
307 Register last_java_fp,
308 address last_java_pc);
309
310 // thread in the default location (r15_thread on 64bit)
311 void set_last_Java_frame(Register last_java_sp,
312 Register last_java_fp,
313 address last_java_pc);
314
315 void reset_last_Java_frame(Register thread, bool clear_fp);
316
317 // thread in the default location (r15_thread on 64bit)
318 void reset_last_Java_frame(bool clear_fp);
319
320 // jobjects
321 void clear_jweak_tag(Register possibly_jweak);
322 void resolve_jobject(Register value, Register thread, Register tmp);
323
324 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
325 void c2bool(Register x);
326
327 // C++ bool manipulation
328
329 void movbool(Register dst, Address src);
330 void movbool(Address dst, bool boolconst);
331 void movbool(Address dst, Register src);
332 void testbool(Register dst);
333
334 void resolve_oop_handle(Register result, Register tmp = rscratch2);
335 void resolve_weak_handle(Register result, Register tmp);
336 void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
337 void load_method_holder_cld(Register rresult, Register rmethod);
338
339 void load_method_holder(Register holder, Register method);
340
341 // oop manipulations
342 void load_klass(Register dst, Register src, Register tmp, bool null_check_src = false);
343 void store_klass(Register dst, Register src, Register tmp);
344
345 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
346 Register tmp1, Register thread_tmp);
347 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
348 Register tmp1, Register tmp2);
349
350 void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
351 Register thread_tmp = noreg, DecoratorSet decorators = 0);
352 void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
353 Register thread_tmp = noreg, DecoratorSet decorators = 0);
354 void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
355 Register tmp2 = noreg, DecoratorSet decorators = 0);
356
357 // Used for storing NULL. All other oop constants should be
358 // stored using routines that take a jobject.
359 void store_heap_oop_null(Address dst);
360
361 #ifdef _LP64
362 void store_klass_gap(Register dst, Register src);
363
364 // This dummy is to prevent a call to store_heap_oop from
365 // converting a zero (like NULL) into a Register by giving
366 // the compiler two choices it can't resolve
367
368 void store_heap_oop(Address dst, void* dummy);
369
370 void encode_heap_oop(Register r);
371 void decode_heap_oop(Register r);
372 void encode_heap_oop_not_null(Register r);
373 void decode_heap_oop_not_null(Register r);
374 void encode_heap_oop_not_null(Register dst, Register src);
375 void decode_heap_oop_not_null(Register dst, Register src);
376
377 void set_narrow_oop(Register dst, jobject obj);
378 void set_narrow_oop(Address dst, jobject obj);
379 void cmp_narrow_oop(Register dst, jobject obj);
380 void cmp_narrow_oop(Address dst, jobject obj);
381
382 void encode_klass_not_null(Register r, Register tmp);
383 void decode_klass_not_null(Register r, Register tmp);
384 void encode_and_move_klass_not_null(Register dst, Register src);
385 void decode_and_move_klass_not_null(Register dst, Register src);
386 void set_narrow_klass(Register dst, Klass* k);
387 void set_narrow_klass(Address dst, Klass* k);
388 void cmp_narrow_klass(Register dst, Klass* k);
389 void cmp_narrow_klass(Address dst, Klass* k);
390
391 // if heap base register is used - reinit it with the correct value
392 void reinit_heapbase();
393
394 DEBUG_ONLY(void verify_heapbase(const char* msg);)
395
396 #endif // _LP64
397
398 // Int division/remainder for Java
399 // (as idivl, but checks for special case as described in JVM spec.)
400 // returns idivl instruction offset for implicit exception handling
401 int corrected_idivl(Register reg);
402
403 // Long division/remainder for Java
404 // (as idivq, but checks for special case as described in JVM spec.)
405 // returns idivq instruction offset for implicit exception handling
406 int corrected_idivq(Register reg);
407
408 void int3();
409
410 // Long operation macros for a 32bit cpu
411 // Long negation for Java
412 void lneg(Register hi, Register lo);
413
414 // Long multiplication for Java
415 // (destroys contents of eax, ebx, ecx and edx)
416 void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
417
418 // Long shifts for Java
419 // (semantics as described in JVM spec.)
420 void lshl(Register hi, Register lo); // hi:lo << (rcx & 0x3f)
421 void lshr(Register hi, Register lo, bool sign_extension = false); // hi:lo >> (rcx & 0x3f)
422
423 // Long compare for Java
424 // (semantics as described in JVM spec.)
425 void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
426
427
428 // misc
429
430 // Sign extension
431 void sign_extend_short(Register reg);
432 void sign_extend_byte(Register reg);
433
434 // Division by power of 2, rounding towards 0
435 void division_with_shift(Register reg, int shift_value);
436
437 #ifndef _LP64
438 // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
439 //
440 // CF (corresponds to C0) if x < y
441 // PF (corresponds to C2) if unordered
442 // ZF (corresponds to C3) if x = y
443 //
444 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
445 // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
446 void fcmp(Register tmp);
447 // Variant of the above which allows y to be further down the stack
448 // and which only pops x and y if specified. If pop_right is
449 // specified then pop_left must also be specified.
450 void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
451
452 // Floating-point comparison for Java
453 // Compares the top-most stack entries on the FPU stack and stores the result in dst.
454 // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
455 // (semantics as described in JVM spec.)
456 void fcmp2int(Register dst, bool unordered_is_less);
457 // Variant of the above which allows y to be further down the stack
458 // and which only pops x and y if specified. If pop_right is
459 // specified then pop_left must also be specified.
460 void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
461
462 // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
463 // tmp is a temporary register, if none is available use noreg
464 void fremr(Register tmp);
465
466 // only if +VerifyFPU
467 void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
468 #endif // !LP64
469
470 // dst = c = a * b + c
471 void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
472 void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
473
474 void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
475 void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
476 void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
477 void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
478
479
480 // same as fcmp2int, but using SSE2
481 void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
482 void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
483
484 // branch to L if FPU flag C2 is set/not set
485 // tmp is a temporary register, if none is available use noreg
486 void jC2 (Register tmp, Label& L);
487 void jnC2(Register tmp, Label& L);
488
489 // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
490 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
491 void load_float(Address src);
492
493 // Store float value to 'address'. If UseSSE >= 1, the value is stored
494 // from register xmm0. Otherwise, the value is stored from the FPU stack.
495 void store_float(Address dst);
496
497 // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
498 // register xmm0. Otherwise, the value is loaded onto the FPU stack.
499 void load_double(Address src);
500
501 // Store double value to 'address'. If UseSSE >= 2, the value is stored
502 // from register xmm0. Otherwise, the value is stored from the FPU stack.
503 void store_double(Address dst);
504
505 #ifndef _LP64
506 // Pop ST (ffree & fincstp combined)
507 void fpop();
508
509 void empty_FPU_stack();
510 #endif // !_LP64
511
512 void push_IU_state();
513 void pop_IU_state();
514
515 void push_FPU_state();
516 void pop_FPU_state();
517
518 void push_CPU_state();
519 void pop_CPU_state();
520
521 // Round up to a power of two
522 void round_to(Register reg, int modulus);
523
524 // Callee saved registers handling
525 void push_callee_saved_registers();
526 void pop_callee_saved_registers();
527
528 // allocation
529 void eden_allocate(
530 Register thread, // Current thread
531 Register obj, // result: pointer to object after successful allocation
532 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
533 int con_size_in_bytes, // object size in bytes if known at compile time
534 Register t1, // temp register
535 Label& slow_case // continuation point if fast allocation fails
536 );
537 void tlab_allocate(
538 Register thread, // Current thread
539 Register obj, // result: pointer to object after successful allocation
540 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
541 int con_size_in_bytes, // object size in bytes if known at compile time
542 Register t1, // temp register
543 Register t2, // temp register
544 Label& slow_case // continuation point if fast allocation fails
545 );
546 void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
547
548 // interface method calling
549 void lookup_interface_method(Register recv_klass,
550 Register intf_klass,
551 RegisterOrConstant itable_index,
552 Register method_result,
553 Register scan_temp,
554 Label& no_such_interface,
555 bool return_method = true);
556
557 // virtual method calling
558 void lookup_virtual_method(Register recv_klass,
559 RegisterOrConstant vtable_index,
560 Register method_result);
561
562 // Test sub_klass against super_klass, with fast and slow paths.
563
564 // The fast path produces a tri-state answer: yes / no / maybe-slow.
565 // One of the three labels can be NULL, meaning take the fall-through.
566 // If super_check_offset is -1, the value is loaded up from super_klass.
567 // No registers are killed, except temp_reg.
568 void check_klass_subtype_fast_path(Register sub_klass,
569 Register super_klass,
570 Register temp_reg,
571 Label* L_success,
572 Label* L_failure,
573 Label* L_slow_path,
574 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
575
576 // The rest of the type check; must be wired to a corresponding fast path.
577 // It does not repeat the fast path logic, so don't use it standalone.
578 // The temp_reg and temp2_reg can be noreg, if no temps are available.
579 // Updates the sub's secondary super cache as necessary.
580 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
581 void check_klass_subtype_slow_path(Register sub_klass,
582 Register super_klass,
583 Register temp_reg,
584 Register temp2_reg,
585 Label* L_success,
586 Label* L_failure,
587 bool set_cond_codes = false);
588
589 // Simplified, combined version, good for typical uses.
590 // Falls through on failure.
591 void check_klass_subtype(Register sub_klass,
592 Register super_klass,
593 Register temp_reg,
594 Label& L_success);
595
596 void clinit_barrier(Register klass,
597 Register thread,
598 Label* L_fast_path = NULL,
599 Label* L_slow_path = NULL);
600
601 // method handles (JSR 292)
602 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
603
604 // Debugging
605
606 // only if +VerifyOops
607 void _verify_oop(Register reg, const char* s, const char* file, int line);
608 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
609
610 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
611 if (VerifyOops) {
612 _verify_oop(reg, s, file, line);
613 }
614 }
615 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
616 if (VerifyOops) {
617 _verify_oop_addr(reg, s, file, line);
618 }
619 }
620
621 // TODO: verify method and klass metadata (compare against vptr?)
622 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
623 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
624
625 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
626 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
627 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
628 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
629 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
630
631 // Verify or restore cpu control state after JNI call
632 void restore_cpu_control_state_after_jni();
633
634 // prints msg, dumps registers and stops execution
635 void stop(const char* msg);
636
637 // prints msg and continues
638 void warn(const char* msg);
639
640 // dumps registers and other state
641 void print_state();
642
643 static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
644 static void debug64(char* msg, int64_t pc, int64_t regs[]);
645 static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
646 static void print_state64(int64_t pc, int64_t regs[]);
647
648 void os_breakpoint();
649
650 void untested() { stop("untested"); }
651
652 void unimplemented(const char* what = "");
653
654 void should_not_reach_here() { stop("should not reach here"); }
655
656 void print_CPU_state();
657
658 // Stack overflow checking
659 void bang_stack_with_offset(int offset) {
660 // stack grows down, caller passes positive offset
661 assert(offset > 0, "must bang with negative offset");
662 movl(Address(rsp, (-offset)), rax);
663 }
664
665 // Writes to stack successive pages until offset reached to check for
666 // stack overflow + shadow pages. Also, clobbers tmp
667 void bang_stack_size(Register size, Register tmp);
668
669 // Check for reserved stack access in method being exited (for JIT)
670 void reserved_stack_check();
671
672 void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
673
674 void verify_tlab();
675
676 Condition negate_condition(Condition cond);
677
678 // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
679 // operands. In general the names are modified to avoid hiding the instruction in Assembler
680 // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
681 // here in MacroAssembler. The major exception to this rule is call
682
683 // Arithmetics
684
685
686 void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
687 void addptr(Address dst, Register src);
688
689 void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
690 void addptr(Register dst, int32_t src);
691 void addptr(Register dst, Register src);
692 void addptr(Register dst, RegisterOrConstant src) {
693 if (src.is_constant()) addptr(dst, (int) src.as_constant());
694 else addptr(dst, src.as_register());
695 }
696
697 void andptr(Register dst, int32_t src);
698 void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
699
700 void cmp8(AddressLiteral src1, int imm);
701
702 // renamed to drag out the casting of address to int32_t/intptr_t
703 void cmp32(Register src1, int32_t imm);
704
705 void cmp32(AddressLiteral src1, int32_t imm);
706 // compare reg - mem, or reg - &mem
707 void cmp32(Register src1, AddressLiteral src2);
708
709 void cmp32(Register src1, Address src2);
710
711 #ifndef _LP64
712 void cmpklass(Address dst, Metadata* obj);
713 void cmpklass(Register dst, Metadata* obj);
714 void cmpoop(Address dst, jobject obj);
715 #endif // _LP64
716
717 void cmpoop(Register src1, Register src2);
718 void cmpoop(Register src1, Address src2);
719 void cmpoop(Register dst, jobject obj);
720
721 // NOTE src2 must be the lval. This is NOT an mem-mem compare
722 void cmpptr(Address src1, AddressLiteral src2);
723
724 void cmpptr(Register src1, AddressLiteral src2);
725
726 void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
727 void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
728 // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
729
730 void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
731 void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
732
733 // cmp64 to avoild hiding cmpq
734 void cmp64(Register src1, AddressLiteral src);
735
736 void cmpxchgptr(Register reg, Address adr);
737
738 void locked_cmpxchgptr(Register reg, AddressLiteral adr);
739
740
741 void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
742 void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
743
744
745 void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
746
747 void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
748
749 void shlptr(Register dst, int32_t shift);
750 void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
751
752 void shrptr(Register dst, int32_t shift);
753 void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
754
755 void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
756 void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
757
758 void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
759
760 void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
761 void subptr(Register dst, int32_t src);
762 // Force generation of a 4 byte immediate value even if it fits into 8bit
763 void subptr_imm32(Register dst, int32_t src);
764 void subptr(Register dst, Register src);
765 void subptr(Register dst, RegisterOrConstant src) {
766 if (src.is_constant()) subptr(dst, (int) src.as_constant());
767 else subptr(dst, src.as_register());
768 }
769
770 void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
771 void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
772
773 void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
774 void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
775
776 void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
777
778
779
780 // Helper functions for statistics gathering.
781 // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
782 void cond_inc32(Condition cond, AddressLiteral counter_addr);
783 // Unconditional atomic increment.
784 void atomic_incl(Address counter_addr);
785 void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
786 #ifdef _LP64
787 void atomic_incq(Address counter_addr);
788 void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
789 #endif
790 void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
791 void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
792
793 void lea(Register dst, AddressLiteral adr);
794 void lea(Address dst, AddressLiteral adr);
795 void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
796
797 void leal32(Register dst, Address src) { leal(dst, src); }
798
799 // Import other testl() methods from the parent class or else
800 // they will be hidden by the following overriding declaration.
801 using Assembler::testl;
802 void testl(Register dst, AddressLiteral src);
803
804 void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
805 void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
806 void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
807 void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
808
809 void testptr(Register src, int32_t imm32) { LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
810 void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
811 void testptr(Register src1, Register src2);
812
813 void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
814 void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
815
816 // Calls
817
818 void call(Label& L, relocInfo::relocType rtype);
819 void call(Register entry);
820 void call(Address addr) { Assembler::call(addr); }
821
822 // NOTE: this call transfers to the effective address of entry NOT
823 // the address contained by entry. This is because this is more natural
824 // for jumps/calls.
825 void call(AddressLiteral entry);
826
827 // Emit the CompiledIC call idiom
828 void ic_call(address entry, jint method_index = 0);
829
830 // Jumps
831
832 // NOTE: these jumps tranfer to the effective address of dst NOT
833 // the address contained by dst. This is because this is more natural
834 // for jumps/calls.
835 void jump(AddressLiteral dst);
836 void jump_cc(Condition cc, AddressLiteral dst);
837
838 // 32bit can do a case table jump in one instruction but we no longer allow the base
839 // to be installed in the Address class. This jump will tranfers to the address
840 // contained in the location described by entry (not the address of entry)
841 void jump(ArrayAddress entry);
842
843 // Floating
844
845 void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
846 void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
847 void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
848
849 void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
850 void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
851 void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
852
853 void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
854 void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
855 void comiss(XMMRegister dst, AddressLiteral src);
856
857 void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
858 void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
859 void comisd(XMMRegister dst, AddressLiteral src);
860
861 #ifndef _LP64
862 void fadd_s(Address src) { Assembler::fadd_s(src); }
863 void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
864
865 void fldcw(Address src) { Assembler::fldcw(src); }
866 void fldcw(AddressLiteral src);
867
868 void fld_s(int index) { Assembler::fld_s(index); }
869 void fld_s(Address src) { Assembler::fld_s(src); }
870 void fld_s(AddressLiteral src);
871
872 void fld_d(Address src) { Assembler::fld_d(src); }
873 void fld_d(AddressLiteral src);
874
875 void fmul_s(Address src) { Assembler::fmul_s(src); }
876 void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
877 #endif // _LP64
878
879 void fld_x(Address src) { Assembler::fld_x(src); }
880 void fld_x(AddressLiteral src);
881
882 void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
883 void ldmxcsr(AddressLiteral src);
884
885 #ifdef _LP64
886 private:
887 void sha256_AVX2_one_round_compute(
888 Register reg_old_h,
889 Register reg_a,
890 Register reg_b,
891 Register reg_c,
892 Register reg_d,
893 Register reg_e,
894 Register reg_f,
895 Register reg_g,
896 Register reg_h,
897 int iter);
898 void sha256_AVX2_four_rounds_compute_first(int start);
899 void sha256_AVX2_four_rounds_compute_last(int start);
900 void sha256_AVX2_one_round_and_sched(
901 XMMRegister xmm_0, /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
902 XMMRegister xmm_1, /* ymm5 */ /* full cycle is 16 iterations */
903 XMMRegister xmm_2, /* ymm6 */
904 XMMRegister xmm_3, /* ymm7 */
905 Register reg_a, /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
906 Register reg_b, /* ebx */ /* full cycle is 8 iterations */
907 Register reg_c, /* edi */
908 Register reg_d, /* esi */
909 Register reg_e, /* r8d */
910 Register reg_f, /* r9d */
911 Register reg_g, /* r10d */
912 Register reg_h, /* r11d */
913 int iter);
914
915 void addm(int disp, Register r1, Register r2);
916 void gfmul(XMMRegister tmp0, XMMRegister t);
917 void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
918 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
919 void generateHtbl_one_block(Register htbl);
920 void generateHtbl_eight_blocks(Register htbl);
921 public:
922 void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
923 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
924 Register buf, Register state, Register ofs, Register limit, Register rsp,
925 bool multi_block, XMMRegister shuf_mask);
926 void avx_ghash(Register state, Register htbl, Register data, Register blocks);
927 #endif
928
929 #ifdef _LP64
930 private:
931 void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
932 Register e, Register f, Register g, Register h, int iteration);
933
934 void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
935 Register a, Register b, Register c, Register d, Register e, Register f,
936 Register g, Register h, int iteration);
937
938 void addmq(int disp, Register r1, Register r2);
939 public:
940 void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
941 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
942 Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
943 XMMRegister shuf_mask);
944 private:
945 void roundEnc(XMMRegister key, int rnum);
946 void lastroundEnc(XMMRegister key, int rnum);
947 void roundDec(XMMRegister key, int rnum);
948 void lastroundDec(XMMRegister key, int rnum);
949 void ev_load_key(XMMRegister xmmdst, Register key, int offset, XMMRegister xmm_shuf_mask);
950 void gfmul_avx512(XMMRegister ghash, XMMRegister hkey);
951 void generateHtbl_48_block_zmm(Register htbl, Register avx512_subkeyHtbl);
952 void ghash16_encrypt16_parallel(Register key, Register subkeyHtbl, XMMRegister ctr_blockx,
953 XMMRegister aad_hashx, Register in, Register out, Register data, Register pos, bool reduction,
954 XMMRegister addmask, bool no_ghash_input, Register rounds, Register ghash_pos,
955 bool final_reduction, int index, XMMRegister counter_inc_mask);
956 public:
957 void aesecb_encrypt(Register source_addr, Register dest_addr, Register key, Register len);
958 void aesecb_decrypt(Register source_addr, Register dest_addr, Register key, Register len);
959 void aesctr_encrypt(Register src_addr, Register dest_addr, Register key, Register counter,
960 Register len_reg, Register used, Register used_addr, Register saved_encCounter_start);
961 void aesgcm_encrypt(Register in, Register len, Register ct, Register out, Register key,
962 Register state, Register subkeyHtbl, Register avx512_subkeyHtbl, Register counter);
963
964 #endif
965
966 void fast_md5(Register buf, Address state, Address ofs, Address limit,
967 bool multi_block);
968
969 void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
970 XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
971 Register buf, Register state, Register ofs, Register limit, Register rsp,
972 bool multi_block);
973
974 #ifdef _LP64
975 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
976 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
977 Register buf, Register state, Register ofs, Register limit, Register rsp,
978 bool multi_block, XMMRegister shuf_mask);
979 #else
980 void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
981 XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
982 Register buf, Register state, Register ofs, Register limit, Register rsp,
983 bool multi_block);
984 #endif
985
986 void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
987 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
988 Register rax, Register rcx, Register rdx, Register tmp);
989
990 #ifdef _LP64
991 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
992 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
993 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
994
995 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
996 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
997 Register rax, Register rcx, Register rdx, Register r11);
998
999 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1000 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1001 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1002
1003 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1004 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1005 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1006 Register tmp3, Register tmp4);
1007
1008 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1009 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1010 Register rax, Register rcx, Register rdx, Register tmp1,
1011 Register tmp2, Register tmp3, Register tmp4);
1012 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1013 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1014 Register rax, Register rcx, Register rdx, Register tmp1,
1015 Register tmp2, Register tmp3, Register tmp4);
1016 #else
1017 void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1018 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1019 Register rax, Register rcx, Register rdx, Register tmp1);
1020
1021 void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023 Register rax, Register rcx, Register rdx, Register tmp);
1024
1025 void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1026 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1027 Register rdx, Register tmp);
1028
1029 void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1030 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1031 Register rax, Register rbx, Register rdx);
1032
1033 void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1034 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1035 Register rax, Register rcx, Register rdx, Register tmp);
1036
1037 void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1038 Register edx, Register ebx, Register esi, Register edi,
1039 Register ebp, Register esp);
1040
1041 void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1042 Register esi, Register edi, Register ebp, Register esp);
1043
1044 void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1045 Register edx, Register ebx, Register esi, Register edi,
1046 Register ebp, Register esp);
1047
1048 void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1049 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1050 Register rax, Register rcx, Register rdx, Register tmp);
1051 #endif
1052
1053 private:
1054
1055 // these are private because users should be doing movflt/movdbl
1056
1057 void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1058 void movss(Address dst, XMMRegister src) { Assembler::movss(dst, src); }
1059 void movss(XMMRegister dst, Address src) { Assembler::movss(dst, src); }
1060 void movss(XMMRegister dst, AddressLiteral src);
1061
1062 void movlpd(XMMRegister dst, Address src) {Assembler::movlpd(dst, src); }
1063 void movlpd(XMMRegister dst, AddressLiteral src);
1064
1065 public:
1066
1067 void addsd(XMMRegister dst, XMMRegister src) { Assembler::addsd(dst, src); }
1068 void addsd(XMMRegister dst, Address src) { Assembler::addsd(dst, src); }
1069 void addsd(XMMRegister dst, AddressLiteral src);
1070
1071 void addss(XMMRegister dst, XMMRegister src) { Assembler::addss(dst, src); }
1072 void addss(XMMRegister dst, Address src) { Assembler::addss(dst, src); }
1073 void addss(XMMRegister dst, AddressLiteral src);
1074
1075 void addpd(XMMRegister dst, XMMRegister src) { Assembler::addpd(dst, src); }
1076 void addpd(XMMRegister dst, Address src) { Assembler::addpd(dst, src); }
1077 void addpd(XMMRegister dst, AddressLiteral src);
1078
1079 void divsd(XMMRegister dst, XMMRegister src) { Assembler::divsd(dst, src); }
1080 void divsd(XMMRegister dst, Address src) { Assembler::divsd(dst, src); }
1081 void divsd(XMMRegister dst, AddressLiteral src);
1082
1083 void divss(XMMRegister dst, XMMRegister src) { Assembler::divss(dst, src); }
1084 void divss(XMMRegister dst, Address src) { Assembler::divss(dst, src); }
1085 void divss(XMMRegister dst, AddressLiteral src);
1086
1087 // Move Unaligned Double Quadword
1088 void movdqu(Address dst, XMMRegister src);
1089 void movdqu(XMMRegister dst, Address src);
1090 void movdqu(XMMRegister dst, XMMRegister src);
1091 void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1092
1093 void kmovwl(KRegister dst, Register src) { Assembler::kmovwl(dst, src); }
1094 void kmovwl(Register dst, KRegister src) { Assembler::kmovwl(dst, src); }
1095 void kmovwl(KRegister dst, Address src) { Assembler::kmovwl(dst, src); }
1096 void kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1097 void kmovwl(Address dst, KRegister src) { Assembler::kmovwl(dst, src); }
1098 void kmovwl(KRegister dst, KRegister src) { Assembler::kmovwl(dst, src); }
1099
1100 void kmovql(KRegister dst, KRegister src) { Assembler::kmovql(dst, src); }
1101 void kmovql(KRegister dst, Register src) { Assembler::kmovql(dst, src); }
1102 void kmovql(Register dst, KRegister src) { Assembler::kmovql(dst, src); }
1103 void kmovql(KRegister dst, Address src) { Assembler::kmovql(dst, src); }
1104 void kmovql(Address dst, KRegister src) { Assembler::kmovql(dst, src); }
1105 void kmovql(KRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1106
1107 // Safe move operation, lowers down to 16bit moves for targets supporting
1108 // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1109 void kmov(Address dst, KRegister src);
1110 void kmov(KRegister dst, Address src);
1111 void kmov(KRegister dst, KRegister src);
1112 void kmov(Register dst, KRegister src);
1113 void kmov(KRegister dst, Register src);
1114
1115 // AVX Unaligned forms
1116 void vmovdqu(Address dst, XMMRegister src);
1117 void vmovdqu(XMMRegister dst, Address src);
1118 void vmovdqu(XMMRegister dst, XMMRegister src);
1119 void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1120
1121 // AVX512 Unaligned
1122 void evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len);
1123 void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len);
1124
1125 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1126 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1127 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, src, merge, vector_len); }
1128 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1129 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1130 void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1131
1132 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1133 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1134 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, src, merge, vector_len); }
1135 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1136 void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1137
1138 void evmovdqul(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1139 void evmovdqul(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1140 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1141 if (dst->encoding() == src->encoding()) return;
1142 Assembler::evmovdqul(dst, src, vector_len);
1143 }
1144 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1145 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1146 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1147 if (dst->encoding() == src->encoding() && mask == k0) return;
1148 Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1149 }
1150 void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1151
1152 void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1153 void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1154 void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1155 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1156 if (dst->encoding() == src->encoding()) return;
1157 Assembler::evmovdquq(dst, src, vector_len);
1158 }
1159 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1160 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1161 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1162 if (dst->encoding() == src->encoding() && mask == k0) return;
1163 Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1164 }
1165 void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1166
1167 // Move Aligned Double Quadword
1168 void movdqa(XMMRegister dst, Address src) { Assembler::movdqa(dst, src); }
1169 void movdqa(XMMRegister dst, XMMRegister src) { Assembler::movdqa(dst, src); }
1170 void movdqa(XMMRegister dst, AddressLiteral src);
1171
1172 void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1173 void movsd(Address dst, XMMRegister src) { Assembler::movsd(dst, src); }
1174 void movsd(XMMRegister dst, Address src) { Assembler::movsd(dst, src); }
1175 void movsd(XMMRegister dst, AddressLiteral src);
1176
1177 void mulpd(XMMRegister dst, XMMRegister src) { Assembler::mulpd(dst, src); }
1178 void mulpd(XMMRegister dst, Address src) { Assembler::mulpd(dst, src); }
1179 void mulpd(XMMRegister dst, AddressLiteral src);
1180
1181 void mulsd(XMMRegister dst, XMMRegister src) { Assembler::mulsd(dst, src); }
1182 void mulsd(XMMRegister dst, Address src) { Assembler::mulsd(dst, src); }
1183 void mulsd(XMMRegister dst, AddressLiteral src);
1184
1185 void mulss(XMMRegister dst, XMMRegister src) { Assembler::mulss(dst, src); }
1186 void mulss(XMMRegister dst, Address src) { Assembler::mulss(dst, src); }
1187 void mulss(XMMRegister dst, AddressLiteral src);
1188
1189 // Carry-Less Multiplication Quadword
1190 void pclmulldq(XMMRegister dst, XMMRegister src) {
1191 // 0x00 - multiply lower 64 bits [0:63]
1192 Assembler::pclmulqdq(dst, src, 0x00);
1193 }
1194 void pclmulhdq(XMMRegister dst, XMMRegister src) {
1195 // 0x11 - multiply upper 64 bits [64:127]
1196 Assembler::pclmulqdq(dst, src, 0x11);
1197 }
1198
1199 void pcmpeqb(XMMRegister dst, XMMRegister src);
1200 void pcmpeqw(XMMRegister dst, XMMRegister src);
1201
1202 void pcmpestri(XMMRegister dst, Address src, int imm8);
1203 void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1204
1205 void pmovzxbw(XMMRegister dst, XMMRegister src);
1206 void pmovzxbw(XMMRegister dst, Address src);
1207
1208 void pmovmskb(Register dst, XMMRegister src);
1209
1210 void ptest(XMMRegister dst, XMMRegister src);
1211
1212 void sqrtsd(XMMRegister dst, XMMRegister src) { Assembler::sqrtsd(dst, src); }
1213 void sqrtsd(XMMRegister dst, Address src) { Assembler::sqrtsd(dst, src); }
1214 void sqrtsd(XMMRegister dst, AddressLiteral src);
1215
1216 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1217 void roundsd(XMMRegister dst, Address src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1218 void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg);
1219
1220 void sqrtss(XMMRegister dst, XMMRegister src) { Assembler::sqrtss(dst, src); }
1221 void sqrtss(XMMRegister dst, Address src) { Assembler::sqrtss(dst, src); }
1222 void sqrtss(XMMRegister dst, AddressLiteral src);
1223
1224 void subsd(XMMRegister dst, XMMRegister src) { Assembler::subsd(dst, src); }
1225 void subsd(XMMRegister dst, Address src) { Assembler::subsd(dst, src); }
1226 void subsd(XMMRegister dst, AddressLiteral src);
1227
1228 void subss(XMMRegister dst, XMMRegister src) { Assembler::subss(dst, src); }
1229 void subss(XMMRegister dst, Address src) { Assembler::subss(dst, src); }
1230 void subss(XMMRegister dst, AddressLiteral src);
1231
1232 void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1233 void ucomiss(XMMRegister dst, Address src) { Assembler::ucomiss(dst, src); }
1234 void ucomiss(XMMRegister dst, AddressLiteral src);
1235
1236 void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1237 void ucomisd(XMMRegister dst, Address src) { Assembler::ucomisd(dst, src); }
1238 void ucomisd(XMMRegister dst, AddressLiteral src);
1239
1240 // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1241 void xorpd(XMMRegister dst, XMMRegister src);
1242 void xorpd(XMMRegister dst, Address src) { Assembler::xorpd(dst, src); }
1243 void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1244
1245 // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1246 void xorps(XMMRegister dst, XMMRegister src);
1247 void xorps(XMMRegister dst, Address src) { Assembler::xorps(dst, src); }
1248 void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1249
1250 // Shuffle Bytes
1251 void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1252 void pshufb(XMMRegister dst, Address src) { Assembler::pshufb(dst, src); }
1253 void pshufb(XMMRegister dst, AddressLiteral src);
1254 // AVX 3-operands instructions
1255
1256 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1257 void vaddsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddsd(dst, nds, src); }
1258 void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1259
1260 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1261 void vaddss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vaddss(dst, nds, src); }
1262 void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1263
1264 void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1265 void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1266
1267 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1268 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1269 void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1270
1271 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1272 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1273
1274 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1275 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1276 void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch);
1277
1278 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1279 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1280 void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1281
1282 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1283 void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1284
1285 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1286
1287 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1288 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1289
1290 // Vector compares
1291 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1292 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1293 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1294 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1295 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1296 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1297 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1298 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1299 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1300 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1301 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1302 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1303 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
1304 int comparison, bool is_signed, int vector_len) { Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len); }
1305 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
1306 int comparison, bool is_signed, int vector_len, Register scratch_reg);
1307
1308 void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1309
1310 // Emit comparison instruction for the specified comparison predicate.
1311 void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg);
1312 void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1313
1314 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1315 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1316
1317 void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1318
1319 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1320 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1321 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1322 Assembler::vpmulld(dst, nds, src, vector_len);
1323 };
1324 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1325 Assembler::vpmulld(dst, nds, src, vector_len);
1326 }
1327 void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1328
1329 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1330 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1331
1332 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1333 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1334
1335 void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1336 void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1337
1338 void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1339 void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1340
1341 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1342 if (!is_varshift) {
1343 Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1344 } else {
1345 Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1346 }
1347 }
1348 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1349 if (!is_varshift) {
1350 Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1351 } else {
1352 Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1353 }
1354 }
1355 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1356 if (!is_varshift) {
1357 Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1358 } else {
1359 Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1360 }
1361 }
1362 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1363 if (!is_varshift) {
1364 Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1365 } else {
1366 Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1367 }
1368 }
1369 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1370 if (!is_varshift) {
1371 Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1372 } else {
1373 Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1374 }
1375 }
1376 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1377 if (!is_varshift) {
1378 Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1379 } else {
1380 Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1381 }
1382 }
1383 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1384 if (!is_varshift) {
1385 Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1386 } else {
1387 Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1388 }
1389 }
1390 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1391 if (!is_varshift) {
1392 Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1393 } else {
1394 Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1395 }
1396 }
1397 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1398 if (!is_varshift) {
1399 Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1400 } else {
1401 Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1402 }
1403 }
1404
1405 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1406 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1407 void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1408 void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1409
1410 void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1411 void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1412
1413 void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1414 void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1415
1416 void vptest(XMMRegister dst, XMMRegister src);
1417 void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1418
1419 void punpcklbw(XMMRegister dst, XMMRegister src);
1420 void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1421
1422 void pshufd(XMMRegister dst, Address src, int mode);
1423 void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1424
1425 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1426 void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1427
1428 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1429 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1430 void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1431
1432 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1433 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1434 void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1435
1436 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register scratch_reg);
1437
1438 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1439 void vdivsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivsd(dst, nds, src); }
1440 void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1441
1442 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1443 void vdivss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vdivss(dst, nds, src); }
1444 void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1445
1446 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1447 void vmulsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulsd(dst, nds, src); }
1448 void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1449
1450 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1451 void vmulss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vmulss(dst, nds, src); }
1452 void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1453
1454 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1455 void vsubsd(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubsd(dst, nds, src); }
1456 void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1457
1458 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1459 void vsubss(XMMRegister dst, XMMRegister nds, Address src) { Assembler::vsubss(dst, nds, src); }
1460 void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1461
1462 void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1463 void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1464
1465 // AVX Vector instructions
1466
1467 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1468 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1469 void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1470
1471 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1472 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1473 void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1474
1475 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1476 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1477 Assembler::vpxor(dst, nds, src, vector_len);
1478 else
1479 Assembler::vxorpd(dst, nds, src, vector_len);
1480 }
1481 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1482 if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1483 Assembler::vpxor(dst, nds, src, vector_len);
1484 else
1485 Assembler::vxorpd(dst, nds, src, vector_len);
1486 }
1487 void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1488
1489 // Simple version for AVX2 256bit vectors
1490 void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1491 void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1492
1493 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1494 void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg);
1495
1496 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1497 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1498 Assembler::vinserti32x4(dst, nds, src, imm8);
1499 } else if (UseAVX > 1) {
1500 // vinserti128 is available only in AVX2
1501 Assembler::vinserti128(dst, nds, src, imm8);
1502 } else {
1503 Assembler::vinsertf128(dst, nds, src, imm8);
1504 }
1505 }
1506
1507 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1508 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1509 Assembler::vinserti32x4(dst, nds, src, imm8);
1510 } else if (UseAVX > 1) {
1511 // vinserti128 is available only in AVX2
1512 Assembler::vinserti128(dst, nds, src, imm8);
1513 } else {
1514 Assembler::vinsertf128(dst, nds, src, imm8);
1515 }
1516 }
1517
1518 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1519 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1520 Assembler::vextracti32x4(dst, src, imm8);
1521 } else if (UseAVX > 1) {
1522 // vextracti128 is available only in AVX2
1523 Assembler::vextracti128(dst, src, imm8);
1524 } else {
1525 Assembler::vextractf128(dst, src, imm8);
1526 }
1527 }
1528
1529 void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1530 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1531 Assembler::vextracti32x4(dst, src, imm8);
1532 } else if (UseAVX > 1) {
1533 // vextracti128 is available only in AVX2
1534 Assembler::vextracti128(dst, src, imm8);
1535 } else {
1536 Assembler::vextractf128(dst, src, imm8);
1537 }
1538 }
1539
1540 // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1541 void vinserti128_high(XMMRegister dst, XMMRegister src) {
1542 vinserti128(dst, dst, src, 1);
1543 }
1544 void vinserti128_high(XMMRegister dst, Address src) {
1545 vinserti128(dst, dst, src, 1);
1546 }
1547 void vextracti128_high(XMMRegister dst, XMMRegister src) {
1548 vextracti128(dst, src, 1);
1549 }
1550 void vextracti128_high(Address dst, XMMRegister src) {
1551 vextracti128(dst, src, 1);
1552 }
1553
1554 void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1555 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1556 Assembler::vinsertf32x4(dst, dst, src, 1);
1557 } else {
1558 Assembler::vinsertf128(dst, dst, src, 1);
1559 }
1560 }
1561
1562 void vinsertf128_high(XMMRegister dst, Address src) {
1563 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1564 Assembler::vinsertf32x4(dst, dst, src, 1);
1565 } else {
1566 Assembler::vinsertf128(dst, dst, src, 1);
1567 }
1568 }
1569
1570 void vextractf128_high(XMMRegister dst, XMMRegister src) {
1571 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1572 Assembler::vextractf32x4(dst, src, 1);
1573 } else {
1574 Assembler::vextractf128(dst, src, 1);
1575 }
1576 }
1577
1578 void vextractf128_high(Address dst, XMMRegister src) {
1579 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1580 Assembler::vextractf32x4(dst, src, 1);
1581 } else {
1582 Assembler::vextractf128(dst, src, 1);
1583 }
1584 }
1585
1586 // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1587 void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1588 Assembler::vinserti64x4(dst, dst, src, 1);
1589 }
1590 void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1591 Assembler::vinsertf64x4(dst, dst, src, 1);
1592 }
1593 void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1594 Assembler::vextracti64x4(dst, src, 1);
1595 }
1596 void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1597 Assembler::vextractf64x4(dst, src, 1);
1598 }
1599 void vextractf64x4_high(Address dst, XMMRegister src) {
1600 Assembler::vextractf64x4(dst, src, 1);
1601 }
1602 void vinsertf64x4_high(XMMRegister dst, Address src) {
1603 Assembler::vinsertf64x4(dst, dst, src, 1);
1604 }
1605
1606 // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1607 void vinserti128_low(XMMRegister dst, XMMRegister src) {
1608 vinserti128(dst, dst, src, 0);
1609 }
1610 void vinserti128_low(XMMRegister dst, Address src) {
1611 vinserti128(dst, dst, src, 0);
1612 }
1613 void vextracti128_low(XMMRegister dst, XMMRegister src) {
1614 vextracti128(dst, src, 0);
1615 }
1616 void vextracti128_low(Address dst, XMMRegister src) {
1617 vextracti128(dst, src, 0);
1618 }
1619
1620 void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1621 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1622 Assembler::vinsertf32x4(dst, dst, src, 0);
1623 } else {
1624 Assembler::vinsertf128(dst, dst, src, 0);
1625 }
1626 }
1627
1628 void vinsertf128_low(XMMRegister dst, Address src) {
1629 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1630 Assembler::vinsertf32x4(dst, dst, src, 0);
1631 } else {
1632 Assembler::vinsertf128(dst, dst, src, 0);
1633 }
1634 }
1635
1636 void vextractf128_low(XMMRegister dst, XMMRegister src) {
1637 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1638 Assembler::vextractf32x4(dst, src, 0);
1639 } else {
1640 Assembler::vextractf128(dst, src, 0);
1641 }
1642 }
1643
1644 void vextractf128_low(Address dst, XMMRegister src) {
1645 if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1646 Assembler::vextractf32x4(dst, src, 0);
1647 } else {
1648 Assembler::vextractf128(dst, src, 0);
1649 }
1650 }
1651
1652 // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1653 void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1654 Assembler::vinserti64x4(dst, dst, src, 0);
1655 }
1656 void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1657 Assembler::vinsertf64x4(dst, dst, src, 0);
1658 }
1659 void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1660 Assembler::vextracti64x4(dst, src, 0);
1661 }
1662 void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1663 Assembler::vextractf64x4(dst, src, 0);
1664 }
1665 void vextractf64x4_low(Address dst, XMMRegister src) {
1666 Assembler::vextractf64x4(dst, src, 0);
1667 }
1668 void vinsertf64x4_low(XMMRegister dst, Address src) {
1669 Assembler::vinsertf64x4(dst, dst, src, 0);
1670 }
1671
1672 // Carry-Less Multiplication Quadword
1673 void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1674 // 0x00 - multiply lower 64 bits [0:63]
1675 Assembler::vpclmulqdq(dst, nds, src, 0x00);
1676 }
1677 void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1678 // 0x11 - multiply upper 64 bits [64:127]
1679 Assembler::vpclmulqdq(dst, nds, src, 0x11);
1680 }
1681 void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1682 // 0x10 - multiply nds[0:63] and src[64:127]
1683 Assembler::vpclmulqdq(dst, nds, src, 0x10);
1684 }
1685 void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1686 //0x01 - multiply nds[64:127] and src[0:63]
1687 Assembler::vpclmulqdq(dst, nds, src, 0x01);
1688 }
1689
1690 void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1691 // 0x00 - multiply lower 64 bits [0:63]
1692 Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1693 }
1694 void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1695 // 0x11 - multiply upper 64 bits [64:127]
1696 Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1697 }
1698
1699 // AVX-512 mask operations.
1700 void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1701 void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1702 void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1703 void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1704 void kortest(uint masklen, KRegister src1, KRegister src2);
1705 void ktest(uint masklen, KRegister src1, KRegister src2);
1706
1707 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1708 void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1709
1710 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1711 void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1712
1713 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1714 void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1715
1716 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1717 void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1718
1719 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1720 void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1721 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1722 void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1723
1724 void alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch);
1725 void anytrue(Register dst, uint masklen, KRegister src, KRegister kscratch);
1726
1727 void cmov32( Condition cc, Register dst, Address src);
1728 void cmov32( Condition cc, Register dst, Register src);
1729
1730 void cmov( Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1731
1732 void cmovptr(Condition cc, Register dst, Address src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1733 void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1734
1735 void movoop(Register dst, jobject obj);
1736 void movoop(Address dst, jobject obj);
1737
1738 void mov_metadata(Register dst, Metadata* obj);
1739 void mov_metadata(Address dst, Metadata* obj);
1740
1741 void movptr(ArrayAddress dst, Register src);
1742 // can this do an lea?
1743 void movptr(Register dst, ArrayAddress src);
1744
1745 void movptr(Register dst, Address src);
1746
1747 #ifdef _LP64
1748 void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1749 #else
1750 void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1751 #endif
1752
1753 void movptr(Register dst, intptr_t src);
1754 void movptr(Register dst, Register src);
1755 void movptr(Address dst, intptr_t src);
1756
1757 void movptr(Address dst, Register src);
1758
1759 void movptr(Register dst, RegisterOrConstant src) {
1760 if (src.is_constant()) movptr(dst, src.as_constant());
1761 else movptr(dst, src.as_register());
1762 }
1763
1764 #ifdef _LP64
1765 // Generally the next two are only used for moving NULL
1766 // Although there are situations in initializing the mark word where
1767 // they could be used. They are dangerous.
1768
1769 // They only exist on LP64 so that int32_t and intptr_t are not the same
1770 // and we have ambiguous declarations.
1771
1772 void movptr(Address dst, int32_t imm32);
1773 void movptr(Register dst, int32_t imm32);
1774 #endif // _LP64
1775
1776 // to avoid hiding movl
1777 void mov32(AddressLiteral dst, Register src);
1778 void mov32(Register dst, AddressLiteral src);
1779
1780 // to avoid hiding movb
1781 void movbyte(ArrayAddress dst, int src);
1782
1783 // Import other mov() methods from the parent class or else
1784 // they will be hidden by the following overriding declaration.
1785 using Assembler::movdl;
1786 using Assembler::movq;
1787 void movdl(XMMRegister dst, AddressLiteral src);
1788 void movq(XMMRegister dst, AddressLiteral src);
1789
1790 // Can push value or effective address
1791 void pushptr(AddressLiteral src);
1792
1793 void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1794 void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1795
1796 void pushoop(jobject obj);
1797 void pushklass(Metadata* obj);
1798
1799 // sign extend as need a l to ptr sized element
1800 void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1801 void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1802
1803
1804 public:
1805 // C2 compiled method's prolog code.
1806 void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1807
1808 // clear memory of size 'cnt' qwords, starting at 'base';
1809 // if 'is_large' is set, do not try to produce short loop
1810 void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1811
1812 // clear memory initialization sequence for constant size;
1813 void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1814
1815 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1816 void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1817
1818 // Fill primitive arrays
1819 void generate_fill(BasicType t, bool aligned,
1820 Register to, Register value, Register count,
1821 Register rtmp, XMMRegister xtmp);
1822
1823 void encode_iso_array(Register src, Register dst, Register len,
1824 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1825 XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1826
1827 #ifdef _LP64
1828 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1829 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1830 Register y, Register y_idx, Register z,
1831 Register carry, Register product,
1832 Register idx, Register kdx);
1833 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1834 Register yz_idx, Register idx,
1835 Register carry, Register product, int offset);
1836 void multiply_128_x_128_bmi2_loop(Register y, Register z,
1837 Register carry, Register carry2,
1838 Register idx, Register jdx,
1839 Register yz_idx1, Register yz_idx2,
1840 Register tmp, Register tmp3, Register tmp4);
1841 void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1842 Register yz_idx, Register idx, Register jdx,
1843 Register carry, Register product,
1844 Register carry2);
1845 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1846 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1847 void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1848 Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1849 void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1850 Register tmp2);
1851 void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1852 Register rdxReg, Register raxReg);
1853 void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1854 void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1855 Register tmp3, Register tmp4);
1856 void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1857 Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1858
1859 void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1860 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1861 Register raxReg);
1862 void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1863 Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1864 Register raxReg);
1865 void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1866 Register result, Register tmp1, Register tmp2,
1867 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1868 #endif
1869
1870 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1871 void update_byte_crc32(Register crc, Register val, Register table);
1872 void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1873
1874
1875 #ifdef _LP64
1876 void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1877 void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1878 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1879 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1880 void updateBytesAdler32(Register adler32, Register buf, Register length, XMMRegister shuf0, XMMRegister shuf1, ExternalAddress scale);
1881 #endif // _LP64
1882
1883 // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1884 // Note on a naming convention:
1885 // Prefix w = register only used on a Westmere+ architecture
1886 // Prefix n = register only used on a Nehalem architecture
1887 #ifdef _LP64
1888 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1889 Register tmp1, Register tmp2, Register tmp3);
1890 #else
1891 void crc32c_ipl_alg4(Register in_out, uint32_t n,
1892 Register tmp1, Register tmp2, Register tmp3,
1893 XMMRegister xtmp1, XMMRegister xtmp2);
1894 #endif
1895 void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1896 Register in_out,
1897 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1898 XMMRegister w_xtmp2,
1899 Register tmp1,
1900 Register n_tmp2, Register n_tmp3);
1901 void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1902 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1903 Register tmp1, Register tmp2,
1904 Register n_tmp3);
1905 void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1906 Register in_out1, Register in_out2, Register in_out3,
1907 Register tmp1, Register tmp2, Register tmp3,
1908 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1909 Register tmp4, Register tmp5,
1910 Register n_tmp6);
1911 void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1912 Register tmp1, Register tmp2, Register tmp3,
1913 Register tmp4, Register tmp5, Register tmp6,
1914 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1915 bool is_pclmulqdq_supported);
1916 // Fold 128-bit data chunk
1917 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1918 void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1919 #ifdef _LP64
1920 // Fold 512-bit data chunk
1921 void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
1922 #endif // _LP64
1923 // Fold 8-bit data
1924 void fold_8bit_crc32(Register crc, Register table, Register tmp);
1925 void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1926
1927 // Compress char[] array to byte[].
1928 void char_array_compress(Register src, Register dst, Register len,
1929 XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1930 XMMRegister tmp4, Register tmp5, Register result,
1931 KRegister mask1 = knoreg, KRegister mask2 = knoreg);
1932
1933 // Inflate byte[] array to char[].
1934 void byte_array_inflate(Register src, Register dst, Register len,
1935 XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
1936
1937 void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
1938 Register length, Register temp, int vec_enc);
1939
1940 void fill64_masked(uint shift, Register dst, int disp,
1941 XMMRegister xmm, KRegister mask, Register length,
1942 Register temp, bool use64byteVector = false);
1943
1944 void fill32_masked(uint shift, Register dst, int disp,
1945 XMMRegister xmm, KRegister mask, Register length,
1946 Register temp);
1947
1948 void fill32(Register dst, int disp, XMMRegister xmm);
1949
1950 void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
1951
1952 #ifdef _LP64
1953 void convert_f2i(Register dst, XMMRegister src);
1954 void convert_d2i(Register dst, XMMRegister src);
1955 void convert_f2l(Register dst, XMMRegister src);
1956 void convert_d2l(Register dst, XMMRegister src);
1957
1958 void cache_wb(Address line);
1959 void cache_wbsync(bool is_pre);
1960
1961 #if COMPILER2_OR_JVMCI
1962 void arraycopy_avx3_special_cases(XMMRegister xmm, KRegister mask, Register from,
1963 Register to, Register count, int shift,
1964 Register index, Register temp,
1965 bool use64byteVector, Label& L_entry, Label& L_exit);
1966
1967 void arraycopy_avx3_special_cases_conjoint(XMMRegister xmm, KRegister mask, Register from,
1968 Register to, Register start_index, Register end_index,
1969 Register count, int shift, Register temp,
1970 bool use64byteVector, Label& L_entry, Label& L_exit);
1971
1972 void copy64_masked_avx(Register dst, Register src, XMMRegister xmm,
1973 KRegister mask, Register length, Register index,
1974 Register temp, int shift = Address::times_1, int offset = 0,
1975 bool use64byteVector = false);
1976
1977 void copy32_masked_avx(Register dst, Register src, XMMRegister xmm,
1978 KRegister mask, Register length, Register index,
1979 Register temp, int shift = Address::times_1, int offset = 0);
1980
1981 void copy32_avx(Register dst, Register src, Register index, XMMRegister xmm,
1982 int shift = Address::times_1, int offset = 0);
1983
1984 void copy64_avx(Register dst, Register src, Register index, XMMRegister xmm,
1985 bool conjoint, int shift = Address::times_1, int offset = 0,
1986 bool use64byteVector = false);
1987
1988 void generate_fill_avx3(BasicType type, Register to, Register value,
1989 Register count, Register rtmp, XMMRegister xtmp);
1990
1991 #endif // COMPILER2_OR_JVMCI
1992
1993 #endif // _LP64
1994
1995 void vallones(XMMRegister dst, int vector_len);
1996 };
1997
1998 /**
1999 * class SkipIfEqual:
2000 *
2001 * Instantiating this class will result in assembly code being output that will
2002 * jump around any code emitted between the creation of the instance and it's
2003 * automatic destruction at the end of a scope block, depending on the value of
2004 * the flag passed to the constructor, which will be checked at run-time.
2005 */
2006 class SkipIfEqual {
2007 private:
2008 MacroAssembler* _masm;
2009 Label _label;
2010
2011 public:
2012 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
2013 ~SkipIfEqual();
2014 };
2015
2016 #endif // CPU_X86_MACROASSEMBLER_X86_HPP