1 /*
   2  * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "asm/register.hpp"
  30 #include "code/vmreg.inline.hpp"
  31 #include "compiler/oopMap.hpp"
  32 #include "utilities/macros.hpp"
  33 #include "runtime/rtmLocking.hpp"
  34 #include "runtime/vm_version.hpp"
  35 
  36 // MacroAssembler extends Assembler by frequently used macros.
  37 //
  38 // Instructions for which a 'better' code sequence exists depending
  39 // on arguments should also go in here.
  40 
  41 class MacroAssembler: public Assembler {
  42   friend class LIR_Assembler;
  43   friend class Runtime1;      // as_Address()
  44 
  45  public:
  46   // Support for VM calls
  47   //
  48   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  49   // may customize this version by overriding it for its purposes (e.g., to save/restore
  50   // additional registers when doing a VM call).
  51 
  52   virtual void call_VM_leaf_base(
  53     address entry_point,               // the entry point
  54     int     number_of_arguments        // the number of arguments to pop after the call
  55   );
  56 
  57  protected:
  58   // This is the base routine called by the different versions of call_VM. The interpreter
  59   // may customize this version by overriding it for its purposes (e.g., to save/restore
  60   // additional registers when doing a VM call).
  61   //
  62   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  63   // returns the register which contains the thread upon return. If a thread register has been
  64   // specified, the return value will correspond to that register. If no last_java_sp is specified
  65   // (noreg) than rsp will be used instead.
  66   virtual void call_VM_base(           // returns the register containing the thread upon return
  67     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  68     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  69     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  70     address  entry_point,              // the entry point
  71     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  72     bool     check_exceptions          // whether to check for pending exceptions after return
  73   );
  74 
  75   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  76 
  77   // helpers for FPU flag access
  78   // tmp is a temporary register, if none is available use noreg
  79   void save_rax   (Register tmp);
  80   void restore_rax(Register tmp);
  81 
  82  public:
  83   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  84 
  85  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  86  // The implementation is only non-empty for the InterpreterMacroAssembler,
  87  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  88  virtual void check_and_handle_popframe(Register java_thread);
  89  virtual void check_and_handle_earlyret(Register java_thread);
  90 
  91   Address as_Address(AddressLiteral adr);
  92   Address as_Address(ArrayAddress adr, Register rscratch);
  93 
  94   // Support for null-checks
  95   //
  96   // Generates code that causes a null OS exception if the content of reg is null.
  97   // If the accessed location is M[reg + offset] and the offset is known, provide the
  98   // offset. No explicit code generation is needed if the offset is within a certain
  99   // range (0 <= offset <= page_size).
 100 
 101   void null_check(Register reg, int offset = -1);
 102   static bool needs_explicit_null_check(intptr_t offset);
 103   static bool uses_implicit_null_check(void* address);
 104 
 105   // Required platform-specific helpers for Label::patch_instructions.
 106   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 107   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 108     unsigned char op = branch[0];
 109     assert(op == 0xE8 /* call */ ||
 110         op == 0xE9 /* jmp */ ||
 111         op == 0xEB /* short jmp */ ||
 112         (op & 0xF0) == 0x70 /* short jcc */ ||
 113         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 114         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 115         "Invalid opcode at patch point");
 116 
 117     if (op == 0xEB || (op & 0xF0) == 0x70) {
 118       // short offset operators (jmp and jcc)
 119       char* disp = (char*) &branch[1];
 120       int imm8 = checked_cast<int>(target - (address) &disp[1]);
 121       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d",
 122                 file == nullptr ? "<null>" : file, line);
 123       *disp = (char)imm8;
 124     } else {
 125       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 126       int imm32 = checked_cast<int>(target - (address) &disp[1]);
 127       *disp = imm32;
 128     }
 129   }
 130 
 131   // The following 4 methods return the offset of the appropriate move instruction
 132 
 133   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 134   int load_unsigned_byte(Register dst, Address src);
 135   int load_unsigned_short(Register dst, Address src);
 136 
 137   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 138   int load_signed_byte(Register dst, Address src);
 139   int load_signed_short(Register dst, Address src);
 140 
 141   // Support for sign-extension (hi:lo = extend_sign(lo))
 142   void extend_sign(Register hi, Register lo);
 143 
 144   // Load and store values by size and signed-ness
 145   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 146   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 147 
 148   // Support for inc/dec with optimal instruction selection depending on value
 149 
 150   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 151   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 152   void increment(Address dst, int value = 1)  { LP64_ONLY(incrementq(dst, value)) NOT_LP64(incrementl(dst, value)) ; }
 153   void decrement(Address dst, int value = 1)  { LP64_ONLY(decrementq(dst, value)) NOT_LP64(decrementl(dst, value)) ; }
 154 
 155   void decrementl(Address dst, int value = 1);
 156   void decrementl(Register reg, int value = 1);
 157 
 158   void decrementq(Register reg, int value = 1);
 159   void decrementq(Address dst, int value = 1);
 160 
 161   void incrementl(Address dst, int value = 1);
 162   void incrementl(Register reg, int value = 1);
 163 
 164   void incrementq(Register reg, int value = 1);
 165   void incrementq(Address dst, int value = 1);
 166 
 167   void incrementl(AddressLiteral dst, Register rscratch = noreg);
 168   void incrementl(ArrayAddress   dst, Register rscratch);
 169 
 170   void incrementq(AddressLiteral dst, Register rscratch = noreg);
 171 
 172   // Support optimal SSE move instructions.
 173   void movflt(XMMRegister dst, XMMRegister src) {
 174     if (dst-> encoding() == src->encoding()) return;
 175     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 176     else                       { movss (dst, src); return; }
 177   }
 178   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 179   void movflt(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 180   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 181 
 182   // Move with zero extension
 183   void movfltz(XMMRegister dst, XMMRegister src) { movss(dst, src); }
 184 
 185   void movdbl(XMMRegister dst, XMMRegister src) {
 186     if (dst-> encoding() == src->encoding()) return;
 187     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 188     else                       { movsd (dst, src); return; }
 189   }
 190 
 191   void movdbl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 192 
 193   void movdbl(XMMRegister dst, Address src) {
 194     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 195     else                         { movlpd(dst, src); return; }
 196   }
 197   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 198 
 199   void flt_to_flt16(Register dst, XMMRegister src, XMMRegister tmp) {
 200     // Use separate tmp XMM register because caller may
 201     // requires src XMM register to be unchanged (as in x86.ad).
 202     vcvtps2ph(tmp, src, 0x04, Assembler::AVX_128bit);
 203     movdl(dst, tmp);
 204     movswl(dst, dst);
 205   }
 206 
 207   void flt16_to_flt(XMMRegister dst, Register src) {
 208     movdl(dst, src);
 209     vcvtph2ps(dst, dst, Assembler::AVX_128bit);
 210   }
 211 
 212   // Alignment
 213   void align32();
 214   void align64();
 215   void align(int modulus);
 216   void align(int modulus, int target);
 217 
 218   void post_call_nop();
 219   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 220   void fat_nop();
 221 
 222   // Stack frame creation/removal
 223   void enter();
 224   void leave();
 225 
 226   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 227   // The pointer will be loaded into the thread register.
 228   void get_thread(Register thread);
 229 
 230 #ifdef _LP64
 231   // Support for argument shuffling
 232 
 233   // bias in bytes
 234   void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 235   void long_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 236   void float_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 237   void double_move(VMRegPair src, VMRegPair dst, Register tmp = rax, int in_stk_bias = 0, int out_stk_bias = 0);
 238   void move_ptr(VMRegPair src, VMRegPair dst);
 239   void object_move(OopMap* map,
 240                    int oop_handle_offset,
 241                    int framesize_in_slots,
 242                    VMRegPair src,
 243                    VMRegPair dst,
 244                    bool is_receiver,
 245                    int* receiver_offset);
 246 #endif // _LP64
 247 
 248   // Support for VM calls
 249   //
 250   // It is imperative that all calls into the VM are handled via the call_VM macros.
 251   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 252   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 253 
 254 
 255   void call_VM(Register oop_result,
 256                address entry_point,
 257                bool check_exceptions = true);
 258   void call_VM(Register oop_result,
 259                address entry_point,
 260                Register arg_1,
 261                bool check_exceptions = true);
 262   void call_VM(Register oop_result,
 263                address entry_point,
 264                Register arg_1, Register arg_2,
 265                bool check_exceptions = true);
 266   void call_VM(Register oop_result,
 267                address entry_point,
 268                Register arg_1, Register arg_2, Register arg_3,
 269                bool check_exceptions = true);
 270 
 271   // Overloadings with last_Java_sp
 272   void call_VM(Register oop_result,
 273                Register last_java_sp,
 274                address entry_point,
 275                int number_of_arguments = 0,
 276                bool check_exceptions = true);
 277   void call_VM(Register oop_result,
 278                Register last_java_sp,
 279                address entry_point,
 280                Register arg_1, bool
 281                check_exceptions = true);
 282   void call_VM(Register oop_result,
 283                Register last_java_sp,
 284                address entry_point,
 285                Register arg_1, Register arg_2,
 286                bool check_exceptions = true);
 287   void call_VM(Register oop_result,
 288                Register last_java_sp,
 289                address entry_point,
 290                Register arg_1, Register arg_2, Register arg_3,
 291                bool check_exceptions = true);
 292 
 293   void get_vm_result  (Register oop_result, Register thread);
 294   void get_vm_result_2(Register metadata_result, Register thread);
 295 
 296   // These always tightly bind to MacroAssembler::call_VM_base
 297   // bypassing the virtual implementation
 298   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 299   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 300   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 301   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 302   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 303 
 304   void call_VM_leaf0(address entry_point);
 305   void call_VM_leaf(address entry_point,
 306                     int number_of_arguments = 0);
 307   void call_VM_leaf(address entry_point,
 308                     Register arg_1);
 309   void call_VM_leaf(address entry_point,
 310                     Register arg_1, Register arg_2);
 311   void call_VM_leaf(address entry_point,
 312                     Register arg_1, Register arg_2, Register arg_3);
 313 
 314   void call_VM_leaf(address entry_point,
 315                     Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 316 
 317   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 318   // bypassing the virtual implementation
 319   void super_call_VM_leaf(address entry_point);
 320   void super_call_VM_leaf(address entry_point, Register arg_1);
 321   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 322   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 323   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 324 
 325   // last Java Frame (fills frame anchor)
 326   void set_last_Java_frame(Register thread,
 327                            Register last_java_sp,
 328                            Register last_java_fp,
 329                            address  last_java_pc,
 330                            Register rscratch);
 331 
 332   // thread in the default location (r15_thread on 64bit)
 333   void set_last_Java_frame(Register last_java_sp,
 334                            Register last_java_fp,
 335                            address  last_java_pc,
 336                            Register rscratch);
 337 
 338   void reset_last_Java_frame(Register thread, bool clear_fp);
 339 
 340   // thread in the default location (r15_thread on 64bit)
 341   void reset_last_Java_frame(bool clear_fp);
 342 
 343   // jobjects
 344   void clear_jobject_tag(Register possibly_non_local);
 345   void resolve_jobject(Register value, Register thread, Register tmp);
 346   void resolve_global_jobject(Register value, Register thread, Register tmp);
 347 
 348   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 349   void c2bool(Register x);
 350 
 351   // C++ bool manipulation
 352 
 353   void movbool(Register dst, Address src);
 354   void movbool(Address dst, bool boolconst);
 355   void movbool(Address dst, Register src);
 356   void testbool(Register dst);
 357 
 358   void resolve_oop_handle(Register result, Register tmp);
 359   void resolve_weak_handle(Register result, Register tmp);
 360   void load_mirror(Register mirror, Register method, Register tmp);
 361   void load_method_holder_cld(Register rresult, Register rmethod);
 362 
 363   void load_method_holder(Register holder, Register method);
 364 
 365   // oop manipulations
 366 #ifdef _LP64
 367   void load_nklass(Register dst, Register src);
 368 #endif
 369   void load_klass(Register dst, Register src, Register tmp);
 370   void store_klass(Register dst, Register src, Register tmp);
 371 
 372   // Compares the Klass pointer of an object to a given Klass (which might be narrow,
 373   // depending on UseCompressedClassPointers).
 374   void cmp_klass(Register klass, Register dst, Register tmp);
 375 
 376   // Compares the Klass pointer of two objects o1 and o2. Result is in the condition flags.
 377   // Uses t1 and t2 as temporary registers.
 378   void cmp_klass(Register src, Register dst, Register tmp1, Register tmp2);
 379 
 380   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 381                       Register tmp1, Register thread_tmp);
 382   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
 383                        Register tmp1, Register tmp2, Register tmp3);
 384 
 385   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 386                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 387   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 388                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 389   void store_heap_oop(Address dst, Register val, Register tmp1 = noreg,
 390                       Register tmp2 = noreg, Register tmp3 = noreg, DecoratorSet decorators = 0);
 391 
 392   // Used for storing null. All other oop constants should be
 393   // stored using routines that take a jobject.
 394   void store_heap_oop_null(Address dst);
 395 
 396 #ifdef _LP64
 397   void store_klass_gap(Register dst, Register src);
 398 
 399   // This dummy is to prevent a call to store_heap_oop from
 400   // converting a zero (like null) into a Register by giving
 401   // the compiler two choices it can't resolve
 402 
 403   void store_heap_oop(Address dst, void* dummy);
 404 
 405   void encode_heap_oop(Register r);
 406   void decode_heap_oop(Register r);
 407   void encode_heap_oop_not_null(Register r);
 408   void decode_heap_oop_not_null(Register r);
 409   void encode_heap_oop_not_null(Register dst, Register src);
 410   void decode_heap_oop_not_null(Register dst, Register src);
 411 
 412   void set_narrow_oop(Register dst, jobject obj);
 413   void set_narrow_oop(Address dst, jobject obj);
 414   void cmp_narrow_oop(Register dst, jobject obj);
 415   void cmp_narrow_oop(Address dst, jobject obj);
 416 
 417   void encode_klass_not_null(Register r, Register tmp);
 418   void decode_klass_not_null(Register r, Register tmp);
 419   void encode_and_move_klass_not_null(Register dst, Register src);
 420   void decode_and_move_klass_not_null(Register dst, Register src);
 421   void set_narrow_klass(Register dst, Klass* k);
 422   void set_narrow_klass(Address dst, Klass* k);
 423   void cmp_narrow_klass(Register dst, Klass* k);
 424   void cmp_narrow_klass(Address dst, Klass* k);
 425 
 426   // if heap base register is used - reinit it with the correct value
 427   void reinit_heapbase();
 428 
 429   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 430 
 431 #endif // _LP64
 432 
 433   // Int division/remainder for Java
 434   // (as idivl, but checks for special case as described in JVM spec.)
 435   // returns idivl instruction offset for implicit exception handling
 436   int corrected_idivl(Register reg);
 437 
 438   // Long division/remainder for Java
 439   // (as idivq, but checks for special case as described in JVM spec.)
 440   // returns idivq instruction offset for implicit exception handling
 441   int corrected_idivq(Register reg);
 442 
 443   void int3();
 444 
 445   // Long operation macros for a 32bit cpu
 446   // Long negation for Java
 447   void lneg(Register hi, Register lo);
 448 
 449   // Long multiplication for Java
 450   // (destroys contents of eax, ebx, ecx and edx)
 451   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 452 
 453   // Long shifts for Java
 454   // (semantics as described in JVM spec.)
 455   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 456   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 457 
 458   // Long compare for Java
 459   // (semantics as described in JVM spec.)
 460   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 461 
 462 
 463   // misc
 464 
 465   // Sign extension
 466   void sign_extend_short(Register reg);
 467   void sign_extend_byte(Register reg);
 468 
 469   // Division by power of 2, rounding towards 0
 470   void division_with_shift(Register reg, int shift_value);
 471 
 472 #ifndef _LP64
 473   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 474   //
 475   // CF (corresponds to C0) if x < y
 476   // PF (corresponds to C2) if unordered
 477   // ZF (corresponds to C3) if x = y
 478   //
 479   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 480   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 481   void fcmp(Register tmp);
 482   // Variant of the above which allows y to be further down the stack
 483   // and which only pops x and y if specified. If pop_right is
 484   // specified then pop_left must also be specified.
 485   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 486 
 487   // Floating-point comparison for Java
 488   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 489   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 490   // (semantics as described in JVM spec.)
 491   void fcmp2int(Register dst, bool unordered_is_less);
 492   // Variant of the above which allows y to be further down the stack
 493   // and which only pops x and y if specified. If pop_right is
 494   // specified then pop_left must also be specified.
 495   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 496 
 497   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 498   // tmp is a temporary register, if none is available use noreg
 499   void fremr(Register tmp);
 500 
 501   // only if +VerifyFPU
 502   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 503 #endif // !LP64
 504 
 505   // dst = c = a * b + c
 506   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 507   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 508 
 509   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 510   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 511   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 512   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 513 
 514 
 515   // same as fcmp2int, but using SSE2
 516   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 517   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 518 
 519   // branch to L if FPU flag C2 is set/not set
 520   // tmp is a temporary register, if none is available use noreg
 521   void jC2 (Register tmp, Label& L);
 522   void jnC2(Register tmp, Label& L);
 523 
 524   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 525   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 526   void load_float(Address src);
 527 
 528   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 529   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 530   void store_float(Address dst);
 531 
 532   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 533   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 534   void load_double(Address src);
 535 
 536   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 537   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 538   void store_double(Address dst);
 539 
 540 #ifndef _LP64
 541   // Pop ST (ffree & fincstp combined)
 542   void fpop();
 543 
 544   void empty_FPU_stack();
 545 #endif // !_LP64
 546 
 547   void push_IU_state();
 548   void pop_IU_state();
 549 
 550   void push_FPU_state();
 551   void pop_FPU_state();
 552 
 553   void push_CPU_state();
 554   void pop_CPU_state();
 555 
 556   void push_cont_fastpath();
 557   void pop_cont_fastpath();
 558 
 559   void inc_held_monitor_count();
 560   void dec_held_monitor_count();
 561 
 562   DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
 563 
 564   // Round up to a power of two
 565   void round_to(Register reg, int modulus);
 566 
 567 private:
 568   // General purpose and XMM registers potentially clobbered by native code; there
 569   // is no need for FPU or AVX opmask related methods because C1/interpreter
 570   // - we save/restore FPU state as a whole always
 571   // - do not care about AVX-512 opmask
 572   static RegSet call_clobbered_gp_registers();
 573   static XMMRegSet call_clobbered_xmm_registers();
 574 
 575   void push_set(XMMRegSet set, int offset);
 576   void pop_set(XMMRegSet set, int offset);
 577 
 578 public:
 579   void push_set(RegSet set, int offset = -1);
 580   void pop_set(RegSet set, int offset = -1);
 581 
 582   // Push and pop everything that might be clobbered by a native
 583   // runtime call.
 584   // Only save the lower 64 bits of each vector register.
 585   // Additional registers can be excluded in a passed RegSet.
 586   void push_call_clobbered_registers_except(RegSet exclude, bool save_fpu = true);
 587   void pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu = true);
 588 
 589   void push_call_clobbered_registers(bool save_fpu = true) {
 590     push_call_clobbered_registers_except(RegSet(), save_fpu);
 591   }
 592   void pop_call_clobbered_registers(bool restore_fpu = true) {
 593     pop_call_clobbered_registers_except(RegSet(), restore_fpu);
 594   }
 595 
 596   // allocation
 597   void tlab_allocate(
 598     Register thread,                   // Current thread
 599     Register obj,                      // result: pointer to object after successful allocation
 600     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 601     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 602     Register t1,                       // temp register
 603     Register t2,                       // temp register
 604     Label&   slow_case                 // continuation point if fast allocation fails
 605   );
 606   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 607 
 608   // interface method calling
 609   void lookup_interface_method(Register recv_klass,
 610                                Register intf_klass,
 611                                RegisterOrConstant itable_index,
 612                                Register method_result,
 613                                Register scan_temp,
 614                                Label& no_such_interface,
 615                                bool return_method = true);
 616 
 617   void lookup_interface_method_stub(Register recv_klass,
 618                                     Register holder_klass,
 619                                     Register resolved_klass,
 620                                     Register method_result,
 621                                     Register scan_temp,
 622                                     Register temp_reg2,
 623                                     Register receiver,
 624                                     int itable_index,
 625                                     Label& L_no_such_interface);
 626 
 627   // virtual method calling
 628   void lookup_virtual_method(Register recv_klass,
 629                              RegisterOrConstant vtable_index,
 630                              Register method_result);
 631 
 632   // Test sub_klass against super_klass, with fast and slow paths.
 633 
 634   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 635   // One of the three labels can be null, meaning take the fall-through.
 636   // If super_check_offset is -1, the value is loaded up from super_klass.
 637   // No registers are killed, except temp_reg.
 638   void check_klass_subtype_fast_path(Register sub_klass,
 639                                      Register super_klass,
 640                                      Register temp_reg,
 641                                      Label* L_success,
 642                                      Label* L_failure,
 643                                      Label* L_slow_path,
 644                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 645 
 646   // The rest of the type check; must be wired to a corresponding fast path.
 647   // It does not repeat the fast path logic, so don't use it standalone.
 648   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 649   // Updates the sub's secondary super cache as necessary.
 650   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 651   void check_klass_subtype_slow_path(Register sub_klass,
 652                                      Register super_klass,
 653                                      Register temp_reg,
 654                                      Register temp2_reg,
 655                                      Label* L_success,
 656                                      Label* L_failure,
 657                                      bool set_cond_codes = false);
 658 
 659   // Simplified, combined version, good for typical uses.
 660   // Falls through on failure.
 661   void check_klass_subtype(Register sub_klass,
 662                            Register super_klass,
 663                            Register temp_reg,
 664                            Label& L_success);
 665 
 666   void clinit_barrier(Register klass,
 667                       Register thread,
 668                       Label* L_fast_path = nullptr,
 669                       Label* L_slow_path = nullptr);
 670 
 671   // method handles (JSR 292)
 672   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 673 
 674   // Debugging
 675 
 676   // only if +VerifyOops
 677   void _verify_oop(Register reg, const char* s, const char* file, int line);
 678   void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
 679 
 680   void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
 681     if (VerifyOops) {
 682       _verify_oop(reg, s, file, line);
 683     }
 684   }
 685   void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
 686     if (VerifyOops) {
 687       _verify_oop_addr(reg, s, file, line);
 688     }
 689   }
 690 
 691   // TODO: verify method and klass metadata (compare against vptr?)
 692   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 693   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 694 
 695 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
 696 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
 697 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
 698 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 699 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 700 
 701   // Verify or restore cpu control state after JNI call
 702   void restore_cpu_control_state_after_jni(Register rscratch);
 703 
 704   // prints msg, dumps registers and stops execution
 705   void stop(const char* msg);
 706 
 707   // prints msg and continues
 708   void warn(const char* msg);
 709 
 710   // dumps registers and other state
 711   void print_state();
 712 
 713   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 714   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 715   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 716   static void print_state64(int64_t pc, int64_t regs[]);
 717 
 718   void os_breakpoint();
 719 
 720   void untested()                                { stop("untested"); }
 721 
 722   void unimplemented(const char* what = "");
 723 
 724   void should_not_reach_here()                   { stop("should not reach here"); }
 725 
 726   void print_CPU_state();
 727 
 728   // Stack overflow checking
 729   void bang_stack_with_offset(int offset) {
 730     // stack grows down, caller passes positive offset
 731     assert(offset > 0, "must bang with negative offset");
 732     movl(Address(rsp, (-offset)), rax);
 733   }
 734 
 735   // Writes to stack successive pages until offset reached to check for
 736   // stack overflow + shadow pages.  Also, clobbers tmp
 737   void bang_stack_size(Register size, Register tmp);
 738 
 739   // Check for reserved stack access in method being exited (for JIT)
 740   void reserved_stack_check();
 741 
 742   void safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod);
 743 
 744   void verify_tlab();
 745 
 746   static Condition negate_condition(Condition cond);
 747 
 748   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 749   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 750   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 751   // here in MacroAssembler. The major exception to this rule is call
 752 
 753   // Arithmetics
 754 
 755 
 756   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 757   void addptr(Address dst, Register src);
 758 
 759   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 760   void addptr(Register dst, int32_t src);
 761   void addptr(Register dst, Register src);
 762   void addptr(Register dst, RegisterOrConstant src) {
 763     if (src.is_constant()) addptr(dst, checked_cast<int>(src.as_constant()));
 764     else                   addptr(dst, src.as_register());
 765   }
 766 
 767   void andptr(Register dst, int32_t src);
 768   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 769 
 770 #ifdef _LP64
 771   using Assembler::andq;
 772   void andq(Register dst, AddressLiteral src, Register rscratch = noreg);
 773 #endif
 774 
 775   void cmp8(AddressLiteral src1, int imm, Register rscratch = noreg);
 776 
 777   // renamed to drag out the casting of address to int32_t/intptr_t
 778   void cmp32(Register src1, int32_t imm);
 779 
 780   void cmp32(AddressLiteral src1, int32_t imm, Register rscratch = noreg);
 781   // compare reg - mem, or reg - &mem
 782   void cmp32(Register src1, AddressLiteral src2, Register rscratch = noreg);
 783 
 784   void cmp32(Register src1, Address src2);
 785 
 786 #ifndef _LP64
 787   void cmpklass(Address dst, Metadata* obj);
 788   void cmpklass(Register dst, Metadata* obj);
 789   void cmpoop(Address dst, jobject obj);
 790 #endif // _LP64
 791 
 792   void cmpoop(Register src1, Register src2);
 793   void cmpoop(Register src1, Address src2);
 794   void cmpoop(Register dst, jobject obj, Register rscratch);
 795 
 796   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 797   void cmpptr(Address src1, AddressLiteral src2, Register rscratch);
 798 
 799   void cmpptr(Register src1, AddressLiteral src2, Register rscratch = noreg);
 800 
 801   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 802   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 803   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 804 
 805   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 806   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 807 
 808   // cmp64 to avoild hiding cmpq
 809   void cmp64(Register src1, AddressLiteral src, Register rscratch = noreg);
 810 
 811   void cmpxchgptr(Register reg, Address adr);
 812 
 813   void locked_cmpxchgptr(Register reg, AddressLiteral adr, Register rscratch = noreg);
 814 
 815   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 816   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 817 
 818 
 819   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 820 
 821   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 822 
 823   void shlptr(Register dst, int32_t shift);
 824   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 825 
 826   void shrptr(Register dst, int32_t shift);
 827   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 828 
 829   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 830   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 831 
 832   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 833 
 834   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 835   void subptr(Register dst, int32_t src);
 836   // Force generation of a 4 byte immediate value even if it fits into 8bit
 837   void subptr_imm32(Register dst, int32_t src);
 838   void subptr(Register dst, Register src);
 839   void subptr(Register dst, RegisterOrConstant src) {
 840     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 841     else                   subptr(dst,       src.as_register());
 842   }
 843 
 844   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 845   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 846 
 847   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 848   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 849 
 850   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 851 
 852 
 853 
 854   // Helper functions for statistics gathering.
 855   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 856   void cond_inc32(Condition cond, AddressLiteral counter_addr, Register rscratch = noreg);
 857   // Unconditional atomic increment.
 858   void atomic_incl(Address counter_addr);
 859   void atomic_incl(AddressLiteral counter_addr, Register rscratch = noreg);
 860 #ifdef _LP64
 861   void atomic_incq(Address counter_addr);
 862   void atomic_incq(AddressLiteral counter_addr, Register rscratch = noreg);
 863 #endif
 864   void atomic_incptr(AddressLiteral counter_addr, Register rscratch = noreg) { LP64_ONLY(atomic_incq(counter_addr, rscratch)) NOT_LP64(atomic_incl(counter_addr, rscratch)) ; }
 865   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 866 
 867   void lea(Register dst, Address        adr) { Assembler::lea(dst, adr); }
 868   void lea(Register dst, AddressLiteral adr);
 869   void lea(Address  dst, AddressLiteral adr, Register rscratch);
 870 
 871   void leal32(Register dst, Address src) { leal(dst, src); }
 872 
 873   // Import other testl() methods from the parent class or else
 874   // they will be hidden by the following overriding declaration.
 875   using Assembler::testl;
 876   void testl(Address dst, int32_t imm32);
 877   void testl(Register dst, int32_t imm32);
 878   void testl(Register dst, AddressLiteral src); // requires reachable address
 879   using Assembler::testq;
 880   void testq(Address dst, int32_t imm32);
 881   void testq(Register dst, int32_t imm32);
 882 
 883   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 884   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 885   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 886   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 887 
 888   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 889   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 890   void testptr(Register src1, Register src2);
 891 
 892   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 893   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 894 
 895   // Calls
 896 
 897   void call(Label& L, relocInfo::relocType rtype);
 898   void call(Register entry);
 899   void call(Address addr) { Assembler::call(addr); }
 900 
 901   // NOTE: this call transfers to the effective address of entry NOT
 902   // the address contained by entry. This is because this is more natural
 903   // for jumps/calls.
 904   void call(AddressLiteral entry, Register rscratch = rax);
 905 
 906   // Emit the CompiledIC call idiom
 907   void ic_call(address entry, jint method_index = 0);
 908 
 909   void emit_static_call_stub();
 910 
 911   // Jumps
 912 
 913   // NOTE: these jumps transfer to the effective address of dst NOT
 914   // the address contained by dst. This is because this is more natural
 915   // for jumps/calls.
 916   void jump(AddressLiteral dst, Register rscratch = noreg);
 917 
 918   void jump_cc(Condition cc, AddressLiteral dst, Register rscratch = noreg);
 919 
 920   // 32bit can do a case table jump in one instruction but we no longer allow the base
 921   // to be installed in the Address class. This jump will transfer to the address
 922   // contained in the location described by entry (not the address of entry)
 923   void jump(ArrayAddress entry, Register rscratch);
 924 
 925   // Floating
 926 
 927   void push_f(XMMRegister r);
 928   void pop_f(XMMRegister r);
 929   void push_d(XMMRegister r);
 930   void pop_d(XMMRegister r);
 931 
 932   void andpd(XMMRegister dst, XMMRegister    src) { Assembler::andpd(dst, src); }
 933   void andpd(XMMRegister dst, Address        src) { Assembler::andpd(dst, src); }
 934   void andpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 935 
 936   void andps(XMMRegister dst, XMMRegister    src) { Assembler::andps(dst, src); }
 937   void andps(XMMRegister dst, Address        src) { Assembler::andps(dst, src); }
 938   void andps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 939 
 940   void comiss(XMMRegister dst, XMMRegister    src) { Assembler::comiss(dst, src); }
 941   void comiss(XMMRegister dst, Address        src) { Assembler::comiss(dst, src); }
 942   void comiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 943 
 944   void comisd(XMMRegister dst, XMMRegister    src) { Assembler::comisd(dst, src); }
 945   void comisd(XMMRegister dst, Address        src) { Assembler::comisd(dst, src); }
 946   void comisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
 947 
 948 #ifndef _LP64
 949   void fadd_s(Address        src) { Assembler::fadd_s(src); }
 950   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 951 
 952   void fldcw(Address        src) { Assembler::fldcw(src); }
 953   void fldcw(AddressLiteral src);
 954 
 955   void fld_s(int index)          { Assembler::fld_s(index); }
 956   void fld_s(Address        src) { Assembler::fld_s(src); }
 957   void fld_s(AddressLiteral src);
 958 
 959   void fld_d(Address        src) { Assembler::fld_d(src); }
 960   void fld_d(AddressLiteral src);
 961 
 962   void fld_x(Address        src) { Assembler::fld_x(src); }
 963   void fld_x(AddressLiteral src) { Assembler::fld_x(as_Address(src)); }
 964 
 965   void fmul_s(Address        src) { Assembler::fmul_s(src); }
 966   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 967 #endif // !_LP64
 968 
 969   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 970   void ldmxcsr(AddressLiteral src, Register rscratch = noreg);
 971 
 972 #ifdef _LP64
 973  private:
 974   void sha256_AVX2_one_round_compute(
 975     Register  reg_old_h,
 976     Register  reg_a,
 977     Register  reg_b,
 978     Register  reg_c,
 979     Register  reg_d,
 980     Register  reg_e,
 981     Register  reg_f,
 982     Register  reg_g,
 983     Register  reg_h,
 984     int iter);
 985   void sha256_AVX2_four_rounds_compute_first(int start);
 986   void sha256_AVX2_four_rounds_compute_last(int start);
 987   void sha256_AVX2_one_round_and_sched(
 988         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 989         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 990         XMMRegister xmm_2,     /* ymm6 */
 991         XMMRegister xmm_3,     /* ymm7 */
 992         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 993         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 994         Register    reg_c,      /* edi */
 995         Register    reg_d,      /* esi */
 996         Register    reg_e,      /* r8d */
 997         Register    reg_f,      /* r9d */
 998         Register    reg_g,      /* r10d */
 999         Register    reg_h,      /* r11d */
1000         int iter);
1001 
1002   void addm(int disp, Register r1, Register r2);
1003 
1004   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
1005                                      Register e, Register f, Register g, Register h, int iteration);
1006 
1007   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1008                                           Register a, Register b, Register c, Register d, Register e, Register f,
1009                                           Register g, Register h, int iteration);
1010 
1011   void addmq(int disp, Register r1, Register r2);
1012  public:
1013   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1014                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1015                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1016                    bool multi_block, XMMRegister shuf_mask);
1017   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1018                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1019                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
1020                    XMMRegister shuf_mask);
1021 #endif // _LP64
1022 
1023   void fast_md5(Register buf, Address state, Address ofs, Address limit,
1024                 bool multi_block);
1025 
1026   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1027                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1028                  Register buf, Register state, Register ofs, Register limit, Register rsp,
1029                  bool multi_block);
1030 
1031 #ifdef _LP64
1032   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1033                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1034                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1035                    bool multi_block, XMMRegister shuf_mask);
1036 #else
1037   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1038                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1039                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1040                    bool multi_block);
1041 #endif
1042 
1043   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1044                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1045                 Register rax, Register rcx, Register rdx, Register tmp);
1046 
1047 #ifndef _LP64
1048  private:
1049   // Initialized in macroAssembler_x86_constants.cpp
1050   static address ONES;
1051   static address L_2IL0FLOATPACKET_0;
1052   static address PI4_INV;
1053   static address PI4X3;
1054   static address PI4X4;
1055 
1056  public:
1057   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1058                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1059                 Register rax, Register rcx, Register rdx, Register tmp1);
1060 
1061   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1062                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1063                 Register rax, Register rcx, Register rdx, Register tmp);
1064 
1065   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1066                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1067                 Register rdx, Register tmp);
1068 
1069   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1070                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1071                 Register rax, Register rbx, Register rdx);
1072 
1073   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1074                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1075                 Register rax, Register rcx, Register rdx, Register tmp);
1076 
1077   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1078                         Register edx, Register ebx, Register esi, Register edi,
1079                         Register ebp, Register esp);
1080 
1081   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1082                          Register esi, Register edi, Register ebp, Register esp);
1083 
1084   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1085                         Register edx, Register ebx, Register esi, Register edi,
1086                         Register ebp, Register esp);
1087 
1088   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1089                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1090                 Register rax, Register rcx, Register rdx, Register tmp);
1091 #endif // !_LP64
1092 
1093 private:
1094 
1095   // these are private because users should be doing movflt/movdbl
1096 
1097   void movss(Address     dst, XMMRegister    src) { Assembler::movss(dst, src); }
1098   void movss(XMMRegister dst, XMMRegister    src) { Assembler::movss(dst, src); }
1099   void movss(XMMRegister dst, Address        src) { Assembler::movss(dst, src); }
1100   void movss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1101 
1102   void movlpd(XMMRegister dst, Address        src) {Assembler::movlpd(dst, src); }
1103   void movlpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1104 
1105 public:
1106 
1107   void addsd(XMMRegister dst, XMMRegister    src) { Assembler::addsd(dst, src); }
1108   void addsd(XMMRegister dst, Address        src) { Assembler::addsd(dst, src); }
1109   void addsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1110 
1111   void addss(XMMRegister dst, XMMRegister    src) { Assembler::addss(dst, src); }
1112   void addss(XMMRegister dst, Address        src) { Assembler::addss(dst, src); }
1113   void addss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1114 
1115   void addpd(XMMRegister dst, XMMRegister    src) { Assembler::addpd(dst, src); }
1116   void addpd(XMMRegister dst, Address        src) { Assembler::addpd(dst, src); }
1117   void addpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1118 
1119   using Assembler::vbroadcastsd;
1120   void vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1121 
1122   using Assembler::vbroadcastss;
1123   void vbroadcastss(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1124 
1125   void divsd(XMMRegister dst, XMMRegister    src) { Assembler::divsd(dst, src); }
1126   void divsd(XMMRegister dst, Address        src) { Assembler::divsd(dst, src); }
1127   void divsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1128 
1129   void divss(XMMRegister dst, XMMRegister    src) { Assembler::divss(dst, src); }
1130   void divss(XMMRegister dst, Address        src) { Assembler::divss(dst, src); }
1131   void divss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1132 
1133   // Move Unaligned Double Quadword
1134   void movdqu(Address     dst, XMMRegister    src);
1135   void movdqu(XMMRegister dst, XMMRegister    src);
1136   void movdqu(XMMRegister dst, Address        src);
1137   void movdqu(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1138 
1139   void kmovwl(Register  dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1140   void kmovwl(Address   dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1141   void kmovwl(KRegister dst, KRegister      src) { Assembler::kmovwl(dst, src); }
1142   void kmovwl(KRegister dst, Register       src) { Assembler::kmovwl(dst, src); }
1143   void kmovwl(KRegister dst, Address        src) { Assembler::kmovwl(dst, src); }
1144   void kmovwl(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1145 
1146   void kmovql(KRegister dst, KRegister      src) { Assembler::kmovql(dst, src); }
1147   void kmovql(KRegister dst, Register       src) { Assembler::kmovql(dst, src); }
1148   void kmovql(Register  dst, KRegister      src) { Assembler::kmovql(dst, src); }
1149   void kmovql(KRegister dst, Address        src) { Assembler::kmovql(dst, src); }
1150   void kmovql(Address   dst, KRegister      src) { Assembler::kmovql(dst, src); }
1151   void kmovql(KRegister dst, AddressLiteral src, Register rscratch = noreg);
1152 
1153   // Safe move operation, lowers down to 16bit moves for targets supporting
1154   // AVX512F feature and 64bit moves for targets supporting AVX512BW feature.
1155   void kmov(Address  dst, KRegister src);
1156   void kmov(KRegister dst, Address src);
1157   void kmov(KRegister dst, KRegister src);
1158   void kmov(Register dst, KRegister src);
1159   void kmov(KRegister dst, Register src);
1160 
1161   using Assembler::movddup;
1162   void movddup(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1163 
1164   using Assembler::vmovddup;
1165   void vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1166 
1167   // AVX Unaligned forms
1168   void vmovdqu(Address     dst, XMMRegister    src);
1169   void vmovdqu(XMMRegister dst, Address        src);
1170   void vmovdqu(XMMRegister dst, XMMRegister    src);
1171   void vmovdqu(XMMRegister dst, AddressLiteral src,                 Register rscratch = noreg);
1172   void vmovdqu(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1173 
1174   // AVX512 Unaligned
1175   void evmovdqu(BasicType type, KRegister kmask, Address     dst, XMMRegister src, bool merge, int vector_len);
1176   void evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address     src, bool merge, int vector_len);
1177 
1178   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1179   void evmovdqub(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdqub(dst, src, vector_len); }
1180 
1181   void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1182     if (dst->encoding() != src->encoding() || mask != k0)  {
1183       Assembler::evmovdqub(dst, mask, src, merge, vector_len);
1184     }
1185   }
1186   void evmovdqub(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1187   void evmovdqub(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdqub(dst, mask, src, merge, vector_len); }
1188   void evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1189 
1190   void evmovdquw(Address     dst, XMMRegister src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1191   void evmovdquw(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdquw(dst, src, vector_len); }
1192 
1193   void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1194     if (dst->encoding() != src->encoding() || mask != k0) {
1195       Assembler::evmovdquw(dst, mask, src, merge, vector_len);
1196     }
1197   }
1198   void evmovdquw(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1199   void evmovdquw(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdquw(dst, mask, src, merge, vector_len); }
1200   void evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1201 
1202   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
1203      if (dst->encoding() != src->encoding()) {
1204        Assembler::evmovdqul(dst, src, vector_len);
1205      }
1206   }
1207   void evmovdqul(Address     dst, XMMRegister src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1208   void evmovdqul(XMMRegister dst, Address     src, int vector_len) { Assembler::evmovdqul(dst, src, vector_len); }
1209 
1210   void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1211     if (dst->encoding() != src->encoding() || mask != k0)  {
1212       Assembler::evmovdqul(dst, mask, src, merge, vector_len);
1213     }
1214   }
1215   void evmovdqul(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1216   void evmovdqul(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdqul(dst, mask, src, merge, vector_len); }
1217   void evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1218 
1219   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
1220     if (dst->encoding() != src->encoding()) {
1221       Assembler::evmovdquq(dst, src, vector_len);
1222     }
1223   }
1224   void evmovdquq(XMMRegister dst, Address        src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1225   void evmovdquq(Address     dst, XMMRegister    src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1226   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1227 
1228   void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
1229     if (dst->encoding() != src->encoding() || mask != k0) {
1230       Assembler::evmovdquq(dst, mask, src, merge, vector_len);
1231     }
1232   }
1233   void evmovdquq(Address     dst, KRegister mask, XMMRegister    src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1234   void evmovdquq(XMMRegister dst, KRegister mask, Address        src, bool merge, int vector_len) { Assembler::evmovdquq(dst, mask, src, merge, vector_len); }
1235   void evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1236 
1237   // Move Aligned Double Quadword
1238   void movdqa(XMMRegister dst, XMMRegister    src) { Assembler::movdqa(dst, src); }
1239   void movdqa(XMMRegister dst, Address        src) { Assembler::movdqa(dst, src); }
1240   void movdqa(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1241 
1242   void movsd(Address     dst, XMMRegister    src) { Assembler::movsd(dst, src); }
1243   void movsd(XMMRegister dst, XMMRegister    src) { Assembler::movsd(dst, src); }
1244   void movsd(XMMRegister dst, Address        src) { Assembler::movsd(dst, src); }
1245   void movsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1246 
1247   void mulpd(XMMRegister dst, XMMRegister    src) { Assembler::mulpd(dst, src); }
1248   void mulpd(XMMRegister dst, Address        src) { Assembler::mulpd(dst, src); }
1249   void mulpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1250 
1251   void mulsd(XMMRegister dst, XMMRegister    src) { Assembler::mulsd(dst, src); }
1252   void mulsd(XMMRegister dst, Address        src) { Assembler::mulsd(dst, src); }
1253   void mulsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1254 
1255   void mulss(XMMRegister dst, XMMRegister    src) { Assembler::mulss(dst, src); }
1256   void mulss(XMMRegister dst, Address        src) { Assembler::mulss(dst, src); }
1257   void mulss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1258 
1259   // Carry-Less Multiplication Quadword
1260   void pclmulldq(XMMRegister dst, XMMRegister src) {
1261     // 0x00 - multiply lower 64 bits [0:63]
1262     Assembler::pclmulqdq(dst, src, 0x00);
1263   }
1264   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1265     // 0x11 - multiply upper 64 bits [64:127]
1266     Assembler::pclmulqdq(dst, src, 0x11);
1267   }
1268 
1269   void pcmpeqb(XMMRegister dst, XMMRegister src);
1270   void pcmpeqw(XMMRegister dst, XMMRegister src);
1271 
1272   void pcmpestri(XMMRegister dst, Address src, int imm8);
1273   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1274 
1275   void pmovzxbw(XMMRegister dst, XMMRegister src);
1276   void pmovzxbw(XMMRegister dst, Address src);
1277 
1278   void pmovmskb(Register dst, XMMRegister src);
1279 
1280   void ptest(XMMRegister dst, XMMRegister src);
1281 
1282   void roundsd(XMMRegister dst, XMMRegister    src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1283   void roundsd(XMMRegister dst, Address        src, int32_t rmode) { Assembler::roundsd(dst, src, rmode); }
1284   void roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register rscratch = noreg);
1285 
1286   void sqrtss(XMMRegister dst, XMMRegister     src) { Assembler::sqrtss(dst, src); }
1287   void sqrtss(XMMRegister dst, Address         src) { Assembler::sqrtss(dst, src); }
1288   void sqrtss(XMMRegister dst, AddressLiteral  src, Register rscratch = noreg);
1289 
1290   void subsd(XMMRegister dst, XMMRegister    src) { Assembler::subsd(dst, src); }
1291   void subsd(XMMRegister dst, Address        src) { Assembler::subsd(dst, src); }
1292   void subsd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1293 
1294   void subss(XMMRegister dst, XMMRegister    src) { Assembler::subss(dst, src); }
1295   void subss(XMMRegister dst, Address        src) { Assembler::subss(dst, src); }
1296   void subss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1297 
1298   void ucomiss(XMMRegister dst, XMMRegister    src) { Assembler::ucomiss(dst, src); }
1299   void ucomiss(XMMRegister dst, Address        src) { Assembler::ucomiss(dst, src); }
1300   void ucomiss(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1301 
1302   void ucomisd(XMMRegister dst, XMMRegister    src) { Assembler::ucomisd(dst, src); }
1303   void ucomisd(XMMRegister dst, Address        src) { Assembler::ucomisd(dst, src); }
1304   void ucomisd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1305 
1306   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1307   void xorpd(XMMRegister dst, XMMRegister    src);
1308   void xorpd(XMMRegister dst, Address        src) { Assembler::xorpd(dst, src); }
1309   void xorpd(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1310 
1311   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1312   void xorps(XMMRegister dst, XMMRegister    src);
1313   void xorps(XMMRegister dst, Address        src) { Assembler::xorps(dst, src); }
1314   void xorps(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1315 
1316   // Shuffle Bytes
1317   void pshufb(XMMRegister dst, XMMRegister    src) { Assembler::pshufb(dst, src); }
1318   void pshufb(XMMRegister dst, Address        src) { Assembler::pshufb(dst, src); }
1319   void pshufb(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1320   // AVX 3-operands instructions
1321 
1322   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vaddsd(dst, nds, src); }
1323   void vaddsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vaddsd(dst, nds, src); }
1324   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1325 
1326   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vaddss(dst, nds, src); }
1327   void vaddss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vaddss(dst, nds, src); }
1328   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1329 
1330   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1331   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len, Register rscratch = noreg);
1332 
1333   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len);
1334   void vpaddb(XMMRegister dst, XMMRegister nds, Address        src, int vector_len);
1335   void vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1336 
1337   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1338   void vpaddw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1339 
1340   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1341   void vpaddd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpaddd(dst, nds, src, vector_len); }
1342   void vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1343 
1344   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1345   void vpand(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1346   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1347 
1348   using Assembler::vpbroadcastd;
1349   void vpbroadcastd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1350 
1351   using Assembler::vpbroadcastq;
1352   void vpbroadcastq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch = noreg);
1353 
1354   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1355 
1356   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1357   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1358 
1359   // Vector compares
1360   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1361     Assembler::evpcmpd(kdst, mask, nds, src, comparison, is_signed, vector_len);
1362   }
1363   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1364 
1365   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1366     Assembler::evpcmpq(kdst, mask, nds, src, comparison, is_signed, vector_len);
1367   }
1368   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1369 
1370   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1371     Assembler::evpcmpb(kdst, mask, nds, src, comparison, is_signed, vector_len);
1372   }
1373   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1374 
1375   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister    src, int comparison, bool is_signed, int vector_len) {
1376     Assembler::evpcmpw(kdst, mask, nds, src, comparison, is_signed, vector_len);
1377   }
1378   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src, int comparison, bool is_signed, int vector_len, Register rscratch = noreg);
1379 
1380   void evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len);
1381 
1382   // Emit comparison instruction for the specified comparison predicate.
1383   void vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len);
1384   void vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len);
1385 
1386   void vpmovzxbw(XMMRegister dst, Address     src, int vector_len);
1387   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1388 
1389   void vpmovmskb(Register dst, XMMRegister src, int vector_len = Assembler::AVX_256bit);
1390 
1391   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1392   void vpmullw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1393 
1394   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1395   void vpmulld(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vpmulld(dst, nds, src, vector_len); }
1396   void vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1397 
1398   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1399   void vpsubb(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1400 
1401   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1402   void vpsubw(XMMRegister dst, XMMRegister nds, Address     src, int vector_len);
1403 
1404   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1405   void vpsraw(XMMRegister dst, XMMRegister nds, int         shift, int vector_len);
1406 
1407   void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1408   void evpsraq(XMMRegister dst, XMMRegister nds, int         shift, int vector_len);
1409 
1410   void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1411     if (!is_varshift) {
1412       Assembler::evpsllw(dst, mask, nds, src, merge, vector_len);
1413     } else {
1414       Assembler::evpsllvw(dst, mask, nds, src, merge, vector_len);
1415     }
1416   }
1417   void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1418     if (!is_varshift) {
1419       Assembler::evpslld(dst, mask, nds, src, merge, vector_len);
1420     } else {
1421       Assembler::evpsllvd(dst, mask, nds, src, merge, vector_len);
1422     }
1423   }
1424   void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1425     if (!is_varshift) {
1426       Assembler::evpsllq(dst, mask, nds, src, merge, vector_len);
1427     } else {
1428       Assembler::evpsllvq(dst, mask, nds, src, merge, vector_len);
1429     }
1430   }
1431   void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1432     if (!is_varshift) {
1433       Assembler::evpsrlw(dst, mask, nds, src, merge, vector_len);
1434     } else {
1435       Assembler::evpsrlvw(dst, mask, nds, src, merge, vector_len);
1436     }
1437   }
1438   void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1439     if (!is_varshift) {
1440       Assembler::evpsrld(dst, mask, nds, src, merge, vector_len);
1441     } else {
1442       Assembler::evpsrlvd(dst, mask, nds, src, merge, vector_len);
1443     }
1444   }
1445   void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1446     if (!is_varshift) {
1447       Assembler::evpsrlq(dst, mask, nds, src, merge, vector_len);
1448     } else {
1449       Assembler::evpsrlvq(dst, mask, nds, src, merge, vector_len);
1450     }
1451   }
1452   void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1453     if (!is_varshift) {
1454       Assembler::evpsraw(dst, mask, nds, src, merge, vector_len);
1455     } else {
1456       Assembler::evpsravw(dst, mask, nds, src, merge, vector_len);
1457     }
1458   }
1459   void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1460     if (!is_varshift) {
1461       Assembler::evpsrad(dst, mask, nds, src, merge, vector_len);
1462     } else {
1463       Assembler::evpsravd(dst, mask, nds, src, merge, vector_len);
1464     }
1465   }
1466   void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len, bool is_varshift) {
1467     if (!is_varshift) {
1468       Assembler::evpsraq(dst, mask, nds, src, merge, vector_len);
1469     } else {
1470       Assembler::evpsravq(dst, mask, nds, src, merge, vector_len);
1471     }
1472   }
1473 
1474   void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1475   void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1476   void evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1477   void evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1478 
1479   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1480   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1481 
1482   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1483   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1484 
1485   void vptest(XMMRegister dst, XMMRegister src);
1486   void vptest(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vptest(dst, src, vector_len); }
1487 
1488   void punpcklbw(XMMRegister dst, XMMRegister src);
1489   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1490 
1491   void pshufd(XMMRegister dst, Address src, int mode);
1492   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1493 
1494   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1495   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1496 
1497   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1498   void vandpd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1499   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1500 
1501   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1502   void vandps(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1503   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1504 
1505   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src, bool merge, int vector_len, Register rscratch = noreg);
1506 
1507   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vdivsd(dst, nds, src); }
1508   void vdivsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vdivsd(dst, nds, src); }
1509   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1510 
1511   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vdivss(dst, nds, src); }
1512   void vdivss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vdivss(dst, nds, src); }
1513   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1514 
1515   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vmulsd(dst, nds, src); }
1516   void vmulsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vmulsd(dst, nds, src); }
1517   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1518 
1519   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vmulss(dst, nds, src); }
1520   void vmulss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vmulss(dst, nds, src); }
1521   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1522 
1523   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vsubsd(dst, nds, src); }
1524   void vsubsd(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vsubsd(dst, nds, src); }
1525   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1526 
1527   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister    src) { Assembler::vsubss(dst, nds, src); }
1528   void vsubss(XMMRegister dst, XMMRegister nds, Address        src) { Assembler::vsubss(dst, nds, src); }
1529   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1530 
1531   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1532   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src, Register rscratch = noreg);
1533 
1534   // AVX Vector instructions
1535 
1536   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1537   void vxorpd(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1538   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1539 
1540   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1541   void vxorps(XMMRegister dst, XMMRegister nds, Address        src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1542   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1543 
1544   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1545     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1546       Assembler::vpxor(dst, nds, src, vector_len);
1547     else
1548       Assembler::vxorpd(dst, nds, src, vector_len);
1549   }
1550   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1551     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1552       Assembler::vpxor(dst, nds, src, vector_len);
1553     else
1554       Assembler::vxorpd(dst, nds, src, vector_len);
1555   }
1556   void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1557 
1558   // Simple version for AVX2 256bit vectors
1559   void vpxor(XMMRegister dst, XMMRegister src) {
1560     assert(UseAVX >= 2, "Should be at least AVX2");
1561     Assembler::vpxor(dst, dst, src, AVX_256bit);
1562   }
1563   void vpxor(XMMRegister dst, Address src) {
1564     assert(UseAVX >= 2, "Should be at least AVX2");
1565     Assembler::vpxor(dst, dst, src, AVX_256bit);
1566   }
1567 
1568   void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister    src, int vector_len) { Assembler::vpermd(dst, nds, src, vector_len); }
1569   void vpermd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1570 
1571   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1572     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1573       Assembler::vinserti32x4(dst, nds, src, imm8);
1574     } else if (UseAVX > 1) {
1575       // vinserti128 is available only in AVX2
1576       Assembler::vinserti128(dst, nds, src, imm8);
1577     } else {
1578       Assembler::vinsertf128(dst, nds, src, imm8);
1579     }
1580   }
1581 
1582   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1583     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1584       Assembler::vinserti32x4(dst, nds, src, imm8);
1585     } else if (UseAVX > 1) {
1586       // vinserti128 is available only in AVX2
1587       Assembler::vinserti128(dst, nds, src, imm8);
1588     } else {
1589       Assembler::vinsertf128(dst, nds, src, imm8);
1590     }
1591   }
1592 
1593   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1594     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1595       Assembler::vextracti32x4(dst, src, imm8);
1596     } else if (UseAVX > 1) {
1597       // vextracti128 is available only in AVX2
1598       Assembler::vextracti128(dst, src, imm8);
1599     } else {
1600       Assembler::vextractf128(dst, src, imm8);
1601     }
1602   }
1603 
1604   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1605     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1606       Assembler::vextracti32x4(dst, src, imm8);
1607     } else if (UseAVX > 1) {
1608       // vextracti128 is available only in AVX2
1609       Assembler::vextracti128(dst, src, imm8);
1610     } else {
1611       Assembler::vextractf128(dst, src, imm8);
1612     }
1613   }
1614 
1615   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1616   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1617     vinserti128(dst, dst, src, 1);
1618   }
1619   void vinserti128_high(XMMRegister dst, Address src) {
1620     vinserti128(dst, dst, src, 1);
1621   }
1622   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1623     vextracti128(dst, src, 1);
1624   }
1625   void vextracti128_high(Address dst, XMMRegister src) {
1626     vextracti128(dst, src, 1);
1627   }
1628 
1629   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1630     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1631       Assembler::vinsertf32x4(dst, dst, src, 1);
1632     } else {
1633       Assembler::vinsertf128(dst, dst, src, 1);
1634     }
1635   }
1636 
1637   void vinsertf128_high(XMMRegister dst, Address src) {
1638     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1639       Assembler::vinsertf32x4(dst, dst, src, 1);
1640     } else {
1641       Assembler::vinsertf128(dst, dst, src, 1);
1642     }
1643   }
1644 
1645   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1646     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1647       Assembler::vextractf32x4(dst, src, 1);
1648     } else {
1649       Assembler::vextractf128(dst, src, 1);
1650     }
1651   }
1652 
1653   void vextractf128_high(Address dst, XMMRegister src) {
1654     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1655       Assembler::vextractf32x4(dst, src, 1);
1656     } else {
1657       Assembler::vextractf128(dst, src, 1);
1658     }
1659   }
1660 
1661   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1662   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1663     Assembler::vinserti64x4(dst, dst, src, 1);
1664   }
1665   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1666     Assembler::vinsertf64x4(dst, dst, src, 1);
1667   }
1668   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1669     Assembler::vextracti64x4(dst, src, 1);
1670   }
1671   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1672     Assembler::vextractf64x4(dst, src, 1);
1673   }
1674   void vextractf64x4_high(Address dst, XMMRegister src) {
1675     Assembler::vextractf64x4(dst, src, 1);
1676   }
1677   void vinsertf64x4_high(XMMRegister dst, Address src) {
1678     Assembler::vinsertf64x4(dst, dst, src, 1);
1679   }
1680 
1681   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1682   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1683     vinserti128(dst, dst, src, 0);
1684   }
1685   void vinserti128_low(XMMRegister dst, Address src) {
1686     vinserti128(dst, dst, src, 0);
1687   }
1688   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1689     vextracti128(dst, src, 0);
1690   }
1691   void vextracti128_low(Address dst, XMMRegister src) {
1692     vextracti128(dst, src, 0);
1693   }
1694 
1695   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1696     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1697       Assembler::vinsertf32x4(dst, dst, src, 0);
1698     } else {
1699       Assembler::vinsertf128(dst, dst, src, 0);
1700     }
1701   }
1702 
1703   void vinsertf128_low(XMMRegister dst, Address src) {
1704     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1705       Assembler::vinsertf32x4(dst, dst, src, 0);
1706     } else {
1707       Assembler::vinsertf128(dst, dst, src, 0);
1708     }
1709   }
1710 
1711   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1712     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1713       Assembler::vextractf32x4(dst, src, 0);
1714     } else {
1715       Assembler::vextractf128(dst, src, 0);
1716     }
1717   }
1718 
1719   void vextractf128_low(Address dst, XMMRegister src) {
1720     if (UseAVX > 2 && VM_Version::supports_avx512novl()) {
1721       Assembler::vextractf32x4(dst, src, 0);
1722     } else {
1723       Assembler::vextractf128(dst, src, 0);
1724     }
1725   }
1726 
1727   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1728   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1729     Assembler::vinserti64x4(dst, dst, src, 0);
1730   }
1731   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1732     Assembler::vinsertf64x4(dst, dst, src, 0);
1733   }
1734   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1735     Assembler::vextracti64x4(dst, src, 0);
1736   }
1737   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1738     Assembler::vextractf64x4(dst, src, 0);
1739   }
1740   void vextractf64x4_low(Address dst, XMMRegister src) {
1741     Assembler::vextractf64x4(dst, src, 0);
1742   }
1743   void vinsertf64x4_low(XMMRegister dst, Address src) {
1744     Assembler::vinsertf64x4(dst, dst, src, 0);
1745   }
1746 
1747   // Carry-Less Multiplication Quadword
1748   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1749     // 0x00 - multiply lower 64 bits [0:63]
1750     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1751   }
1752   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1753     // 0x11 - multiply upper 64 bits [64:127]
1754     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1755   }
1756   void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1757     // 0x10 - multiply nds[0:63] and src[64:127]
1758     Assembler::vpclmulqdq(dst, nds, src, 0x10);
1759   }
1760   void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1761     //0x01 - multiply nds[64:127] and src[0:63]
1762     Assembler::vpclmulqdq(dst, nds, src, 0x01);
1763   }
1764 
1765   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1766     // 0x00 - multiply lower 64 bits [0:63]
1767     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1768   }
1769   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1770     // 0x11 - multiply upper 64 bits [64:127]
1771     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1772   }
1773 
1774   // AVX-512 mask operations.
1775   void kand(BasicType etype, KRegister dst, KRegister src1, KRegister src2);
1776   void kor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1777   void knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp = knoreg, Register rtmp = noreg);
1778   void kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2);
1779   void kortest(uint masklen, KRegister src1, KRegister src2);
1780   void ktest(uint masklen, KRegister src1, KRegister src2);
1781 
1782   void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1783   void evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1784 
1785   void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1786   void evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1787 
1788   void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1789   void evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1790 
1791   void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1792   void evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
1793 
1794   void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1795   void evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1796   void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc);
1797   void evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc);
1798 
1799   using Assembler::evpandq;
1800   void evpandq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1801 
1802   using Assembler::evporq;
1803   void evporq(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch = noreg);
1804 
1805   using Assembler::vpternlogq;
1806   void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, AddressLiteral src3, int vector_len, Register rscratch = noreg);
1807 
1808   void cmov32( Condition cc, Register dst, Address  src);
1809   void cmov32( Condition cc, Register dst, Register src);
1810 
1811   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1812 
1813   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1814   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1815 
1816   void movoop(Register dst, jobject obj);
1817   void movoop(Address  dst, jobject obj, Register rscratch);
1818 
1819   void mov_metadata(Register dst, Metadata* obj);
1820   void mov_metadata(Address  dst, Metadata* obj, Register rscratch);
1821 
1822   void movptr(Register     dst, Register       src);
1823   void movptr(Register     dst, Address        src);
1824   void movptr(Register     dst, AddressLiteral src);
1825   void movptr(Register     dst, ArrayAddress   src);
1826   void movptr(Register     dst, intptr_t       src);
1827   void movptr(Address      dst, Register       src);
1828   void movptr(Address      dst, int32_t        imm);
1829   void movptr(Address      dst, intptr_t       src, Register rscratch);
1830   void movptr(ArrayAddress dst, Register       src, Register rscratch);
1831 
1832   void movptr(Register dst, RegisterOrConstant src) {
1833     if (src.is_constant()) movptr(dst, src.as_constant());
1834     else                   movptr(dst, src.as_register());
1835   }
1836 
1837 
1838   // to avoid hiding movl
1839   void mov32(Register       dst, AddressLiteral src);
1840   void mov32(AddressLiteral dst, Register        src, Register rscratch = noreg);
1841 
1842   // Import other mov() methods from the parent class or else
1843   // they will be hidden by the following overriding declaration.
1844   using Assembler::movdl;
1845   void movdl(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1846 
1847   using Assembler::movq;
1848   void movq(XMMRegister dst, AddressLiteral src, Register rscratch = noreg);
1849 
1850   // Can push value or effective address
1851   void pushptr(AddressLiteral src, Register rscratch);
1852 
1853   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1854   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1855 
1856   void pushoop(jobject obj, Register rscratch);
1857   void pushklass(Metadata* obj, Register rscratch);
1858 
1859   // sign extend as need a l to ptr sized element
1860   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1861   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1862 
1863 
1864  public:
1865   // clear memory of size 'cnt' qwords, starting at 'base';
1866   // if 'is_large' is set, do not try to produce short loop
1867   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large, KRegister mask=knoreg);
1868 
1869   // clear memory initialization sequence for constant size;
1870   void clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1871 
1872   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1873   void xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask=knoreg);
1874 
1875   // Fill primitive arrays
1876   void generate_fill(BasicType t, bool aligned,
1877                      Register to, Register value, Register count,
1878                      Register rtmp, XMMRegister xtmp);
1879 
1880   void encode_iso_array(Register src, Register dst, Register len,
1881                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1882                         XMMRegister tmp4, Register tmp5, Register result, bool ascii);
1883 
1884 #ifdef _LP64
1885   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1886   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1887                              Register y, Register y_idx, Register z,
1888                              Register carry, Register product,
1889                              Register idx, Register kdx);
1890   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1891                               Register yz_idx, Register idx,
1892                               Register carry, Register product, int offset);
1893   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1894                                     Register carry, Register carry2,
1895                                     Register idx, Register jdx,
1896                                     Register yz_idx1, Register yz_idx2,
1897                                     Register tmp, Register tmp3, Register tmp4);
1898   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1899                                Register yz_idx, Register idx, Register jdx,
1900                                Register carry, Register product,
1901                                Register carry2);
1902   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1903                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1904   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1905                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1906   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1907                             Register tmp2);
1908   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1909                        Register rdxReg, Register raxReg);
1910   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1911   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1912                        Register tmp3, Register tmp4);
1913   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1914                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1915 
1916   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1917                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1918                Register raxReg);
1919   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1920                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1921                Register raxReg);
1922   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1923                            Register result, Register tmp1, Register tmp2,
1924                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1925 #endif
1926 
1927   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1928   void update_byte_crc32(Register crc, Register val, Register table);
1929   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1930 
1931 
1932 #ifdef _LP64
1933   void kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2);
1934   void kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
1935                                 Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
1936                                 Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup);
1937 #endif // _LP64
1938 
1939   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1940   // Note on a naming convention:
1941   // Prefix w = register only used on a Westmere+ architecture
1942   // Prefix n = register only used on a Nehalem architecture
1943 #ifdef _LP64
1944   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1945                        Register tmp1, Register tmp2, Register tmp3);
1946 #else
1947   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1948                        Register tmp1, Register tmp2, Register tmp3,
1949                        XMMRegister xtmp1, XMMRegister xtmp2);
1950 #endif
1951   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1952                         Register in_out,
1953                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1954                         XMMRegister w_xtmp2,
1955                         Register tmp1,
1956                         Register n_tmp2, Register n_tmp3);
1957   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1958                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1959                        Register tmp1, Register tmp2,
1960                        Register n_tmp3);
1961   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1962                          Register in_out1, Register in_out2, Register in_out3,
1963                          Register tmp1, Register tmp2, Register tmp3,
1964                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1965                          Register tmp4, Register tmp5,
1966                          Register n_tmp6);
1967   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1968                             Register tmp1, Register tmp2, Register tmp3,
1969                             Register tmp4, Register tmp5, Register tmp6,
1970                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1971                             bool is_pclmulqdq_supported);
1972   // Fold 128-bit data chunk
1973   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1974   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1975 #ifdef _LP64
1976   // Fold 512-bit data chunk
1977   void fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, Register pos, int offset);
1978 #endif // _LP64
1979   // Fold 8-bit data
1980   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1981   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1982 
1983   // Compress char[] array to byte[].
1984   void char_array_compress(Register src, Register dst, Register len,
1985                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1986                            XMMRegister tmp4, Register tmp5, Register result,
1987                            KRegister mask1 = knoreg, KRegister mask2 = knoreg);
1988 
1989   // Inflate byte[] array to char[].
1990   void byte_array_inflate(Register src, Register dst, Register len,
1991                           XMMRegister tmp1, Register tmp2, KRegister mask = knoreg);
1992 
1993   void fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
1994                    Register length, Register temp, int vec_enc);
1995 
1996   void fill64_masked(uint shift, Register dst, int disp,
1997                          XMMRegister xmm, KRegister mask, Register length,
1998                          Register temp, bool use64byteVector = false);
1999 
2000   void fill32_masked(uint shift, Register dst, int disp,
2001                          XMMRegister xmm, KRegister mask, Register length,
2002                          Register temp);
2003 
2004   void fill32(Address dst, XMMRegister xmm);
2005 
2006   void fill32(Register dst, int disp, XMMRegister xmm);
2007 
2008   void fill64(Address dst, XMMRegister xmm, bool use64byteVector = false);
2009 
2010   void fill64(Register dst, int dis, XMMRegister xmm, bool use64byteVector = false);
2011 
2012 #ifdef _LP64
2013   void convert_f2i(Register dst, XMMRegister src);
2014   void convert_d2i(Register dst, XMMRegister src);
2015   void convert_f2l(Register dst, XMMRegister src);
2016   void convert_d2l(Register dst, XMMRegister src);
2017   void round_double(Register dst, XMMRegister src, Register rtmp, Register rcx);
2018   void round_float(Register dst, XMMRegister src, Register rtmp, Register rcx);
2019 
2020   void cache_wb(Address line);
2021   void cache_wbsync(bool is_pre);
2022 
2023 #ifdef COMPILER2_OR_JVMCI
2024   void generate_fill_avx3(BasicType type, Register to, Register value,
2025                           Register count, Register rtmp, XMMRegister xtmp);
2026 #endif // COMPILER2_OR_JVMCI
2027 #endif // _LP64
2028 
2029   void vallones(XMMRegister dst, int vector_len);
2030 
2031   void check_stack_alignment(Register sp, const char* msg, unsigned bias = 0, Register tmp = noreg);
2032 
2033   void fast_lock_impl(Register obj, Register hdr, Register thread, Register tmp, Label& slow);
2034   void fast_unlock_impl(Register obj, Register hdr, Register tmp, Label& slow);
2035 };
2036 
2037 /**
2038  * class SkipIfEqual:
2039  *
2040  * Instantiating this class will result in assembly code being output that will
2041  * jump around any code emitted between the creation of the instance and it's
2042  * automatic destruction at the end of a scope block, depending on the value of
2043  * the flag passed to the constructor, which will be checked at run-time.
2044  */
2045 class SkipIfEqual {
2046  private:
2047   MacroAssembler* _masm;
2048   Label _label;
2049 
2050  public:
2051    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value, Register rscratch);
2052    ~SkipIfEqual();
2053 };
2054 
2055 #endif // CPU_X86_MACROASSEMBLER_X86_HPP