1 //
    2 // Copyright (c) 2003, 2025, Oracle and/or its affiliates. All rights reserved.
    3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    4 //
    5 // This code is free software; you can redistribute it and/or modify it
    6 // under the terms of the GNU General Public License version 2 only, as
    7 // published by the Free Software Foundation.
    8 //
    9 // This code is distributed in the hope that it will be useful, but WITHOUT
   10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   12 // version 2 for more details (a copy is included in the LICENSE file that
   13 // accompanied this code).
   14 //
   15 // You should have received a copy of the GNU General Public License version
   16 // 2 along with this work; if not, write to the Free Software Foundation,
   17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   18 //
   19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   20 // or visit www.oracle.com if you need additional information or have any
   21 // questions.
   22 //
   23 //
   24 
   25 // AMD64 Architecture Description File
   26 
   27 //----------REGISTER DEFINITION BLOCK------------------------------------------
   28 // This information is used by the matcher and the register allocator to
   29 // describe individual registers and classes of registers within the target
   30 // architecture.
   31 
   32 register %{
   33 //----------Architecture Description Register Definitions----------------------
   34 // General Registers
   35 // "reg_def"  name ( register save type, C convention save type,
   36 //                   ideal register type, encoding );
   37 // Register Save Types:
   38 //
   39 // NS  = No-Save:       The register allocator assumes that these registers
   40 //                      can be used without saving upon entry to the method, &
   41 //                      that they do not need to be saved at call sites.
   42 //
   43 // SOC = Save-On-Call:  The register allocator assumes that these registers
   44 //                      can be used without saving upon entry to the method,
   45 //                      but that they must be saved at call sites.
   46 //
   47 // SOE = Save-On-Entry: The register allocator assumes that these registers
   48 //                      must be saved before using them upon entry to the
   49 //                      method, but they do not need to be saved at call
   50 //                      sites.
   51 //
   52 // AS  = Always-Save:   The register allocator assumes that these registers
   53 //                      must be saved before using them upon entry to the
   54 //                      method, & that they must be saved at call sites.
   55 //
   56 // Ideal Register Type is used to determine how to save & restore a
   57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   59 //
   60 // The encoding number is the actual bit-pattern placed into the opcodes.
   61 
   62 // General Registers
   63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
   64 // used as byte registers)
   65 
   66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
   67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
   68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
   69 
   70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
   71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
   72 
   73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
   74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
   75 
   76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
   77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
   78 
   79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
   80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
   81 
   82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
   83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
   84 
   85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
   86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
   87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
   88 
   89 #ifdef _WIN64
   90 
   91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
   92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
   93 
   94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
   95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
   96 
   97 #else
   98 
   99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
  100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
  101 
  102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
  103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
  104 
  105 #endif
  106 
  107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
  108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
  109 
  110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
  111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
  112 
  113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
  114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
  115 
  116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
  117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
  118 
  119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
  120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
  121 
  122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
  123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
  124 
  125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
  126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
  127 
  128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
  129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
  130 
  131 reg_def R16  (SOC, SOC, Op_RegI, 16, r16->as_VMReg());
  132 reg_def R16_H(SOC, SOC, Op_RegI, 16, r16->as_VMReg()->next());
  133 
  134 reg_def R17  (SOC, SOC, Op_RegI, 17, r17->as_VMReg());
  135 reg_def R17_H(SOC, SOC, Op_RegI, 17, r17->as_VMReg()->next());
  136 
  137 reg_def R18  (SOC, SOC, Op_RegI, 18, r18->as_VMReg());
  138 reg_def R18_H(SOC, SOC, Op_RegI, 18, r18->as_VMReg()->next());
  139 
  140 reg_def R19  (SOC, SOC, Op_RegI, 19, r19->as_VMReg());
  141 reg_def R19_H(SOC, SOC, Op_RegI, 19, r19->as_VMReg()->next());
  142 
  143 reg_def R20  (SOC, SOC, Op_RegI, 20, r20->as_VMReg());
  144 reg_def R20_H(SOC, SOC, Op_RegI, 20, r20->as_VMReg()->next());
  145 
  146 reg_def R21  (SOC, SOC, Op_RegI, 21, r21->as_VMReg());
  147 reg_def R21_H(SOC, SOC, Op_RegI, 21, r21->as_VMReg()->next());
  148 
  149 reg_def R22  (SOC, SOC, Op_RegI, 22, r22->as_VMReg());
  150 reg_def R22_H(SOC, SOC, Op_RegI, 22, r22->as_VMReg()->next());
  151 
  152 reg_def R23  (SOC, SOC, Op_RegI, 23, r23->as_VMReg());
  153 reg_def R23_H(SOC, SOC, Op_RegI, 23, r23->as_VMReg()->next());
  154 
  155 reg_def R24  (SOC, SOC, Op_RegI, 24, r24->as_VMReg());
  156 reg_def R24_H(SOC, SOC, Op_RegI, 24, r24->as_VMReg()->next());
  157 
  158 reg_def R25  (SOC, SOC, Op_RegI, 25, r25->as_VMReg());
  159 reg_def R25_H(SOC, SOC, Op_RegI, 25, r25->as_VMReg()->next());
  160 
  161 reg_def R26  (SOC, SOC, Op_RegI, 26, r26->as_VMReg());
  162 reg_def R26_H(SOC, SOC, Op_RegI, 26, r26->as_VMReg()->next());
  163 
  164 reg_def R27  (SOC, SOC, Op_RegI, 27, r27->as_VMReg());
  165 reg_def R27_H(SOC, SOC, Op_RegI, 27, r27->as_VMReg()->next());
  166 
  167 reg_def R28  (SOC, SOC, Op_RegI, 28, r28->as_VMReg());
  168 reg_def R28_H(SOC, SOC, Op_RegI, 28, r28->as_VMReg()->next());
  169 
  170 reg_def R29  (SOC, SOC, Op_RegI, 29, r29->as_VMReg());
  171 reg_def R29_H(SOC, SOC, Op_RegI, 29, r29->as_VMReg()->next());
  172 
  173 reg_def R30  (SOC, SOC, Op_RegI, 30, r30->as_VMReg());
  174 reg_def R30_H(SOC, SOC, Op_RegI, 30, r30->as_VMReg()->next());
  175 
  176 reg_def R31  (SOC, SOC, Op_RegI, 31, r31->as_VMReg());
  177 reg_def R31_H(SOC, SOC, Op_RegI, 31, r31->as_VMReg()->next());
  178 
  179 // Floating Point Registers
  180 
  181 // Specify priority of register selection within phases of register
  182 // allocation.  Highest priority is first.  A useful heuristic is to
  183 // give registers a low priority when they are required by machine
  184 // instructions, like EAX and EDX on I486, and choose no-save registers
  185 // before save-on-call, & save-on-call before save-on-entry.  Registers
  186 // which participate in fixed calling sequences should come last.
  187 // Registers which are used as pairs must fall on an even boundary.
  188 
  189 alloc_class chunk0(R10,         R10_H,
  190                    R11,         R11_H,
  191                    R8,          R8_H,
  192                    R9,          R9_H,
  193                    R12,         R12_H,
  194                    RCX,         RCX_H,
  195                    RBX,         RBX_H,
  196                    RDI,         RDI_H,
  197                    RDX,         RDX_H,
  198                    RSI,         RSI_H,
  199                    RAX,         RAX_H,
  200                    RBP,         RBP_H,
  201                    R13,         R13_H,
  202                    R14,         R14_H,
  203                    R15,         R15_H,
  204                    R16,         R16_H,
  205                    R17,         R17_H,
  206                    R18,         R18_H,
  207                    R19,         R19_H,
  208                    R20,         R20_H,
  209                    R21,         R21_H,
  210                    R22,         R22_H,
  211                    R23,         R23_H,
  212                    R24,         R24_H,
  213                    R25,         R25_H,
  214                    R26,         R26_H,
  215                    R27,         R27_H,
  216                    R28,         R28_H,
  217                    R29,         R29_H,
  218                    R30,         R30_H,
  219                    R31,         R31_H,
  220                    RSP,         RSP_H);
  221 
  222 
  223 //----------Architecture Description Register Classes--------------------------
  224 // Several register classes are automatically defined based upon information in
  225 // this architecture description.
  226 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  227 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  228 //
  229 
  230 // Empty register class.
  231 reg_class no_reg();
  232 
  233 // Class for all pointer/long registers including APX extended GPRs.
  234 reg_class all_reg(RAX, RAX_H,
  235                   RDX, RDX_H,
  236                   RBP, RBP_H,
  237                   RDI, RDI_H,
  238                   RSI, RSI_H,
  239                   RCX, RCX_H,
  240                   RBX, RBX_H,
  241                   RSP, RSP_H,
  242                   R8,  R8_H,
  243                   R9,  R9_H,
  244                   R10, R10_H,
  245                   R11, R11_H,
  246                   R12, R12_H,
  247                   R13, R13_H,
  248                   R14, R14_H,
  249                   R15, R15_H,
  250                   R16, R16_H,
  251                   R17, R17_H,
  252                   R18, R18_H,
  253                   R19, R19_H,
  254                   R20, R20_H,
  255                   R21, R21_H,
  256                   R22, R22_H,
  257                   R23, R23_H,
  258                   R24, R24_H,
  259                   R25, R25_H,
  260                   R26, R26_H,
  261                   R27, R27_H,
  262                   R28, R28_H,
  263                   R29, R29_H,
  264                   R30, R30_H,
  265                   R31, R31_H);
  266 
  267 // Class for all int registers including APX extended GPRs.
  268 reg_class all_int_reg(RAX
  269                       RDX,
  270                       RBP,
  271                       RDI,
  272                       RSI,
  273                       RCX,
  274                       RBX,
  275                       R8,
  276                       R9,
  277                       R10,
  278                       R11,
  279                       R12,
  280                       R13,
  281                       R14,
  282                       R16,
  283                       R17,
  284                       R18,
  285                       R19,
  286                       R20,
  287                       R21,
  288                       R22,
  289                       R23,
  290                       R24,
  291                       R25,
  292                       R26,
  293                       R27,
  294                       R28,
  295                       R29,
  296                       R30,
  297                       R31);
  298 
  299 // Class for all pointer registers
  300 reg_class any_reg %{
  301   return _ANY_REG_mask;
  302 %}
  303 
  304 // Class for all pointer registers (excluding RSP)
  305 reg_class ptr_reg %{
  306   return _PTR_REG_mask;
  307 %}
  308 
  309 // Class for all pointer registers (excluding RSP and RBP)
  310 reg_class ptr_reg_no_rbp %{
  311   return _PTR_REG_NO_RBP_mask;
  312 %}
  313 
  314 // Class for all pointer registers (excluding RAX and RSP)
  315 reg_class ptr_no_rax_reg %{
  316   return _PTR_NO_RAX_REG_mask;
  317 %}
  318 
  319 // Class for all pointer registers (excluding RAX, RBX, and RSP)
  320 reg_class ptr_no_rax_rbx_reg %{
  321   return _PTR_NO_RAX_RBX_REG_mask;
  322 %}
  323 
  324 // Class for all long registers (excluding RSP)
  325 reg_class long_reg %{
  326   return _LONG_REG_mask;
  327 %}
  328 
  329 // Class for all long registers (excluding RAX, RDX and RSP)
  330 reg_class long_no_rax_rdx_reg %{
  331   return _LONG_NO_RAX_RDX_REG_mask;
  332 %}
  333 
  334 // Class for all long registers (excluding RCX and RSP)
  335 reg_class long_no_rcx_reg %{
  336   return _LONG_NO_RCX_REG_mask;
  337 %}
  338 
  339 // Class for all long registers (excluding RBP and R13)
  340 reg_class long_no_rbp_r13_reg %{
  341   return _LONG_NO_RBP_R13_REG_mask;
  342 %}
  343 
  344 // Class for all int registers (excluding RSP)
  345 reg_class int_reg %{
  346   return _INT_REG_mask;
  347 %}
  348 
  349 // Class for all int registers (excluding RAX, RDX, and RSP)
  350 reg_class int_no_rax_rdx_reg %{
  351   return _INT_NO_RAX_RDX_REG_mask;
  352 %}
  353 
  354 // Class for all int registers (excluding RCX and RSP)
  355 reg_class int_no_rcx_reg %{
  356   return _INT_NO_RCX_REG_mask;
  357 %}
  358 
  359 // Class for all int registers (excluding RBP and R13)
  360 reg_class int_no_rbp_r13_reg %{
  361   return _INT_NO_RBP_R13_REG_mask;
  362 %}
  363 
  364 // Singleton class for RAX pointer register
  365 reg_class ptr_rax_reg(RAX, RAX_H);
  366 
  367 // Singleton class for RBX pointer register
  368 reg_class ptr_rbx_reg(RBX, RBX_H);
  369 
  370 // Singleton class for RSI pointer register
  371 reg_class ptr_rsi_reg(RSI, RSI_H);
  372 
  373 // Singleton class for RBP pointer register
  374 reg_class ptr_rbp_reg(RBP, RBP_H);
  375 
  376 // Singleton class for RDI pointer register
  377 reg_class ptr_rdi_reg(RDI, RDI_H);
  378 
  379 // Singleton class for stack pointer
  380 reg_class ptr_rsp_reg(RSP, RSP_H);
  381 
  382 // Singleton class for TLS pointer
  383 reg_class ptr_r15_reg(R15, R15_H);
  384 
  385 // Singleton class for RAX long register
  386 reg_class long_rax_reg(RAX, RAX_H);
  387 
  388 // Singleton class for RCX long register
  389 reg_class long_rcx_reg(RCX, RCX_H);
  390 
  391 // Singleton class for RDX long register
  392 reg_class long_rdx_reg(RDX, RDX_H);
  393 
  394 // Singleton class for R11 long register
  395 reg_class long_r11_reg(R11, R11_H);
  396 
  397 // Singleton class for RAX int register
  398 reg_class int_rax_reg(RAX);
  399 
  400 // Singleton class for RBX int register
  401 reg_class int_rbx_reg(RBX);
  402 
  403 // Singleton class for RCX int register
  404 reg_class int_rcx_reg(RCX);
  405 
  406 // Singleton class for RDX int register
  407 reg_class int_rdx_reg(RDX);
  408 
  409 // Singleton class for RDI int register
  410 reg_class int_rdi_reg(RDI);
  411 
  412 // Singleton class for instruction pointer
  413 // reg_class ip_reg(RIP);
  414 
  415 %}
  416 
  417 //----------SOURCE BLOCK-------------------------------------------------------
  418 // This is a block of C++ code which provides values, functions, and
  419 // definitions necessary in the rest of the architecture description
  420 
  421 source_hpp %{
  422 
  423 #include "peephole_x86_64.hpp"
  424 
  425 bool castLL_is_imm32(const Node* n);
  426 
  427 %}
  428 
  429 source %{
  430 
  431 bool castLL_is_imm32(const Node* n) {
  432   assert(n->is_CastLL(), "must be a CastLL");
  433   const TypeLong* t = n->bottom_type()->is_long();
  434   return (t->_lo == min_jlong || Assembler::is_simm32(t->_lo)) && (t->_hi == max_jlong || Assembler::is_simm32(t->_hi));
  435 }
  436 
  437 %}
  438 
  439 // Register masks
  440 source_hpp %{
  441 
  442 extern RegMask _ANY_REG_mask;
  443 extern RegMask _PTR_REG_mask;
  444 extern RegMask _PTR_REG_NO_RBP_mask;
  445 extern RegMask _PTR_NO_RAX_REG_mask;
  446 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
  447 extern RegMask _LONG_REG_mask;
  448 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
  449 extern RegMask _LONG_NO_RCX_REG_mask;
  450 extern RegMask _LONG_NO_RBP_R13_REG_mask;
  451 extern RegMask _INT_REG_mask;
  452 extern RegMask _INT_NO_RAX_RDX_REG_mask;
  453 extern RegMask _INT_NO_RCX_REG_mask;
  454 extern RegMask _INT_NO_RBP_R13_REG_mask;
  455 extern RegMask _FLOAT_REG_mask;
  456 
  457 extern RegMask _STACK_OR_PTR_REG_mask;
  458 extern RegMask _STACK_OR_LONG_REG_mask;
  459 extern RegMask _STACK_OR_INT_REG_mask;
  460 
  461 inline const RegMask& STACK_OR_PTR_REG_mask()  { return _STACK_OR_PTR_REG_mask;  }
  462 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
  463 inline const RegMask& STACK_OR_INT_REG_mask()  { return _STACK_OR_INT_REG_mask;  }
  464 
  465 %}
  466 
  467 source %{
  468 #define   RELOC_IMM64    Assembler::imm_operand
  469 #define   RELOC_DISP32   Assembler::disp32_operand
  470 
  471 #define __ masm->
  472 
  473 RegMask _ANY_REG_mask;
  474 RegMask _PTR_REG_mask;
  475 RegMask _PTR_REG_NO_RBP_mask;
  476 RegMask _PTR_NO_RAX_REG_mask;
  477 RegMask _PTR_NO_RAX_RBX_REG_mask;
  478 RegMask _LONG_REG_mask;
  479 RegMask _LONG_NO_RAX_RDX_REG_mask;
  480 RegMask _LONG_NO_RCX_REG_mask;
  481 RegMask _LONG_NO_RBP_R13_REG_mask;
  482 RegMask _INT_REG_mask;
  483 RegMask _INT_NO_RAX_RDX_REG_mask;
  484 RegMask _INT_NO_RCX_REG_mask;
  485 RegMask _INT_NO_RBP_R13_REG_mask;
  486 RegMask _FLOAT_REG_mask;
  487 RegMask _STACK_OR_PTR_REG_mask;
  488 RegMask _STACK_OR_LONG_REG_mask;
  489 RegMask _STACK_OR_INT_REG_mask;
  490 
  491 static bool need_r12_heapbase() {
  492   return UseCompressedOops;
  493 }
  494 
  495 void reg_mask_init() {
  496   constexpr Register egprs[] = {r16, r17, r18, r19, r20, r21, r22, r23, r24, r25, r26, r27, r28, r29, r30, r31};
  497 
  498   // _ALL_REG_mask is generated by adlc from the all_reg register class below.
  499   // We derive a number of subsets from it.
  500   _ANY_REG_mask = _ALL_REG_mask;
  501 
  502   if (PreserveFramePointer) {
  503     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  504     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  505   }
  506   if (need_r12_heapbase()) {
  507     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  508     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
  509   }
  510 
  511   _PTR_REG_mask = _ANY_REG_mask;
  512   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
  513   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
  514   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
  515   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
  516   if (!UseAPX) {
  517     for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
  518       _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
  519       _PTR_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()->next()));
  520     }
  521   }
  522 
  523   _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
  524   _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  525 
  526   _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
  527   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  528   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  529 
  530   _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
  531   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  532   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  533 
  534   _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
  535   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
  536   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
  537 
  538 
  539   _LONG_REG_mask = _PTR_REG_mask;
  540   _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
  541   _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  542 
  543   _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
  544   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  545   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  546   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  547   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
  548 
  549   _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
  550   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  551   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
  552 
  553   _LONG_NO_RBP_R13_REG_mask = _LONG_REG_mask;
  554   _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  555   _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  556   _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
  557   _LONG_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()->next()));
  558 
  559   _INT_REG_mask = _ALL_INT_REG_mask;
  560   if (!UseAPX) {
  561     for (uint i = 0; i < sizeof(egprs)/sizeof(Register); i++) {
  562       _INT_REG_mask.Remove(OptoReg::as_OptoReg(egprs[i]->as_VMReg()));
  563     }
  564   }
  565 
  566   if (PreserveFramePointer) {
  567     _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  568   }
  569   if (need_r12_heapbase()) {
  570     _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  571   }
  572 
  573   _STACK_OR_INT_REG_mask = _INT_REG_mask;
  574   _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  575 
  576   _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
  577   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  578   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  579 
  580   _INT_NO_RCX_REG_mask = _INT_REG_mask;
  581   _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  582 
  583   _INT_NO_RBP_R13_REG_mask = _INT_REG_mask;
  584   _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  585   _INT_NO_RBP_R13_REG_mask.Remove(OptoReg::as_OptoReg(r13->as_VMReg()));
  586 
  587   // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
  588   // from the float_reg_legacy/float_reg_evex register class.
  589   _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
  590 }
  591 
  592 static bool generate_vzeroupper(Compile* C) {
  593   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
  594 }
  595 
  596 static int clear_avx_size() {
  597   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
  598 }
  599 
  600 // !!!!! Special hack to get all types of calls to specify the byte offset
  601 //       from the start of the call to the point where the return address
  602 //       will point.
  603 int MachCallStaticJavaNode::ret_addr_offset()
  604 {
  605   int offset = 5; // 5 bytes from start of call to where return address points
  606   offset += clear_avx_size();
  607   return offset;
  608 }
  609 
  610 int MachCallDynamicJavaNode::ret_addr_offset()
  611 {
  612   int offset = 15; // 15 bytes from start of call to where return address points
  613   offset += clear_avx_size();
  614   return offset;
  615 }
  616 
  617 int MachCallRuntimeNode::ret_addr_offset() {
  618   int offset = 13; // movq r10,#addr; callq (r10)
  619   if (this->ideal_Opcode() != Op_CallLeafVector) {
  620     offset += clear_avx_size();
  621   }
  622   return offset;
  623 }
  624 //
  625 // Compute padding required for nodes which need alignment
  626 //
  627 
  628 // The address of the call instruction needs to be 4-byte aligned to
  629 // ensure that it does not span a cache line so that it can be patched.
  630 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
  631 {
  632   current_offset += clear_avx_size(); // skip vzeroupper
  633   current_offset += 1; // skip call opcode byte
  634   return align_up(current_offset, alignment_required()) - current_offset;
  635 }
  636 
  637 // The address of the call instruction needs to be 4-byte aligned to
  638 // ensure that it does not span a cache line so that it can be patched.
  639 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
  640 {
  641   current_offset += clear_avx_size(); // skip vzeroupper
  642   current_offset += 11; // skip movq instruction + call opcode byte
  643   return align_up(current_offset, alignment_required()) - current_offset;
  644 }
  645 
  646 // This could be in MacroAssembler but it's fairly C2 specific
  647 static void emit_cmpfp_fixup(MacroAssembler* masm) {
  648   Label exit;
  649   __ jccb(Assembler::noParity, exit);
  650   __ pushf();
  651   //
  652   // comiss/ucomiss instructions set ZF,PF,CF flags and
  653   // zero OF,AF,SF for NaN values.
  654   // Fixup flags by zeroing ZF,PF so that compare of NaN
  655   // values returns 'less than' result (CF is set).
  656   // Leave the rest of flags unchanged.
  657   //
  658   //    7 6 5 4 3 2 1 0
  659   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
  660   //    0 0 1 0 1 0 1 1   (0x2B)
  661   //
  662   __ andq(Address(rsp, 0), 0xffffff2b);
  663   __ popf();
  664   __ bind(exit);
  665 }
  666 
  667 static void emit_cmpfp3(MacroAssembler* masm, Register dst) {
  668   Label done;
  669   __ movl(dst, -1);
  670   __ jcc(Assembler::parity, done);
  671   __ jcc(Assembler::below, done);
  672   __ setcc(Assembler::notEqual, dst);
  673   __ bind(done);
  674 }
  675 
  676 // Math.min()    # Math.max()
  677 // --------------------------
  678 // ucomis[s/d]   #
  679 // ja   -> b     # a
  680 // jp   -> NaN   # NaN
  681 // jb   -> a     # b
  682 // je            #
  683 // |-jz -> a | b # a & b
  684 // |    -> a     #
  685 static void emit_fp_min_max(MacroAssembler* masm, XMMRegister dst,
  686                             XMMRegister a, XMMRegister b,
  687                             XMMRegister xmmt, Register rt,
  688                             bool min, bool single) {
  689 
  690   Label nan, zero, below, above, done;
  691 
  692   if (single)
  693     __ ucomiss(a, b);
  694   else
  695     __ ucomisd(a, b);
  696 
  697   if (dst->encoding() != (min ? b : a)->encoding())
  698     __ jccb(Assembler::above, above); // CF=0 & ZF=0
  699   else
  700     __ jccb(Assembler::above, done);
  701 
  702   __ jccb(Assembler::parity, nan);  // PF=1
  703   __ jccb(Assembler::below, below); // CF=1
  704 
  705   // equal
  706   __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
  707   if (single) {
  708     __ ucomiss(a, xmmt);
  709     __ jccb(Assembler::equal, zero);
  710 
  711     __ movflt(dst, a);
  712     __ jmp(done);
  713   }
  714   else {
  715     __ ucomisd(a, xmmt);
  716     __ jccb(Assembler::equal, zero);
  717 
  718     __ movdbl(dst, a);
  719     __ jmp(done);
  720   }
  721 
  722   __ bind(zero);
  723   if (min)
  724     __ vpor(dst, a, b, Assembler::AVX_128bit);
  725   else
  726     __ vpand(dst, a, b, Assembler::AVX_128bit);
  727 
  728   __ jmp(done);
  729 
  730   __ bind(above);
  731   if (single)
  732     __ movflt(dst, min ? b : a);
  733   else
  734     __ movdbl(dst, min ? b : a);
  735 
  736   __ jmp(done);
  737 
  738   __ bind(nan);
  739   if (single) {
  740     __ movl(rt, 0x7fc00000); // Float.NaN
  741     __ movdl(dst, rt);
  742   }
  743   else {
  744     __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
  745     __ movdq(dst, rt);
  746   }
  747   __ jmp(done);
  748 
  749   __ bind(below);
  750   if (single)
  751     __ movflt(dst, min ? a : b);
  752   else
  753     __ movdbl(dst, min ? a : b);
  754 
  755   __ bind(done);
  756 }
  757 
  758 //=============================================================================
  759 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
  760 
  761 int ConstantTable::calculate_table_base_offset() const {
  762   return 0;  // absolute addressing, no offset
  763 }
  764 
  765 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
  766 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
  767   ShouldNotReachHere();
  768 }
  769 
  770 void MachConstantBaseNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const {
  771   // Empty encoding
  772 }
  773 
  774 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
  775   return 0;
  776 }
  777 
  778 #ifndef PRODUCT
  779 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  780   st->print("# MachConstantBaseNode (empty encoding)");
  781 }
  782 #endif
  783 
  784 
  785 //=============================================================================
  786 #ifndef PRODUCT
  787 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  788   Compile* C = ra_->C;
  789 
  790   int framesize = C->output()->frame_size_in_bytes();
  791   int bangsize = C->output()->bang_size_in_bytes();
  792   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  793   // Remove wordSize for return addr which is already pushed.
  794   framesize -= wordSize;
  795 
  796   if (C->output()->need_stack_bang(bangsize)) {
  797     framesize -= wordSize;
  798     st->print("# stack bang (%d bytes)", bangsize);
  799     st->print("\n\t");
  800     st->print("pushq   rbp\t# Save rbp");
  801     if (PreserveFramePointer) {
  802         st->print("\n\t");
  803         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  804     }
  805     if (framesize) {
  806       st->print("\n\t");
  807       st->print("subq    rsp, #%d\t# Create frame",framesize);
  808     }
  809   } else {
  810     st->print("subq    rsp, #%d\t# Create frame",framesize);
  811     st->print("\n\t");
  812     framesize -= wordSize;
  813     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
  814     if (PreserveFramePointer) {
  815       st->print("\n\t");
  816       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  817       if (framesize > 0) {
  818         st->print("\n\t");
  819         st->print("addq    rbp, #%d", framesize);
  820       }
  821     }
  822   }
  823 
  824   if (VerifyStackAtCalls) {
  825     st->print("\n\t");
  826     framesize -= wordSize;
  827     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
  828 #ifdef ASSERT
  829     st->print("\n\t");
  830     st->print("# stack alignment check");
  831 #endif
  832   }
  833   if (C->stub_function() != nullptr) {
  834     st->print("\n\t");
  835     st->print("cmpl    [r15_thread + #disarmed_guard_value_offset], #disarmed_guard_value\t");
  836     st->print("\n\t");
  837     st->print("je      fast_entry\t");
  838     st->print("\n\t");
  839     st->print("call    #nmethod_entry_barrier_stub\t");
  840     st->print("\n\tfast_entry:");
  841   }
  842   st->cr();
  843 }
  844 #endif
  845 
  846 void MachPrologNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
  847   Compile* C = ra_->C;
  848 
  849   int framesize = C->output()->frame_size_in_bytes();
  850   int bangsize = C->output()->bang_size_in_bytes();
  851 
  852   if (C->clinit_barrier_on_entry()) {
  853     assert(VM_Version::supports_fast_class_init_checks(), "sanity");
  854     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
  855 
  856     Label L_skip_barrier;
  857     Register klass = rscratch1;
  858 
  859     __ mov_metadata(klass, C->method()->holder()->constant_encoding());
  860     __ clinit_barrier(klass, &L_skip_barrier /*L_fast_path*/);
  861 
  862     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
  863 
  864     __ bind(L_skip_barrier);
  865   }
  866 
  867   __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != nullptr);
  868 
  869   C->output()->set_frame_complete(__ offset());
  870 
  871   if (C->has_mach_constant_base_node()) {
  872     // NOTE: We set the table base offset here because users might be
  873     // emitted before MachConstantBaseNode.
  874     ConstantTable& constant_table = C->output()->constant_table();
  875     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
  876   }
  877 }
  878 
  879 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
  880 {
  881   return MachNode::size(ra_); // too many variables; just compute it
  882                               // the hard way
  883 }
  884 
  885 int MachPrologNode::reloc() const
  886 {
  887   return 0; // a large enough number
  888 }
  889 
  890 //=============================================================================
  891 #ifndef PRODUCT
  892 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
  893 {
  894   Compile* C = ra_->C;
  895   if (generate_vzeroupper(C)) {
  896     st->print("vzeroupper");
  897     st->cr(); st->print("\t");
  898   }
  899 
  900   int framesize = C->output()->frame_size_in_bytes();
  901   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  902   // Remove word for return adr already pushed
  903   // and RBP
  904   framesize -= 2*wordSize;
  905 
  906   if (framesize) {
  907     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
  908     st->print("\t");
  909   }
  910 
  911   st->print_cr("popq    rbp");
  912   if (do_polling() && C->is_method_compilation()) {
  913     st->print("\t");
  914     st->print_cr("cmpq    rsp, poll_offset[r15_thread] \n\t"
  915                  "ja      #safepoint_stub\t"
  916                  "# Safepoint: poll for GC");
  917   }
  918 }
  919 #endif
  920 
  921 void MachEpilogNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
  922 {
  923   Compile* C = ra_->C;
  924 
  925   if (generate_vzeroupper(C)) {
  926     // Clear upper bits of YMM registers when current compiled code uses
  927     // wide vectors to avoid AVX <-> SSE transition penalty during call.
  928     __ vzeroupper();
  929   }
  930 
  931   int framesize = C->output()->frame_size_in_bytes();
  932   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  933   // Remove word for return adr already pushed
  934   // and RBP
  935   framesize -= 2*wordSize;
  936 
  937   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
  938 
  939   if (framesize) {
  940     __ addq(rsp, framesize);
  941   }
  942 
  943   __ popq(rbp);
  944 
  945   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
  946     __ reserved_stack_check();
  947   }
  948 
  949   if (do_polling() && C->is_method_compilation()) {
  950     Label dummy_label;
  951     Label* code_stub = &dummy_label;
  952     if (!C->output()->in_scratch_emit_size()) {
  953       C2SafepointPollStub* stub = new (C->comp_arena()) C2SafepointPollStub(__ offset());
  954       C->output()->add_stub(stub);
  955       code_stub = &stub->entry();
  956     }
  957     __ relocate(relocInfo::poll_return_type);
  958     __ safepoint_poll(*code_stub, true /* at_return */, true /* in_nmethod */);
  959   }
  960 }
  961 
  962 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
  963 {
  964   return MachNode::size(ra_); // too many variables; just compute it
  965                               // the hard way
  966 }
  967 
  968 int MachEpilogNode::reloc() const
  969 {
  970   return 2; // a large enough number
  971 }
  972 
  973 const Pipeline* MachEpilogNode::pipeline() const
  974 {
  975   return MachNode::pipeline_class();
  976 }
  977 
  978 //=============================================================================
  979 
  980 enum RC {
  981   rc_bad,
  982   rc_int,
  983   rc_kreg,
  984   rc_float,
  985   rc_stack
  986 };
  987 
  988 static enum RC rc_class(OptoReg::Name reg)
  989 {
  990   if( !OptoReg::is_valid(reg)  ) return rc_bad;
  991 
  992   if (OptoReg::is_stack(reg)) return rc_stack;
  993 
  994   VMReg r = OptoReg::as_VMReg(reg);
  995 
  996   if (r->is_Register()) return rc_int;
  997 
  998   if (r->is_KRegister()) return rc_kreg;
  999 
 1000   assert(r->is_XMMRegister(), "must be");
 1001   return rc_float;
 1002 }
 1003 
 1004 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 1005 static void vec_mov_helper(C2_MacroAssembler *masm, int src_lo, int dst_lo,
 1006                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 1007 
 1008 void vec_spill_helper(C2_MacroAssembler *masm, bool is_load,
 1009                      int stack_offset, int reg, uint ireg, outputStream* st);
 1010 
 1011 static void vec_stack_to_stack_helper(C2_MacroAssembler *masm, int src_offset,
 1012                                       int dst_offset, uint ireg, outputStream* st) {
 1013   if (masm) {
 1014     switch (ireg) {
 1015     case Op_VecS:
 1016       __ movq(Address(rsp, -8), rax);
 1017       __ movl(rax, Address(rsp, src_offset));
 1018       __ movl(Address(rsp, dst_offset), rax);
 1019       __ movq(rax, Address(rsp, -8));
 1020       break;
 1021     case Op_VecD:
 1022       __ pushq(Address(rsp, src_offset));
 1023       __ popq (Address(rsp, dst_offset));
 1024       break;
 1025     case Op_VecX:
 1026       __ pushq(Address(rsp, src_offset));
 1027       __ popq (Address(rsp, dst_offset));
 1028       __ pushq(Address(rsp, src_offset+8));
 1029       __ popq (Address(rsp, dst_offset+8));
 1030       break;
 1031     case Op_VecY:
 1032       __ vmovdqu(Address(rsp, -32), xmm0);
 1033       __ vmovdqu(xmm0, Address(rsp, src_offset));
 1034       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 1035       __ vmovdqu(xmm0, Address(rsp, -32));
 1036       break;
 1037     case Op_VecZ:
 1038       __ evmovdquq(Address(rsp, -64), xmm0, 2);
 1039       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
 1040       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
 1041       __ evmovdquq(xmm0, Address(rsp, -64), 2);
 1042       break;
 1043     default:
 1044       ShouldNotReachHere();
 1045     }
 1046 #ifndef PRODUCT
 1047   } else {
 1048     switch (ireg) {
 1049     case Op_VecS:
 1050       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1051                 "movl    rax, [rsp + #%d]\n\t"
 1052                 "movl    [rsp + #%d], rax\n\t"
 1053                 "movq    rax, [rsp - #8]",
 1054                 src_offset, dst_offset);
 1055       break;
 1056     case Op_VecD:
 1057       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1058                 "popq    [rsp + #%d]",
 1059                 src_offset, dst_offset);
 1060       break;
 1061      case Op_VecX:
 1062       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
 1063                 "popq    [rsp + #%d]\n\t"
 1064                 "pushq   [rsp + #%d]\n\t"
 1065                 "popq    [rsp + #%d]",
 1066                 src_offset, dst_offset, src_offset+8, dst_offset+8);
 1067       break;
 1068     case Op_VecY:
 1069       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 1070                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1071                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1072                 "vmovdqu xmm0, [rsp - #32]",
 1073                 src_offset, dst_offset);
 1074       break;
 1075     case Op_VecZ:
 1076       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
 1077                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1078                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1079                 "vmovdqu xmm0, [rsp - #64]",
 1080                 src_offset, dst_offset);
 1081       break;
 1082     default:
 1083       ShouldNotReachHere();
 1084     }
 1085 #endif
 1086   }
 1087 }
 1088 
 1089 uint MachSpillCopyNode::implementation(C2_MacroAssembler* masm,
 1090                                        PhaseRegAlloc* ra_,
 1091                                        bool do_size,
 1092                                        outputStream* st) const {
 1093   assert(masm != nullptr || st  != nullptr, "sanity");
 1094   // Get registers to move
 1095   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 1096   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 1097   OptoReg::Name dst_second = ra_->get_reg_second(this);
 1098   OptoReg::Name dst_first = ra_->get_reg_first(this);
 1099 
 1100   enum RC src_second_rc = rc_class(src_second);
 1101   enum RC src_first_rc = rc_class(src_first);
 1102   enum RC dst_second_rc = rc_class(dst_second);
 1103   enum RC dst_first_rc = rc_class(dst_first);
 1104 
 1105   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
 1106          "must move at least 1 register" );
 1107 
 1108   if (src_first == dst_first && src_second == dst_second) {
 1109     // Self copy, no move
 1110     return 0;
 1111   }
 1112   if (bottom_type()->isa_vect() != nullptr && bottom_type()->isa_vectmask() == nullptr) {
 1113     uint ireg = ideal_reg();
 1114     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
 1115     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
 1116     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
 1117       // mem -> mem
 1118       int src_offset = ra_->reg2offset(src_first);
 1119       int dst_offset = ra_->reg2offset(dst_first);
 1120       vec_stack_to_stack_helper(masm, src_offset, dst_offset, ireg, st);
 1121     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
 1122       vec_mov_helper(masm, src_first, dst_first, src_second, dst_second, ireg, st);
 1123     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
 1124       int stack_offset = ra_->reg2offset(dst_first);
 1125       vec_spill_helper(masm, false, stack_offset, src_first, ireg, st);
 1126     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
 1127       int stack_offset = ra_->reg2offset(src_first);
 1128       vec_spill_helper(masm, true,  stack_offset, dst_first, ireg, st);
 1129     } else {
 1130       ShouldNotReachHere();
 1131     }
 1132     return 0;
 1133   }
 1134   if (src_first_rc == rc_stack) {
 1135     // mem ->
 1136     if (dst_first_rc == rc_stack) {
 1137       // mem -> mem
 1138       assert(src_second != dst_first, "overlap");
 1139       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1140           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1141         // 64-bit
 1142         int src_offset = ra_->reg2offset(src_first);
 1143         int dst_offset = ra_->reg2offset(dst_first);
 1144         if (masm) {
 1145           __ pushq(Address(rsp, src_offset));
 1146           __ popq (Address(rsp, dst_offset));
 1147 #ifndef PRODUCT
 1148         } else {
 1149           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1150                     "popq    [rsp + #%d]",
 1151                      src_offset, dst_offset);
 1152 #endif
 1153         }
 1154       } else {
 1155         // 32-bit
 1156         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1157         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1158         // No pushl/popl, so:
 1159         int src_offset = ra_->reg2offset(src_first);
 1160         int dst_offset = ra_->reg2offset(dst_first);
 1161         if (masm) {
 1162           __ movq(Address(rsp, -8), rax);
 1163           __ movl(rax, Address(rsp, src_offset));
 1164           __ movl(Address(rsp, dst_offset), rax);
 1165           __ movq(rax, Address(rsp, -8));
 1166 #ifndef PRODUCT
 1167         } else {
 1168           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1169                     "movl    rax, [rsp + #%d]\n\t"
 1170                     "movl    [rsp + #%d], rax\n\t"
 1171                     "movq    rax, [rsp - #8]",
 1172                      src_offset, dst_offset);
 1173 #endif
 1174         }
 1175       }
 1176       return 0;
 1177     } else if (dst_first_rc == rc_int) {
 1178       // mem -> gpr
 1179       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1180           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1181         // 64-bit
 1182         int offset = ra_->reg2offset(src_first);
 1183         if (masm) {
 1184           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1185 #ifndef PRODUCT
 1186         } else {
 1187           st->print("movq    %s, [rsp + #%d]\t# spill",
 1188                      Matcher::regName[dst_first],
 1189                      offset);
 1190 #endif
 1191         }
 1192       } else {
 1193         // 32-bit
 1194         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1195         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1196         int offset = ra_->reg2offset(src_first);
 1197         if (masm) {
 1198           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1199 #ifndef PRODUCT
 1200         } else {
 1201           st->print("movl    %s, [rsp + #%d]\t# spill",
 1202                      Matcher::regName[dst_first],
 1203                      offset);
 1204 #endif
 1205         }
 1206       }
 1207       return 0;
 1208     } else if (dst_first_rc == rc_float) {
 1209       // mem-> xmm
 1210       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1211           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1212         // 64-bit
 1213         int offset = ra_->reg2offset(src_first);
 1214         if (masm) {
 1215           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1216 #ifndef PRODUCT
 1217         } else {
 1218           st->print("%s  %s, [rsp + #%d]\t# spill",
 1219                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
 1220                      Matcher::regName[dst_first],
 1221                      offset);
 1222 #endif
 1223         }
 1224       } else {
 1225         // 32-bit
 1226         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1227         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1228         int offset = ra_->reg2offset(src_first);
 1229         if (masm) {
 1230           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1231 #ifndef PRODUCT
 1232         } else {
 1233           st->print("movss   %s, [rsp + #%d]\t# spill",
 1234                      Matcher::regName[dst_first],
 1235                      offset);
 1236 #endif
 1237         }
 1238       }
 1239       return 0;
 1240     } else if (dst_first_rc == rc_kreg) {
 1241       // mem -> kreg
 1242       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1243           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1244         // 64-bit
 1245         int offset = ra_->reg2offset(src_first);
 1246         if (masm) {
 1247           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1248 #ifndef PRODUCT
 1249         } else {
 1250           st->print("kmovq   %s, [rsp + #%d]\t# spill",
 1251                      Matcher::regName[dst_first],
 1252                      offset);
 1253 #endif
 1254         }
 1255       }
 1256       return 0;
 1257     }
 1258   } else if (src_first_rc == rc_int) {
 1259     // gpr ->
 1260     if (dst_first_rc == rc_stack) {
 1261       // gpr -> mem
 1262       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1263           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1264         // 64-bit
 1265         int offset = ra_->reg2offset(dst_first);
 1266         if (masm) {
 1267           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1268 #ifndef PRODUCT
 1269         } else {
 1270           st->print("movq    [rsp + #%d], %s\t# spill",
 1271                      offset,
 1272                      Matcher::regName[src_first]);
 1273 #endif
 1274         }
 1275       } else {
 1276         // 32-bit
 1277         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1278         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1279         int offset = ra_->reg2offset(dst_first);
 1280         if (masm) {
 1281           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1282 #ifndef PRODUCT
 1283         } else {
 1284           st->print("movl    [rsp + #%d], %s\t# spill",
 1285                      offset,
 1286                      Matcher::regName[src_first]);
 1287 #endif
 1288         }
 1289       }
 1290       return 0;
 1291     } else if (dst_first_rc == rc_int) {
 1292       // gpr -> gpr
 1293       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1294           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1295         // 64-bit
 1296         if (masm) {
 1297           __ movq(as_Register(Matcher::_regEncode[dst_first]),
 1298                   as_Register(Matcher::_regEncode[src_first]));
 1299 #ifndef PRODUCT
 1300         } else {
 1301           st->print("movq    %s, %s\t# spill",
 1302                      Matcher::regName[dst_first],
 1303                      Matcher::regName[src_first]);
 1304 #endif
 1305         }
 1306         return 0;
 1307       } else {
 1308         // 32-bit
 1309         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1310         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1311         if (masm) {
 1312           __ movl(as_Register(Matcher::_regEncode[dst_first]),
 1313                   as_Register(Matcher::_regEncode[src_first]));
 1314 #ifndef PRODUCT
 1315         } else {
 1316           st->print("movl    %s, %s\t# spill",
 1317                      Matcher::regName[dst_first],
 1318                      Matcher::regName[src_first]);
 1319 #endif
 1320         }
 1321         return 0;
 1322       }
 1323     } else if (dst_first_rc == rc_float) {
 1324       // gpr -> xmm
 1325       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1326           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1327         // 64-bit
 1328         if (masm) {
 1329           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1330 #ifndef PRODUCT
 1331         } else {
 1332           st->print("movdq   %s, %s\t# spill",
 1333                      Matcher::regName[dst_first],
 1334                      Matcher::regName[src_first]);
 1335 #endif
 1336         }
 1337       } else {
 1338         // 32-bit
 1339         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1340         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1341         if (masm) {
 1342           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1343 #ifndef PRODUCT
 1344         } else {
 1345           st->print("movdl   %s, %s\t# spill",
 1346                      Matcher::regName[dst_first],
 1347                      Matcher::regName[src_first]);
 1348 #endif
 1349         }
 1350       }
 1351       return 0;
 1352     } else if (dst_first_rc == rc_kreg) {
 1353       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1354           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1355         // 64-bit
 1356         if (masm) {
 1357           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1358   #ifndef PRODUCT
 1359         } else {
 1360            st->print("kmovq   %s, %s\t# spill",
 1361                        Matcher::regName[dst_first],
 1362                        Matcher::regName[src_first]);
 1363   #endif
 1364         }
 1365       }
 1366       Unimplemented();
 1367       return 0;
 1368     }
 1369   } else if (src_first_rc == rc_float) {
 1370     // xmm ->
 1371     if (dst_first_rc == rc_stack) {
 1372       // xmm -> mem
 1373       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1374           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1375         // 64-bit
 1376         int offset = ra_->reg2offset(dst_first);
 1377         if (masm) {
 1378           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1379 #ifndef PRODUCT
 1380         } else {
 1381           st->print("movsd   [rsp + #%d], %s\t# spill",
 1382                      offset,
 1383                      Matcher::regName[src_first]);
 1384 #endif
 1385         }
 1386       } else {
 1387         // 32-bit
 1388         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1389         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1390         int offset = ra_->reg2offset(dst_first);
 1391         if (masm) {
 1392           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1393 #ifndef PRODUCT
 1394         } else {
 1395           st->print("movss   [rsp + #%d], %s\t# spill",
 1396                      offset,
 1397                      Matcher::regName[src_first]);
 1398 #endif
 1399         }
 1400       }
 1401       return 0;
 1402     } else if (dst_first_rc == rc_int) {
 1403       // xmm -> gpr
 1404       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1405           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1406         // 64-bit
 1407         if (masm) {
 1408           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1409 #ifndef PRODUCT
 1410         } else {
 1411           st->print("movdq   %s, %s\t# spill",
 1412                      Matcher::regName[dst_first],
 1413                      Matcher::regName[src_first]);
 1414 #endif
 1415         }
 1416       } else {
 1417         // 32-bit
 1418         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1419         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1420         if (masm) {
 1421           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1422 #ifndef PRODUCT
 1423         } else {
 1424           st->print("movdl   %s, %s\t# spill",
 1425                      Matcher::regName[dst_first],
 1426                      Matcher::regName[src_first]);
 1427 #endif
 1428         }
 1429       }
 1430       return 0;
 1431     } else if (dst_first_rc == rc_float) {
 1432       // xmm -> xmm
 1433       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1434           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1435         // 64-bit
 1436         if (masm) {
 1437           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1438 #ifndef PRODUCT
 1439         } else {
 1440           st->print("%s  %s, %s\t# spill",
 1441                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
 1442                      Matcher::regName[dst_first],
 1443                      Matcher::regName[src_first]);
 1444 #endif
 1445         }
 1446       } else {
 1447         // 32-bit
 1448         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1449         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1450         if (masm) {
 1451           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1452 #ifndef PRODUCT
 1453         } else {
 1454           st->print("%s  %s, %s\t# spill",
 1455                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
 1456                      Matcher::regName[dst_first],
 1457                      Matcher::regName[src_first]);
 1458 #endif
 1459         }
 1460       }
 1461       return 0;
 1462     } else if (dst_first_rc == rc_kreg) {
 1463       assert(false, "Illegal spilling");
 1464       return 0;
 1465     }
 1466   } else if (src_first_rc == rc_kreg) {
 1467     if (dst_first_rc == rc_stack) {
 1468       // mem -> kreg
 1469       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1470           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1471         // 64-bit
 1472         int offset = ra_->reg2offset(dst_first);
 1473         if (masm) {
 1474           __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
 1475 #ifndef PRODUCT
 1476         } else {
 1477           st->print("kmovq   [rsp + #%d] , %s\t# spill",
 1478                      offset,
 1479                      Matcher::regName[src_first]);
 1480 #endif
 1481         }
 1482       }
 1483       return 0;
 1484     } else if (dst_first_rc == rc_int) {
 1485       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1486           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1487         // 64-bit
 1488         if (masm) {
 1489           __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1490 #ifndef PRODUCT
 1491         } else {
 1492          st->print("kmovq   %s, %s\t# spill",
 1493                      Matcher::regName[dst_first],
 1494                      Matcher::regName[src_first]);
 1495 #endif
 1496         }
 1497       }
 1498       Unimplemented();
 1499       return 0;
 1500     } else if (dst_first_rc == rc_kreg) {
 1501       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1502           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1503         // 64-bit
 1504         if (masm) {
 1505           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1506 #ifndef PRODUCT
 1507         } else {
 1508          st->print("kmovq   %s, %s\t# spill",
 1509                      Matcher::regName[dst_first],
 1510                      Matcher::regName[src_first]);
 1511 #endif
 1512         }
 1513       }
 1514       return 0;
 1515     } else if (dst_first_rc == rc_float) {
 1516       assert(false, "Illegal spill");
 1517       return 0;
 1518     }
 1519   }
 1520 
 1521   assert(0," foo ");
 1522   Unimplemented();
 1523   return 0;
 1524 }
 1525 
 1526 #ifndef PRODUCT
 1527 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
 1528   implementation(nullptr, ra_, false, st);
 1529 }
 1530 #endif
 1531 
 1532 void MachSpillCopyNode::emit(C2_MacroAssembler *masm, PhaseRegAlloc *ra_) const {
 1533   implementation(masm, ra_, false, nullptr);
 1534 }
 1535 
 1536 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1537   return MachNode::size(ra_);
 1538 }
 1539 
 1540 //=============================================================================
 1541 #ifndef PRODUCT
 1542 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1543 {
 1544   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1545   int reg = ra_->get_reg_first(this);
 1546   st->print("leaq    %s, [rsp + #%d]\t# box lock",
 1547             Matcher::regName[reg], offset);
 1548 }
 1549 #endif
 1550 
 1551 void BoxLockNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
 1552 {
 1553   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1554   int reg = ra_->get_encode(this);
 1555 
 1556   __ lea(as_Register(reg), Address(rsp, offset));
 1557 }
 1558 
 1559 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
 1560 {
 1561   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1562   if (ra_->get_encode(this) > 15) {
 1563     return (offset < 0x80) ? 6 : 9; // REX2
 1564   } else {
 1565     return (offset < 0x80) ? 5 : 8; // REX
 1566   }
 1567 }
 1568 
 1569 //=============================================================================
 1570 #ifndef PRODUCT
 1571 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1572 {
 1573   if (UseCompressedClassPointers) {
 1574     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1575     st->print_cr("\tcmpl    rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
 1576   } else {
 1577     st->print_cr("movq    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1578     st->print_cr("\tcmpq    rscratch1, [rax + CompiledICData::speculated_klass_offset()]\t # Inline cache check");
 1579   }
 1580   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
 1581 }
 1582 #endif
 1583 
 1584 void MachUEPNode::emit(C2_MacroAssembler* masm, PhaseRegAlloc* ra_) const
 1585 {
 1586   __ ic_check(InteriorEntryAlignment);
 1587 }
 1588 
 1589 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1590 {
 1591   return MachNode::size(ra_); // too many variables; just compute it
 1592                               // the hard way
 1593 }
 1594 
 1595 
 1596 //=============================================================================
 1597 
 1598 bool Matcher::supports_vector_calling_convention(void) {
 1599   return EnableVectorSupport;
 1600 }
 1601 
 1602 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1603   assert(EnableVectorSupport, "sanity");
 1604   int lo = XMM0_num;
 1605   int hi = XMM0b_num;
 1606   if (ideal_reg == Op_VecX) hi = XMM0d_num;
 1607   else if (ideal_reg == Op_VecY) hi = XMM0h_num;
 1608   else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
 1609   return OptoRegPair(hi, lo);
 1610 }
 1611 
 1612 // Is this branch offset short enough that a short branch can be used?
 1613 //
 1614 // NOTE: If the platform does not provide any short branch variants, then
 1615 //       this method should return false for offset 0.
 1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1617   // The passed offset is relative to address of the branch.
 1618   // On 86 a branch displacement is calculated relative to address
 1619   // of a next instruction.
 1620   offset -= br_size;
 1621 
 1622   // the short version of jmpConUCF2 contains multiple branches,
 1623   // making the reach slightly less
 1624   if (rule == jmpConUCF2_rule)
 1625     return (-126 <= offset && offset <= 125);
 1626   return (-128 <= offset && offset <= 127);
 1627 }
 1628 
 1629 // Return whether or not this register is ever used as an argument.
 1630 // This function is used on startup to build the trampoline stubs in
 1631 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1632 // call in the trampoline, and arguments in those registers not be
 1633 // available to the callee.
 1634 bool Matcher::can_be_java_arg(int reg)
 1635 {
 1636   return
 1637     reg ==  RDI_num || reg == RDI_H_num ||
 1638     reg ==  RSI_num || reg == RSI_H_num ||
 1639     reg ==  RDX_num || reg == RDX_H_num ||
 1640     reg ==  RCX_num || reg == RCX_H_num ||
 1641     reg ==   R8_num || reg ==  R8_H_num ||
 1642     reg ==   R9_num || reg ==  R9_H_num ||
 1643     reg ==  R12_num || reg == R12_H_num ||
 1644     reg == XMM0_num || reg == XMM0b_num ||
 1645     reg == XMM1_num || reg == XMM1b_num ||
 1646     reg == XMM2_num || reg == XMM2b_num ||
 1647     reg == XMM3_num || reg == XMM3b_num ||
 1648     reg == XMM4_num || reg == XMM4b_num ||
 1649     reg == XMM5_num || reg == XMM5b_num ||
 1650     reg == XMM6_num || reg == XMM6b_num ||
 1651     reg == XMM7_num || reg == XMM7b_num;
 1652 }
 1653 
 1654 bool Matcher::is_spillable_arg(int reg)
 1655 {
 1656   return can_be_java_arg(reg);
 1657 }
 1658 
 1659 uint Matcher::int_pressure_limit()
 1660 {
 1661   return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
 1662 }
 1663 
 1664 uint Matcher::float_pressure_limit()
 1665 {
 1666   // After experiment around with different values, the following default threshold
 1667   // works best for LCM's register pressure scheduling on x64.
 1668   uint dec_count  = VM_Version::supports_evex() ? 4 : 2;
 1669   uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
 1670   return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
 1671 }
 1672 
 1673 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
 1674   // In 64 bit mode a code which use multiply when
 1675   // devisor is constant is faster than hardware
 1676   // DIV instruction (it uses MulHiL).
 1677   return false;
 1678 }
 1679 
 1680 // Register for DIVI projection of divmodI
 1681 RegMask Matcher::divI_proj_mask() {
 1682   return INT_RAX_REG_mask();
 1683 }
 1684 
 1685 // Register for MODI projection of divmodI
 1686 RegMask Matcher::modI_proj_mask() {
 1687   return INT_RDX_REG_mask();
 1688 }
 1689 
 1690 // Register for DIVL projection of divmodL
 1691 RegMask Matcher::divL_proj_mask() {
 1692   return LONG_RAX_REG_mask();
 1693 }
 1694 
 1695 // Register for MODL projection of divmodL
 1696 RegMask Matcher::modL_proj_mask() {
 1697   return LONG_RDX_REG_mask();
 1698 }
 1699 
 1700 // Register for saving SP into on method handle invokes. Not used on x86_64.
 1701 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1702     return NO_REG_mask();
 1703 }
 1704 
 1705 %}
 1706 
 1707 //----------ENCODING BLOCK-----------------------------------------------------
 1708 // This block specifies the encoding classes used by the compiler to
 1709 // output byte streams.  Encoding classes are parameterized macros
 1710 // used by Machine Instruction Nodes in order to generate the bit
 1711 // encoding of the instruction.  Operands specify their base encoding
 1712 // interface with the interface keyword.  There are currently
 1713 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 1714 // COND_INTER.  REG_INTER causes an operand to generate a function
 1715 // which returns its register number when queried.  CONST_INTER causes
 1716 // an operand to generate a function which returns the value of the
 1717 // constant when queried.  MEMORY_INTER causes an operand to generate
 1718 // four functions which return the Base Register, the Index Register,
 1719 // the Scale Value, and the Offset Value of the operand when queried.
 1720 // COND_INTER causes an operand to generate six functions which return
 1721 // the encoding code (ie - encoding bits for the instruction)
 1722 // associated with each basic boolean condition for a conditional
 1723 // instruction.
 1724 //
 1725 // Instructions specify two basic values for encoding.  Again, a
 1726 // function is available to check if the constant displacement is an
 1727 // oop. They use the ins_encode keyword to specify their encoding
 1728 // classes (which must be a sequence of enc_class names, and their
 1729 // parameters, specified in the encoding block), and they use the
 1730 // opcode keyword to specify, in order, their primary, secondary, and
 1731 // tertiary opcode.  Only the opcode sections which a particular
 1732 // instruction needs for encoding need to be specified.
 1733 encode %{
 1734   enc_class cdql_enc(no_rax_rdx_RegI div)
 1735   %{
 1736     // Full implementation of Java idiv and irem; checks for
 1737     // special case as described in JVM spec., p.243 & p.271.
 1738     //
 1739     //         normal case                           special case
 1740     //
 1741     // input : rax: dividend                         min_int
 1742     //         reg: divisor                          -1
 1743     //
 1744     // output: rax: quotient  (= rax idiv reg)       min_int
 1745     //         rdx: remainder (= rax irem reg)       0
 1746     //
 1747     //  Code sequnce:
 1748     //
 1749     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
 1750     //    5:   75 07/08                jne    e <normal>
 1751     //    7:   33 d2                   xor    %edx,%edx
 1752     //  [div >= 8 -> offset + 1]
 1753     //  [REX_B]
 1754     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
 1755     //    c:   74 03/04                je     11 <done>
 1756     // 000000000000000e <normal>:
 1757     //    e:   99                      cltd
 1758     //  [div >= 8 -> offset + 1]
 1759     //  [REX_B]
 1760     //    f:   f7 f9                   idiv   $div
 1761     // 0000000000000011 <done>:
 1762     Label normal;
 1763     Label done;
 1764 
 1765     // cmp    $0x80000000,%eax
 1766     __ cmpl(as_Register(RAX_enc), 0x80000000);
 1767 
 1768     // jne    e <normal>
 1769     __ jccb(Assembler::notEqual, normal);
 1770 
 1771     // xor    %edx,%edx
 1772     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1773 
 1774     // cmp    $0xffffffffffffffff,%ecx
 1775     __ cmpl($div$$Register, -1);
 1776 
 1777     // je     11 <done>
 1778     __ jccb(Assembler::equal, done);
 1779 
 1780     // <normal>
 1781     // cltd
 1782     __ bind(normal);
 1783     __ cdql();
 1784 
 1785     // idivl
 1786     // <done>
 1787     __ idivl($div$$Register);
 1788     __ bind(done);
 1789   %}
 1790 
 1791   enc_class cdqq_enc(no_rax_rdx_RegL div)
 1792   %{
 1793     // Full implementation of Java ldiv and lrem; checks for
 1794     // special case as described in JVM spec., p.243 & p.271.
 1795     //
 1796     //         normal case                           special case
 1797     //
 1798     // input : rax: dividend                         min_long
 1799     //         reg: divisor                          -1
 1800     //
 1801     // output: rax: quotient  (= rax idiv reg)       min_long
 1802     //         rdx: remainder (= rax irem reg)       0
 1803     //
 1804     //  Code sequnce:
 1805     //
 1806     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
 1807     //    7:   00 00 80
 1808     //    a:   48 39 d0                cmp    %rdx,%rax
 1809     //    d:   75 08                   jne    17 <normal>
 1810     //    f:   33 d2                   xor    %edx,%edx
 1811     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
 1812     //   15:   74 05                   je     1c <done>
 1813     // 0000000000000017 <normal>:
 1814     //   17:   48 99                   cqto
 1815     //   19:   48 f7 f9                idiv   $div
 1816     // 000000000000001c <done>:
 1817     Label normal;
 1818     Label done;
 1819 
 1820     // mov    $0x8000000000000000,%rdx
 1821     __ mov64(as_Register(RDX_enc), 0x8000000000000000);
 1822 
 1823     // cmp    %rdx,%rax
 1824     __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
 1825 
 1826     // jne    17 <normal>
 1827     __ jccb(Assembler::notEqual, normal);
 1828 
 1829     // xor    %edx,%edx
 1830     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1831 
 1832     // cmp    $0xffffffffffffffff,$div
 1833     __ cmpq($div$$Register, -1);
 1834 
 1835     // je     1e <done>
 1836     __ jccb(Assembler::equal, done);
 1837 
 1838     // <normal>
 1839     // cqto
 1840     __ bind(normal);
 1841     __ cdqq();
 1842 
 1843     // idivq (note: must be emitted by the user of this rule)
 1844     // <done>
 1845     __ idivq($div$$Register);
 1846     __ bind(done);
 1847   %}
 1848 
 1849   enc_class clear_avx %{
 1850     DEBUG_ONLY(int off0 = __ offset());
 1851     if (generate_vzeroupper(Compile::current())) {
 1852       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
 1853       // Clear upper bits of YMM registers when current compiled code uses
 1854       // wide vectors to avoid AVX <-> SSE transition penalty during call.
 1855       __ vzeroupper();
 1856     }
 1857     DEBUG_ONLY(int off1 = __ offset());
 1858     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
 1859   %}
 1860 
 1861   enc_class Java_To_Runtime(method meth) %{
 1862     // No relocation needed
 1863     __ mov64(r10, (int64_t) $meth$$method);
 1864     __ call(r10);
 1865     __ post_call_nop();
 1866   %}
 1867 
 1868   enc_class Java_Static_Call(method meth)
 1869   %{
 1870     // JAVA STATIC CALL
 1871     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
 1872     // determine who we intended to call.
 1873     if (!_method) {
 1874       __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, $meth$$method)));
 1875     } else if (_method->intrinsic_id() == vmIntrinsicID::_ensureMaterializedForStackWalk) {
 1876       // The NOP here is purely to ensure that eliding a call to
 1877       // JVM_EnsureMaterializedForStackWalk doesn't change the code size.
 1878       __ addr_nop_5();
 1879       __ block_comment("call JVM_EnsureMaterializedForStackWalk (elided)");
 1880     } else {
 1881       int method_index = resolved_method_index(masm);
 1882       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 1883                                                   : static_call_Relocation::spec(method_index);
 1884       address mark = __ pc();
 1885       int call_offset = __ offset();
 1886       __ call(AddressLiteral(CAST_FROM_FN_PTR(address, $meth$$method), rspec));
 1887       if (CodeBuffer::supports_shared_stubs() && _method->can_be_statically_bound()) {
 1888         // Calls of the same statically bound method can share
 1889         // a stub to the interpreter.
 1890         __ code()->shared_stub_to_interp_for(_method, call_offset);
 1891       } else {
 1892         // Emit stubs for static call.
 1893         address stub = CompiledDirectCall::emit_to_interp_stub(masm, mark);
 1894         __ clear_inst_mark();
 1895         if (stub == nullptr) {
 1896           ciEnv::current()->record_failure("CodeCache is full");
 1897           return;
 1898         }
 1899       }
 1900     }
 1901     __ post_call_nop();
 1902   %}
 1903 
 1904   enc_class Java_Dynamic_Call(method meth) %{
 1905     __ ic_call((address)$meth$$method, resolved_method_index(masm));
 1906     __ post_call_nop();
 1907   %}
 1908 
 1909 %}
 1910 
 1911 
 1912 
 1913 //----------FRAME--------------------------------------------------------------
 1914 // Definition of frame structure and management information.
 1915 //
 1916 //  S T A C K   L A Y O U T    Allocators stack-slot number
 1917 //                             |   (to get allocators register number
 1918 //  G  Owned by    |        |  v    add OptoReg::stack0())
 1919 //  r   CALLER     |        |
 1920 //  o     |        +--------+      pad to even-align allocators stack-slot
 1921 //  w     V        |  pad0  |        numbers; owned by CALLER
 1922 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 1923 //  h     ^        |   in   |  5
 1924 //        |        |  args  |  4   Holes in incoming args owned by SELF
 1925 //  |     |        |        |  3
 1926 //  |     |        +--------+
 1927 //  V     |        | old out|      Empty on Intel, window on Sparc
 1928 //        |    old |preserve|      Must be even aligned.
 1929 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 1930 //        |        |   in   |  3   area for Intel ret address
 1931 //     Owned by    |preserve|      Empty on Sparc.
 1932 //       SELF      +--------+
 1933 //        |        |  pad2  |  2   pad to align old SP
 1934 //        |        +--------+  1
 1935 //        |        | locks  |  0
 1936 //        |        +--------+----> OptoReg::stack0(), even aligned
 1937 //        |        |  pad1  | 11   pad to align new SP
 1938 //        |        +--------+
 1939 //        |        |        | 10
 1940 //        |        | spills |  9   spills
 1941 //        V        |        |  8   (pad0 slot for callee)
 1942 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 1943 //        ^        |  out   |  7
 1944 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 1945 //     Owned by    +--------+
 1946 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 1947 //        |    new |preserve|      Must be even-aligned.
 1948 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 1949 //        |        |        |
 1950 //
 1951 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 1952 //         known from SELF's arguments and the Java calling convention.
 1953 //         Region 6-7 is determined per call site.
 1954 // Note 2: If the calling convention leaves holes in the incoming argument
 1955 //         area, those holes are owned by SELF.  Holes in the outgoing area
 1956 //         are owned by the CALLEE.  Holes should not be necessary in the
 1957 //         incoming area, as the Java calling convention is completely under
 1958 //         the control of the AD file.  Doubles can be sorted and packed to
 1959 //         avoid holes.  Holes in the outgoing arguments may be necessary for
 1960 //         varargs C calling conventions.
 1961 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 1962 //         even aligned with pad0 as needed.
 1963 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 1964 //         region 6-11 is even aligned; it may be padded out more so that
 1965 //         the region from SP to FP meets the minimum stack alignment.
 1966 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 1967 //         alignment.  Region 11, pad1, may be dynamically extended so that
 1968 //         SP meets the minimum alignment.
 1969 
 1970 frame
 1971 %{
 1972   // These three registers define part of the calling convention
 1973   // between compiled code and the interpreter.
 1974   inline_cache_reg(RAX);                // Inline Cache Register
 1975 
 1976   // Optional: name the operand used by cisc-spilling to access
 1977   // [stack_pointer + offset]
 1978   cisc_spilling_operand_name(indOffset32);
 1979 
 1980   // Number of stack slots consumed by locking an object
 1981   sync_stack_slots(2);
 1982 
 1983   // Compiled code's Frame Pointer
 1984   frame_pointer(RSP);
 1985 
 1986   // Interpreter stores its frame pointer in a register which is
 1987   // stored to the stack by I2CAdaptors.
 1988   // I2CAdaptors convert from interpreted java to compiled java.
 1989   interpreter_frame_pointer(RBP);
 1990 
 1991   // Stack alignment requirement
 1992   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 1993 
 1994   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 1995   // for calls to C.  Supports the var-args backing area for register parms.
 1996   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
 1997 
 1998   // The after-PROLOG location of the return address.  Location of
 1999   // return address specifies a type (REG or STACK) and a number
 2000   // representing the register number (i.e. - use a register name) or
 2001   // stack slot.
 2002   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2003   // Otherwise, it is above the locks and verification slot and alignment word
 2004   return_addr(STACK - 2 +
 2005               align_up((Compile::current()->in_preserve_stack_slots() +
 2006                         Compile::current()->fixed_slots()),
 2007                        stack_alignment_in_slots()));
 2008 
 2009   // Location of compiled Java return values.  Same as C for now.
 2010   return_value
 2011   %{
 2012     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2013            "only return normal values");
 2014 
 2015     static const int lo[Op_RegL + 1] = {
 2016       0,
 2017       0,
 2018       RAX_num,  // Op_RegN
 2019       RAX_num,  // Op_RegI
 2020       RAX_num,  // Op_RegP
 2021       XMM0_num, // Op_RegF
 2022       XMM0_num, // Op_RegD
 2023       RAX_num   // Op_RegL
 2024     };
 2025     static const int hi[Op_RegL + 1] = {
 2026       0,
 2027       0,
 2028       OptoReg::Bad, // Op_RegN
 2029       OptoReg::Bad, // Op_RegI
 2030       RAX_H_num,    // Op_RegP
 2031       OptoReg::Bad, // Op_RegF
 2032       XMM0b_num,    // Op_RegD
 2033       RAX_H_num     // Op_RegL
 2034     };
 2035     // Excluded flags and vector registers.
 2036     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
 2037     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2038   %}
 2039 %}
 2040 
 2041 //----------ATTRIBUTES---------------------------------------------------------
 2042 //----------Operand Attributes-------------------------------------------------
 2043 op_attrib op_cost(0);        // Required cost attribute
 2044 
 2045 //----------Instruction Attributes---------------------------------------------
 2046 ins_attrib ins_cost(100);       // Required cost attribute
 2047 ins_attrib ins_size(8);         // Required size attribute (in bits)
 2048 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2049                                 // a non-matching short branch variant
 2050                                 // of some long branch?
 2051 ins_attrib ins_alignment(1);    // Required alignment attribute (must
 2052                                 // be a power of 2) specifies the
 2053                                 // alignment that some part of the
 2054                                 // instruction (not necessarily the
 2055                                 // start) requires.  If > 1, a
 2056                                 // compute_padding() function must be
 2057                                 // provided for the instruction
 2058 
 2059 //----------OPERANDS-----------------------------------------------------------
 2060 // Operand definitions must precede instruction definitions for correct parsing
 2061 // in the ADLC because operands constitute user defined types which are used in
 2062 // instruction definitions.
 2063 
 2064 //----------Simple Operands----------------------------------------------------
 2065 // Immediate Operands
 2066 // Integer Immediate
 2067 operand immI()
 2068 %{
 2069   match(ConI);
 2070 
 2071   op_cost(10);
 2072   format %{ %}
 2073   interface(CONST_INTER);
 2074 %}
 2075 
 2076 // Constant for test vs zero
 2077 operand immI_0()
 2078 %{
 2079   predicate(n->get_int() == 0);
 2080   match(ConI);
 2081 
 2082   op_cost(0);
 2083   format %{ %}
 2084   interface(CONST_INTER);
 2085 %}
 2086 
 2087 // Constant for increment
 2088 operand immI_1()
 2089 %{
 2090   predicate(n->get_int() == 1);
 2091   match(ConI);
 2092 
 2093   op_cost(0);
 2094   format %{ %}
 2095   interface(CONST_INTER);
 2096 %}
 2097 
 2098 // Constant for decrement
 2099 operand immI_M1()
 2100 %{
 2101   predicate(n->get_int() == -1);
 2102   match(ConI);
 2103 
 2104   op_cost(0);
 2105   format %{ %}
 2106   interface(CONST_INTER);
 2107 %}
 2108 
 2109 operand immI_2()
 2110 %{
 2111   predicate(n->get_int() == 2);
 2112   match(ConI);
 2113 
 2114   op_cost(0);
 2115   format %{ %}
 2116   interface(CONST_INTER);
 2117 %}
 2118 
 2119 operand immI_4()
 2120 %{
 2121   predicate(n->get_int() == 4);
 2122   match(ConI);
 2123 
 2124   op_cost(0);
 2125   format %{ %}
 2126   interface(CONST_INTER);
 2127 %}
 2128 
 2129 operand immI_8()
 2130 %{
 2131   predicate(n->get_int() == 8);
 2132   match(ConI);
 2133 
 2134   op_cost(0);
 2135   format %{ %}
 2136   interface(CONST_INTER);
 2137 %}
 2138 
 2139 // Valid scale values for addressing modes
 2140 operand immI2()
 2141 %{
 2142   predicate(0 <= n->get_int() && (n->get_int() <= 3));
 2143   match(ConI);
 2144 
 2145   format %{ %}
 2146   interface(CONST_INTER);
 2147 %}
 2148 
 2149 operand immU7()
 2150 %{
 2151   predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
 2152   match(ConI);
 2153 
 2154   op_cost(5);
 2155   format %{ %}
 2156   interface(CONST_INTER);
 2157 %}
 2158 
 2159 operand immI8()
 2160 %{
 2161   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
 2162   match(ConI);
 2163 
 2164   op_cost(5);
 2165   format %{ %}
 2166   interface(CONST_INTER);
 2167 %}
 2168 
 2169 operand immU8()
 2170 %{
 2171   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
 2172   match(ConI);
 2173 
 2174   op_cost(5);
 2175   format %{ %}
 2176   interface(CONST_INTER);
 2177 %}
 2178 
 2179 operand immI16()
 2180 %{
 2181   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
 2182   match(ConI);
 2183 
 2184   op_cost(10);
 2185   format %{ %}
 2186   interface(CONST_INTER);
 2187 %}
 2188 
 2189 // Int Immediate non-negative
 2190 operand immU31()
 2191 %{
 2192   predicate(n->get_int() >= 0);
 2193   match(ConI);
 2194 
 2195   op_cost(0);
 2196   format %{ %}
 2197   interface(CONST_INTER);
 2198 %}
 2199 
 2200 // Pointer Immediate
 2201 operand immP()
 2202 %{
 2203   match(ConP);
 2204 
 2205   op_cost(10);
 2206   format %{ %}
 2207   interface(CONST_INTER);
 2208 %}
 2209 
 2210 // Null Pointer Immediate
 2211 operand immP0()
 2212 %{
 2213   predicate(n->get_ptr() == 0);
 2214   match(ConP);
 2215 
 2216   op_cost(5);
 2217   format %{ %}
 2218   interface(CONST_INTER);
 2219 %}
 2220 
 2221 // Pointer Immediate
 2222 operand immN() %{
 2223   match(ConN);
 2224 
 2225   op_cost(10);
 2226   format %{ %}
 2227   interface(CONST_INTER);
 2228 %}
 2229 
 2230 operand immNKlass() %{
 2231   match(ConNKlass);
 2232 
 2233   op_cost(10);
 2234   format %{ %}
 2235   interface(CONST_INTER);
 2236 %}
 2237 
 2238 // Null Pointer Immediate
 2239 operand immN0() %{
 2240   predicate(n->get_narrowcon() == 0);
 2241   match(ConN);
 2242 
 2243   op_cost(5);
 2244   format %{ %}
 2245   interface(CONST_INTER);
 2246 %}
 2247 
 2248 operand immP31()
 2249 %{
 2250   predicate(n->as_Type()->type()->reloc() == relocInfo::none
 2251             && (n->get_ptr() >> 31) == 0);
 2252   match(ConP);
 2253 
 2254   op_cost(5);
 2255   format %{ %}
 2256   interface(CONST_INTER);
 2257 %}
 2258 
 2259 
 2260 // Long Immediate
 2261 operand immL()
 2262 %{
 2263   match(ConL);
 2264 
 2265   op_cost(20);
 2266   format %{ %}
 2267   interface(CONST_INTER);
 2268 %}
 2269 
 2270 // Long Immediate 8-bit
 2271 operand immL8()
 2272 %{
 2273   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
 2274   match(ConL);
 2275 
 2276   op_cost(5);
 2277   format %{ %}
 2278   interface(CONST_INTER);
 2279 %}
 2280 
 2281 // Long Immediate 32-bit unsigned
 2282 operand immUL32()
 2283 %{
 2284   predicate(n->get_long() == (unsigned int) (n->get_long()));
 2285   match(ConL);
 2286 
 2287   op_cost(10);
 2288   format %{ %}
 2289   interface(CONST_INTER);
 2290 %}
 2291 
 2292 // Long Immediate 32-bit signed
 2293 operand immL32()
 2294 %{
 2295   predicate(n->get_long() == (int) (n->get_long()));
 2296   match(ConL);
 2297 
 2298   op_cost(15);
 2299   format %{ %}
 2300   interface(CONST_INTER);
 2301 %}
 2302 
 2303 operand immL_Pow2()
 2304 %{
 2305   predicate(is_power_of_2((julong)n->get_long()));
 2306   match(ConL);
 2307 
 2308   op_cost(15);
 2309   format %{ %}
 2310   interface(CONST_INTER);
 2311 %}
 2312 
 2313 operand immL_NotPow2()
 2314 %{
 2315   predicate(is_power_of_2((julong)~n->get_long()));
 2316   match(ConL);
 2317 
 2318   op_cost(15);
 2319   format %{ %}
 2320   interface(CONST_INTER);
 2321 %}
 2322 
 2323 // Long Immediate zero
 2324 operand immL0()
 2325 %{
 2326   predicate(n->get_long() == 0L);
 2327   match(ConL);
 2328 
 2329   op_cost(10);
 2330   format %{ %}
 2331   interface(CONST_INTER);
 2332 %}
 2333 
 2334 // Constant for increment
 2335 operand immL1()
 2336 %{
 2337   predicate(n->get_long() == 1);
 2338   match(ConL);
 2339 
 2340   format %{ %}
 2341   interface(CONST_INTER);
 2342 %}
 2343 
 2344 // Constant for decrement
 2345 operand immL_M1()
 2346 %{
 2347   predicate(n->get_long() == -1);
 2348   match(ConL);
 2349 
 2350   format %{ %}
 2351   interface(CONST_INTER);
 2352 %}
 2353 
 2354 // Long Immediate: low 32-bit mask
 2355 operand immL_32bits()
 2356 %{
 2357   predicate(n->get_long() == 0xFFFFFFFFL);
 2358   match(ConL);
 2359   op_cost(20);
 2360 
 2361   format %{ %}
 2362   interface(CONST_INTER);
 2363 %}
 2364 
 2365 // Int Immediate: 2^n-1, positive
 2366 operand immI_Pow2M1()
 2367 %{
 2368   predicate((n->get_int() > 0)
 2369             && is_power_of_2((juint)n->get_int() + 1));
 2370   match(ConI);
 2371 
 2372   op_cost(20);
 2373   format %{ %}
 2374   interface(CONST_INTER);
 2375 %}
 2376 
 2377 // Float Immediate zero
 2378 operand immF0()
 2379 %{
 2380   predicate(jint_cast(n->getf()) == 0);
 2381   match(ConF);
 2382 
 2383   op_cost(5);
 2384   format %{ %}
 2385   interface(CONST_INTER);
 2386 %}
 2387 
 2388 // Float Immediate
 2389 operand immF()
 2390 %{
 2391   match(ConF);
 2392 
 2393   op_cost(15);
 2394   format %{ %}
 2395   interface(CONST_INTER);
 2396 %}
 2397 
 2398 // Half Float Immediate
 2399 operand immH()
 2400 %{
 2401   match(ConH);
 2402 
 2403   op_cost(15);
 2404   format %{ %}
 2405   interface(CONST_INTER);
 2406 %}
 2407 
 2408 // Double Immediate zero
 2409 operand immD0()
 2410 %{
 2411   predicate(jlong_cast(n->getd()) == 0);
 2412   match(ConD);
 2413 
 2414   op_cost(5);
 2415   format %{ %}
 2416   interface(CONST_INTER);
 2417 %}
 2418 
 2419 // Double Immediate
 2420 operand immD()
 2421 %{
 2422   match(ConD);
 2423 
 2424   op_cost(15);
 2425   format %{ %}
 2426   interface(CONST_INTER);
 2427 %}
 2428 
 2429 // Immediates for special shifts (sign extend)
 2430 
 2431 // Constants for increment
 2432 operand immI_16()
 2433 %{
 2434   predicate(n->get_int() == 16);
 2435   match(ConI);
 2436 
 2437   format %{ %}
 2438   interface(CONST_INTER);
 2439 %}
 2440 
 2441 operand immI_24()
 2442 %{
 2443   predicate(n->get_int() == 24);
 2444   match(ConI);
 2445 
 2446   format %{ %}
 2447   interface(CONST_INTER);
 2448 %}
 2449 
 2450 // Constant for byte-wide masking
 2451 operand immI_255()
 2452 %{
 2453   predicate(n->get_int() == 255);
 2454   match(ConI);
 2455 
 2456   format %{ %}
 2457   interface(CONST_INTER);
 2458 %}
 2459 
 2460 // Constant for short-wide masking
 2461 operand immI_65535()
 2462 %{
 2463   predicate(n->get_int() == 65535);
 2464   match(ConI);
 2465 
 2466   format %{ %}
 2467   interface(CONST_INTER);
 2468 %}
 2469 
 2470 // Constant for byte-wide masking
 2471 operand immL_255()
 2472 %{
 2473   predicate(n->get_long() == 255);
 2474   match(ConL);
 2475 
 2476   format %{ %}
 2477   interface(CONST_INTER);
 2478 %}
 2479 
 2480 // Constant for short-wide masking
 2481 operand immL_65535()
 2482 %{
 2483   predicate(n->get_long() == 65535);
 2484   match(ConL);
 2485 
 2486   format %{ %}
 2487   interface(CONST_INTER);
 2488 %}
 2489 
 2490 operand kReg()
 2491 %{
 2492   constraint(ALLOC_IN_RC(vectmask_reg));
 2493   match(RegVectMask);
 2494   format %{%}
 2495   interface(REG_INTER);
 2496 %}
 2497 
 2498 // Register Operands
 2499 // Integer Register
 2500 operand rRegI()
 2501 %{
 2502   constraint(ALLOC_IN_RC(int_reg));
 2503   match(RegI);
 2504 
 2505   match(rax_RegI);
 2506   match(rbx_RegI);
 2507   match(rcx_RegI);
 2508   match(rdx_RegI);
 2509   match(rdi_RegI);
 2510 
 2511   format %{ %}
 2512   interface(REG_INTER);
 2513 %}
 2514 
 2515 // Special Registers
 2516 operand rax_RegI()
 2517 %{
 2518   constraint(ALLOC_IN_RC(int_rax_reg));
 2519   match(RegI);
 2520   match(rRegI);
 2521 
 2522   format %{ "RAX" %}
 2523   interface(REG_INTER);
 2524 %}
 2525 
 2526 // Special Registers
 2527 operand rbx_RegI()
 2528 %{
 2529   constraint(ALLOC_IN_RC(int_rbx_reg));
 2530   match(RegI);
 2531   match(rRegI);
 2532 
 2533   format %{ "RBX" %}
 2534   interface(REG_INTER);
 2535 %}
 2536 
 2537 operand rcx_RegI()
 2538 %{
 2539   constraint(ALLOC_IN_RC(int_rcx_reg));
 2540   match(RegI);
 2541   match(rRegI);
 2542 
 2543   format %{ "RCX" %}
 2544   interface(REG_INTER);
 2545 %}
 2546 
 2547 operand rdx_RegI()
 2548 %{
 2549   constraint(ALLOC_IN_RC(int_rdx_reg));
 2550   match(RegI);
 2551   match(rRegI);
 2552 
 2553   format %{ "RDX" %}
 2554   interface(REG_INTER);
 2555 %}
 2556 
 2557 operand rdi_RegI()
 2558 %{
 2559   constraint(ALLOC_IN_RC(int_rdi_reg));
 2560   match(RegI);
 2561   match(rRegI);
 2562 
 2563   format %{ "RDI" %}
 2564   interface(REG_INTER);
 2565 %}
 2566 
 2567 operand no_rax_rdx_RegI()
 2568 %{
 2569   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
 2570   match(RegI);
 2571   match(rbx_RegI);
 2572   match(rcx_RegI);
 2573   match(rdi_RegI);
 2574 
 2575   format %{ %}
 2576   interface(REG_INTER);
 2577 %}
 2578 
 2579 operand no_rbp_r13_RegI()
 2580 %{
 2581   constraint(ALLOC_IN_RC(int_no_rbp_r13_reg));
 2582   match(RegI);
 2583   match(rRegI);
 2584   match(rax_RegI);
 2585   match(rbx_RegI);
 2586   match(rcx_RegI);
 2587   match(rdx_RegI);
 2588   match(rdi_RegI);
 2589 
 2590   format %{ %}
 2591   interface(REG_INTER);
 2592 %}
 2593 
 2594 // Pointer Register
 2595 operand any_RegP()
 2596 %{
 2597   constraint(ALLOC_IN_RC(any_reg));
 2598   match(RegP);
 2599   match(rax_RegP);
 2600   match(rbx_RegP);
 2601   match(rdi_RegP);
 2602   match(rsi_RegP);
 2603   match(rbp_RegP);
 2604   match(r15_RegP);
 2605   match(rRegP);
 2606 
 2607   format %{ %}
 2608   interface(REG_INTER);
 2609 %}
 2610 
 2611 operand rRegP()
 2612 %{
 2613   constraint(ALLOC_IN_RC(ptr_reg));
 2614   match(RegP);
 2615   match(rax_RegP);
 2616   match(rbx_RegP);
 2617   match(rdi_RegP);
 2618   match(rsi_RegP);
 2619   match(rbp_RegP);  // See Q&A below about
 2620   match(r15_RegP);  // r15_RegP and rbp_RegP.
 2621 
 2622   format %{ %}
 2623   interface(REG_INTER);
 2624 %}
 2625 
 2626 operand rRegN() %{
 2627   constraint(ALLOC_IN_RC(int_reg));
 2628   match(RegN);
 2629 
 2630   format %{ %}
 2631   interface(REG_INTER);
 2632 %}
 2633 
 2634 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
 2635 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
 2636 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
 2637 // The output of an instruction is controlled by the allocator, which respects
 2638 // register class masks, not match rules.  Unless an instruction mentions
 2639 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
 2640 // by the allocator as an input.
 2641 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
 2642 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
 2643 // result, RBP is not included in the output of the instruction either.
 2644 
 2645 // This operand is not allowed to use RBP even if
 2646 // RBP is not used to hold the frame pointer.
 2647 operand no_rbp_RegP()
 2648 %{
 2649   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
 2650   match(RegP);
 2651   match(rbx_RegP);
 2652   match(rsi_RegP);
 2653   match(rdi_RegP);
 2654 
 2655   format %{ %}
 2656   interface(REG_INTER);
 2657 %}
 2658 
 2659 // Special Registers
 2660 // Return a pointer value
 2661 operand rax_RegP()
 2662 %{
 2663   constraint(ALLOC_IN_RC(ptr_rax_reg));
 2664   match(RegP);
 2665   match(rRegP);
 2666 
 2667   format %{ %}
 2668   interface(REG_INTER);
 2669 %}
 2670 
 2671 // Special Registers
 2672 // Return a compressed pointer value
 2673 operand rax_RegN()
 2674 %{
 2675   constraint(ALLOC_IN_RC(int_rax_reg));
 2676   match(RegN);
 2677   match(rRegN);
 2678 
 2679   format %{ %}
 2680   interface(REG_INTER);
 2681 %}
 2682 
 2683 // Used in AtomicAdd
 2684 operand rbx_RegP()
 2685 %{
 2686   constraint(ALLOC_IN_RC(ptr_rbx_reg));
 2687   match(RegP);
 2688   match(rRegP);
 2689 
 2690   format %{ %}
 2691   interface(REG_INTER);
 2692 %}
 2693 
 2694 operand rsi_RegP()
 2695 %{
 2696   constraint(ALLOC_IN_RC(ptr_rsi_reg));
 2697   match(RegP);
 2698   match(rRegP);
 2699 
 2700   format %{ %}
 2701   interface(REG_INTER);
 2702 %}
 2703 
 2704 operand rbp_RegP()
 2705 %{
 2706   constraint(ALLOC_IN_RC(ptr_rbp_reg));
 2707   match(RegP);
 2708   match(rRegP);
 2709 
 2710   format %{ %}
 2711   interface(REG_INTER);
 2712 %}
 2713 
 2714 // Used in rep stosq
 2715 operand rdi_RegP()
 2716 %{
 2717   constraint(ALLOC_IN_RC(ptr_rdi_reg));
 2718   match(RegP);
 2719   match(rRegP);
 2720 
 2721   format %{ %}
 2722   interface(REG_INTER);
 2723 %}
 2724 
 2725 operand r15_RegP()
 2726 %{
 2727   constraint(ALLOC_IN_RC(ptr_r15_reg));
 2728   match(RegP);
 2729   match(rRegP);
 2730 
 2731   format %{ %}
 2732   interface(REG_INTER);
 2733 %}
 2734 
 2735 operand rRegL()
 2736 %{
 2737   constraint(ALLOC_IN_RC(long_reg));
 2738   match(RegL);
 2739   match(rax_RegL);
 2740   match(rdx_RegL);
 2741 
 2742   format %{ %}
 2743   interface(REG_INTER);
 2744 %}
 2745 
 2746 // Special Registers
 2747 operand no_rax_rdx_RegL()
 2748 %{
 2749   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
 2750   match(RegL);
 2751   match(rRegL);
 2752 
 2753   format %{ %}
 2754   interface(REG_INTER);
 2755 %}
 2756 
 2757 operand rax_RegL()
 2758 %{
 2759   constraint(ALLOC_IN_RC(long_rax_reg));
 2760   match(RegL);
 2761   match(rRegL);
 2762 
 2763   format %{ "RAX" %}
 2764   interface(REG_INTER);
 2765 %}
 2766 
 2767 operand rcx_RegL()
 2768 %{
 2769   constraint(ALLOC_IN_RC(long_rcx_reg));
 2770   match(RegL);
 2771   match(rRegL);
 2772 
 2773   format %{ %}
 2774   interface(REG_INTER);
 2775 %}
 2776 
 2777 operand rdx_RegL()
 2778 %{
 2779   constraint(ALLOC_IN_RC(long_rdx_reg));
 2780   match(RegL);
 2781   match(rRegL);
 2782 
 2783   format %{ %}
 2784   interface(REG_INTER);
 2785 %}
 2786 
 2787 operand r11_RegL()
 2788 %{
 2789   constraint(ALLOC_IN_RC(long_r11_reg));
 2790   match(RegL);
 2791   match(rRegL);
 2792 
 2793   format %{ %}
 2794   interface(REG_INTER);
 2795 %}
 2796 
 2797 operand no_rbp_r13_RegL()
 2798 %{
 2799   constraint(ALLOC_IN_RC(long_no_rbp_r13_reg));
 2800   match(RegL);
 2801   match(rRegL);
 2802   match(rax_RegL);
 2803   match(rcx_RegL);
 2804   match(rdx_RegL);
 2805 
 2806   format %{ %}
 2807   interface(REG_INTER);
 2808 %}
 2809 
 2810 // Flags register, used as output of compare instructions
 2811 operand rFlagsReg()
 2812 %{
 2813   constraint(ALLOC_IN_RC(int_flags));
 2814   match(RegFlags);
 2815 
 2816   format %{ "RFLAGS" %}
 2817   interface(REG_INTER);
 2818 %}
 2819 
 2820 // Flags register, used as output of FLOATING POINT compare instructions
 2821 operand rFlagsRegU()
 2822 %{
 2823   constraint(ALLOC_IN_RC(int_flags));
 2824   match(RegFlags);
 2825 
 2826   format %{ "RFLAGS_U" %}
 2827   interface(REG_INTER);
 2828 %}
 2829 
 2830 operand rFlagsRegUCF() %{
 2831   constraint(ALLOC_IN_RC(int_flags));
 2832   match(RegFlags);
 2833   predicate(false);
 2834 
 2835   format %{ "RFLAGS_U_CF" %}
 2836   interface(REG_INTER);
 2837 %}
 2838 
 2839 // Float register operands
 2840 operand regF() %{
 2841    constraint(ALLOC_IN_RC(float_reg));
 2842    match(RegF);
 2843 
 2844    format %{ %}
 2845    interface(REG_INTER);
 2846 %}
 2847 
 2848 // Float register operands
 2849 operand legRegF() %{
 2850    constraint(ALLOC_IN_RC(float_reg_legacy));
 2851    match(RegF);
 2852 
 2853    format %{ %}
 2854    interface(REG_INTER);
 2855 %}
 2856 
 2857 // Float register operands
 2858 operand vlRegF() %{
 2859    constraint(ALLOC_IN_RC(float_reg_vl));
 2860    match(RegF);
 2861 
 2862    format %{ %}
 2863    interface(REG_INTER);
 2864 %}
 2865 
 2866 // Double register operands
 2867 operand regD() %{
 2868    constraint(ALLOC_IN_RC(double_reg));
 2869    match(RegD);
 2870 
 2871    format %{ %}
 2872    interface(REG_INTER);
 2873 %}
 2874 
 2875 // Double register operands
 2876 operand legRegD() %{
 2877    constraint(ALLOC_IN_RC(double_reg_legacy));
 2878    match(RegD);
 2879 
 2880    format %{ %}
 2881    interface(REG_INTER);
 2882 %}
 2883 
 2884 // Double register operands
 2885 operand vlRegD() %{
 2886    constraint(ALLOC_IN_RC(double_reg_vl));
 2887    match(RegD);
 2888 
 2889    format %{ %}
 2890    interface(REG_INTER);
 2891 %}
 2892 
 2893 //----------Memory Operands----------------------------------------------------
 2894 // Direct Memory Operand
 2895 // operand direct(immP addr)
 2896 // %{
 2897 //   match(addr);
 2898 
 2899 //   format %{ "[$addr]" %}
 2900 //   interface(MEMORY_INTER) %{
 2901 //     base(0xFFFFFFFF);
 2902 //     index(0x4);
 2903 //     scale(0x0);
 2904 //     disp($addr);
 2905 //   %}
 2906 // %}
 2907 
 2908 // Indirect Memory Operand
 2909 operand indirect(any_RegP reg)
 2910 %{
 2911   constraint(ALLOC_IN_RC(ptr_reg));
 2912   match(reg);
 2913 
 2914   format %{ "[$reg]" %}
 2915   interface(MEMORY_INTER) %{
 2916     base($reg);
 2917     index(0x4);
 2918     scale(0x0);
 2919     disp(0x0);
 2920   %}
 2921 %}
 2922 
 2923 // Indirect Memory Plus Short Offset Operand
 2924 operand indOffset8(any_RegP reg, immL8 off)
 2925 %{
 2926   constraint(ALLOC_IN_RC(ptr_reg));
 2927   match(AddP reg off);
 2928 
 2929   format %{ "[$reg + $off (8-bit)]" %}
 2930   interface(MEMORY_INTER) %{
 2931     base($reg);
 2932     index(0x4);
 2933     scale(0x0);
 2934     disp($off);
 2935   %}
 2936 %}
 2937 
 2938 // Indirect Memory Plus Long Offset Operand
 2939 operand indOffset32(any_RegP reg, immL32 off)
 2940 %{
 2941   constraint(ALLOC_IN_RC(ptr_reg));
 2942   match(AddP reg off);
 2943 
 2944   format %{ "[$reg + $off (32-bit)]" %}
 2945   interface(MEMORY_INTER) %{
 2946     base($reg);
 2947     index(0x4);
 2948     scale(0x0);
 2949     disp($off);
 2950   %}
 2951 %}
 2952 
 2953 // Indirect Memory Plus Index Register Plus Offset Operand
 2954 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
 2955 %{
 2956   constraint(ALLOC_IN_RC(ptr_reg));
 2957   match(AddP (AddP reg lreg) off);
 2958 
 2959   op_cost(10);
 2960   format %{"[$reg + $off + $lreg]" %}
 2961   interface(MEMORY_INTER) %{
 2962     base($reg);
 2963     index($lreg);
 2964     scale(0x0);
 2965     disp($off);
 2966   %}
 2967 %}
 2968 
 2969 // Indirect Memory Plus Index Register Plus Offset Operand
 2970 operand indIndex(any_RegP reg, rRegL lreg)
 2971 %{
 2972   constraint(ALLOC_IN_RC(ptr_reg));
 2973   match(AddP reg lreg);
 2974 
 2975   op_cost(10);
 2976   format %{"[$reg + $lreg]" %}
 2977   interface(MEMORY_INTER) %{
 2978     base($reg);
 2979     index($lreg);
 2980     scale(0x0);
 2981     disp(0x0);
 2982   %}
 2983 %}
 2984 
 2985 // Indirect Memory Times Scale Plus Index Register
 2986 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
 2987 %{
 2988   constraint(ALLOC_IN_RC(ptr_reg));
 2989   match(AddP reg (LShiftL lreg scale));
 2990 
 2991   op_cost(10);
 2992   format %{"[$reg + $lreg << $scale]" %}
 2993   interface(MEMORY_INTER) %{
 2994     base($reg);
 2995     index($lreg);
 2996     scale($scale);
 2997     disp(0x0);
 2998   %}
 2999 %}
 3000 
 3001 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
 3002 %{
 3003   constraint(ALLOC_IN_RC(ptr_reg));
 3004   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3005   match(AddP reg (LShiftL (ConvI2L idx) scale));
 3006 
 3007   op_cost(10);
 3008   format %{"[$reg + pos $idx << $scale]" %}
 3009   interface(MEMORY_INTER) %{
 3010     base($reg);
 3011     index($idx);
 3012     scale($scale);
 3013     disp(0x0);
 3014   %}
 3015 %}
 3016 
 3017 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 3018 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
 3019 %{
 3020   constraint(ALLOC_IN_RC(ptr_reg));
 3021   match(AddP (AddP reg (LShiftL lreg scale)) off);
 3022 
 3023   op_cost(10);
 3024   format %{"[$reg + $off + $lreg << $scale]" %}
 3025   interface(MEMORY_INTER) %{
 3026     base($reg);
 3027     index($lreg);
 3028     scale($scale);
 3029     disp($off);
 3030   %}
 3031 %}
 3032 
 3033 // Indirect Memory Plus Positive Index Register Plus Offset Operand
 3034 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
 3035 %{
 3036   constraint(ALLOC_IN_RC(ptr_reg));
 3037   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 3038   match(AddP (AddP reg (ConvI2L idx)) off);
 3039 
 3040   op_cost(10);
 3041   format %{"[$reg + $off + $idx]" %}
 3042   interface(MEMORY_INTER) %{
 3043     base($reg);
 3044     index($idx);
 3045     scale(0x0);
 3046     disp($off);
 3047   %}
 3048 %}
 3049 
 3050 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 3051 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
 3052 %{
 3053   constraint(ALLOC_IN_RC(ptr_reg));
 3054   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3055   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
 3056 
 3057   op_cost(10);
 3058   format %{"[$reg + $off + $idx << $scale]" %}
 3059   interface(MEMORY_INTER) %{
 3060     base($reg);
 3061     index($idx);
 3062     scale($scale);
 3063     disp($off);
 3064   %}
 3065 %}
 3066 
 3067 // Indirect Narrow Oop Plus Offset Operand
 3068 // Note: x86 architecture doesn't support "scale * index + offset" without a base
 3069 // we can't free r12 even with CompressedOops::base() == nullptr.
 3070 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
 3071   predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
 3072   constraint(ALLOC_IN_RC(ptr_reg));
 3073   match(AddP (DecodeN reg) off);
 3074 
 3075   op_cost(10);
 3076   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
 3077   interface(MEMORY_INTER) %{
 3078     base(0xc); // R12
 3079     index($reg);
 3080     scale(0x3);
 3081     disp($off);
 3082   %}
 3083 %}
 3084 
 3085 // Indirect Memory Operand
 3086 operand indirectNarrow(rRegN reg)
 3087 %{
 3088   predicate(CompressedOops::shift() == 0);
 3089   constraint(ALLOC_IN_RC(ptr_reg));
 3090   match(DecodeN reg);
 3091 
 3092   format %{ "[$reg]" %}
 3093   interface(MEMORY_INTER) %{
 3094     base($reg);
 3095     index(0x4);
 3096     scale(0x0);
 3097     disp(0x0);
 3098   %}
 3099 %}
 3100 
 3101 // Indirect Memory Plus Short Offset Operand
 3102 operand indOffset8Narrow(rRegN reg, immL8 off)
 3103 %{
 3104   predicate(CompressedOops::shift() == 0);
 3105   constraint(ALLOC_IN_RC(ptr_reg));
 3106   match(AddP (DecodeN reg) off);
 3107 
 3108   format %{ "[$reg + $off (8-bit)]" %}
 3109   interface(MEMORY_INTER) %{
 3110     base($reg);
 3111     index(0x4);
 3112     scale(0x0);
 3113     disp($off);
 3114   %}
 3115 %}
 3116 
 3117 // Indirect Memory Plus Long Offset Operand
 3118 operand indOffset32Narrow(rRegN reg, immL32 off)
 3119 %{
 3120   predicate(CompressedOops::shift() == 0);
 3121   constraint(ALLOC_IN_RC(ptr_reg));
 3122   match(AddP (DecodeN reg) off);
 3123 
 3124   format %{ "[$reg + $off (32-bit)]" %}
 3125   interface(MEMORY_INTER) %{
 3126     base($reg);
 3127     index(0x4);
 3128     scale(0x0);
 3129     disp($off);
 3130   %}
 3131 %}
 3132 
 3133 // Indirect Memory Plus Index Register Plus Offset Operand
 3134 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
 3135 %{
 3136   predicate(CompressedOops::shift() == 0);
 3137   constraint(ALLOC_IN_RC(ptr_reg));
 3138   match(AddP (AddP (DecodeN reg) lreg) off);
 3139 
 3140   op_cost(10);
 3141   format %{"[$reg + $off + $lreg]" %}
 3142   interface(MEMORY_INTER) %{
 3143     base($reg);
 3144     index($lreg);
 3145     scale(0x0);
 3146     disp($off);
 3147   %}
 3148 %}
 3149 
 3150 // Indirect Memory Plus Index Register Plus Offset Operand
 3151 operand indIndexNarrow(rRegN reg, rRegL lreg)
 3152 %{
 3153   predicate(CompressedOops::shift() == 0);
 3154   constraint(ALLOC_IN_RC(ptr_reg));
 3155   match(AddP (DecodeN reg) lreg);
 3156 
 3157   op_cost(10);
 3158   format %{"[$reg + $lreg]" %}
 3159   interface(MEMORY_INTER) %{
 3160     base($reg);
 3161     index($lreg);
 3162     scale(0x0);
 3163     disp(0x0);
 3164   %}
 3165 %}
 3166 
 3167 // Indirect Memory Times Scale Plus Index Register
 3168 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
 3169 %{
 3170   predicate(CompressedOops::shift() == 0);
 3171   constraint(ALLOC_IN_RC(ptr_reg));
 3172   match(AddP (DecodeN reg) (LShiftL lreg scale));
 3173 
 3174   op_cost(10);
 3175   format %{"[$reg + $lreg << $scale]" %}
 3176   interface(MEMORY_INTER) %{
 3177     base($reg);
 3178     index($lreg);
 3179     scale($scale);
 3180     disp(0x0);
 3181   %}
 3182 %}
 3183 
 3184 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 3185 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
 3186 %{
 3187   predicate(CompressedOops::shift() == 0);
 3188   constraint(ALLOC_IN_RC(ptr_reg));
 3189   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
 3190 
 3191   op_cost(10);
 3192   format %{"[$reg + $off + $lreg << $scale]" %}
 3193   interface(MEMORY_INTER) %{
 3194     base($reg);
 3195     index($lreg);
 3196     scale($scale);
 3197     disp($off);
 3198   %}
 3199 %}
 3200 
 3201 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
 3202 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
 3203 %{
 3204   constraint(ALLOC_IN_RC(ptr_reg));
 3205   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 3206   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
 3207 
 3208   op_cost(10);
 3209   format %{"[$reg + $off + $idx]" %}
 3210   interface(MEMORY_INTER) %{
 3211     base($reg);
 3212     index($idx);
 3213     scale(0x0);
 3214     disp($off);
 3215   %}
 3216 %}
 3217 
 3218 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 3219 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
 3220 %{
 3221   constraint(ALLOC_IN_RC(ptr_reg));
 3222   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3223   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
 3224 
 3225   op_cost(10);
 3226   format %{"[$reg + $off + $idx << $scale]" %}
 3227   interface(MEMORY_INTER) %{
 3228     base($reg);
 3229     index($idx);
 3230     scale($scale);
 3231     disp($off);
 3232   %}
 3233 %}
 3234 
 3235 //----------Special Memory Operands--------------------------------------------
 3236 // Stack Slot Operand - This operand is used for loading and storing temporary
 3237 //                      values on the stack where a match requires a value to
 3238 //                      flow through memory.
 3239 operand stackSlotP(sRegP reg)
 3240 %{
 3241   constraint(ALLOC_IN_RC(stack_slots));
 3242   // No match rule because this operand is only generated in matching
 3243 
 3244   format %{ "[$reg]" %}
 3245   interface(MEMORY_INTER) %{
 3246     base(0x4);   // RSP
 3247     index(0x4);  // No Index
 3248     scale(0x0);  // No Scale
 3249     disp($reg);  // Stack Offset
 3250   %}
 3251 %}
 3252 
 3253 operand stackSlotI(sRegI reg)
 3254 %{
 3255   constraint(ALLOC_IN_RC(stack_slots));
 3256   // No match rule because this operand is only generated in matching
 3257 
 3258   format %{ "[$reg]" %}
 3259   interface(MEMORY_INTER) %{
 3260     base(0x4);   // RSP
 3261     index(0x4);  // No Index
 3262     scale(0x0);  // No Scale
 3263     disp($reg);  // Stack Offset
 3264   %}
 3265 %}
 3266 
 3267 operand stackSlotF(sRegF reg)
 3268 %{
 3269   constraint(ALLOC_IN_RC(stack_slots));
 3270   // No match rule because this operand is only generated in matching
 3271 
 3272   format %{ "[$reg]" %}
 3273   interface(MEMORY_INTER) %{
 3274     base(0x4);   // RSP
 3275     index(0x4);  // No Index
 3276     scale(0x0);  // No Scale
 3277     disp($reg);  // Stack Offset
 3278   %}
 3279 %}
 3280 
 3281 operand stackSlotD(sRegD reg)
 3282 %{
 3283   constraint(ALLOC_IN_RC(stack_slots));
 3284   // No match rule because this operand is only generated in matching
 3285 
 3286   format %{ "[$reg]" %}
 3287   interface(MEMORY_INTER) %{
 3288     base(0x4);   // RSP
 3289     index(0x4);  // No Index
 3290     scale(0x0);  // No Scale
 3291     disp($reg);  // Stack Offset
 3292   %}
 3293 %}
 3294 operand stackSlotL(sRegL reg)
 3295 %{
 3296   constraint(ALLOC_IN_RC(stack_slots));
 3297   // No match rule because this operand is only generated in matching
 3298 
 3299   format %{ "[$reg]" %}
 3300   interface(MEMORY_INTER) %{
 3301     base(0x4);   // RSP
 3302     index(0x4);  // No Index
 3303     scale(0x0);  // No Scale
 3304     disp($reg);  // Stack Offset
 3305   %}
 3306 %}
 3307 
 3308 //----------Conditional Branch Operands----------------------------------------
 3309 // Comparison Op  - This is the operation of the comparison, and is limited to
 3310 //                  the following set of codes:
 3311 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3312 //
 3313 // Other attributes of the comparison, such as unsignedness, are specified
 3314 // by the comparison instruction that sets a condition code flags register.
 3315 // That result is represented by a flags operand whose subtype is appropriate
 3316 // to the unsignedness (etc.) of the comparison.
 3317 //
 3318 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3319 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3320 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 3321 
 3322 // Comparison Code
 3323 operand cmpOp()
 3324 %{
 3325   match(Bool);
 3326 
 3327   format %{ "" %}
 3328   interface(COND_INTER) %{
 3329     equal(0x4, "e");
 3330     not_equal(0x5, "ne");
 3331     less(0xC, "l");
 3332     greater_equal(0xD, "ge");
 3333     less_equal(0xE, "le");
 3334     greater(0xF, "g");
 3335     overflow(0x0, "o");
 3336     no_overflow(0x1, "no");
 3337   %}
 3338 %}
 3339 
 3340 // Comparison Code, unsigned compare.  Used by FP also, with
 3341 // C2 (unordered) turned into GT or LT already.  The other bits
 3342 // C0 and C3 are turned into Carry & Zero flags.
 3343 operand cmpOpU()
 3344 %{
 3345   match(Bool);
 3346 
 3347   format %{ "" %}
 3348   interface(COND_INTER) %{
 3349     equal(0x4, "e");
 3350     not_equal(0x5, "ne");
 3351     less(0x2, "b");
 3352     greater_equal(0x3, "ae");
 3353     less_equal(0x6, "be");
 3354     greater(0x7, "a");
 3355     overflow(0x0, "o");
 3356     no_overflow(0x1, "no");
 3357   %}
 3358 %}
 3359 
 3360 
 3361 // Floating comparisons that don't require any fixup for the unordered case,
 3362 // If both inputs of the comparison are the same, ZF is always set so we
 3363 // don't need to use cmpOpUCF2 for eq/ne
 3364 operand cmpOpUCF() %{
 3365   match(Bool);
 3366   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 3367             n->as_Bool()->_test._test == BoolTest::ge ||
 3368             n->as_Bool()->_test._test == BoolTest::le ||
 3369             n->as_Bool()->_test._test == BoolTest::gt ||
 3370             n->in(1)->in(1) == n->in(1)->in(2));
 3371   format %{ "" %}
 3372   interface(COND_INTER) %{
 3373     equal(0xb, "np");
 3374     not_equal(0xa, "p");
 3375     less(0x2, "b");
 3376     greater_equal(0x3, "ae");
 3377     less_equal(0x6, "be");
 3378     greater(0x7, "a");
 3379     overflow(0x0, "o");
 3380     no_overflow(0x1, "no");
 3381   %}
 3382 %}
 3383 
 3384 
 3385 // Floating comparisons that can be fixed up with extra conditional jumps
 3386 operand cmpOpUCF2() %{
 3387   match(Bool);
 3388   predicate((n->as_Bool()->_test._test == BoolTest::ne ||
 3389              n->as_Bool()->_test._test == BoolTest::eq) &&
 3390             n->in(1)->in(1) != n->in(1)->in(2));
 3391   format %{ "" %}
 3392   interface(COND_INTER) %{
 3393     equal(0x4, "e");
 3394     not_equal(0x5, "ne");
 3395     less(0x2, "b");
 3396     greater_equal(0x3, "ae");
 3397     less_equal(0x6, "be");
 3398     greater(0x7, "a");
 3399     overflow(0x0, "o");
 3400     no_overflow(0x1, "no");
 3401   %}
 3402 %}
 3403 
 3404 //----------OPERAND CLASSES----------------------------------------------------
 3405 // Operand Classes are groups of operands that are used as to simplify
 3406 // instruction definitions by not requiring the AD writer to specify separate
 3407 // instructions for every form of operand when the instruction accepts
 3408 // multiple operand types with the same basic encoding and format.  The classic
 3409 // case of this is memory operands.
 3410 
 3411 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
 3412                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
 3413                indCompressedOopOffset,
 3414                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
 3415                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
 3416                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
 3417 
 3418 //----------PIPELINE-----------------------------------------------------------
 3419 // Rules which define the behavior of the target architectures pipeline.
 3420 pipeline %{
 3421 
 3422 //----------ATTRIBUTES---------------------------------------------------------
 3423 attributes %{
 3424   variable_size_instructions;        // Fixed size instructions
 3425   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
 3426   instruction_unit_size = 1;         // An instruction is 1 bytes long
 3427   instruction_fetch_unit_size = 16;  // The processor fetches one line
 3428   instruction_fetch_units = 1;       // of 16 bytes
 3429 
 3430   // List of nop instructions
 3431   nops( MachNop );
 3432 %}
 3433 
 3434 //----------RESOURCES----------------------------------------------------------
 3435 // Resources are the functional units available to the machine
 3436 
 3437 // Generic P2/P3 pipeline
 3438 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
 3439 // 3 instructions decoded per cycle.
 3440 // 2 load/store ops per cycle, 1 branch, 1 FPU,
 3441 // 3 ALU op, only ALU0 handles mul instructions.
 3442 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
 3443            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
 3444            BR, FPU,
 3445            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
 3446 
 3447 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3448 // Pipeline Description specifies the stages in the machine's pipeline
 3449 
 3450 // Generic P2/P3 pipeline
 3451 pipe_desc(S0, S1, S2, S3, S4, S5);
 3452 
 3453 //----------PIPELINE CLASSES---------------------------------------------------
 3454 // Pipeline Classes describe the stages in which input and output are
 3455 // referenced by the hardware pipeline.
 3456 
 3457 // Naming convention: ialu or fpu
 3458 // Then: _reg
 3459 // Then: _reg if there is a 2nd register
 3460 // Then: _long if it's a pair of instructions implementing a long
 3461 // Then: _fat if it requires the big decoder
 3462 //   Or: _mem if it requires the big decoder and a memory unit.
 3463 
 3464 // Integer ALU reg operation
 3465 pipe_class ialu_reg(rRegI dst)
 3466 %{
 3467     single_instruction;
 3468     dst    : S4(write);
 3469     dst    : S3(read);
 3470     DECODE : S0;        // any decoder
 3471     ALU    : S3;        // any alu
 3472 %}
 3473 
 3474 // Long ALU reg operation
 3475 pipe_class ialu_reg_long(rRegL dst)
 3476 %{
 3477     instruction_count(2);
 3478     dst    : S4(write);
 3479     dst    : S3(read);
 3480     DECODE : S0(2);     // any 2 decoders
 3481     ALU    : S3(2);     // both alus
 3482 %}
 3483 
 3484 // Integer ALU reg operation using big decoder
 3485 pipe_class ialu_reg_fat(rRegI dst)
 3486 %{
 3487     single_instruction;
 3488     dst    : S4(write);
 3489     dst    : S3(read);
 3490     D0     : S0;        // big decoder only
 3491     ALU    : S3;        // any alu
 3492 %}
 3493 
 3494 // Integer ALU reg-reg operation
 3495 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
 3496 %{
 3497     single_instruction;
 3498     dst    : S4(write);
 3499     src    : S3(read);
 3500     DECODE : S0;        // any decoder
 3501     ALU    : S3;        // any alu
 3502 %}
 3503 
 3504 // Integer ALU reg-reg operation
 3505 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
 3506 %{
 3507     single_instruction;
 3508     dst    : S4(write);
 3509     src    : S3(read);
 3510     D0     : S0;        // big decoder only
 3511     ALU    : S3;        // any alu
 3512 %}
 3513 
 3514 // Integer ALU reg-mem operation
 3515 pipe_class ialu_reg_mem(rRegI dst, memory mem)
 3516 %{
 3517     single_instruction;
 3518     dst    : S5(write);
 3519     mem    : S3(read);
 3520     D0     : S0;        // big decoder only
 3521     ALU    : S4;        // any alu
 3522     MEM    : S3;        // any mem
 3523 %}
 3524 
 3525 // Integer mem operation (prefetch)
 3526 pipe_class ialu_mem(memory mem)
 3527 %{
 3528     single_instruction;
 3529     mem    : S3(read);
 3530     D0     : S0;        // big decoder only
 3531     MEM    : S3;        // any mem
 3532 %}
 3533 
 3534 // Integer Store to Memory
 3535 pipe_class ialu_mem_reg(memory mem, rRegI src)
 3536 %{
 3537     single_instruction;
 3538     mem    : S3(read);
 3539     src    : S5(read);
 3540     D0     : S0;        // big decoder only
 3541     ALU    : S4;        // any alu
 3542     MEM    : S3;
 3543 %}
 3544 
 3545 // // Long Store to Memory
 3546 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
 3547 // %{
 3548 //     instruction_count(2);
 3549 //     mem    : S3(read);
 3550 //     src    : S5(read);
 3551 //     D0     : S0(2);          // big decoder only; twice
 3552 //     ALU    : S4(2);     // any 2 alus
 3553 //     MEM    : S3(2);  // Both mems
 3554 // %}
 3555 
 3556 // Integer Store to Memory
 3557 pipe_class ialu_mem_imm(memory mem)
 3558 %{
 3559     single_instruction;
 3560     mem    : S3(read);
 3561     D0     : S0;        // big decoder only
 3562     ALU    : S4;        // any alu
 3563     MEM    : S3;
 3564 %}
 3565 
 3566 // Integer ALU0 reg-reg operation
 3567 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
 3568 %{
 3569     single_instruction;
 3570     dst    : S4(write);
 3571     src    : S3(read);
 3572     D0     : S0;        // Big decoder only
 3573     ALU0   : S3;        // only alu0
 3574 %}
 3575 
 3576 // Integer ALU0 reg-mem operation
 3577 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
 3578 %{
 3579     single_instruction;
 3580     dst    : S5(write);
 3581     mem    : S3(read);
 3582     D0     : S0;        // big decoder only
 3583     ALU0   : S4;        // ALU0 only
 3584     MEM    : S3;        // any mem
 3585 %}
 3586 
 3587 // Integer ALU reg-reg operation
 3588 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
 3589 %{
 3590     single_instruction;
 3591     cr     : S4(write);
 3592     src1   : S3(read);
 3593     src2   : S3(read);
 3594     DECODE : S0;        // any decoder
 3595     ALU    : S3;        // any alu
 3596 %}
 3597 
 3598 // Integer ALU reg-imm operation
 3599 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
 3600 %{
 3601     single_instruction;
 3602     cr     : S4(write);
 3603     src1   : S3(read);
 3604     DECODE : S0;        // any decoder
 3605     ALU    : S3;        // any alu
 3606 %}
 3607 
 3608 // Integer ALU reg-mem operation
 3609 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
 3610 %{
 3611     single_instruction;
 3612     cr     : S4(write);
 3613     src1   : S3(read);
 3614     src2   : S3(read);
 3615     D0     : S0;        // big decoder only
 3616     ALU    : S4;        // any alu
 3617     MEM    : S3;
 3618 %}
 3619 
 3620 // Conditional move reg-reg
 3621 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
 3622 %{
 3623     instruction_count(4);
 3624     y      : S4(read);
 3625     q      : S3(read);
 3626     p      : S3(read);
 3627     DECODE : S0(4);     // any decoder
 3628 %}
 3629 
 3630 // Conditional move reg-reg
 3631 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
 3632 %{
 3633     single_instruction;
 3634     dst    : S4(write);
 3635     src    : S3(read);
 3636     cr     : S3(read);
 3637     DECODE : S0;        // any decoder
 3638 %}
 3639 
 3640 // Conditional move reg-mem
 3641 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
 3642 %{
 3643     single_instruction;
 3644     dst    : S4(write);
 3645     src    : S3(read);
 3646     cr     : S3(read);
 3647     DECODE : S0;        // any decoder
 3648     MEM    : S3;
 3649 %}
 3650 
 3651 // Conditional move reg-reg long
 3652 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
 3653 %{
 3654     single_instruction;
 3655     dst    : S4(write);
 3656     src    : S3(read);
 3657     cr     : S3(read);
 3658     DECODE : S0(2);     // any 2 decoders
 3659 %}
 3660 
 3661 // Float reg-reg operation
 3662 pipe_class fpu_reg(regD dst)
 3663 %{
 3664     instruction_count(2);
 3665     dst    : S3(read);
 3666     DECODE : S0(2);     // any 2 decoders
 3667     FPU    : S3;
 3668 %}
 3669 
 3670 // Float reg-reg operation
 3671 pipe_class fpu_reg_reg(regD dst, regD src)
 3672 %{
 3673     instruction_count(2);
 3674     dst    : S4(write);
 3675     src    : S3(read);
 3676     DECODE : S0(2);     // any 2 decoders
 3677     FPU    : S3;
 3678 %}
 3679 
 3680 // Float reg-reg operation
 3681 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
 3682 %{
 3683     instruction_count(3);
 3684     dst    : S4(write);
 3685     src1   : S3(read);
 3686     src2   : S3(read);
 3687     DECODE : S0(3);     // any 3 decoders
 3688     FPU    : S3(2);
 3689 %}
 3690 
 3691 // Float reg-reg operation
 3692 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
 3693 %{
 3694     instruction_count(4);
 3695     dst    : S4(write);
 3696     src1   : S3(read);
 3697     src2   : S3(read);
 3698     src3   : S3(read);
 3699     DECODE : S0(4);     // any 3 decoders
 3700     FPU    : S3(2);
 3701 %}
 3702 
 3703 // Float reg-reg operation
 3704 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
 3705 %{
 3706     instruction_count(4);
 3707     dst    : S4(write);
 3708     src1   : S3(read);
 3709     src2   : S3(read);
 3710     src3   : S3(read);
 3711     DECODE : S1(3);     // any 3 decoders
 3712     D0     : S0;        // Big decoder only
 3713     FPU    : S3(2);
 3714     MEM    : S3;
 3715 %}
 3716 
 3717 // Float reg-mem operation
 3718 pipe_class fpu_reg_mem(regD dst, memory mem)
 3719 %{
 3720     instruction_count(2);
 3721     dst    : S5(write);
 3722     mem    : S3(read);
 3723     D0     : S0;        // big decoder only
 3724     DECODE : S1;        // any decoder for FPU POP
 3725     FPU    : S4;
 3726     MEM    : S3;        // any mem
 3727 %}
 3728 
 3729 // Float reg-mem operation
 3730 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
 3731 %{
 3732     instruction_count(3);
 3733     dst    : S5(write);
 3734     src1   : S3(read);
 3735     mem    : S3(read);
 3736     D0     : S0;        // big decoder only
 3737     DECODE : S1(2);     // any decoder for FPU POP
 3738     FPU    : S4;
 3739     MEM    : S3;        // any mem
 3740 %}
 3741 
 3742 // Float mem-reg operation
 3743 pipe_class fpu_mem_reg(memory mem, regD src)
 3744 %{
 3745     instruction_count(2);
 3746     src    : S5(read);
 3747     mem    : S3(read);
 3748     DECODE : S0;        // any decoder for FPU PUSH
 3749     D0     : S1;        // big decoder only
 3750     FPU    : S4;
 3751     MEM    : S3;        // any mem
 3752 %}
 3753 
 3754 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
 3755 %{
 3756     instruction_count(3);
 3757     src1   : S3(read);
 3758     src2   : S3(read);
 3759     mem    : S3(read);
 3760     DECODE : S0(2);     // any decoder for FPU PUSH
 3761     D0     : S1;        // big decoder only
 3762     FPU    : S4;
 3763     MEM    : S3;        // any mem
 3764 %}
 3765 
 3766 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
 3767 %{
 3768     instruction_count(3);
 3769     src1   : S3(read);
 3770     src2   : S3(read);
 3771     mem    : S4(read);
 3772     DECODE : S0;        // any decoder for FPU PUSH
 3773     D0     : S0(2);     // big decoder only
 3774     FPU    : S4;
 3775     MEM    : S3(2);     // any mem
 3776 %}
 3777 
 3778 pipe_class fpu_mem_mem(memory dst, memory src1)
 3779 %{
 3780     instruction_count(2);
 3781     src1   : S3(read);
 3782     dst    : S4(read);
 3783     D0     : S0(2);     // big decoder only
 3784     MEM    : S3(2);     // any mem
 3785 %}
 3786 
 3787 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
 3788 %{
 3789     instruction_count(3);
 3790     src1   : S3(read);
 3791     src2   : S3(read);
 3792     dst    : S4(read);
 3793     D0     : S0(3);     // big decoder only
 3794     FPU    : S4;
 3795     MEM    : S3(3);     // any mem
 3796 %}
 3797 
 3798 pipe_class fpu_mem_reg_con(memory mem, regD src1)
 3799 %{
 3800     instruction_count(3);
 3801     src1   : S4(read);
 3802     mem    : S4(read);
 3803     DECODE : S0;        // any decoder for FPU PUSH
 3804     D0     : S0(2);     // big decoder only
 3805     FPU    : S4;
 3806     MEM    : S3(2);     // any mem
 3807 %}
 3808 
 3809 // Float load constant
 3810 pipe_class fpu_reg_con(regD dst)
 3811 %{
 3812     instruction_count(2);
 3813     dst    : S5(write);
 3814     D0     : S0;        // big decoder only for the load
 3815     DECODE : S1;        // any decoder for FPU POP
 3816     FPU    : S4;
 3817     MEM    : S3;        // any mem
 3818 %}
 3819 
 3820 // Float load constant
 3821 pipe_class fpu_reg_reg_con(regD dst, regD src)
 3822 %{
 3823     instruction_count(3);
 3824     dst    : S5(write);
 3825     src    : S3(read);
 3826     D0     : S0;        // big decoder only for the load
 3827     DECODE : S1(2);     // any decoder for FPU POP
 3828     FPU    : S4;
 3829     MEM    : S3;        // any mem
 3830 %}
 3831 
 3832 // UnConditional branch
 3833 pipe_class pipe_jmp(label labl)
 3834 %{
 3835     single_instruction;
 3836     BR   : S3;
 3837 %}
 3838 
 3839 // Conditional branch
 3840 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
 3841 %{
 3842     single_instruction;
 3843     cr    : S1(read);
 3844     BR    : S3;
 3845 %}
 3846 
 3847 // Allocation idiom
 3848 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
 3849 %{
 3850     instruction_count(1); force_serialization;
 3851     fixed_latency(6);
 3852     heap_ptr : S3(read);
 3853     DECODE   : S0(3);
 3854     D0       : S2;
 3855     MEM      : S3;
 3856     ALU      : S3(2);
 3857     dst      : S5(write);
 3858     BR       : S5;
 3859 %}
 3860 
 3861 // Generic big/slow expanded idiom
 3862 pipe_class pipe_slow()
 3863 %{
 3864     instruction_count(10); multiple_bundles; force_serialization;
 3865     fixed_latency(100);
 3866     D0  : S0(2);
 3867     MEM : S3(2);
 3868 %}
 3869 
 3870 // The real do-nothing guy
 3871 pipe_class empty()
 3872 %{
 3873     instruction_count(0);
 3874 %}
 3875 
 3876 // Define the class for the Nop node
 3877 define
 3878 %{
 3879    MachNop = empty;
 3880 %}
 3881 
 3882 %}
 3883 
 3884 //----------INSTRUCTIONS-------------------------------------------------------
 3885 //
 3886 // match      -- States which machine-independent subtree may be replaced
 3887 //               by this instruction.
 3888 // ins_cost   -- The estimated cost of this instruction is used by instruction
 3889 //               selection to identify a minimum cost tree of machine
 3890 //               instructions that matches a tree of machine-independent
 3891 //               instructions.
 3892 // format     -- A string providing the disassembly for this instruction.
 3893 //               The value of an instruction's operand may be inserted
 3894 //               by referring to it with a '$' prefix.
 3895 // opcode     -- Three instruction opcodes may be provided.  These are referred
 3896 //               to within an encode class as $primary, $secondary, and $tertiary
 3897 //               rrspectively.  The primary opcode is commonly used to
 3898 //               indicate the type of machine instruction, while secondary
 3899 //               and tertiary are often used for prefix options or addressing
 3900 //               modes.
 3901 // ins_encode -- A list of encode classes with parameters. The encode class
 3902 //               name must have been defined in an 'enc_class' specification
 3903 //               in the encode section of the architecture description.
 3904 
 3905 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
 3906 // Load Float
 3907 instruct MoveF2VL(vlRegF dst, regF src) %{
 3908   match(Set dst src);
 3909   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 3910   ins_encode %{
 3911     ShouldNotReachHere();
 3912   %}
 3913   ins_pipe( fpu_reg_reg );
 3914 %}
 3915 
 3916 // Load Float
 3917 instruct MoveF2LEG(legRegF dst, regF src) %{
 3918   match(Set dst src);
 3919   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 3920   ins_encode %{
 3921     ShouldNotReachHere();
 3922   %}
 3923   ins_pipe( fpu_reg_reg );
 3924 %}
 3925 
 3926 // Load Float
 3927 instruct MoveVL2F(regF dst, vlRegF src) %{
 3928   match(Set dst src);
 3929   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 3930   ins_encode %{
 3931     ShouldNotReachHere();
 3932   %}
 3933   ins_pipe( fpu_reg_reg );
 3934 %}
 3935 
 3936 // Load Float
 3937 instruct MoveLEG2F(regF dst, legRegF src) %{
 3938   match(Set dst src);
 3939   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 3940   ins_encode %{
 3941     ShouldNotReachHere();
 3942   %}
 3943   ins_pipe( fpu_reg_reg );
 3944 %}
 3945 
 3946 // Load Double
 3947 instruct MoveD2VL(vlRegD dst, regD src) %{
 3948   match(Set dst src);
 3949   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 3950   ins_encode %{
 3951     ShouldNotReachHere();
 3952   %}
 3953   ins_pipe( fpu_reg_reg );
 3954 %}
 3955 
 3956 // Load Double
 3957 instruct MoveD2LEG(legRegD dst, regD src) %{
 3958   match(Set dst src);
 3959   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 3960   ins_encode %{
 3961     ShouldNotReachHere();
 3962   %}
 3963   ins_pipe( fpu_reg_reg );
 3964 %}
 3965 
 3966 // Load Double
 3967 instruct MoveVL2D(regD dst, vlRegD src) %{
 3968   match(Set dst src);
 3969   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 3970   ins_encode %{
 3971     ShouldNotReachHere();
 3972   %}
 3973   ins_pipe( fpu_reg_reg );
 3974 %}
 3975 
 3976 // Load Double
 3977 instruct MoveLEG2D(regD dst, legRegD src) %{
 3978   match(Set dst src);
 3979   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 3980   ins_encode %{
 3981     ShouldNotReachHere();
 3982   %}
 3983   ins_pipe( fpu_reg_reg );
 3984 %}
 3985 
 3986 //----------Load/Store/Move Instructions---------------------------------------
 3987 //----------Load Instructions--------------------------------------------------
 3988 
 3989 // Load Byte (8 bit signed)
 3990 instruct loadB(rRegI dst, memory mem)
 3991 %{
 3992   match(Set dst (LoadB mem));
 3993 
 3994   ins_cost(125);
 3995   format %{ "movsbl  $dst, $mem\t# byte" %}
 3996 
 3997   ins_encode %{
 3998     __ movsbl($dst$$Register, $mem$$Address);
 3999   %}
 4000 
 4001   ins_pipe(ialu_reg_mem);
 4002 %}
 4003 
 4004 // Load Byte (8 bit signed) into Long Register
 4005 instruct loadB2L(rRegL dst, memory mem)
 4006 %{
 4007   match(Set dst (ConvI2L (LoadB mem)));
 4008 
 4009   ins_cost(125);
 4010   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
 4011 
 4012   ins_encode %{
 4013     __ movsbq($dst$$Register, $mem$$Address);
 4014   %}
 4015 
 4016   ins_pipe(ialu_reg_mem);
 4017 %}
 4018 
 4019 // Load Unsigned Byte (8 bit UNsigned)
 4020 instruct loadUB(rRegI dst, memory mem)
 4021 %{
 4022   match(Set dst (LoadUB mem));
 4023 
 4024   ins_cost(125);
 4025   format %{ "movzbl  $dst, $mem\t# ubyte" %}
 4026 
 4027   ins_encode %{
 4028     __ movzbl($dst$$Register, $mem$$Address);
 4029   %}
 4030 
 4031   ins_pipe(ialu_reg_mem);
 4032 %}
 4033 
 4034 // Load Unsigned Byte (8 bit UNsigned) into Long Register
 4035 instruct loadUB2L(rRegL dst, memory mem)
 4036 %{
 4037   match(Set dst (ConvI2L (LoadUB mem)));
 4038 
 4039   ins_cost(125);
 4040   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
 4041 
 4042   ins_encode %{
 4043     __ movzbq($dst$$Register, $mem$$Address);
 4044   %}
 4045 
 4046   ins_pipe(ialu_reg_mem);
 4047 %}
 4048 
 4049 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
 4050 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 4051   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
 4052   effect(KILL cr);
 4053 
 4054   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
 4055             "andl    $dst, right_n_bits($mask, 8)" %}
 4056   ins_encode %{
 4057     Register Rdst = $dst$$Register;
 4058     __ movzbq(Rdst, $mem$$Address);
 4059     __ andl(Rdst, $mask$$constant & right_n_bits(8));
 4060   %}
 4061   ins_pipe(ialu_reg_mem);
 4062 %}
 4063 
 4064 // Load Short (16 bit signed)
 4065 instruct loadS(rRegI dst, memory mem)
 4066 %{
 4067   match(Set dst (LoadS mem));
 4068 
 4069   ins_cost(125);
 4070   format %{ "movswl $dst, $mem\t# short" %}
 4071 
 4072   ins_encode %{
 4073     __ movswl($dst$$Register, $mem$$Address);
 4074   %}
 4075 
 4076   ins_pipe(ialu_reg_mem);
 4077 %}
 4078 
 4079 // Load Short (16 bit signed) to Byte (8 bit signed)
 4080 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4081   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
 4082 
 4083   ins_cost(125);
 4084   format %{ "movsbl $dst, $mem\t# short -> byte" %}
 4085   ins_encode %{
 4086     __ movsbl($dst$$Register, $mem$$Address);
 4087   %}
 4088   ins_pipe(ialu_reg_mem);
 4089 %}
 4090 
 4091 // Load Short (16 bit signed) into Long Register
 4092 instruct loadS2L(rRegL dst, memory mem)
 4093 %{
 4094   match(Set dst (ConvI2L (LoadS mem)));
 4095 
 4096   ins_cost(125);
 4097   format %{ "movswq $dst, $mem\t# short -> long" %}
 4098 
 4099   ins_encode %{
 4100     __ movswq($dst$$Register, $mem$$Address);
 4101   %}
 4102 
 4103   ins_pipe(ialu_reg_mem);
 4104 %}
 4105 
 4106 // Load Unsigned Short/Char (16 bit UNsigned)
 4107 instruct loadUS(rRegI dst, memory mem)
 4108 %{
 4109   match(Set dst (LoadUS mem));
 4110 
 4111   ins_cost(125);
 4112   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
 4113 
 4114   ins_encode %{
 4115     __ movzwl($dst$$Register, $mem$$Address);
 4116   %}
 4117 
 4118   ins_pipe(ialu_reg_mem);
 4119 %}
 4120 
 4121 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
 4122 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4123   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
 4124 
 4125   ins_cost(125);
 4126   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
 4127   ins_encode %{
 4128     __ movsbl($dst$$Register, $mem$$Address);
 4129   %}
 4130   ins_pipe(ialu_reg_mem);
 4131 %}
 4132 
 4133 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
 4134 instruct loadUS2L(rRegL dst, memory mem)
 4135 %{
 4136   match(Set dst (ConvI2L (LoadUS mem)));
 4137 
 4138   ins_cost(125);
 4139   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
 4140 
 4141   ins_encode %{
 4142     __ movzwq($dst$$Register, $mem$$Address);
 4143   %}
 4144 
 4145   ins_pipe(ialu_reg_mem);
 4146 %}
 4147 
 4148 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
 4149 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 4150   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 4151 
 4152   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
 4153   ins_encode %{
 4154     __ movzbq($dst$$Register, $mem$$Address);
 4155   %}
 4156   ins_pipe(ialu_reg_mem);
 4157 %}
 4158 
 4159 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
 4160 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 4161   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 4162   effect(KILL cr);
 4163 
 4164   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
 4165             "andl    $dst, right_n_bits($mask, 16)" %}
 4166   ins_encode %{
 4167     Register Rdst = $dst$$Register;
 4168     __ movzwq(Rdst, $mem$$Address);
 4169     __ andl(Rdst, $mask$$constant & right_n_bits(16));
 4170   %}
 4171   ins_pipe(ialu_reg_mem);
 4172 %}
 4173 
 4174 // Load Integer
 4175 instruct loadI(rRegI dst, memory mem)
 4176 %{
 4177   match(Set dst (LoadI mem));
 4178 
 4179   ins_cost(125);
 4180   format %{ "movl    $dst, $mem\t# int" %}
 4181 
 4182   ins_encode %{
 4183     __ movl($dst$$Register, $mem$$Address);
 4184   %}
 4185 
 4186   ins_pipe(ialu_reg_mem);
 4187 %}
 4188 
 4189 // Load Integer (32 bit signed) to Byte (8 bit signed)
 4190 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4191   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
 4192 
 4193   ins_cost(125);
 4194   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
 4195   ins_encode %{
 4196     __ movsbl($dst$$Register, $mem$$Address);
 4197   %}
 4198   ins_pipe(ialu_reg_mem);
 4199 %}
 4200 
 4201 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
 4202 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
 4203   match(Set dst (AndI (LoadI mem) mask));
 4204 
 4205   ins_cost(125);
 4206   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
 4207   ins_encode %{
 4208     __ movzbl($dst$$Register, $mem$$Address);
 4209   %}
 4210   ins_pipe(ialu_reg_mem);
 4211 %}
 4212 
 4213 // Load Integer (32 bit signed) to Short (16 bit signed)
 4214 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
 4215   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
 4216 
 4217   ins_cost(125);
 4218   format %{ "movswl  $dst, $mem\t# int -> short" %}
 4219   ins_encode %{
 4220     __ movswl($dst$$Register, $mem$$Address);
 4221   %}
 4222   ins_pipe(ialu_reg_mem);
 4223 %}
 4224 
 4225 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
 4226 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
 4227   match(Set dst (AndI (LoadI mem) mask));
 4228 
 4229   ins_cost(125);
 4230   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
 4231   ins_encode %{
 4232     __ movzwl($dst$$Register, $mem$$Address);
 4233   %}
 4234   ins_pipe(ialu_reg_mem);
 4235 %}
 4236 
 4237 // Load Integer into Long Register
 4238 instruct loadI2L(rRegL dst, memory mem)
 4239 %{
 4240   match(Set dst (ConvI2L (LoadI mem)));
 4241 
 4242   ins_cost(125);
 4243   format %{ "movslq  $dst, $mem\t# int -> long" %}
 4244 
 4245   ins_encode %{
 4246     __ movslq($dst$$Register, $mem$$Address);
 4247   %}
 4248 
 4249   ins_pipe(ialu_reg_mem);
 4250 %}
 4251 
 4252 // Load Integer with mask 0xFF into Long Register
 4253 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 4254   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 4255 
 4256   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
 4257   ins_encode %{
 4258     __ movzbq($dst$$Register, $mem$$Address);
 4259   %}
 4260   ins_pipe(ialu_reg_mem);
 4261 %}
 4262 
 4263 // Load Integer with mask 0xFFFF into Long Register
 4264 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
 4265   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 4266 
 4267   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
 4268   ins_encode %{
 4269     __ movzwq($dst$$Register, $mem$$Address);
 4270   %}
 4271   ins_pipe(ialu_reg_mem);
 4272 %}
 4273 
 4274 // Load Integer with a 31-bit mask into Long Register
 4275 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
 4276   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 4277   effect(KILL cr);
 4278 
 4279   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
 4280             "andl    $dst, $mask" %}
 4281   ins_encode %{
 4282     Register Rdst = $dst$$Register;
 4283     __ movl(Rdst, $mem$$Address);
 4284     __ andl(Rdst, $mask$$constant);
 4285   %}
 4286   ins_pipe(ialu_reg_mem);
 4287 %}
 4288 
 4289 // Load Unsigned Integer into Long Register
 4290 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
 4291 %{
 4292   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4293 
 4294   ins_cost(125);
 4295   format %{ "movl    $dst, $mem\t# uint -> long" %}
 4296 
 4297   ins_encode %{
 4298     __ movl($dst$$Register, $mem$$Address);
 4299   %}
 4300 
 4301   ins_pipe(ialu_reg_mem);
 4302 %}
 4303 
 4304 // Load Long
 4305 instruct loadL(rRegL dst, memory mem)
 4306 %{
 4307   match(Set dst (LoadL mem));
 4308 
 4309   ins_cost(125);
 4310   format %{ "movq    $dst, $mem\t# long" %}
 4311 
 4312   ins_encode %{
 4313     __ movq($dst$$Register, $mem$$Address);
 4314   %}
 4315 
 4316   ins_pipe(ialu_reg_mem); // XXX
 4317 %}
 4318 
 4319 // Load Range
 4320 instruct loadRange(rRegI dst, memory mem)
 4321 %{
 4322   match(Set dst (LoadRange mem));
 4323 
 4324   ins_cost(125); // XXX
 4325   format %{ "movl    $dst, $mem\t# range" %}
 4326   ins_encode %{
 4327     __ movl($dst$$Register, $mem$$Address);
 4328   %}
 4329   ins_pipe(ialu_reg_mem);
 4330 %}
 4331 
 4332 // Load Pointer
 4333 instruct loadP(rRegP dst, memory mem)
 4334 %{
 4335   match(Set dst (LoadP mem));
 4336   predicate(n->as_Load()->barrier_data() == 0);
 4337 
 4338   ins_cost(125); // XXX
 4339   format %{ "movq    $dst, $mem\t# ptr" %}
 4340   ins_encode %{
 4341     __ movq($dst$$Register, $mem$$Address);
 4342   %}
 4343   ins_pipe(ialu_reg_mem); // XXX
 4344 %}
 4345 
 4346 // Load Compressed Pointer
 4347 instruct loadN(rRegN dst, memory mem)
 4348 %{
 4349    predicate(n->as_Load()->barrier_data() == 0);
 4350    match(Set dst (LoadN mem));
 4351 
 4352    ins_cost(125); // XXX
 4353    format %{ "movl    $dst, $mem\t# compressed ptr" %}
 4354    ins_encode %{
 4355      __ movl($dst$$Register, $mem$$Address);
 4356    %}
 4357    ins_pipe(ialu_reg_mem); // XXX
 4358 %}
 4359 
 4360 
 4361 // Load Klass Pointer
 4362 instruct loadKlass(rRegP dst, memory mem)
 4363 %{
 4364   match(Set dst (LoadKlass mem));
 4365 
 4366   ins_cost(125); // XXX
 4367   format %{ "movq    $dst, $mem\t# class" %}
 4368   ins_encode %{
 4369     __ movq($dst$$Register, $mem$$Address);
 4370   %}
 4371   ins_pipe(ialu_reg_mem); // XXX
 4372 %}
 4373 
 4374 // Load narrow Klass Pointer
 4375 instruct loadNKlass(rRegN dst, memory mem)
 4376 %{
 4377   predicate(!UseCompactObjectHeaders);
 4378   match(Set dst (LoadNKlass mem));
 4379 
 4380   ins_cost(125); // XXX
 4381   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
 4382   ins_encode %{
 4383     __ movl($dst$$Register, $mem$$Address);
 4384   %}
 4385   ins_pipe(ialu_reg_mem); // XXX
 4386 %}
 4387 
 4388 instruct loadNKlassCompactHeaders(rRegN dst, memory mem, rFlagsReg cr)
 4389 %{
 4390   predicate(UseCompactObjectHeaders);
 4391   match(Set dst (LoadNKlass mem));
 4392   effect(KILL cr);
 4393   ins_cost(125);
 4394   format %{
 4395     "movl    $dst, $mem\t# compressed klass ptr, shifted\n\t"
 4396     "shrl    $dst, markWord::klass_shift"
 4397   %}
 4398   ins_encode %{
 4399     // The incoming address is pointing into obj-start + Type::klass_offset(). We need to extract
 4400     // obj-start, so that we can load from the object's mark-word instead.
 4401     Register d = $dst$$Register;
 4402     Address  s = ($mem$$Address).plus_disp(-Type::klass_offset());
 4403     if (UseAPX) {
 4404       __ eshrl(d, s, markWord::klass_shift, false);
 4405     } else {
 4406       __ movl(d, s);
 4407       __ shrl(d, markWord::klass_shift);
 4408     }
 4409   %}
 4410   ins_pipe(ialu_reg_mem);
 4411 %}
 4412 
 4413 // Load Float
 4414 instruct loadF(regF dst, memory mem)
 4415 %{
 4416   match(Set dst (LoadF mem));
 4417 
 4418   ins_cost(145); // XXX
 4419   format %{ "movss   $dst, $mem\t# float" %}
 4420   ins_encode %{
 4421     __ movflt($dst$$XMMRegister, $mem$$Address);
 4422   %}
 4423   ins_pipe(pipe_slow); // XXX
 4424 %}
 4425 
 4426 // Load Double
 4427 instruct loadD_partial(regD dst, memory mem)
 4428 %{
 4429   predicate(!UseXmmLoadAndClearUpper);
 4430   match(Set dst (LoadD mem));
 4431 
 4432   ins_cost(145); // XXX
 4433   format %{ "movlpd  $dst, $mem\t# double" %}
 4434   ins_encode %{
 4435     __ movdbl($dst$$XMMRegister, $mem$$Address);
 4436   %}
 4437   ins_pipe(pipe_slow); // XXX
 4438 %}
 4439 
 4440 instruct loadD(regD dst, memory mem)
 4441 %{
 4442   predicate(UseXmmLoadAndClearUpper);
 4443   match(Set dst (LoadD mem));
 4444 
 4445   ins_cost(145); // XXX
 4446   format %{ "movsd   $dst, $mem\t# double" %}
 4447   ins_encode %{
 4448     __ movdbl($dst$$XMMRegister, $mem$$Address);
 4449   %}
 4450   ins_pipe(pipe_slow); // XXX
 4451 %}
 4452 
 4453 // max = java.lang.Math.max(float a, float b)
 4454 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 4455   predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
 4456   match(Set dst (MaxF a b));
 4457   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 4458   format %{ "maxF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
 4459   ins_encode %{
 4460     __ vminmax_fp(Op_MaxV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
 4461   %}
 4462   ins_pipe( pipe_slow );
 4463 %}
 4464 
 4465 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
 4466   predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
 4467   match(Set dst (MaxF a b));
 4468   effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
 4469 
 4470   format %{ "maxF_reduction $dst, $a, $b \t!using $xtmp and $rtmp as TEMP" %}
 4471   ins_encode %{
 4472     emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
 4473                     false /*min*/, true /*single*/);
 4474   %}
 4475   ins_pipe( pipe_slow );
 4476 %}
 4477 
 4478 // max = java.lang.Math.max(double a, double b)
 4479 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 4480   predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
 4481   match(Set dst (MaxD a b));
 4482   effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
 4483   format %{ "maxD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
 4484   ins_encode %{
 4485     __ vminmax_fp(Op_MaxV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
 4486   %}
 4487   ins_pipe( pipe_slow );
 4488 %}
 4489 
 4490 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
 4491   predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
 4492   match(Set dst (MaxD a b));
 4493   effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
 4494 
 4495   format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
 4496   ins_encode %{
 4497     emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
 4498                     false /*min*/, false /*single*/);
 4499   %}
 4500   ins_pipe( pipe_slow );
 4501 %}
 4502 
 4503 // min = java.lang.Math.min(float a, float b)
 4504 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 4505   predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
 4506   match(Set dst (MinF a b));
 4507   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 4508   format %{ "minF $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
 4509   ins_encode %{
 4510     __ vminmax_fp(Op_MinV, T_FLOAT, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
 4511   %}
 4512   ins_pipe( pipe_slow );
 4513 %}
 4514 
 4515 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xtmp, rRegI rtmp, rFlagsReg cr) %{
 4516   predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
 4517   match(Set dst (MinF a b));
 4518   effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
 4519 
 4520   format %{ "minF_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
 4521   ins_encode %{
 4522     emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
 4523                     true /*min*/, true /*single*/);
 4524   %}
 4525   ins_pipe( pipe_slow );
 4526 %}
 4527 
 4528 // min = java.lang.Math.min(double a, double b)
 4529 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 4530   predicate(UseAVX > 0 && !VLoopReductions::is_reduction(n));
 4531   match(Set dst (MinD a b));
 4532   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 4533     format %{ "minD $dst, $a, $b \t! using $tmp, $atmp and $btmp as TEMP" %}
 4534   ins_encode %{
 4535     __ vminmax_fp(Op_MinV, T_DOUBLE, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, Assembler::AVX_128bit);
 4536   %}
 4537   ins_pipe( pipe_slow );
 4538 %}
 4539 
 4540 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xtmp, rRegL rtmp, rFlagsReg cr) %{
 4541   predicate(UseAVX > 0 && VLoopReductions::is_reduction(n));
 4542   match(Set dst (MinD a b));
 4543   effect(USE a, USE b, TEMP xtmp, TEMP rtmp, KILL cr);
 4544 
 4545   format %{ "maxD_reduction $dst, $a, $b \t! using $xtmp and $rtmp as TEMP" %}
 4546   ins_encode %{
 4547     emit_fp_min_max(masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xtmp$$XMMRegister, $rtmp$$Register,
 4548                     true /*min*/, false /*single*/);
 4549   %}
 4550   ins_pipe( pipe_slow );
 4551 %}
 4552 
 4553 // Load Effective Address
 4554 instruct leaP8(rRegP dst, indOffset8 mem)
 4555 %{
 4556   match(Set dst mem);
 4557 
 4558   ins_cost(110); // XXX
 4559   format %{ "leaq    $dst, $mem\t# ptr 8" %}
 4560   ins_encode %{
 4561     __ leaq($dst$$Register, $mem$$Address);
 4562   %}
 4563   ins_pipe(ialu_reg_reg_fat);
 4564 %}
 4565 
 4566 instruct leaP32(rRegP dst, indOffset32 mem)
 4567 %{
 4568   match(Set dst mem);
 4569 
 4570   ins_cost(110);
 4571   format %{ "leaq    $dst, $mem\t# ptr 32" %}
 4572   ins_encode %{
 4573     __ leaq($dst$$Register, $mem$$Address);
 4574   %}
 4575   ins_pipe(ialu_reg_reg_fat);
 4576 %}
 4577 
 4578 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
 4579 %{
 4580   match(Set dst mem);
 4581 
 4582   ins_cost(110);
 4583   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
 4584   ins_encode %{
 4585     __ leaq($dst$$Register, $mem$$Address);
 4586   %}
 4587   ins_pipe(ialu_reg_reg_fat);
 4588 %}
 4589 
 4590 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
 4591 %{
 4592   match(Set dst mem);
 4593 
 4594   ins_cost(110);
 4595   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 4596   ins_encode %{
 4597     __ leaq($dst$$Register, $mem$$Address);
 4598   %}
 4599   ins_pipe(ialu_reg_reg_fat);
 4600 %}
 4601 
 4602 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
 4603 %{
 4604   match(Set dst mem);
 4605 
 4606   ins_cost(110);
 4607   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 4608   ins_encode %{
 4609     __ leaq($dst$$Register, $mem$$Address);
 4610   %}
 4611   ins_pipe(ialu_reg_reg_fat);
 4612 %}
 4613 
 4614 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
 4615 %{
 4616   match(Set dst mem);
 4617 
 4618   ins_cost(110);
 4619   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
 4620   ins_encode %{
 4621     __ leaq($dst$$Register, $mem$$Address);
 4622   %}
 4623   ins_pipe(ialu_reg_reg_fat);
 4624 %}
 4625 
 4626 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
 4627 %{
 4628   match(Set dst mem);
 4629 
 4630   ins_cost(110);
 4631   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
 4632   ins_encode %{
 4633     __ leaq($dst$$Register, $mem$$Address);
 4634   %}
 4635   ins_pipe(ialu_reg_reg_fat);
 4636 %}
 4637 
 4638 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
 4639 %{
 4640   match(Set dst mem);
 4641 
 4642   ins_cost(110);
 4643   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
 4644   ins_encode %{
 4645     __ leaq($dst$$Register, $mem$$Address);
 4646   %}
 4647   ins_pipe(ialu_reg_reg_fat);
 4648 %}
 4649 
 4650 // Load Effective Address which uses Narrow (32-bits) oop
 4651 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
 4652 %{
 4653   predicate(UseCompressedOops && (CompressedOops::shift() != 0));
 4654   match(Set dst mem);
 4655 
 4656   ins_cost(110);
 4657   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
 4658   ins_encode %{
 4659     __ leaq($dst$$Register, $mem$$Address);
 4660   %}
 4661   ins_pipe(ialu_reg_reg_fat);
 4662 %}
 4663 
 4664 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
 4665 %{
 4666   predicate(CompressedOops::shift() == 0);
 4667   match(Set dst mem);
 4668 
 4669   ins_cost(110); // XXX
 4670   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
 4671   ins_encode %{
 4672     __ leaq($dst$$Register, $mem$$Address);
 4673   %}
 4674   ins_pipe(ialu_reg_reg_fat);
 4675 %}
 4676 
 4677 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
 4678 %{
 4679   predicate(CompressedOops::shift() == 0);
 4680   match(Set dst mem);
 4681 
 4682   ins_cost(110);
 4683   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
 4684   ins_encode %{
 4685     __ leaq($dst$$Register, $mem$$Address);
 4686   %}
 4687   ins_pipe(ialu_reg_reg_fat);
 4688 %}
 4689 
 4690 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
 4691 %{
 4692   predicate(CompressedOops::shift() == 0);
 4693   match(Set dst mem);
 4694 
 4695   ins_cost(110);
 4696   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
 4697   ins_encode %{
 4698     __ leaq($dst$$Register, $mem$$Address);
 4699   %}
 4700   ins_pipe(ialu_reg_reg_fat);
 4701 %}
 4702 
 4703 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
 4704 %{
 4705   predicate(CompressedOops::shift() == 0);
 4706   match(Set dst mem);
 4707 
 4708   ins_cost(110);
 4709   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
 4710   ins_encode %{
 4711     __ leaq($dst$$Register, $mem$$Address);
 4712   %}
 4713   ins_pipe(ialu_reg_reg_fat);
 4714 %}
 4715 
 4716 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
 4717 %{
 4718   predicate(CompressedOops::shift() == 0);
 4719   match(Set dst mem);
 4720 
 4721   ins_cost(110);
 4722   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
 4723   ins_encode %{
 4724     __ leaq($dst$$Register, $mem$$Address);
 4725   %}
 4726   ins_pipe(ialu_reg_reg_fat);
 4727 %}
 4728 
 4729 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
 4730 %{
 4731   predicate(CompressedOops::shift() == 0);
 4732   match(Set dst mem);
 4733 
 4734   ins_cost(110);
 4735   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
 4736   ins_encode %{
 4737     __ leaq($dst$$Register, $mem$$Address);
 4738   %}
 4739   ins_pipe(ialu_reg_reg_fat);
 4740 %}
 4741 
 4742 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
 4743 %{
 4744   predicate(CompressedOops::shift() == 0);
 4745   match(Set dst mem);
 4746 
 4747   ins_cost(110);
 4748   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
 4749   ins_encode %{
 4750     __ leaq($dst$$Register, $mem$$Address);
 4751   %}
 4752   ins_pipe(ialu_reg_reg_fat);
 4753 %}
 4754 
 4755 instruct loadConI(rRegI dst, immI src)
 4756 %{
 4757   match(Set dst src);
 4758 
 4759   format %{ "movl    $dst, $src\t# int" %}
 4760   ins_encode %{
 4761     __ movl($dst$$Register, $src$$constant);
 4762   %}
 4763   ins_pipe(ialu_reg_fat); // XXX
 4764 %}
 4765 
 4766 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
 4767 %{
 4768   match(Set dst src);
 4769   effect(KILL cr);
 4770 
 4771   ins_cost(50);
 4772   format %{ "xorl    $dst, $dst\t# int" %}
 4773   ins_encode %{
 4774     __ xorl($dst$$Register, $dst$$Register);
 4775   %}
 4776   ins_pipe(ialu_reg);
 4777 %}
 4778 
 4779 instruct loadConL(rRegL dst, immL src)
 4780 %{
 4781   match(Set dst src);
 4782 
 4783   ins_cost(150);
 4784   format %{ "movq    $dst, $src\t# long" %}
 4785   ins_encode %{
 4786     __ mov64($dst$$Register, $src$$constant);
 4787   %}
 4788   ins_pipe(ialu_reg);
 4789 %}
 4790 
 4791 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
 4792 %{
 4793   match(Set dst src);
 4794   effect(KILL cr);
 4795 
 4796   ins_cost(50);
 4797   format %{ "xorl    $dst, $dst\t# long" %}
 4798   ins_encode %{
 4799     __ xorl($dst$$Register, $dst$$Register);
 4800   %}
 4801   ins_pipe(ialu_reg); // XXX
 4802 %}
 4803 
 4804 instruct loadConUL32(rRegL dst, immUL32 src)
 4805 %{
 4806   match(Set dst src);
 4807 
 4808   ins_cost(60);
 4809   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
 4810   ins_encode %{
 4811     __ movl($dst$$Register, $src$$constant);
 4812   %}
 4813   ins_pipe(ialu_reg);
 4814 %}
 4815 
 4816 instruct loadConL32(rRegL dst, immL32 src)
 4817 %{
 4818   match(Set dst src);
 4819 
 4820   ins_cost(70);
 4821   format %{ "movq    $dst, $src\t# long (32-bit)" %}
 4822   ins_encode %{
 4823     __ movq($dst$$Register, $src$$constant);
 4824   %}
 4825   ins_pipe(ialu_reg);
 4826 %}
 4827 
 4828 instruct loadConP(rRegP dst, immP con) %{
 4829   match(Set dst con);
 4830 
 4831   format %{ "movq    $dst, $con\t# ptr" %}
 4832   ins_encode %{
 4833     __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
 4834   %}
 4835   ins_pipe(ialu_reg_fat); // XXX
 4836 %}
 4837 
 4838 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
 4839 %{
 4840   match(Set dst src);
 4841   effect(KILL cr);
 4842 
 4843   ins_cost(50);
 4844   format %{ "xorl    $dst, $dst\t# ptr" %}
 4845   ins_encode %{
 4846     __ xorl($dst$$Register, $dst$$Register);
 4847   %}
 4848   ins_pipe(ialu_reg);
 4849 %}
 4850 
 4851 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
 4852 %{
 4853   match(Set dst src);
 4854   effect(KILL cr);
 4855 
 4856   ins_cost(60);
 4857   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
 4858   ins_encode %{
 4859     __ movl($dst$$Register, $src$$constant);
 4860   %}
 4861   ins_pipe(ialu_reg);
 4862 %}
 4863 
 4864 instruct loadConF(regF dst, immF con) %{
 4865   match(Set dst con);
 4866   ins_cost(125);
 4867   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
 4868   ins_encode %{
 4869     __ movflt($dst$$XMMRegister, $constantaddress($con));
 4870   %}
 4871   ins_pipe(pipe_slow);
 4872 %}
 4873 
 4874 instruct loadConH(regF dst, immH con) %{
 4875   match(Set dst con);
 4876   ins_cost(125);
 4877   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: halffloat=$con" %}
 4878   ins_encode %{
 4879     __ movflt($dst$$XMMRegister, $constantaddress($con));
 4880   %}
 4881   ins_pipe(pipe_slow);
 4882 %}
 4883 
 4884 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
 4885   match(Set dst src);
 4886   effect(KILL cr);
 4887   format %{ "xorq    $dst, $src\t# compressed null pointer" %}
 4888   ins_encode %{
 4889     __ xorq($dst$$Register, $dst$$Register);
 4890   %}
 4891   ins_pipe(ialu_reg);
 4892 %}
 4893 
 4894 instruct loadConN(rRegN dst, immN src) %{
 4895   match(Set dst src);
 4896 
 4897   ins_cost(125);
 4898   format %{ "movl    $dst, $src\t# compressed ptr" %}
 4899   ins_encode %{
 4900     address con = (address)$src$$constant;
 4901     if (con == nullptr) {
 4902       ShouldNotReachHere();
 4903     } else {
 4904       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
 4905     }
 4906   %}
 4907   ins_pipe(ialu_reg_fat); // XXX
 4908 %}
 4909 
 4910 instruct loadConNKlass(rRegN dst, immNKlass src) %{
 4911   match(Set dst src);
 4912 
 4913   ins_cost(125);
 4914   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
 4915   ins_encode %{
 4916     address con = (address)$src$$constant;
 4917     if (con == nullptr) {
 4918       ShouldNotReachHere();
 4919     } else {
 4920       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
 4921     }
 4922   %}
 4923   ins_pipe(ialu_reg_fat); // XXX
 4924 %}
 4925 
 4926 instruct loadConF0(regF dst, immF0 src)
 4927 %{
 4928   match(Set dst src);
 4929   ins_cost(100);
 4930 
 4931   format %{ "xorps   $dst, $dst\t# float 0.0" %}
 4932   ins_encode %{
 4933     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
 4934   %}
 4935   ins_pipe(pipe_slow);
 4936 %}
 4937 
 4938 // Use the same format since predicate() can not be used here.
 4939 instruct loadConD(regD dst, immD con) %{
 4940   match(Set dst con);
 4941   ins_cost(125);
 4942   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
 4943   ins_encode %{
 4944     __ movdbl($dst$$XMMRegister, $constantaddress($con));
 4945   %}
 4946   ins_pipe(pipe_slow);
 4947 %}
 4948 
 4949 instruct loadConD0(regD dst, immD0 src)
 4950 %{
 4951   match(Set dst src);
 4952   ins_cost(100);
 4953 
 4954   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
 4955   ins_encode %{
 4956     __ xorpd($dst$$XMMRegister, $dst$$XMMRegister);
 4957   %}
 4958   ins_pipe(pipe_slow);
 4959 %}
 4960 
 4961 instruct loadSSI(rRegI dst, stackSlotI src)
 4962 %{
 4963   match(Set dst src);
 4964 
 4965   ins_cost(125);
 4966   format %{ "movl    $dst, $src\t# int stk" %}
 4967   ins_encode %{
 4968     __ movl($dst$$Register, $src$$Address);
 4969   %}
 4970   ins_pipe(ialu_reg_mem);
 4971 %}
 4972 
 4973 instruct loadSSL(rRegL dst, stackSlotL src)
 4974 %{
 4975   match(Set dst src);
 4976 
 4977   ins_cost(125);
 4978   format %{ "movq    $dst, $src\t# long stk" %}
 4979   ins_encode %{
 4980     __ movq($dst$$Register, $src$$Address);
 4981   %}
 4982   ins_pipe(ialu_reg_mem);
 4983 %}
 4984 
 4985 instruct loadSSP(rRegP dst, stackSlotP src)
 4986 %{
 4987   match(Set dst src);
 4988 
 4989   ins_cost(125);
 4990   format %{ "movq    $dst, $src\t# ptr stk" %}
 4991   ins_encode %{
 4992     __ movq($dst$$Register, $src$$Address);
 4993   %}
 4994   ins_pipe(ialu_reg_mem);
 4995 %}
 4996 
 4997 instruct loadSSF(regF dst, stackSlotF src)
 4998 %{
 4999   match(Set dst src);
 5000 
 5001   ins_cost(125);
 5002   format %{ "movss   $dst, $src\t# float stk" %}
 5003   ins_encode %{
 5004     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
 5005   %}
 5006   ins_pipe(pipe_slow); // XXX
 5007 %}
 5008 
 5009 // Use the same format since predicate() can not be used here.
 5010 instruct loadSSD(regD dst, stackSlotD src)
 5011 %{
 5012   match(Set dst src);
 5013 
 5014   ins_cost(125);
 5015   format %{ "movsd   $dst, $src\t# double stk" %}
 5016   ins_encode  %{
 5017     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
 5018   %}
 5019   ins_pipe(pipe_slow); // XXX
 5020 %}
 5021 
 5022 // Prefetch instructions for allocation.
 5023 // Must be safe to execute with invalid address (cannot fault).
 5024 
 5025 instruct prefetchAlloc( memory mem ) %{
 5026   predicate(AllocatePrefetchInstr==3);
 5027   match(PrefetchAllocation mem);
 5028   ins_cost(125);
 5029 
 5030   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
 5031   ins_encode %{
 5032     __ prefetchw($mem$$Address);
 5033   %}
 5034   ins_pipe(ialu_mem);
 5035 %}
 5036 
 5037 instruct prefetchAllocNTA( memory mem ) %{
 5038   predicate(AllocatePrefetchInstr==0);
 5039   match(PrefetchAllocation mem);
 5040   ins_cost(125);
 5041 
 5042   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
 5043   ins_encode %{
 5044     __ prefetchnta($mem$$Address);
 5045   %}
 5046   ins_pipe(ialu_mem);
 5047 %}
 5048 
 5049 instruct prefetchAllocT0( memory mem ) %{
 5050   predicate(AllocatePrefetchInstr==1);
 5051   match(PrefetchAllocation mem);
 5052   ins_cost(125);
 5053 
 5054   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
 5055   ins_encode %{
 5056     __ prefetcht0($mem$$Address);
 5057   %}
 5058   ins_pipe(ialu_mem);
 5059 %}
 5060 
 5061 instruct prefetchAllocT2( memory mem ) %{
 5062   predicate(AllocatePrefetchInstr==2);
 5063   match(PrefetchAllocation mem);
 5064   ins_cost(125);
 5065 
 5066   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
 5067   ins_encode %{
 5068     __ prefetcht2($mem$$Address);
 5069   %}
 5070   ins_pipe(ialu_mem);
 5071 %}
 5072 
 5073 //----------Store Instructions-------------------------------------------------
 5074 
 5075 // Store Byte
 5076 instruct storeB(memory mem, rRegI src)
 5077 %{
 5078   match(Set mem (StoreB mem src));
 5079 
 5080   ins_cost(125); // XXX
 5081   format %{ "movb    $mem, $src\t# byte" %}
 5082   ins_encode %{
 5083     __ movb($mem$$Address, $src$$Register);
 5084   %}
 5085   ins_pipe(ialu_mem_reg);
 5086 %}
 5087 
 5088 // Store Char/Short
 5089 instruct storeC(memory mem, rRegI src)
 5090 %{
 5091   match(Set mem (StoreC mem src));
 5092 
 5093   ins_cost(125); // XXX
 5094   format %{ "movw    $mem, $src\t# char/short" %}
 5095   ins_encode %{
 5096     __ movw($mem$$Address, $src$$Register);
 5097   %}
 5098   ins_pipe(ialu_mem_reg);
 5099 %}
 5100 
 5101 // Store Integer
 5102 instruct storeI(memory mem, rRegI src)
 5103 %{
 5104   match(Set mem (StoreI mem src));
 5105 
 5106   ins_cost(125); // XXX
 5107   format %{ "movl    $mem, $src\t# int" %}
 5108   ins_encode %{
 5109     __ movl($mem$$Address, $src$$Register);
 5110   %}
 5111   ins_pipe(ialu_mem_reg);
 5112 %}
 5113 
 5114 // Store Long
 5115 instruct storeL(memory mem, rRegL src)
 5116 %{
 5117   match(Set mem (StoreL mem src));
 5118 
 5119   ins_cost(125); // XXX
 5120   format %{ "movq    $mem, $src\t# long" %}
 5121   ins_encode %{
 5122     __ movq($mem$$Address, $src$$Register);
 5123   %}
 5124   ins_pipe(ialu_mem_reg); // XXX
 5125 %}
 5126 
 5127 // Store Pointer
 5128 instruct storeP(memory mem, any_RegP src)
 5129 %{
 5130   predicate(n->as_Store()->barrier_data() == 0);
 5131   match(Set mem (StoreP mem src));
 5132 
 5133   ins_cost(125); // XXX
 5134   format %{ "movq    $mem, $src\t# ptr" %}
 5135   ins_encode %{
 5136     __ movq($mem$$Address, $src$$Register);
 5137   %}
 5138   ins_pipe(ialu_mem_reg);
 5139 %}
 5140 
 5141 instruct storeImmP0(memory mem, immP0 zero)
 5142 %{
 5143   predicate(UseCompressedOops && (CompressedOops::base() == nullptr) && n->as_Store()->barrier_data() == 0);
 5144   match(Set mem (StoreP mem zero));
 5145 
 5146   ins_cost(125); // XXX
 5147   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
 5148   ins_encode %{
 5149     __ movq($mem$$Address, r12);
 5150   %}
 5151   ins_pipe(ialu_mem_reg);
 5152 %}
 5153 
 5154 // Store Null Pointer, mark word, or other simple pointer constant.
 5155 instruct storeImmP(memory mem, immP31 src)
 5156 %{
 5157   predicate(n->as_Store()->barrier_data() == 0);
 5158   match(Set mem (StoreP mem src));
 5159 
 5160   ins_cost(150); // XXX
 5161   format %{ "movq    $mem, $src\t# ptr" %}
 5162   ins_encode %{
 5163     __ movq($mem$$Address, $src$$constant);
 5164   %}
 5165   ins_pipe(ialu_mem_imm);
 5166 %}
 5167 
 5168 // Store Compressed Pointer
 5169 instruct storeN(memory mem, rRegN src)
 5170 %{
 5171   predicate(n->as_Store()->barrier_data() == 0);
 5172   match(Set mem (StoreN mem src));
 5173 
 5174   ins_cost(125); // XXX
 5175   format %{ "movl    $mem, $src\t# compressed ptr" %}
 5176   ins_encode %{
 5177     __ movl($mem$$Address, $src$$Register);
 5178   %}
 5179   ins_pipe(ialu_mem_reg);
 5180 %}
 5181 
 5182 instruct storeNKlass(memory mem, rRegN src)
 5183 %{
 5184   match(Set mem (StoreNKlass mem src));
 5185 
 5186   ins_cost(125); // XXX
 5187   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 5188   ins_encode %{
 5189     __ movl($mem$$Address, $src$$Register);
 5190   %}
 5191   ins_pipe(ialu_mem_reg);
 5192 %}
 5193 
 5194 instruct storeImmN0(memory mem, immN0 zero)
 5195 %{
 5196   predicate(CompressedOops::base() == nullptr && n->as_Store()->barrier_data() == 0);
 5197   match(Set mem (StoreN mem zero));
 5198 
 5199   ins_cost(125); // XXX
 5200   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
 5201   ins_encode %{
 5202     __ movl($mem$$Address, r12);
 5203   %}
 5204   ins_pipe(ialu_mem_reg);
 5205 %}
 5206 
 5207 instruct storeImmN(memory mem, immN src)
 5208 %{
 5209   predicate(n->as_Store()->barrier_data() == 0);
 5210   match(Set mem (StoreN mem src));
 5211 
 5212   ins_cost(150); // XXX
 5213   format %{ "movl    $mem, $src\t# compressed ptr" %}
 5214   ins_encode %{
 5215     address con = (address)$src$$constant;
 5216     if (con == nullptr) {
 5217       __ movl($mem$$Address, 0);
 5218     } else {
 5219       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
 5220     }
 5221   %}
 5222   ins_pipe(ialu_mem_imm);
 5223 %}
 5224 
 5225 instruct storeImmNKlass(memory mem, immNKlass src)
 5226 %{
 5227   match(Set mem (StoreNKlass mem src));
 5228 
 5229   ins_cost(150); // XXX
 5230   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 5231   ins_encode %{
 5232     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
 5233   %}
 5234   ins_pipe(ialu_mem_imm);
 5235 %}
 5236 
 5237 // Store Integer Immediate
 5238 instruct storeImmI0(memory mem, immI_0 zero)
 5239 %{
 5240   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5241   match(Set mem (StoreI mem zero));
 5242 
 5243   ins_cost(125); // XXX
 5244   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
 5245   ins_encode %{
 5246     __ movl($mem$$Address, r12);
 5247   %}
 5248   ins_pipe(ialu_mem_reg);
 5249 %}
 5250 
 5251 instruct storeImmI(memory mem, immI src)
 5252 %{
 5253   match(Set mem (StoreI mem src));
 5254 
 5255   ins_cost(150);
 5256   format %{ "movl    $mem, $src\t# int" %}
 5257   ins_encode %{
 5258     __ movl($mem$$Address, $src$$constant);
 5259   %}
 5260   ins_pipe(ialu_mem_imm);
 5261 %}
 5262 
 5263 // Store Long Immediate
 5264 instruct storeImmL0(memory mem, immL0 zero)
 5265 %{
 5266   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5267   match(Set mem (StoreL mem zero));
 5268 
 5269   ins_cost(125); // XXX
 5270   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
 5271   ins_encode %{
 5272     __ movq($mem$$Address, r12);
 5273   %}
 5274   ins_pipe(ialu_mem_reg);
 5275 %}
 5276 
 5277 instruct storeImmL(memory mem, immL32 src)
 5278 %{
 5279   match(Set mem (StoreL mem src));
 5280 
 5281   ins_cost(150);
 5282   format %{ "movq    $mem, $src\t# long" %}
 5283   ins_encode %{
 5284     __ movq($mem$$Address, $src$$constant);
 5285   %}
 5286   ins_pipe(ialu_mem_imm);
 5287 %}
 5288 
 5289 // Store Short/Char Immediate
 5290 instruct storeImmC0(memory mem, immI_0 zero)
 5291 %{
 5292   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5293   match(Set mem (StoreC mem zero));
 5294 
 5295   ins_cost(125); // XXX
 5296   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
 5297   ins_encode %{
 5298     __ movw($mem$$Address, r12);
 5299   %}
 5300   ins_pipe(ialu_mem_reg);
 5301 %}
 5302 
 5303 instruct storeImmI16(memory mem, immI16 src)
 5304 %{
 5305   predicate(UseStoreImmI16);
 5306   match(Set mem (StoreC mem src));
 5307 
 5308   ins_cost(150);
 5309   format %{ "movw    $mem, $src\t# short/char" %}
 5310   ins_encode %{
 5311     __ movw($mem$$Address, $src$$constant);
 5312   %}
 5313   ins_pipe(ialu_mem_imm);
 5314 %}
 5315 
 5316 // Store Byte Immediate
 5317 instruct storeImmB0(memory mem, immI_0 zero)
 5318 %{
 5319   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5320   match(Set mem (StoreB mem zero));
 5321 
 5322   ins_cost(125); // XXX
 5323   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
 5324   ins_encode %{
 5325     __ movb($mem$$Address, r12);
 5326   %}
 5327   ins_pipe(ialu_mem_reg);
 5328 %}
 5329 
 5330 instruct storeImmB(memory mem, immI8 src)
 5331 %{
 5332   match(Set mem (StoreB mem src));
 5333 
 5334   ins_cost(150); // XXX
 5335   format %{ "movb    $mem, $src\t# byte" %}
 5336   ins_encode %{
 5337     __ movb($mem$$Address, $src$$constant);
 5338   %}
 5339   ins_pipe(ialu_mem_imm);
 5340 %}
 5341 
 5342 // Store Float
 5343 instruct storeF(memory mem, regF src)
 5344 %{
 5345   match(Set mem (StoreF mem src));
 5346 
 5347   ins_cost(95); // XXX
 5348   format %{ "movss   $mem, $src\t# float" %}
 5349   ins_encode %{
 5350     __ movflt($mem$$Address, $src$$XMMRegister);
 5351   %}
 5352   ins_pipe(pipe_slow); // XXX
 5353 %}
 5354 
 5355 // Store immediate Float value (it is faster than store from XMM register)
 5356 instruct storeF0(memory mem, immF0 zero)
 5357 %{
 5358   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5359   match(Set mem (StoreF mem zero));
 5360 
 5361   ins_cost(25); // XXX
 5362   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
 5363   ins_encode %{
 5364     __ movl($mem$$Address, r12);
 5365   %}
 5366   ins_pipe(ialu_mem_reg);
 5367 %}
 5368 
 5369 instruct storeF_imm(memory mem, immF src)
 5370 %{
 5371   match(Set mem (StoreF mem src));
 5372 
 5373   ins_cost(50);
 5374   format %{ "movl    $mem, $src\t# float" %}
 5375   ins_encode %{
 5376     __ movl($mem$$Address, jint_cast($src$$constant));
 5377   %}
 5378   ins_pipe(ialu_mem_imm);
 5379 %}
 5380 
 5381 // Store Double
 5382 instruct storeD(memory mem, regD src)
 5383 %{
 5384   match(Set mem (StoreD mem src));
 5385 
 5386   ins_cost(95); // XXX
 5387   format %{ "movsd   $mem, $src\t# double" %}
 5388   ins_encode %{
 5389     __ movdbl($mem$$Address, $src$$XMMRegister);
 5390   %}
 5391   ins_pipe(pipe_slow); // XXX
 5392 %}
 5393 
 5394 // Store immediate double 0.0 (it is faster than store from XMM register)
 5395 instruct storeD0_imm(memory mem, immD0 src)
 5396 %{
 5397   predicate(!UseCompressedOops || (CompressedOops::base() != nullptr));
 5398   match(Set mem (StoreD mem src));
 5399 
 5400   ins_cost(50);
 5401   format %{ "movq    $mem, $src\t# double 0." %}
 5402   ins_encode %{
 5403     __ movq($mem$$Address, $src$$constant);
 5404   %}
 5405   ins_pipe(ialu_mem_imm);
 5406 %}
 5407 
 5408 instruct storeD0(memory mem, immD0 zero)
 5409 %{
 5410   predicate(UseCompressedOops && (CompressedOops::base() == nullptr));
 5411   match(Set mem (StoreD mem zero));
 5412 
 5413   ins_cost(25); // XXX
 5414   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
 5415   ins_encode %{
 5416     __ movq($mem$$Address, r12);
 5417   %}
 5418   ins_pipe(ialu_mem_reg);
 5419 %}
 5420 
 5421 instruct storeSSI(stackSlotI dst, rRegI src)
 5422 %{
 5423   match(Set dst src);
 5424 
 5425   ins_cost(100);
 5426   format %{ "movl    $dst, $src\t# int stk" %}
 5427   ins_encode %{
 5428     __ movl($dst$$Address, $src$$Register);
 5429   %}
 5430   ins_pipe( ialu_mem_reg );
 5431 %}
 5432 
 5433 instruct storeSSL(stackSlotL dst, rRegL src)
 5434 %{
 5435   match(Set dst src);
 5436 
 5437   ins_cost(100);
 5438   format %{ "movq    $dst, $src\t# long stk" %}
 5439   ins_encode %{
 5440     __ movq($dst$$Address, $src$$Register);
 5441   %}
 5442   ins_pipe(ialu_mem_reg);
 5443 %}
 5444 
 5445 instruct storeSSP(stackSlotP dst, rRegP src)
 5446 %{
 5447   match(Set dst src);
 5448 
 5449   ins_cost(100);
 5450   format %{ "movq    $dst, $src\t# ptr stk" %}
 5451   ins_encode %{
 5452     __ movq($dst$$Address, $src$$Register);
 5453   %}
 5454   ins_pipe(ialu_mem_reg);
 5455 %}
 5456 
 5457 instruct storeSSF(stackSlotF dst, regF src)
 5458 %{
 5459   match(Set dst src);
 5460 
 5461   ins_cost(95); // XXX
 5462   format %{ "movss   $dst, $src\t# float stk" %}
 5463   ins_encode %{
 5464     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
 5465   %}
 5466   ins_pipe(pipe_slow); // XXX
 5467 %}
 5468 
 5469 instruct storeSSD(stackSlotD dst, regD src)
 5470 %{
 5471   match(Set dst src);
 5472 
 5473   ins_cost(95); // XXX
 5474   format %{ "movsd   $dst, $src\t# double stk" %}
 5475   ins_encode %{
 5476     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
 5477   %}
 5478   ins_pipe(pipe_slow); // XXX
 5479 %}
 5480 
 5481 instruct cacheWB(indirect addr)
 5482 %{
 5483   predicate(VM_Version::supports_data_cache_line_flush());
 5484   match(CacheWB addr);
 5485 
 5486   ins_cost(100);
 5487   format %{"cache wb $addr" %}
 5488   ins_encode %{
 5489     assert($addr->index_position() < 0, "should be");
 5490     assert($addr$$disp == 0, "should be");
 5491     __ cache_wb(Address($addr$$base$$Register, 0));
 5492   %}
 5493   ins_pipe(pipe_slow); // XXX
 5494 %}
 5495 
 5496 instruct cacheWBPreSync()
 5497 %{
 5498   predicate(VM_Version::supports_data_cache_line_flush());
 5499   match(CacheWBPreSync);
 5500 
 5501   ins_cost(100);
 5502   format %{"cache wb presync" %}
 5503   ins_encode %{
 5504     __ cache_wbsync(true);
 5505   %}
 5506   ins_pipe(pipe_slow); // XXX
 5507 %}
 5508 
 5509 instruct cacheWBPostSync()
 5510 %{
 5511   predicate(VM_Version::supports_data_cache_line_flush());
 5512   match(CacheWBPostSync);
 5513 
 5514   ins_cost(100);
 5515   format %{"cache wb postsync" %}
 5516   ins_encode %{
 5517     __ cache_wbsync(false);
 5518   %}
 5519   ins_pipe(pipe_slow); // XXX
 5520 %}
 5521 
 5522 //----------BSWAP Instructions-------------------------------------------------
 5523 instruct bytes_reverse_int(rRegI dst) %{
 5524   match(Set dst (ReverseBytesI dst));
 5525 
 5526   format %{ "bswapl  $dst" %}
 5527   ins_encode %{
 5528     __ bswapl($dst$$Register);
 5529   %}
 5530   ins_pipe( ialu_reg );
 5531 %}
 5532 
 5533 instruct bytes_reverse_long(rRegL dst) %{
 5534   match(Set dst (ReverseBytesL dst));
 5535 
 5536   format %{ "bswapq  $dst" %}
 5537   ins_encode %{
 5538     __ bswapq($dst$$Register);
 5539   %}
 5540   ins_pipe( ialu_reg);
 5541 %}
 5542 
 5543 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
 5544   match(Set dst (ReverseBytesUS dst));
 5545   effect(KILL cr);
 5546 
 5547   format %{ "bswapl  $dst\n\t"
 5548             "shrl    $dst,16\n\t" %}
 5549   ins_encode %{
 5550     __ bswapl($dst$$Register);
 5551     __ shrl($dst$$Register, 16);
 5552   %}
 5553   ins_pipe( ialu_reg );
 5554 %}
 5555 
 5556 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
 5557   match(Set dst (ReverseBytesS dst));
 5558   effect(KILL cr);
 5559 
 5560   format %{ "bswapl  $dst\n\t"
 5561             "sar     $dst,16\n\t" %}
 5562   ins_encode %{
 5563     __ bswapl($dst$$Register);
 5564     __ sarl($dst$$Register, 16);
 5565   %}
 5566   ins_pipe( ialu_reg );
 5567 %}
 5568 
 5569 //---------- Zeros Count Instructions ------------------------------------------
 5570 
 5571 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 5572   predicate(UseCountLeadingZerosInstruction);
 5573   match(Set dst (CountLeadingZerosI src));
 5574   effect(KILL cr);
 5575 
 5576   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
 5577   ins_encode %{
 5578     __ lzcntl($dst$$Register, $src$$Register);
 5579   %}
 5580   ins_pipe(ialu_reg);
 5581 %}
 5582 
 5583 instruct countLeadingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
 5584   predicate(UseCountLeadingZerosInstruction);
 5585   match(Set dst (CountLeadingZerosI (LoadI src)));
 5586   effect(KILL cr);
 5587   ins_cost(175);
 5588   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
 5589   ins_encode %{
 5590     __ lzcntl($dst$$Register, $src$$Address);
 5591   %}
 5592   ins_pipe(ialu_reg_mem);
 5593 %}
 5594 
 5595 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
 5596   predicate(!UseCountLeadingZerosInstruction);
 5597   match(Set dst (CountLeadingZerosI src));
 5598   effect(KILL cr);
 5599 
 5600   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
 5601             "jnz     skip\n\t"
 5602             "movl    $dst, -1\n"
 5603       "skip:\n\t"
 5604             "negl    $dst\n\t"
 5605             "addl    $dst, 31" %}
 5606   ins_encode %{
 5607     Register Rdst = $dst$$Register;
 5608     Register Rsrc = $src$$Register;
 5609     Label skip;
 5610     __ bsrl(Rdst, Rsrc);
 5611     __ jccb(Assembler::notZero, skip);
 5612     __ movl(Rdst, -1);
 5613     __ bind(skip);
 5614     __ negl(Rdst);
 5615     __ addl(Rdst, BitsPerInt - 1);
 5616   %}
 5617   ins_pipe(ialu_reg);
 5618 %}
 5619 
 5620 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 5621   predicate(UseCountLeadingZerosInstruction);
 5622   match(Set dst (CountLeadingZerosL src));
 5623   effect(KILL cr);
 5624 
 5625   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
 5626   ins_encode %{
 5627     __ lzcntq($dst$$Register, $src$$Register);
 5628   %}
 5629   ins_pipe(ialu_reg);
 5630 %}
 5631 
 5632 instruct countLeadingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
 5633   predicate(UseCountLeadingZerosInstruction);
 5634   match(Set dst (CountLeadingZerosL (LoadL src)));
 5635   effect(KILL cr);
 5636   ins_cost(175);
 5637   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
 5638   ins_encode %{
 5639     __ lzcntq($dst$$Register, $src$$Address);
 5640   %}
 5641   ins_pipe(ialu_reg_mem);
 5642 %}
 5643 
 5644 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
 5645   predicate(!UseCountLeadingZerosInstruction);
 5646   match(Set dst (CountLeadingZerosL src));
 5647   effect(KILL cr);
 5648 
 5649   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
 5650             "jnz     skip\n\t"
 5651             "movl    $dst, -1\n"
 5652       "skip:\n\t"
 5653             "negl    $dst\n\t"
 5654             "addl    $dst, 63" %}
 5655   ins_encode %{
 5656     Register Rdst = $dst$$Register;
 5657     Register Rsrc = $src$$Register;
 5658     Label skip;
 5659     __ bsrq(Rdst, Rsrc);
 5660     __ jccb(Assembler::notZero, skip);
 5661     __ movl(Rdst, -1);
 5662     __ bind(skip);
 5663     __ negl(Rdst);
 5664     __ addl(Rdst, BitsPerLong - 1);
 5665   %}
 5666   ins_pipe(ialu_reg);
 5667 %}
 5668 
 5669 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 5670   predicate(UseCountTrailingZerosInstruction);
 5671   match(Set dst (CountTrailingZerosI src));
 5672   effect(KILL cr);
 5673 
 5674   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
 5675   ins_encode %{
 5676     __ tzcntl($dst$$Register, $src$$Register);
 5677   %}
 5678   ins_pipe(ialu_reg);
 5679 %}
 5680 
 5681 instruct countTrailingZerosI_mem(rRegI dst, memory src, rFlagsReg cr) %{
 5682   predicate(UseCountTrailingZerosInstruction);
 5683   match(Set dst (CountTrailingZerosI (LoadI src)));
 5684   effect(KILL cr);
 5685   ins_cost(175);
 5686   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
 5687   ins_encode %{
 5688     __ tzcntl($dst$$Register, $src$$Address);
 5689   %}
 5690   ins_pipe(ialu_reg_mem);
 5691 %}
 5692 
 5693 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
 5694   predicate(!UseCountTrailingZerosInstruction);
 5695   match(Set dst (CountTrailingZerosI src));
 5696   effect(KILL cr);
 5697 
 5698   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
 5699             "jnz     done\n\t"
 5700             "movl    $dst, 32\n"
 5701       "done:" %}
 5702   ins_encode %{
 5703     Register Rdst = $dst$$Register;
 5704     Label done;
 5705     __ bsfl(Rdst, $src$$Register);
 5706     __ jccb(Assembler::notZero, done);
 5707     __ movl(Rdst, BitsPerInt);
 5708     __ bind(done);
 5709   %}
 5710   ins_pipe(ialu_reg);
 5711 %}
 5712 
 5713 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 5714   predicate(UseCountTrailingZerosInstruction);
 5715   match(Set dst (CountTrailingZerosL src));
 5716   effect(KILL cr);
 5717 
 5718   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
 5719   ins_encode %{
 5720     __ tzcntq($dst$$Register, $src$$Register);
 5721   %}
 5722   ins_pipe(ialu_reg);
 5723 %}
 5724 
 5725 instruct countTrailingZerosL_mem(rRegI dst, memory src, rFlagsReg cr) %{
 5726   predicate(UseCountTrailingZerosInstruction);
 5727   match(Set dst (CountTrailingZerosL (LoadL src)));
 5728   effect(KILL cr);
 5729   ins_cost(175);
 5730   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
 5731   ins_encode %{
 5732     __ tzcntq($dst$$Register, $src$$Address);
 5733   %}
 5734   ins_pipe(ialu_reg_mem);
 5735 %}
 5736 
 5737 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
 5738   predicate(!UseCountTrailingZerosInstruction);
 5739   match(Set dst (CountTrailingZerosL src));
 5740   effect(KILL cr);
 5741 
 5742   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
 5743             "jnz     done\n\t"
 5744             "movl    $dst, 64\n"
 5745       "done:" %}
 5746   ins_encode %{
 5747     Register Rdst = $dst$$Register;
 5748     Label done;
 5749     __ bsfq(Rdst, $src$$Register);
 5750     __ jccb(Assembler::notZero, done);
 5751     __ movl(Rdst, BitsPerLong);
 5752     __ bind(done);
 5753   %}
 5754   ins_pipe(ialu_reg);
 5755 %}
 5756 
 5757 //--------------- Reverse Operation Instructions ----------------
 5758 instruct bytes_reversebit_int(rRegI dst, rRegI src, rRegI rtmp, rFlagsReg cr) %{
 5759   predicate(!VM_Version::supports_gfni());
 5760   match(Set dst (ReverseI src));
 5761   effect(TEMP dst, TEMP rtmp, KILL cr);
 5762   format %{ "reverse_int $dst $src\t! using $rtmp as TEMP" %}
 5763   ins_encode %{
 5764     __ reverseI($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp$$Register);
 5765   %}
 5766   ins_pipe( ialu_reg );
 5767 %}
 5768 
 5769 instruct bytes_reversebit_int_gfni(rRegI dst, rRegI src, vlRegF xtmp1, vlRegF xtmp2, rRegL rtmp, rFlagsReg cr) %{
 5770   predicate(VM_Version::supports_gfni());
 5771   match(Set dst (ReverseI src));
 5772   effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
 5773   format %{ "reverse_int $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
 5774   ins_encode %{
 5775     __ reverseI($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register);
 5776   %}
 5777   ins_pipe( ialu_reg );
 5778 %}
 5779 
 5780 instruct bytes_reversebit_long(rRegL dst, rRegL src, rRegL rtmp1, rRegL rtmp2, rFlagsReg cr) %{
 5781   predicate(!VM_Version::supports_gfni());
 5782   match(Set dst (ReverseL src));
 5783   effect(TEMP dst, TEMP rtmp1, TEMP rtmp2, KILL cr);
 5784   format %{ "reverse_long $dst $src\t! using $rtmp1 and $rtmp2 as TEMP" %}
 5785   ins_encode %{
 5786     __ reverseL($dst$$Register, $src$$Register, xnoreg, xnoreg, $rtmp1$$Register, $rtmp2$$Register);
 5787   %}
 5788   ins_pipe( ialu_reg );
 5789 %}
 5790 
 5791 instruct bytes_reversebit_long_gfni(rRegL dst, rRegL src, vlRegD xtmp1, vlRegD xtmp2, rRegL rtmp, rFlagsReg cr) %{
 5792   predicate(VM_Version::supports_gfni());
 5793   match(Set dst (ReverseL src));
 5794   effect(TEMP dst, TEMP xtmp1, TEMP xtmp2, TEMP rtmp, KILL cr);
 5795   format %{ "reverse_long $dst $src\t! using $rtmp, $xtmp1 and $xtmp2 as TEMP" %}
 5796   ins_encode %{
 5797     __ reverseL($dst$$Register, $src$$Register, $xtmp1$$XMMRegister, $xtmp2$$XMMRegister, $rtmp$$Register, noreg);
 5798   %}
 5799   ins_pipe( ialu_reg );
 5800 %}
 5801 
 5802 //---------- Population Count Instructions -------------------------------------
 5803 
 5804 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
 5805   predicate(UsePopCountInstruction);
 5806   match(Set dst (PopCountI src));
 5807   effect(KILL cr);
 5808 
 5809   format %{ "popcnt  $dst, $src" %}
 5810   ins_encode %{
 5811     __ popcntl($dst$$Register, $src$$Register);
 5812   %}
 5813   ins_pipe(ialu_reg);
 5814 %}
 5815 
 5816 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 5817   predicate(UsePopCountInstruction);
 5818   match(Set dst (PopCountI (LoadI mem)));
 5819   effect(KILL cr);
 5820 
 5821   format %{ "popcnt  $dst, $mem" %}
 5822   ins_encode %{
 5823     __ popcntl($dst$$Register, $mem$$Address);
 5824   %}
 5825   ins_pipe(ialu_reg);
 5826 %}
 5827 
 5828 // Note: Long.bitCount(long) returns an int.
 5829 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
 5830   predicate(UsePopCountInstruction);
 5831   match(Set dst (PopCountL src));
 5832   effect(KILL cr);
 5833 
 5834   format %{ "popcnt  $dst, $src" %}
 5835   ins_encode %{
 5836     __ popcntq($dst$$Register, $src$$Register);
 5837   %}
 5838   ins_pipe(ialu_reg);
 5839 %}
 5840 
 5841 // Note: Long.bitCount(long) returns an int.
 5842 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 5843   predicate(UsePopCountInstruction);
 5844   match(Set dst (PopCountL (LoadL mem)));
 5845   effect(KILL cr);
 5846 
 5847   format %{ "popcnt  $dst, $mem" %}
 5848   ins_encode %{
 5849     __ popcntq($dst$$Register, $mem$$Address);
 5850   %}
 5851   ins_pipe(ialu_reg);
 5852 %}
 5853 
 5854 
 5855 //----------MemBar Instructions-----------------------------------------------
 5856 // Memory barrier flavors
 5857 
 5858 instruct membar_acquire()
 5859 %{
 5860   match(MemBarAcquire);
 5861   match(LoadFence);
 5862   ins_cost(0);
 5863 
 5864   size(0);
 5865   format %{ "MEMBAR-acquire ! (empty encoding)" %}
 5866   ins_encode();
 5867   ins_pipe(empty);
 5868 %}
 5869 
 5870 instruct membar_acquire_lock()
 5871 %{
 5872   match(MemBarAcquireLock);
 5873   ins_cost(0);
 5874 
 5875   size(0);
 5876   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
 5877   ins_encode();
 5878   ins_pipe(empty);
 5879 %}
 5880 
 5881 instruct membar_release()
 5882 %{
 5883   match(MemBarRelease);
 5884   match(StoreFence);
 5885   ins_cost(0);
 5886 
 5887   size(0);
 5888   format %{ "MEMBAR-release ! (empty encoding)" %}
 5889   ins_encode();
 5890   ins_pipe(empty);
 5891 %}
 5892 
 5893 instruct membar_release_lock()
 5894 %{
 5895   match(MemBarReleaseLock);
 5896   ins_cost(0);
 5897 
 5898   size(0);
 5899   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
 5900   ins_encode();
 5901   ins_pipe(empty);
 5902 %}
 5903 
 5904 instruct membar_volatile(rFlagsReg cr) %{
 5905   match(MemBarVolatile);
 5906   effect(KILL cr);
 5907   ins_cost(400);
 5908 
 5909   format %{
 5910     $$template
 5911     $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
 5912   %}
 5913   ins_encode %{
 5914     __ membar(Assembler::StoreLoad);
 5915   %}
 5916   ins_pipe(pipe_slow);
 5917 %}
 5918 
 5919 instruct unnecessary_membar_volatile()
 5920 %{
 5921   match(MemBarVolatile);
 5922   predicate(Matcher::post_store_load_barrier(n));
 5923   ins_cost(0);
 5924 
 5925   size(0);
 5926   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
 5927   ins_encode();
 5928   ins_pipe(empty);
 5929 %}
 5930 
 5931 instruct membar_storestore() %{
 5932   match(MemBarStoreStore);
 5933   match(StoreStoreFence);
 5934   ins_cost(0);
 5935 
 5936   size(0);
 5937   format %{ "MEMBAR-storestore (empty encoding)" %}
 5938   ins_encode( );
 5939   ins_pipe(empty);
 5940 %}
 5941 
 5942 //----------Move Instructions--------------------------------------------------
 5943 
 5944 instruct castX2P(rRegP dst, rRegL src)
 5945 %{
 5946   match(Set dst (CastX2P src));
 5947 
 5948   format %{ "movq    $dst, $src\t# long->ptr" %}
 5949   ins_encode %{
 5950     if ($dst$$reg != $src$$reg) {
 5951       __ movptr($dst$$Register, $src$$Register);
 5952     }
 5953   %}
 5954   ins_pipe(ialu_reg_reg); // XXX
 5955 %}
 5956 
 5957 instruct castP2X(rRegL dst, rRegP src)
 5958 %{
 5959   match(Set dst (CastP2X src));
 5960 
 5961   format %{ "movq    $dst, $src\t# ptr -> long" %}
 5962   ins_encode %{
 5963     if ($dst$$reg != $src$$reg) {
 5964       __ movptr($dst$$Register, $src$$Register);
 5965     }
 5966   %}
 5967   ins_pipe(ialu_reg_reg); // XXX
 5968 %}
 5969 
 5970 // Convert oop into int for vectors alignment masking
 5971 instruct convP2I(rRegI dst, rRegP src)
 5972 %{
 5973   match(Set dst (ConvL2I (CastP2X src)));
 5974 
 5975   format %{ "movl    $dst, $src\t# ptr -> int" %}
 5976   ins_encode %{
 5977     __ movl($dst$$Register, $src$$Register);
 5978   %}
 5979   ins_pipe(ialu_reg_reg); // XXX
 5980 %}
 5981 
 5982 // Convert compressed oop into int for vectors alignment masking
 5983 // in case of 32bit oops (heap < 4Gb).
 5984 instruct convN2I(rRegI dst, rRegN src)
 5985 %{
 5986   predicate(CompressedOops::shift() == 0);
 5987   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 5988 
 5989   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
 5990   ins_encode %{
 5991     __ movl($dst$$Register, $src$$Register);
 5992   %}
 5993   ins_pipe(ialu_reg_reg); // XXX
 5994 %}
 5995 
 5996 // Convert oop pointer into compressed form
 5997 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
 5998   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
 5999   match(Set dst (EncodeP src));
 6000   effect(KILL cr);
 6001   format %{ "encode_heap_oop $dst,$src" %}
 6002   ins_encode %{
 6003     Register s = $src$$Register;
 6004     Register d = $dst$$Register;
 6005     if (s != d) {
 6006       __ movq(d, s);
 6007     }
 6008     __ encode_heap_oop(d);
 6009   %}
 6010   ins_pipe(ialu_reg_long);
 6011 %}
 6012 
 6013 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6014   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
 6015   match(Set dst (EncodeP src));
 6016   effect(KILL cr);
 6017   format %{ "encode_heap_oop_not_null $dst,$src" %}
 6018   ins_encode %{
 6019     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
 6020   %}
 6021   ins_pipe(ialu_reg_long);
 6022 %}
 6023 
 6024 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
 6025   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 6026             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 6027   match(Set dst (DecodeN src));
 6028   effect(KILL cr);
 6029   format %{ "decode_heap_oop $dst,$src" %}
 6030   ins_encode %{
 6031     Register s = $src$$Register;
 6032     Register d = $dst$$Register;
 6033     if (s != d) {
 6034       __ movq(d, s);
 6035     }
 6036     __ decode_heap_oop(d);
 6037   %}
 6038   ins_pipe(ialu_reg_long);
 6039 %}
 6040 
 6041 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6042   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 6043             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 6044   match(Set dst (DecodeN src));
 6045   effect(KILL cr);
 6046   format %{ "decode_heap_oop_not_null $dst,$src" %}
 6047   ins_encode %{
 6048     Register s = $src$$Register;
 6049     Register d = $dst$$Register;
 6050     if (s != d) {
 6051       __ decode_heap_oop_not_null(d, s);
 6052     } else {
 6053       __ decode_heap_oop_not_null(d);
 6054     }
 6055   %}
 6056   ins_pipe(ialu_reg_long);
 6057 %}
 6058 
 6059 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6060   match(Set dst (EncodePKlass src));
 6061   effect(TEMP dst, KILL cr);
 6062   format %{ "encode_and_move_klass_not_null $dst,$src" %}
 6063   ins_encode %{
 6064     __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6065   %}
 6066   ins_pipe(ialu_reg_long);
 6067 %}
 6068 
 6069 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6070   match(Set dst (DecodeNKlass src));
 6071   effect(TEMP dst, KILL cr);
 6072   format %{ "decode_and_move_klass_not_null $dst,$src" %}
 6073   ins_encode %{
 6074     __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6075   %}
 6076   ins_pipe(ialu_reg_long);
 6077 %}
 6078 
 6079 //----------Conditional Move---------------------------------------------------
 6080 // Jump
 6081 // dummy instruction for generating temp registers
 6082 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
 6083   match(Jump (LShiftL switch_val shift));
 6084   ins_cost(350);
 6085   predicate(false);
 6086   effect(TEMP dest);
 6087 
 6088   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6089             "jmp     [$dest + $switch_val << $shift]\n\t" %}
 6090   ins_encode %{
 6091     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6092     // to do that and the compiler is using that register as one it can allocate.
 6093     // So we build it all by hand.
 6094     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
 6095     // ArrayAddress dispatch(table, index);
 6096     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
 6097     __ lea($dest$$Register, $constantaddress);
 6098     __ jmp(dispatch);
 6099   %}
 6100   ins_pipe(pipe_jmp);
 6101 %}
 6102 
 6103 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
 6104   match(Jump (AddL (LShiftL switch_val shift) offset));
 6105   ins_cost(350);
 6106   effect(TEMP dest);
 6107 
 6108   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6109             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
 6110   ins_encode %{
 6111     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6112     // to do that and the compiler is using that register as one it can allocate.
 6113     // So we build it all by hand.
 6114     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6115     // ArrayAddress dispatch(table, index);
 6116     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6117     __ lea($dest$$Register, $constantaddress);
 6118     __ jmp(dispatch);
 6119   %}
 6120   ins_pipe(pipe_jmp);
 6121 %}
 6122 
 6123 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
 6124   match(Jump switch_val);
 6125   ins_cost(350);
 6126   effect(TEMP dest);
 6127 
 6128   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6129             "jmp     [$dest + $switch_val]\n\t" %}
 6130   ins_encode %{
 6131     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6132     // to do that and the compiler is using that register as one it can allocate.
 6133     // So we build it all by hand.
 6134     // Address index(noreg, switch_reg, Address::times_1);
 6135     // ArrayAddress dispatch(table, index);
 6136     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
 6137     __ lea($dest$$Register, $constantaddress);
 6138     __ jmp(dispatch);
 6139   %}
 6140   ins_pipe(pipe_jmp);
 6141 %}
 6142 
 6143 // Conditional move
 6144 instruct cmovI_imm_01(rRegI dst, immI_1 src, rFlagsReg cr, cmpOp cop)
 6145 %{
 6146   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
 6147   match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
 6148 
 6149   ins_cost(100); // XXX
 6150   format %{ "setbn$cop $dst\t# signed, int" %}
 6151   ins_encode %{
 6152     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6153     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6154   %}
 6155   ins_pipe(ialu_reg);
 6156 %}
 6157 
 6158 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
 6159 %{
 6160   predicate(!UseAPX);
 6161   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6162 
 6163   ins_cost(200); // XXX
 6164   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 6165   ins_encode %{
 6166     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6167   %}
 6168   ins_pipe(pipe_cmov_reg);
 6169 %}
 6170 
 6171 instruct cmovI_reg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr, cmpOp cop)
 6172 %{
 6173   predicate(UseAPX);
 6174   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
 6175 
 6176   ins_cost(200);
 6177   format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
 6178   ins_encode %{
 6179     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6180   %}
 6181   ins_pipe(pipe_cmov_reg);
 6182 %}
 6183 
 6184 instruct cmovI_imm_01U(rRegI dst, immI_1 src, rFlagsRegU cr, cmpOpU cop)
 6185 %{
 6186   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
 6187   match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
 6188 
 6189   ins_cost(100); // XXX
 6190   format %{ "setbn$cop $dst\t# unsigned, int" %}
 6191   ins_encode %{
 6192     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6193     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6194   %}
 6195   ins_pipe(ialu_reg);
 6196 %}
 6197 
 6198 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
 6199   predicate(!UseAPX);
 6200   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6201 
 6202   ins_cost(200); // XXX
 6203   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 6204   ins_encode %{
 6205     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6206   %}
 6207   ins_pipe(pipe_cmov_reg);
 6208 %}
 6209 
 6210 instruct cmovI_regU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, rRegI src2) %{
 6211   predicate(UseAPX);
 6212   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
 6213 
 6214   ins_cost(200);
 6215   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
 6216   ins_encode %{
 6217     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6218   %}
 6219   ins_pipe(pipe_cmov_reg);
 6220 %}
 6221 
 6222 instruct cmovI_imm_01UCF(rRegI dst, immI_1 src, rFlagsRegUCF cr, cmpOpUCF cop)
 6223 %{
 6224   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_int() == 0);
 6225   match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
 6226 
 6227   ins_cost(100); // XXX
 6228   format %{ "setbn$cop $dst\t# unsigned, int" %}
 6229   ins_encode %{
 6230     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6231     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6232   %}
 6233   ins_pipe(ialu_reg);
 6234 %}
 6235 
 6236 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
 6237   predicate(!UseAPX);
 6238   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6239   ins_cost(200);
 6240   expand %{
 6241     cmovI_regU(cop, cr, dst, src);
 6242   %}
 6243 %}
 6244 
 6245 instruct cmovI_regUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, rRegI src2) %{
 6246   predicate(UseAPX);
 6247   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
 6248   ins_cost(200);
 6249   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
 6250   ins_encode %{
 6251     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6252   %}
 6253   ins_pipe(pipe_cmov_reg);
 6254 %}
 6255 
 6256 instruct cmovI_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
 6257   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6258   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 6259 
 6260   ins_cost(200); // XXX
 6261   format %{ "cmovpl  $dst, $src\n\t"
 6262             "cmovnel $dst, $src" %}
 6263   ins_encode %{
 6264     __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
 6265     __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
 6266   %}
 6267   ins_pipe(pipe_cmov_reg);
 6268 %}
 6269 
 6270 instruct cmovI_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
 6271   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6272   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
 6273 
 6274   ins_cost(200);
 6275   format %{ "ecmovpl  $dst, $src1, $src2\n\t"
 6276             "ecmovnel $dst, $src1, $src2" %}
 6277   ins_encode %{
 6278     __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6279     __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6280   %}
 6281   ins_pipe(pipe_cmov_reg);
 6282 %}
 6283 
 6284 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
 6285 // inputs of the CMove
 6286 instruct cmovI_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
 6287   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6288   match(Set dst (CMoveI (Binary cop cr) (Binary src dst)));
 6289 
 6290   ins_cost(200); // XXX
 6291   format %{ "cmovpl  $dst, $src\n\t"
 6292             "cmovnel $dst, $src" %}
 6293   ins_encode %{
 6294     __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
 6295     __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
 6296   %}
 6297   ins_pipe(pipe_cmov_reg);
 6298 %}
 6299 
 6300 // We need this special handling for only eq / neq comparison since NaN == NaN is false,
 6301 // and parity flag bit is set if any of the operand is a NaN.
 6302 instruct cmovI_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegI dst, rRegI src1, rRegI src2) %{
 6303   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6304   match(Set dst (CMoveI (Binary cop cr) (Binary src1 src2)));
 6305 
 6306   ins_cost(200);
 6307   format %{ "ecmovpl  $dst, $src1, $src2\n\t"
 6308             "ecmovnel $dst, $src1, $src2" %}
 6309   ins_encode %{
 6310     __ ecmovl(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6311     __ ecmovl(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6312   %}
 6313   ins_pipe(pipe_cmov_reg);
 6314 %}
 6315 
 6316 // Conditional move
 6317 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
 6318   predicate(!UseAPX);
 6319   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 6320 
 6321   ins_cost(250); // XXX
 6322   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 6323   ins_encode %{
 6324     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 6325   %}
 6326   ins_pipe(pipe_cmov_mem);
 6327 %}
 6328 
 6329 // Conditional move
 6330 instruct cmovI_rReg_rReg_mem_ndd(rRegI dst, cmpOp cop, rFlagsReg cr, rRegI src1, memory src2)
 6331 %{
 6332   predicate(UseAPX);
 6333   match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
 6334 
 6335   ins_cost(250);
 6336   format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, int ndd" %}
 6337   ins_encode %{
 6338     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6339   %}
 6340   ins_pipe(pipe_cmov_mem);
 6341 %}
 6342 
 6343 // Conditional move
 6344 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
 6345 %{
 6346   predicate(!UseAPX);
 6347   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 6348 
 6349   ins_cost(250); // XXX
 6350   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 6351   ins_encode %{
 6352     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 6353   %}
 6354   ins_pipe(pipe_cmov_mem);
 6355 %}
 6356 
 6357 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
 6358   predicate(!UseAPX);
 6359   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 6360   ins_cost(250);
 6361   expand %{
 6362     cmovI_memU(cop, cr, dst, src);
 6363   %}
 6364 %}
 6365 
 6366 instruct cmovI_rReg_rReg_memU_ndd(rRegI dst, cmpOpU cop, rFlagsRegU cr, rRegI src1, memory src2)
 6367 %{
 6368   predicate(UseAPX);
 6369   match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
 6370 
 6371   ins_cost(250);
 6372   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
 6373   ins_encode %{
 6374     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6375   %}
 6376   ins_pipe(pipe_cmov_mem);
 6377 %}
 6378 
 6379 instruct cmovI_rReg_rReg_memUCF_ndd(rRegI dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegI src1, memory src2) 
 6380 %{
 6381   predicate(UseAPX);
 6382   match(Set dst (CMoveI (Binary cop cr) (Binary src1 (LoadI src2))));
 6383   ins_cost(250);
 6384   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, int ndd" %}
 6385   ins_encode %{
 6386     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6387   %}
 6388   ins_pipe(pipe_cmov_mem);
 6389 %}
 6390 
 6391 // Conditional move
 6392 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
 6393 %{
 6394   predicate(!UseAPX);
 6395   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 6396 
 6397   ins_cost(200); // XXX
 6398   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
 6399   ins_encode %{
 6400     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6401   %}
 6402   ins_pipe(pipe_cmov_reg);
 6403 %}
 6404 
 6405 // Conditional move ndd
 6406 instruct cmovN_reg_ndd(rRegN dst, rRegN src1, rRegN src2, rFlagsReg cr, cmpOp cop)
 6407 %{
 6408   predicate(UseAPX);
 6409   match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
 6410 
 6411   ins_cost(200);
 6412   format %{ "ecmovl$cop $dst, $src1, $src2\t# signed, compressed ptr ndd" %}
 6413   ins_encode %{
 6414     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6415   %}
 6416   ins_pipe(pipe_cmov_reg);
 6417 %}
 6418 
 6419 // Conditional move
 6420 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
 6421 %{
 6422   predicate(!UseAPX);
 6423   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 6424 
 6425   ins_cost(200); // XXX
 6426   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
 6427   ins_encode %{
 6428     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6429   %}
 6430   ins_pipe(pipe_cmov_reg);
 6431 %}
 6432 
 6433 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
 6434   predicate(!UseAPX);
 6435   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 6436   ins_cost(200);
 6437   expand %{
 6438     cmovN_regU(cop, cr, dst, src);
 6439   %}
 6440 %}
 6441 
 6442 // Conditional move ndd
 6443 instruct cmovN_regU_ndd(rRegN dst, cmpOpU cop, rFlagsRegU cr, rRegN src1, rRegN src2)
 6444 %{
 6445   predicate(UseAPX);
 6446   match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
 6447 
 6448   ins_cost(200);
 6449   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
 6450   ins_encode %{
 6451     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6452   %}
 6453   ins_pipe(pipe_cmov_reg);
 6454 %}
 6455 
 6456 instruct cmovN_regUCF_ndd(rRegN dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegN src1, rRegN src2) %{
 6457   predicate(UseAPX);
 6458   match(Set dst (CMoveN (Binary cop cr) (Binary src1 src2)));
 6459   ins_cost(200);
 6460   format %{ "ecmovl$cop $dst, $src1, $src2\t# unsigned, compressed ptr ndd" %}
 6461   ins_encode %{
 6462     __ ecmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6463   %}
 6464   ins_pipe(pipe_cmov_reg);
 6465 %}
 6466 
 6467 instruct cmovN_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
 6468   predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6469   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 6470 
 6471   ins_cost(200); // XXX
 6472   format %{ "cmovpl  $dst, $src\n\t"
 6473             "cmovnel $dst, $src" %}
 6474   ins_encode %{
 6475     __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
 6476     __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
 6477   %}
 6478   ins_pipe(pipe_cmov_reg);
 6479 %}
 6480 
 6481 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
 6482 // inputs of the CMove
 6483 instruct cmovN_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
 6484   predicate(n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6485   match(Set dst (CMoveN (Binary cop cr) (Binary src dst)));
 6486 
 6487   ins_cost(200); // XXX
 6488   format %{ "cmovpl  $dst, $src\n\t"
 6489             "cmovnel $dst, $src" %}
 6490   ins_encode %{
 6491     __ cmovl(Assembler::parity, $dst$$Register, $src$$Register);
 6492     __ cmovl(Assembler::notEqual, $dst$$Register, $src$$Register);
 6493   %}
 6494   ins_pipe(pipe_cmov_reg);
 6495 %}
 6496 
 6497 // Conditional move
 6498 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
 6499 %{
 6500   predicate(!UseAPX);
 6501   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 6502 
 6503   ins_cost(200); // XXX
 6504   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
 6505   ins_encode %{
 6506     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6507   %}
 6508   ins_pipe(pipe_cmov_reg);  // XXX
 6509 %}
 6510 
 6511 // Conditional move ndd
 6512 instruct cmovP_reg_ndd(rRegP dst, rRegP src1, rRegP src2, rFlagsReg cr, cmpOp cop)
 6513 %{
 6514   predicate(UseAPX);
 6515   match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
 6516 
 6517   ins_cost(200);
 6518   format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, ptr ndd" %}
 6519   ins_encode %{
 6520     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6521   %}
 6522   ins_pipe(pipe_cmov_reg);
 6523 %}
 6524 
 6525 // Conditional move
 6526 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
 6527 %{
 6528   predicate(!UseAPX);
 6529   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 6530 
 6531   ins_cost(200); // XXX
 6532   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
 6533   ins_encode %{
 6534     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6535   %}
 6536   ins_pipe(pipe_cmov_reg); // XXX
 6537 %}
 6538 
 6539 // Conditional move ndd
 6540 instruct cmovP_regU_ndd(rRegP dst, cmpOpU cop, rFlagsRegU cr, rRegP src1, rRegP src2)
 6541 %{
 6542   predicate(UseAPX);
 6543   match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
 6544 
 6545   ins_cost(200);
 6546   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
 6547   ins_encode %{
 6548     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6549   %}
 6550   ins_pipe(pipe_cmov_reg);
 6551 %}
 6552 
 6553 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
 6554   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 6555   ins_cost(200);
 6556   expand %{
 6557     cmovP_regU(cop, cr, dst, src);
 6558   %}
 6559 %}
 6560 
 6561 instruct cmovP_regUCF_ndd(rRegP dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegP src1, rRegP src2) %{
 6562   match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
 6563   ins_cost(200);
 6564   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, ptr ndd" %}
 6565   ins_encode %{
 6566     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6567   %}
 6568   ins_pipe(pipe_cmov_reg);
 6569 %}
 6570 
 6571 instruct cmovP_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
 6572   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6573   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 6574 
 6575   ins_cost(200); // XXX
 6576   format %{ "cmovpq  $dst, $src\n\t"
 6577             "cmovneq $dst, $src" %}
 6578   ins_encode %{
 6579     __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
 6580     __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
 6581   %}
 6582   ins_pipe(pipe_cmov_reg);
 6583 %}
 6584 
 6585 instruct cmovP_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
 6586   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6587   match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
 6588 
 6589   ins_cost(200);
 6590   format %{ "ecmovpq  $dst, $src1, $src2\n\t"
 6591             "ecmovneq $dst, $src1, $src2" %}
 6592   ins_encode %{
 6593     __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6594     __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6595   %}
 6596   ins_pipe(pipe_cmov_reg);
 6597 %}
 6598 
 6599 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
 6600 // inputs of the CMove
 6601 instruct cmovP_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
 6602   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6603   match(Set dst (CMoveP (Binary cop cr) (Binary src dst)));
 6604 
 6605   ins_cost(200); // XXX
 6606   format %{ "cmovpq  $dst, $src\n\t"
 6607             "cmovneq $dst, $src" %}
 6608   ins_encode %{
 6609     __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
 6610     __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
 6611   %}
 6612   ins_pipe(pipe_cmov_reg);
 6613 %}
 6614 
 6615 instruct cmovP_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegP dst, rRegP src1, rRegP src2) %{
 6616   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6617   match(Set dst (CMoveP (Binary cop cr) (Binary src1 src2)));
 6618 
 6619   ins_cost(200);
 6620   format %{ "ecmovpq  $dst, $src1, $src2\n\t"
 6621             "ecmovneq $dst, $src1, $src2" %}
 6622   ins_encode %{
 6623     __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6624     __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6625   %}
 6626   ins_pipe(pipe_cmov_reg);
 6627 %}
 6628 
 6629 instruct cmovL_imm_01(rRegL dst, immL1 src, rFlagsReg cr, cmpOp cop)
 6630 %{
 6631   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
 6632   match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
 6633 
 6634   ins_cost(100); // XXX
 6635   format %{ "setbn$cop $dst\t# signed, long" %}
 6636   ins_encode %{
 6637     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6638     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6639   %}
 6640   ins_pipe(ialu_reg);
 6641 %}
 6642 
 6643 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
 6644 %{
 6645   predicate(!UseAPX);
 6646   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 6647 
 6648   ins_cost(200); // XXX
 6649   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 6650   ins_encode %{
 6651     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6652   %}
 6653   ins_pipe(pipe_cmov_reg);  // XXX
 6654 %}
 6655 
 6656 instruct cmovL_reg_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, rRegL src2)
 6657 %{
 6658   predicate(UseAPX);
 6659   match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
 6660 
 6661   ins_cost(200);
 6662   format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
 6663   ins_encode %{
 6664     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6665   %}
 6666   ins_pipe(pipe_cmov_reg);
 6667 %}
 6668 
 6669 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
 6670 %{
 6671   predicate(!UseAPX);
 6672   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 6673 
 6674   ins_cost(200); // XXX
 6675   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 6676   ins_encode %{
 6677     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 6678   %}
 6679   ins_pipe(pipe_cmov_mem);  // XXX
 6680 %}
 6681 
 6682 instruct cmovL_rReg_rReg_mem_ndd(rRegL dst, cmpOp cop, rFlagsReg cr, rRegL src1, memory src2)
 6683 %{
 6684   predicate(UseAPX);
 6685   match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
 6686 
 6687   ins_cost(200);
 6688   format %{ "ecmovq$cop $dst, $src1, $src2\t# signed, long ndd" %}
 6689   ins_encode %{
 6690     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6691   %}
 6692   ins_pipe(pipe_cmov_mem);
 6693 %}
 6694 
 6695 instruct cmovL_imm_01U(rRegL dst, immL1 src, rFlagsRegU cr, cmpOpU cop)
 6696 %{
 6697   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
 6698   match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
 6699 
 6700   ins_cost(100); // XXX
 6701   format %{ "setbn$cop $dst\t# unsigned, long" %}
 6702   ins_encode %{
 6703     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6704     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6705   %}
 6706   ins_pipe(ialu_reg);
 6707 %}
 6708 
 6709 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
 6710 %{
 6711   predicate(!UseAPX);
 6712   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 6713 
 6714   ins_cost(200); // XXX
 6715   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 6716   ins_encode %{
 6717     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 6718   %}
 6719   ins_pipe(pipe_cmov_reg); // XXX
 6720 %}
 6721 
 6722 instruct cmovL_regU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, rRegL src2)
 6723 %{
 6724   predicate(UseAPX);
 6725   match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
 6726 
 6727   ins_cost(200);
 6728   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
 6729   ins_encode %{
 6730     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6731   %}
 6732   ins_pipe(pipe_cmov_reg);
 6733 %}
 6734 
 6735 instruct cmovL_imm_01UCF(rRegL dst, immL1 src, rFlagsRegUCF cr, cmpOpUCF cop)
 6736 %{
 6737   predicate(n->in(2)->in(2)->is_Con() && n->in(2)->in(2)->get_long() == 0);
 6738   match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
 6739 
 6740   ins_cost(100); // XXX
 6741   format %{ "setbn$cop $dst\t# unsigned, long" %}
 6742   ins_encode %{
 6743     Assembler::Condition cond = (Assembler::Condition)($cop$$cmpcode);
 6744     __ setb(MacroAssembler::negate_condition(cond), $dst$$Register);
 6745   %}
 6746   ins_pipe(ialu_reg);
 6747 %}
 6748 
 6749 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
 6750   predicate(!UseAPX);
 6751   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 6752   ins_cost(200);
 6753   expand %{
 6754     cmovL_regU(cop, cr, dst, src);
 6755   %}
 6756 %}
 6757 
 6758 instruct cmovL_regUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, rRegL src2) 
 6759 %{
 6760   predicate(UseAPX);
 6761   match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
 6762   ins_cost(200);
 6763   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
 6764   ins_encode %{
 6765     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Register);
 6766   %}
 6767   ins_pipe(pipe_cmov_reg);
 6768 %}
 6769 
 6770 instruct cmovL_regUCF2_ne(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
 6771   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6772   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 6773 
 6774   ins_cost(200); // XXX
 6775   format %{ "cmovpq  $dst, $src\n\t"
 6776             "cmovneq $dst, $src" %}
 6777   ins_encode %{
 6778     __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
 6779     __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
 6780   %}
 6781   ins_pipe(pipe_cmov_reg);
 6782 %}
 6783 
 6784 instruct cmovL_regUCF2_ne_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
 6785   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::ne);
 6786   match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
 6787 
 6788   ins_cost(200);
 6789   format %{ "ecmovpq  $dst, $src1, $src2\n\t"
 6790             "ecmovneq $dst, $src1, $src2" %}
 6791   ins_encode %{
 6792     __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6793     __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6794   %}
 6795   ins_pipe(pipe_cmov_reg);
 6796 %}
 6797 
 6798 // Since (x == y) == !(x != y), we can flip the sense of the test by flipping the
 6799 // inputs of the CMove
 6800 instruct cmovL_regUCF2_eq(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
 6801   predicate(!UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6802   match(Set dst (CMoveL (Binary cop cr) (Binary src dst)));
 6803 
 6804   ins_cost(200); // XXX
 6805   format %{ "cmovpq  $dst, $src\n\t"
 6806             "cmovneq $dst, $src" %}
 6807   ins_encode %{
 6808     __ cmovq(Assembler::parity, $dst$$Register, $src$$Register);
 6809     __ cmovq(Assembler::notEqual, $dst$$Register, $src$$Register);
 6810   %}
 6811   ins_pipe(pipe_cmov_reg);
 6812 %}
 6813 
 6814 instruct cmovL_regUCF2_eq_ndd(cmpOpUCF2 cop, rFlagsRegUCF cr, rRegL dst, rRegL src1, rRegL src2) %{
 6815   predicate(UseAPX && n->in(1)->in(1)->as_Bool()->_test._test == BoolTest::eq);
 6816   match(Set dst (CMoveL (Binary cop cr) (Binary src1 src2)));
 6817 
 6818   ins_cost(200);
 6819   format %{ "ecmovpq  $dst, $src1, $src2\n\t"
 6820             "ecmovneq $dst, $src1, $src2" %}
 6821   ins_encode %{
 6822     __ ecmovq(Assembler::parity, $dst$$Register, $src1$$Register, $src2$$Register);
 6823     __ ecmovq(Assembler::notEqual, $dst$$Register, $src1$$Register, $src2$$Register);
 6824   %}
 6825   ins_pipe(pipe_cmov_reg);
 6826 %}
 6827 
 6828 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
 6829 %{
 6830   predicate(!UseAPX);
 6831   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 6832 
 6833   ins_cost(200); // XXX
 6834   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 6835   ins_encode %{
 6836     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 6837   %}
 6838   ins_pipe(pipe_cmov_mem); // XXX
 6839 %}
 6840 
 6841 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
 6842   predicate(!UseAPX);
 6843   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 6844   ins_cost(200);
 6845   expand %{
 6846     cmovL_memU(cop, cr, dst, src);
 6847   %}
 6848 %}
 6849 
 6850 instruct cmovL_rReg_rReg_memU_ndd(rRegL dst, cmpOpU cop, rFlagsRegU cr, rRegL src1, memory src2)
 6851 %{
 6852   predicate(UseAPX);
 6853   match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
 6854 
 6855   ins_cost(200);
 6856   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
 6857   ins_encode %{
 6858     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6859   %}
 6860   ins_pipe(pipe_cmov_mem);
 6861 %}
 6862 
 6863 instruct cmovL_rReg_rReg_memUCF_ndd(rRegL dst, cmpOpUCF cop, rFlagsRegUCF cr, rRegL src1, memory src2) 
 6864 %{
 6865   predicate(UseAPX);
 6866   match(Set dst (CMoveL (Binary cop cr) (Binary src1 (LoadL src2))));
 6867   ins_cost(200);
 6868   format %{ "ecmovq$cop $dst, $src1, $src2\t# unsigned, long ndd" %}
 6869   ins_encode %{
 6870     __ ecmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src1$$Register, $src2$$Address);
 6871   %}
 6872   ins_pipe(pipe_cmov_mem);
 6873 %}
 6874 
 6875 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
 6876 %{
 6877   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 6878 
 6879   ins_cost(200); // XXX
 6880   format %{ "jn$cop    skip\t# signed cmove float\n\t"
 6881             "movss     $dst, $src\n"
 6882     "skip:" %}
 6883   ins_encode %{
 6884     Label Lskip;
 6885     // Invert sense of branch from sense of CMOV
 6886     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 6887     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 6888     __ bind(Lskip);
 6889   %}
 6890   ins_pipe(pipe_slow);
 6891 %}
 6892 
 6893 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
 6894 %{
 6895   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 6896 
 6897   ins_cost(200); // XXX
 6898   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
 6899             "movss     $dst, $src\n"
 6900     "skip:" %}
 6901   ins_encode %{
 6902     Label Lskip;
 6903     // Invert sense of branch from sense of CMOV
 6904     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 6905     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 6906     __ bind(Lskip);
 6907   %}
 6908   ins_pipe(pipe_slow);
 6909 %}
 6910 
 6911 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
 6912   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 6913   ins_cost(200);
 6914   expand %{
 6915     cmovF_regU(cop, cr, dst, src);
 6916   %}
 6917 %}
 6918 
 6919 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
 6920 %{
 6921   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 6922 
 6923   ins_cost(200); // XXX
 6924   format %{ "jn$cop    skip\t# signed cmove double\n\t"
 6925             "movsd     $dst, $src\n"
 6926     "skip:" %}
 6927   ins_encode %{
 6928     Label Lskip;
 6929     // Invert sense of branch from sense of CMOV
 6930     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 6931     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 6932     __ bind(Lskip);
 6933   %}
 6934   ins_pipe(pipe_slow);
 6935 %}
 6936 
 6937 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
 6938 %{
 6939   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 6940 
 6941   ins_cost(200); // XXX
 6942   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
 6943             "movsd     $dst, $src\n"
 6944     "skip:" %}
 6945   ins_encode %{
 6946     Label Lskip;
 6947     // Invert sense of branch from sense of CMOV
 6948     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 6949     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 6950     __ bind(Lskip);
 6951   %}
 6952   ins_pipe(pipe_slow);
 6953 %}
 6954 
 6955 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
 6956   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 6957   ins_cost(200);
 6958   expand %{
 6959     cmovD_regU(cop, cr, dst, src);
 6960   %}
 6961 %}
 6962 
 6963 //----------Arithmetic Instructions--------------------------------------------
 6964 //----------Addition Instructions----------------------------------------------
 6965 
 6966 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 6967 %{
 6968   predicate(!UseAPX);
 6969   match(Set dst (AddI dst src));
 6970   effect(KILL cr);
 6971   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 6972   format %{ "addl    $dst, $src\t# int" %}
 6973   ins_encode %{
 6974     __ addl($dst$$Register, $src$$Register);
 6975   %}
 6976   ins_pipe(ialu_reg_reg);
 6977 %}
 6978 
 6979 instruct addI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
 6980 %{
 6981   predicate(UseAPX);
 6982   match(Set dst (AddI src1 src2));
 6983   effect(KILL cr);
 6984   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 6985 
 6986   format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
 6987   ins_encode %{
 6988     __ eaddl($dst$$Register, $src1$$Register, $src2$$Register, false);
 6989   %}
 6990   ins_pipe(ialu_reg_reg);
 6991 %}
 6992 
 6993 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 6994 %{
 6995   predicate(!UseAPX);
 6996   match(Set dst (AddI dst src));
 6997   effect(KILL cr);
 6998   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 6999 
 7000   format %{ "addl    $dst, $src\t# int" %}
 7001   ins_encode %{
 7002     __ addl($dst$$Register, $src$$constant);
 7003   %}
 7004   ins_pipe( ialu_reg );
 7005 %}
 7006 
 7007 instruct addI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
 7008 %{
 7009   predicate(UseAPX);
 7010   match(Set dst (AddI src1 src2));
 7011   effect(KILL cr);
 7012   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7013 
 7014   format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
 7015   ins_encode %{
 7016     __ eaddl($dst$$Register, $src1$$Register, $src2$$constant, false);
 7017   %}
 7018   ins_pipe( ialu_reg );
 7019 %}
 7020 
 7021 instruct addI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
 7022 %{
 7023   predicate(UseAPX);
 7024   match(Set dst (AddI (LoadI src1) src2));
 7025   effect(KILL cr);
 7026   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7027 
 7028   format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
 7029   ins_encode %{
 7030     __ eaddl($dst$$Register, $src1$$Address, $src2$$constant, false);
 7031   %}
 7032   ins_pipe( ialu_reg );
 7033 %}
 7034 
 7035 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 7036 %{
 7037   predicate(!UseAPX);
 7038   match(Set dst (AddI dst (LoadI src)));
 7039   effect(KILL cr);
 7040   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7041 
 7042   ins_cost(150); // XXX
 7043   format %{ "addl    $dst, $src\t# int" %}
 7044   ins_encode %{
 7045     __ addl($dst$$Register, $src$$Address);
 7046   %}
 7047   ins_pipe(ialu_reg_mem);
 7048 %}
 7049 
 7050 instruct addI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
 7051 %{
 7052   predicate(UseAPX);
 7053   match(Set dst (AddI (LoadI src1) src2));
 7054   effect(KILL cr);
 7055   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7056 
 7057   ins_cost(150);
 7058   format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
 7059   ins_encode %{
 7060     __ eaddl($dst$$Register, $src1$$Address, $src2$$Register, false);
 7061   %}
 7062   ins_pipe(ialu_reg_mem);
 7063 %}
 7064 
 7065 instruct addI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
 7066 %{
 7067   predicate(UseAPX);
 7068   match(Set dst (AddI src1 (LoadI src2)));
 7069   effect(KILL cr);
 7070   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7071 
 7072   ins_cost(150);
 7073   format %{ "eaddl    $dst, $src1, $src2\t# int ndd" %}
 7074   ins_encode %{
 7075     __ eaddl($dst$$Register, $src1$$Register, $src2$$Address, false);
 7076   %}
 7077   ins_pipe(ialu_reg_mem);
 7078 %}
 7079 
 7080 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 7081 %{
 7082   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7083   effect(KILL cr);
 7084   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7085 
 7086   ins_cost(150); // XXX
 7087   format %{ "addl    $dst, $src\t# int" %}
 7088   ins_encode %{
 7089     __ addl($dst$$Address, $src$$Register);
 7090   %}
 7091   ins_pipe(ialu_mem_reg);
 7092 %}
 7093 
 7094 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
 7095 %{
 7096   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7097   effect(KILL cr);
 7098   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7099 
 7100 
 7101   ins_cost(125); // XXX
 7102   format %{ "addl    $dst, $src\t# int" %}
 7103   ins_encode %{
 7104     __ addl($dst$$Address, $src$$constant);
 7105   %}
 7106   ins_pipe(ialu_mem_imm);
 7107 %}
 7108 
 7109 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
 7110 %{
 7111   predicate(!UseAPX && UseIncDec);
 7112   match(Set dst (AddI dst src));
 7113   effect(KILL cr);
 7114 
 7115   format %{ "incl    $dst\t# int" %}
 7116   ins_encode %{
 7117     __ incrementl($dst$$Register);
 7118   %}
 7119   ins_pipe(ialu_reg);
 7120 %}
 7121 
 7122 instruct incI_rReg_ndd(rRegI dst, rRegI src, immI_1 val, rFlagsReg cr)
 7123 %{
 7124   predicate(UseAPX && UseIncDec);
 7125   match(Set dst (AddI src val));
 7126   effect(KILL cr);
 7127 
 7128   format %{ "eincl    $dst, $src\t# int ndd" %}
 7129   ins_encode %{
 7130     __ eincl($dst$$Register, $src$$Register, false);
 7131   %}
 7132   ins_pipe(ialu_reg);
 7133 %}
 7134 
 7135 instruct incI_rReg_mem_ndd(rRegI dst, memory src, immI_1 val, rFlagsReg cr)
 7136 %{
 7137   predicate(UseAPX && UseIncDec);
 7138   match(Set dst (AddI (LoadI src) val));
 7139   effect(KILL cr);
 7140 
 7141   format %{ "eincl    $dst, $src\t# int ndd" %}
 7142   ins_encode %{
 7143     __ eincl($dst$$Register, $src$$Address, false);
 7144   %}
 7145   ins_pipe(ialu_reg);
 7146 %}
 7147 
 7148 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
 7149 %{
 7150   predicate(UseIncDec);
 7151   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7152   effect(KILL cr);
 7153 
 7154   ins_cost(125); // XXX
 7155   format %{ "incl    $dst\t# int" %}
 7156   ins_encode %{
 7157     __ incrementl($dst$$Address);
 7158   %}
 7159   ins_pipe(ialu_mem_imm);
 7160 %}
 7161 
 7162 // XXX why does that use AddI
 7163 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
 7164 %{
 7165   predicate(!UseAPX && UseIncDec);
 7166   match(Set dst (AddI dst src));
 7167   effect(KILL cr);
 7168 
 7169   format %{ "decl    $dst\t# int" %}
 7170   ins_encode %{
 7171     __ decrementl($dst$$Register);
 7172   %}
 7173   ins_pipe(ialu_reg);
 7174 %}
 7175 
 7176 instruct decI_rReg_ndd(rRegI dst, rRegI src, immI_M1 val, rFlagsReg cr)
 7177 %{
 7178   predicate(UseAPX && UseIncDec);
 7179   match(Set dst (AddI src val));
 7180   effect(KILL cr);
 7181 
 7182   format %{ "edecl    $dst, $src\t# int ndd" %}
 7183   ins_encode %{
 7184     __ edecl($dst$$Register, $src$$Register, false);
 7185   %}
 7186   ins_pipe(ialu_reg);
 7187 %}
 7188 
 7189 instruct decI_rReg_mem_ndd(rRegI dst, memory src, immI_M1 val, rFlagsReg cr)
 7190 %{
 7191   predicate(UseAPX && UseIncDec);
 7192   match(Set dst (AddI (LoadI src) val));
 7193   effect(KILL cr);
 7194 
 7195   format %{ "edecl    $dst, $src\t# int ndd" %}
 7196   ins_encode %{
 7197     __ edecl($dst$$Register, $src$$Address, false);
 7198   %}
 7199   ins_pipe(ialu_reg);
 7200 %}
 7201 
 7202 // XXX why does that use AddI
 7203 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
 7204 %{
 7205   predicate(UseIncDec);
 7206   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7207   effect(KILL cr);
 7208 
 7209   ins_cost(125); // XXX
 7210   format %{ "decl    $dst\t# int" %}
 7211   ins_encode %{
 7212     __ decrementl($dst$$Address);
 7213   %}
 7214   ins_pipe(ialu_mem_imm);
 7215 %}
 7216 
 7217 instruct leaI_rReg_immI2_immI(rRegI dst, rRegI index, immI2 scale, immI disp)
 7218 %{
 7219   predicate(VM_Version::supports_fast_2op_lea());
 7220   match(Set dst (AddI (LShiftI index scale) disp));
 7221 
 7222   format %{ "leal $dst, [$index << $scale + $disp]\t# int" %}
 7223   ins_encode %{
 7224     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7225     __ leal($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
 7226   %}
 7227   ins_pipe(ialu_reg_reg);
 7228 %}
 7229 
 7230 instruct leaI_rReg_rReg_immI(rRegI dst, rRegI base, rRegI index, immI disp)
 7231 %{
 7232   predicate(VM_Version::supports_fast_3op_lea());
 7233   match(Set dst (AddI (AddI base index) disp));
 7234 
 7235   format %{ "leal $dst, [$base + $index + $disp]\t# int" %}
 7236   ins_encode %{
 7237     __ leal($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
 7238   %}
 7239   ins_pipe(ialu_reg_reg);
 7240 %}
 7241 
 7242 instruct leaI_rReg_rReg_immI2(rRegI dst, no_rbp_r13_RegI base, rRegI index, immI2 scale)
 7243 %{
 7244   predicate(VM_Version::supports_fast_2op_lea());
 7245   match(Set dst (AddI base (LShiftI index scale)));
 7246 
 7247   format %{ "leal $dst, [$base + $index << $scale]\t# int" %}
 7248   ins_encode %{
 7249     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7250     __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale));
 7251   %}
 7252   ins_pipe(ialu_reg_reg);
 7253 %}
 7254 
 7255 instruct leaI_rReg_rReg_immI2_immI(rRegI dst, rRegI base, rRegI index, immI2 scale, immI disp)
 7256 %{
 7257   predicate(VM_Version::supports_fast_3op_lea());
 7258   match(Set dst (AddI (AddI base (LShiftI index scale)) disp));
 7259 
 7260   format %{ "leal $dst, [$base + $index << $scale + $disp]\t# int" %}
 7261   ins_encode %{
 7262     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7263     __ leal($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
 7264   %}
 7265   ins_pipe(ialu_reg_reg);
 7266 %}
 7267 
 7268 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 7269 %{
 7270   predicate(!UseAPX);
 7271   match(Set dst (AddL dst src));
 7272   effect(KILL cr);
 7273   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7274 
 7275   format %{ "addq    $dst, $src\t# long" %}
 7276   ins_encode %{
 7277     __ addq($dst$$Register, $src$$Register);
 7278   %}
 7279   ins_pipe(ialu_reg_reg);
 7280 %}
 7281 
 7282 instruct addL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
 7283 %{
 7284   predicate(UseAPX);
 7285   match(Set dst (AddL src1 src2));
 7286   effect(KILL cr);
 7287   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7288 
 7289   format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
 7290   ins_encode %{
 7291     __ eaddq($dst$$Register, $src1$$Register, $src2$$Register, false);
 7292   %}
 7293   ins_pipe(ialu_reg_reg);
 7294 %}
 7295 
 7296 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
 7297 %{
 7298   predicate(!UseAPX);
 7299   match(Set dst (AddL dst src));
 7300   effect(KILL cr);
 7301   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7302 
 7303   format %{ "addq    $dst, $src\t# long" %}
 7304   ins_encode %{
 7305     __ addq($dst$$Register, $src$$constant);
 7306   %}
 7307   ins_pipe( ialu_reg );
 7308 %}
 7309 
 7310 instruct addL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
 7311 %{
 7312   predicate(UseAPX);
 7313   match(Set dst (AddL src1 src2));
 7314   effect(KILL cr);
 7315   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7316 
 7317   format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
 7318   ins_encode %{
 7319     __ eaddq($dst$$Register, $src1$$Register, $src2$$constant, false);
 7320   %}
 7321   ins_pipe( ialu_reg );
 7322 %}
 7323 
 7324 instruct addL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
 7325 %{
 7326   predicate(UseAPX);
 7327   match(Set dst (AddL (LoadL src1) src2));
 7328   effect(KILL cr);
 7329   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7330 
 7331   format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
 7332   ins_encode %{
 7333     __ eaddq($dst$$Register, $src1$$Address, $src2$$constant, false);
 7334   %}
 7335   ins_pipe( ialu_reg );
 7336 %}
 7337 
 7338 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 7339 %{
 7340   predicate(!UseAPX);
 7341   match(Set dst (AddL dst (LoadL src)));
 7342   effect(KILL cr);
 7343   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7344 
 7345   ins_cost(150); // XXX
 7346   format %{ "addq    $dst, $src\t# long" %}
 7347   ins_encode %{
 7348     __ addq($dst$$Register, $src$$Address);
 7349   %}
 7350   ins_pipe(ialu_reg_mem);
 7351 %}
 7352 
 7353 instruct addL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
 7354 %{
 7355   predicate(UseAPX);
 7356   match(Set dst (AddL src1 (LoadL src2)));
 7357   effect(KILL cr);
 7358   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7359 
 7360   ins_cost(150);
 7361   format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
 7362   ins_encode %{
 7363     __ eaddq($dst$$Register, $src1$$Register, $src2$$Address, false);
 7364   %}
 7365   ins_pipe(ialu_reg_mem);
 7366 %}
 7367 
 7368 instruct addL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
 7369 %{
 7370   predicate(UseAPX);
 7371   match(Set dst (AddL (LoadL src1) src2));
 7372   effect(KILL cr);
 7373   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7374 
 7375   ins_cost(150);
 7376   format %{ "eaddq    $dst, $src1, $src2\t# long ndd" %}
 7377   ins_encode %{
 7378     __ eaddq($dst$$Register, $src1$$Address, $src2$$Register, false);
 7379   %}
 7380   ins_pipe(ialu_reg_mem);
 7381 %}
 7382 
 7383 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 7384 %{
 7385   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7386   effect(KILL cr);
 7387   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7388 
 7389   ins_cost(150); // XXX
 7390   format %{ "addq    $dst, $src\t# long" %}
 7391   ins_encode %{
 7392     __ addq($dst$$Address, $src$$Register);
 7393   %}
 7394   ins_pipe(ialu_mem_reg);
 7395 %}
 7396 
 7397 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 7398 %{
 7399   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7400   effect(KILL cr);
 7401   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7402 
 7403   ins_cost(125); // XXX
 7404   format %{ "addq    $dst, $src\t# long" %}
 7405   ins_encode %{
 7406     __ addq($dst$$Address, $src$$constant);
 7407   %}
 7408   ins_pipe(ialu_mem_imm);
 7409 %}
 7410 
 7411 instruct incL_rReg(rRegL dst, immL1 src, rFlagsReg cr)
 7412 %{
 7413   predicate(!UseAPX && UseIncDec);
 7414   match(Set dst (AddL dst src));
 7415   effect(KILL cr);
 7416 
 7417   format %{ "incq    $dst\t# long" %}
 7418   ins_encode %{
 7419     __ incrementq($dst$$Register);
 7420   %}
 7421   ins_pipe(ialu_reg);
 7422 %}
 7423 
 7424 instruct incL_rReg_ndd(rRegL dst, rRegI src, immL1 val, rFlagsReg cr)
 7425 %{
 7426   predicate(UseAPX && UseIncDec);
 7427   match(Set dst (AddL src val));
 7428   effect(KILL cr);
 7429 
 7430   format %{ "eincq    $dst, $src\t# long ndd" %}
 7431   ins_encode %{
 7432     __ eincq($dst$$Register, $src$$Register, false);
 7433   %}
 7434   ins_pipe(ialu_reg);
 7435 %}
 7436 
 7437 instruct incL_rReg_mem_ndd(rRegL dst, memory src, immL1 val, rFlagsReg cr)
 7438 %{
 7439   predicate(UseAPX && UseIncDec);
 7440   match(Set dst (AddL (LoadL src) val));
 7441   effect(KILL cr);
 7442 
 7443   format %{ "eincq    $dst, $src\t# long ndd" %}
 7444   ins_encode %{
 7445     __ eincq($dst$$Register, $src$$Address, false);
 7446   %}
 7447   ins_pipe(ialu_reg);
 7448 %}
 7449 
 7450 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
 7451 %{
 7452   predicate(UseIncDec);
 7453   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7454   effect(KILL cr);
 7455 
 7456   ins_cost(125); // XXX
 7457   format %{ "incq    $dst\t# long" %}
 7458   ins_encode %{
 7459     __ incrementq($dst$$Address);
 7460   %}
 7461   ins_pipe(ialu_mem_imm);
 7462 %}
 7463 
 7464 // XXX why does that use AddL
 7465 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
 7466 %{
 7467   predicate(!UseAPX && UseIncDec);
 7468   match(Set dst (AddL dst src));
 7469   effect(KILL cr);
 7470 
 7471   format %{ "decq    $dst\t# long" %}
 7472   ins_encode %{
 7473     __ decrementq($dst$$Register);
 7474   %}
 7475   ins_pipe(ialu_reg);
 7476 %}
 7477 
 7478 instruct decL_rReg_ndd(rRegL dst, rRegL src, immL_M1 val, rFlagsReg cr)
 7479 %{
 7480   predicate(UseAPX && UseIncDec);
 7481   match(Set dst (AddL src val));
 7482   effect(KILL cr);
 7483 
 7484   format %{ "edecq    $dst, $src\t# long ndd" %}
 7485   ins_encode %{
 7486     __ edecq($dst$$Register, $src$$Register, false);
 7487   %}
 7488   ins_pipe(ialu_reg);
 7489 %}
 7490 
 7491 instruct decL_rReg_mem_ndd(rRegL dst, memory src, immL_M1 val, rFlagsReg cr)
 7492 %{
 7493   predicate(UseAPX && UseIncDec);
 7494   match(Set dst (AddL (LoadL src) val));
 7495   effect(KILL cr);
 7496 
 7497   format %{ "edecq    $dst, $src\t# long ndd" %}
 7498   ins_encode %{
 7499     __ edecq($dst$$Register, $src$$Address, false);
 7500   %}
 7501   ins_pipe(ialu_reg);
 7502 %}
 7503 
 7504 // XXX why does that use AddL
 7505 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
 7506 %{
 7507   predicate(UseIncDec);
 7508   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7509   effect(KILL cr);
 7510 
 7511   ins_cost(125); // XXX
 7512   format %{ "decq    $dst\t# long" %}
 7513   ins_encode %{
 7514     __ decrementq($dst$$Address);
 7515   %}
 7516   ins_pipe(ialu_mem_imm);
 7517 %}
 7518 
 7519 instruct leaL_rReg_immI2_immL32(rRegL dst, rRegL index, immI2 scale, immL32 disp)
 7520 %{
 7521   predicate(VM_Version::supports_fast_2op_lea());
 7522   match(Set dst (AddL (LShiftL index scale) disp));
 7523 
 7524   format %{ "leaq $dst, [$index << $scale + $disp]\t# long" %}
 7525   ins_encode %{
 7526     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7527     __ leaq($dst$$Register, Address(noreg, $index$$Register, scale, $disp$$constant));
 7528   %}
 7529   ins_pipe(ialu_reg_reg);
 7530 %}
 7531 
 7532 instruct leaL_rReg_rReg_immL32(rRegL dst, rRegL base, rRegL index, immL32 disp)
 7533 %{
 7534   predicate(VM_Version::supports_fast_3op_lea());
 7535   match(Set dst (AddL (AddL base index) disp));
 7536 
 7537   format %{ "leaq $dst, [$base + $index + $disp]\t# long" %}
 7538   ins_encode %{
 7539     __ leaq($dst$$Register, Address($base$$Register, $index$$Register, Address::times_1, $disp$$constant));
 7540   %}
 7541   ins_pipe(ialu_reg_reg);
 7542 %}
 7543 
 7544 instruct leaL_rReg_rReg_immI2(rRegL dst, no_rbp_r13_RegL base, rRegL index, immI2 scale)
 7545 %{
 7546   predicate(VM_Version::supports_fast_2op_lea());
 7547   match(Set dst (AddL base (LShiftL index scale)));
 7548 
 7549   format %{ "leaq $dst, [$base + $index << $scale]\t# long" %}
 7550   ins_encode %{
 7551     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7552     __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale));
 7553   %}
 7554   ins_pipe(ialu_reg_reg);
 7555 %}
 7556 
 7557 instruct leaL_rReg_rReg_immI2_immL32(rRegL dst, rRegL base, rRegL index, immI2 scale, immL32 disp)
 7558 %{
 7559   predicate(VM_Version::supports_fast_3op_lea());
 7560   match(Set dst (AddL (AddL base (LShiftL index scale)) disp));
 7561 
 7562   format %{ "leaq $dst, [$base + $index << $scale + $disp]\t# long" %}
 7563   ins_encode %{
 7564     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($scale$$constant);
 7565     __ leaq($dst$$Register, Address($base$$Register, $index$$Register, scale, $disp$$constant));
 7566   %}
 7567   ins_pipe(ialu_reg_reg);
 7568 %}
 7569 
 7570 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
 7571 %{
 7572   match(Set dst (AddP dst src));
 7573   effect(KILL cr);
 7574   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7575 
 7576   format %{ "addq    $dst, $src\t# ptr" %}
 7577   ins_encode %{
 7578     __ addq($dst$$Register, $src$$Register);
 7579   %}
 7580   ins_pipe(ialu_reg_reg);
 7581 %}
 7582 
 7583 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
 7584 %{
 7585   match(Set dst (AddP dst src));
 7586   effect(KILL cr);
 7587   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 7588 
 7589   format %{ "addq    $dst, $src\t# ptr" %}
 7590   ins_encode %{
 7591     __ addq($dst$$Register, $src$$constant);
 7592   %}
 7593   ins_pipe( ialu_reg );
 7594 %}
 7595 
 7596 // XXX addP mem ops ????
 7597 
 7598 instruct checkCastPP(rRegP dst)
 7599 %{
 7600   match(Set dst (CheckCastPP dst));
 7601 
 7602   size(0);
 7603   format %{ "# checkcastPP of $dst" %}
 7604   ins_encode(/* empty encoding */);
 7605   ins_pipe(empty);
 7606 %}
 7607 
 7608 instruct castPP(rRegP dst)
 7609 %{
 7610   match(Set dst (CastPP dst));
 7611 
 7612   size(0);
 7613   format %{ "# castPP of $dst" %}
 7614   ins_encode(/* empty encoding */);
 7615   ins_pipe(empty);
 7616 %}
 7617 
 7618 instruct castII(rRegI dst)
 7619 %{
 7620   predicate(VerifyConstraintCasts == 0);
 7621   match(Set dst (CastII dst));
 7622 
 7623   size(0);
 7624   format %{ "# castII of $dst" %}
 7625   ins_encode(/* empty encoding */);
 7626   ins_cost(0);
 7627   ins_pipe(empty);
 7628 %}
 7629 
 7630 instruct castII_checked(rRegI dst, rFlagsReg cr)
 7631 %{
 7632   predicate(VerifyConstraintCasts > 0);
 7633   match(Set dst (CastII dst));
 7634 
 7635   effect(KILL cr);
 7636   format %{ "# cast_checked_II $dst" %}
 7637   ins_encode %{
 7638     __ verify_int_in_range(_idx, bottom_type()->is_int(), $dst$$Register);
 7639   %}
 7640   ins_pipe(pipe_slow);
 7641 %}
 7642 
 7643 instruct castLL(rRegL dst)
 7644 %{
 7645   predicate(VerifyConstraintCasts == 0);
 7646   match(Set dst (CastLL dst));
 7647 
 7648   size(0);
 7649   format %{ "# castLL of $dst" %}
 7650   ins_encode(/* empty encoding */);
 7651   ins_cost(0);
 7652   ins_pipe(empty);
 7653 %}
 7654 
 7655 instruct castLL_checked_L32(rRegL dst, rFlagsReg cr)
 7656 %{
 7657   predicate(VerifyConstraintCasts > 0 && castLL_is_imm32(n));
 7658   match(Set dst (CastLL dst));
 7659 
 7660   effect(KILL cr);
 7661   format %{ "# cast_checked_LL $dst" %}
 7662   ins_encode %{
 7663     __ verify_long_in_range(_idx, bottom_type()->is_long(), $dst$$Register, noreg);
 7664   %}
 7665   ins_pipe(pipe_slow);
 7666 %}
 7667 
 7668 instruct castLL_checked(rRegL dst, rRegL tmp, rFlagsReg cr)
 7669 %{
 7670   predicate(VerifyConstraintCasts > 0 && !castLL_is_imm32(n));
 7671   match(Set dst (CastLL dst));
 7672 
 7673   effect(KILL cr, TEMP tmp);
 7674   format %{ "# cast_checked_LL $dst\tusing $tmp as TEMP" %}
 7675   ins_encode %{
 7676     __ verify_long_in_range(_idx, bottom_type()->is_long(), $dst$$Register, $tmp$$Register);
 7677   %}
 7678   ins_pipe(pipe_slow);
 7679 %}
 7680 
 7681 instruct castFF(regF dst)
 7682 %{
 7683   match(Set dst (CastFF dst));
 7684 
 7685   size(0);
 7686   format %{ "# castFF of $dst" %}
 7687   ins_encode(/* empty encoding */);
 7688   ins_cost(0);
 7689   ins_pipe(empty);
 7690 %}
 7691 
 7692 instruct castHH(regF dst)
 7693 %{
 7694   match(Set dst (CastHH dst));
 7695 
 7696   size(0);
 7697   format %{ "# castHH of $dst" %}
 7698   ins_encode(/* empty encoding */);
 7699   ins_cost(0);
 7700   ins_pipe(empty);
 7701 %}
 7702 
 7703 instruct castDD(regD dst)
 7704 %{
 7705   match(Set dst (CastDD dst));
 7706 
 7707   size(0);
 7708   format %{ "# castDD of $dst" %}
 7709   ins_encode(/* empty encoding */);
 7710   ins_cost(0);
 7711   ins_pipe(empty);
 7712 %}
 7713 
 7714 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
 7715 instruct compareAndSwapP(rRegI res,
 7716                          memory mem_ptr,
 7717                          rax_RegP oldval, rRegP newval,
 7718                          rFlagsReg cr)
 7719 %{
 7720   predicate(n->as_LoadStore()->barrier_data() == 0);
 7721   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
 7722   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
 7723   effect(KILL cr, KILL oldval);
 7724 
 7725   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7726             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7727             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7728   ins_encode %{
 7729     __ lock();
 7730     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7731     __ setcc(Assembler::equal, $res$$Register);
 7732   %}
 7733   ins_pipe( pipe_cmpxchg );
 7734 %}
 7735 
 7736 instruct compareAndSwapL(rRegI res,
 7737                          memory mem_ptr,
 7738                          rax_RegL oldval, rRegL newval,
 7739                          rFlagsReg cr)
 7740 %{
 7741   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
 7742   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
 7743   effect(KILL cr, KILL oldval);
 7744 
 7745   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7746             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7747             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7748   ins_encode %{
 7749     __ lock();
 7750     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7751     __ setcc(Assembler::equal, $res$$Register);
 7752   %}
 7753   ins_pipe( pipe_cmpxchg );
 7754 %}
 7755 
 7756 instruct compareAndSwapI(rRegI res,
 7757                          memory mem_ptr,
 7758                          rax_RegI oldval, rRegI newval,
 7759                          rFlagsReg cr)
 7760 %{
 7761   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
 7762   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
 7763   effect(KILL cr, KILL oldval);
 7764 
 7765   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7766             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7767             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7768   ins_encode %{
 7769     __ lock();
 7770     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7771     __ setcc(Assembler::equal, $res$$Register);
 7772   %}
 7773   ins_pipe( pipe_cmpxchg );
 7774 %}
 7775 
 7776 instruct compareAndSwapB(rRegI res,
 7777                          memory mem_ptr,
 7778                          rax_RegI oldval, rRegI newval,
 7779                          rFlagsReg cr)
 7780 %{
 7781   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
 7782   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
 7783   effect(KILL cr, KILL oldval);
 7784 
 7785   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7786             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7787             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7788   ins_encode %{
 7789     __ lock();
 7790     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7791     __ setcc(Assembler::equal, $res$$Register);
 7792   %}
 7793   ins_pipe( pipe_cmpxchg );
 7794 %}
 7795 
 7796 instruct compareAndSwapS(rRegI res,
 7797                          memory mem_ptr,
 7798                          rax_RegI oldval, rRegI newval,
 7799                          rFlagsReg cr)
 7800 %{
 7801   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
 7802   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
 7803   effect(KILL cr, KILL oldval);
 7804 
 7805   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7806             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7807             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7808   ins_encode %{
 7809     __ lock();
 7810     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7811     __ setcc(Assembler::equal, $res$$Register);
 7812   %}
 7813   ins_pipe( pipe_cmpxchg );
 7814 %}
 7815 
 7816 instruct compareAndSwapN(rRegI res,
 7817                           memory mem_ptr,
 7818                           rax_RegN oldval, rRegN newval,
 7819                           rFlagsReg cr) %{
 7820   predicate(n->as_LoadStore()->barrier_data() == 0);
 7821   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
 7822   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
 7823   effect(KILL cr, KILL oldval);
 7824 
 7825   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7826             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7827             "setcc $res \t# emits sete + movzbl or setzue for APX" %}
 7828   ins_encode %{
 7829     __ lock();
 7830     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7831     __ setcc(Assembler::equal, $res$$Register);
 7832   %}
 7833   ins_pipe( pipe_cmpxchg );
 7834 %}
 7835 
 7836 instruct compareAndExchangeB(
 7837                          memory mem_ptr,
 7838                          rax_RegI oldval, rRegI newval,
 7839                          rFlagsReg cr)
 7840 %{
 7841   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
 7842   effect(KILL cr);
 7843 
 7844   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7845             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7846   ins_encode %{
 7847     __ lock();
 7848     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7849   %}
 7850   ins_pipe( pipe_cmpxchg );
 7851 %}
 7852 
 7853 instruct compareAndExchangeS(
 7854                          memory mem_ptr,
 7855                          rax_RegI oldval, rRegI newval,
 7856                          rFlagsReg cr)
 7857 %{
 7858   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
 7859   effect(KILL cr);
 7860 
 7861   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7862             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7863   ins_encode %{
 7864     __ lock();
 7865     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7866   %}
 7867   ins_pipe( pipe_cmpxchg );
 7868 %}
 7869 
 7870 instruct compareAndExchangeI(
 7871                          memory mem_ptr,
 7872                          rax_RegI oldval, rRegI newval,
 7873                          rFlagsReg cr)
 7874 %{
 7875   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
 7876   effect(KILL cr);
 7877 
 7878   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7879             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7880   ins_encode %{
 7881     __ lock();
 7882     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7883   %}
 7884   ins_pipe( pipe_cmpxchg );
 7885 %}
 7886 
 7887 instruct compareAndExchangeL(
 7888                          memory mem_ptr,
 7889                          rax_RegL oldval, rRegL newval,
 7890                          rFlagsReg cr)
 7891 %{
 7892   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
 7893   effect(KILL cr);
 7894 
 7895   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7896             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7897   ins_encode %{
 7898     __ lock();
 7899     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7900   %}
 7901   ins_pipe( pipe_cmpxchg );
 7902 %}
 7903 
 7904 instruct compareAndExchangeN(
 7905                           memory mem_ptr,
 7906                           rax_RegN oldval, rRegN newval,
 7907                           rFlagsReg cr) %{
 7908   predicate(n->as_LoadStore()->barrier_data() == 0);
 7909   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
 7910   effect(KILL cr);
 7911 
 7912   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7913             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7914   ins_encode %{
 7915     __ lock();
 7916     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7917   %}
 7918   ins_pipe( pipe_cmpxchg );
 7919 %}
 7920 
 7921 instruct compareAndExchangeP(
 7922                          memory mem_ptr,
 7923                          rax_RegP oldval, rRegP newval,
 7924                          rFlagsReg cr)
 7925 %{
 7926   predicate(n->as_LoadStore()->barrier_data() == 0);
 7927   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
 7928   effect(KILL cr);
 7929 
 7930   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7931             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7932   ins_encode %{
 7933     __ lock();
 7934     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7935   %}
 7936   ins_pipe( pipe_cmpxchg );
 7937 %}
 7938 
 7939 instruct xaddB_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
 7940   predicate(n->as_LoadStore()->result_not_used());
 7941   match(Set dummy (GetAndAddB mem add));
 7942   effect(KILL cr);
 7943   format %{ "addb_lock   $mem, $add" %}
 7944   ins_encode %{
 7945     __ lock();
 7946     __ addb($mem$$Address, $add$$Register);
 7947   %}
 7948   ins_pipe(pipe_cmpxchg);
 7949 %}
 7950 
 7951 instruct xaddB_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 7952   predicate(n->as_LoadStore()->result_not_used());
 7953   match(Set dummy (GetAndAddB mem add));
 7954   effect(KILL cr);
 7955   format %{ "addb_lock   $mem, $add" %}
 7956   ins_encode %{
 7957     __ lock();
 7958     __ addb($mem$$Address, $add$$constant);
 7959   %}
 7960   ins_pipe(pipe_cmpxchg);
 7961 %}
 7962 
 7963 instruct xaddB(memory mem, rRegI newval, rFlagsReg cr) %{
 7964   predicate(!n->as_LoadStore()->result_not_used());
 7965   match(Set newval (GetAndAddB mem newval));
 7966   effect(KILL cr);
 7967   format %{ "xaddb_lock  $mem, $newval" %}
 7968   ins_encode %{
 7969     __ lock();
 7970     __ xaddb($mem$$Address, $newval$$Register);
 7971   %}
 7972   ins_pipe(pipe_cmpxchg);
 7973 %}
 7974 
 7975 instruct xaddS_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
 7976   predicate(n->as_LoadStore()->result_not_used());
 7977   match(Set dummy (GetAndAddS mem add));
 7978   effect(KILL cr);
 7979   format %{ "addw_lock   $mem, $add" %}
 7980   ins_encode %{
 7981     __ lock();
 7982     __ addw($mem$$Address, $add$$Register);
 7983   %}
 7984   ins_pipe(pipe_cmpxchg);
 7985 %}
 7986 
 7987 instruct xaddS_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 7988   predicate(UseStoreImmI16 && n->as_LoadStore()->result_not_used());
 7989   match(Set dummy (GetAndAddS mem add));
 7990   effect(KILL cr);
 7991   format %{ "addw_lock   $mem, $add" %}
 7992   ins_encode %{
 7993     __ lock();
 7994     __ addw($mem$$Address, $add$$constant);
 7995   %}
 7996   ins_pipe(pipe_cmpxchg);
 7997 %}
 7998 
 7999 instruct xaddS(memory mem, rRegI newval, rFlagsReg cr) %{
 8000   predicate(!n->as_LoadStore()->result_not_used());
 8001   match(Set newval (GetAndAddS mem newval));
 8002   effect(KILL cr);
 8003   format %{ "xaddw_lock  $mem, $newval" %}
 8004   ins_encode %{
 8005     __ lock();
 8006     __ xaddw($mem$$Address, $newval$$Register);
 8007   %}
 8008   ins_pipe(pipe_cmpxchg);
 8009 %}
 8010 
 8011 instruct xaddI_reg_no_res(memory mem, Universe dummy, rRegI add, rFlagsReg cr) %{
 8012   predicate(n->as_LoadStore()->result_not_used());
 8013   match(Set dummy (GetAndAddI mem add));
 8014   effect(KILL cr);
 8015   format %{ "addl_lock   $mem, $add" %}
 8016   ins_encode %{
 8017     __ lock();
 8018     __ addl($mem$$Address, $add$$Register);
 8019   %}
 8020   ins_pipe(pipe_cmpxchg);
 8021 %}
 8022 
 8023 instruct xaddI_imm_no_res(memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 8024   predicate(n->as_LoadStore()->result_not_used());
 8025   match(Set dummy (GetAndAddI mem add));
 8026   effect(KILL cr);
 8027   format %{ "addl_lock   $mem, $add" %}
 8028   ins_encode %{
 8029     __ lock();
 8030     __ addl($mem$$Address, $add$$constant);
 8031   %}
 8032   ins_pipe(pipe_cmpxchg);
 8033 %}
 8034 
 8035 instruct xaddI(memory mem, rRegI newval, rFlagsReg cr) %{
 8036   predicate(!n->as_LoadStore()->result_not_used());
 8037   match(Set newval (GetAndAddI mem newval));
 8038   effect(KILL cr);
 8039   format %{ "xaddl_lock  $mem, $newval" %}
 8040   ins_encode %{
 8041     __ lock();
 8042     __ xaddl($mem$$Address, $newval$$Register);
 8043   %}
 8044   ins_pipe(pipe_cmpxchg);
 8045 %}
 8046 
 8047 instruct xaddL_reg_no_res(memory mem, Universe dummy, rRegL add, rFlagsReg cr) %{
 8048   predicate(n->as_LoadStore()->result_not_used());
 8049   match(Set dummy (GetAndAddL mem add));
 8050   effect(KILL cr);
 8051   format %{ "addq_lock   $mem, $add" %}
 8052   ins_encode %{
 8053     __ lock();
 8054     __ addq($mem$$Address, $add$$Register);
 8055   %}
 8056   ins_pipe(pipe_cmpxchg);
 8057 %}
 8058 
 8059 instruct xaddL_imm_no_res(memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
 8060   predicate(n->as_LoadStore()->result_not_used());
 8061   match(Set dummy (GetAndAddL mem add));
 8062   effect(KILL cr);
 8063   format %{ "addq_lock   $mem, $add" %}
 8064   ins_encode %{
 8065     __ lock();
 8066     __ addq($mem$$Address, $add$$constant);
 8067   %}
 8068   ins_pipe(pipe_cmpxchg);
 8069 %}
 8070 
 8071 instruct xaddL(memory mem, rRegL newval, rFlagsReg cr) %{
 8072   predicate(!n->as_LoadStore()->result_not_used());
 8073   match(Set newval (GetAndAddL mem newval));
 8074   effect(KILL cr);
 8075   format %{ "xaddq_lock  $mem, $newval" %}
 8076   ins_encode %{
 8077     __ lock();
 8078     __ xaddq($mem$$Address, $newval$$Register);
 8079   %}
 8080   ins_pipe(pipe_cmpxchg);
 8081 %}
 8082 
 8083 instruct xchgB( memory mem, rRegI newval) %{
 8084   match(Set newval (GetAndSetB mem newval));
 8085   format %{ "XCHGB  $newval,[$mem]" %}
 8086   ins_encode %{
 8087     __ xchgb($newval$$Register, $mem$$Address);
 8088   %}
 8089   ins_pipe( pipe_cmpxchg );
 8090 %}
 8091 
 8092 instruct xchgS( memory mem, rRegI newval) %{
 8093   match(Set newval (GetAndSetS mem newval));
 8094   format %{ "XCHGW  $newval,[$mem]" %}
 8095   ins_encode %{
 8096     __ xchgw($newval$$Register, $mem$$Address);
 8097   %}
 8098   ins_pipe( pipe_cmpxchg );
 8099 %}
 8100 
 8101 instruct xchgI( memory mem, rRegI newval) %{
 8102   match(Set newval (GetAndSetI mem newval));
 8103   format %{ "XCHGL  $newval,[$mem]" %}
 8104   ins_encode %{
 8105     __ xchgl($newval$$Register, $mem$$Address);
 8106   %}
 8107   ins_pipe( pipe_cmpxchg );
 8108 %}
 8109 
 8110 instruct xchgL( memory mem, rRegL newval) %{
 8111   match(Set newval (GetAndSetL mem newval));
 8112   format %{ "XCHGL  $newval,[$mem]" %}
 8113   ins_encode %{
 8114     __ xchgq($newval$$Register, $mem$$Address);
 8115   %}
 8116   ins_pipe( pipe_cmpxchg );
 8117 %}
 8118 
 8119 instruct xchgP( memory mem, rRegP newval) %{
 8120   match(Set newval (GetAndSetP mem newval));
 8121   predicate(n->as_LoadStore()->barrier_data() == 0);
 8122   format %{ "XCHGQ  $newval,[$mem]" %}
 8123   ins_encode %{
 8124     __ xchgq($newval$$Register, $mem$$Address);
 8125   %}
 8126   ins_pipe( pipe_cmpxchg );
 8127 %}
 8128 
 8129 instruct xchgN( memory mem, rRegN newval) %{
 8130   predicate(n->as_LoadStore()->barrier_data() == 0);
 8131   match(Set newval (GetAndSetN mem newval));
 8132   format %{ "XCHGL  $newval,$mem]" %}
 8133   ins_encode %{
 8134     __ xchgl($newval$$Register, $mem$$Address);
 8135   %}
 8136   ins_pipe( pipe_cmpxchg );
 8137 %}
 8138 
 8139 //----------Abs Instructions-------------------------------------------
 8140 
 8141 // Integer Absolute Instructions
 8142 instruct absI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8143 %{
 8144   match(Set dst (AbsI src));
 8145   effect(TEMP dst, KILL cr);
 8146   format %{ "xorl    $dst, $dst\t# abs int\n\t"
 8147             "subl    $dst, $src\n\t"
 8148             "cmovll  $dst, $src" %}
 8149   ins_encode %{
 8150     __ xorl($dst$$Register, $dst$$Register);
 8151     __ subl($dst$$Register, $src$$Register);
 8152     __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
 8153   %}
 8154 
 8155   ins_pipe(ialu_reg_reg);
 8156 %}
 8157 
 8158 // Long Absolute Instructions
 8159 instruct absL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8160 %{
 8161   match(Set dst (AbsL src));
 8162   effect(TEMP dst, KILL cr);
 8163   format %{ "xorl    $dst, $dst\t# abs long\n\t"
 8164             "subq    $dst, $src\n\t"
 8165             "cmovlq  $dst, $src" %}
 8166   ins_encode %{
 8167     __ xorl($dst$$Register, $dst$$Register);
 8168     __ subq($dst$$Register, $src$$Register);
 8169     __ cmovq(Assembler::less, $dst$$Register, $src$$Register);
 8170   %}
 8171 
 8172   ins_pipe(ialu_reg_reg);
 8173 %}
 8174 
 8175 //----------Subtraction Instructions-------------------------------------------
 8176 
 8177 // Integer Subtraction Instructions
 8178 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8179 %{
 8180   predicate(!UseAPX);
 8181   match(Set dst (SubI dst src));
 8182   effect(KILL cr);
 8183   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8184 
 8185   format %{ "subl    $dst, $src\t# int" %}
 8186   ins_encode %{
 8187     __ subl($dst$$Register, $src$$Register);
 8188   %}
 8189   ins_pipe(ialu_reg_reg);
 8190 %}
 8191 
 8192 instruct subI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
 8193 %{
 8194   predicate(UseAPX);
 8195   match(Set dst (SubI src1 src2));
 8196   effect(KILL cr);
 8197   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8198 
 8199   format %{ "esubl    $dst, $src1, $src2\t# int ndd" %}
 8200   ins_encode %{
 8201     __ esubl($dst$$Register, $src1$$Register, $src2$$Register, false);
 8202   %}
 8203   ins_pipe(ialu_reg_reg);
 8204 %}
 8205 
 8206 instruct subI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
 8207 %{
 8208   predicate(UseAPX);
 8209   match(Set dst (SubI src1 src2));
 8210   effect(KILL cr);
 8211   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8212 
 8213   format %{ "esubl    $dst, $src1, $src2\t# int ndd" %}
 8214   ins_encode %{
 8215     __ esubl($dst$$Register, $src1$$Register, $src2$$constant, false);
 8216   %}
 8217   ins_pipe(ialu_reg_reg);
 8218 %}
 8219 
 8220 instruct subI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
 8221 %{
 8222   predicate(UseAPX);
 8223   match(Set dst (SubI (LoadI src1) src2));
 8224   effect(KILL cr);
 8225   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8226 
 8227   format %{ "esubl    $dst, $src1, $src2\t# int ndd" %}
 8228   ins_encode %{
 8229     __ esubl($dst$$Register, $src1$$Address, $src2$$constant, false);
 8230   %}
 8231   ins_pipe(ialu_reg_reg);
 8232 %}
 8233 
 8234 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 8235 %{
 8236   predicate(!UseAPX);
 8237   match(Set dst (SubI dst (LoadI src)));
 8238   effect(KILL cr);
 8239   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8240 
 8241   ins_cost(150);
 8242   format %{ "subl    $dst, $src\t# int" %}
 8243   ins_encode %{
 8244     __ subl($dst$$Register, $src$$Address);
 8245   %}
 8246   ins_pipe(ialu_reg_mem);
 8247 %}
 8248 
 8249 instruct subI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
 8250 %{
 8251   predicate(UseAPX);
 8252   match(Set dst (SubI src1 (LoadI src2)));
 8253   effect(KILL cr);
 8254   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8255 
 8256   ins_cost(150);
 8257   format %{ "esubl    $dst, $src1, $src2\t# int ndd" %}
 8258   ins_encode %{
 8259     __ esubl($dst$$Register, $src1$$Register, $src2$$Address, false);
 8260   %}
 8261   ins_pipe(ialu_reg_mem);
 8262 %}
 8263 
 8264 instruct subI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
 8265 %{
 8266   predicate(UseAPX);
 8267   match(Set dst (SubI (LoadI src1) src2));
 8268   effect(KILL cr);
 8269   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8270 
 8271   ins_cost(150);
 8272   format %{ "esubl    $dst, $src1, $src2\t# int ndd" %}
 8273   ins_encode %{
 8274     __ esubl($dst$$Register, $src1$$Address, $src2$$Register, false);
 8275   %}
 8276   ins_pipe(ialu_reg_mem);
 8277 %}
 8278 
 8279 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 8280 %{
 8281   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
 8282   effect(KILL cr);
 8283   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8284 
 8285   ins_cost(150);
 8286   format %{ "subl    $dst, $src\t# int" %}
 8287   ins_encode %{
 8288     __ subl($dst$$Address, $src$$Register);
 8289   %}
 8290   ins_pipe(ialu_mem_reg);
 8291 %}
 8292 
 8293 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8294 %{
 8295   predicate(!UseAPX);
 8296   match(Set dst (SubL dst src));
 8297   effect(KILL cr);
 8298   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8299 
 8300   format %{ "subq    $dst, $src\t# long" %}
 8301   ins_encode %{
 8302     __ subq($dst$$Register, $src$$Register);
 8303   %}
 8304   ins_pipe(ialu_reg_reg);
 8305 %}
 8306 
 8307 instruct subL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
 8308 %{
 8309   predicate(UseAPX);
 8310   match(Set dst (SubL src1 src2));
 8311   effect(KILL cr);
 8312   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8313 
 8314   format %{ "esubq    $dst, $src1, $src2\t# long ndd" %}
 8315   ins_encode %{
 8316     __ esubq($dst$$Register, $src1$$Register, $src2$$Register, false);
 8317   %}
 8318   ins_pipe(ialu_reg_reg);
 8319 %}
 8320 
 8321 instruct subL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
 8322 %{
 8323   predicate(UseAPX);
 8324   match(Set dst (SubL src1 src2));
 8325   effect(KILL cr);
 8326   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8327 
 8328   format %{ "esubq    $dst, $src1, $src2\t# long ndd" %}
 8329   ins_encode %{
 8330     __ esubq($dst$$Register, $src1$$Register, $src2$$constant, false);
 8331   %}
 8332   ins_pipe(ialu_reg_reg);
 8333 %}
 8334 
 8335 instruct subL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
 8336 %{
 8337   predicate(UseAPX);
 8338   match(Set dst (SubL (LoadL src1) src2));
 8339   effect(KILL cr);
 8340   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8341 
 8342   format %{ "esubq    $dst, $src1, $src2\t# long ndd" %}
 8343   ins_encode %{
 8344     __ esubq($dst$$Register, $src1$$Address, $src2$$constant, false);
 8345   %}
 8346   ins_pipe(ialu_reg_reg);
 8347 %}
 8348 
 8349 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 8350 %{
 8351   predicate(!UseAPX);
 8352   match(Set dst (SubL dst (LoadL src)));
 8353   effect(KILL cr);
 8354   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8355 
 8356   ins_cost(150);
 8357   format %{ "subq    $dst, $src\t# long" %}
 8358   ins_encode %{
 8359     __ subq($dst$$Register, $src$$Address);
 8360   %}
 8361   ins_pipe(ialu_reg_mem);
 8362 %}
 8363 
 8364 instruct subL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
 8365 %{
 8366   predicate(UseAPX);
 8367   match(Set dst (SubL src1 (LoadL src2)));
 8368   effect(KILL cr);
 8369   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8370 
 8371   ins_cost(150);
 8372   format %{ "esubq    $dst, $src1, $src2\t# long ndd" %}
 8373   ins_encode %{
 8374     __ esubq($dst$$Register, $src1$$Register, $src2$$Address, false);
 8375   %}
 8376   ins_pipe(ialu_reg_mem);
 8377 %}
 8378 
 8379 instruct subL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
 8380 %{
 8381   predicate(UseAPX);
 8382   match(Set dst (SubL (LoadL src1) src2));
 8383   effect(KILL cr);
 8384   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8385 
 8386   ins_cost(150);
 8387   format %{ "esubq    $dst, $src1, $src2\t# long ndd" %}
 8388   ins_encode %{
 8389     __ esubq($dst$$Register, $src1$$Address, $src2$$Register, false);
 8390   %}
 8391   ins_pipe(ialu_reg_mem);
 8392 %}
 8393 
 8394 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 8395 %{
 8396   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
 8397   effect(KILL cr);
 8398   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_carry_flag, PD::Flag_sets_parity_flag);
 8399 
 8400   ins_cost(150);
 8401   format %{ "subq    $dst, $src\t# long" %}
 8402   ins_encode %{
 8403     __ subq($dst$$Address, $src$$Register);
 8404   %}
 8405   ins_pipe(ialu_mem_reg);
 8406 %}
 8407 
 8408 // Subtract from a pointer
 8409 // XXX hmpf???
 8410 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
 8411 %{
 8412   match(Set dst (AddP dst (SubI zero src)));
 8413   effect(KILL cr);
 8414 
 8415   format %{ "subq    $dst, $src\t# ptr - int" %}
 8416   ins_encode %{
 8417     __ subq($dst$$Register, $src$$Register);
 8418   %}
 8419   ins_pipe(ialu_reg_reg);
 8420 %}
 8421 
 8422 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
 8423 %{
 8424   predicate(!UseAPX);
 8425   match(Set dst (SubI zero dst));
 8426   effect(KILL cr);
 8427   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8428 
 8429   format %{ "negl    $dst\t# int" %}
 8430   ins_encode %{
 8431     __ negl($dst$$Register);
 8432   %}
 8433   ins_pipe(ialu_reg);
 8434 %}
 8435 
 8436 instruct negI_rReg_ndd(rRegI dst, rRegI src, immI_0 zero, rFlagsReg cr)
 8437 %{
 8438   predicate(UseAPX);
 8439   match(Set dst (SubI zero src));
 8440   effect(KILL cr);
 8441   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8442 
 8443   format %{ "enegl    $dst, $src\t# int ndd" %}
 8444   ins_encode %{
 8445     __ enegl($dst$$Register, $src$$Register, false);
 8446   %}
 8447   ins_pipe(ialu_reg);
 8448 %}
 8449 
 8450 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
 8451 %{
 8452   predicate(!UseAPX);
 8453   match(Set dst (NegI dst));
 8454   effect(KILL cr);
 8455   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8456 
 8457   format %{ "negl    $dst\t# int" %}
 8458   ins_encode %{
 8459     __ negl($dst$$Register);
 8460   %}
 8461   ins_pipe(ialu_reg);
 8462 %}
 8463 
 8464 instruct negI_rReg_2_ndd(rRegI dst, rRegI src, rFlagsReg cr)
 8465 %{
 8466   predicate(UseAPX);
 8467   match(Set dst (NegI src));
 8468   effect(KILL cr);
 8469   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8470 
 8471   format %{ "enegl    $dst, $src\t# int ndd" %}
 8472   ins_encode %{
 8473     __ enegl($dst$$Register, $src$$Register, false);
 8474   %}
 8475   ins_pipe(ialu_reg);
 8476 %}
 8477 
 8478 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
 8479 %{
 8480   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
 8481   effect(KILL cr);
 8482   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8483 
 8484   format %{ "negl    $dst\t# int" %}
 8485   ins_encode %{
 8486     __ negl($dst$$Address);
 8487   %}
 8488   ins_pipe(ialu_reg);
 8489 %}
 8490 
 8491 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
 8492 %{
 8493   predicate(!UseAPX);
 8494   match(Set dst (SubL zero dst));
 8495   effect(KILL cr);
 8496   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8497 
 8498   format %{ "negq    $dst\t# long" %}
 8499   ins_encode %{
 8500     __ negq($dst$$Register);
 8501   %}
 8502   ins_pipe(ialu_reg);
 8503 %}
 8504 
 8505 instruct negL_rReg_ndd(rRegL dst, rRegL src, immL0 zero, rFlagsReg cr)
 8506 %{
 8507   predicate(UseAPX);
 8508   match(Set dst (SubL zero src));
 8509   effect(KILL cr);
 8510   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8511 
 8512   format %{ "enegq    $dst, $src\t# long ndd" %}
 8513   ins_encode %{
 8514     __ enegq($dst$$Register, $src$$Register, false);
 8515   %}
 8516   ins_pipe(ialu_reg);
 8517 %}
 8518 
 8519 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
 8520 %{
 8521   predicate(!UseAPX);
 8522   match(Set dst (NegL dst));
 8523   effect(KILL cr);
 8524   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8525 
 8526   format %{ "negq    $dst\t# int" %}
 8527   ins_encode %{
 8528     __ negq($dst$$Register);
 8529   %}
 8530   ins_pipe(ialu_reg);
 8531 %}
 8532 
 8533 instruct negL_rReg_2_ndd(rRegL dst, rRegL src, rFlagsReg cr)
 8534 %{
 8535   predicate(UseAPX);
 8536   match(Set dst (NegL src));
 8537   effect(KILL cr);
 8538   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8539 
 8540   format %{ "enegq    $dst, $src\t# long ndd" %}
 8541   ins_encode %{
 8542     __ enegq($dst$$Register, $src$$Register, false);
 8543   %}
 8544   ins_pipe(ialu_reg);
 8545 %}
 8546 
 8547 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
 8548 %{
 8549   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
 8550   effect(KILL cr);
 8551   flag(PD::Flag_sets_overflow_flag, PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag);
 8552 
 8553   format %{ "negq    $dst\t# long" %}
 8554   ins_encode %{
 8555     __ negq($dst$$Address);
 8556   %}
 8557   ins_pipe(ialu_reg);
 8558 %}
 8559 
 8560 //----------Multiplication/Division Instructions-------------------------------
 8561 // Integer Multiplication Instructions
 8562 // Multiply Register
 8563 
 8564 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8565 %{
 8566   predicate(!UseAPX);
 8567   match(Set dst (MulI dst src));
 8568   effect(KILL cr);
 8569 
 8570   ins_cost(300);
 8571   format %{ "imull   $dst, $src\t# int" %}
 8572   ins_encode %{
 8573     __ imull($dst$$Register, $src$$Register);
 8574   %}
 8575   ins_pipe(ialu_reg_reg_alu0);
 8576 %}
 8577 
 8578 instruct mulI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
 8579 %{
 8580   predicate(UseAPX);
 8581   match(Set dst (MulI src1 src2));
 8582   effect(KILL cr);
 8583 
 8584   ins_cost(300);
 8585   format %{ "eimull   $dst, $src1, $src2\t# int ndd" %}
 8586   ins_encode %{
 8587     __ eimull($dst$$Register, $src1$$Register, $src2$$Register, false);
 8588   %}
 8589   ins_pipe(ialu_reg_reg_alu0);
 8590 %}
 8591 
 8592 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
 8593 %{
 8594   predicate(!UseAPX);
 8595   match(Set dst (MulI src imm));
 8596   effect(KILL cr);
 8597 
 8598   ins_cost(300);
 8599   format %{ "imull   $dst, $src, $imm\t# int" %}
 8600   ins_encode %{
 8601     __ imull($dst$$Register, $src$$Register, $imm$$constant);
 8602   %}
 8603   ins_pipe(ialu_reg_reg_alu0);
 8604 %}
 8605 
 8606 instruct mulI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
 8607 %{
 8608   predicate(UseAPX);
 8609   match(Set dst (MulI src1 src2));
 8610   effect(KILL cr);
 8611 
 8612   ins_cost(300);
 8613   format %{ "eimull   $dst, $src1, $src2\t# int ndd" %}
 8614   ins_encode %{
 8615     __ eimull($dst$$Register, $src1$$Register, $src2$$constant, false);
 8616   %}
 8617   ins_pipe(ialu_reg_reg_alu0);
 8618 %}
 8619 
 8620 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
 8621 %{
 8622   predicate(!UseAPX);
 8623   match(Set dst (MulI dst (LoadI src)));
 8624   effect(KILL cr);
 8625 
 8626   ins_cost(350);
 8627   format %{ "imull   $dst, $src\t# int" %}
 8628   ins_encode %{
 8629     __ imull($dst$$Register, $src$$Address);
 8630   %}
 8631   ins_pipe(ialu_reg_mem_alu0);
 8632 %}
 8633 
 8634 instruct mulI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
 8635 %{
 8636   predicate(UseAPX);
 8637   match(Set dst (MulI src1 (LoadI src2)));
 8638   effect(KILL cr);
 8639 
 8640   ins_cost(350);
 8641   format %{ "eimull   $dst, $src1, $src2\t# int ndd" %}
 8642   ins_encode %{
 8643     __ eimull($dst$$Register, $src1$$Register, $src2$$Address, false);
 8644   %}
 8645   ins_pipe(ialu_reg_mem_alu0);
 8646 %}
 8647 
 8648 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
 8649 %{
 8650   predicate(!UseAPX);
 8651   match(Set dst (MulI (LoadI src) imm));
 8652   effect(KILL cr);
 8653 
 8654   ins_cost(300);
 8655   format %{ "imull   $dst, $src, $imm\t# int" %}
 8656   ins_encode %{
 8657     __ imull($dst$$Register, $src$$Address, $imm$$constant);
 8658   %}
 8659   ins_pipe(ialu_reg_mem_alu0);
 8660 %}
 8661 
 8662 instruct mulI_rReg_mem_imm(rRegI dst, memory src1, immI src2, rFlagsReg cr)
 8663 %{
 8664   predicate(UseAPX);
 8665   match(Set dst (MulI (LoadI src1) src2));
 8666   effect(KILL cr);
 8667 
 8668   ins_cost(300);
 8669   format %{ "eimull   $dst, $src1, $src2\t# int ndd" %}
 8670   ins_encode %{
 8671     __ eimull($dst$$Register, $src1$$Address, $src2$$constant, false);
 8672   %}
 8673   ins_pipe(ialu_reg_mem_alu0);
 8674 %}
 8675 
 8676 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
 8677 %{
 8678   match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
 8679   effect(KILL cr, KILL src2);
 8680 
 8681   expand %{ mulI_rReg(dst, src1, cr);
 8682            mulI_rReg(src2, src3, cr);
 8683            addI_rReg(dst, src2, cr); %}
 8684 %}
 8685 
 8686 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8687 %{
 8688   predicate(!UseAPX);
 8689   match(Set dst (MulL dst src));
 8690   effect(KILL cr);
 8691 
 8692   ins_cost(300);
 8693   format %{ "imulq   $dst, $src\t# long" %}
 8694   ins_encode %{
 8695     __ imulq($dst$$Register, $src$$Register);
 8696   %}
 8697   ins_pipe(ialu_reg_reg_alu0);
 8698 %}
 8699 
 8700 instruct mulL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
 8701 %{
 8702   predicate(UseAPX);
 8703   match(Set dst (MulL src1 src2));
 8704   effect(KILL cr);
 8705 
 8706   ins_cost(300);
 8707   format %{ "eimulq   $dst, $src1, $src2\t# long ndd" %}
 8708   ins_encode %{
 8709     __ eimulq($dst$$Register, $src1$$Register, $src2$$Register, false);
 8710   %}
 8711   ins_pipe(ialu_reg_reg_alu0);
 8712 %}
 8713 
 8714 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
 8715 %{
 8716   predicate(!UseAPX);
 8717   match(Set dst (MulL src imm));
 8718   effect(KILL cr);
 8719 
 8720   ins_cost(300);
 8721   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8722   ins_encode %{
 8723     __ imulq($dst$$Register, $src$$Register, $imm$$constant);
 8724   %}
 8725   ins_pipe(ialu_reg_reg_alu0);
 8726 %}
 8727 
 8728 instruct mulL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
 8729 %{
 8730   predicate(UseAPX);
 8731   match(Set dst (MulL src1 src2));
 8732   effect(KILL cr);
 8733 
 8734   ins_cost(300);
 8735   format %{ "eimulq   $dst, $src1, $src2\t# long ndd" %}
 8736   ins_encode %{
 8737     __ eimulq($dst$$Register, $src1$$Register, $src2$$constant, false);
 8738   %}
 8739   ins_pipe(ialu_reg_reg_alu0);
 8740 %}
 8741 
 8742 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
 8743 %{
 8744   predicate(!UseAPX);
 8745   match(Set dst (MulL dst (LoadL src)));
 8746   effect(KILL cr);
 8747 
 8748   ins_cost(350);
 8749   format %{ "imulq   $dst, $src\t# long" %}
 8750   ins_encode %{
 8751     __ imulq($dst$$Register, $src$$Address);
 8752   %}
 8753   ins_pipe(ialu_reg_mem_alu0);
 8754 %}
 8755 
 8756 instruct mulL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
 8757 %{
 8758   predicate(UseAPX);
 8759   match(Set dst (MulL src1 (LoadL src2)));
 8760   effect(KILL cr);
 8761 
 8762   ins_cost(350);
 8763   format %{ "eimulq   $dst, $src1, $src2 \t# long" %}
 8764   ins_encode %{
 8765     __ eimulq($dst$$Register, $src1$$Register, $src2$$Address, false);
 8766   %}
 8767   ins_pipe(ialu_reg_mem_alu0);
 8768 %}
 8769 
 8770 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
 8771 %{
 8772   predicate(!UseAPX);
 8773   match(Set dst (MulL (LoadL src) imm));
 8774   effect(KILL cr);
 8775 
 8776   ins_cost(300);
 8777   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8778   ins_encode %{
 8779     __ imulq($dst$$Register, $src$$Address, $imm$$constant);
 8780   %}
 8781   ins_pipe(ialu_reg_mem_alu0);
 8782 %}
 8783 
 8784 instruct mulL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
 8785 %{
 8786   predicate(UseAPX);
 8787   match(Set dst (MulL (LoadL src1) src2));
 8788   effect(KILL cr);
 8789 
 8790   ins_cost(300);
 8791   format %{ "eimulq   $dst, $src1, $src2\t# long ndd" %}
 8792   ins_encode %{
 8793     __ eimulq($dst$$Register, $src1$$Address, $src2$$constant, false);
 8794   %}
 8795   ins_pipe(ialu_reg_mem_alu0);
 8796 %}
 8797 
 8798 instruct mulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
 8799 %{
 8800   match(Set dst (MulHiL src rax));
 8801   effect(USE_KILL rax, KILL cr);
 8802 
 8803   ins_cost(300);
 8804   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
 8805   ins_encode %{
 8806     __ imulq($src$$Register);
 8807   %}
 8808   ins_pipe(ialu_reg_reg_alu0);
 8809 %}
 8810 
 8811 instruct umulHiL_rReg(rdx_RegL dst, rRegL src, rax_RegL rax, rFlagsReg cr)
 8812 %{
 8813   match(Set dst (UMulHiL src rax));
 8814   effect(USE_KILL rax, KILL cr);
 8815 
 8816   ins_cost(300);
 8817   format %{ "mulq   RDX:RAX, RAX, $src\t# umulhi" %}
 8818   ins_encode %{
 8819     __ mulq($src$$Register);
 8820   %}
 8821   ins_pipe(ialu_reg_reg_alu0);
 8822 %}
 8823 
 8824 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8825                    rFlagsReg cr)
 8826 %{
 8827   match(Set rax (DivI rax div));
 8828   effect(KILL rdx, KILL cr);
 8829 
 8830   ins_cost(30*100+10*100); // XXX
 8831   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8832             "jne,s   normal\n\t"
 8833             "xorl    rdx, rdx\n\t"
 8834             "cmpl    $div, -1\n\t"
 8835             "je,s    done\n"
 8836     "normal: cdql\n\t"
 8837             "idivl   $div\n"
 8838     "done:"        %}
 8839   ins_encode(cdql_enc(div));
 8840   ins_pipe(ialu_reg_reg_alu0);
 8841 %}
 8842 
 8843 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8844                    rFlagsReg cr)
 8845 %{
 8846   match(Set rax (DivL rax div));
 8847   effect(KILL rdx, KILL cr);
 8848 
 8849   ins_cost(30*100+10*100); // XXX
 8850   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8851             "cmpq    rax, rdx\n\t"
 8852             "jne,s   normal\n\t"
 8853             "xorl    rdx, rdx\n\t"
 8854             "cmpq    $div, -1\n\t"
 8855             "je,s    done\n"
 8856     "normal: cdqq\n\t"
 8857             "idivq   $div\n"
 8858     "done:"        %}
 8859   ins_encode(cdqq_enc(div));
 8860   ins_pipe(ialu_reg_reg_alu0);
 8861 %}
 8862 
 8863 instruct udivI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div, rFlagsReg cr)
 8864 %{
 8865   match(Set rax (UDivI rax div));
 8866   effect(KILL rdx, KILL cr);
 8867 
 8868   ins_cost(300);
 8869   format %{ "udivl $rax,$rax,$div\t# UDivI\n" %}
 8870   ins_encode %{
 8871     __ udivI($rax$$Register, $div$$Register, $rdx$$Register);
 8872   %}
 8873   ins_pipe(ialu_reg_reg_alu0);
 8874 %}
 8875 
 8876 instruct udivL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div, rFlagsReg cr)
 8877 %{
 8878   match(Set rax (UDivL rax div));
 8879   effect(KILL rdx, KILL cr);
 8880 
 8881   ins_cost(300);
 8882   format %{ "udivq $rax,$rax,$div\t# UDivL\n" %}
 8883   ins_encode %{
 8884      __ udivL($rax$$Register, $div$$Register, $rdx$$Register);
 8885   %}
 8886   ins_pipe(ialu_reg_reg_alu0);
 8887 %}
 8888 
 8889 // Integer DIVMOD with Register, both quotient and mod results
 8890 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8891                              rFlagsReg cr)
 8892 %{
 8893   match(DivModI rax div);
 8894   effect(KILL cr);
 8895 
 8896   ins_cost(30*100+10*100); // XXX
 8897   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8898             "jne,s   normal\n\t"
 8899             "xorl    rdx, rdx\n\t"
 8900             "cmpl    $div, -1\n\t"
 8901             "je,s    done\n"
 8902     "normal: cdql\n\t"
 8903             "idivl   $div\n"
 8904     "done:"        %}
 8905   ins_encode(cdql_enc(div));
 8906   ins_pipe(pipe_slow);
 8907 %}
 8908 
 8909 // Long DIVMOD with Register, both quotient and mod results
 8910 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8911                              rFlagsReg cr)
 8912 %{
 8913   match(DivModL rax div);
 8914   effect(KILL cr);
 8915 
 8916   ins_cost(30*100+10*100); // XXX
 8917   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8918             "cmpq    rax, rdx\n\t"
 8919             "jne,s   normal\n\t"
 8920             "xorl    rdx, rdx\n\t"
 8921             "cmpq    $div, -1\n\t"
 8922             "je,s    done\n"
 8923     "normal: cdqq\n\t"
 8924             "idivq   $div\n"
 8925     "done:"        %}
 8926   ins_encode(cdqq_enc(div));
 8927   ins_pipe(pipe_slow);
 8928 %}
 8929 
 8930 // Unsigned integer DIVMOD with Register, both quotient and mod results
 8931 instruct udivModI_rReg_divmod(rax_RegI rax, no_rax_rdx_RegI tmp, rdx_RegI rdx,
 8932                               no_rax_rdx_RegI div, rFlagsReg cr)
 8933 %{
 8934   match(UDivModI rax div);
 8935   effect(TEMP tmp, KILL cr);
 8936 
 8937   ins_cost(300);
 8938   format %{ "udivl $rax,$rax,$div\t# begin UDivModI\n\t"
 8939             "umodl $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModI\n"
 8940           %}
 8941   ins_encode %{
 8942     __ udivmodI($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
 8943   %}
 8944   ins_pipe(pipe_slow);
 8945 %}
 8946 
 8947 // Unsigned long DIVMOD with Register, both quotient and mod results
 8948 instruct udivModL_rReg_divmod(rax_RegL rax, no_rax_rdx_RegL tmp, rdx_RegL rdx,
 8949                               no_rax_rdx_RegL div, rFlagsReg cr)
 8950 %{
 8951   match(UDivModL rax div);
 8952   effect(TEMP tmp, KILL cr);
 8953 
 8954   ins_cost(300);
 8955   format %{ "udivq $rax,$rax,$div\t# begin UDivModL\n\t"
 8956             "umodq $rdx,$rax,$div\t! using $tmp as TEMP # end UDivModL\n"
 8957           %}
 8958   ins_encode %{
 8959     __ udivmodL($rax$$Register, $div$$Register, $rdx$$Register, $tmp$$Register);
 8960   %}
 8961   ins_pipe(pipe_slow);
 8962 %}
 8963 
 8964 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
 8965                    rFlagsReg cr)
 8966 %{
 8967   match(Set rdx (ModI rax div));
 8968   effect(KILL rax, KILL cr);
 8969 
 8970   ins_cost(300); // XXX
 8971   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
 8972             "jne,s   normal\n\t"
 8973             "xorl    rdx, rdx\n\t"
 8974             "cmpl    $div, -1\n\t"
 8975             "je,s    done\n"
 8976     "normal: cdql\n\t"
 8977             "idivl   $div\n"
 8978     "done:"        %}
 8979   ins_encode(cdql_enc(div));
 8980   ins_pipe(ialu_reg_reg_alu0);
 8981 %}
 8982 
 8983 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
 8984                    rFlagsReg cr)
 8985 %{
 8986   match(Set rdx (ModL rax div));
 8987   effect(KILL rax, KILL cr);
 8988 
 8989   ins_cost(300); // XXX
 8990   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
 8991             "cmpq    rax, rdx\n\t"
 8992             "jne,s   normal\n\t"
 8993             "xorl    rdx, rdx\n\t"
 8994             "cmpq    $div, -1\n\t"
 8995             "je,s    done\n"
 8996     "normal: cdqq\n\t"
 8997             "idivq   $div\n"
 8998     "done:"        %}
 8999   ins_encode(cdqq_enc(div));
 9000   ins_pipe(ialu_reg_reg_alu0);
 9001 %}
 9002 
 9003 instruct umodI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div, rFlagsReg cr)
 9004 %{
 9005   match(Set rdx (UModI rax div));
 9006   effect(KILL rax, KILL cr);
 9007 
 9008   ins_cost(300);
 9009   format %{ "umodl $rdx,$rax,$div\t# UModI\n" %}
 9010   ins_encode %{
 9011     __ umodI($rax$$Register, $div$$Register, $rdx$$Register);
 9012   %}
 9013   ins_pipe(ialu_reg_reg_alu0);
 9014 %}
 9015 
 9016 instruct umodL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div, rFlagsReg cr)
 9017 %{
 9018   match(Set rdx (UModL rax div));
 9019   effect(KILL rax, KILL cr);
 9020 
 9021   ins_cost(300);
 9022   format %{ "umodq $rdx,$rax,$div\t# UModL\n" %}
 9023   ins_encode %{
 9024     __ umodL($rax$$Register, $div$$Register, $rdx$$Register);
 9025   %}
 9026   ins_pipe(ialu_reg_reg_alu0);
 9027 %}
 9028 
 9029 // Integer Shift Instructions
 9030 // Shift Left by one, two, three
 9031 instruct salI_rReg_immI2(rRegI dst, immI2 shift, rFlagsReg cr)
 9032 %{
 9033   predicate(!UseAPX);
 9034   match(Set dst (LShiftI dst shift));
 9035   effect(KILL cr);
 9036 
 9037   format %{ "sall    $dst, $shift" %}
 9038   ins_encode %{
 9039     __ sall($dst$$Register, $shift$$constant);
 9040   %}
 9041   ins_pipe(ialu_reg);
 9042 %}
 9043 
 9044 // Shift Left by one, two, three
 9045 instruct salI_rReg_immI2_ndd(rRegI dst, rRegI src, immI2 shift, rFlagsReg cr)
 9046 %{
 9047   predicate(UseAPX);
 9048   match(Set dst (LShiftI src shift));
 9049   effect(KILL cr);
 9050 
 9051   format %{ "esall    $dst, $src, $shift\t# int(ndd)" %}
 9052   ins_encode %{
 9053     __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
 9054   %}
 9055   ins_pipe(ialu_reg);
 9056 %}
 9057 
 9058 // Shift Left by 8-bit immediate
 9059 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 9060 %{
 9061   predicate(!UseAPX);
 9062   match(Set dst (LShiftI dst shift));
 9063   effect(KILL cr);
 9064 
 9065   format %{ "sall    $dst, $shift" %}
 9066   ins_encode %{
 9067     __ sall($dst$$Register, $shift$$constant);
 9068   %}
 9069   ins_pipe(ialu_reg);
 9070 %}
 9071 
 9072 // Shift Left by 8-bit immediate
 9073 instruct salI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
 9074 %{
 9075   predicate(UseAPX);
 9076   match(Set dst (LShiftI src shift));
 9077   effect(KILL cr);
 9078 
 9079   format %{ "esall    $dst, $src, $shift\t# int (ndd)" %}
 9080   ins_encode %{
 9081     __ esall($dst$$Register, $src$$Register, $shift$$constant, false);
 9082   %}
 9083   ins_pipe(ialu_reg);
 9084 %}
 9085 
 9086 instruct salI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
 9087 %{
 9088   predicate(UseAPX);
 9089   match(Set dst (LShiftI (LoadI src) shift));
 9090   effect(KILL cr);
 9091 
 9092   format %{ "esall    $dst, $src, $shift\t# int (ndd)" %}
 9093   ins_encode %{
 9094     __ esall($dst$$Register, $src$$Address, $shift$$constant, false);
 9095   %}
 9096   ins_pipe(ialu_reg);
 9097 %}
 9098 
 9099 // Shift Left by 8-bit immediate
 9100 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9101 %{
 9102   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 9103   effect(KILL cr);
 9104 
 9105   format %{ "sall    $dst, $shift" %}
 9106   ins_encode %{
 9107     __ sall($dst$$Address, $shift$$constant);
 9108   %}
 9109   ins_pipe(ialu_mem_imm);
 9110 %}
 9111 
 9112 // Shift Left by variable
 9113 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9114 %{
 9115   predicate(!VM_Version::supports_bmi2());
 9116   match(Set dst (LShiftI dst shift));
 9117   effect(KILL cr);
 9118 
 9119   format %{ "sall    $dst, $shift" %}
 9120   ins_encode %{
 9121     __ sall($dst$$Register);
 9122   %}
 9123   ins_pipe(ialu_reg_reg);
 9124 %}
 9125 
 9126 // Shift Left by variable
 9127 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9128 %{
 9129   predicate(!VM_Version::supports_bmi2());
 9130   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 9131   effect(KILL cr);
 9132 
 9133   format %{ "sall    $dst, $shift" %}
 9134   ins_encode %{
 9135     __ sall($dst$$Address);
 9136   %}
 9137   ins_pipe(ialu_mem_reg);
 9138 %}
 9139 
 9140 instruct salI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
 9141 %{
 9142   predicate(VM_Version::supports_bmi2());
 9143   match(Set dst (LShiftI src shift));
 9144 
 9145   format %{ "shlxl   $dst, $src, $shift" %}
 9146   ins_encode %{
 9147     __ shlxl($dst$$Register, $src$$Register, $shift$$Register);
 9148   %}
 9149   ins_pipe(ialu_reg_reg);
 9150 %}
 9151 
 9152 instruct salI_mem_rReg(rRegI dst, memory src, rRegI shift)
 9153 %{
 9154   predicate(VM_Version::supports_bmi2());
 9155   match(Set dst (LShiftI (LoadI src) shift));
 9156   ins_cost(175);
 9157   format %{ "shlxl   $dst, $src, $shift" %}
 9158   ins_encode %{
 9159     __ shlxl($dst$$Register, $src$$Address, $shift$$Register);
 9160   %}
 9161   ins_pipe(ialu_reg_mem);
 9162 %}
 9163 
 9164 // Arithmetic Shift Right by 8-bit immediate
 9165 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 9166 %{
 9167   predicate(!UseAPX);
 9168   match(Set dst (RShiftI dst shift));
 9169   effect(KILL cr);
 9170 
 9171   format %{ "sarl    $dst, $shift" %}
 9172   ins_encode %{
 9173     __ sarl($dst$$Register, $shift$$constant);
 9174   %}
 9175   ins_pipe(ialu_mem_imm);
 9176 %}
 9177 
 9178 // Arithmetic Shift Right by 8-bit immediate
 9179 instruct sarI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
 9180 %{
 9181   predicate(UseAPX);
 9182   match(Set dst (RShiftI src shift));
 9183   effect(KILL cr);
 9184 
 9185   format %{ "esarl    $dst, $src, $shift\t# int (ndd)" %}
 9186   ins_encode %{
 9187     __ esarl($dst$$Register, $src$$Register, $shift$$constant, false);
 9188   %}
 9189   ins_pipe(ialu_mem_imm);
 9190 %}
 9191 
 9192 instruct sarI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
 9193 %{
 9194   predicate(UseAPX);
 9195   match(Set dst (RShiftI (LoadI src) shift));
 9196   effect(KILL cr);
 9197 
 9198   format %{ "esarl    $dst, $src, $shift\t# int (ndd)" %}
 9199   ins_encode %{
 9200     __ esarl($dst$$Register, $src$$Address, $shift$$constant, false);
 9201   %}
 9202   ins_pipe(ialu_mem_imm);
 9203 %}
 9204 
 9205 // Arithmetic Shift Right by 8-bit immediate
 9206 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9207 %{
 9208   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 9209   effect(KILL cr);
 9210 
 9211   format %{ "sarl    $dst, $shift" %}
 9212   ins_encode %{
 9213     __ sarl($dst$$Address, $shift$$constant);
 9214   %}
 9215   ins_pipe(ialu_mem_imm);
 9216 %}
 9217 
 9218 // Arithmetic Shift Right by variable
 9219 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9220 %{
 9221   predicate(!VM_Version::supports_bmi2());
 9222   match(Set dst (RShiftI dst shift));
 9223   effect(KILL cr);
 9224 
 9225   format %{ "sarl    $dst, $shift" %}
 9226   ins_encode %{
 9227     __ sarl($dst$$Register);
 9228   %}
 9229   ins_pipe(ialu_reg_reg);
 9230 %}
 9231 
 9232 // Arithmetic Shift Right by variable
 9233 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9234 %{
 9235   predicate(!VM_Version::supports_bmi2());
 9236   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 9237   effect(KILL cr);
 9238 
 9239   format %{ "sarl    $dst, $shift" %}
 9240   ins_encode %{
 9241     __ sarl($dst$$Address);
 9242   %}
 9243   ins_pipe(ialu_mem_reg);
 9244 %}
 9245 
 9246 instruct sarI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
 9247 %{
 9248   predicate(VM_Version::supports_bmi2());
 9249   match(Set dst (RShiftI src shift));
 9250 
 9251   format %{ "sarxl   $dst, $src, $shift" %}
 9252   ins_encode %{
 9253     __ sarxl($dst$$Register, $src$$Register, $shift$$Register);
 9254   %}
 9255   ins_pipe(ialu_reg_reg);
 9256 %}
 9257 
 9258 instruct sarI_mem_rReg(rRegI dst, memory src, rRegI shift)
 9259 %{
 9260   predicate(VM_Version::supports_bmi2());
 9261   match(Set dst (RShiftI (LoadI src) shift));
 9262   ins_cost(175);
 9263   format %{ "sarxl   $dst, $src, $shift" %}
 9264   ins_encode %{
 9265     __ sarxl($dst$$Register, $src$$Address, $shift$$Register);
 9266   %}
 9267   ins_pipe(ialu_reg_mem);
 9268 %}
 9269 
 9270 // Logical Shift Right by 8-bit immediate
 9271 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 9272 %{
 9273   predicate(!UseAPX);
 9274   match(Set dst (URShiftI dst shift));
 9275   effect(KILL cr);
 9276 
 9277   format %{ "shrl    $dst, $shift" %}
 9278   ins_encode %{
 9279     __ shrl($dst$$Register, $shift$$constant);
 9280   %}
 9281   ins_pipe(ialu_reg);
 9282 %}
 9283 
 9284 // Logical Shift Right by 8-bit immediate
 9285 instruct shrI_rReg_imm_ndd(rRegI dst, rRegI src, immI8 shift, rFlagsReg cr)
 9286 %{
 9287   predicate(UseAPX);
 9288   match(Set dst (URShiftI src shift));
 9289   effect(KILL cr);
 9290 
 9291   format %{ "eshrl    $dst, $src, $shift\t # int (ndd)" %}
 9292   ins_encode %{
 9293     __ eshrl($dst$$Register, $src$$Register, $shift$$constant, false);
 9294   %}
 9295   ins_pipe(ialu_reg);
 9296 %}
 9297 
 9298 instruct shrI_rReg_mem_imm_ndd(rRegI dst, memory src, immI8 shift, rFlagsReg cr)
 9299 %{
 9300   predicate(UseAPX);
 9301   match(Set dst (URShiftI (LoadI src) shift));
 9302   effect(KILL cr);
 9303 
 9304   format %{ "eshrl    $dst, $src, $shift\t # int (ndd)" %}
 9305   ins_encode %{
 9306     __ eshrl($dst$$Register, $src$$Address, $shift$$constant, false);
 9307   %}
 9308   ins_pipe(ialu_reg);
 9309 %}
 9310 
 9311 // Logical Shift Right by 8-bit immediate
 9312 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9313 %{
 9314   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 9315   effect(KILL cr);
 9316 
 9317   format %{ "shrl    $dst, $shift" %}
 9318   ins_encode %{
 9319     __ shrl($dst$$Address, $shift$$constant);
 9320   %}
 9321   ins_pipe(ialu_mem_imm);
 9322 %}
 9323 
 9324 // Logical Shift Right by variable
 9325 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9326 %{
 9327   predicate(!VM_Version::supports_bmi2());
 9328   match(Set dst (URShiftI dst shift));
 9329   effect(KILL cr);
 9330 
 9331   format %{ "shrl    $dst, $shift" %}
 9332   ins_encode %{
 9333     __ shrl($dst$$Register);
 9334   %}
 9335   ins_pipe(ialu_reg_reg);
 9336 %}
 9337 
 9338 // Logical Shift Right by variable
 9339 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9340 %{
 9341   predicate(!VM_Version::supports_bmi2());
 9342   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 9343   effect(KILL cr);
 9344 
 9345   format %{ "shrl    $dst, $shift" %}
 9346   ins_encode %{
 9347     __ shrl($dst$$Address);
 9348   %}
 9349   ins_pipe(ialu_mem_reg);
 9350 %}
 9351 
 9352 instruct shrI_rReg_rReg(rRegI dst, rRegI src, rRegI shift)
 9353 %{
 9354   predicate(VM_Version::supports_bmi2());
 9355   match(Set dst (URShiftI src shift));
 9356 
 9357   format %{ "shrxl   $dst, $src, $shift" %}
 9358   ins_encode %{
 9359     __ shrxl($dst$$Register, $src$$Register, $shift$$Register);
 9360   %}
 9361   ins_pipe(ialu_reg_reg);
 9362 %}
 9363 
 9364 instruct shrI_mem_rReg(rRegI dst, memory src, rRegI shift)
 9365 %{
 9366   predicate(VM_Version::supports_bmi2());
 9367   match(Set dst (URShiftI (LoadI src) shift));
 9368   ins_cost(175);
 9369   format %{ "shrxl   $dst, $src, $shift" %}
 9370   ins_encode %{
 9371     __ shrxl($dst$$Register, $src$$Address, $shift$$Register);
 9372   %}
 9373   ins_pipe(ialu_reg_mem);
 9374 %}
 9375 
 9376 // Long Shift Instructions
 9377 // Shift Left by one, two, three
 9378 instruct salL_rReg_immI2(rRegL dst, immI2 shift, rFlagsReg cr)
 9379 %{
 9380   predicate(!UseAPX);
 9381   match(Set dst (LShiftL dst shift));
 9382   effect(KILL cr);
 9383 
 9384   format %{ "salq    $dst, $shift" %}
 9385   ins_encode %{
 9386     __ salq($dst$$Register, $shift$$constant);
 9387   %}
 9388   ins_pipe(ialu_reg);
 9389 %}
 9390 
 9391 // Shift Left by one, two, three
 9392 instruct salL_rReg_immI2_ndd(rRegL dst, rRegL src, immI2 shift, rFlagsReg cr)
 9393 %{
 9394   predicate(UseAPX);
 9395   match(Set dst (LShiftL src shift));
 9396   effect(KILL cr);
 9397 
 9398   format %{ "esalq    $dst, $src, $shift\t# long (ndd)" %}
 9399   ins_encode %{
 9400     __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
 9401   %}
 9402   ins_pipe(ialu_reg);
 9403 %}
 9404 
 9405 // Shift Left by 8-bit immediate
 9406 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9407 %{
 9408   predicate(!UseAPX);
 9409   match(Set dst (LShiftL dst shift));
 9410   effect(KILL cr);
 9411 
 9412   format %{ "salq    $dst, $shift" %}
 9413   ins_encode %{
 9414     __ salq($dst$$Register, $shift$$constant);
 9415   %}
 9416   ins_pipe(ialu_reg);
 9417 %}
 9418 
 9419 // Shift Left by 8-bit immediate
 9420 instruct salL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
 9421 %{
 9422   predicate(UseAPX);
 9423   match(Set dst (LShiftL src shift));
 9424   effect(KILL cr);
 9425 
 9426   format %{ "esalq    $dst, $src, $shift\t# long (ndd)" %}
 9427   ins_encode %{
 9428     __ esalq($dst$$Register, $src$$Register, $shift$$constant, false);
 9429   %}
 9430   ins_pipe(ialu_reg);
 9431 %}
 9432 
 9433 instruct salL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
 9434 %{
 9435   predicate(UseAPX);
 9436   match(Set dst (LShiftL (LoadL src) shift));
 9437   effect(KILL cr);
 9438 
 9439   format %{ "esalq    $dst, $src, $shift\t# long (ndd)" %}
 9440   ins_encode %{
 9441     __ esalq($dst$$Register, $src$$Address, $shift$$constant, false);
 9442   %}
 9443   ins_pipe(ialu_reg);
 9444 %}
 9445 
 9446 // Shift Left by 8-bit immediate
 9447 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9448 %{
 9449   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 9450   effect(KILL cr);
 9451 
 9452   format %{ "salq    $dst, $shift" %}
 9453   ins_encode %{
 9454     __ salq($dst$$Address, $shift$$constant);
 9455   %}
 9456   ins_pipe(ialu_mem_imm);
 9457 %}
 9458 
 9459 // Shift Left by variable
 9460 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9461 %{
 9462   predicate(!VM_Version::supports_bmi2());
 9463   match(Set dst (LShiftL dst shift));
 9464   effect(KILL cr);
 9465 
 9466   format %{ "salq    $dst, $shift" %}
 9467   ins_encode %{
 9468     __ salq($dst$$Register);
 9469   %}
 9470   ins_pipe(ialu_reg_reg);
 9471 %}
 9472 
 9473 // Shift Left by variable
 9474 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9475 %{
 9476   predicate(!VM_Version::supports_bmi2());
 9477   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 9478   effect(KILL cr);
 9479 
 9480   format %{ "salq    $dst, $shift" %}
 9481   ins_encode %{
 9482     __ salq($dst$$Address);
 9483   %}
 9484   ins_pipe(ialu_mem_reg);
 9485 %}
 9486 
 9487 instruct salL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
 9488 %{
 9489   predicate(VM_Version::supports_bmi2());
 9490   match(Set dst (LShiftL src shift));
 9491 
 9492   format %{ "shlxq   $dst, $src, $shift" %}
 9493   ins_encode %{
 9494     __ shlxq($dst$$Register, $src$$Register, $shift$$Register);
 9495   %}
 9496   ins_pipe(ialu_reg_reg);
 9497 %}
 9498 
 9499 instruct salL_mem_rReg(rRegL dst, memory src, rRegI shift)
 9500 %{
 9501   predicate(VM_Version::supports_bmi2());
 9502   match(Set dst (LShiftL (LoadL src) shift));
 9503   ins_cost(175);
 9504   format %{ "shlxq   $dst, $src, $shift" %}
 9505   ins_encode %{
 9506     __ shlxq($dst$$Register, $src$$Address, $shift$$Register);
 9507   %}
 9508   ins_pipe(ialu_reg_mem);
 9509 %}
 9510 
 9511 // Arithmetic Shift Right by 8-bit immediate
 9512 instruct sarL_rReg_imm(rRegL dst, immI shift, rFlagsReg cr)
 9513 %{
 9514   predicate(!UseAPX);
 9515   match(Set dst (RShiftL dst shift));
 9516   effect(KILL cr);
 9517 
 9518   format %{ "sarq    $dst, $shift" %}
 9519   ins_encode %{
 9520     __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
 9521   %}
 9522   ins_pipe(ialu_mem_imm);
 9523 %}
 9524 
 9525 // Arithmetic Shift Right by 8-bit immediate
 9526 instruct sarL_rReg_imm_ndd(rRegL dst, rRegL src, immI shift, rFlagsReg cr)
 9527 %{
 9528   predicate(UseAPX);
 9529   match(Set dst (RShiftL src shift));
 9530   effect(KILL cr);
 9531 
 9532   format %{ "esarq    $dst, $src, $shift\t# long (ndd)" %}
 9533   ins_encode %{
 9534     __ esarq($dst$$Register, $src$$Register, (unsigned char)($shift$$constant & 0x3F), false);
 9535   %}
 9536   ins_pipe(ialu_mem_imm);
 9537 %}
 9538 
 9539 instruct sarL_rReg_mem_imm_ndd(rRegL dst, memory src, immI shift, rFlagsReg cr)
 9540 %{
 9541   predicate(UseAPX);
 9542   match(Set dst (RShiftL (LoadL src) shift));
 9543   effect(KILL cr);
 9544 
 9545   format %{ "esarq    $dst, $src, $shift\t# long (ndd)" %}
 9546   ins_encode %{
 9547     __ esarq($dst$$Register, $src$$Address, (unsigned char)($shift$$constant & 0x3F), false);
 9548   %}
 9549   ins_pipe(ialu_mem_imm);
 9550 %}
 9551 
 9552 // Arithmetic Shift Right by 8-bit immediate
 9553 instruct sarL_mem_imm(memory dst, immI shift, rFlagsReg cr)
 9554 %{
 9555   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9556   effect(KILL cr);
 9557 
 9558   format %{ "sarq    $dst, $shift" %}
 9559   ins_encode %{
 9560     __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
 9561   %}
 9562   ins_pipe(ialu_mem_imm);
 9563 %}
 9564 
 9565 // Arithmetic Shift Right by variable
 9566 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9567 %{
 9568   predicate(!VM_Version::supports_bmi2());
 9569   match(Set dst (RShiftL dst shift));
 9570   effect(KILL cr);
 9571 
 9572   format %{ "sarq    $dst, $shift" %}
 9573   ins_encode %{
 9574     __ sarq($dst$$Register);
 9575   %}
 9576   ins_pipe(ialu_reg_reg);
 9577 %}
 9578 
 9579 // Arithmetic Shift Right by variable
 9580 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9581 %{
 9582   predicate(!VM_Version::supports_bmi2());
 9583   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9584   effect(KILL cr);
 9585 
 9586   format %{ "sarq    $dst, $shift" %}
 9587   ins_encode %{
 9588     __ sarq($dst$$Address);
 9589   %}
 9590   ins_pipe(ialu_mem_reg);
 9591 %}
 9592 
 9593 instruct sarL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
 9594 %{
 9595   predicate(VM_Version::supports_bmi2());
 9596   match(Set dst (RShiftL src shift));
 9597 
 9598   format %{ "sarxq   $dst, $src, $shift" %}
 9599   ins_encode %{
 9600     __ sarxq($dst$$Register, $src$$Register, $shift$$Register);
 9601   %}
 9602   ins_pipe(ialu_reg_reg);
 9603 %}
 9604 
 9605 instruct sarL_mem_rReg(rRegL dst, memory src, rRegI shift)
 9606 %{
 9607   predicate(VM_Version::supports_bmi2());
 9608   match(Set dst (RShiftL (LoadL src) shift));
 9609   ins_cost(175);
 9610   format %{ "sarxq   $dst, $src, $shift" %}
 9611   ins_encode %{
 9612     __ sarxq($dst$$Register, $src$$Address, $shift$$Register);
 9613   %}
 9614   ins_pipe(ialu_reg_mem);
 9615 %}
 9616 
 9617 // Logical Shift Right by 8-bit immediate
 9618 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9619 %{
 9620   predicate(!UseAPX);
 9621   match(Set dst (URShiftL dst shift));
 9622   effect(KILL cr);
 9623 
 9624   format %{ "shrq    $dst, $shift" %}
 9625   ins_encode %{
 9626     __ shrq($dst$$Register, $shift$$constant);
 9627   %}
 9628   ins_pipe(ialu_reg);
 9629 %}
 9630 
 9631 // Logical Shift Right by 8-bit immediate
 9632 instruct shrL_rReg_imm_ndd(rRegL dst, rRegL src, immI8 shift, rFlagsReg cr)
 9633 %{
 9634   predicate(UseAPX);
 9635   match(Set dst (URShiftL src shift));
 9636   effect(KILL cr);
 9637 
 9638   format %{ "eshrq    $dst, $src, $shift\t# long (ndd)" %}
 9639   ins_encode %{
 9640     __ eshrq($dst$$Register, $src$$Register, $shift$$constant, false);
 9641   %}
 9642   ins_pipe(ialu_reg);
 9643 %}
 9644 
 9645 instruct shrL_rReg_mem_imm_ndd(rRegL dst, memory src, immI8 shift, rFlagsReg cr)
 9646 %{
 9647   predicate(UseAPX);
 9648   match(Set dst (URShiftL (LoadL src) shift));
 9649   effect(KILL cr);
 9650 
 9651   format %{ "eshrq    $dst, $src, $shift\t# long (ndd)" %}
 9652   ins_encode %{
 9653     __ eshrq($dst$$Register, $src$$Address, $shift$$constant, false);
 9654   %}
 9655   ins_pipe(ialu_reg);
 9656 %}
 9657 
 9658 // Logical Shift Right by 8-bit immediate
 9659 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9660 %{
 9661   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9662   effect(KILL cr);
 9663 
 9664   format %{ "shrq    $dst, $shift" %}
 9665   ins_encode %{
 9666     __ shrq($dst$$Address, $shift$$constant);
 9667   %}
 9668   ins_pipe(ialu_mem_imm);
 9669 %}
 9670 
 9671 // Logical Shift Right by variable
 9672 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9673 %{
 9674   predicate(!VM_Version::supports_bmi2());
 9675   match(Set dst (URShiftL dst shift));
 9676   effect(KILL cr);
 9677 
 9678   format %{ "shrq    $dst, $shift" %}
 9679   ins_encode %{
 9680     __ shrq($dst$$Register);
 9681   %}
 9682   ins_pipe(ialu_reg_reg);
 9683 %}
 9684 
 9685 // Logical Shift Right by variable
 9686 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9687 %{
 9688   predicate(!VM_Version::supports_bmi2());
 9689   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9690   effect(KILL cr);
 9691 
 9692   format %{ "shrq    $dst, $shift" %}
 9693   ins_encode %{
 9694     __ shrq($dst$$Address);
 9695   %}
 9696   ins_pipe(ialu_mem_reg);
 9697 %}
 9698 
 9699 instruct shrL_rReg_rReg(rRegL dst, rRegL src, rRegI shift)
 9700 %{
 9701   predicate(VM_Version::supports_bmi2());
 9702   match(Set dst (URShiftL src shift));
 9703 
 9704   format %{ "shrxq   $dst, $src, $shift" %}
 9705   ins_encode %{
 9706     __ shrxq($dst$$Register, $src$$Register, $shift$$Register);
 9707   %}
 9708   ins_pipe(ialu_reg_reg);
 9709 %}
 9710 
 9711 instruct shrL_mem_rReg(rRegL dst, memory src, rRegI shift)
 9712 %{
 9713   predicate(VM_Version::supports_bmi2());
 9714   match(Set dst (URShiftL (LoadL src) shift));
 9715   ins_cost(175);
 9716   format %{ "shrxq   $dst, $src, $shift" %}
 9717   ins_encode %{
 9718     __ shrxq($dst$$Register, $src$$Address, $shift$$Register);
 9719   %}
 9720   ins_pipe(ialu_reg_mem);
 9721 %}
 9722 
 9723 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
 9724 // This idiom is used by the compiler for the i2b bytecode.
 9725 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
 9726 %{
 9727   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
 9728 
 9729   format %{ "movsbl  $dst, $src\t# i2b" %}
 9730   ins_encode %{
 9731     __ movsbl($dst$$Register, $src$$Register);
 9732   %}
 9733   ins_pipe(ialu_reg_reg);
 9734 %}
 9735 
 9736 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
 9737 // This idiom is used by the compiler the i2s bytecode.
 9738 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
 9739 %{
 9740   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
 9741 
 9742   format %{ "movswl  $dst, $src\t# i2s" %}
 9743   ins_encode %{
 9744     __ movswl($dst$$Register, $src$$Register);
 9745   %}
 9746   ins_pipe(ialu_reg_reg);
 9747 %}
 9748 
 9749 // ROL/ROR instructions
 9750 
 9751 // Rotate left by constant.
 9752 instruct rolI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
 9753 %{
 9754   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9755   match(Set dst (RotateLeft dst shift));
 9756   effect(KILL cr);
 9757   format %{ "roll    $dst, $shift" %}
 9758   ins_encode %{
 9759     __ roll($dst$$Register, $shift$$constant);
 9760   %}
 9761   ins_pipe(ialu_reg);
 9762 %}
 9763 
 9764 instruct rolI_immI8(rRegI dst, rRegI src, immI8 shift)
 9765 %{
 9766   predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9767   match(Set dst (RotateLeft src shift));
 9768   format %{ "rolxl   $dst, $src, $shift" %}
 9769   ins_encode %{
 9770     int shift = 32 - ($shift$$constant & 31);
 9771     __ rorxl($dst$$Register, $src$$Register, shift);
 9772   %}
 9773   ins_pipe(ialu_reg_reg);
 9774 %}
 9775 
 9776 instruct rolI_mem_immI8(rRegI dst, memory src, immI8 shift)
 9777 %{
 9778   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9779   match(Set dst (RotateLeft (LoadI src) shift));
 9780   ins_cost(175);
 9781   format %{ "rolxl   $dst, $src, $shift" %}
 9782   ins_encode %{
 9783     int shift = 32 - ($shift$$constant & 31);
 9784     __ rorxl($dst$$Register, $src$$Address, shift);
 9785   %}
 9786   ins_pipe(ialu_reg_mem);
 9787 %}
 9788 
 9789 // Rotate Left by variable
 9790 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9791 %{
 9792   predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
 9793   match(Set dst (RotateLeft dst shift));
 9794   effect(KILL cr);
 9795   format %{ "roll    $dst, $shift" %}
 9796   ins_encode %{
 9797     __ roll($dst$$Register);
 9798   %}
 9799   ins_pipe(ialu_reg_reg);
 9800 %}
 9801 
 9802 // Rotate Left by variable
 9803 instruct rolI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
 9804 %{
 9805   predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
 9806   match(Set dst (RotateLeft src shift));
 9807   effect(KILL cr);
 9808 
 9809   format %{ "eroll    $dst, $src, $shift\t# rotate left (int ndd)" %}
 9810   ins_encode %{
 9811     __ eroll($dst$$Register, $src$$Register, false);
 9812   %}
 9813   ins_pipe(ialu_reg_reg);
 9814 %}
 9815 
 9816 // Rotate Right by constant.
 9817 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
 9818 %{
 9819   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9820   match(Set dst (RotateRight dst shift));
 9821   effect(KILL cr);
 9822   format %{ "rorl    $dst, $shift" %}
 9823   ins_encode %{
 9824     __ rorl($dst$$Register, $shift$$constant);
 9825   %}
 9826   ins_pipe(ialu_reg);
 9827 %}
 9828 
 9829 // Rotate Right by constant.
 9830 instruct rorI_immI8(rRegI dst, rRegI src, immI8 shift)
 9831 %{
 9832   predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9833   match(Set dst (RotateRight src shift));
 9834   format %{ "rorxl   $dst, $src, $shift" %}
 9835   ins_encode %{
 9836     __ rorxl($dst$$Register, $src$$Register, $shift$$constant);
 9837   %}
 9838   ins_pipe(ialu_reg_reg);
 9839 %}
 9840 
 9841 instruct rorI_mem_immI8(rRegI dst, memory src, immI8 shift)
 9842 %{
 9843   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9844   match(Set dst (RotateRight (LoadI src) shift));
 9845   ins_cost(175);
 9846   format %{ "rorxl   $dst, $src, $shift" %}
 9847   ins_encode %{
 9848     __ rorxl($dst$$Register, $src$$Address, $shift$$constant);
 9849   %}
 9850   ins_pipe(ialu_reg_mem);
 9851 %}
 9852 
 9853 // Rotate Right by variable
 9854 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9855 %{
 9856   predicate(!UseAPX && n->bottom_type()->basic_type() == T_INT);
 9857   match(Set dst (RotateRight dst shift));
 9858   effect(KILL cr);
 9859   format %{ "rorl    $dst, $shift" %}
 9860   ins_encode %{
 9861     __ rorl($dst$$Register);
 9862   %}
 9863   ins_pipe(ialu_reg_reg);
 9864 %}
 9865 
 9866 // Rotate Right by variable
 9867 instruct rorI_rReg_Var_ndd(rRegI dst, rRegI src, rcx_RegI shift, rFlagsReg cr)
 9868 %{
 9869   predicate(UseAPX && n->bottom_type()->basic_type() == T_INT);
 9870   match(Set dst (RotateRight src shift));
 9871   effect(KILL cr);
 9872 
 9873   format %{ "erorl    $dst, $src, $shift\t# rotate right(int ndd)" %}
 9874   ins_encode %{
 9875     __ erorl($dst$$Register, $src$$Register, false);
 9876   %}
 9877   ins_pipe(ialu_reg_reg);
 9878 %}
 9879 
 9880 // Rotate Left by constant.
 9881 instruct rolL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
 9882 %{
 9883   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9884   match(Set dst (RotateLeft dst shift));
 9885   effect(KILL cr);
 9886   format %{ "rolq    $dst, $shift" %}
 9887   ins_encode %{
 9888     __ rolq($dst$$Register, $shift$$constant);
 9889   %}
 9890   ins_pipe(ialu_reg);
 9891 %}
 9892 
 9893 instruct rolL_immI8(rRegL dst, rRegL src, immI8 shift)
 9894 %{
 9895   predicate(!UseAPX && VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9896   match(Set dst (RotateLeft src shift));
 9897   format %{ "rolxq   $dst, $src, $shift" %}
 9898   ins_encode %{
 9899     int shift = 64 - ($shift$$constant & 63);
 9900     __ rorxq($dst$$Register, $src$$Register, shift);
 9901   %}
 9902   ins_pipe(ialu_reg_reg);
 9903 %}
 9904 
 9905 instruct rolL_mem_immI8(rRegL dst, memory src, immI8 shift)
 9906 %{
 9907   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9908   match(Set dst (RotateLeft (LoadL src) shift));
 9909   ins_cost(175);
 9910   format %{ "rolxq   $dst, $src, $shift" %}
 9911   ins_encode %{
 9912     int shift = 64 - ($shift$$constant & 63);
 9913     __ rorxq($dst$$Register, $src$$Address, shift);
 9914   %}
 9915   ins_pipe(ialu_reg_mem);
 9916 %}
 9917 
 9918 // Rotate Left by variable
 9919 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9920 %{
 9921   predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
 9922   match(Set dst (RotateLeft dst shift));
 9923   effect(KILL cr);
 9924   format %{ "rolq    $dst, $shift" %}
 9925   ins_encode %{
 9926     __ rolq($dst$$Register);
 9927   %}
 9928   ins_pipe(ialu_reg_reg);
 9929 %}
 9930 
 9931 // Rotate Left by variable
 9932 instruct rolL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
 9933 %{
 9934   predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
 9935   match(Set dst (RotateLeft src shift));
 9936   effect(KILL cr);
 9937 
 9938   format %{ "erolq    $dst, $src, $shift\t# rotate left(long ndd)" %}
 9939   ins_encode %{
 9940     __ erolq($dst$$Register, $src$$Register, false);
 9941   %}
 9942   ins_pipe(ialu_reg_reg);
 9943 %}
 9944 
 9945 // Rotate Right by constant.
 9946 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
 9947 %{
 9948   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9949   match(Set dst (RotateRight dst shift));
 9950   effect(KILL cr);
 9951   format %{ "rorq    $dst, $shift" %}
 9952   ins_encode %{
 9953     __ rorq($dst$$Register, $shift$$constant);
 9954   %}
 9955   ins_pipe(ialu_reg);
 9956 %}
 9957 
 9958 // Rotate Right by constant
 9959 instruct rorL_immI8(rRegL dst, rRegL src, immI8 shift)
 9960 %{
 9961   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9962   match(Set dst (RotateRight src shift));
 9963   format %{ "rorxq   $dst, $src, $shift" %}
 9964   ins_encode %{
 9965     __ rorxq($dst$$Register, $src$$Register, $shift$$constant);
 9966   %}
 9967   ins_pipe(ialu_reg_reg);
 9968 %}
 9969 
 9970 instruct rorL_mem_immI8(rRegL dst, memory src, immI8 shift)
 9971 %{
 9972   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9973   match(Set dst (RotateRight (LoadL src) shift));
 9974   ins_cost(175);
 9975   format %{ "rorxq   $dst, $src, $shift" %}
 9976   ins_encode %{
 9977     __ rorxq($dst$$Register, $src$$Address, $shift$$constant);
 9978   %}
 9979   ins_pipe(ialu_reg_mem);
 9980 %}
 9981 
 9982 // Rotate Right by variable
 9983 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9984 %{
 9985   predicate(!UseAPX && n->bottom_type()->basic_type() == T_LONG);
 9986   match(Set dst (RotateRight dst shift));
 9987   effect(KILL cr);
 9988   format %{ "rorq    $dst, $shift" %}
 9989   ins_encode %{
 9990     __ rorq($dst$$Register);
 9991   %}
 9992   ins_pipe(ialu_reg_reg);
 9993 %}
 9994 
 9995 // Rotate Right by variable
 9996 instruct rorL_rReg_Var_ndd(rRegL dst, rRegL src, rcx_RegI shift, rFlagsReg cr)
 9997 %{
 9998   predicate(UseAPX && n->bottom_type()->basic_type() == T_LONG);
 9999   match(Set dst (RotateRight src shift));
10000   effect(KILL cr);
10001 
10002   format %{ "erorq    $dst, $src, $shift\t# rotate right(long ndd)" %}
10003   ins_encode %{
10004     __ erorq($dst$$Register, $src$$Register, false);
10005   %}
10006   ins_pipe(ialu_reg_reg);
10007 %}
10008 
10009 //----------------------------- CompressBits/ExpandBits ------------------------
10010 
10011 instruct compressBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
10012   predicate(n->bottom_type()->isa_long());
10013   match(Set dst (CompressBits src mask));
10014   format %{ "pextq  $dst, $src, $mask\t! parallel bit extract" %}
10015   ins_encode %{
10016     __ pextq($dst$$Register, $src$$Register, $mask$$Register);
10017   %}
10018   ins_pipe( pipe_slow );
10019 %}
10020 
10021 instruct expandBitsL_reg(rRegL dst, rRegL src, rRegL mask) %{
10022   predicate(n->bottom_type()->isa_long());
10023   match(Set dst (ExpandBits src mask));
10024   format %{ "pdepq  $dst, $src, $mask\t! parallel bit deposit" %}
10025   ins_encode %{
10026     __ pdepq($dst$$Register, $src$$Register, $mask$$Register);
10027   %}
10028   ins_pipe( pipe_slow );
10029 %}
10030 
10031 instruct compressBitsL_mem(rRegL dst, rRegL src, memory mask) %{
10032   predicate(n->bottom_type()->isa_long());
10033   match(Set dst (CompressBits src (LoadL mask)));
10034   format %{ "pextq  $dst, $src, $mask\t! parallel bit extract" %}
10035   ins_encode %{
10036     __ pextq($dst$$Register, $src$$Register, $mask$$Address);
10037   %}
10038   ins_pipe( pipe_slow );
10039 %}
10040 
10041 instruct expandBitsL_mem(rRegL dst, rRegL src, memory mask) %{
10042   predicate(n->bottom_type()->isa_long());
10043   match(Set dst (ExpandBits src (LoadL mask)));
10044   format %{ "pdepq  $dst, $src, $mask\t! parallel bit deposit" %}
10045   ins_encode %{
10046     __ pdepq($dst$$Register, $src$$Register, $mask$$Address);
10047   %}
10048   ins_pipe( pipe_slow );
10049 %}
10050 
10051 
10052 // Logical Instructions
10053 
10054 // Integer Logical Instructions
10055 
10056 // And Instructions
10057 // And Register with Register
10058 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10059 %{
10060   predicate(!UseAPX);
10061   match(Set dst (AndI dst src));
10062   effect(KILL cr);
10063   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10064 
10065   format %{ "andl    $dst, $src\t# int" %}
10066   ins_encode %{
10067     __ andl($dst$$Register, $src$$Register);
10068   %}
10069   ins_pipe(ialu_reg_reg);
10070 %}
10071 
10072 // And Register with Register using New Data Destination (NDD)
10073 instruct andI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10074 %{
10075   predicate(UseAPX);
10076   match(Set dst (AndI src1 src2));
10077   effect(KILL cr);
10078   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10079 
10080   format %{ "eandl     $dst, $src1, $src2\t# int ndd" %}
10081   ins_encode %{
10082     __ eandl($dst$$Register, $src1$$Register, $src2$$Register, false);
10083 
10084   %}
10085   ins_pipe(ialu_reg_reg);
10086 %}
10087 
10088 // And Register with Immediate 255
10089 instruct andI_rReg_imm255(rRegI dst, rRegI src, immI_255 mask)
10090 %{
10091   match(Set dst (AndI src mask));
10092 
10093   format %{ "movzbl  $dst, $src\t# int & 0xFF" %}
10094   ins_encode %{
10095     __ movzbl($dst$$Register, $src$$Register);
10096   %}
10097   ins_pipe(ialu_reg);
10098 %}
10099 
10100 // And Register with Immediate 255 and promote to long
10101 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
10102 %{
10103   match(Set dst (ConvI2L (AndI src mask)));
10104 
10105   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
10106   ins_encode %{
10107     __ movzbl($dst$$Register, $src$$Register);
10108   %}
10109   ins_pipe(ialu_reg);
10110 %}
10111 
10112 // And Register with Immediate 65535
10113 instruct andI_rReg_imm65535(rRegI dst, rRegI src, immI_65535 mask)
10114 %{
10115   match(Set dst (AndI src mask));
10116 
10117   format %{ "movzwl  $dst, $src\t# int & 0xFFFF" %}
10118   ins_encode %{
10119     __ movzwl($dst$$Register, $src$$Register);
10120   %}
10121   ins_pipe(ialu_reg);
10122 %}
10123 
10124 // And Register with Immediate 65535 and promote to long
10125 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
10126 %{
10127   match(Set dst (ConvI2L (AndI src mask)));
10128 
10129   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
10130   ins_encode %{
10131     __ movzwl($dst$$Register, $src$$Register);
10132   %}
10133   ins_pipe(ialu_reg);
10134 %}
10135 
10136 // Can skip int2long conversions after AND with small bitmask
10137 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src,  immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
10138 %{
10139   predicate(VM_Version::supports_bmi2());
10140   ins_cost(125);
10141   effect(TEMP tmp, KILL cr);
10142   match(Set dst (ConvI2L (AndI src mask)));
10143   format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int &  immI_Pow2M1 -> long" %}
10144   ins_encode %{
10145     __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
10146     __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
10147   %}
10148   ins_pipe(ialu_reg_reg);
10149 %}
10150 
10151 // And Register with Immediate
10152 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10153 %{
10154   predicate(!UseAPX);
10155   match(Set dst (AndI dst src));
10156   effect(KILL cr);
10157   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10158 
10159   format %{ "andl    $dst, $src\t# int" %}
10160   ins_encode %{
10161     __ andl($dst$$Register, $src$$constant);
10162   %}
10163   ins_pipe(ialu_reg);
10164 %}
10165 
10166 instruct andI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10167 %{
10168   predicate(UseAPX);
10169   match(Set dst (AndI src1 src2));
10170   effect(KILL cr);
10171   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10172 
10173   format %{ "eandl    $dst, $src1, $src2\t# int ndd" %}
10174   ins_encode %{
10175     __ eandl($dst$$Register, $src1$$Register, $src2$$constant, false);
10176   %}
10177   ins_pipe(ialu_reg);
10178 %}
10179 
10180 instruct andI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10181 %{
10182   predicate(UseAPX);
10183   match(Set dst (AndI (LoadI src1) src2));
10184   effect(KILL cr);
10185   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10186 
10187   format %{ "eandl    $dst, $src1, $src2\t# int ndd" %}
10188   ins_encode %{
10189     __ eandl($dst$$Register, $src1$$Address, $src2$$constant, false);
10190   %}
10191   ins_pipe(ialu_reg);
10192 %}
10193 
10194 // And Register with Memory
10195 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10196 %{
10197   predicate(!UseAPX);
10198   match(Set dst (AndI dst (LoadI src)));
10199   effect(KILL cr);
10200   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10201 
10202   ins_cost(150);
10203   format %{ "andl    $dst, $src\t# int" %}
10204   ins_encode %{
10205     __ andl($dst$$Register, $src$$Address);
10206   %}
10207   ins_pipe(ialu_reg_mem);
10208 %}
10209 
10210 instruct andI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10211 %{
10212   predicate(UseAPX);
10213   match(Set dst (AndI src1 (LoadI src2)));
10214   effect(KILL cr);
10215   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10216 
10217   ins_cost(150);
10218   format %{ "eandl    $dst, $src1, $src2\t# int ndd" %}
10219   ins_encode %{
10220     __ eandl($dst$$Register, $src1$$Register, $src2$$Address, false);
10221   %}
10222   ins_pipe(ialu_reg_mem);
10223 %}
10224 
10225 // And Memory with Register
10226 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10227 %{
10228   match(Set dst (StoreB dst (AndI (LoadB dst) src)));
10229   effect(KILL cr);
10230   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10231 
10232   ins_cost(150);
10233   format %{ "andb    $dst, $src\t# byte" %}
10234   ins_encode %{
10235     __ andb($dst$$Address, $src$$Register);
10236   %}
10237   ins_pipe(ialu_mem_reg);
10238 %}
10239 
10240 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10241 %{
10242   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10243   effect(KILL cr);
10244   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10245 
10246   ins_cost(150);
10247   format %{ "andl    $dst, $src\t# int" %}
10248   ins_encode %{
10249     __ andl($dst$$Address, $src$$Register);
10250   %}
10251   ins_pipe(ialu_mem_reg);
10252 %}
10253 
10254 // And Memory with Immediate
10255 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
10256 %{
10257   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
10258   effect(KILL cr);
10259   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10260 
10261   ins_cost(125);
10262   format %{ "andl    $dst, $src\t# int" %}
10263   ins_encode %{
10264     __ andl($dst$$Address, $src$$constant);
10265   %}
10266   ins_pipe(ialu_mem_imm);
10267 %}
10268 
10269 // BMI1 instructions
10270 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
10271   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
10272   predicate(UseBMI1Instructions);
10273   effect(KILL cr);
10274   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10275 
10276   ins_cost(125);
10277   format %{ "andnl  $dst, $src1, $src2" %}
10278 
10279   ins_encode %{
10280     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
10281   %}
10282   ins_pipe(ialu_reg_mem);
10283 %}
10284 
10285 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
10286   match(Set dst (AndI (XorI src1 minus_1) src2));
10287   predicate(UseBMI1Instructions);
10288   effect(KILL cr);
10289   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10290 
10291   format %{ "andnl  $dst, $src1, $src2" %}
10292 
10293   ins_encode %{
10294     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
10295   %}
10296   ins_pipe(ialu_reg);
10297 %}
10298 
10299 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
10300   match(Set dst (AndI (SubI imm_zero src) src));
10301   predicate(UseBMI1Instructions);
10302   effect(KILL cr);
10303   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10304 
10305   format %{ "blsil  $dst, $src" %}
10306 
10307   ins_encode %{
10308     __ blsil($dst$$Register, $src$$Register);
10309   %}
10310   ins_pipe(ialu_reg);
10311 %}
10312 
10313 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
10314   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
10315   predicate(UseBMI1Instructions);
10316   effect(KILL cr);
10317   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10318 
10319   ins_cost(125);
10320   format %{ "blsil  $dst, $src" %}
10321 
10322   ins_encode %{
10323     __ blsil($dst$$Register, $src$$Address);
10324   %}
10325   ins_pipe(ialu_reg_mem);
10326 %}
10327 
10328 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10329 %{
10330   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
10331   predicate(UseBMI1Instructions);
10332   effect(KILL cr);
10333   flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10334 
10335   ins_cost(125);
10336   format %{ "blsmskl $dst, $src" %}
10337 
10338   ins_encode %{
10339     __ blsmskl($dst$$Register, $src$$Address);
10340   %}
10341   ins_pipe(ialu_reg_mem);
10342 %}
10343 
10344 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10345 %{
10346   match(Set dst (XorI (AddI src minus_1) src));
10347   predicate(UseBMI1Instructions);
10348   effect(KILL cr);
10349   flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
10350 
10351   format %{ "blsmskl $dst, $src" %}
10352 
10353   ins_encode %{
10354     __ blsmskl($dst$$Register, $src$$Register);
10355   %}
10356 
10357   ins_pipe(ialu_reg);
10358 %}
10359 
10360 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
10361 %{
10362   match(Set dst (AndI (AddI src minus_1) src) );
10363   predicate(UseBMI1Instructions);
10364   effect(KILL cr);
10365   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10366 
10367   format %{ "blsrl  $dst, $src" %}
10368 
10369   ins_encode %{
10370     __ blsrl($dst$$Register, $src$$Register);
10371   %}
10372 
10373   ins_pipe(ialu_reg_mem);
10374 %}
10375 
10376 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
10377 %{
10378   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
10379   predicate(UseBMI1Instructions);
10380   effect(KILL cr);
10381   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10382 
10383   ins_cost(125);
10384   format %{ "blsrl  $dst, $src" %}
10385 
10386   ins_encode %{
10387     __ blsrl($dst$$Register, $src$$Address);
10388   %}
10389 
10390   ins_pipe(ialu_reg);
10391 %}
10392 
10393 // Or Instructions
10394 // Or Register with Register
10395 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10396 %{
10397   predicate(!UseAPX);
10398   match(Set dst (OrI dst src));
10399   effect(KILL cr);
10400   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10401 
10402   format %{ "orl     $dst, $src\t# int" %}
10403   ins_encode %{
10404     __ orl($dst$$Register, $src$$Register);
10405   %}
10406   ins_pipe(ialu_reg_reg);
10407 %}
10408 
10409 // Or Register with Register using New Data Destination (NDD)
10410 instruct orI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10411 %{
10412   predicate(UseAPX);
10413   match(Set dst (OrI src1 src2));
10414   effect(KILL cr);
10415   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10416 
10417   format %{ "eorl     $dst, $src1, $src2\t# int ndd" %}
10418   ins_encode %{
10419     __ eorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10420   %}
10421   ins_pipe(ialu_reg_reg);
10422 %}
10423 
10424 // Or Register with Immediate
10425 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10426 %{
10427   predicate(!UseAPX);
10428   match(Set dst (OrI dst src));
10429   effect(KILL cr);
10430   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10431 
10432   format %{ "orl     $dst, $src\t# int" %}
10433   ins_encode %{
10434     __ orl($dst$$Register, $src$$constant);
10435   %}
10436   ins_pipe(ialu_reg);
10437 %}
10438 
10439 instruct orI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10440 %{
10441   predicate(UseAPX);
10442   match(Set dst (OrI src1 src2));
10443   effect(KILL cr);
10444   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10445 
10446   format %{ "eorl     $dst, $src1, $src2\t# int ndd" %}
10447   ins_encode %{
10448     __ eorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10449   %}
10450   ins_pipe(ialu_reg);
10451 %}
10452 
10453 instruct orI_rReg_imm_rReg_ndd(rRegI dst, immI src1, rRegI src2, rFlagsReg cr)
10454 %{
10455   predicate(UseAPX);
10456   match(Set dst (OrI src1 src2));
10457   effect(KILL cr);
10458   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10459 
10460   format %{ "eorl     $dst, $src2, $src1\t# int ndd" %}
10461   ins_encode %{
10462     __ eorl($dst$$Register, $src2$$Register, $src1$$constant, false);
10463   %}
10464   ins_pipe(ialu_reg);
10465 %}
10466 
10467 instruct orI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10468 %{
10469   predicate(UseAPX);
10470   match(Set dst (OrI (LoadI src1) src2));
10471   effect(KILL cr);
10472   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10473 
10474   format %{ "eorl     $dst, $src1, $src2\t# int ndd" %}
10475   ins_encode %{
10476     __ eorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10477   %}
10478   ins_pipe(ialu_reg);
10479 %}
10480 
10481 // Or Register with Memory
10482 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10483 %{
10484   predicate(!UseAPX);
10485   match(Set dst (OrI dst (LoadI src)));
10486   effect(KILL cr);
10487   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10488 
10489   ins_cost(150);
10490   format %{ "orl     $dst, $src\t# int" %}
10491   ins_encode %{
10492     __ orl($dst$$Register, $src$$Address);
10493   %}
10494   ins_pipe(ialu_reg_mem);
10495 %}
10496 
10497 instruct orI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10498 %{
10499   predicate(UseAPX);
10500   match(Set dst (OrI src1 (LoadI src2)));
10501   effect(KILL cr);
10502   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10503 
10504   ins_cost(150);
10505   format %{ "eorl     $dst, $src1, $src2\t# int ndd" %}
10506   ins_encode %{
10507     __ eorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10508   %}
10509   ins_pipe(ialu_reg_mem);
10510 %}
10511 
10512 // Or Memory with Register
10513 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10514 %{
10515   match(Set dst (StoreB dst (OrI (LoadB dst) src)));
10516   effect(KILL cr);
10517   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10518 
10519   ins_cost(150);
10520   format %{ "orb    $dst, $src\t# byte" %}
10521   ins_encode %{
10522     __ orb($dst$$Address, $src$$Register);
10523   %}
10524   ins_pipe(ialu_mem_reg);
10525 %}
10526 
10527 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10528 %{
10529   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10530   effect(KILL cr);
10531   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10532 
10533   ins_cost(150);
10534   format %{ "orl     $dst, $src\t# int" %}
10535   ins_encode %{
10536     __ orl($dst$$Address, $src$$Register);
10537   %}
10538   ins_pipe(ialu_mem_reg);
10539 %}
10540 
10541 // Or Memory with Immediate
10542 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
10543 %{
10544   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
10545   effect(KILL cr);
10546   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10547 
10548   ins_cost(125);
10549   format %{ "orl     $dst, $src\t# int" %}
10550   ins_encode %{
10551     __ orl($dst$$Address, $src$$constant);
10552   %}
10553   ins_pipe(ialu_mem_imm);
10554 %}
10555 
10556 // Xor Instructions
10557 // Xor Register with Register
10558 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
10559 %{
10560   predicate(!UseAPX);
10561   match(Set dst (XorI dst src));
10562   effect(KILL cr);
10563   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10564 
10565   format %{ "xorl    $dst, $src\t# int" %}
10566   ins_encode %{
10567     __ xorl($dst$$Register, $src$$Register);
10568   %}
10569   ins_pipe(ialu_reg_reg);
10570 %}
10571 
10572 // Xor Register with Register using New Data Destination (NDD)
10573 instruct xorI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
10574 %{
10575   predicate(UseAPX);
10576   match(Set dst (XorI src1 src2));
10577   effect(KILL cr);
10578   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10579 
10580   format %{ "exorl    $dst, $src1, $src2\t# int ndd" %}
10581   ins_encode %{
10582     __ exorl($dst$$Register, $src1$$Register, $src2$$Register, false);
10583   %}
10584   ins_pipe(ialu_reg_reg);
10585 %}
10586 
10587 // Xor Register with Immediate -1
10588 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm)
10589 %{
10590   predicate(!UseAPX);
10591   match(Set dst (XorI dst imm));
10592 
10593   format %{ "notl    $dst" %}
10594   ins_encode %{
10595      __ notl($dst$$Register);
10596   %}
10597   ins_pipe(ialu_reg);
10598 %}
10599 
10600 instruct xorI_rReg_im1_ndd(rRegI dst, rRegI src, immI_M1 imm)
10601 %{
10602   match(Set dst (XorI src imm));
10603   predicate(UseAPX);
10604 
10605   format %{ "enotl    $dst, $src" %}
10606   ins_encode %{
10607      __ enotl($dst$$Register, $src$$Register);
10608   %}
10609   ins_pipe(ialu_reg);
10610 %}
10611 
10612 // Xor Register with Immediate
10613 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
10614 %{
10615   predicate(!UseAPX);
10616   match(Set dst (XorI dst src));
10617   effect(KILL cr);
10618   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10619 
10620   format %{ "xorl    $dst, $src\t# int" %}
10621   ins_encode %{
10622     __ xorl($dst$$Register, $src$$constant);
10623   %}
10624   ins_pipe(ialu_reg);
10625 %}
10626 
10627 instruct xorI_rReg_rReg_imm_ndd(rRegI dst, rRegI src1, immI src2, rFlagsReg cr)
10628 %{
10629   predicate(UseAPX);
10630   match(Set dst (XorI src1 src2));
10631   effect(KILL cr);
10632   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10633 
10634   format %{ "exorl    $dst, $src1, $src2\t# int ndd" %}
10635   ins_encode %{
10636     __ exorl($dst$$Register, $src1$$Register, $src2$$constant, false);
10637   %}
10638   ins_pipe(ialu_reg);
10639 %}
10640 
10641 // Xor Memory with Immediate
10642 instruct xorI_rReg_mem_imm_ndd(rRegI dst, memory src1, immI src2, rFlagsReg cr)
10643 %{
10644   predicate(UseAPX);
10645   match(Set dst (XorI (LoadI src1) src2));
10646   effect(KILL cr);
10647   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10648 
10649   format %{ "exorl    $dst, $src1, $src2\t# int ndd" %}
10650   ins_encode %{
10651     __ exorl($dst$$Register, $src1$$Address, $src2$$constant, false);
10652   %}
10653   ins_pipe(ialu_reg);
10654 %}
10655 
10656 // Xor Register with Memory
10657 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
10658 %{
10659   predicate(!UseAPX);
10660   match(Set dst (XorI dst (LoadI src)));
10661   effect(KILL cr);
10662   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10663 
10664   ins_cost(150);
10665   format %{ "xorl    $dst, $src\t# int" %}
10666   ins_encode %{
10667     __ xorl($dst$$Register, $src$$Address);
10668   %}
10669   ins_pipe(ialu_reg_mem);
10670 %}
10671 
10672 instruct xorI_rReg_rReg_mem_ndd(rRegI dst, rRegI src1, memory src2, rFlagsReg cr)
10673 %{
10674   predicate(UseAPX);
10675   match(Set dst (XorI src1 (LoadI src2)));
10676   effect(KILL cr);
10677   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10678 
10679   ins_cost(150);
10680   format %{ "exorl    $dst, $src1, $src2\t# int ndd" %}
10681   ins_encode %{
10682     __ exorl($dst$$Register, $src1$$Register, $src2$$Address, false);
10683   %}
10684   ins_pipe(ialu_reg_mem);
10685 %}
10686 
10687 instruct xorI_rReg_mem_rReg_ndd(rRegI dst, memory src1, rRegI src2, rFlagsReg cr)
10688 %{
10689   predicate(UseAPX);
10690   match(Set dst (XorI (LoadI src1) src2));
10691   effect(KILL cr);
10692   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10693 
10694   ins_cost(150);
10695   format %{ "exorl    $dst, $src1, $src2\t# int ndd" %}
10696   ins_encode %{
10697     __ exorl($dst$$Register, $src1$$Address, $src2$$Register, false);
10698   %}
10699   ins_pipe(ialu_reg_mem);
10700 %}
10701 
10702 // Xor Memory with Register
10703 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10704 %{
10705   match(Set dst (StoreB dst (XorI (LoadB dst) src)));
10706   effect(KILL cr);
10707   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10708 
10709   ins_cost(150);
10710   format %{ "xorb    $dst, $src\t# byte" %}
10711   ins_encode %{
10712     __ xorb($dst$$Address, $src$$Register);
10713   %}
10714   ins_pipe(ialu_mem_reg);
10715 %}
10716 
10717 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
10718 %{
10719   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10720   effect(KILL cr);
10721   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10722 
10723   ins_cost(150);
10724   format %{ "xorl    $dst, $src\t# int" %}
10725   ins_encode %{
10726     __ xorl($dst$$Address, $src$$Register);
10727   %}
10728   ins_pipe(ialu_mem_reg);
10729 %}
10730 
10731 // Xor Memory with Immediate
10732 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
10733 %{
10734   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
10735   effect(KILL cr);
10736   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10737 
10738   ins_cost(125);
10739   format %{ "xorl    $dst, $src\t# int" %}
10740   ins_encode %{
10741     __ xorl($dst$$Address, $src$$constant);
10742   %}
10743   ins_pipe(ialu_mem_imm);
10744 %}
10745 
10746 
10747 // Long Logical Instructions
10748 
10749 // And Instructions
10750 // And Register with Register
10751 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10752 %{
10753   predicate(!UseAPX);
10754   match(Set dst (AndL dst src));
10755   effect(KILL cr);
10756   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10757 
10758   format %{ "andq    $dst, $src\t# long" %}
10759   ins_encode %{
10760     __ andq($dst$$Register, $src$$Register);
10761   %}
10762   ins_pipe(ialu_reg_reg);
10763 %}
10764 
10765 // And Register with Register using New Data Destination (NDD)
10766 instruct andL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
10767 %{
10768   predicate(UseAPX);
10769   match(Set dst (AndL src1 src2));
10770   effect(KILL cr);
10771   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10772 
10773   format %{ "eandq     $dst, $src1, $src2\t# long ndd" %}
10774   ins_encode %{
10775     __ eandq($dst$$Register, $src1$$Register, $src2$$Register, false);
10776 
10777   %}
10778   ins_pipe(ialu_reg_reg);
10779 %}
10780 
10781 // And Register with Immediate 255
10782 instruct andL_rReg_imm255(rRegL dst, rRegL src, immL_255 mask)
10783 %{
10784   match(Set dst (AndL src mask));
10785 
10786   format %{ "movzbl  $dst, $src\t# long & 0xFF" %}
10787   ins_encode %{
10788     // movzbl zeroes out the upper 32-bit and does not need REX.W
10789     __ movzbl($dst$$Register, $src$$Register);
10790   %}
10791   ins_pipe(ialu_reg);
10792 %}
10793 
10794 // And Register with Immediate 65535
10795 instruct andL_rReg_imm65535(rRegL dst, rRegL src, immL_65535 mask)
10796 %{
10797   match(Set dst (AndL src mask));
10798 
10799   format %{ "movzwl  $dst, $src\t# long & 0xFFFF" %}
10800   ins_encode %{
10801     // movzwl zeroes out the upper 32-bit and does not need REX.W
10802     __ movzwl($dst$$Register, $src$$Register);
10803   %}
10804   ins_pipe(ialu_reg);
10805 %}
10806 
10807 // And Register with Immediate
10808 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10809 %{
10810   predicate(!UseAPX);
10811   match(Set dst (AndL dst src));
10812   effect(KILL cr);
10813   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10814 
10815   format %{ "andq    $dst, $src\t# long" %}
10816   ins_encode %{
10817     __ andq($dst$$Register, $src$$constant);
10818   %}
10819   ins_pipe(ialu_reg);
10820 %}
10821 
10822 instruct andL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
10823 %{
10824   predicate(UseAPX);
10825   match(Set dst (AndL src1 src2));
10826   effect(KILL cr);
10827   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10828 
10829   format %{ "eandq    $dst, $src1, $src2\t# long ndd" %}
10830   ins_encode %{
10831     __ eandq($dst$$Register, $src1$$Register, $src2$$constant, false);
10832   %}
10833   ins_pipe(ialu_reg);
10834 %}
10835 
10836 instruct andL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
10837 %{
10838   predicate(UseAPX);
10839   match(Set dst (AndL (LoadL src1) src2));
10840   effect(KILL cr);
10841   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10842 
10843   format %{ "eandq    $dst, $src1, $src2\t# long ndd" %}
10844   ins_encode %{
10845     __ eandq($dst$$Register, $src1$$Address, $src2$$constant, false);
10846   %}
10847   ins_pipe(ialu_reg);
10848 %}
10849 
10850 // And Register with Memory
10851 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10852 %{
10853   predicate(!UseAPX);
10854   match(Set dst (AndL dst (LoadL src)));
10855   effect(KILL cr);
10856   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10857 
10858   ins_cost(150);
10859   format %{ "andq    $dst, $src\t# long" %}
10860   ins_encode %{
10861     __ andq($dst$$Register, $src$$Address);
10862   %}
10863   ins_pipe(ialu_reg_mem);
10864 %}
10865 
10866 instruct andL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
10867 %{
10868   predicate(UseAPX);
10869   match(Set dst (AndL src1 (LoadL src2)));
10870   effect(KILL cr);
10871   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10872 
10873   ins_cost(150);
10874   format %{ "eandq    $dst, $src1, $src2\t# long ndd" %}
10875   ins_encode %{
10876     __ eandq($dst$$Register, $src1$$Register, $src2$$Address, false);
10877   %}
10878   ins_pipe(ialu_reg_mem);
10879 %}
10880 
10881 instruct andL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
10882 %{
10883   predicate(UseAPX);
10884   match(Set dst (AndL (LoadL src1) src2));
10885   effect(KILL cr);
10886   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10887 
10888   ins_cost(150);
10889   format %{ "eandq    $dst, $src1, $src2\t# long ndd" %}
10890   ins_encode %{
10891     __ eandq($dst$$Register, $src1$$Address, $src2$$Register, false);
10892   %}
10893   ins_pipe(ialu_reg_mem);
10894 %}
10895 
10896 // And Memory with Register
10897 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10898 %{
10899   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10900   effect(KILL cr);
10901   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10902 
10903   ins_cost(150);
10904   format %{ "andq    $dst, $src\t# long" %}
10905   ins_encode %{
10906     __ andq($dst$$Address, $src$$Register);
10907   %}
10908   ins_pipe(ialu_mem_reg);
10909 %}
10910 
10911 // And Memory with Immediate
10912 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10913 %{
10914   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
10915   effect(KILL cr);
10916   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10917 
10918   ins_cost(125);
10919   format %{ "andq    $dst, $src\t# long" %}
10920   ins_encode %{
10921     __ andq($dst$$Address, $src$$constant);
10922   %}
10923   ins_pipe(ialu_mem_imm);
10924 %}
10925 
10926 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
10927 %{
10928   // con should be a pure 64-bit immediate given that not(con) is a power of 2
10929   // because AND/OR works well enough for 8/32-bit values.
10930   predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
10931 
10932   match(Set dst (StoreL dst (AndL (LoadL dst) con)));
10933   effect(KILL cr);
10934 
10935   ins_cost(125);
10936   format %{ "btrq    $dst, log2(not($con))\t# long" %}
10937   ins_encode %{
10938     __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
10939   %}
10940   ins_pipe(ialu_mem_imm);
10941 %}
10942 
10943 // BMI1 instructions
10944 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
10945   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
10946   predicate(UseBMI1Instructions);
10947   effect(KILL cr);
10948   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10949 
10950   ins_cost(125);
10951   format %{ "andnq  $dst, $src1, $src2" %}
10952 
10953   ins_encode %{
10954     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
10955   %}
10956   ins_pipe(ialu_reg_mem);
10957 %}
10958 
10959 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
10960   match(Set dst (AndL (XorL src1 minus_1) src2));
10961   predicate(UseBMI1Instructions);
10962   effect(KILL cr);
10963   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
10964 
10965   format %{ "andnq  $dst, $src1, $src2" %}
10966 
10967   ins_encode %{
10968   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
10969   %}
10970   ins_pipe(ialu_reg_mem);
10971 %}
10972 
10973 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
10974   match(Set dst (AndL (SubL imm_zero src) src));
10975   predicate(UseBMI1Instructions);
10976   effect(KILL cr);
10977   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10978 
10979   format %{ "blsiq  $dst, $src" %}
10980 
10981   ins_encode %{
10982     __ blsiq($dst$$Register, $src$$Register);
10983   %}
10984   ins_pipe(ialu_reg);
10985 %}
10986 
10987 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
10988   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
10989   predicate(UseBMI1Instructions);
10990   effect(KILL cr);
10991   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
10992 
10993   ins_cost(125);
10994   format %{ "blsiq  $dst, $src" %}
10995 
10996   ins_encode %{
10997     __ blsiq($dst$$Register, $src$$Address);
10998   %}
10999   ins_pipe(ialu_reg_mem);
11000 %}
11001 
11002 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
11003 %{
11004   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
11005   predicate(UseBMI1Instructions);
11006   effect(KILL cr);
11007   flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
11008 
11009   ins_cost(125);
11010   format %{ "blsmskq $dst, $src" %}
11011 
11012   ins_encode %{
11013     __ blsmskq($dst$$Register, $src$$Address);
11014   %}
11015   ins_pipe(ialu_reg_mem);
11016 %}
11017 
11018 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
11019 %{
11020   match(Set dst (XorL (AddL src minus_1) src));
11021   predicate(UseBMI1Instructions);
11022   effect(KILL cr);
11023   flag(PD::Flag_sets_sign_flag, PD::Flag_clears_zero_flag, PD::Flag_clears_overflow_flag);
11024 
11025   format %{ "blsmskq $dst, $src" %}
11026 
11027   ins_encode %{
11028     __ blsmskq($dst$$Register, $src$$Register);
11029   %}
11030 
11031   ins_pipe(ialu_reg);
11032 %}
11033 
11034 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
11035 %{
11036   match(Set dst (AndL (AddL src minus_1) src) );
11037   predicate(UseBMI1Instructions);
11038   effect(KILL cr);
11039   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11040 
11041   format %{ "blsrq  $dst, $src" %}
11042 
11043   ins_encode %{
11044     __ blsrq($dst$$Register, $src$$Register);
11045   %}
11046 
11047   ins_pipe(ialu_reg);
11048 %}
11049 
11050 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
11051 %{
11052   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
11053   predicate(UseBMI1Instructions);
11054   effect(KILL cr);
11055   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_clears_overflow_flag);
11056 
11057   ins_cost(125);
11058   format %{ "blsrq  $dst, $src" %}
11059 
11060   ins_encode %{
11061     __ blsrq($dst$$Register, $src$$Address);
11062   %}
11063 
11064   ins_pipe(ialu_reg);
11065 %}
11066 
11067 // Or Instructions
11068 // Or Register with Register
11069 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11070 %{
11071   predicate(!UseAPX);
11072   match(Set dst (OrL dst src));
11073   effect(KILL cr);
11074   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11075 
11076   format %{ "orq     $dst, $src\t# long" %}
11077   ins_encode %{
11078     __ orq($dst$$Register, $src$$Register);
11079   %}
11080   ins_pipe(ialu_reg_reg);
11081 %}
11082 
11083 // Or Register with Register using New Data Destination (NDD)
11084 instruct orL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11085 %{
11086   predicate(UseAPX);
11087   match(Set dst (OrL src1 src2));
11088   effect(KILL cr);
11089   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11090 
11091   format %{ "eorq     $dst, $src1, $src2\t# long ndd" %}
11092   ins_encode %{
11093     __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11094 
11095   %}
11096   ins_pipe(ialu_reg_reg);
11097 %}
11098 
11099 // Use any_RegP to match R15 (TLS register) without spilling.
11100 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
11101   match(Set dst (OrL dst (CastP2X src)));
11102   effect(KILL cr);
11103   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11104 
11105   format %{ "orq     $dst, $src\t# long" %}
11106   ins_encode %{
11107     __ orq($dst$$Register, $src$$Register);
11108   %}
11109   ins_pipe(ialu_reg_reg);
11110 %}
11111 
11112 instruct orL_rReg_castP2X_ndd(rRegL dst, any_RegP src1, any_RegP src2, rFlagsReg cr) %{
11113   match(Set dst (OrL src1 (CastP2X src2)));
11114   effect(KILL cr);
11115   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11116 
11117   format %{ "eorq     $dst, $src1, $src2\t# long ndd" %}
11118   ins_encode %{
11119     __ eorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11120   %}
11121   ins_pipe(ialu_reg_reg);
11122 %}
11123 
11124 // Or Register with Immediate
11125 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11126 %{
11127   predicate(!UseAPX);
11128   match(Set dst (OrL dst src));
11129   effect(KILL cr);
11130   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11131 
11132   format %{ "orq     $dst, $src\t# long" %}
11133   ins_encode %{
11134     __ orq($dst$$Register, $src$$constant);
11135   %}
11136   ins_pipe(ialu_reg);
11137 %}
11138 
11139 instruct orL_rReg_rReg_imm_ndd(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11140 %{
11141   predicate(UseAPX);
11142   match(Set dst (OrL src1 src2));
11143   effect(KILL cr);
11144   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11145 
11146   format %{ "eorq     $dst, $src1, $src2\t# long ndd" %}
11147   ins_encode %{
11148     __ eorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11149   %}
11150   ins_pipe(ialu_reg);
11151 %}
11152 
11153 instruct orL_rReg_imm_rReg_ndd(rRegL dst, immL32 src1, rRegL src2, rFlagsReg cr)
11154 %{
11155   predicate(UseAPX);
11156   match(Set dst (OrL src1 src2));
11157   effect(KILL cr);
11158   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11159 
11160   format %{ "eorq     $dst, $src2, $src1\t# long ndd" %}
11161   ins_encode %{
11162     __ eorq($dst$$Register, $src2$$Register, $src1$$constant, false);
11163   %}
11164   ins_pipe(ialu_reg);
11165 %}
11166 
11167 // Or Memory with Immediate
11168 instruct orL_rReg_mem_imm_ndd(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11169 %{
11170   predicate(UseAPX);
11171   match(Set dst (OrL (LoadL src1) src2));
11172   effect(KILL cr);
11173   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11174 
11175   format %{ "eorq     $dst, $src1, $src2\t# long ndd" %}
11176   ins_encode %{
11177     __ eorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11178   %}
11179   ins_pipe(ialu_reg);
11180 %}
11181 
11182 // Or Register with Memory
11183 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11184 %{
11185   predicate(!UseAPX);
11186   match(Set dst (OrL dst (LoadL src)));
11187   effect(KILL cr);
11188   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11189 
11190   ins_cost(150);
11191   format %{ "orq     $dst, $src\t# long" %}
11192   ins_encode %{
11193     __ orq($dst$$Register, $src$$Address);
11194   %}
11195   ins_pipe(ialu_reg_mem);
11196 %}
11197 
11198 instruct orL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11199 %{
11200   predicate(UseAPX);
11201   match(Set dst (OrL src1 (LoadL src2)));
11202   effect(KILL cr);
11203   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11204 
11205   ins_cost(150);
11206   format %{ "eorq     $dst, $src1, $src2\t# long ndd" %}
11207   ins_encode %{
11208     __ eorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11209   %}
11210   ins_pipe(ialu_reg_mem);
11211 %}
11212 
11213 // Or Memory with Register
11214 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11215 %{
11216   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11217   effect(KILL cr);
11218   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11219 
11220   ins_cost(150);
11221   format %{ "orq     $dst, $src\t# long" %}
11222   ins_encode %{
11223     __ orq($dst$$Address, $src$$Register);
11224   %}
11225   ins_pipe(ialu_mem_reg);
11226 %}
11227 
11228 // Or Memory with Immediate
11229 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11230 %{
11231   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
11232   effect(KILL cr);
11233   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11234 
11235   ins_cost(125);
11236   format %{ "orq     $dst, $src\t# long" %}
11237   ins_encode %{
11238     __ orq($dst$$Address, $src$$constant);
11239   %}
11240   ins_pipe(ialu_mem_imm);
11241 %}
11242 
11243 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
11244 %{
11245   // con should be a pure 64-bit power of 2 immediate
11246   // because AND/OR works well enough for 8/32-bit values.
11247   predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
11248 
11249   match(Set dst (StoreL dst (OrL (LoadL dst) con)));
11250   effect(KILL cr);
11251 
11252   ins_cost(125);
11253   format %{ "btsq    $dst, log2($con)\t# long" %}
11254   ins_encode %{
11255     __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
11256   %}
11257   ins_pipe(ialu_mem_imm);
11258 %}
11259 
11260 // Xor Instructions
11261 // Xor Register with Register
11262 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
11263 %{
11264   predicate(!UseAPX);
11265   match(Set dst (XorL dst src));
11266   effect(KILL cr);
11267   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11268 
11269   format %{ "xorq    $dst, $src\t# long" %}
11270   ins_encode %{
11271     __ xorq($dst$$Register, $src$$Register);
11272   %}
11273   ins_pipe(ialu_reg_reg);
11274 %}
11275 
11276 // Xor Register with Register using New Data Destination (NDD)
11277 instruct xorL_rReg_ndd(rRegL dst, rRegL src1, rRegL src2, rFlagsReg cr)
11278 %{
11279   predicate(UseAPX);
11280   match(Set dst (XorL src1 src2));
11281   effect(KILL cr);
11282   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11283 
11284   format %{ "exorq    $dst, $src1, $src2\t# long ndd" %}
11285   ins_encode %{
11286     __ exorq($dst$$Register, $src1$$Register, $src2$$Register, false);
11287   %}
11288   ins_pipe(ialu_reg_reg);
11289 %}
11290 
11291 // Xor Register with Immediate -1
11292 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm)
11293 %{
11294   predicate(!UseAPX);
11295   match(Set dst (XorL dst imm));
11296 
11297   format %{ "notq   $dst" %}
11298   ins_encode %{
11299      __ notq($dst$$Register);
11300   %}
11301   ins_pipe(ialu_reg);
11302 %}
11303 
11304 instruct xorL_rReg_im1_ndd(rRegL dst,rRegL src, immL_M1 imm)
11305 %{
11306   predicate(UseAPX);
11307   match(Set dst (XorL src imm));
11308 
11309   format %{ "enotq   $dst, $src" %}
11310   ins_encode %{
11311     __ enotq($dst$$Register, $src$$Register);
11312   %}
11313   ins_pipe(ialu_reg);
11314 %}
11315 
11316 // Xor Register with Immediate
11317 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
11318 %{
11319   predicate(!UseAPX);
11320   match(Set dst (XorL dst src));
11321   effect(KILL cr);
11322   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11323 
11324   format %{ "xorq    $dst, $src\t# long" %}
11325   ins_encode %{
11326     __ xorq($dst$$Register, $src$$constant);
11327   %}
11328   ins_pipe(ialu_reg);
11329 %}
11330 
11331 instruct xorL_rReg_rReg_imm(rRegL dst, rRegL src1, immL32 src2, rFlagsReg cr)
11332 %{
11333   predicate(UseAPX);
11334   match(Set dst (XorL src1 src2));
11335   effect(KILL cr);
11336   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11337 
11338   format %{ "exorq    $dst, $src1, $src2\t# long ndd" %}
11339   ins_encode %{
11340     __ exorq($dst$$Register, $src1$$Register, $src2$$constant, false);
11341   %}
11342   ins_pipe(ialu_reg);
11343 %}
11344 
11345 // Xor Memory with Immediate
11346 instruct xorL_rReg_mem_imm(rRegL dst, memory src1, immL32 src2, rFlagsReg cr)
11347 %{
11348   predicate(UseAPX);
11349   match(Set dst (XorL (LoadL src1) src2));
11350   effect(KILL cr);
11351   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11352 
11353   format %{ "exorq    $dst, $src1, $src2\t# long ndd" %}
11354   ins_encode %{
11355     __ exorq($dst$$Register, $src1$$Address, $src2$$constant, false);
11356   %}
11357   ins_pipe(ialu_reg);
11358 %}
11359 
11360 // Xor Register with Memory
11361 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
11362 %{
11363   predicate(!UseAPX);
11364   match(Set dst (XorL dst (LoadL src)));
11365   effect(KILL cr);
11366   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11367 
11368   ins_cost(150);
11369   format %{ "xorq    $dst, $src\t# long" %}
11370   ins_encode %{
11371     __ xorq($dst$$Register, $src$$Address);
11372   %}
11373   ins_pipe(ialu_reg_mem);
11374 %}
11375 
11376 instruct xorL_rReg_rReg_mem_ndd(rRegL dst, rRegL src1, memory src2, rFlagsReg cr)
11377 %{
11378   predicate(UseAPX);
11379   match(Set dst (XorL src1 (LoadL src2)));
11380   effect(KILL cr);
11381   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11382 
11383   ins_cost(150);
11384   format %{ "exorq    $dst, $src1, $src2\t# long ndd" %}
11385   ins_encode %{
11386     __ exorq($dst$$Register, $src1$$Register, $src2$$Address, false);
11387   %}
11388   ins_pipe(ialu_reg_mem);
11389 %}
11390 
11391 instruct xorL_rReg_mem_rReg_ndd(rRegL dst, memory src1, rRegL src2, rFlagsReg cr)
11392 %{
11393   predicate(UseAPX);
11394   match(Set dst (XorL (LoadL src1) src2));
11395   effect(KILL cr);
11396   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11397 
11398   ins_cost(150);
11399   format %{ "exorq    $dst, $src1, $src2\t# long ndd" %}
11400   ins_encode %{
11401     __ exorq($dst$$Register, $src1$$Address, $src2$$Register, false);
11402   %}
11403   ins_pipe(ialu_reg_mem);
11404 %}
11405 
11406 // Xor Memory with Register
11407 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
11408 %{
11409   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11410   effect(KILL cr);
11411   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11412 
11413   ins_cost(150);
11414   format %{ "xorq    $dst, $src\t# long" %}
11415   ins_encode %{
11416     __ xorq($dst$$Address, $src$$Register);
11417   %}
11418   ins_pipe(ialu_mem_reg);
11419 %}
11420 
11421 // Xor Memory with Immediate
11422 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
11423 %{
11424   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
11425   effect(KILL cr);
11426   flag(PD::Flag_sets_sign_flag, PD::Flag_sets_zero_flag, PD::Flag_sets_parity_flag, PD::Flag_clears_overflow_flag, PD::Flag_clears_carry_flag);
11427 
11428   ins_cost(125);
11429   format %{ "xorq    $dst, $src\t# long" %}
11430   ins_encode %{
11431     __ xorq($dst$$Address, $src$$constant);
11432   %}
11433   ins_pipe(ialu_mem_imm);
11434 %}
11435 
11436 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
11437 %{
11438   match(Set dst (CmpLTMask p q));
11439   effect(KILL cr);
11440 
11441   ins_cost(400);
11442   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
11443             "setcc   $dst \t# emits setlt + movzbl or setzul for APX"
11444             "negl    $dst" %}
11445   ins_encode %{
11446     __ cmpl($p$$Register, $q$$Register);
11447     __ setcc(Assembler::less, $dst$$Register);
11448     __ negl($dst$$Register);
11449   %}
11450   ins_pipe(pipe_slow);
11451 %}
11452 
11453 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
11454 %{
11455   match(Set dst (CmpLTMask dst zero));
11456   effect(KILL cr);
11457 
11458   ins_cost(100);
11459   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
11460   ins_encode %{
11461     __ sarl($dst$$Register, 31);
11462   %}
11463   ins_pipe(ialu_reg);
11464 %}
11465 
11466 /* Better to save a register than avoid a branch */
11467 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11468 %{
11469   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
11470   effect(KILL cr);
11471   ins_cost(300);
11472   format %{ "subl    $p,$q\t# cadd_cmpLTMask\n\t"
11473             "jge     done\n\t"
11474             "addl    $p,$y\n"
11475             "done:   " %}
11476   ins_encode %{
11477     Register Rp = $p$$Register;
11478     Register Rq = $q$$Register;
11479     Register Ry = $y$$Register;
11480     Label done;
11481     __ subl(Rp, Rq);
11482     __ jccb(Assembler::greaterEqual, done);
11483     __ addl(Rp, Ry);
11484     __ bind(done);
11485   %}
11486   ins_pipe(pipe_cmplt);
11487 %}
11488 
11489 /* Better to save a register than avoid a branch */
11490 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
11491 %{
11492   match(Set y (AndI (CmpLTMask p q) y));
11493   effect(KILL cr);
11494 
11495   ins_cost(300);
11496 
11497   format %{ "cmpl    $p, $q\t# and_cmpLTMask\n\t"
11498             "jlt     done\n\t"
11499             "xorl    $y, $y\n"
11500             "done:   " %}
11501   ins_encode %{
11502     Register Rp = $p$$Register;
11503     Register Rq = $q$$Register;
11504     Register Ry = $y$$Register;
11505     Label done;
11506     __ cmpl(Rp, Rq);
11507     __ jccb(Assembler::less, done);
11508     __ xorl(Ry, Ry);
11509     __ bind(done);
11510   %}
11511   ins_pipe(pipe_cmplt);
11512 %}
11513 
11514 
11515 //---------- FP Instructions------------------------------------------------
11516 
11517 // Really expensive, avoid
11518 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
11519 %{
11520   match(Set cr (CmpF src1 src2));
11521 
11522   ins_cost(500);
11523   format %{ "ucomiss $src1, $src2\n\t"
11524             "jnp,s   exit\n\t"
11525             "pushfq\t# saw NaN, set CF\n\t"
11526             "andq    [rsp], #0xffffff2b\n\t"
11527             "popfq\n"
11528     "exit:" %}
11529   ins_encode %{
11530     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11531     emit_cmpfp_fixup(masm);
11532   %}
11533   ins_pipe(pipe_slow);
11534 %}
11535 
11536 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
11537   match(Set cr (CmpF src1 src2));
11538 
11539   ins_cost(100);
11540   format %{ "ucomiss $src1, $src2" %}
11541   ins_encode %{
11542     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11543   %}
11544   ins_pipe(pipe_slow);
11545 %}
11546 
11547 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
11548   match(Set cr (CmpF src1 (LoadF src2)));
11549 
11550   ins_cost(100);
11551   format %{ "ucomiss $src1, $src2" %}
11552   ins_encode %{
11553     __ ucomiss($src1$$XMMRegister, $src2$$Address);
11554   %}
11555   ins_pipe(pipe_slow);
11556 %}
11557 
11558 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
11559   match(Set cr (CmpF src con));
11560   ins_cost(100);
11561   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
11562   ins_encode %{
11563     __ ucomiss($src$$XMMRegister, $constantaddress($con));
11564   %}
11565   ins_pipe(pipe_slow);
11566 %}
11567 
11568 // Really expensive, avoid
11569 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
11570 %{
11571   match(Set cr (CmpD src1 src2));
11572 
11573   ins_cost(500);
11574   format %{ "ucomisd $src1, $src2\n\t"
11575             "jnp,s   exit\n\t"
11576             "pushfq\t# saw NaN, set CF\n\t"
11577             "andq    [rsp], #0xffffff2b\n\t"
11578             "popfq\n"
11579     "exit:" %}
11580   ins_encode %{
11581     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11582     emit_cmpfp_fixup(masm);
11583   %}
11584   ins_pipe(pipe_slow);
11585 %}
11586 
11587 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
11588   match(Set cr (CmpD src1 src2));
11589 
11590   ins_cost(100);
11591   format %{ "ucomisd $src1, $src2 test" %}
11592   ins_encode %{
11593     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11594   %}
11595   ins_pipe(pipe_slow);
11596 %}
11597 
11598 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
11599   match(Set cr (CmpD src1 (LoadD src2)));
11600 
11601   ins_cost(100);
11602   format %{ "ucomisd $src1, $src2" %}
11603   ins_encode %{
11604     __ ucomisd($src1$$XMMRegister, $src2$$Address);
11605   %}
11606   ins_pipe(pipe_slow);
11607 %}
11608 
11609 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
11610   match(Set cr (CmpD src con));
11611   ins_cost(100);
11612   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
11613   ins_encode %{
11614     __ ucomisd($src$$XMMRegister, $constantaddress($con));
11615   %}
11616   ins_pipe(pipe_slow);
11617 %}
11618 
11619 // Compare into -1,0,1
11620 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
11621 %{
11622   match(Set dst (CmpF3 src1 src2));
11623   effect(KILL cr);
11624 
11625   ins_cost(275);
11626   format %{ "ucomiss $src1, $src2\n\t"
11627             "movl    $dst, #-1\n\t"
11628             "jp,s    done\n\t"
11629             "jb,s    done\n\t"
11630             "setne   $dst\n\t"
11631             "movzbl  $dst, $dst\n"
11632     "done:" %}
11633   ins_encode %{
11634     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
11635     emit_cmpfp3(masm, $dst$$Register);
11636   %}
11637   ins_pipe(pipe_slow);
11638 %}
11639 
11640 // Compare into -1,0,1
11641 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
11642 %{
11643   match(Set dst (CmpF3 src1 (LoadF src2)));
11644   effect(KILL cr);
11645 
11646   ins_cost(275);
11647   format %{ "ucomiss $src1, $src2\n\t"
11648             "movl    $dst, #-1\n\t"
11649             "jp,s    done\n\t"
11650             "jb,s    done\n\t"
11651             "setne   $dst\n\t"
11652             "movzbl  $dst, $dst\n"
11653     "done:" %}
11654   ins_encode %{
11655     __ ucomiss($src1$$XMMRegister, $src2$$Address);
11656     emit_cmpfp3(masm, $dst$$Register);
11657   %}
11658   ins_pipe(pipe_slow);
11659 %}
11660 
11661 // Compare into -1,0,1
11662 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
11663   match(Set dst (CmpF3 src con));
11664   effect(KILL cr);
11665 
11666   ins_cost(275);
11667   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
11668             "movl    $dst, #-1\n\t"
11669             "jp,s    done\n\t"
11670             "jb,s    done\n\t"
11671             "setne   $dst\n\t"
11672             "movzbl  $dst, $dst\n"
11673     "done:" %}
11674   ins_encode %{
11675     __ ucomiss($src$$XMMRegister, $constantaddress($con));
11676     emit_cmpfp3(masm, $dst$$Register);
11677   %}
11678   ins_pipe(pipe_slow);
11679 %}
11680 
11681 // Compare into -1,0,1
11682 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
11683 %{
11684   match(Set dst (CmpD3 src1 src2));
11685   effect(KILL cr);
11686 
11687   ins_cost(275);
11688   format %{ "ucomisd $src1, $src2\n\t"
11689             "movl    $dst, #-1\n\t"
11690             "jp,s    done\n\t"
11691             "jb,s    done\n\t"
11692             "setne   $dst\n\t"
11693             "movzbl  $dst, $dst\n"
11694     "done:" %}
11695   ins_encode %{
11696     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
11697     emit_cmpfp3(masm, $dst$$Register);
11698   %}
11699   ins_pipe(pipe_slow);
11700 %}
11701 
11702 // Compare into -1,0,1
11703 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
11704 %{
11705   match(Set dst (CmpD3 src1 (LoadD src2)));
11706   effect(KILL cr);
11707 
11708   ins_cost(275);
11709   format %{ "ucomisd $src1, $src2\n\t"
11710             "movl    $dst, #-1\n\t"
11711             "jp,s    done\n\t"
11712             "jb,s    done\n\t"
11713             "setne   $dst\n\t"
11714             "movzbl  $dst, $dst\n"
11715     "done:" %}
11716   ins_encode %{
11717     __ ucomisd($src1$$XMMRegister, $src2$$Address);
11718     emit_cmpfp3(masm, $dst$$Register);
11719   %}
11720   ins_pipe(pipe_slow);
11721 %}
11722 
11723 // Compare into -1,0,1
11724 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
11725   match(Set dst (CmpD3 src con));
11726   effect(KILL cr);
11727 
11728   ins_cost(275);
11729   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
11730             "movl    $dst, #-1\n\t"
11731             "jp,s    done\n\t"
11732             "jb,s    done\n\t"
11733             "setne   $dst\n\t"
11734             "movzbl  $dst, $dst\n"
11735     "done:" %}
11736   ins_encode %{
11737     __ ucomisd($src$$XMMRegister, $constantaddress($con));
11738     emit_cmpfp3(masm, $dst$$Register);
11739   %}
11740   ins_pipe(pipe_slow);
11741 %}
11742 
11743 //----------Arithmetic Conversion Instructions---------------------------------
11744 
11745 instruct convF2D_reg_reg(regD dst, regF src)
11746 %{
11747   match(Set dst (ConvF2D src));
11748 
11749   format %{ "cvtss2sd $dst, $src" %}
11750   ins_encode %{
11751     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
11752   %}
11753   ins_pipe(pipe_slow); // XXX
11754 %}
11755 
11756 instruct convF2D_reg_mem(regD dst, memory src)
11757 %{
11758   predicate(UseAVX == 0);
11759   match(Set dst (ConvF2D (LoadF src)));
11760 
11761   format %{ "cvtss2sd $dst, $src" %}
11762   ins_encode %{
11763     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
11764   %}
11765   ins_pipe(pipe_slow); // XXX
11766 %}
11767 
11768 instruct convD2F_reg_reg(regF dst, regD src)
11769 %{
11770   match(Set dst (ConvD2F src));
11771 
11772   format %{ "cvtsd2ss $dst, $src" %}
11773   ins_encode %{
11774     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
11775   %}
11776   ins_pipe(pipe_slow); // XXX
11777 %}
11778 
11779 instruct convD2F_reg_mem(regF dst, memory src)
11780 %{
11781   predicate(UseAVX == 0);
11782   match(Set dst (ConvD2F (LoadD src)));
11783 
11784   format %{ "cvtsd2ss $dst, $src" %}
11785   ins_encode %{
11786     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
11787   %}
11788   ins_pipe(pipe_slow); // XXX
11789 %}
11790 
11791 // XXX do mem variants
11792 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
11793 %{
11794   match(Set dst (ConvF2I src));
11795   effect(KILL cr);
11796   format %{ "convert_f2i $dst, $src" %}
11797   ins_encode %{
11798     __ convertF2I(T_INT, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11799   %}
11800   ins_pipe(pipe_slow);
11801 %}
11802 
11803 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
11804 %{
11805   match(Set dst (ConvF2L src));
11806   effect(KILL cr);
11807   format %{ "convert_f2l $dst, $src"%}
11808   ins_encode %{
11809     __ convertF2I(T_LONG, T_FLOAT, $dst$$Register, $src$$XMMRegister);
11810   %}
11811   ins_pipe(pipe_slow);
11812 %}
11813 
11814 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
11815 %{
11816   match(Set dst (ConvD2I src));
11817   effect(KILL cr);
11818   format %{ "convert_d2i $dst, $src"%}
11819   ins_encode %{
11820     __ convertF2I(T_INT, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11821   %}
11822   ins_pipe(pipe_slow);
11823 %}
11824 
11825 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
11826 %{
11827   match(Set dst (ConvD2L src));
11828   effect(KILL cr);
11829   format %{ "convert_d2l $dst, $src"%}
11830   ins_encode %{
11831     __ convertF2I(T_LONG, T_DOUBLE, $dst$$Register, $src$$XMMRegister);
11832   %}
11833   ins_pipe(pipe_slow);
11834 %}
11835 
11836 instruct round_double_reg(rRegL dst, regD src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11837 %{
11838   match(Set dst (RoundD src));
11839   effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11840   format %{ "round_double $dst,$src \t! using $rtmp and $rcx as TEMP"%}
11841   ins_encode %{
11842     __ round_double($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11843   %}
11844   ins_pipe(pipe_slow);
11845 %}
11846 
11847 instruct round_float_reg(rRegI dst, regF src, rRegL rtmp, rcx_RegL rcx, rFlagsReg cr)
11848 %{
11849   match(Set dst (RoundF src));
11850   effect(TEMP dst, TEMP rtmp, TEMP rcx, KILL cr);
11851   format %{ "round_float $dst,$src" %}
11852   ins_encode %{
11853     __ round_float($dst$$Register, $src$$XMMRegister, $rtmp$$Register, $rcx$$Register);
11854   %}
11855   ins_pipe(pipe_slow);
11856 %}
11857 
11858 instruct convI2F_reg_reg(vlRegF dst, rRegI src)
11859 %{
11860   predicate(!UseXmmI2F);
11861   match(Set dst (ConvI2F src));
11862 
11863   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11864   ins_encode %{
11865     if (UseAVX > 0) {
11866       __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11867     }
11868     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
11869   %}
11870   ins_pipe(pipe_slow); // XXX
11871 %}
11872 
11873 instruct convI2F_reg_mem(regF dst, memory src)
11874 %{
11875   predicate(UseAVX == 0);
11876   match(Set dst (ConvI2F (LoadI src)));
11877 
11878   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
11879   ins_encode %{
11880     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
11881   %}
11882   ins_pipe(pipe_slow); // XXX
11883 %}
11884 
11885 instruct convI2D_reg_reg(vlRegD dst, rRegI src)
11886 %{
11887   predicate(!UseXmmI2D);
11888   match(Set dst (ConvI2D src));
11889 
11890   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11891   ins_encode %{
11892     if (UseAVX > 0) {
11893       __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11894     }
11895     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
11896   %}
11897   ins_pipe(pipe_slow); // XXX
11898 %}
11899 
11900 instruct convI2D_reg_mem(regD dst, memory src)
11901 %{
11902   predicate(UseAVX == 0);
11903   match(Set dst (ConvI2D (LoadI src)));
11904 
11905   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
11906   ins_encode %{
11907     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
11908   %}
11909   ins_pipe(pipe_slow); // XXX
11910 %}
11911 
11912 instruct convXI2F_reg(regF dst, rRegI src)
11913 %{
11914   predicate(UseXmmI2F);
11915   match(Set dst (ConvI2F src));
11916 
11917   format %{ "movdl $dst, $src\n\t"
11918             "cvtdq2psl $dst, $dst\t# i2f" %}
11919   ins_encode %{
11920     __ movdl($dst$$XMMRegister, $src$$Register);
11921     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
11922   %}
11923   ins_pipe(pipe_slow); // XXX
11924 %}
11925 
11926 instruct convXI2D_reg(regD dst, rRegI src)
11927 %{
11928   predicate(UseXmmI2D);
11929   match(Set dst (ConvI2D src));
11930 
11931   format %{ "movdl $dst, $src\n\t"
11932             "cvtdq2pdl $dst, $dst\t# i2d" %}
11933   ins_encode %{
11934     __ movdl($dst$$XMMRegister, $src$$Register);
11935     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
11936   %}
11937   ins_pipe(pipe_slow); // XXX
11938 %}
11939 
11940 instruct convL2F_reg_reg(vlRegF dst, rRegL src)
11941 %{
11942   match(Set dst (ConvL2F src));
11943 
11944   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11945   ins_encode %{
11946     if (UseAVX > 0) {
11947       __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11948     }
11949     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
11950   %}
11951   ins_pipe(pipe_slow); // XXX
11952 %}
11953 
11954 instruct convL2F_reg_mem(regF dst, memory src)
11955 %{
11956   predicate(UseAVX == 0);
11957   match(Set dst (ConvL2F (LoadL src)));
11958 
11959   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
11960   ins_encode %{
11961     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
11962   %}
11963   ins_pipe(pipe_slow); // XXX
11964 %}
11965 
11966 instruct convL2D_reg_reg(vlRegD dst, rRegL src)
11967 %{
11968   match(Set dst (ConvL2D src));
11969 
11970   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11971   ins_encode %{
11972     if (UseAVX > 0) {
11973       __ pxor($dst$$XMMRegister, $dst$$XMMRegister);
11974     }
11975     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
11976   %}
11977   ins_pipe(pipe_slow); // XXX
11978 %}
11979 
11980 instruct convL2D_reg_mem(regD dst, memory src)
11981 %{
11982   predicate(UseAVX == 0);
11983   match(Set dst (ConvL2D (LoadL src)));
11984 
11985   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
11986   ins_encode %{
11987     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
11988   %}
11989   ins_pipe(pipe_slow); // XXX
11990 %}
11991 
11992 instruct convI2L_reg_reg(rRegL dst, rRegI src)
11993 %{
11994   match(Set dst (ConvI2L src));
11995 
11996   ins_cost(125);
11997   format %{ "movslq  $dst, $src\t# i2l" %}
11998   ins_encode %{
11999     __ movslq($dst$$Register, $src$$Register);
12000   %}
12001   ins_pipe(ialu_reg_reg);
12002 %}
12003 
12004 // Zero-extend convert int to long
12005 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
12006 %{
12007   match(Set dst (AndL (ConvI2L src) mask));
12008 
12009   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
12010   ins_encode %{
12011     if ($dst$$reg != $src$$reg) {
12012       __ movl($dst$$Register, $src$$Register);
12013     }
12014   %}
12015   ins_pipe(ialu_reg_reg);
12016 %}
12017 
12018 // Zero-extend convert int to long
12019 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
12020 %{
12021   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
12022 
12023   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
12024   ins_encode %{
12025     __ movl($dst$$Register, $src$$Address);
12026   %}
12027   ins_pipe(ialu_reg_mem);
12028 %}
12029 
12030 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
12031 %{
12032   match(Set dst (AndL src mask));
12033 
12034   format %{ "movl    $dst, $src\t# zero-extend long" %}
12035   ins_encode %{
12036     __ movl($dst$$Register, $src$$Register);
12037   %}
12038   ins_pipe(ialu_reg_reg);
12039 %}
12040 
12041 instruct convL2I_reg_reg(rRegI dst, rRegL src)
12042 %{
12043   match(Set dst (ConvL2I src));
12044 
12045   format %{ "movl    $dst, $src\t# l2i" %}
12046   ins_encode %{
12047     __ movl($dst$$Register, $src$$Register);
12048   %}
12049   ins_pipe(ialu_reg_reg);
12050 %}
12051 
12052 
12053 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
12054   match(Set dst (MoveF2I src));
12055   effect(DEF dst, USE src);
12056 
12057   ins_cost(125);
12058   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
12059   ins_encode %{
12060     __ movl($dst$$Register, Address(rsp, $src$$disp));
12061   %}
12062   ins_pipe(ialu_reg_mem);
12063 %}
12064 
12065 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
12066   match(Set dst (MoveI2F src));
12067   effect(DEF dst, USE src);
12068 
12069   ins_cost(125);
12070   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
12071   ins_encode %{
12072     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
12073   %}
12074   ins_pipe(pipe_slow);
12075 %}
12076 
12077 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
12078   match(Set dst (MoveD2L src));
12079   effect(DEF dst, USE src);
12080 
12081   ins_cost(125);
12082   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
12083   ins_encode %{
12084     __ movq($dst$$Register, Address(rsp, $src$$disp));
12085   %}
12086   ins_pipe(ialu_reg_mem);
12087 %}
12088 
12089 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
12090   predicate(!UseXmmLoadAndClearUpper);
12091   match(Set dst (MoveL2D src));
12092   effect(DEF dst, USE src);
12093 
12094   ins_cost(125);
12095   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
12096   ins_encode %{
12097     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12098   %}
12099   ins_pipe(pipe_slow);
12100 %}
12101 
12102 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
12103   predicate(UseXmmLoadAndClearUpper);
12104   match(Set dst (MoveL2D src));
12105   effect(DEF dst, USE src);
12106 
12107   ins_cost(125);
12108   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
12109   ins_encode %{
12110     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
12111   %}
12112   ins_pipe(pipe_slow);
12113 %}
12114 
12115 
12116 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
12117   match(Set dst (MoveF2I src));
12118   effect(DEF dst, USE src);
12119 
12120   ins_cost(95); // XXX
12121   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
12122   ins_encode %{
12123     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
12124   %}
12125   ins_pipe(pipe_slow);
12126 %}
12127 
12128 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
12129   match(Set dst (MoveI2F src));
12130   effect(DEF dst, USE src);
12131 
12132   ins_cost(100);
12133   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
12134   ins_encode %{
12135     __ movl(Address(rsp, $dst$$disp), $src$$Register);
12136   %}
12137   ins_pipe( ialu_mem_reg );
12138 %}
12139 
12140 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
12141   match(Set dst (MoveD2L src));
12142   effect(DEF dst, USE src);
12143 
12144   ins_cost(95); // XXX
12145   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
12146   ins_encode %{
12147     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
12148   %}
12149   ins_pipe(pipe_slow);
12150 %}
12151 
12152 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
12153   match(Set dst (MoveL2D src));
12154   effect(DEF dst, USE src);
12155 
12156   ins_cost(100);
12157   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
12158   ins_encode %{
12159     __ movq(Address(rsp, $dst$$disp), $src$$Register);
12160   %}
12161   ins_pipe(ialu_mem_reg);
12162 %}
12163 
12164 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
12165   match(Set dst (MoveF2I src));
12166   effect(DEF dst, USE src);
12167   ins_cost(85);
12168   format %{ "movd    $dst,$src\t# MoveF2I" %}
12169   ins_encode %{
12170     __ movdl($dst$$Register, $src$$XMMRegister);
12171   %}
12172   ins_pipe( pipe_slow );
12173 %}
12174 
12175 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
12176   match(Set dst (MoveD2L src));
12177   effect(DEF dst, USE src);
12178   ins_cost(85);
12179   format %{ "movd    $dst,$src\t# MoveD2L" %}
12180   ins_encode %{
12181     __ movdq($dst$$Register, $src$$XMMRegister);
12182   %}
12183   ins_pipe( pipe_slow );
12184 %}
12185 
12186 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
12187   match(Set dst (MoveI2F src));
12188   effect(DEF dst, USE src);
12189   ins_cost(100);
12190   format %{ "movd    $dst,$src\t# MoveI2F" %}
12191   ins_encode %{
12192     __ movdl($dst$$XMMRegister, $src$$Register);
12193   %}
12194   ins_pipe( pipe_slow );
12195 %}
12196 
12197 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
12198   match(Set dst (MoveL2D src));
12199   effect(DEF dst, USE src);
12200   ins_cost(100);
12201   format %{ "movd    $dst,$src\t# MoveL2D" %}
12202   ins_encode %{
12203      __ movdq($dst$$XMMRegister, $src$$Register);
12204   %}
12205   ins_pipe( pipe_slow );
12206 %}
12207 
12208 // Fast clearing of an array
12209 // Small non-constant lenght ClearArray for non-AVX512 targets.
12210 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12211                   Universe dummy, rFlagsReg cr)
12212 %{
12213   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
12214   match(Set dummy (ClearArray cnt base));
12215   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12216 
12217   format %{ $$template
12218     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12219     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
12220     $$emit$$"jg      LARGE\n\t"
12221     $$emit$$"dec     rcx\n\t"
12222     $$emit$$"js      DONE\t# Zero length\n\t"
12223     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
12224     $$emit$$"dec     rcx\n\t"
12225     $$emit$$"jge     LOOP\n\t"
12226     $$emit$$"jmp     DONE\n\t"
12227     $$emit$$"# LARGE:\n\t"
12228     if (UseFastStosb) {
12229        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
12230        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
12231     } else if (UseXMMForObjInit) {
12232        $$emit$$"mov     rdi,rax\n\t"
12233        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
12234        $$emit$$"jmpq    L_zero_64_bytes\n\t"
12235        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12236        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12237        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12238        $$emit$$"add     0x40,rax\n\t"
12239        $$emit$$"# L_zero_64_bytes:\n\t"
12240        $$emit$$"sub     0x8,rcx\n\t"
12241        $$emit$$"jge     L_loop\n\t"
12242        $$emit$$"add     0x4,rcx\n\t"
12243        $$emit$$"jl      L_tail\n\t"
12244        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12245        $$emit$$"add     0x20,rax\n\t"
12246        $$emit$$"sub     0x4,rcx\n\t"
12247        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12248        $$emit$$"add     0x4,rcx\n\t"
12249        $$emit$$"jle     L_end\n\t"
12250        $$emit$$"dec     rcx\n\t"
12251        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12252        $$emit$$"vmovq   xmm0,(rax)\n\t"
12253        $$emit$$"add     0x8,rax\n\t"
12254        $$emit$$"dec     rcx\n\t"
12255        $$emit$$"jge     L_sloop\n\t"
12256        $$emit$$"# L_end:\n\t"
12257     } else {
12258        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
12259     }
12260     $$emit$$"# DONE"
12261   %}
12262   ins_encode %{
12263     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12264                  $tmp$$XMMRegister, false, knoreg);
12265   %}
12266   ins_pipe(pipe_slow);
12267 %}
12268 
12269 // Small non-constant length ClearArray for AVX512 targets.
12270 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12271                        Universe dummy, rFlagsReg cr)
12272 %{
12273   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
12274   match(Set dummy (ClearArray cnt base));
12275   ins_cost(125);
12276   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12277 
12278   format %{ $$template
12279     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12280     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
12281     $$emit$$"jg      LARGE\n\t"
12282     $$emit$$"dec     rcx\n\t"
12283     $$emit$$"js      DONE\t# Zero length\n\t"
12284     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
12285     $$emit$$"dec     rcx\n\t"
12286     $$emit$$"jge     LOOP\n\t"
12287     $$emit$$"jmp     DONE\n\t"
12288     $$emit$$"# LARGE:\n\t"
12289     if (UseFastStosb) {
12290        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
12291        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
12292     } else if (UseXMMForObjInit) {
12293        $$emit$$"mov     rdi,rax\n\t"
12294        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
12295        $$emit$$"jmpq    L_zero_64_bytes\n\t"
12296        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12297        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12298        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12299        $$emit$$"add     0x40,rax\n\t"
12300        $$emit$$"# L_zero_64_bytes:\n\t"
12301        $$emit$$"sub     0x8,rcx\n\t"
12302        $$emit$$"jge     L_loop\n\t"
12303        $$emit$$"add     0x4,rcx\n\t"
12304        $$emit$$"jl      L_tail\n\t"
12305        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12306        $$emit$$"add     0x20,rax\n\t"
12307        $$emit$$"sub     0x4,rcx\n\t"
12308        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12309        $$emit$$"add     0x4,rcx\n\t"
12310        $$emit$$"jle     L_end\n\t"
12311        $$emit$$"dec     rcx\n\t"
12312        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12313        $$emit$$"vmovq   xmm0,(rax)\n\t"
12314        $$emit$$"add     0x8,rax\n\t"
12315        $$emit$$"dec     rcx\n\t"
12316        $$emit$$"jge     L_sloop\n\t"
12317        $$emit$$"# L_end:\n\t"
12318     } else {
12319        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
12320     }
12321     $$emit$$"# DONE"
12322   %}
12323   ins_encode %{
12324     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12325                  $tmp$$XMMRegister, false, $ktmp$$KRegister);
12326   %}
12327   ins_pipe(pipe_slow);
12328 %}
12329 
12330 // Large non-constant length ClearArray for non-AVX512 targets.
12331 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
12332                         Universe dummy, rFlagsReg cr)
12333 %{
12334   predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
12335   match(Set dummy (ClearArray cnt base));
12336   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
12337 
12338   format %{ $$template
12339     if (UseFastStosb) {
12340        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12341        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
12342        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
12343     } else if (UseXMMForObjInit) {
12344        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
12345        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
12346        $$emit$$"jmpq    L_zero_64_bytes\n\t"
12347        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12348        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12349        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12350        $$emit$$"add     0x40,rax\n\t"
12351        $$emit$$"# L_zero_64_bytes:\n\t"
12352        $$emit$$"sub     0x8,rcx\n\t"
12353        $$emit$$"jge     L_loop\n\t"
12354        $$emit$$"add     0x4,rcx\n\t"
12355        $$emit$$"jl      L_tail\n\t"
12356        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12357        $$emit$$"add     0x20,rax\n\t"
12358        $$emit$$"sub     0x4,rcx\n\t"
12359        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12360        $$emit$$"add     0x4,rcx\n\t"
12361        $$emit$$"jle     L_end\n\t"
12362        $$emit$$"dec     rcx\n\t"
12363        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12364        $$emit$$"vmovq   xmm0,(rax)\n\t"
12365        $$emit$$"add     0x8,rax\n\t"
12366        $$emit$$"dec     rcx\n\t"
12367        $$emit$$"jge     L_sloop\n\t"
12368        $$emit$$"# L_end:\n\t"
12369     } else {
12370        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12371        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
12372     }
12373   %}
12374   ins_encode %{
12375     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12376                  $tmp$$XMMRegister, true, knoreg);
12377   %}
12378   ins_pipe(pipe_slow);
12379 %}
12380 
12381 // Large non-constant length ClearArray for AVX512 targets.
12382 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
12383                              Universe dummy, rFlagsReg cr)
12384 %{
12385   predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
12386   match(Set dummy (ClearArray cnt base));
12387   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
12388 
12389   format %{ $$template
12390     if (UseFastStosb) {
12391        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12392        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
12393        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
12394     } else if (UseXMMForObjInit) {
12395        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
12396        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
12397        $$emit$$"jmpq    L_zero_64_bytes\n\t"
12398        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
12399        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12400        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
12401        $$emit$$"add     0x40,rax\n\t"
12402        $$emit$$"# L_zero_64_bytes:\n\t"
12403        $$emit$$"sub     0x8,rcx\n\t"
12404        $$emit$$"jge     L_loop\n\t"
12405        $$emit$$"add     0x4,rcx\n\t"
12406        $$emit$$"jl      L_tail\n\t"
12407        $$emit$$"vmovdqu ymm0,(rax)\n\t"
12408        $$emit$$"add     0x20,rax\n\t"
12409        $$emit$$"sub     0x4,rcx\n\t"
12410        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
12411        $$emit$$"add     0x4,rcx\n\t"
12412        $$emit$$"jle     L_end\n\t"
12413        $$emit$$"dec     rcx\n\t"
12414        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
12415        $$emit$$"vmovq   xmm0,(rax)\n\t"
12416        $$emit$$"add     0x8,rax\n\t"
12417        $$emit$$"dec     rcx\n\t"
12418        $$emit$$"jge     L_sloop\n\t"
12419        $$emit$$"# L_end:\n\t"
12420     } else {
12421        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
12422        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
12423     }
12424   %}
12425   ins_encode %{
12426     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
12427                  $tmp$$XMMRegister, true, $ktmp$$KRegister);
12428   %}
12429   ins_pipe(pipe_slow);
12430 %}
12431 
12432 // Small constant length ClearArray for AVX512 targets.
12433 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
12434 %{
12435   predicate(!((ClearArrayNode*)n)->is_large() && (MaxVectorSize >= 32) && VM_Version::supports_avx512vl());
12436   match(Set dummy (ClearArray cnt base));
12437   ins_cost(100);
12438   effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
12439   format %{ "clear_mem_imm $base , $cnt  \n\t" %}
12440   ins_encode %{
12441    __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
12442   %}
12443   ins_pipe(pipe_slow);
12444 %}
12445 
12446 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12447                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
12448 %{
12449   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12450   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12451   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12452 
12453   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12454   ins_encode %{
12455     __ string_compare($str1$$Register, $str2$$Register,
12456                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12457                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
12458   %}
12459   ins_pipe( pipe_slow );
12460 %}
12461 
12462 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12463                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12464 %{
12465   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
12466   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12467   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12468 
12469   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12470   ins_encode %{
12471     __ string_compare($str1$$Register, $str2$$Register,
12472                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12473                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
12474   %}
12475   ins_pipe( pipe_slow );
12476 %}
12477 
12478 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12479                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
12480 %{
12481   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12482   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12483   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12484 
12485   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12486   ins_encode %{
12487     __ string_compare($str1$$Register, $str2$$Register,
12488                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12489                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
12490   %}
12491   ins_pipe( pipe_slow );
12492 %}
12493 
12494 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12495                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12496 %{
12497   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
12498   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12499   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12500 
12501   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12502   ins_encode %{
12503     __ string_compare($str1$$Register, $str2$$Register,
12504                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12505                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
12506   %}
12507   ins_pipe( pipe_slow );
12508 %}
12509 
12510 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12511                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
12512 %{
12513   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12514   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12515   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12516 
12517   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12518   ins_encode %{
12519     __ string_compare($str1$$Register, $str2$$Register,
12520                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12521                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
12522   %}
12523   ins_pipe( pipe_slow );
12524 %}
12525 
12526 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
12527                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12528 %{
12529   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
12530   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12531   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12532 
12533   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12534   ins_encode %{
12535     __ string_compare($str1$$Register, $str2$$Register,
12536                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
12537                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
12538   %}
12539   ins_pipe( pipe_slow );
12540 %}
12541 
12542 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12543                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
12544 %{
12545   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12546   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12547   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12548 
12549   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12550   ins_encode %{
12551     __ string_compare($str2$$Register, $str1$$Register,
12552                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
12553                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
12554   %}
12555   ins_pipe( pipe_slow );
12556 %}
12557 
12558 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
12559                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
12560 %{
12561   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
12562   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
12563   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
12564 
12565   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
12566   ins_encode %{
12567     __ string_compare($str2$$Register, $str1$$Register,
12568                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
12569                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
12570   %}
12571   ins_pipe( pipe_slow );
12572 %}
12573 
12574 // fast search of substring with known size.
12575 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12576                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12577 %{
12578   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12579   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12580   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12581 
12582   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12583   ins_encode %{
12584     int icnt2 = (int)$int_cnt2$$constant;
12585     if (icnt2 >= 16) {
12586       // IndexOf for constant substrings with size >= 16 elements
12587       // which don't need to be loaded through stack.
12588       __ string_indexofC8($str1$$Register, $str2$$Register,
12589                           $cnt1$$Register, $cnt2$$Register,
12590                           icnt2, $result$$Register,
12591                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12592     } else {
12593       // Small strings are loaded through stack if they cross page boundary.
12594       __ string_indexof($str1$$Register, $str2$$Register,
12595                         $cnt1$$Register, $cnt2$$Register,
12596                         icnt2, $result$$Register,
12597                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12598     }
12599   %}
12600   ins_pipe( pipe_slow );
12601 %}
12602 
12603 // fast search of substring with known size.
12604 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12605                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12606 %{
12607   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12608   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12609   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12610 
12611   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12612   ins_encode %{
12613     int icnt2 = (int)$int_cnt2$$constant;
12614     if (icnt2 >= 8) {
12615       // IndexOf for constant substrings with size >= 8 elements
12616       // which don't need to be loaded through stack.
12617       __ string_indexofC8($str1$$Register, $str2$$Register,
12618                           $cnt1$$Register, $cnt2$$Register,
12619                           icnt2, $result$$Register,
12620                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12621     } else {
12622       // Small strings are loaded through stack if they cross page boundary.
12623       __ string_indexof($str1$$Register, $str2$$Register,
12624                         $cnt1$$Register, $cnt2$$Register,
12625                         icnt2, $result$$Register,
12626                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12627     }
12628   %}
12629   ins_pipe( pipe_slow );
12630 %}
12631 
12632 // fast search of substring with known size.
12633 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
12634                               rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
12635 %{
12636   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12637   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
12638   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
12639 
12640   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
12641   ins_encode %{
12642     int icnt2 = (int)$int_cnt2$$constant;
12643     if (icnt2 >= 8) {
12644       // IndexOf for constant substrings with size >= 8 elements
12645       // which don't need to be loaded through stack.
12646       __ string_indexofC8($str1$$Register, $str2$$Register,
12647                           $cnt1$$Register, $cnt2$$Register,
12648                           icnt2, $result$$Register,
12649                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12650     } else {
12651       // Small strings are loaded through stack if they cross page boundary.
12652       __ string_indexof($str1$$Register, $str2$$Register,
12653                         $cnt1$$Register, $cnt2$$Register,
12654                         icnt2, $result$$Register,
12655                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12656     }
12657   %}
12658   ins_pipe( pipe_slow );
12659 %}
12660 
12661 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12662                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12663 %{
12664   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
12665   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12666   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12667 
12668   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
12669   ins_encode %{
12670     __ string_indexof($str1$$Register, $str2$$Register,
12671                       $cnt1$$Register, $cnt2$$Register,
12672                       (-1), $result$$Register,
12673                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
12674   %}
12675   ins_pipe( pipe_slow );
12676 %}
12677 
12678 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12679                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12680 %{
12681   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
12682   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12683   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12684 
12685   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
12686   ins_encode %{
12687     __ string_indexof($str1$$Register, $str2$$Register,
12688                       $cnt1$$Register, $cnt2$$Register,
12689                       (-1), $result$$Register,
12690                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
12691   %}
12692   ins_pipe( pipe_slow );
12693 %}
12694 
12695 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
12696                           rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
12697 %{
12698   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
12699   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
12700   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
12701 
12702   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
12703   ins_encode %{
12704     __ string_indexof($str1$$Register, $str2$$Register,
12705                       $cnt1$$Register, $cnt2$$Register,
12706                       (-1), $result$$Register,
12707                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
12708   %}
12709   ins_pipe( pipe_slow );
12710 %}
12711 
12712 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12713                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12714 %{
12715   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
12716   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12717   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12718   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
12719   ins_encode %{
12720     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12721                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12722   %}
12723   ins_pipe( pipe_slow );
12724 %}
12725 
12726 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
12727                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
12728 %{
12729   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
12730   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
12731   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
12732   format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
12733   ins_encode %{
12734     __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
12735                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
12736   %}
12737   ins_pipe( pipe_slow );
12738 %}
12739 
12740 // fast string equals
12741 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12742                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
12743 %{
12744   predicate(!VM_Version::supports_avx512vlbw());
12745   match(Set result (StrEquals (Binary str1 str2) cnt));
12746   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12747 
12748   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
12749   ins_encode %{
12750     __ arrays_equals(false, $str1$$Register, $str2$$Register,
12751                      $cnt$$Register, $result$$Register, $tmp3$$Register,
12752                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12753   %}
12754   ins_pipe( pipe_slow );
12755 %}
12756 
12757 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
12758                            legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
12759 %{
12760   predicate(VM_Version::supports_avx512vlbw());
12761   match(Set result (StrEquals (Binary str1 str2) cnt));
12762   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
12763 
12764   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
12765   ins_encode %{
12766     __ arrays_equals(false, $str1$$Register, $str2$$Register,
12767                      $cnt$$Register, $result$$Register, $tmp3$$Register,
12768                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12769   %}
12770   ins_pipe( pipe_slow );
12771 %}
12772 
12773 // fast array equals
12774 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12775                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12776 %{
12777   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12778   match(Set result (AryEq ary1 ary2));
12779   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12780 
12781   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12782   ins_encode %{
12783     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12784                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
12785                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
12786   %}
12787   ins_pipe( pipe_slow );
12788 %}
12789 
12790 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12791                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12792 %{
12793   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
12794   match(Set result (AryEq ary1 ary2));
12795   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12796 
12797   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12798   ins_encode %{
12799     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12800                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
12801                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
12802   %}
12803   ins_pipe( pipe_slow );
12804 %}
12805 
12806 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12807                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12808 %{
12809   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12810   match(Set result (AryEq ary1 ary2));
12811   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12812 
12813   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12814   ins_encode %{
12815     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12816                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
12817                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
12818   %}
12819   ins_pipe( pipe_slow );
12820 %}
12821 
12822 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
12823                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
12824 %{
12825   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
12826   match(Set result (AryEq ary1 ary2));
12827   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
12828 
12829   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
12830   ins_encode %{
12831     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
12832                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
12833                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
12834   %}
12835   ins_pipe( pipe_slow );
12836 %}
12837 
12838 instruct arrays_hashcode(rdi_RegP ary1, rdx_RegI cnt1, rbx_RegI result, immU8 basic_type,
12839                          legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, legRegD tmp_vec4,
12840                          legRegD tmp_vec5, legRegD tmp_vec6, legRegD tmp_vec7, legRegD tmp_vec8,
12841                          legRegD tmp_vec9, legRegD tmp_vec10, legRegD tmp_vec11, legRegD tmp_vec12,
12842                          legRegD tmp_vec13, rRegI tmp1, rRegI tmp2, rRegI tmp3, rFlagsReg cr)
12843 %{
12844   predicate(UseAVX >= 2);
12845   match(Set result (VectorizedHashCode (Binary ary1 cnt1) (Binary result basic_type)));
12846   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, TEMP tmp_vec4, TEMP tmp_vec5, TEMP tmp_vec6,
12847          TEMP tmp_vec7, TEMP tmp_vec8, TEMP tmp_vec9, TEMP tmp_vec10, TEMP tmp_vec11, TEMP tmp_vec12,
12848          TEMP tmp_vec13, TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL ary1, USE_KILL cnt1,
12849          USE basic_type, KILL cr);
12850 
12851   format %{ "Array HashCode array[] $ary1,$cnt1,$result,$basic_type -> $result   // KILL all" %}
12852   ins_encode %{
12853     __ arrays_hashcode($ary1$$Register, $cnt1$$Register, $result$$Register,
12854                        $tmp1$$Register, $tmp2$$Register, $tmp3$$Register,
12855                        $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister,
12856                        $tmp_vec4$$XMMRegister, $tmp_vec5$$XMMRegister, $tmp_vec6$$XMMRegister,
12857                        $tmp_vec7$$XMMRegister, $tmp_vec8$$XMMRegister, $tmp_vec9$$XMMRegister,
12858                        $tmp_vec10$$XMMRegister, $tmp_vec11$$XMMRegister, $tmp_vec12$$XMMRegister,
12859                        $tmp_vec13$$XMMRegister, (BasicType)$basic_type$$constant);
12860   %}
12861   ins_pipe( pipe_slow );
12862 %}
12863 
12864 instruct count_positives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12865                          legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
12866 %{
12867   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12868   match(Set result (CountPositives ary1 len));
12869   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12870 
12871   format %{ "countPositives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
12872   ins_encode %{
12873     __ count_positives($ary1$$Register, $len$$Register,
12874                        $result$$Register, $tmp3$$Register,
12875                        $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
12876   %}
12877   ins_pipe( pipe_slow );
12878 %}
12879 
12880 instruct count_positives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
12881                               legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
12882 %{
12883   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12884   match(Set result (CountPositives ary1 len));
12885   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
12886 
12887   format %{ "countPositives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
12888   ins_encode %{
12889     __ count_positives($ary1$$Register, $len$$Register,
12890                        $result$$Register, $tmp3$$Register,
12891                        $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
12892   %}
12893   ins_pipe( pipe_slow );
12894 %}
12895 
12896 // fast char[] to byte[] compression
12897 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12898                          legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12899   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12900   match(Set result (StrCompressedCopy src (Binary dst len)));
12901   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
12902          USE_KILL len, KILL tmp5, KILL cr);
12903 
12904   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
12905   ins_encode %{
12906     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12907                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12908                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12909                            knoreg, knoreg);
12910   %}
12911   ins_pipe( pipe_slow );
12912 %}
12913 
12914 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
12915                               legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12916   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12917   match(Set result (StrCompressedCopy src (Binary dst len)));
12918   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
12919          USE_KILL len, KILL tmp5, KILL cr);
12920 
12921   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
12922   ins_encode %{
12923     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
12924                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12925                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
12926                            $ktmp1$$KRegister, $ktmp2$$KRegister);
12927   %}
12928   ins_pipe( pipe_slow );
12929 %}
12930 // fast byte[] to char[] inflation
12931 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12932                         legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
12933   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
12934   match(Set dummy (StrInflatedCopy src (Binary dst len)));
12935   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12936 
12937   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
12938   ins_encode %{
12939     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12940                           $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
12941   %}
12942   ins_pipe( pipe_slow );
12943 %}
12944 
12945 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12946                              legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
12947   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
12948   match(Set dummy (StrInflatedCopy src (Binary dst len)));
12949   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
12950 
12951   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
12952   ins_encode %{
12953     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
12954                           $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
12955   %}
12956   ins_pipe( pipe_slow );
12957 %}
12958 
12959 // encode char[] to byte[] in ISO_8859_1
12960 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12961                           legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12962                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12963   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
12964   match(Set result (EncodeISOArray src (Binary dst len)));
12965   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12966 
12967   format %{ "Encode iso array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12968   ins_encode %{
12969     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12970                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12971                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
12972   %}
12973   ins_pipe( pipe_slow );
12974 %}
12975 
12976 // encode char[] to byte[] in ASCII
12977 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
12978                             legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
12979                             rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
12980   predicate(((EncodeISOArrayNode*)n)->is_ascii());
12981   match(Set result (EncodeISOArray src (Binary dst len)));
12982   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
12983 
12984   format %{ "Encode ascii array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
12985   ins_encode %{
12986     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
12987                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
12988                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
12989   %}
12990   ins_pipe( pipe_slow );
12991 %}
12992 
12993 //----------Overflow Math Instructions-----------------------------------------
12994 
12995 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
12996 %{
12997   match(Set cr (OverflowAddI op1 op2));
12998   effect(DEF cr, USE_KILL op1, USE op2);
12999 
13000   format %{ "addl    $op1, $op2\t# overflow check int" %}
13001 
13002   ins_encode %{
13003     __ addl($op1$$Register, $op2$$Register);
13004   %}
13005   ins_pipe(ialu_reg_reg);
13006 %}
13007 
13008 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
13009 %{
13010   match(Set cr (OverflowAddI op1 op2));
13011   effect(DEF cr, USE_KILL op1, USE op2);
13012 
13013   format %{ "addl    $op1, $op2\t# overflow check int" %}
13014 
13015   ins_encode %{
13016     __ addl($op1$$Register, $op2$$constant);
13017   %}
13018   ins_pipe(ialu_reg_reg);
13019 %}
13020 
13021 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13022 %{
13023   match(Set cr (OverflowAddL op1 op2));
13024   effect(DEF cr, USE_KILL op1, USE op2);
13025 
13026   format %{ "addq    $op1, $op2\t# overflow check long" %}
13027   ins_encode %{
13028     __ addq($op1$$Register, $op2$$Register);
13029   %}
13030   ins_pipe(ialu_reg_reg);
13031 %}
13032 
13033 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
13034 %{
13035   match(Set cr (OverflowAddL op1 op2));
13036   effect(DEF cr, USE_KILL op1, USE op2);
13037 
13038   format %{ "addq    $op1, $op2\t# overflow check long" %}
13039   ins_encode %{
13040     __ addq($op1$$Register, $op2$$constant);
13041   %}
13042   ins_pipe(ialu_reg_reg);
13043 %}
13044 
13045 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13046 %{
13047   match(Set cr (OverflowSubI op1 op2));
13048 
13049   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
13050   ins_encode %{
13051     __ cmpl($op1$$Register, $op2$$Register);
13052   %}
13053   ins_pipe(ialu_reg_reg);
13054 %}
13055 
13056 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13057 %{
13058   match(Set cr (OverflowSubI op1 op2));
13059 
13060   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
13061   ins_encode %{
13062     __ cmpl($op1$$Register, $op2$$constant);
13063   %}
13064   ins_pipe(ialu_reg_reg);
13065 %}
13066 
13067 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13068 %{
13069   match(Set cr (OverflowSubL op1 op2));
13070 
13071   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
13072   ins_encode %{
13073     __ cmpq($op1$$Register, $op2$$Register);
13074   %}
13075   ins_pipe(ialu_reg_reg);
13076 %}
13077 
13078 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13079 %{
13080   match(Set cr (OverflowSubL op1 op2));
13081 
13082   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
13083   ins_encode %{
13084     __ cmpq($op1$$Register, $op2$$constant);
13085   %}
13086   ins_pipe(ialu_reg_reg);
13087 %}
13088 
13089 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
13090 %{
13091   match(Set cr (OverflowSubI zero op2));
13092   effect(DEF cr, USE_KILL op2);
13093 
13094   format %{ "negl    $op2\t# overflow check int" %}
13095   ins_encode %{
13096     __ negl($op2$$Register);
13097   %}
13098   ins_pipe(ialu_reg_reg);
13099 %}
13100 
13101 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
13102 %{
13103   match(Set cr (OverflowSubL zero op2));
13104   effect(DEF cr, USE_KILL op2);
13105 
13106   format %{ "negq    $op2\t# overflow check long" %}
13107   ins_encode %{
13108     __ negq($op2$$Register);
13109   %}
13110   ins_pipe(ialu_reg_reg);
13111 %}
13112 
13113 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
13114 %{
13115   match(Set cr (OverflowMulI op1 op2));
13116   effect(DEF cr, USE_KILL op1, USE op2);
13117 
13118   format %{ "imull    $op1, $op2\t# overflow check int" %}
13119   ins_encode %{
13120     __ imull($op1$$Register, $op2$$Register);
13121   %}
13122   ins_pipe(ialu_reg_reg_alu0);
13123 %}
13124 
13125 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
13126 %{
13127   match(Set cr (OverflowMulI op1 op2));
13128   effect(DEF cr, TEMP tmp, USE op1, USE op2);
13129 
13130   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
13131   ins_encode %{
13132     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
13133   %}
13134   ins_pipe(ialu_reg_reg_alu0);
13135 %}
13136 
13137 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
13138 %{
13139   match(Set cr (OverflowMulL op1 op2));
13140   effect(DEF cr, USE_KILL op1, USE op2);
13141 
13142   format %{ "imulq    $op1, $op2\t# overflow check long" %}
13143   ins_encode %{
13144     __ imulq($op1$$Register, $op2$$Register);
13145   %}
13146   ins_pipe(ialu_reg_reg_alu0);
13147 %}
13148 
13149 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
13150 %{
13151   match(Set cr (OverflowMulL op1 op2));
13152   effect(DEF cr, TEMP tmp, USE op1, USE op2);
13153 
13154   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
13155   ins_encode %{
13156     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
13157   %}
13158   ins_pipe(ialu_reg_reg_alu0);
13159 %}
13160 
13161 
13162 //----------Control Flow Instructions------------------------------------------
13163 // Signed compare Instructions
13164 
13165 // XXX more variants!!
13166 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
13167 %{
13168   match(Set cr (CmpI op1 op2));
13169   effect(DEF cr, USE op1, USE op2);
13170 
13171   format %{ "cmpl    $op1, $op2" %}
13172   ins_encode %{
13173     __ cmpl($op1$$Register, $op2$$Register);
13174   %}
13175   ins_pipe(ialu_cr_reg_reg);
13176 %}
13177 
13178 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
13179 %{
13180   match(Set cr (CmpI op1 op2));
13181 
13182   format %{ "cmpl    $op1, $op2" %}
13183   ins_encode %{
13184     __ cmpl($op1$$Register, $op2$$constant);
13185   %}
13186   ins_pipe(ialu_cr_reg_imm);
13187 %}
13188 
13189 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
13190 %{
13191   match(Set cr (CmpI op1 (LoadI op2)));
13192 
13193   ins_cost(500); // XXX
13194   format %{ "cmpl    $op1, $op2" %}
13195   ins_encode %{
13196     __ cmpl($op1$$Register, $op2$$Address);
13197   %}
13198   ins_pipe(ialu_cr_reg_mem);
13199 %}
13200 
13201 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
13202 %{
13203   match(Set cr (CmpI src zero));
13204 
13205   format %{ "testl   $src, $src" %}
13206   ins_encode %{
13207     __ testl($src$$Register, $src$$Register);
13208   %}
13209   ins_pipe(ialu_cr_reg_imm);
13210 %}
13211 
13212 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
13213 %{
13214   match(Set cr (CmpI (AndI src con) zero));
13215 
13216   format %{ "testl   $src, $con" %}
13217   ins_encode %{
13218     __ testl($src$$Register, $con$$constant);
13219   %}
13220   ins_pipe(ialu_cr_reg_imm);
13221 %}
13222 
13223 instruct testI_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2, immI_0 zero)
13224 %{
13225   match(Set cr (CmpI (AndI src1 src2) zero));
13226 
13227   format %{ "testl   $src1, $src2" %}
13228   ins_encode %{
13229     __ testl($src1$$Register, $src2$$Register);
13230   %}
13231   ins_pipe(ialu_cr_reg_imm);
13232 %}
13233 
13234 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
13235 %{
13236   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
13237 
13238   format %{ "testl   $src, $mem" %}
13239   ins_encode %{
13240     __ testl($src$$Register, $mem$$Address);
13241   %}
13242   ins_pipe(ialu_cr_reg_mem);
13243 %}
13244 
13245 // Unsigned compare Instructions; really, same as signed except they
13246 // produce an rFlagsRegU instead of rFlagsReg.
13247 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
13248 %{
13249   match(Set cr (CmpU op1 op2));
13250 
13251   format %{ "cmpl    $op1, $op2\t# unsigned" %}
13252   ins_encode %{
13253     __ cmpl($op1$$Register, $op2$$Register);
13254   %}
13255   ins_pipe(ialu_cr_reg_reg);
13256 %}
13257 
13258 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
13259 %{
13260   match(Set cr (CmpU op1 op2));
13261 
13262   format %{ "cmpl    $op1, $op2\t# unsigned" %}
13263   ins_encode %{
13264     __ cmpl($op1$$Register, $op2$$constant);
13265   %}
13266   ins_pipe(ialu_cr_reg_imm);
13267 %}
13268 
13269 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
13270 %{
13271   match(Set cr (CmpU op1 (LoadI op2)));
13272 
13273   ins_cost(500); // XXX
13274   format %{ "cmpl    $op1, $op2\t# unsigned" %}
13275   ins_encode %{
13276     __ cmpl($op1$$Register, $op2$$Address);
13277   %}
13278   ins_pipe(ialu_cr_reg_mem);
13279 %}
13280 
13281 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
13282 %{
13283   match(Set cr (CmpU src zero));
13284 
13285   format %{ "testl   $src, $src\t# unsigned" %}
13286   ins_encode %{
13287     __ testl($src$$Register, $src$$Register);
13288   %}
13289   ins_pipe(ialu_cr_reg_imm);
13290 %}
13291 
13292 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
13293 %{
13294   match(Set cr (CmpP op1 op2));
13295 
13296   format %{ "cmpq    $op1, $op2\t# ptr" %}
13297   ins_encode %{
13298     __ cmpq($op1$$Register, $op2$$Register);
13299   %}
13300   ins_pipe(ialu_cr_reg_reg);
13301 %}
13302 
13303 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
13304 %{
13305   match(Set cr (CmpP op1 (LoadP op2)));
13306   predicate(n->in(2)->as_Load()->barrier_data() == 0);
13307 
13308   ins_cost(500); // XXX
13309   format %{ "cmpq    $op1, $op2\t# ptr" %}
13310   ins_encode %{
13311     __ cmpq($op1$$Register, $op2$$Address);
13312   %}
13313   ins_pipe(ialu_cr_reg_mem);
13314 %}
13315 
13316 // XXX this is generalized by compP_rReg_mem???
13317 // Compare raw pointer (used in out-of-heap check).
13318 // Only works because non-oop pointers must be raw pointers
13319 // and raw pointers have no anti-dependencies.
13320 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
13321 %{
13322   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
13323             n->in(2)->as_Load()->barrier_data() == 0);
13324   match(Set cr (CmpP op1 (LoadP op2)));
13325 
13326   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
13327   ins_encode %{
13328     __ cmpq($op1$$Register, $op2$$Address);
13329   %}
13330   ins_pipe(ialu_cr_reg_mem);
13331 %}
13332 
13333 // This will generate a signed flags result. This should be OK since
13334 // any compare to a zero should be eq/neq.
13335 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
13336 %{
13337   match(Set cr (CmpP src zero));
13338 
13339   format %{ "testq   $src, $src\t# ptr" %}
13340   ins_encode %{
13341     __ testq($src$$Register, $src$$Register);
13342   %}
13343   ins_pipe(ialu_cr_reg_imm);
13344 %}
13345 
13346 // This will generate a signed flags result. This should be OK since
13347 // any compare to a zero should be eq/neq.
13348 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
13349 %{
13350   predicate((!UseCompressedOops || (CompressedOops::base() != nullptr)) &&
13351             n->in(1)->as_Load()->barrier_data() == 0);
13352   match(Set cr (CmpP (LoadP op) zero));
13353 
13354   ins_cost(500); // XXX
13355   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
13356   ins_encode %{
13357     __ testq($op$$Address, 0xFFFFFFFF);
13358   %}
13359   ins_pipe(ialu_cr_reg_imm);
13360 %}
13361 
13362 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
13363 %{
13364   predicate(UseCompressedOops && (CompressedOops::base() == nullptr) &&
13365             n->in(1)->as_Load()->barrier_data() == 0);
13366   match(Set cr (CmpP (LoadP mem) zero));
13367 
13368   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
13369   ins_encode %{
13370     __ cmpq(r12, $mem$$Address);
13371   %}
13372   ins_pipe(ialu_cr_reg_mem);
13373 %}
13374 
13375 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
13376 %{
13377   match(Set cr (CmpN op1 op2));
13378 
13379   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
13380   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
13381   ins_pipe(ialu_cr_reg_reg);
13382 %}
13383 
13384 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
13385 %{
13386   predicate(n->in(2)->as_Load()->barrier_data() == 0);
13387   match(Set cr (CmpN src (LoadN mem)));
13388 
13389   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
13390   ins_encode %{
13391     __ cmpl($src$$Register, $mem$$Address);
13392   %}
13393   ins_pipe(ialu_cr_reg_mem);
13394 %}
13395 
13396 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
13397   match(Set cr (CmpN op1 op2));
13398 
13399   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
13400   ins_encode %{
13401     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
13402   %}
13403   ins_pipe(ialu_cr_reg_imm);
13404 %}
13405 
13406 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
13407 %{
13408   predicate(n->in(2)->as_Load()->barrier_data() == 0);
13409   match(Set cr (CmpN src (LoadN mem)));
13410 
13411   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
13412   ins_encode %{
13413     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
13414   %}
13415   ins_pipe(ialu_cr_reg_mem);
13416 %}
13417 
13418 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
13419   match(Set cr (CmpN op1 op2));
13420 
13421   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
13422   ins_encode %{
13423     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
13424   %}
13425   ins_pipe(ialu_cr_reg_imm);
13426 %}
13427 
13428 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
13429 %{
13430   predicate(!UseCompactObjectHeaders);
13431   match(Set cr (CmpN src (LoadNKlass mem)));
13432 
13433   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
13434   ins_encode %{
13435     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
13436   %}
13437   ins_pipe(ialu_cr_reg_mem);
13438 %}
13439 
13440 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
13441   match(Set cr (CmpN src zero));
13442 
13443   format %{ "testl   $src, $src\t# compressed ptr" %}
13444   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
13445   ins_pipe(ialu_cr_reg_imm);
13446 %}
13447 
13448 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
13449 %{
13450   predicate(CompressedOops::base() != nullptr &&
13451             n->in(1)->as_Load()->barrier_data() == 0);
13452   match(Set cr (CmpN (LoadN mem) zero));
13453 
13454   ins_cost(500); // XXX
13455   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
13456   ins_encode %{
13457     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
13458   %}
13459   ins_pipe(ialu_cr_reg_mem);
13460 %}
13461 
13462 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
13463 %{
13464   predicate(CompressedOops::base() == nullptr &&
13465             n->in(1)->as_Load()->barrier_data() == 0);
13466   match(Set cr (CmpN (LoadN mem) zero));
13467 
13468   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
13469   ins_encode %{
13470     __ cmpl(r12, $mem$$Address);
13471   %}
13472   ins_pipe(ialu_cr_reg_mem);
13473 %}
13474 
13475 // Yanked all unsigned pointer compare operations.
13476 // Pointer compares are done with CmpP which is already unsigned.
13477 
13478 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
13479 %{
13480   match(Set cr (CmpL op1 op2));
13481 
13482   format %{ "cmpq    $op1, $op2" %}
13483   ins_encode %{
13484     __ cmpq($op1$$Register, $op2$$Register);
13485   %}
13486   ins_pipe(ialu_cr_reg_reg);
13487 %}
13488 
13489 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
13490 %{
13491   match(Set cr (CmpL op1 op2));
13492 
13493   format %{ "cmpq    $op1, $op2" %}
13494   ins_encode %{
13495     __ cmpq($op1$$Register, $op2$$constant);
13496   %}
13497   ins_pipe(ialu_cr_reg_imm);
13498 %}
13499 
13500 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
13501 %{
13502   match(Set cr (CmpL op1 (LoadL op2)));
13503 
13504   format %{ "cmpq    $op1, $op2" %}
13505   ins_encode %{
13506     __ cmpq($op1$$Register, $op2$$Address);
13507   %}
13508   ins_pipe(ialu_cr_reg_mem);
13509 %}
13510 
13511 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
13512 %{
13513   match(Set cr (CmpL src zero));
13514 
13515   format %{ "testq   $src, $src" %}
13516   ins_encode %{
13517     __ testq($src$$Register, $src$$Register);
13518   %}
13519   ins_pipe(ialu_cr_reg_imm);
13520 %}
13521 
13522 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
13523 %{
13524   match(Set cr (CmpL (AndL src con) zero));
13525 
13526   format %{ "testq   $src, $con\t# long" %}
13527   ins_encode %{
13528     __ testq($src$$Register, $con$$constant);
13529   %}
13530   ins_pipe(ialu_cr_reg_imm);
13531 %}
13532 
13533 instruct testL_reg_reg(rFlagsReg cr, rRegL src1, rRegL src2, immL0 zero)
13534 %{
13535   match(Set cr (CmpL (AndL src1 src2) zero));
13536 
13537   format %{ "testq   $src1, $src2\t# long" %}
13538   ins_encode %{
13539     __ testq($src1$$Register, $src2$$Register);
13540   %}
13541   ins_pipe(ialu_cr_reg_imm);
13542 %}
13543 
13544 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
13545 %{
13546   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
13547 
13548   format %{ "testq   $src, $mem" %}
13549   ins_encode %{
13550     __ testq($src$$Register, $mem$$Address);
13551   %}
13552   ins_pipe(ialu_cr_reg_mem);
13553 %}
13554 
13555 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
13556 %{
13557   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
13558 
13559   format %{ "testq   $src, $mem" %}
13560   ins_encode %{
13561     __ testq($src$$Register, $mem$$Address);
13562   %}
13563   ins_pipe(ialu_cr_reg_mem);
13564 %}
13565 
13566 // Manifest a CmpU result in an integer register.  Very painful.
13567 // This is the test to avoid.
13568 instruct cmpU3_reg_reg(rRegI dst, rRegI src1, rRegI src2, rFlagsReg flags)
13569 %{
13570   match(Set dst (CmpU3 src1 src2));
13571   effect(KILL flags);
13572 
13573   ins_cost(275); // XXX
13574   format %{ "cmpl    $src1, $src2\t# CmpL3\n\t"
13575             "movl    $dst, -1\n\t"
13576             "jb,u    done\n\t"
13577             "setcc   $dst \t# emits setne + movzbl or setzune for APX"
13578     "done:" %}
13579   ins_encode %{
13580     Label done;
13581     __ cmpl($src1$$Register, $src2$$Register);
13582     __ movl($dst$$Register, -1);
13583     __ jccb(Assembler::below, done);
13584     __ setcc(Assembler::notZero, $dst$$Register);
13585     __ bind(done);
13586   %}
13587   ins_pipe(pipe_slow);
13588 %}
13589 
13590 // Manifest a CmpL result in an integer register.  Very painful.
13591 // This is the test to avoid.
13592 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13593 %{
13594   match(Set dst (CmpL3 src1 src2));
13595   effect(KILL flags);
13596 
13597   ins_cost(275); // XXX
13598   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
13599             "movl    $dst, -1\n\t"
13600             "jl,s    done\n\t"
13601             "setcc   $dst \t# emits setne + movzbl or setzune for APX"
13602     "done:" %}
13603   ins_encode %{
13604     Label done;
13605     __ cmpq($src1$$Register, $src2$$Register);
13606     __ movl($dst$$Register, -1);
13607     __ jccb(Assembler::less, done);
13608     __ setcc(Assembler::notZero, $dst$$Register);
13609     __ bind(done);
13610   %}
13611   ins_pipe(pipe_slow);
13612 %}
13613 
13614 // Manifest a CmpUL result in an integer register.  Very painful.
13615 // This is the test to avoid.
13616 instruct cmpUL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
13617 %{
13618   match(Set dst (CmpUL3 src1 src2));
13619   effect(KILL flags);
13620 
13621   ins_cost(275); // XXX
13622   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
13623             "movl    $dst, -1\n\t"
13624             "jb,u    done\n\t"
13625             "setcc   $dst \t# emits setne + movzbl or setzune for APX"
13626     "done:" %}
13627   ins_encode %{
13628     Label done;
13629     __ cmpq($src1$$Register, $src2$$Register);
13630     __ movl($dst$$Register, -1);
13631     __ jccb(Assembler::below, done);
13632     __ setcc(Assembler::notZero, $dst$$Register);
13633     __ bind(done);
13634   %}
13635   ins_pipe(pipe_slow);
13636 %}
13637 
13638 // Unsigned long compare Instructions; really, same as signed long except they
13639 // produce an rFlagsRegU instead of rFlagsReg.
13640 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
13641 %{
13642   match(Set cr (CmpUL op1 op2));
13643 
13644   format %{ "cmpq    $op1, $op2\t# unsigned" %}
13645   ins_encode %{
13646     __ cmpq($op1$$Register, $op2$$Register);
13647   %}
13648   ins_pipe(ialu_cr_reg_reg);
13649 %}
13650 
13651 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
13652 %{
13653   match(Set cr (CmpUL op1 op2));
13654 
13655   format %{ "cmpq    $op1, $op2\t# unsigned" %}
13656   ins_encode %{
13657     __ cmpq($op1$$Register, $op2$$constant);
13658   %}
13659   ins_pipe(ialu_cr_reg_imm);
13660 %}
13661 
13662 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
13663 %{
13664   match(Set cr (CmpUL op1 (LoadL op2)));
13665 
13666   format %{ "cmpq    $op1, $op2\t# unsigned" %}
13667   ins_encode %{
13668     __ cmpq($op1$$Register, $op2$$Address);
13669   %}
13670   ins_pipe(ialu_cr_reg_mem);
13671 %}
13672 
13673 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
13674 %{
13675   match(Set cr (CmpUL src zero));
13676 
13677   format %{ "testq   $src, $src\t# unsigned" %}
13678   ins_encode %{
13679     __ testq($src$$Register, $src$$Register);
13680   %}
13681   ins_pipe(ialu_cr_reg_imm);
13682 %}
13683 
13684 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
13685 %{
13686   match(Set cr (CmpI (LoadB mem) imm));
13687 
13688   ins_cost(125);
13689   format %{ "cmpb    $mem, $imm" %}
13690   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
13691   ins_pipe(ialu_cr_reg_mem);
13692 %}
13693 
13694 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
13695 %{
13696   match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
13697 
13698   ins_cost(125);
13699   format %{ "testb   $mem, $imm\t# ubyte" %}
13700   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13701   ins_pipe(ialu_cr_reg_mem);
13702 %}
13703 
13704 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
13705 %{
13706   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
13707 
13708   ins_cost(125);
13709   format %{ "testb   $mem, $imm\t# byte" %}
13710   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
13711   ins_pipe(ialu_cr_reg_mem);
13712 %}
13713 
13714 //----------Max and Min--------------------------------------------------------
13715 // Min Instructions
13716 
13717 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
13718 %{
13719   predicate(!UseAPX);
13720   effect(USE_DEF dst, USE src, USE cr);
13721 
13722   format %{ "cmovlgt $dst, $src\t# min" %}
13723   ins_encode %{
13724     __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
13725   %}
13726   ins_pipe(pipe_cmov_reg);
13727 %}
13728 
13729 instruct cmovI_reg_g_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13730 %{
13731   predicate(UseAPX);
13732   effect(DEF dst, USE src1, USE src2, USE cr);
13733 
13734   format %{ "ecmovlgt $dst, $src1, $src2\t# min ndd" %}
13735   ins_encode %{
13736     __ ecmovl(Assembler::greater, $dst$$Register, $src1$$Register, $src2$$Register);
13737   %}
13738   ins_pipe(pipe_cmov_reg);
13739 %}
13740 
13741 instruct minI_rReg(rRegI dst, rRegI src)
13742 %{
13743   predicate(!UseAPX);
13744   match(Set dst (MinI dst src));
13745 
13746   ins_cost(200);
13747   expand %{
13748     rFlagsReg cr;
13749     compI_rReg(cr, dst, src);
13750     cmovI_reg_g(dst, src, cr);
13751   %}
13752 %}
13753 
13754 instruct minI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13755 %{
13756   predicate(UseAPX);
13757   match(Set dst (MinI src1 src2));
13758   effect(DEF dst, USE src1, USE src2);
13759 
13760   ins_cost(200);
13761   expand %{
13762     rFlagsReg cr;
13763     compI_rReg(cr, src1, src2);
13764     cmovI_reg_g_ndd(dst, src1, src2, cr);
13765   %}
13766 %}
13767 
13768 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
13769 %{
13770   predicate(!UseAPX);
13771   effect(USE_DEF dst, USE src, USE cr);
13772 
13773   format %{ "cmovllt $dst, $src\t# max" %}
13774   ins_encode %{
13775     __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
13776   %}
13777   ins_pipe(pipe_cmov_reg);
13778 %}
13779 
13780 instruct cmovI_reg_l_ndd(rRegI dst, rRegI src1, rRegI src2, rFlagsReg cr)
13781 %{
13782   predicate(UseAPX);
13783   effect(DEF dst, USE src1, USE src2, USE cr);
13784 
13785   format %{ "ecmovllt $dst, $src1, $src2\t# max ndd" %}
13786   ins_encode %{
13787     __ ecmovl(Assembler::less, $dst$$Register, $src1$$Register, $src2$$Register);
13788   %}
13789   ins_pipe(pipe_cmov_reg);
13790 %}
13791 
13792 instruct maxI_rReg(rRegI dst, rRegI src)
13793 %{
13794   predicate(!UseAPX);
13795   match(Set dst (MaxI dst src));
13796 
13797   ins_cost(200);
13798   expand %{
13799     rFlagsReg cr;
13800     compI_rReg(cr, dst, src);
13801     cmovI_reg_l(dst, src, cr);
13802   %}
13803 %}
13804 
13805 instruct maxI_rReg_ndd(rRegI dst, rRegI src1, rRegI src2)
13806 %{
13807   predicate(UseAPX);
13808   match(Set dst (MaxI src1 src2));
13809   effect(DEF dst, USE src1, USE src2);
13810 
13811   ins_cost(200);
13812   expand %{
13813     rFlagsReg cr;
13814     compI_rReg(cr, src1, src2);
13815     cmovI_reg_l_ndd(dst, src1, src2, cr);
13816   %}
13817 %}
13818 
13819 // ============================================================================
13820 // Branch Instructions
13821 
13822 // Jump Direct - Label defines a relative address from JMP+1
13823 instruct jmpDir(label labl)
13824 %{
13825   match(Goto);
13826   effect(USE labl);
13827 
13828   ins_cost(300);
13829   format %{ "jmp     $labl" %}
13830   size(5);
13831   ins_encode %{
13832     Label* L = $labl$$label;
13833     __ jmp(*L, false); // Always long jump
13834   %}
13835   ins_pipe(pipe_jmp);
13836 %}
13837 
13838 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13839 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
13840 %{
13841   match(If cop cr);
13842   effect(USE labl);
13843 
13844   ins_cost(300);
13845   format %{ "j$cop     $labl" %}
13846   size(6);
13847   ins_encode %{
13848     Label* L = $labl$$label;
13849     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13850   %}
13851   ins_pipe(pipe_jcc);
13852 %}
13853 
13854 // Jump Direct Conditional - Label defines a relative address from Jcc+1
13855 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
13856 %{
13857   match(CountedLoopEnd cop cr);
13858   effect(USE labl);
13859 
13860   ins_cost(300);
13861   format %{ "j$cop     $labl\t# loop end" %}
13862   size(6);
13863   ins_encode %{
13864     Label* L = $labl$$label;
13865     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13866   %}
13867   ins_pipe(pipe_jcc);
13868 %}
13869 
13870 // Jump Direct Conditional - using unsigned comparison
13871 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
13872   match(If cop cmp);
13873   effect(USE labl);
13874 
13875   ins_cost(300);
13876   format %{ "j$cop,u   $labl" %}
13877   size(6);
13878   ins_encode %{
13879     Label* L = $labl$$label;
13880     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13881   %}
13882   ins_pipe(pipe_jcc);
13883 %}
13884 
13885 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
13886   match(If cop cmp);
13887   effect(USE labl);
13888 
13889   ins_cost(200);
13890   format %{ "j$cop,u   $labl" %}
13891   size(6);
13892   ins_encode %{
13893     Label* L = $labl$$label;
13894     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
13895   %}
13896   ins_pipe(pipe_jcc);
13897 %}
13898 
13899 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
13900   match(If cop cmp);
13901   effect(USE labl);
13902 
13903   ins_cost(200);
13904   format %{ $$template
13905     if ($cop$$cmpcode == Assembler::notEqual) {
13906       $$emit$$"jp,u    $labl\n\t"
13907       $$emit$$"j$cop,u   $labl"
13908     } else {
13909       $$emit$$"jp,u    done\n\t"
13910       $$emit$$"j$cop,u   $labl\n\t"
13911       $$emit$$"done:"
13912     }
13913   %}
13914   ins_encode %{
13915     Label* l = $labl$$label;
13916     if ($cop$$cmpcode == Assembler::notEqual) {
13917       __ jcc(Assembler::parity, *l, false);
13918       __ jcc(Assembler::notEqual, *l, false);
13919     } else if ($cop$$cmpcode == Assembler::equal) {
13920       Label done;
13921       __ jccb(Assembler::parity, done);
13922       __ jcc(Assembler::equal, *l, false);
13923       __ bind(done);
13924     } else {
13925        ShouldNotReachHere();
13926     }
13927   %}
13928   ins_pipe(pipe_jcc);
13929 %}
13930 
13931 // ============================================================================
13932 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
13933 // superklass array for an instance of the superklass.  Set a hidden
13934 // internal cache on a hit (cache is checked with exposed code in
13935 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
13936 // encoding ALSO sets flags.
13937 
13938 instruct partialSubtypeCheck(rdi_RegP result,
13939                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
13940                              rFlagsReg cr)
13941 %{
13942   match(Set result (PartialSubtypeCheck sub super));
13943   predicate(!UseSecondarySupersTable);
13944   effect(KILL rcx, KILL cr);
13945 
13946   ins_cost(1100);  // slightly larger than the next version
13947   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
13948             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
13949             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
13950             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
13951             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
13952             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
13953             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
13954     "miss:\t" %}
13955 
13956   ins_encode %{
13957     Label miss;
13958     // NB: Callers may assume that, when $result is a valid register,
13959     // check_klass_subtype_slow_path_linear sets it to a nonzero
13960     // value.
13961     __ check_klass_subtype_slow_path_linear($sub$$Register, $super$$Register,
13962                                             $rcx$$Register, $result$$Register,
13963                                             nullptr, &miss,
13964                                             /*set_cond_codes:*/ true);
13965     __ xorptr($result$$Register, $result$$Register);
13966     __ bind(miss);
13967   %}
13968 
13969   ins_pipe(pipe_slow);
13970 %}
13971 
13972 // ============================================================================
13973 // Two versions of hashtable-based partialSubtypeCheck, both used when
13974 // we need to search for a super class in the secondary supers array.
13975 // The first is used when we don't know _a priori_ the class being
13976 // searched for. The second, far more common, is used when we do know:
13977 // this is used for instanceof, checkcast, and any case where C2 can
13978 // determine it by constant propagation.
13979 
13980 instruct partialSubtypeCheckVarSuper(rsi_RegP sub, rax_RegP super, rdi_RegP result,
13981                                        rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
13982                                        rFlagsReg cr)
13983 %{
13984   match(Set result (PartialSubtypeCheck sub super));
13985   predicate(UseSecondarySupersTable);
13986   effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
13987 
13988   ins_cost(1000);
13989   format %{ "partialSubtypeCheck $result, $sub, $super" %}
13990 
13991   ins_encode %{
13992     __ lookup_secondary_supers_table_var($sub$$Register, $super$$Register, $temp1$$Register, $temp2$$Register,
13993 					 $temp3$$Register, $temp4$$Register, $result$$Register);
13994   %}
13995 
13996   ins_pipe(pipe_slow);
13997 %}
13998 
13999 instruct partialSubtypeCheckConstSuper(rsi_RegP sub, rax_RegP super_reg, immP super_con, rdi_RegP result,
14000                                        rdx_RegL temp1, rcx_RegL temp2, rbx_RegP temp3, r11_RegL temp4,
14001                                        rFlagsReg cr)
14002 %{
14003   match(Set result (PartialSubtypeCheck sub (Binary super_reg super_con)));
14004   predicate(UseSecondarySupersTable);
14005   effect(KILL cr, TEMP temp1, TEMP temp2, TEMP temp3, TEMP temp4);
14006 
14007   ins_cost(700);  // smaller than the next version
14008   format %{ "partialSubtypeCheck $result, $sub, $super_reg, $super_con" %}
14009 
14010   ins_encode %{
14011     u1 super_klass_slot = ((Klass*)$super_con$$constant)->hash_slot();
14012     if (InlineSecondarySupersTest) {
14013       __ lookup_secondary_supers_table_const($sub$$Register, $super_reg$$Register, $temp1$$Register, $temp2$$Register,
14014                                        $temp3$$Register, $temp4$$Register, $result$$Register,
14015                                        super_klass_slot);
14016     } else {
14017       __ call(RuntimeAddress(StubRoutines::lookup_secondary_supers_table_stub(super_klass_slot)));
14018     }
14019   %}
14020 
14021   ins_pipe(pipe_slow);
14022 %}
14023 
14024 // ============================================================================
14025 // Branch Instructions -- short offset versions
14026 //
14027 // These instructions are used to replace jumps of a long offset (the default
14028 // match) with jumps of a shorter offset.  These instructions are all tagged
14029 // with the ins_short_branch attribute, which causes the ADLC to suppress the
14030 // match rules in general matching.  Instead, the ADLC generates a conversion
14031 // method in the MachNode which can be used to do in-place replacement of the
14032 // long variant with the shorter variant.  The compiler will determine if a
14033 // branch can be taken by the is_short_branch_offset() predicate in the machine
14034 // specific code section of the file.
14035 
14036 // Jump Direct - Label defines a relative address from JMP+1
14037 instruct jmpDir_short(label labl) %{
14038   match(Goto);
14039   effect(USE labl);
14040 
14041   ins_cost(300);
14042   format %{ "jmp,s   $labl" %}
14043   size(2);
14044   ins_encode %{
14045     Label* L = $labl$$label;
14046     __ jmpb(*L);
14047   %}
14048   ins_pipe(pipe_jmp);
14049   ins_short_branch(1);
14050 %}
14051 
14052 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14053 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
14054   match(If cop cr);
14055   effect(USE labl);
14056 
14057   ins_cost(300);
14058   format %{ "j$cop,s   $labl" %}
14059   size(2);
14060   ins_encode %{
14061     Label* L = $labl$$label;
14062     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14063   %}
14064   ins_pipe(pipe_jcc);
14065   ins_short_branch(1);
14066 %}
14067 
14068 // Jump Direct Conditional - Label defines a relative address from Jcc+1
14069 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
14070   match(CountedLoopEnd cop cr);
14071   effect(USE labl);
14072 
14073   ins_cost(300);
14074   format %{ "j$cop,s   $labl\t# loop end" %}
14075   size(2);
14076   ins_encode %{
14077     Label* L = $labl$$label;
14078     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14079   %}
14080   ins_pipe(pipe_jcc);
14081   ins_short_branch(1);
14082 %}
14083 
14084 // Jump Direct Conditional - using unsigned comparison
14085 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
14086   match(If cop cmp);
14087   effect(USE labl);
14088 
14089   ins_cost(300);
14090   format %{ "j$cop,us  $labl" %}
14091   size(2);
14092   ins_encode %{
14093     Label* L = $labl$$label;
14094     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14095   %}
14096   ins_pipe(pipe_jcc);
14097   ins_short_branch(1);
14098 %}
14099 
14100 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
14101   match(If cop cmp);
14102   effect(USE labl);
14103 
14104   ins_cost(300);
14105   format %{ "j$cop,us  $labl" %}
14106   size(2);
14107   ins_encode %{
14108     Label* L = $labl$$label;
14109     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
14110   %}
14111   ins_pipe(pipe_jcc);
14112   ins_short_branch(1);
14113 %}
14114 
14115 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
14116   match(If cop cmp);
14117   effect(USE labl);
14118 
14119   ins_cost(300);
14120   format %{ $$template
14121     if ($cop$$cmpcode == Assembler::notEqual) {
14122       $$emit$$"jp,u,s  $labl\n\t"
14123       $$emit$$"j$cop,u,s  $labl"
14124     } else {
14125       $$emit$$"jp,u,s  done\n\t"
14126       $$emit$$"j$cop,u,s  $labl\n\t"
14127       $$emit$$"done:"
14128     }
14129   %}
14130   size(4);
14131   ins_encode %{
14132     Label* l = $labl$$label;
14133     if ($cop$$cmpcode == Assembler::notEqual) {
14134       __ jccb(Assembler::parity, *l);
14135       __ jccb(Assembler::notEqual, *l);
14136     } else if ($cop$$cmpcode == Assembler::equal) {
14137       Label done;
14138       __ jccb(Assembler::parity, done);
14139       __ jccb(Assembler::equal, *l);
14140       __ bind(done);
14141     } else {
14142        ShouldNotReachHere();
14143     }
14144   %}
14145   ins_pipe(pipe_jcc);
14146   ins_short_branch(1);
14147 %}
14148 
14149 // ============================================================================
14150 // inlined locking and unlocking
14151 
14152 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
14153   predicate(LockingMode != LM_LIGHTWEIGHT);
14154   match(Set cr (FastLock object box));
14155   effect(TEMP tmp, TEMP scr, USE_KILL box);
14156   ins_cost(300);
14157   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
14158   ins_encode %{
14159     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
14160                  $scr$$Register, noreg, noreg, r15_thread, nullptr);
14161   %}
14162   ins_pipe(pipe_slow);
14163 %}
14164 
14165 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
14166   predicate(LockingMode != LM_LIGHTWEIGHT);
14167   match(Set cr (FastUnlock object box));
14168   effect(TEMP tmp, USE_KILL box);
14169   ins_cost(300);
14170   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
14171   ins_encode %{
14172     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register);
14173   %}
14174   ins_pipe(pipe_slow);
14175 %}
14176 
14177 instruct cmpFastLockLightweight(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI rax_reg, rRegP tmp) %{
14178   predicate(LockingMode == LM_LIGHTWEIGHT);
14179   match(Set cr (FastLock object box));
14180   effect(TEMP rax_reg, TEMP tmp, USE_KILL box);
14181   ins_cost(300);
14182   format %{ "fastlock $object,$box\t! kills $box,$rax_reg,$tmp" %}
14183   ins_encode %{
14184     __ fast_lock_lightweight($object$$Register, $box$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14185   %}
14186   ins_pipe(pipe_slow);
14187 %}
14188 
14189 instruct cmpFastUnlockLightweight(rFlagsReg cr, rRegP object, rax_RegP rax_reg, rRegP tmp) %{
14190   predicate(LockingMode == LM_LIGHTWEIGHT);
14191   match(Set cr (FastUnlock object rax_reg));
14192   effect(TEMP tmp, USE_KILL rax_reg);
14193   ins_cost(300);
14194   format %{ "fastunlock $object,$rax_reg\t! kills $rax_reg,$tmp" %}
14195   ins_encode %{
14196     __ fast_unlock_lightweight($object$$Register, $rax_reg$$Register, $tmp$$Register, r15_thread);
14197   %}
14198   ins_pipe(pipe_slow);
14199 %}
14200 
14201 
14202 // ============================================================================
14203 // Safepoint Instructions
14204 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
14205 %{
14206   match(SafePoint poll);
14207   effect(KILL cr, USE poll);
14208 
14209   format %{ "testl   rax, [$poll]\t"
14210             "# Safepoint: poll for GC" %}
14211   ins_cost(125);
14212   ins_encode %{
14213     __ relocate(relocInfo::poll_type);
14214     address pre_pc = __ pc();
14215     __ testl(rax, Address($poll$$Register, 0));
14216     assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
14217   %}
14218   ins_pipe(ialu_reg_mem);
14219 %}
14220 
14221 instruct mask_all_evexL(kReg dst, rRegL src) %{
14222   match(Set dst (MaskAll src));
14223   format %{ "mask_all_evexL $dst, $src \t! mask all operation" %}
14224   ins_encode %{
14225     int mask_len = Matcher::vector_length(this);
14226     __ vector_maskall_operation($dst$$KRegister, $src$$Register, mask_len);
14227   %}
14228   ins_pipe( pipe_slow );
14229 %}
14230 
14231 instruct mask_all_evexI_GT32(kReg dst, rRegI src, rRegL tmp) %{
14232   predicate(Matcher::vector_length(n) > 32);
14233   match(Set dst (MaskAll src));
14234   effect(TEMP tmp);
14235   format %{ "mask_all_evexI_GT32 $dst, $src \t! using $tmp as TEMP" %}
14236   ins_encode %{
14237     int mask_len = Matcher::vector_length(this);
14238     __ movslq($tmp$$Register, $src$$Register);
14239     __ vector_maskall_operation($dst$$KRegister, $tmp$$Register, mask_len);
14240   %}
14241   ins_pipe( pipe_slow );
14242 %}
14243 
14244 // ============================================================================
14245 // Procedure Call/Return Instructions
14246 // Call Java Static Instruction
14247 // Note: If this code changes, the corresponding ret_addr_offset() and
14248 //       compute_padding() functions will have to be adjusted.
14249 instruct CallStaticJavaDirect(method meth) %{
14250   match(CallStaticJava);
14251   effect(USE meth);
14252 
14253   ins_cost(300);
14254   format %{ "call,static " %}
14255   opcode(0xE8); /* E8 cd */
14256   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
14257   ins_pipe(pipe_slow);
14258   ins_alignment(4);
14259 %}
14260 
14261 // Call Java Dynamic Instruction
14262 // Note: If this code changes, the corresponding ret_addr_offset() and
14263 //       compute_padding() functions will have to be adjusted.
14264 instruct CallDynamicJavaDirect(method meth)
14265 %{
14266   match(CallDynamicJava);
14267   effect(USE meth);
14268 
14269   ins_cost(300);
14270   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
14271             "call,dynamic " %}
14272   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
14273   ins_pipe(pipe_slow);
14274   ins_alignment(4);
14275 %}
14276 
14277 // Call Runtime Instruction
14278 instruct CallRuntimeDirect(method meth)
14279 %{
14280   match(CallRuntime);
14281   effect(USE meth);
14282 
14283   ins_cost(300);
14284   format %{ "call,runtime " %}
14285   ins_encode(clear_avx, Java_To_Runtime(meth));
14286   ins_pipe(pipe_slow);
14287 %}
14288 
14289 // Call runtime without safepoint
14290 instruct CallLeafDirect(method meth)
14291 %{
14292   match(CallLeaf);
14293   effect(USE meth);
14294 
14295   ins_cost(300);
14296   format %{ "call_leaf,runtime " %}
14297   ins_encode(clear_avx, Java_To_Runtime(meth));
14298   ins_pipe(pipe_slow);
14299 %}
14300 
14301 // Call runtime without safepoint and with vector arguments
14302 instruct CallLeafDirectVector(method meth)
14303 %{
14304   match(CallLeafVector);
14305   effect(USE meth);
14306 
14307   ins_cost(300);
14308   format %{ "call_leaf,vector " %}
14309   ins_encode(Java_To_Runtime(meth));
14310   ins_pipe(pipe_slow);
14311 %}
14312 
14313 // Call runtime without safepoint
14314 instruct CallLeafNoFPDirect(method meth)
14315 %{
14316   match(CallLeafNoFP);
14317   effect(USE meth);
14318 
14319   ins_cost(300);
14320   format %{ "call_leaf_nofp,runtime " %}
14321   ins_encode(clear_avx, Java_To_Runtime(meth));
14322   ins_pipe(pipe_slow);
14323 %}
14324 
14325 // Return Instruction
14326 // Remove the return address & jump to it.
14327 // Notice: We always emit a nop after a ret to make sure there is room
14328 // for safepoint patching
14329 instruct Ret()
14330 %{
14331   match(Return);
14332 
14333   format %{ "ret" %}
14334   ins_encode %{
14335     __ ret(0);
14336   %}
14337   ins_pipe(pipe_jmp);
14338 %}
14339 
14340 // Tail Call; Jump from runtime stub to Java code.
14341 // Also known as an 'interprocedural jump'.
14342 // Target of jump will eventually return to caller.
14343 // TailJump below removes the return address.
14344 // Don't use rbp for 'jump_target' because a MachEpilogNode has already been
14345 // emitted just above the TailCall which has reset rbp to the caller state.
14346 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
14347 %{
14348   match(TailCall jump_target method_ptr);
14349 
14350   ins_cost(300);
14351   format %{ "jmp     $jump_target\t# rbx holds method" %}
14352   ins_encode %{
14353     __ jmp($jump_target$$Register);
14354   %}
14355   ins_pipe(pipe_jmp);
14356 %}
14357 
14358 // Tail Jump; remove the return address; jump to target.
14359 // TailCall above leaves the return address around.
14360 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
14361 %{
14362   match(TailJump jump_target ex_oop);
14363 
14364   ins_cost(300);
14365   format %{ "popq    rdx\t# pop return address\n\t"
14366             "jmp     $jump_target" %}
14367   ins_encode %{
14368     __ popq(as_Register(RDX_enc));
14369     __ jmp($jump_target$$Register);
14370   %}
14371   ins_pipe(pipe_jmp);
14372 %}
14373 
14374 // Forward exception.
14375 instruct ForwardExceptionjmp()
14376 %{
14377   match(ForwardException);
14378 
14379   format %{ "jmp     forward_exception_stub" %}
14380   ins_encode %{
14381     __ jump(RuntimeAddress(StubRoutines::forward_exception_entry()), noreg);
14382   %}
14383   ins_pipe(pipe_jmp);
14384 %}
14385 
14386 // Create exception oop: created by stack-crawling runtime code.
14387 // Created exception is now available to this handler, and is setup
14388 // just prior to jumping to this handler.  No code emitted.
14389 instruct CreateException(rax_RegP ex_oop)
14390 %{
14391   match(Set ex_oop (CreateEx));
14392 
14393   size(0);
14394   // use the following format syntax
14395   format %{ "# exception oop is in rax; no code emitted" %}
14396   ins_encode();
14397   ins_pipe(empty);
14398 %}
14399 
14400 // Rethrow exception:
14401 // The exception oop will come in the first argument position.
14402 // Then JUMP (not call) to the rethrow stub code.
14403 instruct RethrowException()
14404 %{
14405   match(Rethrow);
14406 
14407   // use the following format syntax
14408   format %{ "jmp     rethrow_stub" %}
14409   ins_encode %{
14410     __ jump(RuntimeAddress(OptoRuntime::rethrow_stub()), noreg);
14411   %}
14412   ins_pipe(pipe_jmp);
14413 %}
14414 
14415 // ============================================================================
14416 // This name is KNOWN by the ADLC and cannot be changed.
14417 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
14418 // for this guy.
14419 instruct tlsLoadP(r15_RegP dst) %{
14420   match(Set dst (ThreadLocal));
14421   effect(DEF dst);
14422 
14423   size(0);
14424   format %{ "# TLS is in R15" %}
14425   ins_encode( /*empty encoding*/ );
14426   ins_pipe(ialu_reg_reg);
14427 %}
14428 
14429 
14430 //----------PEEPHOLE RULES-----------------------------------------------------
14431 // These must follow all instruction definitions as they use the names
14432 // defined in the instructions definitions.
14433 //
14434 // peeppredicate ( rule_predicate );
14435 // // the predicate unless which the peephole rule will be ignored
14436 //
14437 // peepmatch ( root_instr_name [preceding_instruction]* );
14438 //
14439 // peepprocedure ( procedure_name );
14440 // // provide a procedure name to perform the optimization, the procedure should
14441 // // reside in the architecture dependent peephole file, the method has the
14442 // // signature of MachNode* (Block*, int, PhaseRegAlloc*, (MachNode*)(*)(), int...)
14443 // // with the arguments being the basic block, the current node index inside the
14444 // // block, the register allocator, the functions upon invoked return a new node
14445 // // defined in peepreplace, and the rules of the nodes appearing in the
14446 // // corresponding peepmatch, the function return true if successful, else
14447 // // return false
14448 //
14449 // peepconstraint %{
14450 // (instruction_number.operand_name relational_op instruction_number.operand_name
14451 //  [, ...] );
14452 // // instruction numbers are zero-based using left to right order in peepmatch
14453 //
14454 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
14455 // // provide an instruction_number.operand_name for each operand that appears
14456 // // in the replacement instruction's match rule
14457 //
14458 // ---------VM FLAGS---------------------------------------------------------
14459 //
14460 // All peephole optimizations can be turned off using -XX:-OptoPeephole
14461 //
14462 // Each peephole rule is given an identifying number starting with zero and
14463 // increasing by one in the order seen by the parser.  An individual peephole
14464 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
14465 // on the command-line.
14466 //
14467 // ---------CURRENT LIMITATIONS----------------------------------------------
14468 //
14469 // Only transformations inside a basic block (do we need more for peephole)
14470 //
14471 // ---------EXAMPLE----------------------------------------------------------
14472 //
14473 // // pertinent parts of existing instructions in architecture description
14474 // instruct movI(rRegI dst, rRegI src)
14475 // %{
14476 //   match(Set dst (CopyI src));
14477 // %}
14478 //
14479 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
14480 // %{
14481 //   match(Set dst (AddI dst src));
14482 //   effect(KILL cr);
14483 // %}
14484 //
14485 // instruct leaI_rReg_immI(rRegI dst, immI_1 src)
14486 // %{
14487 //   match(Set dst (AddI dst src));
14488 // %}
14489 //
14490 // 1. Simple replacement
14491 // - Only match adjacent instructions in same basic block
14492 // - Only equality constraints
14493 // - Only constraints between operands, not (0.dest_reg == RAX_enc)
14494 // - Only one replacement instruction
14495 //
14496 // // Change (inc mov) to lea
14497 // peephole %{
14498 //   // lea should only be emitted when beneficial
14499 //   peeppredicate( VM_Version::supports_fast_2op_lea() );
14500 //   // increment preceded by register-register move
14501 //   peepmatch ( incI_rReg movI );
14502 //   // require that the destination register of the increment
14503 //   // match the destination register of the move
14504 //   peepconstraint ( 0.dst == 1.dst );
14505 //   // construct a replacement instruction that sets
14506 //   // the destination to ( move's source register + one )
14507 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
14508 // %}
14509 //
14510 // 2. Procedural replacement
14511 // - More flexible finding relevent nodes
14512 // - More flexible constraints
14513 // - More flexible transformations
14514 // - May utilise architecture-dependent API more effectively
14515 // - Currently only one replacement instruction due to adlc parsing capabilities
14516 //
14517 // // Change (inc mov) to lea
14518 // peephole %{
14519 //   // lea should only be emitted when beneficial
14520 //   peeppredicate( VM_Version::supports_fast_2op_lea() );
14521 //   // the rule numbers of these nodes inside are passed into the function below
14522 //   peepmatch ( incI_rReg movI );
14523 //   // the method that takes the responsibility of transformation
14524 //   peepprocedure ( inc_mov_to_lea );
14525 //   // the replacement is a leaI_rReg_immI, a lambda upon invoked creating this
14526 //   // node is passed into the function above
14527 //   peepreplace ( leaI_rReg_immI() );
14528 // %}
14529 
14530 // These instructions is not matched by the matcher but used by the peephole
14531 instruct leaI_rReg_rReg_peep(rRegI dst, rRegI src1, rRegI src2)
14532 %{
14533   predicate(false);
14534   match(Set dst (AddI src1 src2));
14535   format %{ "leal    $dst, [$src1 + $src2]" %}
14536   ins_encode %{
14537     Register dst = $dst$$Register;
14538     Register src1 = $src1$$Register;
14539     Register src2 = $src2$$Register;
14540     if (src1 != rbp && src1 != r13) {
14541       __ leal(dst, Address(src1, src2, Address::times_1));
14542     } else {
14543       assert(src2 != rbp && src2 != r13, "");
14544       __ leal(dst, Address(src2, src1, Address::times_1));
14545     }
14546   %}
14547   ins_pipe(ialu_reg_reg);
14548 %}
14549 
14550 instruct leaI_rReg_immI_peep(rRegI dst, rRegI src1, immI src2)
14551 %{
14552   predicate(false);
14553   match(Set dst (AddI src1 src2));
14554   format %{ "leal    $dst, [$src1 + $src2]" %}
14555   ins_encode %{
14556     __ leal($dst$$Register, Address($src1$$Register, $src2$$constant));
14557   %}
14558   ins_pipe(ialu_reg_reg);
14559 %}
14560 
14561 instruct leaI_rReg_immI2_peep(rRegI dst, rRegI src, immI2 shift)
14562 %{
14563   predicate(false);
14564   match(Set dst (LShiftI src shift));
14565   format %{ "leal    $dst, [$src << $shift]" %}
14566   ins_encode %{
14567     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14568     Register src = $src$$Register;
14569     if (scale == Address::times_2 && src != rbp && src != r13) {
14570       __ leal($dst$$Register, Address(src, src, Address::times_1));
14571     } else {
14572       __ leal($dst$$Register, Address(noreg, src, scale));
14573     }
14574   %}
14575   ins_pipe(ialu_reg_reg);
14576 %}
14577 
14578 instruct leaL_rReg_rReg_peep(rRegL dst, rRegL src1, rRegL src2)
14579 %{
14580   predicate(false);
14581   match(Set dst (AddL src1 src2));
14582   format %{ "leaq    $dst, [$src1 + $src2]" %}
14583   ins_encode %{
14584     Register dst = $dst$$Register;
14585     Register src1 = $src1$$Register;
14586     Register src2 = $src2$$Register;
14587     if (src1 != rbp && src1 != r13) {
14588       __ leaq(dst, Address(src1, src2, Address::times_1));
14589     } else {
14590       assert(src2 != rbp && src2 != r13, "");
14591       __ leaq(dst, Address(src2, src1, Address::times_1));
14592     }
14593   %}
14594   ins_pipe(ialu_reg_reg);
14595 %}
14596 
14597 instruct leaL_rReg_immL32_peep(rRegL dst, rRegL src1, immL32 src2)
14598 %{
14599   predicate(false);
14600   match(Set dst (AddL src1 src2));
14601   format %{ "leaq    $dst, [$src1 + $src2]" %}
14602   ins_encode %{
14603     __ leaq($dst$$Register, Address($src1$$Register, $src2$$constant));
14604   %}
14605   ins_pipe(ialu_reg_reg);
14606 %}
14607 
14608 instruct leaL_rReg_immI2_peep(rRegL dst, rRegL src, immI2 shift)
14609 %{
14610   predicate(false);
14611   match(Set dst (LShiftL src shift));
14612   format %{ "leaq    $dst, [$src << $shift]" %}
14613   ins_encode %{
14614     Address::ScaleFactor scale = static_cast<Address::ScaleFactor>($shift$$constant);
14615     Register src = $src$$Register;
14616     if (scale == Address::times_2 && src != rbp && src != r13) {
14617       __ leaq($dst$$Register, Address(src, src, Address::times_1));
14618     } else {
14619       __ leaq($dst$$Register, Address(noreg, src, scale));
14620     }
14621   %}
14622   ins_pipe(ialu_reg_reg);
14623 %}
14624 
14625 // These peephole rules replace mov + I pairs (where I is one of {add, inc, dec,
14626 // sal}) with lea instructions. The {add, sal} rules are beneficial in
14627 // processors with at least partial ALU support for lea
14628 // (supports_fast_2op_lea()), whereas the {inc, dec} rules are only generally
14629 // beneficial for processors with full ALU support
14630 // (VM_Version::supports_fast_3op_lea()) and Intel Cascade Lake.
14631 
14632 peephole
14633 %{
14634   peeppredicate(VM_Version::supports_fast_2op_lea());
14635   peepmatch (addI_rReg);
14636   peepprocedure (lea_coalesce_reg);
14637   peepreplace (leaI_rReg_rReg_peep());
14638 %}
14639 
14640 peephole
14641 %{
14642   peeppredicate(VM_Version::supports_fast_2op_lea());
14643   peepmatch (addI_rReg_imm);
14644   peepprocedure (lea_coalesce_imm);
14645   peepreplace (leaI_rReg_immI_peep());
14646 %}
14647 
14648 peephole
14649 %{
14650   peeppredicate(VM_Version::supports_fast_3op_lea() ||
14651                 VM_Version::is_intel_cascade_lake());
14652   peepmatch (incI_rReg);
14653   peepprocedure (lea_coalesce_imm);
14654   peepreplace (leaI_rReg_immI_peep());
14655 %}
14656 
14657 peephole
14658 %{
14659   peeppredicate(VM_Version::supports_fast_3op_lea() ||
14660                 VM_Version::is_intel_cascade_lake());
14661   peepmatch (decI_rReg);
14662   peepprocedure (lea_coalesce_imm);
14663   peepreplace (leaI_rReg_immI_peep());
14664 %}
14665 
14666 peephole
14667 %{
14668   peeppredicate(VM_Version::supports_fast_2op_lea());
14669   peepmatch (salI_rReg_immI2);
14670   peepprocedure (lea_coalesce_imm);
14671   peepreplace (leaI_rReg_immI2_peep());
14672 %}
14673 
14674 peephole
14675 %{
14676   peeppredicate(VM_Version::supports_fast_2op_lea());
14677   peepmatch (addL_rReg);
14678   peepprocedure (lea_coalesce_reg);
14679   peepreplace (leaL_rReg_rReg_peep());
14680 %}
14681 
14682 peephole
14683 %{
14684   peeppredicate(VM_Version::supports_fast_2op_lea());
14685   peepmatch (addL_rReg_imm);
14686   peepprocedure (lea_coalesce_imm);
14687   peepreplace (leaL_rReg_immL32_peep());
14688 %}
14689 
14690 peephole
14691 %{
14692   peeppredicate(VM_Version::supports_fast_3op_lea() ||
14693                 VM_Version::is_intel_cascade_lake());
14694   peepmatch (incL_rReg);
14695   peepprocedure (lea_coalesce_imm);
14696   peepreplace (leaL_rReg_immL32_peep());
14697 %}
14698 
14699 peephole
14700 %{
14701   peeppredicate(VM_Version::supports_fast_3op_lea() ||
14702                 VM_Version::is_intel_cascade_lake());
14703   peepmatch (decL_rReg);
14704   peepprocedure (lea_coalesce_imm);
14705   peepreplace (leaL_rReg_immL32_peep());
14706 %}
14707 
14708 peephole
14709 %{
14710   peeppredicate(VM_Version::supports_fast_2op_lea());
14711   peepmatch (salL_rReg_immI2);
14712   peepprocedure (lea_coalesce_imm);
14713   peepreplace (leaL_rReg_immI2_peep());
14714 %}
14715 
14716 // These peephole rules matches instructions which set flags and are followed by a testI/L_reg
14717 // The test instruction is redudanent in case the downstream instuctions (like JCC or CMOV) only use flags that are already set by the previous instruction
14718 
14719 //int variant
14720 peephole
14721 %{
14722   peepmatch (testI_reg);
14723   peepprocedure (test_may_remove);
14724 %}
14725 
14726 //long variant
14727 peephole
14728 %{
14729   peepmatch (testL_reg);
14730   peepprocedure (test_may_remove);
14731 %}
14732 
14733 
14734 //----------SMARTSPILL RULES---------------------------------------------------
14735 // These must follow all instruction definitions as they use the names
14736 // defined in the instructions definitions.