1 /*
   2  * Copyright (c) 2005, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "c1/c1_CFGPrinter.hpp"
  27 #include "c1/c1_CodeStubs.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_FrameMap.hpp"
  30 #include "c1/c1_IR.hpp"
  31 #include "c1/c1_LIRGenerator.hpp"
  32 #include "c1/c1_LinearScan.hpp"
  33 #include "c1/c1_ValueStack.hpp"
  34 #include "code/vmreg.inline.hpp"
  35 #include "runtime/timerTrace.hpp"
  36 #include "utilities/bitMap.inline.hpp"
  37 
  38 #ifndef PRODUCT
  39 
  40   static LinearScanStatistic _stat_before_alloc;
  41   static LinearScanStatistic _stat_after_asign;
  42   static LinearScanStatistic _stat_final;
  43 
  44   static LinearScanTimers _total_timer;
  45 
  46   // helper macro for short definition of timer
  47   #define TIME_LINEAR_SCAN(timer_name)  TraceTime _block_timer("", _total_timer.timer(LinearScanTimers::timer_name), TimeLinearScan || TimeEachLinearScan, Verbose);
  48 
  49 #else
  50   #define TIME_LINEAR_SCAN(timer_name)
  51 #endif
  52 
  53 #ifdef ASSERT
  54 
  55   // helper macro for short definition of trace-output inside code
  56   #define TRACE_LINEAR_SCAN(level, code)       \
  57     if (TraceLinearScanLevel >= level) {       \
  58       code;                                    \
  59     }
  60 #else
  61   #define TRACE_LINEAR_SCAN(level, code)
  62 #endif
  63 
  64 // Map BasicType to spill size in 32-bit words, matching VMReg's notion of words
  65 #ifdef _LP64
  66 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 2, 2, 0, 2,  1, 2, 1, -1};
  67 #else
  68 static int type2spill_size[T_CONFLICT+1]={ -1, 0, 0, 0, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 0, 1, -1, 1, 1, -1};
  69 #endif
  70 
  71 
  72 // Implementation of LinearScan
  73 
  74 LinearScan::LinearScan(IR* ir, LIRGenerator* gen, FrameMap* frame_map)
  75  : _compilation(ir->compilation())
  76  , _ir(ir)
  77  , _gen(gen)
  78  , _frame_map(frame_map)
  79  , _cached_blocks(*ir->linear_scan_order())
  80  , _num_virtual_regs(gen->max_virtual_register_number())
  81  , _has_fpu_registers(false)
  82  , _num_calls(-1)
  83  , _max_spills(0)
  84  , _unused_spill_slot(-1)
  85  , _intervals(0)   // initialized later with correct length
  86  , _new_intervals_from_allocation(NULL)
  87  , _sorted_intervals(NULL)
  88  , _needs_full_resort(false)
  89  , _lir_ops(0)     // initialized later with correct length
  90  , _block_of_op(0) // initialized later with correct length
  91  , _has_info(0)
  92  , _has_call(0)
  93  , _interval_in_loop(0)  // initialized later with correct length
  94  , _scope_value_cache(0) // initialized later with correct length
  95 #ifdef IA32
  96  , _fpu_stack_allocator(NULL)
  97 #endif
  98 {
  99   assert(this->ir() != NULL,          "check if valid");
 100   assert(this->compilation() != NULL, "check if valid");
 101   assert(this->gen() != NULL,         "check if valid");
 102   assert(this->frame_map() != NULL,   "check if valid");
 103 }
 104 
 105 
 106 // ********** functions for converting LIR-Operands to register numbers
 107 //
 108 // Emulate a flat register file comprising physical integer registers,
 109 // physical floating-point registers and virtual registers, in that order.
 110 // Virtual registers already have appropriate numbers, since V0 is
 111 // the number of physical registers.
 112 // Returns -1 for hi word if opr is a single word operand.
 113 //
 114 // Note: the inverse operation (calculating an operand for register numbers)
 115 //       is done in calc_operand_for_interval()
 116 
 117 int LinearScan::reg_num(LIR_Opr opr) {
 118   assert(opr->is_register(), "should not call this otherwise");
 119 
 120   if (opr->is_virtual_register()) {
 121     assert(opr->vreg_number() >= nof_regs, "found a virtual register with a fixed-register number");
 122     return opr->vreg_number();
 123   } else if (opr->is_single_cpu()) {
 124     return opr->cpu_regnr();
 125   } else if (opr->is_double_cpu()) {
 126     return opr->cpu_regnrLo();
 127 #ifdef X86
 128   } else if (opr->is_single_xmm()) {
 129     return opr->fpu_regnr() + pd_first_xmm_reg;
 130   } else if (opr->is_double_xmm()) {
 131     return opr->fpu_regnrLo() + pd_first_xmm_reg;
 132 #endif
 133   } else if (opr->is_single_fpu()) {
 134     return opr->fpu_regnr() + pd_first_fpu_reg;
 135   } else if (opr->is_double_fpu()) {
 136     return opr->fpu_regnrLo() + pd_first_fpu_reg;
 137   } else {
 138     ShouldNotReachHere();
 139     return -1;
 140   }
 141 }
 142 
 143 int LinearScan::reg_numHi(LIR_Opr opr) {
 144   assert(opr->is_register(), "should not call this otherwise");
 145 
 146   if (opr->is_virtual_register()) {
 147     return -1;
 148   } else if (opr->is_single_cpu()) {
 149     return -1;
 150   } else if (opr->is_double_cpu()) {
 151     return opr->cpu_regnrHi();
 152 #ifdef X86
 153   } else if (opr->is_single_xmm()) {
 154     return -1;
 155   } else if (opr->is_double_xmm()) {
 156     return -1;
 157 #endif
 158   } else if (opr->is_single_fpu()) {
 159     return -1;
 160   } else if (opr->is_double_fpu()) {
 161     return opr->fpu_regnrHi() + pd_first_fpu_reg;
 162   } else {
 163     ShouldNotReachHere();
 164     return -1;
 165   }
 166 }
 167 
 168 
 169 // ********** functions for classification of intervals
 170 
 171 bool LinearScan::is_precolored_interval(const Interval* i) {
 172   return i->reg_num() < LinearScan::nof_regs;
 173 }
 174 
 175 bool LinearScan::is_virtual_interval(const Interval* i) {
 176   return i->reg_num() >= LIR_Opr::vreg_base;
 177 }
 178 
 179 bool LinearScan::is_precolored_cpu_interval(const Interval* i) {
 180   return i->reg_num() < LinearScan::nof_cpu_regs;
 181 }
 182 
 183 bool LinearScan::is_virtual_cpu_interval(const Interval* i) {
 184 #if defined(__SOFTFP__) || defined(E500V2)
 185   return i->reg_num() >= LIR_Opr::vreg_base;
 186 #else
 187   return i->reg_num() >= LIR_Opr::vreg_base && (i->type() != T_FLOAT && i->type() != T_DOUBLE);
 188 #endif // __SOFTFP__ or E500V2
 189 }
 190 
 191 bool LinearScan::is_precolored_fpu_interval(const Interval* i) {
 192   return i->reg_num() >= LinearScan::nof_cpu_regs && i->reg_num() < LinearScan::nof_regs;
 193 }
 194 
 195 bool LinearScan::is_virtual_fpu_interval(const Interval* i) {
 196 #if defined(__SOFTFP__) || defined(E500V2)
 197   return false;
 198 #else
 199   return i->reg_num() >= LIR_Opr::vreg_base && (i->type() == T_FLOAT || i->type() == T_DOUBLE);
 200 #endif // __SOFTFP__ or E500V2
 201 }
 202 
 203 bool LinearScan::is_in_fpu_register(const Interval* i) {
 204   // fixed intervals not needed for FPU stack allocation
 205   return i->reg_num() >= nof_regs && pd_first_fpu_reg <= i->assigned_reg() && i->assigned_reg() <= pd_last_fpu_reg;
 206 }
 207 
 208 bool LinearScan::is_oop_interval(const Interval* i) {
 209   // fixed intervals never contain oops
 210   return i->reg_num() >= nof_regs && i->type() == T_OBJECT;
 211 }
 212 
 213 
 214 // ********** General helper functions
 215 
 216 // compute next unused stack index that can be used for spilling
 217 int LinearScan::allocate_spill_slot(bool double_word) {
 218   int spill_slot;
 219   if (double_word) {
 220     if ((_max_spills & 1) == 1) {
 221       // alignment of double-word values
 222       // the hole because of the alignment is filled with the next single-word value
 223       assert(_unused_spill_slot == -1, "wasting a spill slot");
 224       _unused_spill_slot = _max_spills;
 225       _max_spills++;
 226     }
 227     spill_slot = _max_spills;
 228     _max_spills += 2;
 229 
 230   } else if (_unused_spill_slot != -1) {
 231     // re-use hole that was the result of a previous double-word alignment
 232     spill_slot = _unused_spill_slot;
 233     _unused_spill_slot = -1;
 234 
 235   } else {
 236     spill_slot = _max_spills;
 237     _max_spills++;
 238   }
 239 
 240   int result = spill_slot + LinearScan::nof_regs + frame_map()->argcount();
 241 
 242   // if too many slots used, bailout compilation.
 243   if (result > 2000) {
 244     bailout("too many stack slots used");
 245   }
 246 
 247   return result;
 248 }
 249 
 250 void LinearScan::assign_spill_slot(Interval* it) {
 251   // assign the canonical spill slot of the parent (if a part of the interval
 252   // is already spilled) or allocate a new spill slot
 253   if (it->canonical_spill_slot() >= 0) {
 254     it->assign_reg(it->canonical_spill_slot());
 255   } else {
 256     int spill = allocate_spill_slot(type2spill_size[it->type()] == 2);
 257     it->set_canonical_spill_slot(spill);
 258     it->assign_reg(spill);
 259   }
 260 }
 261 
 262 void LinearScan::propagate_spill_slots() {
 263   if (!frame_map()->finalize_frame(max_spills())) {
 264     bailout("frame too large");
 265   }
 266 }
 267 
 268 // create a new interval with a predefined reg_num
 269 // (only used for parent intervals that are created during the building phase)
 270 Interval* LinearScan::create_interval(int reg_num) {
 271   assert(_intervals.at(reg_num) == NULL, "overwriting existing interval");
 272 
 273   Interval* interval = new Interval(reg_num);
 274   _intervals.at_put(reg_num, interval);
 275 
 276   // assign register number for precolored intervals
 277   if (reg_num < LIR_Opr::vreg_base) {
 278     interval->assign_reg(reg_num);
 279   }
 280   return interval;
 281 }
 282 
 283 // assign a new reg_num to the interval and append it to the list of intervals
 284 // (only used for child intervals that are created during register allocation)
 285 void LinearScan::append_interval(Interval* it) {
 286   it->set_reg_num(_intervals.length());
 287   _intervals.append(it);
 288   IntervalList* new_intervals = _new_intervals_from_allocation;
 289   if (new_intervals == NULL) {
 290     new_intervals = _new_intervals_from_allocation = new IntervalList();
 291   }
 292   new_intervals->append(it);
 293 }
 294 
 295 // copy the vreg-flags if an interval is split
 296 void LinearScan::copy_register_flags(Interval* from, Interval* to) {
 297   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::byte_reg)) {
 298     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::byte_reg);
 299   }
 300   if (gen()->is_vreg_flag_set(from->reg_num(), LIRGenerator::callee_saved)) {
 301     gen()->set_vreg_flag(to->reg_num(), LIRGenerator::callee_saved);
 302   }
 303 
 304   // Note: do not copy the must_start_in_memory flag because it is not necessary for child
 305   //       intervals (only the very beginning of the interval must be in memory)
 306 }
 307 
 308 
 309 // ********** spill move optimization
 310 // eliminate moves from register to stack if stack slot is known to be correct
 311 
 312 // called during building of intervals
 313 void LinearScan::change_spill_definition_pos(Interval* interval, int def_pos) {
 314   assert(interval->is_split_parent(), "can only be called for split parents");
 315 
 316   switch (interval->spill_state()) {
 317     case noDefinitionFound:
 318       assert(interval->spill_definition_pos() == -1, "must no be set before");
 319       interval->set_spill_definition_pos(def_pos);
 320       interval->set_spill_state(oneDefinitionFound);
 321       break;
 322 
 323     case oneDefinitionFound:
 324       assert(def_pos <= interval->spill_definition_pos(), "positions are processed in reverse order when intervals are created");
 325       if (def_pos < interval->spill_definition_pos() - 2) {
 326         // second definition found, so no spill optimization possible for this interval
 327         interval->set_spill_state(noOptimization);
 328       } else {
 329         // two consecutive definitions (because of two-operand LIR form)
 330         assert(block_of_op_with_id(def_pos) == block_of_op_with_id(interval->spill_definition_pos()), "block must be equal");
 331       }
 332       break;
 333 
 334     case noOptimization:
 335       // nothing to do
 336       break;
 337 
 338     default:
 339       assert(false, "other states not allowed at this time");
 340   }
 341 }
 342 
 343 // called during register allocation
 344 void LinearScan::change_spill_state(Interval* interval, int spill_pos) {
 345   switch (interval->spill_state()) {
 346     case oneDefinitionFound: {
 347       int def_loop_depth = block_of_op_with_id(interval->spill_definition_pos())->loop_depth();
 348       int spill_loop_depth = block_of_op_with_id(spill_pos)->loop_depth();
 349 
 350       if (def_loop_depth < spill_loop_depth) {
 351         // the loop depth of the spilling position is higher then the loop depth
 352         // at the definition of the interval -> move write to memory out of loop
 353         // by storing at definitin of the interval
 354         interval->set_spill_state(storeAtDefinition);
 355       } else {
 356         // the interval is currently spilled only once, so for now there is no
 357         // reason to store the interval at the definition
 358         interval->set_spill_state(oneMoveInserted);
 359       }
 360       break;
 361     }
 362 
 363     case oneMoveInserted: {
 364       // the interval is spilled more then once, so it is better to store it to
 365       // memory at the definition
 366       interval->set_spill_state(storeAtDefinition);
 367       break;
 368     }
 369 
 370     case storeAtDefinition:
 371     case startInMemory:
 372     case noOptimization:
 373     case noDefinitionFound:
 374       // nothing to do
 375       break;
 376 
 377     default:
 378       assert(false, "other states not allowed at this time");
 379   }
 380 }
 381 
 382 
 383 bool LinearScan::must_store_at_definition(const Interval* i) {
 384   return i->is_split_parent() && i->spill_state() == storeAtDefinition;
 385 }
 386 
 387 // called once before assignment of register numbers
 388 void LinearScan::eliminate_spill_moves() {
 389   TIME_LINEAR_SCAN(timer_eliminate_spill_moves);
 390   TRACE_LINEAR_SCAN(3, tty->print_cr("***** Eliminating unnecessary spill moves"));
 391 
 392   // collect all intervals that must be stored after their definion.
 393   // the list is sorted by Interval::spill_definition_pos
 394   Interval* interval;
 395   Interval* temp_list;
 396   create_unhandled_lists(&interval, &temp_list, must_store_at_definition, NULL);
 397 
 398 #ifdef ASSERT
 399   Interval* prev = NULL;
 400   Interval* temp = interval;
 401   while (temp != Interval::end()) {
 402     assert(temp->spill_definition_pos() > 0, "invalid spill definition pos");
 403     if (prev != NULL) {
 404       assert(temp->from() >= prev->from(), "intervals not sorted");
 405       assert(temp->spill_definition_pos() >= prev->spill_definition_pos(), "when intervals are sorted by from, then they must also be sorted by spill_definition_pos");
 406     }
 407 
 408     assert(temp->canonical_spill_slot() >= LinearScan::nof_regs, "interval has no spill slot assigned");
 409     assert(temp->spill_definition_pos() >= temp->from(), "invalid order");
 410     assert(temp->spill_definition_pos() <= temp->from() + 2, "only intervals defined once at their start-pos can be optimized");
 411 
 412     TRACE_LINEAR_SCAN(4, tty->print_cr("interval %d (from %d to %d) must be stored at %d", temp->reg_num(), temp->from(), temp->to(), temp->spill_definition_pos()));
 413 
 414     temp = temp->next();
 415   }
 416 #endif
 417 
 418   LIR_InsertionBuffer insertion_buffer;
 419   int num_blocks = block_count();
 420   for (int i = 0; i < num_blocks; i++) {
 421     BlockBegin* block = block_at(i);
 422     LIR_OpList* instructions = block->lir()->instructions_list();
 423     int         num_inst = instructions->length();
 424     bool        has_new = false;
 425 
 426     // iterate all instructions of the block. skip the first because it is always a label
 427     for (int j = 1; j < num_inst; j++) {
 428       LIR_Op* op = instructions->at(j);
 429       int op_id = op->id();
 430 
 431       if (op_id == -1) {
 432         // remove move from register to stack if the stack slot is guaranteed to be correct.
 433         // only moves that have been inserted by LinearScan can be removed.
 434         assert(op->code() == lir_move, "only moves can have a op_id of -1");
 435         assert(op->as_Op1() != NULL, "move must be LIR_Op1");
 436         assert(op->as_Op1()->result_opr()->is_virtual(), "LinearScan inserts only moves to virtual registers");
 437 
 438         LIR_Op1* op1 = (LIR_Op1*)op;
 439         Interval* interval = interval_at(op1->result_opr()->vreg_number());
 440 
 441         if (interval->assigned_reg() >= LinearScan::nof_regs && interval->always_in_memory()) {
 442           // move target is a stack slot that is always correct, so eliminate instruction
 443           TRACE_LINEAR_SCAN(4, tty->print_cr("eliminating move from interval %d to %d", op1->in_opr()->vreg_number(), op1->result_opr()->vreg_number()));
 444           instructions->at_put(j, NULL); // NULL-instructions are deleted by assign_reg_num
 445         }
 446 
 447       } else {
 448         // insert move from register to stack just after the beginning of the interval
 449         assert(interval == Interval::end() || interval->spill_definition_pos() >= op_id, "invalid order");
 450         assert(interval == Interval::end() || (interval->is_split_parent() && interval->spill_state() == storeAtDefinition), "invalid interval");
 451 
 452         while (interval != Interval::end() && interval->spill_definition_pos() == op_id) {
 453           if (!has_new) {
 454             // prepare insertion buffer (appended when all instructions of the block are processed)
 455             insertion_buffer.init(block->lir());
 456             has_new = true;
 457           }
 458 
 459           LIR_Opr from_opr = operand_for_interval(interval);
 460           LIR_Opr to_opr = canonical_spill_opr(interval);
 461           assert(from_opr->is_fixed_cpu() || from_opr->is_fixed_fpu(), "from operand must be a register");
 462           assert(to_opr->is_stack(), "to operand must be a stack slot");
 463 
 464           insertion_buffer.move(j, from_opr, to_opr);
 465           TRACE_LINEAR_SCAN(4, tty->print_cr("inserting move after definition of interval %d to stack slot %d at op_id %d", interval->reg_num(), interval->canonical_spill_slot() - LinearScan::nof_regs, op_id));
 466 
 467           interval = interval->next();
 468         }
 469       }
 470     } // end of instruction iteration
 471 
 472     if (has_new) {
 473       block->lir()->append(&insertion_buffer);
 474     }
 475   } // end of block iteration
 476 
 477   assert(interval == Interval::end(), "missed an interval");
 478 }
 479 
 480 
 481 // ********** Phase 1: number all instructions in all blocks
 482 // Compute depth-first and linear scan block orders, and number LIR_Op nodes for linear scan.
 483 
 484 void LinearScan::number_instructions() {
 485   {
 486     // dummy-timer to measure the cost of the timer itself
 487     // (this time is then subtracted from all other timers to get the real value)
 488     TIME_LINEAR_SCAN(timer_do_nothing);
 489   }
 490   TIME_LINEAR_SCAN(timer_number_instructions);
 491 
 492   // Assign IDs to LIR nodes and build a mapping, lir_ops, from ID to LIR_Op node.
 493   int num_blocks = block_count();
 494   int num_instructions = 0;
 495   int i;
 496   for (i = 0; i < num_blocks; i++) {
 497     num_instructions += block_at(i)->lir()->instructions_list()->length();
 498   }
 499 
 500   // initialize with correct length
 501   _lir_ops = LIR_OpArray(num_instructions, num_instructions, NULL);
 502   _block_of_op = BlockBeginArray(num_instructions, num_instructions, NULL);
 503 
 504   int op_id = 0;
 505   int idx = 0;
 506 
 507   for (i = 0; i < num_blocks; i++) {
 508     BlockBegin* block = block_at(i);
 509     block->set_first_lir_instruction_id(op_id);
 510     LIR_OpList* instructions = block->lir()->instructions_list();
 511 
 512     int num_inst = instructions->length();
 513     for (int j = 0; j < num_inst; j++) {
 514       LIR_Op* op = instructions->at(j);
 515       op->set_id(op_id);
 516 
 517       _lir_ops.at_put(idx, op);
 518       _block_of_op.at_put(idx, block);
 519       assert(lir_op_with_id(op_id) == op, "must match");
 520 
 521       idx++;
 522       op_id += 2; // numbering of lir_ops by two
 523     }
 524     block->set_last_lir_instruction_id(op_id - 2);
 525   }
 526   assert(idx == num_instructions, "must match");
 527   assert(idx * 2 == op_id, "must match");
 528 
 529   _has_call.initialize(num_instructions);
 530   _has_info.initialize(num_instructions);
 531 }
 532 
 533 
 534 // ********** Phase 2: compute local live sets separately for each block
 535 // (sets live_gen and live_kill for each block)
 536 
 537 void LinearScan::set_live_gen_kill(Value value, LIR_Op* op, BitMap& live_gen, BitMap& live_kill) {
 538   LIR_Opr opr = value->operand();
 539   Constant* con = value->as_Constant();
 540 
 541   // check some asumptions about debug information
 542   assert(!value->type()->is_illegal(), "if this local is used by the interpreter it shouldn't be of indeterminate type");
 543   assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands");
 544   assert(con != NULL || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
 545 
 546   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 547     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 548     int reg = opr->vreg_number();
 549     if (!live_kill.at(reg)) {
 550       live_gen.set_bit(reg);
 551       TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for value %c%d, LIR op_id %d, register number %d", value->type()->tchar(), value->id(), op->id(), reg));
 552     }
 553   }
 554 }
 555 
 556 
 557 void LinearScan::compute_local_live_sets() {
 558   TIME_LINEAR_SCAN(timer_compute_local_live_sets);
 559 
 560   int  num_blocks = block_count();
 561   int  live_size = live_set_size();
 562   bool local_has_fpu_registers = false;
 563   int  local_num_calls = 0;
 564   LIR_OpVisitState visitor;
 565 
 566   BitMap2D local_interval_in_loop = BitMap2D(_num_virtual_regs, num_loops());
 567 
 568   // iterate all blocks
 569   for (int i = 0; i < num_blocks; i++) {
 570     BlockBegin* block = block_at(i);
 571 
 572     ResourceBitMap live_gen(live_size);
 573     ResourceBitMap live_kill(live_size);
 574 
 575     if (block->is_set(BlockBegin::exception_entry_flag)) {
 576       // Phi functions at the begin of an exception handler are
 577       // implicitly defined (= killed) at the beginning of the block.
 578       for_each_phi_fun(block, phi,
 579         if (!phi->is_illegal()) { live_kill.set_bit(phi->operand()->vreg_number()); }
 580       );
 581     }
 582 
 583     LIR_OpList* instructions = block->lir()->instructions_list();
 584     int num_inst = instructions->length();
 585 
 586     // iterate all instructions of the block. skip the first because it is always a label
 587     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
 588     for (int j = 1; j < num_inst; j++) {
 589       LIR_Op* op = instructions->at(j);
 590 
 591       // visit operation to collect all operands
 592       visitor.visit(op);
 593 
 594       if (visitor.has_call()) {
 595         _has_call.set_bit(op->id() >> 1);
 596         local_num_calls++;
 597       }
 598       if (visitor.info_count() > 0) {
 599         _has_info.set_bit(op->id() >> 1);
 600       }
 601 
 602       // iterate input operands of instruction
 603       int k, n, reg;
 604       n = visitor.opr_count(LIR_OpVisitState::inputMode);
 605       for (k = 0; k < n; k++) {
 606         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
 607         assert(opr->is_register(), "visitor should only return register operands");
 608 
 609         if (opr->is_virtual_register()) {
 610           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 611           reg = opr->vreg_number();
 612           if (!live_kill.at(reg)) {
 613             live_gen.set_bit(reg);
 614             TRACE_LINEAR_SCAN(4, tty->print_cr("  Setting live_gen for register %d at instruction %d", reg, op->id()));
 615           }
 616           if (block->loop_index() >= 0) {
 617             local_interval_in_loop.set_bit(reg, block->loop_index());
 618           }
 619           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 620         }
 621 
 622 #ifdef ASSERT
 623         // fixed intervals are never live at block boundaries, so
 624         // they need not be processed in live sets.
 625         // this is checked by these assertions to be sure about it.
 626         // the entry block may have incoming values in registers, which is ok.
 627         if (!opr->is_virtual_register() && block != ir()->start()) {
 628           reg = reg_num(opr);
 629           if (is_processed_reg_num(reg)) {
 630             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 631           }
 632           reg = reg_numHi(opr);
 633           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 634             assert(live_kill.at(reg), "using fixed register that is not defined in this block");
 635           }
 636         }
 637 #endif
 638       }
 639 
 640       // Add uses of live locals from interpreter's point of view for proper debug information generation
 641       n = visitor.info_count();
 642       for (k = 0; k < n; k++) {
 643         CodeEmitInfo* info = visitor.info_at(k);
 644         ValueStack* stack = info->stack();
 645         for_each_state_value(stack, value,
 646           set_live_gen_kill(value, op, live_gen, live_kill);
 647           local_has_fpu_registers = local_has_fpu_registers || value->type()->is_float_kind();
 648         );
 649       }
 650 
 651       // iterate temp operands of instruction
 652       n = visitor.opr_count(LIR_OpVisitState::tempMode);
 653       for (k = 0; k < n; k++) {
 654         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
 655         assert(opr->is_register(), "visitor should only return register operands");
 656 
 657         if (opr->is_virtual_register()) {
 658           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 659           reg = opr->vreg_number();
 660           live_kill.set_bit(reg);
 661           if (block->loop_index() >= 0) {
 662             local_interval_in_loop.set_bit(reg, block->loop_index());
 663           }
 664           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 665         }
 666 
 667 #ifdef ASSERT
 668         // fixed intervals are never live at block boundaries, so
 669         // they need not be processed in live sets
 670         // process them only in debug mode so that this can be checked
 671         if (!opr->is_virtual_register()) {
 672           reg = reg_num(opr);
 673           if (is_processed_reg_num(reg)) {
 674             live_kill.set_bit(reg_num(opr));
 675           }
 676           reg = reg_numHi(opr);
 677           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 678             live_kill.set_bit(reg);
 679           }
 680         }
 681 #endif
 682       }
 683 
 684       // iterate output operands of instruction
 685       n = visitor.opr_count(LIR_OpVisitState::outputMode);
 686       for (k = 0; k < n; k++) {
 687         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
 688         assert(opr->is_register(), "visitor should only return register operands");
 689 
 690         if (opr->is_virtual_register()) {
 691           assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 692           reg = opr->vreg_number();
 693           live_kill.set_bit(reg);
 694           if (block->loop_index() >= 0) {
 695             local_interval_in_loop.set_bit(reg, block->loop_index());
 696           }
 697           local_has_fpu_registers = local_has_fpu_registers || opr->is_virtual_fpu();
 698         }
 699 
 700 #ifdef ASSERT
 701         // fixed intervals are never live at block boundaries, so
 702         // they need not be processed in live sets
 703         // process them only in debug mode so that this can be checked
 704         if (!opr->is_virtual_register()) {
 705           reg = reg_num(opr);
 706           if (is_processed_reg_num(reg)) {
 707             live_kill.set_bit(reg_num(opr));
 708           }
 709           reg = reg_numHi(opr);
 710           if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 711             live_kill.set_bit(reg);
 712           }
 713         }
 714 #endif
 715       }
 716     } // end of instruction iteration
 717 
 718     block->set_live_gen (live_gen);
 719     block->set_live_kill(live_kill);
 720     block->set_live_in  (ResourceBitMap(live_size));
 721     block->set_live_out (ResourceBitMap(live_size));
 722 
 723     TRACE_LINEAR_SCAN(4, tty->print("live_gen  B%d ", block->block_id()); print_bitmap(block->live_gen()));
 724     TRACE_LINEAR_SCAN(4, tty->print("live_kill B%d ", block->block_id()); print_bitmap(block->live_kill()));
 725   } // end of block iteration
 726 
 727   // propagate local calculated information into LinearScan object
 728   _has_fpu_registers = local_has_fpu_registers;
 729   compilation()->set_has_fpu_code(local_has_fpu_registers);
 730 
 731   _num_calls = local_num_calls;
 732   _interval_in_loop = local_interval_in_loop;
 733 }
 734 
 735 
 736 // ********** Phase 3: perform a backward dataflow analysis to compute global live sets
 737 // (sets live_in and live_out for each block)
 738 
 739 void LinearScan::compute_global_live_sets() {
 740   TIME_LINEAR_SCAN(timer_compute_global_live_sets);
 741 
 742   int  num_blocks = block_count();
 743   bool change_occurred;
 744   bool change_occurred_in_block;
 745   int  iteration_count = 0;
 746   ResourceBitMap live_out(live_set_size()); // scratch set for calculations
 747 
 748   // Perform a backward dataflow analysis to compute live_out and live_in for each block.
 749   // The loop is executed until a fixpoint is reached (no changes in an iteration)
 750   // Exception handlers must be processed because not all live values are
 751   // present in the state array, e.g. because of global value numbering
 752   do {
 753     change_occurred = false;
 754 
 755     // iterate all blocks in reverse order
 756     for (int i = num_blocks - 1; i >= 0; i--) {
 757       BlockBegin* block = block_at(i);
 758 
 759       change_occurred_in_block = false;
 760 
 761       // live_out(block) is the union of live_in(sux), for successors sux of block
 762       int n = block->number_of_sux();
 763       int e = block->number_of_exception_handlers();
 764       if (n + e > 0) {
 765         // block has successors
 766         if (n > 0) {
 767           live_out.set_from(block->sux_at(0)->live_in());
 768           for (int j = 1; j < n; j++) {
 769             live_out.set_union(block->sux_at(j)->live_in());
 770           }
 771         } else {
 772           live_out.clear();
 773         }
 774         for (int j = 0; j < e; j++) {
 775           live_out.set_union(block->exception_handler_at(j)->live_in());
 776         }
 777 
 778         if (!block->live_out().is_same(live_out)) {
 779           // A change occurred.  Swap the old and new live out sets to avoid copying.
 780           ResourceBitMap temp = block->live_out();
 781           block->set_live_out(live_out);
 782           live_out = temp;
 783 
 784           change_occurred = true;
 785           change_occurred_in_block = true;
 786         }
 787       }
 788 
 789       if (iteration_count == 0 || change_occurred_in_block) {
 790         // live_in(block) is the union of live_gen(block) with (live_out(block) & !live_kill(block))
 791         // note: live_in has to be computed only in first iteration or if live_out has changed!
 792         ResourceBitMap live_in = block->live_in();
 793         live_in.set_from(block->live_out());
 794         live_in.set_difference(block->live_kill());
 795         live_in.set_union(block->live_gen());
 796       }
 797 
 798 #ifdef ASSERT
 799       if (TraceLinearScanLevel >= 4) {
 800         char c = ' ';
 801         if (iteration_count == 0 || change_occurred_in_block) {
 802           c = '*';
 803         }
 804         tty->print("(%d) live_in%c  B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_in());
 805         tty->print("(%d) live_out%c B%d ", iteration_count, c, block->block_id()); print_bitmap(block->live_out());
 806       }
 807 #endif
 808     }
 809     iteration_count++;
 810 
 811     if (change_occurred && iteration_count > 50) {
 812       BAILOUT("too many iterations in compute_global_live_sets");
 813     }
 814   } while (change_occurred);
 815 
 816 
 817 #ifdef ASSERT
 818   // check that fixed intervals are not live at block boundaries
 819   // (live set must be empty at fixed intervals)
 820   for (int i = 0; i < num_blocks; i++) {
 821     BlockBegin* block = block_at(i);
 822     for (int j = 0; j < LIR_Opr::vreg_base; j++) {
 823       assert(block->live_in().at(j)  == false, "live_in  set of fixed register must be empty");
 824       assert(block->live_out().at(j) == false, "live_out set of fixed register must be empty");
 825       assert(block->live_gen().at(j) == false, "live_gen set of fixed register must be empty");
 826     }
 827   }
 828 #endif
 829 
 830   // check that the live_in set of the first block is empty
 831   ResourceBitMap live_in_args(ir()->start()->live_in().size());
 832   if (!ir()->start()->live_in().is_same(live_in_args)) {
 833 #ifdef ASSERT
 834     tty->print_cr("Error: live_in set of first block must be empty (when this fails, virtual registers are used before they are defined)");
 835     tty->print_cr("affected registers:");
 836     print_bitmap(ir()->start()->live_in());
 837 
 838     // print some additional information to simplify debugging
 839     for (unsigned int i = 0; i < ir()->start()->live_in().size(); i++) {
 840       if (ir()->start()->live_in().at(i)) {
 841         Instruction* instr = gen()->instruction_for_vreg(i);
 842         tty->print_cr("* vreg %d (HIR instruction %c%d)", i, instr == NULL ? ' ' : instr->type()->tchar(), instr == NULL ? 0 : instr->id());
 843 
 844         for (int j = 0; j < num_blocks; j++) {
 845           BlockBegin* block = block_at(j);
 846           if (block->live_gen().at(i)) {
 847             tty->print_cr("  used in block B%d", block->block_id());
 848           }
 849           if (block->live_kill().at(i)) {
 850             tty->print_cr("  defined in block B%d", block->block_id());
 851           }
 852         }
 853       }
 854     }
 855 
 856 #endif
 857     // when this fails, virtual registers are used before they are defined.
 858     assert(false, "live_in set of first block must be empty");
 859     // bailout of if this occurs in product mode.
 860     bailout("live_in set of first block not empty");
 861   }
 862 }
 863 
 864 
 865 // ********** Phase 4: build intervals
 866 // (fills the list _intervals)
 867 
 868 void LinearScan::add_use(Value value, int from, int to, IntervalUseKind use_kind) {
 869   assert(!value->type()->is_illegal(), "if this value is used by the interpreter it shouldn't be of indeterminate type");
 870   LIR_Opr opr = value->operand();
 871   Constant* con = value->as_Constant();
 872 
 873   if ((con == NULL || con->is_pinned()) && opr->is_register()) {
 874     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 875     add_use(opr, from, to, use_kind);
 876   }
 877 }
 878 
 879 
 880 void LinearScan::add_def(LIR_Opr opr, int def_pos, IntervalUseKind use_kind) {
 881   TRACE_LINEAR_SCAN(2, tty->print(" def "); opr->print(tty); tty->print_cr(" def_pos %d (%d)", def_pos, use_kind));
 882   assert(opr->is_register(), "should not be called otherwise");
 883 
 884   if (opr->is_virtual_register()) {
 885     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 886     add_def(opr->vreg_number(), def_pos, use_kind, opr->type_register());
 887 
 888   } else {
 889     int reg = reg_num(opr);
 890     if (is_processed_reg_num(reg)) {
 891       add_def(reg, def_pos, use_kind, opr->type_register());
 892     }
 893     reg = reg_numHi(opr);
 894     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 895       add_def(reg, def_pos, use_kind, opr->type_register());
 896     }
 897   }
 898 }
 899 
 900 void LinearScan::add_use(LIR_Opr opr, int from, int to, IntervalUseKind use_kind) {
 901   TRACE_LINEAR_SCAN(2, tty->print(" use "); opr->print(tty); tty->print_cr(" from %d to %d (%d)", from, to, use_kind));
 902   assert(opr->is_register(), "should not be called otherwise");
 903 
 904   if (opr->is_virtual_register()) {
 905     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 906     add_use(opr->vreg_number(), from, to, use_kind, opr->type_register());
 907 
 908   } else {
 909     int reg = reg_num(opr);
 910     if (is_processed_reg_num(reg)) {
 911       add_use(reg, from, to, use_kind, opr->type_register());
 912     }
 913     reg = reg_numHi(opr);
 914     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 915       add_use(reg, from, to, use_kind, opr->type_register());
 916     }
 917   }
 918 }
 919 
 920 void LinearScan::add_temp(LIR_Opr opr, int temp_pos, IntervalUseKind use_kind) {
 921   TRACE_LINEAR_SCAN(2, tty->print(" temp "); opr->print(tty); tty->print_cr(" temp_pos %d (%d)", temp_pos, use_kind));
 922   assert(opr->is_register(), "should not be called otherwise");
 923 
 924   if (opr->is_virtual_register()) {
 925     assert(reg_num(opr) == opr->vreg_number() && !is_valid_reg_num(reg_numHi(opr)), "invalid optimization below");
 926     add_temp(opr->vreg_number(), temp_pos, use_kind, opr->type_register());
 927 
 928   } else {
 929     int reg = reg_num(opr);
 930     if (is_processed_reg_num(reg)) {
 931       add_temp(reg, temp_pos, use_kind, opr->type_register());
 932     }
 933     reg = reg_numHi(opr);
 934     if (is_valid_reg_num(reg) && is_processed_reg_num(reg)) {
 935       add_temp(reg, temp_pos, use_kind, opr->type_register());
 936     }
 937   }
 938 }
 939 
 940 
 941 void LinearScan::add_def(int reg_num, int def_pos, IntervalUseKind use_kind, BasicType type) {
 942   Interval* interval = interval_at(reg_num);
 943   if (interval != NULL) {
 944     assert(interval->reg_num() == reg_num, "wrong interval");
 945 
 946     if (type != T_ILLEGAL) {
 947       interval->set_type(type);
 948     }
 949 
 950     Range* r = interval->first();
 951     if (r->from() <= def_pos) {
 952       // Update the starting point (when a range is first created for a use, its
 953       // start is the beginning of the current block until a def is encountered.)
 954       r->set_from(def_pos);
 955       interval->add_use_pos(def_pos, use_kind);
 956 
 957     } else {
 958       // Dead value - make vacuous interval
 959       // also add use_kind for dead intervals
 960       interval->add_range(def_pos, def_pos + 1);
 961       interval->add_use_pos(def_pos, use_kind);
 962       TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: def of reg %d at %d occurs without use", reg_num, def_pos));
 963     }
 964 
 965   } else {
 966     // Dead value - make vacuous interval
 967     // also add use_kind for dead intervals
 968     interval = create_interval(reg_num);
 969     if (type != T_ILLEGAL) {
 970       interval->set_type(type);
 971     }
 972 
 973     interval->add_range(def_pos, def_pos + 1);
 974     interval->add_use_pos(def_pos, use_kind);
 975     TRACE_LINEAR_SCAN(2, tty->print_cr("Warning: dead value %d at %d in live intervals", reg_num, def_pos));
 976   }
 977 
 978   change_spill_definition_pos(interval, def_pos);
 979   if (use_kind == noUse && interval->spill_state() <= startInMemory) {
 980         // detection of method-parameters and roundfp-results
 981         // TODO: move this directly to position where use-kind is computed
 982     interval->set_spill_state(startInMemory);
 983   }
 984 }
 985 
 986 void LinearScan::add_use(int reg_num, int from, int to, IntervalUseKind use_kind, BasicType type) {
 987   Interval* interval = interval_at(reg_num);
 988   if (interval == NULL) {
 989     interval = create_interval(reg_num);
 990   }
 991   assert(interval->reg_num() == reg_num, "wrong interval");
 992 
 993   if (type != T_ILLEGAL) {
 994     interval->set_type(type);
 995   }
 996 
 997   interval->add_range(from, to);
 998   interval->add_use_pos(to, use_kind);
 999 }
1000 
1001 void LinearScan::add_temp(int reg_num, int temp_pos, IntervalUseKind use_kind, BasicType type) {
1002   Interval* interval = interval_at(reg_num);
1003   if (interval == NULL) {
1004     interval = create_interval(reg_num);
1005   }
1006   assert(interval->reg_num() == reg_num, "wrong interval");
1007 
1008   if (type != T_ILLEGAL) {
1009     interval->set_type(type);
1010   }
1011 
1012   interval->add_range(temp_pos, temp_pos + 1);
1013   interval->add_use_pos(temp_pos, use_kind);
1014 }
1015 
1016 
1017 // the results of this functions are used for optimizing spilling and reloading
1018 // if the functions return shouldHaveRegister and the interval is spilled,
1019 // it is not reloaded to a register.
1020 IntervalUseKind LinearScan::use_kind_of_output_operand(LIR_Op* op, LIR_Opr opr) {
1021   if (op->code() == lir_move) {
1022     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1023     LIR_Op1* move = (LIR_Op1*)op;
1024     LIR_Opr res = move->result_opr();
1025     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1026 
1027     if (result_in_memory) {
1028       // Begin of an interval with must_start_in_memory set.
1029       // This interval will always get a stack slot first, so return noUse.
1030       return noUse;
1031 
1032     } else if (move->in_opr()->is_stack()) {
1033       // method argument (condition must be equal to handle_method_arguments)
1034       return noUse;
1035 
1036     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1037       // Move from register to register
1038       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1039         // special handling of phi-function moves inside osr-entry blocks
1040         // input operand must have a register instead of output operand (leads to better register allocation)
1041         return shouldHaveRegister;
1042       }
1043     }
1044   }
1045 
1046   if (opr->is_virtual() &&
1047       gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::must_start_in_memory)) {
1048     // result is a stack-slot, so prevent immediate reloading
1049     return noUse;
1050   }
1051 
1052   // all other operands require a register
1053   return mustHaveRegister;
1054 }
1055 
1056 IntervalUseKind LinearScan::use_kind_of_input_operand(LIR_Op* op, LIR_Opr opr) {
1057   if (op->code() == lir_move) {
1058     assert(op->as_Op1() != NULL, "lir_move must be LIR_Op1");
1059     LIR_Op1* move = (LIR_Op1*)op;
1060     LIR_Opr res = move->result_opr();
1061     bool result_in_memory = res->is_virtual() && gen()->is_vreg_flag_set(res->vreg_number(), LIRGenerator::must_start_in_memory);
1062 
1063     if (result_in_memory) {
1064       // Move to an interval with must_start_in_memory set.
1065       // To avoid moves from stack to stack (not allowed) force the input operand to a register
1066       return mustHaveRegister;
1067 
1068     } else if (move->in_opr()->is_register() && move->result_opr()->is_register()) {
1069       // Move from register to register
1070       if (block_of_op_with_id(op->id())->is_set(BlockBegin::osr_entry_flag)) {
1071         // special handling of phi-function moves inside osr-entry blocks
1072         // input operand must have a register instead of output operand (leads to better register allocation)
1073         return mustHaveRegister;
1074       }
1075 
1076       // The input operand is not forced to a register (moves from stack to register are allowed),
1077       // but it is faster if the input operand is in a register
1078       return shouldHaveRegister;
1079     }
1080   }
1081 
1082 
1083 #if defined(X86) || defined(S390)
1084   if (op->code() == lir_cmove) {
1085     // conditional moves can handle stack operands
1086     assert(op->result_opr()->is_register(), "result must always be in a register");
1087     return shouldHaveRegister;
1088   }
1089 
1090   // optimizations for second input operand of arithmehtic operations on Intel
1091   // this operand is allowed to be on the stack in some cases
1092   BasicType opr_type = opr->type_register();
1093   if (opr_type == T_FLOAT || opr_type == T_DOUBLE) {
1094     if (IA32_ONLY( (UseSSE == 1 && opr_type == T_FLOAT) || UseSSE >= 2 ) NOT_IA32( true )) {
1095       // SSE float instruction (T_DOUBLE only supported with SSE2)
1096       switch (op->code()) {
1097         case lir_cmp:
1098         case lir_add:
1099         case lir_sub:
1100         case lir_mul:
1101         case lir_div:
1102         {
1103           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1104           LIR_Op2* op2 = (LIR_Op2*)op;
1105           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1106             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1107             return shouldHaveRegister;
1108           }
1109         }
1110         default:
1111           break;
1112       }
1113     } else {
1114       // FPU stack float instruction
1115       switch (op->code()) {
1116         case lir_add:
1117         case lir_sub:
1118         case lir_mul:
1119         case lir_div:
1120         {
1121           assert(op->as_Op2() != NULL, "must be LIR_Op2");
1122           LIR_Op2* op2 = (LIR_Op2*)op;
1123           if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1124             assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1125             return shouldHaveRegister;
1126           }
1127         }
1128         default:
1129           break;
1130       }
1131     }
1132     // We want to sometimes use logical operations on pointers, in particular in GC barriers.
1133     // Since 64bit logical operations do not current support operands on stack, we have to make sure
1134     // T_OBJECT doesn't get spilled along with T_LONG.
1135   } else if (opr_type != T_LONG LP64_ONLY(&& opr_type != T_OBJECT)) {
1136     // integer instruction (note: long operands must always be in register)
1137     switch (op->code()) {
1138       case lir_cmp:
1139       case lir_add:
1140       case lir_sub:
1141       case lir_logic_and:
1142       case lir_logic_or:
1143       case lir_logic_xor:
1144       {
1145         assert(op->as_Op2() != NULL, "must be LIR_Op2");
1146         LIR_Op2* op2 = (LIR_Op2*)op;
1147         if (op2->in_opr1() != op2->in_opr2() && op2->in_opr2() == opr) {
1148           assert((op2->result_opr()->is_register() || op->code() == lir_cmp) && op2->in_opr1()->is_register(), "cannot mark second operand as stack if others are not in register");
1149           return shouldHaveRegister;
1150         }
1151       }
1152       default:
1153         break;
1154     }
1155   }
1156 #endif // X86 || S390
1157 
1158   // all other operands require a register
1159   return mustHaveRegister;
1160 }
1161 
1162 
1163 void LinearScan::handle_method_arguments(LIR_Op* op) {
1164   // special handling for method arguments (moves from stack to virtual register):
1165   // the interval gets no register assigned, but the stack slot.
1166   // it is split before the first use by the register allocator.
1167 
1168   if (op->code() == lir_move) {
1169     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1170     LIR_Op1* move = (LIR_Op1*)op;
1171 
1172     if (move->in_opr()->is_stack()) {
1173 #ifdef ASSERT
1174       int arg_size = compilation()->method()->arg_size();
1175       LIR_Opr o = move->in_opr();
1176       if (o->is_single_stack()) {
1177         assert(o->single_stack_ix() >= 0 && o->single_stack_ix() < arg_size, "out of range");
1178       } else if (o->is_double_stack()) {
1179         assert(o->double_stack_ix() >= 0 && o->double_stack_ix() < arg_size, "out of range");
1180       } else {
1181         ShouldNotReachHere();
1182       }
1183 
1184       assert(move->id() > 0, "invalid id");
1185       assert(block_of_op_with_id(move->id())->number_of_preds() == 0, "move from stack must be in first block");
1186       assert(move->result_opr()->is_virtual(), "result of move must be a virtual register");
1187 
1188       TRACE_LINEAR_SCAN(4, tty->print_cr("found move from stack slot %d to vreg %d", o->is_single_stack() ? o->single_stack_ix() : o->double_stack_ix(), reg_num(move->result_opr())));
1189 #endif
1190 
1191       Interval* interval = interval_at(reg_num(move->result_opr()));
1192 
1193       int stack_slot = LinearScan::nof_regs + (move->in_opr()->is_single_stack() ? move->in_opr()->single_stack_ix() : move->in_opr()->double_stack_ix());
1194       interval->set_canonical_spill_slot(stack_slot);
1195       interval->assign_reg(stack_slot);
1196     }
1197   }
1198 }
1199 
1200 void LinearScan::handle_doubleword_moves(LIR_Op* op) {
1201   // special handling for doubleword move from memory to register:
1202   // in this case the registers of the input address and the result
1203   // registers must not overlap -> add a temp range for the input registers
1204   if (op->code() == lir_move) {
1205     assert(op->as_Op1() != NULL, "must be LIR_Op1");
1206     LIR_Op1* move = (LIR_Op1*)op;
1207 
1208     if (move->result_opr()->is_double_cpu() && move->in_opr()->is_pointer()) {
1209       LIR_Address* address = move->in_opr()->as_address_ptr();
1210       if (address != NULL) {
1211         if (address->base()->is_valid()) {
1212           add_temp(address->base(), op->id(), noUse);
1213         }
1214         if (address->index()->is_valid()) {
1215           add_temp(address->index(), op->id(), noUse);
1216         }
1217       }
1218     }
1219   }
1220 }
1221 
1222 void LinearScan::add_register_hints(LIR_Op* op) {
1223   switch (op->code()) {
1224     case lir_move:      // fall through
1225     case lir_convert: {
1226       assert(op->as_Op1() != NULL, "lir_move, lir_convert must be LIR_Op1");
1227       LIR_Op1* move = (LIR_Op1*)op;
1228 
1229       LIR_Opr move_from = move->in_opr();
1230       LIR_Opr move_to = move->result_opr();
1231 
1232       if (move_to->is_register() && move_from->is_register()) {
1233         Interval* from = interval_at(reg_num(move_from));
1234         Interval* to = interval_at(reg_num(move_to));
1235         if (from != NULL && to != NULL) {
1236           to->set_register_hint(from);
1237           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", move->id(), from->reg_num(), to->reg_num()));
1238         }
1239       }
1240       break;
1241     }
1242     case lir_cmove: {
1243       assert(op->as_Op4() != NULL, "lir_cmove must be LIR_Op4");
1244       LIR_Op4* cmove = (LIR_Op4*)op;
1245 
1246       LIR_Opr move_from = cmove->in_opr1();
1247       LIR_Opr move_to   = cmove->result_opr();
1248 
1249       if (move_to->is_register() && move_from->is_register()) {
1250         Interval* from = interval_at(reg_num(move_from));
1251         Interval* to = interval_at(reg_num(move_to));
1252         if (from != NULL && to != NULL) {
1253           to->set_register_hint(from);
1254           TRACE_LINEAR_SCAN(4, tty->print_cr("operation at op_id %d: added hint from interval %d to %d", cmove->id(), from->reg_num(), to->reg_num()));
1255         }
1256       }
1257       break;
1258     }
1259     default:
1260       break;
1261   }
1262 }
1263 
1264 
1265 void LinearScan::build_intervals() {
1266   TIME_LINEAR_SCAN(timer_build_intervals);
1267 
1268   // initialize interval list with expected number of intervals
1269   // (32 is added to have some space for split children without having to resize the list)
1270   _intervals = IntervalList(num_virtual_regs() + 32);
1271   // initialize all slots that are used by build_intervals
1272   _intervals.at_put_grow(num_virtual_regs() - 1, NULL, NULL);
1273 
1274   // create a list with all caller-save registers (cpu, fpu, xmm)
1275   // when an instruction is a call, a temp range is created for all these registers
1276   int num_caller_save_registers = 0;
1277   int caller_save_registers[LinearScan::nof_regs];
1278 
1279   int i;
1280   for (i = 0; i < FrameMap::nof_caller_save_cpu_regs(); i++) {
1281     LIR_Opr opr = FrameMap::caller_save_cpu_reg_at(i);
1282     assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1283     assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1284     caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1285   }
1286 
1287   // temp ranges for fpu registers are only created when the method has
1288   // virtual fpu operands. Otherwise no allocation for fpu registers is
1289   // performed and so the temp ranges would be useless
1290   if (has_fpu_registers()) {
1291 #ifdef X86
1292     if (UseSSE < 2) {
1293 #endif // X86
1294       for (i = 0; i < FrameMap::nof_caller_save_fpu_regs; i++) {
1295         LIR_Opr opr = FrameMap::caller_save_fpu_reg_at(i);
1296         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1297         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1298         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1299       }
1300 #ifdef X86
1301     }
1302 #endif // X86
1303 
1304 #ifdef X86
1305     if (UseSSE > 0) {
1306       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
1307       for (i = 0; i < num_caller_save_xmm_regs; i ++) {
1308         LIR_Opr opr = FrameMap::caller_save_xmm_reg_at(i);
1309         assert(opr->is_valid() && opr->is_register(), "FrameMap should not return invalid operands");
1310         assert(reg_numHi(opr) == -1, "missing addition of range for hi-register");
1311         caller_save_registers[num_caller_save_registers++] = reg_num(opr);
1312       }
1313     }
1314 #endif // X86
1315   }
1316   assert(num_caller_save_registers <= LinearScan::nof_regs, "out of bounds");
1317 
1318 
1319   LIR_OpVisitState visitor;
1320 
1321   // iterate all blocks in reverse order
1322   for (i = block_count() - 1; i >= 0; i--) {
1323     BlockBegin* block = block_at(i);
1324     LIR_OpList* instructions = block->lir()->instructions_list();
1325     int         block_from =   block->first_lir_instruction_id();
1326     int         block_to =     block->last_lir_instruction_id();
1327 
1328     assert(block_from == instructions->at(0)->id(), "must be");
1329     assert(block_to   == instructions->at(instructions->length() - 1)->id(), "must be");
1330 
1331     // Update intervals for registers live at the end of this block;
1332     ResourceBitMap live = block->live_out();
1333     int size = (int)live.size();
1334     for (int number = (int)live.get_next_one_offset(0, size); number < size; number = (int)live.get_next_one_offset(number + 1, size)) {
1335       assert(live.at(number), "should not stop here otherwise");
1336       assert(number >= LIR_Opr::vreg_base, "fixed intervals must not be live on block bounds");
1337       TRACE_LINEAR_SCAN(2, tty->print_cr("live in %d to %d", number, block_to + 2));
1338 
1339       add_use(number, block_from, block_to + 2, noUse, T_ILLEGAL);
1340 
1341       // add special use positions for loop-end blocks when the
1342       // interval is used anywhere inside this loop.  It's possible
1343       // that the block was part of a non-natural loop, so it might
1344       // have an invalid loop index.
1345       if (block->is_set(BlockBegin::linear_scan_loop_end_flag) &&
1346           block->loop_index() != -1 &&
1347           is_interval_in_loop(number, block->loop_index())) {
1348         interval_at(number)->add_use_pos(block_to + 1, loopEndMarker);
1349       }
1350     }
1351 
1352     // iterate all instructions of the block in reverse order.
1353     // skip the first instruction because it is always a label
1354     // definitions of intervals are processed before uses
1355     assert(visitor.no_operands(instructions->at(0)), "first operation must always be a label");
1356     for (int j = instructions->length() - 1; j >= 1; j--) {
1357       LIR_Op* op = instructions->at(j);
1358       int op_id = op->id();
1359 
1360       // visit operation to collect all operands
1361       visitor.visit(op);
1362 
1363       // add a temp range for each register if operation destroys caller-save registers
1364       if (visitor.has_call()) {
1365         for (int k = 0; k < num_caller_save_registers; k++) {
1366           add_temp(caller_save_registers[k], op_id, noUse, T_ILLEGAL);
1367         }
1368         TRACE_LINEAR_SCAN(4, tty->print_cr("operation destroys all caller-save registers"));
1369       }
1370 
1371       // Add any platform dependent temps
1372       pd_add_temps(op);
1373 
1374       // visit definitions (output and temp operands)
1375       int k, n;
1376       n = visitor.opr_count(LIR_OpVisitState::outputMode);
1377       for (k = 0; k < n; k++) {
1378         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, k);
1379         assert(opr->is_register(), "visitor should only return register operands");
1380         add_def(opr, op_id, use_kind_of_output_operand(op, opr));
1381       }
1382 
1383       n = visitor.opr_count(LIR_OpVisitState::tempMode);
1384       for (k = 0; k < n; k++) {
1385         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, k);
1386         assert(opr->is_register(), "visitor should only return register operands");
1387         add_temp(opr, op_id, mustHaveRegister);
1388       }
1389 
1390       // visit uses (input operands)
1391       n = visitor.opr_count(LIR_OpVisitState::inputMode);
1392       for (k = 0; k < n; k++) {
1393         LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, k);
1394         assert(opr->is_register(), "visitor should only return register operands");
1395         add_use(opr, block_from, op_id, use_kind_of_input_operand(op, opr));
1396       }
1397 
1398       // Add uses of live locals from interpreter's point of view for proper
1399       // debug information generation
1400       // Treat these operands as temp values (if the life range is extended
1401       // to a call site, the value would be in a register at the call otherwise)
1402       n = visitor.info_count();
1403       for (k = 0; k < n; k++) {
1404         CodeEmitInfo* info = visitor.info_at(k);
1405         ValueStack* stack = info->stack();
1406         for_each_state_value(stack, value,
1407           add_use(value, block_from, op_id + 1, noUse);
1408         );
1409       }
1410 
1411       // special steps for some instructions (especially moves)
1412       handle_method_arguments(op);
1413       handle_doubleword_moves(op);
1414       add_register_hints(op);
1415 
1416     } // end of instruction iteration
1417   } // end of block iteration
1418 
1419 
1420   // add the range [0, 1[ to all fixed intervals
1421   // -> the register allocator need not handle unhandled fixed intervals
1422   for (int n = 0; n < LinearScan::nof_regs; n++) {
1423     Interval* interval = interval_at(n);
1424     if (interval != NULL) {
1425       interval->add_range(0, 1);
1426     }
1427   }
1428 }
1429 
1430 
1431 // ********** Phase 5: actual register allocation
1432 
1433 int LinearScan::interval_cmp(Interval** a, Interval** b) {
1434   if (*a != NULL) {
1435     if (*b != NULL) {
1436       return (*a)->from() - (*b)->from();
1437     } else {
1438       return -1;
1439     }
1440   } else {
1441     if (*b != NULL) {
1442       return 1;
1443     } else {
1444       return 0;
1445     }
1446   }
1447 }
1448 
1449 #ifndef PRODUCT
1450 int interval_cmp(Interval* const& l, Interval* const& r) {
1451   return l->from() - r->from();
1452 }
1453 
1454 bool find_interval(Interval* interval, IntervalArray* intervals) {
1455   bool found;
1456   int idx = intervals->find_sorted<Interval*, interval_cmp>(interval, found);
1457 
1458   if (!found) {
1459     return false;
1460   }
1461 
1462   int from = interval->from();
1463 
1464   // The index we've found using binary search is pointing to an interval
1465   // that is defined in the same place as the interval we were looking for.
1466   // So now we have to look around that index and find exact interval.
1467   for (int i = idx; i >= 0; i--) {
1468     if (intervals->at(i) == interval) {
1469       return true;
1470     }
1471     if (intervals->at(i)->from() != from) {
1472       break;
1473     }
1474   }
1475 
1476   for (int i = idx + 1; i < intervals->length(); i++) {
1477     if (intervals->at(i) == interval) {
1478       return true;
1479     }
1480     if (intervals->at(i)->from() != from) {
1481       break;
1482     }
1483   }
1484 
1485   return false;
1486 }
1487 
1488 bool LinearScan::is_sorted(IntervalArray* intervals) {
1489   int from = -1;
1490   int null_count = 0;
1491 
1492   for (int i = 0; i < intervals->length(); i++) {
1493     Interval* it = intervals->at(i);
1494     if (it != NULL) {
1495       assert(from <= it->from(), "Intervals are unordered");
1496       from = it->from();
1497     } else {
1498       null_count++;
1499     }
1500   }
1501 
1502   assert(null_count == 0, "Sorted intervals should not contain nulls");
1503 
1504   null_count = 0;
1505 
1506   for (int i = 0; i < interval_count(); i++) {
1507     Interval* interval = interval_at(i);
1508     if (interval != NULL) {
1509       assert(find_interval(interval, intervals), "Lists do not contain same intervals");
1510     } else {
1511       null_count++;
1512     }
1513   }
1514 
1515   assert(interval_count() - null_count == intervals->length(),
1516       "Sorted list should contain the same amount of non-NULL intervals as unsorted list");
1517 
1518   return true;
1519 }
1520 #endif
1521 
1522 void LinearScan::add_to_list(Interval** first, Interval** prev, Interval* interval) {
1523   if (*prev != NULL) {
1524     (*prev)->set_next(interval);
1525   } else {
1526     *first = interval;
1527   }
1528   *prev = interval;
1529 }
1530 
1531 void LinearScan::create_unhandled_lists(Interval** list1, Interval** list2, bool (is_list1)(const Interval* i), bool (is_list2)(const Interval* i)) {
1532   assert(is_sorted(_sorted_intervals), "interval list is not sorted");
1533 
1534   *list1 = *list2 = Interval::end();
1535 
1536   Interval* list1_prev = NULL;
1537   Interval* list2_prev = NULL;
1538   Interval* v;
1539 
1540   const int n = _sorted_intervals->length();
1541   for (int i = 0; i < n; i++) {
1542     v = _sorted_intervals->at(i);
1543     if (v == NULL) continue;
1544 
1545     if (is_list1(v)) {
1546       add_to_list(list1, &list1_prev, v);
1547     } else if (is_list2 == NULL || is_list2(v)) {
1548       add_to_list(list2, &list2_prev, v);
1549     }
1550   }
1551 
1552   if (list1_prev != NULL) list1_prev->set_next(Interval::end());
1553   if (list2_prev != NULL) list2_prev->set_next(Interval::end());
1554 
1555   assert(list1_prev == NULL || list1_prev->next() == Interval::end(), "linear list ends not with sentinel");
1556   assert(list2_prev == NULL || list2_prev->next() == Interval::end(), "linear list ends not with sentinel");
1557 }
1558 
1559 
1560 void LinearScan::sort_intervals_before_allocation() {
1561   TIME_LINEAR_SCAN(timer_sort_intervals_before);
1562 
1563   if (_needs_full_resort) {
1564     // There is no known reason why this should occur but just in case...
1565     assert(false, "should never occur");
1566     // Re-sort existing interval list because an Interval::from() has changed
1567     _sorted_intervals->sort(interval_cmp);
1568     _needs_full_resort = false;
1569   }
1570 
1571   IntervalList* unsorted_list = &_intervals;
1572   int unsorted_len = unsorted_list->length();
1573   int sorted_len = 0;
1574   int unsorted_idx;
1575   int sorted_idx = 0;
1576   int sorted_from_max = -1;
1577 
1578   // calc number of items for sorted list (sorted list must not contain NULL values)
1579   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1580     if (unsorted_list->at(unsorted_idx) != NULL) {
1581       sorted_len++;
1582     }
1583   }
1584   IntervalArray* sorted_list = new IntervalArray(sorted_len, sorted_len, NULL);
1585 
1586   // special sorting algorithm: the original interval-list is almost sorted,
1587   // only some intervals are swapped. So this is much faster than a complete QuickSort
1588   for (unsorted_idx = 0; unsorted_idx < unsorted_len; unsorted_idx++) {
1589     Interval* cur_interval = unsorted_list->at(unsorted_idx);
1590 
1591     if (cur_interval != NULL) {
1592       int cur_from = cur_interval->from();
1593 
1594       if (sorted_from_max <= cur_from) {
1595         sorted_list->at_put(sorted_idx++, cur_interval);
1596         sorted_from_max = cur_interval->from();
1597       } else {
1598         // the assumption that the intervals are already sorted failed,
1599         // so this interval must be sorted in manually
1600         int j;
1601         for (j = sorted_idx - 1; j >= 0 && cur_from < sorted_list->at(j)->from(); j--) {
1602           sorted_list->at_put(j + 1, sorted_list->at(j));
1603         }
1604         sorted_list->at_put(j + 1, cur_interval);
1605         sorted_idx++;
1606       }
1607     }
1608   }
1609   _sorted_intervals = sorted_list;
1610   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1611 }
1612 
1613 void LinearScan::sort_intervals_after_allocation() {
1614   TIME_LINEAR_SCAN(timer_sort_intervals_after);
1615 
1616   if (_needs_full_resort) {
1617     // Re-sort existing interval list because an Interval::from() has changed
1618     _sorted_intervals->sort(interval_cmp);
1619     _needs_full_resort = false;
1620   }
1621 
1622   IntervalArray* old_list = _sorted_intervals;
1623   IntervalList* new_list = _new_intervals_from_allocation;
1624   int old_len = old_list->length();
1625   int new_len = new_list == NULL ? 0 : new_list->length();
1626 
1627   if (new_len == 0) {
1628     // no intervals have been added during allocation, so sorted list is already up to date
1629     assert(is_sorted(_sorted_intervals), "intervals unsorted");
1630     return;
1631   }
1632 
1633   // conventional sort-algorithm for new intervals
1634   new_list->sort(interval_cmp);
1635 
1636   // merge old and new list (both already sorted) into one combined list
1637   int combined_list_len = old_len + new_len;
1638   IntervalArray* combined_list = new IntervalArray(combined_list_len, combined_list_len, NULL);
1639   int old_idx = 0;
1640   int new_idx = 0;
1641 
1642   while (old_idx + new_idx < old_len + new_len) {
1643     if (new_idx >= new_len || (old_idx < old_len && old_list->at(old_idx)->from() <= new_list->at(new_idx)->from())) {
1644       combined_list->at_put(old_idx + new_idx, old_list->at(old_idx));
1645       old_idx++;
1646     } else {
1647       combined_list->at_put(old_idx + new_idx, new_list->at(new_idx));
1648       new_idx++;
1649     }
1650   }
1651 
1652   _sorted_intervals = combined_list;
1653   assert(is_sorted(_sorted_intervals), "intervals unsorted");
1654 }
1655 
1656 
1657 void LinearScan::allocate_registers() {
1658   TIME_LINEAR_SCAN(timer_allocate_registers);
1659 
1660   Interval* precolored_cpu_intervals, *not_precolored_cpu_intervals;
1661   Interval* precolored_fpu_intervals, *not_precolored_fpu_intervals;
1662 
1663   // collect cpu intervals
1664   create_unhandled_lists(&precolored_cpu_intervals, &not_precolored_cpu_intervals,
1665                          is_precolored_cpu_interval, is_virtual_cpu_interval);
1666 
1667   // collect fpu intervals
1668   create_unhandled_lists(&precolored_fpu_intervals, &not_precolored_fpu_intervals,
1669                          is_precolored_fpu_interval, is_virtual_fpu_interval);
1670   // this fpu interval collection cannot be moved down below with the allocation section as
1671   // the cpu_lsw.walk() changes interval positions.
1672 
1673   if (!has_fpu_registers()) {
1674 #ifdef ASSERT
1675     assert(not_precolored_fpu_intervals == Interval::end(), "missed an uncolored fpu interval");
1676 #else
1677     if (not_precolored_fpu_intervals != Interval::end()) {
1678       BAILOUT("missed an uncolored fpu interval");
1679     }
1680 #endif
1681   }
1682 
1683   // allocate cpu registers
1684   LinearScanWalker cpu_lsw(this, precolored_cpu_intervals, not_precolored_cpu_intervals);
1685   cpu_lsw.walk();
1686   cpu_lsw.finish_allocation();
1687 
1688   if (has_fpu_registers()) {
1689     // allocate fpu registers
1690     LinearScanWalker fpu_lsw(this, precolored_fpu_intervals, not_precolored_fpu_intervals);
1691     fpu_lsw.walk();
1692     fpu_lsw.finish_allocation();
1693   }
1694 }
1695 
1696 
1697 // ********** Phase 6: resolve data flow
1698 // (insert moves at edges between blocks if intervals have been split)
1699 
1700 // wrapper for Interval::split_child_at_op_id that performs a bailout in product mode
1701 // instead of returning NULL
1702 Interval* LinearScan::split_child_at_op_id(Interval* interval, int op_id, LIR_OpVisitState::OprMode mode) {
1703   Interval* result = interval->split_child_at_op_id(op_id, mode);
1704   if (result != NULL) {
1705     return result;
1706   }
1707 
1708   assert(false, "must find an interval, but do a clean bailout in product mode");
1709   result = new Interval(LIR_Opr::vreg_base);
1710   result->assign_reg(0);
1711   result->set_type(T_INT);
1712   BAILOUT_("LinearScan: interval is NULL", result);
1713 }
1714 
1715 
1716 Interval* LinearScan::interval_at_block_begin(BlockBegin* block, int reg_num) {
1717   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1718   assert(interval_at(reg_num) != NULL, "no interval found");
1719 
1720   return split_child_at_op_id(interval_at(reg_num), block->first_lir_instruction_id(), LIR_OpVisitState::outputMode);
1721 }
1722 
1723 Interval* LinearScan::interval_at_block_end(BlockBegin* block, int reg_num) {
1724   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1725   assert(interval_at(reg_num) != NULL, "no interval found");
1726 
1727   return split_child_at_op_id(interval_at(reg_num), block->last_lir_instruction_id() + 1, LIR_OpVisitState::outputMode);
1728 }
1729 
1730 Interval* LinearScan::interval_at_op_id(int reg_num, int op_id) {
1731   assert(LinearScan::nof_regs <= reg_num && reg_num < num_virtual_regs(), "register number out of bounds");
1732   assert(interval_at(reg_num) != NULL, "no interval found");
1733 
1734   return split_child_at_op_id(interval_at(reg_num), op_id, LIR_OpVisitState::inputMode);
1735 }
1736 
1737 
1738 void LinearScan::resolve_collect_mappings(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1739   DEBUG_ONLY(move_resolver.check_empty());
1740 
1741   const int size = live_set_size();
1742   const ResourceBitMap live_at_edge = to_block->live_in();
1743 
1744   // visit all registers where the live_at_edge bit is set
1745   for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
1746     assert(r < num_virtual_regs(), "live information set for not existing interval");
1747     assert(from_block->live_out().at(r) && to_block->live_in().at(r), "interval not live at this edge");
1748 
1749     Interval* from_interval = interval_at_block_end(from_block, r);
1750     Interval* to_interval = interval_at_block_begin(to_block, r);
1751 
1752     if (from_interval != to_interval && (from_interval->assigned_reg() != to_interval->assigned_reg() || from_interval->assigned_regHi() != to_interval->assigned_regHi())) {
1753       // need to insert move instruction
1754       move_resolver.add_mapping(from_interval, to_interval);
1755     }
1756   }
1757 }
1758 
1759 
1760 void LinearScan::resolve_find_insert_pos(BlockBegin* from_block, BlockBegin* to_block, MoveResolver &move_resolver) {
1761   if (from_block->number_of_sux() <= 1) {
1762     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at end of from_block B%d", from_block->block_id()));
1763 
1764     LIR_OpList* instructions = from_block->lir()->instructions_list();
1765     LIR_OpBranch* branch = instructions->last()->as_OpBranch();
1766     if (branch != NULL) {
1767       // insert moves before branch
1768       assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
1769       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 2);
1770     } else {
1771       move_resolver.set_insert_position(from_block->lir(), instructions->length() - 1);
1772     }
1773 
1774   } else {
1775     TRACE_LINEAR_SCAN(4, tty->print_cr("inserting moves at beginning of to_block B%d", to_block->block_id()));
1776 #ifdef ASSERT
1777     assert(from_block->lir()->instructions_list()->at(0)->as_OpLabel() != NULL, "block does not start with a label");
1778 
1779     // because the number of predecessor edges matches the number of
1780     // successor edges, blocks which are reached by switch statements
1781     // may have be more than one predecessor but it will be guaranteed
1782     // that all predecessors will be the same.
1783     for (int i = 0; i < to_block->number_of_preds(); i++) {
1784       assert(from_block == to_block->pred_at(i), "all critical edges must be broken");
1785     }
1786 #endif
1787 
1788     move_resolver.set_insert_position(to_block->lir(), 0);
1789   }
1790 }
1791 
1792 
1793 // insert necessary moves (spilling or reloading) at edges between blocks if interval has been split
1794 void LinearScan::resolve_data_flow() {
1795   TIME_LINEAR_SCAN(timer_resolve_data_flow);
1796 
1797   int num_blocks = block_count();
1798   MoveResolver move_resolver(this);
1799   ResourceBitMap block_completed(num_blocks);
1800   ResourceBitMap already_resolved(num_blocks);
1801 
1802   int i;
1803   for (i = 0; i < num_blocks; i++) {
1804     BlockBegin* block = block_at(i);
1805 
1806     // check if block has only one predecessor and only one successor
1807     if (block->number_of_preds() == 1 && block->number_of_sux() == 1 && block->number_of_exception_handlers() == 0) {
1808       LIR_OpList* instructions = block->lir()->instructions_list();
1809       assert(instructions->at(0)->code() == lir_label, "block must start with label");
1810       assert(instructions->last()->code() == lir_branch, "block with successors must end with branch");
1811       assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block with successor must end with unconditional branch");
1812 
1813       // check if block is empty (only label and branch)
1814       if (instructions->length() == 2) {
1815         BlockBegin* pred = block->pred_at(0);
1816         BlockBegin* sux = block->sux_at(0);
1817 
1818         // prevent optimization of two consecutive blocks
1819         if (!block_completed.at(pred->linear_scan_number()) && !block_completed.at(sux->linear_scan_number())) {
1820           TRACE_LINEAR_SCAN(3, tty->print_cr("**** optimizing empty block B%d (pred: B%d, sux: B%d)", block->block_id(), pred->block_id(), sux->block_id()));
1821           block_completed.set_bit(block->linear_scan_number());
1822 
1823           // directly resolve between pred and sux (without looking at the empty block between)
1824           resolve_collect_mappings(pred, sux, move_resolver);
1825           if (move_resolver.has_mappings()) {
1826             move_resolver.set_insert_position(block->lir(), 0);
1827             move_resolver.resolve_and_append_moves();
1828           }
1829         }
1830       }
1831     }
1832   }
1833 
1834 
1835   for (i = 0; i < num_blocks; i++) {
1836     if (!block_completed.at(i)) {
1837       BlockBegin* from_block = block_at(i);
1838       already_resolved.set_from(block_completed);
1839 
1840       int num_sux = from_block->number_of_sux();
1841       for (int s = 0; s < num_sux; s++) {
1842         BlockBegin* to_block = from_block->sux_at(s);
1843 
1844         // check for duplicate edges between the same blocks (can happen with switch blocks)
1845         if (!already_resolved.at(to_block->linear_scan_number())) {
1846           TRACE_LINEAR_SCAN(3, tty->print_cr("**** processing edge between B%d and B%d", from_block->block_id(), to_block->block_id()));
1847           already_resolved.set_bit(to_block->linear_scan_number());
1848 
1849           // collect all intervals that have been split between from_block and to_block
1850           resolve_collect_mappings(from_block, to_block, move_resolver);
1851           if (move_resolver.has_mappings()) {
1852             resolve_find_insert_pos(from_block, to_block, move_resolver);
1853             move_resolver.resolve_and_append_moves();
1854           }
1855         }
1856       }
1857     }
1858   }
1859 }
1860 
1861 
1862 void LinearScan::resolve_exception_entry(BlockBegin* block, int reg_num, MoveResolver &move_resolver) {
1863   if (interval_at(reg_num) == NULL) {
1864     // if a phi function is never used, no interval is created -> ignore this
1865     return;
1866   }
1867 
1868   Interval* interval = interval_at_block_begin(block, reg_num);
1869   int reg = interval->assigned_reg();
1870   int regHi = interval->assigned_regHi();
1871 
1872   if ((reg < nof_regs && interval->always_in_memory()) ||
1873       (use_fpu_stack_allocation() && reg >= pd_first_fpu_reg && reg <= pd_last_fpu_reg)) {
1874     // the interval is split to get a short range that is located on the stack
1875     // in the following two cases:
1876     // * the interval started in memory (e.g. method parameter), but is currently in a register
1877     //   this is an optimization for exception handling that reduces the number of moves that
1878     //   are necessary for resolving the states when an exception uses this exception handler
1879     // * the interval would be on the fpu stack at the begin of the exception handler
1880     //   this is not allowed because of the complicated fpu stack handling on Intel
1881 
1882     // range that will be spilled to memory
1883     int from_op_id = block->first_lir_instruction_id();
1884     int to_op_id = from_op_id + 1;  // short live range of length 1
1885     assert(interval->from() <= from_op_id && interval->to() >= to_op_id,
1886            "no split allowed between exception entry and first instruction");
1887 
1888     if (interval->from() != from_op_id) {
1889       // the part before from_op_id is unchanged
1890       interval = interval->split(from_op_id);
1891       interval->assign_reg(reg, regHi);
1892       append_interval(interval);
1893     } else {
1894       _needs_full_resort = true;
1895     }
1896     assert(interval->from() == from_op_id, "must be true now");
1897 
1898     Interval* spilled_part = interval;
1899     if (interval->to() != to_op_id) {
1900       // the part after to_op_id is unchanged
1901       spilled_part = interval->split_from_start(to_op_id);
1902       append_interval(spilled_part);
1903       move_resolver.add_mapping(spilled_part, interval);
1904     }
1905     assign_spill_slot(spilled_part);
1906 
1907     assert(spilled_part->from() == from_op_id && spilled_part->to() == to_op_id, "just checking");
1908   }
1909 }
1910 
1911 void LinearScan::resolve_exception_entry(BlockBegin* block, MoveResolver &move_resolver) {
1912   assert(block->is_set(BlockBegin::exception_entry_flag), "should not call otherwise");
1913   DEBUG_ONLY(move_resolver.check_empty());
1914 
1915   // visit all registers where the live_in bit is set
1916   int size = live_set_size();
1917   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1918     resolve_exception_entry(block, r, move_resolver);
1919   }
1920 
1921   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1922   for_each_phi_fun(block, phi,
1923     if (!phi->is_illegal()) { resolve_exception_entry(block, phi->operand()->vreg_number(), move_resolver); }
1924   );
1925 
1926   if (move_resolver.has_mappings()) {
1927     // insert moves after first instruction
1928     move_resolver.set_insert_position(block->lir(), 0);
1929     move_resolver.resolve_and_append_moves();
1930   }
1931 }
1932 
1933 
1934 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, int reg_num, Phi* phi, MoveResolver &move_resolver) {
1935   if (interval_at(reg_num) == NULL) {
1936     // if a phi function is never used, no interval is created -> ignore this
1937     return;
1938   }
1939 
1940   // the computation of to_interval is equal to resolve_collect_mappings,
1941   // but from_interval is more complicated because of phi functions
1942   BlockBegin* to_block = handler->entry_block();
1943   Interval* to_interval = interval_at_block_begin(to_block, reg_num);
1944 
1945   if (phi != NULL) {
1946     // phi function of the exception entry block
1947     // no moves are created for this phi function in the LIR_Generator, so the
1948     // interval at the throwing instruction must be searched using the operands
1949     // of the phi function
1950     Value from_value = phi->operand_at(handler->phi_operand());
1951 
1952     // with phi functions it can happen that the same from_value is used in
1953     // multiple mappings, so notify move-resolver that this is allowed
1954     move_resolver.set_multiple_reads_allowed();
1955 
1956     Constant* con = from_value->as_Constant();
1957     if (con != NULL && (!con->is_pinned() || con->operand()->is_constant())) {
1958       // Need a mapping from constant to interval if unpinned (may have no register) or if the operand is a constant (no register).
1959       move_resolver.add_mapping(LIR_OprFact::value_type(con->type()), to_interval);
1960     } else {
1961       // search split child at the throwing op_id
1962       Interval* from_interval = interval_at_op_id(from_value->operand()->vreg_number(), throwing_op_id);
1963       move_resolver.add_mapping(from_interval, to_interval);
1964     }
1965   } else {
1966     // no phi function, so use reg_num also for from_interval
1967     // search split child at the throwing op_id
1968     Interval* from_interval = interval_at_op_id(reg_num, throwing_op_id);
1969     if (from_interval != to_interval) {
1970       // optimization to reduce number of moves: when to_interval is on stack and
1971       // the stack slot is known to be always correct, then no move is necessary
1972       if (!from_interval->always_in_memory() || from_interval->canonical_spill_slot() != to_interval->assigned_reg()) {
1973         move_resolver.add_mapping(from_interval, to_interval);
1974       }
1975     }
1976   }
1977 }
1978 
1979 void LinearScan::resolve_exception_edge(XHandler* handler, int throwing_op_id, MoveResolver &move_resolver) {
1980   TRACE_LINEAR_SCAN(4, tty->print_cr("resolving exception handler B%d: throwing_op_id=%d", handler->entry_block()->block_id(), throwing_op_id));
1981 
1982   DEBUG_ONLY(move_resolver.check_empty());
1983   assert(handler->lir_op_id() == -1, "already processed this xhandler");
1984   DEBUG_ONLY(handler->set_lir_op_id(throwing_op_id));
1985   assert(handler->entry_code() == NULL, "code already present");
1986 
1987   // visit all registers where the live_in bit is set
1988   BlockBegin* block = handler->entry_block();
1989   int size = live_set_size();
1990   for (int r = (int)block->live_in().get_next_one_offset(0, size); r < size; r = (int)block->live_in().get_next_one_offset(r + 1, size)) {
1991     resolve_exception_edge(handler, throwing_op_id, r, NULL, move_resolver);
1992   }
1993 
1994   // the live_in bits are not set for phi functions of the xhandler entry, so iterate them separately
1995   for_each_phi_fun(block, phi,
1996     if (!phi->is_illegal()) { resolve_exception_edge(handler, throwing_op_id, phi->operand()->vreg_number(), phi, move_resolver); }
1997   );
1998 
1999   if (move_resolver.has_mappings()) {
2000     LIR_List* entry_code = new LIR_List(compilation());
2001     move_resolver.set_insert_position(entry_code, 0);
2002     move_resolver.resolve_and_append_moves();
2003 
2004     entry_code->jump(handler->entry_block());
2005     handler->set_entry_code(entry_code);
2006   }
2007 }
2008 
2009 
2010 void LinearScan::resolve_exception_handlers() {
2011   MoveResolver move_resolver(this);
2012   LIR_OpVisitState visitor;
2013   int num_blocks = block_count();
2014 
2015   int i;
2016   for (i = 0; i < num_blocks; i++) {
2017     BlockBegin* block = block_at(i);
2018     if (block->is_set(BlockBegin::exception_entry_flag)) {
2019       resolve_exception_entry(block, move_resolver);
2020     }
2021   }
2022 
2023   for (i = 0; i < num_blocks; i++) {
2024     BlockBegin* block = block_at(i);
2025     LIR_List* ops = block->lir();
2026     int num_ops = ops->length();
2027 
2028     // iterate all instructions of the block. skip the first because it is always a label
2029     assert(visitor.no_operands(ops->at(0)), "first operation must always be a label");
2030     for (int j = 1; j < num_ops; j++) {
2031       LIR_Op* op = ops->at(j);
2032       int op_id = op->id();
2033 
2034       if (op_id != -1 && has_info(op_id)) {
2035         // visit operation to collect all operands
2036         visitor.visit(op);
2037         assert(visitor.info_count() > 0, "should not visit otherwise");
2038 
2039         XHandlers* xhandlers = visitor.all_xhandler();
2040         int n = xhandlers->length();
2041         for (int k = 0; k < n; k++) {
2042           resolve_exception_edge(xhandlers->handler_at(k), op_id, move_resolver);
2043         }
2044 
2045 #ifdef ASSERT
2046       } else {
2047         visitor.visit(op);
2048         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
2049 #endif
2050       }
2051     }
2052   }
2053 }
2054 
2055 
2056 // ********** Phase 7: assign register numbers back to LIR
2057 // (includes computation of debug information and oop maps)
2058 
2059 VMReg LinearScan::vm_reg_for_interval(Interval* interval) {
2060   VMReg reg = interval->cached_vm_reg();
2061   if (!reg->is_valid() ) {
2062     reg = vm_reg_for_operand(operand_for_interval(interval));
2063     interval->set_cached_vm_reg(reg);
2064   }
2065   assert(reg == vm_reg_for_operand(operand_for_interval(interval)), "wrong cached value");
2066   return reg;
2067 }
2068 
2069 VMReg LinearScan::vm_reg_for_operand(LIR_Opr opr) {
2070   assert(opr->is_oop(), "currently only implemented for oop operands");
2071   return frame_map()->regname(opr);
2072 }
2073 
2074 
2075 LIR_Opr LinearScan::operand_for_interval(Interval* interval) {
2076   LIR_Opr opr = interval->cached_opr();
2077   if (opr->is_illegal()) {
2078     opr = calc_operand_for_interval(interval);
2079     interval->set_cached_opr(opr);
2080   }
2081 
2082   assert(opr == calc_operand_for_interval(interval), "wrong cached value");
2083   return opr;
2084 }
2085 
2086 LIR_Opr LinearScan::calc_operand_for_interval(const Interval* interval) {
2087   int assigned_reg = interval->assigned_reg();
2088   BasicType type = interval->type();
2089 
2090   if (assigned_reg >= nof_regs) {
2091     // stack slot
2092     assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2093     return LIR_OprFact::stack(assigned_reg - nof_regs, type);
2094 
2095   } else {
2096     // register
2097     switch (type) {
2098       case T_OBJECT: {
2099         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2100         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2101         return LIR_OprFact::single_cpu_oop(assigned_reg);
2102       }
2103 
2104       case T_ADDRESS: {
2105         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2106         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2107         return LIR_OprFact::single_cpu_address(assigned_reg);
2108       }
2109 
2110       case T_METADATA: {
2111         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2112         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2113         return LIR_OprFact::single_cpu_metadata(assigned_reg);
2114       }
2115 
2116 #ifdef __SOFTFP__
2117       case T_FLOAT:  // fall through
2118 #endif // __SOFTFP__
2119       case T_INT: {
2120         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2121         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2122         return LIR_OprFact::single_cpu(assigned_reg);
2123       }
2124 
2125 #ifdef __SOFTFP__
2126       case T_DOUBLE:  // fall through
2127 #endif // __SOFTFP__
2128       case T_LONG: {
2129         int assigned_regHi = interval->assigned_regHi();
2130         assert(assigned_reg >= pd_first_cpu_reg && assigned_reg <= pd_last_cpu_reg, "no cpu register");
2131         assert(num_physical_regs(T_LONG) == 1 ||
2132                (assigned_regHi >= pd_first_cpu_reg && assigned_regHi <= pd_last_cpu_reg), "no cpu register");
2133 
2134         assert(assigned_reg != assigned_regHi, "invalid allocation");
2135         assert(num_physical_regs(T_LONG) == 1 || assigned_reg < assigned_regHi,
2136                "register numbers must be sorted (ensure that e.g. a move from eax,ebx to ebx,eax can not occur)");
2137         assert((assigned_regHi != any_reg) ^ (num_physical_regs(T_LONG) == 1), "must be match");
2138         if (requires_adjacent_regs(T_LONG)) {
2139           assert(assigned_reg % 2 == 0 && assigned_reg + 1 == assigned_regHi, "must be sequential and even");
2140         }
2141 
2142 #ifdef _LP64
2143         return LIR_OprFact::double_cpu(assigned_reg, assigned_reg);
2144 #else
2145         return LIR_OprFact::double_cpu(assigned_reg, assigned_regHi);
2146 #endif // LP64
2147       }
2148 
2149 #ifndef __SOFTFP__
2150       case T_FLOAT: {
2151 #ifdef X86
2152         if (UseSSE >= 1) {
2153           int last_xmm_reg = pd_last_xmm_reg;
2154 #ifdef _LP64
2155           if (UseAVX < 3) {
2156             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2157           }
2158 #endif // LP64
2159           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2160           assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2161           return LIR_OprFact::single_xmm(assigned_reg - pd_first_xmm_reg);
2162         }
2163 #endif // X86
2164 
2165         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2166         assert(interval->assigned_regHi() == any_reg, "must not have hi register");
2167         return LIR_OprFact::single_fpu(assigned_reg - pd_first_fpu_reg);
2168       }
2169 
2170       case T_DOUBLE: {
2171 #ifdef X86
2172         if (UseSSE >= 2) {
2173           int last_xmm_reg = pd_last_xmm_reg;
2174 #ifdef _LP64
2175           if (UseAVX < 3) {
2176             last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
2177           }
2178 #endif // LP64
2179           assert(assigned_reg >= pd_first_xmm_reg && assigned_reg <= last_xmm_reg, "no xmm register");
2180           assert(interval->assigned_regHi() == any_reg, "must not have hi register (double xmm values are stored in one register)");
2181           return LIR_OprFact::double_xmm(assigned_reg - pd_first_xmm_reg);
2182         }
2183 #endif // X86
2184 
2185 #if defined(ARM32)
2186         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2187         assert(interval->assigned_regHi() >= pd_first_fpu_reg && interval->assigned_regHi() <= pd_last_fpu_reg, "no fpu register");
2188         assert(assigned_reg % 2 == 0 && assigned_reg + 1 == interval->assigned_regHi(), "must be sequential and even");
2189         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg, interval->assigned_regHi() - pd_first_fpu_reg);
2190 #else
2191         assert(assigned_reg >= pd_first_fpu_reg && assigned_reg <= pd_last_fpu_reg, "no fpu register");
2192         assert(interval->assigned_regHi() == any_reg, "must not have hi register (double fpu values are stored in one register on Intel)");
2193         LIR_Opr result = LIR_OprFact::double_fpu(assigned_reg - pd_first_fpu_reg);
2194 #endif
2195         return result;
2196       }
2197 #endif // __SOFTFP__
2198 
2199       default: {
2200         ShouldNotReachHere();
2201         return LIR_OprFact::illegalOpr;
2202       }
2203     }
2204   }
2205 }
2206 
2207 LIR_Opr LinearScan::canonical_spill_opr(Interval* interval) {
2208   assert(interval->canonical_spill_slot() >= nof_regs, "canonical spill slot not set");
2209   return LIR_OprFact::stack(interval->canonical_spill_slot() - nof_regs, interval->type());
2210 }
2211 
2212 LIR_Opr LinearScan::color_lir_opr(LIR_Opr opr, int op_id, LIR_OpVisitState::OprMode mode) {
2213   assert(opr->is_virtual(), "should not call this otherwise");
2214 
2215   Interval* interval = interval_at(opr->vreg_number());
2216   assert(interval != NULL, "interval must exist");
2217 
2218   if (op_id != -1) {
2219 #ifdef ASSERT
2220     BlockBegin* block = block_of_op_with_id(op_id);
2221     if (block->number_of_sux() <= 1 && op_id == block->last_lir_instruction_id()) {
2222       // check if spill moves could have been appended at the end of this block, but
2223       // before the branch instruction. So the split child information for this branch would
2224       // be incorrect.
2225       LIR_OpBranch* branch = block->lir()->instructions_list()->last()->as_OpBranch();
2226       if (branch != NULL) {
2227         if (block->live_out().at(opr->vreg_number())) {
2228           assert(branch->cond() == lir_cond_always, "block does not end with an unconditional jump");
2229           assert(false, "can't get split child for the last branch of a block because the information would be incorrect (moves are inserted before the branch in resolve_data_flow)");
2230         }
2231       }
2232     }
2233 #endif
2234 
2235     // operands are not changed when an interval is split during allocation,
2236     // so search the right interval here
2237     interval = split_child_at_op_id(interval, op_id, mode);
2238   }
2239 
2240   LIR_Opr res = operand_for_interval(interval);
2241 
2242 #ifdef X86
2243   // new semantic for is_last_use: not only set on definite end of interval,
2244   // but also before hole
2245   // This may still miss some cases (e.g. for dead values), but it is not necessary that the
2246   // last use information is completely correct
2247   // information is only needed for fpu stack allocation
2248   if (res->is_fpu_register()) {
2249     if (opr->is_last_use() || op_id == interval->to() || (op_id != -1 && interval->has_hole_between(op_id, op_id + 1))) {
2250       assert(op_id == -1 || !is_block_begin(op_id), "holes at begin of block may also result from control flow");
2251       res = res->make_last_use();
2252     }
2253   }
2254 #endif
2255 
2256   assert(!gen()->is_vreg_flag_set(opr->vreg_number(), LIRGenerator::callee_saved) || !FrameMap::is_caller_save_register(res), "bad allocation");
2257 
2258   return res;
2259 }
2260 
2261 
2262 #ifdef ASSERT
2263 // some methods used to check correctness of debug information
2264 
2265 void assert_no_register_values(GrowableArray<ScopeValue*>* values) {
2266   if (values == NULL) {
2267     return;
2268   }
2269 
2270   for (int i = 0; i < values->length(); i++) {
2271     ScopeValue* value = values->at(i);
2272 
2273     if (value->is_location()) {
2274       Location location = ((LocationValue*)value)->location();
2275       assert(location.where() == Location::on_stack, "value is in register");
2276     }
2277   }
2278 }
2279 
2280 void assert_no_register_values(GrowableArray<MonitorValue*>* values) {
2281   if (values == NULL) {
2282     return;
2283   }
2284 
2285   for (int i = 0; i < values->length(); i++) {
2286     MonitorValue* value = values->at(i);
2287 
2288     if (value->owner()->is_location()) {
2289       Location location = ((LocationValue*)value->owner())->location();
2290       assert(location.where() == Location::on_stack, "owner is in register");
2291     }
2292     assert(value->basic_lock().where() == Location::on_stack, "basic_lock is in register");
2293   }
2294 }
2295 
2296 void assert_equal(Location l1, Location l2) {
2297   assert(l1.where() == l2.where() && l1.type() == l2.type() && l1.offset() == l2.offset(), "");
2298 }
2299 
2300 void assert_equal(ScopeValue* v1, ScopeValue* v2) {
2301   if (v1->is_location()) {
2302     assert(v2->is_location(), "");
2303     assert_equal(((LocationValue*)v1)->location(), ((LocationValue*)v2)->location());
2304   } else if (v1->is_constant_int()) {
2305     assert(v2->is_constant_int(), "");
2306     assert(((ConstantIntValue*)v1)->value() == ((ConstantIntValue*)v2)->value(), "");
2307   } else if (v1->is_constant_double()) {
2308     assert(v2->is_constant_double(), "");
2309     assert(((ConstantDoubleValue*)v1)->value() == ((ConstantDoubleValue*)v2)->value(), "");
2310   } else if (v1->is_constant_long()) {
2311     assert(v2->is_constant_long(), "");
2312     assert(((ConstantLongValue*)v1)->value() == ((ConstantLongValue*)v2)->value(), "");
2313   } else if (v1->is_constant_oop()) {
2314     assert(v2->is_constant_oop(), "");
2315     assert(((ConstantOopWriteValue*)v1)->value() == ((ConstantOopWriteValue*)v2)->value(), "");
2316   } else {
2317     ShouldNotReachHere();
2318   }
2319 }
2320 
2321 void assert_equal(MonitorValue* m1, MonitorValue* m2) {
2322   assert_equal(m1->owner(), m2->owner());
2323   assert_equal(m1->basic_lock(), m2->basic_lock());
2324 }
2325 
2326 void assert_equal(IRScopeDebugInfo* d1, IRScopeDebugInfo* d2) {
2327   assert(d1->scope() == d2->scope(), "not equal");
2328   assert(d1->bci() == d2->bci(), "not equal");
2329 
2330   if (d1->locals() != NULL) {
2331     assert(d1->locals() != NULL && d2->locals() != NULL, "not equal");
2332     assert(d1->locals()->length() == d2->locals()->length(), "not equal");
2333     for (int i = 0; i < d1->locals()->length(); i++) {
2334       assert_equal(d1->locals()->at(i), d2->locals()->at(i));
2335     }
2336   } else {
2337     assert(d1->locals() == NULL && d2->locals() == NULL, "not equal");
2338   }
2339 
2340   if (d1->expressions() != NULL) {
2341     assert(d1->expressions() != NULL && d2->expressions() != NULL, "not equal");
2342     assert(d1->expressions()->length() == d2->expressions()->length(), "not equal");
2343     for (int i = 0; i < d1->expressions()->length(); i++) {
2344       assert_equal(d1->expressions()->at(i), d2->expressions()->at(i));
2345     }
2346   } else {
2347     assert(d1->expressions() == NULL && d2->expressions() == NULL, "not equal");
2348   }
2349 
2350   if (d1->monitors() != NULL) {
2351     assert(d1->monitors() != NULL && d2->monitors() != NULL, "not equal");
2352     assert(d1->monitors()->length() == d2->monitors()->length(), "not equal");
2353     for (int i = 0; i < d1->monitors()->length(); i++) {
2354       assert_equal(d1->monitors()->at(i), d2->monitors()->at(i));
2355     }
2356   } else {
2357     assert(d1->monitors() == NULL && d2->monitors() == NULL, "not equal");
2358   }
2359 
2360   if (d1->caller() != NULL) {
2361     assert(d1->caller() != NULL && d2->caller() != NULL, "not equal");
2362     assert_equal(d1->caller(), d2->caller());
2363   } else {
2364     assert(d1->caller() == NULL && d2->caller() == NULL, "not equal");
2365   }
2366 }
2367 
2368 void check_stack_depth(CodeEmitInfo* info, int stack_end) {
2369   if (info->stack()->bci() != SynchronizationEntryBCI && !info->scope()->method()->is_native()) {
2370     Bytecodes::Code code = info->scope()->method()->java_code_at_bci(info->stack()->bci());
2371     switch (code) {
2372       case Bytecodes::_ifnull    : // fall through
2373       case Bytecodes::_ifnonnull : // fall through
2374       case Bytecodes::_ifeq      : // fall through
2375       case Bytecodes::_ifne      : // fall through
2376       case Bytecodes::_iflt      : // fall through
2377       case Bytecodes::_ifge      : // fall through
2378       case Bytecodes::_ifgt      : // fall through
2379       case Bytecodes::_ifle      : // fall through
2380       case Bytecodes::_if_icmpeq : // fall through
2381       case Bytecodes::_if_icmpne : // fall through
2382       case Bytecodes::_if_icmplt : // fall through
2383       case Bytecodes::_if_icmpge : // fall through
2384       case Bytecodes::_if_icmpgt : // fall through
2385       case Bytecodes::_if_icmple : // fall through
2386       case Bytecodes::_if_acmpeq : // fall through
2387       case Bytecodes::_if_acmpne :
2388         assert(stack_end >= -Bytecodes::depth(code), "must have non-empty expression stack at if bytecode");
2389         break;
2390       default:
2391         break;
2392     }
2393   }
2394 }
2395 
2396 #endif // ASSERT
2397 
2398 
2399 IntervalWalker* LinearScan::init_compute_oop_maps() {
2400   // setup lists of potential oops for walking
2401   Interval* oop_intervals;
2402   Interval* non_oop_intervals;
2403 
2404   create_unhandled_lists(&oop_intervals, &non_oop_intervals, is_oop_interval, NULL);
2405 
2406   // intervals that have no oops inside need not to be processed
2407   // to ensure a walking until the last instruction id, add a dummy interval
2408   // with a high operation id
2409   non_oop_intervals = new Interval(any_reg);
2410   non_oop_intervals->add_range(max_jint - 2, max_jint - 1);
2411 
2412   return new IntervalWalker(this, oop_intervals, non_oop_intervals);
2413 }
2414 
2415 
2416 OopMap* LinearScan::compute_oop_map(IntervalWalker* iw, LIR_Op* op, CodeEmitInfo* info, bool is_call_site) {
2417   TRACE_LINEAR_SCAN(3, tty->print_cr("creating oop map at op_id %d", op->id()));
2418 
2419   // walk before the current operation -> intervals that start at
2420   // the operation (= output operands of the operation) are not
2421   // included in the oop map
2422   iw->walk_before(op->id());
2423 
2424   int frame_size = frame_map()->framesize();
2425   int arg_count = frame_map()->oop_map_arg_count();
2426   OopMap* map = new OopMap(frame_size, arg_count);
2427 
2428   // Iterate through active intervals
2429   for (Interval* interval = iw->active_first(fixedKind); interval != Interval::end(); interval = interval->next()) {
2430     int assigned_reg = interval->assigned_reg();
2431 
2432     assert(interval->current_from() <= op->id() && op->id() <= interval->current_to(), "interval should not be active otherwise");
2433     assert(interval->assigned_regHi() == any_reg, "oop must be single word");
2434     assert(interval->reg_num() >= LIR_Opr::vreg_base, "fixed interval found");
2435 
2436     // Check if this range covers the instruction. Intervals that
2437     // start or end at the current operation are not included in the
2438     // oop map, except in the case of patching moves.  For patching
2439     // moves, any intervals which end at this instruction are included
2440     // in the oop map since we may safepoint while doing the patch
2441     // before we've consumed the inputs.
2442     if (op->is_patching() || op->id() < interval->current_to()) {
2443 
2444       // caller-save registers must not be included into oop-maps at calls
2445       assert(!is_call_site || assigned_reg >= nof_regs || !is_caller_save(assigned_reg), "interval is in a caller-save register at a call -> register will be overwritten");
2446 
2447       VMReg name = vm_reg_for_interval(interval);
2448       set_oop(map, name);
2449 
2450       // Spill optimization: when the stack value is guaranteed to be always correct,
2451       // then it must be added to the oop map even if the interval is currently in a register
2452       if (interval->always_in_memory() &&
2453           op->id() > interval->spill_definition_pos() &&
2454           interval->assigned_reg() != interval->canonical_spill_slot()) {
2455         assert(interval->spill_definition_pos() > 0, "position not set correctly");
2456         assert(interval->canonical_spill_slot() >= LinearScan::nof_regs, "no spill slot assigned");
2457         assert(interval->assigned_reg() < LinearScan::nof_regs, "interval is on stack, so stack slot is registered twice");
2458 
2459         set_oop(map, frame_map()->slot_regname(interval->canonical_spill_slot() - LinearScan::nof_regs));
2460       }
2461     }
2462   }
2463 
2464   // add oops from lock stack
2465   assert(info->stack() != NULL, "CodeEmitInfo must always have a stack");
2466   int locks_count = info->stack()->total_locks_size();
2467   for (int i = 0; i < locks_count; i++) {
2468     set_oop(map, frame_map()->monitor_object_regname(i));
2469   }
2470 
2471   return map;
2472 }
2473 
2474 
2475 void LinearScan::compute_oop_map(IntervalWalker* iw, const LIR_OpVisitState &visitor, LIR_Op* op) {
2476   assert(visitor.info_count() > 0, "no oop map needed");
2477 
2478   // compute oop_map only for first CodeEmitInfo
2479   // because it is (in most cases) equal for all other infos of the same operation
2480   CodeEmitInfo* first_info = visitor.info_at(0);
2481   OopMap* first_oop_map = compute_oop_map(iw, op, first_info, visitor.has_call());
2482 
2483   for (int i = 0; i < visitor.info_count(); i++) {
2484     CodeEmitInfo* info = visitor.info_at(i);
2485     OopMap* oop_map = first_oop_map;
2486 
2487     // compute worst case interpreter size in case of a deoptimization
2488     _compilation->update_interpreter_frame_size(info->interpreter_frame_size());
2489 
2490     if (info->stack()->locks_size() != first_info->stack()->locks_size()) {
2491       // this info has a different number of locks then the precomputed oop map
2492       // (possible for lock and unlock instructions) -> compute oop map with
2493       // correct lock information
2494       oop_map = compute_oop_map(iw, op, info, visitor.has_call());
2495     }
2496 
2497     if (info->_oop_map == NULL) {
2498       info->_oop_map = oop_map;
2499     } else {
2500       // a CodeEmitInfo can not be shared between different LIR-instructions
2501       // because interval splitting can occur anywhere between two instructions
2502       // and so the oop maps must be different
2503       // -> check if the already set oop_map is exactly the one calculated for this operation
2504       assert(info->_oop_map == oop_map, "same CodeEmitInfo used for multiple LIR instructions");
2505     }
2506   }
2507 }
2508 
2509 
2510 // frequently used constants
2511 // Allocate them with new so they are never destroyed (otherwise, a
2512 // forced exit could destroy these objects while they are still in
2513 // use).
2514 ConstantOopWriteValue* LinearScan::_oop_null_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantOopWriteValue(NULL);
2515 ConstantIntValue*      LinearScan::_int_m1_scope_value = new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(-1);
2516 ConstantIntValue*      LinearScan::_int_0_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue((jint)0);
2517 ConstantIntValue*      LinearScan::_int_1_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(1);
2518 ConstantIntValue*      LinearScan::_int_2_scope_value =  new (ResourceObj::C_HEAP, mtCompiler) ConstantIntValue(2);
2519 LocationValue*         _illegal_value = new (ResourceObj::C_HEAP, mtCompiler) LocationValue(Location());
2520 
2521 void LinearScan::init_compute_debug_info() {
2522   // cache for frequently used scope values
2523   // (cpu registers and stack slots)
2524   int cache_size = (LinearScan::nof_cpu_regs + frame_map()->argcount() + max_spills()) * 2;
2525   _scope_value_cache = ScopeValueArray(cache_size, cache_size, NULL);
2526 }
2527 
2528 MonitorValue* LinearScan::location_for_monitor_index(int monitor_index) {
2529   Location loc;
2530   if (!frame_map()->location_for_monitor_object(monitor_index, &loc)) {
2531     bailout("too large frame");
2532   }
2533   ScopeValue* object_scope_value = new LocationValue(loc);
2534 
2535   return new MonitorValue(object_scope_value, loc);
2536 }
2537 
2538 LocationValue* LinearScan::location_for_name(int name, Location::Type loc_type) {
2539   Location loc;
2540   if (!frame_map()->locations_for_slot(name, loc_type, &loc)) {
2541     bailout("too large frame");
2542   }
2543   return new LocationValue(loc);
2544 }
2545 
2546 
2547 int LinearScan::append_scope_value_for_constant(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2548   assert(opr->is_constant(), "should not be called otherwise");
2549 
2550   LIR_Const* c = opr->as_constant_ptr();
2551   BasicType t = c->type();
2552   switch (t) {
2553     case T_OBJECT: {
2554       jobject value = c->as_jobject();
2555       if (value == NULL) {
2556         scope_values->append(_oop_null_scope_value);
2557       } else {
2558         scope_values->append(new ConstantOopWriteValue(c->as_jobject()));
2559       }
2560       return 1;
2561     }
2562 
2563     case T_INT: // fall through
2564     case T_FLOAT: {
2565       int value = c->as_jint_bits();
2566       switch (value) {
2567         case -1: scope_values->append(_int_m1_scope_value); break;
2568         case 0:  scope_values->append(_int_0_scope_value); break;
2569         case 1:  scope_values->append(_int_1_scope_value); break;
2570         case 2:  scope_values->append(_int_2_scope_value); break;
2571         default: scope_values->append(new ConstantIntValue(c->as_jint_bits())); break;
2572       }
2573       return 1;
2574     }
2575 
2576     case T_LONG: // fall through
2577     case T_DOUBLE: {
2578 #ifdef _LP64
2579       scope_values->append(_int_0_scope_value);
2580       scope_values->append(new ConstantLongValue(c->as_jlong_bits()));
2581 #else
2582       if (hi_word_offset_in_bytes > lo_word_offset_in_bytes) {
2583         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2584         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2585       } else {
2586         scope_values->append(new ConstantIntValue(c->as_jint_lo_bits()));
2587         scope_values->append(new ConstantIntValue(c->as_jint_hi_bits()));
2588       }
2589 #endif
2590       return 2;
2591     }
2592 
2593     case T_ADDRESS: {
2594 #ifdef _LP64
2595       scope_values->append(new ConstantLongValue(c->as_jint()));
2596 #else
2597       scope_values->append(new ConstantIntValue(c->as_jint()));
2598 #endif
2599       return 1;
2600     }
2601 
2602     default:
2603       ShouldNotReachHere();
2604       return -1;
2605   }
2606 }
2607 
2608 int LinearScan::append_scope_value_for_operand(LIR_Opr opr, GrowableArray<ScopeValue*>* scope_values) {
2609   if (opr->is_single_stack()) {
2610     int stack_idx = opr->single_stack_ix();
2611     bool is_oop = opr->is_oop_register();
2612     int cache_idx = (stack_idx + LinearScan::nof_cpu_regs) * 2 + (is_oop ? 1 : 0);
2613 
2614     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2615     if (sv == NULL) {
2616       Location::Type loc_type = is_oop ? Location::oop : Location::normal;
2617       sv = location_for_name(stack_idx, loc_type);
2618       _scope_value_cache.at_put(cache_idx, sv);
2619     }
2620 
2621     // check if cached value is correct
2622     DEBUG_ONLY(assert_equal(sv, location_for_name(stack_idx, is_oop ? Location::oop : Location::normal)));
2623 
2624     scope_values->append(sv);
2625     return 1;
2626 
2627   } else if (opr->is_single_cpu()) {
2628     bool is_oop = opr->is_oop_register();
2629     int cache_idx = opr->cpu_regnr() * 2 + (is_oop ? 1 : 0);
2630     Location::Type int_loc_type = NOT_LP64(Location::normal) LP64_ONLY(Location::int_in_long);
2631 
2632     ScopeValue* sv = _scope_value_cache.at(cache_idx);
2633     if (sv == NULL) {
2634       Location::Type loc_type = is_oop ? Location::oop : int_loc_type;
2635       VMReg rname = frame_map()->regname(opr);
2636       sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2637       _scope_value_cache.at_put(cache_idx, sv);
2638     }
2639 
2640     // check if cached value is correct
2641     DEBUG_ONLY(assert_equal(sv, new LocationValue(Location::new_reg_loc(is_oop ? Location::oop : int_loc_type, frame_map()->regname(opr)))));
2642 
2643     scope_values->append(sv);
2644     return 1;
2645 
2646 #ifdef X86
2647   } else if (opr->is_single_xmm()) {
2648     VMReg rname = opr->as_xmm_float_reg()->as_VMReg();
2649     LocationValue* sv = new LocationValue(Location::new_reg_loc(Location::normal, rname));
2650 
2651     scope_values->append(sv);
2652     return 1;
2653 #endif
2654 
2655   } else if (opr->is_single_fpu()) {
2656 #ifdef IA32
2657     // the exact location of fpu stack values is only known
2658     // during fpu stack allocation, so the stack allocator object
2659     // must be present
2660     assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2661     assert(_fpu_stack_allocator != NULL, "must be present");
2662     opr = _fpu_stack_allocator->to_fpu_stack(opr);
2663 #elif defined(AMD64)
2664     assert(false, "FPU not used on x86-64");
2665 #endif
2666 
2667     Location::Type loc_type = float_saved_as_double ? Location::float_in_dbl : Location::normal;
2668     VMReg rname = frame_map()->fpu_regname(opr->fpu_regnr());
2669 #ifndef __SOFTFP__
2670 #ifndef VM_LITTLE_ENDIAN
2671     // On S390 a (single precision) float value occupies only the high
2672     // word of the full double register. So when the double register is
2673     // stored to memory (e.g. by the RegisterSaver), then the float value
2674     // is found at offset 0. I.e. the code below is not needed on S390.
2675 #ifndef S390
2676     if (! float_saved_as_double) {
2677       // On big endian system, we may have an issue if float registers use only
2678       // the low half of the (same) double registers.
2679       // Both the float and the double could have the same regnr but would correspond
2680       // to two different addresses once saved.
2681 
2682       // get next safely (no assertion checks)
2683       VMReg next = VMRegImpl::as_VMReg(1+rname->value());
2684       if (next->is_reg() &&
2685           (next->as_FloatRegister() == rname->as_FloatRegister())) {
2686         // the back-end does use the same numbering for the double and the float
2687         rname = next; // VMReg for the low bits, e.g. the real VMReg for the float
2688       }
2689     }
2690 #endif // !S390
2691 #endif
2692 #endif
2693     LocationValue* sv = new LocationValue(Location::new_reg_loc(loc_type, rname));
2694 
2695     scope_values->append(sv);
2696     return 1;
2697 
2698   } else {
2699     // double-size operands
2700 
2701     ScopeValue* first;
2702     ScopeValue* second;
2703 
2704     if (opr->is_double_stack()) {
2705 #ifdef _LP64
2706       Location loc1;
2707       Location::Type loc_type = opr->type() == T_LONG ? Location::lng : Location::dbl;
2708       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), loc_type, &loc1, NULL)) {
2709         bailout("too large frame");
2710       }
2711 
2712       first =  new LocationValue(loc1);
2713       second = _int_0_scope_value;
2714 #else
2715       Location loc1, loc2;
2716       if (!frame_map()->locations_for_slot(opr->double_stack_ix(), Location::normal, &loc1, &loc2)) {
2717         bailout("too large frame");
2718       }
2719       first =  new LocationValue(loc1);
2720       second = new LocationValue(loc2);
2721 #endif // _LP64
2722 
2723     } else if (opr->is_double_cpu()) {
2724 #ifdef _LP64
2725       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2726       first = new LocationValue(Location::new_reg_loc(Location::lng, rname_first));
2727       second = _int_0_scope_value;
2728 #else
2729       VMReg rname_first = opr->as_register_lo()->as_VMReg();
2730       VMReg rname_second = opr->as_register_hi()->as_VMReg();
2731 
2732       if (hi_word_offset_in_bytes < lo_word_offset_in_bytes) {
2733         // lo/hi and swapped relative to first and second, so swap them
2734         VMReg tmp = rname_first;
2735         rname_first = rname_second;
2736         rname_second = tmp;
2737       }
2738 
2739       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2740       second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2741 #endif //_LP64
2742 
2743 
2744 #ifdef X86
2745     } else if (opr->is_double_xmm()) {
2746       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation");
2747       VMReg rname_first  = opr->as_xmm_double_reg()->as_VMReg();
2748 #  ifdef _LP64
2749       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2750       second = _int_0_scope_value;
2751 #  else
2752       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2753       // %%% This is probably a waste but we'll keep things as they were for now
2754       if (true) {
2755         VMReg rname_second = rname_first->next();
2756         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2757       }
2758 #  endif
2759 #endif
2760 
2761     } else if (opr->is_double_fpu()) {
2762       // On SPARC, fpu_regnrLo/fpu_regnrHi represents the two halves of
2763       // the double as float registers in the native ordering. On X86,
2764       // fpu_regnrLo is a FPU stack slot whose VMReg represents
2765       // the low-order word of the double and fpu_regnrLo + 1 is the
2766       // name for the other half.  *first and *second must represent the
2767       // least and most significant words, respectively.
2768 
2769 #ifdef IA32
2770       // the exact location of fpu stack values is only known
2771       // during fpu stack allocation, so the stack allocator object
2772       // must be present
2773       assert(use_fpu_stack_allocation(), "should not have float stack values without fpu stack allocation (all floats must be SSE2)");
2774       assert(_fpu_stack_allocator != NULL, "must be present");
2775       opr = _fpu_stack_allocator->to_fpu_stack(opr);
2776 
2777       assert(opr->fpu_regnrLo() == opr->fpu_regnrHi(), "assumed in calculation (only fpu_regnrLo is used)");
2778 #endif
2779 #ifdef AMD64
2780       assert(false, "FPU not used on x86-64");
2781 #endif
2782 #ifdef ARM32
2783       assert(opr->fpu_regnrHi() == opr->fpu_regnrLo() + 1, "assumed in calculation (only fpu_regnrLo is used)");
2784 #endif
2785 
2786 #ifdef VM_LITTLE_ENDIAN
2787       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrLo());
2788 #else
2789       VMReg rname_first = frame_map()->fpu_regname(opr->fpu_regnrHi());
2790 #endif
2791 
2792 #ifdef _LP64
2793       first = new LocationValue(Location::new_reg_loc(Location::dbl, rname_first));
2794       second = _int_0_scope_value;
2795 #else
2796       first = new LocationValue(Location::new_reg_loc(Location::normal, rname_first));
2797       // %%% This is probably a waste but we'll keep things as they were for now
2798       if (true) {
2799         VMReg rname_second = rname_first->next();
2800         second = new LocationValue(Location::new_reg_loc(Location::normal, rname_second));
2801       }
2802 #endif
2803 
2804     } else {
2805       ShouldNotReachHere();
2806       first = NULL;
2807       second = NULL;
2808     }
2809 
2810     assert(first != NULL && second != NULL, "must be set");
2811     // The convention the interpreter uses is that the second local
2812     // holds the first raw word of the native double representation.
2813     // This is actually reasonable, since locals and stack arrays
2814     // grow downwards in all implementations.
2815     // (If, on some machine, the interpreter's Java locals or stack
2816     // were to grow upwards, the embedded doubles would be word-swapped.)
2817     scope_values->append(second);
2818     scope_values->append(first);
2819     return 2;
2820   }
2821 }
2822 
2823 
2824 int LinearScan::append_scope_value(int op_id, Value value, GrowableArray<ScopeValue*>* scope_values) {
2825   if (value != NULL) {
2826     LIR_Opr opr = value->operand();
2827     Constant* con = value->as_Constant();
2828 
2829     assert(con == NULL || opr->is_virtual() || opr->is_constant() || opr->is_illegal(), "assumption: Constant instructions have only constant operands (or illegal if constant is optimized away)");
2830     assert(con != NULL || opr->is_virtual(), "assumption: non-Constant instructions have only virtual operands");
2831 
2832     if (con != NULL && !con->is_pinned() && !opr->is_constant()) {
2833       // Unpinned constants may have a virtual operand for a part of the lifetime
2834       // or may be illegal when it was optimized away,
2835       // so always use a constant operand
2836       opr = LIR_OprFact::value_type(con->type());
2837     }
2838     assert(opr->is_virtual() || opr->is_constant(), "other cases not allowed here");
2839 
2840     if (opr->is_virtual()) {
2841       LIR_OpVisitState::OprMode mode = LIR_OpVisitState::inputMode;
2842 
2843       BlockBegin* block = block_of_op_with_id(op_id);
2844       if (block->number_of_sux() == 1 && op_id == block->last_lir_instruction_id()) {
2845         // generating debug information for the last instruction of a block.
2846         // if this instruction is a branch, spill moves are inserted before this branch
2847         // and so the wrong operand would be returned (spill moves at block boundaries are not
2848         // considered in the live ranges of intervals)
2849         // Solution: use the first op_id of the branch target block instead.
2850         if (block->lir()->instructions_list()->last()->as_OpBranch() != NULL) {
2851           if (block->live_out().at(opr->vreg_number())) {
2852             op_id = block->sux_at(0)->first_lir_instruction_id();
2853             mode = LIR_OpVisitState::outputMode;
2854           }
2855         }
2856       }
2857 
2858       // Get current location of operand
2859       // The operand must be live because debug information is considered when building the intervals
2860       // if the interval is not live, color_lir_opr will cause an assertion failure
2861       opr = color_lir_opr(opr, op_id, mode);
2862       assert(!has_call(op_id) || opr->is_stack() || !is_caller_save(reg_num(opr)), "can not have caller-save register operands at calls");
2863 
2864       // Append to ScopeValue array
2865       return append_scope_value_for_operand(opr, scope_values);
2866 
2867     } else {
2868       assert(value->as_Constant() != NULL, "all other instructions have only virtual operands");
2869       assert(opr->is_constant(), "operand must be constant");
2870 
2871       return append_scope_value_for_constant(opr, scope_values);
2872     }
2873   } else {
2874     // append a dummy value because real value not needed
2875     scope_values->append(_illegal_value);
2876     return 1;
2877   }
2878 }
2879 
2880 
2881 IRScopeDebugInfo* LinearScan::compute_debug_info_for_scope(int op_id, IRScope* cur_scope, ValueStack* cur_state, ValueStack* innermost_state) {
2882   IRScopeDebugInfo* caller_debug_info = NULL;
2883 
2884   ValueStack* caller_state = cur_state->caller_state();
2885   if (caller_state != NULL) {
2886     // process recursively to compute outermost scope first
2887     caller_debug_info = compute_debug_info_for_scope(op_id, cur_scope->caller(), caller_state, innermost_state);
2888   }
2889 
2890   // initialize these to null.
2891   // If we don't need deopt info or there are no locals, expressions or monitors,
2892   // then these get recorded as no information and avoids the allocation of 0 length arrays.
2893   GrowableArray<ScopeValue*>*   locals      = NULL;
2894   GrowableArray<ScopeValue*>*   expressions = NULL;
2895   GrowableArray<MonitorValue*>* monitors    = NULL;
2896 
2897   // describe local variable values
2898   int nof_locals = cur_state->locals_size();
2899   if (nof_locals > 0) {
2900     locals = new GrowableArray<ScopeValue*>(nof_locals);
2901 
2902     int pos = 0;
2903     while (pos < nof_locals) {
2904       assert(pos < cur_state->locals_size(), "why not?");
2905 
2906       Value local = cur_state->local_at(pos);
2907       pos += append_scope_value(op_id, local, locals);
2908 
2909       assert(locals->length() == pos, "must match");
2910     }
2911     assert(locals->length() == cur_scope->method()->max_locals(), "wrong number of locals");
2912     assert(locals->length() == cur_state->locals_size(), "wrong number of locals");
2913   } else if (cur_scope->method()->max_locals() > 0) {
2914     assert(cur_state->kind() == ValueStack::EmptyExceptionState, "should be");
2915     nof_locals = cur_scope->method()->max_locals();
2916     locals = new GrowableArray<ScopeValue*>(nof_locals);
2917     for(int i = 0; i < nof_locals; i++) {
2918       locals->append(_illegal_value);
2919     }
2920   }
2921 
2922   // describe expression stack
2923   int nof_stack = cur_state->stack_size();
2924   if (nof_stack > 0) {
2925     expressions = new GrowableArray<ScopeValue*>(nof_stack);
2926 
2927     int pos = 0;
2928     while (pos < nof_stack) {
2929       Value expression = cur_state->stack_at_inc(pos);
2930       append_scope_value(op_id, expression, expressions);
2931 
2932       assert(expressions->length() == pos, "must match");
2933     }
2934     assert(expressions->length() == cur_state->stack_size(), "wrong number of stack entries");
2935   }
2936 
2937   // describe monitors
2938   int nof_locks = cur_state->locks_size();
2939   if (nof_locks > 0) {
2940     int lock_offset = cur_state->caller_state() != NULL ? cur_state->caller_state()->total_locks_size() : 0;
2941     monitors = new GrowableArray<MonitorValue*>(nof_locks);
2942     for (int i = 0; i < nof_locks; i++) {
2943       monitors->append(location_for_monitor_index(lock_offset + i));
2944     }
2945   }
2946 
2947   return new IRScopeDebugInfo(cur_scope, cur_state->bci(), locals, expressions, monitors, caller_debug_info);
2948 }
2949 
2950 
2951 void LinearScan::compute_debug_info(CodeEmitInfo* info, int op_id) {
2952   TRACE_LINEAR_SCAN(3, tty->print_cr("creating debug information at op_id %d", op_id));
2953 
2954   IRScope* innermost_scope = info->scope();
2955   ValueStack* innermost_state = info->stack();
2956 
2957   assert(innermost_scope != NULL && innermost_state != NULL, "why is it missing?");
2958 
2959   DEBUG_ONLY(check_stack_depth(info, innermost_state->stack_size()));
2960 
2961   if (info->_scope_debug_info == NULL) {
2962     // compute debug information
2963     info->_scope_debug_info = compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state);
2964   } else {
2965     // debug information already set. Check that it is correct from the current point of view
2966     DEBUG_ONLY(assert_equal(info->_scope_debug_info, compute_debug_info_for_scope(op_id, innermost_scope, innermost_state, innermost_state)));
2967   }
2968 }
2969 
2970 
2971 void LinearScan::assign_reg_num(LIR_OpList* instructions, IntervalWalker* iw) {
2972   LIR_OpVisitState visitor;
2973   int num_inst = instructions->length();
2974   bool has_dead = false;
2975 
2976   for (int j = 0; j < num_inst; j++) {
2977     LIR_Op* op = instructions->at(j);
2978     if (op == NULL) {  // this can happen when spill-moves are removed in eliminate_spill_moves
2979       has_dead = true;
2980       continue;
2981     }
2982     int op_id = op->id();
2983 
2984     // visit instruction to get list of operands
2985     visitor.visit(op);
2986 
2987     // iterate all modes of the visitor and process all virtual operands
2988     for_each_visitor_mode(mode) {
2989       int n = visitor.opr_count(mode);
2990       for (int k = 0; k < n; k++) {
2991         LIR_Opr opr = visitor.opr_at(mode, k);
2992         if (opr->is_virtual_register()) {
2993           visitor.set_opr_at(mode, k, color_lir_opr(opr, op_id, mode));
2994         }
2995       }
2996     }
2997 
2998     if (visitor.info_count() > 0) {
2999       // exception handling
3000       if (compilation()->has_exception_handlers()) {
3001         XHandlers* xhandlers = visitor.all_xhandler();
3002         int n = xhandlers->length();
3003         for (int k = 0; k < n; k++) {
3004           XHandler* handler = xhandlers->handler_at(k);
3005           if (handler->entry_code() != NULL) {
3006             assign_reg_num(handler->entry_code()->instructions_list(), NULL);
3007           }
3008         }
3009       } else {
3010         assert(visitor.all_xhandler()->length() == 0, "missed exception handler");
3011       }
3012 
3013       // compute oop map
3014       assert(iw != NULL, "needed for compute_oop_map");
3015       compute_oop_map(iw, visitor, op);
3016 
3017       // compute debug information
3018       if (!use_fpu_stack_allocation()) {
3019         // compute debug information if fpu stack allocation is not needed.
3020         // when fpu stack allocation is needed, the debug information can not
3021         // be computed here because the exact location of fpu operands is not known
3022         // -> debug information is created inside the fpu stack allocator
3023         int n = visitor.info_count();
3024         for (int k = 0; k < n; k++) {
3025           compute_debug_info(visitor.info_at(k), op_id);
3026         }
3027       }
3028     }
3029 
3030 #ifdef ASSERT
3031     // make sure we haven't made the op invalid.
3032     op->verify();
3033 #endif
3034 
3035     // remove useless moves
3036     if (op->code() == lir_move) {
3037       assert(op->as_Op1() != NULL, "move must be LIR_Op1");
3038       LIR_Op1* move = (LIR_Op1*)op;
3039       LIR_Opr src = move->in_opr();
3040       LIR_Opr dst = move->result_opr();
3041       if (dst == src ||
3042           (!dst->is_pointer() && !src->is_pointer() &&
3043            src->is_same_register(dst))) {
3044         instructions->at_put(j, NULL);
3045         has_dead = true;
3046       }
3047     }
3048   }
3049 
3050   if (has_dead) {
3051     // iterate all instructions of the block and remove all null-values.
3052     int insert_point = 0;
3053     for (int j = 0; j < num_inst; j++) {
3054       LIR_Op* op = instructions->at(j);
3055       if (op != NULL) {
3056         if (insert_point != j) {
3057           instructions->at_put(insert_point, op);
3058         }
3059         insert_point++;
3060       }
3061     }
3062     instructions->trunc_to(insert_point);
3063   }
3064 }
3065 
3066 void LinearScan::assign_reg_num() {
3067   TIME_LINEAR_SCAN(timer_assign_reg_num);
3068 
3069   init_compute_debug_info();
3070   IntervalWalker* iw = init_compute_oop_maps();
3071 
3072   int num_blocks = block_count();
3073   for (int i = 0; i < num_blocks; i++) {
3074     BlockBegin* block = block_at(i);
3075     assign_reg_num(block->lir()->instructions_list(), iw);
3076   }
3077 }
3078 
3079 
3080 void LinearScan::do_linear_scan() {
3081   NOT_PRODUCT(_total_timer.begin_method());
3082 
3083   number_instructions();
3084 
3085   NOT_PRODUCT(print_lir(1, "Before Register Allocation"));
3086 
3087   compute_local_live_sets();
3088   compute_global_live_sets();
3089   CHECK_BAILOUT();
3090 
3091   build_intervals();
3092   CHECK_BAILOUT();
3093   sort_intervals_before_allocation();
3094 
3095   NOT_PRODUCT(print_intervals("Before Register Allocation"));
3096   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_before_alloc));
3097 
3098   allocate_registers();
3099   CHECK_BAILOUT();
3100 
3101   resolve_data_flow();
3102   if (compilation()->has_exception_handlers()) {
3103     resolve_exception_handlers();
3104   }
3105   // fill in number of spill slots into frame_map
3106   propagate_spill_slots();
3107   CHECK_BAILOUT();
3108 
3109   NOT_PRODUCT(print_intervals("After Register Allocation"));
3110   NOT_PRODUCT(print_lir(2, "LIR after register allocation:"));
3111 
3112   sort_intervals_after_allocation();
3113 
3114   DEBUG_ONLY(verify());
3115 
3116   eliminate_spill_moves();
3117   assign_reg_num();
3118   CHECK_BAILOUT();
3119 
3120   NOT_PRODUCT(print_lir(2, "LIR after assignment of register numbers:"));
3121   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_after_asign));
3122 
3123   { TIME_LINEAR_SCAN(timer_allocate_fpu_stack);
3124 
3125     if (use_fpu_stack_allocation()) {
3126       allocate_fpu_stack(); // Only has effect on Intel
3127       NOT_PRODUCT(print_lir(2, "LIR after FPU stack allocation:"));
3128     }
3129   }
3130 
3131 #ifndef RISCV
3132   // Disable these optimizations on riscv temporarily, because it does not
3133   // work when the comparison operands are bound to branches or cmoves.
3134   { TIME_LINEAR_SCAN(timer_optimize_lir);
3135 
3136     EdgeMoveOptimizer::optimize(ir()->code());
3137     ControlFlowOptimizer::optimize(ir()->code());
3138     // check that cfg is still correct after optimizations
3139     ir()->verify();
3140   }
3141 #endif
3142 
3143   NOT_PRODUCT(print_lir(1, "Before Code Generation", false));
3144   NOT_PRODUCT(LinearScanStatistic::compute(this, _stat_final));
3145   NOT_PRODUCT(_total_timer.end_method(this));
3146 }
3147 
3148 
3149 // ********** Printing functions
3150 
3151 #ifndef PRODUCT
3152 
3153 void LinearScan::print_timers(double total) {
3154   _total_timer.print(total);
3155 }
3156 
3157 void LinearScan::print_statistics() {
3158   _stat_before_alloc.print("before allocation");
3159   _stat_after_asign.print("after assignment of register");
3160   _stat_final.print("after optimization");
3161 }
3162 
3163 void LinearScan::print_bitmap(BitMap& b) {
3164   for (unsigned int i = 0; i < b.size(); i++) {
3165     if (b.at(i)) tty->print("%d ", i);
3166   }
3167   tty->cr();
3168 }
3169 
3170 void LinearScan::print_intervals(const char* label) {
3171   if (TraceLinearScanLevel >= 1) {
3172     int i;
3173     tty->cr();
3174     tty->print_cr("%s", label);
3175 
3176     for (i = 0; i < interval_count(); i++) {
3177       Interval* interval = interval_at(i);
3178       if (interval != NULL) {
3179         interval->print();
3180       }
3181     }
3182 
3183     tty->cr();
3184     tty->print_cr("--- Basic Blocks ---");
3185     for (i = 0; i < block_count(); i++) {
3186       BlockBegin* block = block_at(i);
3187       tty->print("B%d [%d, %d, %d, %d] ", block->block_id(), block->first_lir_instruction_id(), block->last_lir_instruction_id(), block->loop_index(), block->loop_depth());
3188     }
3189     tty->cr();
3190     tty->cr();
3191   }
3192 
3193   if (PrintCFGToFile) {
3194     CFGPrinter::print_intervals(&_intervals, label);
3195   }
3196 }
3197 
3198 void LinearScan::print_lir(int level, const char* label, bool hir_valid) {
3199   if (TraceLinearScanLevel >= level) {
3200     tty->cr();
3201     tty->print_cr("%s", label);
3202     print_LIR(ir()->linear_scan_order());
3203     tty->cr();
3204   }
3205 
3206   if (level == 1 && PrintCFGToFile) {
3207     CFGPrinter::print_cfg(ir()->linear_scan_order(), label, hir_valid, true);
3208   }
3209 }
3210 
3211 void LinearScan::print_reg_num(outputStream* out, int reg_num) {
3212   if (reg_num == -1) {
3213     out->print("[ANY]");
3214     return;
3215   } else if (reg_num >= LIR_Opr::vreg_base) {
3216     out->print("[VREG %d]", reg_num);
3217     return;
3218   }
3219 
3220   LIR_Opr opr = get_operand(reg_num);
3221   assert(opr->is_valid(), "unknown register");
3222   opr->print(out);
3223 }
3224 
3225 LIR_Opr LinearScan::get_operand(int reg_num) {
3226   LIR_Opr opr = LIR_OprFact::illegal();
3227 
3228 #ifdef X86
3229   int last_xmm_reg = pd_last_xmm_reg;
3230 #ifdef _LP64
3231   if (UseAVX < 3) {
3232     last_xmm_reg = pd_first_xmm_reg + (pd_nof_xmm_regs_frame_map / 2) - 1;
3233   }
3234 #endif
3235 #endif
3236   if (reg_num >= pd_first_cpu_reg && reg_num <= pd_last_cpu_reg) {
3237     opr = LIR_OprFact::single_cpu(reg_num);
3238   } else if (reg_num >= pd_first_fpu_reg && reg_num <= pd_last_fpu_reg) {
3239     opr = LIR_OprFact::single_fpu(reg_num - pd_first_fpu_reg);
3240 #ifdef X86
3241   } else if (reg_num >= pd_first_xmm_reg && reg_num <= last_xmm_reg) {
3242     opr = LIR_OprFact::single_xmm(reg_num - pd_first_xmm_reg);
3243 #endif
3244   } else {
3245     // reg_num == -1 or a virtual register, return the illegal operand
3246   }
3247   return opr;
3248 }
3249 
3250 Interval* LinearScan::find_interval_at(int reg_num) const {
3251   if (reg_num < 0 || reg_num >= _intervals.length()) {
3252     return NULL;
3253   }
3254   return interval_at(reg_num);
3255 }
3256 
3257 #endif // PRODUCT
3258 
3259 
3260 // ********** verification functions for allocation
3261 // (check that all intervals have a correct register and that no registers are overwritten)
3262 #ifdef ASSERT
3263 
3264 void LinearScan::verify() {
3265   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying intervals ******************************************"));
3266   verify_intervals();
3267 
3268   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that no oops are in fixed intervals ****************"));
3269   verify_no_oops_in_fixed_intervals();
3270 
3271   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying that unpinned constants are not alive across block boundaries"));
3272   verify_constants();
3273 
3274   TRACE_LINEAR_SCAN(2, tty->print_cr("********* verifying register allocation ********************************"));
3275   verify_registers();
3276 
3277   TRACE_LINEAR_SCAN(2, tty->print_cr("********* no errors found **********************************************"));
3278 }
3279 
3280 void LinearScan::verify_intervals() {
3281   int len = interval_count();
3282   bool has_error = false;
3283 
3284   for (int i = 0; i < len; i++) {
3285     Interval* i1 = interval_at(i);
3286     if (i1 == NULL) continue;
3287 
3288     i1->check_split_children();
3289 
3290     if (i1->reg_num() != i) {
3291       tty->print_cr("Interval %d is on position %d in list", i1->reg_num(), i); i1->print(); tty->cr();
3292       has_error = true;
3293     }
3294 
3295     if (i1->reg_num() >= LIR_Opr::vreg_base && i1->type() == T_ILLEGAL) {
3296       tty->print_cr("Interval %d has no type assigned", i1->reg_num()); i1->print(); tty->cr();
3297       has_error = true;
3298     }
3299 
3300     if (i1->assigned_reg() == any_reg) {
3301       tty->print_cr("Interval %d has no register assigned", i1->reg_num()); i1->print(); tty->cr();
3302       has_error = true;
3303     }
3304 
3305     if (i1->assigned_reg() == i1->assigned_regHi()) {
3306       tty->print_cr("Interval %d: low and high register equal", i1->reg_num()); i1->print(); tty->cr();
3307       has_error = true;
3308     }
3309 
3310     if (!is_processed_reg_num(i1->assigned_reg())) {
3311       tty->print_cr("Can not have an Interval for an ignored register"); i1->print(); tty->cr();
3312       has_error = true;
3313     }
3314 
3315     // special intervals that are created in MoveResolver
3316     // -> ignore them because the range information has no meaning there
3317     if (i1->from() == 1 && i1->to() == 2) continue;
3318 
3319     if (i1->first() == Range::end()) {
3320       tty->print_cr("Interval %d has no Range", i1->reg_num()); i1->print(); tty->cr();
3321       has_error = true;
3322     }
3323 
3324     for (Range* r = i1->first(); r != Range::end(); r = r->next()) {
3325       if (r->from() >= r->to()) {
3326         tty->print_cr("Interval %d has zero length range", i1->reg_num()); i1->print(); tty->cr();
3327         has_error = true;
3328       }
3329     }
3330 
3331     for (int j = i + 1; j < len; j++) {
3332       Interval* i2 = interval_at(j);
3333       if (i2 == NULL || (i2->from() == 1 && i2->to() == 2)) continue;
3334 
3335       int r1 = i1->assigned_reg();
3336       int r1Hi = i1->assigned_regHi();
3337       int r2 = i2->assigned_reg();
3338       int r2Hi = i2->assigned_regHi();
3339       if ((r1 == r2 || r1 == r2Hi || (r1Hi != any_reg && (r1Hi == r2 || r1Hi == r2Hi))) && i1->intersects(i2)) {
3340         tty->print_cr("Intervals %d and %d overlap and have the same register assigned", i1->reg_num(), i2->reg_num());
3341         i1->print(); tty->cr();
3342         i2->print(); tty->cr();
3343         has_error = true;
3344       }
3345     }
3346   }
3347 
3348   assert(has_error == false, "register allocation invalid");
3349 }
3350 
3351 
3352 void LinearScan::verify_no_oops_in_fixed_intervals() {
3353   Interval* fixed_intervals;
3354   Interval* other_intervals;
3355   create_unhandled_lists(&fixed_intervals, &other_intervals, is_precolored_cpu_interval, NULL);
3356 
3357   // to ensure a walking until the last instruction id, add a dummy interval
3358   // with a high operation id
3359   other_intervals = new Interval(any_reg);
3360   other_intervals->add_range(max_jint - 2, max_jint - 1);
3361   IntervalWalker* iw = new IntervalWalker(this, fixed_intervals, other_intervals);
3362 
3363   LIR_OpVisitState visitor;
3364   for (int i = 0; i < block_count(); i++) {
3365     BlockBegin* block = block_at(i);
3366 
3367     LIR_OpList* instructions = block->lir()->instructions_list();
3368 
3369     for (int j = 0; j < instructions->length(); j++) {
3370       LIR_Op* op = instructions->at(j);
3371       int op_id = op->id();
3372 
3373       visitor.visit(op);
3374 
3375       if (visitor.info_count() > 0) {
3376         iw->walk_before(op->id());
3377         bool check_live = true;
3378         if (op->code() == lir_move) {
3379           LIR_Op1* move = (LIR_Op1*)op;
3380           check_live = (move->patch_code() == lir_patch_none);
3381         }
3382         LIR_OpBranch* branch = op->as_OpBranch();
3383         if (branch != NULL && branch->stub() != NULL && branch->stub()->is_exception_throw_stub()) {
3384           // Don't bother checking the stub in this case since the
3385           // exception stub will never return to normal control flow.
3386           check_live = false;
3387         }
3388 
3389         // Make sure none of the fixed registers is live across an
3390         // oopmap since we can't handle that correctly.
3391         if (check_live) {
3392           for (Interval* interval = iw->active_first(fixedKind);
3393                interval != Interval::end();
3394                interval = interval->next()) {
3395             if (interval->current_to() > op->id() + 1) {
3396               // This interval is live out of this op so make sure
3397               // that this interval represents some value that's
3398               // referenced by this op either as an input or output.
3399               bool ok = false;
3400               for_each_visitor_mode(mode) {
3401                 int n = visitor.opr_count(mode);
3402                 for (int k = 0; k < n; k++) {
3403                   LIR_Opr opr = visitor.opr_at(mode, k);
3404                   if (opr->is_fixed_cpu()) {
3405                     if (interval_at(reg_num(opr)) == interval) {
3406                       ok = true;
3407                       break;
3408                     }
3409                     int hi = reg_numHi(opr);
3410                     if (hi != -1 && interval_at(hi) == interval) {
3411                       ok = true;
3412                       break;
3413                     }
3414                   }
3415                 }
3416               }
3417               assert(ok, "fixed intervals should never be live across an oopmap point");
3418             }
3419           }
3420         }
3421       }
3422 
3423       // oop-maps at calls do not contain registers, so check is not needed
3424       if (!visitor.has_call()) {
3425 
3426         for_each_visitor_mode(mode) {
3427           int n = visitor.opr_count(mode);
3428           for (int k = 0; k < n; k++) {
3429             LIR_Opr opr = visitor.opr_at(mode, k);
3430 
3431             if (opr->is_fixed_cpu() && opr->is_oop()) {
3432               // operand is a non-virtual cpu register and contains an oop
3433               TRACE_LINEAR_SCAN(4, op->print_on(tty); tty->print("checking operand "); opr->print(); tty->cr());
3434 
3435               Interval* interval = interval_at(reg_num(opr));
3436               assert(interval != NULL, "no interval");
3437 
3438               if (mode == LIR_OpVisitState::inputMode) {
3439                 if (interval->to() >= op_id + 1) {
3440                   assert(interval->to() < op_id + 2 ||
3441                          interval->has_hole_between(op_id, op_id + 2),
3442                          "oop input operand live after instruction");
3443                 }
3444               } else if (mode == LIR_OpVisitState::outputMode) {
3445                 if (interval->from() <= op_id - 1) {
3446                   assert(interval->has_hole_between(op_id - 1, op_id),
3447                          "oop input operand live after instruction");
3448                 }
3449               }
3450             }
3451           }
3452         }
3453       }
3454     }
3455   }
3456 }
3457 
3458 
3459 void LinearScan::verify_constants() {
3460   int num_regs = num_virtual_regs();
3461   int size = live_set_size();
3462   int num_blocks = block_count();
3463 
3464   for (int i = 0; i < num_blocks; i++) {
3465     BlockBegin* block = block_at(i);
3466     ResourceBitMap live_at_edge = block->live_in();
3467 
3468     // visit all registers where the live_at_edge bit is set
3469     for (int r = (int)live_at_edge.get_next_one_offset(0, size); r < size; r = (int)live_at_edge.get_next_one_offset(r + 1, size)) {
3470       TRACE_LINEAR_SCAN(4, tty->print("checking interval %d of block B%d", r, block->block_id()));
3471 
3472       Value value = gen()->instruction_for_vreg(r);
3473 
3474       assert(value != NULL, "all intervals live across block boundaries must have Value");
3475       assert(value->operand()->is_register() && value->operand()->is_virtual(), "value must have virtual operand");
3476       assert(value->operand()->vreg_number() == r, "register number must match");
3477       // TKR assert(value->as_Constant() == NULL || value->is_pinned(), "only pinned constants can be alive across block boundaries");
3478     }
3479   }
3480 }
3481 
3482 
3483 class RegisterVerifier: public StackObj {
3484  private:
3485   LinearScan*   _allocator;
3486   BlockList     _work_list;      // all blocks that must be processed
3487   IntervalsList _saved_states;   // saved information of previous check
3488 
3489   // simplified access to methods of LinearScan
3490   Compilation*  compilation() const              { return _allocator->compilation(); }
3491   Interval*     interval_at(int reg_num) const   { return _allocator->interval_at(reg_num); }
3492   int           reg_num(LIR_Opr opr) const       { return _allocator->reg_num(opr); }
3493 
3494   // currently, only registers are processed
3495   int           state_size()                     { return LinearScan::nof_regs; }
3496 
3497   // accessors
3498   IntervalList* state_for_block(BlockBegin* block) { return _saved_states.at(block->block_id()); }
3499   void          set_state_for_block(BlockBegin* block, IntervalList* saved_state) { _saved_states.at_put(block->block_id(), saved_state); }
3500   void          add_to_work_list(BlockBegin* block) { if (!_work_list.contains(block)) _work_list.append(block); }
3501 
3502   // helper functions
3503   IntervalList* copy(IntervalList* input_state);
3504   void          state_put(IntervalList* input_state, int reg, Interval* interval);
3505   bool          check_state(IntervalList* input_state, int reg, Interval* interval);
3506 
3507   void process_block(BlockBegin* block);
3508   void process_xhandler(XHandler* xhandler, IntervalList* input_state);
3509   void process_successor(BlockBegin* block, IntervalList* input_state);
3510   void process_operations(LIR_List* ops, IntervalList* input_state);
3511 
3512  public:
3513   RegisterVerifier(LinearScan* allocator)
3514     : _allocator(allocator)
3515     , _work_list(16)
3516     , _saved_states(BlockBegin::number_of_blocks(), BlockBegin::number_of_blocks(), NULL)
3517   { }
3518 
3519   void verify(BlockBegin* start);
3520 };
3521 
3522 
3523 // entry function from LinearScan that starts the verification
3524 void LinearScan::verify_registers() {
3525   RegisterVerifier verifier(this);
3526   verifier.verify(block_at(0));
3527 }
3528 
3529 
3530 void RegisterVerifier::verify(BlockBegin* start) {
3531   // setup input registers (method arguments) for first block
3532   int input_state_len = state_size();
3533   IntervalList* input_state = new IntervalList(input_state_len, input_state_len, NULL);
3534   CallingConvention* args = compilation()->frame_map()->incoming_arguments();
3535   for (int n = 0; n < args->length(); n++) {
3536     LIR_Opr opr = args->at(n);
3537     if (opr->is_register()) {
3538       Interval* interval = interval_at(reg_num(opr));
3539 
3540       if (interval->assigned_reg() < state_size()) {
3541         input_state->at_put(interval->assigned_reg(), interval);
3542       }
3543       if (interval->assigned_regHi() != LinearScan::any_reg && interval->assigned_regHi() < state_size()) {
3544         input_state->at_put(interval->assigned_regHi(), interval);
3545       }
3546     }
3547   }
3548 
3549   set_state_for_block(start, input_state);
3550   add_to_work_list(start);
3551 
3552   // main loop for verification
3553   do {
3554     BlockBegin* block = _work_list.at(0);
3555     _work_list.remove_at(0);
3556 
3557     process_block(block);
3558   } while (!_work_list.is_empty());
3559 }
3560 
3561 void RegisterVerifier::process_block(BlockBegin* block) {
3562   TRACE_LINEAR_SCAN(2, tty->cr(); tty->print_cr("process_block B%d", block->block_id()));
3563 
3564   // must copy state because it is modified
3565   IntervalList* input_state = copy(state_for_block(block));
3566 
3567   if (TraceLinearScanLevel >= 4) {
3568     tty->print_cr("Input-State of intervals:");
3569     tty->print("    ");
3570     for (int i = 0; i < state_size(); i++) {
3571       if (input_state->at(i) != NULL) {
3572         tty->print(" %4d", input_state->at(i)->reg_num());
3573       } else {
3574         tty->print("   __");
3575       }
3576     }
3577     tty->cr();
3578     tty->cr();
3579   }
3580 
3581   // process all operations of the block
3582   process_operations(block->lir(), input_state);
3583 
3584   // iterate all successors
3585   for (int i = 0; i < block->number_of_sux(); i++) {
3586     process_successor(block->sux_at(i), input_state);
3587   }
3588 }
3589 
3590 void RegisterVerifier::process_xhandler(XHandler* xhandler, IntervalList* input_state) {
3591   TRACE_LINEAR_SCAN(2, tty->print_cr("process_xhandler B%d", xhandler->entry_block()->block_id()));
3592 
3593   // must copy state because it is modified
3594   input_state = copy(input_state);
3595 
3596   if (xhandler->entry_code() != NULL) {
3597     process_operations(xhandler->entry_code(), input_state);
3598   }
3599   process_successor(xhandler->entry_block(), input_state);
3600 }
3601 
3602 void RegisterVerifier::process_successor(BlockBegin* block, IntervalList* input_state) {
3603   IntervalList* saved_state = state_for_block(block);
3604 
3605   if (saved_state != NULL) {
3606     // this block was already processed before.
3607     // check if new input_state is consistent with saved_state
3608 
3609     bool saved_state_correct = true;
3610     for (int i = 0; i < state_size(); i++) {
3611       if (input_state->at(i) != saved_state->at(i)) {
3612         // current input_state and previous saved_state assume a different
3613         // interval in this register -> assume that this register is invalid
3614         if (saved_state->at(i) != NULL) {
3615           // invalidate old calculation only if it assumed that
3616           // register was valid. when the register was already invalid,
3617           // then the old calculation was correct.
3618           saved_state_correct = false;
3619           saved_state->at_put(i, NULL);
3620 
3621           TRACE_LINEAR_SCAN(4, tty->print_cr("process_successor B%d: invalidating slot %d", block->block_id(), i));
3622         }
3623       }
3624     }
3625 
3626     if (saved_state_correct) {
3627       // already processed block with correct input_state
3628       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: previous visit already correct", block->block_id()));
3629     } else {
3630       // must re-visit this block
3631       TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: must re-visit because input state changed", block->block_id()));
3632       add_to_work_list(block);
3633     }
3634 
3635   } else {
3636     // block was not processed before, so set initial input_state
3637     TRACE_LINEAR_SCAN(2, tty->print_cr("process_successor B%d: initial visit", block->block_id()));
3638 
3639     set_state_for_block(block, copy(input_state));
3640     add_to_work_list(block);
3641   }
3642 }
3643 
3644 
3645 IntervalList* RegisterVerifier::copy(IntervalList* input_state) {
3646   IntervalList* copy_state = new IntervalList(input_state->length());
3647   copy_state->appendAll(input_state);
3648   return copy_state;
3649 }
3650 
3651 void RegisterVerifier::state_put(IntervalList* input_state, int reg, Interval* interval) {
3652   if (reg != LinearScan::any_reg && reg < state_size()) {
3653     if (interval != NULL) {
3654       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = %d", reg, interval->reg_num()));
3655     } else if (input_state->at(reg) != NULL) {
3656       TRACE_LINEAR_SCAN(4, tty->print_cr("        reg[%d] = NULL", reg));
3657     }
3658 
3659     input_state->at_put(reg, interval);
3660   }
3661 }
3662 
3663 bool RegisterVerifier::check_state(IntervalList* input_state, int reg, Interval* interval) {
3664   if (reg != LinearScan::any_reg && reg < state_size()) {
3665     if (input_state->at(reg) != interval) {
3666       tty->print_cr("!! Error in register allocation: register %d does not contain interval %d", reg, interval->reg_num());
3667       return true;
3668     }
3669   }
3670   return false;
3671 }
3672 
3673 void RegisterVerifier::process_operations(LIR_List* ops, IntervalList* input_state) {
3674   // visit all instructions of the block
3675   LIR_OpVisitState visitor;
3676   bool has_error = false;
3677 
3678   for (int i = 0; i < ops->length(); i++) {
3679     LIR_Op* op = ops->at(i);
3680     visitor.visit(op);
3681 
3682     TRACE_LINEAR_SCAN(4, op->print_on(tty));
3683 
3684     // check if input operands are correct
3685     int j;
3686     int n = visitor.opr_count(LIR_OpVisitState::inputMode);
3687     for (j = 0; j < n; j++) {
3688       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::inputMode, j);
3689       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3690         Interval* interval = interval_at(reg_num(opr));
3691         if (op->id() != -1) {
3692           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::inputMode);
3693         }
3694 
3695         has_error |= check_state(input_state, interval->assigned_reg(),   interval->split_parent());
3696         has_error |= check_state(input_state, interval->assigned_regHi(), interval->split_parent());
3697 
3698         // When an operand is marked with is_last_use, then the fpu stack allocator
3699         // removes the register from the fpu stack -> the register contains no value
3700         if (opr->is_last_use()) {
3701           state_put(input_state, interval->assigned_reg(),   NULL);
3702           state_put(input_state, interval->assigned_regHi(), NULL);
3703         }
3704       }
3705     }
3706 
3707     // invalidate all caller save registers at calls
3708     if (visitor.has_call()) {
3709       for (j = 0; j < FrameMap::nof_caller_save_cpu_regs(); j++) {
3710         state_put(input_state, reg_num(FrameMap::caller_save_cpu_reg_at(j)), NULL);
3711       }
3712       for (j = 0; j < FrameMap::nof_caller_save_fpu_regs; j++) {
3713         state_put(input_state, reg_num(FrameMap::caller_save_fpu_reg_at(j)), NULL);
3714       }
3715 
3716 #ifdef X86
3717       int num_caller_save_xmm_regs = FrameMap::get_num_caller_save_xmms();
3718       for (j = 0; j < num_caller_save_xmm_regs; j++) {
3719         state_put(input_state, reg_num(FrameMap::caller_save_xmm_reg_at(j)), NULL);
3720       }
3721 #endif
3722     }
3723 
3724     // process xhandler before output and temp operands
3725     XHandlers* xhandlers = visitor.all_xhandler();
3726     n = xhandlers->length();
3727     for (int k = 0; k < n; k++) {
3728       process_xhandler(xhandlers->handler_at(k), input_state);
3729     }
3730 
3731     // set temp operands (some operations use temp operands also as output operands, so can't set them NULL)
3732     n = visitor.opr_count(LIR_OpVisitState::tempMode);
3733     for (j = 0; j < n; j++) {
3734       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::tempMode, j);
3735       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3736         Interval* interval = interval_at(reg_num(opr));
3737         if (op->id() != -1) {
3738           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::tempMode);
3739         }
3740 
3741         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3742         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3743       }
3744     }
3745 
3746     // set output operands
3747     n = visitor.opr_count(LIR_OpVisitState::outputMode);
3748     for (j = 0; j < n; j++) {
3749       LIR_Opr opr = visitor.opr_at(LIR_OpVisitState::outputMode, j);
3750       if (opr->is_register() && LinearScan::is_processed_reg_num(reg_num(opr))) {
3751         Interval* interval = interval_at(reg_num(opr));
3752         if (op->id() != -1) {
3753           interval = interval->split_child_at_op_id(op->id(), LIR_OpVisitState::outputMode);
3754         }
3755 
3756         state_put(input_state, interval->assigned_reg(),   interval->split_parent());
3757         state_put(input_state, interval->assigned_regHi(), interval->split_parent());
3758       }
3759     }
3760   }
3761   assert(has_error == false, "Error in register allocation");
3762 }
3763 
3764 #endif // ASSERT
3765 
3766 
3767 
3768 // **** Implementation of MoveResolver ******************************
3769 
3770 MoveResolver::MoveResolver(LinearScan* allocator) :
3771   _allocator(allocator),
3772   _insert_list(NULL),
3773   _insert_idx(-1),
3774   _insertion_buffer(),
3775   _mapping_from(8),
3776   _mapping_from_opr(8),
3777   _mapping_to(8),
3778   _multiple_reads_allowed(false)
3779 {
3780   for (int i = 0; i < LinearScan::nof_regs; i++) {
3781     _register_blocked[i] = 0;
3782   }
3783   DEBUG_ONLY(check_empty());
3784 }
3785 
3786 
3787 #ifdef ASSERT
3788 
3789 void MoveResolver::check_empty() {
3790   assert(_mapping_from.length() == 0 && _mapping_from_opr.length() == 0 && _mapping_to.length() == 0, "list must be empty before and after processing");
3791   for (int i = 0; i < LinearScan::nof_regs; i++) {
3792     assert(register_blocked(i) == 0, "register map must be empty before and after processing");
3793   }
3794   assert(_multiple_reads_allowed == false, "must have default value");
3795 }
3796 
3797 void MoveResolver::verify_before_resolve() {
3798   assert(_mapping_from.length() == _mapping_from_opr.length(), "length must be equal");
3799   assert(_mapping_from.length() == _mapping_to.length(), "length must be equal");
3800   assert(_insert_list != NULL && _insert_idx != -1, "insert position not set");
3801 
3802   int i, j;
3803   if (!_multiple_reads_allowed) {
3804     for (i = 0; i < _mapping_from.length(); i++) {
3805       for (j = i + 1; j < _mapping_from.length(); j++) {
3806         assert(_mapping_from.at(i) == NULL || _mapping_from.at(i) != _mapping_from.at(j), "cannot read from same interval twice");
3807       }
3808     }
3809   }
3810 
3811   for (i = 0; i < _mapping_to.length(); i++) {
3812     for (j = i + 1; j < _mapping_to.length(); j++) {
3813       assert(_mapping_to.at(i) != _mapping_to.at(j), "cannot write to same interval twice");
3814     }
3815   }
3816 
3817 
3818   ResourceBitMap used_regs(LinearScan::nof_regs + allocator()->frame_map()->argcount() + allocator()->max_spills());
3819   if (!_multiple_reads_allowed) {
3820     for (i = 0; i < _mapping_from.length(); i++) {
3821       Interval* it = _mapping_from.at(i);
3822       if (it != NULL) {
3823         assert(!used_regs.at(it->assigned_reg()), "cannot read from same register twice");
3824         used_regs.set_bit(it->assigned_reg());
3825 
3826         if (it->assigned_regHi() != LinearScan::any_reg) {
3827           assert(!used_regs.at(it->assigned_regHi()), "cannot read from same register twice");
3828           used_regs.set_bit(it->assigned_regHi());
3829         }
3830       }
3831     }
3832   }
3833 
3834   used_regs.clear();
3835   for (i = 0; i < _mapping_to.length(); i++) {
3836     Interval* it = _mapping_to.at(i);
3837     assert(!used_regs.at(it->assigned_reg()), "cannot write to same register twice");
3838     used_regs.set_bit(it->assigned_reg());
3839 
3840     if (it->assigned_regHi() != LinearScan::any_reg) {
3841       assert(!used_regs.at(it->assigned_regHi()), "cannot write to same register twice");
3842       used_regs.set_bit(it->assigned_regHi());
3843     }
3844   }
3845 
3846   used_regs.clear();
3847   for (i = 0; i < _mapping_from.length(); i++) {
3848     Interval* it = _mapping_from.at(i);
3849     if (it != NULL && it->assigned_reg() >= LinearScan::nof_regs) {
3850       used_regs.set_bit(it->assigned_reg());
3851     }
3852   }
3853   for (i = 0; i < _mapping_to.length(); i++) {
3854     Interval* it = _mapping_to.at(i);
3855     assert(!used_regs.at(it->assigned_reg()) || it->assigned_reg() == _mapping_from.at(i)->assigned_reg(), "stack slots used in _mapping_from must be disjoint to _mapping_to");
3856   }
3857 }
3858 
3859 #endif // ASSERT
3860 
3861 
3862 // mark assigned_reg and assigned_regHi of the interval as blocked
3863 void MoveResolver::block_registers(Interval* it) {
3864   int reg = it->assigned_reg();
3865   if (reg < LinearScan::nof_regs) {
3866     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3867     set_register_blocked(reg, 1);
3868   }
3869   reg = it->assigned_regHi();
3870   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3871     assert(_multiple_reads_allowed || register_blocked(reg) == 0, "register already marked as used");
3872     set_register_blocked(reg, 1);
3873   }
3874 }
3875 
3876 // mark assigned_reg and assigned_regHi of the interval as unblocked
3877 void MoveResolver::unblock_registers(Interval* it) {
3878   int reg = it->assigned_reg();
3879   if (reg < LinearScan::nof_regs) {
3880     assert(register_blocked(reg) > 0, "register already marked as unused");
3881     set_register_blocked(reg, -1);
3882   }
3883   reg = it->assigned_regHi();
3884   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3885     assert(register_blocked(reg) > 0, "register already marked as unused");
3886     set_register_blocked(reg, -1);
3887   }
3888 }
3889 
3890 // check if assigned_reg and assigned_regHi of the to-interval are not blocked (or only blocked by from)
3891 bool MoveResolver::save_to_process_move(Interval* from, Interval* to) {
3892   int from_reg = -1;
3893   int from_regHi = -1;
3894   if (from != NULL) {
3895     from_reg = from->assigned_reg();
3896     from_regHi = from->assigned_regHi();
3897   }
3898 
3899   int reg = to->assigned_reg();
3900   if (reg < LinearScan::nof_regs) {
3901     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3902       return false;
3903     }
3904   }
3905   reg = to->assigned_regHi();
3906   if (reg != LinearScan::any_reg && reg < LinearScan::nof_regs) {
3907     if (register_blocked(reg) > 1 || (register_blocked(reg) == 1 && reg != from_reg && reg != from_regHi)) {
3908       return false;
3909     }
3910   }
3911 
3912   return true;
3913 }
3914 
3915 
3916 void MoveResolver::create_insertion_buffer(LIR_List* list) {
3917   assert(!_insertion_buffer.initialized(), "overwriting existing buffer");
3918   _insertion_buffer.init(list);
3919 }
3920 
3921 void MoveResolver::append_insertion_buffer() {
3922   if (_insertion_buffer.initialized()) {
3923     _insertion_buffer.lir_list()->append(&_insertion_buffer);
3924   }
3925   assert(!_insertion_buffer.initialized(), "must be uninitialized now");
3926 
3927   _insert_list = NULL;
3928   _insert_idx = -1;
3929 }
3930 
3931 void MoveResolver::insert_move(Interval* from_interval, Interval* to_interval) {
3932   assert(from_interval->reg_num() != to_interval->reg_num(), "from and to interval equal");
3933   assert(from_interval->type() == to_interval->type(), "move between different types");
3934   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3935   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3936 
3937   LIR_Opr from_opr = get_virtual_register(from_interval);
3938   LIR_Opr to_opr = get_virtual_register(to_interval);
3939 
3940   if (!_multiple_reads_allowed) {
3941     // the last_use flag is an optimization for FPU stack allocation. When the same
3942     // input interval is used in more than one move, then it is too difficult to determine
3943     // if this move is really the last use.
3944     from_opr = from_opr->make_last_use();
3945   }
3946   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3947 
3948   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: inserted move from register %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3949 }
3950 
3951 void MoveResolver::insert_move(LIR_Opr from_opr, Interval* to_interval) {
3952   assert(from_opr->type() == to_interval->type(), "move between different types");
3953   assert(_insert_list != NULL && _insert_idx != -1, "must setup insert position first");
3954   assert(_insertion_buffer.lir_list() == _insert_list, "wrong insertion buffer");
3955 
3956   LIR_Opr to_opr = get_virtual_register(to_interval);
3957   _insertion_buffer.move(_insert_idx, from_opr, to_opr);
3958 
3959   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: inserted move from constant "); from_opr->print(); tty->print_cr("  to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
3960 }
3961 
3962 LIR_Opr MoveResolver::get_virtual_register(Interval* interval) {
3963   // Add a little fudge factor for the bailout since the bailout is only checked periodically. This allows us to hand out
3964   // a few extra registers before we really run out which helps to avoid to trip over assertions.
3965   int reg_num = interval->reg_num();
3966   if (reg_num + 20 >= LIR_Opr::vreg_max) {
3967     _allocator->bailout("out of virtual registers in linear scan");
3968     if (reg_num + 2 >= LIR_Opr::vreg_max) {
3969       // Wrap it around and continue until bailout really happens to avoid hitting assertions.
3970       reg_num = LIR_Opr::vreg_base;
3971     }
3972   }
3973   LIR_Opr vreg = LIR_OprFact::virtual_register(reg_num, interval->type());
3974   assert(vreg != LIR_OprFact::illegal(), "ran out of virtual registers");
3975   return vreg;
3976 }
3977 
3978 void MoveResolver::resolve_mappings() {
3979   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: resolving mappings for Block B%d, index %d", _insert_list->block() != NULL ? _insert_list->block()->block_id() : -1, _insert_idx));
3980   DEBUG_ONLY(verify_before_resolve());
3981 
3982   // Block all registers that are used as input operands of a move.
3983   // When a register is blocked, no move to this register is emitted.
3984   // This is necessary for detecting cycles in moves.
3985   int i;
3986   for (i = _mapping_from.length() - 1; i >= 0; i--) {
3987     Interval* from_interval = _mapping_from.at(i);
3988     if (from_interval != NULL) {
3989       block_registers(from_interval);
3990     }
3991   }
3992 
3993   int spill_candidate = -1;
3994   while (_mapping_from.length() > 0) {
3995     bool processed_interval = false;
3996 
3997     for (i = _mapping_from.length() - 1; i >= 0; i--) {
3998       Interval* from_interval = _mapping_from.at(i);
3999       Interval* to_interval = _mapping_to.at(i);
4000 
4001       if (save_to_process_move(from_interval, to_interval)) {
4002         // this interval can be processed because target is free
4003         if (from_interval != NULL) {
4004           insert_move(from_interval, to_interval);
4005           unblock_registers(from_interval);
4006         } else {
4007           insert_move(_mapping_from_opr.at(i), to_interval);
4008         }
4009         _mapping_from.remove_at(i);
4010         _mapping_from_opr.remove_at(i);
4011         _mapping_to.remove_at(i);
4012 
4013         processed_interval = true;
4014       } else if (from_interval != NULL && from_interval->assigned_reg() < LinearScan::nof_regs) {
4015         // this interval cannot be processed now because target is not free
4016         // it starts in a register, so it is a possible candidate for spilling
4017         spill_candidate = i;
4018       }
4019     }
4020 
4021     if (!processed_interval) {
4022       // no move could be processed because there is a cycle in the move list
4023       // (e.g. r1 -> r2, r2 -> r1), so one interval must be spilled to memory
4024       guarantee(spill_candidate != -1, "no interval in register for spilling found");
4025 
4026       // create a new spill interval and assign a stack slot to it
4027       Interval* from_interval = _mapping_from.at(spill_candidate);
4028       Interval* spill_interval = new Interval(-1);
4029       spill_interval->set_type(from_interval->type());
4030 
4031       // add a dummy range because real position is difficult to calculate
4032       // Note: this range is a special case when the integrity of the allocation is checked
4033       spill_interval->add_range(1, 2);
4034 
4035       //       do not allocate a new spill slot for temporary interval, but
4036       //       use spill slot assigned to from_interval. Otherwise moves from
4037       //       one stack slot to another can happen (not allowed by LIR_Assembler
4038       int spill_slot = from_interval->canonical_spill_slot();
4039       if (spill_slot < 0) {
4040         spill_slot = allocator()->allocate_spill_slot(type2spill_size[spill_interval->type()] == 2);
4041         from_interval->set_canonical_spill_slot(spill_slot);
4042       }
4043       spill_interval->assign_reg(spill_slot);
4044       allocator()->append_interval(spill_interval);
4045 
4046       TRACE_LINEAR_SCAN(4, tty->print_cr("created new Interval %d for spilling", spill_interval->reg_num()));
4047 
4048       // insert a move from register to stack and update the mapping
4049       insert_move(from_interval, spill_interval);
4050       _mapping_from.at_put(spill_candidate, spill_interval);
4051       unblock_registers(from_interval);
4052     }
4053   }
4054 
4055   // reset to default value
4056   _multiple_reads_allowed = false;
4057 
4058   // check that all intervals have been processed
4059   DEBUG_ONLY(check_empty());
4060 }
4061 
4062 
4063 void MoveResolver::set_insert_position(LIR_List* insert_list, int insert_idx) {
4064   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: setting insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4065   assert(_insert_list == NULL && _insert_idx == -1, "use move_insert_position instead of set_insert_position when data already set");
4066 
4067   create_insertion_buffer(insert_list);
4068   _insert_list = insert_list;
4069   _insert_idx = insert_idx;
4070 }
4071 
4072 void MoveResolver::move_insert_position(LIR_List* insert_list, int insert_idx) {
4073   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: moving insert position to Block B%d, index %d", insert_list->block() != NULL ? insert_list->block()->block_id() : -1, insert_idx));
4074 
4075   if (_insert_list != NULL && (insert_list != _insert_list || insert_idx != _insert_idx)) {
4076     // insert position changed -> resolve current mappings
4077     resolve_mappings();
4078   }
4079 
4080   if (insert_list != _insert_list) {
4081     // block changed -> append insertion_buffer because it is
4082     // bound to a specific block and create a new insertion_buffer
4083     append_insertion_buffer();
4084     create_insertion_buffer(insert_list);
4085   }
4086 
4087   _insert_list = insert_list;
4088   _insert_idx = insert_idx;
4089 }
4090 
4091 void MoveResolver::add_mapping(Interval* from_interval, Interval* to_interval) {
4092   TRACE_LINEAR_SCAN(4, tty->print_cr("MoveResolver: adding mapping from %d (%d, %d) to %d (%d, %d)", from_interval->reg_num(), from_interval->assigned_reg(), from_interval->assigned_regHi(), to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4093 
4094   _mapping_from.append(from_interval);
4095   _mapping_from_opr.append(LIR_OprFact::illegalOpr);
4096   _mapping_to.append(to_interval);
4097 }
4098 
4099 
4100 void MoveResolver::add_mapping(LIR_Opr from_opr, Interval* to_interval) {
4101   TRACE_LINEAR_SCAN(4, tty->print("MoveResolver: adding mapping from "); from_opr->print(); tty->print_cr(" to %d (%d, %d)", to_interval->reg_num(), to_interval->assigned_reg(), to_interval->assigned_regHi()));
4102   assert(from_opr->is_constant(), "only for constants");
4103 
4104   _mapping_from.append(NULL);
4105   _mapping_from_opr.append(from_opr);
4106   _mapping_to.append(to_interval);
4107 }
4108 
4109 void MoveResolver::resolve_and_append_moves() {
4110   if (has_mappings()) {
4111     resolve_mappings();
4112   }
4113   append_insertion_buffer();
4114 }
4115 
4116 
4117 
4118 // **** Implementation of Range *************************************
4119 
4120 Range::Range(int from, int to, Range* next) :
4121   _from(from),
4122   _to(to),
4123   _next(next)
4124 {
4125 }
4126 
4127 // initialize sentinel
4128 Range* Range::_end = NULL;
4129 void Range::initialize(Arena* arena) {
4130   _end = new (arena) Range(max_jint, max_jint, NULL);
4131 }
4132 
4133 int Range::intersects_at(Range* r2) const {
4134   const Range* r1 = this;
4135 
4136   assert(r1 != NULL && r2 != NULL, "null ranges not allowed");
4137   assert(r1 != _end && r2 != _end, "empty ranges not allowed");
4138 
4139   do {
4140     if (r1->from() < r2->from()) {
4141       if (r1->to() <= r2->from()) {
4142         r1 = r1->next(); if (r1 == _end) return -1;
4143       } else {
4144         return r2->from();
4145       }
4146     } else if (r2->from() < r1->from()) {
4147       if (r2->to() <= r1->from()) {
4148         r2 = r2->next(); if (r2 == _end) return -1;
4149       } else {
4150         return r1->from();
4151       }
4152     } else { // r1->from() == r2->from()
4153       if (r1->from() == r1->to()) {
4154         r1 = r1->next(); if (r1 == _end) return -1;
4155       } else if (r2->from() == r2->to()) {
4156         r2 = r2->next(); if (r2 == _end) return -1;
4157       } else {
4158         return r1->from();
4159       }
4160     }
4161   } while (true);
4162 }
4163 
4164 #ifndef PRODUCT
4165 void Range::print(outputStream* out) const {
4166   out->print("[%d, %d[ ", _from, _to);
4167 }
4168 #endif
4169 
4170 
4171 
4172 // **** Implementation of Interval **********************************
4173 
4174 // initialize sentinel
4175 Interval* Interval::_end = NULL;
4176 void Interval::initialize(Arena* arena) {
4177   Range::initialize(arena);
4178   _end = new (arena) Interval(-1);
4179 }
4180 
4181 Interval::Interval(int reg_num) :
4182   _reg_num(reg_num),
4183   _type(T_ILLEGAL),
4184   _first(Range::end()),
4185   _use_pos_and_kinds(12),
4186   _current(Range::end()),
4187   _next(_end),
4188   _state(invalidState),
4189   _assigned_reg(LinearScan::any_reg),
4190   _assigned_regHi(LinearScan::any_reg),
4191   _cached_to(-1),
4192   _cached_opr(LIR_OprFact::illegalOpr),
4193   _cached_vm_reg(VMRegImpl::Bad()),
4194   _split_children(NULL),
4195   _canonical_spill_slot(-1),
4196   _insert_move_when_activated(false),
4197   _spill_state(noDefinitionFound),
4198   _spill_definition_pos(-1),
4199   _register_hint(NULL)
4200 {
4201   _split_parent = this;
4202   _current_split_child = this;
4203 }
4204 
4205 int Interval::calc_to() {
4206   assert(_first != Range::end(), "interval has no range");
4207 
4208   Range* r = _first;
4209   while (r->next() != Range::end()) {
4210     r = r->next();
4211   }
4212   return r->to();
4213 }
4214 
4215 
4216 #ifdef ASSERT
4217 // consistency check of split-children
4218 void Interval::check_split_children() {
4219   if (_split_children != NULL && _split_children->length() > 0) {
4220     assert(is_split_parent(), "only split parents can have children");
4221 
4222     for (int i = 0; i < _split_children->length(); i++) {
4223       Interval* i1 = _split_children->at(i);
4224 
4225       assert(i1->split_parent() == this, "not a split child of this interval");
4226       assert(i1->type() == type(), "must be equal for all split children");
4227       assert(i1->canonical_spill_slot() == canonical_spill_slot(), "must be equal for all split children");
4228 
4229       for (int j = i + 1; j < _split_children->length(); j++) {
4230         Interval* i2 = _split_children->at(j);
4231 
4232         assert(i1->reg_num() != i2->reg_num(), "same register number");
4233 
4234         if (i1->from() < i2->from()) {
4235           assert(i1->to() <= i2->from() && i1->to() < i2->to(), "intervals overlapping");
4236         } else {
4237           assert(i2->from() < i1->from(), "intervals start at same op_id");
4238           assert(i2->to() <= i1->from() && i2->to() < i1->to(), "intervals overlapping");
4239         }
4240       }
4241     }
4242   }
4243 }
4244 #endif // ASSERT
4245 
4246 Interval* Interval::register_hint(bool search_split_child) const {
4247   if (!search_split_child) {
4248     return _register_hint;
4249   }
4250 
4251   if (_register_hint != NULL) {
4252     assert(_register_hint->is_split_parent(), "only split parents are valid hint registers");
4253 
4254     if (_register_hint->assigned_reg() >= 0 && _register_hint->assigned_reg() < LinearScan::nof_regs) {
4255       return _register_hint;
4256 
4257     } else if (_register_hint->_split_children != NULL && _register_hint->_split_children->length() > 0) {
4258       // search the first split child that has a register assigned
4259       int len = _register_hint->_split_children->length();
4260       for (int i = 0; i < len; i++) {
4261         Interval* cur = _register_hint->_split_children->at(i);
4262 
4263         if (cur->assigned_reg() >= 0 && cur->assigned_reg() < LinearScan::nof_regs) {
4264           return cur;
4265         }
4266       }
4267     }
4268   }
4269 
4270   // no hint interval found that has a register assigned
4271   return NULL;
4272 }
4273 
4274 
4275 Interval* Interval::split_child_at_op_id(int op_id, LIR_OpVisitState::OprMode mode) {
4276   assert(is_split_parent(), "can only be called for split parents");
4277   assert(op_id >= 0, "invalid op_id (method can not be called for spill moves)");
4278 
4279   Interval* result;
4280   if (_split_children == NULL || _split_children->length() == 0) {
4281     result = this;
4282   } else {
4283     result = NULL;
4284     int len = _split_children->length();
4285 
4286     // in outputMode, the end of the interval (op_id == cur->to()) is not valid
4287     int to_offset = (mode == LIR_OpVisitState::outputMode ? 0 : 1);
4288 
4289     int i;
4290     for (i = 0; i < len; i++) {
4291       Interval* cur = _split_children->at(i);
4292       if (cur->from() <= op_id && op_id < cur->to() + to_offset) {
4293         if (i > 0) {
4294           // exchange current split child to start of list (faster access for next call)
4295           _split_children->at_put(i, _split_children->at(0));
4296           _split_children->at_put(0, cur);
4297         }
4298 
4299         // interval found
4300         result = cur;
4301         break;
4302       }
4303     }
4304 
4305 #ifdef ASSERT
4306     for (i = 0; i < len; i++) {
4307       Interval* tmp = _split_children->at(i);
4308       if (tmp != result && tmp->from() <= op_id && op_id < tmp->to() + to_offset) {
4309         tty->print_cr("two valid result intervals found for op_id %d: %d and %d", op_id, result->reg_num(), tmp->reg_num());
4310         result->print();
4311         tmp->print();
4312         assert(false, "two valid result intervals found");
4313       }
4314     }
4315 #endif
4316   }
4317 
4318   assert(result != NULL, "no matching interval found");
4319   assert(result->covers(op_id, mode), "op_id not covered by interval");
4320 
4321   return result;
4322 }
4323 
4324 
4325 // returns the last split child that ends before the given op_id
4326 Interval* Interval::split_child_before_op_id(int op_id) {
4327   assert(op_id >= 0, "invalid op_id");
4328 
4329   Interval* parent = split_parent();
4330   Interval* result = NULL;
4331 
4332   assert(parent->_split_children != NULL, "no split children available");
4333   int len = parent->_split_children->length();
4334   assert(len > 0, "no split children available");
4335 
4336   for (int i = len - 1; i >= 0; i--) {
4337     Interval* cur = parent->_split_children->at(i);
4338     if (cur->to() <= op_id && (result == NULL || result->to() < cur->to())) {
4339       result = cur;
4340     }
4341   }
4342 
4343   assert(result != NULL, "no split child found");
4344   return result;
4345 }
4346 
4347 
4348 // Note: use positions are sorted descending -> first use has highest index
4349 int Interval::first_usage(IntervalUseKind min_use_kind) const {
4350   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4351 
4352   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4353     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4354       return _use_pos_and_kinds.at(i);
4355     }
4356   }
4357   return max_jint;
4358 }
4359 
4360 int Interval::next_usage(IntervalUseKind min_use_kind, int from) const {
4361   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4362 
4363   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4364     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4365       return _use_pos_and_kinds.at(i);
4366     }
4367   }
4368   return max_jint;
4369 }
4370 
4371 int Interval::next_usage_exact(IntervalUseKind exact_use_kind, int from) const {
4372   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4373 
4374   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4375     if (_use_pos_and_kinds.at(i) >= from && _use_pos_and_kinds.at(i + 1) == exact_use_kind) {
4376       return _use_pos_and_kinds.at(i);
4377     }
4378   }
4379   return max_jint;
4380 }
4381 
4382 int Interval::previous_usage(IntervalUseKind min_use_kind, int from) const {
4383   assert(LinearScan::is_virtual_interval(this), "cannot access use positions for fixed intervals");
4384 
4385   int prev = 0;
4386   for (int i = _use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4387     if (_use_pos_and_kinds.at(i) > from) {
4388       return prev;
4389     }
4390     if (_use_pos_and_kinds.at(i + 1) >= min_use_kind) {
4391       prev = _use_pos_and_kinds.at(i);
4392     }
4393   }
4394   return prev;
4395 }
4396 
4397 void Interval::add_use_pos(int pos, IntervalUseKind use_kind) {
4398   assert(covers(pos, LIR_OpVisitState::inputMode), "use position not covered by live range");
4399 
4400   // do not add use positions for precolored intervals because
4401   // they are never used
4402   if (use_kind != noUse && reg_num() >= LIR_Opr::vreg_base) {
4403 #ifdef ASSERT
4404     assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4405     for (int i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4406       assert(pos <= _use_pos_and_kinds.at(i), "already added a use-position with lower position");
4407       assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4408       if (i > 0) {
4409         assert(_use_pos_and_kinds.at(i) < _use_pos_and_kinds.at(i - 2), "not sorted descending");
4410       }
4411     }
4412 #endif
4413 
4414     // Note: add_use is called in descending order, so list gets sorted
4415     //       automatically by just appending new use positions
4416     int len = _use_pos_and_kinds.length();
4417     if (len == 0 || _use_pos_and_kinds.at(len - 2) > pos) {
4418       _use_pos_and_kinds.append(pos);
4419       _use_pos_and_kinds.append(use_kind);
4420     } else if (_use_pos_and_kinds.at(len - 1) < use_kind) {
4421       assert(_use_pos_and_kinds.at(len - 2) == pos, "list not sorted correctly");
4422       _use_pos_and_kinds.at_put(len - 1, use_kind);
4423     }
4424   }
4425 }
4426 
4427 void Interval::add_range(int from, int to) {
4428   assert(from < to, "invalid range");
4429   assert(first() == Range::end() || to < first()->next()->from(), "not inserting at begin of interval");
4430   assert(from <= first()->to(), "not inserting at begin of interval");
4431 
4432   if (first()->from() <= to) {
4433     // join intersecting ranges
4434     first()->set_from(MIN2(from, first()->from()));
4435     first()->set_to  (MAX2(to,   first()->to()));
4436   } else {
4437     // insert new range
4438     _first = new Range(from, to, first());
4439   }
4440 }
4441 
4442 Interval* Interval::new_split_child() {
4443   // allocate new interval
4444   Interval* result = new Interval(-1);
4445   result->set_type(type());
4446 
4447   Interval* parent = split_parent();
4448   result->_split_parent = parent;
4449   result->set_register_hint(parent);
4450 
4451   // insert new interval in children-list of parent
4452   if (parent->_split_children == NULL) {
4453     assert(is_split_parent(), "list must be initialized at first split");
4454 
4455     parent->_split_children = new IntervalList(4);
4456     parent->_split_children->append(this);
4457   }
4458   parent->_split_children->append(result);
4459 
4460   return result;
4461 }
4462 
4463 // split this interval at the specified position and return
4464 // the remainder as a new interval.
4465 //
4466 // when an interval is split, a bi-directional link is established between the original interval
4467 // (the split parent) and the intervals that are split off this interval (the split children)
4468 // When a split child is split again, the new created interval is also a direct child
4469 // of the original parent (there is no tree of split children stored, but a flat list)
4470 // All split children are spilled to the same stack slot (stored in _canonical_spill_slot)
4471 //
4472 // Note: The new interval has no valid reg_num
4473 Interval* Interval::split(int split_pos) {
4474   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4475 
4476   // allocate new interval
4477   Interval* result = new_split_child();
4478 
4479   // split the ranges
4480   Range* prev = NULL;
4481   Range* cur = _first;
4482   while (cur != Range::end() && cur->to() <= split_pos) {
4483     prev = cur;
4484     cur = cur->next();
4485   }
4486   assert(cur != Range::end(), "split interval after end of last range");
4487 
4488   if (cur->from() < split_pos) {
4489     result->_first = new Range(split_pos, cur->to(), cur->next());
4490     cur->set_to(split_pos);
4491     cur->set_next(Range::end());
4492 
4493   } else {
4494     assert(prev != NULL, "split before start of first range");
4495     result->_first = cur;
4496     prev->set_next(Range::end());
4497   }
4498   result->_current = result->_first;
4499   _cached_to = -1; // clear cached value
4500 
4501   // split list of use positions
4502   int total_len = _use_pos_and_kinds.length();
4503   int start_idx = total_len - 2;
4504   while (start_idx >= 0 && _use_pos_and_kinds.at(start_idx) < split_pos) {
4505     start_idx -= 2;
4506   }
4507 
4508   intStack new_use_pos_and_kinds(total_len - start_idx);
4509   int i;
4510   for (i = start_idx + 2; i < total_len; i++) {
4511     new_use_pos_and_kinds.append(_use_pos_and_kinds.at(i));
4512   }
4513 
4514   _use_pos_and_kinds.trunc_to(start_idx + 2);
4515   result->_use_pos_and_kinds = _use_pos_and_kinds;
4516   _use_pos_and_kinds = new_use_pos_and_kinds;
4517 
4518 #ifdef ASSERT
4519   assert(_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4520   assert(result->_use_pos_and_kinds.length() % 2 == 0, "must have use kind for each use pos");
4521   assert(_use_pos_and_kinds.length() + result->_use_pos_and_kinds.length() == total_len, "missed some entries");
4522 
4523   for (i = 0; i < _use_pos_and_kinds.length(); i += 2) {
4524     assert(_use_pos_and_kinds.at(i) < split_pos, "must be");
4525     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4526   }
4527   for (i = 0; i < result->_use_pos_and_kinds.length(); i += 2) {
4528     assert(result->_use_pos_and_kinds.at(i) >= split_pos, "must be");
4529     assert(result->_use_pos_and_kinds.at(i + 1) >= firstValidKind && result->_use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4530   }
4531 #endif
4532 
4533   return result;
4534 }
4535 
4536 // split this interval at the specified position and return
4537 // the head as a new interval (the original interval is the tail)
4538 //
4539 // Currently, only the first range can be split, and the new interval
4540 // must not have split positions
4541 Interval* Interval::split_from_start(int split_pos) {
4542   assert(LinearScan::is_virtual_interval(this), "cannot split fixed intervals");
4543   assert(split_pos > from() && split_pos < to(), "can only split inside interval");
4544   assert(split_pos > _first->from() && split_pos <= _first->to(), "can only split inside first range");
4545   assert(first_usage(noUse) > split_pos, "can not split when use positions are present");
4546 
4547   // allocate new interval
4548   Interval* result = new_split_child();
4549 
4550   // the new created interval has only one range (checked by assertion above),
4551   // so the splitting of the ranges is very simple
4552   result->add_range(_first->from(), split_pos);
4553 
4554   if (split_pos == _first->to()) {
4555     assert(_first->next() != Range::end(), "must not be at end");
4556     _first = _first->next();
4557   } else {
4558     _first->set_from(split_pos);
4559   }
4560 
4561   return result;
4562 }
4563 
4564 
4565 // returns true if the op_id is inside the interval
4566 bool Interval::covers(int op_id, LIR_OpVisitState::OprMode mode) const {
4567   Range* cur  = _first;
4568 
4569   while (cur != Range::end() && cur->to() < op_id) {
4570     cur = cur->next();
4571   }
4572   if (cur != Range::end()) {
4573     assert(cur->to() != cur->next()->from(), "ranges not separated");
4574 
4575     if (mode == LIR_OpVisitState::outputMode) {
4576       return cur->from() <= op_id && op_id < cur->to();
4577     } else {
4578       return cur->from() <= op_id && op_id <= cur->to();
4579     }
4580   }
4581   return false;
4582 }
4583 
4584 // returns true if the interval has any hole between hole_from and hole_to
4585 // (even if the hole has only the length 1)
4586 bool Interval::has_hole_between(int hole_from, int hole_to) {
4587   assert(hole_from < hole_to, "check");
4588   assert(from() <= hole_from && hole_to <= to(), "index out of interval");
4589 
4590   Range* cur  = _first;
4591   while (cur != Range::end()) {
4592     assert(cur->to() < cur->next()->from(), "no space between ranges");
4593 
4594     // hole-range starts before this range -> hole
4595     if (hole_from < cur->from()) {
4596       return true;
4597 
4598     // hole-range completely inside this range -> no hole
4599     } else if (hole_to <= cur->to()) {
4600       return false;
4601 
4602     // overlapping of hole-range with this range -> hole
4603     } else if (hole_from <= cur->to()) {
4604       return true;
4605     }
4606 
4607     cur = cur->next();
4608   }
4609 
4610   return false;
4611 }
4612 
4613 // Check if there is an intersection with any of the split children of 'interval'
4614 bool Interval::intersects_any_children_of(Interval* interval) const {
4615   if (interval->_split_children != NULL) {
4616     for (int i = 0; i < interval->_split_children->length(); i++) {
4617       if (intersects(interval->_split_children->at(i))) {
4618         return true;
4619       }
4620     }
4621   }
4622   return false;
4623 }
4624 
4625 
4626 #ifndef PRODUCT
4627 void Interval::print_on(outputStream* out, bool is_cfg_printer) const {
4628   const char* SpillState2Name[] = { "no definition", "no spill store", "one spill store", "store at definition", "start in memory", "no optimization" };
4629   const char* UseKind2Name[] = { "N", "L", "S", "M" };
4630 
4631   const char* type_name;
4632   if (reg_num() < LIR_Opr::vreg_base) {
4633     type_name = "fixed";
4634   } else {
4635     type_name = type2name(type());
4636   }
4637   out->print("%d %s ", reg_num(), type_name);
4638 
4639   if (is_cfg_printer) {
4640     // Special version for compatibility with C1 Visualizer.
4641     LIR_Opr opr = LinearScan::get_operand(reg_num());
4642     if (opr->is_valid()) {
4643       out->print("\"");
4644       opr->print(out);
4645       out->print("\" ");
4646     }
4647   } else {
4648     // Improved output for normal debugging.
4649     if (reg_num() < LIR_Opr::vreg_base) {
4650       LinearScan::print_reg_num(out, assigned_reg());
4651     } else if (assigned_reg() != -1 && (LinearScan::num_physical_regs(type()) == 1 || assigned_regHi() != -1)) {
4652       LinearScan::calc_operand_for_interval(this)->print(out);
4653     } else {
4654       // Virtual register that has no assigned register yet.
4655       out->print("[ANY]");
4656     }
4657     out->print(" ");
4658   }
4659   out->print("%d %d ", split_parent()->reg_num(), (register_hint(false) != NULL ? register_hint(false)->reg_num() : -1));
4660 
4661   // print ranges
4662   Range* cur = _first;
4663   while (cur != Range::end()) {
4664     cur->print(out);
4665     cur = cur->next();
4666     assert(cur != NULL, "range list not closed with range sentinel");
4667   }
4668 
4669   // print use positions
4670   int prev = 0;
4671   assert(_use_pos_and_kinds.length() % 2 == 0, "must be");
4672   for (int i =_use_pos_and_kinds.length() - 2; i >= 0; i -= 2) {
4673     assert(_use_pos_and_kinds.at(i + 1) >= firstValidKind && _use_pos_and_kinds.at(i + 1) <= lastValidKind, "invalid use kind");
4674     assert(prev < _use_pos_and_kinds.at(i), "use positions not sorted");
4675 
4676     out->print("%d %s ", _use_pos_and_kinds.at(i), UseKind2Name[_use_pos_and_kinds.at(i + 1)]);
4677     prev = _use_pos_and_kinds.at(i);
4678   }
4679 
4680   out->print(" \"%s\"", SpillState2Name[spill_state()]);
4681   out->cr();
4682 }
4683 
4684 void Interval::print_parent() const {
4685   if (_split_parent != this) {
4686     _split_parent->print_on(tty);
4687   } else {
4688     tty->print_cr("Parent: this");
4689   }
4690 }
4691 
4692 void Interval::print_children() const {
4693   if (_split_children == NULL) {
4694     tty->print_cr("Children: []");
4695   } else {
4696     tty->print_cr("Children:");
4697     for (int i = 0; i < _split_children->length(); i++) {
4698       tty->print("%d: ", i);
4699       _split_children->at(i)->print_on(tty);
4700     }
4701   }
4702 }
4703 #endif // NOT PRODUCT
4704 
4705 
4706 
4707 
4708 // **** Implementation of IntervalWalker ****************************
4709 
4710 IntervalWalker::IntervalWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4711  : _compilation(allocator->compilation())
4712  , _allocator(allocator)
4713 {
4714   _unhandled_first[fixedKind] = unhandled_fixed_first;
4715   _unhandled_first[anyKind]   = unhandled_any_first;
4716   _active_first[fixedKind]    = Interval::end();
4717   _inactive_first[fixedKind]  = Interval::end();
4718   _active_first[anyKind]      = Interval::end();
4719   _inactive_first[anyKind]    = Interval::end();
4720   _current_position = -1;
4721   _current = NULL;
4722   next_interval();
4723 }
4724 
4725 
4726 // append interval in order of current range from()
4727 void IntervalWalker::append_sorted(Interval** list, Interval* interval) {
4728   Interval* prev = NULL;
4729   Interval* cur  = *list;
4730   while (cur->current_from() < interval->current_from()) {
4731     prev = cur; cur = cur->next();
4732   }
4733   if (prev == NULL) {
4734     *list = interval;
4735   } else {
4736     prev->set_next(interval);
4737   }
4738   interval->set_next(cur);
4739 }
4740 
4741 void IntervalWalker::append_to_unhandled(Interval** list, Interval* interval) {
4742   assert(interval->from() >= current()->current_from(), "cannot append new interval before current walk position");
4743 
4744   Interval* prev = NULL;
4745   Interval* cur  = *list;
4746   while (cur->from() < interval->from() || (cur->from() == interval->from() && cur->first_usage(noUse) < interval->first_usage(noUse))) {
4747     prev = cur; cur = cur->next();
4748   }
4749   if (prev == NULL) {
4750     *list = interval;
4751   } else {
4752     prev->set_next(interval);
4753   }
4754   interval->set_next(cur);
4755 }
4756 
4757 
4758 inline bool IntervalWalker::remove_from_list(Interval** list, Interval* i) {
4759   while (*list != Interval::end() && *list != i) {
4760     list = (*list)->next_addr();
4761   }
4762   if (*list != Interval::end()) {
4763     assert(*list == i, "check");
4764     *list = (*list)->next();
4765     return true;
4766   } else {
4767     return false;
4768   }
4769 }
4770 
4771 void IntervalWalker::remove_from_list(Interval* i) {
4772   bool deleted;
4773 
4774   if (i->state() == activeState) {
4775     deleted = remove_from_list(active_first_addr(anyKind), i);
4776   } else {
4777     assert(i->state() == inactiveState, "invalid state");
4778     deleted = remove_from_list(inactive_first_addr(anyKind), i);
4779   }
4780 
4781   assert(deleted, "interval has not been found in list");
4782 }
4783 
4784 
4785 void IntervalWalker::walk_to(IntervalState state, int from) {
4786   assert (state == activeState || state == inactiveState, "wrong state");
4787   for_each_interval_kind(kind) {
4788     Interval** prev = state == activeState ? active_first_addr(kind) : inactive_first_addr(kind);
4789     Interval* next   = *prev;
4790     while (next->current_from() <= from) {
4791       Interval* cur = next;
4792       next = cur->next();
4793 
4794       bool range_has_changed = false;
4795       while (cur->current_to() <= from) {
4796         cur->next_range();
4797         range_has_changed = true;
4798       }
4799 
4800       // also handle move from inactive list to active list
4801       range_has_changed = range_has_changed || (state == inactiveState && cur->current_from() <= from);
4802 
4803       if (range_has_changed) {
4804         // remove cur from list
4805         *prev = next;
4806         if (cur->current_at_end()) {
4807           // move to handled state (not maintained as a list)
4808           cur->set_state(handledState);
4809           DEBUG_ONLY(interval_moved(cur, kind, state, handledState);)
4810         } else if (cur->current_from() <= from){
4811           // sort into active list
4812           append_sorted(active_first_addr(kind), cur);
4813           cur->set_state(activeState);
4814           if (*prev == cur) {
4815             assert(state == activeState, "check");
4816             prev = cur->next_addr();
4817           }
4818           DEBUG_ONLY(interval_moved(cur, kind, state, activeState);)
4819         } else {
4820           // sort into inactive list
4821           append_sorted(inactive_first_addr(kind), cur);
4822           cur->set_state(inactiveState);
4823           if (*prev == cur) {
4824             assert(state == inactiveState, "check");
4825             prev = cur->next_addr();
4826           }
4827           DEBUG_ONLY(interval_moved(cur, kind, state, inactiveState);)
4828         }
4829       } else {
4830         prev = cur->next_addr();
4831         continue;
4832       }
4833     }
4834   }
4835 }
4836 
4837 
4838 void IntervalWalker::next_interval() {
4839   IntervalKind kind;
4840   Interval* any   = _unhandled_first[anyKind];
4841   Interval* fixed = _unhandled_first[fixedKind];
4842 
4843   if (any != Interval::end()) {
4844     // intervals may start at same position -> prefer fixed interval
4845     kind = fixed != Interval::end() && fixed->from() <= any->from() ? fixedKind : anyKind;
4846 
4847     assert (kind == fixedKind && fixed->from() <= any->from() ||
4848             kind == anyKind   && any->from() <= fixed->from(), "wrong interval!!!");
4849     assert(any == Interval::end() || fixed == Interval::end() || any->from() != fixed->from() || kind == fixedKind, "if fixed and any-Interval start at same position, fixed must be processed first");
4850 
4851   } else if (fixed != Interval::end()) {
4852     kind = fixedKind;
4853   } else {
4854     _current = NULL; return;
4855   }
4856   _current_kind = kind;
4857   _current = _unhandled_first[kind];
4858   _unhandled_first[kind] = _current->next();
4859   _current->set_next(Interval::end());
4860   _current->rewind_range();
4861 }
4862 
4863 
4864 void IntervalWalker::walk_to(int lir_op_id) {
4865   assert(_current_position <= lir_op_id, "can not walk backwards");
4866   while (current() != NULL) {
4867     bool is_active = current()->from() <= lir_op_id;
4868     int id = is_active ? current()->from() : lir_op_id;
4869 
4870     TRACE_LINEAR_SCAN(2, if (_current_position < id) { tty->cr(); tty->print_cr("walk_to(%d) **************************************************************", id); })
4871 
4872     // set _current_position prior to call of walk_to
4873     _current_position = id;
4874 
4875     // call walk_to even if _current_position == id
4876     walk_to(activeState, id);
4877     walk_to(inactiveState, id);
4878 
4879     if (is_active) {
4880       current()->set_state(activeState);
4881       if (activate_current()) {
4882         append_sorted(active_first_addr(current_kind()), current());
4883         DEBUG_ONLY(interval_moved(current(), current_kind(), unhandledState, activeState);)
4884       }
4885 
4886       next_interval();
4887     } else {
4888       return;
4889     }
4890   }
4891 }
4892 
4893 #ifdef ASSERT
4894 void IntervalWalker::interval_moved(Interval* interval, IntervalKind kind, IntervalState from, IntervalState to) {
4895   if (TraceLinearScanLevel >= 4) {
4896     #define print_state(state) \
4897     switch(state) {\
4898       case unhandledState: tty->print("unhandled"); break;\
4899       case activeState: tty->print("active"); break;\
4900       case inactiveState: tty->print("inactive"); break;\
4901       case handledState: tty->print("handled"); break;\
4902       default: ShouldNotReachHere(); \
4903     }
4904 
4905     print_state(from); tty->print(" to "); print_state(to);
4906     tty->fill_to(23);
4907     interval->print();
4908 
4909     #undef print_state
4910   }
4911 }
4912 #endif // ASSERT
4913 
4914 // **** Implementation of LinearScanWalker **************************
4915 
4916 LinearScanWalker::LinearScanWalker(LinearScan* allocator, Interval* unhandled_fixed_first, Interval* unhandled_any_first)
4917   : IntervalWalker(allocator, unhandled_fixed_first, unhandled_any_first)
4918   , _move_resolver(allocator)
4919 {
4920   for (int i = 0; i < LinearScan::nof_regs; i++) {
4921     _spill_intervals[i] = new IntervalList(2);
4922   }
4923 }
4924 
4925 
4926 inline void LinearScanWalker::init_use_lists(bool only_process_use_pos) {
4927   for (int i = _first_reg; i <= _last_reg; i++) {
4928     _use_pos[i] = max_jint;
4929 
4930     if (!only_process_use_pos) {
4931       _block_pos[i] = max_jint;
4932       _spill_intervals[i]->clear();
4933     }
4934   }
4935 }
4936 
4937 inline void LinearScanWalker::exclude_from_use(int reg) {
4938   assert(reg < LinearScan::nof_regs, "interval must have a register assigned (stack slots not allowed)");
4939   if (reg >= _first_reg && reg <= _last_reg) {
4940     _use_pos[reg] = 0;
4941   }
4942 }
4943 inline void LinearScanWalker::exclude_from_use(Interval* i) {
4944   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4945 
4946   exclude_from_use(i->assigned_reg());
4947   exclude_from_use(i->assigned_regHi());
4948 }
4949 
4950 inline void LinearScanWalker::set_use_pos(int reg, Interval* i, int use_pos, bool only_process_use_pos) {
4951   assert(use_pos != 0, "must use exclude_from_use to set use_pos to 0");
4952 
4953   if (reg >= _first_reg && reg <= _last_reg) {
4954     if (_use_pos[reg] > use_pos) {
4955       _use_pos[reg] = use_pos;
4956     }
4957     if (!only_process_use_pos) {
4958       _spill_intervals[reg]->append(i);
4959     }
4960   }
4961 }
4962 inline void LinearScanWalker::set_use_pos(Interval* i, int use_pos, bool only_process_use_pos) {
4963   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4964   if (use_pos != -1) {
4965     set_use_pos(i->assigned_reg(), i, use_pos, only_process_use_pos);
4966     set_use_pos(i->assigned_regHi(), i, use_pos, only_process_use_pos);
4967   }
4968 }
4969 
4970 inline void LinearScanWalker::set_block_pos(int reg, Interval* i, int block_pos) {
4971   if (reg >= _first_reg && reg <= _last_reg) {
4972     if (_block_pos[reg] > block_pos) {
4973       _block_pos[reg] = block_pos;
4974     }
4975     if (_use_pos[reg] > block_pos) {
4976       _use_pos[reg] = block_pos;
4977     }
4978   }
4979 }
4980 inline void LinearScanWalker::set_block_pos(Interval* i, int block_pos) {
4981   assert(i->assigned_reg() != any_reg, "interval has no register assigned");
4982   if (block_pos != -1) {
4983     set_block_pos(i->assigned_reg(), i, block_pos);
4984     set_block_pos(i->assigned_regHi(), i, block_pos);
4985   }
4986 }
4987 
4988 
4989 void LinearScanWalker::free_exclude_active_fixed() {
4990   Interval* list = active_first(fixedKind);
4991   while (list != Interval::end()) {
4992     assert(list->assigned_reg() < LinearScan::nof_regs, "active interval must have a register assigned");
4993     exclude_from_use(list);
4994     list = list->next();
4995   }
4996 }
4997 
4998 void LinearScanWalker::free_exclude_active_any() {
4999   Interval* list = active_first(anyKind);
5000   while (list != Interval::end()) {
5001     exclude_from_use(list);
5002     list = list->next();
5003   }
5004 }
5005 
5006 void LinearScanWalker::free_collect_inactive_fixed(Interval* cur) {
5007   Interval* list = inactive_first(fixedKind);
5008   while (list != Interval::end()) {
5009     if (cur->to() <= list->current_from()) {
5010       assert(list->current_intersects_at(cur) == -1, "must not intersect");
5011       set_use_pos(list, list->current_from(), true);
5012     } else {
5013       set_use_pos(list, list->current_intersects_at(cur), true);
5014     }
5015     list = list->next();
5016   }
5017 }
5018 
5019 void LinearScanWalker::free_collect_inactive_any(Interval* cur) {
5020   Interval* list = inactive_first(anyKind);
5021   while (list != Interval::end()) {
5022     set_use_pos(list, list->current_intersects_at(cur), true);
5023     list = list->next();
5024   }
5025 }
5026 
5027 void LinearScanWalker::spill_exclude_active_fixed() {
5028   Interval* list = active_first(fixedKind);
5029   while (list != Interval::end()) {
5030     exclude_from_use(list);
5031     list = list->next();
5032   }
5033 }
5034 
5035 void LinearScanWalker::spill_block_inactive_fixed(Interval* cur) {
5036   Interval* list = inactive_first(fixedKind);
5037   while (list != Interval::end()) {
5038     if (cur->to() > list->current_from()) {
5039       set_block_pos(list, list->current_intersects_at(cur));
5040     } else {
5041       assert(list->current_intersects_at(cur) == -1, "invalid optimization: intervals intersect");
5042     }
5043 
5044     list = list->next();
5045   }
5046 }
5047 
5048 void LinearScanWalker::spill_collect_active_any() {
5049   Interval* list = active_first(anyKind);
5050   while (list != Interval::end()) {
5051     set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5052     list = list->next();
5053   }
5054 }
5055 
5056 void LinearScanWalker::spill_collect_inactive_any(Interval* cur) {
5057   Interval* list = inactive_first(anyKind);
5058   while (list != Interval::end()) {
5059     if (list->current_intersects(cur)) {
5060       set_use_pos(list, MIN2(list->next_usage(loopEndMarker, _current_position), list->to()), false);
5061     }
5062     list = list->next();
5063   }
5064 }
5065 
5066 
5067 void LinearScanWalker::insert_move(int op_id, Interval* src_it, Interval* dst_it) {
5068   // output all moves here. When source and target are equal, the move is
5069   // optimized away later in assign_reg_nums
5070 
5071   op_id = (op_id + 1) & ~1;
5072   BlockBegin* op_block = allocator()->block_of_op_with_id(op_id);
5073   assert(op_id > 0 && allocator()->block_of_op_with_id(op_id - 2) == op_block, "cannot insert move at block boundary");
5074 
5075   // calculate index of instruction inside instruction list of current block
5076   // the minimal index (for a block with no spill moves) can be calculated because the
5077   // numbering of instructions is known.
5078   // When the block already contains spill moves, the index must be increased until the
5079   // correct index is reached.
5080   LIR_OpList* list = op_block->lir()->instructions_list();
5081   int index = (op_id - list->at(0)->id()) / 2;
5082   assert(list->at(index)->id() <= op_id, "error in calculation");
5083 
5084   while (list->at(index)->id() != op_id) {
5085     index++;
5086     assert(0 <= index && index < list->length(), "index out of bounds");
5087   }
5088   assert(1 <= index && index < list->length(), "index out of bounds");
5089   assert(list->at(index)->id() == op_id, "error in calculation");
5090 
5091   // insert new instruction before instruction at position index
5092   _move_resolver.move_insert_position(op_block->lir(), index - 1);
5093   _move_resolver.add_mapping(src_it, dst_it);
5094 }
5095 
5096 
5097 int LinearScanWalker::find_optimal_split_pos(BlockBegin* min_block, BlockBegin* max_block, int max_split_pos) {
5098   int from_block_nr = min_block->linear_scan_number();
5099   int to_block_nr = max_block->linear_scan_number();
5100 
5101   assert(0 <= from_block_nr && from_block_nr < block_count(), "out of range");
5102   assert(0 <= to_block_nr && to_block_nr < block_count(), "out of range");
5103   assert(from_block_nr < to_block_nr, "must cross block boundary");
5104 
5105   // Try to split at end of max_block. If this would be after
5106   // max_split_pos, then use the begin of max_block
5107   int optimal_split_pos = max_block->last_lir_instruction_id() + 2;
5108   if (optimal_split_pos > max_split_pos) {
5109     optimal_split_pos = max_block->first_lir_instruction_id();
5110   }
5111 
5112   int min_loop_depth = max_block->loop_depth();
5113   for (int i = to_block_nr - 1; i >= from_block_nr; i--) {
5114     BlockBegin* cur = block_at(i);
5115 
5116     if (cur->loop_depth() < min_loop_depth) {
5117       // block with lower loop-depth found -> split at the end of this block
5118       min_loop_depth = cur->loop_depth();
5119       optimal_split_pos = cur->last_lir_instruction_id() + 2;
5120     }
5121   }
5122   assert(optimal_split_pos > allocator()->max_lir_op_id() || allocator()->is_block_begin(optimal_split_pos), "algorithm must move split pos to block boundary");
5123 
5124   return optimal_split_pos;
5125 }
5126 
5127 
5128 int LinearScanWalker::find_optimal_split_pos(Interval* it, int min_split_pos, int max_split_pos, bool do_loop_optimization) {
5129   int optimal_split_pos = -1;
5130   if (min_split_pos == max_split_pos) {
5131     // trivial case, no optimization of split position possible
5132     TRACE_LINEAR_SCAN(4, tty->print_cr("      min-pos and max-pos are equal, no optimization possible"));
5133     optimal_split_pos = min_split_pos;
5134 
5135   } else {
5136     assert(min_split_pos < max_split_pos, "must be true then");
5137     assert(min_split_pos > 0, "cannot access min_split_pos - 1 otherwise");
5138 
5139     // reason for using min_split_pos - 1: when the minimal split pos is exactly at the
5140     // beginning of a block, then min_split_pos is also a possible split position.
5141     // Use the block before as min_block, because then min_block->last_lir_instruction_id() + 2 == min_split_pos
5142     BlockBegin* min_block = allocator()->block_of_op_with_id(min_split_pos - 1);
5143 
5144     // reason for using max_split_pos - 1: otherwise there would be an assertion failure
5145     // when an interval ends at the end of the last block of the method
5146     // (in this case, max_split_pos == allocator()->max_lir_op_id() + 2, and there is no
5147     // block at this op_id)
5148     BlockBegin* max_block = allocator()->block_of_op_with_id(max_split_pos - 1);
5149 
5150     assert(min_block->linear_scan_number() <= max_block->linear_scan_number(), "invalid order");
5151     if (min_block == max_block) {
5152       // split position cannot be moved to block boundary, so split as late as possible
5153       TRACE_LINEAR_SCAN(4, tty->print_cr("      cannot move split pos to block boundary because min_pos and max_pos are in same block"));
5154       optimal_split_pos = max_split_pos;
5155 
5156     } else if (it->has_hole_between(max_split_pos - 1, max_split_pos) && !allocator()->is_block_begin(max_split_pos)) {
5157       // Do not move split position if the interval has a hole before max_split_pos.
5158       // Intervals resulting from Phi-Functions have more than one definition (marked
5159       // as mustHaveRegister) with a hole before each definition. When the register is needed
5160       // for the second definition, an earlier reloading is unnecessary.
5161       TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has hole just before max_split_pos, so splitting at max_split_pos"));
5162       optimal_split_pos = max_split_pos;
5163 
5164     } else {
5165       // search optimal block boundary between min_split_pos and max_split_pos
5166       TRACE_LINEAR_SCAN(4, tty->print_cr("      moving split pos to optimal block boundary between block B%d and B%d", min_block->block_id(), max_block->block_id()));
5167 
5168       if (do_loop_optimization) {
5169         // Loop optimization: if a loop-end marker is found between min- and max-position,
5170         // then split before this loop
5171         int loop_end_pos = it->next_usage_exact(loopEndMarker, min_block->last_lir_instruction_id() + 2);
5172         TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization: loop end found at pos %d", loop_end_pos));
5173 
5174         assert(loop_end_pos > min_split_pos, "invalid order");
5175         if (loop_end_pos < max_split_pos) {
5176           // loop-end marker found between min- and max-position
5177           // if it is not the end marker for the same loop as the min-position, then move
5178           // the max-position to this loop block.
5179           // Desired result: uses tagged as shouldHaveRegister inside a loop cause a reloading
5180           // of the interval (normally, only mustHaveRegister causes a reloading)
5181           BlockBegin* loop_block = allocator()->block_of_op_with_id(loop_end_pos);
5182 
5183           TRACE_LINEAR_SCAN(4, tty->print_cr("      interval is used in loop that ends in block B%d, so trying to move max_block back from B%d to B%d", loop_block->block_id(), max_block->block_id(), loop_block->block_id()));
5184           assert(loop_block != min_block, "loop_block and min_block must be different because block boundary is needed between");
5185 
5186           optimal_split_pos = find_optimal_split_pos(min_block, loop_block, loop_block->last_lir_instruction_id() + 2);
5187           if (optimal_split_pos == loop_block->last_lir_instruction_id() + 2) {
5188             optimal_split_pos = -1;
5189             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization not necessary"));
5190           } else {
5191             TRACE_LINEAR_SCAN(4, tty->print_cr("      loop optimization successful"));
5192           }
5193         }
5194       }
5195 
5196       if (optimal_split_pos == -1) {
5197         // not calculated by loop optimization
5198         optimal_split_pos = find_optimal_split_pos(min_block, max_block, max_split_pos);
5199       }
5200     }
5201   }
5202   TRACE_LINEAR_SCAN(4, tty->print_cr("      optimal split position: %d", optimal_split_pos));
5203 
5204   return optimal_split_pos;
5205 }
5206 
5207 
5208 /*
5209   split an interval at the optimal position between min_split_pos and
5210   max_split_pos in two parts:
5211   1) the left part has already a location assigned
5212   2) the right part is sorted into to the unhandled-list
5213 */
5214 void LinearScanWalker::split_before_usage(Interval* it, int min_split_pos, int max_split_pos) {
5215   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting interval: "); it->print());
5216   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5217 
5218   assert(it->from() < min_split_pos,         "cannot split at start of interval");
5219   assert(current_position() < min_split_pos, "cannot split before current position");
5220   assert(min_split_pos <= max_split_pos,     "invalid order");
5221   assert(max_split_pos <= it->to(),          "cannot split after end of interval");
5222 
5223   int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, true);
5224 
5225   assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5226   assert(optimal_split_pos <= it->to(),  "cannot split after end of interval");
5227   assert(optimal_split_pos > it->from(), "cannot split at start of interval");
5228 
5229   if (optimal_split_pos == it->to() && it->next_usage(mustHaveRegister, min_split_pos) == max_jint) {
5230     // the split position would be just before the end of the interval
5231     // -> no split at all necessary
5232     TRACE_LINEAR_SCAN(4, tty->print_cr("      no split necessary because optimal split position is at end of interval"));
5233     return;
5234   }
5235 
5236   // must calculate this before the actual split is performed and before split position is moved to odd op_id
5237   bool move_necessary = !allocator()->is_block_begin(optimal_split_pos) && !it->has_hole_between(optimal_split_pos - 1, optimal_split_pos);
5238 
5239   if (!allocator()->is_block_begin(optimal_split_pos)) {
5240     // move position before actual instruction (odd op_id)
5241     optimal_split_pos = (optimal_split_pos - 1) | 1;
5242   }
5243 
5244   TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5245   assert(allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5246   assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5247 
5248   Interval* split_part = it->split(optimal_split_pos);
5249 
5250   allocator()->append_interval(split_part);
5251   allocator()->copy_register_flags(it, split_part);
5252   split_part->set_insert_move_when_activated(move_necessary);
5253   append_to_unhandled(unhandled_first_addr(anyKind), split_part);
5254 
5255   TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts (insert_move_when_activated: %d)", move_necessary));
5256   TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5257   TRACE_LINEAR_SCAN(2, tty->print   ("      "); split_part->print());
5258 }
5259 
5260 /*
5261   split an interval at the optimal position between min_split_pos and
5262   max_split_pos in two parts:
5263   1) the left part has already a location assigned
5264   2) the right part is always on the stack and therefore ignored in further processing
5265 */
5266 void LinearScanWalker::split_for_spilling(Interval* it) {
5267   // calculate allowed range of splitting position
5268   int max_split_pos = current_position();
5269   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, max_split_pos) + 1, it->from());
5270 
5271   TRACE_LINEAR_SCAN(2, tty->print   ("----- splitting and spilling interval: "); it->print());
5272   TRACE_LINEAR_SCAN(2, tty->print_cr("      between %d and %d", min_split_pos, max_split_pos));
5273 
5274   assert(it->state() == activeState,     "why spill interval that is not active?");
5275   assert(it->from() <= min_split_pos,    "cannot split before start of interval");
5276   assert(min_split_pos <= max_split_pos, "invalid order");
5277   assert(max_split_pos < it->to(),       "cannot split at end end of interval");
5278   assert(current_position() < it->to(),  "interval must not end before current position");
5279 
5280   if (min_split_pos == it->from()) {
5281     // the whole interval is never used, so spill it entirely to memory
5282     TRACE_LINEAR_SCAN(2, tty->print_cr("      spilling entire interval because split pos is at beginning of interval"));
5283     assert(it->first_usage(shouldHaveRegister) > current_position(), "interval must not have use position before current_position");
5284 
5285     allocator()->assign_spill_slot(it);
5286     allocator()->change_spill_state(it, min_split_pos);
5287 
5288     // Also kick parent intervals out of register to memory when they have no use
5289     // position. This avoids short interval in register surrounded by intervals in
5290     // memory -> avoid useless moves from memory to register and back
5291     Interval* parent = it;
5292     while (parent != NULL && parent->is_split_child()) {
5293       parent = parent->split_child_before_op_id(parent->from());
5294 
5295       if (parent->assigned_reg() < LinearScan::nof_regs) {
5296         if (parent->first_usage(shouldHaveRegister) == max_jint) {
5297           // parent is never used, so kick it out of its assigned register
5298           TRACE_LINEAR_SCAN(4, tty->print_cr("      kicking out interval %d out of its register because it is never used", parent->reg_num()));
5299           allocator()->assign_spill_slot(parent);
5300         } else {
5301           // do not go further back because the register is actually used by the interval
5302           parent = NULL;
5303         }
5304       }
5305     }
5306 
5307   } else {
5308     // search optimal split pos, split interval and spill only the right hand part
5309     int optimal_split_pos = find_optimal_split_pos(it, min_split_pos, max_split_pos, false);
5310 
5311     assert(min_split_pos <= optimal_split_pos && optimal_split_pos <= max_split_pos, "out of range");
5312     assert(optimal_split_pos < it->to(), "cannot split at end of interval");
5313     assert(optimal_split_pos >= it->from(), "cannot split before start of interval");
5314 
5315     if (!allocator()->is_block_begin(optimal_split_pos)) {
5316       // move position before actual instruction (odd op_id)
5317       optimal_split_pos = (optimal_split_pos - 1) | 1;
5318     }
5319 
5320     TRACE_LINEAR_SCAN(4, tty->print_cr("      splitting at position %d", optimal_split_pos));
5321     assert(allocator()->is_block_begin(optimal_split_pos)  || (optimal_split_pos % 2 == 1), "split pos must be odd when not on block boundary");
5322     assert(!allocator()->is_block_begin(optimal_split_pos) || (optimal_split_pos % 2 == 0), "split pos must be even on block boundary");
5323 
5324     Interval* spilled_part = it->split(optimal_split_pos);
5325     allocator()->append_interval(spilled_part);
5326     allocator()->assign_spill_slot(spilled_part);
5327     allocator()->change_spill_state(spilled_part, optimal_split_pos);
5328 
5329     if (!allocator()->is_block_begin(optimal_split_pos)) {
5330       TRACE_LINEAR_SCAN(4, tty->print_cr("      inserting move from interval %d to %d", it->reg_num(), spilled_part->reg_num()));
5331       insert_move(optimal_split_pos, it, spilled_part);
5332     }
5333 
5334     // the current_split_child is needed later when moves are inserted for reloading
5335     assert(spilled_part->current_split_child() == it, "overwriting wrong current_split_child");
5336     spilled_part->make_current_split_child();
5337 
5338     TRACE_LINEAR_SCAN(2, tty->print_cr("      split interval in two parts"));
5339     TRACE_LINEAR_SCAN(2, tty->print   ("      "); it->print());
5340     TRACE_LINEAR_SCAN(2, tty->print   ("      "); spilled_part->print());
5341   }
5342 }
5343 
5344 
5345 void LinearScanWalker::split_stack_interval(Interval* it) {
5346   int min_split_pos = current_position() + 1;
5347   int max_split_pos = MIN2(it->first_usage(shouldHaveRegister), it->to());
5348 
5349   split_before_usage(it, min_split_pos, max_split_pos);
5350 }
5351 
5352 void LinearScanWalker::split_when_partial_register_available(Interval* it, int register_available_until) {
5353   int min_split_pos = MAX2(it->previous_usage(shouldHaveRegister, register_available_until), it->from() + 1);
5354   int max_split_pos = register_available_until;
5355 
5356   split_before_usage(it, min_split_pos, max_split_pos);
5357 }
5358 
5359 void LinearScanWalker::split_and_spill_interval(Interval* it) {
5360   assert(it->state() == activeState || it->state() == inactiveState, "other states not allowed");
5361 
5362   int current_pos = current_position();
5363   if (it->state() == inactiveState) {
5364     // the interval is currently inactive, so no spill slot is needed for now.
5365     // when the split part is activated, the interval has a new chance to get a register,
5366     // so in the best case no stack slot is necessary
5367     assert(it->has_hole_between(current_pos - 1, current_pos + 1), "interval can not be inactive otherwise");
5368     split_before_usage(it, current_pos + 1, current_pos + 1);
5369 
5370   } else {
5371     // search the position where the interval must have a register and split
5372     // at the optimal position before.
5373     // The new created part is added to the unhandled list and will get a register
5374     // when it is activated
5375     int min_split_pos = current_pos + 1;
5376     int max_split_pos = MIN2(it->next_usage(mustHaveRegister, min_split_pos), it->to());
5377 
5378     split_before_usage(it, min_split_pos, max_split_pos);
5379 
5380     assert(it->next_usage(mustHaveRegister, current_pos) == max_jint, "the remaining part is spilled to stack and therefore has no register");
5381     split_for_spilling(it);
5382   }
5383 }
5384 
5385 int LinearScanWalker::find_free_reg(int reg_needed_until, int interval_to, int hint_reg, int ignore_reg, bool* need_split) {
5386   int min_full_reg = any_reg;
5387   int max_partial_reg = any_reg;
5388 
5389   for (int i = _first_reg; i <= _last_reg; i++) {
5390     if (i == ignore_reg) {
5391       // this register must be ignored
5392 
5393     } else if (_use_pos[i] >= interval_to) {
5394       // this register is free for the full interval
5395       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5396         min_full_reg = i;
5397       }
5398     } else if (_use_pos[i] > reg_needed_until) {
5399       // this register is at least free until reg_needed_until
5400       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5401         max_partial_reg = i;
5402       }
5403     }
5404   }
5405 
5406   if (min_full_reg != any_reg) {
5407     return min_full_reg;
5408   } else if (max_partial_reg != any_reg) {
5409     *need_split = true;
5410     return max_partial_reg;
5411   } else {
5412     return any_reg;
5413   }
5414 }
5415 
5416 int LinearScanWalker::find_free_double_reg(int reg_needed_until, int interval_to, int hint_reg, bool* need_split) {
5417   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5418 
5419   int min_full_reg = any_reg;
5420   int max_partial_reg = any_reg;
5421 
5422   for (int i = _first_reg; i < _last_reg; i+=2) {
5423     if (_use_pos[i] >= interval_to && _use_pos[i + 1] >= interval_to) {
5424       // this register is free for the full interval
5425       if (min_full_reg == any_reg || i == hint_reg || (_use_pos[i] < _use_pos[min_full_reg] && min_full_reg != hint_reg)) {
5426         min_full_reg = i;
5427       }
5428     } else if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5429       // this register is at least free until reg_needed_until
5430       if (max_partial_reg == any_reg || i == hint_reg || (_use_pos[i] > _use_pos[max_partial_reg] && max_partial_reg != hint_reg)) {
5431         max_partial_reg = i;
5432       }
5433     }
5434   }
5435 
5436   if (min_full_reg != any_reg) {
5437     return min_full_reg;
5438   } else if (max_partial_reg != any_reg) {
5439     *need_split = true;
5440     return max_partial_reg;
5441   } else {
5442     return any_reg;
5443   }
5444 }
5445 
5446 bool LinearScanWalker::alloc_free_reg(Interval* cur) {
5447   TRACE_LINEAR_SCAN(2, tty->print("trying to find free register for "); cur->print());
5448 
5449   init_use_lists(true);
5450   free_exclude_active_fixed();
5451   free_exclude_active_any();
5452   free_collect_inactive_fixed(cur);
5453   free_collect_inactive_any(cur);
5454   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5455 
5456   // _use_pos contains the start of the next interval that has this register assigned
5457   // (either as a fixed register or a normal allocated register in the past)
5458   // only intervals overlapping with cur are processed, non-overlapping invervals can be ignored safely
5459 #ifdef ASSERT
5460   if (TraceLinearScanLevel >= 4) {
5461     tty->print_cr("      state of registers:");
5462     for (int i = _first_reg; i <= _last_reg; i++) {
5463       tty->print("      reg %d (", i);
5464       LinearScan::print_reg_num(i);
5465       tty->print_cr("): use_pos: %d", _use_pos[i]);
5466     }
5467   }
5468 #endif
5469 
5470   int hint_reg, hint_regHi;
5471   Interval* register_hint = cur->register_hint();
5472   if (register_hint != NULL) {
5473     hint_reg = register_hint->assigned_reg();
5474     hint_regHi = register_hint->assigned_regHi();
5475 
5476     if (_num_phys_regs == 2 && allocator()->is_precolored_cpu_interval(register_hint)) {
5477       assert(hint_reg != any_reg && hint_regHi == any_reg, "must be for fixed intervals");
5478       hint_regHi = hint_reg + 1;  // connect e.g. eax-edx
5479     }
5480 #ifdef ASSERT
5481     if (TraceLinearScanLevel >= 4) {
5482       tty->print("      hint registers %d (", hint_reg);
5483       LinearScan::print_reg_num(hint_reg);
5484       tty->print("), %d (", hint_regHi);
5485       LinearScan::print_reg_num(hint_regHi);
5486       tty->print(") from interval ");
5487       register_hint->print();
5488     }
5489 #endif
5490   } else {
5491     hint_reg = any_reg;
5492     hint_regHi = any_reg;
5493   }
5494   assert(hint_reg == any_reg || hint_reg != hint_regHi, "hint reg and regHi equal");
5495   assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned to interval");
5496 
5497   // the register must be free at least until this position
5498   int reg_needed_until = cur->from() + 1;
5499   int interval_to = cur->to();
5500 
5501   bool need_split = false;
5502   int split_pos;
5503   int reg;
5504   int regHi = any_reg;
5505 
5506   if (_adjacent_regs) {
5507     reg = find_free_double_reg(reg_needed_until, interval_to, hint_reg, &need_split);
5508     regHi = reg + 1;
5509     if (reg == any_reg) {
5510       return false;
5511     }
5512     split_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5513 
5514   } else {
5515     reg = find_free_reg(reg_needed_until, interval_to, hint_reg, any_reg, &need_split);
5516     if (reg == any_reg) {
5517       return false;
5518     }
5519     split_pos = _use_pos[reg];
5520 
5521     if (_num_phys_regs == 2) {
5522       regHi = find_free_reg(reg_needed_until, interval_to, hint_regHi, reg, &need_split);
5523 
5524       if (_use_pos[reg] < interval_to && regHi == any_reg) {
5525         // do not split interval if only one register can be assigned until the split pos
5526         // (when one register is found for the whole interval, split&spill is only
5527         // performed for the hi register)
5528         return false;
5529 
5530       } else if (regHi != any_reg) {
5531         split_pos = MIN2(split_pos, _use_pos[regHi]);
5532 
5533         // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5534         if (reg > regHi) {
5535           int temp = reg;
5536           reg = regHi;
5537           regHi = temp;
5538         }
5539       }
5540     }
5541   }
5542 
5543   cur->assign_reg(reg, regHi);
5544 #ifdef ASSERT
5545   if (TraceLinearScanLevel >= 2) {
5546     tty->print("      selected registers %d (", reg);
5547     LinearScan::print_reg_num(reg);
5548     tty->print("), %d (", regHi);
5549     LinearScan::print_reg_num(regHi);
5550     tty->print_cr(")");
5551   }
5552 #endif
5553   assert(split_pos > 0, "invalid split_pos");
5554   if (need_split) {
5555     // register not available for full interval, so split it
5556     split_when_partial_register_available(cur, split_pos);
5557   }
5558 
5559   // only return true if interval is completely assigned
5560   return _num_phys_regs == 1 || regHi != any_reg;
5561 }
5562 
5563 
5564 int LinearScanWalker::find_locked_reg(int reg_needed_until, int interval_to, int ignore_reg, bool* need_split) {
5565   int max_reg = any_reg;
5566 
5567   for (int i = _first_reg; i <= _last_reg; i++) {
5568     if (i == ignore_reg) {
5569       // this register must be ignored
5570 
5571     } else if (_use_pos[i] > reg_needed_until) {
5572       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5573         max_reg = i;
5574       }
5575     }
5576   }
5577 
5578   if (max_reg != any_reg && _block_pos[max_reg] <= interval_to) {
5579     *need_split = true;
5580   }
5581 
5582   return max_reg;
5583 }
5584 
5585 int LinearScanWalker::find_locked_double_reg(int reg_needed_until, int interval_to, bool* need_split) {
5586   assert((_last_reg - _first_reg + 1) % 2 == 0, "adjust algorithm");
5587 
5588   int max_reg = any_reg;
5589 
5590   for (int i = _first_reg; i < _last_reg; i+=2) {
5591     if (_use_pos[i] > reg_needed_until && _use_pos[i + 1] > reg_needed_until) {
5592       if (max_reg == any_reg || _use_pos[i] > _use_pos[max_reg]) {
5593         max_reg = i;
5594       }
5595     }
5596   }
5597 
5598   if (max_reg != any_reg &&
5599       (_block_pos[max_reg] <= interval_to || _block_pos[max_reg + 1] <= interval_to)) {
5600     *need_split = true;
5601   }
5602 
5603   return max_reg;
5604 }
5605 
5606 void LinearScanWalker::split_and_spill_intersecting_intervals(int reg, int regHi) {
5607   assert(reg != any_reg, "no register assigned");
5608 
5609   for (int i = 0; i < _spill_intervals[reg]->length(); i++) {
5610     Interval* it = _spill_intervals[reg]->at(i);
5611     remove_from_list(it);
5612     split_and_spill_interval(it);
5613   }
5614 
5615   if (regHi != any_reg) {
5616     IntervalList* processed = _spill_intervals[reg];
5617     for (int i = 0; i < _spill_intervals[regHi]->length(); i++) {
5618       Interval* it = _spill_intervals[regHi]->at(i);
5619       if (processed->find(it) == -1) {
5620         remove_from_list(it);
5621         split_and_spill_interval(it);
5622       }
5623     }
5624   }
5625 }
5626 
5627 
5628 // Split an Interval and spill it to memory so that cur can be placed in a register
5629 void LinearScanWalker::alloc_locked_reg(Interval* cur) {
5630   TRACE_LINEAR_SCAN(2, tty->print("need to split and spill to get register for "); cur->print());
5631 
5632   // collect current usage of registers
5633   init_use_lists(false);
5634   spill_exclude_active_fixed();
5635   assert(unhandled_first(fixedKind) == Interval::end(), "must not have unhandled fixed intervals because all fixed intervals have a use at position 0");
5636   spill_block_inactive_fixed(cur);
5637   spill_collect_active_any();
5638   spill_collect_inactive_any(cur);
5639 
5640 #ifdef ASSERT
5641   if (TraceLinearScanLevel >= 4) {
5642     tty->print_cr("      state of registers:");
5643     for (int i = _first_reg; i <= _last_reg; i++) {
5644       tty->print("      reg %d(", i);
5645       LinearScan::print_reg_num(i);
5646       tty->print("): use_pos: %d, block_pos: %d, intervals: ", _use_pos[i], _block_pos[i]);
5647       for (int j = 0; j < _spill_intervals[i]->length(); j++) {
5648         tty->print("%d ", _spill_intervals[i]->at(j)->reg_num());
5649       }
5650       tty->cr();
5651     }
5652   }
5653 #endif
5654 
5655   // the register must be free at least until this position
5656   int reg_needed_until = MIN2(cur->first_usage(mustHaveRegister), cur->from() + 1);
5657   int interval_to = cur->to();
5658   assert (reg_needed_until > 0 && reg_needed_until < max_jint, "interval has no use");
5659 
5660   int split_pos = 0;
5661   int use_pos = 0;
5662   bool need_split = false;
5663   int reg, regHi;
5664 
5665   if (_adjacent_regs) {
5666     reg = find_locked_double_reg(reg_needed_until, interval_to, &need_split);
5667     regHi = reg + 1;
5668 
5669     if (reg != any_reg) {
5670       use_pos = MIN2(_use_pos[reg], _use_pos[regHi]);
5671       split_pos = MIN2(_block_pos[reg], _block_pos[regHi]);
5672     }
5673   } else {
5674     reg = find_locked_reg(reg_needed_until, interval_to, cur->assigned_reg(), &need_split);
5675     regHi = any_reg;
5676 
5677     if (reg != any_reg) {
5678       use_pos = _use_pos[reg];
5679       split_pos = _block_pos[reg];
5680 
5681       if (_num_phys_regs == 2) {
5682         if (cur->assigned_reg() != any_reg) {
5683           regHi = reg;
5684           reg = cur->assigned_reg();
5685         } else {
5686           regHi = find_locked_reg(reg_needed_until, interval_to, reg, &need_split);
5687           if (regHi != any_reg) {
5688             use_pos = MIN2(use_pos, _use_pos[regHi]);
5689             split_pos = MIN2(split_pos, _block_pos[regHi]);
5690           }
5691         }
5692 
5693         if (regHi != any_reg && reg > regHi) {
5694           // sort register numbers to prevent e.g. a move from eax,ebx to ebx,eax
5695           int temp = reg;
5696           reg = regHi;
5697           regHi = temp;
5698         }
5699       }
5700     }
5701   }
5702 
5703   if (reg == any_reg || (_num_phys_regs == 2 && regHi == any_reg) || use_pos <= cur->first_usage(mustHaveRegister)) {
5704     // the first use of cur is later than the spilling position -> spill cur
5705     TRACE_LINEAR_SCAN(4, tty->print_cr("able to spill current interval. first_usage(register): %d, use_pos: %d", cur->first_usage(mustHaveRegister), use_pos));
5706 
5707     if (cur->first_usage(mustHaveRegister) <= cur->from() + 1) {
5708       assert(false, "cannot spill interval that is used in first instruction (possible reason: no register found)");
5709       // assign a reasonable register and do a bailout in product mode to avoid errors
5710       allocator()->assign_spill_slot(cur);
5711       BAILOUT("LinearScan: no register found");
5712     }
5713 
5714     split_and_spill_interval(cur);
5715   } else {
5716 #ifdef ASSERT
5717     if (TraceLinearScanLevel >= 4) {
5718       tty->print("decided to use register %d (", reg);
5719       LinearScan::print_reg_num(reg);
5720       tty->print("), %d (", regHi);
5721       LinearScan::print_reg_num(regHi);
5722       tty->print_cr(")");
5723     }
5724 #endif
5725     assert(reg != any_reg && (_num_phys_regs == 1 || regHi != any_reg), "no register found");
5726     assert(split_pos > 0, "invalid split_pos");
5727     assert(need_split == false || split_pos > cur->from(), "splitting interval at from");
5728 
5729     cur->assign_reg(reg, regHi);
5730     if (need_split) {
5731       // register not available for full interval, so split it
5732       split_when_partial_register_available(cur, split_pos);
5733     }
5734 
5735     // perform splitting and spilling for all affected intervals
5736     split_and_spill_intersecting_intervals(reg, regHi);
5737   }
5738 }
5739 
5740 bool LinearScanWalker::no_allocation_possible(Interval* cur) {
5741 #ifdef X86
5742   // fast calculation of intervals that can never get a register because the
5743   // the next instruction is a call that blocks all registers
5744   // Note: this does not work if callee-saved registers are available (e.g. on Sparc)
5745 
5746   // check if this interval is the result of a split operation
5747   // (an interval got a register until this position)
5748   int pos = cur->from();
5749   if ((pos & 1) == 1) {
5750     // the current instruction is a call that blocks all registers
5751     if (pos < allocator()->max_lir_op_id() && allocator()->has_call(pos + 1)) {
5752       TRACE_LINEAR_SCAN(4, tty->print_cr("      free register cannot be available because all registers blocked by following call"));
5753 
5754       // safety check that there is really no register available
5755       assert(alloc_free_reg(cur) == false, "found a register for this interval");
5756       return true;
5757     }
5758 
5759   }
5760 #endif
5761   return false;
5762 }
5763 
5764 void LinearScanWalker::init_vars_for_alloc(Interval* cur) {
5765   BasicType type = cur->type();
5766   _num_phys_regs = LinearScan::num_physical_regs(type);
5767   _adjacent_regs = LinearScan::requires_adjacent_regs(type);
5768 
5769   if (pd_init_regs_for_alloc(cur)) {
5770     // the appropriate register range was selected.
5771   } else if (type == T_FLOAT || type == T_DOUBLE) {
5772     _first_reg = pd_first_fpu_reg;
5773     _last_reg = pd_last_fpu_reg;
5774   } else {
5775     _first_reg = pd_first_cpu_reg;
5776     _last_reg = FrameMap::last_cpu_reg();
5777   }
5778 
5779   assert(0 <= _first_reg && _first_reg < LinearScan::nof_regs, "out of range");
5780   assert(0 <= _last_reg && _last_reg < LinearScan::nof_regs, "out of range");
5781 }
5782 
5783 
5784 bool LinearScanWalker::is_move(LIR_Op* op, Interval* from, Interval* to) {
5785   if (op->code() != lir_move) {
5786     return false;
5787   }
5788   assert(op->as_Op1() != NULL, "move must be LIR_Op1");
5789 
5790   LIR_Opr in = ((LIR_Op1*)op)->in_opr();
5791   LIR_Opr res = ((LIR_Op1*)op)->result_opr();
5792   return in->is_virtual() && res->is_virtual() && in->vreg_number() == from->reg_num() && res->vreg_number() == to->reg_num();
5793 }
5794 
5795 // optimization (especially for phi functions of nested loops):
5796 // assign same spill slot to non-intersecting intervals
5797 void LinearScanWalker::combine_spilled_intervals(Interval* cur) {
5798   if (cur->is_split_child()) {
5799     // optimization is only suitable for split parents
5800     return;
5801   }
5802 
5803   Interval* register_hint = cur->register_hint(false);
5804   if (register_hint == NULL) {
5805     // cur is not the target of a move, otherwise register_hint would be set
5806     return;
5807   }
5808   assert(register_hint->is_split_parent(), "register hint must be split parent");
5809 
5810   if (cur->spill_state() != noOptimization || register_hint->spill_state() != noOptimization) {
5811     // combining the stack slots for intervals where spill move optimization is applied
5812     // is not benefitial and would cause problems
5813     return;
5814   }
5815 
5816   int begin_pos = cur->from();
5817   int end_pos = cur->to();
5818   if (end_pos > allocator()->max_lir_op_id() || (begin_pos & 1) != 0 || (end_pos & 1) != 0) {
5819     // safety check that lir_op_with_id is allowed
5820     return;
5821   }
5822 
5823   if (!is_move(allocator()->lir_op_with_id(begin_pos), register_hint, cur) || !is_move(allocator()->lir_op_with_id(end_pos), cur, register_hint)) {
5824     // cur and register_hint are not connected with two moves
5825     return;
5826   }
5827 
5828   Interval* begin_hint = register_hint->split_child_at_op_id(begin_pos, LIR_OpVisitState::inputMode);
5829   Interval* end_hint = register_hint->split_child_at_op_id(end_pos, LIR_OpVisitState::outputMode);
5830   if (begin_hint == end_hint || begin_hint->to() != begin_pos || end_hint->from() != end_pos) {
5831     // register_hint must be split, otherwise the re-writing of use positions does not work
5832     return;
5833   }
5834 
5835   assert(begin_hint->assigned_reg() != any_reg, "must have register assigned");
5836   assert(end_hint->assigned_reg() == any_reg, "must not have register assigned");
5837   assert(cur->first_usage(mustHaveRegister) == begin_pos, "must have use position at begin of interval because of move");
5838   assert(end_hint->first_usage(mustHaveRegister) == end_pos, "must have use position at begin of interval because of move");
5839 
5840   if (begin_hint->assigned_reg() < LinearScan::nof_regs) {
5841     // register_hint is not spilled at begin_pos, so it would not be benefitial to immediately spill cur
5842     return;
5843   }
5844   assert(register_hint->canonical_spill_slot() != -1, "must be set when part of interval was spilled");
5845   assert(!cur->intersects(register_hint), "cur should not intersect register_hint");
5846 
5847   if (cur->intersects_any_children_of(register_hint)) {
5848     // Bail out if cur intersects any split children of register_hint, which have the same spill slot as their parent. An overlap of two intervals with
5849     // the same spill slot could result in a situation where both intervals are spilled at the same time to the same stack location which is not correct.
5850     return;
5851   }
5852 
5853   // modify intervals such that cur gets the same stack slot as register_hint
5854   // delete use positions to prevent the intervals to get a register at beginning
5855   cur->set_canonical_spill_slot(register_hint->canonical_spill_slot());
5856   cur->remove_first_use_pos();
5857   end_hint->remove_first_use_pos();
5858 }
5859 
5860 
5861 // allocate a physical register or memory location to an interval
5862 bool LinearScanWalker::activate_current() {
5863   Interval* cur = current();
5864   bool result = true;
5865 
5866   TRACE_LINEAR_SCAN(2, tty->print   ("+++++ activating interval "); cur->print());
5867   TRACE_LINEAR_SCAN(4, tty->print_cr("      split_parent: %d, insert_move_when_activated: %d", cur->split_parent()->reg_num(), cur->insert_move_when_activated()));
5868 
5869   if (cur->assigned_reg() >= LinearScan::nof_regs) {
5870     // activating an interval that has a stack slot assigned -> split it at first use position
5871     // used for method parameters
5872     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval has spill slot assigned (method parameter) -> split it before first use"));
5873 
5874     split_stack_interval(cur);
5875     result = false;
5876 
5877   } else if (allocator()->gen()->is_vreg_flag_set(cur->reg_num(), LIRGenerator::must_start_in_memory)) {
5878     // activating an interval that must start in a stack slot, but may get a register later
5879     // used for lir_roundfp: rounding is done by store to stack and reload later
5880     TRACE_LINEAR_SCAN(4, tty->print_cr("      interval must start in stack slot -> split it before first use"));
5881     assert(cur->assigned_reg() == any_reg && cur->assigned_regHi() == any_reg, "register already assigned");
5882 
5883     allocator()->assign_spill_slot(cur);
5884     split_stack_interval(cur);
5885     result = false;
5886 
5887   } else if (cur->assigned_reg() == any_reg) {
5888     // interval has not assigned register -> normal allocation
5889     // (this is the normal case for most intervals)
5890     TRACE_LINEAR_SCAN(4, tty->print_cr("      normal allocation of register"));
5891 
5892     // assign same spill slot to non-intersecting intervals
5893     combine_spilled_intervals(cur);
5894 
5895     init_vars_for_alloc(cur);
5896     if (no_allocation_possible(cur) || !alloc_free_reg(cur)) {
5897       // no empty register available.
5898       // split and spill another interval so that this interval gets a register
5899       alloc_locked_reg(cur);
5900     }
5901 
5902     // spilled intervals need not be move to active-list
5903     if (cur->assigned_reg() >= LinearScan::nof_regs) {
5904       result = false;
5905     }
5906   }
5907 
5908   // load spilled values that become active from stack slot to register
5909   if (cur->insert_move_when_activated()) {
5910     assert(cur->is_split_child(), "must be");
5911     assert(cur->current_split_child() != NULL, "must be");
5912     assert(cur->current_split_child()->reg_num() != cur->reg_num(), "cannot insert move between same interval");
5913     TRACE_LINEAR_SCAN(4, tty->print_cr("Inserting move from interval %d to %d because insert_move_when_activated is set", cur->current_split_child()->reg_num(), cur->reg_num()));
5914 
5915     insert_move(cur->from(), cur->current_split_child(), cur);
5916   }
5917   cur->make_current_split_child();
5918 
5919   return result; // true = interval is moved to active list
5920 }
5921 
5922 
5923 // Implementation of EdgeMoveOptimizer
5924 
5925 EdgeMoveOptimizer::EdgeMoveOptimizer() :
5926   _edge_instructions(4),
5927   _edge_instructions_idx(4)
5928 {
5929 }
5930 
5931 void EdgeMoveOptimizer::optimize(BlockList* code) {
5932   EdgeMoveOptimizer optimizer = EdgeMoveOptimizer();
5933 
5934   // ignore the first block in the list (index 0 is not processed)
5935   for (int i = code->length() - 1; i >= 1; i--) {
5936     BlockBegin* block = code->at(i);
5937 
5938     if (block->number_of_preds() > 1 && !block->is_set(BlockBegin::exception_entry_flag)) {
5939       optimizer.optimize_moves_at_block_end(block);
5940     }
5941     if (block->number_of_sux() == 2) {
5942       optimizer.optimize_moves_at_block_begin(block);
5943     }
5944   }
5945 }
5946 
5947 
5948 // clear all internal data structures
5949 void EdgeMoveOptimizer::init_instructions() {
5950   _edge_instructions.clear();
5951   _edge_instructions_idx.clear();
5952 }
5953 
5954 // append a lir-instruction-list and the index of the current operation in to the list
5955 void EdgeMoveOptimizer::append_instructions(LIR_OpList* instructions, int instructions_idx) {
5956   _edge_instructions.append(instructions);
5957   _edge_instructions_idx.append(instructions_idx);
5958 }
5959 
5960 // return the current operation of the given edge (predecessor or successor)
5961 LIR_Op* EdgeMoveOptimizer::instruction_at(int edge) {
5962   LIR_OpList* instructions = _edge_instructions.at(edge);
5963   int idx = _edge_instructions_idx.at(edge);
5964 
5965   if (idx < instructions->length()) {
5966     return instructions->at(idx);
5967   } else {
5968     return NULL;
5969   }
5970 }
5971 
5972 // removes the current operation of the given edge (predecessor or successor)
5973 void EdgeMoveOptimizer::remove_cur_instruction(int edge, bool decrement_index) {
5974   LIR_OpList* instructions = _edge_instructions.at(edge);
5975   int idx = _edge_instructions_idx.at(edge);
5976   instructions->remove_at(idx);
5977 
5978   if (decrement_index) {
5979     _edge_instructions_idx.at_put(edge, idx - 1);
5980   }
5981 }
5982 
5983 
5984 bool EdgeMoveOptimizer::operations_different(LIR_Op* op1, LIR_Op* op2) {
5985   if (op1 == NULL || op2 == NULL) {
5986     // at least one block is already empty -> no optimization possible
5987     return true;
5988   }
5989 
5990   if (op1->code() == lir_move && op2->code() == lir_move) {
5991     assert(op1->as_Op1() != NULL, "move must be LIR_Op1");
5992     assert(op2->as_Op1() != NULL, "move must be LIR_Op1");
5993     LIR_Op1* move1 = (LIR_Op1*)op1;
5994     LIR_Op1* move2 = (LIR_Op1*)op2;
5995     if (move1->info() == move2->info() && move1->in_opr() == move2->in_opr() && move1->result_opr() == move2->result_opr()) {
5996       // these moves are exactly equal and can be optimized
5997       return false;
5998     }
5999 
6000   } else if (op1->code() == lir_fxch && op2->code() == lir_fxch) {
6001     assert(op1->as_Op1() != NULL, "fxch must be LIR_Op1");
6002     assert(op2->as_Op1() != NULL, "fxch must be LIR_Op1");
6003     LIR_Op1* fxch1 = (LIR_Op1*)op1;
6004     LIR_Op1* fxch2 = (LIR_Op1*)op2;
6005     if (fxch1->in_opr()->as_jint() == fxch2->in_opr()->as_jint()) {
6006       // equal FPU stack operations can be optimized
6007       return false;
6008     }
6009 
6010   } else if (op1->code() == lir_fpop_raw && op2->code() == lir_fpop_raw) {
6011     // equal FPU stack operations can be optimized
6012     return false;
6013   }
6014 
6015   // no optimization possible
6016   return true;
6017 }
6018 
6019 void EdgeMoveOptimizer::optimize_moves_at_block_end(BlockBegin* block) {
6020   TRACE_LINEAR_SCAN(4, tty->print_cr("optimizing moves at end of block B%d", block->block_id()));
6021 
6022   if (block->is_predecessor(block)) {
6023     // currently we can't handle this correctly.
6024     return;
6025   }
6026 
6027   init_instructions();
6028   int num_preds = block->number_of_preds();
6029   assert(num_preds > 1, "do not call otherwise");
6030   assert(!block->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6031 
6032   // setup a list with the lir-instructions of all predecessors
6033   int i;
6034   for (i = 0; i < num_preds; i++) {
6035     BlockBegin* pred = block->pred_at(i);
6036     LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6037 
6038     if (pred->number_of_sux() != 1) {
6039       // this can happen with switch-statements where multiple edges are between
6040       // the same blocks.
6041       return;
6042     }
6043 
6044     assert(pred->number_of_sux() == 1, "can handle only one successor");
6045     assert(pred->sux_at(0) == block, "invalid control flow");
6046     assert(pred_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6047     assert(pred_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6048     assert(pred_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6049 
6050     if (pred_instructions->last()->info() != NULL) {
6051       // can not optimize instructions when debug info is needed
6052       return;
6053     }
6054 
6055     // ignore the unconditional branch at the end of the block
6056     append_instructions(pred_instructions, pred_instructions->length() - 2);
6057   }
6058 
6059 
6060   // process lir-instructions while all predecessors end with the same instruction
6061   while (true) {
6062     LIR_Op* op = instruction_at(0);
6063     for (i = 1; i < num_preds; i++) {
6064       if (operations_different(op, instruction_at(i))) {
6065         // these instructions are different and cannot be optimized ->
6066         // no further optimization possible
6067         return;
6068       }
6069     }
6070 
6071     TRACE_LINEAR_SCAN(4, tty->print("found instruction that is equal in all %d predecessors: ", num_preds); op->print());
6072 
6073     // insert the instruction at the beginning of the current block
6074     block->lir()->insert_before(1, op);
6075 
6076     // delete the instruction at the end of all predecessors
6077     for (i = 0; i < num_preds; i++) {
6078       remove_cur_instruction(i, true);
6079     }
6080   }
6081 }
6082 
6083 
6084 void EdgeMoveOptimizer::optimize_moves_at_block_begin(BlockBegin* block) {
6085   TRACE_LINEAR_SCAN(4, tty->print_cr("optimization moves at begin of block B%d", block->block_id()));
6086 
6087   init_instructions();
6088   int num_sux = block->number_of_sux();
6089 
6090   LIR_OpList* cur_instructions = block->lir()->instructions_list();
6091 
6092   assert(num_sux == 2, "method should not be called otherwise");
6093   assert(cur_instructions->last()->code() == lir_branch, "block with successor must end with branch");
6094   assert(cur_instructions->last()->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6095   assert(cur_instructions->last()->as_OpBranch()->cond() == lir_cond_always, "block must end with unconditional branch");
6096 
6097   if (cur_instructions->last()->info() != NULL) {
6098     // can no optimize instructions when debug info is needed
6099     return;
6100   }
6101 
6102   LIR_Op* branch = cur_instructions->at(cur_instructions->length() - 2);
6103   if (branch->info() != NULL || (branch->code() != lir_branch && branch->code() != lir_cond_float_branch)) {
6104     // not a valid case for optimization
6105     // currently, only blocks that end with two branches (conditional branch followed
6106     // by unconditional branch) are optimized
6107     return;
6108   }
6109 
6110   // now it is guaranteed that the block ends with two branch instructions.
6111   // the instructions are inserted at the end of the block before these two branches
6112   int insert_idx = cur_instructions->length() - 2;
6113 
6114   int i;
6115 #ifdef ASSERT
6116   for (i = insert_idx - 1; i >= 0; i--) {
6117     LIR_Op* op = cur_instructions->at(i);
6118     if ((op->code() == lir_branch || op->code() == lir_cond_float_branch) && ((LIR_OpBranch*)op)->block() != NULL) {
6119       assert(false, "block with two successors can have only two branch instructions");
6120     }
6121   }
6122 #endif
6123 
6124   // setup a list with the lir-instructions of all successors
6125   for (i = 0; i < num_sux; i++) {
6126     BlockBegin* sux = block->sux_at(i);
6127     LIR_OpList* sux_instructions = sux->lir()->instructions_list();
6128 
6129     assert(sux_instructions->at(0)->code() == lir_label, "block must start with label");
6130 
6131     if (sux->number_of_preds() != 1) {
6132       // this can happen with switch-statements where multiple edges are between
6133       // the same blocks.
6134       return;
6135     }
6136     assert(sux->pred_at(0) == block, "invalid control flow");
6137     assert(!sux->is_set(BlockBegin::exception_entry_flag), "exception handlers not allowed");
6138 
6139     // ignore the label at the beginning of the block
6140     append_instructions(sux_instructions, 1);
6141   }
6142 
6143   // process lir-instructions while all successors begin with the same instruction
6144   while (true) {
6145     LIR_Op* op = instruction_at(0);
6146     for (i = 1; i < num_sux; i++) {
6147       if (operations_different(op, instruction_at(i))) {
6148         // these instructions are different and cannot be optimized ->
6149         // no further optimization possible
6150         return;
6151       }
6152     }
6153 
6154     TRACE_LINEAR_SCAN(4, tty->print("----- found instruction that is equal in all %d successors: ", num_sux); op->print());
6155 
6156     // insert instruction at end of current block
6157     block->lir()->insert_before(insert_idx, op);
6158     insert_idx++;
6159 
6160     // delete the instructions at the beginning of all successors
6161     for (i = 0; i < num_sux; i++) {
6162       remove_cur_instruction(i, false);
6163     }
6164   }
6165 }
6166 
6167 
6168 // Implementation of ControlFlowOptimizer
6169 
6170 ControlFlowOptimizer::ControlFlowOptimizer() :
6171   _original_preds(4)
6172 {
6173 }
6174 
6175 void ControlFlowOptimizer::optimize(BlockList* code) {
6176   ControlFlowOptimizer optimizer = ControlFlowOptimizer();
6177 
6178   // push the OSR entry block to the end so that we're not jumping over it.
6179   BlockBegin* osr_entry = code->at(0)->end()->as_Base()->osr_entry();
6180   if (osr_entry) {
6181     int index = osr_entry->linear_scan_number();
6182     assert(code->at(index) == osr_entry, "wrong index");
6183     code->remove_at(index);
6184     code->append(osr_entry);
6185   }
6186 
6187   optimizer.reorder_short_loops(code);
6188   optimizer.delete_empty_blocks(code);
6189   optimizer.delete_unnecessary_jumps(code);
6190   optimizer.delete_jumps_to_return(code);
6191 }
6192 
6193 void ControlFlowOptimizer::reorder_short_loop(BlockList* code, BlockBegin* header_block, int header_idx) {
6194   int i = header_idx + 1;
6195   int max_end = MIN2(header_idx + ShortLoopSize, code->length());
6196   while (i < max_end && code->at(i)->loop_depth() >= header_block->loop_depth()) {
6197     i++;
6198   }
6199 
6200   if (i == code->length() || code->at(i)->loop_depth() < header_block->loop_depth()) {
6201     int end_idx = i - 1;
6202     BlockBegin* end_block = code->at(end_idx);
6203 
6204     if (end_block->number_of_sux() == 1 && end_block->sux_at(0) == header_block) {
6205       // short loop from header_idx to end_idx found -> reorder blocks such that
6206       // the header_block is the last block instead of the first block of the loop
6207       TRACE_LINEAR_SCAN(1, tty->print_cr("Reordering short loop: length %d, header B%d, end B%d",
6208                                          end_idx - header_idx + 1,
6209                                          header_block->block_id(), end_block->block_id()));
6210 
6211       for (int j = header_idx; j < end_idx; j++) {
6212         code->at_put(j, code->at(j + 1));
6213       }
6214       code->at_put(end_idx, header_block);
6215 
6216       // correct the flags so that any loop alignment occurs in the right place.
6217       assert(code->at(end_idx)->is_set(BlockBegin::backward_branch_target_flag), "must be backward branch target");
6218       code->at(end_idx)->clear(BlockBegin::backward_branch_target_flag);
6219       code->at(header_idx)->set(BlockBegin::backward_branch_target_flag);
6220     }
6221   }
6222 }
6223 
6224 void ControlFlowOptimizer::reorder_short_loops(BlockList* code) {
6225   for (int i = code->length() - 1; i >= 0; i--) {
6226     BlockBegin* block = code->at(i);
6227 
6228     if (block->is_set(BlockBegin::linear_scan_loop_header_flag)) {
6229       reorder_short_loop(code, block, i);
6230     }
6231   }
6232 
6233   DEBUG_ONLY(verify(code));
6234 }
6235 
6236 // only blocks with exactly one successor can be deleted. Such blocks
6237 // must always end with an unconditional branch to this successor
6238 bool ControlFlowOptimizer::can_delete_block(BlockBegin* block) {
6239   if (block->number_of_sux() != 1 || block->number_of_exception_handlers() != 0 || block->is_entry_block()) {
6240     return false;
6241   }
6242 
6243   LIR_OpList* instructions = block->lir()->instructions_list();
6244 
6245   assert(instructions->length() >= 2, "block must have label and branch");
6246   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6247   assert(instructions->last()->as_OpBranch() != NULL, "last instruction must always be a branch");
6248   assert(instructions->last()->as_OpBranch()->cond() == lir_cond_always, "branch must be unconditional");
6249   assert(instructions->last()->as_OpBranch()->block() == block->sux_at(0), "branch target must be the successor");
6250 
6251   // block must have exactly one successor
6252 
6253   if (instructions->length() == 2 && instructions->last()->info() == NULL) {
6254     return true;
6255   }
6256   return false;
6257 }
6258 
6259 // substitute branch targets in all branch-instructions of this blocks
6260 void ControlFlowOptimizer::substitute_branch_target(BlockBegin* block, BlockBegin* target_from, BlockBegin* target_to) {
6261   TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting empty block: substituting from B%d to B%d inside B%d", target_from->block_id(), target_to->block_id(), block->block_id()));
6262 
6263   LIR_OpList* instructions = block->lir()->instructions_list();
6264 
6265   assert(instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6266   for (int i = instructions->length() - 1; i >= 1; i--) {
6267     LIR_Op* op = instructions->at(i);
6268 
6269     if (op->code() == lir_branch || op->code() == lir_cond_float_branch) {
6270       assert(op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6271       LIR_OpBranch* branch = (LIR_OpBranch*)op;
6272 
6273       if (branch->block() == target_from) {
6274         branch->change_block(target_to);
6275       }
6276       if (branch->ublock() == target_from) {
6277         branch->change_ublock(target_to);
6278       }
6279     }
6280   }
6281 }
6282 
6283 void ControlFlowOptimizer::delete_empty_blocks(BlockList* code) {
6284   int old_pos = 0;
6285   int new_pos = 0;
6286   int num_blocks = code->length();
6287 
6288   while (old_pos < num_blocks) {
6289     BlockBegin* block = code->at(old_pos);
6290 
6291     if (can_delete_block(block)) {
6292       BlockBegin* new_target = block->sux_at(0);
6293 
6294       // propagate backward branch target flag for correct code alignment
6295       if (block->is_set(BlockBegin::backward_branch_target_flag)) {
6296         new_target->set(BlockBegin::backward_branch_target_flag);
6297       }
6298 
6299       // collect a list with all predecessors that contains each predecessor only once
6300       // the predecessors of cur are changed during the substitution, so a copy of the
6301       // predecessor list is necessary
6302       int j;
6303       _original_preds.clear();
6304       for (j = block->number_of_preds() - 1; j >= 0; j--) {
6305         BlockBegin* pred = block->pred_at(j);
6306         if (_original_preds.find(pred) == -1) {
6307           _original_preds.append(pred);
6308         }
6309       }
6310 
6311       for (j = _original_preds.length() - 1; j >= 0; j--) {
6312         BlockBegin* pred = _original_preds.at(j);
6313         substitute_branch_target(pred, block, new_target);
6314         pred->substitute_sux(block, new_target);
6315       }
6316     } else {
6317       // adjust position of this block in the block list if blocks before
6318       // have been deleted
6319       if (new_pos != old_pos) {
6320         code->at_put(new_pos, code->at(old_pos));
6321       }
6322       new_pos++;
6323     }
6324     old_pos++;
6325   }
6326   code->trunc_to(new_pos);
6327 
6328   DEBUG_ONLY(verify(code));
6329 }
6330 
6331 void ControlFlowOptimizer::delete_unnecessary_jumps(BlockList* code) {
6332   // skip the last block because there a branch is always necessary
6333   for (int i = code->length() - 2; i >= 0; i--) {
6334     BlockBegin* block = code->at(i);
6335     LIR_OpList* instructions = block->lir()->instructions_list();
6336 
6337     LIR_Op* last_op = instructions->last();
6338     if (last_op->code() == lir_branch) {
6339       assert(last_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6340       LIR_OpBranch* last_branch = (LIR_OpBranch*)last_op;
6341 
6342       assert(last_branch->block() != NULL, "last branch must always have a block as target");
6343       assert(last_branch->label() == last_branch->block()->label(), "must be equal");
6344 
6345       if (last_branch->info() == NULL) {
6346         if (last_branch->block() == code->at(i + 1)) {
6347 
6348           TRACE_LINEAR_SCAN(3, tty->print_cr("Deleting unconditional branch at end of block B%d", block->block_id()));
6349 
6350           // delete last branch instruction
6351           instructions->trunc_to(instructions->length() - 1);
6352 
6353         } else {
6354           LIR_Op* prev_op = instructions->at(instructions->length() - 2);
6355           if (prev_op->code() == lir_branch || prev_op->code() == lir_cond_float_branch) {
6356             assert(prev_op->as_OpBranch() != NULL, "branch must be of type LIR_OpBranch");
6357             LIR_OpBranch* prev_branch = (LIR_OpBranch*)prev_op;
6358 
6359             if (prev_branch->stub() == NULL) {
6360 
6361               LIR_Op2* prev_cmp = NULL;
6362               // There might be a cmove inserted for profiling which depends on the same
6363               // compare. If we change the condition of the respective compare, we have
6364               // to take care of this cmove as well.
6365               LIR_Op4* prev_cmove = NULL;
6366 
6367               for(int j = instructions->length() - 3; j >= 0 && prev_cmp == NULL; j--) {
6368                 prev_op = instructions->at(j);
6369                 // check for the cmove
6370                 if (prev_op->code() == lir_cmove) {
6371                   assert(prev_op->as_Op4() != NULL, "cmove must be of type LIR_Op4");
6372                   prev_cmove = (LIR_Op4*)prev_op;
6373                   assert(prev_branch->cond() == prev_cmove->condition(), "should be the same");
6374                 }
6375                 if (prev_op->code() == lir_cmp) {
6376                   assert(prev_op->as_Op2() != NULL, "branch must be of type LIR_Op2");
6377                   prev_cmp = (LIR_Op2*)prev_op;
6378                   assert(prev_branch->cond() == prev_cmp->condition(), "should be the same");
6379                 }
6380               }
6381               // Guarantee because it is dereferenced below.
6382               guarantee(prev_cmp != NULL, "should have found comp instruction for branch");
6383               if (prev_branch->block() == code->at(i + 1) && prev_branch->info() == NULL) {
6384 
6385                 TRACE_LINEAR_SCAN(3, tty->print_cr("Negating conditional branch and deleting unconditional branch at end of block B%d", block->block_id()));
6386 
6387                 // eliminate a conditional branch to the immediate successor
6388                 prev_branch->change_block(last_branch->block());
6389                 prev_branch->negate_cond();
6390                 prev_cmp->set_condition(prev_branch->cond());
6391                 instructions->trunc_to(instructions->length() - 1);
6392                 // if we do change the condition, we have to change the cmove as well
6393                 if (prev_cmove != NULL) {
6394                   prev_cmove->set_condition(prev_branch->cond());
6395                   LIR_Opr t = prev_cmove->in_opr1();
6396                   prev_cmove->set_in_opr1(prev_cmove->in_opr2());
6397                   prev_cmove->set_in_opr2(t);
6398                 }
6399               }
6400             }
6401           }
6402         }
6403       }
6404     }
6405   }
6406 
6407   DEBUG_ONLY(verify(code));
6408 }
6409 
6410 void ControlFlowOptimizer::delete_jumps_to_return(BlockList* code) {
6411 #ifdef ASSERT
6412   ResourceBitMap return_converted(BlockBegin::number_of_blocks());
6413 #endif
6414 
6415   for (int i = code->length() - 1; i >= 0; i--) {
6416     BlockBegin* block = code->at(i);
6417     LIR_OpList* cur_instructions = block->lir()->instructions_list();
6418     LIR_Op*     cur_last_op = cur_instructions->last();
6419 
6420     assert(cur_instructions->at(0)->code() == lir_label, "first instruction must always be a label");
6421     if (cur_instructions->length() == 2 && cur_last_op->code() == lir_return) {
6422       // the block contains only a label and a return
6423       // if a predecessor ends with an unconditional jump to this block, then the jump
6424       // can be replaced with a return instruction
6425       //
6426       // Note: the original block with only a return statement cannot be deleted completely
6427       //       because the predecessors might have other (conditional) jumps to this block
6428       //       -> this may lead to unnecessary return instructions in the final code
6429 
6430       assert(cur_last_op->info() == NULL, "return instructions do not have debug information");
6431       assert(block->number_of_sux() == 0 ||
6432              (return_converted.at(block->block_id()) && block->number_of_sux() == 1),
6433              "blocks that end with return must not have successors");
6434 
6435       assert(cur_last_op->as_Op1() != NULL, "return must be LIR_Op1");
6436       LIR_Opr return_opr = ((LIR_Op1*)cur_last_op)->in_opr();
6437 
6438       for (int j = block->number_of_preds() - 1; j >= 0; j--) {
6439         BlockBegin* pred = block->pred_at(j);
6440         LIR_OpList* pred_instructions = pred->lir()->instructions_list();
6441         LIR_Op*     pred_last_op = pred_instructions->last();
6442 
6443         if (pred_last_op->code() == lir_branch) {
6444           assert(pred_last_op->as_OpBranch() != NULL, "branch must be LIR_OpBranch");
6445           LIR_OpBranch* pred_last_branch = (LIR_OpBranch*)pred_last_op;
6446 
6447           if (pred_last_branch->block() == block && pred_last_branch->cond() == lir_cond_always && pred_last_branch->info() == NULL) {
6448             // replace the jump to a return with a direct return
6449             // Note: currently the edge between the blocks is not deleted
6450             pred_instructions->at_put(pred_instructions->length() - 1, new LIR_OpReturn(return_opr));
6451 #ifdef ASSERT
6452             return_converted.set_bit(pred->block_id());
6453 #endif
6454           }
6455         }
6456       }
6457     }
6458   }
6459 }
6460 
6461 
6462 #ifdef ASSERT
6463 void ControlFlowOptimizer::verify(BlockList* code) {
6464   for (int i = 0; i < code->length(); i++) {
6465     BlockBegin* block = code->at(i);
6466     LIR_OpList* instructions = block->lir()->instructions_list();
6467 
6468     int j;
6469     for (j = 0; j < instructions->length(); j++) {
6470       LIR_OpBranch* op_branch = instructions->at(j)->as_OpBranch();
6471 
6472       if (op_branch != NULL) {
6473         assert(op_branch->block() == NULL || code->find(op_branch->block()) != -1, "branch target not valid");
6474         assert(op_branch->ublock() == NULL || code->find(op_branch->ublock()) != -1, "branch target not valid");
6475       }
6476     }
6477 
6478     for (j = 0; j < block->number_of_sux() - 1; j++) {
6479       BlockBegin* sux = block->sux_at(j);
6480       assert(code->find(sux) != -1, "successor not valid");
6481     }
6482 
6483     for (j = 0; j < block->number_of_preds() - 1; j++) {
6484       BlockBegin* pred = block->pred_at(j);
6485       assert(code->find(pred) != -1, "successor not valid");
6486     }
6487   }
6488 }
6489 #endif
6490 
6491 
6492 #ifndef PRODUCT
6493 
6494 // Implementation of LinearStatistic
6495 
6496 const char* LinearScanStatistic::counter_name(int counter_idx) {
6497   switch (counter_idx) {
6498     case counter_method:          return "compiled methods";
6499     case counter_fpu_method:      return "methods using fpu";
6500     case counter_loop_method:     return "methods with loops";
6501     case counter_exception_method:return "methods with xhandler";
6502 
6503     case counter_loop:            return "loops";
6504     case counter_block:           return "blocks";
6505     case counter_loop_block:      return "blocks inside loop";
6506     case counter_exception_block: return "exception handler entries";
6507     case counter_interval:        return "intervals";
6508     case counter_fixed_interval:  return "fixed intervals";
6509     case counter_range:           return "ranges";
6510     case counter_fixed_range:     return "fixed ranges";
6511     case counter_use_pos:         return "use positions";
6512     case counter_fixed_use_pos:   return "fixed use positions";
6513     case counter_spill_slots:     return "spill slots";
6514 
6515     // counter for classes of lir instructions
6516     case counter_instruction:     return "total instructions";
6517     case counter_label:           return "labels";
6518     case counter_entry:           return "method entries";
6519     case counter_return:          return "method returns";
6520     case counter_call:            return "method calls";
6521     case counter_move:            return "moves";
6522     case counter_cmp:             return "compare";
6523     case counter_cond_branch:     return "conditional branches";
6524     case counter_uncond_branch:   return "unconditional branches";
6525     case counter_stub_branch:     return "branches to stub";
6526     case counter_alu:             return "artithmetic + logic";
6527     case counter_alloc:           return "allocations";
6528     case counter_sync:            return "synchronisation";
6529     case counter_throw:           return "throw";
6530     case counter_unwind:          return "unwind";
6531     case counter_typecheck:       return "type+null-checks";
6532     case counter_fpu_stack:       return "fpu-stack";
6533     case counter_misc_inst:       return "other instructions";
6534     case counter_other_inst:      return "misc. instructions";
6535 
6536     // counter for different types of moves
6537     case counter_move_total:      return "total moves";
6538     case counter_move_reg_reg:    return "register->register";
6539     case counter_move_reg_stack:  return "register->stack";
6540     case counter_move_stack_reg:  return "stack->register";
6541     case counter_move_stack_stack:return "stack->stack";
6542     case counter_move_reg_mem:    return "register->memory";
6543     case counter_move_mem_reg:    return "memory->register";
6544     case counter_move_const_any:  return "constant->any";
6545 
6546     case blank_line_1:            return "";
6547     case blank_line_2:            return "";
6548 
6549     default: ShouldNotReachHere(); return "";
6550   }
6551 }
6552 
6553 LinearScanStatistic::Counter LinearScanStatistic::base_counter(int counter_idx) {
6554   if (counter_idx == counter_fpu_method || counter_idx == counter_loop_method || counter_idx == counter_exception_method) {
6555     return counter_method;
6556   } else if (counter_idx == counter_loop_block || counter_idx == counter_exception_block) {
6557     return counter_block;
6558   } else if (counter_idx >= counter_instruction && counter_idx <= counter_other_inst) {
6559     return counter_instruction;
6560   } else if (counter_idx >= counter_move_total && counter_idx <= counter_move_const_any) {
6561     return counter_move_total;
6562   }
6563   return invalid_counter;
6564 }
6565 
6566 LinearScanStatistic::LinearScanStatistic() {
6567   for (int i = 0; i < number_of_counters; i++) {
6568     _counters_sum[i] = 0;
6569     _counters_max[i] = -1;
6570   }
6571 
6572 }
6573 
6574 // add the method-local numbers to the total sum
6575 void LinearScanStatistic::sum_up(LinearScanStatistic &method_statistic) {
6576   for (int i = 0; i < number_of_counters; i++) {
6577     _counters_sum[i] += method_statistic._counters_sum[i];
6578     _counters_max[i] = MAX2(_counters_max[i], method_statistic._counters_sum[i]);
6579   }
6580 }
6581 
6582 void LinearScanStatistic::print(const char* title) {
6583   if (CountLinearScan || TraceLinearScanLevel > 0) {
6584     tty->cr();
6585     tty->print_cr("***** LinearScan statistic - %s *****", title);
6586 
6587     for (int i = 0; i < number_of_counters; i++) {
6588       if (_counters_sum[i] > 0 || _counters_max[i] >= 0) {
6589         tty->print("%25s: %8d", counter_name(i), _counters_sum[i]);
6590 
6591         LinearScanStatistic::Counter cntr = base_counter(i);
6592         if (cntr != invalid_counter) {
6593           tty->print("  (%5.1f%%) ", _counters_sum[i] * 100.0 / _counters_sum[cntr]);
6594         } else {
6595           tty->print("           ");
6596         }
6597 
6598         if (_counters_max[i] >= 0) {
6599           tty->print("%8d", _counters_max[i]);
6600         }
6601       }
6602       tty->cr();
6603     }
6604   }
6605 }
6606 
6607 void LinearScanStatistic::collect(LinearScan* allocator) {
6608   inc_counter(counter_method);
6609   if (allocator->has_fpu_registers()) {
6610     inc_counter(counter_fpu_method);
6611   }
6612   if (allocator->num_loops() > 0) {
6613     inc_counter(counter_loop_method);
6614   }
6615   inc_counter(counter_loop, allocator->num_loops());
6616   inc_counter(counter_spill_slots, allocator->max_spills());
6617 
6618   int i;
6619   for (i = 0; i < allocator->interval_count(); i++) {
6620     Interval* cur = allocator->interval_at(i);
6621 
6622     if (cur != NULL) {
6623       inc_counter(counter_interval);
6624       inc_counter(counter_use_pos, cur->num_use_positions());
6625       if (LinearScan::is_precolored_interval(cur)) {
6626         inc_counter(counter_fixed_interval);
6627         inc_counter(counter_fixed_use_pos, cur->num_use_positions());
6628       }
6629 
6630       Range* range = cur->first();
6631       while (range != Range::end()) {
6632         inc_counter(counter_range);
6633         if (LinearScan::is_precolored_interval(cur)) {
6634           inc_counter(counter_fixed_range);
6635         }
6636         range = range->next();
6637       }
6638     }
6639   }
6640 
6641   bool has_xhandlers = false;
6642   // Note: only count blocks that are in code-emit order
6643   for (i = 0; i < allocator->ir()->code()->length(); i++) {
6644     BlockBegin* cur = allocator->ir()->code()->at(i);
6645 
6646     inc_counter(counter_block);
6647     if (cur->loop_depth() > 0) {
6648       inc_counter(counter_loop_block);
6649     }
6650     if (cur->is_set(BlockBegin::exception_entry_flag)) {
6651       inc_counter(counter_exception_block);
6652       has_xhandlers = true;
6653     }
6654 
6655     LIR_OpList* instructions = cur->lir()->instructions_list();
6656     for (int j = 0; j < instructions->length(); j++) {
6657       LIR_Op* op = instructions->at(j);
6658 
6659       inc_counter(counter_instruction);
6660 
6661       switch (op->code()) {
6662         case lir_label:           inc_counter(counter_label); break;
6663         case lir_std_entry:
6664         case lir_osr_entry:       inc_counter(counter_entry); break;
6665         case lir_return:          inc_counter(counter_return); break;
6666 
6667         case lir_rtcall:
6668         case lir_static_call:
6669         case lir_optvirtual_call: inc_counter(counter_call); break;
6670 
6671         case lir_move: {
6672           inc_counter(counter_move);
6673           inc_counter(counter_move_total);
6674 
6675           LIR_Opr in = op->as_Op1()->in_opr();
6676           LIR_Opr res = op->as_Op1()->result_opr();
6677           if (in->is_register()) {
6678             if (res->is_register()) {
6679               inc_counter(counter_move_reg_reg);
6680             } else if (res->is_stack()) {
6681               inc_counter(counter_move_reg_stack);
6682             } else if (res->is_address()) {
6683               inc_counter(counter_move_reg_mem);
6684             } else {
6685               ShouldNotReachHere();
6686             }
6687           } else if (in->is_stack()) {
6688             if (res->is_register()) {
6689               inc_counter(counter_move_stack_reg);
6690             } else {
6691               inc_counter(counter_move_stack_stack);
6692             }
6693           } else if (in->is_address()) {
6694             assert(res->is_register(), "must be");
6695             inc_counter(counter_move_mem_reg);
6696           } else if (in->is_constant()) {
6697             inc_counter(counter_move_const_any);
6698           } else {
6699             ShouldNotReachHere();
6700           }
6701           break;
6702         }
6703 
6704         case lir_cmp:             inc_counter(counter_cmp); break;
6705 
6706         case lir_branch:
6707         case lir_cond_float_branch: {
6708           LIR_OpBranch* branch = op->as_OpBranch();
6709           if (branch->block() == NULL) {
6710             inc_counter(counter_stub_branch);
6711           } else if (branch->cond() == lir_cond_always) {
6712             inc_counter(counter_uncond_branch);
6713           } else {
6714             inc_counter(counter_cond_branch);
6715           }
6716           break;
6717         }
6718 
6719         case lir_neg:
6720         case lir_add:
6721         case lir_sub:
6722         case lir_mul:
6723         case lir_div:
6724         case lir_rem:
6725         case lir_sqrt:
6726         case lir_abs:
6727         case lir_log10:
6728         case lir_logic_and:
6729         case lir_logic_or:
6730         case lir_logic_xor:
6731         case lir_shl:
6732         case lir_shr:
6733         case lir_ushr:            inc_counter(counter_alu); break;
6734 
6735         case lir_alloc_object:
6736         case lir_alloc_array:     inc_counter(counter_alloc); break;
6737 
6738         case lir_monaddr:
6739         case lir_lock:
6740         case lir_unlock:          inc_counter(counter_sync); break;
6741 
6742         case lir_throw:           inc_counter(counter_throw); break;
6743 
6744         case lir_unwind:          inc_counter(counter_unwind); break;
6745 
6746         case lir_null_check:
6747         case lir_leal:
6748         case lir_instanceof:
6749         case lir_checkcast:
6750         case lir_store_check:     inc_counter(counter_typecheck); break;
6751 
6752         case lir_fpop_raw:
6753         case lir_fxch:
6754         case lir_fld:             inc_counter(counter_fpu_stack); break;
6755 
6756         case lir_nop:
6757         case lir_push:
6758         case lir_pop:
6759         case lir_convert:
6760         case lir_roundfp:
6761         case lir_cmove:           inc_counter(counter_misc_inst); break;
6762 
6763         default:                  inc_counter(counter_other_inst); break;
6764       }
6765     }
6766   }
6767 
6768   if (has_xhandlers) {
6769     inc_counter(counter_exception_method);
6770   }
6771 }
6772 
6773 void LinearScanStatistic::compute(LinearScan* allocator, LinearScanStatistic &global_statistic) {
6774   if (CountLinearScan || TraceLinearScanLevel > 0) {
6775 
6776     LinearScanStatistic local_statistic = LinearScanStatistic();
6777 
6778     local_statistic.collect(allocator);
6779     global_statistic.sum_up(local_statistic);
6780 
6781     if (TraceLinearScanLevel > 2) {
6782       local_statistic.print("current local statistic");
6783     }
6784   }
6785 }
6786 
6787 
6788 // Implementation of LinearTimers
6789 
6790 LinearScanTimers::LinearScanTimers() {
6791   for (int i = 0; i < number_of_timers; i++) {
6792     timer(i)->reset();
6793   }
6794 }
6795 
6796 const char* LinearScanTimers::timer_name(int idx) {
6797   switch (idx) {
6798     case timer_do_nothing:               return "Nothing (Time Check)";
6799     case timer_number_instructions:      return "Number Instructions";
6800     case timer_compute_local_live_sets:  return "Local Live Sets";
6801     case timer_compute_global_live_sets: return "Global Live Sets";
6802     case timer_build_intervals:          return "Build Intervals";
6803     case timer_sort_intervals_before:    return "Sort Intervals Before";
6804     case timer_allocate_registers:       return "Allocate Registers";
6805     case timer_resolve_data_flow:        return "Resolve Data Flow";
6806     case timer_sort_intervals_after:     return "Sort Intervals After";
6807     case timer_eliminate_spill_moves:    return "Spill optimization";
6808     case timer_assign_reg_num:           return "Assign Reg Num";
6809     case timer_allocate_fpu_stack:       return "Allocate FPU Stack";
6810     case timer_optimize_lir:             return "Optimize LIR";
6811     default: ShouldNotReachHere();       return "";
6812   }
6813 }
6814 
6815 void LinearScanTimers::begin_method() {
6816   if (TimeEachLinearScan) {
6817     // reset all timers to measure only current method
6818     for (int i = 0; i < number_of_timers; i++) {
6819       timer(i)->reset();
6820     }
6821   }
6822 }
6823 
6824 void LinearScanTimers::end_method(LinearScan* allocator) {
6825   if (TimeEachLinearScan) {
6826 
6827     double c = timer(timer_do_nothing)->seconds();
6828     double total = 0;
6829     for (int i = 1; i < number_of_timers; i++) {
6830       total += timer(i)->seconds() - c;
6831     }
6832 
6833     if (total >= 0.0005) {
6834       // print all information in one line for automatic processing
6835       tty->print("@"); allocator->compilation()->method()->print_name();
6836 
6837       tty->print("@ %d ", allocator->compilation()->method()->code_size());
6838       tty->print("@ %d ", allocator->block_at(allocator->block_count() - 1)->last_lir_instruction_id() / 2);
6839       tty->print("@ %d ", allocator->block_count());
6840       tty->print("@ %d ", allocator->num_virtual_regs());
6841       tty->print("@ %d ", allocator->interval_count());
6842       tty->print("@ %d ", allocator->_num_calls);
6843       tty->print("@ %d ", allocator->num_loops());
6844 
6845       tty->print("@ %6.6f ", total);
6846       for (int i = 1; i < number_of_timers; i++) {
6847         tty->print("@ %4.1f ", ((timer(i)->seconds() - c) / total) * 100);
6848       }
6849       tty->cr();
6850     }
6851   }
6852 }
6853 
6854 void LinearScanTimers::print(double total_time) {
6855   if (TimeLinearScan) {
6856     // correction value: sum of dummy-timer that only measures the time that
6857     // is necessary to start and stop itself
6858     double c = timer(timer_do_nothing)->seconds();
6859 
6860     for (int i = 0; i < number_of_timers; i++) {
6861       double t = timer(i)->seconds();
6862       tty->print_cr("    %25s: %6.3f s (%4.1f%%)  corrected: %6.3f s (%4.1f%%)", timer_name(i), t, (t / total_time) * 100.0, t - c, (t - c) / (total_time - 2 * number_of_timers * c) * 100);
6863     }
6864   }
6865 }
6866 
6867 #endif // #ifndef PRODUCT