1 /*
   2  * Copyright (c) 2000, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "asm/assembler.hpp"
  29 #include "c1/c1_CodeStubs.hpp"
  30 #include "c1/c1_Compilation.hpp"
  31 #include "c1/c1_LIRAssembler.hpp"
  32 #include "c1/c1_MacroAssembler.hpp"
  33 #include "c1/c1_Runtime1.hpp"
  34 #include "c1/c1_ValueStack.hpp"
  35 #include "ci/ciArrayKlass.hpp"
  36 #include "ci/ciInstance.hpp"
  37 #include "code/compiledIC.hpp"
  38 #include "gc/shared/collectedHeap.hpp"
  39 #include "gc/shared/gc_globals.hpp"
  40 #include "nativeInst_aarch64.hpp"
  41 #include "oops/objArrayKlass.hpp"
  42 #include "runtime/frame.inline.hpp"
  43 #include "runtime/sharedRuntime.hpp"
  44 #include "runtime/stubRoutines.hpp"
  45 #include "utilities/powerOfTwo.hpp"
  46 #include "vmreg_aarch64.inline.hpp"
  47 
  48 
  49 #ifndef PRODUCT
  50 #define COMMENT(x)   do { __ block_comment(x); } while (0)
  51 #else
  52 #define COMMENT(x)
  53 #endif
  54 
  55 NEEDS_CLEANUP // remove this definitions ?
  56 const Register IC_Klass    = rscratch2;   // where the IC klass is cached
  57 const Register SYNC_header = r0;   // synchronization header
  58 const Register SHIFT_count = r0;   // where count for shift operations must be
  59 
  60 #define __ _masm->
  61 
  62 
  63 static void select_different_registers(Register preserve,
  64                                        Register extra,
  65                                        Register &tmp1,
  66                                        Register &tmp2) {
  67   if (tmp1 == preserve) {
  68     assert_different_registers(tmp1, tmp2, extra);
  69     tmp1 = extra;
  70   } else if (tmp2 == preserve) {
  71     assert_different_registers(tmp1, tmp2, extra);
  72     tmp2 = extra;
  73   }
  74   assert_different_registers(preserve, tmp1, tmp2);
  75 }
  76 
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2,
  83                                        Register &tmp3) {
  84   if (tmp1 == preserve) {
  85     assert_different_registers(tmp1, tmp2, tmp3, extra);
  86     tmp1 = extra;
  87   } else if (tmp2 == preserve) {
  88     assert_different_registers(tmp1, tmp2, tmp3, extra);
  89     tmp2 = extra;
  90   } else if (tmp3 == preserve) {
  91     assert_different_registers(tmp1, tmp2, tmp3, extra);
  92     tmp3 = extra;
  93   }
  94   assert_different_registers(preserve, tmp1, tmp2, tmp3);
  95 }
  96 
  97 
  98 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { Unimplemented(); return false; }
  99 
 100 
 101 LIR_Opr LIR_Assembler::receiverOpr() {
 102   return FrameMap::receiver_opr;
 103 }
 104 
 105 LIR_Opr LIR_Assembler::osrBufferPointer() {
 106   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 107 }
 108 
 109 //--------------fpu register translations-----------------------
 110 
 111 
 112 address LIR_Assembler::float_constant(float f) {
 113   address const_addr = __ float_constant(f);
 114   if (const_addr == NULL) {
 115     bailout("const section overflow");
 116     return __ code()->consts()->start();
 117   } else {
 118     return const_addr;
 119   }
 120 }
 121 
 122 
 123 address LIR_Assembler::double_constant(double d) {
 124   address const_addr = __ double_constant(d);
 125   if (const_addr == NULL) {
 126     bailout("const section overflow");
 127     return __ code()->consts()->start();
 128   } else {
 129     return const_addr;
 130   }
 131 }
 132 
 133 address LIR_Assembler::int_constant(jlong n) {
 134   address const_addr = __ long_constant(n);
 135   if (const_addr == NULL) {
 136     bailout("const section overflow");
 137     return __ code()->consts()->start();
 138   } else {
 139     return const_addr;
 140   }
 141 }
 142 
 143 void LIR_Assembler::breakpoint() { Unimplemented(); }
 144 
 145 void LIR_Assembler::push(LIR_Opr opr) { Unimplemented(); }
 146 
 147 void LIR_Assembler::pop(LIR_Opr opr) { Unimplemented(); }
 148 
 149 bool LIR_Assembler::is_literal_address(LIR_Address* addr) { Unimplemented(); return false; }
 150 //-------------------------------------------
 151 
 152 static Register as_reg(LIR_Opr op) {
 153   return op->is_double_cpu() ? op->as_register_lo() : op->as_register();
 154 }
 155 
 156 static jlong as_long(LIR_Opr data) {
 157   jlong result;
 158   switch (data->type()) {
 159   case T_INT:
 160     result = (data->as_jint());
 161     break;
 162   case T_LONG:
 163     result = (data->as_jlong());
 164     break;
 165   default:
 166     ShouldNotReachHere();
 167     result = 0;  // unreachable
 168   }
 169   return result;
 170 }
 171 
 172 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 173   Register base = addr->base()->as_pointer_register();
 174   LIR_Opr opr = addr->index();
 175   if (opr->is_cpu_register()) {
 176     Register index;
 177     if (opr->is_single_cpu())
 178       index = opr->as_register();
 179     else
 180       index = opr->as_register_lo();
 181     assert(addr->disp() == 0, "must be");
 182     switch(opr->type()) {
 183       case T_INT:
 184         return Address(base, index, Address::sxtw(addr->scale()));
 185       case T_LONG:
 186         return Address(base, index, Address::lsl(addr->scale()));
 187       default:
 188         ShouldNotReachHere();
 189       }
 190   } else  {
 191     intptr_t addr_offset = intptr_t(addr->disp());
 192     if (Address::offset_ok_for_immed(addr_offset, addr->scale()))
 193       return Address(base, addr_offset, Address::lsl(addr->scale()));
 194     else {
 195       __ mov(tmp, addr_offset);
 196       return Address(base, tmp, Address::lsl(addr->scale()));
 197     }
 198   }
 199   return Address();
 200 }
 201 
 202 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 203   ShouldNotReachHere();
 204   return Address();
 205 }
 206 
 207 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 208   return as_Address(addr, rscratch1);
 209 }
 210 
 211 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 212   return as_Address(addr, rscratch1);  // Ouch
 213   // FIXME: This needs to be much more clever.  See x86.
 214 }
 215 
 216 // Ensure a valid Address (base + offset) to a stack-slot. If stack access is
 217 // not encodable as a base + (immediate) offset, generate an explicit address
 218 // calculation to hold the address in a temporary register.
 219 Address LIR_Assembler::stack_slot_address(int index, uint size, Register tmp, int adjust) {
 220   precond(size == 4 || size == 8);
 221   Address addr = frame_map()->address_for_slot(index, adjust);
 222   precond(addr.getMode() == Address::base_plus_offset);
 223   precond(addr.base() == sp);
 224   precond(addr.offset() > 0);
 225   uint mask = size - 1;
 226   assert((addr.offset() & mask) == 0, "scaled offsets only");
 227   return __ legitimize_address(addr, size, tmp);
 228 }
 229 
 230 void LIR_Assembler::osr_entry() {
 231   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 232   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 233   ValueStack* entry_state = osr_entry->state();
 234   int number_of_locks = entry_state->locks_size();
 235 
 236   // we jump here if osr happens with the interpreter
 237   // state set up to continue at the beginning of the
 238   // loop that triggered osr - in particular, we have
 239   // the following registers setup:
 240   //
 241   // r2: osr buffer
 242   //
 243 
 244   // build frame
 245   ciMethod* m = compilation()->method();
 246   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 247 
 248   // OSR buffer is
 249   //
 250   // locals[nlocals-1..0]
 251   // monitors[0..number_of_locks]
 252   //
 253   // locals is a direct copy of the interpreter frame so in the osr buffer
 254   // so first slot in the local array is the last local from the interpreter
 255   // and last slot is local[0] (receiver) from the interpreter
 256   //
 257   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 258   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 259   // in the interpreter frame (the method lock if a sync method)
 260 
 261   // Initialize monitors in the compiled activation.
 262   //   r2: pointer to osr buffer
 263   //
 264   // All other registers are dead at this point and the locals will be
 265   // copied into place by code emitted in the IR.
 266 
 267   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 268   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 269     int monitor_offset = BytesPerWord * method()->max_locals() +
 270       (2 * BytesPerWord) * (number_of_locks - 1);
 271     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 272     // the OSR buffer using 2 word entries: first the lock and then
 273     // the oop.
 274     for (int i = 0; i < number_of_locks; i++) {
 275       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 276 #ifdef ASSERT
 277       // verify the interpreter's monitor has a non-null object
 278       {
 279         Label L;
 280         __ ldr(rscratch1, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 281         __ cbnz(rscratch1, L);
 282         __ stop("locked object is NULL");
 283         __ bind(L);
 284       }
 285 #endif
 286       __ ldr(r19, Address(OSR_buf, slot_offset + 0));
 287       __ str(r19, frame_map()->address_for_monitor_lock(i));
 288       __ ldr(r19, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 289       __ str(r19, frame_map()->address_for_monitor_object(i));
 290     }
 291   }
 292 }
 293 
 294 
 295 // inline cache check; done before the frame is built.
 296 int LIR_Assembler::check_icache() {
 297   Register receiver = FrameMap::receiver_opr->as_register();
 298   Register ic_klass = IC_Klass;
 299   int start_offset = __ offset();
 300   __ inline_cache_check(receiver, ic_klass);
 301 
 302   // if icache check fails, then jump to runtime routine
 303   // Note: RECEIVER must still contain the receiver!
 304   Label dont;
 305   __ br(Assembler::EQ, dont);
 306   __ far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 307 
 308   // We align the verified entry point unless the method body
 309   // (including its inline cache check) will fit in a single 64-byte
 310   // icache line.
 311   if (! method()->is_accessor() || __ offset() - start_offset > 4 * 4) {
 312     // force alignment after the cache check.
 313     __ align(CodeEntryAlignment);
 314   }
 315 
 316   __ bind(dont);
 317   return start_offset;
 318 }
 319 
 320 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 321   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 322   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 323 
 324   Label L_skip_barrier;
 325 
 326   __ mov_metadata(rscratch2, method->holder()->constant_encoding());
 327   __ clinit_barrier(rscratch2, rscratch1, &L_skip_barrier /*L_fast_path*/);
 328   __ far_jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 329   __ bind(L_skip_barrier);
 330 }
 331 
 332 void LIR_Assembler::jobject2reg(jobject o, Register reg) {
 333   if (o == NULL) {
 334     __ mov(reg, zr);
 335   } else {
 336     __ movoop(reg, o, /*immediate*/true);
 337   }
 338 }
 339 
 340 void LIR_Assembler::deoptimize_trap(CodeEmitInfo *info) {
 341   address target = NULL;
 342   relocInfo::relocType reloc_type = relocInfo::none;
 343 
 344   switch (patching_id(info)) {
 345   case PatchingStub::access_field_id:
 346     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 347     reloc_type = relocInfo::section_word_type;
 348     break;
 349   case PatchingStub::load_klass_id:
 350     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 351     reloc_type = relocInfo::metadata_type;
 352     break;
 353   case PatchingStub::load_mirror_id:
 354     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 355     reloc_type = relocInfo::oop_type;
 356     break;
 357   case PatchingStub::load_appendix_id:
 358     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 359     reloc_type = relocInfo::oop_type;
 360     break;
 361   default: ShouldNotReachHere();
 362   }
 363 
 364   __ far_call(RuntimeAddress(target));
 365   add_call_info_here(info);
 366 }
 367 
 368 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) {
 369   deoptimize_trap(info);
 370 }
 371 
 372 
 373 // This specifies the rsp decrement needed to build the frame
 374 int LIR_Assembler::initial_frame_size_in_bytes() const {
 375   // if rounding, must let FrameMap know!
 376 
 377   return in_bytes(frame_map()->framesize_in_bytes());
 378 }
 379 
 380 
 381 int LIR_Assembler::emit_exception_handler() {
 382   // if the last instruction is a call (typically to do a throw which
 383   // is coming at the end after block reordering) the return address
 384   // must still point into the code area in order to avoid assertion
 385   // failures when searching for the corresponding bci => add a nop
 386   // (was bug 5/14/1999 - gri)
 387   __ nop();
 388 
 389   // generate code for exception handler
 390   address handler_base = __ start_a_stub(exception_handler_size());
 391   if (handler_base == NULL) {
 392     // not enough space left for the handler
 393     bailout("exception handler overflow");
 394     return -1;
 395   }
 396 
 397   int offset = code_offset();
 398 
 399   // the exception oop and pc are in r0, and r3
 400   // no other registers need to be preserved, so invalidate them
 401   __ invalidate_registers(false, true, true, false, true, true);
 402 
 403   // check that there is really an exception
 404   __ verify_not_null_oop(r0);
 405 
 406   // search an exception handler (r0: exception oop, r3: throwing pc)
 407   __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));  __ should_not_reach_here();
 408   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 409   __ end_a_stub();
 410 
 411   return offset;
 412 }
 413 
 414 
 415 // Emit the code to remove the frame from the stack in the exception
 416 // unwind path.
 417 int LIR_Assembler::emit_unwind_handler() {
 418 #ifndef PRODUCT
 419   if (CommentedAssembly) {
 420     _masm->block_comment("Unwind handler");
 421   }
 422 #endif
 423 
 424   int offset = code_offset();
 425 
 426   // Fetch the exception from TLS and clear out exception related thread state
 427   __ ldr(r0, Address(rthread, JavaThread::exception_oop_offset()));
 428   __ str(zr, Address(rthread, JavaThread::exception_oop_offset()));
 429   __ str(zr, Address(rthread, JavaThread::exception_pc_offset()));
 430 
 431   __ bind(_unwind_handler_entry);
 432   __ verify_not_null_oop(r0);
 433   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 434     __ mov(r19, r0);  // Preserve the exception
 435   }
 436 
 437   // Preform needed unlocking
 438   MonitorExitStub* stub = NULL;
 439   if (method()->is_synchronized()) {
 440     monitor_address(0, FrameMap::r0_opr);
 441     stub = new MonitorExitStub(FrameMap::r0_opr, true, 0);
 442     __ unlock_object(r5, r4, r0, *stub->entry());
 443     __ bind(*stub->continuation());
 444     __ dec_held_monitor_count(rthread);
 445   }
 446 
 447   if (compilation()->env()->dtrace_method_probes()) {
 448     __ mov(c_rarg0, rthread);
 449     __ mov_metadata(c_rarg1, method()->constant_encoding());
 450     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), c_rarg0, c_rarg1);
 451   }
 452 
 453   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 454     __ mov(r0, r19);  // Restore the exception
 455   }
 456 
 457   // remove the activation and dispatch to the unwind handler
 458   __ block_comment("remove_frame and dispatch to the unwind handler");
 459   __ remove_frame(initial_frame_size_in_bytes());
 460   __ far_jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 461 
 462   // Emit the slow path assembly
 463   if (stub != NULL) {
 464     stub->emit_code(this);
 465   }
 466 
 467   return offset;
 468 }
 469 
 470 
 471 int LIR_Assembler::emit_deopt_handler() {
 472   // if the last instruction is a call (typically to do a throw which
 473   // is coming at the end after block reordering) the return address
 474   // must still point into the code area in order to avoid assertion
 475   // failures when searching for the corresponding bci => add a nop
 476   // (was bug 5/14/1999 - gri)
 477   __ nop();
 478 
 479   // generate code for exception handler
 480   address handler_base = __ start_a_stub(deopt_handler_size());
 481   if (handler_base == NULL) {
 482     // not enough space left for the handler
 483     bailout("deopt handler overflow");
 484     return -1;
 485   }
 486 
 487   int offset = code_offset();
 488 
 489   __ adr(lr, pc());
 490   __ far_jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 491   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 492   __ end_a_stub();
 493 
 494   return offset;
 495 }
 496 
 497 void LIR_Assembler::add_debug_info_for_branch(address adr, CodeEmitInfo* info) {
 498   _masm->code_section()->relocate(adr, relocInfo::poll_type);
 499   int pc_offset = code_offset();
 500   flush_debug_info(pc_offset);
 501   info->record_debug_info(compilation()->debug_info_recorder(), pc_offset);
 502   if (info->exception_handlers() != NULL) {
 503     compilation()->add_exception_handlers_for_pco(pc_offset, info->exception_handlers());
 504   }
 505 }
 506 
 507 void LIR_Assembler::return_op(LIR_Opr result, C1SafepointPollStub* code_stub) {
 508   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == r0, "word returns are in r0,");
 509 
 510   // Pop the stack before the safepoint code
 511   __ remove_frame(initial_frame_size_in_bytes());
 512 
 513   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 514     __ reserved_stack_check();
 515   }
 516 
 517   code_stub->set_safepoint_offset(__ offset());
 518   __ relocate(relocInfo::poll_return_type);
 519   __ safepoint_poll(*code_stub->entry(), true /* at_return */, false /* acquire */, true /* in_nmethod */);
 520   __ ret(lr);
 521 }
 522 
 523 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 524   guarantee(info != NULL, "Shouldn't be NULL");
 525   __ get_polling_page(rscratch1, relocInfo::poll_type);
 526   add_debug_info_for_branch(info);  // This isn't just debug info:
 527                                     // it's the oop map
 528   __ read_polling_page(rscratch1, relocInfo::poll_type);
 529   return __ offset();
 530 }
 531 
 532 
 533 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 534   if (from_reg == r31_sp)
 535     from_reg = sp;
 536   if (to_reg == r31_sp)
 537     to_reg = sp;
 538   __ mov(to_reg, from_reg);
 539 }
 540 
 541 void LIR_Assembler::swap_reg(Register a, Register b) { Unimplemented(); }
 542 
 543 
 544 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 545   assert(src->is_constant(), "should not call otherwise");
 546   assert(dest->is_register(), "should not call otherwise");
 547   LIR_Const* c = src->as_constant_ptr();
 548 
 549   switch (c->type()) {
 550     case T_INT: {
 551       assert(patch_code == lir_patch_none, "no patching handled here");
 552       __ movw(dest->as_register(), c->as_jint());
 553       break;
 554     }
 555 
 556     case T_ADDRESS: {
 557       assert(patch_code == lir_patch_none, "no patching handled here");
 558       __ mov(dest->as_register(), c->as_jint());
 559       break;
 560     }
 561 
 562     case T_LONG: {
 563       assert(patch_code == lir_patch_none, "no patching handled here");
 564       __ mov(dest->as_register_lo(), (intptr_t)c->as_jlong());
 565       break;
 566     }
 567 
 568     case T_OBJECT: {
 569         if (patch_code == lir_patch_none) {
 570           jobject2reg(c->as_jobject(), dest->as_register());
 571         } else {
 572           jobject2reg_with_patching(dest->as_register(), info);
 573         }
 574       break;
 575     }
 576 
 577     case T_METADATA: {
 578       if (patch_code != lir_patch_none) {
 579         klass2reg_with_patching(dest->as_register(), info);
 580       } else {
 581         __ mov_metadata(dest->as_register(), c->as_metadata());
 582       }
 583       break;
 584     }
 585 
 586     case T_FLOAT: {
 587       if (__ operand_valid_for_float_immediate(c->as_jfloat())) {
 588         __ fmovs(dest->as_float_reg(), (c->as_jfloat()));
 589       } else {
 590         __ adr(rscratch1, InternalAddress(float_constant(c->as_jfloat())));
 591         __ ldrs(dest->as_float_reg(), Address(rscratch1));
 592       }
 593       break;
 594     }
 595 
 596     case T_DOUBLE: {
 597       if (__ operand_valid_for_float_immediate(c->as_jdouble())) {
 598         __ fmovd(dest->as_double_reg(), (c->as_jdouble()));
 599       } else {
 600         __ adr(rscratch1, InternalAddress(double_constant(c->as_jdouble())));
 601         __ ldrd(dest->as_double_reg(), Address(rscratch1));
 602       }
 603       break;
 604     }
 605 
 606     default:
 607       ShouldNotReachHere();
 608   }
 609 }
 610 
 611 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 612   LIR_Const* c = src->as_constant_ptr();
 613   switch (c->type()) {
 614   case T_OBJECT:
 615     {
 616       if (! c->as_jobject())
 617         __ str(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 618       else {
 619         const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 620         reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 621       }
 622     }
 623     break;
 624   case T_ADDRESS:
 625     {
 626       const2reg(src, FrameMap::rscratch1_opr, lir_patch_none, NULL);
 627       reg2stack(FrameMap::rscratch1_opr, dest, c->type(), false);
 628     }
 629   case T_INT:
 630   case T_FLOAT:
 631     {
 632       Register reg = zr;
 633       if (c->as_jint_bits() == 0)
 634         __ strw(zr, frame_map()->address_for_slot(dest->single_stack_ix()));
 635       else {
 636         __ movw(rscratch1, c->as_jint_bits());
 637         __ strw(rscratch1, frame_map()->address_for_slot(dest->single_stack_ix()));
 638       }
 639     }
 640     break;
 641   case T_LONG:
 642   case T_DOUBLE:
 643     {
 644       Register reg = zr;
 645       if (c->as_jlong_bits() == 0)
 646         __ str(zr, frame_map()->address_for_slot(dest->double_stack_ix(),
 647                                                  lo_word_offset_in_bytes));
 648       else {
 649         __ mov(rscratch1, (intptr_t)c->as_jlong_bits());
 650         __ str(rscratch1, frame_map()->address_for_slot(dest->double_stack_ix(),
 651                                                         lo_word_offset_in_bytes));
 652       }
 653     }
 654     break;
 655   default:
 656     ShouldNotReachHere();
 657   }
 658 }
 659 
 660 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 661   assert(src->is_constant(), "should not call otherwise");
 662   LIR_Const* c = src->as_constant_ptr();
 663   LIR_Address* to_addr = dest->as_address_ptr();
 664 
 665   void (Assembler::* insn)(Register Rt, const Address &adr);
 666 
 667   switch (type) {
 668   case T_ADDRESS:
 669     assert(c->as_jint() == 0, "should be");
 670     insn = &Assembler::str;
 671     break;
 672   case T_LONG:
 673     assert(c->as_jlong() == 0, "should be");
 674     insn = &Assembler::str;
 675     break;
 676   case T_INT:
 677     assert(c->as_jint() == 0, "should be");
 678     insn = &Assembler::strw;
 679     break;
 680   case T_OBJECT:
 681   case T_ARRAY:
 682     assert(c->as_jobject() == 0, "should be");
 683     if (UseCompressedOops && !wide) {
 684       insn = &Assembler::strw;
 685     } else {
 686       insn = &Assembler::str;
 687     }
 688     break;
 689   case T_CHAR:
 690   case T_SHORT:
 691     assert(c->as_jint() == 0, "should be");
 692     insn = &Assembler::strh;
 693     break;
 694   case T_BOOLEAN:
 695   case T_BYTE:
 696     assert(c->as_jint() == 0, "should be");
 697     insn = &Assembler::strb;
 698     break;
 699   default:
 700     ShouldNotReachHere();
 701     insn = &Assembler::str;  // unreachable
 702   }
 703 
 704   if (info) add_debug_info_for_null_check_here(info);
 705   (_masm->*insn)(zr, as_Address(to_addr, rscratch1));
 706 }
 707 
 708 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 709   assert(src->is_register(), "should not call otherwise");
 710   assert(dest->is_register(), "should not call otherwise");
 711 
 712   // move between cpu-registers
 713   if (dest->is_single_cpu()) {
 714     if (src->type() == T_LONG) {
 715       // Can do LONG -> OBJECT
 716       move_regs(src->as_register_lo(), dest->as_register());
 717       return;
 718     }
 719     assert(src->is_single_cpu(), "must match");
 720     if (src->type() == T_OBJECT) {
 721       __ verify_oop(src->as_register());
 722     }
 723     move_regs(src->as_register(), dest->as_register());
 724 
 725   } else if (dest->is_double_cpu()) {
 726     if (is_reference_type(src->type())) {
 727       // Surprising to me but we can see move of a long to t_object
 728       __ verify_oop(src->as_register());
 729       move_regs(src->as_register(), dest->as_register_lo());
 730       return;
 731     }
 732     assert(src->is_double_cpu(), "must match");
 733     Register f_lo = src->as_register_lo();
 734     Register f_hi = src->as_register_hi();
 735     Register t_lo = dest->as_register_lo();
 736     Register t_hi = dest->as_register_hi();
 737     assert(f_hi == f_lo, "must be same");
 738     assert(t_hi == t_lo, "must be same");
 739     move_regs(f_lo, t_lo);
 740 
 741   } else if (dest->is_single_fpu()) {
 742     __ fmovs(dest->as_float_reg(), src->as_float_reg());
 743 
 744   } else if (dest->is_double_fpu()) {
 745     __ fmovd(dest->as_double_reg(), src->as_double_reg());
 746 
 747   } else {
 748     ShouldNotReachHere();
 749   }
 750 }
 751 
 752 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 753   precond(src->is_register() && dest->is_stack());
 754 
 755   uint const c_sz32 = sizeof(uint32_t);
 756   uint const c_sz64 = sizeof(uint64_t);
 757 
 758   if (src->is_single_cpu()) {
 759     int index = dest->single_stack_ix();
 760     if (is_reference_type(type)) {
 761       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 762       __ verify_oop(src->as_register());
 763     } else if (type == T_METADATA || type == T_DOUBLE || type == T_ADDRESS) {
 764       __ str(src->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 765     } else {
 766       __ strw(src->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 767     }
 768 
 769   } else if (src->is_double_cpu()) {
 770     int index = dest->double_stack_ix();
 771     Address dest_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 772     __ str(src->as_register_lo(), dest_addr_LO);
 773 
 774   } else if (src->is_single_fpu()) {
 775     int index = dest->single_stack_ix();
 776     __ strs(src->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 777 
 778   } else if (src->is_double_fpu()) {
 779     int index = dest->double_stack_ix();
 780     __ strd(src->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 781 
 782   } else {
 783     ShouldNotReachHere();
 784   }
 785 }
 786 
 787 
 788 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide) {
 789   LIR_Address* to_addr = dest->as_address_ptr();
 790   PatchingStub* patch = NULL;
 791   Register compressed_src = rscratch1;
 792 
 793   if (patch_code != lir_patch_none) {
 794     deoptimize_trap(info);
 795     return;
 796   }
 797 
 798   if (is_reference_type(type)) {
 799     __ verify_oop(src->as_register());
 800 
 801     if (UseCompressedOops && !wide) {
 802       __ encode_heap_oop(compressed_src, src->as_register());
 803     } else {
 804       compressed_src = src->as_register();
 805     }
 806   }
 807 
 808   int null_check_here = code_offset();
 809   switch (type) {
 810     case T_FLOAT: {
 811       __ strs(src->as_float_reg(), as_Address(to_addr));
 812       break;
 813     }
 814 
 815     case T_DOUBLE: {
 816       __ strd(src->as_double_reg(), as_Address(to_addr));
 817       break;
 818     }
 819 
 820     case T_ARRAY:   // fall through
 821     case T_OBJECT:  // fall through
 822       if (UseCompressedOops && !wide) {
 823         __ strw(compressed_src, as_Address(to_addr, rscratch2));
 824       } else {
 825          __ str(compressed_src, as_Address(to_addr));
 826       }
 827       break;
 828     case T_METADATA:
 829       // We get here to store a method pointer to the stack to pass to
 830       // a dtrace runtime call. This can't work on 64 bit with
 831       // compressed klass ptrs: T_METADATA can be a compressed klass
 832       // ptr or a 64 bit method pointer.
 833       ShouldNotReachHere();
 834       __ str(src->as_register(), as_Address(to_addr));
 835       break;
 836     case T_ADDRESS:
 837       __ str(src->as_register(), as_Address(to_addr));
 838       break;
 839     case T_INT:
 840       __ strw(src->as_register(), as_Address(to_addr));
 841       break;
 842 
 843     case T_LONG: {
 844       __ str(src->as_register_lo(), as_Address_lo(to_addr));
 845       break;
 846     }
 847 
 848     case T_BYTE:    // fall through
 849     case T_BOOLEAN: {
 850       __ strb(src->as_register(), as_Address(to_addr));
 851       break;
 852     }
 853 
 854     case T_CHAR:    // fall through
 855     case T_SHORT:
 856       __ strh(src->as_register(), as_Address(to_addr));
 857       break;
 858 
 859     default:
 860       ShouldNotReachHere();
 861   }
 862   if (info != NULL) {
 863     add_debug_info_for_null_check(null_check_here, info);
 864   }
 865 }
 866 
 867 
 868 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
 869   precond(src->is_stack() && dest->is_register());
 870 
 871   uint const c_sz32 = sizeof(uint32_t);
 872   uint const c_sz64 = sizeof(uint64_t);
 873 
 874   if (dest->is_single_cpu()) {
 875     int index = src->single_stack_ix();
 876     if (is_reference_type(type)) {
 877       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 878       __ verify_oop(dest->as_register());
 879     } else if (type == T_METADATA || type == T_ADDRESS) {
 880       __ ldr(dest->as_register(), stack_slot_address(index, c_sz64, rscratch1));
 881     } else {
 882       __ ldrw(dest->as_register(), stack_slot_address(index, c_sz32, rscratch1));
 883     }
 884 
 885   } else if (dest->is_double_cpu()) {
 886     int index = src->double_stack_ix();
 887     Address src_addr_LO = stack_slot_address(index, c_sz64, rscratch1, lo_word_offset_in_bytes);
 888     __ ldr(dest->as_register_lo(), src_addr_LO);
 889 
 890   } else if (dest->is_single_fpu()) {
 891     int index = src->single_stack_ix();
 892     __ ldrs(dest->as_float_reg(), stack_slot_address(index, c_sz32, rscratch1));
 893 
 894   } else if (dest->is_double_fpu()) {
 895     int index = src->double_stack_ix();
 896     __ ldrd(dest->as_double_reg(), stack_slot_address(index, c_sz64, rscratch1));
 897 
 898   } else {
 899     ShouldNotReachHere();
 900   }
 901 }
 902 
 903 
 904 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 905   address target = NULL;
 906   relocInfo::relocType reloc_type = relocInfo::none;
 907 
 908   switch (patching_id(info)) {
 909   case PatchingStub::access_field_id:
 910     target = Runtime1::entry_for(Runtime1::access_field_patching_id);
 911     reloc_type = relocInfo::section_word_type;
 912     break;
 913   case PatchingStub::load_klass_id:
 914     target = Runtime1::entry_for(Runtime1::load_klass_patching_id);
 915     reloc_type = relocInfo::metadata_type;
 916     break;
 917   case PatchingStub::load_mirror_id:
 918     target = Runtime1::entry_for(Runtime1::load_mirror_patching_id);
 919     reloc_type = relocInfo::oop_type;
 920     break;
 921   case PatchingStub::load_appendix_id:
 922     target = Runtime1::entry_for(Runtime1::load_appendix_patching_id);
 923     reloc_type = relocInfo::oop_type;
 924     break;
 925   default: ShouldNotReachHere();
 926   }
 927 
 928   __ far_call(RuntimeAddress(target));
 929   add_call_info_here(info);
 930 }
 931 
 932 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
 933 
 934   LIR_Opr temp;
 935   if (type == T_LONG || type == T_DOUBLE)
 936     temp = FrameMap::rscratch1_long_opr;
 937   else
 938     temp = FrameMap::rscratch1_opr;
 939 
 940   stack2reg(src, temp, src->type());
 941   reg2stack(temp, dest, dest->type(), false);
 942 }
 943 
 944 
 945 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide) {
 946   LIR_Address* addr = src->as_address_ptr();
 947   LIR_Address* from_addr = src->as_address_ptr();
 948 
 949   if (addr->base()->type() == T_OBJECT) {
 950     __ verify_oop(addr->base()->as_pointer_register());
 951   }
 952 
 953   if (patch_code != lir_patch_none) {
 954     deoptimize_trap(info);
 955     return;
 956   }
 957 
 958   if (info != NULL) {
 959     add_debug_info_for_null_check_here(info);
 960   }
 961   int null_check_here = code_offset();
 962   switch (type) {
 963     case T_FLOAT: {
 964       __ ldrs(dest->as_float_reg(), as_Address(from_addr));
 965       break;
 966     }
 967 
 968     case T_DOUBLE: {
 969       __ ldrd(dest->as_double_reg(), as_Address(from_addr));
 970       break;
 971     }
 972 
 973     case T_ARRAY:   // fall through
 974     case T_OBJECT:  // fall through
 975       if (UseCompressedOops && !wide) {
 976         __ ldrw(dest->as_register(), as_Address(from_addr));
 977       } else {
 978          __ ldr(dest->as_register(), as_Address(from_addr));
 979       }
 980       break;
 981     case T_METADATA:
 982       // We get here to store a method pointer to the stack to pass to
 983       // a dtrace runtime call. This can't work on 64 bit with
 984       // compressed klass ptrs: T_METADATA can be a compressed klass
 985       // ptr or a 64 bit method pointer.
 986       ShouldNotReachHere();
 987       __ ldr(dest->as_register(), as_Address(from_addr));
 988       break;
 989     case T_ADDRESS:
 990       // FIXME: OMG this is a horrible kludge.  Any offset from an
 991       // address that matches klass_offset_in_bytes() will be loaded
 992       // as a word, not a long.
 993       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
 994         __ ldrw(dest->as_register(), as_Address(from_addr));
 995       } else {
 996         __ ldr(dest->as_register(), as_Address(from_addr));
 997       }
 998       break;
 999     case T_INT:
1000       __ ldrw(dest->as_register(), as_Address(from_addr));
1001       break;
1002 
1003     case T_LONG: {
1004       __ ldr(dest->as_register_lo(), as_Address_lo(from_addr));
1005       break;
1006     }
1007 
1008     case T_BYTE:
1009       __ ldrsb(dest->as_register(), as_Address(from_addr));
1010       break;
1011     case T_BOOLEAN: {
1012       __ ldrb(dest->as_register(), as_Address(from_addr));
1013       break;
1014     }
1015 
1016     case T_CHAR:
1017       __ ldrh(dest->as_register(), as_Address(from_addr));
1018       break;
1019     case T_SHORT:
1020       __ ldrsh(dest->as_register(), as_Address(from_addr));
1021       break;
1022 
1023     default:
1024       ShouldNotReachHere();
1025   }
1026 
1027   if (is_reference_type(type)) {
1028     if (UseCompressedOops && !wide) {
1029       __ decode_heap_oop(dest->as_register());
1030     }
1031 
1032     if (!UseZGC) {
1033       // Load barrier has not yet been applied, so ZGC can't verify the oop here
1034       __ verify_oop(dest->as_register());
1035     }
1036   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1037     if (UseCompressedClassPointers) {
1038       __ decode_klass_not_null(dest->as_register());
1039     }
1040   }
1041 }
1042 
1043 
1044 int LIR_Assembler::array_element_size(BasicType type) const {
1045   int elem_size = type2aelembytes(type);
1046   return exact_log2(elem_size);
1047 }
1048 
1049 
1050 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1051   switch (op->code()) {
1052   case lir_idiv:
1053   case lir_irem:
1054     arithmetic_idiv(op->code(),
1055                     op->in_opr1(),
1056                     op->in_opr2(),
1057                     op->in_opr3(),
1058                     op->result_opr(),
1059                     op->info());
1060     break;
1061   case lir_fmad:
1062     __ fmaddd(op->result_opr()->as_double_reg(),
1063               op->in_opr1()->as_double_reg(),
1064               op->in_opr2()->as_double_reg(),
1065               op->in_opr3()->as_double_reg());
1066     break;
1067   case lir_fmaf:
1068     __ fmadds(op->result_opr()->as_float_reg(),
1069               op->in_opr1()->as_float_reg(),
1070               op->in_opr2()->as_float_reg(),
1071               op->in_opr3()->as_float_reg());
1072     break;
1073   default:      ShouldNotReachHere(); break;
1074   }
1075 }
1076 
1077 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1078 #ifdef ASSERT
1079   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1080   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1081   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1082 #endif
1083 
1084   if (op->cond() == lir_cond_always) {
1085     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1086     __ b(*(op->label()));
1087   } else {
1088     Assembler::Condition acond;
1089     if (op->code() == lir_cond_float_branch) {
1090       bool is_unordered = (op->ublock() == op->block());
1091       // Assembler::EQ does not permit unordered branches, so we add
1092       // another branch here.  Likewise, Assembler::NE does not permit
1093       // ordered branches.
1094       if ((is_unordered && op->cond() == lir_cond_equal)
1095           || (!is_unordered && op->cond() == lir_cond_notEqual))
1096         __ br(Assembler::VS, *(op->ublock()->label()));
1097       switch(op->cond()) {
1098       case lir_cond_equal:        acond = Assembler::EQ; break;
1099       case lir_cond_notEqual:     acond = Assembler::NE; break;
1100       case lir_cond_less:         acond = (is_unordered ? Assembler::LT : Assembler::LO); break;
1101       case lir_cond_lessEqual:    acond = (is_unordered ? Assembler::LE : Assembler::LS); break;
1102       case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::HS : Assembler::GE); break;
1103       case lir_cond_greater:      acond = (is_unordered ? Assembler::HI : Assembler::GT); break;
1104       default:                    ShouldNotReachHere();
1105         acond = Assembler::EQ;  // unreachable
1106       }
1107     } else {
1108       switch (op->cond()) {
1109         case lir_cond_equal:        acond = Assembler::EQ; break;
1110         case lir_cond_notEqual:     acond = Assembler::NE; break;
1111         case lir_cond_less:         acond = Assembler::LT; break;
1112         case lir_cond_lessEqual:    acond = Assembler::LE; break;
1113         case lir_cond_greaterEqual: acond = Assembler::GE; break;
1114         case lir_cond_greater:      acond = Assembler::GT; break;
1115         case lir_cond_belowEqual:   acond = Assembler::LS; break;
1116         case lir_cond_aboveEqual:   acond = Assembler::HS; break;
1117         default:                    ShouldNotReachHere();
1118           acond = Assembler::EQ;  // unreachable
1119       }
1120     }
1121     __ br(acond,*(op->label()));
1122   }
1123 }
1124 
1125 
1126 
1127 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1128   LIR_Opr src  = op->in_opr();
1129   LIR_Opr dest = op->result_opr();
1130 
1131   switch (op->bytecode()) {
1132     case Bytecodes::_i2f:
1133       {
1134         __ scvtfws(dest->as_float_reg(), src->as_register());
1135         break;
1136       }
1137     case Bytecodes::_i2d:
1138       {
1139         __ scvtfwd(dest->as_double_reg(), src->as_register());
1140         break;
1141       }
1142     case Bytecodes::_l2d:
1143       {
1144         __ scvtfd(dest->as_double_reg(), src->as_register_lo());
1145         break;
1146       }
1147     case Bytecodes::_l2f:
1148       {
1149         __ scvtfs(dest->as_float_reg(), src->as_register_lo());
1150         break;
1151       }
1152     case Bytecodes::_f2d:
1153       {
1154         __ fcvts(dest->as_double_reg(), src->as_float_reg());
1155         break;
1156       }
1157     case Bytecodes::_d2f:
1158       {
1159         __ fcvtd(dest->as_float_reg(), src->as_double_reg());
1160         break;
1161       }
1162     case Bytecodes::_i2c:
1163       {
1164         __ ubfx(dest->as_register(), src->as_register(), 0, 16);
1165         break;
1166       }
1167     case Bytecodes::_i2l:
1168       {
1169         __ sxtw(dest->as_register_lo(), src->as_register());
1170         break;
1171       }
1172     case Bytecodes::_i2s:
1173       {
1174         __ sxth(dest->as_register(), src->as_register());
1175         break;
1176       }
1177     case Bytecodes::_i2b:
1178       {
1179         __ sxtb(dest->as_register(), src->as_register());
1180         break;
1181       }
1182     case Bytecodes::_l2i:
1183       {
1184         _masm->block_comment("FIXME: This could be a no-op");
1185         __ uxtw(dest->as_register(), src->as_register_lo());
1186         break;
1187       }
1188     case Bytecodes::_d2l:
1189       {
1190         __ fcvtzd(dest->as_register_lo(), src->as_double_reg());
1191         break;
1192       }
1193     case Bytecodes::_f2i:
1194       {
1195         __ fcvtzsw(dest->as_register(), src->as_float_reg());
1196         break;
1197       }
1198     case Bytecodes::_f2l:
1199       {
1200         __ fcvtzs(dest->as_register_lo(), src->as_float_reg());
1201         break;
1202       }
1203     case Bytecodes::_d2i:
1204       {
1205         __ fcvtzdw(dest->as_register(), src->as_double_reg());
1206         break;
1207       }
1208     default: ShouldNotReachHere();
1209   }
1210 }
1211 
1212 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1213   if (op->init_check()) {
1214     __ ldrb(rscratch1, Address(op->klass()->as_register(),
1215                                InstanceKlass::init_state_offset()));
1216     __ cmpw(rscratch1, InstanceKlass::fully_initialized);
1217     add_debug_info_for_null_check_here(op->stub()->info());
1218     __ br(Assembler::NE, *op->stub()->entry());
1219   }
1220   __ allocate_object(op->obj()->as_register(),
1221                      op->tmp1()->as_register(),
1222                      op->tmp2()->as_register(),
1223                      op->header_size(),
1224                      op->object_size(),
1225                      op->klass()->as_register(),
1226                      *op->stub()->entry());
1227   __ bind(*op->stub()->continuation());
1228 }
1229 
1230 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1231   Register len =  op->len()->as_register();
1232   __ uxtw(len, len);
1233 
1234   if (UseSlowPath ||
1235       (!UseFastNewObjectArray && is_reference_type(op->type())) ||
1236       (!UseFastNewTypeArray   && !is_reference_type(op->type()))) {
1237     __ b(*op->stub()->entry());
1238   } else {
1239     Register tmp1 = op->tmp1()->as_register();
1240     Register tmp2 = op->tmp2()->as_register();
1241     Register tmp3 = op->tmp3()->as_register();
1242     if (len == tmp1) {
1243       tmp1 = tmp3;
1244     } else if (len == tmp2) {
1245       tmp2 = tmp3;
1246     } else if (len == tmp3) {
1247       // everything is ok
1248     } else {
1249       __ mov(tmp3, len);
1250     }
1251     __ allocate_array(op->obj()->as_register(),
1252                       len,
1253                       tmp1,
1254                       tmp2,
1255                       arrayOopDesc::header_size(op->type()),
1256                       array_element_size(op->type()),
1257                       op->klass()->as_register(),
1258                       *op->stub()->entry());
1259   }
1260   __ bind(*op->stub()->continuation());
1261 }
1262 
1263 void LIR_Assembler::type_profile_helper(Register mdo,
1264                                         ciMethodData *md, ciProfileData *data,
1265                                         Register recv, Label* update_done) {
1266   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1267     Label next_test;
1268     // See if the receiver is receiver[n].
1269     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1270     __ ldr(rscratch1, Address(rscratch2));
1271     __ cmp(recv, rscratch1);
1272     __ br(Assembler::NE, next_test);
1273     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1274     __ addptr(data_addr, DataLayout::counter_increment);
1275     __ b(*update_done);
1276     __ bind(next_test);
1277   }
1278 
1279   // Didn't find receiver; find next empty slot and fill it in
1280   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1281     Label next_test;
1282     __ lea(rscratch2,
1283            Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1284     Address recv_addr(rscratch2);
1285     __ ldr(rscratch1, recv_addr);
1286     __ cbnz(rscratch1, next_test);
1287     __ str(recv, recv_addr);
1288     __ mov(rscratch1, DataLayout::counter_increment);
1289     __ lea(rscratch2, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))));
1290     __ str(rscratch1, Address(rscratch2));
1291     __ b(*update_done);
1292     __ bind(next_test);
1293   }
1294 }
1295 
1296 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1297   // we always need a stub for the failure case.
1298   CodeStub* stub = op->stub();
1299   Register obj = op->object()->as_register();
1300   Register k_RInfo = op->tmp1()->as_register();
1301   Register klass_RInfo = op->tmp2()->as_register();
1302   Register dst = op->result_opr()->as_register();
1303   ciKlass* k = op->klass();
1304   Register Rtmp1 = noreg;
1305 
1306   // check if it needs to be profiled
1307   ciMethodData* md;
1308   ciProfileData* data;
1309 
1310   const bool should_profile = op->should_profile();
1311 
1312   if (should_profile) {
1313     ciMethod* method = op->profiled_method();
1314     assert(method != NULL, "Should have method");
1315     int bci = op->profiled_bci();
1316     md = method->method_data_or_null();
1317     assert(md != NULL, "Sanity");
1318     data = md->bci_to_data(bci);
1319     assert(data != NULL,                "need data for type check");
1320     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1321   }
1322   Label profile_cast_success, profile_cast_failure;
1323   Label *success_target = should_profile ? &profile_cast_success : success;
1324   Label *failure_target = should_profile ? &profile_cast_failure : failure;
1325 
1326   if (obj == k_RInfo) {
1327     k_RInfo = dst;
1328   } else if (obj == klass_RInfo) {
1329     klass_RInfo = dst;
1330   }
1331   if (k->is_loaded() && !UseCompressedClassPointers) {
1332     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1333   } else {
1334     Rtmp1 = op->tmp3()->as_register();
1335     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1336   }
1337 
1338   assert_different_registers(obj, k_RInfo, klass_RInfo);
1339 
1340     if (should_profile) {
1341       Label not_null;
1342       __ cbnz(obj, not_null);
1343       // Object is null; update MDO and exit
1344       Register mdo  = klass_RInfo;
1345       __ mov_metadata(mdo, md->constant_encoding());
1346       Address data_addr
1347         = __ form_address(rscratch2, mdo,
1348                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1349                           0);
1350       __ ldrb(rscratch1, data_addr);
1351       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1352       __ strb(rscratch1, data_addr);
1353       __ b(*obj_is_null);
1354       __ bind(not_null);
1355     } else {
1356       __ cbz(obj, *obj_is_null);
1357     }
1358 
1359   if (!k->is_loaded()) {
1360     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1361   } else {
1362     __ mov_metadata(k_RInfo, k->constant_encoding());
1363   }
1364   __ verify_oop(obj);
1365 
1366   if (op->fast_check()) {
1367     // get object class
1368     // not a safepoint as obj null check happens earlier
1369     __ load_klass(rscratch1, obj);
1370     __ cmp( rscratch1, k_RInfo);
1371 
1372     __ br(Assembler::NE, *failure_target);
1373     // successful cast, fall through to profile or jump
1374   } else {
1375     // get object class
1376     // not a safepoint as obj null check happens earlier
1377     __ load_klass(klass_RInfo, obj);
1378     if (k->is_loaded()) {
1379       // See if we get an immediate positive hit
1380       __ ldr(rscratch1, Address(klass_RInfo, int64_t(k->super_check_offset())));
1381       __ cmp(k_RInfo, rscratch1);
1382       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1383         __ br(Assembler::NE, *failure_target);
1384         // successful cast, fall through to profile or jump
1385       } else {
1386         // See if we get an immediate positive hit
1387         __ br(Assembler::EQ, *success_target);
1388         // check for self
1389         __ cmp(klass_RInfo, k_RInfo);
1390         __ br(Assembler::EQ, *success_target);
1391 
1392         __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1393         __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1394         __ ldr(klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1395         // result is a boolean
1396         __ cbzw(klass_RInfo, *failure_target);
1397         // successful cast, fall through to profile or jump
1398       }
1399     } else {
1400       // perform the fast part of the checking logic
1401       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1402       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1403       __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1404       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1405       __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1406       // result is a boolean
1407       __ cbz(k_RInfo, *failure_target);
1408       // successful cast, fall through to profile or jump
1409     }
1410   }
1411   if (should_profile) {
1412     Register mdo  = klass_RInfo, recv = k_RInfo;
1413     __ bind(profile_cast_success);
1414     __ mov_metadata(mdo, md->constant_encoding());
1415     __ load_klass(recv, obj);
1416     Label update_done;
1417     type_profile_helper(mdo, md, data, recv, success);
1418     __ b(*success);
1419 
1420     __ bind(profile_cast_failure);
1421     __ mov_metadata(mdo, md->constant_encoding());
1422     Address counter_addr
1423       = __ form_address(rscratch2, mdo,
1424                         md->byte_offset_of_slot(data, CounterData::count_offset()),
1425                         0);
1426     __ ldr(rscratch1, counter_addr);
1427     __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1428     __ str(rscratch1, counter_addr);
1429     __ b(*failure);
1430   }
1431   __ b(*success);
1432 }
1433 
1434 
1435 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1436   const bool should_profile = op->should_profile();
1437 
1438   LIR_Code code = op->code();
1439   if (code == lir_store_check) {
1440     Register value = op->object()->as_register();
1441     Register array = op->array()->as_register();
1442     Register k_RInfo = op->tmp1()->as_register();
1443     Register klass_RInfo = op->tmp2()->as_register();
1444     Register Rtmp1 = op->tmp3()->as_register();
1445 
1446     CodeStub* stub = op->stub();
1447 
1448     // check if it needs to be profiled
1449     ciMethodData* md;
1450     ciProfileData* data;
1451 
1452     if (should_profile) {
1453       ciMethod* method = op->profiled_method();
1454       assert(method != NULL, "Should have method");
1455       int bci = op->profiled_bci();
1456       md = method->method_data_or_null();
1457       assert(md != NULL, "Sanity");
1458       data = md->bci_to_data(bci);
1459       assert(data != NULL,                "need data for type check");
1460       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1461     }
1462     Label profile_cast_success, profile_cast_failure, done;
1463     Label *success_target = should_profile ? &profile_cast_success : &done;
1464     Label *failure_target = should_profile ? &profile_cast_failure : stub->entry();
1465 
1466     if (should_profile) {
1467       Label not_null;
1468       __ cbnz(value, not_null);
1469       // Object is null; update MDO and exit
1470       Register mdo  = klass_RInfo;
1471       __ mov_metadata(mdo, md->constant_encoding());
1472       Address data_addr
1473         = __ form_address(rscratch2, mdo,
1474                           md->byte_offset_of_slot(data, DataLayout::flags_offset()),
1475                           0);
1476       __ ldrb(rscratch1, data_addr);
1477       __ orr(rscratch1, rscratch1, BitData::null_seen_byte_constant());
1478       __ strb(rscratch1, data_addr);
1479       __ b(done);
1480       __ bind(not_null);
1481     } else {
1482       __ cbz(value, done);
1483     }
1484 
1485     add_debug_info_for_null_check_here(op->info_for_exception());
1486     __ load_klass(k_RInfo, array);
1487     __ load_klass(klass_RInfo, value);
1488 
1489     // get instance klass (it's already uncompressed)
1490     __ ldr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1491     // perform the fast part of the checking logic
1492     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1493     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1494     __ stp(klass_RInfo, k_RInfo, Address(__ pre(sp, -2 * wordSize)));
1495     __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1496     __ ldp(k_RInfo, klass_RInfo, Address(__ post(sp, 2 * wordSize)));
1497     // result is a boolean
1498     __ cbzw(k_RInfo, *failure_target);
1499     // fall through to the success case
1500 
1501     if (should_profile) {
1502       Register mdo  = klass_RInfo, recv = k_RInfo;
1503       __ bind(profile_cast_success);
1504       __ mov_metadata(mdo, md->constant_encoding());
1505       __ load_klass(recv, value);
1506       Label update_done;
1507       type_profile_helper(mdo, md, data, recv, &done);
1508       __ b(done);
1509 
1510       __ bind(profile_cast_failure);
1511       __ mov_metadata(mdo, md->constant_encoding());
1512       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1513       __ lea(rscratch2, counter_addr);
1514       __ ldr(rscratch1, Address(rscratch2));
1515       __ sub(rscratch1, rscratch1, DataLayout::counter_increment);
1516       __ str(rscratch1, Address(rscratch2));
1517       __ b(*stub->entry());
1518     }
1519 
1520     __ bind(done);
1521   } else if (code == lir_checkcast) {
1522     Register obj = op->object()->as_register();
1523     Register dst = op->result_opr()->as_register();
1524     Label success;
1525     emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1526     __ bind(success);
1527     if (dst != obj) {
1528       __ mov(dst, obj);
1529     }
1530   } else if (code == lir_instanceof) {
1531     Register obj = op->object()->as_register();
1532     Register dst = op->result_opr()->as_register();
1533     Label success, failure, done;
1534     emit_typecheck_helper(op, &success, &failure, &failure);
1535     __ bind(failure);
1536     __ mov(dst, zr);
1537     __ b(done);
1538     __ bind(success);
1539     __ mov(dst, 1);
1540     __ bind(done);
1541   } else {
1542     ShouldNotReachHere();
1543   }
1544 }
1545 
1546 void LIR_Assembler::casw(Register addr, Register newval, Register cmpval) {
1547   __ cmpxchg(addr, cmpval, newval, Assembler::word, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1548   __ cset(rscratch1, Assembler::NE);
1549   __ membar(__ AnyAny);
1550 }
1551 
1552 void LIR_Assembler::casl(Register addr, Register newval, Register cmpval) {
1553   __ cmpxchg(addr, cmpval, newval, Assembler::xword, /* acquire*/ true, /* release*/ true, /* weak*/ false, rscratch1);
1554   __ cset(rscratch1, Assembler::NE);
1555   __ membar(__ AnyAny);
1556 }
1557 
1558 
1559 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1560   assert(VM_Version::supports_cx8(), "wrong machine");
1561   Register addr;
1562   if (op->addr()->is_register()) {
1563     addr = as_reg(op->addr());
1564   } else {
1565     assert(op->addr()->is_address(), "what else?");
1566     LIR_Address* addr_ptr = op->addr()->as_address_ptr();
1567     assert(addr_ptr->disp() == 0, "need 0 disp");
1568     assert(addr_ptr->index() == LIR_OprDesc::illegalOpr(), "need 0 index");
1569     addr = as_reg(addr_ptr->base());
1570   }
1571   Register newval = as_reg(op->new_value());
1572   Register cmpval = as_reg(op->cmp_value());
1573 
1574   if (op->code() == lir_cas_obj) {
1575     if (UseCompressedOops) {
1576       Register t1 = op->tmp1()->as_register();
1577       assert(op->tmp1()->is_valid(), "must be");
1578       __ encode_heap_oop(t1, cmpval);
1579       cmpval = t1;
1580       __ encode_heap_oop(rscratch2, newval);
1581       newval = rscratch2;
1582       casw(addr, newval, cmpval);
1583     } else {
1584       casl(addr, newval, cmpval);
1585     }
1586   } else if (op->code() == lir_cas_int) {
1587     casw(addr, newval, cmpval);
1588   } else {
1589     casl(addr, newval, cmpval);
1590   }
1591 }
1592 
1593 
1594 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1595 
1596   Assembler::Condition acond, ncond;
1597   switch (condition) {
1598   case lir_cond_equal:        acond = Assembler::EQ; ncond = Assembler::NE; break;
1599   case lir_cond_notEqual:     acond = Assembler::NE; ncond = Assembler::EQ; break;
1600   case lir_cond_less:         acond = Assembler::LT; ncond = Assembler::GE; break;
1601   case lir_cond_lessEqual:    acond = Assembler::LE; ncond = Assembler::GT; break;
1602   case lir_cond_greaterEqual: acond = Assembler::GE; ncond = Assembler::LT; break;
1603   case lir_cond_greater:      acond = Assembler::GT; ncond = Assembler::LE; break;
1604   case lir_cond_belowEqual:
1605   case lir_cond_aboveEqual:
1606   default:                    ShouldNotReachHere();
1607     acond = Assembler::EQ; ncond = Assembler::NE;  // unreachable
1608   }
1609 
1610   assert(result->is_single_cpu() || result->is_double_cpu(),
1611          "expect single register for result");
1612   if (opr1->is_constant() && opr2->is_constant()
1613       && opr1->type() == T_INT && opr2->type() == T_INT) {
1614     jint val1 = opr1->as_jint();
1615     jint val2 = opr2->as_jint();
1616     if (val1 == 0 && val2 == 1) {
1617       __ cset(result->as_register(), ncond);
1618       return;
1619     } else if (val1 == 1 && val2 == 0) {
1620       __ cset(result->as_register(), acond);
1621       return;
1622     }
1623   }
1624 
1625   if (opr1->is_constant() && opr2->is_constant()
1626       && opr1->type() == T_LONG && opr2->type() == T_LONG) {
1627     jlong val1 = opr1->as_jlong();
1628     jlong val2 = opr2->as_jlong();
1629     if (val1 == 0 && val2 == 1) {
1630       __ cset(result->as_register_lo(), ncond);
1631       return;
1632     } else if (val1 == 1 && val2 == 0) {
1633       __ cset(result->as_register_lo(), acond);
1634       return;
1635     }
1636   }
1637 
1638   if (opr1->is_stack()) {
1639     stack2reg(opr1, FrameMap::rscratch1_opr, result->type());
1640     opr1 = FrameMap::rscratch1_opr;
1641   } else if (opr1->is_constant()) {
1642     LIR_Opr tmp
1643       = opr1->type() == T_LONG ? FrameMap::rscratch1_long_opr : FrameMap::rscratch1_opr;
1644     const2reg(opr1, tmp, lir_patch_none, NULL);
1645     opr1 = tmp;
1646   }
1647 
1648   if (opr2->is_stack()) {
1649     stack2reg(opr2, FrameMap::rscratch2_opr, result->type());
1650     opr2 = FrameMap::rscratch2_opr;
1651   } else if (opr2->is_constant()) {
1652     LIR_Opr tmp
1653       = opr2->type() == T_LONG ? FrameMap::rscratch2_long_opr : FrameMap::rscratch2_opr;
1654     const2reg(opr2, tmp, lir_patch_none, NULL);
1655     opr2 = tmp;
1656   }
1657 
1658   if (result->type() == T_LONG)
1659     __ csel(result->as_register_lo(), opr1->as_register_lo(), opr2->as_register_lo(), acond);
1660   else
1661     __ csel(result->as_register(), opr1->as_register(), opr2->as_register(), acond);
1662 }
1663 
1664 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
1665   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
1666 
1667   if (left->is_single_cpu()) {
1668     Register lreg = left->as_register();
1669     Register dreg = as_reg(dest);
1670 
1671     if (right->is_single_cpu()) {
1672       // cpu register - cpu register
1673 
1674       assert(left->type() == T_INT && right->type() == T_INT && dest->type() == T_INT,
1675              "should be");
1676       Register rreg = right->as_register();
1677       switch (code) {
1678       case lir_add: __ addw (dest->as_register(), lreg, rreg); break;
1679       case lir_sub: __ subw (dest->as_register(), lreg, rreg); break;
1680       case lir_mul: __ mulw (dest->as_register(), lreg, rreg); break;
1681       default:      ShouldNotReachHere();
1682       }
1683 
1684     } else if (right->is_double_cpu()) {
1685       Register rreg = right->as_register_lo();
1686       // single_cpu + double_cpu: can happen with obj+long
1687       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1688       switch (code) {
1689       case lir_add: __ add(dreg, lreg, rreg); break;
1690       case lir_sub: __ sub(dreg, lreg, rreg); break;
1691       default: ShouldNotReachHere();
1692       }
1693     } else if (right->is_constant()) {
1694       // cpu register - constant
1695       jlong c;
1696 
1697       // FIXME.  This is fugly: we really need to factor all this logic.
1698       switch(right->type()) {
1699       case T_LONG:
1700         c = right->as_constant_ptr()->as_jlong();
1701         break;
1702       case T_INT:
1703       case T_ADDRESS:
1704         c = right->as_constant_ptr()->as_jint();
1705         break;
1706       default:
1707         ShouldNotReachHere();
1708         c = 0;  // unreachable
1709         break;
1710       }
1711 
1712       assert(code == lir_add || code == lir_sub, "mismatched arithmetic op");
1713       if (c == 0 && dreg == lreg) {
1714         COMMENT("effective nop elided");
1715         return;
1716       }
1717       switch(left->type()) {
1718       case T_INT:
1719         switch (code) {
1720         case lir_add: __ addw(dreg, lreg, c); break;
1721         case lir_sub: __ subw(dreg, lreg, c); break;
1722         default: ShouldNotReachHere();
1723         }
1724         break;
1725       case T_OBJECT:
1726       case T_ADDRESS:
1727         switch (code) {
1728         case lir_add: __ add(dreg, lreg, c); break;
1729         case lir_sub: __ sub(dreg, lreg, c); break;
1730         default: ShouldNotReachHere();
1731         }
1732         break;
1733       default:
1734         ShouldNotReachHere();
1735       }
1736     } else {
1737       ShouldNotReachHere();
1738     }
1739 
1740   } else if (left->is_double_cpu()) {
1741     Register lreg_lo = left->as_register_lo();
1742 
1743     if (right->is_double_cpu()) {
1744       // cpu register - cpu register
1745       Register rreg_lo = right->as_register_lo();
1746       switch (code) {
1747       case lir_add: __ add (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1748       case lir_sub: __ sub (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1749       case lir_mul: __ mul (dest->as_register_lo(), lreg_lo, rreg_lo); break;
1750       case lir_div: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, false, rscratch1); break;
1751       case lir_rem: __ corrected_idivq(dest->as_register_lo(), lreg_lo, rreg_lo, true, rscratch1); break;
1752       default:
1753         ShouldNotReachHere();
1754       }
1755 
1756     } else if (right->is_constant()) {
1757       jlong c = right->as_constant_ptr()->as_jlong();
1758       Register dreg = as_reg(dest);
1759       switch (code) {
1760         case lir_add:
1761         case lir_sub:
1762           if (c == 0 && dreg == lreg_lo) {
1763             COMMENT("effective nop elided");
1764             return;
1765           }
1766           code == lir_add ? __ add(dreg, lreg_lo, c) : __ sub(dreg, lreg_lo, c);
1767           break;
1768         case lir_div:
1769           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1770           if (c == 1) {
1771             // move lreg_lo to dreg if divisor is 1
1772             __ mov(dreg, lreg_lo);
1773           } else {
1774             unsigned int shift = log2i_exact(c);
1775             // use rscratch1 as intermediate result register
1776             __ asr(rscratch1, lreg_lo, 63);
1777             __ add(rscratch1, lreg_lo, rscratch1, Assembler::LSR, 64 - shift);
1778             __ asr(dreg, rscratch1, shift);
1779           }
1780           break;
1781         case lir_rem:
1782           assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1783           if (c == 1) {
1784             // move 0 to dreg if divisor is 1
1785             __ mov(dreg, zr);
1786           } else {
1787             // use rscratch1 as intermediate result register
1788             __ negs(rscratch1, lreg_lo);
1789             __ andr(dreg, lreg_lo, c - 1);
1790             __ andr(rscratch1, rscratch1, c - 1);
1791             __ csneg(dreg, dreg, rscratch1, Assembler::MI);
1792           }
1793           break;
1794         default:
1795           ShouldNotReachHere();
1796       }
1797     } else {
1798       ShouldNotReachHere();
1799     }
1800   } else if (left->is_single_fpu()) {
1801     assert(right->is_single_fpu(), "right hand side of float arithmetics needs to be float register");
1802     switch (code) {
1803     case lir_add: __ fadds (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1804     case lir_sub: __ fsubs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1805     case lir_mul: __ fmuls (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1806     case lir_div: __ fdivs (dest->as_float_reg(), left->as_float_reg(), right->as_float_reg()); break;
1807     default:
1808       ShouldNotReachHere();
1809     }
1810   } else if (left->is_double_fpu()) {
1811     if (right->is_double_fpu()) {
1812       // fpu register - fpu register
1813       switch (code) {
1814       case lir_add: __ faddd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1815       case lir_sub: __ fsubd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1816       case lir_mul: __ fmuld (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1817       case lir_div: __ fdivd (dest->as_double_reg(), left->as_double_reg(), right->as_double_reg()); break;
1818       default:
1819         ShouldNotReachHere();
1820       }
1821     } else {
1822       if (right->is_constant()) {
1823         ShouldNotReachHere();
1824       }
1825       ShouldNotReachHere();
1826     }
1827   } else if (left->is_single_stack() || left->is_address()) {
1828     assert(left == dest, "left and dest must be equal");
1829     ShouldNotReachHere();
1830   } else {
1831     ShouldNotReachHere();
1832   }
1833 }
1834 
1835 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) { Unimplemented(); }
1836 
1837 
1838 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr unused, LIR_Opr dest, LIR_Op* op) {
1839   switch(code) {
1840   case lir_abs : __ fabsd(dest->as_double_reg(), value->as_double_reg()); break;
1841   case lir_sqrt: __ fsqrtd(dest->as_double_reg(), value->as_double_reg()); break;
1842   default      : ShouldNotReachHere();
1843   }
1844 }
1845 
1846 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
1847 
1848   assert(left->is_single_cpu() || left->is_double_cpu(), "expect single or double register");
1849   Register Rleft = left->is_single_cpu() ? left->as_register() :
1850                                            left->as_register_lo();
1851    if (dst->is_single_cpu()) {
1852      Register Rdst = dst->as_register();
1853      if (right->is_constant()) {
1854        switch (code) {
1855          case lir_logic_and: __ andw (Rdst, Rleft, right->as_jint()); break;
1856          case lir_logic_or:  __ orrw (Rdst, Rleft, right->as_jint()); break;
1857          case lir_logic_xor: __ eorw (Rdst, Rleft, right->as_jint()); break;
1858          default: ShouldNotReachHere(); break;
1859        }
1860      } else {
1861        Register Rright = right->is_single_cpu() ? right->as_register() :
1862                                                   right->as_register_lo();
1863        switch (code) {
1864          case lir_logic_and: __ andw (Rdst, Rleft, Rright); break;
1865          case lir_logic_or:  __ orrw (Rdst, Rleft, Rright); break;
1866          case lir_logic_xor: __ eorw (Rdst, Rleft, Rright); break;
1867          default: ShouldNotReachHere(); break;
1868        }
1869      }
1870    } else {
1871      Register Rdst = dst->as_register_lo();
1872      if (right->is_constant()) {
1873        switch (code) {
1874          case lir_logic_and: __ andr (Rdst, Rleft, right->as_jlong()); break;
1875          case lir_logic_or:  __ orr (Rdst, Rleft, right->as_jlong()); break;
1876          case lir_logic_xor: __ eor (Rdst, Rleft, right->as_jlong()); break;
1877          default: ShouldNotReachHere(); break;
1878        }
1879      } else {
1880        Register Rright = right->is_single_cpu() ? right->as_register() :
1881                                                   right->as_register_lo();
1882        switch (code) {
1883          case lir_logic_and: __ andr (Rdst, Rleft, Rright); break;
1884          case lir_logic_or:  __ orr (Rdst, Rleft, Rright); break;
1885          case lir_logic_xor: __ eor (Rdst, Rleft, Rright); break;
1886          default: ShouldNotReachHere(); break;
1887        }
1888      }
1889    }
1890 }
1891 
1892 
1893 
1894 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr illegal, LIR_Opr result, CodeEmitInfo* info) {
1895 
1896   // opcode check
1897   assert((code == lir_idiv) || (code == lir_irem), "opcode must be idiv or irem");
1898   bool is_irem = (code == lir_irem);
1899 
1900   // operand check
1901   assert(left->is_single_cpu(),   "left must be register");
1902   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
1903   assert(result->is_single_cpu(), "result must be register");
1904   Register lreg = left->as_register();
1905   Register dreg = result->as_register();
1906 
1907   // power-of-2 constant check and codegen
1908   if (right->is_constant()) {
1909     int c = right->as_constant_ptr()->as_jint();
1910     assert(c > 0 && is_power_of_2(c), "divisor must be power-of-2 constant");
1911     if (is_irem) {
1912       if (c == 1) {
1913         // move 0 to dreg if divisor is 1
1914         __ movw(dreg, zr);
1915       } else {
1916         // use rscratch1 as intermediate result register
1917         __ negsw(rscratch1, lreg);
1918         __ andw(dreg, lreg, c - 1);
1919         __ andw(rscratch1, rscratch1, c - 1);
1920         __ csnegw(dreg, dreg, rscratch1, Assembler::MI);
1921       }
1922     } else {
1923       if (c == 1) {
1924         // move lreg to dreg if divisor is 1
1925         __ movw(dreg, lreg);
1926       } else {
1927         unsigned int shift = exact_log2(c);
1928         // use rscratch1 as intermediate result register
1929         __ asrw(rscratch1, lreg, 31);
1930         __ addw(rscratch1, lreg, rscratch1, Assembler::LSR, 32 - shift);
1931         __ asrw(dreg, rscratch1, shift);
1932       }
1933     }
1934   } else {
1935     Register rreg = right->as_register();
1936     __ corrected_idivl(dreg, lreg, rreg, is_irem, rscratch1);
1937   }
1938 }
1939 
1940 
1941 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
1942   if (opr1->is_constant() && opr2->is_single_cpu()) {
1943     // tableswitch
1944     Register reg = as_reg(opr2);
1945     struct tableswitch &table = switches[opr1->as_constant_ptr()->as_jint()];
1946     __ tableswitch(reg, table._first_key, table._last_key, table._branches, table._after);
1947   } else if (opr1->is_single_cpu() || opr1->is_double_cpu()) {
1948     Register reg1 = as_reg(opr1);
1949     if (opr2->is_single_cpu()) {
1950       // cpu register - cpu register
1951       Register reg2 = opr2->as_register();
1952       if (is_reference_type(opr1->type())) {
1953         __ cmpoop(reg1, reg2);
1954       } else {
1955         assert(!is_reference_type(opr2->type()), "cmp int, oop?");
1956         __ cmpw(reg1, reg2);
1957       }
1958       return;
1959     }
1960     if (opr2->is_double_cpu()) {
1961       // cpu register - cpu register
1962       Register reg2 = opr2->as_register_lo();
1963       __ cmp(reg1, reg2);
1964       return;
1965     }
1966 
1967     if (opr2->is_constant()) {
1968       bool is_32bit = false; // width of register operand
1969       jlong imm;
1970 
1971       switch(opr2->type()) {
1972       case T_INT:
1973         imm = opr2->as_constant_ptr()->as_jint();
1974         is_32bit = true;
1975         break;
1976       case T_LONG:
1977         imm = opr2->as_constant_ptr()->as_jlong();
1978         break;
1979       case T_ADDRESS:
1980         imm = opr2->as_constant_ptr()->as_jint();
1981         break;
1982       case T_METADATA:
1983         imm = (intptr_t)(opr2->as_constant_ptr()->as_metadata());
1984         break;
1985       case T_OBJECT:
1986       case T_ARRAY:
1987         jobject2reg(opr2->as_constant_ptr()->as_jobject(), rscratch1);
1988         __ cmpoop(reg1, rscratch1);
1989         return;
1990       default:
1991         ShouldNotReachHere();
1992         imm = 0;  // unreachable
1993         break;
1994       }
1995 
1996       if (Assembler::operand_valid_for_add_sub_immediate(imm)) {
1997         if (is_32bit)
1998           __ cmpw(reg1, imm);
1999         else
2000           __ subs(zr, reg1, imm);
2001         return;
2002       } else {
2003         __ mov(rscratch1, imm);
2004         if (is_32bit)
2005           __ cmpw(reg1, rscratch1);
2006         else
2007           __ cmp(reg1, rscratch1);
2008         return;
2009       }
2010     } else
2011       ShouldNotReachHere();
2012   } else if (opr1->is_single_fpu()) {
2013     FloatRegister reg1 = opr1->as_float_reg();
2014     assert(opr2->is_single_fpu(), "expect single float register");
2015     FloatRegister reg2 = opr2->as_float_reg();
2016     __ fcmps(reg1, reg2);
2017   } else if (opr1->is_double_fpu()) {
2018     FloatRegister reg1 = opr1->as_double_reg();
2019     assert(opr2->is_double_fpu(), "expect double float register");
2020     FloatRegister reg2 = opr2->as_double_reg();
2021     __ fcmpd(reg1, reg2);
2022   } else {
2023     ShouldNotReachHere();
2024   }
2025 }
2026 
2027 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){
2028   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2029     bool is_unordered_less = (code == lir_ucmp_fd2i);
2030     if (left->is_single_fpu()) {
2031       __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register());
2032     } else if (left->is_double_fpu()) {
2033       __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register());
2034     } else {
2035       ShouldNotReachHere();
2036     }
2037   } else if (code == lir_cmp_l2i) {
2038     Label done;
2039     __ cmp(left->as_register_lo(), right->as_register_lo());
2040     __ mov(dst->as_register(), (uint64_t)-1L);
2041     __ br(Assembler::LT, done);
2042     __ csinc(dst->as_register(), zr, zr, Assembler::EQ);
2043     __ bind(done);
2044   } else {
2045     ShouldNotReachHere();
2046   }
2047 }
2048 
2049 
2050 void LIR_Assembler::align_call(LIR_Code code) {  }
2051 
2052 
2053 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2054   address call = __ trampoline_call(Address(op->addr(), rtype));
2055   if (call == NULL) {
2056     bailout("trampoline stub overflow");
2057     return;
2058   }
2059   add_call_info(code_offset(), op->info());
2060   __ post_call_nop();
2061 }
2062 
2063 
2064 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2065   address call = __ ic_call(op->addr());
2066   if (call == NULL) {
2067     bailout("trampoline stub overflow");
2068     return;
2069   }
2070   add_call_info(code_offset(), op->info());
2071   __ post_call_nop();
2072 }
2073 
2074 void LIR_Assembler::emit_static_call_stub() {
2075   address call_pc = __ pc();
2076   address stub = __ start_a_stub(call_stub_size());
2077   if (stub == NULL) {
2078     bailout("static call stub overflow");
2079     return;
2080   }
2081 
2082   int start = __ offset();
2083 
2084   __ relocate(static_stub_Relocation::spec(call_pc));
2085   __ emit_static_call_stub();
2086 
2087   assert(__ offset() - start + CompiledStaticCall::to_trampoline_stub_size()
2088         <= call_stub_size(), "stub too big");
2089   __ end_a_stub();
2090 }
2091 
2092 
2093 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2094   assert(exceptionOop->as_register() == r0, "must match");
2095   assert(exceptionPC->as_register() == r3, "must match");
2096 
2097   // exception object is not added to oop map by LinearScan
2098   // (LinearScan assumes that no oops are in fixed registers)
2099   info->add_register_oop(exceptionOop);
2100   Runtime1::StubID unwind_id;
2101 
2102   // get current pc information
2103   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2104   if (compilation()->debug_info_recorder()->last_pc_offset() == __ offset()) {
2105     // As no instructions have been generated yet for this LIR node it's
2106     // possible that an oop map already exists for the current offset.
2107     // In that case insert an dummy NOP here to ensure all oop map PCs
2108     // are unique. See JDK-8237483.
2109     __ nop();
2110   }
2111   int pc_for_athrow_offset = __ offset();
2112   InternalAddress pc_for_athrow(__ pc());
2113   __ adr(exceptionPC->as_register(), pc_for_athrow);
2114   add_call_info(pc_for_athrow_offset, info); // for exception handler
2115 
2116   __ verify_not_null_oop(r0);
2117   // search an exception handler (r0: exception oop, r3: throwing pc)
2118   if (compilation()->has_fpu_code()) {
2119     unwind_id = Runtime1::handle_exception_id;
2120   } else {
2121     unwind_id = Runtime1::handle_exception_nofpu_id;
2122   }
2123   __ far_call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2124 
2125   // FIXME: enough room for two byte trap   ????
2126   __ nop();
2127 }
2128 
2129 
2130 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2131   assert(exceptionOop->as_register() == r0, "must match");
2132 
2133   __ b(_unwind_handler_entry);
2134 }
2135 
2136 
2137 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2138   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2139   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2140 
2141   switch (left->type()) {
2142     case T_INT: {
2143       switch (code) {
2144       case lir_shl:  __ lslvw (dreg, lreg, count->as_register()); break;
2145       case lir_shr:  __ asrvw (dreg, lreg, count->as_register()); break;
2146       case lir_ushr: __ lsrvw (dreg, lreg, count->as_register()); break;
2147       default:
2148         ShouldNotReachHere();
2149         break;
2150       }
2151       break;
2152     case T_LONG:
2153     case T_ADDRESS:
2154     case T_OBJECT:
2155       switch (code) {
2156       case lir_shl:  __ lslv (dreg, lreg, count->as_register()); break;
2157       case lir_shr:  __ asrv (dreg, lreg, count->as_register()); break;
2158       case lir_ushr: __ lsrv (dreg, lreg, count->as_register()); break;
2159       default:
2160         ShouldNotReachHere();
2161         break;
2162       }
2163       break;
2164     default:
2165       ShouldNotReachHere();
2166       break;
2167     }
2168   }
2169 }
2170 
2171 
2172 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2173   Register dreg = dest->is_single_cpu() ? dest->as_register() : dest->as_register_lo();
2174   Register lreg = left->is_single_cpu() ? left->as_register() : left->as_register_lo();
2175 
2176   switch (left->type()) {
2177     case T_INT: {
2178       switch (code) {
2179       case lir_shl:  __ lslw (dreg, lreg, count); break;
2180       case lir_shr:  __ asrw (dreg, lreg, count); break;
2181       case lir_ushr: __ lsrw (dreg, lreg, count); break;
2182       default:
2183         ShouldNotReachHere();
2184         break;
2185       }
2186       break;
2187     case T_LONG:
2188     case T_ADDRESS:
2189     case T_OBJECT:
2190       switch (code) {
2191       case lir_shl:  __ lsl (dreg, lreg, count); break;
2192       case lir_shr:  __ asr (dreg, lreg, count); break;
2193       case lir_ushr: __ lsr (dreg, lreg, count); break;
2194       default:
2195         ShouldNotReachHere();
2196         break;
2197       }
2198       break;
2199     default:
2200       ShouldNotReachHere();
2201       break;
2202     }
2203   }
2204 }
2205 
2206 
2207 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
2208   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2209   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2210   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2211   __ str (r, Address(sp, offset_from_rsp_in_bytes));
2212 }
2213 
2214 
2215 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
2216   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2217   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2218   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2219   __ mov (rscratch1, c);
2220   __ str (rscratch1, Address(sp, offset_from_rsp_in_bytes));
2221 }
2222 
2223 
2224 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
2225   ShouldNotReachHere();
2226   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
2227   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
2228   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
2229   __ lea(rscratch1, __ constant_oop_address(o));
2230   __ str(rscratch1, Address(sp, offset_from_rsp_in_bytes));
2231 }
2232 
2233 
2234 // This code replaces a call to arraycopy; no exception may
2235 // be thrown in this code, they must be thrown in the System.arraycopy
2236 // activation frame; we could save some checks if this would not be the case
2237 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
2238   ciArrayKlass* default_type = op->expected_type();
2239   Register src = op->src()->as_register();
2240   Register dst = op->dst()->as_register();
2241   Register src_pos = op->src_pos()->as_register();
2242   Register dst_pos = op->dst_pos()->as_register();
2243   Register length  = op->length()->as_register();
2244   Register tmp = op->tmp()->as_register();
2245 
2246   CodeStub* stub = op->stub();
2247   int flags = op->flags();
2248   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
2249   if (is_reference_type(basic_type)) basic_type = T_OBJECT;
2250 
2251   // if we don't know anything, just go through the generic arraycopy
2252   if (default_type == NULL // || basic_type == T_OBJECT
2253       ) {
2254     Label done;
2255     assert(src == r1 && src_pos == r2, "mismatch in calling convention");
2256 
2257     // Save the arguments in case the generic arraycopy fails and we
2258     // have to fall back to the JNI stub
2259     __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2260     __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2261     __ str(src,              Address(sp, 4*BytesPerWord));
2262 
2263     address copyfunc_addr = StubRoutines::generic_arraycopy();
2264     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
2265 
2266     // The arguments are in java calling convention so we shift them
2267     // to C convention
2268     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
2269     __ mov(c_rarg0, j_rarg0);
2270     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
2271     __ mov(c_rarg1, j_rarg1);
2272     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
2273     __ mov(c_rarg2, j_rarg2);
2274     assert_different_registers(c_rarg3, j_rarg4);
2275     __ mov(c_rarg3, j_rarg3);
2276     __ mov(c_rarg4, j_rarg4);
2277 #ifndef PRODUCT
2278     if (PrintC1Statistics) {
2279       __ incrementw(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
2280     }
2281 #endif
2282     __ far_call(RuntimeAddress(copyfunc_addr));
2283 
2284     __ cbz(r0, *stub->continuation());
2285 
2286     // Reload values from the stack so they are where the stub
2287     // expects them.
2288     __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2289     __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2290     __ ldr(src,              Address(sp, 4*BytesPerWord));
2291 
2292     // r0 is -1^K where K == partial copied count
2293     __ eonw(rscratch1, r0, zr);
2294     // adjust length down and src/end pos up by partial copied count
2295     __ subw(length, length, rscratch1);
2296     __ addw(src_pos, src_pos, rscratch1);
2297     __ addw(dst_pos, dst_pos, rscratch1);
2298     __ b(*stub->entry());
2299 
2300     __ bind(*stub->continuation());
2301     return;
2302   }
2303 
2304   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
2305 
2306   int elem_size = type2aelembytes(basic_type);
2307   int scale = exact_log2(elem_size);
2308 
2309   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
2310   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
2311   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
2312   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
2313 
2314   // test for NULL
2315   if (flags & LIR_OpArrayCopy::src_null_check) {
2316     __ cbz(src, *stub->entry());
2317   }
2318   if (flags & LIR_OpArrayCopy::dst_null_check) {
2319     __ cbz(dst, *stub->entry());
2320   }
2321 
2322   // If the compiler was not able to prove that exact type of the source or the destination
2323   // of the arraycopy is an array type, check at runtime if the source or the destination is
2324   // an instance type.
2325   if (flags & LIR_OpArrayCopy::type_check) {
2326     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::dst_objarray)) {
2327       __ load_klass(tmp, dst);
2328       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2329       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2330       __ br(Assembler::GE, *stub->entry());
2331     }
2332 
2333     if (!(flags & LIR_OpArrayCopy::LIR_OpArrayCopy::src_objarray)) {
2334       __ load_klass(tmp, src);
2335       __ ldrw(rscratch1, Address(tmp, in_bytes(Klass::layout_helper_offset())));
2336       __ cmpw(rscratch1, Klass::_lh_neutral_value);
2337       __ br(Assembler::GE, *stub->entry());
2338     }
2339   }
2340 
2341   // check if negative
2342   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
2343     __ cmpw(src_pos, 0);
2344     __ br(Assembler::LT, *stub->entry());
2345   }
2346   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
2347     __ cmpw(dst_pos, 0);
2348     __ br(Assembler::LT, *stub->entry());
2349   }
2350 
2351   if (flags & LIR_OpArrayCopy::length_positive_check) {
2352     __ cmpw(length, 0);
2353     __ br(Assembler::LT, *stub->entry());
2354   }
2355 
2356   if (flags & LIR_OpArrayCopy::src_range_check) {
2357     __ addw(tmp, src_pos, length);
2358     __ ldrw(rscratch1, src_length_addr);
2359     __ cmpw(tmp, rscratch1);
2360     __ br(Assembler::HI, *stub->entry());
2361   }
2362   if (flags & LIR_OpArrayCopy::dst_range_check) {
2363     __ addw(tmp, dst_pos, length);
2364     __ ldrw(rscratch1, dst_length_addr);
2365     __ cmpw(tmp, rscratch1);
2366     __ br(Assembler::HI, *stub->entry());
2367   }
2368 
2369   if (flags & LIR_OpArrayCopy::type_check) {
2370     // We don't know the array types are compatible
2371     if (basic_type != T_OBJECT) {
2372       // Simple test for basic type arrays
2373       if (UseCompressedClassPointers) {
2374         __ ldrw(tmp, src_klass_addr);
2375         __ ldrw(rscratch1, dst_klass_addr);
2376         __ cmpw(tmp, rscratch1);
2377       } else {
2378         __ ldr(tmp, src_klass_addr);
2379         __ ldr(rscratch1, dst_klass_addr);
2380         __ cmp(tmp, rscratch1);
2381       }
2382       __ br(Assembler::NE, *stub->entry());
2383     } else {
2384       // For object arrays, if src is a sub class of dst then we can
2385       // safely do the copy.
2386       Label cont, slow;
2387 
2388 #define PUSH(r1, r2)                                    \
2389       stp(r1, r2, __ pre(sp, -2 * wordSize));
2390 
2391 #define POP(r1, r2)                                     \
2392       ldp(r1, r2, __ post(sp, 2 * wordSize));
2393 
2394       __ PUSH(src, dst);
2395 
2396       __ load_klass(src, src);
2397       __ load_klass(dst, dst);
2398 
2399       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
2400 
2401       __ PUSH(src, dst);
2402       __ far_call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
2403       __ POP(src, dst);
2404 
2405       __ cbnz(src, cont);
2406 
2407       __ bind(slow);
2408       __ POP(src, dst);
2409 
2410       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
2411       if (copyfunc_addr != NULL) { // use stub if available
2412         // src is not a sub class of dst so we have to do a
2413         // per-element check.
2414 
2415         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
2416         if ((flags & mask) != mask) {
2417           // Check that at least both of them object arrays.
2418           assert(flags & mask, "one of the two should be known to be an object array");
2419 
2420           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
2421             __ load_klass(tmp, src);
2422           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
2423             __ load_klass(tmp, dst);
2424           }
2425           int lh_offset = in_bytes(Klass::layout_helper_offset());
2426           Address klass_lh_addr(tmp, lh_offset);
2427           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
2428           __ ldrw(rscratch1, klass_lh_addr);
2429           __ mov(rscratch2, objArray_lh);
2430           __ eorw(rscratch1, rscratch1, rscratch2);
2431           __ cbnzw(rscratch1, *stub->entry());
2432         }
2433 
2434        // Spill because stubs can use any register they like and it's
2435        // easier to restore just those that we care about.
2436         __ stp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2437         __ stp(length,  src_pos, Address(sp, 2*BytesPerWord));
2438         __ str(src,              Address(sp, 4*BytesPerWord));
2439 
2440         __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2441         __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2442         assert_different_registers(c_rarg0, dst, dst_pos, length);
2443         __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2444         __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2445         assert_different_registers(c_rarg1, dst, length);
2446         __ uxtw(c_rarg2, length);
2447         assert_different_registers(c_rarg2, dst);
2448 
2449         __ load_klass(c_rarg4, dst);
2450         __ ldr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
2451         __ ldrw(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
2452         __ far_call(RuntimeAddress(copyfunc_addr));
2453 
2454 #ifndef PRODUCT
2455         if (PrintC1Statistics) {
2456           Label failed;
2457           __ cbnz(r0, failed);
2458           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
2459           __ bind(failed);
2460         }
2461 #endif
2462 
2463         __ cbz(r0, *stub->continuation());
2464 
2465 #ifndef PRODUCT
2466         if (PrintC1Statistics) {
2467           __ incrementw(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
2468         }
2469 #endif
2470         assert_different_registers(dst, dst_pos, length, src_pos, src, r0, rscratch1);
2471 
2472         // Restore previously spilled arguments
2473         __ ldp(dst,     dst_pos, Address(sp, 0*BytesPerWord));
2474         __ ldp(length,  src_pos, Address(sp, 2*BytesPerWord));
2475         __ ldr(src,              Address(sp, 4*BytesPerWord));
2476 
2477         // return value is -1^K where K is partial copied count
2478         __ eonw(rscratch1, r0, zr);
2479         // adjust length down and src/end pos up by partial copied count
2480         __ subw(length, length, rscratch1);
2481         __ addw(src_pos, src_pos, rscratch1);
2482         __ addw(dst_pos, dst_pos, rscratch1);
2483       }
2484 
2485       __ b(*stub->entry());
2486 
2487       __ bind(cont);
2488       __ POP(src, dst);
2489     }
2490   }
2491 
2492 #ifdef ASSERT
2493   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
2494     // Sanity check the known type with the incoming class.  For the
2495     // primitive case the types must match exactly with src.klass and
2496     // dst.klass each exactly matching the default type.  For the
2497     // object array case, if no type check is needed then either the
2498     // dst type is exactly the expected type and the src type is a
2499     // subtype which we can't check or src is the same array as dst
2500     // but not necessarily exactly of type default_type.
2501     Label known_ok, halt;
2502     __ mov_metadata(tmp, default_type->constant_encoding());
2503     if (UseCompressedClassPointers) {
2504       __ encode_klass_not_null(tmp);
2505     }
2506 
2507     if (basic_type != T_OBJECT) {
2508 
2509       if (UseCompressedClassPointers) {
2510         __ ldrw(rscratch1, dst_klass_addr);
2511         __ cmpw(tmp, rscratch1);
2512       } else {
2513         __ ldr(rscratch1, dst_klass_addr);
2514         __ cmp(tmp, rscratch1);
2515       }
2516       __ br(Assembler::NE, halt);
2517       if (UseCompressedClassPointers) {
2518         __ ldrw(rscratch1, src_klass_addr);
2519         __ cmpw(tmp, rscratch1);
2520       } else {
2521         __ ldr(rscratch1, src_klass_addr);
2522         __ cmp(tmp, rscratch1);
2523       }
2524       __ br(Assembler::EQ, known_ok);
2525     } else {
2526       if (UseCompressedClassPointers) {
2527         __ ldrw(rscratch1, dst_klass_addr);
2528         __ cmpw(tmp, rscratch1);
2529       } else {
2530         __ ldr(rscratch1, dst_klass_addr);
2531         __ cmp(tmp, rscratch1);
2532       }
2533       __ br(Assembler::EQ, known_ok);
2534       __ cmp(src, dst);
2535       __ br(Assembler::EQ, known_ok);
2536     }
2537     __ bind(halt);
2538     __ stop("incorrect type information in arraycopy");
2539     __ bind(known_ok);
2540   }
2541 #endif
2542 
2543 #ifndef PRODUCT
2544   if (PrintC1Statistics) {
2545     __ incrementw(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
2546   }
2547 #endif
2548 
2549   __ lea(c_rarg0, Address(src, src_pos, Address::uxtw(scale)));
2550   __ add(c_rarg0, c_rarg0, arrayOopDesc::base_offset_in_bytes(basic_type));
2551   assert_different_registers(c_rarg0, dst, dst_pos, length);
2552   __ lea(c_rarg1, Address(dst, dst_pos, Address::uxtw(scale)));
2553   __ add(c_rarg1, c_rarg1, arrayOopDesc::base_offset_in_bytes(basic_type));
2554   assert_different_registers(c_rarg1, dst, length);
2555   __ uxtw(c_rarg2, length);
2556   assert_different_registers(c_rarg2, dst);
2557 
2558   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
2559   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
2560   const char *name;
2561   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
2562 
2563  CodeBlob *cb = CodeCache::find_blob(entry);
2564  if (cb) {
2565    __ far_call(RuntimeAddress(entry));
2566  } else {
2567    __ call_VM_leaf(entry, 3);
2568  }
2569 
2570   __ bind(*stub->continuation());
2571 }
2572 
2573 
2574 
2575 
2576 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
2577   Register obj = op->obj_opr()->as_register();  // may not be an oop
2578   Register hdr = op->hdr_opr()->as_register();
2579   Register lock = op->lock_opr()->as_register();
2580   if (!UseFastLocking) {
2581     __ b(*op->stub()->entry());
2582   } else if (op->code() == lir_lock) {
2583     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2584     // add debug info for NullPointerException only if one is possible
2585     int null_check_offset = __ lock_object(hdr, obj, lock, *op->stub()->entry());
2586     if (op->info() != NULL) {
2587       add_debug_info_for_null_check(null_check_offset, op->info());
2588     }
2589     // done
2590   } else if (op->code() == lir_unlock) {
2591     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
2592     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
2593   } else {
2594     Unimplemented();
2595   }
2596   if (op->code() == lir_lock) {
2597     // If deoptimization happens in Runtime1::monitorenter, inc_held_monitor_count after backing from slowpath
2598     // will be skipped. Solution is:
2599     // 1. Increase only in fastpath
2600     // 2. Runtime1::monitorenter increase count after locking
2601     __ inc_held_monitor_count(rthread);
2602   }
2603   __ bind(*op->stub()->continuation());
2604   if (op->code() == lir_unlock) {
2605     // unlock in slowpath is JRT_Leaf stub, no deoptimization can happen
2606     __ dec_held_monitor_count(rthread);
2607   }
2608 }
2609 
2610 
2611 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
2612   ciMethod* method = op->profiled_method();
2613   int bci          = op->profiled_bci();
2614   ciMethod* callee = op->profiled_callee();
2615 
2616   // Update counter for all call types
2617   ciMethodData* md = method->method_data_or_null();
2618   assert(md != NULL, "Sanity");
2619   ciProfileData* data = md->bci_to_data(bci);
2620   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
2621   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
2622   Register mdo  = op->mdo()->as_register();
2623   __ mov_metadata(mdo, md->constant_encoding());
2624   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
2625   // Perform additional virtual call profiling for invokevirtual and
2626   // invokeinterface bytecodes
2627   if (op->should_profile_receiver_type()) {
2628     assert(op->recv()->is_single_cpu(), "recv must be allocated");
2629     Register recv = op->recv()->as_register();
2630     assert_different_registers(mdo, recv);
2631     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
2632     ciKlass* known_klass = op->known_holder();
2633     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
2634       // We know the type that will be seen at this call site; we can
2635       // statically update the MethodData* rather than needing to do
2636       // dynamic tests on the receiver type
2637 
2638       // NOTE: we should probably put a lock around this search to
2639       // avoid collisions by concurrent compilations
2640       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
2641       uint i;
2642       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2643         ciKlass* receiver = vc_data->receiver(i);
2644         if (known_klass->equals(receiver)) {
2645           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2646           __ addptr(data_addr, DataLayout::counter_increment);
2647           return;
2648         }
2649       }
2650 
2651       // Receiver type not found in profile data; select an empty slot
2652 
2653       // Note that this is less efficient than it should be because it
2654       // always does a write to the receiver part of the
2655       // VirtualCallData rather than just the first time
2656       for (i = 0; i < VirtualCallData::row_limit(); i++) {
2657         ciKlass* receiver = vc_data->receiver(i);
2658         if (receiver == NULL) {
2659           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
2660           __ mov_metadata(rscratch1, known_klass->constant_encoding());
2661           __ lea(rscratch2, recv_addr);
2662           __ str(rscratch1, Address(rscratch2));
2663           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
2664           __ addptr(data_addr, DataLayout::counter_increment);
2665           return;
2666         }
2667       }
2668     } else {
2669       __ load_klass(recv, recv);
2670       Label update_done;
2671       type_profile_helper(mdo, md, data, recv, &update_done);
2672       // Receiver did not match any saved receiver and there is no empty row for it.
2673       // Increment total counter to indicate polymorphic case.
2674       __ addptr(counter_addr, DataLayout::counter_increment);
2675 
2676       __ bind(update_done);
2677     }
2678   } else {
2679     // Static call
2680     __ addptr(counter_addr, DataLayout::counter_increment);
2681   }
2682 }
2683 
2684 
2685 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
2686   Unimplemented();
2687 }
2688 
2689 
2690 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
2691   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
2692 }
2693 
2694 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
2695   assert(op->crc()->is_single_cpu(),  "crc must be register");
2696   assert(op->val()->is_single_cpu(),  "byte value must be register");
2697   assert(op->result_opr()->is_single_cpu(), "result must be register");
2698   Register crc = op->crc()->as_register();
2699   Register val = op->val()->as_register();
2700   Register res = op->result_opr()->as_register();
2701 
2702   assert_different_registers(val, crc, res);
2703   uint64_t offset;
2704   __ adrp(res, ExternalAddress(StubRoutines::crc_table_addr()), offset);
2705   if (offset) __ add(res, res, offset);
2706 
2707   __ mvnw(crc, crc); // ~crc
2708   __ update_byte_crc32(crc, val, res);
2709   __ mvnw(res, crc); // ~crc
2710 }
2711 
2712 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
2713   COMMENT("emit_profile_type {");
2714   Register obj = op->obj()->as_register();
2715   Register tmp = op->tmp()->as_pointer_register();
2716   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
2717   ciKlass* exact_klass = op->exact_klass();
2718   intptr_t current_klass = op->current_klass();
2719   bool not_null = op->not_null();
2720   bool no_conflict = op->no_conflict();
2721 
2722   Label update, next, none;
2723 
2724   bool do_null = !not_null;
2725   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
2726   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
2727 
2728   assert(do_null || do_update, "why are we here?");
2729   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
2730   assert(mdo_addr.base() != rscratch1, "wrong register");
2731 
2732   __ verify_oop(obj);
2733 
2734   if (tmp != obj) {
2735     __ mov(tmp, obj);
2736   }
2737   if (do_null) {
2738     __ cbnz(tmp, update);
2739     if (!TypeEntries::was_null_seen(current_klass)) {
2740       __ ldr(rscratch2, mdo_addr);
2741       __ orr(rscratch2, rscratch2, TypeEntries::null_seen);
2742       __ str(rscratch2, mdo_addr);
2743     }
2744     if (do_update) {
2745 #ifndef ASSERT
2746       __ b(next);
2747     }
2748 #else
2749       __ b(next);
2750     }
2751   } else {
2752     __ cbnz(tmp, update);
2753     __ stop("unexpected null obj");
2754 #endif
2755   }
2756 
2757   __ bind(update);
2758 
2759   if (do_update) {
2760 #ifdef ASSERT
2761     if (exact_klass != NULL) {
2762       Label ok;
2763       __ load_klass(tmp, tmp);
2764       __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2765       __ eor(rscratch1, tmp, rscratch1);
2766       __ cbz(rscratch1, ok);
2767       __ stop("exact klass and actual klass differ");
2768       __ bind(ok);
2769     }
2770 #endif
2771     if (!no_conflict) {
2772       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
2773         if (exact_klass != NULL) {
2774           __ mov_metadata(tmp, exact_klass->constant_encoding());
2775         } else {
2776           __ load_klass(tmp, tmp);
2777         }
2778 
2779         __ ldr(rscratch2, mdo_addr);
2780         __ eor(tmp, tmp, rscratch2);
2781         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2782         // klass seen before, nothing to do. The unknown bit may have been
2783         // set already but no need to check.
2784         __ cbz(rscratch1, next);
2785 
2786         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2787 
2788         if (TypeEntries::is_type_none(current_klass)) {
2789           __ cbz(rscratch2, none);
2790           __ cmp(rscratch2, (u1)TypeEntries::null_seen);
2791           __ br(Assembler::EQ, none);
2792           // There is a chance that the checks above (re-reading profiling
2793           // data from memory) fail if another thread has just set the
2794           // profiling to this obj's klass
2795           __ dmb(Assembler::ISHLD);
2796           __ ldr(rscratch2, mdo_addr);
2797           __ eor(tmp, tmp, rscratch2);
2798           __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2799           __ cbz(rscratch1, next);
2800         }
2801       } else {
2802         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2803                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
2804 
2805         __ ldr(tmp, mdo_addr);
2806         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2807       }
2808 
2809       // different than before. Cannot keep accurate profile.
2810       __ ldr(rscratch2, mdo_addr);
2811       __ orr(rscratch2, rscratch2, TypeEntries::type_unknown);
2812       __ str(rscratch2, mdo_addr);
2813 
2814       if (TypeEntries::is_type_none(current_klass)) {
2815         __ b(next);
2816 
2817         __ bind(none);
2818         // first time here. Set profile type.
2819         __ str(tmp, mdo_addr);
2820       }
2821     } else {
2822       // There's a single possible klass at this profile point
2823       assert(exact_klass != NULL, "should be");
2824       if (TypeEntries::is_type_none(current_klass)) {
2825         __ mov_metadata(tmp, exact_klass->constant_encoding());
2826         __ ldr(rscratch2, mdo_addr);
2827         __ eor(tmp, tmp, rscratch2);
2828         __ andr(rscratch1, tmp, TypeEntries::type_klass_mask);
2829         __ cbz(rscratch1, next);
2830 #ifdef ASSERT
2831         {
2832           Label ok;
2833           __ ldr(rscratch1, mdo_addr);
2834           __ cbz(rscratch1, ok);
2835           __ cmp(rscratch1, (u1)TypeEntries::null_seen);
2836           __ br(Assembler::EQ, ok);
2837           // may have been set by another thread
2838           __ dmb(Assembler::ISHLD);
2839           __ mov_metadata(rscratch1, exact_klass->constant_encoding());
2840           __ ldr(rscratch2, mdo_addr);
2841           __ eor(rscratch2, rscratch1, rscratch2);
2842           __ andr(rscratch2, rscratch2, TypeEntries::type_mask);
2843           __ cbz(rscratch2, ok);
2844 
2845           __ stop("unexpected profiling mismatch");
2846           __ bind(ok);
2847         }
2848 #endif
2849         // first time here. Set profile type.
2850         __ str(tmp, mdo_addr);
2851       } else {
2852         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
2853                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
2854 
2855         __ ldr(tmp, mdo_addr);
2856         __ tbnz(tmp, exact_log2(TypeEntries::type_unknown), next); // already unknown. Nothing to do anymore.
2857 
2858         __ orr(tmp, tmp, TypeEntries::type_unknown);
2859         __ str(tmp, mdo_addr);
2860         // FIXME: Write barrier needed here?
2861       }
2862     }
2863 
2864     __ bind(next);
2865   }
2866   COMMENT("} emit_profile_type");
2867 }
2868 
2869 
2870 void LIR_Assembler::align_backward_branch_target() {
2871 }
2872 
2873 
2874 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
2875   // tmp must be unused
2876   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2877 
2878   if (left->is_single_cpu()) {
2879     assert(dest->is_single_cpu(), "expect single result reg");
2880     __ negw(dest->as_register(), left->as_register());
2881   } else if (left->is_double_cpu()) {
2882     assert(dest->is_double_cpu(), "expect double result reg");
2883     __ neg(dest->as_register_lo(), left->as_register_lo());
2884   } else if (left->is_single_fpu()) {
2885     assert(dest->is_single_fpu(), "expect single float result reg");
2886     __ fnegs(dest->as_float_reg(), left->as_float_reg());
2887   } else {
2888     assert(left->is_double_fpu(), "expect double float operand reg");
2889     assert(dest->is_double_fpu(), "expect double float result reg");
2890     __ fnegd(dest->as_double_reg(), left->as_double_reg());
2891   }
2892 }
2893 
2894 
2895 void LIR_Assembler::leal(LIR_Opr addr, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
2896   if (patch_code != lir_patch_none) {
2897     deoptimize_trap(info);
2898     return;
2899   }
2900 
2901   __ lea(dest->as_register_lo(), as_Address(addr->as_address_ptr()));
2902 }
2903 
2904 
2905 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
2906   assert(!tmp->is_valid(), "don't need temporary");
2907 
2908   CodeBlob *cb = CodeCache::find_blob(dest);
2909   if (cb) {
2910     __ far_call(RuntimeAddress(dest));
2911   } else {
2912     __ mov(rscratch1, RuntimeAddress(dest));
2913     __ blr(rscratch1);
2914   }
2915 
2916   if (info != NULL) {
2917     add_call_info_here(info);
2918   }
2919   __ post_call_nop();
2920 }
2921 
2922 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
2923   if (dest->is_address() || src->is_address()) {
2924     move_op(src, dest, type, lir_patch_none, info,
2925             /*pop_fpu_stack*/false, /*wide*/false);
2926   } else {
2927     ShouldNotReachHere();
2928   }
2929 }
2930 
2931 #ifdef ASSERT
2932 // emit run-time assertion
2933 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
2934   assert(op->code() == lir_assert, "must be");
2935 
2936   if (op->in_opr1()->is_valid()) {
2937     assert(op->in_opr2()->is_valid(), "both operands must be valid");
2938     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
2939   } else {
2940     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
2941     assert(op->condition() == lir_cond_always, "no other conditions allowed");
2942   }
2943 
2944   Label ok;
2945   if (op->condition() != lir_cond_always) {
2946     Assembler::Condition acond = Assembler::AL;
2947     switch (op->condition()) {
2948       case lir_cond_equal:        acond = Assembler::EQ;  break;
2949       case lir_cond_notEqual:     acond = Assembler::NE;  break;
2950       case lir_cond_less:         acond = Assembler::LT;  break;
2951       case lir_cond_lessEqual:    acond = Assembler::LE;  break;
2952       case lir_cond_greaterEqual: acond = Assembler::GE;  break;
2953       case lir_cond_greater:      acond = Assembler::GT;  break;
2954       case lir_cond_belowEqual:   acond = Assembler::LS;  break;
2955       case lir_cond_aboveEqual:   acond = Assembler::HS;  break;
2956       default:                    ShouldNotReachHere();
2957     }
2958     __ br(acond, ok);
2959   }
2960   if (op->halt()) {
2961     const char* str = __ code_string(op->msg());
2962     __ stop(str);
2963   } else {
2964     breakpoint();
2965   }
2966   __ bind(ok);
2967 }
2968 #endif
2969 
2970 #ifndef PRODUCT
2971 #define COMMENT(x)   do { __ block_comment(x); } while (0)
2972 #else
2973 #define COMMENT(x)
2974 #endif
2975 
2976 void LIR_Assembler::membar() {
2977   COMMENT("membar");
2978   __ membar(MacroAssembler::AnyAny);
2979 }
2980 
2981 void LIR_Assembler::membar_acquire() {
2982   __ membar(Assembler::LoadLoad|Assembler::LoadStore);
2983 }
2984 
2985 void LIR_Assembler::membar_release() {
2986   __ membar(Assembler::LoadStore|Assembler::StoreStore);
2987 }
2988 
2989 void LIR_Assembler::membar_loadload() {
2990   __ membar(Assembler::LoadLoad);
2991 }
2992 
2993 void LIR_Assembler::membar_storestore() {
2994   __ membar(MacroAssembler::StoreStore);
2995 }
2996 
2997 void LIR_Assembler::membar_loadstore() { __ membar(MacroAssembler::LoadStore); }
2998 
2999 void LIR_Assembler::membar_storeload() { __ membar(MacroAssembler::StoreLoad); }
3000 
3001 void LIR_Assembler::on_spin_wait() {
3002   Unimplemented();
3003 }
3004 
3005 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
3006   __ mov(result_reg->as_register(), rthread);
3007 }
3008 
3009 
3010 void LIR_Assembler::peephole(LIR_List *lir) {
3011 #if 0
3012   if (tableswitch_count >= max_tableswitches)
3013     return;
3014 
3015   /*
3016     This finite-state automaton recognizes sequences of compare-and-
3017     branch instructions.  We will turn them into a tableswitch.  You
3018     could argue that C1 really shouldn't be doing this sort of
3019     optimization, but without it the code is really horrible.
3020   */
3021 
3022   enum { start_s, cmp1_s, beq_s, cmp_s } state;
3023   int first_key, last_key = -2147483648;
3024   int next_key = 0;
3025   int start_insn = -1;
3026   int last_insn = -1;
3027   Register reg = noreg;
3028   LIR_Opr reg_opr;
3029   state = start_s;
3030 
3031   LIR_OpList* inst = lir->instructions_list();
3032   for (int i = 0; i < inst->length(); i++) {
3033     LIR_Op* op = inst->at(i);
3034     switch (state) {
3035     case start_s:
3036       first_key = -1;
3037       start_insn = i;
3038       switch (op->code()) {
3039       case lir_cmp:
3040         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3041         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3042         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3043             && opr2->is_constant()
3044             && opr2->type() == T_INT) {
3045           reg_opr = opr1;
3046           reg = opr1->as_register();
3047           first_key = opr2->as_constant_ptr()->as_jint();
3048           next_key = first_key + 1;
3049           state = cmp_s;
3050           goto next_state;
3051         }
3052         break;
3053       }
3054       break;
3055     case cmp_s:
3056       switch (op->code()) {
3057       case lir_branch:
3058         if (op->as_OpBranch()->cond() == lir_cond_equal) {
3059           state = beq_s;
3060           last_insn = i;
3061           goto next_state;
3062         }
3063       }
3064       state = start_s;
3065       break;
3066     case beq_s:
3067       switch (op->code()) {
3068       case lir_cmp: {
3069         LIR_Opr opr1 = op->as_Op2()->in_opr1();
3070         LIR_Opr opr2 = op->as_Op2()->in_opr2();
3071         if (opr1->is_cpu_register() && opr1->is_single_cpu()
3072             && opr1->as_register() == reg
3073             && opr2->is_constant()
3074             && opr2->type() == T_INT
3075             && opr2->as_constant_ptr()->as_jint() == next_key) {
3076           last_key = next_key;
3077           next_key++;
3078           state = cmp_s;
3079           goto next_state;
3080         }
3081       }
3082       }
3083       last_key = next_key;
3084       state = start_s;
3085       break;
3086     default:
3087       assert(false, "impossible state");
3088     }
3089     if (state == start_s) {
3090       if (first_key < last_key - 5L && reg != noreg) {
3091         {
3092           // printf("found run register %d starting at insn %d low value %d high value %d\n",
3093           //        reg->encoding(),
3094           //        start_insn, first_key, last_key);
3095           //   for (int i = 0; i < inst->length(); i++) {
3096           //     inst->at(i)->print();
3097           //     tty->print("\n");
3098           //   }
3099           //   tty->print("\n");
3100         }
3101 
3102         struct tableswitch *sw = &switches[tableswitch_count];
3103         sw->_insn_index = start_insn, sw->_first_key = first_key,
3104           sw->_last_key = last_key, sw->_reg = reg;
3105         inst->insert_before(last_insn + 1, new LIR_OpLabel(&sw->_after));
3106         {
3107           // Insert the new table of branches
3108           int offset = last_insn;
3109           for (int n = first_key; n < last_key; n++) {
3110             inst->insert_before
3111               (last_insn + 1,
3112                new LIR_OpBranch(lir_cond_always, T_ILLEGAL,
3113                                 inst->at(offset)->as_OpBranch()->label()));
3114             offset -= 2, i++;
3115           }
3116         }
3117         // Delete all the old compare-and-branch instructions
3118         for (int n = first_key; n < last_key; n++) {
3119           inst->remove_at(start_insn);
3120           inst->remove_at(start_insn);
3121         }
3122         // Insert the tableswitch instruction
3123         inst->insert_before(start_insn,
3124                             new LIR_Op2(lir_cmp, lir_cond_always,
3125                                         LIR_OprFact::intConst(tableswitch_count),
3126                                         reg_opr));
3127         inst->insert_before(start_insn + 1, new LIR_OpLabel(&sw->_branches));
3128         tableswitch_count++;
3129       }
3130       reg = noreg;
3131       last_key = -2147483648;
3132     }
3133   next_state:
3134     ;
3135   }
3136 #endif
3137 }
3138 
3139 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp_op) {
3140   Address addr = as_Address(src->as_address_ptr());
3141   BasicType type = src->type();
3142   bool is_oop = is_reference_type(type);
3143 
3144   void (MacroAssembler::* add)(Register prev, RegisterOrConstant incr, Register addr);
3145   void (MacroAssembler::* xchg)(Register prev, Register newv, Register addr);
3146 
3147   switch(type) {
3148   case T_INT:
3149     xchg = &MacroAssembler::atomic_xchgalw;
3150     add = &MacroAssembler::atomic_addalw;
3151     break;
3152   case T_LONG:
3153     xchg = &MacroAssembler::atomic_xchgal;
3154     add = &MacroAssembler::atomic_addal;
3155     break;
3156   case T_OBJECT:
3157   case T_ARRAY:
3158     if (UseCompressedOops) {
3159       xchg = &MacroAssembler::atomic_xchgalw;
3160       add = &MacroAssembler::atomic_addalw;
3161     } else {
3162       xchg = &MacroAssembler::atomic_xchgal;
3163       add = &MacroAssembler::atomic_addal;
3164     }
3165     break;
3166   default:
3167     ShouldNotReachHere();
3168     xchg = &MacroAssembler::atomic_xchgal;
3169     add = &MacroAssembler::atomic_addal; // unreachable
3170   }
3171 
3172   switch (code) {
3173   case lir_xadd:
3174     {
3175       RegisterOrConstant inc;
3176       Register tmp = as_reg(tmp_op);
3177       Register dst = as_reg(dest);
3178       if (data->is_constant()) {
3179         inc = RegisterOrConstant(as_long(data));
3180         assert_different_registers(dst, addr.base(), tmp,
3181                                    rscratch1, rscratch2);
3182       } else {
3183         inc = RegisterOrConstant(as_reg(data));
3184         assert_different_registers(inc.as_register(), dst, addr.base(), tmp,
3185                                    rscratch1, rscratch2);
3186       }
3187       __ lea(tmp, addr);
3188       (_masm->*add)(dst, inc, tmp);
3189       break;
3190     }
3191   case lir_xchg:
3192     {
3193       Register tmp = tmp_op->as_register();
3194       Register obj = as_reg(data);
3195       Register dst = as_reg(dest);
3196       if (is_oop && UseCompressedOops) {
3197         __ encode_heap_oop(rscratch2, obj);
3198         obj = rscratch2;
3199       }
3200       assert_different_registers(obj, addr.base(), tmp, rscratch1, dst);
3201       __ lea(tmp, addr);
3202       (_masm->*xchg)(dst, obj, tmp);
3203       if (is_oop && UseCompressedOops) {
3204         __ decode_heap_oop(dst);
3205       }
3206     }
3207     break;
3208   default:
3209     ShouldNotReachHere();
3210   }
3211   __ membar(__ AnyAny);
3212 }
3213 
3214 #undef __