1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "interpreter/interpreterRuntime.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151
152 static uint32_t insn_at(address insn_addr, int n) {
153 return ((uint32_t*)insn_addr)[n];
154 }
155
156 template<typename T>
157 class RelocActions : public AllStatic {
158
159 public:
160
161 static int ALWAYSINLINE run(address insn_addr, address &target) {
162 int instructions = 1;
163 uint32_t insn = insn_at(insn_addr, 0);
164
165 uint32_t dispatch = Instruction_aarch64::extract(insn, 30, 25);
166 switch(dispatch) {
167 case 0b001010:
168 case 0b001011: {
169 instructions = T::unconditionalBranch(insn_addr, target);
170 break;
171 }
172 case 0b101010: // Conditional branch (immediate)
173 case 0b011010: { // Compare & branch (immediate)
174 instructions = T::conditionalBranch(insn_addr, target);
175 break;
176 }
177 case 0b011011: {
178 instructions = T::testAndBranch(insn_addr, target);
179 break;
180 }
181 case 0b001100:
182 case 0b001110:
183 case 0b011100:
184 case 0b011110:
185 case 0b101100:
186 case 0b101110:
187 case 0b111100:
188 case 0b111110: {
189 // load/store
190 if ((Instruction_aarch64::extract(insn, 29, 24) & 0b111011) == 0b011000) {
191 // Load register (literal)
192 instructions = T::loadStore(insn_addr, target);
193 break;
194 } else {
195 // nothing to do
196 assert(target == nullptr, "did not expect to relocate target for polling page load");
197 }
198 break;
199 }
200 case 0b001000:
201 case 0b011000:
202 case 0b101000:
203 case 0b111000: {
204 // adr/adrp
205 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
206 int shift = Instruction_aarch64::extract(insn, 31, 31);
207 if (shift) {
208 uint32_t insn2 = insn_at(insn_addr, 1);
209 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
210 Instruction_aarch64::extract(insn, 4, 0) ==
211 Instruction_aarch64::extract(insn2, 9, 5)) {
212 instructions = T::adrp(insn_addr, target, T::adrpMem);
213 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
214 Instruction_aarch64::extract(insn, 4, 0) ==
215 Instruction_aarch64::extract(insn2, 4, 0)) {
216 instructions = T::adrp(insn_addr, target, T::adrpAdd);
217 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
218 Instruction_aarch64::extract(insn, 4, 0) ==
219 Instruction_aarch64::extract(insn2, 4, 0)) {
220 instructions = T::adrp(insn_addr, target, T::adrpMovk);
221 } else {
222 ShouldNotReachHere();
223 }
224 } else {
225 instructions = T::adr(insn_addr, target);
226 }
227 break;
228 }
229 case 0b001001:
230 case 0b011001:
231 case 0b101001:
232 case 0b111001: {
233 instructions = T::immediate(insn_addr, target);
234 break;
235 }
236 default: {
237 ShouldNotReachHere();
238 }
239 }
240
241 T::verify(insn_addr, target);
242 return instructions * NativeInstruction::instruction_size;
243 }
244 };
245
246 class Patcher : public AllStatic {
247 public:
248 static int unconditionalBranch(address insn_addr, address &target) {
249 intptr_t offset = (target - insn_addr) >> 2;
250 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
251 return 1;
252 }
253 static int conditionalBranch(address insn_addr, address &target) {
254 intptr_t offset = (target - insn_addr) >> 2;
255 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
256 return 1;
257 }
258 static int testAndBranch(address insn_addr, address &target) {
259 intptr_t offset = (target - insn_addr) >> 2;
260 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
261 return 1;
262 }
263 static int loadStore(address insn_addr, address &target) {
264 intptr_t offset = (target - insn_addr) >> 2;
265 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
266 return 1;
267 }
268 static int adr(address insn_addr, address &target) {
269 #ifdef ASSERT
270 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
271 #endif
272 // PC-rel. addressing
273 ptrdiff_t offset = target - insn_addr;
274 int offset_lo = offset & 3;
275 offset >>= 2;
276 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
277 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
278 return 1;
279 }
280 template<typename U>
281 static int adrp(address insn_addr, address &target, U inner) {
282 int instructions = 1;
283 #ifdef ASSERT
284 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 28, 24) == 0b10000, "must be");
285 #endif
286 ptrdiff_t offset = target - insn_addr;
287 instructions = 2;
288 precond(inner != nullptr);
289 // Give the inner reloc a chance to modify the target.
290 address adjusted_target = target;
291 instructions = inner(insn_addr, adjusted_target);
292 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
293 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
294 offset = adr_page - pc_page;
295 int offset_lo = offset & 3;
296 offset >>= 2;
297 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
298 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
299 return instructions;
300 }
301 static int adrpMem(address insn_addr, address &target) {
302 uintptr_t dest = (uintptr_t)target;
303 int offset_lo = dest & 0xfff;
304 uint32_t insn2 = insn_at(insn_addr, 1);
305 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
306 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
307 guarantee(((dest >> size) << size) == dest, "misaligned target");
308 return 2;
309 }
310 static int adrpAdd(address insn_addr, address &target) {
311 uintptr_t dest = (uintptr_t)target;
312 int offset_lo = dest & 0xfff;
313 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
314 return 2;
315 }
316 static int adrpMovk(address insn_addr, address &target) {
317 uintptr_t dest = uintptr_t(target);
318 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
319 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
320 target = address(dest);
321 return 2;
322 }
323 static int immediate(address insn_addr, address &target) {
324 assert(Instruction_aarch64::extract(insn_at(insn_addr, 0), 31, 21) == 0b11010010100, "must be");
325 uint64_t dest = (uint64_t)target;
326 // Move wide constant
327 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
328 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
329 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
330 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
331 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
332 return 3;
333 }
334 static void verify(address insn_addr, address &target) {
335 #ifdef ASSERT
336 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
337 if (!(address_is == target)) {
338 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
339 disnm((intptr_t)insn_addr);
340 assert(address_is == target, "should be");
341 }
342 #endif
343 }
344 };
345
346 // If insn1 and insn2 use the same register to form an address, either
347 // by an offsetted LDR or a simple ADD, return the offset. If the
348 // second instruction is an LDR, the offset may be scaled.
349 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
350 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
351 Instruction_aarch64::extract(insn1, 4, 0) ==
352 Instruction_aarch64::extract(insn2, 9, 5)) {
353 // Load/store register (unsigned immediate)
354 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
355 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
356 byte_offset <<= size;
357 return true;
358 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
359 Instruction_aarch64::extract(insn1, 4, 0) ==
360 Instruction_aarch64::extract(insn2, 4, 0)) {
361 // add (immediate)
362 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
363 return true;
364 }
365 return false;
366 }
367
368 class AArch64Decoder : public AllStatic {
369 public:
370
371 static int loadStore(address insn_addr, address &target) {
372 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
373 target = insn_addr + (offset << 2);
374 return 1;
375 }
376 static int unconditionalBranch(address insn_addr, address &target) {
377 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 25, 0);
378 target = insn_addr + (offset << 2);
379 return 1;
380 }
381 static int conditionalBranch(address insn_addr, address &target) {
382 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 23, 5);
383 target = address(((uint64_t)insn_addr + (offset << 2)));
384 return 1;
385 }
386 static int testAndBranch(address insn_addr, address &target) {
387 intptr_t offset = Instruction_aarch64::sextract(insn_at(insn_addr, 0), 18, 5);
388 target = address(((uint64_t)insn_addr + (offset << 2)));
389 return 1;
390 }
391 static int adr(address insn_addr, address &target) {
392 // PC-rel. addressing
393 uint32_t insn = insn_at(insn_addr, 0);
394 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
395 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
396 target = address((uint64_t)insn_addr + offset);
397 return 1;
398 }
399 template<typename U>
400 static int adrp(address insn_addr, address &target, U inner) {
401 uint32_t insn = insn_at(insn_addr, 0);
402 assert(Instruction_aarch64::extract(insn, 28, 24) == 0b10000, "must be");
403 intptr_t offset = Instruction_aarch64::extract(insn, 30, 29);
404 offset |= Instruction_aarch64::sextract(insn, 23, 5) << 2;
405 int shift = 12;
406 offset <<= shift;
407 uint64_t target_page = ((uint64_t)insn_addr) + offset;
408 target_page &= ((uint64_t)-1) << shift;
409 uint32_t insn2 = insn_at(insn_addr, 1);
410 target = address(target_page);
411 precond(inner != nullptr);
412 inner(insn_addr, target);
413 return 2;
414 }
415 static int adrpMem(address insn_addr, address &target) {
416 uint32_t insn2 = insn_at(insn_addr, 1);
417 // Load/store register (unsigned immediate)
418 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
419 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
420 byte_offset <<= size;
421 target += byte_offset;
422 return 2;
423 }
424 static int adrpAdd(address insn_addr, address &target) {
425 uint32_t insn2 = insn_at(insn_addr, 1);
426 // add (immediate)
427 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
428 target += byte_offset;
429 return 2;
430 }
431 static int adrpMovk(address insn_addr, address &target) {
432 uint32_t insn2 = insn_at(insn_addr, 1);
433 uint64_t dest = uint64_t(target);
434 dest = (dest & 0xffff0000ffffffff) |
435 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
436 target = address(dest);
437
438 // We know the destination 4k page. Maybe we have a third
439 // instruction.
440 uint32_t insn = insn_at(insn_addr, 0);
441 uint32_t insn3 = insn_at(insn_addr, 2);
442 ptrdiff_t byte_offset;
443 if (offset_for(insn, insn3, byte_offset)) {
444 target += byte_offset;
445 return 3;
446 } else {
447 return 2;
448 }
449 }
450 static int immediate(address insn_addr, address &target) {
451 uint32_t *insns = (uint32_t *)insn_addr;
452 assert(Instruction_aarch64::extract(insns[0], 31, 21) == 0b11010010100, "must be");
453 // Move wide constant: movz, movk, movk. See movptr().
454 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
455 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
456 target = address(uint64_t(Instruction_aarch64::extract(insns[0], 20, 5))
457 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
458 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
459 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
460 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
461 return 3;
462 }
463 static void verify(address insn_addr, address &target) {
464 }
465 };
466
467 address MacroAssembler::target_addr_for_insn(address insn_addr) {
468 address target;
469 RelocActions<AArch64Decoder>::run(insn_addr, target);
470 return target;
471 }
472
473 // Patch any kind of instruction; there may be several instructions.
474 // Return the total length (in bytes) of the instructions.
475 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
476 return RelocActions<Patcher>::run(insn_addr, target);
477 }
478
479 int MacroAssembler::patch_oop(address insn_addr, address o) {
480 int instructions;
481 unsigned insn = *(unsigned*)insn_addr;
482 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
483
484 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
485 // narrow OOPs by setting the upper 16 bits in the first
486 // instruction.
487 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
488 // Move narrow OOP
489 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
490 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
491 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
492 instructions = 2;
493 } else {
494 // Move wide OOP
495 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
496 uintptr_t dest = (uintptr_t)o;
497 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
498 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
499 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
500 instructions = 3;
501 }
502 return instructions * NativeInstruction::instruction_size;
503 }
504
505 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
506 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
507 // We encode narrow ones by setting the upper 16 bits in the first
508 // instruction.
509 NativeInstruction *insn = nativeInstruction_at(insn_addr);
510 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
511 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
512
513 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
514 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
515 return 2 * NativeInstruction::instruction_size;
516 }
517
518 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr) {
519 if (NativeInstruction::is_ldrw_to_zr(insn_addr)) {
520 return nullptr;
521 }
522 return MacroAssembler::target_addr_for_insn(insn_addr);
523 }
524
525 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
526 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
527 if (at_return) {
528 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
529 // we may safely use the sp instead to perform the stack watermark check.
530 cmp(in_nmethod ? sp : rfp, tmp);
531 br(Assembler::HI, slow_path);
532 } else {
533 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
534 }
535 }
536
537 void MacroAssembler::rt_call(address dest, Register tmp) {
538 CodeBlob *cb = CodeCache::find_blob(dest);
539 if (cb) {
540 far_call(RuntimeAddress(dest));
541 } else {
542 lea(tmp, RuntimeAddress(dest));
543 blr(tmp);
544 }
545 }
546
547 void MacroAssembler::push_cont_fastpath(Register java_thread) {
548 if (!Continuations::enabled()) return;
549 Label done;
550 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
551 cmp(sp, rscratch1);
552 br(Assembler::LS, done);
553 mov(rscratch1, sp); // we can't use sp as the source in str
554 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
555 bind(done);
556 }
557
558 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
559 if (!Continuations::enabled()) return;
560 Label done;
561 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
562 cmp(sp, rscratch1);
563 br(Assembler::LO, done);
564 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
565 bind(done);
566 }
567
568 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
569 // we must set sp to zero to clear frame
570 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
571
572 // must clear fp, so that compiled frames are not confused; it is
573 // possible that we need it only for debugging
574 if (clear_fp) {
575 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
576 }
577
578 // Always clear the pc because it could have been set by make_walkable()
579 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
580 }
581
582 // Calls to C land
583 //
584 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
585 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
586 // has to be reset to 0. This is required to allow proper stack traversal.
587 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
588 Register last_java_fp,
589 Register last_java_pc,
590 Register scratch) {
591
592 if (last_java_pc->is_valid()) {
593 str(last_java_pc, Address(rthread,
594 JavaThread::frame_anchor_offset()
595 + JavaFrameAnchor::last_Java_pc_offset()));
596 }
597
598 // determine last_java_sp register
599 if (last_java_sp == sp) {
600 mov(scratch, sp);
601 last_java_sp = scratch;
602 } else if (!last_java_sp->is_valid()) {
603 last_java_sp = esp;
604 }
605
606 // last_java_fp is optional
607 if (last_java_fp->is_valid()) {
608 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
609 }
610
611 // We must set sp last.
612 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
613 }
614
615 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
616 Register last_java_fp,
617 address last_java_pc,
618 Register scratch) {
619 assert(last_java_pc != nullptr, "must provide a valid PC");
620
621 adr(scratch, last_java_pc);
622 str(scratch, Address(rthread,
623 JavaThread::frame_anchor_offset()
624 + JavaFrameAnchor::last_Java_pc_offset()));
625
626 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
627 }
628
629 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
630 Register last_java_fp,
631 Label &L,
632 Register scratch) {
633 if (L.is_bound()) {
634 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
635 } else {
636 InstructionMark im(this);
637 L.add_patch_at(code(), locator());
638 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
639 }
640 }
641
642 static inline bool target_needs_far_branch(address addr) {
643 if (AOTCodeCache::is_on_for_dump()) {
644 return true;
645 }
646 // codecache size <= 128M
647 if (!MacroAssembler::far_branches()) {
648 return false;
649 }
650 // codecache size > 240M
651 if (MacroAssembler::codestub_branch_needs_far_jump()) {
652 return true;
653 }
654 // codecache size: 128M..240M
655 return !CodeCache::is_non_nmethod(addr);
656 }
657
658 void MacroAssembler::far_call(Address entry, Register tmp) {
659 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
660 assert(CodeCache::find_blob(entry.target()) != nullptr,
661 "destination of far call not found in code cache");
662 assert(entry.rspec().type() == relocInfo::external_word_type
663 || entry.rspec().type() == relocInfo::runtime_call_type
664 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
665 if (target_needs_far_branch(entry.target())) {
666 uint64_t offset;
667 // We can use ADRP here because we know that the total size of
668 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
669 adrp(tmp, entry, offset);
670 add(tmp, tmp, offset);
671 blr(tmp);
672 } else {
673 bl(entry);
674 }
675 }
676
677 int MacroAssembler::far_jump(Address entry, Register tmp) {
678 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
679 assert(CodeCache::find_blob(entry.target()) != nullptr,
680 "destination of far call not found in code cache");
681 assert(entry.rspec().type() == relocInfo::external_word_type
682 || entry.rspec().type() == relocInfo::runtime_call_type
683 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
684 address start = pc();
685 if (target_needs_far_branch(entry.target())) {
686 uint64_t offset;
687 // We can use ADRP here because we know that the total size of
688 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
689 adrp(tmp, entry, offset);
690 add(tmp, tmp, offset);
691 br(tmp);
692 } else {
693 b(entry);
694 }
695 return pc() - start;
696 }
697
698 void MacroAssembler::reserved_stack_check() {
699 // testing if reserved zone needs to be enabled
700 Label no_reserved_zone_enabling;
701
702 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
703 cmp(sp, rscratch1);
704 br(Assembler::LO, no_reserved_zone_enabling);
705
706 enter(); // LR and FP are live.
707 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
708 mov(c_rarg0, rthread);
709 blr(rscratch1);
710 leave();
711
712 // We have already removed our own frame.
713 // throw_delayed_StackOverflowError will think that it's been
714 // called by our caller.
715 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
716 br(rscratch1);
717 should_not_reach_here();
718
719 bind(no_reserved_zone_enabling);
720 }
721
722 static void pass_arg0(MacroAssembler* masm, Register arg) {
723 if (c_rarg0 != arg ) {
724 masm->mov(c_rarg0, arg);
725 }
726 }
727
728 static void pass_arg1(MacroAssembler* masm, Register arg) {
729 if (c_rarg1 != arg ) {
730 masm->mov(c_rarg1, arg);
731 }
732 }
733
734 static void pass_arg2(MacroAssembler* masm, Register arg) {
735 if (c_rarg2 != arg ) {
736 masm->mov(c_rarg2, arg);
737 }
738 }
739
740 static void pass_arg3(MacroAssembler* masm, Register arg) {
741 if (c_rarg3 != arg ) {
742 masm->mov(c_rarg3, arg);
743 }
744 }
745
746 static bool is_preemptable(address entry_point) {
747 return entry_point == CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter);
748 }
749
750 void MacroAssembler::call_VM_base(Register oop_result,
751 Register java_thread,
752 Register last_java_sp,
753 address entry_point,
754 int number_of_arguments,
755 bool check_exceptions) {
756 // determine java_thread register
757 if (!java_thread->is_valid()) {
758 java_thread = rthread;
759 }
760
761 // determine last_java_sp register
762 if (!last_java_sp->is_valid()) {
763 last_java_sp = esp;
764 }
765
766 // debugging support
767 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
768 assert(java_thread == rthread, "unexpected register");
769 #ifdef ASSERT
770 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
771 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
772 #endif // ASSERT
773
774 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
775 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
776
777 // push java thread (becomes first argument of C function)
778
779 mov(c_rarg0, java_thread);
780
781 // set last Java frame before call
782 assert(last_java_sp != rfp, "can't use rfp");
783
784 Label l;
785 if (is_preemptable(entry_point)) {
786 // skip setting last_pc since we already set it to desired value.
787 set_last_Java_frame(last_java_sp, rfp, noreg, rscratch1);
788 } else {
789 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
790 }
791
792 // do the call, remove parameters
793 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
794
795 // lr could be poisoned with PAC signature during throw_pending_exception
796 // if it was tail-call optimized by compiler, since lr is not callee-saved
797 // reload it with proper value
798 adr(lr, l);
799
800 // reset last Java frame
801 // Only interpreter should have to clear fp
802 reset_last_Java_frame(true);
803
804 // C++ interp handles this in the interpreter
805 check_and_handle_popframe(java_thread);
806 check_and_handle_earlyret(java_thread);
807
808 if (check_exceptions) {
809 // check for pending exceptions (java_thread is set upon return)
810 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
811 Label ok;
812 cbz(rscratch1, ok);
813 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
814 br(rscratch1);
815 bind(ok);
816 }
817
818 // get oop result if there is one and reset the value in the thread
819 if (oop_result->is_valid()) {
820 get_vm_result_oop(oop_result, java_thread);
821 }
822 }
823
824 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
825 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
826 }
827
828 // Check the entry target is always reachable from any branch.
829 static bool is_always_within_branch_range(Address entry) {
830 if (AOTCodeCache::is_on_for_dump()) {
831 return false;
832 }
833 const address target = entry.target();
834
835 if (!CodeCache::contains(target)) {
836 // We always use trampolines for callees outside CodeCache.
837 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
838 return false;
839 }
840
841 if (!MacroAssembler::far_branches()) {
842 return true;
843 }
844
845 if (entry.rspec().type() == relocInfo::runtime_call_type) {
846 // Runtime calls are calls of a non-compiled method (stubs, adapters).
847 // Non-compiled methods stay forever in CodeCache.
848 // We check whether the longest possible branch is within the branch range.
849 assert(CodeCache::find_blob(target) != nullptr &&
850 !CodeCache::find_blob(target)->is_nmethod(),
851 "runtime call of compiled method");
852 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
853 const address left_longest_branch_start = CodeCache::low_bound();
854 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
855 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
856 return is_reachable;
857 }
858
859 return false;
860 }
861
862 // Maybe emit a call via a trampoline. If the code cache is small
863 // trampolines won't be emitted.
864 address MacroAssembler::trampoline_call(Address entry) {
865 assert(entry.rspec().type() == relocInfo::runtime_call_type
866 || entry.rspec().type() == relocInfo::opt_virtual_call_type
867 || entry.rspec().type() == relocInfo::static_call_type
868 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
869
870 address target = entry.target();
871
872 if (!is_always_within_branch_range(entry)) {
873 if (!in_scratch_emit_size()) {
874 // We don't want to emit a trampoline if C2 is generating dummy
875 // code during its branch shortening phase.
876 if (entry.rspec().type() == relocInfo::runtime_call_type) {
877 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
878 code()->share_trampoline_for(entry.target(), offset());
879 } else {
880 address stub = emit_trampoline_stub(offset(), target);
881 if (stub == nullptr) {
882 postcond(pc() == badAddress);
883 return nullptr; // CodeCache is full
884 }
885 }
886 }
887 target = pc();
888 }
889
890 address call_pc = pc();
891 relocate(entry.rspec());
892 bl(target);
893
894 postcond(pc() != badAddress);
895 return call_pc;
896 }
897
898 // Emit a trampoline stub for a call to a target which is too far away.
899 //
900 // code sequences:
901 //
902 // call-site:
903 // branch-and-link to <destination> or <trampoline stub>
904 //
905 // Related trampoline stub for this call site in the stub section:
906 // load the call target from the constant pool
907 // branch (LR still points to the call site above)
908
909 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
910 address dest) {
911 // Max stub size: alignment nop, TrampolineStub.
912 address stub = start_a_stub(max_trampoline_stub_size());
913 if (stub == nullptr) {
914 return nullptr; // CodeBuffer::expand failed
915 }
916
917 // Create a trampoline stub relocation which relates this trampoline stub
918 // with the call instruction at insts_call_instruction_offset in the
919 // instructions code-section.
920 align(wordSize);
921 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
922 + insts_call_instruction_offset));
923 const int stub_start_offset = offset();
924
925 // Now, create the trampoline stub's code:
926 // - load the call
927 // - call
928 Label target;
929 ldr(rscratch1, target);
930 br(rscratch1);
931 bind(target);
932 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
933 "should be");
934 emit_int64((int64_t)dest);
935
936 const address stub_start_addr = addr_at(stub_start_offset);
937
938 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
939
940 end_a_stub();
941 return stub_start_addr;
942 }
943
944 int MacroAssembler::max_trampoline_stub_size() {
945 // Max stub size: alignment nop, TrampolineStub.
946 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
947 }
948
949 void MacroAssembler::emit_static_call_stub() {
950 // CompiledDirectCall::set_to_interpreted knows the
951 // exact layout of this stub.
952
953 isb();
954 mov_metadata(rmethod, nullptr);
955
956 // Jump to the entry point of the c2i stub.
957 if (codestub_branch_needs_far_jump()) {
958 movptr(rscratch1, 0);
959 br(rscratch1);
960 } else {
961 b(pc());
962 }
963 }
964
965 int MacroAssembler::static_call_stub_size() {
966 if (!codestub_branch_needs_far_jump()) {
967 // isb; movk; movz; movz; b
968 return 5 * NativeInstruction::instruction_size;
969 }
970 // isb; movk; movz; movz; movk; movz; movz; br
971 return 8 * NativeInstruction::instruction_size;
972 }
973
974 void MacroAssembler::c2bool(Register x) {
975 // implements x == 0 ? 0 : 1
976 // note: must only look at least-significant byte of x
977 // since C-style booleans are stored in one byte
978 // only! (was bug)
979 tst(x, 0xff);
980 cset(x, Assembler::NE);
981 }
982
983 address MacroAssembler::ic_call(address entry, jint method_index) {
984 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
985 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
986 return trampoline_call(Address(entry, rh));
987 }
988
989 int MacroAssembler::ic_check_size() {
990 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
991 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
992 return NativeInstruction::instruction_size * (7 + extra_instructions);
993 } else {
994 return NativeInstruction::instruction_size * (5 + extra_instructions);
995 }
996 }
997
998 int MacroAssembler::ic_check(int end_alignment) {
999 Register receiver = j_rarg0;
1000 Register data = rscratch2;
1001 Register tmp1 = rscratch1;
1002 Register tmp2 = r10;
1003
1004 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1005 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1006 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1007 // before the inline cache check here, and not after
1008 align(end_alignment, offset() + ic_check_size());
1009
1010 int uep_offset = offset();
1011
1012 if (UseCompactObjectHeaders) {
1013 load_narrow_klass_compact(tmp1, receiver);
1014 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1015 cmpw(tmp1, tmp2);
1016 } else if (UseCompressedClassPointers) {
1017 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1018 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1019 cmpw(tmp1, tmp2);
1020 } else {
1021 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1022 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1023 cmp(tmp1, tmp2);
1024 }
1025
1026 Label dont;
1027 br(Assembler::EQ, dont);
1028 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1029 bind(dont);
1030 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1031
1032 return uep_offset;
1033 }
1034
1035 // Implementation of call_VM versions
1036
1037 void MacroAssembler::call_VM(Register oop_result,
1038 address entry_point,
1039 bool check_exceptions) {
1040 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1041 }
1042
1043 void MacroAssembler::call_VM(Register oop_result,
1044 address entry_point,
1045 Register arg_1,
1046 bool check_exceptions) {
1047 pass_arg1(this, arg_1);
1048 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1049 }
1050
1051 void MacroAssembler::call_VM(Register oop_result,
1052 address entry_point,
1053 Register arg_1,
1054 Register arg_2,
1055 bool check_exceptions) {
1056 assert_different_registers(arg_1, c_rarg2);
1057 pass_arg2(this, arg_2);
1058 pass_arg1(this, arg_1);
1059 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1060 }
1061
1062 void MacroAssembler::call_VM(Register oop_result,
1063 address entry_point,
1064 Register arg_1,
1065 Register arg_2,
1066 Register arg_3,
1067 bool check_exceptions) {
1068 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1069 assert_different_registers(arg_2, c_rarg3);
1070 pass_arg3(this, arg_3);
1071
1072 pass_arg2(this, arg_2);
1073
1074 pass_arg1(this, arg_1);
1075 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1076 }
1077
1078 void MacroAssembler::call_VM(Register oop_result,
1079 Register last_java_sp,
1080 address entry_point,
1081 int number_of_arguments,
1082 bool check_exceptions) {
1083 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1084 }
1085
1086 void MacroAssembler::call_VM(Register oop_result,
1087 Register last_java_sp,
1088 address entry_point,
1089 Register arg_1,
1090 bool check_exceptions) {
1091 pass_arg1(this, arg_1);
1092 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1093 }
1094
1095 void MacroAssembler::call_VM(Register oop_result,
1096 Register last_java_sp,
1097 address entry_point,
1098 Register arg_1,
1099 Register arg_2,
1100 bool check_exceptions) {
1101
1102 assert_different_registers(arg_1, c_rarg2);
1103 pass_arg2(this, arg_2);
1104 pass_arg1(this, arg_1);
1105 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1106 }
1107
1108 void MacroAssembler::call_VM(Register oop_result,
1109 Register last_java_sp,
1110 address entry_point,
1111 Register arg_1,
1112 Register arg_2,
1113 Register arg_3,
1114 bool check_exceptions) {
1115 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1116 assert_different_registers(arg_2, c_rarg3);
1117 pass_arg3(this, arg_3);
1118 pass_arg2(this, arg_2);
1119 pass_arg1(this, arg_1);
1120 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1121 }
1122
1123
1124 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1125 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1126 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1127 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1128 }
1129
1130 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1131 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1132 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1133 }
1134
1135 void MacroAssembler::align(int modulus) {
1136 align(modulus, offset());
1137 }
1138
1139 // Ensure that the code at target bytes offset from the current offset() is aligned
1140 // according to modulus.
1141 void MacroAssembler::align(int modulus, int target) {
1142 int delta = target - offset();
1143 while ((offset() + delta) % modulus != 0) nop();
1144 }
1145
1146 void MacroAssembler::post_call_nop() {
1147 if (!Continuations::enabled()) {
1148 return;
1149 }
1150 InstructionMark im(this);
1151 relocate(post_call_nop_Relocation::spec());
1152 InlineSkippedInstructionsCounter skipCounter(this);
1153 nop();
1154 movk(zr, 0);
1155 movk(zr, 0);
1156 }
1157
1158 // these are no-ops overridden by InterpreterMacroAssembler
1159
1160 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1161
1162 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1163
1164 // Look up the method for a megamorphic invokeinterface call.
1165 // The target method is determined by <intf_klass, itable_index>.
1166 // The receiver klass is in recv_klass.
1167 // On success, the result will be in method_result, and execution falls through.
1168 // On failure, execution transfers to the given label.
1169 void MacroAssembler::lookup_interface_method(Register recv_klass,
1170 Register intf_klass,
1171 RegisterOrConstant itable_index,
1172 Register method_result,
1173 Register scan_temp,
1174 Label& L_no_such_interface,
1175 bool return_method) {
1176 assert_different_registers(recv_klass, intf_klass, scan_temp);
1177 assert_different_registers(method_result, intf_klass, scan_temp);
1178 assert(recv_klass != method_result || !return_method,
1179 "recv_klass can be destroyed when method isn't needed");
1180 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1181 "caller must use same register for non-constant itable index as for method");
1182
1183 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1184 int vtable_base = in_bytes(Klass::vtable_start_offset());
1185 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1186 int scan_step = itableOffsetEntry::size() * wordSize;
1187 int vte_size = vtableEntry::size_in_bytes();
1188 assert(vte_size == wordSize, "else adjust times_vte_scale");
1189
1190 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1191
1192 // Could store the aligned, prescaled offset in the klass.
1193 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1194 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1195 add(scan_temp, scan_temp, vtable_base);
1196
1197 if (return_method) {
1198 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1199 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1200 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1201 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1202 if (itentry_off)
1203 add(recv_klass, recv_klass, itentry_off);
1204 }
1205
1206 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1207 // if (scan->interface() == intf) {
1208 // result = (klass + scan->offset() + itable_index);
1209 // }
1210 // }
1211 Label search, found_method;
1212
1213 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1214 cmp(intf_klass, method_result);
1215 br(Assembler::EQ, found_method);
1216 bind(search);
1217 // Check that the previous entry is non-null. A null entry means that
1218 // the receiver class doesn't implement the interface, and wasn't the
1219 // same as when the caller was compiled.
1220 cbz(method_result, L_no_such_interface);
1221 if (itableOffsetEntry::interface_offset() != 0) {
1222 add(scan_temp, scan_temp, scan_step);
1223 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1224 } else {
1225 ldr(method_result, Address(pre(scan_temp, scan_step)));
1226 }
1227 cmp(intf_klass, method_result);
1228 br(Assembler::NE, search);
1229
1230 bind(found_method);
1231
1232 // Got a hit.
1233 if (return_method) {
1234 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1235 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1236 }
1237 }
1238
1239 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1240 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1241 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1242 // The target method is determined by <holder_klass, itable_index>.
1243 // The receiver klass is in recv_klass.
1244 // On success, the result will be in method_result, and execution falls through.
1245 // On failure, execution transfers to the given label.
1246 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1247 Register holder_klass,
1248 Register resolved_klass,
1249 Register method_result,
1250 Register temp_itbl_klass,
1251 Register scan_temp,
1252 int itable_index,
1253 Label& L_no_such_interface) {
1254 // 'method_result' is only used as output register at the very end of this method.
1255 // Until then we can reuse it as 'holder_offset'.
1256 Register holder_offset = method_result;
1257 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1258
1259 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1260 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1261 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1262 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1263
1264 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1265
1266 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1267 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1268 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1269 // temp_itbl_klass = itable[0]._interface;
1270 int vtblEntrySize = vtableEntry::size_in_bytes();
1271 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1272 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1273 mov(holder_offset, zr);
1274 // scan_temp = &(itable[0]._interface)
1275 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1276
1277 // Initial checks:
1278 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1279 // - if (itable[0] == holder_klass), shortcut to "holder found"
1280 // - if (itable[0] == 0), no such interface
1281 cmp(resolved_klass, holder_klass);
1282 br(Assembler::NE, L_loop_search_resolved_entry);
1283 cmp(holder_klass, temp_itbl_klass);
1284 br(Assembler::EQ, L_holder_found);
1285 cbz(temp_itbl_klass, L_no_such_interface);
1286
1287 // Loop: Look for holder_klass record in itable
1288 // do {
1289 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1290 // if (temp_itbl_klass == holder_klass) {
1291 // goto L_holder_found; // Found!
1292 // }
1293 // } while (temp_itbl_klass != 0);
1294 // goto L_no_such_interface // Not found.
1295 Label L_search_holder;
1296 bind(L_search_holder);
1297 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1298 cmp(holder_klass, temp_itbl_klass);
1299 br(Assembler::EQ, L_holder_found);
1300 cbnz(temp_itbl_klass, L_search_holder);
1301
1302 b(L_no_such_interface);
1303
1304 // Loop: Look for resolved_class record in itable
1305 // while (true) {
1306 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1307 // if (temp_itbl_klass == 0) {
1308 // goto L_no_such_interface;
1309 // }
1310 // if (temp_itbl_klass == resolved_klass) {
1311 // goto L_resolved_found; // Found!
1312 // }
1313 // if (temp_itbl_klass == holder_klass) {
1314 // holder_offset = scan_temp;
1315 // }
1316 // }
1317 //
1318 Label L_loop_search_resolved;
1319 bind(L_loop_search_resolved);
1320 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1321 bind(L_loop_search_resolved_entry);
1322 cbz(temp_itbl_klass, L_no_such_interface);
1323 cmp(resolved_klass, temp_itbl_klass);
1324 br(Assembler::EQ, L_resolved_found);
1325 cmp(holder_klass, temp_itbl_klass);
1326 br(Assembler::NE, L_loop_search_resolved);
1327 mov(holder_offset, scan_temp);
1328 b(L_loop_search_resolved);
1329
1330 // See if we already have a holder klass. If not, go and scan for it.
1331 bind(L_resolved_found);
1332 cbz(holder_offset, L_search_holder);
1333 mov(scan_temp, holder_offset);
1334
1335 // Finally, scan_temp contains holder_klass vtable offset
1336 bind(L_holder_found);
1337 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1338 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1339 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1340 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1341 }
1342
1343 // virtual method calling
1344 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1345 RegisterOrConstant vtable_index,
1346 Register method_result) {
1347 assert(vtableEntry::size() * wordSize == 8,
1348 "adjust the scaling in the code below");
1349 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1350
1351 if (vtable_index.is_register()) {
1352 lea(method_result, Address(recv_klass,
1353 vtable_index.as_register(),
1354 Address::lsl(LogBytesPerWord)));
1355 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1356 } else {
1357 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1358 ldr(method_result,
1359 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1360 }
1361 }
1362
1363 void MacroAssembler::check_klass_subtype(Register sub_klass,
1364 Register super_klass,
1365 Register temp_reg,
1366 Label& L_success) {
1367 Label L_failure;
1368 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1369 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1370 bind(L_failure);
1371 }
1372
1373
1374 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1375 Register super_klass,
1376 Register temp_reg,
1377 Label* L_success,
1378 Label* L_failure,
1379 Label* L_slow_path,
1380 Register super_check_offset) {
1381 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1382 bool must_load_sco = ! super_check_offset->is_valid();
1383 if (must_load_sco) {
1384 assert(temp_reg != noreg, "supply either a temp or a register offset");
1385 }
1386
1387 Label L_fallthrough;
1388 int label_nulls = 0;
1389 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1390 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1391 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1392 assert(label_nulls <= 1, "at most one null in the batch");
1393
1394 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1395 Address super_check_offset_addr(super_klass, sco_offset);
1396
1397 // Hacked jmp, which may only be used just before L_fallthrough.
1398 #define final_jmp(label) \
1399 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1400 else b(label) /*omit semi*/
1401
1402 // If the pointers are equal, we are done (e.g., String[] elements).
1403 // This self-check enables sharing of secondary supertype arrays among
1404 // non-primary types such as array-of-interface. Otherwise, each such
1405 // type would need its own customized SSA.
1406 // We move this check to the front of the fast path because many
1407 // type checks are in fact trivially successful in this manner,
1408 // so we get a nicely predicted branch right at the start of the check.
1409 cmp(sub_klass, super_klass);
1410 br(Assembler::EQ, *L_success);
1411
1412 // Check the supertype display:
1413 if (must_load_sco) {
1414 ldrw(temp_reg, super_check_offset_addr);
1415 super_check_offset = temp_reg;
1416 }
1417
1418 Address super_check_addr(sub_klass, super_check_offset);
1419 ldr(rscratch1, super_check_addr);
1420 cmp(super_klass, rscratch1); // load displayed supertype
1421 br(Assembler::EQ, *L_success);
1422
1423 // This check has worked decisively for primary supers.
1424 // Secondary supers are sought in the super_cache ('super_cache_addr').
1425 // (Secondary supers are interfaces and very deeply nested subtypes.)
1426 // This works in the same check above because of a tricky aliasing
1427 // between the super_cache and the primary super display elements.
1428 // (The 'super_check_addr' can address either, as the case requires.)
1429 // Note that the cache is updated below if it does not help us find
1430 // what we need immediately.
1431 // So if it was a primary super, we can just fail immediately.
1432 // Otherwise, it's the slow path for us (no success at this point).
1433
1434 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1435 if (L_failure == &L_fallthrough) {
1436 cbz(rscratch1, *L_slow_path);
1437 } else {
1438 cbnz(rscratch1, *L_failure);
1439 final_jmp(*L_slow_path);
1440 }
1441
1442 bind(L_fallthrough);
1443
1444 #undef final_jmp
1445 }
1446
1447 // These two are taken from x86, but they look generally useful
1448
1449 // scans count pointer sized words at [addr] for occurrence of value,
1450 // generic
1451 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1452 Register scratch) {
1453 Label Lloop, Lexit;
1454 cbz(count, Lexit);
1455 bind(Lloop);
1456 ldr(scratch, post(addr, wordSize));
1457 cmp(value, scratch);
1458 br(EQ, Lexit);
1459 sub(count, count, 1);
1460 cbnz(count, Lloop);
1461 bind(Lexit);
1462 }
1463
1464 // scans count 4 byte words at [addr] for occurrence of value,
1465 // generic
1466 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1467 Register scratch) {
1468 Label Lloop, Lexit;
1469 cbz(count, Lexit);
1470 bind(Lloop);
1471 ldrw(scratch, post(addr, wordSize));
1472 cmpw(value, scratch);
1473 br(EQ, Lexit);
1474 sub(count, count, 1);
1475 cbnz(count, Lloop);
1476 bind(Lexit);
1477 }
1478
1479 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1480 Register super_klass,
1481 Register temp_reg,
1482 Register temp2_reg,
1483 Label* L_success,
1484 Label* L_failure,
1485 bool set_cond_codes) {
1486 // NB! Callers may assume that, when temp2_reg is a valid register,
1487 // this code sets it to a nonzero value.
1488
1489 assert_different_registers(sub_klass, super_klass, temp_reg);
1490 if (temp2_reg != noreg)
1491 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1492 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1493
1494 Label L_fallthrough;
1495 int label_nulls = 0;
1496 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1497 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1498 assert(label_nulls <= 1, "at most one null in the batch");
1499
1500 // a couple of useful fields in sub_klass:
1501 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1502 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1503 Address secondary_supers_addr(sub_klass, ss_offset);
1504 Address super_cache_addr( sub_klass, sc_offset);
1505
1506 BLOCK_COMMENT("check_klass_subtype_slow_path");
1507
1508 // Do a linear scan of the secondary super-klass chain.
1509 // This code is rarely used, so simplicity is a virtue here.
1510 // The repne_scan instruction uses fixed registers, which we must spill.
1511 // Don't worry too much about pre-existing connections with the input regs.
1512
1513 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1514 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1515
1516 RegSet pushed_registers;
1517 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1518 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1519
1520 if (super_klass != r0) {
1521 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1522 }
1523
1524 push(pushed_registers, sp);
1525
1526 // Get super_klass value into r0 (even if it was in r5 or r2).
1527 if (super_klass != r0) {
1528 mov(r0, super_klass);
1529 }
1530
1531 #ifndef PRODUCT
1532 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1533 #endif //PRODUCT
1534
1535 // We will consult the secondary-super array.
1536 ldr(r5, secondary_supers_addr);
1537 // Load the array length.
1538 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1539 // Skip to start of data.
1540 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1541
1542 cmp(sp, zr); // Clear Z flag; SP is never zero
1543 // Scan R2 words at [R5] for an occurrence of R0.
1544 // Set NZ/Z based on last compare.
1545 repne_scan(r5, r0, r2, rscratch1);
1546
1547 // Unspill the temp. registers:
1548 pop(pushed_registers, sp);
1549
1550 br(Assembler::NE, *L_failure);
1551
1552 // Success. Cache the super we found and proceed in triumph.
1553
1554 if (UseSecondarySupersCache) {
1555 str(super_klass, super_cache_addr);
1556 }
1557
1558 if (L_success != &L_fallthrough) {
1559 b(*L_success);
1560 }
1561
1562 #undef IS_A_TEMP
1563
1564 bind(L_fallthrough);
1565 }
1566
1567 // If Register r is invalid, remove a new register from
1568 // available_regs, and add new register to regs_to_push.
1569 Register MacroAssembler::allocate_if_noreg(Register r,
1570 RegSetIterator<Register> &available_regs,
1571 RegSet ®s_to_push) {
1572 if (!r->is_valid()) {
1573 r = *available_regs++;
1574 regs_to_push += r;
1575 }
1576 return r;
1577 }
1578
1579 // check_klass_subtype_slow_path_table() looks for super_klass in the
1580 // hash table belonging to super_klass, branching to L_success or
1581 // L_failure as appropriate. This is essentially a shim which
1582 // allocates registers as necessary then calls
1583 // lookup_secondary_supers_table() to do the work. Any of the temp
1584 // regs may be noreg, in which case this logic will chooses some
1585 // registers push and pop them from the stack.
1586 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1587 Register super_klass,
1588 Register temp_reg,
1589 Register temp2_reg,
1590 Register temp3_reg,
1591 Register result_reg,
1592 FloatRegister vtemp,
1593 Label* L_success,
1594 Label* L_failure,
1595 bool set_cond_codes) {
1596 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1597
1598 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1599
1600 Label L_fallthrough;
1601 int label_nulls = 0;
1602 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1603 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1604 assert(label_nulls <= 1, "at most one null in the batch");
1605
1606 BLOCK_COMMENT("check_klass_subtype_slow_path");
1607
1608 RegSetIterator<Register> available_regs
1609 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1610
1611 RegSet pushed_regs;
1612
1613 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1614 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1615 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1616 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1617
1618 push(pushed_regs, sp);
1619
1620 lookup_secondary_supers_table_var(sub_klass,
1621 super_klass,
1622 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1623 nullptr);
1624 cmp(result_reg, zr);
1625
1626 // Unspill the temp. registers:
1627 pop(pushed_regs, sp);
1628
1629 // NB! Callers may assume that, when set_cond_codes is true, this
1630 // code sets temp2_reg to a nonzero value.
1631 if (set_cond_codes) {
1632 mov(temp2_reg, 1);
1633 }
1634
1635 br(Assembler::NE, *L_failure);
1636
1637 if (L_success != &L_fallthrough) {
1638 b(*L_success);
1639 }
1640
1641 bind(L_fallthrough);
1642 }
1643
1644 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1645 Register super_klass,
1646 Register temp_reg,
1647 Register temp2_reg,
1648 Label* L_success,
1649 Label* L_failure,
1650 bool set_cond_codes) {
1651 if (UseSecondarySupersTable) {
1652 check_klass_subtype_slow_path_table
1653 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1654 /*vtemp*/fnoreg,
1655 L_success, L_failure, set_cond_codes);
1656 } else {
1657 check_klass_subtype_slow_path_linear
1658 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1659 }
1660 }
1661
1662
1663 // Ensure that the inline code and the stub are using the same registers.
1664 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1665 do { \
1666 assert(r_super_klass == r0 && \
1667 r_array_base == r1 && \
1668 r_array_length == r2 && \
1669 (r_array_index == r3 || r_array_index == noreg) && \
1670 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1671 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1672 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1673 } while(0)
1674
1675 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1676 Register r_super_klass,
1677 Register temp1,
1678 Register temp2,
1679 Register temp3,
1680 FloatRegister vtemp,
1681 Register result,
1682 u1 super_klass_slot,
1683 bool stub_is_near) {
1684 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1685
1686 Label L_fallthrough;
1687
1688 BLOCK_COMMENT("lookup_secondary_supers_table {");
1689
1690 const Register
1691 r_array_base = temp1, // r1
1692 r_array_length = temp2, // r2
1693 r_array_index = temp3, // r3
1694 r_bitmap = rscratch2;
1695
1696 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1697
1698 u1 bit = super_klass_slot;
1699
1700 // Make sure that result is nonzero if the TBZ below misses.
1701 mov(result, 1);
1702
1703 // We're going to need the bitmap in a vector reg and in a core reg,
1704 // so load both now.
1705 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1706 if (bit != 0) {
1707 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1708 }
1709 // First check the bitmap to see if super_klass might be present. If
1710 // the bit is zero, we are certain that super_klass is not one of
1711 // the secondary supers.
1712 tbz(r_bitmap, bit, L_fallthrough);
1713
1714 // Get the first array index that can contain super_klass into r_array_index.
1715 if (bit != 0) {
1716 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1717 cnt(vtemp, T8B, vtemp);
1718 addv(vtemp, T8B, vtemp);
1719 fmovd(r_array_index, vtemp);
1720 } else {
1721 mov(r_array_index, (u1)1);
1722 }
1723 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1724
1725 // We will consult the secondary-super array.
1726 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1727
1728 // The value i in r_array_index is >= 1, so even though r_array_base
1729 // points to the length, we don't need to adjust it to point to the
1730 // data.
1731 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1732 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1733
1734 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1735 eor(result, result, r_super_klass);
1736 cbz(result, L_fallthrough); // Found a match
1737
1738 // Is there another entry to check? Consult the bitmap.
1739 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1740
1741 // Linear probe.
1742 if (bit != 0) {
1743 ror(r_bitmap, r_bitmap, bit);
1744 }
1745
1746 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1747 // The next slot to be inspected, by the stub we're about to call,
1748 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1749 // have been checked.
1750 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1751 if (stub_is_near) {
1752 bl(stub);
1753 } else {
1754 address call = trampoline_call(stub);
1755 if (call == nullptr) {
1756 return false; // trampoline allocation failed
1757 }
1758 }
1759
1760 BLOCK_COMMENT("} lookup_secondary_supers_table");
1761
1762 bind(L_fallthrough);
1763
1764 if (VerifySecondarySupers) {
1765 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1766 temp1, temp2, result); // r1, r2, r5
1767 }
1768 return true;
1769 }
1770
1771 // At runtime, return 0 in result if r_super_klass is a superclass of
1772 // r_sub_klass, otherwise return nonzero. Use this version of
1773 // lookup_secondary_supers_table() if you don't know ahead of time
1774 // which superclass will be searched for. Used by interpreter and
1775 // runtime stubs. It is larger and has somewhat greater latency than
1776 // the version above, which takes a constant super_klass_slot.
1777 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1778 Register r_super_klass,
1779 Register temp1,
1780 Register temp2,
1781 Register temp3,
1782 FloatRegister vtemp,
1783 Register result,
1784 Label *L_success) {
1785 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1786
1787 Label L_fallthrough;
1788
1789 BLOCK_COMMENT("lookup_secondary_supers_table {");
1790
1791 const Register
1792 r_array_index = temp3,
1793 slot = rscratch1,
1794 r_bitmap = rscratch2;
1795
1796 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1797
1798 // Make sure that result is nonzero if the test below misses.
1799 mov(result, 1);
1800
1801 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1802
1803 // First check the bitmap to see if super_klass might be present. If
1804 // the bit is zero, we are certain that super_klass is not one of
1805 // the secondary supers.
1806
1807 // This next instruction is equivalent to:
1808 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1809 // sub(temp2, tmp_reg, slot);
1810 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1811 lslv(temp2, r_bitmap, temp2);
1812 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1813
1814 bool must_save_v0 = (vtemp == fnoreg);
1815 if (must_save_v0) {
1816 // temp1 and result are free, so use them to preserve vtemp
1817 vtemp = v0;
1818 mov(temp1, vtemp, D, 0);
1819 mov(result, vtemp, D, 1);
1820 }
1821
1822 // Get the first array index that can contain super_klass into r_array_index.
1823 mov(vtemp, D, 0, temp2);
1824 cnt(vtemp, T8B, vtemp);
1825 addv(vtemp, T8B, vtemp);
1826 mov(r_array_index, vtemp, D, 0);
1827
1828 if (must_save_v0) {
1829 mov(vtemp, D, 0, temp1 );
1830 mov(vtemp, D, 1, result);
1831 }
1832
1833 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1834
1835 const Register
1836 r_array_base = temp1,
1837 r_array_length = temp2;
1838
1839 // The value i in r_array_index is >= 1, so even though r_array_base
1840 // points to the length, we don't need to adjust it to point to the
1841 // data.
1842 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1843 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1844
1845 // We will consult the secondary-super array.
1846 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1847
1848 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1849 eor(result, result, r_super_klass);
1850 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1851
1852 // Is there another entry to check? Consult the bitmap.
1853 rorv(r_bitmap, r_bitmap, slot);
1854 // rol(r_bitmap, r_bitmap, 1);
1855 tbz(r_bitmap, 1, L_fallthrough);
1856
1857 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1858 // The next slot to be inspected, by the logic we're about to call,
1859 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1860 // have been checked.
1861 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1862 r_bitmap, r_array_length, result, /*is_stub*/false);
1863
1864 BLOCK_COMMENT("} lookup_secondary_supers_table");
1865
1866 bind(L_fallthrough);
1867
1868 if (VerifySecondarySupers) {
1869 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1870 temp1, temp2, result); // r1, r2, r5
1871 }
1872
1873 if (L_success) {
1874 cbz(result, *L_success);
1875 }
1876 }
1877
1878 // Called by code generated by check_klass_subtype_slow_path
1879 // above. This is called when there is a collision in the hashed
1880 // lookup in the secondary supers array.
1881 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1882 Register r_array_base,
1883 Register r_array_index,
1884 Register r_bitmap,
1885 Register temp1,
1886 Register result,
1887 bool is_stub) {
1888 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1889
1890 const Register
1891 r_array_length = temp1,
1892 r_sub_klass = noreg; // unused
1893
1894 if (is_stub) {
1895 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1896 }
1897
1898 Label L_fallthrough, L_huge;
1899
1900 // Load the array length.
1901 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1902 // And adjust the array base to point to the data.
1903 // NB! Effectively increments current slot index by 1.
1904 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1905 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1906
1907 // The bitmap is full to bursting.
1908 // Implicit invariant: BITMAP_FULL implies (length > 0)
1909 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1910 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1911 br(GT, L_huge);
1912
1913 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1914 // current slot (at secondary_supers[r_array_index]) has not yet
1915 // been inspected, and r_array_index may be out of bounds if we
1916 // wrapped around the end of the array.
1917
1918 { // This is conventional linear probing, but instead of terminating
1919 // when a null entry is found in the table, we maintain a bitmap
1920 // in which a 0 indicates missing entries.
1921 // As long as the bitmap is not completely full,
1922 // array_length == popcount(bitmap). The array_length check above
1923 // guarantees there are 0s in the bitmap, so the loop eventually
1924 // terminates.
1925 Label L_loop;
1926 bind(L_loop);
1927
1928 // Check for wraparound.
1929 cmp(r_array_index, r_array_length);
1930 csel(r_array_index, zr, r_array_index, GE);
1931
1932 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1933 eor(result, rscratch1, r_super_klass);
1934 cbz(result, L_fallthrough);
1935
1936 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1937
1938 ror(r_bitmap, r_bitmap, 1);
1939 add(r_array_index, r_array_index, 1);
1940 b(L_loop);
1941 }
1942
1943 { // Degenerate case: more than 64 secondary supers.
1944 // FIXME: We could do something smarter here, maybe a vectorized
1945 // comparison or a binary search, but is that worth any added
1946 // complexity?
1947 bind(L_huge);
1948 cmp(sp, zr); // Clear Z flag; SP is never zero
1949 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1950 cset(result, NE); // result == 0 iff we got a match.
1951 }
1952
1953 bind(L_fallthrough);
1954 }
1955
1956 // Make sure that the hashed lookup and a linear scan agree.
1957 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1958 Register r_super_klass,
1959 Register temp1,
1960 Register temp2,
1961 Register result) {
1962 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1963
1964 const Register
1965 r_array_base = temp1,
1966 r_array_length = temp2,
1967 r_array_index = noreg, // unused
1968 r_bitmap = noreg; // unused
1969
1970 BLOCK_COMMENT("verify_secondary_supers_table {");
1971
1972 // We will consult the secondary-super array.
1973 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1974
1975 // Load the array length.
1976 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1977 // And adjust the array base to point to the data.
1978 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1979
1980 cmp(sp, zr); // Clear Z flag; SP is never zero
1981 // Scan R2 words at [R5] for an occurrence of R0.
1982 // Set NZ/Z based on last compare.
1983 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
1984 // rscratch1 == 0 iff we got a match.
1985 cset(rscratch1, NE);
1986
1987 Label passed;
1988 cmp(result, zr);
1989 cset(result, NE); // normalize result to 0/1 for comparison
1990
1991 cmp(rscratch1, result);
1992 br(EQ, passed);
1993 {
1994 mov(r0, r_super_klass); // r0 <- r0
1995 mov(r1, r_sub_klass); // r1 <- r4
1996 mov(r2, /*expected*/rscratch1); // r2 <- r8
1997 mov(r3, result); // r3 <- r5
1998 mov(r4, (address)("mismatch")); // r4 <- const
1999 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
2000 should_not_reach_here();
2001 }
2002 bind(passed);
2003
2004 BLOCK_COMMENT("} verify_secondary_supers_table");
2005 }
2006
2007 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2008 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2009 assert_different_registers(klass, rthread, scratch);
2010
2011 Label L_fallthrough, L_tmp;
2012 if (L_fast_path == nullptr) {
2013 L_fast_path = &L_fallthrough;
2014 } else if (L_slow_path == nullptr) {
2015 L_slow_path = &L_fallthrough;
2016 }
2017 // Fast path check: class is fully initialized
2018 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2019 ldarb(scratch, scratch);
2020 cmp(scratch, InstanceKlass::fully_initialized);
2021 br(Assembler::EQ, *L_fast_path);
2022
2023 // Fast path check: current thread is initializer thread
2024 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2025 cmp(rthread, scratch);
2026
2027 if (L_slow_path == &L_fallthrough) {
2028 br(Assembler::EQ, *L_fast_path);
2029 bind(*L_slow_path);
2030 } else if (L_fast_path == &L_fallthrough) {
2031 br(Assembler::NE, *L_slow_path);
2032 bind(*L_fast_path);
2033 } else {
2034 Unimplemented();
2035 }
2036 }
2037
2038 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2039 if (!VerifyOops) return;
2040
2041 // Pass register number to verify_oop_subroutine
2042 const char* b = nullptr;
2043 {
2044 ResourceMark rm;
2045 stringStream ss;
2046 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2047 b = code_string(ss.as_string());
2048 }
2049 BLOCK_COMMENT("verify_oop {");
2050
2051 strip_return_address(); // This might happen within a stack frame.
2052 protect_return_address();
2053 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2054 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2055
2056 mov(r0, reg);
2057 movptr(rscratch1, (uintptr_t)(address)b);
2058
2059 // call indirectly to solve generation ordering problem
2060 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2061 ldr(rscratch2, Address(rscratch2));
2062 blr(rscratch2);
2063
2064 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2065 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2066 authenticate_return_address();
2067
2068 BLOCK_COMMENT("} verify_oop");
2069 }
2070
2071 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2072 if (!VerifyOops) return;
2073
2074 const char* b = nullptr;
2075 {
2076 ResourceMark rm;
2077 stringStream ss;
2078 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2079 b = code_string(ss.as_string());
2080 }
2081 BLOCK_COMMENT("verify_oop_addr {");
2082
2083 strip_return_address(); // This might happen within a stack frame.
2084 protect_return_address();
2085 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2086 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2087
2088 // addr may contain sp so we will have to adjust it based on the
2089 // pushes that we just did.
2090 if (addr.uses(sp)) {
2091 lea(r0, addr);
2092 ldr(r0, Address(r0, 4 * wordSize));
2093 } else {
2094 ldr(r0, addr);
2095 }
2096 movptr(rscratch1, (uintptr_t)(address)b);
2097
2098 // call indirectly to solve generation ordering problem
2099 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2100 ldr(rscratch2, Address(rscratch2));
2101 blr(rscratch2);
2102
2103 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2104 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2105 authenticate_return_address();
2106
2107 BLOCK_COMMENT("} verify_oop_addr");
2108 }
2109
2110 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2111 int extra_slot_offset) {
2112 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2113 int stackElementSize = Interpreter::stackElementSize;
2114 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2115 #ifdef ASSERT
2116 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2117 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2118 #endif
2119 if (arg_slot.is_constant()) {
2120 return Address(esp, arg_slot.as_constant() * stackElementSize
2121 + offset);
2122 } else {
2123 add(rscratch1, esp, arg_slot.as_register(),
2124 ext::uxtx, exact_log2(stackElementSize));
2125 return Address(rscratch1, offset);
2126 }
2127 }
2128
2129 void MacroAssembler::call_VM_leaf_base(address entry_point,
2130 int number_of_arguments,
2131 Label *retaddr) {
2132 Label E, L;
2133
2134 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2135
2136 mov(rscratch1, RuntimeAddress(entry_point));
2137 blr(rscratch1);
2138 if (retaddr)
2139 bind(*retaddr);
2140
2141 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2142 }
2143
2144 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2145 call_VM_leaf_base(entry_point, number_of_arguments);
2146 }
2147
2148 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2149 pass_arg0(this, arg_0);
2150 call_VM_leaf_base(entry_point, 1);
2151 }
2152
2153 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2154 assert_different_registers(arg_1, c_rarg0);
2155 pass_arg0(this, arg_0);
2156 pass_arg1(this, arg_1);
2157 call_VM_leaf_base(entry_point, 2);
2158 }
2159
2160 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2161 Register arg_1, Register arg_2) {
2162 assert_different_registers(arg_1, c_rarg0);
2163 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2164 pass_arg0(this, arg_0);
2165 pass_arg1(this, arg_1);
2166 pass_arg2(this, arg_2);
2167 call_VM_leaf_base(entry_point, 3);
2168 }
2169
2170 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2171 pass_arg0(this, arg_0);
2172 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2173 }
2174
2175 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2176
2177 assert_different_registers(arg_0, c_rarg1);
2178 pass_arg1(this, arg_1);
2179 pass_arg0(this, arg_0);
2180 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2181 }
2182
2183 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2184 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2185 assert_different_registers(arg_1, c_rarg2);
2186 pass_arg2(this, arg_2);
2187 pass_arg1(this, arg_1);
2188 pass_arg0(this, arg_0);
2189 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2190 }
2191
2192 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2193 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2194 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2195 assert_different_registers(arg_2, c_rarg3);
2196 pass_arg3(this, arg_3);
2197 pass_arg2(this, arg_2);
2198 pass_arg1(this, arg_1);
2199 pass_arg0(this, arg_0);
2200 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2201 }
2202
2203 void MacroAssembler::null_check(Register reg, int offset) {
2204 if (needs_explicit_null_check(offset)) {
2205 // provoke OS null exception if reg is null by
2206 // accessing M[reg] w/o changing any registers
2207 // NOTE: this is plenty to provoke a segv
2208 ldr(zr, Address(reg));
2209 } else {
2210 // nothing to do, (later) access of M[reg + offset]
2211 // will provoke OS null exception if reg is null
2212 }
2213 }
2214
2215 // MacroAssembler protected routines needed to implement
2216 // public methods
2217
2218 void MacroAssembler::mov(Register r, Address dest) {
2219 code_section()->relocate(pc(), dest.rspec());
2220 uint64_t imm64 = (uint64_t)dest.target();
2221 movptr(r, imm64);
2222 }
2223
2224 // Move a constant pointer into r. In AArch64 mode the virtual
2225 // address space is 48 bits in size, so we only need three
2226 // instructions to create a patchable instruction sequence that can
2227 // reach anywhere.
2228 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2229 #ifndef PRODUCT
2230 {
2231 char buffer[64];
2232 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2233 block_comment(buffer);
2234 }
2235 #endif
2236 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2237 movz(r, imm64 & 0xffff);
2238 imm64 >>= 16;
2239 movk(r, imm64 & 0xffff, 16);
2240 imm64 >>= 16;
2241 movk(r, imm64 & 0xffff, 32);
2242 }
2243
2244 // Macro to mov replicated immediate to vector register.
2245 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2246 // the upper 56/48/32 bits must be zeros for B/H/S type.
2247 // Vd will get the following values for different arrangements in T
2248 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2249 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2250 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2251 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2252 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2253 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2254 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2255 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2256 // Clobbers rscratch1
2257 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2258 assert(T != T1Q, "unsupported");
2259 if (T == T1D || T == T2D) {
2260 int imm = operand_valid_for_movi_immediate(imm64, T);
2261 if (-1 != imm) {
2262 movi(Vd, T, imm);
2263 } else {
2264 mov(rscratch1, imm64);
2265 dup(Vd, T, rscratch1);
2266 }
2267 return;
2268 }
2269
2270 #ifdef ASSERT
2271 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2272 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2273 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2274 #endif
2275 int shift = operand_valid_for_movi_immediate(imm64, T);
2276 uint32_t imm32 = imm64 & 0xffffffffULL;
2277 if (shift >= 0) {
2278 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2279 } else {
2280 movw(rscratch1, imm32);
2281 dup(Vd, T, rscratch1);
2282 }
2283 }
2284
2285 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2286 {
2287 #ifndef PRODUCT
2288 {
2289 char buffer[64];
2290 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2291 block_comment(buffer);
2292 }
2293 #endif
2294 if (operand_valid_for_logical_immediate(false, imm64)) {
2295 orr(dst, zr, imm64);
2296 } else {
2297 // we can use a combination of MOVZ or MOVN with
2298 // MOVK to build up the constant
2299 uint64_t imm_h[4];
2300 int zero_count = 0;
2301 int neg_count = 0;
2302 int i;
2303 for (i = 0; i < 4; i++) {
2304 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2305 if (imm_h[i] == 0) {
2306 zero_count++;
2307 } else if (imm_h[i] == 0xffffL) {
2308 neg_count++;
2309 }
2310 }
2311 if (zero_count == 4) {
2312 // one MOVZ will do
2313 movz(dst, 0);
2314 } else if (neg_count == 4) {
2315 // one MOVN will do
2316 movn(dst, 0);
2317 } else if (zero_count == 3) {
2318 for (i = 0; i < 4; i++) {
2319 if (imm_h[i] != 0L) {
2320 movz(dst, (uint32_t)imm_h[i], (i << 4));
2321 break;
2322 }
2323 }
2324 } else if (neg_count == 3) {
2325 // one MOVN will do
2326 for (int i = 0; i < 4; i++) {
2327 if (imm_h[i] != 0xffffL) {
2328 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2329 break;
2330 }
2331 }
2332 } else if (zero_count == 2) {
2333 // one MOVZ and one MOVK will do
2334 for (i = 0; i < 3; i++) {
2335 if (imm_h[i] != 0L) {
2336 movz(dst, (uint32_t)imm_h[i], (i << 4));
2337 i++;
2338 break;
2339 }
2340 }
2341 for (;i < 4; i++) {
2342 if (imm_h[i] != 0L) {
2343 movk(dst, (uint32_t)imm_h[i], (i << 4));
2344 }
2345 }
2346 } else if (neg_count == 2) {
2347 // one MOVN and one MOVK will do
2348 for (i = 0; i < 4; i++) {
2349 if (imm_h[i] != 0xffffL) {
2350 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2351 i++;
2352 break;
2353 }
2354 }
2355 for (;i < 4; i++) {
2356 if (imm_h[i] != 0xffffL) {
2357 movk(dst, (uint32_t)imm_h[i], (i << 4));
2358 }
2359 }
2360 } else if (zero_count == 1) {
2361 // one MOVZ and two MOVKs will do
2362 for (i = 0; i < 4; i++) {
2363 if (imm_h[i] != 0L) {
2364 movz(dst, (uint32_t)imm_h[i], (i << 4));
2365 i++;
2366 break;
2367 }
2368 }
2369 for (;i < 4; i++) {
2370 if (imm_h[i] != 0x0L) {
2371 movk(dst, (uint32_t)imm_h[i], (i << 4));
2372 }
2373 }
2374 } else if (neg_count == 1) {
2375 // one MOVN and two MOVKs will do
2376 for (i = 0; i < 4; i++) {
2377 if (imm_h[i] != 0xffffL) {
2378 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2379 i++;
2380 break;
2381 }
2382 }
2383 for (;i < 4; i++) {
2384 if (imm_h[i] != 0xffffL) {
2385 movk(dst, (uint32_t)imm_h[i], (i << 4));
2386 }
2387 }
2388 } else {
2389 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2390 movz(dst, (uint32_t)imm_h[0], 0);
2391 for (i = 1; i < 4; i++) {
2392 movk(dst, (uint32_t)imm_h[i], (i << 4));
2393 }
2394 }
2395 }
2396 }
2397
2398 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2399 {
2400 #ifndef PRODUCT
2401 {
2402 char buffer[64];
2403 os::snprintf_checked(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2404 block_comment(buffer);
2405 }
2406 #endif
2407 if (operand_valid_for_logical_immediate(true, imm32)) {
2408 orrw(dst, zr, imm32);
2409 } else {
2410 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2411 // constant
2412 uint32_t imm_h[2];
2413 imm_h[0] = imm32 & 0xffff;
2414 imm_h[1] = ((imm32 >> 16) & 0xffff);
2415 if (imm_h[0] == 0) {
2416 movzw(dst, imm_h[1], 16);
2417 } else if (imm_h[0] == 0xffff) {
2418 movnw(dst, imm_h[1] ^ 0xffff, 16);
2419 } else if (imm_h[1] == 0) {
2420 movzw(dst, imm_h[0], 0);
2421 } else if (imm_h[1] == 0xffff) {
2422 movnw(dst, imm_h[0] ^ 0xffff, 0);
2423 } else {
2424 // use a MOVZ and MOVK (makes it easier to debug)
2425 movzw(dst, imm_h[0], 0);
2426 movkw(dst, imm_h[1], 16);
2427 }
2428 }
2429 }
2430
2431 // Form an address from base + offset in Rd. Rd may or may
2432 // not actually be used: you must use the Address that is returned.
2433 // It is up to you to ensure that the shift provided matches the size
2434 // of your data.
2435 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2436 if (Address::offset_ok_for_immed(byte_offset, shift))
2437 // It fits; no need for any heroics
2438 return Address(base, byte_offset);
2439
2440 // Don't do anything clever with negative or misaligned offsets
2441 unsigned mask = (1 << shift) - 1;
2442 if (byte_offset < 0 || byte_offset & mask) {
2443 mov(Rd, byte_offset);
2444 add(Rd, base, Rd);
2445 return Address(Rd);
2446 }
2447
2448 // See if we can do this with two 12-bit offsets
2449 {
2450 uint64_t word_offset = byte_offset >> shift;
2451 uint64_t masked_offset = word_offset & 0xfff000;
2452 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2453 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2454 add(Rd, base, masked_offset << shift);
2455 word_offset -= masked_offset;
2456 return Address(Rd, word_offset << shift);
2457 }
2458 }
2459
2460 // Do it the hard way
2461 mov(Rd, byte_offset);
2462 add(Rd, base, Rd);
2463 return Address(Rd);
2464 }
2465
2466 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2467 bool want_remainder, Register scratch)
2468 {
2469 // Full implementation of Java idiv and irem. The function
2470 // returns the (pc) offset of the div instruction - may be needed
2471 // for implicit exceptions.
2472 //
2473 // constraint : ra/rb =/= scratch
2474 // normal case
2475 //
2476 // input : ra: dividend
2477 // rb: divisor
2478 //
2479 // result: either
2480 // quotient (= ra idiv rb)
2481 // remainder (= ra irem rb)
2482
2483 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2484
2485 int idivl_offset = offset();
2486 if (! want_remainder) {
2487 sdivw(result, ra, rb);
2488 } else {
2489 sdivw(scratch, ra, rb);
2490 Assembler::msubw(result, scratch, rb, ra);
2491 }
2492
2493 return idivl_offset;
2494 }
2495
2496 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2497 bool want_remainder, Register scratch)
2498 {
2499 // Full implementation of Java ldiv and lrem. The function
2500 // returns the (pc) offset of the div instruction - may be needed
2501 // for implicit exceptions.
2502 //
2503 // constraint : ra/rb =/= scratch
2504 // normal case
2505 //
2506 // input : ra: dividend
2507 // rb: divisor
2508 //
2509 // result: either
2510 // quotient (= ra idiv rb)
2511 // remainder (= ra irem rb)
2512
2513 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2514
2515 int idivq_offset = offset();
2516 if (! want_remainder) {
2517 sdiv(result, ra, rb);
2518 } else {
2519 sdiv(scratch, ra, rb);
2520 Assembler::msub(result, scratch, rb, ra);
2521 }
2522
2523 return idivq_offset;
2524 }
2525
2526 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2527 address prev = pc() - NativeMembar::instruction_size;
2528 address last = code()->last_insn();
2529 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2530 NativeMembar *bar = NativeMembar_at(prev);
2531 if (AlwaysMergeDMB) {
2532 bar->set_kind(bar->get_kind() | order_constraint);
2533 BLOCK_COMMENT("merged membar(always)");
2534 return;
2535 }
2536 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2537 // doing so would introduce a StoreLoad which the caller did not
2538 // intend
2539 if (bar->get_kind() == order_constraint
2540 || bar->get_kind() == AnyAny
2541 || order_constraint == AnyAny) {
2542 // We are merging two memory barrier instructions. On AArch64 we
2543 // can do this simply by ORing them together.
2544 bar->set_kind(bar->get_kind() | order_constraint);
2545 BLOCK_COMMENT("merged membar");
2546 return;
2547 } else {
2548 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2549 // We need check the last 2 instructions
2550 address prev2 = prev - NativeMembar::instruction_size;
2551 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2552 NativeMembar *bar2 = NativeMembar_at(prev2);
2553 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2554 BLOCK_COMMENT("merged membar(elided)");
2555 return;
2556 }
2557 }
2558 }
2559 code()->set_last_insn(pc());
2560 dmb(Assembler::barrier(order_constraint));
2561 }
2562
2563 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2564 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2565 merge_ldst(rt, adr, size_in_bytes, is_store);
2566 code()->clear_last_insn();
2567 return true;
2568 } else {
2569 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2570 const uint64_t mask = size_in_bytes - 1;
2571 if (adr.getMode() == Address::base_plus_offset &&
2572 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2573 code()->set_last_insn(pc());
2574 }
2575 return false;
2576 }
2577 }
2578
2579 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2580 // We always try to merge two adjacent loads into one ldp.
2581 if (!try_merge_ldst(Rx, adr, 8, false)) {
2582 Assembler::ldr(Rx, adr);
2583 }
2584 }
2585
2586 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2587 // We always try to merge two adjacent loads into one ldp.
2588 if (!try_merge_ldst(Rw, adr, 4, false)) {
2589 Assembler::ldrw(Rw, adr);
2590 }
2591 }
2592
2593 void MacroAssembler::str(Register Rx, const Address &adr) {
2594 // We always try to merge two adjacent stores into one stp.
2595 if (!try_merge_ldst(Rx, adr, 8, true)) {
2596 Assembler::str(Rx, adr);
2597 }
2598 }
2599
2600 void MacroAssembler::strw(Register Rw, const Address &adr) {
2601 // We always try to merge two adjacent stores into one stp.
2602 if (!try_merge_ldst(Rw, adr, 4, true)) {
2603 Assembler::strw(Rw, adr);
2604 }
2605 }
2606
2607 // MacroAssembler routines found actually to be needed
2608
2609 void MacroAssembler::push(Register src)
2610 {
2611 str(src, Address(pre(esp, -1 * wordSize)));
2612 }
2613
2614 void MacroAssembler::pop(Register dst)
2615 {
2616 ldr(dst, Address(post(esp, 1 * wordSize)));
2617 }
2618
2619 // Note: load_unsigned_short used to be called load_unsigned_word.
2620 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2621 int off = offset();
2622 ldrh(dst, src);
2623 return off;
2624 }
2625
2626 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2627 int off = offset();
2628 ldrb(dst, src);
2629 return off;
2630 }
2631
2632 int MacroAssembler::load_signed_short(Register dst, Address src) {
2633 int off = offset();
2634 ldrsh(dst, src);
2635 return off;
2636 }
2637
2638 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2639 int off = offset();
2640 ldrsb(dst, src);
2641 return off;
2642 }
2643
2644 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2645 int off = offset();
2646 ldrshw(dst, src);
2647 return off;
2648 }
2649
2650 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2651 int off = offset();
2652 ldrsbw(dst, src);
2653 return off;
2654 }
2655
2656 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2657 switch (size_in_bytes) {
2658 case 8: ldr(dst, src); break;
2659 case 4: ldrw(dst, src); break;
2660 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2661 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2662 default: ShouldNotReachHere();
2663 }
2664 }
2665
2666 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2667 switch (size_in_bytes) {
2668 case 8: str(src, dst); break;
2669 case 4: strw(src, dst); break;
2670 case 2: strh(src, dst); break;
2671 case 1: strb(src, dst); break;
2672 default: ShouldNotReachHere();
2673 }
2674 }
2675
2676 void MacroAssembler::decrementw(Register reg, int value)
2677 {
2678 if (value < 0) { incrementw(reg, -value); return; }
2679 if (value == 0) { return; }
2680 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2681 /* else */ {
2682 guarantee(reg != rscratch2, "invalid dst for register decrement");
2683 movw(rscratch2, (unsigned)value);
2684 subw(reg, reg, rscratch2);
2685 }
2686 }
2687
2688 void MacroAssembler::decrement(Register reg, int value)
2689 {
2690 if (value < 0) { increment(reg, -value); return; }
2691 if (value == 0) { return; }
2692 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2693 /* else */ {
2694 assert(reg != rscratch2, "invalid dst for register decrement");
2695 mov(rscratch2, (uint64_t)value);
2696 sub(reg, reg, rscratch2);
2697 }
2698 }
2699
2700 void MacroAssembler::decrementw(Address dst, int value)
2701 {
2702 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2703 if (dst.getMode() == Address::literal) {
2704 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2705 lea(rscratch2, dst);
2706 dst = Address(rscratch2);
2707 }
2708 ldrw(rscratch1, dst);
2709 decrementw(rscratch1, value);
2710 strw(rscratch1, dst);
2711 }
2712
2713 void MacroAssembler::decrement(Address dst, int value)
2714 {
2715 assert(!dst.uses(rscratch1), "invalid address for decrement");
2716 if (dst.getMode() == Address::literal) {
2717 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2718 lea(rscratch2, dst);
2719 dst = Address(rscratch2);
2720 }
2721 ldr(rscratch1, dst);
2722 decrement(rscratch1, value);
2723 str(rscratch1, dst);
2724 }
2725
2726 void MacroAssembler::incrementw(Register reg, int value)
2727 {
2728 if (value < 0) { decrementw(reg, -value); return; }
2729 if (value == 0) { return; }
2730 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2731 /* else */ {
2732 assert(reg != rscratch2, "invalid dst for register increment");
2733 movw(rscratch2, (unsigned)value);
2734 addw(reg, reg, rscratch2);
2735 }
2736 }
2737
2738 void MacroAssembler::increment(Register reg, int value)
2739 {
2740 if (value < 0) { decrement(reg, -value); return; }
2741 if (value == 0) { return; }
2742 if (value < (1 << 12)) { add(reg, reg, value); return; }
2743 /* else */ {
2744 assert(reg != rscratch2, "invalid dst for register increment");
2745 movw(rscratch2, (unsigned)value);
2746 add(reg, reg, rscratch2);
2747 }
2748 }
2749
2750 void MacroAssembler::incrementw(Address dst, int value)
2751 {
2752 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2753 if (dst.getMode() == Address::literal) {
2754 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2755 lea(rscratch2, dst);
2756 dst = Address(rscratch2);
2757 }
2758 ldrw(rscratch1, dst);
2759 incrementw(rscratch1, value);
2760 strw(rscratch1, dst);
2761 }
2762
2763 void MacroAssembler::increment(Address dst, int value)
2764 {
2765 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2766 if (dst.getMode() == Address::literal) {
2767 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2768 lea(rscratch2, dst);
2769 dst = Address(rscratch2);
2770 }
2771 ldr(rscratch1, dst);
2772 increment(rscratch1, value);
2773 str(rscratch1, dst);
2774 }
2775
2776 // Push lots of registers in the bit set supplied. Don't push sp.
2777 // Return the number of words pushed
2778 int MacroAssembler::push(unsigned int bitset, Register stack) {
2779 int words_pushed = 0;
2780
2781 // Scan bitset to accumulate register pairs
2782 unsigned char regs[32];
2783 int count = 0;
2784 for (int reg = 0; reg <= 30; reg++) {
2785 if (1 & bitset)
2786 regs[count++] = reg;
2787 bitset >>= 1;
2788 }
2789 regs[count++] = zr->raw_encoding();
2790 count &= ~1; // Only push an even number of regs
2791
2792 if (count) {
2793 stp(as_Register(regs[0]), as_Register(regs[1]),
2794 Address(pre(stack, -count * wordSize)));
2795 words_pushed += 2;
2796 }
2797 for (int i = 2; i < count; i += 2) {
2798 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2799 Address(stack, i * wordSize));
2800 words_pushed += 2;
2801 }
2802
2803 assert(words_pushed == count, "oops, pushed != count");
2804
2805 return count;
2806 }
2807
2808 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2809 int words_pushed = 0;
2810
2811 // Scan bitset to accumulate register pairs
2812 unsigned char regs[32];
2813 int count = 0;
2814 for (int reg = 0; reg <= 30; reg++) {
2815 if (1 & bitset)
2816 regs[count++] = reg;
2817 bitset >>= 1;
2818 }
2819 regs[count++] = zr->raw_encoding();
2820 count &= ~1;
2821
2822 for (int i = 2; i < count; i += 2) {
2823 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2824 Address(stack, i * wordSize));
2825 words_pushed += 2;
2826 }
2827 if (count) {
2828 ldp(as_Register(regs[0]), as_Register(regs[1]),
2829 Address(post(stack, count * wordSize)));
2830 words_pushed += 2;
2831 }
2832
2833 assert(words_pushed == count, "oops, pushed != count");
2834
2835 return count;
2836 }
2837
2838 // Push lots of registers in the bit set supplied. Don't push sp.
2839 // Return the number of dwords pushed
2840 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2841 int words_pushed = 0;
2842 bool use_sve = false;
2843 int sve_vector_size_in_bytes = 0;
2844
2845 #ifdef COMPILER2
2846 use_sve = Matcher::supports_scalable_vector();
2847 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2848 #endif
2849
2850 // Scan bitset to accumulate register pairs
2851 unsigned char regs[32];
2852 int count = 0;
2853 for (int reg = 0; reg <= 31; reg++) {
2854 if (1 & bitset)
2855 regs[count++] = reg;
2856 bitset >>= 1;
2857 }
2858
2859 if (count == 0) {
2860 return 0;
2861 }
2862
2863 if (mode == PushPopFull) {
2864 if (use_sve && sve_vector_size_in_bytes > 16) {
2865 mode = PushPopSVE;
2866 } else {
2867 mode = PushPopNeon;
2868 }
2869 }
2870
2871 #ifndef PRODUCT
2872 {
2873 char buffer[48];
2874 if (mode == PushPopSVE) {
2875 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
2876 } else if (mode == PushPopNeon) {
2877 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
2878 } else {
2879 os::snprintf_checked(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
2880 }
2881 block_comment(buffer);
2882 }
2883 #endif
2884
2885 if (mode == PushPopSVE) {
2886 sub(stack, stack, sve_vector_size_in_bytes * count);
2887 for (int i = 0; i < count; i++) {
2888 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2889 }
2890 return count * sve_vector_size_in_bytes / 8;
2891 }
2892
2893 if (mode == PushPopNeon) {
2894 if (count == 1) {
2895 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2896 return 2;
2897 }
2898
2899 bool odd = (count & 1) == 1;
2900 int push_slots = count + (odd ? 1 : 0);
2901
2902 // Always pushing full 128 bit registers.
2903 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
2904 words_pushed += 2;
2905
2906 for (int i = 2; i + 1 < count; i += 2) {
2907 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2908 words_pushed += 2;
2909 }
2910
2911 if (odd) {
2912 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2913 words_pushed++;
2914 }
2915
2916 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2917 return count * 2;
2918 }
2919
2920 if (mode == PushPopFp) {
2921 bool odd = (count & 1) == 1;
2922 int push_slots = count + (odd ? 1 : 0);
2923
2924 if (count == 1) {
2925 // Stack pointer must be 16 bytes aligned
2926 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
2927 return 1;
2928 }
2929
2930 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
2931 words_pushed += 2;
2932
2933 for (int i = 2; i + 1 < count; i += 2) {
2934 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
2935 words_pushed += 2;
2936 }
2937
2938 if (odd) {
2939 // Stack pointer must be 16 bytes aligned
2940 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
2941 words_pushed++;
2942 }
2943
2944 assert(words_pushed == count, "oops, pushed != count");
2945
2946 return count;
2947 }
2948
2949 return 0;
2950 }
2951
2952 // Return the number of dwords popped
2953 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2954 int words_pushed = 0;
2955 bool use_sve = false;
2956 int sve_vector_size_in_bytes = 0;
2957
2958 #ifdef COMPILER2
2959 use_sve = Matcher::supports_scalable_vector();
2960 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2961 #endif
2962 // Scan bitset to accumulate register pairs
2963 unsigned char regs[32];
2964 int count = 0;
2965 for (int reg = 0; reg <= 31; reg++) {
2966 if (1 & bitset)
2967 regs[count++] = reg;
2968 bitset >>= 1;
2969 }
2970
2971 if (count == 0) {
2972 return 0;
2973 }
2974
2975 if (mode == PushPopFull) {
2976 if (use_sve && sve_vector_size_in_bytes > 16) {
2977 mode = PushPopSVE;
2978 } else {
2979 mode = PushPopNeon;
2980 }
2981 }
2982
2983 #ifndef PRODUCT
2984 {
2985 char buffer[48];
2986 if (mode == PushPopSVE) {
2987 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
2988 } else if (mode == PushPopNeon) {
2989 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
2990 } else {
2991 os::snprintf_checked(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
2992 }
2993 block_comment(buffer);
2994 }
2995 #endif
2996
2997 if (mode == PushPopSVE) {
2998 for (int i = count - 1; i >= 0; i--) {
2999 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3000 }
3001 add(stack, stack, sve_vector_size_in_bytes * count);
3002 return count * sve_vector_size_in_bytes / 8;
3003 }
3004
3005 if (mode == PushPopNeon) {
3006 if (count == 1) {
3007 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3008 return 2;
3009 }
3010
3011 bool odd = (count & 1) == 1;
3012 int push_slots = count + (odd ? 1 : 0);
3013
3014 if (odd) {
3015 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3016 words_pushed++;
3017 }
3018
3019 for (int i = 2; i + 1 < count; i += 2) {
3020 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3021 words_pushed += 2;
3022 }
3023
3024 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3025 words_pushed += 2;
3026
3027 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3028
3029 return count * 2;
3030 }
3031
3032 if (mode == PushPopFp) {
3033 bool odd = (count & 1) == 1;
3034 int push_slots = count + (odd ? 1 : 0);
3035
3036 if (count == 1) {
3037 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3038 return 1;
3039 }
3040
3041 if (odd) {
3042 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3043 words_pushed++;
3044 }
3045
3046 for (int i = 2; i + 1 < count; i += 2) {
3047 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3048 words_pushed += 2;
3049 }
3050
3051 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3052 words_pushed += 2;
3053
3054 assert(words_pushed == count, "oops, pushed != count");
3055
3056 return count;
3057 }
3058
3059 return 0;
3060 }
3061
3062 // Return the number of dwords pushed
3063 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3064 bool use_sve = false;
3065 int sve_predicate_size_in_slots = 0;
3066
3067 #ifdef COMPILER2
3068 use_sve = Matcher::supports_scalable_vector();
3069 if (use_sve) {
3070 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3071 }
3072 #endif
3073
3074 if (!use_sve) {
3075 return 0;
3076 }
3077
3078 unsigned char regs[PRegister::number_of_registers];
3079 int count = 0;
3080 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3081 if (1 & bitset)
3082 regs[count++] = reg;
3083 bitset >>= 1;
3084 }
3085
3086 if (count == 0) {
3087 return 0;
3088 }
3089
3090 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3091 VMRegImpl::stack_slot_size * count, 16);
3092 sub(stack, stack, total_push_bytes);
3093 for (int i = 0; i < count; i++) {
3094 sve_str(as_PRegister(regs[i]), Address(stack, i));
3095 }
3096 return total_push_bytes / 8;
3097 }
3098
3099 // Return the number of dwords popped
3100 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3101 bool use_sve = false;
3102 int sve_predicate_size_in_slots = 0;
3103
3104 #ifdef COMPILER2
3105 use_sve = Matcher::supports_scalable_vector();
3106 if (use_sve) {
3107 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3108 }
3109 #endif
3110
3111 if (!use_sve) {
3112 return 0;
3113 }
3114
3115 unsigned char regs[PRegister::number_of_registers];
3116 int count = 0;
3117 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3118 if (1 & bitset)
3119 regs[count++] = reg;
3120 bitset >>= 1;
3121 }
3122
3123 if (count == 0) {
3124 return 0;
3125 }
3126
3127 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3128 VMRegImpl::stack_slot_size * count, 16);
3129 for (int i = count - 1; i >= 0; i--) {
3130 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3131 }
3132 add(stack, stack, total_pop_bytes);
3133 return total_pop_bytes / 8;
3134 }
3135
3136 #ifdef ASSERT
3137 void MacroAssembler::verify_heapbase(const char* msg) {
3138 #if 0
3139 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3140 assert (Universe::heap() != nullptr, "java heap should be initialized");
3141 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3142 // rheapbase is allocated as general register
3143 return;
3144 }
3145 if (CheckCompressedOops) {
3146 Label ok;
3147 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3148 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3149 br(Assembler::EQ, ok);
3150 stop(msg);
3151 bind(ok);
3152 pop(1 << rscratch1->encoding(), sp);
3153 }
3154 #endif
3155 }
3156 #endif
3157
3158 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3159 assert_different_registers(value, tmp1, tmp2);
3160 Label done, tagged, weak_tagged;
3161
3162 cbz(value, done); // Use null as-is.
3163 tst(value, JNIHandles::tag_mask); // Test for tag.
3164 br(Assembler::NE, tagged);
3165
3166 // Resolve local handle
3167 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3168 verify_oop(value);
3169 b(done);
3170
3171 bind(tagged);
3172 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3173 tbnz(value, 0, weak_tagged); // Test for weak tag.
3174
3175 // Resolve global handle
3176 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3177 verify_oop(value);
3178 b(done);
3179
3180 bind(weak_tagged);
3181 // Resolve jweak.
3182 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3183 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3184 verify_oop(value);
3185
3186 bind(done);
3187 }
3188
3189 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3190 assert_different_registers(value, tmp1, tmp2);
3191 Label done;
3192
3193 cbz(value, done); // Use null as-is.
3194
3195 #ifdef ASSERT
3196 {
3197 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3198 Label valid_global_tag;
3199 tbnz(value, 1, valid_global_tag); // Test for global tag
3200 stop("non global jobject using resolve_global_jobject");
3201 bind(valid_global_tag);
3202 }
3203 #endif
3204
3205 // Resolve global handle
3206 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3207 verify_oop(value);
3208
3209 bind(done);
3210 }
3211
3212 void MacroAssembler::stop(const char* msg) {
3213 // Skip AOT caching C strings in scratch buffer.
3214 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3215 BLOCK_COMMENT(str);
3216 // load msg into r0 so we can access it from the signal handler
3217 // ExternalAddress enables saving and restoring via the code cache
3218 lea(c_rarg0, ExternalAddress((address) str));
3219 dcps1(0xdeae);
3220 }
3221
3222 void MacroAssembler::unimplemented(const char* what) {
3223 const char* buf = nullptr;
3224 {
3225 ResourceMark rm;
3226 stringStream ss;
3227 ss.print("unimplemented: %s", what);
3228 buf = code_string(ss.as_string());
3229 }
3230 stop(buf);
3231 }
3232
3233 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3234 #ifdef ASSERT
3235 Label OK;
3236 br(cc, OK);
3237 stop(msg);
3238 bind(OK);
3239 #endif
3240 }
3241
3242 // If a constant does not fit in an immediate field, generate some
3243 // number of MOV instructions and then perform the operation.
3244 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3245 add_sub_imm_insn insn1,
3246 add_sub_reg_insn insn2,
3247 bool is32) {
3248 assert(Rd != zr, "Rd = zr and not setting flags?");
3249 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3250 if (fits) {
3251 (this->*insn1)(Rd, Rn, imm);
3252 } else {
3253 if (g_uabs(imm) < (1 << 24)) {
3254 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3255 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3256 } else {
3257 assert_different_registers(Rd, Rn);
3258 mov(Rd, imm);
3259 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3260 }
3261 }
3262 }
3263
3264 // Separate vsn which sets the flags. Optimisations are more restricted
3265 // because we must set the flags correctly.
3266 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3267 add_sub_imm_insn insn1,
3268 add_sub_reg_insn insn2,
3269 bool is32) {
3270 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3271 if (fits) {
3272 (this->*insn1)(Rd, Rn, imm);
3273 } else {
3274 assert_different_registers(Rd, Rn);
3275 assert(Rd != zr, "overflow in immediate operand");
3276 mov(Rd, imm);
3277 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3278 }
3279 }
3280
3281
3282 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3283 if (increment.is_register()) {
3284 add(Rd, Rn, increment.as_register());
3285 } else {
3286 add(Rd, Rn, increment.as_constant());
3287 }
3288 }
3289
3290 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3291 if (increment.is_register()) {
3292 addw(Rd, Rn, increment.as_register());
3293 } else {
3294 addw(Rd, Rn, increment.as_constant());
3295 }
3296 }
3297
3298 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3299 if (decrement.is_register()) {
3300 sub(Rd, Rn, decrement.as_register());
3301 } else {
3302 sub(Rd, Rn, decrement.as_constant());
3303 }
3304 }
3305
3306 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3307 if (decrement.is_register()) {
3308 subw(Rd, Rn, decrement.as_register());
3309 } else {
3310 subw(Rd, Rn, decrement.as_constant());
3311 }
3312 }
3313
3314 void MacroAssembler::reinit_heapbase()
3315 {
3316 if (UseCompressedOops) {
3317 if (Universe::is_fully_initialized()) {
3318 mov(rheapbase, CompressedOops::base());
3319 } else {
3320 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3321 ldr(rheapbase, Address(rheapbase));
3322 }
3323 }
3324 }
3325
3326 // this simulates the behaviour of the x86 cmpxchg instruction using a
3327 // load linked/store conditional pair. we use the acquire/release
3328 // versions of these instructions so that we flush pending writes as
3329 // per Java semantics.
3330
3331 // n.b the x86 version assumes the old value to be compared against is
3332 // in rax and updates rax with the value located in memory if the
3333 // cmpxchg fails. we supply a register for the old value explicitly
3334
3335 // the aarch64 load linked/store conditional instructions do not
3336 // accept an offset. so, unlike x86, we must provide a plain register
3337 // to identify the memory word to be compared/exchanged rather than a
3338 // register+offset Address.
3339
3340 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
3341 Label &succeed, Label *fail) {
3342 // oldv holds comparison value
3343 // newv holds value to write in exchange
3344 // addr identifies memory word to compare against/update
3345 if (UseLSE) {
3346 mov(tmp, oldv);
3347 casal(Assembler::xword, oldv, newv, addr);
3348 cmp(tmp, oldv);
3349 br(Assembler::EQ, succeed);
3350 membar(AnyAny);
3351 } else {
3352 Label retry_load, nope;
3353 prfm(Address(addr), PSTL1STRM);
3354 bind(retry_load);
3355 // flush and load exclusive from the memory location
3356 // and fail if it is not what we expect
3357 ldaxr(tmp, addr);
3358 cmp(tmp, oldv);
3359 br(Assembler::NE, nope);
3360 // if we store+flush with no intervening write tmp will be zero
3361 stlxr(tmp, newv, addr);
3362 cbzw(tmp, succeed);
3363 // retry so we only ever return after a load fails to compare
3364 // ensures we don't return a stale value after a failed write.
3365 b(retry_load);
3366 // if the memory word differs we return it in oldv and signal a fail
3367 bind(nope);
3368 membar(AnyAny);
3369 mov(oldv, tmp);
3370 }
3371 if (fail)
3372 b(*fail);
3373 }
3374
3375 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
3376 Label &succeed, Label *fail) {
3377 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
3378 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
3379 }
3380
3381 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
3382 Label &succeed, Label *fail) {
3383 // oldv holds comparison value
3384 // newv holds value to write in exchange
3385 // addr identifies memory word to compare against/update
3386 // tmp returns 0/1 for success/failure
3387 if (UseLSE) {
3388 mov(tmp, oldv);
3389 casal(Assembler::word, oldv, newv, addr);
3390 cmp(tmp, oldv);
3391 br(Assembler::EQ, succeed);
3392 membar(AnyAny);
3393 } else {
3394 Label retry_load, nope;
3395 prfm(Address(addr), PSTL1STRM);
3396 bind(retry_load);
3397 // flush and load exclusive from the memory location
3398 // and fail if it is not what we expect
3399 ldaxrw(tmp, addr);
3400 cmp(tmp, oldv);
3401 br(Assembler::NE, nope);
3402 // if we store+flush with no intervening write tmp will be zero
3403 stlxrw(tmp, newv, addr);
3404 cbzw(tmp, succeed);
3405 // retry so we only ever return after a load fails to compare
3406 // ensures we don't return a stale value after a failed write.
3407 b(retry_load);
3408 // if the memory word differs we return it in oldv and signal a fail
3409 bind(nope);
3410 membar(AnyAny);
3411 mov(oldv, tmp);
3412 }
3413 if (fail)
3414 b(*fail);
3415 }
3416
3417 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3418 // doesn't retry and may fail spuriously. If the oldval is wanted,
3419 // Pass a register for the result, otherwise pass noreg.
3420
3421 // Clobbers rscratch1
3422 void MacroAssembler::cmpxchg(Register addr, Register expected,
3423 Register new_val,
3424 enum operand_size size,
3425 bool acquire, bool release,
3426 bool weak,
3427 Register result) {
3428 if (result == noreg) result = rscratch1;
3429 BLOCK_COMMENT("cmpxchg {");
3430 if (UseLSE) {
3431 mov(result, expected);
3432 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3433 compare_eq(result, expected, size);
3434 #ifdef ASSERT
3435 // Poison rscratch1 which is written on !UseLSE branch
3436 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3437 #endif
3438 } else {
3439 Label retry_load, done;
3440 prfm(Address(addr), PSTL1STRM);
3441 bind(retry_load);
3442 load_exclusive(result, addr, size, acquire);
3443 compare_eq(result, expected, size);
3444 br(Assembler::NE, done);
3445 store_exclusive(rscratch1, new_val, addr, size, release);
3446 if (weak) {
3447 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3448 } else {
3449 cbnzw(rscratch1, retry_load);
3450 }
3451 bind(done);
3452 }
3453 BLOCK_COMMENT("} cmpxchg");
3454 }
3455
3456 // A generic comparison. Only compares for equality, clobbers rscratch1.
3457 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3458 if (size == xword) {
3459 cmp(rm, rn);
3460 } else if (size == word) {
3461 cmpw(rm, rn);
3462 } else if (size == halfword) {
3463 eorw(rscratch1, rm, rn);
3464 ands(zr, rscratch1, 0xffff);
3465 } else if (size == byte) {
3466 eorw(rscratch1, rm, rn);
3467 ands(zr, rscratch1, 0xff);
3468 } else {
3469 ShouldNotReachHere();
3470 }
3471 }
3472
3473
3474 static bool different(Register a, RegisterOrConstant b, Register c) {
3475 if (b.is_constant())
3476 return a != c;
3477 else
3478 return a != b.as_register() && a != c && b.as_register() != c;
3479 }
3480
3481 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3482 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3483 if (UseLSE) { \
3484 prev = prev->is_valid() ? prev : zr; \
3485 if (incr.is_register()) { \
3486 AOP(sz, incr.as_register(), prev, addr); \
3487 } else { \
3488 mov(rscratch2, incr.as_constant()); \
3489 AOP(sz, rscratch2, prev, addr); \
3490 } \
3491 return; \
3492 } \
3493 Register result = rscratch2; \
3494 if (prev->is_valid()) \
3495 result = different(prev, incr, addr) ? prev : rscratch2; \
3496 \
3497 Label retry_load; \
3498 prfm(Address(addr), PSTL1STRM); \
3499 bind(retry_load); \
3500 LDXR(result, addr); \
3501 OP(rscratch1, result, incr); \
3502 STXR(rscratch2, rscratch1, addr); \
3503 cbnzw(rscratch2, retry_load); \
3504 if (prev->is_valid() && prev != result) { \
3505 IOP(prev, rscratch1, incr); \
3506 } \
3507 }
3508
3509 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3510 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3511 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3512 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3513
3514 #undef ATOMIC_OP
3515
3516 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3517 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3518 if (UseLSE) { \
3519 prev = prev->is_valid() ? prev : zr; \
3520 AOP(sz, newv, prev, addr); \
3521 return; \
3522 } \
3523 Register result = rscratch2; \
3524 if (prev->is_valid()) \
3525 result = different(prev, newv, addr) ? prev : rscratch2; \
3526 \
3527 Label retry_load; \
3528 prfm(Address(addr), PSTL1STRM); \
3529 bind(retry_load); \
3530 LDXR(result, addr); \
3531 STXR(rscratch1, newv, addr); \
3532 cbnzw(rscratch1, retry_load); \
3533 if (prev->is_valid() && prev != result) \
3534 mov(prev, result); \
3535 }
3536
3537 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3538 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3539 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3540 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3541 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3542 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3543
3544 #undef ATOMIC_XCHG
3545
3546 #ifndef PRODUCT
3547 extern "C" void findpc(intptr_t x);
3548 #endif
3549
3550 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3551 {
3552 // In order to get locks to work, we need to fake a in_VM state
3553 if (ShowMessageBoxOnError ) {
3554 JavaThread* thread = JavaThread::current();
3555 JavaThreadState saved_state = thread->thread_state();
3556 thread->set_thread_state(_thread_in_vm);
3557 #ifndef PRODUCT
3558 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3559 ttyLocker ttyl;
3560 BytecodeCounter::print();
3561 }
3562 #endif
3563 if (os::message_box(msg, "Execution stopped, print registers?")) {
3564 ttyLocker ttyl;
3565 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3566 #ifndef PRODUCT
3567 tty->cr();
3568 findpc(pc);
3569 tty->cr();
3570 #endif
3571 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3572 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3573 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3574 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3575 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3576 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3577 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3578 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3579 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3580 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3581 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3582 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3583 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3584 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3585 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3586 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3587 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3588 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3589 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3590 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3591 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3592 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3593 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3594 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3595 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3596 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3597 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3598 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3599 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3600 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3601 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3602 BREAKPOINT;
3603 }
3604 }
3605 fatal("DEBUG MESSAGE: %s", msg);
3606 }
3607
3608 RegSet MacroAssembler::call_clobbered_gp_registers() {
3609 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3610 #ifndef R18_RESERVED
3611 regs += r18_tls;
3612 #endif
3613 return regs;
3614 }
3615
3616 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3617 int step = 4 * wordSize;
3618 push(call_clobbered_gp_registers() - exclude, sp);
3619 sub(sp, sp, step);
3620 mov(rscratch1, -step);
3621 // Push v0-v7, v16-v31.
3622 for (int i = 31; i>= 4; i -= 4) {
3623 if (i <= v7->encoding() || i >= v16->encoding())
3624 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3625 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3626 }
3627 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3628 as_FloatRegister(3), T1D, Address(sp));
3629 }
3630
3631 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3632 for (int i = 0; i < 32; i += 4) {
3633 if (i <= v7->encoding() || i >= v16->encoding())
3634 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3635 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3636 }
3637
3638 reinitialize_ptrue();
3639
3640 pop(call_clobbered_gp_registers() - exclude, sp);
3641 }
3642
3643 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3644 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3645 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3646 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3647 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3648 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3649 sve_str(as_FloatRegister(i), Address(sp, i));
3650 }
3651 } else {
3652 int step = (save_vectors ? 8 : 4) * wordSize;
3653 mov(rscratch1, -step);
3654 sub(sp, sp, step);
3655 for (int i = 28; i >= 4; i -= 4) {
3656 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3657 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3658 }
3659 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3660 }
3661 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3662 sub(sp, sp, total_predicate_in_bytes);
3663 for (int i = 0; i < PRegister::number_of_registers; i++) {
3664 sve_str(as_PRegister(i), Address(sp, i));
3665 }
3666 }
3667 }
3668
3669 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3670 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3671 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3672 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3673 sve_ldr(as_PRegister(i), Address(sp, i));
3674 }
3675 add(sp, sp, total_predicate_in_bytes);
3676 }
3677 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3678 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3679 sve_ldr(as_FloatRegister(i), Address(sp, i));
3680 }
3681 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3682 } else {
3683 int step = (restore_vectors ? 8 : 4) * wordSize;
3684 for (int i = 0; i <= 28; i += 4)
3685 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3686 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3687 }
3688
3689 // We may use predicate registers and rely on ptrue with SVE,
3690 // regardless of wide vector (> 8 bytes) used or not.
3691 if (use_sve) {
3692 reinitialize_ptrue();
3693 }
3694
3695 // integer registers except lr & sp
3696 pop(RegSet::range(r0, r17), sp);
3697 #ifdef R18_RESERVED
3698 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3699 pop(RegSet::range(r20, r29), sp);
3700 #else
3701 pop(RegSet::range(r18_tls, r29), sp);
3702 #endif
3703 }
3704
3705 /**
3706 * Helpers for multiply_to_len().
3707 */
3708 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3709 Register src1, Register src2) {
3710 adds(dest_lo, dest_lo, src1);
3711 adc(dest_hi, dest_hi, zr);
3712 adds(dest_lo, dest_lo, src2);
3713 adc(final_dest_hi, dest_hi, zr);
3714 }
3715
3716 // Generate an address from (r + r1 extend offset). "size" is the
3717 // size of the operand. The result may be in rscratch2.
3718 Address MacroAssembler::offsetted_address(Register r, Register r1,
3719 Address::extend ext, int offset, int size) {
3720 if (offset || (ext.shift() % size != 0)) {
3721 lea(rscratch2, Address(r, r1, ext));
3722 return Address(rscratch2, offset);
3723 } else {
3724 return Address(r, r1, ext);
3725 }
3726 }
3727
3728 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3729 {
3730 assert(offset >= 0, "spill to negative address?");
3731 // Offset reachable ?
3732 // Not aligned - 9 bits signed offset
3733 // Aligned - 12 bits unsigned offset shifted
3734 Register base = sp;
3735 if ((offset & (size-1)) && offset >= (1<<8)) {
3736 add(tmp, base, offset & ((1<<12)-1));
3737 base = tmp;
3738 offset &= -1u<<12;
3739 }
3740
3741 if (offset >= (1<<12) * size) {
3742 add(tmp, base, offset & (((1<<12)-1)<<12));
3743 base = tmp;
3744 offset &= ~(((1<<12)-1)<<12);
3745 }
3746
3747 return Address(base, offset);
3748 }
3749
3750 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3751 assert(offset >= 0, "spill to negative address?");
3752
3753 Register base = sp;
3754
3755 // An immediate offset in the range 0 to 255 which is multiplied
3756 // by the current vector or predicate register size in bytes.
3757 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3758 return Address(base, offset / sve_reg_size_in_bytes);
3759 }
3760
3761 add(tmp, base, offset);
3762 return Address(tmp);
3763 }
3764
3765 // Checks whether offset is aligned.
3766 // Returns true if it is, else false.
3767 bool MacroAssembler::merge_alignment_check(Register base,
3768 size_t size,
3769 int64_t cur_offset,
3770 int64_t prev_offset) const {
3771 if (AvoidUnalignedAccesses) {
3772 if (base == sp) {
3773 // Checks whether low offset if aligned to pair of registers.
3774 int64_t pair_mask = size * 2 - 1;
3775 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3776 return (offset & pair_mask) == 0;
3777 } else { // If base is not sp, we can't guarantee the access is aligned.
3778 return false;
3779 }
3780 } else {
3781 int64_t mask = size - 1;
3782 // Load/store pair instruction only supports element size aligned offset.
3783 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3784 }
3785 }
3786
3787 // Checks whether current and previous loads/stores can be merged.
3788 // Returns true if it can be merged, else false.
3789 bool MacroAssembler::ldst_can_merge(Register rt,
3790 const Address &adr,
3791 size_t cur_size_in_bytes,
3792 bool is_store) const {
3793 address prev = pc() - NativeInstruction::instruction_size;
3794 address last = code()->last_insn();
3795
3796 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3797 return false;
3798 }
3799
3800 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3801 return false;
3802 }
3803
3804 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3805 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3806
3807 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3808 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3809
3810 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3811 return false;
3812 }
3813
3814 int64_t max_offset = 63 * prev_size_in_bytes;
3815 int64_t min_offset = -64 * prev_size_in_bytes;
3816
3817 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3818
3819 // Only same base can be merged.
3820 if (adr.base() != prev_ldst->base()) {
3821 return false;
3822 }
3823
3824 int64_t cur_offset = adr.offset();
3825 int64_t prev_offset = prev_ldst->offset();
3826 size_t diff = abs(cur_offset - prev_offset);
3827 if (diff != prev_size_in_bytes) {
3828 return false;
3829 }
3830
3831 // Following cases can not be merged:
3832 // ldr x2, [x2, #8]
3833 // ldr x3, [x2, #16]
3834 // or:
3835 // ldr x2, [x3, #8]
3836 // ldr x2, [x3, #16]
3837 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3838 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3839 return false;
3840 }
3841
3842 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3843 // Offset range must be in ldp/stp instruction's range.
3844 if (low_offset > max_offset || low_offset < min_offset) {
3845 return false;
3846 }
3847
3848 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3849 return true;
3850 }
3851
3852 return false;
3853 }
3854
3855 // Merge current load/store with previous load/store into ldp/stp.
3856 void MacroAssembler::merge_ldst(Register rt,
3857 const Address &adr,
3858 size_t cur_size_in_bytes,
3859 bool is_store) {
3860
3861 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3862
3863 Register rt_low, rt_high;
3864 address prev = pc() - NativeInstruction::instruction_size;
3865 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3866
3867 int64_t offset;
3868
3869 if (adr.offset() < prev_ldst->offset()) {
3870 offset = adr.offset();
3871 rt_low = rt;
3872 rt_high = prev_ldst->target();
3873 } else {
3874 offset = prev_ldst->offset();
3875 rt_low = prev_ldst->target();
3876 rt_high = rt;
3877 }
3878
3879 Address adr_p = Address(prev_ldst->base(), offset);
3880 // Overwrite previous generated binary.
3881 code_section()->set_end(prev);
3882
3883 const size_t sz = prev_ldst->size_in_bytes();
3884 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3885 if (!is_store) {
3886 BLOCK_COMMENT("merged ldr pair");
3887 if (sz == 8) {
3888 ldp(rt_low, rt_high, adr_p);
3889 } else {
3890 ldpw(rt_low, rt_high, adr_p);
3891 }
3892 } else {
3893 BLOCK_COMMENT("merged str pair");
3894 if (sz == 8) {
3895 stp(rt_low, rt_high, adr_p);
3896 } else {
3897 stpw(rt_low, rt_high, adr_p);
3898 }
3899 }
3900 }
3901
3902 /**
3903 * Multiply 64 bit by 64 bit first loop.
3904 */
3905 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3906 Register y, Register y_idx, Register z,
3907 Register carry, Register product,
3908 Register idx, Register kdx) {
3909 //
3910 // jlong carry, x[], y[], z[];
3911 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3912 // huge_128 product = y[idx] * x[xstart] + carry;
3913 // z[kdx] = (jlong)product;
3914 // carry = (jlong)(product >>> 64);
3915 // }
3916 // z[xstart] = carry;
3917 //
3918
3919 Label L_first_loop, L_first_loop_exit;
3920 Label L_one_x, L_one_y, L_multiply;
3921
3922 subsw(xstart, xstart, 1);
3923 br(Assembler::MI, L_one_x);
3924
3925 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3926 ldr(x_xstart, Address(rscratch1));
3927 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3928
3929 bind(L_first_loop);
3930 subsw(idx, idx, 1);
3931 br(Assembler::MI, L_first_loop_exit);
3932 subsw(idx, idx, 1);
3933 br(Assembler::MI, L_one_y);
3934 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3935 ldr(y_idx, Address(rscratch1));
3936 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3937 bind(L_multiply);
3938
3939 // AArch64 has a multiply-accumulate instruction that we can't use
3940 // here because it has no way to process carries, so we have to use
3941 // separate add and adc instructions. Bah.
3942 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3943 mul(product, x_xstart, y_idx);
3944 adds(product, product, carry);
3945 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3946
3947 subw(kdx, kdx, 2);
3948 ror(product, product, 32); // back to big-endian
3949 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3950
3951 b(L_first_loop);
3952
3953 bind(L_one_y);
3954 ldrw(y_idx, Address(y, 0));
3955 b(L_multiply);
3956
3957 bind(L_one_x);
3958 ldrw(x_xstart, Address(x, 0));
3959 b(L_first_loop);
3960
3961 bind(L_first_loop_exit);
3962 }
3963
3964 /**
3965 * Multiply 128 bit by 128. Unrolled inner loop.
3966 *
3967 */
3968 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3969 Register carry, Register carry2,
3970 Register idx, Register jdx,
3971 Register yz_idx1, Register yz_idx2,
3972 Register tmp, Register tmp3, Register tmp4,
3973 Register tmp6, Register product_hi) {
3974
3975 // jlong carry, x[], y[], z[];
3976 // int kdx = ystart+1;
3977 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
3978 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
3979 // jlong carry2 = (jlong)(tmp3 >>> 64);
3980 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
3981 // carry = (jlong)(tmp4 >>> 64);
3982 // z[kdx+idx+1] = (jlong)tmp3;
3983 // z[kdx+idx] = (jlong)tmp4;
3984 // }
3985 // idx += 2;
3986 // if (idx > 0) {
3987 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
3988 // z[kdx+idx] = (jlong)yz_idx1;
3989 // carry = (jlong)(yz_idx1 >>> 64);
3990 // }
3991 //
3992
3993 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
3994
3995 lsrw(jdx, idx, 2);
3996
3997 bind(L_third_loop);
3998
3999 subsw(jdx, jdx, 1);
4000 br(Assembler::MI, L_third_loop_exit);
4001 subw(idx, idx, 4);
4002
4003 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4004
4005 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4006
4007 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4008
4009 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4010 ror(yz_idx2, yz_idx2, 32);
4011
4012 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4013
4014 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4015 umulh(tmp4, product_hi, yz_idx1);
4016
4017 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4018 ror(rscratch2, rscratch2, 32);
4019
4020 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4021 umulh(carry2, product_hi, yz_idx2);
4022
4023 // propagate sum of both multiplications into carry:tmp4:tmp3
4024 adds(tmp3, tmp3, carry);
4025 adc(tmp4, tmp4, zr);
4026 adds(tmp3, tmp3, rscratch1);
4027 adcs(tmp4, tmp4, tmp);
4028 adc(carry, carry2, zr);
4029 adds(tmp4, tmp4, rscratch2);
4030 adc(carry, carry, zr);
4031
4032 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4033 ror(tmp4, tmp4, 32);
4034 stp(tmp4, tmp3, Address(tmp6, 0));
4035
4036 b(L_third_loop);
4037 bind (L_third_loop_exit);
4038
4039 andw (idx, idx, 0x3);
4040 cbz(idx, L_post_third_loop_done);
4041
4042 Label L_check_1;
4043 subsw(idx, idx, 2);
4044 br(Assembler::MI, L_check_1);
4045
4046 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4047 ldr(yz_idx1, Address(rscratch1, 0));
4048 ror(yz_idx1, yz_idx1, 32);
4049 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4050 umulh(tmp4, product_hi, yz_idx1);
4051 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4052 ldr(yz_idx2, Address(rscratch1, 0));
4053 ror(yz_idx2, yz_idx2, 32);
4054
4055 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4056
4057 ror(tmp3, tmp3, 32);
4058 str(tmp3, Address(rscratch1, 0));
4059
4060 bind (L_check_1);
4061
4062 andw (idx, idx, 0x1);
4063 subsw(idx, idx, 1);
4064 br(Assembler::MI, L_post_third_loop_done);
4065 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4066 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4067 umulh(carry2, tmp4, product_hi);
4068 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4069
4070 add2_with_carry(carry2, tmp3, tmp4, carry);
4071
4072 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4073 extr(carry, carry2, tmp3, 32);
4074
4075 bind(L_post_third_loop_done);
4076 }
4077
4078 /**
4079 * Code for BigInteger::multiplyToLen() intrinsic.
4080 *
4081 * r0: x
4082 * r1: xlen
4083 * r2: y
4084 * r3: ylen
4085 * r4: z
4086 * r5: tmp0
4087 * r10: tmp1
4088 * r11: tmp2
4089 * r12: tmp3
4090 * r13: tmp4
4091 * r14: tmp5
4092 * r15: tmp6
4093 * r16: tmp7
4094 *
4095 */
4096 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4097 Register z, Register tmp0,
4098 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4099 Register tmp5, Register tmp6, Register product_hi) {
4100
4101 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4102
4103 const Register idx = tmp1;
4104 const Register kdx = tmp2;
4105 const Register xstart = tmp3;
4106
4107 const Register y_idx = tmp4;
4108 const Register carry = tmp5;
4109 const Register product = xlen;
4110 const Register x_xstart = tmp0;
4111
4112 // First Loop.
4113 //
4114 // final static long LONG_MASK = 0xffffffffL;
4115 // int xstart = xlen - 1;
4116 // int ystart = ylen - 1;
4117 // long carry = 0;
4118 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4119 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4120 // z[kdx] = (int)product;
4121 // carry = product >>> 32;
4122 // }
4123 // z[xstart] = (int)carry;
4124 //
4125
4126 movw(idx, ylen); // idx = ylen;
4127 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4128 mov(carry, zr); // carry = 0;
4129
4130 Label L_done;
4131
4132 movw(xstart, xlen);
4133 subsw(xstart, xstart, 1);
4134 br(Assembler::MI, L_done);
4135
4136 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4137
4138 Label L_second_loop;
4139 cbzw(kdx, L_second_loop);
4140
4141 Label L_carry;
4142 subw(kdx, kdx, 1);
4143 cbzw(kdx, L_carry);
4144
4145 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4146 lsr(carry, carry, 32);
4147 subw(kdx, kdx, 1);
4148
4149 bind(L_carry);
4150 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4151
4152 // Second and third (nested) loops.
4153 //
4154 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4155 // carry = 0;
4156 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4157 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4158 // (z[k] & LONG_MASK) + carry;
4159 // z[k] = (int)product;
4160 // carry = product >>> 32;
4161 // }
4162 // z[i] = (int)carry;
4163 // }
4164 //
4165 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4166
4167 const Register jdx = tmp1;
4168
4169 bind(L_second_loop);
4170 mov(carry, zr); // carry = 0;
4171 movw(jdx, ylen); // j = ystart+1
4172
4173 subsw(xstart, xstart, 1); // i = xstart-1;
4174 br(Assembler::MI, L_done);
4175
4176 str(z, Address(pre(sp, -4 * wordSize)));
4177
4178 Label L_last_x;
4179 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4180 subsw(xstart, xstart, 1); // i = xstart-1;
4181 br(Assembler::MI, L_last_x);
4182
4183 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4184 ldr(product_hi, Address(rscratch1));
4185 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4186
4187 Label L_third_loop_prologue;
4188 bind(L_third_loop_prologue);
4189
4190 str(ylen, Address(sp, wordSize));
4191 stp(x, xstart, Address(sp, 2 * wordSize));
4192 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4193 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4194 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4195 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4196
4197 addw(tmp3, xlen, 1);
4198 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4199 subsw(tmp3, tmp3, 1);
4200 br(Assembler::MI, L_done);
4201
4202 lsr(carry, carry, 32);
4203 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4204 b(L_second_loop);
4205
4206 // Next infrequent code is moved outside loops.
4207 bind(L_last_x);
4208 ldrw(product_hi, Address(x, 0));
4209 b(L_third_loop_prologue);
4210
4211 bind(L_done);
4212 }
4213
4214 // Code for BigInteger::mulAdd intrinsic
4215 // out = r0
4216 // in = r1
4217 // offset = r2 (already out.length-offset)
4218 // len = r3
4219 // k = r4
4220 //
4221 // pseudo code from java implementation:
4222 // carry = 0;
4223 // offset = out.length-offset - 1;
4224 // for (int j=len-1; j >= 0; j--) {
4225 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4226 // out[offset--] = (int)product;
4227 // carry = product >>> 32;
4228 // }
4229 // return (int)carry;
4230 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4231 Register len, Register k) {
4232 Label LOOP, END;
4233 // pre-loop
4234 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4235 csel(out, zr, out, Assembler::EQ);
4236 br(Assembler::EQ, END);
4237 add(in, in, len, LSL, 2); // in[j+1] address
4238 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4239 mov(out, zr); // used to keep carry now
4240 BIND(LOOP);
4241 ldrw(rscratch1, Address(pre(in, -4)));
4242 madd(rscratch1, rscratch1, k, out);
4243 ldrw(rscratch2, Address(pre(offset, -4)));
4244 add(rscratch1, rscratch1, rscratch2);
4245 strw(rscratch1, Address(offset));
4246 lsr(out, rscratch1, 32);
4247 subs(len, len, 1);
4248 br(Assembler::NE, LOOP);
4249 BIND(END);
4250 }
4251
4252 /**
4253 * Emits code to update CRC-32 with a byte value according to constants in table
4254 *
4255 * @param [in,out]crc Register containing the crc.
4256 * @param [in]val Register containing the byte to fold into the CRC.
4257 * @param [in]table Register containing the table of crc constants.
4258 *
4259 * uint32_t crc;
4260 * val = crc_table[(val ^ crc) & 0xFF];
4261 * crc = val ^ (crc >> 8);
4262 *
4263 */
4264 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4265 eor(val, val, crc);
4266 andr(val, val, 0xff);
4267 ldrw(val, Address(table, val, Address::lsl(2)));
4268 eor(crc, val, crc, Assembler::LSR, 8);
4269 }
4270
4271 /**
4272 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4273 *
4274 * @param [in,out]crc Register containing the crc.
4275 * @param [in]v Register containing the 32-bit to fold into the CRC.
4276 * @param [in]table0 Register containing table 0 of crc constants.
4277 * @param [in]table1 Register containing table 1 of crc constants.
4278 * @param [in]table2 Register containing table 2 of crc constants.
4279 * @param [in]table3 Register containing table 3 of crc constants.
4280 *
4281 * uint32_t crc;
4282 * v = crc ^ v
4283 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4284 *
4285 */
4286 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4287 Register table0, Register table1, Register table2, Register table3,
4288 bool upper) {
4289 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4290 uxtb(tmp, v);
4291 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4292 ubfx(tmp, v, 8, 8);
4293 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4294 eor(crc, crc, tmp);
4295 ubfx(tmp, v, 16, 8);
4296 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4297 eor(crc, crc, tmp);
4298 ubfx(tmp, v, 24, 8);
4299 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4300 eor(crc, crc, tmp);
4301 }
4302
4303 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4304 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4305 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4306 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4307
4308 subs(tmp0, len, 384);
4309 mvnw(crc, crc);
4310 br(Assembler::GE, CRC_by128_pre);
4311 BIND(CRC_less128);
4312 subs(len, len, 32);
4313 br(Assembler::GE, CRC_by32_loop);
4314 BIND(CRC_less32);
4315 adds(len, len, 32 - 4);
4316 br(Assembler::GE, CRC_by4_loop);
4317 adds(len, len, 4);
4318 br(Assembler::GT, CRC_by1_loop);
4319 b(L_exit);
4320
4321 BIND(CRC_by32_loop);
4322 ldp(tmp0, tmp1, Address(buf));
4323 crc32x(crc, crc, tmp0);
4324 ldp(tmp2, tmp3, Address(buf, 16));
4325 crc32x(crc, crc, tmp1);
4326 add(buf, buf, 32);
4327 crc32x(crc, crc, tmp2);
4328 subs(len, len, 32);
4329 crc32x(crc, crc, tmp3);
4330 br(Assembler::GE, CRC_by32_loop);
4331 cmn(len, (u1)32);
4332 br(Assembler::NE, CRC_less32);
4333 b(L_exit);
4334
4335 BIND(CRC_by4_loop);
4336 ldrw(tmp0, Address(post(buf, 4)));
4337 subs(len, len, 4);
4338 crc32w(crc, crc, tmp0);
4339 br(Assembler::GE, CRC_by4_loop);
4340 adds(len, len, 4);
4341 br(Assembler::LE, L_exit);
4342 BIND(CRC_by1_loop);
4343 ldrb(tmp0, Address(post(buf, 1)));
4344 subs(len, len, 1);
4345 crc32b(crc, crc, tmp0);
4346 br(Assembler::GT, CRC_by1_loop);
4347 b(L_exit);
4348
4349 BIND(CRC_by128_pre);
4350 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4351 4*256*sizeof(juint) + 8*sizeof(juint));
4352 mov(crc, 0);
4353 crc32x(crc, crc, tmp0);
4354 crc32x(crc, crc, tmp1);
4355
4356 cbnz(len, CRC_less128);
4357
4358 BIND(L_exit);
4359 mvnw(crc, crc);
4360 }
4361
4362 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4363 Register len, Register tmp0, Register tmp1, Register tmp2,
4364 Register tmp3) {
4365 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4366 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4367
4368 mvnw(crc, crc);
4369
4370 subs(len, len, 128);
4371 br(Assembler::GE, CRC_by64_pre);
4372 BIND(CRC_less64);
4373 adds(len, len, 128-32);
4374 br(Assembler::GE, CRC_by32_loop);
4375 BIND(CRC_less32);
4376 adds(len, len, 32-4);
4377 br(Assembler::GE, CRC_by4_loop);
4378 adds(len, len, 4);
4379 br(Assembler::GT, CRC_by1_loop);
4380 b(L_exit);
4381
4382 BIND(CRC_by32_loop);
4383 ldp(tmp0, tmp1, Address(post(buf, 16)));
4384 subs(len, len, 32);
4385 crc32x(crc, crc, tmp0);
4386 ldr(tmp2, Address(post(buf, 8)));
4387 crc32x(crc, crc, tmp1);
4388 ldr(tmp3, Address(post(buf, 8)));
4389 crc32x(crc, crc, tmp2);
4390 crc32x(crc, crc, tmp3);
4391 br(Assembler::GE, CRC_by32_loop);
4392 cmn(len, (u1)32);
4393 br(Assembler::NE, CRC_less32);
4394 b(L_exit);
4395
4396 BIND(CRC_by4_loop);
4397 ldrw(tmp0, Address(post(buf, 4)));
4398 subs(len, len, 4);
4399 crc32w(crc, crc, tmp0);
4400 br(Assembler::GE, CRC_by4_loop);
4401 adds(len, len, 4);
4402 br(Assembler::LE, L_exit);
4403 BIND(CRC_by1_loop);
4404 ldrb(tmp0, Address(post(buf, 1)));
4405 subs(len, len, 1);
4406 crc32b(crc, crc, tmp0);
4407 br(Assembler::GT, CRC_by1_loop);
4408 b(L_exit);
4409
4410 BIND(CRC_by64_pre);
4411 sub(buf, buf, 8);
4412 ldp(tmp0, tmp1, Address(buf, 8));
4413 crc32x(crc, crc, tmp0);
4414 ldr(tmp2, Address(buf, 24));
4415 crc32x(crc, crc, tmp1);
4416 ldr(tmp3, Address(buf, 32));
4417 crc32x(crc, crc, tmp2);
4418 ldr(tmp0, Address(buf, 40));
4419 crc32x(crc, crc, tmp3);
4420 ldr(tmp1, Address(buf, 48));
4421 crc32x(crc, crc, tmp0);
4422 ldr(tmp2, Address(buf, 56));
4423 crc32x(crc, crc, tmp1);
4424 ldr(tmp3, Address(pre(buf, 64)));
4425
4426 b(CRC_by64_loop);
4427
4428 align(CodeEntryAlignment);
4429 BIND(CRC_by64_loop);
4430 subs(len, len, 64);
4431 crc32x(crc, crc, tmp2);
4432 ldr(tmp0, Address(buf, 8));
4433 crc32x(crc, crc, tmp3);
4434 ldr(tmp1, Address(buf, 16));
4435 crc32x(crc, crc, tmp0);
4436 ldr(tmp2, Address(buf, 24));
4437 crc32x(crc, crc, tmp1);
4438 ldr(tmp3, Address(buf, 32));
4439 crc32x(crc, crc, tmp2);
4440 ldr(tmp0, Address(buf, 40));
4441 crc32x(crc, crc, tmp3);
4442 ldr(tmp1, Address(buf, 48));
4443 crc32x(crc, crc, tmp0);
4444 ldr(tmp2, Address(buf, 56));
4445 crc32x(crc, crc, tmp1);
4446 ldr(tmp3, Address(pre(buf, 64)));
4447 br(Assembler::GE, CRC_by64_loop);
4448
4449 // post-loop
4450 crc32x(crc, crc, tmp2);
4451 crc32x(crc, crc, tmp3);
4452
4453 sub(len, len, 64);
4454 add(buf, buf, 8);
4455 cmn(len, (u1)128);
4456 br(Assembler::NE, CRC_less64);
4457 BIND(L_exit);
4458 mvnw(crc, crc);
4459 }
4460
4461 /**
4462 * @param crc register containing existing CRC (32-bit)
4463 * @param buf register pointing to input byte buffer (byte*)
4464 * @param len register containing number of bytes
4465 * @param table register that will contain address of CRC table
4466 * @param tmp scratch register
4467 */
4468 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4469 Register table0, Register table1, Register table2, Register table3,
4470 Register tmp, Register tmp2, Register tmp3) {
4471 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4472
4473 if (UseCryptoPmullForCRC32) {
4474 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4475 return;
4476 }
4477
4478 if (UseCRC32) {
4479 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4480 return;
4481 }
4482
4483 mvnw(crc, crc);
4484
4485 {
4486 uint64_t offset;
4487 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4488 add(table0, table0, offset);
4489 }
4490 add(table1, table0, 1*256*sizeof(juint));
4491 add(table2, table0, 2*256*sizeof(juint));
4492 add(table3, table0, 3*256*sizeof(juint));
4493
4494 { // Neon code start
4495 cmp(len, (u1)64);
4496 br(Assembler::LT, L_by16);
4497 eor(v16, T16B, v16, v16);
4498
4499 Label L_fold;
4500
4501 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4502
4503 ld1(v0, v1, T2D, post(buf, 32));
4504 ld1r(v4, T2D, post(tmp, 8));
4505 ld1r(v5, T2D, post(tmp, 8));
4506 ld1r(v6, T2D, post(tmp, 8));
4507 ld1r(v7, T2D, post(tmp, 8));
4508 mov(v16, S, 0, crc);
4509
4510 eor(v0, T16B, v0, v16);
4511 sub(len, len, 64);
4512
4513 BIND(L_fold);
4514 pmull(v22, T8H, v0, v5, T8B);
4515 pmull(v20, T8H, v0, v7, T8B);
4516 pmull(v23, T8H, v0, v4, T8B);
4517 pmull(v21, T8H, v0, v6, T8B);
4518
4519 pmull2(v18, T8H, v0, v5, T16B);
4520 pmull2(v16, T8H, v0, v7, T16B);
4521 pmull2(v19, T8H, v0, v4, T16B);
4522 pmull2(v17, T8H, v0, v6, T16B);
4523
4524 uzp1(v24, T8H, v20, v22);
4525 uzp2(v25, T8H, v20, v22);
4526 eor(v20, T16B, v24, v25);
4527
4528 uzp1(v26, T8H, v16, v18);
4529 uzp2(v27, T8H, v16, v18);
4530 eor(v16, T16B, v26, v27);
4531
4532 ushll2(v22, T4S, v20, T8H, 8);
4533 ushll(v20, T4S, v20, T4H, 8);
4534
4535 ushll2(v18, T4S, v16, T8H, 8);
4536 ushll(v16, T4S, v16, T4H, 8);
4537
4538 eor(v22, T16B, v23, v22);
4539 eor(v18, T16B, v19, v18);
4540 eor(v20, T16B, v21, v20);
4541 eor(v16, T16B, v17, v16);
4542
4543 uzp1(v17, T2D, v16, v20);
4544 uzp2(v21, T2D, v16, v20);
4545 eor(v17, T16B, v17, v21);
4546
4547 ushll2(v20, T2D, v17, T4S, 16);
4548 ushll(v16, T2D, v17, T2S, 16);
4549
4550 eor(v20, T16B, v20, v22);
4551 eor(v16, T16B, v16, v18);
4552
4553 uzp1(v17, T2D, v20, v16);
4554 uzp2(v21, T2D, v20, v16);
4555 eor(v28, T16B, v17, v21);
4556
4557 pmull(v22, T8H, v1, v5, T8B);
4558 pmull(v20, T8H, v1, v7, T8B);
4559 pmull(v23, T8H, v1, v4, T8B);
4560 pmull(v21, T8H, v1, v6, T8B);
4561
4562 pmull2(v18, T8H, v1, v5, T16B);
4563 pmull2(v16, T8H, v1, v7, T16B);
4564 pmull2(v19, T8H, v1, v4, T16B);
4565 pmull2(v17, T8H, v1, v6, T16B);
4566
4567 ld1(v0, v1, T2D, post(buf, 32));
4568
4569 uzp1(v24, T8H, v20, v22);
4570 uzp2(v25, T8H, v20, v22);
4571 eor(v20, T16B, v24, v25);
4572
4573 uzp1(v26, T8H, v16, v18);
4574 uzp2(v27, T8H, v16, v18);
4575 eor(v16, T16B, v26, v27);
4576
4577 ushll2(v22, T4S, v20, T8H, 8);
4578 ushll(v20, T4S, v20, T4H, 8);
4579
4580 ushll2(v18, T4S, v16, T8H, 8);
4581 ushll(v16, T4S, v16, T4H, 8);
4582
4583 eor(v22, T16B, v23, v22);
4584 eor(v18, T16B, v19, v18);
4585 eor(v20, T16B, v21, v20);
4586 eor(v16, T16B, v17, v16);
4587
4588 uzp1(v17, T2D, v16, v20);
4589 uzp2(v21, T2D, v16, v20);
4590 eor(v16, T16B, v17, v21);
4591
4592 ushll2(v20, T2D, v16, T4S, 16);
4593 ushll(v16, T2D, v16, T2S, 16);
4594
4595 eor(v20, T16B, v22, v20);
4596 eor(v16, T16B, v16, v18);
4597
4598 uzp1(v17, T2D, v20, v16);
4599 uzp2(v21, T2D, v20, v16);
4600 eor(v20, T16B, v17, v21);
4601
4602 shl(v16, T2D, v28, 1);
4603 shl(v17, T2D, v20, 1);
4604
4605 eor(v0, T16B, v0, v16);
4606 eor(v1, T16B, v1, v17);
4607
4608 subs(len, len, 32);
4609 br(Assembler::GE, L_fold);
4610
4611 mov(crc, 0);
4612 mov(tmp, v0, D, 0);
4613 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4614 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4615 mov(tmp, v0, D, 1);
4616 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4617 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4618 mov(tmp, v1, D, 0);
4619 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4620 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4621 mov(tmp, v1, D, 1);
4622 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4623 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4624
4625 add(len, len, 32);
4626 } // Neon code end
4627
4628 BIND(L_by16);
4629 subs(len, len, 16);
4630 br(Assembler::GE, L_by16_loop);
4631 adds(len, len, 16-4);
4632 br(Assembler::GE, L_by4_loop);
4633 adds(len, len, 4);
4634 br(Assembler::GT, L_by1_loop);
4635 b(L_exit);
4636
4637 BIND(L_by4_loop);
4638 ldrw(tmp, Address(post(buf, 4)));
4639 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4640 subs(len, len, 4);
4641 br(Assembler::GE, L_by4_loop);
4642 adds(len, len, 4);
4643 br(Assembler::LE, L_exit);
4644 BIND(L_by1_loop);
4645 subs(len, len, 1);
4646 ldrb(tmp, Address(post(buf, 1)));
4647 update_byte_crc32(crc, tmp, table0);
4648 br(Assembler::GT, L_by1_loop);
4649 b(L_exit);
4650
4651 align(CodeEntryAlignment);
4652 BIND(L_by16_loop);
4653 subs(len, len, 16);
4654 ldp(tmp, tmp3, Address(post(buf, 16)));
4655 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4656 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4657 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4658 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4659 br(Assembler::GE, L_by16_loop);
4660 adds(len, len, 16-4);
4661 br(Assembler::GE, L_by4_loop);
4662 adds(len, len, 4);
4663 br(Assembler::GT, L_by1_loop);
4664 BIND(L_exit);
4665 mvnw(crc, crc);
4666 }
4667
4668 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4669 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4670 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4671 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4672
4673 subs(tmp0, len, 384);
4674 br(Assembler::GE, CRC_by128_pre);
4675 BIND(CRC_less128);
4676 subs(len, len, 32);
4677 br(Assembler::GE, CRC_by32_loop);
4678 BIND(CRC_less32);
4679 adds(len, len, 32 - 4);
4680 br(Assembler::GE, CRC_by4_loop);
4681 adds(len, len, 4);
4682 br(Assembler::GT, CRC_by1_loop);
4683 b(L_exit);
4684
4685 BIND(CRC_by32_loop);
4686 ldp(tmp0, tmp1, Address(buf));
4687 crc32cx(crc, crc, tmp0);
4688 ldr(tmp2, Address(buf, 16));
4689 crc32cx(crc, crc, tmp1);
4690 ldr(tmp3, Address(buf, 24));
4691 crc32cx(crc, crc, tmp2);
4692 add(buf, buf, 32);
4693 subs(len, len, 32);
4694 crc32cx(crc, crc, tmp3);
4695 br(Assembler::GE, CRC_by32_loop);
4696 cmn(len, (u1)32);
4697 br(Assembler::NE, CRC_less32);
4698 b(L_exit);
4699
4700 BIND(CRC_by4_loop);
4701 ldrw(tmp0, Address(post(buf, 4)));
4702 subs(len, len, 4);
4703 crc32cw(crc, crc, tmp0);
4704 br(Assembler::GE, CRC_by4_loop);
4705 adds(len, len, 4);
4706 br(Assembler::LE, L_exit);
4707 BIND(CRC_by1_loop);
4708 ldrb(tmp0, Address(post(buf, 1)));
4709 subs(len, len, 1);
4710 crc32cb(crc, crc, tmp0);
4711 br(Assembler::GT, CRC_by1_loop);
4712 b(L_exit);
4713
4714 BIND(CRC_by128_pre);
4715 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4716 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4717 mov(crc, 0);
4718 crc32cx(crc, crc, tmp0);
4719 crc32cx(crc, crc, tmp1);
4720
4721 cbnz(len, CRC_less128);
4722
4723 BIND(L_exit);
4724 }
4725
4726 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4727 Register len, Register tmp0, Register tmp1, Register tmp2,
4728 Register tmp3) {
4729 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4730 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4731
4732 subs(len, len, 128);
4733 br(Assembler::GE, CRC_by64_pre);
4734 BIND(CRC_less64);
4735 adds(len, len, 128-32);
4736 br(Assembler::GE, CRC_by32_loop);
4737 BIND(CRC_less32);
4738 adds(len, len, 32-4);
4739 br(Assembler::GE, CRC_by4_loop);
4740 adds(len, len, 4);
4741 br(Assembler::GT, CRC_by1_loop);
4742 b(L_exit);
4743
4744 BIND(CRC_by32_loop);
4745 ldp(tmp0, tmp1, Address(post(buf, 16)));
4746 subs(len, len, 32);
4747 crc32cx(crc, crc, tmp0);
4748 ldr(tmp2, Address(post(buf, 8)));
4749 crc32cx(crc, crc, tmp1);
4750 ldr(tmp3, Address(post(buf, 8)));
4751 crc32cx(crc, crc, tmp2);
4752 crc32cx(crc, crc, tmp3);
4753 br(Assembler::GE, CRC_by32_loop);
4754 cmn(len, (u1)32);
4755 br(Assembler::NE, CRC_less32);
4756 b(L_exit);
4757
4758 BIND(CRC_by4_loop);
4759 ldrw(tmp0, Address(post(buf, 4)));
4760 subs(len, len, 4);
4761 crc32cw(crc, crc, tmp0);
4762 br(Assembler::GE, CRC_by4_loop);
4763 adds(len, len, 4);
4764 br(Assembler::LE, L_exit);
4765 BIND(CRC_by1_loop);
4766 ldrb(tmp0, Address(post(buf, 1)));
4767 subs(len, len, 1);
4768 crc32cb(crc, crc, tmp0);
4769 br(Assembler::GT, CRC_by1_loop);
4770 b(L_exit);
4771
4772 BIND(CRC_by64_pre);
4773 sub(buf, buf, 8);
4774 ldp(tmp0, tmp1, Address(buf, 8));
4775 crc32cx(crc, crc, tmp0);
4776 ldr(tmp2, Address(buf, 24));
4777 crc32cx(crc, crc, tmp1);
4778 ldr(tmp3, Address(buf, 32));
4779 crc32cx(crc, crc, tmp2);
4780 ldr(tmp0, Address(buf, 40));
4781 crc32cx(crc, crc, tmp3);
4782 ldr(tmp1, Address(buf, 48));
4783 crc32cx(crc, crc, tmp0);
4784 ldr(tmp2, Address(buf, 56));
4785 crc32cx(crc, crc, tmp1);
4786 ldr(tmp3, Address(pre(buf, 64)));
4787
4788 b(CRC_by64_loop);
4789
4790 align(CodeEntryAlignment);
4791 BIND(CRC_by64_loop);
4792 subs(len, len, 64);
4793 crc32cx(crc, crc, tmp2);
4794 ldr(tmp0, Address(buf, 8));
4795 crc32cx(crc, crc, tmp3);
4796 ldr(tmp1, Address(buf, 16));
4797 crc32cx(crc, crc, tmp0);
4798 ldr(tmp2, Address(buf, 24));
4799 crc32cx(crc, crc, tmp1);
4800 ldr(tmp3, Address(buf, 32));
4801 crc32cx(crc, crc, tmp2);
4802 ldr(tmp0, Address(buf, 40));
4803 crc32cx(crc, crc, tmp3);
4804 ldr(tmp1, Address(buf, 48));
4805 crc32cx(crc, crc, tmp0);
4806 ldr(tmp2, Address(buf, 56));
4807 crc32cx(crc, crc, tmp1);
4808 ldr(tmp3, Address(pre(buf, 64)));
4809 br(Assembler::GE, CRC_by64_loop);
4810
4811 // post-loop
4812 crc32cx(crc, crc, tmp2);
4813 crc32cx(crc, crc, tmp3);
4814
4815 sub(len, len, 64);
4816 add(buf, buf, 8);
4817 cmn(len, (u1)128);
4818 br(Assembler::NE, CRC_less64);
4819 BIND(L_exit);
4820 }
4821
4822 /**
4823 * @param crc register containing existing CRC (32-bit)
4824 * @param buf register pointing to input byte buffer (byte*)
4825 * @param len register containing number of bytes
4826 * @param table register that will contain address of CRC table
4827 * @param tmp scratch register
4828 */
4829 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4830 Register table0, Register table1, Register table2, Register table3,
4831 Register tmp, Register tmp2, Register tmp3) {
4832 if (UseCryptoPmullForCRC32) {
4833 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4834 } else {
4835 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4836 }
4837 }
4838
4839 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4840 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4841 Label CRC_by128_loop;
4842 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4843
4844 sub(len, len, 256);
4845 Register table = tmp0;
4846 {
4847 uint64_t offset;
4848 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4849 add(table, table, offset);
4850 }
4851 add(table, table, table_offset);
4852
4853 // Registers v0..v7 are used as data registers.
4854 // Registers v16..v31 are used as tmp registers.
4855 sub(buf, buf, 0x10);
4856 ldrq(v0, Address(buf, 0x10));
4857 ldrq(v1, Address(buf, 0x20));
4858 ldrq(v2, Address(buf, 0x30));
4859 ldrq(v3, Address(buf, 0x40));
4860 ldrq(v4, Address(buf, 0x50));
4861 ldrq(v5, Address(buf, 0x60));
4862 ldrq(v6, Address(buf, 0x70));
4863 ldrq(v7, Address(pre(buf, 0x80)));
4864
4865 movi(v31, T4S, 0);
4866 mov(v31, S, 0, crc);
4867 eor(v0, T16B, v0, v31);
4868
4869 // Register v16 contains constants from the crc table.
4870 ldrq(v16, Address(table));
4871 b(CRC_by128_loop);
4872
4873 align(OptoLoopAlignment);
4874 BIND(CRC_by128_loop);
4875 pmull (v17, T1Q, v0, v16, T1D);
4876 pmull2(v18, T1Q, v0, v16, T2D);
4877 ldrq(v0, Address(buf, 0x10));
4878 eor3(v0, T16B, v17, v18, v0);
4879
4880 pmull (v19, T1Q, v1, v16, T1D);
4881 pmull2(v20, T1Q, v1, v16, T2D);
4882 ldrq(v1, Address(buf, 0x20));
4883 eor3(v1, T16B, v19, v20, v1);
4884
4885 pmull (v21, T1Q, v2, v16, T1D);
4886 pmull2(v22, T1Q, v2, v16, T2D);
4887 ldrq(v2, Address(buf, 0x30));
4888 eor3(v2, T16B, v21, v22, v2);
4889
4890 pmull (v23, T1Q, v3, v16, T1D);
4891 pmull2(v24, T1Q, v3, v16, T2D);
4892 ldrq(v3, Address(buf, 0x40));
4893 eor3(v3, T16B, v23, v24, v3);
4894
4895 pmull (v25, T1Q, v4, v16, T1D);
4896 pmull2(v26, T1Q, v4, v16, T2D);
4897 ldrq(v4, Address(buf, 0x50));
4898 eor3(v4, T16B, v25, v26, v4);
4899
4900 pmull (v27, T1Q, v5, v16, T1D);
4901 pmull2(v28, T1Q, v5, v16, T2D);
4902 ldrq(v5, Address(buf, 0x60));
4903 eor3(v5, T16B, v27, v28, v5);
4904
4905 pmull (v29, T1Q, v6, v16, T1D);
4906 pmull2(v30, T1Q, v6, v16, T2D);
4907 ldrq(v6, Address(buf, 0x70));
4908 eor3(v6, T16B, v29, v30, v6);
4909
4910 // Reuse registers v23, v24.
4911 // Using them won't block the first instruction of the next iteration.
4912 pmull (v23, T1Q, v7, v16, T1D);
4913 pmull2(v24, T1Q, v7, v16, T2D);
4914 ldrq(v7, Address(pre(buf, 0x80)));
4915 eor3(v7, T16B, v23, v24, v7);
4916
4917 subs(len, len, 0x80);
4918 br(Assembler::GE, CRC_by128_loop);
4919
4920 // fold into 512 bits
4921 // Use v31 for constants because v16 can be still in use.
4922 ldrq(v31, Address(table, 0x10));
4923
4924 pmull (v17, T1Q, v0, v31, T1D);
4925 pmull2(v18, T1Q, v0, v31, T2D);
4926 eor3(v0, T16B, v17, v18, v4);
4927
4928 pmull (v19, T1Q, v1, v31, T1D);
4929 pmull2(v20, T1Q, v1, v31, T2D);
4930 eor3(v1, T16B, v19, v20, v5);
4931
4932 pmull (v21, T1Q, v2, v31, T1D);
4933 pmull2(v22, T1Q, v2, v31, T2D);
4934 eor3(v2, T16B, v21, v22, v6);
4935
4936 pmull (v23, T1Q, v3, v31, T1D);
4937 pmull2(v24, T1Q, v3, v31, T2D);
4938 eor3(v3, T16B, v23, v24, v7);
4939
4940 // fold into 128 bits
4941 // Use v17 for constants because v31 can be still in use.
4942 ldrq(v17, Address(table, 0x20));
4943 pmull (v25, T1Q, v0, v17, T1D);
4944 pmull2(v26, T1Q, v0, v17, T2D);
4945 eor3(v3, T16B, v3, v25, v26);
4946
4947 // Use v18 for constants because v17 can be still in use.
4948 ldrq(v18, Address(table, 0x30));
4949 pmull (v27, T1Q, v1, v18, T1D);
4950 pmull2(v28, T1Q, v1, v18, T2D);
4951 eor3(v3, T16B, v3, v27, v28);
4952
4953 // Use v19 for constants because v18 can be still in use.
4954 ldrq(v19, Address(table, 0x40));
4955 pmull (v29, T1Q, v2, v19, T1D);
4956 pmull2(v30, T1Q, v2, v19, T2D);
4957 eor3(v0, T16B, v3, v29, v30);
4958
4959 add(len, len, 0x80);
4960 add(buf, buf, 0x10);
4961
4962 mov(tmp0, v0, D, 0);
4963 mov(tmp1, v0, D, 1);
4964 }
4965
4966 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4967 Address adr;
4968 switch(dst.getMode()) {
4969 case Address::base_plus_offset:
4970 // This is the expected mode, although we allow all the other
4971 // forms below.
4972 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
4973 break;
4974 default:
4975 lea(rscratch2, dst);
4976 adr = Address(rscratch2);
4977 break;
4978 }
4979 ldr(rscratch1, adr);
4980 add(rscratch1, rscratch1, src);
4981 str(rscratch1, adr);
4982 }
4983
4984 void MacroAssembler::cmpptr(Register src1, Address src2) {
4985 uint64_t offset;
4986 adrp(rscratch1, src2, offset);
4987 ldr(rscratch1, Address(rscratch1, offset));
4988 cmp(src1, rscratch1);
4989 }
4990
4991 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
4992 cmp(obj1, obj2);
4993 }
4994
4995 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4996 load_method_holder(rresult, rmethod);
4997 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4998 }
4999
5000 void MacroAssembler::load_method_holder(Register holder, Register method) {
5001 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5002 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5003 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5004 }
5005
5006 // Loads the obj's Klass* into dst.
5007 // Preserves all registers (incl src, rscratch1 and rscratch2).
5008 // Input:
5009 // src - the oop we want to load the klass from.
5010 // dst - output narrow klass.
5011 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5012 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5013 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5014 lsr(dst, dst, markWord::klass_shift);
5015 }
5016
5017 void MacroAssembler::load_klass(Register dst, Register src) {
5018 if (UseCompactObjectHeaders) {
5019 load_narrow_klass_compact(dst, src);
5020 decode_klass_not_null(dst);
5021 } else if (UseCompressedClassPointers) {
5022 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5023 decode_klass_not_null(dst);
5024 } else {
5025 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5026 }
5027 }
5028
5029 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5030 if (RestoreMXCSROnJNICalls) {
5031 Label OK;
5032 get_fpcr(tmp1);
5033 mov(tmp2, tmp1);
5034 // Set FPCR to the state we need. We do want Round to Nearest. We
5035 // don't want non-IEEE rounding modes or floating-point traps.
5036 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5037 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5038 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5039 eor(tmp2, tmp1, tmp2);
5040 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5041 set_fpcr(tmp1);
5042 bind(OK);
5043 }
5044 }
5045
5046 // ((OopHandle)result).resolve();
5047 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5048 // OopHandle::resolve is an indirection.
5049 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5050 }
5051
5052 // ((WeakHandle)result).resolve();
5053 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5054 assert_different_registers(result, tmp1, tmp2);
5055 Label resolved;
5056
5057 // A null weak handle resolves to null.
5058 cbz(result, resolved);
5059
5060 // Only 64 bit platforms support GCs that require a tmp register
5061 // WeakHandle::resolve is an indirection like jweak.
5062 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5063 result, Address(result), tmp1, tmp2);
5064 bind(resolved);
5065 }
5066
5067 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5068 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5069 ldr(dst, Address(rmethod, Method::const_offset()));
5070 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5071 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5072 ldr(dst, Address(dst, mirror_offset));
5073 resolve_oop_handle(dst, tmp1, tmp2);
5074 }
5075
5076 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5077 assert_different_registers(obj, klass, tmp);
5078 if (UseCompressedClassPointers) {
5079 if (UseCompactObjectHeaders) {
5080 load_narrow_klass_compact(tmp, obj);
5081 } else {
5082 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5083 }
5084 if (CompressedKlassPointers::base() == nullptr) {
5085 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5086 return;
5087 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5088 && CompressedKlassPointers::shift() == 0) {
5089 // Only the bottom 32 bits matter
5090 cmpw(klass, tmp);
5091 return;
5092 }
5093 decode_klass_not_null(tmp);
5094 } else {
5095 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5096 }
5097 cmp(klass, tmp);
5098 }
5099
5100 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5101 if (UseCompactObjectHeaders) {
5102 load_narrow_klass_compact(tmp1, obj1);
5103 load_narrow_klass_compact(tmp2, obj2);
5104 cmpw(tmp1, tmp2);
5105 } else if (UseCompressedClassPointers) {
5106 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5107 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5108 cmpw(tmp1, tmp2);
5109 } else {
5110 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5111 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5112 cmp(tmp1, tmp2);
5113 }
5114 }
5115
5116 void MacroAssembler::store_klass(Register dst, Register src) {
5117 // FIXME: Should this be a store release? concurrent gcs assumes
5118 // klass length is valid if klass field is not null.
5119 assert(!UseCompactObjectHeaders, "not with compact headers");
5120 if (UseCompressedClassPointers) {
5121 encode_klass_not_null(src);
5122 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5123 } else {
5124 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5125 }
5126 }
5127
5128 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5129 assert(!UseCompactObjectHeaders, "not with compact headers");
5130 if (UseCompressedClassPointers) {
5131 // Store to klass gap in destination
5132 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5133 }
5134 }
5135
5136 // Algorithm must match CompressedOops::encode.
5137 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5138 #ifdef ASSERT
5139 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5140 #endif
5141 verify_oop_msg(s, "broken oop in encode_heap_oop");
5142 if (CompressedOops::base() == nullptr) {
5143 if (CompressedOops::shift() != 0) {
5144 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5145 lsr(d, s, LogMinObjAlignmentInBytes);
5146 } else {
5147 mov(d, s);
5148 }
5149 } else {
5150 subs(d, s, rheapbase);
5151 csel(d, d, zr, Assembler::HS);
5152 lsr(d, d, LogMinObjAlignmentInBytes);
5153
5154 /* Old algorithm: is this any worse?
5155 Label nonnull;
5156 cbnz(r, nonnull);
5157 sub(r, r, rheapbase);
5158 bind(nonnull);
5159 lsr(r, r, LogMinObjAlignmentInBytes);
5160 */
5161 }
5162 }
5163
5164 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5165 #ifdef ASSERT
5166 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5167 if (CheckCompressedOops) {
5168 Label ok;
5169 cbnz(r, ok);
5170 stop("null oop passed to encode_heap_oop_not_null");
5171 bind(ok);
5172 }
5173 #endif
5174 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5175 if (CompressedOops::base() != nullptr) {
5176 sub(r, r, rheapbase);
5177 }
5178 if (CompressedOops::shift() != 0) {
5179 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5180 lsr(r, r, LogMinObjAlignmentInBytes);
5181 }
5182 }
5183
5184 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5185 #ifdef ASSERT
5186 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5187 if (CheckCompressedOops) {
5188 Label ok;
5189 cbnz(src, ok);
5190 stop("null oop passed to encode_heap_oop_not_null2");
5191 bind(ok);
5192 }
5193 #endif
5194 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5195
5196 Register data = src;
5197 if (CompressedOops::base() != nullptr) {
5198 sub(dst, src, rheapbase);
5199 data = dst;
5200 }
5201 if (CompressedOops::shift() != 0) {
5202 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5203 lsr(dst, data, LogMinObjAlignmentInBytes);
5204 data = dst;
5205 }
5206 if (data == src)
5207 mov(dst, src);
5208 }
5209
5210 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5211 #ifdef ASSERT
5212 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5213 #endif
5214 if (CompressedOops::base() == nullptr) {
5215 if (CompressedOops::shift() != 0) {
5216 lsl(d, s, CompressedOops::shift());
5217 } else if (d != s) {
5218 mov(d, s);
5219 }
5220 } else {
5221 Label done;
5222 if (d != s)
5223 mov(d, s);
5224 cbz(s, done);
5225 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5226 bind(done);
5227 }
5228 verify_oop_msg(d, "broken oop in decode_heap_oop");
5229 }
5230
5231 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5232 assert (UseCompressedOops, "should only be used for compressed headers");
5233 assert (Universe::heap() != nullptr, "java heap should be initialized");
5234 // Cannot assert, unverified entry point counts instructions (see .ad file)
5235 // vtableStubs also counts instructions in pd_code_size_limit.
5236 // Also do not verify_oop as this is called by verify_oop.
5237 if (CompressedOops::shift() != 0) {
5238 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5239 if (CompressedOops::base() != nullptr) {
5240 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5241 } else {
5242 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5243 }
5244 } else {
5245 assert (CompressedOops::base() == nullptr, "sanity");
5246 }
5247 }
5248
5249 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5250 assert (UseCompressedOops, "should only be used for compressed headers");
5251 assert (Universe::heap() != nullptr, "java heap should be initialized");
5252 // Cannot assert, unverified entry point counts instructions (see .ad file)
5253 // vtableStubs also counts instructions in pd_code_size_limit.
5254 // Also do not verify_oop as this is called by verify_oop.
5255 if (CompressedOops::shift() != 0) {
5256 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5257 if (CompressedOops::base() != nullptr) {
5258 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5259 } else {
5260 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5261 }
5262 } else {
5263 assert (CompressedOops::base() == nullptr, "sanity");
5264 if (dst != src) {
5265 mov(dst, src);
5266 }
5267 }
5268 }
5269
5270 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5271
5272 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5273 assert(Metaspace::initialized(), "metaspace not initialized yet");
5274 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5275 return _klass_decode_mode;
5276 }
5277
5278 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5279 assert(UseCompressedClassPointers, "not using compressed class pointers");
5280
5281 // KlassDecodeMode shouldn't be set already.
5282 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5283
5284 if (base == nullptr) {
5285 return KlassDecodeZero;
5286 }
5287
5288 if (operand_valid_for_logical_immediate(
5289 /*is32*/false, (uint64_t)base)) {
5290 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5291 if (((uint64_t)base & range_mask) == 0) {
5292 return KlassDecodeXor;
5293 }
5294 }
5295
5296 const uint64_t shifted_base =
5297 (uint64_t)base >> shift;
5298 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5299 return KlassDecodeMovk;
5300 }
5301
5302 // No valid encoding.
5303 return KlassDecodeNone;
5304 }
5305
5306 // Check if one of the above decoding modes will work for given base, shift and range.
5307 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5308 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5309 }
5310
5311 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5312 _klass_decode_mode = klass_decode_mode(base, shift, range);
5313 return _klass_decode_mode != KlassDecodeNone;
5314 }
5315
5316 static Register pick_different_tmp(Register dst, Register src) {
5317 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5318 return *tmps.begin();
5319 }
5320
5321 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5322 // we have to load the klass base from the AOT constants area but
5323 // not the shift because it is not allowed to change
5324 int shift = CompressedKlassPointers::shift();
5325 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5326 if (dst != src) {
5327 // we can load the base into dst, subtract it formthe src and shift down
5328 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5329 ldr(dst, dst);
5330 sub(dst, src, dst);
5331 lsr(dst, dst, shift);
5332 } else {
5333 // we need an extra register in order to load the coop base
5334 Register tmp = pick_different_tmp(dst, src);
5335 RegSet regs = RegSet::of(tmp);
5336 push(regs, sp);
5337 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5338 ldr(tmp, tmp);
5339 sub(dst, src, tmp);
5340 lsr(dst, dst, shift);
5341 pop(regs, sp);
5342 }
5343 }
5344
5345 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5346 if (AOTCodeCache::is_on_for_dump()) {
5347 encode_klass_not_null_for_aot(dst, src);
5348 return;
5349 }
5350
5351 switch (klass_decode_mode()) {
5352 case KlassDecodeZero:
5353 if (CompressedKlassPointers::shift() != 0) {
5354 lsr(dst, src, CompressedKlassPointers::shift());
5355 } else {
5356 if (dst != src) mov(dst, src);
5357 }
5358 break;
5359
5360 case KlassDecodeXor:
5361 if (CompressedKlassPointers::shift() != 0) {
5362 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5363 lsr(dst, dst, CompressedKlassPointers::shift());
5364 } else {
5365 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5366 }
5367 break;
5368
5369 case KlassDecodeMovk:
5370 if (CompressedKlassPointers::shift() != 0) {
5371 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5372 } else {
5373 movw(dst, src);
5374 }
5375 break;
5376
5377 case KlassDecodeNone:
5378 ShouldNotReachHere();
5379 break;
5380 }
5381 }
5382
5383 void MacroAssembler::encode_klass_not_null(Register r) {
5384 encode_klass_not_null(r, r);
5385 }
5386
5387 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5388 // we have to load the klass base from the AOT constants area but
5389 // not the shift because it is not allowed to change
5390 int shift = CompressedKlassPointers::shift();
5391 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5392 if (dst != src) {
5393 // we can load the base into dst then add the offset with a suitable shift
5394 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5395 ldr(dst, dst);
5396 add(dst, dst, src, LSL, shift);
5397 } else {
5398 // we need an extra register in order to load the coop base
5399 Register tmp = pick_different_tmp(dst, src);
5400 RegSet regs = RegSet::of(tmp);
5401 push(regs, sp);
5402 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5403 ldr(tmp, tmp);
5404 add(dst, tmp, src, LSL, shift);
5405 pop(regs, sp);
5406 }
5407 }
5408
5409 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5410 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5411
5412 if (AOTCodeCache::is_on_for_dump()) {
5413 decode_klass_not_null_for_aot(dst, src);
5414 return;
5415 }
5416
5417 switch (klass_decode_mode()) {
5418 case KlassDecodeZero:
5419 if (CompressedKlassPointers::shift() != 0) {
5420 lsl(dst, src, CompressedKlassPointers::shift());
5421 } else {
5422 if (dst != src) mov(dst, src);
5423 }
5424 break;
5425
5426 case KlassDecodeXor:
5427 if (CompressedKlassPointers::shift() != 0) {
5428 lsl(dst, src, CompressedKlassPointers::shift());
5429 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5430 } else {
5431 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5432 }
5433 break;
5434
5435 case KlassDecodeMovk: {
5436 const uint64_t shifted_base =
5437 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5438
5439 if (dst != src) movw(dst, src);
5440 movk(dst, shifted_base >> 32, 32);
5441
5442 if (CompressedKlassPointers::shift() != 0) {
5443 lsl(dst, dst, CompressedKlassPointers::shift());
5444 }
5445
5446 break;
5447 }
5448
5449 case KlassDecodeNone:
5450 ShouldNotReachHere();
5451 break;
5452 }
5453 }
5454
5455 void MacroAssembler::decode_klass_not_null(Register r) {
5456 decode_klass_not_null(r, r);
5457 }
5458
5459 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5460 #ifdef ASSERT
5461 {
5462 ThreadInVMfromUnknown tiv;
5463 assert (UseCompressedOops, "should only be used for compressed oops");
5464 assert (Universe::heap() != nullptr, "java heap should be initialized");
5465 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5466 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5467 }
5468 #endif
5469 int oop_index = oop_recorder()->find_index(obj);
5470 InstructionMark im(this);
5471 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5472 code_section()->relocate(inst_mark(), rspec);
5473 movz(dst, 0xDEAD, 16);
5474 movk(dst, 0xBEEF);
5475 }
5476
5477 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5478 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5479 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5480 int index = oop_recorder()->find_index(k);
5481 assert(! Universe::heap()->is_in(k), "should not be an oop");
5482
5483 InstructionMark im(this);
5484 RelocationHolder rspec = metadata_Relocation::spec(index);
5485 code_section()->relocate(inst_mark(), rspec);
5486 narrowKlass nk = CompressedKlassPointers::encode(k);
5487 movz(dst, (nk >> 16), 16);
5488 movk(dst, nk & 0xffff);
5489 }
5490
5491 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5492 Register dst, Address src,
5493 Register tmp1, Register tmp2) {
5494 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5495 decorators = AccessInternal::decorator_fixup(decorators, type);
5496 bool as_raw = (decorators & AS_RAW) != 0;
5497 if (as_raw) {
5498 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5499 } else {
5500 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5501 }
5502 }
5503
5504 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5505 Address dst, Register val,
5506 Register tmp1, Register tmp2, Register tmp3) {
5507 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5508 decorators = AccessInternal::decorator_fixup(decorators, type);
5509 bool as_raw = (decorators & AS_RAW) != 0;
5510 if (as_raw) {
5511 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5512 } else {
5513 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5514 }
5515 }
5516
5517 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5518 Register tmp2, DecoratorSet decorators) {
5519 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5520 }
5521
5522 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5523 Register tmp2, DecoratorSet decorators) {
5524 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5525 }
5526
5527 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5528 Register tmp2, Register tmp3, DecoratorSet decorators) {
5529 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5530 }
5531
5532 // Used for storing nulls.
5533 void MacroAssembler::store_heap_oop_null(Address dst) {
5534 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5535 }
5536
5537 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5538 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5539 int index = oop_recorder()->allocate_metadata_index(obj);
5540 RelocationHolder rspec = metadata_Relocation::spec(index);
5541 return Address((address)obj, rspec);
5542 }
5543
5544 // Move an oop into a register.
5545 void MacroAssembler::movoop(Register dst, jobject obj) {
5546 int oop_index;
5547 if (obj == nullptr) {
5548 oop_index = oop_recorder()->allocate_oop_index(obj);
5549 } else {
5550 #ifdef ASSERT
5551 {
5552 ThreadInVMfromUnknown tiv;
5553 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5554 }
5555 #endif
5556 oop_index = oop_recorder()->find_index(obj);
5557 }
5558 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5559
5560 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5561 mov(dst, Address((address)obj, rspec));
5562 } else {
5563 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5564 ldr(dst, Address(dummy, rspec));
5565 }
5566 }
5567
5568 // Move a metadata address into a register.
5569 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5570 int oop_index;
5571 if (obj == nullptr) {
5572 oop_index = oop_recorder()->allocate_metadata_index(obj);
5573 } else {
5574 oop_index = oop_recorder()->find_index(obj);
5575 }
5576 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5577 mov(dst, Address((address)obj, rspec));
5578 }
5579
5580 Address MacroAssembler::constant_oop_address(jobject obj) {
5581 #ifdef ASSERT
5582 {
5583 ThreadInVMfromUnknown tiv;
5584 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5585 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5586 }
5587 #endif
5588 int oop_index = oop_recorder()->find_index(obj);
5589 return Address((address)obj, oop_Relocation::spec(oop_index));
5590 }
5591
5592 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5593 void MacroAssembler::tlab_allocate(Register obj,
5594 Register var_size_in_bytes,
5595 int con_size_in_bytes,
5596 Register t1,
5597 Register t2,
5598 Label& slow_case) {
5599 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5600 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5601 }
5602
5603 void MacroAssembler::verify_tlab() {
5604 #ifdef ASSERT
5605 if (UseTLAB && VerifyOops) {
5606 Label next, ok;
5607
5608 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5609
5610 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5611 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5612 cmp(rscratch2, rscratch1);
5613 br(Assembler::HS, next);
5614 STOP("assert(top >= start)");
5615 should_not_reach_here();
5616
5617 bind(next);
5618 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5619 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5620 cmp(rscratch2, rscratch1);
5621 br(Assembler::HS, ok);
5622 STOP("assert(top <= end)");
5623 should_not_reach_here();
5624
5625 bind(ok);
5626 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5627 }
5628 #endif
5629 }
5630
5631 // Writes to stack successive pages until offset reached to check for
5632 // stack overflow + shadow pages. This clobbers tmp.
5633 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5634 assert_different_registers(tmp, size, rscratch1);
5635 mov(tmp, sp);
5636 // Bang stack for total size given plus shadow page size.
5637 // Bang one page at a time because large size can bang beyond yellow and
5638 // red zones.
5639 Label loop;
5640 mov(rscratch1, (int)os::vm_page_size());
5641 bind(loop);
5642 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5643 subsw(size, size, rscratch1);
5644 str(size, Address(tmp));
5645 br(Assembler::GT, loop);
5646
5647 // Bang down shadow pages too.
5648 // At this point, (tmp-0) is the last address touched, so don't
5649 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5650 // was post-decremented.) Skip this address by starting at i=1, and
5651 // touch a few more pages below. N.B. It is important to touch all
5652 // the way down to and including i=StackShadowPages.
5653 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5654 // this could be any sized move but this is can be a debugging crumb
5655 // so the bigger the better.
5656 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5657 str(size, Address(tmp));
5658 }
5659 }
5660
5661 // Move the address of the polling page into dest.
5662 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5663 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5664 }
5665
5666 // Read the polling page. The address of the polling page must
5667 // already be in r.
5668 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5669 address mark;
5670 {
5671 InstructionMark im(this);
5672 code_section()->relocate(inst_mark(), rtype);
5673 ldrw(zr, Address(r, 0));
5674 mark = inst_mark();
5675 }
5676 verify_cross_modify_fence_not_required();
5677 return mark;
5678 }
5679
5680 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5681 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5682 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5683 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5684 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5685 int64_t offset_low = dest_page - low_page;
5686 int64_t offset_high = dest_page - high_page;
5687
5688 assert(is_valid_AArch64_address(dest.target()), "bad address");
5689 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5690
5691 InstructionMark im(this);
5692 code_section()->relocate(inst_mark(), dest.rspec());
5693 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5694 // the code cache so that if it is relocated we know it will still reach
5695 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5696 _adrp(reg1, dest.target());
5697 } else {
5698 uint64_t target = (uint64_t)dest.target();
5699 uint64_t adrp_target
5700 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5701
5702 _adrp(reg1, (address)adrp_target);
5703 movk(reg1, target >> 32, 32);
5704 }
5705 byte_offset = (uint64_t)dest.target() & 0xfff;
5706 }
5707
5708 void MacroAssembler::load_byte_map_base(Register reg) {
5709 CardTable::CardValue* byte_map_base =
5710 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5711
5712 // Strictly speaking the byte_map_base isn't an address at all, and it might
5713 // even be negative. It is thus materialised as a constant.
5714 mov(reg, (uint64_t)byte_map_base);
5715 }
5716
5717 void MacroAssembler::build_frame(int framesize) {
5718 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5719 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5720 protect_return_address();
5721 if (framesize < ((1 << 9) + 2 * wordSize)) {
5722 sub(sp, sp, framesize);
5723 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5724 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5725 } else {
5726 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5727 if (PreserveFramePointer) mov(rfp, sp);
5728 if (framesize < ((1 << 12) + 2 * wordSize))
5729 sub(sp, sp, framesize - 2 * wordSize);
5730 else {
5731 mov(rscratch1, framesize - 2 * wordSize);
5732 sub(sp, sp, rscratch1);
5733 }
5734 }
5735 verify_cross_modify_fence_not_required();
5736 }
5737
5738 void MacroAssembler::remove_frame(int framesize) {
5739 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5740 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5741 if (framesize < ((1 << 9) + 2 * wordSize)) {
5742 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5743 add(sp, sp, framesize);
5744 } else {
5745 if (framesize < ((1 << 12) + 2 * wordSize))
5746 add(sp, sp, framesize - 2 * wordSize);
5747 else {
5748 mov(rscratch1, framesize - 2 * wordSize);
5749 add(sp, sp, rscratch1);
5750 }
5751 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5752 }
5753 authenticate_return_address();
5754 }
5755
5756
5757 // This method counts leading positive bytes (highest bit not set) in provided byte array
5758 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5759 // Simple and most common case of aligned small array which is not at the
5760 // end of memory page is placed here. All other cases are in stub.
5761 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5762 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5763 assert_different_registers(ary1, len, result);
5764
5765 mov(result, len);
5766 cmpw(len, 0);
5767 br(LE, DONE);
5768 cmpw(len, 4 * wordSize);
5769 br(GE, STUB_LONG); // size > 32 then go to stub
5770
5771 int shift = 64 - exact_log2(os::vm_page_size());
5772 lsl(rscratch1, ary1, shift);
5773 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5774 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5775 br(CS, STUB); // at the end of page then go to stub
5776 subs(len, len, wordSize);
5777 br(LT, END);
5778
5779 BIND(LOOP);
5780 ldr(rscratch1, Address(post(ary1, wordSize)));
5781 tst(rscratch1, UPPER_BIT_MASK);
5782 br(NE, SET_RESULT);
5783 subs(len, len, wordSize);
5784 br(GE, LOOP);
5785 cmpw(len, -wordSize);
5786 br(EQ, DONE);
5787
5788 BIND(END);
5789 ldr(rscratch1, Address(ary1));
5790 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5791 lslv(rscratch1, rscratch1, rscratch2);
5792 tst(rscratch1, UPPER_BIT_MASK);
5793 br(NE, SET_RESULT);
5794 b(DONE);
5795
5796 BIND(STUB);
5797 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5798 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5799 address tpc1 = trampoline_call(count_pos);
5800 if (tpc1 == nullptr) {
5801 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5802 postcond(pc() == badAddress);
5803 return nullptr;
5804 }
5805 b(DONE);
5806
5807 BIND(STUB_LONG);
5808 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5809 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5810 address tpc2 = trampoline_call(count_pos_long);
5811 if (tpc2 == nullptr) {
5812 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5813 postcond(pc() == badAddress);
5814 return nullptr;
5815 }
5816 b(DONE);
5817
5818 BIND(SET_RESULT);
5819
5820 add(len, len, wordSize);
5821 sub(result, result, len);
5822
5823 BIND(DONE);
5824 postcond(pc() != badAddress);
5825 return pc();
5826 }
5827
5828 // Clobbers: rscratch1, rscratch2, rflags
5829 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5830 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5831 Register tmp4, Register tmp5, Register result,
5832 Register cnt1, int elem_size) {
5833 Label DONE, SAME;
5834 Register tmp1 = rscratch1;
5835 Register tmp2 = rscratch2;
5836 int elem_per_word = wordSize/elem_size;
5837 int log_elem_size = exact_log2(elem_size);
5838 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5839 int length_offset = arrayOopDesc::length_offset_in_bytes();
5840 int base_offset
5841 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5842 // When the length offset is not aligned to 8 bytes,
5843 // then we align it down. This is valid because the new
5844 // offset will always be the klass which is the same
5845 // for type arrays.
5846 int start_offset = align_down(length_offset, BytesPerWord);
5847 int extra_length = base_offset - start_offset;
5848 assert(start_offset == length_offset || start_offset == klass_offset,
5849 "start offset must be 8-byte-aligned or be the klass offset");
5850 assert(base_offset != start_offset, "must include the length field");
5851 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5852 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5853
5854 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5855 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5856
5857 #ifndef PRODUCT
5858 {
5859 const char kind = (elem_size == 2) ? 'U' : 'L';
5860 char comment[64];
5861 os::snprintf_checked(comment, sizeof comment, "array_equals%c{", kind);
5862 BLOCK_COMMENT(comment);
5863 }
5864 #endif
5865
5866 // if (a1 == a2)
5867 // return true;
5868 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5869 br(EQ, SAME);
5870
5871 if (UseSimpleArrayEquals) {
5872 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5873 // if (a1 == nullptr || a2 == nullptr)
5874 // return false;
5875 // a1 & a2 == 0 means (some-pointer is null) or
5876 // (very-rare-or-even-probably-impossible-pointer-values)
5877 // so, we can save one branch in most cases
5878 tst(a1, a2);
5879 mov(result, false);
5880 br(EQ, A_MIGHT_BE_NULL);
5881 // if (a1.length != a2.length)
5882 // return false;
5883 bind(A_IS_NOT_NULL);
5884 ldrw(cnt1, Address(a1, length_offset));
5885 // Increase loop counter by diff between base- and actual start-offset.
5886 addw(cnt1, cnt1, extra_length);
5887 lea(a1, Address(a1, start_offset));
5888 lea(a2, Address(a2, start_offset));
5889 // Check for short strings, i.e. smaller than wordSize.
5890 subs(cnt1, cnt1, elem_per_word);
5891 br(Assembler::LT, SHORT);
5892 // Main 8 byte comparison loop.
5893 bind(NEXT_WORD); {
5894 ldr(tmp1, Address(post(a1, wordSize)));
5895 ldr(tmp2, Address(post(a2, wordSize)));
5896 subs(cnt1, cnt1, elem_per_word);
5897 eor(tmp5, tmp1, tmp2);
5898 cbnz(tmp5, DONE);
5899 } br(GT, NEXT_WORD);
5900 // Last longword. In the case where length == 4 we compare the
5901 // same longword twice, but that's still faster than another
5902 // conditional branch.
5903 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5904 // length == 4.
5905 if (log_elem_size > 0)
5906 lsl(cnt1, cnt1, log_elem_size);
5907 ldr(tmp3, Address(a1, cnt1));
5908 ldr(tmp4, Address(a2, cnt1));
5909 eor(tmp5, tmp3, tmp4);
5910 cbnz(tmp5, DONE);
5911 b(SAME);
5912 bind(A_MIGHT_BE_NULL);
5913 // in case both a1 and a2 are not-null, proceed with loads
5914 cbz(a1, DONE);
5915 cbz(a2, DONE);
5916 b(A_IS_NOT_NULL);
5917 bind(SHORT);
5918
5919 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5920 {
5921 ldrw(tmp1, Address(post(a1, 4)));
5922 ldrw(tmp2, Address(post(a2, 4)));
5923 eorw(tmp5, tmp1, tmp2);
5924 cbnzw(tmp5, DONE);
5925 }
5926 bind(TAIL03);
5927 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5928 {
5929 ldrh(tmp3, Address(post(a1, 2)));
5930 ldrh(tmp4, Address(post(a2, 2)));
5931 eorw(tmp5, tmp3, tmp4);
5932 cbnzw(tmp5, DONE);
5933 }
5934 bind(TAIL01);
5935 if (elem_size == 1) { // Only needed when comparing byte arrays.
5936 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5937 {
5938 ldrb(tmp1, a1);
5939 ldrb(tmp2, a2);
5940 eorw(tmp5, tmp1, tmp2);
5941 cbnzw(tmp5, DONE);
5942 }
5943 }
5944 } else {
5945 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
5946 CSET_EQ, LAST_CHECK;
5947 mov(result, false);
5948 cbz(a1, DONE);
5949 ldrw(cnt1, Address(a1, length_offset));
5950 cbz(a2, DONE);
5951 // Increase loop counter by diff between base- and actual start-offset.
5952 addw(cnt1, cnt1, extra_length);
5953
5954 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
5955 // faster to perform another branch before comparing a1 and a2
5956 cmp(cnt1, (u1)elem_per_word);
5957 br(LE, SHORT); // short or same
5958 ldr(tmp3, Address(pre(a1, start_offset)));
5959 subs(zr, cnt1, stubBytesThreshold);
5960 br(GE, STUB);
5961 ldr(tmp4, Address(pre(a2, start_offset)));
5962 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
5963
5964 // Main 16 byte comparison loop with 2 exits
5965 bind(NEXT_DWORD); {
5966 ldr(tmp1, Address(pre(a1, wordSize)));
5967 ldr(tmp2, Address(pre(a2, wordSize)));
5968 subs(cnt1, cnt1, 2 * elem_per_word);
5969 br(LE, TAIL);
5970 eor(tmp4, tmp3, tmp4);
5971 cbnz(tmp4, DONE);
5972 ldr(tmp3, Address(pre(a1, wordSize)));
5973 ldr(tmp4, Address(pre(a2, wordSize)));
5974 cmp(cnt1, (u1)elem_per_word);
5975 br(LE, TAIL2);
5976 cmp(tmp1, tmp2);
5977 } br(EQ, NEXT_DWORD);
5978 b(DONE);
5979
5980 bind(TAIL);
5981 eor(tmp4, tmp3, tmp4);
5982 eor(tmp2, tmp1, tmp2);
5983 lslv(tmp2, tmp2, tmp5);
5984 orr(tmp5, tmp4, tmp2);
5985 cmp(tmp5, zr);
5986 b(CSET_EQ);
5987
5988 bind(TAIL2);
5989 eor(tmp2, tmp1, tmp2);
5990 cbnz(tmp2, DONE);
5991 b(LAST_CHECK);
5992
5993 bind(STUB);
5994 ldr(tmp4, Address(pre(a2, start_offset)));
5995 if (elem_size == 2) { // convert to byte counter
5996 lsl(cnt1, cnt1, 1);
5997 }
5998 eor(tmp5, tmp3, tmp4);
5999 cbnz(tmp5, DONE);
6000 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6001 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6002 address tpc = trampoline_call(stub);
6003 if (tpc == nullptr) {
6004 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6005 postcond(pc() == badAddress);
6006 return nullptr;
6007 }
6008 b(DONE);
6009
6010 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6011 // so, if a2 == null => return false(0), else return true, so we can return a2
6012 mov(result, a2);
6013 b(DONE);
6014 bind(SHORT);
6015 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6016 ldr(tmp3, Address(a1, start_offset));
6017 ldr(tmp4, Address(a2, start_offset));
6018 bind(LAST_CHECK);
6019 eor(tmp4, tmp3, tmp4);
6020 lslv(tmp5, tmp4, tmp5);
6021 cmp(tmp5, zr);
6022 bind(CSET_EQ);
6023 cset(result, EQ);
6024 b(DONE);
6025 }
6026
6027 bind(SAME);
6028 mov(result, true);
6029 // That's it.
6030 bind(DONE);
6031
6032 BLOCK_COMMENT("} array_equals");
6033 postcond(pc() != badAddress);
6034 return pc();
6035 }
6036
6037 // Compare Strings
6038
6039 // For Strings we're passed the address of the first characters in a1
6040 // and a2 and the length in cnt1.
6041 // There are two implementations. For arrays >= 8 bytes, all
6042 // comparisons (including the final one, which may overlap) are
6043 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6044 // halfword, then a short, and then a byte.
6045
6046 void MacroAssembler::string_equals(Register a1, Register a2,
6047 Register result, Register cnt1)
6048 {
6049 Label SAME, DONE, SHORT, NEXT_WORD;
6050 Register tmp1 = rscratch1;
6051 Register tmp2 = rscratch2;
6052 Register cnt2 = tmp2; // cnt2 only used in array length compare
6053
6054 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6055
6056 #ifndef PRODUCT
6057 {
6058 char comment[64];
6059 os::snprintf_checked(comment, sizeof comment, "{string_equalsL");
6060 BLOCK_COMMENT(comment);
6061 }
6062 #endif
6063
6064 mov(result, false);
6065
6066 // Check for short strings, i.e. smaller than wordSize.
6067 subs(cnt1, cnt1, wordSize);
6068 br(Assembler::LT, SHORT);
6069 // Main 8 byte comparison loop.
6070 bind(NEXT_WORD); {
6071 ldr(tmp1, Address(post(a1, wordSize)));
6072 ldr(tmp2, Address(post(a2, wordSize)));
6073 subs(cnt1, cnt1, wordSize);
6074 eor(tmp1, tmp1, tmp2);
6075 cbnz(tmp1, DONE);
6076 } br(GT, NEXT_WORD);
6077 // Last longword. In the case where length == 4 we compare the
6078 // same longword twice, but that's still faster than another
6079 // conditional branch.
6080 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6081 // length == 4.
6082 ldr(tmp1, Address(a1, cnt1));
6083 ldr(tmp2, Address(a2, cnt1));
6084 eor(tmp2, tmp1, tmp2);
6085 cbnz(tmp2, DONE);
6086 b(SAME);
6087
6088 bind(SHORT);
6089 Label TAIL03, TAIL01;
6090
6091 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6092 {
6093 ldrw(tmp1, Address(post(a1, 4)));
6094 ldrw(tmp2, Address(post(a2, 4)));
6095 eorw(tmp1, tmp1, tmp2);
6096 cbnzw(tmp1, DONE);
6097 }
6098 bind(TAIL03);
6099 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6100 {
6101 ldrh(tmp1, Address(post(a1, 2)));
6102 ldrh(tmp2, Address(post(a2, 2)));
6103 eorw(tmp1, tmp1, tmp2);
6104 cbnzw(tmp1, DONE);
6105 }
6106 bind(TAIL01);
6107 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6108 {
6109 ldrb(tmp1, a1);
6110 ldrb(tmp2, a2);
6111 eorw(tmp1, tmp1, tmp2);
6112 cbnzw(tmp1, DONE);
6113 }
6114 // Arrays are equal.
6115 bind(SAME);
6116 mov(result, true);
6117
6118 // That's it.
6119 bind(DONE);
6120 BLOCK_COMMENT("} string_equals");
6121 }
6122
6123
6124 // The size of the blocks erased by the zero_blocks stub. We must
6125 // handle anything smaller than this ourselves in zero_words().
6126 const int MacroAssembler::zero_words_block_size = 8;
6127
6128 // zero_words() is used by C2 ClearArray patterns and by
6129 // C1_MacroAssembler. It is as small as possible, handling small word
6130 // counts locally and delegating anything larger to the zero_blocks
6131 // stub. It is expanded many times in compiled code, so it is
6132 // important to keep it short.
6133
6134 // ptr: Address of a buffer to be zeroed.
6135 // cnt: Count in HeapWords.
6136 //
6137 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6138 address MacroAssembler::zero_words(Register ptr, Register cnt)
6139 {
6140 assert(is_power_of_2(zero_words_block_size), "adjust this");
6141
6142 BLOCK_COMMENT("zero_words {");
6143 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6144 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6145 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6146
6147 subs(rscratch1, cnt, zero_words_block_size);
6148 Label around;
6149 br(LO, around);
6150 {
6151 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6152 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6153 // Make sure this is a C2 compilation. C1 allocates space only for
6154 // trampoline stubs generated by Call LIR ops, and in any case it
6155 // makes sense for a C1 compilation task to proceed as quickly as
6156 // possible.
6157 CompileTask* task;
6158 if (StubRoutines::aarch64::complete()
6159 && Thread::current()->is_Compiler_thread()
6160 && (task = ciEnv::current()->task())
6161 && is_c2_compile(task->comp_level())) {
6162 address tpc = trampoline_call(zero_blocks);
6163 if (tpc == nullptr) {
6164 DEBUG_ONLY(reset_labels(around));
6165 return nullptr;
6166 }
6167 } else {
6168 far_call(zero_blocks);
6169 }
6170 }
6171 bind(around);
6172
6173 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6174 // for us.
6175 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6176 Label l;
6177 tbz(cnt, exact_log2(i), l);
6178 for (int j = 0; j < i; j += 2) {
6179 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6180 }
6181 bind(l);
6182 }
6183 {
6184 Label l;
6185 tbz(cnt, 0, l);
6186 str(zr, Address(ptr));
6187 bind(l);
6188 }
6189
6190 BLOCK_COMMENT("} zero_words");
6191 return pc();
6192 }
6193
6194 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6195 // cnt: Immediate count in HeapWords.
6196 //
6197 // r10, r11, rscratch1, and rscratch2 are clobbered.
6198 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6199 {
6200 assert(wordSize <= BlockZeroingLowLimit,
6201 "increase BlockZeroingLowLimit");
6202 address result = nullptr;
6203 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6204 #ifndef PRODUCT
6205 {
6206 char buf[64];
6207 os::snprintf_checked(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6208 BLOCK_COMMENT(buf);
6209 }
6210 #endif
6211 if (cnt >= 16) {
6212 uint64_t loops = cnt/16;
6213 if (loops > 1) {
6214 mov(rscratch2, loops - 1);
6215 }
6216 {
6217 Label loop;
6218 bind(loop);
6219 for (int i = 0; i < 16; i += 2) {
6220 stp(zr, zr, Address(base, i * BytesPerWord));
6221 }
6222 add(base, base, 16 * BytesPerWord);
6223 if (loops > 1) {
6224 subs(rscratch2, rscratch2, 1);
6225 br(GE, loop);
6226 }
6227 }
6228 }
6229 cnt %= 16;
6230 int i = cnt & 1; // store any odd word to start
6231 if (i) str(zr, Address(base));
6232 for (; i < (int)cnt; i += 2) {
6233 stp(zr, zr, Address(base, i * wordSize));
6234 }
6235 BLOCK_COMMENT("} zero_words");
6236 result = pc();
6237 } else {
6238 mov(r10, base); mov(r11, cnt);
6239 result = zero_words(r10, r11);
6240 }
6241 return result;
6242 }
6243
6244 // Zero blocks of memory by using DC ZVA.
6245 //
6246 // Aligns the base address first sufficiently for DC ZVA, then uses
6247 // DC ZVA repeatedly for every full block. cnt is the size to be
6248 // zeroed in HeapWords. Returns the count of words left to be zeroed
6249 // in cnt.
6250 //
6251 // NOTE: This is intended to be used in the zero_blocks() stub. If
6252 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6253 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6254 Register tmp = rscratch1;
6255 Register tmp2 = rscratch2;
6256 int zva_length = VM_Version::zva_length();
6257 Label initial_table_end, loop_zva;
6258 Label fini;
6259
6260 // Base must be 16 byte aligned. If not just return and let caller handle it
6261 tst(base, 0x0f);
6262 br(Assembler::NE, fini);
6263 // Align base with ZVA length.
6264 neg(tmp, base);
6265 andr(tmp, tmp, zva_length - 1);
6266
6267 // tmp: the number of bytes to be filled to align the base with ZVA length.
6268 add(base, base, tmp);
6269 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6270 adr(tmp2, initial_table_end);
6271 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6272 br(tmp2);
6273
6274 for (int i = -zva_length + 16; i < 0; i += 16)
6275 stp(zr, zr, Address(base, i));
6276 bind(initial_table_end);
6277
6278 sub(cnt, cnt, zva_length >> 3);
6279 bind(loop_zva);
6280 dc(Assembler::ZVA, base);
6281 subs(cnt, cnt, zva_length >> 3);
6282 add(base, base, zva_length);
6283 br(Assembler::GE, loop_zva);
6284 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6285 bind(fini);
6286 }
6287
6288 // base: Address of a buffer to be filled, 8 bytes aligned.
6289 // cnt: Count in 8-byte unit.
6290 // value: Value to be filled with.
6291 // base will point to the end of the buffer after filling.
6292 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6293 {
6294 // Algorithm:
6295 //
6296 // if (cnt == 0) {
6297 // return;
6298 // }
6299 // if ((p & 8) != 0) {
6300 // *p++ = v;
6301 // }
6302 //
6303 // scratch1 = cnt & 14;
6304 // cnt -= scratch1;
6305 // p += scratch1;
6306 // switch (scratch1 / 2) {
6307 // do {
6308 // cnt -= 16;
6309 // p[-16] = v;
6310 // p[-15] = v;
6311 // case 7:
6312 // p[-14] = v;
6313 // p[-13] = v;
6314 // case 6:
6315 // p[-12] = v;
6316 // p[-11] = v;
6317 // // ...
6318 // case 1:
6319 // p[-2] = v;
6320 // p[-1] = v;
6321 // case 0:
6322 // p += 16;
6323 // } while (cnt);
6324 // }
6325 // if ((cnt & 1) == 1) {
6326 // *p++ = v;
6327 // }
6328
6329 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6330
6331 Label fini, skip, entry, loop;
6332 const int unroll = 8; // Number of stp instructions we'll unroll
6333
6334 cbz(cnt, fini);
6335 tbz(base, 3, skip);
6336 str(value, Address(post(base, 8)));
6337 sub(cnt, cnt, 1);
6338 bind(skip);
6339
6340 andr(rscratch1, cnt, (unroll-1) * 2);
6341 sub(cnt, cnt, rscratch1);
6342 add(base, base, rscratch1, Assembler::LSL, 3);
6343 adr(rscratch2, entry);
6344 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6345 br(rscratch2);
6346
6347 bind(loop);
6348 add(base, base, unroll * 16);
6349 for (int i = -unroll; i < 0; i++)
6350 stp(value, value, Address(base, i * 16));
6351 bind(entry);
6352 subs(cnt, cnt, unroll * 2);
6353 br(Assembler::GE, loop);
6354
6355 tbz(cnt, 0, fini);
6356 str(value, Address(post(base, 8)));
6357 bind(fini);
6358 }
6359
6360 // Intrinsic for
6361 //
6362 // - sun.nio.cs.ISO_8859_1.Encoder#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6363 // Encodes char[] to byte[] in ISO-8859-1
6364 //
6365 // - java.lang.StringCoding#encodeISOArray0(byte[] sa, int sp, byte[] da, int dp, int len)
6366 // Encodes byte[] (containing UTF-16) to byte[] in ISO-8859-1
6367 //
6368 // - java.lang.StringCoding#encodeAsciiArray0(char[] sa, int sp, byte[] da, int dp, int len)
6369 // Encodes char[] to byte[] in ASCII
6370 //
6371 // This version always returns the number of characters copied, and does not
6372 // clobber the 'len' register. A successful copy will complete with the post-
6373 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6374 // post-condition: 0 <= 'res' < 'len'.
6375 //
6376 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6377 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6378 // beyond the acceptable, even though the footprint would be smaller.
6379 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6380 // avoid additional bloat.
6381 //
6382 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6383 void MacroAssembler::encode_iso_array(Register src, Register dst,
6384 Register len, Register res, bool ascii,
6385 FloatRegister vtmp0, FloatRegister vtmp1,
6386 FloatRegister vtmp2, FloatRegister vtmp3,
6387 FloatRegister vtmp4, FloatRegister vtmp5)
6388 {
6389 Register cnt = res;
6390 Register max = rscratch1;
6391 Register chk = rscratch2;
6392
6393 prfm(Address(src), PLDL1STRM);
6394 movw(cnt, len);
6395
6396 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6397
6398 Label LOOP_32, DONE_32, FAIL_32;
6399
6400 BIND(LOOP_32);
6401 {
6402 cmpw(cnt, 32);
6403 br(LT, DONE_32);
6404 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6405 // Extract lower bytes.
6406 FloatRegister vlo0 = vtmp4;
6407 FloatRegister vlo1 = vtmp5;
6408 uzp1(vlo0, T16B, vtmp0, vtmp1);
6409 uzp1(vlo1, T16B, vtmp2, vtmp3);
6410 // Merge bits...
6411 orr(vtmp0, T16B, vtmp0, vtmp1);
6412 orr(vtmp2, T16B, vtmp2, vtmp3);
6413 // Extract merged upper bytes.
6414 FloatRegister vhix = vtmp0;
6415 uzp2(vhix, T16B, vtmp0, vtmp2);
6416 // ISO-check on hi-parts (all zero).
6417 // ASCII-check on lo-parts (no sign).
6418 FloatRegister vlox = vtmp1; // Merge lower bytes.
6419 ASCII(orr(vlox, T16B, vlo0, vlo1));
6420 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6421 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6422 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6423 ASCII(orr(chk, chk, max));
6424 cbnz(chk, FAIL_32);
6425 subw(cnt, cnt, 32);
6426 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6427 b(LOOP_32);
6428 }
6429 BIND(FAIL_32);
6430 sub(src, src, 64);
6431 BIND(DONE_32);
6432
6433 Label LOOP_8, SKIP_8;
6434
6435 BIND(LOOP_8);
6436 {
6437 cmpw(cnt, 8);
6438 br(LT, SKIP_8);
6439 FloatRegister vhi = vtmp0;
6440 FloatRegister vlo = vtmp1;
6441 ld1(vtmp3, T8H, src);
6442 uzp1(vlo, T16B, vtmp3, vtmp3);
6443 uzp2(vhi, T16B, vtmp3, vtmp3);
6444 // ISO-check on hi-parts (all zero).
6445 // ASCII-check on lo-parts (no sign).
6446 ASCII(cm(LT, vtmp2, T16B, vlo));
6447 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6448 ASCII(umov(max, vtmp2, B, 0));
6449 ASCII(orr(chk, chk, max));
6450 cbnz(chk, SKIP_8);
6451
6452 strd(vlo, Address(post(dst, 8)));
6453 subw(cnt, cnt, 8);
6454 add(src, src, 16);
6455 b(LOOP_8);
6456 }
6457 BIND(SKIP_8);
6458
6459 #undef ASCII
6460
6461 Label LOOP, DONE;
6462
6463 cbz(cnt, DONE);
6464 BIND(LOOP);
6465 {
6466 Register chr = rscratch1;
6467 ldrh(chr, Address(post(src, 2)));
6468 tst(chr, ascii ? 0xff80 : 0xff00);
6469 br(NE, DONE);
6470 strb(chr, Address(post(dst, 1)));
6471 subs(cnt, cnt, 1);
6472 br(GT, LOOP);
6473 }
6474 BIND(DONE);
6475 // Return index where we stopped.
6476 subw(res, len, cnt);
6477 }
6478
6479 // Inflate byte[] array to char[].
6480 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6481 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6482 FloatRegister vtmp1, FloatRegister vtmp2,
6483 FloatRegister vtmp3, Register tmp4) {
6484 Label big, done, after_init, to_stub;
6485
6486 assert_different_registers(src, dst, len, tmp4, rscratch1);
6487
6488 fmovd(vtmp1, 0.0);
6489 lsrw(tmp4, len, 3);
6490 bind(after_init);
6491 cbnzw(tmp4, big);
6492 // Short string: less than 8 bytes.
6493 {
6494 Label loop, tiny;
6495
6496 cmpw(len, 4);
6497 br(LT, tiny);
6498 // Use SIMD to do 4 bytes.
6499 ldrs(vtmp2, post(src, 4));
6500 zip1(vtmp3, T8B, vtmp2, vtmp1);
6501 subw(len, len, 4);
6502 strd(vtmp3, post(dst, 8));
6503
6504 cbzw(len, done);
6505
6506 // Do the remaining bytes by steam.
6507 bind(loop);
6508 ldrb(tmp4, post(src, 1));
6509 strh(tmp4, post(dst, 2));
6510 subw(len, len, 1);
6511
6512 bind(tiny);
6513 cbnz(len, loop);
6514
6515 b(done);
6516 }
6517
6518 if (SoftwarePrefetchHintDistance >= 0) {
6519 bind(to_stub);
6520 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6521 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6522 address tpc = trampoline_call(stub);
6523 if (tpc == nullptr) {
6524 DEBUG_ONLY(reset_labels(big, done));
6525 postcond(pc() == badAddress);
6526 return nullptr;
6527 }
6528 b(after_init);
6529 }
6530
6531 // Unpack the bytes 8 at a time.
6532 bind(big);
6533 {
6534 Label loop, around, loop_last, loop_start;
6535
6536 if (SoftwarePrefetchHintDistance >= 0) {
6537 const int large_loop_threshold = (64 + 16)/8;
6538 ldrd(vtmp2, post(src, 8));
6539 andw(len, len, 7);
6540 cmp(tmp4, (u1)large_loop_threshold);
6541 br(GE, to_stub);
6542 b(loop_start);
6543
6544 bind(loop);
6545 ldrd(vtmp2, post(src, 8));
6546 bind(loop_start);
6547 subs(tmp4, tmp4, 1);
6548 br(EQ, loop_last);
6549 zip1(vtmp2, T16B, vtmp2, vtmp1);
6550 ldrd(vtmp3, post(src, 8));
6551 st1(vtmp2, T8H, post(dst, 16));
6552 subs(tmp4, tmp4, 1);
6553 zip1(vtmp3, T16B, vtmp3, vtmp1);
6554 st1(vtmp3, T8H, post(dst, 16));
6555 br(NE, loop);
6556 b(around);
6557 bind(loop_last);
6558 zip1(vtmp2, T16B, vtmp2, vtmp1);
6559 st1(vtmp2, T8H, post(dst, 16));
6560 bind(around);
6561 cbz(len, done);
6562 } else {
6563 andw(len, len, 7);
6564 bind(loop);
6565 ldrd(vtmp2, post(src, 8));
6566 sub(tmp4, tmp4, 1);
6567 zip1(vtmp3, T16B, vtmp2, vtmp1);
6568 st1(vtmp3, T8H, post(dst, 16));
6569 cbnz(tmp4, loop);
6570 }
6571 }
6572
6573 // Do the tail of up to 8 bytes.
6574 add(src, src, len);
6575 ldrd(vtmp3, Address(src, -8));
6576 add(dst, dst, len, ext::uxtw, 1);
6577 zip1(vtmp3, T16B, vtmp3, vtmp1);
6578 strq(vtmp3, Address(dst, -16));
6579
6580 bind(done);
6581 postcond(pc() != badAddress);
6582 return pc();
6583 }
6584
6585 // Compress char[] array to byte[].
6586 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6587 // Return the array length if every element in array can be encoded,
6588 // otherwise, the index of first non-latin1 (> 0xff) character.
6589 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6590 Register res,
6591 FloatRegister tmp0, FloatRegister tmp1,
6592 FloatRegister tmp2, FloatRegister tmp3,
6593 FloatRegister tmp4, FloatRegister tmp5) {
6594 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6595 }
6596
6597 // java.math.round(double a)
6598 // Returns the closest long to the argument, with ties rounding to
6599 // positive infinity. This requires some fiddling for corner
6600 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6601 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6602 FloatRegister ftmp) {
6603 Label DONE;
6604 BLOCK_COMMENT("java_round_double: { ");
6605 fmovd(rscratch1, src);
6606 // Use RoundToNearestTiesAway unless src small and -ve.
6607 fcvtasd(dst, src);
6608 // Test if src >= 0 || abs(src) >= 0x1.0p52
6609 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6610 mov(rscratch2, julong_cast(0x1.0p52));
6611 cmp(rscratch1, rscratch2);
6612 br(HS, DONE); {
6613 // src < 0 && abs(src) < 0x1.0p52
6614 // src may have a fractional part, so add 0.5
6615 fmovd(ftmp, 0.5);
6616 faddd(ftmp, src, ftmp);
6617 // Convert double to jlong, use RoundTowardsNegative
6618 fcvtmsd(dst, ftmp);
6619 }
6620 bind(DONE);
6621 BLOCK_COMMENT("} java_round_double");
6622 }
6623
6624 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6625 FloatRegister ftmp) {
6626 Label DONE;
6627 BLOCK_COMMENT("java_round_float: { ");
6628 fmovs(rscratch1, src);
6629 // Use RoundToNearestTiesAway unless src small and -ve.
6630 fcvtassw(dst, src);
6631 // Test if src >= 0 || abs(src) >= 0x1.0p23
6632 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6633 mov(rscratch2, jint_cast(0x1.0p23f));
6634 cmp(rscratch1, rscratch2);
6635 br(HS, DONE); {
6636 // src < 0 && |src| < 0x1.0p23
6637 // src may have a fractional part, so add 0.5
6638 fmovs(ftmp, 0.5f);
6639 fadds(ftmp, src, ftmp);
6640 // Convert float to jint, use RoundTowardsNegative
6641 fcvtmssw(dst, ftmp);
6642 }
6643 bind(DONE);
6644 BLOCK_COMMENT("} java_round_float");
6645 }
6646
6647 // get_thread() can be called anywhere inside generated code so we
6648 // need to save whatever non-callee save context might get clobbered
6649 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6650 // the call setup code.
6651 //
6652 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6653 // On other systems, the helper is a usual C function.
6654 //
6655 void MacroAssembler::get_thread(Register dst) {
6656 RegSet saved_regs =
6657 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6658 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6659
6660 protect_return_address();
6661 push(saved_regs, sp);
6662
6663 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6664 blr(lr);
6665 if (dst != c_rarg0) {
6666 mov(dst, c_rarg0);
6667 }
6668
6669 pop(saved_regs, sp);
6670 authenticate_return_address();
6671 }
6672
6673 void MacroAssembler::cache_wb(Address line) {
6674 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6675 assert(line.index() == noreg, "index should be noreg");
6676 assert(line.offset() == 0, "offset should be 0");
6677 // would like to assert this
6678 // assert(line._ext.shift == 0, "shift should be zero");
6679 if (VM_Version::supports_dcpop()) {
6680 // writeback using clear virtual address to point of persistence
6681 dc(Assembler::CVAP, line.base());
6682 } else {
6683 // no need to generate anything as Unsafe.writebackMemory should
6684 // never invoke this stub
6685 }
6686 }
6687
6688 void MacroAssembler::cache_wbsync(bool is_pre) {
6689 // we only need a barrier post sync
6690 if (!is_pre) {
6691 membar(Assembler::AnyAny);
6692 }
6693 }
6694
6695 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6696 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6697 return;
6698 }
6699 // Make sure that native code does not change SVE vector length.
6700 Label verify_ok;
6701 movw(tmp, zr);
6702 sve_inc(tmp, B);
6703 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6704 br(EQ, verify_ok);
6705 stop("Error: SVE vector length has changed since jvm startup");
6706 bind(verify_ok);
6707 }
6708
6709 void MacroAssembler::verify_ptrue() {
6710 Label verify_ok;
6711 if (!UseSVE) {
6712 return;
6713 }
6714 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6715 sve_dec(rscratch1, B);
6716 cbz(rscratch1, verify_ok);
6717 stop("Error: the preserved predicate register (p7) elements are not all true");
6718 bind(verify_ok);
6719 }
6720
6721 void MacroAssembler::safepoint_isb() {
6722 isb();
6723 #ifndef PRODUCT
6724 if (VerifyCrossModifyFence) {
6725 // Clear the thread state.
6726 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6727 }
6728 #endif
6729 }
6730
6731 #ifndef PRODUCT
6732 void MacroAssembler::verify_cross_modify_fence_not_required() {
6733 if (VerifyCrossModifyFence) {
6734 // Check if thread needs a cross modify fence.
6735 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6736 Label fence_not_required;
6737 cbz(rscratch1, fence_not_required);
6738 // If it does then fail.
6739 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6740 mov(c_rarg0, rthread);
6741 blr(rscratch1);
6742 bind(fence_not_required);
6743 }
6744 }
6745 #endif
6746
6747 void MacroAssembler::spin_wait() {
6748 block_comment("spin_wait {");
6749 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6750 switch (VM_Version::spin_wait_desc().inst()) {
6751 case SpinWait::NOP:
6752 nop();
6753 break;
6754 case SpinWait::ISB:
6755 isb();
6756 break;
6757 case SpinWait::YIELD:
6758 yield();
6759 break;
6760 case SpinWait::SB:
6761 assert(VM_Version::supports_sb(), "current CPU does not support SB instruction");
6762 sb();
6763 break;
6764 default:
6765 ShouldNotReachHere();
6766 }
6767 }
6768 block_comment("}");
6769 }
6770
6771 // Stack frame creation/removal
6772
6773 void MacroAssembler::enter(bool strip_ret_addr) {
6774 if (strip_ret_addr) {
6775 // Addresses can only be signed once. If there are multiple nested frames being created
6776 // in the same function, then the return address needs stripping first.
6777 strip_return_address();
6778 }
6779 protect_return_address();
6780 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6781 mov(rfp, sp);
6782 }
6783
6784 void MacroAssembler::leave() {
6785 mov(sp, rfp);
6786 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6787 authenticate_return_address();
6788 }
6789
6790 // ROP Protection
6791 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6792 // destroying stack frames or whenever directly loading/storing the LR to memory.
6793 // If ROP protection is not set then these functions are no-ops.
6794 // For more details on PAC see pauth_aarch64.hpp.
6795
6796 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6797 // Uses value zero as the modifier.
6798 //
6799 void MacroAssembler::protect_return_address() {
6800 if (VM_Version::use_rop_protection()) {
6801 check_return_address();
6802 paciaz();
6803 }
6804 }
6805
6806 // Sign the return value in the given register. Use before updating the LR in the existing stack
6807 // frame for the current function.
6808 // Uses value zero as the modifier.
6809 //
6810 void MacroAssembler::protect_return_address(Register return_reg) {
6811 if (VM_Version::use_rop_protection()) {
6812 check_return_address(return_reg);
6813 paciza(return_reg);
6814 }
6815 }
6816
6817 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6818 // Uses value zero as the modifier.
6819 //
6820 void MacroAssembler::authenticate_return_address() {
6821 if (VM_Version::use_rop_protection()) {
6822 autiaz();
6823 check_return_address();
6824 }
6825 }
6826
6827 // Authenticate the return value in the given register. Use before updating the LR in the existing
6828 // stack frame for the current function.
6829 // Uses value zero as the modifier.
6830 //
6831 void MacroAssembler::authenticate_return_address(Register return_reg) {
6832 if (VM_Version::use_rop_protection()) {
6833 autiza(return_reg);
6834 check_return_address(return_reg);
6835 }
6836 }
6837
6838 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6839 // there is no guaranteed way of authenticating the LR.
6840 //
6841 void MacroAssembler::strip_return_address() {
6842 if (VM_Version::use_rop_protection()) {
6843 xpaclri();
6844 }
6845 }
6846
6847 #ifndef PRODUCT
6848 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6849 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6850 // it is difficult to debug back to the callee function.
6851 // This function simply loads from the address in the given register.
6852 // Use directly after authentication to catch authentication failures.
6853 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6854 //
6855 void MacroAssembler::check_return_address(Register return_reg) {
6856 if (VM_Version::use_rop_protection()) {
6857 ldr(zr, Address(return_reg));
6858 }
6859 }
6860 #endif
6861
6862 // The java_calling_convention describes stack locations as ideal slots on
6863 // a frame with no abi restrictions. Since we must observe abi restrictions
6864 // (like the placement of the register window) the slots must be biased by
6865 // the following value.
6866 static int reg2offset_in(VMReg r) {
6867 // Account for saved rfp and lr
6868 // This should really be in_preserve_stack_slots
6869 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6870 }
6871
6872 static int reg2offset_out(VMReg r) {
6873 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6874 }
6875
6876 // On 64bit we will store integer like items to the stack as
6877 // 64bits items (AArch64 ABI) even though java would only store
6878 // 32bits for a parameter. On 32bit it will simply be 32bits
6879 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6880 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6881 if (src.first()->is_stack()) {
6882 if (dst.first()->is_stack()) {
6883 // stack to stack
6884 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6885 str(tmp, Address(sp, reg2offset_out(dst.first())));
6886 } else {
6887 // stack to reg
6888 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6889 }
6890 } else if (dst.first()->is_stack()) {
6891 // reg to stack
6892 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6893 } else {
6894 if (dst.first() != src.first()) {
6895 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6896 }
6897 }
6898 }
6899
6900 // An oop arg. Must pass a handle not the oop itself
6901 void MacroAssembler::object_move(
6902 OopMap* map,
6903 int oop_handle_offset,
6904 int framesize_in_slots,
6905 VMRegPair src,
6906 VMRegPair dst,
6907 bool is_receiver,
6908 int* receiver_offset) {
6909
6910 // must pass a handle. First figure out the location we use as a handle
6911
6912 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6913
6914 // See if oop is null if it is we need no handle
6915
6916 if (src.first()->is_stack()) {
6917
6918 // Oop is already on the stack as an argument
6919 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6920 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6921 if (is_receiver) {
6922 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6923 }
6924
6925 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6926 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6927 // conditionally move a null
6928 cmp(rscratch1, zr);
6929 csel(rHandle, zr, rHandle, Assembler::EQ);
6930 } else {
6931
6932 // Oop is in an a register we must store it to the space we reserve
6933 // on the stack for oop_handles and pass a handle if oop is non-null
6934
6935 const Register rOop = src.first()->as_Register();
6936 int oop_slot;
6937 if (rOop == j_rarg0)
6938 oop_slot = 0;
6939 else if (rOop == j_rarg1)
6940 oop_slot = 1;
6941 else if (rOop == j_rarg2)
6942 oop_slot = 2;
6943 else if (rOop == j_rarg3)
6944 oop_slot = 3;
6945 else if (rOop == j_rarg4)
6946 oop_slot = 4;
6947 else if (rOop == j_rarg5)
6948 oop_slot = 5;
6949 else if (rOop == j_rarg6)
6950 oop_slot = 6;
6951 else {
6952 assert(rOop == j_rarg7, "wrong register");
6953 oop_slot = 7;
6954 }
6955
6956 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
6957 int offset = oop_slot*VMRegImpl::stack_slot_size;
6958
6959 map->set_oop(VMRegImpl::stack2reg(oop_slot));
6960 // Store oop in handle area, may be null
6961 str(rOop, Address(sp, offset));
6962 if (is_receiver) {
6963 *receiver_offset = offset;
6964 }
6965
6966 cmp(rOop, zr);
6967 lea(rHandle, Address(sp, offset));
6968 // conditionally move a null
6969 csel(rHandle, zr, rHandle, Assembler::EQ);
6970 }
6971
6972 // If arg is on the stack then place it otherwise it is already in correct reg.
6973 if (dst.first()->is_stack()) {
6974 str(rHandle, Address(sp, reg2offset_out(dst.first())));
6975 }
6976 }
6977
6978 // A float arg may have to do float reg int reg conversion
6979 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
6980 if (src.first()->is_stack()) {
6981 if (dst.first()->is_stack()) {
6982 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
6983 strw(tmp, Address(sp, reg2offset_out(dst.first())));
6984 } else {
6985 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
6986 }
6987 } else if (src.first() != dst.first()) {
6988 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
6989 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
6990 else
6991 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
6992 }
6993 }
6994
6995 // A long move
6996 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
6997 if (src.first()->is_stack()) {
6998 if (dst.first()->is_stack()) {
6999 // stack to stack
7000 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7001 str(tmp, Address(sp, reg2offset_out(dst.first())));
7002 } else {
7003 // stack to reg
7004 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7005 }
7006 } else if (dst.first()->is_stack()) {
7007 // reg to stack
7008 // Do we really have to sign extend???
7009 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7010 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7011 } else {
7012 if (dst.first() != src.first()) {
7013 mov(dst.first()->as_Register(), src.first()->as_Register());
7014 }
7015 }
7016 }
7017
7018
7019 // A double move
7020 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7021 if (src.first()->is_stack()) {
7022 if (dst.first()->is_stack()) {
7023 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7024 str(tmp, Address(sp, reg2offset_out(dst.first())));
7025 } else {
7026 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7027 }
7028 } else if (src.first() != dst.first()) {
7029 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7030 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7031 else
7032 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7033 }
7034 }
7035
7036 // Implements lightweight-locking.
7037 //
7038 // - obj: the object to be locked
7039 // - t1, t2, t3: temporary registers, will be destroyed
7040 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7041 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7042 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7043
7044 Label push;
7045 const Register top = t1;
7046 const Register mark = t2;
7047 const Register t = t3;
7048
7049 // Preload the markWord. It is important that this is the first
7050 // instruction emitted as it is part of C1's null check semantics.
7051 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7052
7053 if (UseObjectMonitorTable) {
7054 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7055 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7056 }
7057
7058 if (DiagnoseSyncOnValueBasedClasses != 0) {
7059 load_klass(t1, obj);
7060 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7061 tst(t1, KlassFlags::_misc_is_value_based_class);
7062 br(Assembler::NE, slow);
7063 }
7064
7065 // Check if the lock-stack is full.
7066 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7067 cmpw(top, (unsigned)LockStack::end_offset());
7068 br(Assembler::GE, slow);
7069
7070 // Check for recursion.
7071 subw(t, top, oopSize);
7072 ldr(t, Address(rthread, t));
7073 cmp(obj, t);
7074 br(Assembler::EQ, push);
7075
7076 // Check header for monitor (0b10).
7077 tst(mark, markWord::monitor_value);
7078 br(Assembler::NE, slow);
7079
7080 // Try to lock. Transition lock bits 0b01 => 0b00
7081 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7082 orr(mark, mark, markWord::unlocked_value);
7083 eor(t, mark, markWord::unlocked_value);
7084 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7085 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7086 br(Assembler::NE, slow);
7087
7088 bind(push);
7089 // After successful lock, push object on lock-stack.
7090 str(obj, Address(rthread, top));
7091 addw(top, top, oopSize);
7092 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7093 }
7094
7095 // Implements lightweight-unlocking.
7096 //
7097 // - obj: the object to be unlocked
7098 // - t1, t2, t3: temporary registers
7099 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7100 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7101 // cmpxchg clobbers rscratch1.
7102 assert_different_registers(obj, t1, t2, t3, rscratch1);
7103
7104 #ifdef ASSERT
7105 {
7106 // Check for lock-stack underflow.
7107 Label stack_ok;
7108 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7109 cmpw(t1, (unsigned)LockStack::start_offset());
7110 br(Assembler::GE, stack_ok);
7111 STOP("Lock-stack underflow");
7112 bind(stack_ok);
7113 }
7114 #endif
7115
7116 Label unlocked, push_and_slow;
7117 const Register top = t1;
7118 const Register mark = t2;
7119 const Register t = t3;
7120
7121 // Check if obj is top of lock-stack.
7122 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7123 subw(top, top, oopSize);
7124 ldr(t, Address(rthread, top));
7125 cmp(obj, t);
7126 br(Assembler::NE, slow);
7127
7128 // Pop lock-stack.
7129 DEBUG_ONLY(str(zr, Address(rthread, top));)
7130 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7131
7132 // Check if recursive.
7133 subw(t, top, oopSize);
7134 ldr(t, Address(rthread, t));
7135 cmp(obj, t);
7136 br(Assembler::EQ, unlocked);
7137
7138 // Not recursive. Check header for monitor (0b10).
7139 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7140 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7141
7142 #ifdef ASSERT
7143 // Check header not unlocked (0b01).
7144 Label not_unlocked;
7145 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7146 stop("lightweight_unlock already unlocked");
7147 bind(not_unlocked);
7148 #endif
7149
7150 // Try to unlock. Transition lock bits 0b00 => 0b01
7151 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7152 orr(t, mark, markWord::unlocked_value);
7153 cmpxchg(obj, mark, t, Assembler::xword,
7154 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7155 br(Assembler::EQ, unlocked);
7156
7157 bind(push_and_slow);
7158 // Restore lock-stack and handle the unlock in runtime.
7159 DEBUG_ONLY(str(obj, Address(rthread, top));)
7160 addw(top, top, oopSize);
7161 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7162 b(slow);
7163
7164 bind(unlocked);
7165 }