1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "ci/ciEnv.hpp"
29 #include "code/compiledIC.hpp"
30 #include "compiler/compileTask.hpp"
31 #include "compiler/disassembler.hpp"
32 #include "compiler/oopMap.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "gc/shared/cardTableBarrierSet.hpp"
36 #include "gc/shared/cardTable.hpp"
37 #include "gc/shared/collectedHeap.hpp"
38 #include "gc/shared/tlab_globals.hpp"
39 #include "interpreter/bytecodeHistogram.hpp"
40 #include "interpreter/interpreter.hpp"
41 #include "interpreter/interpreterRuntime.hpp"
42 #include "jvm.h"
43 #include "memory/resourceArea.hpp"
44 #include "memory/universe.hpp"
45 #include "nativeInst_aarch64.hpp"
46 #include "oops/accessDecorators.hpp"
47 #include "oops/compressedKlass.inline.hpp"
48 #include "oops/compressedOops.inline.hpp"
49 #include "oops/klass.inline.hpp"
50 #include "runtime/continuation.hpp"
51 #include "runtime/icache.hpp"
52 #include "runtime/interfaceSupport.inline.hpp"
53 #include "runtime/javaThread.hpp"
54 #include "runtime/jniHandles.inline.hpp"
55 #include "runtime/sharedRuntime.hpp"
56 #include "runtime/stubRoutines.hpp"
57 #include "utilities/globalDefinitions.hpp"
58 #include "utilities/powerOfTwo.hpp"
59 #ifdef COMPILER1
60 #include "c1/c1_LIRAssembler.hpp"
61 #endif
62 #ifdef COMPILER2
63 #include "oops/oop.hpp"
64 #include "opto/compile.hpp"
65 #include "opto/node.hpp"
66 #include "opto/output.hpp"
67 #endif
68
69 #include <sys/types.h>
70
71 #ifdef PRODUCT
72 #define BLOCK_COMMENT(str) /* nothing */
73 #else
74 #define BLOCK_COMMENT(str) block_comment(str)
75 #endif
76 #define STOP(str) stop(str);
77 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
78
79 #ifdef ASSERT
80 extern "C" void disnm(intptr_t p);
81 #endif
82 // Target-dependent relocation processing
83 //
84 // Instruction sequences whose target may need to be retrieved or
85 // patched are distinguished by their leading instruction, sorting
86 // them into three main instruction groups and related subgroups.
87 //
88 // 1) Branch, Exception and System (insn count = 1)
89 // 1a) Unconditional branch (immediate):
90 // b/bl imm19
91 // 1b) Compare & branch (immediate):
92 // cbz/cbnz Rt imm19
93 // 1c) Test & branch (immediate):
94 // tbz/tbnz Rt imm14
95 // 1d) Conditional branch (immediate):
96 // b.cond imm19
97 //
98 // 2) Loads and Stores (insn count = 1)
99 // 2a) Load register literal:
100 // ldr Rt imm19
101 //
102 // 3) Data Processing Immediate (insn count = 2 or 3)
103 // 3a) PC-rel. addressing
104 // adr/adrp Rx imm21; ldr/str Ry Rx #imm12
105 // adr/adrp Rx imm21; add Ry Rx #imm12
106 // adr/adrp Rx imm21; movk Rx #imm16<<32; ldr/str Ry, [Rx, #offset_in_page]
107 // adr/adrp Rx imm21
108 // adr/adrp Rx imm21; movk Rx #imm16<<32
109 // adr/adrp Rx imm21; movk Rx #imm16<<32; add Ry, Rx, #offset_in_page
110 // The latter form can only happen when the target is an
111 // ExternalAddress, and (by definition) ExternalAddresses don't
112 // move. Because of that property, there is never any need to
113 // patch the last of the three instructions. However,
114 // MacroAssembler::target_addr_for_insn takes all three
115 // instructions into account and returns the correct address.
116 // 3b) Move wide (immediate)
117 // movz Rx #imm16; movk Rx #imm16 << 16; movk Rx #imm16 << 32;
118 //
119 // A switch on a subset of the instruction's bits provides an
120 // efficient dispatch to these subcases.
121 //
122 // insn[28:26] -> main group ('x' == don't care)
123 // 00x -> UNALLOCATED
124 // 100 -> Data Processing Immediate
125 // 101 -> Branch, Exception and System
126 // x1x -> Loads and Stores
127 //
128 // insn[30:25] -> subgroup ('_' == group, 'x' == don't care).
129 // n.b. in some cases extra bits need to be checked to verify the
130 // instruction is as expected
131 //
132 // 1) ... xx101x Branch, Exception and System
133 // 1a) 00___x Unconditional branch (immediate)
134 // 1b) 01___0 Compare & branch (immediate)
135 // 1c) 01___1 Test & branch (immediate)
136 // 1d) 10___0 Conditional branch (immediate)
137 // other Should not happen
138 //
139 // 2) ... xxx1x0 Loads and Stores
140 // 2a) xx1__00 Load/Store register (insn[28] == 1 && insn[24] == 0)
141 // 2aa) x01__00 Load register literal (i.e. requires insn[29] == 0)
142 // strictly should be 64 bit non-FP/SIMD i.e.
143 // 0101_000 (i.e. requires insn[31:24] == 01011000)
144 //
145 // 3) ... xx100x Data Processing Immediate
146 // 3a) xx___00 PC-rel. addressing (n.b. requires insn[24] == 0)
147 // 3b) xx___101 Move wide (immediate) (n.b. requires insn[24:23] == 01)
148 // strictly should be 64 bit movz #imm16<<0
149 // 110___10100 (i.e. requires insn[31:21] == 11010010100)
150 //
151 class RelocActions {
152 protected:
153 typedef int (*reloc_insn)(address insn_addr, address &target);
154
155 virtual reloc_insn adrpMem() = 0;
156 virtual reloc_insn adrpAdd() = 0;
157 virtual reloc_insn adrpMovk() = 0;
158
159 const address _insn_addr;
160 const uint32_t _insn;
161
162 static uint32_t insn_at(address insn_addr, int n) {
163 return ((uint32_t*)insn_addr)[n];
164 }
165 uint32_t insn_at(int n) const {
166 return insn_at(_insn_addr, n);
167 }
168
169 public:
170
171 RelocActions(address insn_addr) : _insn_addr(insn_addr), _insn(insn_at(insn_addr, 0)) {}
172 RelocActions(address insn_addr, uint32_t insn)
173 : _insn_addr(insn_addr), _insn(insn) {}
174
175 virtual int unconditionalBranch(address insn_addr, address &target) = 0;
176 virtual int conditionalBranch(address insn_addr, address &target) = 0;
177 virtual int testAndBranch(address insn_addr, address &target) = 0;
178 virtual int loadStore(address insn_addr, address &target) = 0;
179 virtual int adr(address insn_addr, address &target) = 0;
180 virtual int adrp(address insn_addr, address &target, reloc_insn inner) = 0;
181 virtual int immediate(address insn_addr, address &target) = 0;
182 virtual void verify(address insn_addr, address &target) = 0;
183
184 int ALWAYSINLINE run(address insn_addr, address &target) {
185 int instructions = 1;
186
187 uint32_t dispatch = Instruction_aarch64::extract(_insn, 30, 25);
188 switch(dispatch) {
189 case 0b001010:
190 case 0b001011: {
191 instructions = unconditionalBranch(insn_addr, target);
192 break;
193 }
194 case 0b101010: // Conditional branch (immediate)
195 case 0b011010: { // Compare & branch (immediate)
196 instructions = conditionalBranch(insn_addr, target);
197 break;
198 }
199 case 0b011011: {
200 instructions = testAndBranch(insn_addr, target);
201 break;
202 }
203 case 0b001100:
204 case 0b001110:
205 case 0b011100:
206 case 0b011110:
207 case 0b101100:
208 case 0b101110:
209 case 0b111100:
210 case 0b111110: {
211 // load/store
212 if ((Instruction_aarch64::extract(_insn, 29, 24) & 0b111011) == 0b011000) {
213 // Load register (literal)
214 instructions = loadStore(insn_addr, target);
215 break;
216 } else {
217 // nothing to do
218 assert(target == nullptr, "did not expect to relocate target for polling page load");
219 }
220 break;
221 }
222 case 0b001000:
223 case 0b011000:
224 case 0b101000:
225 case 0b111000: {
226 // adr/adrp
227 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
228 int shift = Instruction_aarch64::extract(_insn, 31, 31);
229 if (shift) {
230 uint32_t insn2 = insn_at(1);
231 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
232 Instruction_aarch64::extract(_insn, 4, 0) ==
233 Instruction_aarch64::extract(insn2, 9, 5)) {
234 instructions = adrp(insn_addr, target, adrpMem());
235 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
236 Instruction_aarch64::extract(_insn, 4, 0) ==
237 Instruction_aarch64::extract(insn2, 4, 0)) {
238 instructions = adrp(insn_addr, target, adrpAdd());
239 } else if (Instruction_aarch64::extract(insn2, 31, 21) == 0b11110010110 &&
240 Instruction_aarch64::extract(_insn, 4, 0) ==
241 Instruction_aarch64::extract(insn2, 4, 0)) {
242 instructions = adrp(insn_addr, target, adrpMovk());
243 } else {
244 ShouldNotReachHere();
245 }
246 } else {
247 instructions = adr(insn_addr, target);
248 }
249 break;
250 }
251 case 0b001001:
252 case 0b011001:
253 case 0b101001:
254 case 0b111001: {
255 instructions = immediate(insn_addr, target);
256 break;
257 }
258 default: {
259 ShouldNotReachHere();
260 }
261 }
262
263 verify(insn_addr, target);
264 return instructions * NativeInstruction::instruction_size;
265 }
266 };
267
268 class Patcher : public RelocActions {
269 virtual reloc_insn adrpMem() { return &Patcher::adrpMem_impl; }
270 virtual reloc_insn adrpAdd() { return &Patcher::adrpAdd_impl; }
271 virtual reloc_insn adrpMovk() { return &Patcher::adrpMovk_impl; }
272
273 public:
274 Patcher(address insn_addr) : RelocActions(insn_addr) {}
275
276 virtual int unconditionalBranch(address insn_addr, address &target) {
277 intptr_t offset = (target - insn_addr) >> 2;
278 Instruction_aarch64::spatch(insn_addr, 25, 0, offset);
279 return 1;
280 }
281 virtual int conditionalBranch(address insn_addr, address &target) {
282 intptr_t offset = (target - insn_addr) >> 2;
283 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
284 return 1;
285 }
286 virtual int testAndBranch(address insn_addr, address &target) {
287 intptr_t offset = (target - insn_addr) >> 2;
288 Instruction_aarch64::spatch(insn_addr, 18, 5, offset);
289 return 1;
290 }
291 virtual int loadStore(address insn_addr, address &target) {
292 intptr_t offset = (target - insn_addr) >> 2;
293 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
294 return 1;
295 }
296 virtual int adr(address insn_addr, address &target) {
297 #ifdef ASSERT
298 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
299 #endif
300 // PC-rel. addressing
301 ptrdiff_t offset = target - insn_addr;
302 int offset_lo = offset & 3;
303 offset >>= 2;
304 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
305 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
306 return 1;
307 }
308 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
309 int instructions = 1;
310 #ifdef ASSERT
311 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
312 #endif
313 ptrdiff_t offset = target - insn_addr;
314 instructions = 2;
315 precond(inner != nullptr);
316 // Give the inner reloc a chance to modify the target.
317 address adjusted_target = target;
318 instructions = (*inner)(insn_addr, adjusted_target);
319 uintptr_t pc_page = (uintptr_t)insn_addr >> 12;
320 uintptr_t adr_page = (uintptr_t)adjusted_target >> 12;
321 offset = adr_page - pc_page;
322 int offset_lo = offset & 3;
323 offset >>= 2;
324 Instruction_aarch64::spatch(insn_addr, 23, 5, offset);
325 Instruction_aarch64::patch(insn_addr, 30, 29, offset_lo);
326 return instructions;
327 }
328 static int adrpMem_impl(address insn_addr, address &target) {
329 uintptr_t dest = (uintptr_t)target;
330 int offset_lo = dest & 0xfff;
331 uint32_t insn2 = insn_at(insn_addr, 1);
332 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
333 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo >> size);
334 guarantee(((dest >> size) << size) == dest, "misaligned target");
335 return 2;
336 }
337 static int adrpAdd_impl(address insn_addr, address &target) {
338 uintptr_t dest = (uintptr_t)target;
339 int offset_lo = dest & 0xfff;
340 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 21, 10, offset_lo);
341 return 2;
342 }
343 static int adrpMovk_impl(address insn_addr, address &target) {
344 uintptr_t dest = uintptr_t(target);
345 Instruction_aarch64::patch(insn_addr + sizeof (uint32_t), 20, 5, (uintptr_t)target >> 32);
346 dest = (dest & 0xffffffffULL) | (uintptr_t(insn_addr) & 0xffff00000000ULL);
347 target = address(dest);
348 return 2;
349 }
350 virtual int immediate(address insn_addr, address &target) {
351 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
352 uint64_t dest = (uint64_t)target;
353 // Move wide constant
354 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
355 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
356 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
357 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
358 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
359 return 3;
360 }
361 virtual void verify(address insn_addr, address &target) {
362 #ifdef ASSERT
363 address address_is = MacroAssembler::target_addr_for_insn(insn_addr);
364 if (!(address_is == target)) {
365 tty->print_cr("%p at %p should be %p", address_is, insn_addr, target);
366 disnm((intptr_t)insn_addr);
367 assert(address_is == target, "should be");
368 }
369 #endif
370 }
371 };
372
373 // If insn1 and insn2 use the same register to form an address, either
374 // by an offsetted LDR or a simple ADD, return the offset. If the
375 // second instruction is an LDR, the offset may be scaled.
376 static bool offset_for(uint32_t insn1, uint32_t insn2, ptrdiff_t &byte_offset) {
377 if (Instruction_aarch64::extract(insn2, 29, 24) == 0b111001 &&
378 Instruction_aarch64::extract(insn1, 4, 0) ==
379 Instruction_aarch64::extract(insn2, 9, 5)) {
380 // Load/store register (unsigned immediate)
381 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
382 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
383 byte_offset <<= size;
384 return true;
385 } else if (Instruction_aarch64::extract(insn2, 31, 22) == 0b1001000100 &&
386 Instruction_aarch64::extract(insn1, 4, 0) ==
387 Instruction_aarch64::extract(insn2, 4, 0)) {
388 // add (immediate)
389 byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
390 return true;
391 }
392 return false;
393 }
394
395 class AArch64Decoder : public RelocActions {
396 virtual reloc_insn adrpMem() { return &AArch64Decoder::adrpMem_impl; }
397 virtual reloc_insn adrpAdd() { return &AArch64Decoder::adrpAdd_impl; }
398 virtual reloc_insn adrpMovk() { return &AArch64Decoder::adrpMovk_impl; }
399
400 public:
401 AArch64Decoder(address insn_addr, uint32_t insn) : RelocActions(insn_addr, insn) {}
402
403 virtual int loadStore(address insn_addr, address &target) {
404 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
405 target = insn_addr + (offset << 2);
406 return 1;
407 }
408 virtual int unconditionalBranch(address insn_addr, address &target) {
409 intptr_t offset = Instruction_aarch64::sextract(_insn, 25, 0);
410 target = insn_addr + (offset << 2);
411 return 1;
412 }
413 virtual int conditionalBranch(address insn_addr, address &target) {
414 intptr_t offset = Instruction_aarch64::sextract(_insn, 23, 5);
415 target = address(((uint64_t)insn_addr + (offset << 2)));
416 return 1;
417 }
418 virtual int testAndBranch(address insn_addr, address &target) {
419 intptr_t offset = Instruction_aarch64::sextract(_insn, 18, 5);
420 target = address(((uint64_t)insn_addr + (offset << 2)));
421 return 1;
422 }
423 virtual int adr(address insn_addr, address &target) {
424 // PC-rel. addressing
425 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
426 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
427 target = address((uint64_t)insn_addr + offset);
428 return 1;
429 }
430 virtual int adrp(address insn_addr, address &target, reloc_insn inner) {
431 assert(Instruction_aarch64::extract(_insn, 28, 24) == 0b10000, "must be");
432 intptr_t offset = Instruction_aarch64::extract(_insn, 30, 29);
433 offset |= Instruction_aarch64::sextract(_insn, 23, 5) << 2;
434 int shift = 12;
435 offset <<= shift;
436 uint64_t target_page = ((uint64_t)insn_addr) + offset;
437 target_page &= ((uint64_t)-1) << shift;
438 uint32_t insn2 = insn_at(1);
439 target = address(target_page);
440 precond(inner != nullptr);
441 (*inner)(insn_addr, target);
442 return 2;
443 }
444 static int adrpMem_impl(address insn_addr, address &target) {
445 uint32_t insn2 = insn_at(insn_addr, 1);
446 // Load/store register (unsigned immediate)
447 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
448 uint32_t size = Instruction_aarch64::extract(insn2, 31, 30);
449 byte_offset <<= size;
450 target += byte_offset;
451 return 2;
452 }
453 static int adrpAdd_impl(address insn_addr, address &target) {
454 uint32_t insn2 = insn_at(insn_addr, 1);
455 // add (immediate)
456 ptrdiff_t byte_offset = Instruction_aarch64::extract(insn2, 21, 10);
457 target += byte_offset;
458 return 2;
459 }
460 static int adrpMovk_impl(address insn_addr, address &target) {
461 uint32_t insn2 = insn_at(insn_addr, 1);
462 uint64_t dest = uint64_t(target);
463 dest = (dest & 0xffff0000ffffffff) |
464 ((uint64_t)Instruction_aarch64::extract(insn2, 20, 5) << 32);
465 target = address(dest);
466
467 // We know the destination 4k page. Maybe we have a third
468 // instruction.
469 uint32_t insn = insn_at(insn_addr, 0);
470 uint32_t insn3 = insn_at(insn_addr, 2);
471 ptrdiff_t byte_offset;
472 if (offset_for(insn, insn3, byte_offset)) {
473 target += byte_offset;
474 return 3;
475 } else {
476 return 2;
477 }
478 }
479 virtual int immediate(address insn_addr, address &target) {
480 uint32_t *insns = (uint32_t *)insn_addr;
481 assert(Instruction_aarch64::extract(_insn, 31, 21) == 0b11010010100, "must be");
482 // Move wide constant: movz, movk, movk. See movptr().
483 assert(nativeInstruction_at(insns+1)->is_movk(), "wrong insns in patch");
484 assert(nativeInstruction_at(insns+2)->is_movk(), "wrong insns in patch");
485 target = address(uint64_t(Instruction_aarch64::extract(_insn, 20, 5))
486 + (uint64_t(Instruction_aarch64::extract(insns[1], 20, 5)) << 16)
487 + (uint64_t(Instruction_aarch64::extract(insns[2], 20, 5)) << 32));
488 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
489 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
490 return 3;
491 }
492 virtual void verify(address insn_addr, address &target) {
493 }
494 };
495
496 address MacroAssembler::target_addr_for_insn(address insn_addr, uint32_t insn) {
497 AArch64Decoder decoder(insn_addr, insn);
498 address target;
499 decoder.run(insn_addr, target);
500 return target;
501 }
502
503 // Patch any kind of instruction; there may be several instructions.
504 // Return the total length (in bytes) of the instructions.
505 int MacroAssembler::pd_patch_instruction_size(address insn_addr, address target) {
506 Patcher patcher(insn_addr);
507 return patcher.run(insn_addr, target);
508 }
509
510 int MacroAssembler::patch_oop(address insn_addr, address o) {
511 int instructions;
512 unsigned insn = *(unsigned*)insn_addr;
513 assert(nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
514
515 // OOPs are either narrow (32 bits) or wide (48 bits). We encode
516 // narrow OOPs by setting the upper 16 bits in the first
517 // instruction.
518 if (Instruction_aarch64::extract(insn, 31, 21) == 0b11010010101) {
519 // Move narrow OOP
520 uint32_t n = CompressedOops::narrow_oop_value(cast_to_oop(o));
521 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
522 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
523 instructions = 2;
524 } else {
525 // Move wide OOP
526 assert(nativeInstruction_at(insn_addr+8)->is_movk(), "wrong insns in patch");
527 uintptr_t dest = (uintptr_t)o;
528 Instruction_aarch64::patch(insn_addr, 20, 5, dest & 0xffff);
529 Instruction_aarch64::patch(insn_addr+4, 20, 5, (dest >>= 16) & 0xffff);
530 Instruction_aarch64::patch(insn_addr+8, 20, 5, (dest >>= 16) & 0xffff);
531 instructions = 3;
532 }
533 return instructions * NativeInstruction::instruction_size;
534 }
535
536 int MacroAssembler::patch_narrow_klass(address insn_addr, narrowKlass n) {
537 // Metadata pointers are either narrow (32 bits) or wide (48 bits).
538 // We encode narrow ones by setting the upper 16 bits in the first
539 // instruction.
540 NativeInstruction *insn = nativeInstruction_at(insn_addr);
541 assert(Instruction_aarch64::extract(insn->encoding(), 31, 21) == 0b11010010101 &&
542 nativeInstruction_at(insn_addr+4)->is_movk(), "wrong insns in patch");
543
544 Instruction_aarch64::patch(insn_addr, 20, 5, n >> 16);
545 Instruction_aarch64::patch(insn_addr+4, 20, 5, n & 0xffff);
546 return 2 * NativeInstruction::instruction_size;
547 }
548
549 address MacroAssembler::target_addr_for_insn_or_null(address insn_addr, unsigned insn) {
550 if (NativeInstruction::is_ldrw_to_zr(address(&insn))) {
551 return nullptr;
552 }
553 return MacroAssembler::target_addr_for_insn(insn_addr, insn);
554 }
555
556 void MacroAssembler::safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp) {
557 ldr(tmp, Address(rthread, JavaThread::polling_word_offset()));
558 if (at_return) {
559 // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
560 // we may safely use the sp instead to perform the stack watermark check.
561 cmp(in_nmethod ? sp : rfp, tmp);
562 br(Assembler::HI, slow_path);
563 } else {
564 tbnz(tmp, log2i_exact(SafepointMechanism::poll_bit()), slow_path);
565 }
566 }
567
568 void MacroAssembler::rt_call(address dest, Register tmp) {
569 CodeBlob *cb = CodeCache::find_blob(dest);
570 if (cb) {
571 far_call(RuntimeAddress(dest));
572 } else {
573 lea(tmp, RuntimeAddress(dest));
574 blr(tmp);
575 }
576 }
577
578 void MacroAssembler::push_cont_fastpath(Register java_thread) {
579 if (!Continuations::enabled()) return;
580 Label done;
581 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
582 cmp(sp, rscratch1);
583 br(Assembler::LS, done);
584 mov(rscratch1, sp); // we can't use sp as the source in str
585 str(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
586 bind(done);
587 }
588
589 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
590 if (!Continuations::enabled()) return;
591 Label done;
592 ldr(rscratch1, Address(java_thread, JavaThread::cont_fastpath_offset()));
593 cmp(sp, rscratch1);
594 br(Assembler::LO, done);
595 str(zr, Address(java_thread, JavaThread::cont_fastpath_offset()));
596 bind(done);
597 }
598
599 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
600 // we must set sp to zero to clear frame
601 str(zr, Address(rthread, JavaThread::last_Java_sp_offset()));
602
603 // must clear fp, so that compiled frames are not confused; it is
604 // possible that we need it only for debugging
605 if (clear_fp) {
606 str(zr, Address(rthread, JavaThread::last_Java_fp_offset()));
607 }
608
609 // Always clear the pc because it could have been set by make_walkable()
610 str(zr, Address(rthread, JavaThread::last_Java_pc_offset()));
611 }
612
613 // Calls to C land
614 //
615 // When entering C land, the rfp, & resp of the last Java frame have to be recorded
616 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
617 // has to be reset to 0. This is required to allow proper stack traversal.
618 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
619 Register last_java_fp,
620 Register last_java_pc,
621 Register scratch) {
622
623 if (last_java_pc->is_valid()) {
624 str(last_java_pc, Address(rthread,
625 JavaThread::frame_anchor_offset()
626 + JavaFrameAnchor::last_Java_pc_offset()));
627 }
628
629 // determine last_java_sp register
630 if (last_java_sp == sp) {
631 mov(scratch, sp);
632 last_java_sp = scratch;
633 } else if (!last_java_sp->is_valid()) {
634 last_java_sp = esp;
635 }
636
637 str(last_java_sp, Address(rthread, JavaThread::last_Java_sp_offset()));
638
639 // last_java_fp is optional
640 if (last_java_fp->is_valid()) {
641 str(last_java_fp, Address(rthread, JavaThread::last_Java_fp_offset()));
642 }
643 }
644
645 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
646 Register last_java_fp,
647 address last_java_pc,
648 Register scratch) {
649 assert(last_java_pc != nullptr, "must provide a valid PC");
650
651 adr(scratch, last_java_pc);
652 str(scratch, Address(rthread,
653 JavaThread::frame_anchor_offset()
654 + JavaFrameAnchor::last_Java_pc_offset()));
655
656 set_last_Java_frame(last_java_sp, last_java_fp, noreg, scratch);
657 }
658
659 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
660 Register last_java_fp,
661 Label &L,
662 Register scratch) {
663 if (L.is_bound()) {
664 set_last_Java_frame(last_java_sp, last_java_fp, target(L), scratch);
665 } else {
666 InstructionMark im(this);
667 L.add_patch_at(code(), locator());
668 set_last_Java_frame(last_java_sp, last_java_fp, pc() /* Patched later */, scratch);
669 }
670 }
671
672 static inline bool target_needs_far_branch(address addr) {
673 if (AOTCodeCache::is_on_for_dump()) {
674 return true;
675 }
676 // codecache size <= 128M
677 if (!MacroAssembler::far_branches()) {
678 return false;
679 }
680 // codecache size > 240M
681 if (MacroAssembler::codestub_branch_needs_far_jump()) {
682 return true;
683 }
684 // codecache size: 128M..240M
685 return !CodeCache::is_non_nmethod(addr);
686 }
687
688 void MacroAssembler::far_call(Address entry, Register tmp) {
689 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
690 assert(CodeCache::find_blob(entry.target()) != nullptr,
691 "destination of far call not found in code cache");
692 assert(entry.rspec().type() == relocInfo::external_word_type
693 || entry.rspec().type() == relocInfo::runtime_call_type
694 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
695 if (target_needs_far_branch(entry.target())) {
696 uint64_t offset;
697 // We can use ADRP here because we know that the total size of
698 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
699 adrp(tmp, entry, offset);
700 add(tmp, tmp, offset);
701 blr(tmp);
702 } else {
703 bl(entry);
704 }
705 }
706
707 int MacroAssembler::far_jump(Address entry, Register tmp) {
708 assert(ReservedCodeCacheSize < 4*G, "branch out of range");
709 assert(CodeCache::find_blob(entry.target()) != nullptr,
710 "destination of far call not found in code cache");
711 assert(entry.rspec().type() == relocInfo::external_word_type
712 || entry.rspec().type() == relocInfo::runtime_call_type
713 || entry.rspec().type() == relocInfo::none, "wrong entry relocInfo type");
714 address start = pc();
715 if (target_needs_far_branch(entry.target())) {
716 uint64_t offset;
717 // We can use ADRP here because we know that the total size of
718 // the code cache cannot exceed 2Gb (ADRP limit is 4GB).
719 adrp(tmp, entry, offset);
720 add(tmp, tmp, offset);
721 br(tmp);
722 } else {
723 b(entry);
724 }
725 return pc() - start;
726 }
727
728 void MacroAssembler::reserved_stack_check() {
729 // testing if reserved zone needs to be enabled
730 Label no_reserved_zone_enabling;
731
732 ldr(rscratch1, Address(rthread, JavaThread::reserved_stack_activation_offset()));
733 cmp(sp, rscratch1);
734 br(Assembler::LO, no_reserved_zone_enabling);
735
736 enter(); // LR and FP are live.
737 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone)));
738 mov(c_rarg0, rthread);
739 blr(rscratch1);
740 leave();
741
742 // We have already removed our own frame.
743 // throw_delayed_StackOverflowError will think that it's been
744 // called by our caller.
745 lea(rscratch1, RuntimeAddress(SharedRuntime::throw_delayed_StackOverflowError_entry()));
746 br(rscratch1);
747 should_not_reach_here();
748
749 bind(no_reserved_zone_enabling);
750 }
751
752 static void pass_arg0(MacroAssembler* masm, Register arg) {
753 if (c_rarg0 != arg ) {
754 masm->mov(c_rarg0, arg);
755 }
756 }
757
758 static void pass_arg1(MacroAssembler* masm, Register arg) {
759 if (c_rarg1 != arg ) {
760 masm->mov(c_rarg1, arg);
761 }
762 }
763
764 static void pass_arg2(MacroAssembler* masm, Register arg) {
765 if (c_rarg2 != arg ) {
766 masm->mov(c_rarg2, arg);
767 }
768 }
769
770 static void pass_arg3(MacroAssembler* masm, Register arg) {
771 if (c_rarg3 != arg ) {
772 masm->mov(c_rarg3, arg);
773 }
774 }
775
776 static bool is_preemptable(address entry_point) {
777 return entry_point == CAST_FROM_FN_PTR(address, InterpreterRuntime::monitorenter);
778 }
779
780 void MacroAssembler::call_VM_base(Register oop_result,
781 Register java_thread,
782 Register last_java_sp,
783 address entry_point,
784 int number_of_arguments,
785 bool check_exceptions) {
786 // determine java_thread register
787 if (!java_thread->is_valid()) {
788 java_thread = rthread;
789 }
790
791 // determine last_java_sp register
792 if (!last_java_sp->is_valid()) {
793 last_java_sp = esp;
794 }
795
796 // debugging support
797 assert(number_of_arguments >= 0 , "cannot have negative number of arguments");
798 assert(java_thread == rthread, "unexpected register");
799 #ifdef ASSERT
800 // TraceBytecodes does not use r12 but saves it over the call, so don't verify
801 // if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");
802 #endif // ASSERT
803
804 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result");
805 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
806
807 // push java thread (becomes first argument of C function)
808
809 mov(c_rarg0, java_thread);
810
811 // set last Java frame before call
812 assert(last_java_sp != rfp, "can't use rfp");
813
814 Label l;
815 if (is_preemptable(entry_point)) {
816 // skip setting last_pc since we already set it to desired value.
817 set_last_Java_frame(last_java_sp, rfp, noreg, rscratch1);
818 } else {
819 set_last_Java_frame(last_java_sp, rfp, l, rscratch1);
820 }
821
822 // do the call, remove parameters
823 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments, &l);
824
825 // lr could be poisoned with PAC signature during throw_pending_exception
826 // if it was tail-call optimized by compiler, since lr is not callee-saved
827 // reload it with proper value
828 adr(lr, l);
829
830 // reset last Java frame
831 // Only interpreter should have to clear fp
832 reset_last_Java_frame(true);
833
834 // C++ interp handles this in the interpreter
835 check_and_handle_popframe(java_thread);
836 check_and_handle_earlyret(java_thread);
837
838 if (check_exceptions) {
839 // check for pending exceptions (java_thread is set upon return)
840 ldr(rscratch1, Address(java_thread, in_bytes(Thread::pending_exception_offset())));
841 Label ok;
842 cbz(rscratch1, ok);
843 lea(rscratch1, RuntimeAddress(StubRoutines::forward_exception_entry()));
844 br(rscratch1);
845 bind(ok);
846 }
847
848 // get oop result if there is one and reset the value in the thread
849 if (oop_result->is_valid()) {
850 get_vm_result_oop(oop_result, java_thread);
851 }
852 }
853
854 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
855 call_VM_base(oop_result, noreg, noreg, entry_point, number_of_arguments, check_exceptions);
856 }
857
858 // Check the entry target is always reachable from any branch.
859 static bool is_always_within_branch_range(Address entry) {
860 if (AOTCodeCache::is_on_for_dump()) {
861 return false;
862 }
863 const address target = entry.target();
864
865 if (!CodeCache::contains(target)) {
866 // We always use trampolines for callees outside CodeCache.
867 assert(entry.rspec().type() == relocInfo::runtime_call_type, "non-runtime call of an external target");
868 return false;
869 }
870
871 if (!MacroAssembler::far_branches()) {
872 return true;
873 }
874
875 if (entry.rspec().type() == relocInfo::runtime_call_type) {
876 // Runtime calls are calls of a non-compiled method (stubs, adapters).
877 // Non-compiled methods stay forever in CodeCache.
878 // We check whether the longest possible branch is within the branch range.
879 assert(CodeCache::find_blob(target) != nullptr &&
880 !CodeCache::find_blob(target)->is_nmethod(),
881 "runtime call of compiled method");
882 const address right_longest_branch_start = CodeCache::high_bound() - NativeInstruction::instruction_size;
883 const address left_longest_branch_start = CodeCache::low_bound();
884 const bool is_reachable = Assembler::reachable_from_branch_at(left_longest_branch_start, target) &&
885 Assembler::reachable_from_branch_at(right_longest_branch_start, target);
886 return is_reachable;
887 }
888
889 return false;
890 }
891
892 // Maybe emit a call via a trampoline. If the code cache is small
893 // trampolines won't be emitted.
894 address MacroAssembler::trampoline_call(Address entry) {
895 assert(entry.rspec().type() == relocInfo::runtime_call_type
896 || entry.rspec().type() == relocInfo::opt_virtual_call_type
897 || entry.rspec().type() == relocInfo::static_call_type
898 || entry.rspec().type() == relocInfo::virtual_call_type, "wrong reloc type");
899
900 address target = entry.target();
901
902 if (!is_always_within_branch_range(entry)) {
903 if (!in_scratch_emit_size()) {
904 // We don't want to emit a trampoline if C2 is generating dummy
905 // code during its branch shortening phase.
906 if (entry.rspec().type() == relocInfo::runtime_call_type) {
907 assert(CodeBuffer::supports_shared_stubs(), "must support shared stubs");
908 code()->share_trampoline_for(entry.target(), offset());
909 } else {
910 address stub = emit_trampoline_stub(offset(), target);
911 if (stub == nullptr) {
912 postcond(pc() == badAddress);
913 return nullptr; // CodeCache is full
914 }
915 }
916 }
917 target = pc();
918 }
919
920 address call_pc = pc();
921 relocate(entry.rspec());
922 bl(target);
923
924 postcond(pc() != badAddress);
925 return call_pc;
926 }
927
928 // Emit a trampoline stub for a call to a target which is too far away.
929 //
930 // code sequences:
931 //
932 // call-site:
933 // branch-and-link to <destination> or <trampoline stub>
934 //
935 // Related trampoline stub for this call site in the stub section:
936 // load the call target from the constant pool
937 // branch (LR still points to the call site above)
938
939 address MacroAssembler::emit_trampoline_stub(int insts_call_instruction_offset,
940 address dest) {
941 // Max stub size: alignment nop, TrampolineStub.
942 address stub = start_a_stub(max_trampoline_stub_size());
943 if (stub == nullptr) {
944 return nullptr; // CodeBuffer::expand failed
945 }
946
947 // Create a trampoline stub relocation which relates this trampoline stub
948 // with the call instruction at insts_call_instruction_offset in the
949 // instructions code-section.
950 align(wordSize);
951 relocate(trampoline_stub_Relocation::spec(code()->insts()->start()
952 + insts_call_instruction_offset));
953 const int stub_start_offset = offset();
954
955 // Now, create the trampoline stub's code:
956 // - load the call
957 // - call
958 Label target;
959 ldr(rscratch1, target);
960 br(rscratch1);
961 bind(target);
962 assert(offset() - stub_start_offset == NativeCallTrampolineStub::data_offset,
963 "should be");
964 emit_int64((int64_t)dest);
965
966 const address stub_start_addr = addr_at(stub_start_offset);
967
968 assert(is_NativeCallTrampolineStub_at(stub_start_addr), "doesn't look like a trampoline");
969
970 end_a_stub();
971 return stub_start_addr;
972 }
973
974 int MacroAssembler::max_trampoline_stub_size() {
975 // Max stub size: alignment nop, TrampolineStub.
976 return NativeInstruction::instruction_size + NativeCallTrampolineStub::instruction_size;
977 }
978
979 void MacroAssembler::emit_static_call_stub() {
980 // CompiledDirectCall::set_to_interpreted knows the
981 // exact layout of this stub.
982
983 isb();
984 mov_metadata(rmethod, nullptr);
985
986 // Jump to the entry point of the c2i stub.
987 if (codestub_branch_needs_far_jump()) {
988 movptr(rscratch1, 0);
989 br(rscratch1);
990 } else {
991 b(pc());
992 }
993 }
994
995 int MacroAssembler::static_call_stub_size() {
996 if (!codestub_branch_needs_far_jump()) {
997 // isb; movk; movz; movz; b
998 return 5 * NativeInstruction::instruction_size;
999 }
1000 // isb; movk; movz; movz; movk; movz; movz; br
1001 return 8 * NativeInstruction::instruction_size;
1002 }
1003
1004 void MacroAssembler::c2bool(Register x) {
1005 // implements x == 0 ? 0 : 1
1006 // note: must only look at least-significant byte of x
1007 // since C-style booleans are stored in one byte
1008 // only! (was bug)
1009 tst(x, 0xff);
1010 cset(x, Assembler::NE);
1011 }
1012
1013 address MacroAssembler::ic_call(address entry, jint method_index) {
1014 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1015 movptr(rscratch2, (intptr_t)Universe::non_oop_word());
1016 return trampoline_call(Address(entry, rh));
1017 }
1018
1019 int MacroAssembler::ic_check_size() {
1020 int extra_instructions = UseCompactObjectHeaders ? 1 : 0;
1021 if (target_needs_far_branch(CAST_FROM_FN_PTR(address, SharedRuntime::get_ic_miss_stub()))) {
1022 return NativeInstruction::instruction_size * (7 + extra_instructions);
1023 } else {
1024 return NativeInstruction::instruction_size * (5 + extra_instructions);
1025 }
1026 }
1027
1028 int MacroAssembler::ic_check(int end_alignment) {
1029 Register receiver = j_rarg0;
1030 Register data = rscratch2;
1031 Register tmp1 = rscratch1;
1032 Register tmp2 = r10;
1033
1034 // The UEP of a code blob ensures that the VEP is padded. However, the padding of the UEP is placed
1035 // before the inline cache check, so we don't have to execute any nop instructions when dispatching
1036 // through the UEP, yet we can ensure that the VEP is aligned appropriately. That's why we align
1037 // before the inline cache check here, and not after
1038 align(end_alignment, offset() + ic_check_size());
1039
1040 int uep_offset = offset();
1041
1042 if (UseCompactObjectHeaders) {
1043 load_narrow_klass_compact(tmp1, receiver);
1044 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1045 cmpw(tmp1, tmp2);
1046 } else if (UseCompressedClassPointers) {
1047 ldrw(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1048 ldrw(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1049 cmpw(tmp1, tmp2);
1050 } else {
1051 ldr(tmp1, Address(receiver, oopDesc::klass_offset_in_bytes()));
1052 ldr(tmp2, Address(data, CompiledICData::speculated_klass_offset()));
1053 cmp(tmp1, tmp2);
1054 }
1055
1056 Label dont;
1057 br(Assembler::EQ, dont);
1058 far_jump(RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1059 bind(dont);
1060 assert((offset() % end_alignment) == 0, "Misaligned verified entry point");
1061
1062 return uep_offset;
1063 }
1064
1065 // Implementation of call_VM versions
1066
1067 void MacroAssembler::call_VM(Register oop_result,
1068 address entry_point,
1069 bool check_exceptions) {
1070 call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1071 }
1072
1073 void MacroAssembler::call_VM(Register oop_result,
1074 address entry_point,
1075 Register arg_1,
1076 bool check_exceptions) {
1077 pass_arg1(this, arg_1);
1078 call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1079 }
1080
1081 void MacroAssembler::call_VM(Register oop_result,
1082 address entry_point,
1083 Register arg_1,
1084 Register arg_2,
1085 bool check_exceptions) {
1086 assert_different_registers(arg_1, c_rarg2);
1087 pass_arg2(this, arg_2);
1088 pass_arg1(this, arg_1);
1089 call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1090 }
1091
1092 void MacroAssembler::call_VM(Register oop_result,
1093 address entry_point,
1094 Register arg_1,
1095 Register arg_2,
1096 Register arg_3,
1097 bool check_exceptions) {
1098 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1099 assert_different_registers(arg_2, c_rarg3);
1100 pass_arg3(this, arg_3);
1101
1102 pass_arg2(this, arg_2);
1103
1104 pass_arg1(this, arg_1);
1105 call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1106 }
1107
1108 void MacroAssembler::call_VM(Register oop_result,
1109 Register last_java_sp,
1110 address entry_point,
1111 int number_of_arguments,
1112 bool check_exceptions) {
1113 call_VM_base(oop_result, rthread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1114 }
1115
1116 void MacroAssembler::call_VM(Register oop_result,
1117 Register last_java_sp,
1118 address entry_point,
1119 Register arg_1,
1120 bool check_exceptions) {
1121 pass_arg1(this, arg_1);
1122 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1123 }
1124
1125 void MacroAssembler::call_VM(Register oop_result,
1126 Register last_java_sp,
1127 address entry_point,
1128 Register arg_1,
1129 Register arg_2,
1130 bool check_exceptions) {
1131
1132 assert_different_registers(arg_1, c_rarg2);
1133 pass_arg2(this, arg_2);
1134 pass_arg1(this, arg_1);
1135 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1136 }
1137
1138 void MacroAssembler::call_VM(Register oop_result,
1139 Register last_java_sp,
1140 address entry_point,
1141 Register arg_1,
1142 Register arg_2,
1143 Register arg_3,
1144 bool check_exceptions) {
1145 assert_different_registers(arg_1, c_rarg2, c_rarg3);
1146 assert_different_registers(arg_2, c_rarg3);
1147 pass_arg3(this, arg_3);
1148 pass_arg2(this, arg_2);
1149 pass_arg1(this, arg_1);
1150 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1151 }
1152
1153
1154 void MacroAssembler::get_vm_result_oop(Register oop_result, Register java_thread) {
1155 ldr(oop_result, Address(java_thread, JavaThread::vm_result_oop_offset()));
1156 str(zr, Address(java_thread, JavaThread::vm_result_oop_offset()));
1157 verify_oop_msg(oop_result, "broken oop in call_VM_base");
1158 }
1159
1160 void MacroAssembler::get_vm_result_metadata(Register metadata_result, Register java_thread) {
1161 ldr(metadata_result, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1162 str(zr, Address(java_thread, JavaThread::vm_result_metadata_offset()));
1163 }
1164
1165 void MacroAssembler::align(int modulus) {
1166 align(modulus, offset());
1167 }
1168
1169 // Ensure that the code at target bytes offset from the current offset() is aligned
1170 // according to modulus.
1171 void MacroAssembler::align(int modulus, int target) {
1172 int delta = target - offset();
1173 while ((offset() + delta) % modulus != 0) nop();
1174 }
1175
1176 void MacroAssembler::post_call_nop() {
1177 if (!Continuations::enabled()) {
1178 return;
1179 }
1180 InstructionMark im(this);
1181 relocate(post_call_nop_Relocation::spec());
1182 InlineSkippedInstructionsCounter skipCounter(this);
1183 nop();
1184 movk(zr, 0);
1185 movk(zr, 0);
1186 }
1187
1188 // these are no-ops overridden by InterpreterMacroAssembler
1189
1190 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { }
1191
1192 void MacroAssembler::check_and_handle_popframe(Register java_thread) { }
1193
1194 // Look up the method for a megamorphic invokeinterface call.
1195 // The target method is determined by <intf_klass, itable_index>.
1196 // The receiver klass is in recv_klass.
1197 // On success, the result will be in method_result, and execution falls through.
1198 // On failure, execution transfers to the given label.
1199 void MacroAssembler::lookup_interface_method(Register recv_klass,
1200 Register intf_klass,
1201 RegisterOrConstant itable_index,
1202 Register method_result,
1203 Register scan_temp,
1204 Label& L_no_such_interface,
1205 bool return_method) {
1206 assert_different_registers(recv_klass, intf_klass, scan_temp);
1207 assert_different_registers(method_result, intf_klass, scan_temp);
1208 assert(recv_klass != method_result || !return_method,
1209 "recv_klass can be destroyed when method isn't needed");
1210 assert(itable_index.is_constant() || itable_index.as_register() == method_result,
1211 "caller must use same register for non-constant itable index as for method");
1212
1213 // Compute start of first itableOffsetEntry (which is at the end of the vtable)
1214 int vtable_base = in_bytes(Klass::vtable_start_offset());
1215 int itentry_off = in_bytes(itableMethodEntry::method_offset());
1216 int scan_step = itableOffsetEntry::size() * wordSize;
1217 int vte_size = vtableEntry::size_in_bytes();
1218 assert(vte_size == wordSize, "else adjust times_vte_scale");
1219
1220 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1221
1222 // Could store the aligned, prescaled offset in the klass.
1223 // lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
1224 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(3)));
1225 add(scan_temp, scan_temp, vtable_base);
1226
1227 if (return_method) {
1228 // Adjust recv_klass by scaled itable_index, so we can free itable_index.
1229 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
1230 // lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
1231 lea(recv_klass, Address(recv_klass, itable_index, Address::lsl(3)));
1232 if (itentry_off)
1233 add(recv_klass, recv_klass, itentry_off);
1234 }
1235
1236 // for (scan = klass->itable(); scan->interface() != nullptr; scan += scan_step) {
1237 // if (scan->interface() == intf) {
1238 // result = (klass + scan->offset() + itable_index);
1239 // }
1240 // }
1241 Label search, found_method;
1242
1243 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1244 cmp(intf_klass, method_result);
1245 br(Assembler::EQ, found_method);
1246 bind(search);
1247 // Check that the previous entry is non-null. A null entry means that
1248 // the receiver class doesn't implement the interface, and wasn't the
1249 // same as when the caller was compiled.
1250 cbz(method_result, L_no_such_interface);
1251 if (itableOffsetEntry::interface_offset() != 0) {
1252 add(scan_temp, scan_temp, scan_step);
1253 ldr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset()));
1254 } else {
1255 ldr(method_result, Address(pre(scan_temp, scan_step)));
1256 }
1257 cmp(intf_klass, method_result);
1258 br(Assembler::NE, search);
1259
1260 bind(found_method);
1261
1262 // Got a hit.
1263 if (return_method) {
1264 ldrw(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset()));
1265 ldr(method_result, Address(recv_klass, scan_temp, Address::uxtw(0)));
1266 }
1267 }
1268
1269 // Look up the method for a megamorphic invokeinterface call in a single pass over itable:
1270 // - check recv_klass (actual object class) is a subtype of resolved_klass from CompiledICData
1271 // - find a holder_klass (class that implements the method) vtable offset and get the method from vtable by index
1272 // The target method is determined by <holder_klass, itable_index>.
1273 // The receiver klass is in recv_klass.
1274 // On success, the result will be in method_result, and execution falls through.
1275 // On failure, execution transfers to the given label.
1276 void MacroAssembler::lookup_interface_method_stub(Register recv_klass,
1277 Register holder_klass,
1278 Register resolved_klass,
1279 Register method_result,
1280 Register temp_itbl_klass,
1281 Register scan_temp,
1282 int itable_index,
1283 Label& L_no_such_interface) {
1284 // 'method_result' is only used as output register at the very end of this method.
1285 // Until then we can reuse it as 'holder_offset'.
1286 Register holder_offset = method_result;
1287 assert_different_registers(resolved_klass, recv_klass, holder_klass, temp_itbl_klass, scan_temp, holder_offset);
1288
1289 int vtable_start_offset = in_bytes(Klass::vtable_start_offset());
1290 int itable_offset_entry_size = itableOffsetEntry::size() * wordSize;
1291 int ioffset = in_bytes(itableOffsetEntry::interface_offset());
1292 int ooffset = in_bytes(itableOffsetEntry::offset_offset());
1293
1294 Label L_loop_search_resolved_entry, L_resolved_found, L_holder_found;
1295
1296 ldrw(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
1297 add(recv_klass, recv_klass, vtable_start_offset + ioffset);
1298 // itableOffsetEntry[] itable = recv_klass + Klass::vtable_start_offset() + sizeof(vtableEntry) * recv_klass->_vtable_len;
1299 // temp_itbl_klass = itable[0]._interface;
1300 int vtblEntrySize = vtableEntry::size_in_bytes();
1301 assert(vtblEntrySize == wordSize, "ldr lsl shift amount must be 3");
1302 ldr(temp_itbl_klass, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1303 mov(holder_offset, zr);
1304 // scan_temp = &(itable[0]._interface)
1305 lea(scan_temp, Address(recv_klass, scan_temp, Address::lsl(exact_log2(vtblEntrySize))));
1306
1307 // Initial checks:
1308 // - if (holder_klass != resolved_klass), go to "scan for resolved"
1309 // - if (itable[0] == holder_klass), shortcut to "holder found"
1310 // - if (itable[0] == 0), no such interface
1311 cmp(resolved_klass, holder_klass);
1312 br(Assembler::NE, L_loop_search_resolved_entry);
1313 cmp(holder_klass, temp_itbl_klass);
1314 br(Assembler::EQ, L_holder_found);
1315 cbz(temp_itbl_klass, L_no_such_interface);
1316
1317 // Loop: Look for holder_klass record in itable
1318 // do {
1319 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1320 // if (temp_itbl_klass == holder_klass) {
1321 // goto L_holder_found; // Found!
1322 // }
1323 // } while (temp_itbl_klass != 0);
1324 // goto L_no_such_interface // Not found.
1325 Label L_search_holder;
1326 bind(L_search_holder);
1327 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1328 cmp(holder_klass, temp_itbl_klass);
1329 br(Assembler::EQ, L_holder_found);
1330 cbnz(temp_itbl_klass, L_search_holder);
1331
1332 b(L_no_such_interface);
1333
1334 // Loop: Look for resolved_class record in itable
1335 // while (true) {
1336 // temp_itbl_klass = *(scan_temp += itable_offset_entry_size);
1337 // if (temp_itbl_klass == 0) {
1338 // goto L_no_such_interface;
1339 // }
1340 // if (temp_itbl_klass == resolved_klass) {
1341 // goto L_resolved_found; // Found!
1342 // }
1343 // if (temp_itbl_klass == holder_klass) {
1344 // holder_offset = scan_temp;
1345 // }
1346 // }
1347 //
1348 Label L_loop_search_resolved;
1349 bind(L_loop_search_resolved);
1350 ldr(temp_itbl_klass, Address(pre(scan_temp, itable_offset_entry_size)));
1351 bind(L_loop_search_resolved_entry);
1352 cbz(temp_itbl_klass, L_no_such_interface);
1353 cmp(resolved_klass, temp_itbl_klass);
1354 br(Assembler::EQ, L_resolved_found);
1355 cmp(holder_klass, temp_itbl_klass);
1356 br(Assembler::NE, L_loop_search_resolved);
1357 mov(holder_offset, scan_temp);
1358 b(L_loop_search_resolved);
1359
1360 // See if we already have a holder klass. If not, go and scan for it.
1361 bind(L_resolved_found);
1362 cbz(holder_offset, L_search_holder);
1363 mov(scan_temp, holder_offset);
1364
1365 // Finally, scan_temp contains holder_klass vtable offset
1366 bind(L_holder_found);
1367 ldrw(method_result, Address(scan_temp, ooffset - ioffset));
1368 add(recv_klass, recv_klass, itable_index * wordSize + in_bytes(itableMethodEntry::method_offset())
1369 - vtable_start_offset - ioffset); // substract offsets to restore the original value of recv_klass
1370 ldr(method_result, Address(recv_klass, method_result, Address::uxtw(0)));
1371 }
1372
1373 // virtual method calling
1374 void MacroAssembler::lookup_virtual_method(Register recv_klass,
1375 RegisterOrConstant vtable_index,
1376 Register method_result) {
1377 assert(vtableEntry::size() * wordSize == 8,
1378 "adjust the scaling in the code below");
1379 int64_t vtable_offset_in_bytes = in_bytes(Klass::vtable_start_offset() + vtableEntry::method_offset());
1380
1381 if (vtable_index.is_register()) {
1382 lea(method_result, Address(recv_klass,
1383 vtable_index.as_register(),
1384 Address::lsl(LogBytesPerWord)));
1385 ldr(method_result, Address(method_result, vtable_offset_in_bytes));
1386 } else {
1387 vtable_offset_in_bytes += vtable_index.as_constant() * wordSize;
1388 ldr(method_result,
1389 form_address(rscratch1, recv_klass, vtable_offset_in_bytes, 0));
1390 }
1391 }
1392
1393 void MacroAssembler::check_klass_subtype(Register sub_klass,
1394 Register super_klass,
1395 Register temp_reg,
1396 Label& L_success) {
1397 Label L_failure;
1398 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, nullptr);
1399 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, nullptr);
1400 bind(L_failure);
1401 }
1402
1403
1404 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
1405 Register super_klass,
1406 Register temp_reg,
1407 Label* L_success,
1408 Label* L_failure,
1409 Label* L_slow_path,
1410 Register super_check_offset) {
1411 assert_different_registers(sub_klass, super_klass, temp_reg, super_check_offset);
1412 bool must_load_sco = ! super_check_offset->is_valid();
1413 if (must_load_sco) {
1414 assert(temp_reg != noreg, "supply either a temp or a register offset");
1415 }
1416
1417 Label L_fallthrough;
1418 int label_nulls = 0;
1419 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1420 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1421 if (L_slow_path == nullptr) { L_slow_path = &L_fallthrough; label_nulls++; }
1422 assert(label_nulls <= 1, "at most one null in the batch");
1423
1424 int sco_offset = in_bytes(Klass::super_check_offset_offset());
1425 Address super_check_offset_addr(super_klass, sco_offset);
1426
1427 // Hacked jmp, which may only be used just before L_fallthrough.
1428 #define final_jmp(label) \
1429 if (&(label) == &L_fallthrough) { /*do nothing*/ } \
1430 else b(label) /*omit semi*/
1431
1432 // If the pointers are equal, we are done (e.g., String[] elements).
1433 // This self-check enables sharing of secondary supertype arrays among
1434 // non-primary types such as array-of-interface. Otherwise, each such
1435 // type would need its own customized SSA.
1436 // We move this check to the front of the fast path because many
1437 // type checks are in fact trivially successful in this manner,
1438 // so we get a nicely predicted branch right at the start of the check.
1439 cmp(sub_klass, super_klass);
1440 br(Assembler::EQ, *L_success);
1441
1442 // Check the supertype display:
1443 if (must_load_sco) {
1444 ldrw(temp_reg, super_check_offset_addr);
1445 super_check_offset = temp_reg;
1446 }
1447
1448 Address super_check_addr(sub_klass, super_check_offset);
1449 ldr(rscratch1, super_check_addr);
1450 cmp(super_klass, rscratch1); // load displayed supertype
1451 br(Assembler::EQ, *L_success);
1452
1453 // This check has worked decisively for primary supers.
1454 // Secondary supers are sought in the super_cache ('super_cache_addr').
1455 // (Secondary supers are interfaces and very deeply nested subtypes.)
1456 // This works in the same check above because of a tricky aliasing
1457 // between the super_cache and the primary super display elements.
1458 // (The 'super_check_addr' can address either, as the case requires.)
1459 // Note that the cache is updated below if it does not help us find
1460 // what we need immediately.
1461 // So if it was a primary super, we can just fail immediately.
1462 // Otherwise, it's the slow path for us (no success at this point).
1463
1464 sub(rscratch1, super_check_offset, in_bytes(Klass::secondary_super_cache_offset()));
1465 if (L_failure == &L_fallthrough) {
1466 cbz(rscratch1, *L_slow_path);
1467 } else {
1468 cbnz(rscratch1, *L_failure);
1469 final_jmp(*L_slow_path);
1470 }
1471
1472 bind(L_fallthrough);
1473
1474 #undef final_jmp
1475 }
1476
1477 // These two are taken from x86, but they look generally useful
1478
1479 // scans count pointer sized words at [addr] for occurrence of value,
1480 // generic
1481 void MacroAssembler::repne_scan(Register addr, Register value, Register count,
1482 Register scratch) {
1483 Label Lloop, Lexit;
1484 cbz(count, Lexit);
1485 bind(Lloop);
1486 ldr(scratch, post(addr, wordSize));
1487 cmp(value, scratch);
1488 br(EQ, Lexit);
1489 sub(count, count, 1);
1490 cbnz(count, Lloop);
1491 bind(Lexit);
1492 }
1493
1494 // scans count 4 byte words at [addr] for occurrence of value,
1495 // generic
1496 void MacroAssembler::repne_scanw(Register addr, Register value, Register count,
1497 Register scratch) {
1498 Label Lloop, Lexit;
1499 cbz(count, Lexit);
1500 bind(Lloop);
1501 ldrw(scratch, post(addr, wordSize));
1502 cmpw(value, scratch);
1503 br(EQ, Lexit);
1504 sub(count, count, 1);
1505 cbnz(count, Lloop);
1506 bind(Lexit);
1507 }
1508
1509 void MacroAssembler::check_klass_subtype_slow_path_linear(Register sub_klass,
1510 Register super_klass,
1511 Register temp_reg,
1512 Register temp2_reg,
1513 Label* L_success,
1514 Label* L_failure,
1515 bool set_cond_codes) {
1516 // NB! Callers may assume that, when temp2_reg is a valid register,
1517 // this code sets it to a nonzero value.
1518
1519 assert_different_registers(sub_klass, super_klass, temp_reg);
1520 if (temp2_reg != noreg)
1521 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1522 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
1523
1524 Label L_fallthrough;
1525 int label_nulls = 0;
1526 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1527 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1528 assert(label_nulls <= 1, "at most one null in the batch");
1529
1530 // a couple of useful fields in sub_klass:
1531 int ss_offset = in_bytes(Klass::secondary_supers_offset());
1532 int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
1533 Address secondary_supers_addr(sub_klass, ss_offset);
1534 Address super_cache_addr( sub_klass, sc_offset);
1535
1536 BLOCK_COMMENT("check_klass_subtype_slow_path");
1537
1538 // Do a linear scan of the secondary super-klass chain.
1539 // This code is rarely used, so simplicity is a virtue here.
1540 // The repne_scan instruction uses fixed registers, which we must spill.
1541 // Don't worry too much about pre-existing connections with the input regs.
1542
1543 assert(sub_klass != r0, "killed reg"); // killed by mov(r0, super)
1544 assert(sub_klass != r2, "killed reg"); // killed by lea(r2, &pst_counter)
1545
1546 RegSet pushed_registers;
1547 if (!IS_A_TEMP(r2)) pushed_registers += r2;
1548 if (!IS_A_TEMP(r5)) pushed_registers += r5;
1549
1550 if (super_klass != r0) {
1551 if (!IS_A_TEMP(r0)) pushed_registers += r0;
1552 }
1553
1554 push(pushed_registers, sp);
1555
1556 // Get super_klass value into r0 (even if it was in r5 or r2).
1557 if (super_klass != r0) {
1558 mov(r0, super_klass);
1559 }
1560
1561 #ifndef PRODUCT
1562 incrementw(ExternalAddress((address)&SharedRuntime::_partial_subtype_ctr));
1563 #endif //PRODUCT
1564
1565 // We will consult the secondary-super array.
1566 ldr(r5, secondary_supers_addr);
1567 // Load the array length.
1568 ldrw(r2, Address(r5, Array<Klass*>::length_offset_in_bytes()));
1569 // Skip to start of data.
1570 add(r5, r5, Array<Klass*>::base_offset_in_bytes());
1571
1572 cmp(sp, zr); // Clear Z flag; SP is never zero
1573 // Scan R2 words at [R5] for an occurrence of R0.
1574 // Set NZ/Z based on last compare.
1575 repne_scan(r5, r0, r2, rscratch1);
1576
1577 // Unspill the temp. registers:
1578 pop(pushed_registers, sp);
1579
1580 br(Assembler::NE, *L_failure);
1581
1582 // Success. Cache the super we found and proceed in triumph.
1583
1584 if (UseSecondarySupersCache) {
1585 str(super_klass, super_cache_addr);
1586 }
1587
1588 if (L_success != &L_fallthrough) {
1589 b(*L_success);
1590 }
1591
1592 #undef IS_A_TEMP
1593
1594 bind(L_fallthrough);
1595 }
1596
1597 // If Register r is invalid, remove a new register from
1598 // available_regs, and add new register to regs_to_push.
1599 Register MacroAssembler::allocate_if_noreg(Register r,
1600 RegSetIterator<Register> &available_regs,
1601 RegSet ®s_to_push) {
1602 if (!r->is_valid()) {
1603 r = *available_regs++;
1604 regs_to_push += r;
1605 }
1606 return r;
1607 }
1608
1609 // check_klass_subtype_slow_path_table() looks for super_klass in the
1610 // hash table belonging to super_klass, branching to L_success or
1611 // L_failure as appropriate. This is essentially a shim which
1612 // allocates registers as necessary then calls
1613 // lookup_secondary_supers_table() to do the work. Any of the temp
1614 // regs may be noreg, in which case this logic will chooses some
1615 // registers push and pop them from the stack.
1616 void MacroAssembler::check_klass_subtype_slow_path_table(Register sub_klass,
1617 Register super_klass,
1618 Register temp_reg,
1619 Register temp2_reg,
1620 Register temp3_reg,
1621 Register result_reg,
1622 FloatRegister vtemp,
1623 Label* L_success,
1624 Label* L_failure,
1625 bool set_cond_codes) {
1626 RegSet temps = RegSet::of(temp_reg, temp2_reg, temp3_reg);
1627
1628 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg, rscratch1);
1629
1630 Label L_fallthrough;
1631 int label_nulls = 0;
1632 if (L_success == nullptr) { L_success = &L_fallthrough; label_nulls++; }
1633 if (L_failure == nullptr) { L_failure = &L_fallthrough; label_nulls++; }
1634 assert(label_nulls <= 1, "at most one null in the batch");
1635
1636 BLOCK_COMMENT("check_klass_subtype_slow_path");
1637
1638 RegSetIterator<Register> available_regs
1639 = (RegSet::range(r0, r15) - temps - sub_klass - super_klass).begin();
1640
1641 RegSet pushed_regs;
1642
1643 temp_reg = allocate_if_noreg(temp_reg, available_regs, pushed_regs);
1644 temp2_reg = allocate_if_noreg(temp2_reg, available_regs, pushed_regs);
1645 temp3_reg = allocate_if_noreg(temp3_reg, available_regs, pushed_regs);
1646 result_reg = allocate_if_noreg(result_reg, available_regs, pushed_regs);
1647
1648 push(pushed_regs, sp);
1649
1650 lookup_secondary_supers_table_var(sub_klass,
1651 super_klass,
1652 temp_reg, temp2_reg, temp3_reg, vtemp, result_reg,
1653 nullptr);
1654 cmp(result_reg, zr);
1655
1656 // Unspill the temp. registers:
1657 pop(pushed_regs, sp);
1658
1659 // NB! Callers may assume that, when set_cond_codes is true, this
1660 // code sets temp2_reg to a nonzero value.
1661 if (set_cond_codes) {
1662 mov(temp2_reg, 1);
1663 }
1664
1665 br(Assembler::NE, *L_failure);
1666
1667 if (L_success != &L_fallthrough) {
1668 b(*L_success);
1669 }
1670
1671 bind(L_fallthrough);
1672 }
1673
1674 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
1675 Register super_klass,
1676 Register temp_reg,
1677 Register temp2_reg,
1678 Label* L_success,
1679 Label* L_failure,
1680 bool set_cond_codes) {
1681 if (UseSecondarySupersTable) {
1682 check_klass_subtype_slow_path_table
1683 (sub_klass, super_klass, temp_reg, temp2_reg, /*temp3*/noreg, /*result*/noreg,
1684 /*vtemp*/fnoreg,
1685 L_success, L_failure, set_cond_codes);
1686 } else {
1687 check_klass_subtype_slow_path_linear
1688 (sub_klass, super_klass, temp_reg, temp2_reg, L_success, L_failure, set_cond_codes);
1689 }
1690 }
1691
1692
1693 // Ensure that the inline code and the stub are using the same registers.
1694 #define LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS \
1695 do { \
1696 assert(r_super_klass == r0 && \
1697 r_array_base == r1 && \
1698 r_array_length == r2 && \
1699 (r_array_index == r3 || r_array_index == noreg) && \
1700 (r_sub_klass == r4 || r_sub_klass == noreg) && \
1701 (r_bitmap == rscratch2 || r_bitmap == noreg) && \
1702 (result == r5 || result == noreg), "registers must match aarch64.ad"); \
1703 } while(0)
1704
1705 bool MacroAssembler::lookup_secondary_supers_table_const(Register r_sub_klass,
1706 Register r_super_klass,
1707 Register temp1,
1708 Register temp2,
1709 Register temp3,
1710 FloatRegister vtemp,
1711 Register result,
1712 u1 super_klass_slot,
1713 bool stub_is_near) {
1714 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1715
1716 Label L_fallthrough;
1717
1718 BLOCK_COMMENT("lookup_secondary_supers_table {");
1719
1720 const Register
1721 r_array_base = temp1, // r1
1722 r_array_length = temp2, // r2
1723 r_array_index = temp3, // r3
1724 r_bitmap = rscratch2;
1725
1726 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1727
1728 u1 bit = super_klass_slot;
1729
1730 // Make sure that result is nonzero if the TBZ below misses.
1731 mov(result, 1);
1732
1733 // We're going to need the bitmap in a vector reg and in a core reg,
1734 // so load both now.
1735 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1736 if (bit != 0) {
1737 ldrd(vtemp, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1738 }
1739 // First check the bitmap to see if super_klass might be present. If
1740 // the bit is zero, we are certain that super_klass is not one of
1741 // the secondary supers.
1742 tbz(r_bitmap, bit, L_fallthrough);
1743
1744 // Get the first array index that can contain super_klass into r_array_index.
1745 if (bit != 0) {
1746 shld(vtemp, vtemp, Klass::SECONDARY_SUPERS_TABLE_MASK - bit);
1747 cnt(vtemp, T8B, vtemp);
1748 addv(vtemp, T8B, vtemp);
1749 fmovd(r_array_index, vtemp);
1750 } else {
1751 mov(r_array_index, (u1)1);
1752 }
1753 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1754
1755 // We will consult the secondary-super array.
1756 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1757
1758 // The value i in r_array_index is >= 1, so even though r_array_base
1759 // points to the length, we don't need to adjust it to point to the
1760 // data.
1761 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1762 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1763
1764 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1765 eor(result, result, r_super_klass);
1766 cbz(result, L_fallthrough); // Found a match
1767
1768 // Is there another entry to check? Consult the bitmap.
1769 tbz(r_bitmap, (bit + 1) & Klass::SECONDARY_SUPERS_TABLE_MASK, L_fallthrough);
1770
1771 // Linear probe.
1772 if (bit != 0) {
1773 ror(r_bitmap, r_bitmap, bit);
1774 }
1775
1776 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1777 // The next slot to be inspected, by the stub we're about to call,
1778 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1779 // have been checked.
1780 Address stub = RuntimeAddress(StubRoutines::lookup_secondary_supers_table_slow_path_stub());
1781 if (stub_is_near) {
1782 bl(stub);
1783 } else {
1784 address call = trampoline_call(stub);
1785 if (call == nullptr) {
1786 return false; // trampoline allocation failed
1787 }
1788 }
1789
1790 BLOCK_COMMENT("} lookup_secondary_supers_table");
1791
1792 bind(L_fallthrough);
1793
1794 if (VerifySecondarySupers) {
1795 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1796 temp1, temp2, result); // r1, r2, r5
1797 }
1798 return true;
1799 }
1800
1801 // At runtime, return 0 in result if r_super_klass is a superclass of
1802 // r_sub_klass, otherwise return nonzero. Use this version of
1803 // lookup_secondary_supers_table() if you don't know ahead of time
1804 // which superclass will be searched for. Used by interpreter and
1805 // runtime stubs. It is larger and has somewhat greater latency than
1806 // the version above, which takes a constant super_klass_slot.
1807 void MacroAssembler::lookup_secondary_supers_table_var(Register r_sub_klass,
1808 Register r_super_klass,
1809 Register temp1,
1810 Register temp2,
1811 Register temp3,
1812 FloatRegister vtemp,
1813 Register result,
1814 Label *L_success) {
1815 assert_different_registers(r_sub_klass, temp1, temp2, temp3, result, rscratch1, rscratch2);
1816
1817 Label L_fallthrough;
1818
1819 BLOCK_COMMENT("lookup_secondary_supers_table {");
1820
1821 const Register
1822 r_array_index = temp3,
1823 slot = rscratch1,
1824 r_bitmap = rscratch2;
1825
1826 ldrb(slot, Address(r_super_klass, Klass::hash_slot_offset()));
1827
1828 // Make sure that result is nonzero if the test below misses.
1829 mov(result, 1);
1830
1831 ldr(r_bitmap, Address(r_sub_klass, Klass::secondary_supers_bitmap_offset()));
1832
1833 // First check the bitmap to see if super_klass might be present. If
1834 // the bit is zero, we are certain that super_klass is not one of
1835 // the secondary supers.
1836
1837 // This next instruction is equivalent to:
1838 // mov(tmp_reg, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1839 // sub(temp2, tmp_reg, slot);
1840 eor(temp2, slot, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 1));
1841 lslv(temp2, r_bitmap, temp2);
1842 tbz(temp2, Klass::SECONDARY_SUPERS_TABLE_SIZE - 1, L_fallthrough);
1843
1844 bool must_save_v0 = (vtemp == fnoreg);
1845 if (must_save_v0) {
1846 // temp1 and result are free, so use them to preserve vtemp
1847 vtemp = v0;
1848 mov(temp1, vtemp, D, 0);
1849 mov(result, vtemp, D, 1);
1850 }
1851
1852 // Get the first array index that can contain super_klass into r_array_index.
1853 mov(vtemp, D, 0, temp2);
1854 cnt(vtemp, T8B, vtemp);
1855 addv(vtemp, T8B, vtemp);
1856 mov(r_array_index, vtemp, D, 0);
1857
1858 if (must_save_v0) {
1859 mov(vtemp, D, 0, temp1 );
1860 mov(vtemp, D, 1, result);
1861 }
1862
1863 // NB! r_array_index is off by 1. It is compensated by keeping r_array_base off by 1 word.
1864
1865 const Register
1866 r_array_base = temp1,
1867 r_array_length = temp2;
1868
1869 // The value i in r_array_index is >= 1, so even though r_array_base
1870 // points to the length, we don't need to adjust it to point to the
1871 // data.
1872 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "Adjust this code");
1873 assert(Array<Klass*>::length_offset_in_bytes() == 0, "Adjust this code");
1874
1875 // We will consult the secondary-super array.
1876 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
1877
1878 ldr(result, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1879 eor(result, result, r_super_klass);
1880 cbz(result, L_success ? *L_success : L_fallthrough); // Found a match
1881
1882 // Is there another entry to check? Consult the bitmap.
1883 rorv(r_bitmap, r_bitmap, slot);
1884 // rol(r_bitmap, r_bitmap, 1);
1885 tbz(r_bitmap, 1, L_fallthrough);
1886
1887 // The slot we just inspected is at secondary_supers[r_array_index - 1].
1888 // The next slot to be inspected, by the logic we're about to call,
1889 // is secondary_supers[r_array_index]. Bits 0 and 1 in the bitmap
1890 // have been checked.
1891 lookup_secondary_supers_table_slow_path(r_super_klass, r_array_base, r_array_index,
1892 r_bitmap, r_array_length, result, /*is_stub*/false);
1893
1894 BLOCK_COMMENT("} lookup_secondary_supers_table");
1895
1896 bind(L_fallthrough);
1897
1898 if (VerifySecondarySupers) {
1899 verify_secondary_supers_table(r_sub_klass, r_super_klass, // r4, r0
1900 temp1, temp2, result); // r1, r2, r5
1901 }
1902
1903 if (L_success) {
1904 cbz(result, *L_success);
1905 }
1906 }
1907
1908 // Called by code generated by check_klass_subtype_slow_path
1909 // above. This is called when there is a collision in the hashed
1910 // lookup in the secondary supers array.
1911 void MacroAssembler::lookup_secondary_supers_table_slow_path(Register r_super_klass,
1912 Register r_array_base,
1913 Register r_array_index,
1914 Register r_bitmap,
1915 Register temp1,
1916 Register result,
1917 bool is_stub) {
1918 assert_different_registers(r_super_klass, r_array_base, r_array_index, r_bitmap, temp1, result, rscratch1);
1919
1920 const Register
1921 r_array_length = temp1,
1922 r_sub_klass = noreg; // unused
1923
1924 if (is_stub) {
1925 LOOKUP_SECONDARY_SUPERS_TABLE_REGISTERS;
1926 }
1927
1928 Label L_fallthrough, L_huge;
1929
1930 // Load the array length.
1931 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
1932 // And adjust the array base to point to the data.
1933 // NB! Effectively increments current slot index by 1.
1934 assert(Array<Klass*>::base_offset_in_bytes() == wordSize, "");
1935 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
1936
1937 // The bitmap is full to bursting.
1938 // Implicit invariant: BITMAP_FULL implies (length > 0)
1939 assert(Klass::SECONDARY_SUPERS_BITMAP_FULL == ~uintx(0), "");
1940 cmpw(r_array_length, (u1)(Klass::SECONDARY_SUPERS_TABLE_SIZE - 2));
1941 br(GT, L_huge);
1942
1943 // NB! Our caller has checked bits 0 and 1 in the bitmap. The
1944 // current slot (at secondary_supers[r_array_index]) has not yet
1945 // been inspected, and r_array_index may be out of bounds if we
1946 // wrapped around the end of the array.
1947
1948 { // This is conventional linear probing, but instead of terminating
1949 // when a null entry is found in the table, we maintain a bitmap
1950 // in which a 0 indicates missing entries.
1951 // As long as the bitmap is not completely full,
1952 // array_length == popcount(bitmap). The array_length check above
1953 // guarantees there are 0s in the bitmap, so the loop eventually
1954 // terminates.
1955 Label L_loop;
1956 bind(L_loop);
1957
1958 // Check for wraparound.
1959 cmp(r_array_index, r_array_length);
1960 csel(r_array_index, zr, r_array_index, GE);
1961
1962 ldr(rscratch1, Address(r_array_base, r_array_index, Address::lsl(LogBytesPerWord)));
1963 eor(result, rscratch1, r_super_klass);
1964 cbz(result, L_fallthrough);
1965
1966 tbz(r_bitmap, 2, L_fallthrough); // look-ahead check (Bit 2); result is non-zero
1967
1968 ror(r_bitmap, r_bitmap, 1);
1969 add(r_array_index, r_array_index, 1);
1970 b(L_loop);
1971 }
1972
1973 { // Degenerate case: more than 64 secondary supers.
1974 // FIXME: We could do something smarter here, maybe a vectorized
1975 // comparison or a binary search, but is that worth any added
1976 // complexity?
1977 bind(L_huge);
1978 cmp(sp, zr); // Clear Z flag; SP is never zero
1979 repne_scan(r_array_base, r_super_klass, r_array_length, rscratch1);
1980 cset(result, NE); // result == 0 iff we got a match.
1981 }
1982
1983 bind(L_fallthrough);
1984 }
1985
1986 // Make sure that the hashed lookup and a linear scan agree.
1987 void MacroAssembler::verify_secondary_supers_table(Register r_sub_klass,
1988 Register r_super_klass,
1989 Register temp1,
1990 Register temp2,
1991 Register result) {
1992 assert_different_registers(r_sub_klass, r_super_klass, temp1, temp2, result, rscratch1);
1993
1994 const Register
1995 r_array_base = temp1,
1996 r_array_length = temp2,
1997 r_array_index = noreg, // unused
1998 r_bitmap = noreg; // unused
1999
2000 BLOCK_COMMENT("verify_secondary_supers_table {");
2001
2002 // We will consult the secondary-super array.
2003 ldr(r_array_base, Address(r_sub_klass, in_bytes(Klass::secondary_supers_offset())));
2004
2005 // Load the array length.
2006 ldrw(r_array_length, Address(r_array_base, Array<Klass*>::length_offset_in_bytes()));
2007 // And adjust the array base to point to the data.
2008 add(r_array_base, r_array_base, Array<Klass*>::base_offset_in_bytes());
2009
2010 cmp(sp, zr); // Clear Z flag; SP is never zero
2011 // Scan R2 words at [R5] for an occurrence of R0.
2012 // Set NZ/Z based on last compare.
2013 repne_scan(/*addr*/r_array_base, /*value*/r_super_klass, /*count*/r_array_length, rscratch2);
2014 // rscratch1 == 0 iff we got a match.
2015 cset(rscratch1, NE);
2016
2017 Label passed;
2018 cmp(result, zr);
2019 cset(result, NE); // normalize result to 0/1 for comparison
2020
2021 cmp(rscratch1, result);
2022 br(EQ, passed);
2023 {
2024 mov(r0, r_super_klass); // r0 <- r0
2025 mov(r1, r_sub_klass); // r1 <- r4
2026 mov(r2, /*expected*/rscratch1); // r2 <- r8
2027 mov(r3, result); // r3 <- r5
2028 mov(r4, (address)("mismatch")); // r4 <- const
2029 rt_call(CAST_FROM_FN_PTR(address, Klass::on_secondary_supers_verification_failure), rscratch2);
2030 should_not_reach_here();
2031 }
2032 bind(passed);
2033
2034 BLOCK_COMMENT("} verify_secondary_supers_table");
2035 }
2036
2037 void MacroAssembler::clinit_barrier(Register klass, Register scratch, Label* L_fast_path, Label* L_slow_path) {
2038 assert(L_fast_path != nullptr || L_slow_path != nullptr, "at least one is required");
2039 assert_different_registers(klass, rthread, scratch);
2040
2041 Label L_fallthrough, L_tmp;
2042 if (L_fast_path == nullptr) {
2043 L_fast_path = &L_fallthrough;
2044 } else if (L_slow_path == nullptr) {
2045 L_slow_path = &L_fallthrough;
2046 }
2047 // Fast path check: class is fully initialized
2048 lea(scratch, Address(klass, InstanceKlass::init_state_offset()));
2049 ldarb(scratch, scratch);
2050 cmp(scratch, InstanceKlass::fully_initialized);
2051 br(Assembler::EQ, *L_fast_path);
2052
2053 // Fast path check: current thread is initializer thread
2054 ldr(scratch, Address(klass, InstanceKlass::init_thread_offset()));
2055 cmp(rthread, scratch);
2056
2057 if (L_slow_path == &L_fallthrough) {
2058 br(Assembler::EQ, *L_fast_path);
2059 bind(*L_slow_path);
2060 } else if (L_fast_path == &L_fallthrough) {
2061 br(Assembler::NE, *L_slow_path);
2062 bind(*L_fast_path);
2063 } else {
2064 Unimplemented();
2065 }
2066 }
2067
2068 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
2069 if (!VerifyOops) return;
2070
2071 // Pass register number to verify_oop_subroutine
2072 const char* b = nullptr;
2073 {
2074 ResourceMark rm;
2075 stringStream ss;
2076 ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
2077 b = code_string(ss.as_string());
2078 }
2079 BLOCK_COMMENT("verify_oop {");
2080
2081 strip_return_address(); // This might happen within a stack frame.
2082 protect_return_address();
2083 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2084 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2085
2086 mov(r0, reg);
2087 movptr(rscratch1, (uintptr_t)(address)b);
2088
2089 // call indirectly to solve generation ordering problem
2090 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2091 ldr(rscratch2, Address(rscratch2));
2092 blr(rscratch2);
2093
2094 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2095 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2096 authenticate_return_address();
2097
2098 BLOCK_COMMENT("} verify_oop");
2099 }
2100
2101 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
2102 if (!VerifyOops) return;
2103
2104 const char* b = nullptr;
2105 {
2106 ResourceMark rm;
2107 stringStream ss;
2108 ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
2109 b = code_string(ss.as_string());
2110 }
2111 BLOCK_COMMENT("verify_oop_addr {");
2112
2113 strip_return_address(); // This might happen within a stack frame.
2114 protect_return_address();
2115 stp(r0, rscratch1, Address(pre(sp, -2 * wordSize)));
2116 stp(rscratch2, lr, Address(pre(sp, -2 * wordSize)));
2117
2118 // addr may contain sp so we will have to adjust it based on the
2119 // pushes that we just did.
2120 if (addr.uses(sp)) {
2121 lea(r0, addr);
2122 ldr(r0, Address(r0, 4 * wordSize));
2123 } else {
2124 ldr(r0, addr);
2125 }
2126 movptr(rscratch1, (uintptr_t)(address)b);
2127
2128 // call indirectly to solve generation ordering problem
2129 lea(rscratch2, RuntimeAddress(StubRoutines::verify_oop_subroutine_entry_address()));
2130 ldr(rscratch2, Address(rscratch2));
2131 blr(rscratch2);
2132
2133 ldp(rscratch2, lr, Address(post(sp, 2 * wordSize)));
2134 ldp(r0, rscratch1, Address(post(sp, 2 * wordSize)));
2135 authenticate_return_address();
2136
2137 BLOCK_COMMENT("} verify_oop_addr");
2138 }
2139
2140 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
2141 int extra_slot_offset) {
2142 // cf. TemplateTable::prepare_invoke(), if (load_receiver).
2143 int stackElementSize = Interpreter::stackElementSize;
2144 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
2145 #ifdef ASSERT
2146 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
2147 assert(offset1 - offset == stackElementSize, "correct arithmetic");
2148 #endif
2149 if (arg_slot.is_constant()) {
2150 return Address(esp, arg_slot.as_constant() * stackElementSize
2151 + offset);
2152 } else {
2153 add(rscratch1, esp, arg_slot.as_register(),
2154 ext::uxtx, exact_log2(stackElementSize));
2155 return Address(rscratch1, offset);
2156 }
2157 }
2158
2159 void MacroAssembler::call_VM_leaf_base(address entry_point,
2160 int number_of_arguments,
2161 Label *retaddr) {
2162 Label E, L;
2163
2164 stp(rscratch1, rmethod, Address(pre(sp, -2 * wordSize)));
2165
2166 mov(rscratch1, RuntimeAddress(entry_point));
2167 blr(rscratch1);
2168 if (retaddr)
2169 bind(*retaddr);
2170
2171 ldp(rscratch1, rmethod, Address(post(sp, 2 * wordSize)));
2172 }
2173
2174 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
2175 call_VM_leaf_base(entry_point, number_of_arguments);
2176 }
2177
2178 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
2179 pass_arg0(this, arg_0);
2180 call_VM_leaf_base(entry_point, 1);
2181 }
2182
2183 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2184 assert_different_registers(arg_1, c_rarg0);
2185 pass_arg0(this, arg_0);
2186 pass_arg1(this, arg_1);
2187 call_VM_leaf_base(entry_point, 2);
2188 }
2189
2190 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0,
2191 Register arg_1, Register arg_2) {
2192 assert_different_registers(arg_1, c_rarg0);
2193 assert_different_registers(arg_2, c_rarg0, c_rarg1);
2194 pass_arg0(this, arg_0);
2195 pass_arg1(this, arg_1);
2196 pass_arg2(this, arg_2);
2197 call_VM_leaf_base(entry_point, 3);
2198 }
2199
2200 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
2201 pass_arg0(this, arg_0);
2202 MacroAssembler::call_VM_leaf_base(entry_point, 1);
2203 }
2204
2205 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
2206
2207 assert_different_registers(arg_0, c_rarg1);
2208 pass_arg1(this, arg_1);
2209 pass_arg0(this, arg_0);
2210 MacroAssembler::call_VM_leaf_base(entry_point, 2);
2211 }
2212
2213 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
2214 assert_different_registers(arg_0, c_rarg1, c_rarg2);
2215 assert_different_registers(arg_1, c_rarg2);
2216 pass_arg2(this, arg_2);
2217 pass_arg1(this, arg_1);
2218 pass_arg0(this, arg_0);
2219 MacroAssembler::call_VM_leaf_base(entry_point, 3);
2220 }
2221
2222 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
2223 assert_different_registers(arg_0, c_rarg1, c_rarg2, c_rarg3);
2224 assert_different_registers(arg_1, c_rarg2, c_rarg3);
2225 assert_different_registers(arg_2, c_rarg3);
2226 pass_arg3(this, arg_3);
2227 pass_arg2(this, arg_2);
2228 pass_arg1(this, arg_1);
2229 pass_arg0(this, arg_0);
2230 MacroAssembler::call_VM_leaf_base(entry_point, 4);
2231 }
2232
2233 void MacroAssembler::null_check(Register reg, int offset) {
2234 if (needs_explicit_null_check(offset)) {
2235 // provoke OS null exception if reg is null by
2236 // accessing M[reg] w/o changing any registers
2237 // NOTE: this is plenty to provoke a segv
2238 ldr(zr, Address(reg));
2239 } else {
2240 // nothing to do, (later) access of M[reg + offset]
2241 // will provoke OS null exception if reg is null
2242 }
2243 }
2244
2245 // MacroAssembler protected routines needed to implement
2246 // public methods
2247
2248 void MacroAssembler::mov(Register r, Address dest) {
2249 code_section()->relocate(pc(), dest.rspec());
2250 uint64_t imm64 = (uint64_t)dest.target();
2251 movptr(r, imm64);
2252 }
2253
2254 // Move a constant pointer into r. In AArch64 mode the virtual
2255 // address space is 48 bits in size, so we only need three
2256 // instructions to create a patchable instruction sequence that can
2257 // reach anywhere.
2258 void MacroAssembler::movptr(Register r, uintptr_t imm64) {
2259 #ifndef PRODUCT
2260 {
2261 char buffer[64];
2262 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, (uint64_t)imm64);
2263 block_comment(buffer);
2264 }
2265 #endif
2266 assert(imm64 < (1ull << 48), "48-bit overflow in address constant");
2267 movz(r, imm64 & 0xffff);
2268 imm64 >>= 16;
2269 movk(r, imm64 & 0xffff, 16);
2270 imm64 >>= 16;
2271 movk(r, imm64 & 0xffff, 32);
2272 }
2273
2274 // Macro to mov replicated immediate to vector register.
2275 // imm64: only the lower 8/16/32 bits are considered for B/H/S type. That is,
2276 // the upper 56/48/32 bits must be zeros for B/H/S type.
2277 // Vd will get the following values for different arrangements in T
2278 // imm64 == hex 000000gh T8B: Vd = ghghghghghghghgh
2279 // imm64 == hex 000000gh T16B: Vd = ghghghghghghghghghghghghghghghgh
2280 // imm64 == hex 0000efgh T4H: Vd = efghefghefghefgh
2281 // imm64 == hex 0000efgh T8H: Vd = efghefghefghefghefghefghefghefgh
2282 // imm64 == hex abcdefgh T2S: Vd = abcdefghabcdefgh
2283 // imm64 == hex abcdefgh T4S: Vd = abcdefghabcdefghabcdefghabcdefgh
2284 // imm64 == hex abcdefgh T1D: Vd = 00000000abcdefgh
2285 // imm64 == hex abcdefgh T2D: Vd = 00000000abcdefgh00000000abcdefgh
2286 // Clobbers rscratch1
2287 void MacroAssembler::mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64) {
2288 assert(T != T1Q, "unsupported");
2289 if (T == T1D || T == T2D) {
2290 int imm = operand_valid_for_movi_immediate(imm64, T);
2291 if (-1 != imm) {
2292 movi(Vd, T, imm);
2293 } else {
2294 mov(rscratch1, imm64);
2295 dup(Vd, T, rscratch1);
2296 }
2297 return;
2298 }
2299
2300 #ifdef ASSERT
2301 if (T == T8B || T == T16B) assert((imm64 & ~0xff) == 0, "extraneous bits (T8B/T16B)");
2302 if (T == T4H || T == T8H) assert((imm64 & ~0xffff) == 0, "extraneous bits (T4H/T8H)");
2303 if (T == T2S || T == T4S) assert((imm64 & ~0xffffffff) == 0, "extraneous bits (T2S/T4S)");
2304 #endif
2305 int shift = operand_valid_for_movi_immediate(imm64, T);
2306 uint32_t imm32 = imm64 & 0xffffffffULL;
2307 if (shift >= 0) {
2308 movi(Vd, T, (imm32 >> shift) & 0xff, shift);
2309 } else {
2310 movw(rscratch1, imm32);
2311 dup(Vd, T, rscratch1);
2312 }
2313 }
2314
2315 void MacroAssembler::mov_immediate64(Register dst, uint64_t imm64)
2316 {
2317 #ifndef PRODUCT
2318 {
2319 char buffer[64];
2320 snprintf(buffer, sizeof(buffer), "0x%" PRIX64, imm64);
2321 block_comment(buffer);
2322 }
2323 #endif
2324 if (operand_valid_for_logical_immediate(false, imm64)) {
2325 orr(dst, zr, imm64);
2326 } else {
2327 // we can use a combination of MOVZ or MOVN with
2328 // MOVK to build up the constant
2329 uint64_t imm_h[4];
2330 int zero_count = 0;
2331 int neg_count = 0;
2332 int i;
2333 for (i = 0; i < 4; i++) {
2334 imm_h[i] = ((imm64 >> (i * 16)) & 0xffffL);
2335 if (imm_h[i] == 0) {
2336 zero_count++;
2337 } else if (imm_h[i] == 0xffffL) {
2338 neg_count++;
2339 }
2340 }
2341 if (zero_count == 4) {
2342 // one MOVZ will do
2343 movz(dst, 0);
2344 } else if (neg_count == 4) {
2345 // one MOVN will do
2346 movn(dst, 0);
2347 } else if (zero_count == 3) {
2348 for (i = 0; i < 4; i++) {
2349 if (imm_h[i] != 0L) {
2350 movz(dst, (uint32_t)imm_h[i], (i << 4));
2351 break;
2352 }
2353 }
2354 } else if (neg_count == 3) {
2355 // one MOVN will do
2356 for (int i = 0; i < 4; i++) {
2357 if (imm_h[i] != 0xffffL) {
2358 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2359 break;
2360 }
2361 }
2362 } else if (zero_count == 2) {
2363 // one MOVZ and one MOVK will do
2364 for (i = 0; i < 3; i++) {
2365 if (imm_h[i] != 0L) {
2366 movz(dst, (uint32_t)imm_h[i], (i << 4));
2367 i++;
2368 break;
2369 }
2370 }
2371 for (;i < 4; i++) {
2372 if (imm_h[i] != 0L) {
2373 movk(dst, (uint32_t)imm_h[i], (i << 4));
2374 }
2375 }
2376 } else if (neg_count == 2) {
2377 // one MOVN and one MOVK will do
2378 for (i = 0; i < 4; i++) {
2379 if (imm_h[i] != 0xffffL) {
2380 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2381 i++;
2382 break;
2383 }
2384 }
2385 for (;i < 4; i++) {
2386 if (imm_h[i] != 0xffffL) {
2387 movk(dst, (uint32_t)imm_h[i], (i << 4));
2388 }
2389 }
2390 } else if (zero_count == 1) {
2391 // one MOVZ and two MOVKs will do
2392 for (i = 0; i < 4; i++) {
2393 if (imm_h[i] != 0L) {
2394 movz(dst, (uint32_t)imm_h[i], (i << 4));
2395 i++;
2396 break;
2397 }
2398 }
2399 for (;i < 4; i++) {
2400 if (imm_h[i] != 0x0L) {
2401 movk(dst, (uint32_t)imm_h[i], (i << 4));
2402 }
2403 }
2404 } else if (neg_count == 1) {
2405 // one MOVN and two MOVKs will do
2406 for (i = 0; i < 4; i++) {
2407 if (imm_h[i] != 0xffffL) {
2408 movn(dst, (uint32_t)imm_h[i] ^ 0xffffL, (i << 4));
2409 i++;
2410 break;
2411 }
2412 }
2413 for (;i < 4; i++) {
2414 if (imm_h[i] != 0xffffL) {
2415 movk(dst, (uint32_t)imm_h[i], (i << 4));
2416 }
2417 }
2418 } else {
2419 // use a MOVZ and 3 MOVKs (makes it easier to debug)
2420 movz(dst, (uint32_t)imm_h[0], 0);
2421 for (i = 1; i < 4; i++) {
2422 movk(dst, (uint32_t)imm_h[i], (i << 4));
2423 }
2424 }
2425 }
2426 }
2427
2428 void MacroAssembler::mov_immediate32(Register dst, uint32_t imm32)
2429 {
2430 #ifndef PRODUCT
2431 {
2432 char buffer[64];
2433 snprintf(buffer, sizeof(buffer), "0x%" PRIX32, imm32);
2434 block_comment(buffer);
2435 }
2436 #endif
2437 if (operand_valid_for_logical_immediate(true, imm32)) {
2438 orrw(dst, zr, imm32);
2439 } else {
2440 // we can use MOVZ, MOVN or two calls to MOVK to build up the
2441 // constant
2442 uint32_t imm_h[2];
2443 imm_h[0] = imm32 & 0xffff;
2444 imm_h[1] = ((imm32 >> 16) & 0xffff);
2445 if (imm_h[0] == 0) {
2446 movzw(dst, imm_h[1], 16);
2447 } else if (imm_h[0] == 0xffff) {
2448 movnw(dst, imm_h[1] ^ 0xffff, 16);
2449 } else if (imm_h[1] == 0) {
2450 movzw(dst, imm_h[0], 0);
2451 } else if (imm_h[1] == 0xffff) {
2452 movnw(dst, imm_h[0] ^ 0xffff, 0);
2453 } else {
2454 // use a MOVZ and MOVK (makes it easier to debug)
2455 movzw(dst, imm_h[0], 0);
2456 movkw(dst, imm_h[1], 16);
2457 }
2458 }
2459 }
2460
2461 // Form an address from base + offset in Rd. Rd may or may
2462 // not actually be used: you must use the Address that is returned.
2463 // It is up to you to ensure that the shift provided matches the size
2464 // of your data.
2465 Address MacroAssembler::form_address(Register Rd, Register base, int64_t byte_offset, int shift) {
2466 if (Address::offset_ok_for_immed(byte_offset, shift))
2467 // It fits; no need for any heroics
2468 return Address(base, byte_offset);
2469
2470 // Don't do anything clever with negative or misaligned offsets
2471 unsigned mask = (1 << shift) - 1;
2472 if (byte_offset < 0 || byte_offset & mask) {
2473 mov(Rd, byte_offset);
2474 add(Rd, base, Rd);
2475 return Address(Rd);
2476 }
2477
2478 // See if we can do this with two 12-bit offsets
2479 {
2480 uint64_t word_offset = byte_offset >> shift;
2481 uint64_t masked_offset = word_offset & 0xfff000;
2482 if (Address::offset_ok_for_immed(word_offset - masked_offset, 0)
2483 && Assembler::operand_valid_for_add_sub_immediate(masked_offset << shift)) {
2484 add(Rd, base, masked_offset << shift);
2485 word_offset -= masked_offset;
2486 return Address(Rd, word_offset << shift);
2487 }
2488 }
2489
2490 // Do it the hard way
2491 mov(Rd, byte_offset);
2492 add(Rd, base, Rd);
2493 return Address(Rd);
2494 }
2495
2496 int MacroAssembler::corrected_idivl(Register result, Register ra, Register rb,
2497 bool want_remainder, Register scratch)
2498 {
2499 // Full implementation of Java idiv and irem. The function
2500 // returns the (pc) offset of the div instruction - may be needed
2501 // for implicit exceptions.
2502 //
2503 // constraint : ra/rb =/= scratch
2504 // normal case
2505 //
2506 // input : ra: dividend
2507 // rb: divisor
2508 //
2509 // result: either
2510 // quotient (= ra idiv rb)
2511 // remainder (= ra irem rb)
2512
2513 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2514
2515 int idivl_offset = offset();
2516 if (! want_remainder) {
2517 sdivw(result, ra, rb);
2518 } else {
2519 sdivw(scratch, ra, rb);
2520 Assembler::msubw(result, scratch, rb, ra);
2521 }
2522
2523 return idivl_offset;
2524 }
2525
2526 int MacroAssembler::corrected_idivq(Register result, Register ra, Register rb,
2527 bool want_remainder, Register scratch)
2528 {
2529 // Full implementation of Java ldiv and lrem. The function
2530 // returns the (pc) offset of the div instruction - may be needed
2531 // for implicit exceptions.
2532 //
2533 // constraint : ra/rb =/= scratch
2534 // normal case
2535 //
2536 // input : ra: dividend
2537 // rb: divisor
2538 //
2539 // result: either
2540 // quotient (= ra idiv rb)
2541 // remainder (= ra irem rb)
2542
2543 assert(ra != scratch && rb != scratch, "reg cannot be scratch");
2544
2545 int idivq_offset = offset();
2546 if (! want_remainder) {
2547 sdiv(result, ra, rb);
2548 } else {
2549 sdiv(scratch, ra, rb);
2550 Assembler::msub(result, scratch, rb, ra);
2551 }
2552
2553 return idivq_offset;
2554 }
2555
2556 void MacroAssembler::membar(Membar_mask_bits order_constraint) {
2557 address prev = pc() - NativeMembar::instruction_size;
2558 address last = code()->last_insn();
2559 if (last != nullptr && nativeInstruction_at(last)->is_Membar() && prev == last) {
2560 NativeMembar *bar = NativeMembar_at(prev);
2561 if (AlwaysMergeDMB) {
2562 bar->set_kind(bar->get_kind() | order_constraint);
2563 BLOCK_COMMENT("merged membar(always)");
2564 return;
2565 }
2566 // Don't promote DMB ST|DMB LD to DMB (a full barrier) because
2567 // doing so would introduce a StoreLoad which the caller did not
2568 // intend
2569 if (bar->get_kind() == order_constraint
2570 || bar->get_kind() == AnyAny
2571 || order_constraint == AnyAny) {
2572 // We are merging two memory barrier instructions. On AArch64 we
2573 // can do this simply by ORing them together.
2574 bar->set_kind(bar->get_kind() | order_constraint);
2575 BLOCK_COMMENT("merged membar");
2576 return;
2577 } else {
2578 // A special case like "DMB ST;DMB LD;DMB ST", the last DMB can be skipped
2579 // We need check the last 2 instructions
2580 address prev2 = prev - NativeMembar::instruction_size;
2581 if (last != code()->last_label() && nativeInstruction_at(prev2)->is_Membar()) {
2582 NativeMembar *bar2 = NativeMembar_at(prev2);
2583 assert(bar2->get_kind() == order_constraint, "it should be merged before");
2584 BLOCK_COMMENT("merged membar(elided)");
2585 return;
2586 }
2587 }
2588 }
2589 code()->set_last_insn(pc());
2590 dmb(Assembler::barrier(order_constraint));
2591 }
2592
2593 bool MacroAssembler::try_merge_ldst(Register rt, const Address &adr, size_t size_in_bytes, bool is_store) {
2594 if (ldst_can_merge(rt, adr, size_in_bytes, is_store)) {
2595 merge_ldst(rt, adr, size_in_bytes, is_store);
2596 code()->clear_last_insn();
2597 return true;
2598 } else {
2599 assert(size_in_bytes == 8 || size_in_bytes == 4, "only 8 bytes or 4 bytes load/store is supported.");
2600 const uint64_t mask = size_in_bytes - 1;
2601 if (adr.getMode() == Address::base_plus_offset &&
2602 (adr.offset() & mask) == 0) { // only supports base_plus_offset.
2603 code()->set_last_insn(pc());
2604 }
2605 return false;
2606 }
2607 }
2608
2609 void MacroAssembler::ldr(Register Rx, const Address &adr) {
2610 // We always try to merge two adjacent loads into one ldp.
2611 if (!try_merge_ldst(Rx, adr, 8, false)) {
2612 Assembler::ldr(Rx, adr);
2613 }
2614 }
2615
2616 void MacroAssembler::ldrw(Register Rw, const Address &adr) {
2617 // We always try to merge two adjacent loads into one ldp.
2618 if (!try_merge_ldst(Rw, adr, 4, false)) {
2619 Assembler::ldrw(Rw, adr);
2620 }
2621 }
2622
2623 void MacroAssembler::str(Register Rx, const Address &adr) {
2624 // We always try to merge two adjacent stores into one stp.
2625 if (!try_merge_ldst(Rx, adr, 8, true)) {
2626 Assembler::str(Rx, adr);
2627 }
2628 }
2629
2630 void MacroAssembler::strw(Register Rw, const Address &adr) {
2631 // We always try to merge two adjacent stores into one stp.
2632 if (!try_merge_ldst(Rw, adr, 4, true)) {
2633 Assembler::strw(Rw, adr);
2634 }
2635 }
2636
2637 // MacroAssembler routines found actually to be needed
2638
2639 void MacroAssembler::push(Register src)
2640 {
2641 str(src, Address(pre(esp, -1 * wordSize)));
2642 }
2643
2644 void MacroAssembler::pop(Register dst)
2645 {
2646 ldr(dst, Address(post(esp, 1 * wordSize)));
2647 }
2648
2649 // Note: load_unsigned_short used to be called load_unsigned_word.
2650 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2651 int off = offset();
2652 ldrh(dst, src);
2653 return off;
2654 }
2655
2656 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2657 int off = offset();
2658 ldrb(dst, src);
2659 return off;
2660 }
2661
2662 int MacroAssembler::load_signed_short(Register dst, Address src) {
2663 int off = offset();
2664 ldrsh(dst, src);
2665 return off;
2666 }
2667
2668 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2669 int off = offset();
2670 ldrsb(dst, src);
2671 return off;
2672 }
2673
2674 int MacroAssembler::load_signed_short32(Register dst, Address src) {
2675 int off = offset();
2676 ldrshw(dst, src);
2677 return off;
2678 }
2679
2680 int MacroAssembler::load_signed_byte32(Register dst, Address src) {
2681 int off = offset();
2682 ldrsbw(dst, src);
2683 return off;
2684 }
2685
2686 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
2687 switch (size_in_bytes) {
2688 case 8: ldr(dst, src); break;
2689 case 4: ldrw(dst, src); break;
2690 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2691 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2692 default: ShouldNotReachHere();
2693 }
2694 }
2695
2696 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes) {
2697 switch (size_in_bytes) {
2698 case 8: str(src, dst); break;
2699 case 4: strw(src, dst); break;
2700 case 2: strh(src, dst); break;
2701 case 1: strb(src, dst); break;
2702 default: ShouldNotReachHere();
2703 }
2704 }
2705
2706 void MacroAssembler::decrementw(Register reg, int value)
2707 {
2708 if (value < 0) { incrementw(reg, -value); return; }
2709 if (value == 0) { return; }
2710 if (value < (1 << 12)) { subw(reg, reg, value); return; }
2711 /* else */ {
2712 guarantee(reg != rscratch2, "invalid dst for register decrement");
2713 movw(rscratch2, (unsigned)value);
2714 subw(reg, reg, rscratch2);
2715 }
2716 }
2717
2718 void MacroAssembler::decrement(Register reg, int value)
2719 {
2720 if (value < 0) { increment(reg, -value); return; }
2721 if (value == 0) { return; }
2722 if (value < (1 << 12)) { sub(reg, reg, value); return; }
2723 /* else */ {
2724 assert(reg != rscratch2, "invalid dst for register decrement");
2725 mov(rscratch2, (uint64_t)value);
2726 sub(reg, reg, rscratch2);
2727 }
2728 }
2729
2730 void MacroAssembler::decrementw(Address dst, int value)
2731 {
2732 assert(!dst.uses(rscratch1), "invalid dst for address decrement");
2733 if (dst.getMode() == Address::literal) {
2734 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2735 lea(rscratch2, dst);
2736 dst = Address(rscratch2);
2737 }
2738 ldrw(rscratch1, dst);
2739 decrementw(rscratch1, value);
2740 strw(rscratch1, dst);
2741 }
2742
2743 void MacroAssembler::decrement(Address dst, int value)
2744 {
2745 assert(!dst.uses(rscratch1), "invalid address for decrement");
2746 if (dst.getMode() == Address::literal) {
2747 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2748 lea(rscratch2, dst);
2749 dst = Address(rscratch2);
2750 }
2751 ldr(rscratch1, dst);
2752 decrement(rscratch1, value);
2753 str(rscratch1, dst);
2754 }
2755
2756 void MacroAssembler::incrementw(Register reg, int value)
2757 {
2758 if (value < 0) { decrementw(reg, -value); return; }
2759 if (value == 0) { return; }
2760 if (value < (1 << 12)) { addw(reg, reg, value); return; }
2761 /* else */ {
2762 assert(reg != rscratch2, "invalid dst for register increment");
2763 movw(rscratch2, (unsigned)value);
2764 addw(reg, reg, rscratch2);
2765 }
2766 }
2767
2768 void MacroAssembler::increment(Register reg, int value)
2769 {
2770 if (value < 0) { decrement(reg, -value); return; }
2771 if (value == 0) { return; }
2772 if (value < (1 << 12)) { add(reg, reg, value); return; }
2773 /* else */ {
2774 assert(reg != rscratch2, "invalid dst for register increment");
2775 movw(rscratch2, (unsigned)value);
2776 add(reg, reg, rscratch2);
2777 }
2778 }
2779
2780 void MacroAssembler::incrementw(Address dst, int value)
2781 {
2782 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2783 if (dst.getMode() == Address::literal) {
2784 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2785 lea(rscratch2, dst);
2786 dst = Address(rscratch2);
2787 }
2788 ldrw(rscratch1, dst);
2789 incrementw(rscratch1, value);
2790 strw(rscratch1, dst);
2791 }
2792
2793 void MacroAssembler::increment(Address dst, int value)
2794 {
2795 assert(!dst.uses(rscratch1), "invalid dst for address increment");
2796 if (dst.getMode() == Address::literal) {
2797 assert(abs(value) < (1 << 12), "invalid value and address mode combination");
2798 lea(rscratch2, dst);
2799 dst = Address(rscratch2);
2800 }
2801 ldr(rscratch1, dst);
2802 increment(rscratch1, value);
2803 str(rscratch1, dst);
2804 }
2805
2806 // Push lots of registers in the bit set supplied. Don't push sp.
2807 // Return the number of words pushed
2808 int MacroAssembler::push(unsigned int bitset, Register stack) {
2809 int words_pushed = 0;
2810
2811 // Scan bitset to accumulate register pairs
2812 unsigned char regs[32];
2813 int count = 0;
2814 for (int reg = 0; reg <= 30; reg++) {
2815 if (1 & bitset)
2816 regs[count++] = reg;
2817 bitset >>= 1;
2818 }
2819 regs[count++] = zr->raw_encoding();
2820 count &= ~1; // Only push an even number of regs
2821
2822 if (count) {
2823 stp(as_Register(regs[0]), as_Register(regs[1]),
2824 Address(pre(stack, -count * wordSize)));
2825 words_pushed += 2;
2826 }
2827 for (int i = 2; i < count; i += 2) {
2828 stp(as_Register(regs[i]), as_Register(regs[i+1]),
2829 Address(stack, i * wordSize));
2830 words_pushed += 2;
2831 }
2832
2833 assert(words_pushed == count, "oops, pushed != count");
2834
2835 return count;
2836 }
2837
2838 int MacroAssembler::pop(unsigned int bitset, Register stack) {
2839 int words_pushed = 0;
2840
2841 // Scan bitset to accumulate register pairs
2842 unsigned char regs[32];
2843 int count = 0;
2844 for (int reg = 0; reg <= 30; reg++) {
2845 if (1 & bitset)
2846 regs[count++] = reg;
2847 bitset >>= 1;
2848 }
2849 regs[count++] = zr->raw_encoding();
2850 count &= ~1;
2851
2852 for (int i = 2; i < count; i += 2) {
2853 ldp(as_Register(regs[i]), as_Register(regs[i+1]),
2854 Address(stack, i * wordSize));
2855 words_pushed += 2;
2856 }
2857 if (count) {
2858 ldp(as_Register(regs[0]), as_Register(regs[1]),
2859 Address(post(stack, count * wordSize)));
2860 words_pushed += 2;
2861 }
2862
2863 assert(words_pushed == count, "oops, pushed != count");
2864
2865 return count;
2866 }
2867
2868 // Push lots of registers in the bit set supplied. Don't push sp.
2869 // Return the number of dwords pushed
2870 int MacroAssembler::push_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2871 int words_pushed = 0;
2872 bool use_sve = false;
2873 int sve_vector_size_in_bytes = 0;
2874
2875 #ifdef COMPILER2
2876 use_sve = Matcher::supports_scalable_vector();
2877 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2878 #endif
2879
2880 // Scan bitset to accumulate register pairs
2881 unsigned char regs[32];
2882 int count = 0;
2883 for (int reg = 0; reg <= 31; reg++) {
2884 if (1 & bitset)
2885 regs[count++] = reg;
2886 bitset >>= 1;
2887 }
2888
2889 if (count == 0) {
2890 return 0;
2891 }
2892
2893 if (mode == PushPopFull) {
2894 if (use_sve && sve_vector_size_in_bytes > 16) {
2895 mode = PushPopSVE;
2896 } else {
2897 mode = PushPopNeon;
2898 }
2899 }
2900
2901 #ifndef PRODUCT
2902 {
2903 char buffer[48];
2904 if (mode == PushPopSVE) {
2905 snprintf(buffer, sizeof(buffer), "push_fp: %d SVE registers", count);
2906 } else if (mode == PushPopNeon) {
2907 snprintf(buffer, sizeof(buffer), "push_fp: %d Neon registers", count);
2908 } else {
2909 snprintf(buffer, sizeof(buffer), "push_fp: %d fp registers", count);
2910 }
2911 block_comment(buffer);
2912 }
2913 #endif
2914
2915 if (mode == PushPopSVE) {
2916 sub(stack, stack, sve_vector_size_in_bytes * count);
2917 for (int i = 0; i < count; i++) {
2918 sve_str(as_FloatRegister(regs[i]), Address(stack, i));
2919 }
2920 return count * sve_vector_size_in_bytes / 8;
2921 }
2922
2923 if (mode == PushPopNeon) {
2924 if (count == 1) {
2925 strq(as_FloatRegister(regs[0]), Address(pre(stack, -wordSize * 2)));
2926 return 2;
2927 }
2928
2929 bool odd = (count & 1) == 1;
2930 int push_slots = count + (odd ? 1 : 0);
2931
2932 // Always pushing full 128 bit registers.
2933 stpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize * 2)));
2934 words_pushed += 2;
2935
2936 for (int i = 2; i + 1 < count; i += 2) {
2937 stpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
2938 words_pushed += 2;
2939 }
2940
2941 if (odd) {
2942 strq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
2943 words_pushed++;
2944 }
2945
2946 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
2947 return count * 2;
2948 }
2949
2950 if (mode == PushPopFp) {
2951 bool odd = (count & 1) == 1;
2952 int push_slots = count + (odd ? 1 : 0);
2953
2954 if (count == 1) {
2955 // Stack pointer must be 16 bytes aligned
2956 strd(as_FloatRegister(regs[0]), Address(pre(stack, -push_slots * wordSize)));
2957 return 1;
2958 }
2959
2960 stpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(pre(stack, -push_slots * wordSize)));
2961 words_pushed += 2;
2962
2963 for (int i = 2; i + 1 < count; i += 2) {
2964 stpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
2965 words_pushed += 2;
2966 }
2967
2968 if (odd) {
2969 // Stack pointer must be 16 bytes aligned
2970 strd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
2971 words_pushed++;
2972 }
2973
2974 assert(words_pushed == count, "oops, pushed != count");
2975
2976 return count;
2977 }
2978
2979 return 0;
2980 }
2981
2982 // Return the number of dwords popped
2983 int MacroAssembler::pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode) {
2984 int words_pushed = 0;
2985 bool use_sve = false;
2986 int sve_vector_size_in_bytes = 0;
2987
2988 #ifdef COMPILER2
2989 use_sve = Matcher::supports_scalable_vector();
2990 sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
2991 #endif
2992 // Scan bitset to accumulate register pairs
2993 unsigned char regs[32];
2994 int count = 0;
2995 for (int reg = 0; reg <= 31; reg++) {
2996 if (1 & bitset)
2997 regs[count++] = reg;
2998 bitset >>= 1;
2999 }
3000
3001 if (count == 0) {
3002 return 0;
3003 }
3004
3005 if (mode == PushPopFull) {
3006 if (use_sve && sve_vector_size_in_bytes > 16) {
3007 mode = PushPopSVE;
3008 } else {
3009 mode = PushPopNeon;
3010 }
3011 }
3012
3013 #ifndef PRODUCT
3014 {
3015 char buffer[48];
3016 if (mode == PushPopSVE) {
3017 snprintf(buffer, sizeof(buffer), "pop_fp: %d SVE registers", count);
3018 } else if (mode == PushPopNeon) {
3019 snprintf(buffer, sizeof(buffer), "pop_fp: %d Neon registers", count);
3020 } else {
3021 snprintf(buffer, sizeof(buffer), "pop_fp: %d fp registers", count);
3022 }
3023 block_comment(buffer);
3024 }
3025 #endif
3026
3027 if (mode == PushPopSVE) {
3028 for (int i = count - 1; i >= 0; i--) {
3029 sve_ldr(as_FloatRegister(regs[i]), Address(stack, i));
3030 }
3031 add(stack, stack, sve_vector_size_in_bytes * count);
3032 return count * sve_vector_size_in_bytes / 8;
3033 }
3034
3035 if (mode == PushPopNeon) {
3036 if (count == 1) {
3037 ldrq(as_FloatRegister(regs[0]), Address(post(stack, wordSize * 2)));
3038 return 2;
3039 }
3040
3041 bool odd = (count & 1) == 1;
3042 int push_slots = count + (odd ? 1 : 0);
3043
3044 if (odd) {
3045 ldrq(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize * 2));
3046 words_pushed++;
3047 }
3048
3049 for (int i = 2; i + 1 < count; i += 2) {
3050 ldpq(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize * 2));
3051 words_pushed += 2;
3052 }
3053
3054 ldpq(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize * 2)));
3055 words_pushed += 2;
3056
3057 assert(words_pushed == count, "oops, pushed(%d) != count(%d)", words_pushed, count);
3058
3059 return count * 2;
3060 }
3061
3062 if (mode == PushPopFp) {
3063 bool odd = (count & 1) == 1;
3064 int push_slots = count + (odd ? 1 : 0);
3065
3066 if (count == 1) {
3067 ldrd(as_FloatRegister(regs[0]), Address(post(stack, push_slots * wordSize)));
3068 return 1;
3069 }
3070
3071 if (odd) {
3072 ldrd(as_FloatRegister(regs[count - 1]), Address(stack, (count - 1) * wordSize));
3073 words_pushed++;
3074 }
3075
3076 for (int i = 2; i + 1 < count; i += 2) {
3077 ldpd(as_FloatRegister(regs[i]), as_FloatRegister(regs[i+1]), Address(stack, i * wordSize));
3078 words_pushed += 2;
3079 }
3080
3081 ldpd(as_FloatRegister(regs[0]), as_FloatRegister(regs[1]), Address(post(stack, push_slots * wordSize)));
3082 words_pushed += 2;
3083
3084 assert(words_pushed == count, "oops, pushed != count");
3085
3086 return count;
3087 }
3088
3089 return 0;
3090 }
3091
3092 // Return the number of dwords pushed
3093 int MacroAssembler::push_p(unsigned int bitset, Register stack) {
3094 bool use_sve = false;
3095 int sve_predicate_size_in_slots = 0;
3096
3097 #ifdef COMPILER2
3098 use_sve = Matcher::supports_scalable_vector();
3099 if (use_sve) {
3100 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3101 }
3102 #endif
3103
3104 if (!use_sve) {
3105 return 0;
3106 }
3107
3108 unsigned char regs[PRegister::number_of_registers];
3109 int count = 0;
3110 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3111 if (1 & bitset)
3112 regs[count++] = reg;
3113 bitset >>= 1;
3114 }
3115
3116 if (count == 0) {
3117 return 0;
3118 }
3119
3120 int total_push_bytes = align_up(sve_predicate_size_in_slots *
3121 VMRegImpl::stack_slot_size * count, 16);
3122 sub(stack, stack, total_push_bytes);
3123 for (int i = 0; i < count; i++) {
3124 sve_str(as_PRegister(regs[i]), Address(stack, i));
3125 }
3126 return total_push_bytes / 8;
3127 }
3128
3129 // Return the number of dwords popped
3130 int MacroAssembler::pop_p(unsigned int bitset, Register stack) {
3131 bool use_sve = false;
3132 int sve_predicate_size_in_slots = 0;
3133
3134 #ifdef COMPILER2
3135 use_sve = Matcher::supports_scalable_vector();
3136 if (use_sve) {
3137 sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
3138 }
3139 #endif
3140
3141 if (!use_sve) {
3142 return 0;
3143 }
3144
3145 unsigned char regs[PRegister::number_of_registers];
3146 int count = 0;
3147 for (int reg = 0; reg < PRegister::number_of_registers; reg++) {
3148 if (1 & bitset)
3149 regs[count++] = reg;
3150 bitset >>= 1;
3151 }
3152
3153 if (count == 0) {
3154 return 0;
3155 }
3156
3157 int total_pop_bytes = align_up(sve_predicate_size_in_slots *
3158 VMRegImpl::stack_slot_size * count, 16);
3159 for (int i = count - 1; i >= 0; i--) {
3160 sve_ldr(as_PRegister(regs[i]), Address(stack, i));
3161 }
3162 add(stack, stack, total_pop_bytes);
3163 return total_pop_bytes / 8;
3164 }
3165
3166 #ifdef ASSERT
3167 void MacroAssembler::verify_heapbase(const char* msg) {
3168 #if 0
3169 assert (UseCompressedOops || UseCompressedClassPointers, "should be compressed");
3170 assert (Universe::heap() != nullptr, "java heap should be initialized");
3171 if (!UseCompressedOops || Universe::ptr_base() == nullptr) {
3172 // rheapbase is allocated as general register
3173 return;
3174 }
3175 if (CheckCompressedOops) {
3176 Label ok;
3177 push(1 << rscratch1->encoding(), sp); // cmpptr trashes rscratch1
3178 cmpptr(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3179 br(Assembler::EQ, ok);
3180 stop(msg);
3181 bind(ok);
3182 pop(1 << rscratch1->encoding(), sp);
3183 }
3184 #endif
3185 }
3186 #endif
3187
3188 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3189 assert_different_registers(value, tmp1, tmp2);
3190 Label done, tagged, weak_tagged;
3191
3192 cbz(value, done); // Use null as-is.
3193 tst(value, JNIHandles::tag_mask); // Test for tag.
3194 br(Assembler::NE, tagged);
3195
3196 // Resolve local handle
3197 access_load_at(T_OBJECT, IN_NATIVE | AS_RAW, value, Address(value, 0), tmp1, tmp2);
3198 verify_oop(value);
3199 b(done);
3200
3201 bind(tagged);
3202 STATIC_ASSERT(JNIHandles::TypeTag::weak_global == 0b1);
3203 tbnz(value, 0, weak_tagged); // Test for weak tag.
3204
3205 // Resolve global handle
3206 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3207 verify_oop(value);
3208 b(done);
3209
3210 bind(weak_tagged);
3211 // Resolve jweak.
3212 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3213 value, Address(value, -JNIHandles::TypeTag::weak_global), tmp1, tmp2);
3214 verify_oop(value);
3215
3216 bind(done);
3217 }
3218
3219 void MacroAssembler::resolve_global_jobject(Register value, Register tmp1, Register tmp2) {
3220 assert_different_registers(value, tmp1, tmp2);
3221 Label done;
3222
3223 cbz(value, done); // Use null as-is.
3224
3225 #ifdef ASSERT
3226 {
3227 STATIC_ASSERT(JNIHandles::TypeTag::global == 0b10);
3228 Label valid_global_tag;
3229 tbnz(value, 1, valid_global_tag); // Test for global tag
3230 stop("non global jobject using resolve_global_jobject");
3231 bind(valid_global_tag);
3232 }
3233 #endif
3234
3235 // Resolve global handle
3236 access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, -JNIHandles::TypeTag::global), tmp1, tmp2);
3237 verify_oop(value);
3238
3239 bind(done);
3240 }
3241
3242 void MacroAssembler::stop(const char* msg) {
3243 // Skip AOT caching C strings in scratch buffer.
3244 const char* str = (code_section()->scratch_emit()) ? msg : AOTCodeCache::add_C_string(msg);
3245 BLOCK_COMMENT(str);
3246 // load msg into r0 so we can access it from the signal handler
3247 // ExternalAddress enables saving and restoring via the code cache
3248 lea(c_rarg0, ExternalAddress((address) str));
3249 dcps1(0xdeae);
3250 }
3251
3252 void MacroAssembler::unimplemented(const char* what) {
3253 const char* buf = nullptr;
3254 {
3255 ResourceMark rm;
3256 stringStream ss;
3257 ss.print("unimplemented: %s", what);
3258 buf = code_string(ss.as_string());
3259 }
3260 stop(buf);
3261 }
3262
3263 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
3264 #ifdef ASSERT
3265 Label OK;
3266 br(cc, OK);
3267 stop(msg);
3268 bind(OK);
3269 #endif
3270 }
3271
3272 // If a constant does not fit in an immediate field, generate some
3273 // number of MOV instructions and then perform the operation.
3274 void MacroAssembler::wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
3275 add_sub_imm_insn insn1,
3276 add_sub_reg_insn insn2,
3277 bool is32) {
3278 assert(Rd != zr, "Rd = zr and not setting flags?");
3279 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3280 if (fits) {
3281 (this->*insn1)(Rd, Rn, imm);
3282 } else {
3283 if (g_uabs(imm) < (1 << 24)) {
3284 (this->*insn1)(Rd, Rn, imm & -(1 << 12));
3285 (this->*insn1)(Rd, Rd, imm & ((1 << 12)-1));
3286 } else {
3287 assert_different_registers(Rd, Rn);
3288 mov(Rd, imm);
3289 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3290 }
3291 }
3292 }
3293
3294 // Separate vsn which sets the flags. Optimisations are more restricted
3295 // because we must set the flags correctly.
3296 void MacroAssembler::wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
3297 add_sub_imm_insn insn1,
3298 add_sub_reg_insn insn2,
3299 bool is32) {
3300 bool fits = operand_valid_for_add_sub_immediate(is32 ? (int32_t)imm : imm);
3301 if (fits) {
3302 (this->*insn1)(Rd, Rn, imm);
3303 } else {
3304 assert_different_registers(Rd, Rn);
3305 assert(Rd != zr, "overflow in immediate operand");
3306 mov(Rd, imm);
3307 (this->*insn2)(Rd, Rn, Rd, LSL, 0);
3308 }
3309 }
3310
3311
3312 void MacroAssembler::add(Register Rd, Register Rn, RegisterOrConstant increment) {
3313 if (increment.is_register()) {
3314 add(Rd, Rn, increment.as_register());
3315 } else {
3316 add(Rd, Rn, increment.as_constant());
3317 }
3318 }
3319
3320 void MacroAssembler::addw(Register Rd, Register Rn, RegisterOrConstant increment) {
3321 if (increment.is_register()) {
3322 addw(Rd, Rn, increment.as_register());
3323 } else {
3324 addw(Rd, Rn, increment.as_constant());
3325 }
3326 }
3327
3328 void MacroAssembler::sub(Register Rd, Register Rn, RegisterOrConstant decrement) {
3329 if (decrement.is_register()) {
3330 sub(Rd, Rn, decrement.as_register());
3331 } else {
3332 sub(Rd, Rn, decrement.as_constant());
3333 }
3334 }
3335
3336 void MacroAssembler::subw(Register Rd, Register Rn, RegisterOrConstant decrement) {
3337 if (decrement.is_register()) {
3338 subw(Rd, Rn, decrement.as_register());
3339 } else {
3340 subw(Rd, Rn, decrement.as_constant());
3341 }
3342 }
3343
3344 void MacroAssembler::reinit_heapbase()
3345 {
3346 if (UseCompressedOops) {
3347 if (Universe::is_fully_initialized()) {
3348 mov(rheapbase, CompressedOops::base());
3349 } else {
3350 lea(rheapbase, ExternalAddress(CompressedOops::base_addr()));
3351 ldr(rheapbase, Address(rheapbase));
3352 }
3353 }
3354 }
3355
3356 // this simulates the behaviour of the x86 cmpxchg instruction using a
3357 // load linked/store conditional pair. we use the acquire/release
3358 // versions of these instructions so that we flush pending writes as
3359 // per Java semantics.
3360
3361 // n.b the x86 version assumes the old value to be compared against is
3362 // in rax and updates rax with the value located in memory if the
3363 // cmpxchg fails. we supply a register for the old value explicitly
3364
3365 // the aarch64 load linked/store conditional instructions do not
3366 // accept an offset. so, unlike x86, we must provide a plain register
3367 // to identify the memory word to be compared/exchanged rather than a
3368 // register+offset Address.
3369
3370 void MacroAssembler::cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
3371 Label &succeed, Label *fail) {
3372 // oldv holds comparison value
3373 // newv holds value to write in exchange
3374 // addr identifies memory word to compare against/update
3375 if (UseLSE) {
3376 mov(tmp, oldv);
3377 casal(Assembler::xword, oldv, newv, addr);
3378 cmp(tmp, oldv);
3379 br(Assembler::EQ, succeed);
3380 membar(AnyAny);
3381 } else {
3382 Label retry_load, nope;
3383 prfm(Address(addr), PSTL1STRM);
3384 bind(retry_load);
3385 // flush and load exclusive from the memory location
3386 // and fail if it is not what we expect
3387 ldaxr(tmp, addr);
3388 cmp(tmp, oldv);
3389 br(Assembler::NE, nope);
3390 // if we store+flush with no intervening write tmp will be zero
3391 stlxr(tmp, newv, addr);
3392 cbzw(tmp, succeed);
3393 // retry so we only ever return after a load fails to compare
3394 // ensures we don't return a stale value after a failed write.
3395 b(retry_load);
3396 // if the memory word differs we return it in oldv and signal a fail
3397 bind(nope);
3398 membar(AnyAny);
3399 mov(oldv, tmp);
3400 }
3401 if (fail)
3402 b(*fail);
3403 }
3404
3405 void MacroAssembler::cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
3406 Label &succeed, Label *fail) {
3407 assert(oopDesc::mark_offset_in_bytes() == 0, "assumption");
3408 cmpxchgptr(oldv, newv, obj, tmp, succeed, fail);
3409 }
3410
3411 void MacroAssembler::cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
3412 Label &succeed, Label *fail) {
3413 // oldv holds comparison value
3414 // newv holds value to write in exchange
3415 // addr identifies memory word to compare against/update
3416 // tmp returns 0/1 for success/failure
3417 if (UseLSE) {
3418 mov(tmp, oldv);
3419 casal(Assembler::word, oldv, newv, addr);
3420 cmp(tmp, oldv);
3421 br(Assembler::EQ, succeed);
3422 membar(AnyAny);
3423 } else {
3424 Label retry_load, nope;
3425 prfm(Address(addr), PSTL1STRM);
3426 bind(retry_load);
3427 // flush and load exclusive from the memory location
3428 // and fail if it is not what we expect
3429 ldaxrw(tmp, addr);
3430 cmp(tmp, oldv);
3431 br(Assembler::NE, nope);
3432 // if we store+flush with no intervening write tmp will be zero
3433 stlxrw(tmp, newv, addr);
3434 cbzw(tmp, succeed);
3435 // retry so we only ever return after a load fails to compare
3436 // ensures we don't return a stale value after a failed write.
3437 b(retry_load);
3438 // if the memory word differs we return it in oldv and signal a fail
3439 bind(nope);
3440 membar(AnyAny);
3441 mov(oldv, tmp);
3442 }
3443 if (fail)
3444 b(*fail);
3445 }
3446
3447 // A generic CAS; success or failure is in the EQ flag. A weak CAS
3448 // doesn't retry and may fail spuriously. If the oldval is wanted,
3449 // Pass a register for the result, otherwise pass noreg.
3450
3451 // Clobbers rscratch1
3452 void MacroAssembler::cmpxchg(Register addr, Register expected,
3453 Register new_val,
3454 enum operand_size size,
3455 bool acquire, bool release,
3456 bool weak,
3457 Register result) {
3458 if (result == noreg) result = rscratch1;
3459 BLOCK_COMMENT("cmpxchg {");
3460 if (UseLSE) {
3461 mov(result, expected);
3462 lse_cas(result, new_val, addr, size, acquire, release, /*not_pair*/ true);
3463 compare_eq(result, expected, size);
3464 #ifdef ASSERT
3465 // Poison rscratch1 which is written on !UseLSE branch
3466 mov(rscratch1, 0x1f1f1f1f1f1f1f1f);
3467 #endif
3468 } else {
3469 Label retry_load, done;
3470 prfm(Address(addr), PSTL1STRM);
3471 bind(retry_load);
3472 load_exclusive(result, addr, size, acquire);
3473 compare_eq(result, expected, size);
3474 br(Assembler::NE, done);
3475 store_exclusive(rscratch1, new_val, addr, size, release);
3476 if (weak) {
3477 cmpw(rscratch1, 0u); // If the store fails, return NE to our caller.
3478 } else {
3479 cbnzw(rscratch1, retry_load);
3480 }
3481 bind(done);
3482 }
3483 BLOCK_COMMENT("} cmpxchg");
3484 }
3485
3486 // A generic comparison. Only compares for equality, clobbers rscratch1.
3487 void MacroAssembler::compare_eq(Register rm, Register rn, enum operand_size size) {
3488 if (size == xword) {
3489 cmp(rm, rn);
3490 } else if (size == word) {
3491 cmpw(rm, rn);
3492 } else if (size == halfword) {
3493 eorw(rscratch1, rm, rn);
3494 ands(zr, rscratch1, 0xffff);
3495 } else if (size == byte) {
3496 eorw(rscratch1, rm, rn);
3497 ands(zr, rscratch1, 0xff);
3498 } else {
3499 ShouldNotReachHere();
3500 }
3501 }
3502
3503
3504 static bool different(Register a, RegisterOrConstant b, Register c) {
3505 if (b.is_constant())
3506 return a != c;
3507 else
3508 return a != b.as_register() && a != c && b.as_register() != c;
3509 }
3510
3511 #define ATOMIC_OP(NAME, LDXR, OP, IOP, AOP, STXR, sz) \
3512 void MacroAssembler::atomic_##NAME(Register prev, RegisterOrConstant incr, Register addr) { \
3513 if (UseLSE) { \
3514 prev = prev->is_valid() ? prev : zr; \
3515 if (incr.is_register()) { \
3516 AOP(sz, incr.as_register(), prev, addr); \
3517 } else { \
3518 mov(rscratch2, incr.as_constant()); \
3519 AOP(sz, rscratch2, prev, addr); \
3520 } \
3521 return; \
3522 } \
3523 Register result = rscratch2; \
3524 if (prev->is_valid()) \
3525 result = different(prev, incr, addr) ? prev : rscratch2; \
3526 \
3527 Label retry_load; \
3528 prfm(Address(addr), PSTL1STRM); \
3529 bind(retry_load); \
3530 LDXR(result, addr); \
3531 OP(rscratch1, result, incr); \
3532 STXR(rscratch2, rscratch1, addr); \
3533 cbnzw(rscratch2, retry_load); \
3534 if (prev->is_valid() && prev != result) { \
3535 IOP(prev, rscratch1, incr); \
3536 } \
3537 }
3538
3539 ATOMIC_OP(add, ldxr, add, sub, ldadd, stxr, Assembler::xword)
3540 ATOMIC_OP(addw, ldxrw, addw, subw, ldadd, stxrw, Assembler::word)
3541 ATOMIC_OP(addal, ldaxr, add, sub, ldaddal, stlxr, Assembler::xword)
3542 ATOMIC_OP(addalw, ldaxrw, addw, subw, ldaddal, stlxrw, Assembler::word)
3543
3544 #undef ATOMIC_OP
3545
3546 #define ATOMIC_XCHG(OP, AOP, LDXR, STXR, sz) \
3547 void MacroAssembler::atomic_##OP(Register prev, Register newv, Register addr) { \
3548 if (UseLSE) { \
3549 prev = prev->is_valid() ? prev : zr; \
3550 AOP(sz, newv, prev, addr); \
3551 return; \
3552 } \
3553 Register result = rscratch2; \
3554 if (prev->is_valid()) \
3555 result = different(prev, newv, addr) ? prev : rscratch2; \
3556 \
3557 Label retry_load; \
3558 prfm(Address(addr), PSTL1STRM); \
3559 bind(retry_load); \
3560 LDXR(result, addr); \
3561 STXR(rscratch1, newv, addr); \
3562 cbnzw(rscratch1, retry_load); \
3563 if (prev->is_valid() && prev != result) \
3564 mov(prev, result); \
3565 }
3566
3567 ATOMIC_XCHG(xchg, swp, ldxr, stxr, Assembler::xword)
3568 ATOMIC_XCHG(xchgw, swp, ldxrw, stxrw, Assembler::word)
3569 ATOMIC_XCHG(xchgl, swpl, ldxr, stlxr, Assembler::xword)
3570 ATOMIC_XCHG(xchglw, swpl, ldxrw, stlxrw, Assembler::word)
3571 ATOMIC_XCHG(xchgal, swpal, ldaxr, stlxr, Assembler::xword)
3572 ATOMIC_XCHG(xchgalw, swpal, ldaxrw, stlxrw, Assembler::word)
3573
3574 #undef ATOMIC_XCHG
3575
3576 #ifndef PRODUCT
3577 extern "C" void findpc(intptr_t x);
3578 #endif
3579
3580 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[])
3581 {
3582 // In order to get locks to work, we need to fake a in_VM state
3583 if (ShowMessageBoxOnError ) {
3584 JavaThread* thread = JavaThread::current();
3585 JavaThreadState saved_state = thread->thread_state();
3586 thread->set_thread_state(_thread_in_vm);
3587 #ifndef PRODUCT
3588 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
3589 ttyLocker ttyl;
3590 BytecodeCounter::print();
3591 }
3592 #endif
3593 if (os::message_box(msg, "Execution stopped, print registers?")) {
3594 ttyLocker ttyl;
3595 tty->print_cr(" pc = 0x%016" PRIx64, pc);
3596 #ifndef PRODUCT
3597 tty->cr();
3598 findpc(pc);
3599 tty->cr();
3600 #endif
3601 tty->print_cr(" r0 = 0x%016" PRIx64, regs[0]);
3602 tty->print_cr(" r1 = 0x%016" PRIx64, regs[1]);
3603 tty->print_cr(" r2 = 0x%016" PRIx64, regs[2]);
3604 tty->print_cr(" r3 = 0x%016" PRIx64, regs[3]);
3605 tty->print_cr(" r4 = 0x%016" PRIx64, regs[4]);
3606 tty->print_cr(" r5 = 0x%016" PRIx64, regs[5]);
3607 tty->print_cr(" r6 = 0x%016" PRIx64, regs[6]);
3608 tty->print_cr(" r7 = 0x%016" PRIx64, regs[7]);
3609 tty->print_cr(" r8 = 0x%016" PRIx64, regs[8]);
3610 tty->print_cr(" r9 = 0x%016" PRIx64, regs[9]);
3611 tty->print_cr("r10 = 0x%016" PRIx64, regs[10]);
3612 tty->print_cr("r11 = 0x%016" PRIx64, regs[11]);
3613 tty->print_cr("r12 = 0x%016" PRIx64, regs[12]);
3614 tty->print_cr("r13 = 0x%016" PRIx64, regs[13]);
3615 tty->print_cr("r14 = 0x%016" PRIx64, regs[14]);
3616 tty->print_cr("r15 = 0x%016" PRIx64, regs[15]);
3617 tty->print_cr("r16 = 0x%016" PRIx64, regs[16]);
3618 tty->print_cr("r17 = 0x%016" PRIx64, regs[17]);
3619 tty->print_cr("r18 = 0x%016" PRIx64, regs[18]);
3620 tty->print_cr("r19 = 0x%016" PRIx64, regs[19]);
3621 tty->print_cr("r20 = 0x%016" PRIx64, regs[20]);
3622 tty->print_cr("r21 = 0x%016" PRIx64, regs[21]);
3623 tty->print_cr("r22 = 0x%016" PRIx64, regs[22]);
3624 tty->print_cr("r23 = 0x%016" PRIx64, regs[23]);
3625 tty->print_cr("r24 = 0x%016" PRIx64, regs[24]);
3626 tty->print_cr("r25 = 0x%016" PRIx64, regs[25]);
3627 tty->print_cr("r26 = 0x%016" PRIx64, regs[26]);
3628 tty->print_cr("r27 = 0x%016" PRIx64, regs[27]);
3629 tty->print_cr("r28 = 0x%016" PRIx64, regs[28]);
3630 tty->print_cr("r30 = 0x%016" PRIx64, regs[30]);
3631 tty->print_cr("r31 = 0x%016" PRIx64, regs[31]);
3632 BREAKPOINT;
3633 }
3634 }
3635 fatal("DEBUG MESSAGE: %s", msg);
3636 }
3637
3638 RegSet MacroAssembler::call_clobbered_gp_registers() {
3639 RegSet regs = RegSet::range(r0, r17) - RegSet::of(rscratch1, rscratch2);
3640 #ifndef R18_RESERVED
3641 regs += r18_tls;
3642 #endif
3643 return regs;
3644 }
3645
3646 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude) {
3647 int step = 4 * wordSize;
3648 push(call_clobbered_gp_registers() - exclude, sp);
3649 sub(sp, sp, step);
3650 mov(rscratch1, -step);
3651 // Push v0-v7, v16-v31.
3652 for (int i = 31; i>= 4; i -= 4) {
3653 if (i <= v7->encoding() || i >= v16->encoding())
3654 st1(as_FloatRegister(i-3), as_FloatRegister(i-2), as_FloatRegister(i-1),
3655 as_FloatRegister(i), T1D, Address(post(sp, rscratch1)));
3656 }
3657 st1(as_FloatRegister(0), as_FloatRegister(1), as_FloatRegister(2),
3658 as_FloatRegister(3), T1D, Address(sp));
3659 }
3660
3661 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude) {
3662 for (int i = 0; i < 32; i += 4) {
3663 if (i <= v7->encoding() || i >= v16->encoding())
3664 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3665 as_FloatRegister(i+3), T1D, Address(post(sp, 4 * wordSize)));
3666 }
3667
3668 reinitialize_ptrue();
3669
3670 pop(call_clobbered_gp_registers() - exclude, sp);
3671 }
3672
3673 void MacroAssembler::push_CPU_state(bool save_vectors, bool use_sve,
3674 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3675 push(RegSet::range(r0, r29), sp); // integer registers except lr & sp
3676 if (save_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3677 sub(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3678 for (int i = 0; i < FloatRegister::number_of_registers; i++) {
3679 sve_str(as_FloatRegister(i), Address(sp, i));
3680 }
3681 } else {
3682 int step = (save_vectors ? 8 : 4) * wordSize;
3683 mov(rscratch1, -step);
3684 sub(sp, sp, step);
3685 for (int i = 28; i >= 4; i -= 4) {
3686 st1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3687 as_FloatRegister(i+3), save_vectors ? T2D : T1D, Address(post(sp, rscratch1)));
3688 }
3689 st1(v0, v1, v2, v3, save_vectors ? T2D : T1D, sp);
3690 }
3691 if (save_vectors && use_sve && total_predicate_in_bytes > 0) {
3692 sub(sp, sp, total_predicate_in_bytes);
3693 for (int i = 0; i < PRegister::number_of_registers; i++) {
3694 sve_str(as_PRegister(i), Address(sp, i));
3695 }
3696 }
3697 }
3698
3699 void MacroAssembler::pop_CPU_state(bool restore_vectors, bool use_sve,
3700 int sve_vector_size_in_bytes, int total_predicate_in_bytes) {
3701 if (restore_vectors && use_sve && total_predicate_in_bytes > 0) {
3702 for (int i = PRegister::number_of_registers - 1; i >= 0; i--) {
3703 sve_ldr(as_PRegister(i), Address(sp, i));
3704 }
3705 add(sp, sp, total_predicate_in_bytes);
3706 }
3707 if (restore_vectors && use_sve && sve_vector_size_in_bytes > 16) {
3708 for (int i = FloatRegister::number_of_registers - 1; i >= 0; i--) {
3709 sve_ldr(as_FloatRegister(i), Address(sp, i));
3710 }
3711 add(sp, sp, sve_vector_size_in_bytes * FloatRegister::number_of_registers);
3712 } else {
3713 int step = (restore_vectors ? 8 : 4) * wordSize;
3714 for (int i = 0; i <= 28; i += 4)
3715 ld1(as_FloatRegister(i), as_FloatRegister(i+1), as_FloatRegister(i+2),
3716 as_FloatRegister(i+3), restore_vectors ? T2D : T1D, Address(post(sp, step)));
3717 }
3718
3719 // We may use predicate registers and rely on ptrue with SVE,
3720 // regardless of wide vector (> 8 bytes) used or not.
3721 if (use_sve) {
3722 reinitialize_ptrue();
3723 }
3724
3725 // integer registers except lr & sp
3726 pop(RegSet::range(r0, r17), sp);
3727 #ifdef R18_RESERVED
3728 ldp(zr, r19, Address(post(sp, 2 * wordSize)));
3729 pop(RegSet::range(r20, r29), sp);
3730 #else
3731 pop(RegSet::range(r18_tls, r29), sp);
3732 #endif
3733 }
3734
3735 /**
3736 * Helpers for multiply_to_len().
3737 */
3738 void MacroAssembler::add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
3739 Register src1, Register src2) {
3740 adds(dest_lo, dest_lo, src1);
3741 adc(dest_hi, dest_hi, zr);
3742 adds(dest_lo, dest_lo, src2);
3743 adc(final_dest_hi, dest_hi, zr);
3744 }
3745
3746 // Generate an address from (r + r1 extend offset). "size" is the
3747 // size of the operand. The result may be in rscratch2.
3748 Address MacroAssembler::offsetted_address(Register r, Register r1,
3749 Address::extend ext, int offset, int size) {
3750 if (offset || (ext.shift() % size != 0)) {
3751 lea(rscratch2, Address(r, r1, ext));
3752 return Address(rscratch2, offset);
3753 } else {
3754 return Address(r, r1, ext);
3755 }
3756 }
3757
3758 Address MacroAssembler::spill_address(int size, int offset, Register tmp)
3759 {
3760 assert(offset >= 0, "spill to negative address?");
3761 // Offset reachable ?
3762 // Not aligned - 9 bits signed offset
3763 // Aligned - 12 bits unsigned offset shifted
3764 Register base = sp;
3765 if ((offset & (size-1)) && offset >= (1<<8)) {
3766 add(tmp, base, offset & ((1<<12)-1));
3767 base = tmp;
3768 offset &= -1u<<12;
3769 }
3770
3771 if (offset >= (1<<12) * size) {
3772 add(tmp, base, offset & (((1<<12)-1)<<12));
3773 base = tmp;
3774 offset &= ~(((1<<12)-1)<<12);
3775 }
3776
3777 return Address(base, offset);
3778 }
3779
3780 Address MacroAssembler::sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp) {
3781 assert(offset >= 0, "spill to negative address?");
3782
3783 Register base = sp;
3784
3785 // An immediate offset in the range 0 to 255 which is multiplied
3786 // by the current vector or predicate register size in bytes.
3787 if (offset % sve_reg_size_in_bytes == 0 && offset < ((1<<8)*sve_reg_size_in_bytes)) {
3788 return Address(base, offset / sve_reg_size_in_bytes);
3789 }
3790
3791 add(tmp, base, offset);
3792 return Address(tmp);
3793 }
3794
3795 // Checks whether offset is aligned.
3796 // Returns true if it is, else false.
3797 bool MacroAssembler::merge_alignment_check(Register base,
3798 size_t size,
3799 int64_t cur_offset,
3800 int64_t prev_offset) const {
3801 if (AvoidUnalignedAccesses) {
3802 if (base == sp) {
3803 // Checks whether low offset if aligned to pair of registers.
3804 int64_t pair_mask = size * 2 - 1;
3805 int64_t offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3806 return (offset & pair_mask) == 0;
3807 } else { // If base is not sp, we can't guarantee the access is aligned.
3808 return false;
3809 }
3810 } else {
3811 int64_t mask = size - 1;
3812 // Load/store pair instruction only supports element size aligned offset.
3813 return (cur_offset & mask) == 0 && (prev_offset & mask) == 0;
3814 }
3815 }
3816
3817 // Checks whether current and previous loads/stores can be merged.
3818 // Returns true if it can be merged, else false.
3819 bool MacroAssembler::ldst_can_merge(Register rt,
3820 const Address &adr,
3821 size_t cur_size_in_bytes,
3822 bool is_store) const {
3823 address prev = pc() - NativeInstruction::instruction_size;
3824 address last = code()->last_insn();
3825
3826 if (last == nullptr || !nativeInstruction_at(last)->is_Imm_LdSt()) {
3827 return false;
3828 }
3829
3830 if (adr.getMode() != Address::base_plus_offset || prev != last) {
3831 return false;
3832 }
3833
3834 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3835 size_t prev_size_in_bytes = prev_ldst->size_in_bytes();
3836
3837 assert(prev_size_in_bytes == 4 || prev_size_in_bytes == 8, "only supports 64/32bit merging.");
3838 assert(cur_size_in_bytes == 4 || cur_size_in_bytes == 8, "only supports 64/32bit merging.");
3839
3840 if (cur_size_in_bytes != prev_size_in_bytes || is_store != prev_ldst->is_store()) {
3841 return false;
3842 }
3843
3844 int64_t max_offset = 63 * prev_size_in_bytes;
3845 int64_t min_offset = -64 * prev_size_in_bytes;
3846
3847 assert(prev_ldst->is_not_pre_post_index(), "pre-index or post-index is not supported to be merged.");
3848
3849 // Only same base can be merged.
3850 if (adr.base() != prev_ldst->base()) {
3851 return false;
3852 }
3853
3854 int64_t cur_offset = adr.offset();
3855 int64_t prev_offset = prev_ldst->offset();
3856 size_t diff = abs(cur_offset - prev_offset);
3857 if (diff != prev_size_in_bytes) {
3858 return false;
3859 }
3860
3861 // Following cases can not be merged:
3862 // ldr x2, [x2, #8]
3863 // ldr x3, [x2, #16]
3864 // or:
3865 // ldr x2, [x3, #8]
3866 // ldr x2, [x3, #16]
3867 // If t1 and t2 is the same in "ldp t1, t2, [xn, #imm]", we'll get SIGILL.
3868 if (!is_store && (adr.base() == prev_ldst->target() || rt == prev_ldst->target())) {
3869 return false;
3870 }
3871
3872 int64_t low_offset = prev_offset > cur_offset ? cur_offset : prev_offset;
3873 // Offset range must be in ldp/stp instruction's range.
3874 if (low_offset > max_offset || low_offset < min_offset) {
3875 return false;
3876 }
3877
3878 if (merge_alignment_check(adr.base(), prev_size_in_bytes, cur_offset, prev_offset)) {
3879 return true;
3880 }
3881
3882 return false;
3883 }
3884
3885 // Merge current load/store with previous load/store into ldp/stp.
3886 void MacroAssembler::merge_ldst(Register rt,
3887 const Address &adr,
3888 size_t cur_size_in_bytes,
3889 bool is_store) {
3890
3891 assert(ldst_can_merge(rt, adr, cur_size_in_bytes, is_store) == true, "cur and prev must be able to be merged.");
3892
3893 Register rt_low, rt_high;
3894 address prev = pc() - NativeInstruction::instruction_size;
3895 NativeLdSt* prev_ldst = NativeLdSt_at(prev);
3896
3897 int64_t offset;
3898
3899 if (adr.offset() < prev_ldst->offset()) {
3900 offset = adr.offset();
3901 rt_low = rt;
3902 rt_high = prev_ldst->target();
3903 } else {
3904 offset = prev_ldst->offset();
3905 rt_low = prev_ldst->target();
3906 rt_high = rt;
3907 }
3908
3909 Address adr_p = Address(prev_ldst->base(), offset);
3910 // Overwrite previous generated binary.
3911 code_section()->set_end(prev);
3912
3913 const size_t sz = prev_ldst->size_in_bytes();
3914 assert(sz == 8 || sz == 4, "only supports 64/32bit merging.");
3915 if (!is_store) {
3916 BLOCK_COMMENT("merged ldr pair");
3917 if (sz == 8) {
3918 ldp(rt_low, rt_high, adr_p);
3919 } else {
3920 ldpw(rt_low, rt_high, adr_p);
3921 }
3922 } else {
3923 BLOCK_COMMENT("merged str pair");
3924 if (sz == 8) {
3925 stp(rt_low, rt_high, adr_p);
3926 } else {
3927 stpw(rt_low, rt_high, adr_p);
3928 }
3929 }
3930 }
3931
3932 /**
3933 * Multiply 64 bit by 64 bit first loop.
3934 */
3935 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
3936 Register y, Register y_idx, Register z,
3937 Register carry, Register product,
3938 Register idx, Register kdx) {
3939 //
3940 // jlong carry, x[], y[], z[];
3941 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
3942 // huge_128 product = y[idx] * x[xstart] + carry;
3943 // z[kdx] = (jlong)product;
3944 // carry = (jlong)(product >>> 64);
3945 // }
3946 // z[xstart] = carry;
3947 //
3948
3949 Label L_first_loop, L_first_loop_exit;
3950 Label L_one_x, L_one_y, L_multiply;
3951
3952 subsw(xstart, xstart, 1);
3953 br(Assembler::MI, L_one_x);
3954
3955 lea(rscratch1, Address(x, xstart, Address::lsl(LogBytesPerInt)));
3956 ldr(x_xstart, Address(rscratch1));
3957 ror(x_xstart, x_xstart, 32); // convert big-endian to little-endian
3958
3959 bind(L_first_loop);
3960 subsw(idx, idx, 1);
3961 br(Assembler::MI, L_first_loop_exit);
3962 subsw(idx, idx, 1);
3963 br(Assembler::MI, L_one_y);
3964 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
3965 ldr(y_idx, Address(rscratch1));
3966 ror(y_idx, y_idx, 32); // convert big-endian to little-endian
3967 bind(L_multiply);
3968
3969 // AArch64 has a multiply-accumulate instruction that we can't use
3970 // here because it has no way to process carries, so we have to use
3971 // separate add and adc instructions. Bah.
3972 umulh(rscratch1, x_xstart, y_idx); // x_xstart * y_idx -> rscratch1:product
3973 mul(product, x_xstart, y_idx);
3974 adds(product, product, carry);
3975 adc(carry, rscratch1, zr); // x_xstart * y_idx + carry -> carry:product
3976
3977 subw(kdx, kdx, 2);
3978 ror(product, product, 32); // back to big-endian
3979 str(product, offsetted_address(z, kdx, Address::uxtw(LogBytesPerInt), 0, BytesPerLong));
3980
3981 b(L_first_loop);
3982
3983 bind(L_one_y);
3984 ldrw(y_idx, Address(y, 0));
3985 b(L_multiply);
3986
3987 bind(L_one_x);
3988 ldrw(x_xstart, Address(x, 0));
3989 b(L_first_loop);
3990
3991 bind(L_first_loop_exit);
3992 }
3993
3994 /**
3995 * Multiply 128 bit by 128. Unrolled inner loop.
3996 *
3997 */
3998 void MacroAssembler::multiply_128_x_128_loop(Register y, Register z,
3999 Register carry, Register carry2,
4000 Register idx, Register jdx,
4001 Register yz_idx1, Register yz_idx2,
4002 Register tmp, Register tmp3, Register tmp4,
4003 Register tmp6, Register product_hi) {
4004
4005 // jlong carry, x[], y[], z[];
4006 // int kdx = ystart+1;
4007 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
4008 // huge_128 tmp3 = (y[idx+1] * product_hi) + z[kdx+idx+1] + carry;
4009 // jlong carry2 = (jlong)(tmp3 >>> 64);
4010 // huge_128 tmp4 = (y[idx] * product_hi) + z[kdx+idx] + carry2;
4011 // carry = (jlong)(tmp4 >>> 64);
4012 // z[kdx+idx+1] = (jlong)tmp3;
4013 // z[kdx+idx] = (jlong)tmp4;
4014 // }
4015 // idx += 2;
4016 // if (idx > 0) {
4017 // yz_idx1 = (y[idx] * product_hi) + z[kdx+idx] + carry;
4018 // z[kdx+idx] = (jlong)yz_idx1;
4019 // carry = (jlong)(yz_idx1 >>> 64);
4020 // }
4021 //
4022
4023 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
4024
4025 lsrw(jdx, idx, 2);
4026
4027 bind(L_third_loop);
4028
4029 subsw(jdx, jdx, 1);
4030 br(Assembler::MI, L_third_loop_exit);
4031 subw(idx, idx, 4);
4032
4033 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4034
4035 ldp(yz_idx2, yz_idx1, Address(rscratch1, 0));
4036
4037 lea(tmp6, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4038
4039 ror(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
4040 ror(yz_idx2, yz_idx2, 32);
4041
4042 ldp(rscratch2, rscratch1, Address(tmp6, 0));
4043
4044 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4045 umulh(tmp4, product_hi, yz_idx1);
4046
4047 ror(rscratch1, rscratch1, 32); // convert big-endian to little-endian
4048 ror(rscratch2, rscratch2, 32);
4049
4050 mul(tmp, product_hi, yz_idx2); // yz_idx2 * product_hi -> carry2:tmp
4051 umulh(carry2, product_hi, yz_idx2);
4052
4053 // propagate sum of both multiplications into carry:tmp4:tmp3
4054 adds(tmp3, tmp3, carry);
4055 adc(tmp4, tmp4, zr);
4056 adds(tmp3, tmp3, rscratch1);
4057 adcs(tmp4, tmp4, tmp);
4058 adc(carry, carry2, zr);
4059 adds(tmp4, tmp4, rscratch2);
4060 adc(carry, carry, zr);
4061
4062 ror(tmp3, tmp3, 32); // convert little-endian to big-endian
4063 ror(tmp4, tmp4, 32);
4064 stp(tmp4, tmp3, Address(tmp6, 0));
4065
4066 b(L_third_loop);
4067 bind (L_third_loop_exit);
4068
4069 andw (idx, idx, 0x3);
4070 cbz(idx, L_post_third_loop_done);
4071
4072 Label L_check_1;
4073 subsw(idx, idx, 2);
4074 br(Assembler::MI, L_check_1);
4075
4076 lea(rscratch1, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4077 ldr(yz_idx1, Address(rscratch1, 0));
4078 ror(yz_idx1, yz_idx1, 32);
4079 mul(tmp3, product_hi, yz_idx1); // yz_idx1 * product_hi -> tmp4:tmp3
4080 umulh(tmp4, product_hi, yz_idx1);
4081 lea(rscratch1, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4082 ldr(yz_idx2, Address(rscratch1, 0));
4083 ror(yz_idx2, yz_idx2, 32);
4084
4085 add2_with_carry(carry, tmp4, tmp3, carry, yz_idx2);
4086
4087 ror(tmp3, tmp3, 32);
4088 str(tmp3, Address(rscratch1, 0));
4089
4090 bind (L_check_1);
4091
4092 andw (idx, idx, 0x1);
4093 subsw(idx, idx, 1);
4094 br(Assembler::MI, L_post_third_loop_done);
4095 ldrw(tmp4, Address(y, idx, Address::uxtw(LogBytesPerInt)));
4096 mul(tmp3, tmp4, product_hi); // tmp4 * product_hi -> carry2:tmp3
4097 umulh(carry2, tmp4, product_hi);
4098 ldrw(tmp4, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4099
4100 add2_with_carry(carry2, tmp3, tmp4, carry);
4101
4102 strw(tmp3, Address(z, idx, Address::uxtw(LogBytesPerInt)));
4103 extr(carry, carry2, tmp3, 32);
4104
4105 bind(L_post_third_loop_done);
4106 }
4107
4108 /**
4109 * Code for BigInteger::multiplyToLen() intrinsic.
4110 *
4111 * r0: x
4112 * r1: xlen
4113 * r2: y
4114 * r3: ylen
4115 * r4: z
4116 * r5: tmp0
4117 * r10: tmp1
4118 * r11: tmp2
4119 * r12: tmp3
4120 * r13: tmp4
4121 * r14: tmp5
4122 * r15: tmp6
4123 * r16: tmp7
4124 *
4125 */
4126 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen,
4127 Register z, Register tmp0,
4128 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
4129 Register tmp5, Register tmp6, Register product_hi) {
4130
4131 assert_different_registers(x, xlen, y, ylen, z, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5, tmp6, product_hi);
4132
4133 const Register idx = tmp1;
4134 const Register kdx = tmp2;
4135 const Register xstart = tmp3;
4136
4137 const Register y_idx = tmp4;
4138 const Register carry = tmp5;
4139 const Register product = xlen;
4140 const Register x_xstart = tmp0;
4141
4142 // First Loop.
4143 //
4144 // final static long LONG_MASK = 0xffffffffL;
4145 // int xstart = xlen - 1;
4146 // int ystart = ylen - 1;
4147 // long carry = 0;
4148 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
4149 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
4150 // z[kdx] = (int)product;
4151 // carry = product >>> 32;
4152 // }
4153 // z[xstart] = (int)carry;
4154 //
4155
4156 movw(idx, ylen); // idx = ylen;
4157 addw(kdx, xlen, ylen); // kdx = xlen+ylen;
4158 mov(carry, zr); // carry = 0;
4159
4160 Label L_done;
4161
4162 movw(xstart, xlen);
4163 subsw(xstart, xstart, 1);
4164 br(Assembler::MI, L_done);
4165
4166 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
4167
4168 Label L_second_loop;
4169 cbzw(kdx, L_second_loop);
4170
4171 Label L_carry;
4172 subw(kdx, kdx, 1);
4173 cbzw(kdx, L_carry);
4174
4175 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4176 lsr(carry, carry, 32);
4177 subw(kdx, kdx, 1);
4178
4179 bind(L_carry);
4180 strw(carry, Address(z, kdx, Address::uxtw(LogBytesPerInt)));
4181
4182 // Second and third (nested) loops.
4183 //
4184 // for (int i = xstart-1; i >= 0; i--) { // Second loop
4185 // carry = 0;
4186 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
4187 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
4188 // (z[k] & LONG_MASK) + carry;
4189 // z[k] = (int)product;
4190 // carry = product >>> 32;
4191 // }
4192 // z[i] = (int)carry;
4193 // }
4194 //
4195 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = product_hi
4196
4197 const Register jdx = tmp1;
4198
4199 bind(L_second_loop);
4200 mov(carry, zr); // carry = 0;
4201 movw(jdx, ylen); // j = ystart+1
4202
4203 subsw(xstart, xstart, 1); // i = xstart-1;
4204 br(Assembler::MI, L_done);
4205
4206 str(z, Address(pre(sp, -4 * wordSize)));
4207
4208 Label L_last_x;
4209 lea(z, offsetted_address(z, xstart, Address::uxtw(LogBytesPerInt), 4, BytesPerInt)); // z = z + k - j
4210 subsw(xstart, xstart, 1); // i = xstart-1;
4211 br(Assembler::MI, L_last_x);
4212
4213 lea(rscratch1, Address(x, xstart, Address::uxtw(LogBytesPerInt)));
4214 ldr(product_hi, Address(rscratch1));
4215 ror(product_hi, product_hi, 32); // convert big-endian to little-endian
4216
4217 Label L_third_loop_prologue;
4218 bind(L_third_loop_prologue);
4219
4220 str(ylen, Address(sp, wordSize));
4221 stp(x, xstart, Address(sp, 2 * wordSize));
4222 multiply_128_x_128_loop(y, z, carry, x, jdx, ylen, product,
4223 tmp2, x_xstart, tmp3, tmp4, tmp6, product_hi);
4224 ldp(z, ylen, Address(post(sp, 2 * wordSize)));
4225 ldp(x, xlen, Address(post(sp, 2 * wordSize))); // copy old xstart -> xlen
4226
4227 addw(tmp3, xlen, 1);
4228 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4229 subsw(tmp3, tmp3, 1);
4230 br(Assembler::MI, L_done);
4231
4232 lsr(carry, carry, 32);
4233 strw(carry, Address(z, tmp3, Address::uxtw(LogBytesPerInt)));
4234 b(L_second_loop);
4235
4236 // Next infrequent code is moved outside loops.
4237 bind(L_last_x);
4238 ldrw(product_hi, Address(x, 0));
4239 b(L_third_loop_prologue);
4240
4241 bind(L_done);
4242 }
4243
4244 // Code for BigInteger::mulAdd intrinsic
4245 // out = r0
4246 // in = r1
4247 // offset = r2 (already out.length-offset)
4248 // len = r3
4249 // k = r4
4250 //
4251 // pseudo code from java implementation:
4252 // carry = 0;
4253 // offset = out.length-offset - 1;
4254 // for (int j=len-1; j >= 0; j--) {
4255 // product = (in[j] & LONG_MASK) * kLong + (out[offset] & LONG_MASK) + carry;
4256 // out[offset--] = (int)product;
4257 // carry = product >>> 32;
4258 // }
4259 // return (int)carry;
4260 void MacroAssembler::mul_add(Register out, Register in, Register offset,
4261 Register len, Register k) {
4262 Label LOOP, END;
4263 // pre-loop
4264 cmp(len, zr); // cmp, not cbz/cbnz: to use condition twice => less branches
4265 csel(out, zr, out, Assembler::EQ);
4266 br(Assembler::EQ, END);
4267 add(in, in, len, LSL, 2); // in[j+1] address
4268 add(offset, out, offset, LSL, 2); // out[offset + 1] address
4269 mov(out, zr); // used to keep carry now
4270 BIND(LOOP);
4271 ldrw(rscratch1, Address(pre(in, -4)));
4272 madd(rscratch1, rscratch1, k, out);
4273 ldrw(rscratch2, Address(pre(offset, -4)));
4274 add(rscratch1, rscratch1, rscratch2);
4275 strw(rscratch1, Address(offset));
4276 lsr(out, rscratch1, 32);
4277 subs(len, len, 1);
4278 br(Assembler::NE, LOOP);
4279 BIND(END);
4280 }
4281
4282 /**
4283 * Emits code to update CRC-32 with a byte value according to constants in table
4284 *
4285 * @param [in,out]crc Register containing the crc.
4286 * @param [in]val Register containing the byte to fold into the CRC.
4287 * @param [in]table Register containing the table of crc constants.
4288 *
4289 * uint32_t crc;
4290 * val = crc_table[(val ^ crc) & 0xFF];
4291 * crc = val ^ (crc >> 8);
4292 *
4293 */
4294 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
4295 eor(val, val, crc);
4296 andr(val, val, 0xff);
4297 ldrw(val, Address(table, val, Address::lsl(2)));
4298 eor(crc, val, crc, Assembler::LSR, 8);
4299 }
4300
4301 /**
4302 * Emits code to update CRC-32 with a 32-bit value according to tables 0 to 3
4303 *
4304 * @param [in,out]crc Register containing the crc.
4305 * @param [in]v Register containing the 32-bit to fold into the CRC.
4306 * @param [in]table0 Register containing table 0 of crc constants.
4307 * @param [in]table1 Register containing table 1 of crc constants.
4308 * @param [in]table2 Register containing table 2 of crc constants.
4309 * @param [in]table3 Register containing table 3 of crc constants.
4310 *
4311 * uint32_t crc;
4312 * v = crc ^ v
4313 * crc = table3[v&0xff]^table2[(v>>8)&0xff]^table1[(v>>16)&0xff]^table0[v>>24]
4314 *
4315 */
4316 void MacroAssembler::update_word_crc32(Register crc, Register v, Register tmp,
4317 Register table0, Register table1, Register table2, Register table3,
4318 bool upper) {
4319 eor(v, crc, v, upper ? LSR:LSL, upper ? 32:0);
4320 uxtb(tmp, v);
4321 ldrw(crc, Address(table3, tmp, Address::lsl(2)));
4322 ubfx(tmp, v, 8, 8);
4323 ldrw(tmp, Address(table2, tmp, Address::lsl(2)));
4324 eor(crc, crc, tmp);
4325 ubfx(tmp, v, 16, 8);
4326 ldrw(tmp, Address(table1, tmp, Address::lsl(2)));
4327 eor(crc, crc, tmp);
4328 ubfx(tmp, v, 24, 8);
4329 ldrw(tmp, Address(table0, tmp, Address::lsl(2)));
4330 eor(crc, crc, tmp);
4331 }
4332
4333 void MacroAssembler::kernel_crc32_using_crypto_pmull(Register crc, Register buf,
4334 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4335 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4336 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4337
4338 subs(tmp0, len, 384);
4339 mvnw(crc, crc);
4340 br(Assembler::GE, CRC_by128_pre);
4341 BIND(CRC_less128);
4342 subs(len, len, 32);
4343 br(Assembler::GE, CRC_by32_loop);
4344 BIND(CRC_less32);
4345 adds(len, len, 32 - 4);
4346 br(Assembler::GE, CRC_by4_loop);
4347 adds(len, len, 4);
4348 br(Assembler::GT, CRC_by1_loop);
4349 b(L_exit);
4350
4351 BIND(CRC_by32_loop);
4352 ldp(tmp0, tmp1, Address(buf));
4353 crc32x(crc, crc, tmp0);
4354 ldp(tmp2, tmp3, Address(buf, 16));
4355 crc32x(crc, crc, tmp1);
4356 add(buf, buf, 32);
4357 crc32x(crc, crc, tmp2);
4358 subs(len, len, 32);
4359 crc32x(crc, crc, tmp3);
4360 br(Assembler::GE, CRC_by32_loop);
4361 cmn(len, (u1)32);
4362 br(Assembler::NE, CRC_less32);
4363 b(L_exit);
4364
4365 BIND(CRC_by4_loop);
4366 ldrw(tmp0, Address(post(buf, 4)));
4367 subs(len, len, 4);
4368 crc32w(crc, crc, tmp0);
4369 br(Assembler::GE, CRC_by4_loop);
4370 adds(len, len, 4);
4371 br(Assembler::LE, L_exit);
4372 BIND(CRC_by1_loop);
4373 ldrb(tmp0, Address(post(buf, 1)));
4374 subs(len, len, 1);
4375 crc32b(crc, crc, tmp0);
4376 br(Assembler::GT, CRC_by1_loop);
4377 b(L_exit);
4378
4379 BIND(CRC_by128_pre);
4380 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4381 4*256*sizeof(juint) + 8*sizeof(juint));
4382 mov(crc, 0);
4383 crc32x(crc, crc, tmp0);
4384 crc32x(crc, crc, tmp1);
4385
4386 cbnz(len, CRC_less128);
4387
4388 BIND(L_exit);
4389 mvnw(crc, crc);
4390 }
4391
4392 void MacroAssembler::kernel_crc32_using_crc32(Register crc, Register buf,
4393 Register len, Register tmp0, Register tmp1, Register tmp2,
4394 Register tmp3) {
4395 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4396 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4397
4398 mvnw(crc, crc);
4399
4400 subs(len, len, 128);
4401 br(Assembler::GE, CRC_by64_pre);
4402 BIND(CRC_less64);
4403 adds(len, len, 128-32);
4404 br(Assembler::GE, CRC_by32_loop);
4405 BIND(CRC_less32);
4406 adds(len, len, 32-4);
4407 br(Assembler::GE, CRC_by4_loop);
4408 adds(len, len, 4);
4409 br(Assembler::GT, CRC_by1_loop);
4410 b(L_exit);
4411
4412 BIND(CRC_by32_loop);
4413 ldp(tmp0, tmp1, Address(post(buf, 16)));
4414 subs(len, len, 32);
4415 crc32x(crc, crc, tmp0);
4416 ldr(tmp2, Address(post(buf, 8)));
4417 crc32x(crc, crc, tmp1);
4418 ldr(tmp3, Address(post(buf, 8)));
4419 crc32x(crc, crc, tmp2);
4420 crc32x(crc, crc, tmp3);
4421 br(Assembler::GE, CRC_by32_loop);
4422 cmn(len, (u1)32);
4423 br(Assembler::NE, CRC_less32);
4424 b(L_exit);
4425
4426 BIND(CRC_by4_loop);
4427 ldrw(tmp0, Address(post(buf, 4)));
4428 subs(len, len, 4);
4429 crc32w(crc, crc, tmp0);
4430 br(Assembler::GE, CRC_by4_loop);
4431 adds(len, len, 4);
4432 br(Assembler::LE, L_exit);
4433 BIND(CRC_by1_loop);
4434 ldrb(tmp0, Address(post(buf, 1)));
4435 subs(len, len, 1);
4436 crc32b(crc, crc, tmp0);
4437 br(Assembler::GT, CRC_by1_loop);
4438 b(L_exit);
4439
4440 BIND(CRC_by64_pre);
4441 sub(buf, buf, 8);
4442 ldp(tmp0, tmp1, Address(buf, 8));
4443 crc32x(crc, crc, tmp0);
4444 ldr(tmp2, Address(buf, 24));
4445 crc32x(crc, crc, tmp1);
4446 ldr(tmp3, Address(buf, 32));
4447 crc32x(crc, crc, tmp2);
4448 ldr(tmp0, Address(buf, 40));
4449 crc32x(crc, crc, tmp3);
4450 ldr(tmp1, Address(buf, 48));
4451 crc32x(crc, crc, tmp0);
4452 ldr(tmp2, Address(buf, 56));
4453 crc32x(crc, crc, tmp1);
4454 ldr(tmp3, Address(pre(buf, 64)));
4455
4456 b(CRC_by64_loop);
4457
4458 align(CodeEntryAlignment);
4459 BIND(CRC_by64_loop);
4460 subs(len, len, 64);
4461 crc32x(crc, crc, tmp2);
4462 ldr(tmp0, Address(buf, 8));
4463 crc32x(crc, crc, tmp3);
4464 ldr(tmp1, Address(buf, 16));
4465 crc32x(crc, crc, tmp0);
4466 ldr(tmp2, Address(buf, 24));
4467 crc32x(crc, crc, tmp1);
4468 ldr(tmp3, Address(buf, 32));
4469 crc32x(crc, crc, tmp2);
4470 ldr(tmp0, Address(buf, 40));
4471 crc32x(crc, crc, tmp3);
4472 ldr(tmp1, Address(buf, 48));
4473 crc32x(crc, crc, tmp0);
4474 ldr(tmp2, Address(buf, 56));
4475 crc32x(crc, crc, tmp1);
4476 ldr(tmp3, Address(pre(buf, 64)));
4477 br(Assembler::GE, CRC_by64_loop);
4478
4479 // post-loop
4480 crc32x(crc, crc, tmp2);
4481 crc32x(crc, crc, tmp3);
4482
4483 sub(len, len, 64);
4484 add(buf, buf, 8);
4485 cmn(len, (u1)128);
4486 br(Assembler::NE, CRC_less64);
4487 BIND(L_exit);
4488 mvnw(crc, crc);
4489 }
4490
4491 /**
4492 * @param crc register containing existing CRC (32-bit)
4493 * @param buf register pointing to input byte buffer (byte*)
4494 * @param len register containing number of bytes
4495 * @param table register that will contain address of CRC table
4496 * @param tmp scratch register
4497 */
4498 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len,
4499 Register table0, Register table1, Register table2, Register table3,
4500 Register tmp, Register tmp2, Register tmp3) {
4501 Label L_by16, L_by16_loop, L_by4, L_by4_loop, L_by1, L_by1_loop, L_exit;
4502
4503 if (UseCryptoPmullForCRC32) {
4504 kernel_crc32_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4505 return;
4506 }
4507
4508 if (UseCRC32) {
4509 kernel_crc32_using_crc32(crc, buf, len, table0, table1, table2, table3);
4510 return;
4511 }
4512
4513 mvnw(crc, crc);
4514
4515 {
4516 uint64_t offset;
4517 adrp(table0, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4518 add(table0, table0, offset);
4519 }
4520 add(table1, table0, 1*256*sizeof(juint));
4521 add(table2, table0, 2*256*sizeof(juint));
4522 add(table3, table0, 3*256*sizeof(juint));
4523
4524 { // Neon code start
4525 cmp(len, (u1)64);
4526 br(Assembler::LT, L_by16);
4527 eor(v16, T16B, v16, v16);
4528
4529 Label L_fold;
4530
4531 add(tmp, table0, 4*256*sizeof(juint)); // Point at the Neon constants
4532
4533 ld1(v0, v1, T2D, post(buf, 32));
4534 ld1r(v4, T2D, post(tmp, 8));
4535 ld1r(v5, T2D, post(tmp, 8));
4536 ld1r(v6, T2D, post(tmp, 8));
4537 ld1r(v7, T2D, post(tmp, 8));
4538 mov(v16, S, 0, crc);
4539
4540 eor(v0, T16B, v0, v16);
4541 sub(len, len, 64);
4542
4543 BIND(L_fold);
4544 pmull(v22, T8H, v0, v5, T8B);
4545 pmull(v20, T8H, v0, v7, T8B);
4546 pmull(v23, T8H, v0, v4, T8B);
4547 pmull(v21, T8H, v0, v6, T8B);
4548
4549 pmull2(v18, T8H, v0, v5, T16B);
4550 pmull2(v16, T8H, v0, v7, T16B);
4551 pmull2(v19, T8H, v0, v4, T16B);
4552 pmull2(v17, T8H, v0, v6, T16B);
4553
4554 uzp1(v24, T8H, v20, v22);
4555 uzp2(v25, T8H, v20, v22);
4556 eor(v20, T16B, v24, v25);
4557
4558 uzp1(v26, T8H, v16, v18);
4559 uzp2(v27, T8H, v16, v18);
4560 eor(v16, T16B, v26, v27);
4561
4562 ushll2(v22, T4S, v20, T8H, 8);
4563 ushll(v20, T4S, v20, T4H, 8);
4564
4565 ushll2(v18, T4S, v16, T8H, 8);
4566 ushll(v16, T4S, v16, T4H, 8);
4567
4568 eor(v22, T16B, v23, v22);
4569 eor(v18, T16B, v19, v18);
4570 eor(v20, T16B, v21, v20);
4571 eor(v16, T16B, v17, v16);
4572
4573 uzp1(v17, T2D, v16, v20);
4574 uzp2(v21, T2D, v16, v20);
4575 eor(v17, T16B, v17, v21);
4576
4577 ushll2(v20, T2D, v17, T4S, 16);
4578 ushll(v16, T2D, v17, T2S, 16);
4579
4580 eor(v20, T16B, v20, v22);
4581 eor(v16, T16B, v16, v18);
4582
4583 uzp1(v17, T2D, v20, v16);
4584 uzp2(v21, T2D, v20, v16);
4585 eor(v28, T16B, v17, v21);
4586
4587 pmull(v22, T8H, v1, v5, T8B);
4588 pmull(v20, T8H, v1, v7, T8B);
4589 pmull(v23, T8H, v1, v4, T8B);
4590 pmull(v21, T8H, v1, v6, T8B);
4591
4592 pmull2(v18, T8H, v1, v5, T16B);
4593 pmull2(v16, T8H, v1, v7, T16B);
4594 pmull2(v19, T8H, v1, v4, T16B);
4595 pmull2(v17, T8H, v1, v6, T16B);
4596
4597 ld1(v0, v1, T2D, post(buf, 32));
4598
4599 uzp1(v24, T8H, v20, v22);
4600 uzp2(v25, T8H, v20, v22);
4601 eor(v20, T16B, v24, v25);
4602
4603 uzp1(v26, T8H, v16, v18);
4604 uzp2(v27, T8H, v16, v18);
4605 eor(v16, T16B, v26, v27);
4606
4607 ushll2(v22, T4S, v20, T8H, 8);
4608 ushll(v20, T4S, v20, T4H, 8);
4609
4610 ushll2(v18, T4S, v16, T8H, 8);
4611 ushll(v16, T4S, v16, T4H, 8);
4612
4613 eor(v22, T16B, v23, v22);
4614 eor(v18, T16B, v19, v18);
4615 eor(v20, T16B, v21, v20);
4616 eor(v16, T16B, v17, v16);
4617
4618 uzp1(v17, T2D, v16, v20);
4619 uzp2(v21, T2D, v16, v20);
4620 eor(v16, T16B, v17, v21);
4621
4622 ushll2(v20, T2D, v16, T4S, 16);
4623 ushll(v16, T2D, v16, T2S, 16);
4624
4625 eor(v20, T16B, v22, v20);
4626 eor(v16, T16B, v16, v18);
4627
4628 uzp1(v17, T2D, v20, v16);
4629 uzp2(v21, T2D, v20, v16);
4630 eor(v20, T16B, v17, v21);
4631
4632 shl(v16, T2D, v28, 1);
4633 shl(v17, T2D, v20, 1);
4634
4635 eor(v0, T16B, v0, v16);
4636 eor(v1, T16B, v1, v17);
4637
4638 subs(len, len, 32);
4639 br(Assembler::GE, L_fold);
4640
4641 mov(crc, 0);
4642 mov(tmp, v0, D, 0);
4643 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4644 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4645 mov(tmp, v0, D, 1);
4646 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4647 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4648 mov(tmp, v1, D, 0);
4649 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4650 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4651 mov(tmp, v1, D, 1);
4652 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4653 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4654
4655 add(len, len, 32);
4656 } // Neon code end
4657
4658 BIND(L_by16);
4659 subs(len, len, 16);
4660 br(Assembler::GE, L_by16_loop);
4661 adds(len, len, 16-4);
4662 br(Assembler::GE, L_by4_loop);
4663 adds(len, len, 4);
4664 br(Assembler::GT, L_by1_loop);
4665 b(L_exit);
4666
4667 BIND(L_by4_loop);
4668 ldrw(tmp, Address(post(buf, 4)));
4669 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3);
4670 subs(len, len, 4);
4671 br(Assembler::GE, L_by4_loop);
4672 adds(len, len, 4);
4673 br(Assembler::LE, L_exit);
4674 BIND(L_by1_loop);
4675 subs(len, len, 1);
4676 ldrb(tmp, Address(post(buf, 1)));
4677 update_byte_crc32(crc, tmp, table0);
4678 br(Assembler::GT, L_by1_loop);
4679 b(L_exit);
4680
4681 align(CodeEntryAlignment);
4682 BIND(L_by16_loop);
4683 subs(len, len, 16);
4684 ldp(tmp, tmp3, Address(post(buf, 16)));
4685 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, false);
4686 update_word_crc32(crc, tmp, tmp2, table0, table1, table2, table3, true);
4687 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, false);
4688 update_word_crc32(crc, tmp3, tmp2, table0, table1, table2, table3, true);
4689 br(Assembler::GE, L_by16_loop);
4690 adds(len, len, 16-4);
4691 br(Assembler::GE, L_by4_loop);
4692 adds(len, len, 4);
4693 br(Assembler::GT, L_by1_loop);
4694 BIND(L_exit);
4695 mvnw(crc, crc);
4696 }
4697
4698 void MacroAssembler::kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
4699 Register len, Register tmp0, Register tmp1, Register tmp2, Register tmp3) {
4700 Label CRC_by4_loop, CRC_by1_loop, CRC_less128, CRC_by128_pre, CRC_by32_loop, CRC_less32, L_exit;
4701 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4702
4703 subs(tmp0, len, 384);
4704 br(Assembler::GE, CRC_by128_pre);
4705 BIND(CRC_less128);
4706 subs(len, len, 32);
4707 br(Assembler::GE, CRC_by32_loop);
4708 BIND(CRC_less32);
4709 adds(len, len, 32 - 4);
4710 br(Assembler::GE, CRC_by4_loop);
4711 adds(len, len, 4);
4712 br(Assembler::GT, CRC_by1_loop);
4713 b(L_exit);
4714
4715 BIND(CRC_by32_loop);
4716 ldp(tmp0, tmp1, Address(buf));
4717 crc32cx(crc, crc, tmp0);
4718 ldr(tmp2, Address(buf, 16));
4719 crc32cx(crc, crc, tmp1);
4720 ldr(tmp3, Address(buf, 24));
4721 crc32cx(crc, crc, tmp2);
4722 add(buf, buf, 32);
4723 subs(len, len, 32);
4724 crc32cx(crc, crc, tmp3);
4725 br(Assembler::GE, CRC_by32_loop);
4726 cmn(len, (u1)32);
4727 br(Assembler::NE, CRC_less32);
4728 b(L_exit);
4729
4730 BIND(CRC_by4_loop);
4731 ldrw(tmp0, Address(post(buf, 4)));
4732 subs(len, len, 4);
4733 crc32cw(crc, crc, tmp0);
4734 br(Assembler::GE, CRC_by4_loop);
4735 adds(len, len, 4);
4736 br(Assembler::LE, L_exit);
4737 BIND(CRC_by1_loop);
4738 ldrb(tmp0, Address(post(buf, 1)));
4739 subs(len, len, 1);
4740 crc32cb(crc, crc, tmp0);
4741 br(Assembler::GT, CRC_by1_loop);
4742 b(L_exit);
4743
4744 BIND(CRC_by128_pre);
4745 kernel_crc32_common_fold_using_crypto_pmull(crc, buf, len, tmp0, tmp1, tmp2,
4746 4*256*sizeof(juint) + 8*sizeof(juint) + 0x50);
4747 mov(crc, 0);
4748 crc32cx(crc, crc, tmp0);
4749 crc32cx(crc, crc, tmp1);
4750
4751 cbnz(len, CRC_less128);
4752
4753 BIND(L_exit);
4754 }
4755
4756 void MacroAssembler::kernel_crc32c_using_crc32c(Register crc, Register buf,
4757 Register len, Register tmp0, Register tmp1, Register tmp2,
4758 Register tmp3) {
4759 Label CRC_by64_loop, CRC_by4_loop, CRC_by1_loop, CRC_less64, CRC_by64_pre, CRC_by32_loop, CRC_less32, L_exit;
4760 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2, tmp3);
4761
4762 subs(len, len, 128);
4763 br(Assembler::GE, CRC_by64_pre);
4764 BIND(CRC_less64);
4765 adds(len, len, 128-32);
4766 br(Assembler::GE, CRC_by32_loop);
4767 BIND(CRC_less32);
4768 adds(len, len, 32-4);
4769 br(Assembler::GE, CRC_by4_loop);
4770 adds(len, len, 4);
4771 br(Assembler::GT, CRC_by1_loop);
4772 b(L_exit);
4773
4774 BIND(CRC_by32_loop);
4775 ldp(tmp0, tmp1, Address(post(buf, 16)));
4776 subs(len, len, 32);
4777 crc32cx(crc, crc, tmp0);
4778 ldr(tmp2, Address(post(buf, 8)));
4779 crc32cx(crc, crc, tmp1);
4780 ldr(tmp3, Address(post(buf, 8)));
4781 crc32cx(crc, crc, tmp2);
4782 crc32cx(crc, crc, tmp3);
4783 br(Assembler::GE, CRC_by32_loop);
4784 cmn(len, (u1)32);
4785 br(Assembler::NE, CRC_less32);
4786 b(L_exit);
4787
4788 BIND(CRC_by4_loop);
4789 ldrw(tmp0, Address(post(buf, 4)));
4790 subs(len, len, 4);
4791 crc32cw(crc, crc, tmp0);
4792 br(Assembler::GE, CRC_by4_loop);
4793 adds(len, len, 4);
4794 br(Assembler::LE, L_exit);
4795 BIND(CRC_by1_loop);
4796 ldrb(tmp0, Address(post(buf, 1)));
4797 subs(len, len, 1);
4798 crc32cb(crc, crc, tmp0);
4799 br(Assembler::GT, CRC_by1_loop);
4800 b(L_exit);
4801
4802 BIND(CRC_by64_pre);
4803 sub(buf, buf, 8);
4804 ldp(tmp0, tmp1, Address(buf, 8));
4805 crc32cx(crc, crc, tmp0);
4806 ldr(tmp2, Address(buf, 24));
4807 crc32cx(crc, crc, tmp1);
4808 ldr(tmp3, Address(buf, 32));
4809 crc32cx(crc, crc, tmp2);
4810 ldr(tmp0, Address(buf, 40));
4811 crc32cx(crc, crc, tmp3);
4812 ldr(tmp1, Address(buf, 48));
4813 crc32cx(crc, crc, tmp0);
4814 ldr(tmp2, Address(buf, 56));
4815 crc32cx(crc, crc, tmp1);
4816 ldr(tmp3, Address(pre(buf, 64)));
4817
4818 b(CRC_by64_loop);
4819
4820 align(CodeEntryAlignment);
4821 BIND(CRC_by64_loop);
4822 subs(len, len, 64);
4823 crc32cx(crc, crc, tmp2);
4824 ldr(tmp0, Address(buf, 8));
4825 crc32cx(crc, crc, tmp3);
4826 ldr(tmp1, Address(buf, 16));
4827 crc32cx(crc, crc, tmp0);
4828 ldr(tmp2, Address(buf, 24));
4829 crc32cx(crc, crc, tmp1);
4830 ldr(tmp3, Address(buf, 32));
4831 crc32cx(crc, crc, tmp2);
4832 ldr(tmp0, Address(buf, 40));
4833 crc32cx(crc, crc, tmp3);
4834 ldr(tmp1, Address(buf, 48));
4835 crc32cx(crc, crc, tmp0);
4836 ldr(tmp2, Address(buf, 56));
4837 crc32cx(crc, crc, tmp1);
4838 ldr(tmp3, Address(pre(buf, 64)));
4839 br(Assembler::GE, CRC_by64_loop);
4840
4841 // post-loop
4842 crc32cx(crc, crc, tmp2);
4843 crc32cx(crc, crc, tmp3);
4844
4845 sub(len, len, 64);
4846 add(buf, buf, 8);
4847 cmn(len, (u1)128);
4848 br(Assembler::NE, CRC_less64);
4849 BIND(L_exit);
4850 }
4851
4852 /**
4853 * @param crc register containing existing CRC (32-bit)
4854 * @param buf register pointing to input byte buffer (byte*)
4855 * @param len register containing number of bytes
4856 * @param table register that will contain address of CRC table
4857 * @param tmp scratch register
4858 */
4859 void MacroAssembler::kernel_crc32c(Register crc, Register buf, Register len,
4860 Register table0, Register table1, Register table2, Register table3,
4861 Register tmp, Register tmp2, Register tmp3) {
4862 if (UseCryptoPmullForCRC32) {
4863 kernel_crc32c_using_crypto_pmull(crc, buf, len, table0, table1, table2, table3);
4864 } else {
4865 kernel_crc32c_using_crc32c(crc, buf, len, table0, table1, table2, table3);
4866 }
4867 }
4868
4869 void MacroAssembler::kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
4870 Register len, Register tmp0, Register tmp1, Register tmp2, size_t table_offset) {
4871 Label CRC_by128_loop;
4872 assert_different_registers(crc, buf, len, tmp0, tmp1, tmp2);
4873
4874 sub(len, len, 256);
4875 Register table = tmp0;
4876 {
4877 uint64_t offset;
4878 adrp(table, ExternalAddress(StubRoutines::crc_table_addr()), offset);
4879 add(table, table, offset);
4880 }
4881 add(table, table, table_offset);
4882
4883 // Registers v0..v7 are used as data registers.
4884 // Registers v16..v31 are used as tmp registers.
4885 sub(buf, buf, 0x10);
4886 ldrq(v0, Address(buf, 0x10));
4887 ldrq(v1, Address(buf, 0x20));
4888 ldrq(v2, Address(buf, 0x30));
4889 ldrq(v3, Address(buf, 0x40));
4890 ldrq(v4, Address(buf, 0x50));
4891 ldrq(v5, Address(buf, 0x60));
4892 ldrq(v6, Address(buf, 0x70));
4893 ldrq(v7, Address(pre(buf, 0x80)));
4894
4895 movi(v31, T4S, 0);
4896 mov(v31, S, 0, crc);
4897 eor(v0, T16B, v0, v31);
4898
4899 // Register v16 contains constants from the crc table.
4900 ldrq(v16, Address(table));
4901 b(CRC_by128_loop);
4902
4903 align(OptoLoopAlignment);
4904 BIND(CRC_by128_loop);
4905 pmull (v17, T1Q, v0, v16, T1D);
4906 pmull2(v18, T1Q, v0, v16, T2D);
4907 ldrq(v0, Address(buf, 0x10));
4908 eor3(v0, T16B, v17, v18, v0);
4909
4910 pmull (v19, T1Q, v1, v16, T1D);
4911 pmull2(v20, T1Q, v1, v16, T2D);
4912 ldrq(v1, Address(buf, 0x20));
4913 eor3(v1, T16B, v19, v20, v1);
4914
4915 pmull (v21, T1Q, v2, v16, T1D);
4916 pmull2(v22, T1Q, v2, v16, T2D);
4917 ldrq(v2, Address(buf, 0x30));
4918 eor3(v2, T16B, v21, v22, v2);
4919
4920 pmull (v23, T1Q, v3, v16, T1D);
4921 pmull2(v24, T1Q, v3, v16, T2D);
4922 ldrq(v3, Address(buf, 0x40));
4923 eor3(v3, T16B, v23, v24, v3);
4924
4925 pmull (v25, T1Q, v4, v16, T1D);
4926 pmull2(v26, T1Q, v4, v16, T2D);
4927 ldrq(v4, Address(buf, 0x50));
4928 eor3(v4, T16B, v25, v26, v4);
4929
4930 pmull (v27, T1Q, v5, v16, T1D);
4931 pmull2(v28, T1Q, v5, v16, T2D);
4932 ldrq(v5, Address(buf, 0x60));
4933 eor3(v5, T16B, v27, v28, v5);
4934
4935 pmull (v29, T1Q, v6, v16, T1D);
4936 pmull2(v30, T1Q, v6, v16, T2D);
4937 ldrq(v6, Address(buf, 0x70));
4938 eor3(v6, T16B, v29, v30, v6);
4939
4940 // Reuse registers v23, v24.
4941 // Using them won't block the first instruction of the next iteration.
4942 pmull (v23, T1Q, v7, v16, T1D);
4943 pmull2(v24, T1Q, v7, v16, T2D);
4944 ldrq(v7, Address(pre(buf, 0x80)));
4945 eor3(v7, T16B, v23, v24, v7);
4946
4947 subs(len, len, 0x80);
4948 br(Assembler::GE, CRC_by128_loop);
4949
4950 // fold into 512 bits
4951 // Use v31 for constants because v16 can be still in use.
4952 ldrq(v31, Address(table, 0x10));
4953
4954 pmull (v17, T1Q, v0, v31, T1D);
4955 pmull2(v18, T1Q, v0, v31, T2D);
4956 eor3(v0, T16B, v17, v18, v4);
4957
4958 pmull (v19, T1Q, v1, v31, T1D);
4959 pmull2(v20, T1Q, v1, v31, T2D);
4960 eor3(v1, T16B, v19, v20, v5);
4961
4962 pmull (v21, T1Q, v2, v31, T1D);
4963 pmull2(v22, T1Q, v2, v31, T2D);
4964 eor3(v2, T16B, v21, v22, v6);
4965
4966 pmull (v23, T1Q, v3, v31, T1D);
4967 pmull2(v24, T1Q, v3, v31, T2D);
4968 eor3(v3, T16B, v23, v24, v7);
4969
4970 // fold into 128 bits
4971 // Use v17 for constants because v31 can be still in use.
4972 ldrq(v17, Address(table, 0x20));
4973 pmull (v25, T1Q, v0, v17, T1D);
4974 pmull2(v26, T1Q, v0, v17, T2D);
4975 eor3(v3, T16B, v3, v25, v26);
4976
4977 // Use v18 for constants because v17 can be still in use.
4978 ldrq(v18, Address(table, 0x30));
4979 pmull (v27, T1Q, v1, v18, T1D);
4980 pmull2(v28, T1Q, v1, v18, T2D);
4981 eor3(v3, T16B, v3, v27, v28);
4982
4983 // Use v19 for constants because v18 can be still in use.
4984 ldrq(v19, Address(table, 0x40));
4985 pmull (v29, T1Q, v2, v19, T1D);
4986 pmull2(v30, T1Q, v2, v19, T2D);
4987 eor3(v0, T16B, v3, v29, v30);
4988
4989 add(len, len, 0x80);
4990 add(buf, buf, 0x10);
4991
4992 mov(tmp0, v0, D, 0);
4993 mov(tmp1, v0, D, 1);
4994 }
4995
4996 void MacroAssembler::addptr(const Address &dst, int32_t src) {
4997 Address adr;
4998 switch(dst.getMode()) {
4999 case Address::base_plus_offset:
5000 // This is the expected mode, although we allow all the other
5001 // forms below.
5002 adr = form_address(rscratch2, dst.base(), dst.offset(), LogBytesPerWord);
5003 break;
5004 default:
5005 lea(rscratch2, dst);
5006 adr = Address(rscratch2);
5007 break;
5008 }
5009 ldr(rscratch1, adr);
5010 add(rscratch1, rscratch1, src);
5011 str(rscratch1, adr);
5012 }
5013
5014 void MacroAssembler::cmpptr(Register src1, Address src2) {
5015 uint64_t offset;
5016 adrp(rscratch1, src2, offset);
5017 ldr(rscratch1, Address(rscratch1, offset));
5018 cmp(src1, rscratch1);
5019 }
5020
5021 void MacroAssembler::cmpoop(Register obj1, Register obj2) {
5022 cmp(obj1, obj2);
5023 }
5024
5025 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
5026 load_method_holder(rresult, rmethod);
5027 ldr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
5028 }
5029
5030 void MacroAssembler::load_method_holder(Register holder, Register method) {
5031 ldr(holder, Address(method, Method::const_offset())); // ConstMethod*
5032 ldr(holder, Address(holder, ConstMethod::constants_offset())); // ConstantPool*
5033 ldr(holder, Address(holder, ConstantPool::pool_holder_offset())); // InstanceKlass*
5034 }
5035
5036 // Loads the obj's Klass* into dst.
5037 // Preserves all registers (incl src, rscratch1 and rscratch2).
5038 // Input:
5039 // src - the oop we want to load the klass from.
5040 // dst - output narrow klass.
5041 void MacroAssembler::load_narrow_klass_compact(Register dst, Register src) {
5042 assert(UseCompactObjectHeaders, "expects UseCompactObjectHeaders");
5043 ldr(dst, Address(src, oopDesc::mark_offset_in_bytes()));
5044 lsr(dst, dst, markWord::klass_shift);
5045 }
5046
5047 void MacroAssembler::load_klass(Register dst, Register src) {
5048 if (UseCompactObjectHeaders) {
5049 load_narrow_klass_compact(dst, src);
5050 decode_klass_not_null(dst);
5051 } else if (UseCompressedClassPointers) {
5052 ldrw(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5053 decode_klass_not_null(dst);
5054 } else {
5055 ldr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
5056 }
5057 }
5058
5059 void MacroAssembler::restore_cpu_control_state_after_jni(Register tmp1, Register tmp2) {
5060 if (RestoreMXCSROnJNICalls) {
5061 Label OK;
5062 get_fpcr(tmp1);
5063 mov(tmp2, tmp1);
5064 // Set FPCR to the state we need. We do want Round to Nearest. We
5065 // don't want non-IEEE rounding modes or floating-point traps.
5066 bfi(tmp1, zr, 22, 4); // Clear DN, FZ, and Rmode
5067 bfi(tmp1, zr, 8, 5); // Clear exception-control bits (8-12)
5068 bfi(tmp1, zr, 0, 2); // Clear AH:FIZ
5069 eor(tmp2, tmp1, tmp2);
5070 cbz(tmp2, OK); // Only reset FPCR if it's wrong
5071 set_fpcr(tmp1);
5072 bind(OK);
5073 }
5074 }
5075
5076 // ((OopHandle)result).resolve();
5077 void MacroAssembler::resolve_oop_handle(Register result, Register tmp1, Register tmp2) {
5078 // OopHandle::resolve is an indirection.
5079 access_load_at(T_OBJECT, IN_NATIVE, result, Address(result, 0), tmp1, tmp2);
5080 }
5081
5082 // ((WeakHandle)result).resolve();
5083 void MacroAssembler::resolve_weak_handle(Register result, Register tmp1, Register tmp2) {
5084 assert_different_registers(result, tmp1, tmp2);
5085 Label resolved;
5086
5087 // A null weak handle resolves to null.
5088 cbz(result, resolved);
5089
5090 // Only 64 bit platforms support GCs that require a tmp register
5091 // WeakHandle::resolve is an indirection like jweak.
5092 access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
5093 result, Address(result), tmp1, tmp2);
5094 bind(resolved);
5095 }
5096
5097 void MacroAssembler::load_mirror(Register dst, Register method, Register tmp1, Register tmp2) {
5098 const int mirror_offset = in_bytes(Klass::java_mirror_offset());
5099 ldr(dst, Address(rmethod, Method::const_offset()));
5100 ldr(dst, Address(dst, ConstMethod::constants_offset()));
5101 ldr(dst, Address(dst, ConstantPool::pool_holder_offset()));
5102 ldr(dst, Address(dst, mirror_offset));
5103 resolve_oop_handle(dst, tmp1, tmp2);
5104 }
5105
5106 void MacroAssembler::cmp_klass(Register obj, Register klass, Register tmp) {
5107 assert_different_registers(obj, klass, tmp);
5108 if (UseCompressedClassPointers) {
5109 if (UseCompactObjectHeaders) {
5110 load_narrow_klass_compact(tmp, obj);
5111 } else {
5112 ldrw(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5113 }
5114 if (CompressedKlassPointers::base() == nullptr) {
5115 cmp(klass, tmp, LSL, CompressedKlassPointers::shift());
5116 return;
5117 } else if (((uint64_t)CompressedKlassPointers::base() & 0xffffffff) == 0
5118 && CompressedKlassPointers::shift() == 0) {
5119 // Only the bottom 32 bits matter
5120 cmpw(klass, tmp);
5121 return;
5122 }
5123 decode_klass_not_null(tmp);
5124 } else {
5125 ldr(tmp, Address(obj, oopDesc::klass_offset_in_bytes()));
5126 }
5127 cmp(klass, tmp);
5128 }
5129
5130 void MacroAssembler::cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2) {
5131 if (UseCompactObjectHeaders) {
5132 load_narrow_klass_compact(tmp1, obj1);
5133 load_narrow_klass_compact(tmp2, obj2);
5134 cmpw(tmp1, tmp2);
5135 } else if (UseCompressedClassPointers) {
5136 ldrw(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5137 ldrw(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5138 cmpw(tmp1, tmp2);
5139 } else {
5140 ldr(tmp1, Address(obj1, oopDesc::klass_offset_in_bytes()));
5141 ldr(tmp2, Address(obj2, oopDesc::klass_offset_in_bytes()));
5142 cmp(tmp1, tmp2);
5143 }
5144 }
5145
5146 void MacroAssembler::store_klass(Register dst, Register src) {
5147 // FIXME: Should this be a store release? concurrent gcs assumes
5148 // klass length is valid if klass field is not null.
5149 assert(!UseCompactObjectHeaders, "not with compact headers");
5150 if (UseCompressedClassPointers) {
5151 encode_klass_not_null(src);
5152 strw(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5153 } else {
5154 str(src, Address(dst, oopDesc::klass_offset_in_bytes()));
5155 }
5156 }
5157
5158 void MacroAssembler::store_klass_gap(Register dst, Register src) {
5159 assert(!UseCompactObjectHeaders, "not with compact headers");
5160 if (UseCompressedClassPointers) {
5161 // Store to klass gap in destination
5162 strw(src, Address(dst, oopDesc::klass_gap_offset_in_bytes()));
5163 }
5164 }
5165
5166 // Algorithm must match CompressedOops::encode.
5167 void MacroAssembler::encode_heap_oop(Register d, Register s) {
5168 #ifdef ASSERT
5169 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
5170 #endif
5171 verify_oop_msg(s, "broken oop in encode_heap_oop");
5172 if (CompressedOops::base() == nullptr) {
5173 if (CompressedOops::shift() != 0) {
5174 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5175 lsr(d, s, LogMinObjAlignmentInBytes);
5176 } else {
5177 mov(d, s);
5178 }
5179 } else {
5180 subs(d, s, rheapbase);
5181 csel(d, d, zr, Assembler::HS);
5182 lsr(d, d, LogMinObjAlignmentInBytes);
5183
5184 /* Old algorithm: is this any worse?
5185 Label nonnull;
5186 cbnz(r, nonnull);
5187 sub(r, r, rheapbase);
5188 bind(nonnull);
5189 lsr(r, r, LogMinObjAlignmentInBytes);
5190 */
5191 }
5192 }
5193
5194 void MacroAssembler::encode_heap_oop_not_null(Register r) {
5195 #ifdef ASSERT
5196 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
5197 if (CheckCompressedOops) {
5198 Label ok;
5199 cbnz(r, ok);
5200 stop("null oop passed to encode_heap_oop_not_null");
5201 bind(ok);
5202 }
5203 #endif
5204 verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
5205 if (CompressedOops::base() != nullptr) {
5206 sub(r, r, rheapbase);
5207 }
5208 if (CompressedOops::shift() != 0) {
5209 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5210 lsr(r, r, LogMinObjAlignmentInBytes);
5211 }
5212 }
5213
5214 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
5215 #ifdef ASSERT
5216 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
5217 if (CheckCompressedOops) {
5218 Label ok;
5219 cbnz(src, ok);
5220 stop("null oop passed to encode_heap_oop_not_null2");
5221 bind(ok);
5222 }
5223 #endif
5224 verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
5225
5226 Register data = src;
5227 if (CompressedOops::base() != nullptr) {
5228 sub(dst, src, rheapbase);
5229 data = dst;
5230 }
5231 if (CompressedOops::shift() != 0) {
5232 assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5233 lsr(dst, data, LogMinObjAlignmentInBytes);
5234 data = dst;
5235 }
5236 if (data == src)
5237 mov(dst, src);
5238 }
5239
5240 void MacroAssembler::decode_heap_oop(Register d, Register s) {
5241 #ifdef ASSERT
5242 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
5243 #endif
5244 if (CompressedOops::base() == nullptr) {
5245 if (CompressedOops::shift() != 0) {
5246 lsl(d, s, CompressedOops::shift());
5247 } else if (d != s) {
5248 mov(d, s);
5249 }
5250 } else {
5251 Label done;
5252 if (d != s)
5253 mov(d, s);
5254 cbz(s, done);
5255 add(d, rheapbase, s, Assembler::LSL, LogMinObjAlignmentInBytes);
5256 bind(done);
5257 }
5258 verify_oop_msg(d, "broken oop in decode_heap_oop");
5259 }
5260
5261 void MacroAssembler::decode_heap_oop_not_null(Register r) {
5262 assert (UseCompressedOops, "should only be used for compressed headers");
5263 assert (Universe::heap() != nullptr, "java heap should be initialized");
5264 // Cannot assert, unverified entry point counts instructions (see .ad file)
5265 // vtableStubs also counts instructions in pd_code_size_limit.
5266 // Also do not verify_oop as this is called by verify_oop.
5267 if (CompressedOops::shift() != 0) {
5268 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5269 if (CompressedOops::base() != nullptr) {
5270 add(r, rheapbase, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5271 } else {
5272 add(r, zr, r, Assembler::LSL, LogMinObjAlignmentInBytes);
5273 }
5274 } else {
5275 assert (CompressedOops::base() == nullptr, "sanity");
5276 }
5277 }
5278
5279 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
5280 assert (UseCompressedOops, "should only be used for compressed headers");
5281 assert (Universe::heap() != nullptr, "java heap should be initialized");
5282 // Cannot assert, unverified entry point counts instructions (see .ad file)
5283 // vtableStubs also counts instructions in pd_code_size_limit.
5284 // Also do not verify_oop as this is called by verify_oop.
5285 if (CompressedOops::shift() != 0) {
5286 assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
5287 if (CompressedOops::base() != nullptr) {
5288 add(dst, rheapbase, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5289 } else {
5290 add(dst, zr, src, Assembler::LSL, LogMinObjAlignmentInBytes);
5291 }
5292 } else {
5293 assert (CompressedOops::base() == nullptr, "sanity");
5294 if (dst != src) {
5295 mov(dst, src);
5296 }
5297 }
5298 }
5299
5300 MacroAssembler::KlassDecodeMode MacroAssembler::_klass_decode_mode(KlassDecodeNone);
5301
5302 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode() {
5303 assert(Metaspace::initialized(), "metaspace not initialized yet");
5304 assert(_klass_decode_mode != KlassDecodeNone, "should be initialized");
5305 return _klass_decode_mode;
5306 }
5307
5308 MacroAssembler::KlassDecodeMode MacroAssembler::klass_decode_mode(address base, int shift, const size_t range) {
5309 assert(UseCompressedClassPointers, "not using compressed class pointers");
5310
5311 // KlassDecodeMode shouldn't be set already.
5312 assert(_klass_decode_mode == KlassDecodeNone, "set once");
5313
5314 if (base == nullptr) {
5315 return KlassDecodeZero;
5316 }
5317
5318 if (operand_valid_for_logical_immediate(
5319 /*is32*/false, (uint64_t)base)) {
5320 const uint64_t range_mask = right_n_bits(log2i_ceil(range));
5321 if (((uint64_t)base & range_mask) == 0) {
5322 return KlassDecodeXor;
5323 }
5324 }
5325
5326 const uint64_t shifted_base =
5327 (uint64_t)base >> shift;
5328 if ((shifted_base & 0xffff0000ffffffff) == 0) {
5329 return KlassDecodeMovk;
5330 }
5331
5332 // No valid encoding.
5333 return KlassDecodeNone;
5334 }
5335
5336 // Check if one of the above decoding modes will work for given base, shift and range.
5337 bool MacroAssembler::check_klass_decode_mode(address base, int shift, const size_t range) {
5338 return klass_decode_mode(base, shift, range) != KlassDecodeNone;
5339 }
5340
5341 bool MacroAssembler::set_klass_decode_mode(address base, int shift, const size_t range) {
5342 _klass_decode_mode = klass_decode_mode(base, shift, range);
5343 return _klass_decode_mode != KlassDecodeNone;
5344 }
5345
5346 static Register pick_different_tmp(Register dst, Register src) {
5347 auto tmps = RegSet::of(r0, r1, r2) - RegSet::of(src, dst);
5348 return *tmps.begin();
5349 }
5350
5351 void MacroAssembler::encode_klass_not_null_for_aot(Register dst, Register src) {
5352 // we have to load the klass base from the AOT constants area but
5353 // not the shift because it is not allowed to change
5354 int shift = CompressedKlassPointers::shift();
5355 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5356 if (dst != src) {
5357 // we can load the base into dst, subtract it formthe src and shift down
5358 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5359 ldr(dst, dst);
5360 sub(dst, src, dst);
5361 lsr(dst, dst, shift);
5362 } else {
5363 // we need an extra register in order to load the coop base
5364 Register tmp = pick_different_tmp(dst, src);
5365 RegSet regs = RegSet::of(tmp);
5366 push(regs, sp);
5367 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5368 ldr(tmp, tmp);
5369 sub(dst, src, tmp);
5370 lsr(dst, dst, shift);
5371 pop(regs, sp);
5372 }
5373 }
5374
5375 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
5376 if (AOTCodeCache::is_on_for_dump()) {
5377 encode_klass_not_null_for_aot(dst, src);
5378 return;
5379 }
5380
5381 switch (klass_decode_mode()) {
5382 case KlassDecodeZero:
5383 if (CompressedKlassPointers::shift() != 0) {
5384 lsr(dst, src, CompressedKlassPointers::shift());
5385 } else {
5386 if (dst != src) mov(dst, src);
5387 }
5388 break;
5389
5390 case KlassDecodeXor:
5391 if (CompressedKlassPointers::shift() != 0) {
5392 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5393 lsr(dst, dst, CompressedKlassPointers::shift());
5394 } else {
5395 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5396 }
5397 break;
5398
5399 case KlassDecodeMovk:
5400 if (CompressedKlassPointers::shift() != 0) {
5401 ubfx(dst, src, CompressedKlassPointers::shift(), 32);
5402 } else {
5403 movw(dst, src);
5404 }
5405 break;
5406
5407 case KlassDecodeNone:
5408 ShouldNotReachHere();
5409 break;
5410 }
5411 }
5412
5413 void MacroAssembler::encode_klass_not_null(Register r) {
5414 encode_klass_not_null(r, r);
5415 }
5416
5417 void MacroAssembler::decode_klass_not_null_for_aot(Register dst, Register src) {
5418 // we have to load the klass base from the AOT constants area but
5419 // not the shift because it is not allowed to change
5420 int shift = CompressedKlassPointers::shift();
5421 assert(shift >= 0 && shift <= CompressedKlassPointers::max_shift(), "unexpected compressed klass shift!");
5422 if (dst != src) {
5423 // we can load the base into dst then add the offset with a suitable shift
5424 lea(dst, ExternalAddress(CompressedKlassPointers::base_addr()));
5425 ldr(dst, dst);
5426 add(dst, dst, src, LSL, shift);
5427 } else {
5428 // we need an extra register in order to load the coop base
5429 Register tmp = pick_different_tmp(dst, src);
5430 RegSet regs = RegSet::of(tmp);
5431 push(regs, sp);
5432 lea(tmp, ExternalAddress(CompressedKlassPointers::base_addr()));
5433 ldr(tmp, tmp);
5434 add(dst, tmp, src, LSL, shift);
5435 pop(regs, sp);
5436 }
5437 }
5438
5439 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
5440 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5441
5442 if (AOTCodeCache::is_on_for_dump()) {
5443 decode_klass_not_null_for_aot(dst, src);
5444 return;
5445 }
5446
5447 switch (klass_decode_mode()) {
5448 case KlassDecodeZero:
5449 if (CompressedKlassPointers::shift() != 0) {
5450 lsl(dst, src, CompressedKlassPointers::shift());
5451 } else {
5452 if (dst != src) mov(dst, src);
5453 }
5454 break;
5455
5456 case KlassDecodeXor:
5457 if (CompressedKlassPointers::shift() != 0) {
5458 lsl(dst, src, CompressedKlassPointers::shift());
5459 eor(dst, dst, (uint64_t)CompressedKlassPointers::base());
5460 } else {
5461 eor(dst, src, (uint64_t)CompressedKlassPointers::base());
5462 }
5463 break;
5464
5465 case KlassDecodeMovk: {
5466 const uint64_t shifted_base =
5467 (uint64_t)CompressedKlassPointers::base() >> CompressedKlassPointers::shift();
5468
5469 if (dst != src) movw(dst, src);
5470 movk(dst, shifted_base >> 32, 32);
5471
5472 if (CompressedKlassPointers::shift() != 0) {
5473 lsl(dst, dst, CompressedKlassPointers::shift());
5474 }
5475
5476 break;
5477 }
5478
5479 case KlassDecodeNone:
5480 ShouldNotReachHere();
5481 break;
5482 }
5483 }
5484
5485 void MacroAssembler::decode_klass_not_null(Register r) {
5486 decode_klass_not_null(r, r);
5487 }
5488
5489 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5490 #ifdef ASSERT
5491 {
5492 ThreadInVMfromUnknown tiv;
5493 assert (UseCompressedOops, "should only be used for compressed oops");
5494 assert (Universe::heap() != nullptr, "java heap should be initialized");
5495 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5496 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5497 }
5498 #endif
5499 int oop_index = oop_recorder()->find_index(obj);
5500 InstructionMark im(this);
5501 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5502 code_section()->relocate(inst_mark(), rspec);
5503 movz(dst, 0xDEAD, 16);
5504 movk(dst, 0xBEEF);
5505 }
5506
5507 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5508 assert (UseCompressedClassPointers, "should only be used for compressed headers");
5509 assert (oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5510 int index = oop_recorder()->find_index(k);
5511 assert(! Universe::heap()->is_in(k), "should not be an oop");
5512
5513 InstructionMark im(this);
5514 RelocationHolder rspec = metadata_Relocation::spec(index);
5515 code_section()->relocate(inst_mark(), rspec);
5516 narrowKlass nk = CompressedKlassPointers::encode(k);
5517 movz(dst, (nk >> 16), 16);
5518 movk(dst, nk & 0xffff);
5519 }
5520
5521 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
5522 Register dst, Address src,
5523 Register tmp1, Register tmp2) {
5524 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5525 decorators = AccessInternal::decorator_fixup(decorators, type);
5526 bool as_raw = (decorators & AS_RAW) != 0;
5527 if (as_raw) {
5528 bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, tmp2);
5529 } else {
5530 bs->load_at(this, decorators, type, dst, src, tmp1, tmp2);
5531 }
5532 }
5533
5534 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
5535 Address dst, Register val,
5536 Register tmp1, Register tmp2, Register tmp3) {
5537 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5538 decorators = AccessInternal::decorator_fixup(decorators, type);
5539 bool as_raw = (decorators & AS_RAW) != 0;
5540 if (as_raw) {
5541 bs->BarrierSetAssembler::store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5542 } else {
5543 bs->store_at(this, decorators, type, dst, val, tmp1, tmp2, tmp3);
5544 }
5545 }
5546
5547 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
5548 Register tmp2, DecoratorSet decorators) {
5549 access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
5550 }
5551
5552 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
5553 Register tmp2, DecoratorSet decorators) {
5554 access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, tmp2);
5555 }
5556
5557 void MacroAssembler::store_heap_oop(Address dst, Register val, Register tmp1,
5558 Register tmp2, Register tmp3, DecoratorSet decorators) {
5559 access_store_at(T_OBJECT, IN_HEAP | decorators, dst, val, tmp1, tmp2, tmp3);
5560 }
5561
5562 // Used for storing nulls.
5563 void MacroAssembler::store_heap_oop_null(Address dst) {
5564 access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
5565 }
5566
5567 Address MacroAssembler::allocate_metadata_address(Metadata* obj) {
5568 assert(oop_recorder() != nullptr, "this assembler needs a Recorder");
5569 int index = oop_recorder()->allocate_metadata_index(obj);
5570 RelocationHolder rspec = metadata_Relocation::spec(index);
5571 return Address((address)obj, rspec);
5572 }
5573
5574 // Move an oop into a register.
5575 void MacroAssembler::movoop(Register dst, jobject obj) {
5576 int oop_index;
5577 if (obj == nullptr) {
5578 oop_index = oop_recorder()->allocate_oop_index(obj);
5579 } else {
5580 #ifdef ASSERT
5581 {
5582 ThreadInVMfromUnknown tiv;
5583 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "should be real oop");
5584 }
5585 #endif
5586 oop_index = oop_recorder()->find_index(obj);
5587 }
5588 RelocationHolder rspec = oop_Relocation::spec(oop_index);
5589
5590 if (BarrierSet::barrier_set()->barrier_set_assembler()->supports_instruction_patching()) {
5591 mov(dst, Address((address)obj, rspec));
5592 } else {
5593 address dummy = address(uintptr_t(pc()) & -wordSize); // A nearby aligned address
5594 ldr(dst, Address(dummy, rspec));
5595 }
5596 }
5597
5598 // Move a metadata address into a register.
5599 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
5600 int oop_index;
5601 if (obj == nullptr) {
5602 oop_index = oop_recorder()->allocate_metadata_index(obj);
5603 } else {
5604 oop_index = oop_recorder()->find_index(obj);
5605 }
5606 RelocationHolder rspec = metadata_Relocation::spec(oop_index);
5607 mov(dst, Address((address)obj, rspec));
5608 }
5609
5610 Address MacroAssembler::constant_oop_address(jobject obj) {
5611 #ifdef ASSERT
5612 {
5613 ThreadInVMfromUnknown tiv;
5614 assert(oop_recorder() != nullptr, "this assembler needs an OopRecorder");
5615 assert(Universe::heap()->is_in(JNIHandles::resolve(obj)), "not an oop");
5616 }
5617 #endif
5618 int oop_index = oop_recorder()->find_index(obj);
5619 return Address((address)obj, oop_Relocation::spec(oop_index));
5620 }
5621
5622 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
5623 void MacroAssembler::tlab_allocate(Register obj,
5624 Register var_size_in_bytes,
5625 int con_size_in_bytes,
5626 Register t1,
5627 Register t2,
5628 Label& slow_case) {
5629 BarrierSetAssembler *bs = BarrierSet::barrier_set()->barrier_set_assembler();
5630 bs->tlab_allocate(this, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
5631 }
5632
5633 void MacroAssembler::inc_held_monitor_count(Register tmp) {
5634 Address dst(rthread, JavaThread::held_monitor_count_offset());
5635 #ifdef ASSERT
5636 ldr(tmp, dst);
5637 increment(tmp);
5638 str(tmp, dst);
5639 Label ok;
5640 tbz(tmp, 63, ok);
5641 STOP("assert(held monitor count underflow)");
5642 should_not_reach_here();
5643 bind(ok);
5644 #else
5645 increment(dst);
5646 #endif
5647 }
5648
5649 void MacroAssembler::dec_held_monitor_count(Register tmp) {
5650 Address dst(rthread, JavaThread::held_monitor_count_offset());
5651 #ifdef ASSERT
5652 ldr(tmp, dst);
5653 decrement(tmp);
5654 str(tmp, dst);
5655 Label ok;
5656 tbz(tmp, 63, ok);
5657 STOP("assert(held monitor count underflow)");
5658 should_not_reach_here();
5659 bind(ok);
5660 #else
5661 decrement(dst);
5662 #endif
5663 }
5664
5665 void MacroAssembler::verify_tlab() {
5666 #ifdef ASSERT
5667 if (UseTLAB && VerifyOops) {
5668 Label next, ok;
5669
5670 stp(rscratch2, rscratch1, Address(pre(sp, -16)));
5671
5672 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5673 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_start_offset())));
5674 cmp(rscratch2, rscratch1);
5675 br(Assembler::HS, next);
5676 STOP("assert(top >= start)");
5677 should_not_reach_here();
5678
5679 bind(next);
5680 ldr(rscratch2, Address(rthread, in_bytes(JavaThread::tlab_end_offset())));
5681 ldr(rscratch1, Address(rthread, in_bytes(JavaThread::tlab_top_offset())));
5682 cmp(rscratch2, rscratch1);
5683 br(Assembler::HS, ok);
5684 STOP("assert(top <= end)");
5685 should_not_reach_here();
5686
5687 bind(ok);
5688 ldp(rscratch2, rscratch1, Address(post(sp, 16)));
5689 }
5690 #endif
5691 }
5692
5693 // Writes to stack successive pages until offset reached to check for
5694 // stack overflow + shadow pages. This clobbers tmp.
5695 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
5696 assert_different_registers(tmp, size, rscratch1);
5697 mov(tmp, sp);
5698 // Bang stack for total size given plus shadow page size.
5699 // Bang one page at a time because large size can bang beyond yellow and
5700 // red zones.
5701 Label loop;
5702 mov(rscratch1, (int)os::vm_page_size());
5703 bind(loop);
5704 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5705 subsw(size, size, rscratch1);
5706 str(size, Address(tmp));
5707 br(Assembler::GT, loop);
5708
5709 // Bang down shadow pages too.
5710 // At this point, (tmp-0) is the last address touched, so don't
5711 // touch it again. (It was touched as (tmp-pagesize) but then tmp
5712 // was post-decremented.) Skip this address by starting at i=1, and
5713 // touch a few more pages below. N.B. It is important to touch all
5714 // the way down to and including i=StackShadowPages.
5715 for (int i = 0; i < (int)(StackOverflow::stack_shadow_zone_size() / (int)os::vm_page_size()) - 1; i++) {
5716 // this could be any sized move but this is can be a debugging crumb
5717 // so the bigger the better.
5718 lea(tmp, Address(tmp, -(int)os::vm_page_size()));
5719 str(size, Address(tmp));
5720 }
5721 }
5722
5723 // Move the address of the polling page into dest.
5724 void MacroAssembler::get_polling_page(Register dest, relocInfo::relocType rtype) {
5725 ldr(dest, Address(rthread, JavaThread::polling_page_offset()));
5726 }
5727
5728 // Read the polling page. The address of the polling page must
5729 // already be in r.
5730 address MacroAssembler::read_polling_page(Register r, relocInfo::relocType rtype) {
5731 address mark;
5732 {
5733 InstructionMark im(this);
5734 code_section()->relocate(inst_mark(), rtype);
5735 ldrw(zr, Address(r, 0));
5736 mark = inst_mark();
5737 }
5738 verify_cross_modify_fence_not_required();
5739 return mark;
5740 }
5741
5742 void MacroAssembler::adrp(Register reg1, const Address &dest, uint64_t &byte_offset) {
5743 relocInfo::relocType rtype = dest.rspec().reloc()->type();
5744 uint64_t low_page = (uint64_t)CodeCache::low_bound() >> 12;
5745 uint64_t high_page = (uint64_t)(CodeCache::high_bound()-1) >> 12;
5746 uint64_t dest_page = (uint64_t)dest.target() >> 12;
5747 int64_t offset_low = dest_page - low_page;
5748 int64_t offset_high = dest_page - high_page;
5749
5750 assert(is_valid_AArch64_address(dest.target()), "bad address");
5751 assert(dest.getMode() == Address::literal, "ADRP must be applied to a literal address");
5752
5753 InstructionMark im(this);
5754 code_section()->relocate(inst_mark(), dest.rspec());
5755 // 8143067: Ensure that the adrp can reach the dest from anywhere within
5756 // the code cache so that if it is relocated we know it will still reach
5757 if (offset_high >= -(1<<20) && offset_low < (1<<20)) {
5758 _adrp(reg1, dest.target());
5759 } else {
5760 uint64_t target = (uint64_t)dest.target();
5761 uint64_t adrp_target
5762 = (target & 0xffffffffULL) | ((uint64_t)pc() & 0xffff00000000ULL);
5763
5764 _adrp(reg1, (address)adrp_target);
5765 movk(reg1, target >> 32, 32);
5766 }
5767 byte_offset = (uint64_t)dest.target() & 0xfff;
5768 }
5769
5770 void MacroAssembler::load_byte_map_base(Register reg) {
5771 CardTable::CardValue* byte_map_base =
5772 ((CardTableBarrierSet*)(BarrierSet::barrier_set()))->card_table()->byte_map_base();
5773
5774 // Strictly speaking the byte_map_base isn't an address at all, and it might
5775 // even be negative. It is thus materialised as a constant.
5776 mov(reg, (uint64_t)byte_map_base);
5777 }
5778
5779 void MacroAssembler::build_frame(int framesize) {
5780 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5781 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5782 protect_return_address();
5783 if (framesize < ((1 << 9) + 2 * wordSize)) {
5784 sub(sp, sp, framesize);
5785 stp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5786 if (PreserveFramePointer) add(rfp, sp, framesize - 2 * wordSize);
5787 } else {
5788 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
5789 if (PreserveFramePointer) mov(rfp, sp);
5790 if (framesize < ((1 << 12) + 2 * wordSize))
5791 sub(sp, sp, framesize - 2 * wordSize);
5792 else {
5793 mov(rscratch1, framesize - 2 * wordSize);
5794 sub(sp, sp, rscratch1);
5795 }
5796 }
5797 verify_cross_modify_fence_not_required();
5798 }
5799
5800 void MacroAssembler::remove_frame(int framesize) {
5801 assert(framesize >= 2 * wordSize, "framesize must include space for FP/LR");
5802 assert(framesize % (2*wordSize) == 0, "must preserve 2*wordSize alignment");
5803 if (framesize < ((1 << 9) + 2 * wordSize)) {
5804 ldp(rfp, lr, Address(sp, framesize - 2 * wordSize));
5805 add(sp, sp, framesize);
5806 } else {
5807 if (framesize < ((1 << 12) + 2 * wordSize))
5808 add(sp, sp, framesize - 2 * wordSize);
5809 else {
5810 mov(rscratch1, framesize - 2 * wordSize);
5811 add(sp, sp, rscratch1);
5812 }
5813 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
5814 }
5815 authenticate_return_address();
5816 }
5817
5818
5819 // This method counts leading positive bytes (highest bit not set) in provided byte array
5820 address MacroAssembler::count_positives(Register ary1, Register len, Register result) {
5821 // Simple and most common case of aligned small array which is not at the
5822 // end of memory page is placed here. All other cases are in stub.
5823 Label LOOP, END, STUB, STUB_LONG, SET_RESULT, DONE;
5824 const uint64_t UPPER_BIT_MASK=0x8080808080808080;
5825 assert_different_registers(ary1, len, result);
5826
5827 mov(result, len);
5828 cmpw(len, 0);
5829 br(LE, DONE);
5830 cmpw(len, 4 * wordSize);
5831 br(GE, STUB_LONG); // size > 32 then go to stub
5832
5833 int shift = 64 - exact_log2(os::vm_page_size());
5834 lsl(rscratch1, ary1, shift);
5835 mov(rscratch2, (size_t)(4 * wordSize) << shift);
5836 adds(rscratch2, rscratch1, rscratch2); // At end of page?
5837 br(CS, STUB); // at the end of page then go to stub
5838 subs(len, len, wordSize);
5839 br(LT, END);
5840
5841 BIND(LOOP);
5842 ldr(rscratch1, Address(post(ary1, wordSize)));
5843 tst(rscratch1, UPPER_BIT_MASK);
5844 br(NE, SET_RESULT);
5845 subs(len, len, wordSize);
5846 br(GE, LOOP);
5847 cmpw(len, -wordSize);
5848 br(EQ, DONE);
5849
5850 BIND(END);
5851 ldr(rscratch1, Address(ary1));
5852 sub(rscratch2, zr, len, LSL, 3); // LSL 3 is to get bits from bytes
5853 lslv(rscratch1, rscratch1, rscratch2);
5854 tst(rscratch1, UPPER_BIT_MASK);
5855 br(NE, SET_RESULT);
5856 b(DONE);
5857
5858 BIND(STUB);
5859 RuntimeAddress count_pos = RuntimeAddress(StubRoutines::aarch64::count_positives());
5860 assert(count_pos.target() != nullptr, "count_positives stub has not been generated");
5861 address tpc1 = trampoline_call(count_pos);
5862 if (tpc1 == nullptr) {
5863 DEBUG_ONLY(reset_labels(STUB_LONG, SET_RESULT, DONE));
5864 postcond(pc() == badAddress);
5865 return nullptr;
5866 }
5867 b(DONE);
5868
5869 BIND(STUB_LONG);
5870 RuntimeAddress count_pos_long = RuntimeAddress(StubRoutines::aarch64::count_positives_long());
5871 assert(count_pos_long.target() != nullptr, "count_positives_long stub has not been generated");
5872 address tpc2 = trampoline_call(count_pos_long);
5873 if (tpc2 == nullptr) {
5874 DEBUG_ONLY(reset_labels(SET_RESULT, DONE));
5875 postcond(pc() == badAddress);
5876 return nullptr;
5877 }
5878 b(DONE);
5879
5880 BIND(SET_RESULT);
5881
5882 add(len, len, wordSize);
5883 sub(result, result, len);
5884
5885 BIND(DONE);
5886 postcond(pc() != badAddress);
5887 return pc();
5888 }
5889
5890 // Clobbers: rscratch1, rscratch2, rflags
5891 // May also clobber v0-v7 when (!UseSimpleArrayEquals && UseSIMDForArrayEquals)
5892 address MacroAssembler::arrays_equals(Register a1, Register a2, Register tmp3,
5893 Register tmp4, Register tmp5, Register result,
5894 Register cnt1, int elem_size) {
5895 Label DONE, SAME;
5896 Register tmp1 = rscratch1;
5897 Register tmp2 = rscratch2;
5898 int elem_per_word = wordSize/elem_size;
5899 int log_elem_size = exact_log2(elem_size);
5900 int klass_offset = arrayOopDesc::klass_offset_in_bytes();
5901 int length_offset = arrayOopDesc::length_offset_in_bytes();
5902 int base_offset
5903 = arrayOopDesc::base_offset_in_bytes(elem_size == 2 ? T_CHAR : T_BYTE);
5904 // When the length offset is not aligned to 8 bytes,
5905 // then we align it down. This is valid because the new
5906 // offset will always be the klass which is the same
5907 // for type arrays.
5908 int start_offset = align_down(length_offset, BytesPerWord);
5909 int extra_length = base_offset - start_offset;
5910 assert(start_offset == length_offset || start_offset == klass_offset,
5911 "start offset must be 8-byte-aligned or be the klass offset");
5912 assert(base_offset != start_offset, "must include the length field");
5913 extra_length = extra_length / elem_size; // We count in elements, not bytes.
5914 int stubBytesThreshold = 3 * 64 + (UseSIMDForArrayEquals ? 0 : 16);
5915
5916 assert(elem_size == 1 || elem_size == 2, "must be char or byte");
5917 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
5918
5919 #ifndef PRODUCT
5920 {
5921 const char kind = (elem_size == 2) ? 'U' : 'L';
5922 char comment[64];
5923 snprintf(comment, sizeof comment, "array_equals%c{", kind);
5924 BLOCK_COMMENT(comment);
5925 }
5926 #endif
5927
5928 // if (a1 == a2)
5929 // return true;
5930 cmpoop(a1, a2); // May have read barriers for a1 and a2.
5931 br(EQ, SAME);
5932
5933 if (UseSimpleArrayEquals) {
5934 Label NEXT_WORD, SHORT, TAIL03, TAIL01, A_MIGHT_BE_NULL, A_IS_NOT_NULL;
5935 // if (a1 == nullptr || a2 == nullptr)
5936 // return false;
5937 // a1 & a2 == 0 means (some-pointer is null) or
5938 // (very-rare-or-even-probably-impossible-pointer-values)
5939 // so, we can save one branch in most cases
5940 tst(a1, a2);
5941 mov(result, false);
5942 br(EQ, A_MIGHT_BE_NULL);
5943 // if (a1.length != a2.length)
5944 // return false;
5945 bind(A_IS_NOT_NULL);
5946 ldrw(cnt1, Address(a1, length_offset));
5947 // Increase loop counter by diff between base- and actual start-offset.
5948 addw(cnt1, cnt1, extra_length);
5949 lea(a1, Address(a1, start_offset));
5950 lea(a2, Address(a2, start_offset));
5951 // Check for short strings, i.e. smaller than wordSize.
5952 subs(cnt1, cnt1, elem_per_word);
5953 br(Assembler::LT, SHORT);
5954 // Main 8 byte comparison loop.
5955 bind(NEXT_WORD); {
5956 ldr(tmp1, Address(post(a1, wordSize)));
5957 ldr(tmp2, Address(post(a2, wordSize)));
5958 subs(cnt1, cnt1, elem_per_word);
5959 eor(tmp5, tmp1, tmp2);
5960 cbnz(tmp5, DONE);
5961 } br(GT, NEXT_WORD);
5962 // Last longword. In the case where length == 4 we compare the
5963 // same longword twice, but that's still faster than another
5964 // conditional branch.
5965 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
5966 // length == 4.
5967 if (log_elem_size > 0)
5968 lsl(cnt1, cnt1, log_elem_size);
5969 ldr(tmp3, Address(a1, cnt1));
5970 ldr(tmp4, Address(a2, cnt1));
5971 eor(tmp5, tmp3, tmp4);
5972 cbnz(tmp5, DONE);
5973 b(SAME);
5974 bind(A_MIGHT_BE_NULL);
5975 // in case both a1 and a2 are not-null, proceed with loads
5976 cbz(a1, DONE);
5977 cbz(a2, DONE);
5978 b(A_IS_NOT_NULL);
5979 bind(SHORT);
5980
5981 tbz(cnt1, 2 - log_elem_size, TAIL03); // 0-7 bytes left.
5982 {
5983 ldrw(tmp1, Address(post(a1, 4)));
5984 ldrw(tmp2, Address(post(a2, 4)));
5985 eorw(tmp5, tmp1, tmp2);
5986 cbnzw(tmp5, DONE);
5987 }
5988 bind(TAIL03);
5989 tbz(cnt1, 1 - log_elem_size, TAIL01); // 0-3 bytes left.
5990 {
5991 ldrh(tmp3, Address(post(a1, 2)));
5992 ldrh(tmp4, Address(post(a2, 2)));
5993 eorw(tmp5, tmp3, tmp4);
5994 cbnzw(tmp5, DONE);
5995 }
5996 bind(TAIL01);
5997 if (elem_size == 1) { // Only needed when comparing byte arrays.
5998 tbz(cnt1, 0, SAME); // 0-1 bytes left.
5999 {
6000 ldrb(tmp1, a1);
6001 ldrb(tmp2, a2);
6002 eorw(tmp5, tmp1, tmp2);
6003 cbnzw(tmp5, DONE);
6004 }
6005 }
6006 } else {
6007 Label NEXT_DWORD, SHORT, TAIL, TAIL2, STUB,
6008 CSET_EQ, LAST_CHECK;
6009 mov(result, false);
6010 cbz(a1, DONE);
6011 ldrw(cnt1, Address(a1, length_offset));
6012 cbz(a2, DONE);
6013 // Increase loop counter by diff between base- and actual start-offset.
6014 addw(cnt1, cnt1, extra_length);
6015
6016 // on most CPUs a2 is still "locked"(surprisingly) in ldrw and it's
6017 // faster to perform another branch before comparing a1 and a2
6018 cmp(cnt1, (u1)elem_per_word);
6019 br(LE, SHORT); // short or same
6020 ldr(tmp3, Address(pre(a1, start_offset)));
6021 subs(zr, cnt1, stubBytesThreshold);
6022 br(GE, STUB);
6023 ldr(tmp4, Address(pre(a2, start_offset)));
6024 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6025
6026 // Main 16 byte comparison loop with 2 exits
6027 bind(NEXT_DWORD); {
6028 ldr(tmp1, Address(pre(a1, wordSize)));
6029 ldr(tmp2, Address(pre(a2, wordSize)));
6030 subs(cnt1, cnt1, 2 * elem_per_word);
6031 br(LE, TAIL);
6032 eor(tmp4, tmp3, tmp4);
6033 cbnz(tmp4, DONE);
6034 ldr(tmp3, Address(pre(a1, wordSize)));
6035 ldr(tmp4, Address(pre(a2, wordSize)));
6036 cmp(cnt1, (u1)elem_per_word);
6037 br(LE, TAIL2);
6038 cmp(tmp1, tmp2);
6039 } br(EQ, NEXT_DWORD);
6040 b(DONE);
6041
6042 bind(TAIL);
6043 eor(tmp4, tmp3, tmp4);
6044 eor(tmp2, tmp1, tmp2);
6045 lslv(tmp2, tmp2, tmp5);
6046 orr(tmp5, tmp4, tmp2);
6047 cmp(tmp5, zr);
6048 b(CSET_EQ);
6049
6050 bind(TAIL2);
6051 eor(tmp2, tmp1, tmp2);
6052 cbnz(tmp2, DONE);
6053 b(LAST_CHECK);
6054
6055 bind(STUB);
6056 ldr(tmp4, Address(pre(a2, start_offset)));
6057 if (elem_size == 2) { // convert to byte counter
6058 lsl(cnt1, cnt1, 1);
6059 }
6060 eor(tmp5, tmp3, tmp4);
6061 cbnz(tmp5, DONE);
6062 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_array_equals());
6063 assert(stub.target() != nullptr, "array_equals_long stub has not been generated");
6064 address tpc = trampoline_call(stub);
6065 if (tpc == nullptr) {
6066 DEBUG_ONLY(reset_labels(SHORT, LAST_CHECK, CSET_EQ, SAME, DONE));
6067 postcond(pc() == badAddress);
6068 return nullptr;
6069 }
6070 b(DONE);
6071
6072 // (a1 != null && a2 == null) || (a1 != null && a2 != null && a1 == a2)
6073 // so, if a2 == null => return false(0), else return true, so we can return a2
6074 mov(result, a2);
6075 b(DONE);
6076 bind(SHORT);
6077 sub(tmp5, zr, cnt1, LSL, 3 + log_elem_size);
6078 ldr(tmp3, Address(a1, start_offset));
6079 ldr(tmp4, Address(a2, start_offset));
6080 bind(LAST_CHECK);
6081 eor(tmp4, tmp3, tmp4);
6082 lslv(tmp5, tmp4, tmp5);
6083 cmp(tmp5, zr);
6084 bind(CSET_EQ);
6085 cset(result, EQ);
6086 b(DONE);
6087 }
6088
6089 bind(SAME);
6090 mov(result, true);
6091 // That's it.
6092 bind(DONE);
6093
6094 BLOCK_COMMENT("} array_equals");
6095 postcond(pc() != badAddress);
6096 return pc();
6097 }
6098
6099 // Compare Strings
6100
6101 // For Strings we're passed the address of the first characters in a1
6102 // and a2 and the length in cnt1.
6103 // There are two implementations. For arrays >= 8 bytes, all
6104 // comparisons (including the final one, which may overlap) are
6105 // performed 8 bytes at a time. For strings < 8 bytes, we compare a
6106 // halfword, then a short, and then a byte.
6107
6108 void MacroAssembler::string_equals(Register a1, Register a2,
6109 Register result, Register cnt1)
6110 {
6111 Label SAME, DONE, SHORT, NEXT_WORD;
6112 Register tmp1 = rscratch1;
6113 Register tmp2 = rscratch2;
6114 Register cnt2 = tmp2; // cnt2 only used in array length compare
6115
6116 assert_different_registers(a1, a2, result, cnt1, rscratch1, rscratch2);
6117
6118 #ifndef PRODUCT
6119 {
6120 char comment[64];
6121 snprintf(comment, sizeof comment, "{string_equalsL");
6122 BLOCK_COMMENT(comment);
6123 }
6124 #endif
6125
6126 mov(result, false);
6127
6128 // Check for short strings, i.e. smaller than wordSize.
6129 subs(cnt1, cnt1, wordSize);
6130 br(Assembler::LT, SHORT);
6131 // Main 8 byte comparison loop.
6132 bind(NEXT_WORD); {
6133 ldr(tmp1, Address(post(a1, wordSize)));
6134 ldr(tmp2, Address(post(a2, wordSize)));
6135 subs(cnt1, cnt1, wordSize);
6136 eor(tmp1, tmp1, tmp2);
6137 cbnz(tmp1, DONE);
6138 } br(GT, NEXT_WORD);
6139 // Last longword. In the case where length == 4 we compare the
6140 // same longword twice, but that's still faster than another
6141 // conditional branch.
6142 // cnt1 could be 0, -1, -2, -3, -4 for chars; -4 only happens when
6143 // length == 4.
6144 ldr(tmp1, Address(a1, cnt1));
6145 ldr(tmp2, Address(a2, cnt1));
6146 eor(tmp2, tmp1, tmp2);
6147 cbnz(tmp2, DONE);
6148 b(SAME);
6149
6150 bind(SHORT);
6151 Label TAIL03, TAIL01;
6152
6153 tbz(cnt1, 2, TAIL03); // 0-7 bytes left.
6154 {
6155 ldrw(tmp1, Address(post(a1, 4)));
6156 ldrw(tmp2, Address(post(a2, 4)));
6157 eorw(tmp1, tmp1, tmp2);
6158 cbnzw(tmp1, DONE);
6159 }
6160 bind(TAIL03);
6161 tbz(cnt1, 1, TAIL01); // 0-3 bytes left.
6162 {
6163 ldrh(tmp1, Address(post(a1, 2)));
6164 ldrh(tmp2, Address(post(a2, 2)));
6165 eorw(tmp1, tmp1, tmp2);
6166 cbnzw(tmp1, DONE);
6167 }
6168 bind(TAIL01);
6169 tbz(cnt1, 0, SAME); // 0-1 bytes left.
6170 {
6171 ldrb(tmp1, a1);
6172 ldrb(tmp2, a2);
6173 eorw(tmp1, tmp1, tmp2);
6174 cbnzw(tmp1, DONE);
6175 }
6176 // Arrays are equal.
6177 bind(SAME);
6178 mov(result, true);
6179
6180 // That's it.
6181 bind(DONE);
6182 BLOCK_COMMENT("} string_equals");
6183 }
6184
6185
6186 // The size of the blocks erased by the zero_blocks stub. We must
6187 // handle anything smaller than this ourselves in zero_words().
6188 const int MacroAssembler::zero_words_block_size = 8;
6189
6190 // zero_words() is used by C2 ClearArray patterns and by
6191 // C1_MacroAssembler. It is as small as possible, handling small word
6192 // counts locally and delegating anything larger to the zero_blocks
6193 // stub. It is expanded many times in compiled code, so it is
6194 // important to keep it short.
6195
6196 // ptr: Address of a buffer to be zeroed.
6197 // cnt: Count in HeapWords.
6198 //
6199 // ptr, cnt, rscratch1, and rscratch2 are clobbered.
6200 address MacroAssembler::zero_words(Register ptr, Register cnt)
6201 {
6202 assert(is_power_of_2(zero_words_block_size), "adjust this");
6203
6204 BLOCK_COMMENT("zero_words {");
6205 assert(ptr == r10 && cnt == r11, "mismatch in register usage");
6206 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6207 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6208
6209 subs(rscratch1, cnt, zero_words_block_size);
6210 Label around;
6211 br(LO, around);
6212 {
6213 RuntimeAddress zero_blocks = RuntimeAddress(StubRoutines::aarch64::zero_blocks());
6214 assert(zero_blocks.target() != nullptr, "zero_blocks stub has not been generated");
6215 // Make sure this is a C2 compilation. C1 allocates space only for
6216 // trampoline stubs generated by Call LIR ops, and in any case it
6217 // makes sense for a C1 compilation task to proceed as quickly as
6218 // possible.
6219 CompileTask* task;
6220 if (StubRoutines::aarch64::complete()
6221 && Thread::current()->is_Compiler_thread()
6222 && (task = ciEnv::current()->task())
6223 && is_c2_compile(task->comp_level())) {
6224 address tpc = trampoline_call(zero_blocks);
6225 if (tpc == nullptr) {
6226 DEBUG_ONLY(reset_labels(around));
6227 return nullptr;
6228 }
6229 } else {
6230 far_call(zero_blocks);
6231 }
6232 }
6233 bind(around);
6234
6235 // We have a few words left to do. zero_blocks has adjusted r10 and r11
6236 // for us.
6237 for (int i = zero_words_block_size >> 1; i > 1; i >>= 1) {
6238 Label l;
6239 tbz(cnt, exact_log2(i), l);
6240 for (int j = 0; j < i; j += 2) {
6241 stp(zr, zr, post(ptr, 2 * BytesPerWord));
6242 }
6243 bind(l);
6244 }
6245 {
6246 Label l;
6247 tbz(cnt, 0, l);
6248 str(zr, Address(ptr));
6249 bind(l);
6250 }
6251
6252 BLOCK_COMMENT("} zero_words");
6253 return pc();
6254 }
6255
6256 // base: Address of a buffer to be zeroed, 8 bytes aligned.
6257 // cnt: Immediate count in HeapWords.
6258 //
6259 // r10, r11, rscratch1, and rscratch2 are clobbered.
6260 address MacroAssembler::zero_words(Register base, uint64_t cnt)
6261 {
6262 assert(wordSize <= BlockZeroingLowLimit,
6263 "increase BlockZeroingLowLimit");
6264 address result = nullptr;
6265 if (cnt <= (uint64_t)BlockZeroingLowLimit / BytesPerWord) {
6266 #ifndef PRODUCT
6267 {
6268 char buf[64];
6269 snprintf(buf, sizeof buf, "zero_words (count = %" PRIu64 ") {", cnt);
6270 BLOCK_COMMENT(buf);
6271 }
6272 #endif
6273 if (cnt >= 16) {
6274 uint64_t loops = cnt/16;
6275 if (loops > 1) {
6276 mov(rscratch2, loops - 1);
6277 }
6278 {
6279 Label loop;
6280 bind(loop);
6281 for (int i = 0; i < 16; i += 2) {
6282 stp(zr, zr, Address(base, i * BytesPerWord));
6283 }
6284 add(base, base, 16 * BytesPerWord);
6285 if (loops > 1) {
6286 subs(rscratch2, rscratch2, 1);
6287 br(GE, loop);
6288 }
6289 }
6290 }
6291 cnt %= 16;
6292 int i = cnt & 1; // store any odd word to start
6293 if (i) str(zr, Address(base));
6294 for (; i < (int)cnt; i += 2) {
6295 stp(zr, zr, Address(base, i * wordSize));
6296 }
6297 BLOCK_COMMENT("} zero_words");
6298 result = pc();
6299 } else {
6300 mov(r10, base); mov(r11, cnt);
6301 result = zero_words(r10, r11);
6302 }
6303 return result;
6304 }
6305
6306 // Zero blocks of memory by using DC ZVA.
6307 //
6308 // Aligns the base address first sufficiently for DC ZVA, then uses
6309 // DC ZVA repeatedly for every full block. cnt is the size to be
6310 // zeroed in HeapWords. Returns the count of words left to be zeroed
6311 // in cnt.
6312 //
6313 // NOTE: This is intended to be used in the zero_blocks() stub. If
6314 // you want to use it elsewhere, note that cnt must be >= 2*zva_length.
6315 void MacroAssembler::zero_dcache_blocks(Register base, Register cnt) {
6316 Register tmp = rscratch1;
6317 Register tmp2 = rscratch2;
6318 int zva_length = VM_Version::zva_length();
6319 Label initial_table_end, loop_zva;
6320 Label fini;
6321
6322 // Base must be 16 byte aligned. If not just return and let caller handle it
6323 tst(base, 0x0f);
6324 br(Assembler::NE, fini);
6325 // Align base with ZVA length.
6326 neg(tmp, base);
6327 andr(tmp, tmp, zva_length - 1);
6328
6329 // tmp: the number of bytes to be filled to align the base with ZVA length.
6330 add(base, base, tmp);
6331 sub(cnt, cnt, tmp, Assembler::ASR, 3);
6332 adr(tmp2, initial_table_end);
6333 sub(tmp2, tmp2, tmp, Assembler::LSR, 2);
6334 br(tmp2);
6335
6336 for (int i = -zva_length + 16; i < 0; i += 16)
6337 stp(zr, zr, Address(base, i));
6338 bind(initial_table_end);
6339
6340 sub(cnt, cnt, zva_length >> 3);
6341 bind(loop_zva);
6342 dc(Assembler::ZVA, base);
6343 subs(cnt, cnt, zva_length >> 3);
6344 add(base, base, zva_length);
6345 br(Assembler::GE, loop_zva);
6346 add(cnt, cnt, zva_length >> 3); // count not zeroed by DC ZVA
6347 bind(fini);
6348 }
6349
6350 // base: Address of a buffer to be filled, 8 bytes aligned.
6351 // cnt: Count in 8-byte unit.
6352 // value: Value to be filled with.
6353 // base will point to the end of the buffer after filling.
6354 void MacroAssembler::fill_words(Register base, Register cnt, Register value)
6355 {
6356 // Algorithm:
6357 //
6358 // if (cnt == 0) {
6359 // return;
6360 // }
6361 // if ((p & 8) != 0) {
6362 // *p++ = v;
6363 // }
6364 //
6365 // scratch1 = cnt & 14;
6366 // cnt -= scratch1;
6367 // p += scratch1;
6368 // switch (scratch1 / 2) {
6369 // do {
6370 // cnt -= 16;
6371 // p[-16] = v;
6372 // p[-15] = v;
6373 // case 7:
6374 // p[-14] = v;
6375 // p[-13] = v;
6376 // case 6:
6377 // p[-12] = v;
6378 // p[-11] = v;
6379 // // ...
6380 // case 1:
6381 // p[-2] = v;
6382 // p[-1] = v;
6383 // case 0:
6384 // p += 16;
6385 // } while (cnt);
6386 // }
6387 // if ((cnt & 1) == 1) {
6388 // *p++ = v;
6389 // }
6390
6391 assert_different_registers(base, cnt, value, rscratch1, rscratch2);
6392
6393 Label fini, skip, entry, loop;
6394 const int unroll = 8; // Number of stp instructions we'll unroll
6395
6396 cbz(cnt, fini);
6397 tbz(base, 3, skip);
6398 str(value, Address(post(base, 8)));
6399 sub(cnt, cnt, 1);
6400 bind(skip);
6401
6402 andr(rscratch1, cnt, (unroll-1) * 2);
6403 sub(cnt, cnt, rscratch1);
6404 add(base, base, rscratch1, Assembler::LSL, 3);
6405 adr(rscratch2, entry);
6406 sub(rscratch2, rscratch2, rscratch1, Assembler::LSL, 1);
6407 br(rscratch2);
6408
6409 bind(loop);
6410 add(base, base, unroll * 16);
6411 for (int i = -unroll; i < 0; i++)
6412 stp(value, value, Address(base, i * 16));
6413 bind(entry);
6414 subs(cnt, cnt, unroll * 2);
6415 br(Assembler::GE, loop);
6416
6417 tbz(cnt, 0, fini);
6418 str(value, Address(post(base, 8)));
6419 bind(fini);
6420 }
6421
6422 // Intrinsic for
6423 //
6424 // - sun/nio/cs/ISO_8859_1$Encoder.implEncodeISOArray
6425 // return the number of characters copied.
6426 // - java/lang/StringUTF16.compress
6427 // return index of non-latin1 character if copy fails, otherwise 'len'.
6428 //
6429 // This version always returns the number of characters copied, and does not
6430 // clobber the 'len' register. A successful copy will complete with the post-
6431 // condition: 'res' == 'len', while an unsuccessful copy will exit with the
6432 // post-condition: 0 <= 'res' < 'len'.
6433 //
6434 // NOTE: Attempts to use 'ld2' (and 'umaxv' in the ISO part) has proven to
6435 // degrade performance (on Ampere Altra - Neoverse N1), to an extent
6436 // beyond the acceptable, even though the footprint would be smaller.
6437 // Using 'umaxv' in the ASCII-case comes with a small penalty but does
6438 // avoid additional bloat.
6439 //
6440 // Clobbers: src, dst, res, rscratch1, rscratch2, rflags
6441 void MacroAssembler::encode_iso_array(Register src, Register dst,
6442 Register len, Register res, bool ascii,
6443 FloatRegister vtmp0, FloatRegister vtmp1,
6444 FloatRegister vtmp2, FloatRegister vtmp3,
6445 FloatRegister vtmp4, FloatRegister vtmp5)
6446 {
6447 Register cnt = res;
6448 Register max = rscratch1;
6449 Register chk = rscratch2;
6450
6451 prfm(Address(src), PLDL1STRM);
6452 movw(cnt, len);
6453
6454 #define ASCII(insn) do { if (ascii) { insn; } } while (0)
6455
6456 Label LOOP_32, DONE_32, FAIL_32;
6457
6458 BIND(LOOP_32);
6459 {
6460 cmpw(cnt, 32);
6461 br(LT, DONE_32);
6462 ld1(vtmp0, vtmp1, vtmp2, vtmp3, T8H, Address(post(src, 64)));
6463 // Extract lower bytes.
6464 FloatRegister vlo0 = vtmp4;
6465 FloatRegister vlo1 = vtmp5;
6466 uzp1(vlo0, T16B, vtmp0, vtmp1);
6467 uzp1(vlo1, T16B, vtmp2, vtmp3);
6468 // Merge bits...
6469 orr(vtmp0, T16B, vtmp0, vtmp1);
6470 orr(vtmp2, T16B, vtmp2, vtmp3);
6471 // Extract merged upper bytes.
6472 FloatRegister vhix = vtmp0;
6473 uzp2(vhix, T16B, vtmp0, vtmp2);
6474 // ISO-check on hi-parts (all zero).
6475 // ASCII-check on lo-parts (no sign).
6476 FloatRegister vlox = vtmp1; // Merge lower bytes.
6477 ASCII(orr(vlox, T16B, vlo0, vlo1));
6478 umov(chk, vhix, D, 1); ASCII(cm(LT, vlox, T16B, vlox));
6479 fmovd(max, vhix); ASCII(umaxv(vlox, T16B, vlox));
6480 orr(chk, chk, max); ASCII(umov(max, vlox, B, 0));
6481 ASCII(orr(chk, chk, max));
6482 cbnz(chk, FAIL_32);
6483 subw(cnt, cnt, 32);
6484 st1(vlo0, vlo1, T16B, Address(post(dst, 32)));
6485 b(LOOP_32);
6486 }
6487 BIND(FAIL_32);
6488 sub(src, src, 64);
6489 BIND(DONE_32);
6490
6491 Label LOOP_8, SKIP_8;
6492
6493 BIND(LOOP_8);
6494 {
6495 cmpw(cnt, 8);
6496 br(LT, SKIP_8);
6497 FloatRegister vhi = vtmp0;
6498 FloatRegister vlo = vtmp1;
6499 ld1(vtmp3, T8H, src);
6500 uzp1(vlo, T16B, vtmp3, vtmp3);
6501 uzp2(vhi, T16B, vtmp3, vtmp3);
6502 // ISO-check on hi-parts (all zero).
6503 // ASCII-check on lo-parts (no sign).
6504 ASCII(cm(LT, vtmp2, T16B, vlo));
6505 fmovd(chk, vhi); ASCII(umaxv(vtmp2, T16B, vtmp2));
6506 ASCII(umov(max, vtmp2, B, 0));
6507 ASCII(orr(chk, chk, max));
6508 cbnz(chk, SKIP_8);
6509
6510 strd(vlo, Address(post(dst, 8)));
6511 subw(cnt, cnt, 8);
6512 add(src, src, 16);
6513 b(LOOP_8);
6514 }
6515 BIND(SKIP_8);
6516
6517 #undef ASCII
6518
6519 Label LOOP, DONE;
6520
6521 cbz(cnt, DONE);
6522 BIND(LOOP);
6523 {
6524 Register chr = rscratch1;
6525 ldrh(chr, Address(post(src, 2)));
6526 tst(chr, ascii ? 0xff80 : 0xff00);
6527 br(NE, DONE);
6528 strb(chr, Address(post(dst, 1)));
6529 subs(cnt, cnt, 1);
6530 br(GT, LOOP);
6531 }
6532 BIND(DONE);
6533 // Return index where we stopped.
6534 subw(res, len, cnt);
6535 }
6536
6537 // Inflate byte[] array to char[].
6538 // Clobbers: src, dst, len, rflags, rscratch1, v0-v6
6539 address MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
6540 FloatRegister vtmp1, FloatRegister vtmp2,
6541 FloatRegister vtmp3, Register tmp4) {
6542 Label big, done, after_init, to_stub;
6543
6544 assert_different_registers(src, dst, len, tmp4, rscratch1);
6545
6546 fmovd(vtmp1, 0.0);
6547 lsrw(tmp4, len, 3);
6548 bind(after_init);
6549 cbnzw(tmp4, big);
6550 // Short string: less than 8 bytes.
6551 {
6552 Label loop, tiny;
6553
6554 cmpw(len, 4);
6555 br(LT, tiny);
6556 // Use SIMD to do 4 bytes.
6557 ldrs(vtmp2, post(src, 4));
6558 zip1(vtmp3, T8B, vtmp2, vtmp1);
6559 subw(len, len, 4);
6560 strd(vtmp3, post(dst, 8));
6561
6562 cbzw(len, done);
6563
6564 // Do the remaining bytes by steam.
6565 bind(loop);
6566 ldrb(tmp4, post(src, 1));
6567 strh(tmp4, post(dst, 2));
6568 subw(len, len, 1);
6569
6570 bind(tiny);
6571 cbnz(len, loop);
6572
6573 b(done);
6574 }
6575
6576 if (SoftwarePrefetchHintDistance >= 0) {
6577 bind(to_stub);
6578 RuntimeAddress stub = RuntimeAddress(StubRoutines::aarch64::large_byte_array_inflate());
6579 assert(stub.target() != nullptr, "large_byte_array_inflate stub has not been generated");
6580 address tpc = trampoline_call(stub);
6581 if (tpc == nullptr) {
6582 DEBUG_ONLY(reset_labels(big, done));
6583 postcond(pc() == badAddress);
6584 return nullptr;
6585 }
6586 b(after_init);
6587 }
6588
6589 // Unpack the bytes 8 at a time.
6590 bind(big);
6591 {
6592 Label loop, around, loop_last, loop_start;
6593
6594 if (SoftwarePrefetchHintDistance >= 0) {
6595 const int large_loop_threshold = (64 + 16)/8;
6596 ldrd(vtmp2, post(src, 8));
6597 andw(len, len, 7);
6598 cmp(tmp4, (u1)large_loop_threshold);
6599 br(GE, to_stub);
6600 b(loop_start);
6601
6602 bind(loop);
6603 ldrd(vtmp2, post(src, 8));
6604 bind(loop_start);
6605 subs(tmp4, tmp4, 1);
6606 br(EQ, loop_last);
6607 zip1(vtmp2, T16B, vtmp2, vtmp1);
6608 ldrd(vtmp3, post(src, 8));
6609 st1(vtmp2, T8H, post(dst, 16));
6610 subs(tmp4, tmp4, 1);
6611 zip1(vtmp3, T16B, vtmp3, vtmp1);
6612 st1(vtmp3, T8H, post(dst, 16));
6613 br(NE, loop);
6614 b(around);
6615 bind(loop_last);
6616 zip1(vtmp2, T16B, vtmp2, vtmp1);
6617 st1(vtmp2, T8H, post(dst, 16));
6618 bind(around);
6619 cbz(len, done);
6620 } else {
6621 andw(len, len, 7);
6622 bind(loop);
6623 ldrd(vtmp2, post(src, 8));
6624 sub(tmp4, tmp4, 1);
6625 zip1(vtmp3, T16B, vtmp2, vtmp1);
6626 st1(vtmp3, T8H, post(dst, 16));
6627 cbnz(tmp4, loop);
6628 }
6629 }
6630
6631 // Do the tail of up to 8 bytes.
6632 add(src, src, len);
6633 ldrd(vtmp3, Address(src, -8));
6634 add(dst, dst, len, ext::uxtw, 1);
6635 zip1(vtmp3, T16B, vtmp3, vtmp1);
6636 strq(vtmp3, Address(dst, -16));
6637
6638 bind(done);
6639 postcond(pc() != badAddress);
6640 return pc();
6641 }
6642
6643 // Compress char[] array to byte[].
6644 // Intrinsic for java.lang.StringUTF16.compress(char[] src, int srcOff, byte[] dst, int dstOff, int len)
6645 // Return the array length if every element in array can be encoded,
6646 // otherwise, the index of first non-latin1 (> 0xff) character.
6647 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
6648 Register res,
6649 FloatRegister tmp0, FloatRegister tmp1,
6650 FloatRegister tmp2, FloatRegister tmp3,
6651 FloatRegister tmp4, FloatRegister tmp5) {
6652 encode_iso_array(src, dst, len, res, false, tmp0, tmp1, tmp2, tmp3, tmp4, tmp5);
6653 }
6654
6655 // java.math.round(double a)
6656 // Returns the closest long to the argument, with ties rounding to
6657 // positive infinity. This requires some fiddling for corner
6658 // cases. We take care to avoid double rounding in e.g. (jlong)(a + 0.5).
6659 void MacroAssembler::java_round_double(Register dst, FloatRegister src,
6660 FloatRegister ftmp) {
6661 Label DONE;
6662 BLOCK_COMMENT("java_round_double: { ");
6663 fmovd(rscratch1, src);
6664 // Use RoundToNearestTiesAway unless src small and -ve.
6665 fcvtasd(dst, src);
6666 // Test if src >= 0 || abs(src) >= 0x1.0p52
6667 eor(rscratch1, rscratch1, UCONST64(1) << 63); // flip sign bit
6668 mov(rscratch2, julong_cast(0x1.0p52));
6669 cmp(rscratch1, rscratch2);
6670 br(HS, DONE); {
6671 // src < 0 && abs(src) < 0x1.0p52
6672 // src may have a fractional part, so add 0.5
6673 fmovd(ftmp, 0.5);
6674 faddd(ftmp, src, ftmp);
6675 // Convert double to jlong, use RoundTowardsNegative
6676 fcvtmsd(dst, ftmp);
6677 }
6678 bind(DONE);
6679 BLOCK_COMMENT("} java_round_double");
6680 }
6681
6682 void MacroAssembler::java_round_float(Register dst, FloatRegister src,
6683 FloatRegister ftmp) {
6684 Label DONE;
6685 BLOCK_COMMENT("java_round_float: { ");
6686 fmovs(rscratch1, src);
6687 // Use RoundToNearestTiesAway unless src small and -ve.
6688 fcvtassw(dst, src);
6689 // Test if src >= 0 || abs(src) >= 0x1.0p23
6690 eor(rscratch1, rscratch1, 0x80000000); // flip sign bit
6691 mov(rscratch2, jint_cast(0x1.0p23f));
6692 cmp(rscratch1, rscratch2);
6693 br(HS, DONE); {
6694 // src < 0 && |src| < 0x1.0p23
6695 // src may have a fractional part, so add 0.5
6696 fmovs(ftmp, 0.5f);
6697 fadds(ftmp, src, ftmp);
6698 // Convert float to jint, use RoundTowardsNegative
6699 fcvtmssw(dst, ftmp);
6700 }
6701 bind(DONE);
6702 BLOCK_COMMENT("} java_round_float");
6703 }
6704
6705 // get_thread() can be called anywhere inside generated code so we
6706 // need to save whatever non-callee save context might get clobbered
6707 // by the call to JavaThread::aarch64_get_thread_helper() or, indeed,
6708 // the call setup code.
6709 //
6710 // On Linux, aarch64_get_thread_helper() clobbers only r0, r1, and flags.
6711 // On other systems, the helper is a usual C function.
6712 //
6713 void MacroAssembler::get_thread(Register dst) {
6714 RegSet saved_regs =
6715 LINUX_ONLY(RegSet::range(r0, r1) + lr - dst)
6716 NOT_LINUX (RegSet::range(r0, r17) + lr - dst);
6717
6718 protect_return_address();
6719 push(saved_regs, sp);
6720
6721 mov(lr, ExternalAddress(CAST_FROM_FN_PTR(address, JavaThread::aarch64_get_thread_helper)));
6722 blr(lr);
6723 if (dst != c_rarg0) {
6724 mov(dst, c_rarg0);
6725 }
6726
6727 pop(saved_regs, sp);
6728 authenticate_return_address();
6729 }
6730
6731 void MacroAssembler::cache_wb(Address line) {
6732 assert(line.getMode() == Address::base_plus_offset, "mode should be base_plus_offset");
6733 assert(line.index() == noreg, "index should be noreg");
6734 assert(line.offset() == 0, "offset should be 0");
6735 // would like to assert this
6736 // assert(line._ext.shift == 0, "shift should be zero");
6737 if (VM_Version::supports_dcpop()) {
6738 // writeback using clear virtual address to point of persistence
6739 dc(Assembler::CVAP, line.base());
6740 } else {
6741 // no need to generate anything as Unsafe.writebackMemory should
6742 // never invoke this stub
6743 }
6744 }
6745
6746 void MacroAssembler::cache_wbsync(bool is_pre) {
6747 // we only need a barrier post sync
6748 if (!is_pre) {
6749 membar(Assembler::AnyAny);
6750 }
6751 }
6752
6753 void MacroAssembler::verify_sve_vector_length(Register tmp) {
6754 if (!UseSVE || VM_Version::get_max_supported_sve_vector_length() == FloatRegister::sve_vl_min) {
6755 return;
6756 }
6757 // Make sure that native code does not change SVE vector length.
6758 Label verify_ok;
6759 movw(tmp, zr);
6760 sve_inc(tmp, B);
6761 subsw(zr, tmp, VM_Version::get_initial_sve_vector_length());
6762 br(EQ, verify_ok);
6763 stop("Error: SVE vector length has changed since jvm startup");
6764 bind(verify_ok);
6765 }
6766
6767 void MacroAssembler::verify_ptrue() {
6768 Label verify_ok;
6769 if (!UseSVE) {
6770 return;
6771 }
6772 sve_cntp(rscratch1, B, ptrue, ptrue); // get true elements count.
6773 sve_dec(rscratch1, B);
6774 cbz(rscratch1, verify_ok);
6775 stop("Error: the preserved predicate register (p7) elements are not all true");
6776 bind(verify_ok);
6777 }
6778
6779 void MacroAssembler::safepoint_isb() {
6780 isb();
6781 #ifndef PRODUCT
6782 if (VerifyCrossModifyFence) {
6783 // Clear the thread state.
6784 strb(zr, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6785 }
6786 #endif
6787 }
6788
6789 #ifndef PRODUCT
6790 void MacroAssembler::verify_cross_modify_fence_not_required() {
6791 if (VerifyCrossModifyFence) {
6792 // Check if thread needs a cross modify fence.
6793 ldrb(rscratch1, Address(rthread, in_bytes(JavaThread::requires_cross_modify_fence_offset())));
6794 Label fence_not_required;
6795 cbz(rscratch1, fence_not_required);
6796 // If it does then fail.
6797 lea(rscratch1, RuntimeAddress(CAST_FROM_FN_PTR(address, JavaThread::verify_cross_modify_fence_failure)));
6798 mov(c_rarg0, rthread);
6799 blr(rscratch1);
6800 bind(fence_not_required);
6801 }
6802 }
6803 #endif
6804
6805 void MacroAssembler::spin_wait() {
6806 for (int i = 0; i < VM_Version::spin_wait_desc().inst_count(); ++i) {
6807 switch (VM_Version::spin_wait_desc().inst()) {
6808 case SpinWait::NOP:
6809 nop();
6810 break;
6811 case SpinWait::ISB:
6812 isb();
6813 break;
6814 case SpinWait::YIELD:
6815 yield();
6816 break;
6817 case SpinWait::SB:
6818 sb();
6819 break;
6820 default:
6821 ShouldNotReachHere();
6822 }
6823 }
6824 }
6825
6826 // Stack frame creation/removal
6827
6828 void MacroAssembler::enter(bool strip_ret_addr) {
6829 if (strip_ret_addr) {
6830 // Addresses can only be signed once. If there are multiple nested frames being created
6831 // in the same function, then the return address needs stripping first.
6832 strip_return_address();
6833 }
6834 protect_return_address();
6835 stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
6836 mov(rfp, sp);
6837 }
6838
6839 void MacroAssembler::leave() {
6840 mov(sp, rfp);
6841 ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
6842 authenticate_return_address();
6843 }
6844
6845 // ROP Protection
6846 // Use the AArch64 PAC feature to add ROP protection for generated code. Use whenever creating/
6847 // destroying stack frames or whenever directly loading/storing the LR to memory.
6848 // If ROP protection is not set then these functions are no-ops.
6849 // For more details on PAC see pauth_aarch64.hpp.
6850
6851 // Sign the LR. Use during construction of a stack frame, before storing the LR to memory.
6852 // Uses value zero as the modifier.
6853 //
6854 void MacroAssembler::protect_return_address() {
6855 if (VM_Version::use_rop_protection()) {
6856 check_return_address();
6857 paciaz();
6858 }
6859 }
6860
6861 // Sign the return value in the given register. Use before updating the LR in the existing stack
6862 // frame for the current function.
6863 // Uses value zero as the modifier.
6864 //
6865 void MacroAssembler::protect_return_address(Register return_reg) {
6866 if (VM_Version::use_rop_protection()) {
6867 check_return_address(return_reg);
6868 paciza(return_reg);
6869 }
6870 }
6871
6872 // Authenticate the LR. Use before function return, after restoring FP and loading LR from memory.
6873 // Uses value zero as the modifier.
6874 //
6875 void MacroAssembler::authenticate_return_address() {
6876 if (VM_Version::use_rop_protection()) {
6877 autiaz();
6878 check_return_address();
6879 }
6880 }
6881
6882 // Authenticate the return value in the given register. Use before updating the LR in the existing
6883 // stack frame for the current function.
6884 // Uses value zero as the modifier.
6885 //
6886 void MacroAssembler::authenticate_return_address(Register return_reg) {
6887 if (VM_Version::use_rop_protection()) {
6888 autiza(return_reg);
6889 check_return_address(return_reg);
6890 }
6891 }
6892
6893 // Strip any PAC data from LR without performing any authentication. Use with caution - only if
6894 // there is no guaranteed way of authenticating the LR.
6895 //
6896 void MacroAssembler::strip_return_address() {
6897 if (VM_Version::use_rop_protection()) {
6898 xpaclri();
6899 }
6900 }
6901
6902 #ifndef PRODUCT
6903 // PAC failures can be difficult to debug. After an authentication failure, a segfault will only
6904 // occur when the pointer is used - ie when the program returns to the invalid LR. At this point
6905 // it is difficult to debug back to the callee function.
6906 // This function simply loads from the address in the given register.
6907 // Use directly after authentication to catch authentication failures.
6908 // Also use before signing to check that the pointer is valid and hasn't already been signed.
6909 //
6910 void MacroAssembler::check_return_address(Register return_reg) {
6911 if (VM_Version::use_rop_protection()) {
6912 ldr(zr, Address(return_reg));
6913 }
6914 }
6915 #endif
6916
6917 // The java_calling_convention describes stack locations as ideal slots on
6918 // a frame with no abi restrictions. Since we must observe abi restrictions
6919 // (like the placement of the register window) the slots must be biased by
6920 // the following value.
6921 static int reg2offset_in(VMReg r) {
6922 // Account for saved rfp and lr
6923 // This should really be in_preserve_stack_slots
6924 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
6925 }
6926
6927 static int reg2offset_out(VMReg r) {
6928 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
6929 }
6930
6931 // On 64bit we will store integer like items to the stack as
6932 // 64bits items (AArch64 ABI) even though java would only store
6933 // 32bits for a parameter. On 32bit it will simply be 32bits
6934 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
6935 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp) {
6936 if (src.first()->is_stack()) {
6937 if (dst.first()->is_stack()) {
6938 // stack to stack
6939 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
6940 str(tmp, Address(sp, reg2offset_out(dst.first())));
6941 } else {
6942 // stack to reg
6943 ldrsw(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
6944 }
6945 } else if (dst.first()->is_stack()) {
6946 // reg to stack
6947 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
6948 } else {
6949 if (dst.first() != src.first()) {
6950 sxtw(dst.first()->as_Register(), src.first()->as_Register());
6951 }
6952 }
6953 }
6954
6955 // An oop arg. Must pass a handle not the oop itself
6956 void MacroAssembler::object_move(
6957 OopMap* map,
6958 int oop_handle_offset,
6959 int framesize_in_slots,
6960 VMRegPair src,
6961 VMRegPair dst,
6962 bool is_receiver,
6963 int* receiver_offset) {
6964
6965 // must pass a handle. First figure out the location we use as a handle
6966
6967 Register rHandle = dst.first()->is_stack() ? rscratch2 : dst.first()->as_Register();
6968
6969 // See if oop is null if it is we need no handle
6970
6971 if (src.first()->is_stack()) {
6972
6973 // Oop is already on the stack as an argument
6974 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
6975 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
6976 if (is_receiver) {
6977 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
6978 }
6979
6980 ldr(rscratch1, Address(rfp, reg2offset_in(src.first())));
6981 lea(rHandle, Address(rfp, reg2offset_in(src.first())));
6982 // conditionally move a null
6983 cmp(rscratch1, zr);
6984 csel(rHandle, zr, rHandle, Assembler::EQ);
6985 } else {
6986
6987 // Oop is in an a register we must store it to the space we reserve
6988 // on the stack for oop_handles and pass a handle if oop is non-null
6989
6990 const Register rOop = src.first()->as_Register();
6991 int oop_slot;
6992 if (rOop == j_rarg0)
6993 oop_slot = 0;
6994 else if (rOop == j_rarg1)
6995 oop_slot = 1;
6996 else if (rOop == j_rarg2)
6997 oop_slot = 2;
6998 else if (rOop == j_rarg3)
6999 oop_slot = 3;
7000 else if (rOop == j_rarg4)
7001 oop_slot = 4;
7002 else if (rOop == j_rarg5)
7003 oop_slot = 5;
7004 else if (rOop == j_rarg6)
7005 oop_slot = 6;
7006 else {
7007 assert(rOop == j_rarg7, "wrong register");
7008 oop_slot = 7;
7009 }
7010
7011 oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
7012 int offset = oop_slot*VMRegImpl::stack_slot_size;
7013
7014 map->set_oop(VMRegImpl::stack2reg(oop_slot));
7015 // Store oop in handle area, may be null
7016 str(rOop, Address(sp, offset));
7017 if (is_receiver) {
7018 *receiver_offset = offset;
7019 }
7020
7021 cmp(rOop, zr);
7022 lea(rHandle, Address(sp, offset));
7023 // conditionally move a null
7024 csel(rHandle, zr, rHandle, Assembler::EQ);
7025 }
7026
7027 // If arg is on the stack then place it otherwise it is already in correct reg.
7028 if (dst.first()->is_stack()) {
7029 str(rHandle, Address(sp, reg2offset_out(dst.first())));
7030 }
7031 }
7032
7033 // A float arg may have to do float reg int reg conversion
7034 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp) {
7035 if (src.first()->is_stack()) {
7036 if (dst.first()->is_stack()) {
7037 ldrw(tmp, Address(rfp, reg2offset_in(src.first())));
7038 strw(tmp, Address(sp, reg2offset_out(dst.first())));
7039 } else {
7040 ldrs(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7041 }
7042 } else if (src.first() != dst.first()) {
7043 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7044 fmovs(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7045 else
7046 strs(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7047 }
7048 }
7049
7050 // A long move
7051 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp) {
7052 if (src.first()->is_stack()) {
7053 if (dst.first()->is_stack()) {
7054 // stack to stack
7055 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7056 str(tmp, Address(sp, reg2offset_out(dst.first())));
7057 } else {
7058 // stack to reg
7059 ldr(dst.first()->as_Register(), Address(rfp, reg2offset_in(src.first())));
7060 }
7061 } else if (dst.first()->is_stack()) {
7062 // reg to stack
7063 // Do we really have to sign extend???
7064 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
7065 str(src.first()->as_Register(), Address(sp, reg2offset_out(dst.first())));
7066 } else {
7067 if (dst.first() != src.first()) {
7068 mov(dst.first()->as_Register(), src.first()->as_Register());
7069 }
7070 }
7071 }
7072
7073
7074 // A double move
7075 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp) {
7076 if (src.first()->is_stack()) {
7077 if (dst.first()->is_stack()) {
7078 ldr(tmp, Address(rfp, reg2offset_in(src.first())));
7079 str(tmp, Address(sp, reg2offset_out(dst.first())));
7080 } else {
7081 ldrd(dst.first()->as_FloatRegister(), Address(rfp, reg2offset_in(src.first())));
7082 }
7083 } else if (src.first() != dst.first()) {
7084 if (src.is_single_phys_reg() && dst.is_single_phys_reg())
7085 fmovd(dst.first()->as_FloatRegister(), src.first()->as_FloatRegister());
7086 else
7087 strd(src.first()->as_FloatRegister(), Address(sp, reg2offset_out(dst.first())));
7088 }
7089 }
7090
7091 // Implements lightweight-locking.
7092 //
7093 // - obj: the object to be locked
7094 // - t1, t2, t3: temporary registers, will be destroyed
7095 // - slow: branched to if locking fails, absolute offset may larger than 32KB (imm14 encoding).
7096 void MacroAssembler::lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow) {
7097 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7098 assert_different_registers(basic_lock, obj, t1, t2, t3, rscratch1);
7099
7100 Label push;
7101 const Register top = t1;
7102 const Register mark = t2;
7103 const Register t = t3;
7104
7105 // Preload the markWord. It is important that this is the first
7106 // instruction emitted as it is part of C1's null check semantics.
7107 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7108
7109 if (UseObjectMonitorTable) {
7110 // Clear cache in case fast locking succeeds or we need to take the slow-path.
7111 str(zr, Address(basic_lock, BasicObjectLock::lock_offset() + in_ByteSize((BasicLock::object_monitor_cache_offset_in_bytes()))));
7112 }
7113
7114 if (DiagnoseSyncOnValueBasedClasses != 0) {
7115 load_klass(t1, obj);
7116 ldrb(t1, Address(t1, Klass::misc_flags_offset()));
7117 tst(t1, KlassFlags::_misc_is_value_based_class);
7118 br(Assembler::NE, slow);
7119 }
7120
7121 // Check if the lock-stack is full.
7122 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7123 cmpw(top, (unsigned)LockStack::end_offset());
7124 br(Assembler::GE, slow);
7125
7126 // Check for recursion.
7127 subw(t, top, oopSize);
7128 ldr(t, Address(rthread, t));
7129 cmp(obj, t);
7130 br(Assembler::EQ, push);
7131
7132 // Check header for monitor (0b10).
7133 tst(mark, markWord::monitor_value);
7134 br(Assembler::NE, slow);
7135
7136 // Try to lock. Transition lock bits 0b01 => 0b00
7137 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7138 orr(mark, mark, markWord::unlocked_value);
7139 eor(t, mark, markWord::unlocked_value);
7140 cmpxchg(/*addr*/ obj, /*expected*/ mark, /*new*/ t, Assembler::xword,
7141 /*acquire*/ true, /*release*/ false, /*weak*/ false, noreg);
7142 br(Assembler::NE, slow);
7143
7144 bind(push);
7145 // After successful lock, push object on lock-stack.
7146 str(obj, Address(rthread, top));
7147 addw(top, top, oopSize);
7148 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7149 }
7150
7151 // Implements lightweight-unlocking.
7152 //
7153 // - obj: the object to be unlocked
7154 // - t1, t2, t3: temporary registers
7155 // - slow: branched to if unlocking fails, absolute offset may larger than 32KB (imm14 encoding).
7156 void MacroAssembler::lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow) {
7157 assert(LockingMode == LM_LIGHTWEIGHT, "only used with new lightweight locking");
7158 // cmpxchg clobbers rscratch1.
7159 assert_different_registers(obj, t1, t2, t3, rscratch1);
7160
7161 #ifdef ASSERT
7162 {
7163 // Check for lock-stack underflow.
7164 Label stack_ok;
7165 ldrw(t1, Address(rthread, JavaThread::lock_stack_top_offset()));
7166 cmpw(t1, (unsigned)LockStack::start_offset());
7167 br(Assembler::GE, stack_ok);
7168 STOP("Lock-stack underflow");
7169 bind(stack_ok);
7170 }
7171 #endif
7172
7173 Label unlocked, push_and_slow;
7174 const Register top = t1;
7175 const Register mark = t2;
7176 const Register t = t3;
7177
7178 // Check if obj is top of lock-stack.
7179 ldrw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7180 subw(top, top, oopSize);
7181 ldr(t, Address(rthread, top));
7182 cmp(obj, t);
7183 br(Assembler::NE, slow);
7184
7185 // Pop lock-stack.
7186 DEBUG_ONLY(str(zr, Address(rthread, top));)
7187 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7188
7189 // Check if recursive.
7190 subw(t, top, oopSize);
7191 ldr(t, Address(rthread, t));
7192 cmp(obj, t);
7193 br(Assembler::EQ, unlocked);
7194
7195 // Not recursive. Check header for monitor (0b10).
7196 ldr(mark, Address(obj, oopDesc::mark_offset_in_bytes()));
7197 tbnz(mark, log2i_exact(markWord::monitor_value), push_and_slow);
7198
7199 #ifdef ASSERT
7200 // Check header not unlocked (0b01).
7201 Label not_unlocked;
7202 tbz(mark, log2i_exact(markWord::unlocked_value), not_unlocked);
7203 stop("lightweight_unlock already unlocked");
7204 bind(not_unlocked);
7205 #endif
7206
7207 // Try to unlock. Transition lock bits 0b00 => 0b01
7208 assert(oopDesc::mark_offset_in_bytes() == 0, "required to avoid lea");
7209 orr(t, mark, markWord::unlocked_value);
7210 cmpxchg(obj, mark, t, Assembler::xword,
7211 /*acquire*/ false, /*release*/ true, /*weak*/ false, noreg);
7212 br(Assembler::EQ, unlocked);
7213
7214 bind(push_and_slow);
7215 // Restore lock-stack and handle the unlock in runtime.
7216 DEBUG_ONLY(str(obj, Address(rthread, top));)
7217 addw(top, top, oopSize);
7218 strw(top, Address(rthread, JavaThread::lock_stack_top_offset()));
7219 b(slow);
7220
7221 bind(unlocked);
7222 }