1 /*
2 * Copyright (c) 1997, 2025, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2024, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "code/aotCodeCache.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "oops/compressedKlass.hpp"
35 #include "runtime/vm_version.hpp"
36 #include "utilities/powerOfTwo.hpp"
37
38 class OopMap;
39
40 // MacroAssembler extends Assembler by frequently used macros.
41 //
42 // Instructions for which a 'better' code sequence exists depending
43 // on arguments should also go in here.
44
45 class MacroAssembler: public Assembler {
46 friend class LIR_Assembler;
47
48 public:
49 using Assembler::mov;
50 using Assembler::movi;
51
52 protected:
53
54 // Support for VM calls
55 //
56 // This is the base routine called by the different versions of call_VM_leaf. The interpreter
57 // may customize this version by overriding it for its purposes (e.g., to save/restore
58 // additional registers when doing a VM call).
59 virtual void call_VM_leaf_base(
60 address entry_point, // the entry point
61 int number_of_arguments, // the number of arguments to pop after the call
62 Label *retaddr = nullptr
63 );
64
65 virtual void call_VM_leaf_base(
66 address entry_point, // the entry point
67 int number_of_arguments, // the number of arguments to pop after the call
68 Label &retaddr) {
69 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
70 }
71
72 // This is the base routine called by the different versions of call_VM. The interpreter
73 // may customize this version by overriding it for its purposes (e.g., to save/restore
74 // additional registers when doing a VM call).
75 //
76 // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
77 // returns the register which contains the thread upon return. If a thread register has been
78 // specified, the return value will correspond to that register. If no last_java_sp is specified
79 // (noreg) than rsp will be used instead.
80 virtual void call_VM_base( // returns the register containing the thread upon return
81 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
82 Register java_thread, // the thread if computed before ; use noreg otherwise
83 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
84 Label* return_pc, // to set up last_Java_frame; use nullptr otherwise
85 address entry_point, // the entry point
86 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
87 bool check_exceptions // whether to check for pending exceptions after return
88 );
89
90 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
91
92 enum KlassDecodeMode {
93 KlassDecodeNone,
94 KlassDecodeZero,
95 KlassDecodeXor,
96 KlassDecodeMovk
97 };
98
99 // Calculate decoding mode based on given parameters, used for checking then ultimately setting.
100 static KlassDecodeMode klass_decode_mode(address base, int shift, const size_t range);
101
102 private:
103 static KlassDecodeMode _klass_decode_mode;
104
105 // Returns above setting with asserts
106 static KlassDecodeMode klass_decode_mode();
107
108 public:
109 // Checks the decode mode and returns false if not compatible with preferred decoding mode.
110 static bool check_klass_decode_mode(address base, int shift, const size_t range);
111
112 // Sets the decode mode and returns false if cannot be set.
113 static bool set_klass_decode_mode(address base, int shift, const size_t range);
114
115 public:
116 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
117
118 // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
119 // The implementation is only non-empty for the InterpreterMacroAssembler,
120 // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
121 virtual void check_and_handle_popframe(Register java_thread);
122 virtual void check_and_handle_earlyret(Register java_thread);
123
124 void safepoint_poll(Label& slow_path, bool at_return, bool in_nmethod, Register tmp = rscratch1);
125 void rt_call(address dest, Register tmp = rscratch1);
126
127 // Load Effective Address
128 void lea(Register r, const Address &a) {
129 InstructionMark im(this);
130 a.lea(this, r);
131 }
132
133 // Whether materializing the given address for a LDR/STR requires an
134 // additional lea instruction.
135 static bool legitimize_address_requires_lea(const Address &a, int size) {
136 return a.getMode() == Address::base_plus_offset &&
137 !Address::offset_ok_for_immed(a.offset(), exact_log2(size));
138 }
139
140 /* Sometimes we get misaligned loads and stores, usually from Unsafe
141 accesses, and these can exceed the offset range. */
142 Address legitimize_address(const Address &a, int size, Register scratch) {
143 if (legitimize_address_requires_lea(a, size)) {
144 block_comment("legitimize_address {");
145 lea(scratch, a);
146 block_comment("} legitimize_address");
147 return Address(scratch);
148 }
149 return a;
150 }
151
152 void addmw(Address a, Register incr, Register scratch) {
153 ldrw(scratch, a);
154 addw(scratch, scratch, incr);
155 strw(scratch, a);
156 }
157
158 // Add constant to memory word
159 void addmw(Address a, int imm, Register scratch) {
160 ldrw(scratch, a);
161 if (imm > 0)
162 addw(scratch, scratch, (unsigned)imm);
163 else
164 subw(scratch, scratch, (unsigned)-imm);
165 strw(scratch, a);
166 }
167
168 void bind(Label& L) {
169 Assembler::bind(L);
170 code()->clear_last_insn();
171 code()->set_last_label(pc());
172 }
173
174 void membar(Membar_mask_bits order_constraint);
175
176 using Assembler::ldr;
177 using Assembler::str;
178 using Assembler::ldrw;
179 using Assembler::strw;
180
181 void ldr(Register Rx, const Address &adr);
182 void ldrw(Register Rw, const Address &adr);
183 void str(Register Rx, const Address &adr);
184 void strw(Register Rx, const Address &adr);
185
186 // Frame creation and destruction shared between JITs.
187 void build_frame(int framesize);
188 void remove_frame(int framesize);
189
190 virtual void _call_Unimplemented(address call_site) {
191 mov(rscratch2, call_site);
192 }
193
194 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
195 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
196 // https://reviews.llvm.org/D3311
197
198 #ifdef _WIN64
199 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
200 #else
201 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
202 #endif
203
204 // aliases defined in AARCH64 spec
205
206 template<class T>
207 inline void cmpw(Register Rd, T imm) { subsw(zr, Rd, imm); }
208
209 inline void cmp(Register Rd, unsigned char imm8) { subs(zr, Rd, imm8); }
210 inline void cmp(Register Rd, unsigned imm) = delete;
211
212 template<class T>
213 inline void cmnw(Register Rd, T imm) { addsw(zr, Rd, imm); }
214
215 inline void cmn(Register Rd, unsigned char imm8) { adds(zr, Rd, imm8); }
216 inline void cmn(Register Rd, unsigned imm) = delete;
217
218 void cset(Register Rd, Assembler::Condition cond) {
219 csinc(Rd, zr, zr, ~cond);
220 }
221 void csetw(Register Rd, Assembler::Condition cond) {
222 csincw(Rd, zr, zr, ~cond);
223 }
224
225 void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
226 csneg(Rd, Rn, Rn, ~cond);
227 }
228 void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
229 csnegw(Rd, Rn, Rn, ~cond);
230 }
231
232 inline void movw(Register Rd, Register Rn) {
233 if (Rd == sp || Rn == sp) {
234 Assembler::addw(Rd, Rn, 0U);
235 } else {
236 orrw(Rd, zr, Rn);
237 }
238 }
239 inline void mov(Register Rd, Register Rn) {
240 assert(Rd != r31_sp && Rn != r31_sp, "should be");
241 if (Rd == Rn) {
242 } else if (Rd == sp || Rn == sp) {
243 Assembler::add(Rd, Rn, 0U);
244 } else {
245 orr(Rd, zr, Rn);
246 }
247 }
248
249 inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
250 inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
251
252 inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
253 inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
254
255 inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
256 inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
257
258 inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
259 bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
260 }
261 inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
262 bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
263 }
264
265 inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
266 bfmw(Rd, Rn, lsb, (lsb + width - 1));
267 }
268 inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
269 bfm(Rd, Rn, lsb , (lsb + width - 1));
270 }
271
272 inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
273 sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
274 }
275 inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
276 sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
277 }
278
279 inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
280 sbfmw(Rd, Rn, lsb, (lsb + width - 1));
281 }
282 inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
283 sbfm(Rd, Rn, lsb , (lsb + width - 1));
284 }
285
286 inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
287 ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
288 }
289 inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
290 ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
291 }
292
293 inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
294 ubfmw(Rd, Rn, lsb, (lsb + width - 1));
295 }
296 inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
297 ubfm(Rd, Rn, lsb , (lsb + width - 1));
298 }
299
300 inline void asrw(Register Rd, Register Rn, unsigned imm) {
301 sbfmw(Rd, Rn, imm, 31);
302 }
303
304 inline void asr(Register Rd, Register Rn, unsigned imm) {
305 sbfm(Rd, Rn, imm, 63);
306 }
307
308 inline void lslw(Register Rd, Register Rn, unsigned imm) {
309 ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
310 }
311
312 inline void lsl(Register Rd, Register Rn, unsigned imm) {
313 ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
314 }
315
316 inline void lsrw(Register Rd, Register Rn, unsigned imm) {
317 ubfmw(Rd, Rn, imm, 31);
318 }
319
320 inline void lsr(Register Rd, Register Rn, unsigned imm) {
321 ubfm(Rd, Rn, imm, 63);
322 }
323
324 inline void rorw(Register Rd, Register Rn, unsigned imm) {
325 extrw(Rd, Rn, Rn, imm);
326 }
327
328 inline void ror(Register Rd, Register Rn, unsigned imm) {
329 extr(Rd, Rn, Rn, imm);
330 }
331
332 inline void rolw(Register Rd, Register Rn, unsigned imm) {
333 extrw(Rd, Rn, Rn, (32 - imm));
334 }
335
336 inline void rol(Register Rd, Register Rn, unsigned imm) {
337 extr(Rd, Rn, Rn, (64 - imm));
338 }
339
340 using Assembler::rax1;
341 using Assembler::eor3;
342
343 inline void rax1(Register Rd, Register Rn, Register Rm) {
344 eor(Rd, Rn, Rm, ROR, 63); // Rd = Rn ^ rol(Rm, 1)
345 }
346
347 inline void eor3(Register Rd, Register Rn, Register Rm, Register Rk) {
348 assert(Rd != Rn, "Use tmp register");
349 eor(Rd, Rm, Rk);
350 eor(Rd, Rd, Rn);
351 }
352
353 inline void sxtbw(Register Rd, Register Rn) {
354 sbfmw(Rd, Rn, 0, 7);
355 }
356 inline void sxthw(Register Rd, Register Rn) {
357 sbfmw(Rd, Rn, 0, 15);
358 }
359 inline void sxtb(Register Rd, Register Rn) {
360 sbfm(Rd, Rn, 0, 7);
361 }
362 inline void sxth(Register Rd, Register Rn) {
363 sbfm(Rd, Rn, 0, 15);
364 }
365 inline void sxtw(Register Rd, Register Rn) {
366 sbfm(Rd, Rn, 0, 31);
367 }
368
369 inline void uxtbw(Register Rd, Register Rn) {
370 ubfmw(Rd, Rn, 0, 7);
371 }
372 inline void uxthw(Register Rd, Register Rn) {
373 ubfmw(Rd, Rn, 0, 15);
374 }
375 inline void uxtb(Register Rd, Register Rn) {
376 ubfm(Rd, Rn, 0, 7);
377 }
378 inline void uxth(Register Rd, Register Rn) {
379 ubfm(Rd, Rn, 0, 15);
380 }
381 inline void uxtw(Register Rd, Register Rn) {
382 ubfm(Rd, Rn, 0, 31);
383 }
384
385 inline void cmnw(Register Rn, Register Rm) {
386 addsw(zr, Rn, Rm);
387 }
388 inline void cmn(Register Rn, Register Rm) {
389 adds(zr, Rn, Rm);
390 }
391
392 inline void cmpw(Register Rn, Register Rm) {
393 subsw(zr, Rn, Rm);
394 }
395 inline void cmp(Register Rn, Register Rm) {
396 subs(zr, Rn, Rm);
397 }
398
399 inline void negw(Register Rd, Register Rn) {
400 subw(Rd, zr, Rn);
401 }
402
403 inline void neg(Register Rd, Register Rn) {
404 sub(Rd, zr, Rn);
405 }
406
407 inline void negsw(Register Rd, Register Rn) {
408 subsw(Rd, zr, Rn);
409 }
410
411 inline void negs(Register Rd, Register Rn) {
412 subs(Rd, zr, Rn);
413 }
414
415 inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
416 addsw(zr, Rn, Rm, kind, shift);
417 }
418 inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
419 adds(zr, Rn, Rm, kind, shift);
420 }
421
422 inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
423 subsw(zr, Rn, Rm, kind, shift);
424 }
425 inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
426 subs(zr, Rn, Rm, kind, shift);
427 }
428
429 inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
430 subw(Rd, zr, Rn, kind, shift);
431 }
432
433 inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
434 sub(Rd, zr, Rn, kind, shift);
435 }
436
437 inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
438 subsw(Rd, zr, Rn, kind, shift);
439 }
440
441 inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
442 subs(Rd, zr, Rn, kind, shift);
443 }
444
445 inline void mnegw(Register Rd, Register Rn, Register Rm) {
446 msubw(Rd, Rn, Rm, zr);
447 }
448 inline void mneg(Register Rd, Register Rn, Register Rm) {
449 msub(Rd, Rn, Rm, zr);
450 }
451
452 inline void mulw(Register Rd, Register Rn, Register Rm) {
453 maddw(Rd, Rn, Rm, zr);
454 }
455 inline void mul(Register Rd, Register Rn, Register Rm) {
456 madd(Rd, Rn, Rm, zr);
457 }
458
459 inline void smnegl(Register Rd, Register Rn, Register Rm) {
460 smsubl(Rd, Rn, Rm, zr);
461 }
462 inline void smull(Register Rd, Register Rn, Register Rm) {
463 smaddl(Rd, Rn, Rm, zr);
464 }
465
466 inline void umnegl(Register Rd, Register Rn, Register Rm) {
467 umsubl(Rd, Rn, Rm, zr);
468 }
469 inline void umull(Register Rd, Register Rn, Register Rm) {
470 umaddl(Rd, Rn, Rm, zr);
471 }
472
473 #define WRAP(INSN) \
474 void INSN(Register Rd, Register Rn, Register Rm, Register Ra) { \
475 if (VM_Version::supports_a53mac() && Ra != zr) \
476 nop(); \
477 Assembler::INSN(Rd, Rn, Rm, Ra); \
478 }
479
480 WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
481 WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
482 #undef WRAP
483
484
485 // macro assembly operations needed for aarch64
486
487 public:
488
489 enum FpPushPopMode {
490 PushPopFull,
491 PushPopSVE,
492 PushPopNeon,
493 PushPopFp
494 };
495
496 // first two private routines for loading 32 bit or 64 bit constants
497 private:
498
499 void mov_immediate64(Register dst, uint64_t imm64);
500 void mov_immediate32(Register dst, uint32_t imm32);
501
502 int push(unsigned int bitset, Register stack);
503 int pop(unsigned int bitset, Register stack);
504
505 int push_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
506 int pop_fp(unsigned int bitset, Register stack, FpPushPopMode mode);
507
508 int push_p(unsigned int bitset, Register stack);
509 int pop_p(unsigned int bitset, Register stack);
510
511 void mov(Register dst, Address a);
512
513 public:
514
515 void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
516 void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
517
518 void push_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) push_fp(regs.bits(), stack, mode); }
519 void pop_fp(FloatRegSet regs, Register stack, FpPushPopMode mode = PushPopFull) { if (regs.bits()) pop_fp(regs.bits(), stack, mode); }
520
521 static RegSet call_clobbered_gp_registers();
522
523 void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
524 void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
525
526 // Push and pop everything that might be clobbered by a native
527 // runtime call except rscratch1 and rscratch2. (They are always
528 // scratch, so we don't have to protect them.) Only save the lower
529 // 64 bits of each vector register. Additional registers can be excluded
530 // in a passed RegSet.
531 void push_call_clobbered_registers_except(RegSet exclude);
532 void pop_call_clobbered_registers_except(RegSet exclude);
533
534 void push_call_clobbered_registers() {
535 push_call_clobbered_registers_except(RegSet());
536 }
537 void pop_call_clobbered_registers() {
538 pop_call_clobbered_registers_except(RegSet());
539 }
540
541
542 // now mov instructions for loading absolute addresses and 32 or
543 // 64 bit integers
544
545 inline void mov(Register dst, address addr) { mov_immediate64(dst, (uint64_t)addr); }
546
547 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
548 inline void mov(Register dst, T o) { mov_immediate64(dst, (uint64_t)o); }
549
550 inline void movw(Register dst, uint32_t imm32) { mov_immediate32(dst, imm32); }
551
552 void mov(Register dst, RegisterOrConstant src) {
553 if (src.is_register())
554 mov(dst, src.as_register());
555 else
556 mov(dst, src.as_constant());
557 }
558
559 void movptr(Register r, uintptr_t imm64);
560
561 void mov(FloatRegister Vd, SIMD_Arrangement T, uint64_t imm64);
562
563 void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
564 orr(Vd, T, Vn, Vn);
565 }
566
567 void flt_to_flt16(Register dst, FloatRegister src, FloatRegister tmp) {
568 fcvtsh(tmp, src);
569 smov(dst, tmp, H, 0);
570 }
571
572 void flt16_to_flt(FloatRegister dst, Register src, FloatRegister tmp) {
573 mov(tmp, H, 0, src);
574 fcvths(dst, tmp);
575 }
576
577 // Generalized Test Bit And Branch, including a "far" variety which
578 // spans more than 32KiB.
579 void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
580 assert(cond == EQ || cond == NE, "must be");
581
582 if (isfar)
583 cond = ~cond;
584
585 void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
586 if (cond == Assembler::EQ)
587 branch = &Assembler::tbz;
588 else
589 branch = &Assembler::tbnz;
590
591 if (isfar) {
592 Label L;
593 (this->*branch)(Rt, bitpos, L);
594 b(dest);
595 bind(L);
596 } else {
597 (this->*branch)(Rt, bitpos, dest);
598 }
599 }
600
601 // macro instructions for accessing and updating floating point
602 // status register
603 //
604 // FPSR : op1 == 011
605 // CRn == 0100
606 // CRm == 0100
607 // op2 == 001
608
609 inline void get_fpsr(Register reg)
610 {
611 mrs(0b11, 0b0100, 0b0100, 0b001, reg);
612 }
613
614 inline void set_fpsr(Register reg)
615 {
616 msr(0b011, 0b0100, 0b0100, 0b001, reg);
617 }
618
619 inline void clear_fpsr()
620 {
621 msr(0b011, 0b0100, 0b0100, 0b001, zr);
622 }
623
624 // FPCR : op1 == 011
625 // CRn == 0100
626 // CRm == 0100
627 // op2 == 000
628
629 inline void get_fpcr(Register reg) {
630 mrs(0b11, 0b0100, 0b0100, 0b000, reg);
631 }
632
633 inline void set_fpcr(Register reg) {
634 msr(0b011, 0b0100, 0b0100, 0b000, reg);
635 }
636
637 // DCZID_EL0: op1 == 011
638 // CRn == 0000
639 // CRm == 0000
640 // op2 == 111
641 inline void get_dczid_el0(Register reg)
642 {
643 mrs(0b011, 0b0000, 0b0000, 0b111, reg);
644 }
645
646 // CTR_EL0: op1 == 011
647 // CRn == 0000
648 // CRm == 0000
649 // op2 == 001
650 inline void get_ctr_el0(Register reg)
651 {
652 mrs(0b011, 0b0000, 0b0000, 0b001, reg);
653 }
654
655 inline void get_nzcv(Register reg) {
656 mrs(0b011, 0b0100, 0b0010, 0b000, reg);
657 }
658
659 inline void set_nzcv(Register reg) {
660 msr(0b011, 0b0100, 0b0010, 0b000, reg);
661 }
662
663 // idiv variant which deals with MINLONG as dividend and -1 as divisor
664 int corrected_idivl(Register result, Register ra, Register rb,
665 bool want_remainder, Register tmp = rscratch1);
666 int corrected_idivq(Register result, Register ra, Register rb,
667 bool want_remainder, Register tmp = rscratch1);
668
669 // Support for null-checks
670 //
671 // Generates code that causes a null OS exception if the content of reg is null.
672 // If the accessed location is M[reg + offset] and the offset is known, provide the
673 // offset. No explicit code generation is needed if the offset is within a certain
674 // range (0 <= offset <= page_size).
675
676 virtual void null_check(Register reg, int offset = -1);
677 static bool needs_explicit_null_check(intptr_t offset);
678 static bool uses_implicit_null_check(void* address);
679
680 static address target_addr_for_insn(address insn_addr, unsigned insn);
681 static address target_addr_for_insn_or_null(address insn_addr, unsigned insn);
682 static address target_addr_for_insn(address insn_addr) {
683 unsigned insn = *(unsigned*)insn_addr;
684 return target_addr_for_insn(insn_addr, insn);
685 }
686 static address target_addr_for_insn_or_null(address insn_addr) {
687 unsigned insn = *(unsigned*)insn_addr;
688 return target_addr_for_insn_or_null(insn_addr, insn);
689 }
690
691 // Required platform-specific helpers for Label::patch_instructions.
692 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
693 static int pd_patch_instruction_size(address branch, address target);
694 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
695 pd_patch_instruction_size(branch, target);
696 }
697 static address pd_call_destination(address branch) {
698 return target_addr_for_insn(branch);
699 }
700 #ifndef PRODUCT
701 static void pd_print_patched_instruction(address branch);
702 #endif
703
704 static int patch_oop(address insn_addr, address o);
705 static int patch_narrow_klass(address insn_addr, narrowKlass n);
706
707 // Return whether code is emitted to a scratch blob.
708 virtual bool in_scratch_emit_size() {
709 return false;
710 }
711 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
712 static int max_trampoline_stub_size();
713 void emit_static_call_stub();
714 static int static_call_stub_size();
715
716 // The following 4 methods return the offset of the appropriate move instruction
717
718 // Support for fast byte/short loading with zero extension (depending on particular CPU)
719 int load_unsigned_byte(Register dst, Address src);
720 int load_unsigned_short(Register dst, Address src);
721
722 // Support for fast byte/short loading with sign extension (depending on particular CPU)
723 int load_signed_byte(Register dst, Address src);
724 int load_signed_short(Register dst, Address src);
725
726 int load_signed_byte32(Register dst, Address src);
727 int load_signed_short32(Register dst, Address src);
728
729 // Support for sign-extension (hi:lo = extend_sign(lo))
730 void extend_sign(Register hi, Register lo);
731
732 // Load and store values by size and signed-ness
733 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
734 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
735
736 // Support for inc/dec with optimal instruction selection depending on value
737
738 // x86_64 aliases an unqualified register/address increment and
739 // decrement to call incrementq and decrementq but also supports
740 // explicitly sized calls to incrementq/decrementq or
741 // incrementl/decrementl
742
743 // for aarch64 the proper convention would be to use
744 // increment/decrement for 64 bit operations and
745 // incrementw/decrementw for 32 bit operations. so when porting
746 // x86_64 code we can leave calls to increment/decrement as is,
747 // replace incrementq/decrementq with increment/decrement and
748 // replace incrementl/decrementl with incrementw/decrementw.
749
750 // n.b. increment/decrement calls with an Address destination will
751 // need to use a scratch register to load the value to be
752 // incremented. increment/decrement calls which add or subtract a
753 // constant value greater than 2^12 will need to use a 2nd scratch
754 // register to hold the constant. so, a register increment/decrement
755 // may trash rscratch2 and an address increment/decrement trash
756 // rscratch and rscratch2
757
758 void decrementw(Address dst, int value = 1);
759 void decrementw(Register reg, int value = 1);
760
761 void decrement(Register reg, int value = 1);
762 void decrement(Address dst, int value = 1);
763
764 void incrementw(Address dst, int value = 1);
765 void incrementw(Register reg, int value = 1);
766
767 void increment(Register reg, int value = 1);
768 void increment(Address dst, int value = 1);
769
770
771 // Alignment
772 void align(int modulus);
773 void align(int modulus, int target);
774
775 // nop
776 void post_call_nop();
777
778 // Stack frame creation/removal
779 void enter(bool strip_ret_addr = false);
780 void leave();
781
782 // ROP Protection
783 void protect_return_address();
784 void protect_return_address(Register return_reg);
785 void authenticate_return_address();
786 void authenticate_return_address(Register return_reg);
787 void strip_return_address();
788 void check_return_address(Register return_reg=lr) PRODUCT_RETURN;
789
790 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
791 // The pointer will be loaded into the thread register.
792 void get_thread(Register thread);
793
794 // support for argument shuffling
795 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
796 void float_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
797 void long_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
798 void double_move(VMRegPair src, VMRegPair dst, Register tmp = rscratch1);
799 void object_move(
800 OopMap* map,
801 int oop_handle_offset,
802 int framesize_in_slots,
803 VMRegPair src,
804 VMRegPair dst,
805 bool is_receiver,
806 int* receiver_offset);
807
808
809 // Support for VM calls
810 //
811 // It is imperative that all calls into the VM are handled via the call_VM macros.
812 // They make sure that the stack linkage is setup correctly. call_VM's correspond
813 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
814
815
816 void call_VM(Register oop_result,
817 address entry_point,
818 bool check_exceptions = true);
819 void call_VM(Register oop_result,
820 address entry_point,
821 Register arg_1,
822 bool check_exceptions = true);
823 void call_VM(Register oop_result,
824 address entry_point,
825 Register arg_1, Register arg_2,
826 bool check_exceptions = true);
827 void call_VM(Register oop_result,
828 address entry_point,
829 Register arg_1, Register arg_2, Register arg_3,
830 bool check_exceptions = true);
831
832 // Overloadings with last_Java_sp
833 void call_VM(Register oop_result,
834 Register last_java_sp,
835 address entry_point,
836 int number_of_arguments = 0,
837 bool check_exceptions = true);
838 void call_VM(Register oop_result,
839 Register last_java_sp,
840 address entry_point,
841 Register arg_1, bool
842 check_exceptions = true);
843 void call_VM(Register oop_result,
844 Register last_java_sp,
845 address entry_point,
846 Register arg_1, Register arg_2,
847 bool check_exceptions = true);
848 void call_VM(Register oop_result,
849 Register last_java_sp,
850 address entry_point,
851 Register arg_1, Register arg_2, Register arg_3,
852 bool check_exceptions = true);
853
854 void get_vm_result_oop(Register oop_result, Register thread);
855 void get_vm_result_metadata(Register metadata_result, Register thread);
856
857 // These always tightly bind to MacroAssembler::call_VM_base
858 // bypassing the virtual implementation
859 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
860 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
861 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
862 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
863 void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
864
865 void call_VM_leaf(address entry_point,
866 int number_of_arguments = 0);
867 void call_VM_leaf(address entry_point,
868 Register arg_1);
869 void call_VM_leaf(address entry_point,
870 Register arg_1, Register arg_2);
871 void call_VM_leaf(address entry_point,
872 Register arg_1, Register arg_2, Register arg_3);
873
874 // These always tightly bind to MacroAssembler::call_VM_leaf_base
875 // bypassing the virtual implementation
876 void super_call_VM_leaf(address entry_point);
877 void super_call_VM_leaf(address entry_point, Register arg_1);
878 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
879 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
880 void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
881
882 // last Java Frame (fills frame anchor)
883 void set_last_Java_frame(Register last_java_sp,
884 Register last_java_fp,
885 address last_java_pc,
886 Register scratch);
887
888 void set_last_Java_frame(Register last_java_sp,
889 Register last_java_fp,
890 Label &last_java_pc,
891 Register scratch);
892
893 void set_last_Java_frame(Register last_java_sp,
894 Register last_java_fp,
895 Register last_java_pc,
896 Register scratch);
897
898 void reset_last_Java_frame(Register thread);
899
900 // thread in the default location (rthread)
901 void reset_last_Java_frame(bool clear_fp);
902
903 // Stores
904 void store_check(Register obj); // store check for obj - register is destroyed afterwards
905 void store_check(Register obj, Address dst); // same as above, dst is exact store location (reg. is destroyed)
906
907 void resolve_jobject(Register value, Register tmp1, Register tmp2);
908 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
909
910 // C 'boolean' to Java boolean: x == 0 ? 0 : 1
911 void c2bool(Register x);
912
913 void load_method_holder_cld(Register rresult, Register rmethod);
914 void load_method_holder(Register holder, Register method);
915
916 // oop manipulations
917 void load_narrow_klass_compact(Register dst, Register src);
918 void load_klass(Register dst, Register src);
919 void store_klass(Register dst, Register src);
920 void cmp_klass(Register obj, Register klass, Register tmp);
921 void cmp_klasses_from_objects(Register obj1, Register obj2, Register tmp1, Register tmp2);
922
923 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
924 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
925 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
926
927 void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
928 Register tmp1, Register tmp2);
929
930 void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register val,
931 Register tmp1, Register tmp2, Register tmp3);
932
933 void load_heap_oop(Register dst, Address src, Register tmp1,
934 Register tmp2, DecoratorSet decorators = 0);
935
936 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
937 Register tmp2, DecoratorSet decorators = 0);
938 void store_heap_oop(Address dst, Register val, Register tmp1,
939 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
940
941 // currently unimplemented
942 // Used for storing null. All other oop constants should be
943 // stored using routines that take a jobject.
944 void store_heap_oop_null(Address dst);
945
946 void store_klass_gap(Register dst, Register src);
947
948 // This dummy is to prevent a call to store_heap_oop from
949 // converting a zero (like null) into a Register by giving
950 // the compiler two choices it can't resolve
951
952 void store_heap_oop(Address dst, void* dummy);
953
954 void encode_heap_oop(Register d, Register s);
955 void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
956 void decode_heap_oop(Register d, Register s);
957 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
958 void encode_heap_oop_not_null(Register r);
959 void decode_heap_oop_not_null(Register r);
960 void encode_heap_oop_not_null(Register dst, Register src);
961 void decode_heap_oop_not_null(Register dst, Register src);
962
963 void set_narrow_oop(Register dst, jobject obj);
964
965 void decode_klass_not_null_for_aot(Register dst, Register src);
966 void encode_klass_not_null_for_aot(Register dst, Register src);
967 void encode_klass_not_null(Register r);
968 void decode_klass_not_null(Register r);
969 void encode_klass_not_null(Register dst, Register src);
970 void decode_klass_not_null(Register dst, Register src);
971
972 void set_narrow_klass(Register dst, Klass* k);
973
974 // if heap base register is used - reinit it with the correct value
975 void reinit_heapbase();
976
977 DEBUG_ONLY(void verify_heapbase(const char* msg);)
978
979 void push_CPU_state(bool save_vectors = false, bool use_sve = false,
980 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
981 void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
982 int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
983
984 void push_cont_fastpath(Register java_thread = rthread);
985 void pop_cont_fastpath(Register java_thread = rthread);
986
987 void inc_held_monitor_count(Register tmp);
988 void dec_held_monitor_count(Register tmp);
989
990 // Round up to a power of two
991 void round_to(Register reg, int modulus);
992
993 // java.lang.Math::round intrinsics
994 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
995 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
996
997 // allocation
998 void tlab_allocate(
999 Register obj, // result: pointer to object after successful allocation
1000 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
1001 int con_size_in_bytes, // object size in bytes if known at compile time
1002 Register t1, // temp register
1003 Register t2, // temp register
1004 Label& slow_case // continuation point if fast allocation fails
1005 );
1006 void verify_tlab();
1007
1008 // interface method calling
1009 void lookup_interface_method(Register recv_klass,
1010 Register intf_klass,
1011 RegisterOrConstant itable_index,
1012 Register method_result,
1013 Register scan_temp,
1014 Label& no_such_interface,
1015 bool return_method = true);
1016
1017 void lookup_interface_method_stub(Register recv_klass,
1018 Register holder_klass,
1019 Register resolved_klass,
1020 Register method_result,
1021 Register temp_reg,
1022 Register temp_reg2,
1023 int itable_index,
1024 Label& L_no_such_interface);
1025
1026 // virtual method calling
1027 // n.b. x86 allows RegisterOrConstant for vtable_index
1028 void lookup_virtual_method(Register recv_klass,
1029 RegisterOrConstant vtable_index,
1030 Register method_result);
1031
1032 // Test sub_klass against super_klass, with fast and slow paths.
1033
1034 // The fast path produces a tri-state answer: yes / no / maybe-slow.
1035 // One of the three labels can be null, meaning take the fall-through.
1036 // If super_check_offset is -1, the value is loaded up from super_klass.
1037 // No registers are killed, except temp_reg.
1038 void check_klass_subtype_fast_path(Register sub_klass,
1039 Register super_klass,
1040 Register temp_reg,
1041 Label* L_success,
1042 Label* L_failure,
1043 Label* L_slow_path,
1044 Register super_check_offset = noreg);
1045
1046 // The rest of the type check; must be wired to a corresponding fast path.
1047 // It does not repeat the fast path logic, so don't use it standalone.
1048 // The temp_reg and temp2_reg can be noreg, if no temps are available.
1049 // Updates the sub's secondary super cache as necessary.
1050 // If set_cond_codes, condition codes will be Z on success, NZ on failure.
1051 void check_klass_subtype_slow_path(Register sub_klass,
1052 Register super_klass,
1053 Register temp_reg,
1054 Register temp2_reg,
1055 Label* L_success,
1056 Label* L_failure,
1057 bool set_cond_codes = false);
1058
1059 void check_klass_subtype_slow_path_linear(Register sub_klass,
1060 Register super_klass,
1061 Register temp_reg,
1062 Register temp2_reg,
1063 Label* L_success,
1064 Label* L_failure,
1065 bool set_cond_codes = false);
1066
1067 void check_klass_subtype_slow_path_table(Register sub_klass,
1068 Register super_klass,
1069 Register temp_reg,
1070 Register temp2_reg,
1071 Register temp3_reg,
1072 Register result_reg,
1073 FloatRegister vtemp_reg,
1074 Label* L_success,
1075 Label* L_failure,
1076 bool set_cond_codes = false);
1077
1078 // If r is valid, return r.
1079 // If r is invalid, remove a register r2 from available_regs, add r2
1080 // to regs_to_push, then return r2.
1081 Register allocate_if_noreg(const Register r,
1082 RegSetIterator<Register> &available_regs,
1083 RegSet ®s_to_push);
1084
1085 // Secondary subtype checking
1086 void lookup_secondary_supers_table_var(Register sub_klass,
1087 Register r_super_klass,
1088 Register temp1,
1089 Register temp2,
1090 Register temp3,
1091 FloatRegister vtemp,
1092 Register result,
1093 Label *L_success);
1094
1095
1096 // As above, but with a constant super_klass.
1097 // The result is in Register result, not the condition codes.
1098 bool lookup_secondary_supers_table_const(Register r_sub_klass,
1099 Register r_super_klass,
1100 Register temp1,
1101 Register temp2,
1102 Register temp3,
1103 FloatRegister vtemp,
1104 Register result,
1105 u1 super_klass_slot,
1106 bool stub_is_near = false);
1107
1108 void verify_secondary_supers_table(Register r_sub_klass,
1109 Register r_super_klass,
1110 Register temp1,
1111 Register temp2,
1112 Register result);
1113
1114 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
1115 Register r_array_base,
1116 Register r_array_index,
1117 Register r_bitmap,
1118 Register temp1,
1119 Register result,
1120 bool is_stub = true);
1121
1122 // Simplified, combined version, good for typical uses.
1123 // Falls through on failure.
1124 void check_klass_subtype(Register sub_klass,
1125 Register super_klass,
1126 Register temp_reg,
1127 Label& L_success);
1128
1129 void clinit_barrier(Register klass,
1130 Register thread,
1131 Label* L_fast_path = nullptr,
1132 Label* L_slow_path = nullptr);
1133
1134 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
1135
1136 void verify_sve_vector_length(Register tmp = rscratch1);
1137 void reinitialize_ptrue() {
1138 if (UseSVE > 0) {
1139 sve_ptrue(ptrue, B);
1140 }
1141 }
1142 void verify_ptrue();
1143
1144 // Debugging
1145
1146 // only if +VerifyOops
1147 void _verify_oop(Register reg, const char* s, const char* file, int line);
1148 void _verify_oop_addr(Address addr, const char * s, const char* file, int line);
1149
1150 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
1151 if (VerifyOops) {
1152 _verify_oop(reg, s, file, line);
1153 }
1154 }
1155 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
1156 if (VerifyOops) {
1157 _verify_oop_addr(reg, s, file, line);
1158 }
1159 }
1160
1161 // TODO: verify method and klass metadata (compare against vptr?)
1162 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
1163 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
1164
1165 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
1166 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
1167 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
1168 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
1169 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
1170
1171 // Restore cpu control state after JNI call
1172 void restore_cpu_control_state_after_jni(Register tmp1, Register tmp2);
1173
1174 // prints msg, dumps registers and stops execution
1175 void stop(const char* msg);
1176
1177 static void debug64(char* msg, int64_t pc, int64_t regs[]);
1178
1179 void untested() { stop("untested"); }
1180
1181 void unimplemented(const char* what = "");
1182
1183 void should_not_reach_here() { stop("should not reach here"); }
1184
1185 void _assert_asm(Condition cc, const char* msg);
1186 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
1187 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
1188
1189 // Stack overflow checking
1190 void bang_stack_with_offset(int offset) {
1191 // stack grows down, caller passes positive offset
1192 assert(offset > 0, "must bang with negative offset");
1193 sub(rscratch2, sp, offset);
1194 str(zr, Address(rscratch2));
1195 }
1196
1197 // Writes to stack successive pages until offset reached to check for
1198 // stack overflow + shadow pages. Also, clobbers tmp
1199 void bang_stack_size(Register size, Register tmp);
1200
1201 // Check for reserved stack access in method being exited (for JIT)
1202 void reserved_stack_check();
1203
1204 // Arithmetics
1205
1206 // Clobber: rscratch1, rscratch2
1207 void addptr(const Address &dst, int32_t src);
1208
1209 // Clobber: rscratch1
1210 void cmpptr(Register src1, Address src2);
1211
1212 void cmpoop(Register obj1, Register obj2);
1213
1214 // Various forms of CAS
1215
1216 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1217 Label &succeed, Label *fail);
1218 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1219 Label &succeed, Label *fail);
1220
1221 void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1222 Label &succeed, Label *fail);
1223
1224 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1225 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1226 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1227 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1228
1229 void atomic_xchg(Register prev, Register newv, Register addr);
1230 void atomic_xchgw(Register prev, Register newv, Register addr);
1231 void atomic_xchgl(Register prev, Register newv, Register addr);
1232 void atomic_xchglw(Register prev, Register newv, Register addr);
1233 void atomic_xchgal(Register prev, Register newv, Register addr);
1234 void atomic_xchgalw(Register prev, Register newv, Register addr);
1235
1236 void orptr(Address adr, RegisterOrConstant src) {
1237 ldr(rscratch1, adr);
1238 if (src.is_register())
1239 orr(rscratch1, rscratch1, src.as_register());
1240 else
1241 orr(rscratch1, rscratch1, src.as_constant());
1242 str(rscratch1, adr);
1243 }
1244
1245 // A generic CAS; success or failure is in the EQ flag.
1246 // Clobbers rscratch1
1247 void cmpxchg(Register addr, Register expected, Register new_val,
1248 enum operand_size size,
1249 bool acquire, bool release, bool weak,
1250 Register result);
1251
1252 #ifdef ASSERT
1253 // Template short-hand support to clean-up after a failed call to trampoline
1254 // call generation (see trampoline_call() below), when a set of Labels must
1255 // be reset (before returning).
1256 template<typename Label, typename... More>
1257 void reset_labels(Label &lbl, More&... more) {
1258 lbl.reset(); reset_labels(more...);
1259 }
1260 template<typename Label>
1261 void reset_labels(Label &lbl) {
1262 lbl.reset();
1263 }
1264 #endif
1265
1266 private:
1267 void compare_eq(Register rn, Register rm, enum operand_size size);
1268
1269 public:
1270 // AArch64 OpenJDK uses four different types of calls:
1271 // - direct call: bl pc_relative_offset
1272 // This is the shortest and the fastest, but the offset has the range:
1273 // +/-128MB for the release build, +/-2MB for the debug build.
1274 //
1275 // - far call: adrp reg, pc_relative_offset; add; bl reg
1276 // This is longer than a direct call. The offset has
1277 // the range +/-4GB. As the code cache size is limited to 4GB,
1278 // far calls can reach anywhere in the code cache. If a jump is
1279 // needed rather than a call, a far jump 'b reg' can be used instead.
1280 // All instructions are embedded at a call site.
1281 //
1282 // - trampoline call:
1283 // This is only available in C1/C2-generated code (nmethod). It is a combination
1284 // of a direct call, which is used if the destination of a call is in range,
1285 // and a register-indirect call. It has the advantages of reaching anywhere in
1286 // the AArch64 address space and being patchable at runtime when the generated
1287 // code is being executed by other threads.
1288 //
1289 // [Main code section]
1290 // bl trampoline
1291 // [Stub code section]
1292 // trampoline:
1293 // ldr reg, pc + 8
1294 // br reg
1295 // <64-bit destination address>
1296 //
1297 // If the destination is in range when the generated code is moved to the code
1298 // cache, 'bl trampoline' is replaced with 'bl destination' and the trampoline
1299 // is not used.
1300 // The optimization does not remove the trampoline from the stub section.
1301 // This is necessary because the trampoline may well be redirected later when
1302 // code is patched, and the new destination may not be reachable by a simple BR
1303 // instruction.
1304 //
1305 // - indirect call: move reg, address; blr reg
1306 // This too can reach anywhere in the address space, but it cannot be
1307 // patched while code is running, so it must only be modified at a safepoint.
1308 // This form of call is most suitable for targets at fixed addresses, which
1309 // will never be patched.
1310 //
1311 // The patching we do conforms to the "Concurrent modification and
1312 // execution of instructions" section of the Arm Architectural
1313 // Reference Manual, which only allows B, BL, BRK, HVC, ISB, NOP, SMC,
1314 // or SVC instructions to be modified while another thread is
1315 // executing them.
1316 //
1317 // To patch a trampoline call when the BL can't reach, we first modify
1318 // the 64-bit destination address in the trampoline, then modify the
1319 // BL to point to the trampoline, then flush the instruction cache to
1320 // broadcast the change to all executing threads. See
1321 // NativeCall::set_destination_mt_safe for the details.
1322 //
1323 // There is a benign race in that the other thread might observe the
1324 // modified BL before it observes the modified 64-bit destination
1325 // address. That does not matter because the destination method has been
1326 // invalidated, so there will be a trap at its start.
1327 // For this to work, the destination address in the trampoline is
1328 // always updated, even if we're not using the trampoline.
1329
1330 // Emit a direct call if the entry address will always be in range,
1331 // otherwise a trampoline call.
1332 // Supported entry.rspec():
1333 // - relocInfo::runtime_call_type
1334 // - relocInfo::opt_virtual_call_type
1335 // - relocInfo::static_call_type
1336 // - relocInfo::virtual_call_type
1337 //
1338 // Return: the call PC or null if CodeCache is full.
1339 // Clobbers: rscratch1
1340 address trampoline_call(Address entry);
1341
1342 static bool far_branches() {
1343 return ReservedCodeCacheSize > branch_range;
1344 }
1345
1346 // Check if branches to the non nmethod section require a far jump
1347 static bool codestub_branch_needs_far_jump() {
1348 if (AOTCodeCache::is_on_for_dump()) {
1349 // To calculate far_codestub_branch_size correctly.
1350 return true;
1351 }
1352 return CodeCache::max_distance_to_non_nmethod() > branch_range;
1353 }
1354
1355 // Emit a direct call/jump if the entry address will always be in range,
1356 // otherwise a far call/jump.
1357 // The address must be inside the code cache.
1358 // Supported entry.rspec():
1359 // - relocInfo::external_word_type
1360 // - relocInfo::runtime_call_type
1361 // - relocInfo::none
1362 // In the case of a far call/jump, the entry address is put in the tmp register.
1363 // The tmp register is invalidated.
1364 //
1365 // Far_jump returns the amount of the emitted code.
1366 void far_call(Address entry, Register tmp = rscratch1);
1367 int far_jump(Address entry, Register tmp = rscratch1);
1368
1369 static int far_codestub_branch_size() {
1370 if (codestub_branch_needs_far_jump()) {
1371 return 3 * 4; // adrp, add, br
1372 } else {
1373 return 4;
1374 }
1375 }
1376
1377 // Emit the CompiledIC call idiom
1378 address ic_call(address entry, jint method_index = 0);
1379 static int ic_check_size();
1380 int ic_check(int end_alignment);
1381
1382 public:
1383
1384 // Data
1385
1386 void mov_metadata(Register dst, Metadata* obj);
1387 Address allocate_metadata_address(Metadata* obj);
1388 Address constant_oop_address(jobject obj);
1389
1390 void movoop(Register dst, jobject obj);
1391
1392 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1393 void kernel_crc32(Register crc, Register buf, Register len,
1394 Register table0, Register table1, Register table2, Register table3,
1395 Register tmp, Register tmp2, Register tmp3);
1396 // CRC32 code for java.util.zip.CRC32C::updateBytes() intrinsic.
1397 void kernel_crc32c(Register crc, Register buf, Register len,
1398 Register table0, Register table1, Register table2, Register table3,
1399 Register tmp, Register tmp2, Register tmp3);
1400
1401 // Stack push and pop individual 64 bit registers
1402 void push(Register src);
1403 void pop(Register dst);
1404
1405 void repne_scan(Register addr, Register value, Register count,
1406 Register scratch);
1407 void repne_scanw(Register addr, Register value, Register count,
1408 Register scratch);
1409
1410 typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1411 typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1412
1413 // If a constant does not fit in an immediate field, generate some
1414 // number of MOV instructions and then perform the operation
1415 void wrap_add_sub_imm_insn(Register Rd, Register Rn, uint64_t imm,
1416 add_sub_imm_insn insn1,
1417 add_sub_reg_insn insn2, bool is32);
1418 // Separate vsn which sets the flags
1419 void wrap_adds_subs_imm_insn(Register Rd, Register Rn, uint64_t imm,
1420 add_sub_imm_insn insn1,
1421 add_sub_reg_insn insn2, bool is32);
1422
1423 #define WRAP(INSN, is32) \
1424 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1425 wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1426 } \
1427 \
1428 void INSN(Register Rd, Register Rn, Register Rm, \
1429 enum shift_kind kind, unsigned shift = 0) { \
1430 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1431 } \
1432 \
1433 void INSN(Register Rd, Register Rn, Register Rm) { \
1434 Assembler::INSN(Rd, Rn, Rm); \
1435 } \
1436 \
1437 void INSN(Register Rd, Register Rn, Register Rm, \
1438 ext::operation option, int amount = 0) { \
1439 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1440 }
1441
1442 WRAP(add, false) WRAP(addw, true) WRAP(sub, false) WRAP(subw, true)
1443
1444 #undef WRAP
1445 #define WRAP(INSN, is32) \
1446 void INSN(Register Rd, Register Rn, uint64_t imm) { \
1447 wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN, is32); \
1448 } \
1449 \
1450 void INSN(Register Rd, Register Rn, Register Rm, \
1451 enum shift_kind kind, unsigned shift = 0) { \
1452 Assembler::INSN(Rd, Rn, Rm, kind, shift); \
1453 } \
1454 \
1455 void INSN(Register Rd, Register Rn, Register Rm) { \
1456 Assembler::INSN(Rd, Rn, Rm); \
1457 } \
1458 \
1459 void INSN(Register Rd, Register Rn, Register Rm, \
1460 ext::operation option, int amount = 0) { \
1461 Assembler::INSN(Rd, Rn, Rm, option, amount); \
1462 }
1463
1464 WRAP(adds, false) WRAP(addsw, true) WRAP(subs, false) WRAP(subsw, true)
1465
1466 void add(Register Rd, Register Rn, RegisterOrConstant increment);
1467 void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1468 void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1469 void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1470
1471 void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1472
1473 void tableswitch(Register index, jint lowbound, jint highbound,
1474 Label &jumptable, Label &jumptable_end, int stride = 1) {
1475 adr(rscratch1, jumptable);
1476 subsw(rscratch2, index, lowbound);
1477 subsw(zr, rscratch2, highbound - lowbound);
1478 br(Assembler::HS, jumptable_end);
1479 add(rscratch1, rscratch1, rscratch2,
1480 ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1481 br(rscratch1);
1482 }
1483
1484 // Form an address from base + offset in Rd. Rd may or may not
1485 // actually be used: you must use the Address that is returned. It
1486 // is up to you to ensure that the shift provided matches the size
1487 // of your data.
1488 Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1489
1490 // Return true iff an address is within the 48-bit AArch64 address
1491 // space.
1492 bool is_valid_AArch64_address(address a) {
1493 return ((uint64_t)a >> 48) == 0;
1494 }
1495
1496 // Load the base of the cardtable byte map into reg.
1497 void load_byte_map_base(Register reg);
1498
1499 // Prolog generator routines to support switch between x86 code and
1500 // generated ARM code
1501
1502 // routine to generate an x86 prolog for a stub function which
1503 // bootstraps into the generated ARM code which directly follows the
1504 // stub
1505 //
1506
1507 public:
1508
1509 address read_polling_page(Register r, relocInfo::relocType rtype);
1510 void get_polling_page(Register dest, relocInfo::relocType rtype);
1511
1512 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1513 void update_byte_crc32(Register crc, Register val, Register table);
1514 void update_word_crc32(Register crc, Register v, Register tmp,
1515 Register table0, Register table1, Register table2, Register table3,
1516 bool upper = false);
1517
1518 address count_positives(Register ary1, Register len, Register result);
1519
1520 address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1521 Register tmp1, Register tmp2, Register tmp3, int elem_size);
1522
1523 // Ensure that the inline code and the stub use the same registers.
1524 #define ARRAYS_HASHCODE_REGISTERS \
1525 do { \
1526 assert(result == r0 && \
1527 ary == r1 && \
1528 cnt == r2 && \
1529 vdata0 == v3 && \
1530 vdata1 == v2 && \
1531 vdata2 == v1 && \
1532 vdata3 == v0 && \
1533 vmul0 == v4 && \
1534 vmul1 == v5 && \
1535 vmul2 == v6 && \
1536 vmul3 == v7 && \
1537 vpow == v12 && \
1538 vpowm == v13, "registers must match aarch64.ad"); \
1539 } while (0)
1540
1541 void string_equals(Register a1, Register a2, Register result, Register cnt1);
1542
1543 void fill_words(Register base, Register cnt, Register value);
1544 address zero_words(Register base, uint64_t cnt);
1545 address zero_words(Register ptr, Register cnt);
1546 void zero_dcache_blocks(Register base, Register cnt);
1547
1548 static const int zero_words_block_size;
1549
1550 address byte_array_inflate(Register src, Register dst, Register len,
1551 FloatRegister vtmp1, FloatRegister vtmp2,
1552 FloatRegister vtmp3, Register tmp4);
1553
1554 void char_array_compress(Register src, Register dst, Register len,
1555 Register res,
1556 FloatRegister vtmp0, FloatRegister vtmp1,
1557 FloatRegister vtmp2, FloatRegister vtmp3,
1558 FloatRegister vtmp4, FloatRegister vtmp5);
1559
1560 void encode_iso_array(Register src, Register dst,
1561 Register len, Register res, bool ascii,
1562 FloatRegister vtmp0, FloatRegister vtmp1,
1563 FloatRegister vtmp2, FloatRegister vtmp3,
1564 FloatRegister vtmp4, FloatRegister vtmp5);
1565
1566 void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1567 address pio2, address dsin_coef, address dcos_coef);
1568 private:
1569 // begin trigonometric functions support block
1570 void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1571 void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1572 void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1573 void generate_kernel_cos(FloatRegister x, address dcos_coef);
1574 // end trigonometric functions support block
1575 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1576 Register src1, Register src2);
1577 void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1578 add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1579 }
1580 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1581 Register y, Register y_idx, Register z,
1582 Register carry, Register product,
1583 Register idx, Register kdx);
1584 void multiply_128_x_128_loop(Register y, Register z,
1585 Register carry, Register carry2,
1586 Register idx, Register jdx,
1587 Register yz_idx1, Register yz_idx2,
1588 Register tmp, Register tmp3, Register tmp4,
1589 Register tmp7, Register product_hi);
1590 void kernel_crc32_using_crypto_pmull(Register crc, Register buf,
1591 Register len, Register tmp0, Register tmp1, Register tmp2,
1592 Register tmp3);
1593 void kernel_crc32_using_crc32(Register crc, Register buf,
1594 Register len, Register tmp0, Register tmp1, Register tmp2,
1595 Register tmp3);
1596 void kernel_crc32c_using_crypto_pmull(Register crc, Register buf,
1597 Register len, Register tmp0, Register tmp1, Register tmp2,
1598 Register tmp3);
1599 void kernel_crc32c_using_crc32c(Register crc, Register buf,
1600 Register len, Register tmp0, Register tmp1, Register tmp2,
1601 Register tmp3);
1602 void kernel_crc32_common_fold_using_crypto_pmull(Register crc, Register buf,
1603 Register len, Register tmp0, Register tmp1, Register tmp2,
1604 size_t table_offset);
1605
1606 void ghash_modmul (FloatRegister result,
1607 FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1608 FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1609 FloatRegister t1, FloatRegister t2, FloatRegister t3);
1610 void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1611 public:
1612 void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1613 Register tmp0, Register tmp1, Register tmp2, Register tmp3,
1614 Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1615 void mul_add(Register out, Register in, Register offs, Register len, Register k);
1616 void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1617 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1618 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1619 void ghash_multiply_wide(int index,
1620 FloatRegister result_lo, FloatRegister result_hi,
1621 FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1622 FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1623 void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1624 FloatRegister p, FloatRegister z, FloatRegister t1);
1625 void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1626 FloatRegister p, FloatRegister z, FloatRegister t1);
1627 void ghash_processBlocks_wide(Label& p, Register state, Register subkeyH,
1628 Register data, Register blocks, int unrolls);
1629
1630
1631 void aesenc_loadkeys(Register key, Register keylen);
1632 void aesecb_encrypt(Register from, Register to, Register keylen,
1633 FloatRegister data = v0, int unrolls = 1);
1634 void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1635 void aes_round(FloatRegister input, FloatRegister subkey);
1636
1637 // ChaCha20 functions support block
1638 void cc20_qr_add4(FloatRegister (&addFirst)[4],
1639 FloatRegister (&addSecond)[4]);
1640 void cc20_qr_xor4(FloatRegister (&firstElem)[4],
1641 FloatRegister (&secondElem)[4], FloatRegister (&result)[4]);
1642 void cc20_qr_lrot4(FloatRegister (&sourceReg)[4],
1643 FloatRegister (&destReg)[4], int bits, FloatRegister table);
1644 void cc20_set_qr_registers(FloatRegister (&vectorSet)[4],
1645 const FloatRegister (&stateVectors)[16], int idx1, int idx2,
1646 int idx3, int idx4);
1647
1648 // Place an ISB after code may have been modified due to a safepoint.
1649 void safepoint_isb();
1650
1651 private:
1652 // Return the effective address r + (r1 << ext) + offset.
1653 // Uses rscratch2.
1654 Address offsetted_address(Register r, Register r1, Address::extend ext,
1655 int offset, int size);
1656
1657 private:
1658 // Returns an address on the stack which is reachable with a ldr/str of size
1659 // Uses rscratch2 if the address is not directly reachable
1660 Address spill_address(int size, int offset, Register tmp=rscratch2);
1661 Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1662
1663 bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1664
1665 // Check whether two loads/stores can be merged into ldp/stp.
1666 bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1667
1668 // Merge current load/store with previous load/store into ldp/stp.
1669 void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1670
1671 // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1672 bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1673
1674 public:
1675 void spill(Register Rx, bool is64, int offset) {
1676 if (is64) {
1677 str(Rx, spill_address(8, offset));
1678 } else {
1679 strw(Rx, spill_address(4, offset));
1680 }
1681 }
1682 void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1683 str(Vx, T, spill_address(1 << (int)T, offset));
1684 }
1685
1686 void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1687 sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1688 }
1689 void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1690 sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1691 }
1692
1693 void unspill(Register Rx, bool is64, int offset) {
1694 if (is64) {
1695 ldr(Rx, spill_address(8, offset));
1696 } else {
1697 ldrw(Rx, spill_address(4, offset));
1698 }
1699 }
1700 void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1701 ldr(Vx, T, spill_address(1 << (int)T, offset));
1702 }
1703
1704 void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1705 sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1706 }
1707 void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1708 sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1709 }
1710
1711 void spill_copy128(int src_offset, int dst_offset,
1712 Register tmp1=rscratch1, Register tmp2=rscratch2) {
1713 if (src_offset < 512 && (src_offset & 7) == 0 &&
1714 dst_offset < 512 && (dst_offset & 7) == 0) {
1715 ldp(tmp1, tmp2, Address(sp, src_offset));
1716 stp(tmp1, tmp2, Address(sp, dst_offset));
1717 } else {
1718 unspill(tmp1, true, src_offset);
1719 spill(tmp1, true, dst_offset);
1720 unspill(tmp1, true, src_offset+8);
1721 spill(tmp1, true, dst_offset+8);
1722 }
1723 }
1724 void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1725 int sve_vec_reg_size_in_bytes) {
1726 assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1727 for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1728 spill_copy128(src_offset, dst_offset);
1729 src_offset += 16;
1730 dst_offset += 16;
1731 }
1732 }
1733 void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1734 int sve_predicate_reg_size_in_bytes) {
1735 sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1736 sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1737 reinitialize_ptrue();
1738 }
1739 void cache_wb(Address line);
1740 void cache_wbsync(bool is_pre);
1741
1742 // Code for java.lang.Thread::onSpinWait() intrinsic.
1743 void spin_wait();
1744
1745 void lightweight_lock(Register basic_lock, Register obj, Register t1, Register t2, Register t3, Label& slow);
1746 void lightweight_unlock(Register obj, Register t1, Register t2, Register t3, Label& slow);
1747
1748 private:
1749 // Check the current thread doesn't need a cross modify fence.
1750 void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1751
1752 };
1753
1754 #ifdef ASSERT
1755 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1756 #endif
1757
1758 struct tableswitch {
1759 Register _reg;
1760 int _insn_index; jint _first_key; jint _last_key;
1761 Label _after;
1762 Label _branches;
1763 };
1764
1765 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP