1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "runtime/vm_version.hpp"
  32 #include "utilities/powerOfTwo.hpp"
  33 
  34 // MacroAssembler extends Assembler by frequently used macros.
  35 //
  36 // Instructions for which a 'better' code sequence exists depending
  37 // on arguments should also go in here.
  38 
  39 class MacroAssembler: public Assembler {
  40   friend class LIR_Assembler;
  41 
  42  public:
  43   using Assembler::mov;
  44   using Assembler::movi;
  45 
  46  protected:
  47 
  48   // Support for VM calls
  49   //
  50   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  51   // may customize this version by overriding it for its purposes (e.g., to save/restore
  52   // additional registers when doing a VM call).
  53   virtual void call_VM_leaf_base(
  54     address entry_point,               // the entry point
  55     int     number_of_arguments,        // the number of arguments to pop after the call
  56     Label *retaddr = NULL
  57   );
  58 
  59   virtual void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments,        // the number of arguments to pop after the call
  62     Label &retaddr) {
  63     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  64   }
  65 
  66   // This is the base routine called by the different versions of call_VM. The interpreter
  67   // may customize this version by overriding it for its purposes (e.g., to save/restore
  68   // additional registers when doing a VM call).
  69   //
  70   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  71   // returns the register which contains the thread upon return. If a thread register has been
  72   // specified, the return value will correspond to that register. If no last_java_sp is specified
  73   // (noreg) than rsp will be used instead.
  74   virtual void call_VM_base(           // returns the register containing the thread upon return
  75     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  76     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  77     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  78     address  entry_point,              // the entry point
  79     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  80     bool     check_exceptions          // whether to check for pending exceptions after return
  81   );
  82 
  83   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  84 
  85   enum KlassDecodeMode {
  86     KlassDecodeNone,
  87     KlassDecodeZero,
  88     KlassDecodeXor,
  89     KlassDecodeMovk
  90   };
  91 
  92   KlassDecodeMode klass_decode_mode();
  93 
  94  private:
  95   static KlassDecodeMode _klass_decode_mode;
  96 
  97  public:
  98   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  99 
 100  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 101  // The implementation is only non-empty for the InterpreterMacroAssembler,
 102  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 103  virtual void check_and_handle_popframe(Register java_thread);
 104  virtual void check_and_handle_earlyret(Register java_thread);
 105 
 106   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
 107 
 108   // Helper functions for statistics gathering.
 109   // Unconditional atomic increment.
 110   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 111   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 112     lea(tmp1, counter_addr);
 113     atomic_incw(tmp1, tmp2, tmp3);
 114   }
 115   // Load Effective Address
 116   void lea(Register r, const Address &a) {
 117     InstructionMark im(this);
 118     code_section()->relocate(inst_mark(), a.rspec());
 119     a.lea(this, r);
 120   }
 121 
 122   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 123      accesses, and these can exceed the offset range. */
 124   Address legitimize_address(const Address &a, int size, Register scratch) {
 125     if (a.getMode() == Address::base_plus_offset) {
 126       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 127         block_comment("legitimize_address {");
 128         lea(scratch, a);
 129         block_comment("} legitimize_address");
 130         return Address(scratch);
 131       }
 132     }
 133     return a;
 134   }
 135 
 136   void addmw(Address a, Register incr, Register scratch) {
 137     ldrw(scratch, a);
 138     addw(scratch, scratch, incr);
 139     strw(scratch, a);
 140   }
 141 
 142   // Add constant to memory word
 143   void addmw(Address a, int imm, Register scratch) {
 144     ldrw(scratch, a);
 145     if (imm > 0)
 146       addw(scratch, scratch, (unsigned)imm);
 147     else
 148       subw(scratch, scratch, (unsigned)-imm);
 149     strw(scratch, a);
 150   }
 151 
 152   void bind(Label& L) {
 153     Assembler::bind(L);
 154     code()->clear_last_insn();
 155   }
 156 
 157   void membar(Membar_mask_bits order_constraint);
 158 
 159   using Assembler::ldr;
 160   using Assembler::str;
 161   using Assembler::ldrw;
 162   using Assembler::strw;
 163 
 164   void ldr(Register Rx, const Address &adr);
 165   void ldrw(Register Rw, const Address &adr);
 166   void str(Register Rx, const Address &adr);
 167   void strw(Register Rx, const Address &adr);
 168 
 169   // Frame creation and destruction shared between JITs.
 170   void build_frame(int framesize);
 171   void remove_frame(int framesize);
 172 
 173   virtual void _call_Unimplemented(address call_site) {
 174     mov(rscratch2, call_site);
 175   }
 176 
 177 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 178 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 179 // https://reviews.llvm.org/D3311
 180 
 181 #ifdef _WIN64
 182 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 183 #else
 184 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 185 #endif
 186 
 187   // aliases defined in AARCH64 spec
 188 
 189   template<class T>
 190   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 191 
 192   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 193   inline void cmp(Register Rd, unsigned imm) = delete;
 194 
 195   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 196   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 197 
 198   void cset(Register Rd, Assembler::Condition cond) {
 199     csinc(Rd, zr, zr, ~cond);
 200   }
 201   void csetw(Register Rd, Assembler::Condition cond) {
 202     csincw(Rd, zr, zr, ~cond);
 203   }
 204 
 205   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 206     csneg(Rd, Rn, Rn, ~cond);
 207   }
 208   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 209     csnegw(Rd, Rn, Rn, ~cond);
 210   }
 211 
 212   inline void movw(Register Rd, Register Rn) {
 213     if (Rd == sp || Rn == sp) {
 214       addw(Rd, Rn, 0U);
 215     } else {
 216       orrw(Rd, zr, Rn);
 217     }
 218   }
 219   inline void mov(Register Rd, Register Rn) {
 220     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 221     if (Rd == Rn) {
 222     } else if (Rd == sp || Rn == sp) {
 223       add(Rd, Rn, 0U);
 224     } else {
 225       orr(Rd, zr, Rn);
 226     }
 227   }
 228 
 229   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 230   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 231 
 232   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 233   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 234 
 235   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 236   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 237 
 238   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 240   }
 241   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 242     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 243   }
 244 
 245   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 247   }
 248   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     bfm(Rd, Rn, lsb , (lsb + width - 1));
 250   }
 251 
 252   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 254   }
 255   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 257   }
 258 
 259   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 261   }
 262   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 263     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 264   }
 265 
 266   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 267     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 268   }
 269   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 270     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 271   }
 272 
 273   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 274     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 275   }
 276   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 277     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 278   }
 279 
 280   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 281     sbfmw(Rd, Rn, imm, 31);
 282   }
 283 
 284   inline void asr(Register Rd, Register Rn, unsigned imm) {
 285     sbfm(Rd, Rn, imm, 63);
 286   }
 287 
 288   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 289     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 290   }
 291 
 292   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 293     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 294   }
 295 
 296   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 297     ubfmw(Rd, Rn, imm, 31);
 298   }
 299 
 300   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 301     ubfm(Rd, Rn, imm, 63);
 302   }
 303 
 304   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 305     extrw(Rd, Rn, Rn, imm);
 306   }
 307 
 308   inline void ror(Register Rd, Register Rn, unsigned imm) {
 309     extr(Rd, Rn, Rn, imm);
 310   }
 311 
 312   inline void sxtbw(Register Rd, Register Rn) {
 313     sbfmw(Rd, Rn, 0, 7);
 314   }
 315   inline void sxthw(Register Rd, Register Rn) {
 316     sbfmw(Rd, Rn, 0, 15);
 317   }
 318   inline void sxtb(Register Rd, Register Rn) {
 319     sbfm(Rd, Rn, 0, 7);
 320   }
 321   inline void sxth(Register Rd, Register Rn) {
 322     sbfm(Rd, Rn, 0, 15);
 323   }
 324   inline void sxtw(Register Rd, Register Rn) {
 325     sbfm(Rd, Rn, 0, 31);
 326   }
 327 
 328   inline void uxtbw(Register Rd, Register Rn) {
 329     ubfmw(Rd, Rn, 0, 7);
 330   }
 331   inline void uxthw(Register Rd, Register Rn) {
 332     ubfmw(Rd, Rn, 0, 15);
 333   }
 334   inline void uxtb(Register Rd, Register Rn) {
 335     ubfm(Rd, Rn, 0, 7);
 336   }
 337   inline void uxth(Register Rd, Register Rn) {
 338     ubfm(Rd, Rn, 0, 15);
 339   }
 340   inline void uxtw(Register Rd, Register Rn) {
 341     ubfm(Rd, Rn, 0, 31);
 342   }
 343 
 344   inline void cmnw(Register Rn, Register Rm) {
 345     addsw(zr, Rn, Rm);
 346   }
 347   inline void cmn(Register Rn, Register Rm) {
 348     adds(zr, Rn, Rm);
 349   }
 350 
 351   inline void cmpw(Register Rn, Register Rm) {
 352     subsw(zr, Rn, Rm);
 353   }
 354   inline void cmp(Register Rn, Register Rm) {
 355     subs(zr, Rn, Rm);
 356   }
 357 
 358   inline void negw(Register Rd, Register Rn) {
 359     subw(Rd, zr, Rn);
 360   }
 361 
 362   inline void neg(Register Rd, Register Rn) {
 363     sub(Rd, zr, Rn);
 364   }
 365 
 366   inline void negsw(Register Rd, Register Rn) {
 367     subsw(Rd, zr, Rn);
 368   }
 369 
 370   inline void negs(Register Rd, Register Rn) {
 371     subs(Rd, zr, Rn);
 372   }
 373 
 374   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 375     addsw(zr, Rn, Rm, kind, shift);
 376   }
 377   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 378     adds(zr, Rn, Rm, kind, shift);
 379   }
 380 
 381   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 382     subsw(zr, Rn, Rm, kind, shift);
 383   }
 384   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 385     subs(zr, Rn, Rm, kind, shift);
 386   }
 387 
 388   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 389     subw(Rd, zr, Rn, kind, shift);
 390   }
 391 
 392   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 393     sub(Rd, zr, Rn, kind, shift);
 394   }
 395 
 396   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 397     subsw(Rd, zr, Rn, kind, shift);
 398   }
 399 
 400   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 401     subs(Rd, zr, Rn, kind, shift);
 402   }
 403 
 404   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 405     msubw(Rd, Rn, Rm, zr);
 406   }
 407   inline void mneg(Register Rd, Register Rn, Register Rm) {
 408     msub(Rd, Rn, Rm, zr);
 409   }
 410 
 411   inline void mulw(Register Rd, Register Rn, Register Rm) {
 412     maddw(Rd, Rn, Rm, zr);
 413   }
 414   inline void mul(Register Rd, Register Rn, Register Rm) {
 415     madd(Rd, Rn, Rm, zr);
 416   }
 417 
 418   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 419     smsubl(Rd, Rn, Rm, zr);
 420   }
 421   inline void smull(Register Rd, Register Rn, Register Rm) {
 422     smaddl(Rd, Rn, Rm, zr);
 423   }
 424 
 425   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 426     umsubl(Rd, Rn, Rm, zr);
 427   }
 428   inline void umull(Register Rd, Register Rn, Register Rm) {
 429     umaddl(Rd, Rn, Rm, zr);
 430   }
 431 
 432 #define WRAP(INSN)                                                            \
 433   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 434     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 435       nop();                                                                  \
 436     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 437   }
 438 
 439   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 440   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 441 #undef WRAP
 442 
 443 
 444   // macro assembly operations needed for aarch64
 445 
 446   // first two private routines for loading 32 bit or 64 bit constants
 447 private:
 448 
 449   void mov_immediate64(Register dst, uint64_t imm64);
 450   void mov_immediate32(Register dst, uint32_t imm32);
 451 
 452   int push(unsigned int bitset, Register stack);
 453   int pop(unsigned int bitset, Register stack);
 454 
 455   int push_fp(unsigned int bitset, Register stack);
 456   int pop_fp(unsigned int bitset, Register stack);
 457 
 458   void mov(Register dst, Address a);
 459 
 460 public:
 461   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 462   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 463 
 464   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 465   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 466 
 467   static RegSet call_clobbered_registers();
 468 
 469   // Push and pop everything that might be clobbered by a native
 470   // runtime call except rscratch1 and rscratch2.  (They are always
 471   // scratch, so we don't have to protect them.)  Only save the lower
 472   // 64 bits of each vector register. Additonal registers can be excluded
 473   // in a passed RegSet.
 474   void push_call_clobbered_registers_except(RegSet exclude);
 475   void pop_call_clobbered_registers_except(RegSet exclude);
 476 
 477   void push_call_clobbered_registers() {
 478     push_call_clobbered_registers_except(RegSet());
 479   }
 480   void pop_call_clobbered_registers() {
 481     pop_call_clobbered_registers_except(RegSet());
 482   }
 483 
 484 
 485   // now mov instructions for loading absolute addresses and 32 or
 486   // 64 bit integers
 487 
 488   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 489 
 490   inline void mov(Register dst, int imm64)                { mov_immediate64(dst, (uint64_t)imm64); }
 491   inline void mov(Register dst, long imm64)               { mov_immediate64(dst, (uint64_t)imm64); }
 492   inline void mov(Register dst, long long imm64)          { mov_immediate64(dst, (uint64_t)imm64); }
 493   inline void mov(Register dst, unsigned int imm64)       { mov_immediate64(dst, (uint64_t)imm64); }
 494   inline void mov(Register dst, unsigned long imm64)      { mov_immediate64(dst, (uint64_t)imm64); }
 495   inline void mov(Register dst, unsigned long long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
 496 
 497   inline void movw(Register dst, uint32_t imm32)
 498   {
 499     mov_immediate32(dst, imm32);
 500   }
 501 
 502   void mov(Register dst, RegisterOrConstant src) {
 503     if (src.is_register())
 504       mov(dst, src.as_register());
 505     else
 506       mov(dst, src.as_constant());
 507   }
 508 
 509   void movptr(Register r, uintptr_t imm64);
 510 
 511   void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
 512 
 513   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 514     orr(Vd, T, Vn, Vn);
 515   }
 516 
 517 
 518 public:
 519 
 520   // Generalized Test Bit And Branch, including a "far" variety which
 521   // spans more than 32KiB.
 522   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 523     assert(cond == EQ || cond == NE, "must be");
 524 
 525     if (isfar)
 526       cond = ~cond;
 527 
 528     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 529     if (cond == Assembler::EQ)
 530       branch = &Assembler::tbz;
 531     else
 532       branch = &Assembler::tbnz;
 533 
 534     if (isfar) {
 535       Label L;
 536       (this->*branch)(Rt, bitpos, L);
 537       b(dest);
 538       bind(L);
 539     } else {
 540       (this->*branch)(Rt, bitpos, dest);
 541     }
 542   }
 543 
 544   // macro instructions for accessing and updating floating point
 545   // status register
 546   //
 547   // FPSR : op1 == 011
 548   //        CRn == 0100
 549   //        CRm == 0100
 550   //        op2 == 001
 551 
 552   inline void get_fpsr(Register reg)
 553   {
 554     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 555   }
 556 
 557   inline void set_fpsr(Register reg)
 558   {
 559     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 560   }
 561 
 562   inline void clear_fpsr()
 563   {
 564     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 565   }
 566 
 567   // DCZID_EL0: op1 == 011
 568   //            CRn == 0000
 569   //            CRm == 0000
 570   //            op2 == 111
 571   inline void get_dczid_el0(Register reg)
 572   {
 573     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 574   }
 575 
 576   // CTR_EL0:   op1 == 011
 577   //            CRn == 0000
 578   //            CRm == 0000
 579   //            op2 == 001
 580   inline void get_ctr_el0(Register reg)
 581   {
 582     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 583   }
 584 
 585   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 586   int corrected_idivl(Register result, Register ra, Register rb,
 587                       bool want_remainder, Register tmp = rscratch1);
 588   int corrected_idivq(Register result, Register ra, Register rb,
 589                       bool want_remainder, Register tmp = rscratch1);
 590 
 591   // Support for NULL-checks
 592   //
 593   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 594   // If the accessed location is M[reg + offset] and the offset is known, provide the
 595   // offset. No explicit code generation is needed if the offset is within a certain
 596   // range (0 <= offset <= page_size).
 597 
 598   virtual void null_check(Register reg, int offset = -1);
 599   static bool needs_explicit_null_check(intptr_t offset);
 600   static bool uses_implicit_null_check(void* address);
 601 
 602   static address target_addr_for_insn(address insn_addr, unsigned insn);
 603   static address target_addr_for_insn(address insn_addr) {
 604     unsigned insn = *(unsigned*)insn_addr;
 605     return target_addr_for_insn(insn_addr, insn);
 606   }
 607 
 608   // Required platform-specific helpers for Label::patch_instructions.
 609   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 610   static int pd_patch_instruction_size(address branch, address target);
 611   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 612     pd_patch_instruction_size(branch, target);
 613   }
 614   static address pd_call_destination(address branch) {
 615     return target_addr_for_insn(branch);
 616   }
 617 #ifndef PRODUCT
 618   static void pd_print_patched_instruction(address branch);
 619 #endif
 620 
 621   static int patch_oop(address insn_addr, address o);
 622   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 623 
 624   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 625   void emit_static_call_stub();
 626 
 627   // The following 4 methods return the offset of the appropriate move instruction
 628 
 629   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 630   int load_unsigned_byte(Register dst, Address src);
 631   int load_unsigned_short(Register dst, Address src);
 632 
 633   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 634   int load_signed_byte(Register dst, Address src);
 635   int load_signed_short(Register dst, Address src);
 636 
 637   int load_signed_byte32(Register dst, Address src);
 638   int load_signed_short32(Register dst, Address src);
 639 
 640   // Support for sign-extension (hi:lo = extend_sign(lo))
 641   void extend_sign(Register hi, Register lo);
 642 
 643   // Load and store values by size and signed-ness
 644   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 645   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 646 
 647   // Support for inc/dec with optimal instruction selection depending on value
 648 
 649   // x86_64 aliases an unqualified register/address increment and
 650   // decrement to call incrementq and decrementq but also supports
 651   // explicitly sized calls to incrementq/decrementq or
 652   // incrementl/decrementl
 653 
 654   // for aarch64 the proper convention would be to use
 655   // increment/decrement for 64 bit operatons and
 656   // incrementw/decrementw for 32 bit operations. so when porting
 657   // x86_64 code we can leave calls to increment/decrement as is,
 658   // replace incrementq/decrementq with increment/decrement and
 659   // replace incrementl/decrementl with incrementw/decrementw.
 660 
 661   // n.b. increment/decrement calls with an Address destination will
 662   // need to use a scratch register to load the value to be
 663   // incremented. increment/decrement calls which add or subtract a
 664   // constant value greater than 2^12 will need to use a 2nd scratch
 665   // register to hold the constant. so, a register increment/decrement
 666   // may trash rscratch2 and an address increment/decrement trash
 667   // rscratch and rscratch2
 668 
 669   void decrementw(Address dst, int value = 1);
 670   void decrementw(Register reg, int value = 1);
 671 
 672   void decrement(Register reg, int value = 1);
 673   void decrement(Address dst, int value = 1);
 674 
 675   void incrementw(Address dst, int value = 1);
 676   void incrementw(Register reg, int value = 1);
 677 
 678   void increment(Register reg, int value = 1);
 679   void increment(Address dst, int value = 1);
 680 
 681 
 682   // Alignment
 683   void align(int modulus);
 684 
 685   // nop
 686   void post_call_nop() { nop(); }
 687 
 688   // Stack frame creation/removal
 689   void enter()
 690   {
 691     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 692     mov(rfp, sp);
 693   }
 694   void leave()
 695   {
 696     mov(sp, rfp);
 697     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 698   }
 699 
 700   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 701   // The pointer will be loaded into the thread register.
 702   void get_thread(Register thread);
 703 
 704 
 705   // Support for VM calls
 706   //
 707   // It is imperative that all calls into the VM are handled via the call_VM macros.
 708   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 709   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 710 
 711 
 712   void call_VM(Register oop_result,
 713                address entry_point,
 714                bool check_exceptions = true);
 715   void call_VM(Register oop_result,
 716                address entry_point,
 717                Register arg_1,
 718                bool check_exceptions = true);
 719   void call_VM(Register oop_result,
 720                address entry_point,
 721                Register arg_1, Register arg_2,
 722                bool check_exceptions = true);
 723   void call_VM(Register oop_result,
 724                address entry_point,
 725                Register arg_1, Register arg_2, Register arg_3,
 726                bool check_exceptions = true);
 727 
 728   // Overloadings with last_Java_sp
 729   void call_VM(Register oop_result,
 730                Register last_java_sp,
 731                address entry_point,
 732                int number_of_arguments = 0,
 733                bool check_exceptions = true);
 734   void call_VM(Register oop_result,
 735                Register last_java_sp,
 736                address entry_point,
 737                Register arg_1, bool
 738                check_exceptions = true);
 739   void call_VM(Register oop_result,
 740                Register last_java_sp,
 741                address entry_point,
 742                Register arg_1, Register arg_2,
 743                bool check_exceptions = true);
 744   void call_VM(Register oop_result,
 745                Register last_java_sp,
 746                address entry_point,
 747                Register arg_1, Register arg_2, Register arg_3,
 748                bool check_exceptions = true);
 749 
 750   void get_vm_result  (Register oop_result, Register thread);
 751   void get_vm_result_2(Register metadata_result, Register thread);
 752 
 753   // These always tightly bind to MacroAssembler::call_VM_base
 754   // bypassing the virtual implementation
 755   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 756   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 757   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 758   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 759   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 760 
 761   void call_VM_leaf(address entry_point,
 762                     int number_of_arguments = 0);
 763   void call_VM_leaf(address entry_point,
 764                     Register arg_1);
 765   void call_VM_leaf(address entry_point,
 766                     Register arg_1, Register arg_2);
 767   void call_VM_leaf(address entry_point,
 768                     Register arg_1, Register arg_2, Register arg_3);
 769 
 770   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 771   // bypassing the virtual implementation
 772   void super_call_VM_leaf(address entry_point);
 773   void super_call_VM_leaf(address entry_point, Register arg_1);
 774   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 775   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 776   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 777 
 778   // last Java Frame (fills frame anchor)
 779   void set_last_Java_frame(Register last_java_sp,
 780                            Register last_java_fp,
 781                            address last_java_pc,
 782                            Register scratch);
 783 
 784   void set_last_Java_frame(Register last_java_sp,
 785                            Register last_java_fp,
 786                            Label &last_java_pc,
 787                            Register scratch);
 788 
 789   void set_last_Java_frame(Register last_java_sp,
 790                            Register last_java_fp,
 791                            Register last_java_pc,
 792                            Register scratch);
 793 
 794   void reset_last_Java_frame(Register thread);
 795 
 796   // thread in the default location (rthread)
 797   void reset_last_Java_frame(bool clear_fp);
 798 
 799   // Stores
 800   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 801   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 802 
 803   void resolve_jobject(Register value, Register thread, Register tmp);
 804 
 805   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 806   void c2bool(Register x);
 807 
 808   void load_method_holder_cld(Register rresult, Register rmethod);
 809   void load_method_holder(Register holder, Register method);
 810 
 811   // oop manipulations
 812   void load_klass(Register dst, Register src);
 813   void store_klass(Register dst, Register src);
 814   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 815 
 816   void resolve_weak_handle(Register result, Register tmp);
 817   void resolve_oop_handle(Register result, Register tmp = r5);
 818   void load_mirror(Register dst, Register method, Register tmp = r5);
 819 
 820   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 821                       Register tmp1, Register tmp_thread);
 822 
 823   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 824                        Register tmp1, Register tmp_thread);
 825 
 826   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 827                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 828 
 829   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 830                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 831   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 832                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 833 
 834   // currently unimplemented
 835   // Used for storing NULL. All other oop constants should be
 836   // stored using routines that take a jobject.
 837   void store_heap_oop_null(Address dst);
 838 
 839   void store_klass_gap(Register dst, Register src);
 840 
 841   // This dummy is to prevent a call to store_heap_oop from
 842   // converting a zero (like NULL) into a Register by giving
 843   // the compiler two choices it can't resolve
 844 
 845   void store_heap_oop(Address dst, void* dummy);
 846 
 847   void encode_heap_oop(Register d, Register s);
 848   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 849   void decode_heap_oop(Register d, Register s);
 850   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 851   void encode_heap_oop_not_null(Register r);
 852   void decode_heap_oop_not_null(Register r);
 853   void encode_heap_oop_not_null(Register dst, Register src);
 854   void decode_heap_oop_not_null(Register dst, Register src);
 855 
 856   void set_narrow_oop(Register dst, jobject obj);
 857 
 858   void encode_klass_not_null(Register r);
 859   void decode_klass_not_null(Register r);
 860   void encode_klass_not_null(Register dst, Register src);
 861   void decode_klass_not_null(Register dst, Register src);
 862 
 863   void set_narrow_klass(Register dst, Klass* k);
 864 
 865   // if heap base register is used - reinit it with the correct value
 866   void reinit_heapbase();
 867 
 868   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 869 
 870   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 871                       int sve_vector_size_in_bytes = 0);
 872   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 873                       int sve_vector_size_in_bytes = 0);
 874 
 875   void push_cont_fastpath(Register java_thread);
 876   void pop_cont_fastpath(Register java_thread);
 877   void inc_held_monitor_count(Register java_thread);
 878   void dec_held_monitor_count(Register java_thread);
 879   void reset_held_monitor_count(Register java_thread);
 880 
 881   // Round up to a power of two
 882   void round_to(Register reg, int modulus);
 883 
 884   // allocation
 885   void eden_allocate(
 886     Register obj,                      // result: pointer to object after successful allocation
 887     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 888     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 889     Register t1,                       // temp register
 890     Label&   slow_case                 // continuation point if fast allocation fails
 891   );
 892   void tlab_allocate(
 893     Register obj,                      // result: pointer to object after successful allocation
 894     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 895     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 896     Register t1,                       // temp register
 897     Register t2,                       // temp register
 898     Label&   slow_case                 // continuation point if fast allocation fails
 899   );
 900   void verify_tlab();
 901 
 902   // interface method calling
 903   void lookup_interface_method(Register recv_klass,
 904                                Register intf_klass,
 905                                RegisterOrConstant itable_index,
 906                                Register method_result,
 907                                Register scan_temp,
 908                                Label& no_such_interface,
 909                    bool return_method = true);
 910 
 911   // virtual method calling
 912   // n.b. x86 allows RegisterOrConstant for vtable_index
 913   void lookup_virtual_method(Register recv_klass,
 914                              RegisterOrConstant vtable_index,
 915                              Register method_result);
 916 
 917   // Test sub_klass against super_klass, with fast and slow paths.
 918 
 919   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 920   // One of the three labels can be NULL, meaning take the fall-through.
 921   // If super_check_offset is -1, the value is loaded up from super_klass.
 922   // No registers are killed, except temp_reg.
 923   void check_klass_subtype_fast_path(Register sub_klass,
 924                                      Register super_klass,
 925                                      Register temp_reg,
 926                                      Label* L_success,
 927                                      Label* L_failure,
 928                                      Label* L_slow_path,
 929                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 930 
 931   // The rest of the type check; must be wired to a corresponding fast path.
 932   // It does not repeat the fast path logic, so don't use it standalone.
 933   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 934   // Updates the sub's secondary super cache as necessary.
 935   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 936   void check_klass_subtype_slow_path(Register sub_klass,
 937                                      Register super_klass,
 938                                      Register temp_reg,
 939                                      Register temp2_reg,
 940                                      Label* L_success,
 941                                      Label* L_failure,
 942                                      bool set_cond_codes = false);
 943 
 944   // Simplified, combined version, good for typical uses.
 945   // Falls through on failure.
 946   void check_klass_subtype(Register sub_klass,
 947                            Register super_klass,
 948                            Register temp_reg,
 949                            Label& L_success);
 950 
 951   void clinit_barrier(Register klass,
 952                       Register thread,
 953                       Label* L_fast_path = NULL,
 954                       Label* L_slow_path = NULL);
 955 
 956   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 957 
 958   void verify_sve_vector_length();
 959   void reinitialize_ptrue() {
 960     if (UseSVE > 0) {
 961       sve_ptrue(ptrue, B);
 962     }
 963   }
 964   void verify_ptrue();
 965 
 966   // Debugging
 967 
 968   // only if +VerifyOops
 969   void verify_oop(Register reg, const char* s = "broken oop");
 970   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 971 
 972 // TODO: verify method and klass metadata (compare against vptr?)
 973   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 974   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 975 
 976 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 977 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 978 
 979   // only if +VerifyFPU
 980   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 981 
 982   // prints msg, dumps registers and stops execution
 983   void stop(const char* msg);
 984 
 985   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 986 
 987   void untested()                                { stop("untested"); }
 988 
 989   void unimplemented(const char* what = "");
 990 
 991   void should_not_reach_here()                   { stop("should not reach here"); }
 992 
 993   void _assert_asm(Condition cc, const char* msg);
 994 #define assert_asm0(cc, msg) _assert_asm(cc, FILE_AND_LINE ": " msg)
 995 #define assert_asm(masm, command, cc, msg) DEBUG_ONLY(command; (masm)->_assert_asm(cc, FILE_AND_LINE ": " #command " " #cc ": " msg))
 996 
 997   // Stack overflow checking
 998   void bang_stack_with_offset(int offset) {
 999     // stack grows down, caller passes positive offset
1000     assert(offset > 0, "must bang with negative offset");
1001     sub(rscratch2, sp, offset);
1002     str(zr, Address(rscratch2));
1003   }
1004 
1005   // Writes to stack successive pages until offset reached to check for
1006   // stack overflow + shadow pages.  Also, clobbers tmp
1007   void bang_stack_size(Register size, Register tmp);
1008 
1009   // Check for reserved stack access in method being exited (for JIT)
1010   void reserved_stack_check();
1011 
1012   // Arithmetics
1013 
1014   void addptr(const Address &dst, int32_t src);
1015   void cmpptr(Register src1, Address src2);
1016 
1017   void cmpoop(Register obj1, Register obj2);
1018 
1019   // Various forms of CAS
1020 
1021   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1022                           Label &suceed, Label *fail);
1023   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1024                   Label &suceed, Label *fail);
1025 
1026   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1027                   Label &suceed, Label *fail);
1028 
1029   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1030   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1031   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1032   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1033 
1034   void atomic_xchg(Register prev, Register newv, Register addr);
1035   void atomic_xchgw(Register prev, Register newv, Register addr);
1036   void atomic_xchgl(Register prev, Register newv, Register addr);
1037   void atomic_xchglw(Register prev, Register newv, Register addr);
1038   void atomic_xchgal(Register prev, Register newv, Register addr);
1039   void atomic_xchgalw(Register prev, Register newv, Register addr);
1040 
1041   void orptr(Address adr, RegisterOrConstant src) {
1042     ldr(rscratch1, adr);
1043     if (src.is_register())
1044       orr(rscratch1, rscratch1, src.as_register());
1045     else
1046       orr(rscratch1, rscratch1, src.as_constant());
1047     str(rscratch1, adr);
1048   }
1049 
1050   // A generic CAS; success or failure is in the EQ flag.
1051   // Clobbers rscratch1
1052   void cmpxchg(Register addr, Register expected, Register new_val,
1053                enum operand_size size,
1054                bool acquire, bool release, bool weak,
1055                Register result);
1056 
1057 private:
1058   void compare_eq(Register rn, Register rm, enum operand_size size);
1059 
1060 #ifdef ASSERT
1061   // Template short-hand support to clean-up after a failed call to trampoline
1062   // call generation (see trampoline_call() below),  when a set of Labels must
1063   // be reset (before returning).
1064   template<typename Label, typename... More>
1065   void reset_labels(Label &lbl, More&... more) {
1066     lbl.reset(); reset_labels(more...);
1067   }
1068   template<typename Label>
1069   void reset_labels(Label &lbl) {
1070     lbl.reset();
1071   }
1072 #endif
1073 
1074 public:
1075   // Calls
1076 
1077   address trampoline_call(Address entry, CodeBuffer* cbuf = NULL) { return trampoline_call1(entry, cbuf, true); }
1078   address trampoline_call1(Address entry, CodeBuffer* cbuf, bool check_emit_size = true);
1079 
1080   static bool far_branches() {
1081     return ReservedCodeCacheSize > branch_range;
1082   }
1083 
1084   // Jumps that can reach anywhere in the code cache.
1085   // Trashes tmp.
1086   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1087   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1088 
1089   static int far_branch_size() {
1090     if (far_branches()) {
1091       return 3 * 4;  // adrp, add, br
1092     } else {
1093       return 4;
1094     }
1095   }
1096 
1097   // Emit the CompiledIC call idiom
1098   address ic_call(address entry, jint method_index = 0);
1099 
1100 public:
1101 
1102   // Data
1103 
1104   void mov_metadata(Register dst, Metadata* obj);
1105   Address allocate_metadata_address(Metadata* obj);
1106   Address constant_oop_address(jobject obj);
1107 
1108   void movoop(Register dst, jobject obj, bool immediate = false);
1109 
1110   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1111   void kernel_crc32(Register crc, Register buf, Register len,
1112         Register table0, Register table1, Register table2, Register table3,
1113         Register tmp, Register tmp2, Register tmp3);
1114   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1115   void kernel_crc32c(Register crc, Register buf, Register len,
1116         Register table0, Register table1, Register table2, Register table3,
1117         Register tmp, Register tmp2, Register tmp3);
1118 
1119   // Stack push and pop individual 64 bit registers
1120   void push(Register src);
1121   void pop(Register dst);
1122 
1123   // push all registers onto the stack
1124   void pusha();
1125   void popa();
1126 
1127   void repne_scan(Register addr, Register value, Register count,
1128                   Register scratch);
1129   void repne_scanw(Register addr, Register value, Register count,
1130                    Register scratch);
1131 
1132   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1133   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1134 
1135   // If a constant does not fit in an immediate field, generate some
1136   // number of MOV instructions and then perform the operation
1137   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1138                              add_sub_imm_insn insn1,
1139                              add_sub_reg_insn insn2);
1140   // Seperate vsn which sets the flags
1141   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1142                              add_sub_imm_insn insn1,
1143                              add_sub_reg_insn insn2);
1144 
1145 #define WRAP(INSN)                                                      \
1146   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1147     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1148   }                                                                     \
1149                                                                         \
1150   void INSN(Register Rd, Register Rn, Register Rm,                      \
1151              enum shift_kind kind, unsigned shift = 0) {                \
1152     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1153   }                                                                     \
1154                                                                         \
1155   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1156     Assembler::INSN(Rd, Rn, Rm);                                        \
1157   }                                                                     \
1158                                                                         \
1159   void INSN(Register Rd, Register Rn, Register Rm,                      \
1160            ext::operation option, int amount = 0) {                     \
1161     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1162   }
1163 
1164   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1165 
1166 #undef WRAP
1167 #define WRAP(INSN)                                                      \
1168   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1169     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1170   }                                                                     \
1171                                                                         \
1172   void INSN(Register Rd, Register Rn, Register Rm,                      \
1173              enum shift_kind kind, unsigned shift = 0) {                \
1174     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1175   }                                                                     \
1176                                                                         \
1177   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1178     Assembler::INSN(Rd, Rn, Rm);                                        \
1179   }                                                                     \
1180                                                                         \
1181   void INSN(Register Rd, Register Rn, Register Rm,                      \
1182            ext::operation option, int amount = 0) {                     \
1183     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1184   }
1185 
1186   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1187 
1188   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1189   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1190   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1191   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1192 
1193   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1194 
1195   void tableswitch(Register index, jint lowbound, jint highbound,
1196                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1197     adr(rscratch1, jumptable);
1198     subsw(rscratch2, index, lowbound);
1199     subsw(zr, rscratch2, highbound - lowbound);
1200     br(Assembler::HS, jumptable_end);
1201     add(rscratch1, rscratch1, rscratch2,
1202         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1203     br(rscratch1);
1204   }
1205 
1206   // Form an address from base + offset in Rd.  Rd may or may not
1207   // actually be used: you must use the Address that is returned.  It
1208   // is up to you to ensure that the shift provided matches the size
1209   // of your data.
1210   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1211 
1212   // Return true iff an address is within the 48-bit AArch64 address
1213   // space.
1214   bool is_valid_AArch64_address(address a) {
1215     return ((uint64_t)a >> 48) == 0;
1216   }
1217 
1218   // Load the base of the cardtable byte map into reg.
1219   void load_byte_map_base(Register reg);
1220 
1221   // Prolog generator routines to support switch between x86 code and
1222   // generated ARM code
1223 
1224   // routine to generate an x86 prolog for a stub function which
1225   // bootstraps into the generated ARM code which directly follows the
1226   // stub
1227   //
1228 
1229   public:
1230 
1231   void ldr_constant(Register dest, const Address &const_addr) {
1232     if (NearCpool) {
1233       ldr(dest, const_addr);
1234     } else {
1235       uint64_t offset;
1236       adrp(dest, InternalAddress(const_addr.target()), offset);
1237       ldr(dest, Address(dest, offset));
1238     }
1239   }
1240 
1241   address read_polling_page(Register r, relocInfo::relocType rtype);
1242   void get_polling_page(Register dest, relocInfo::relocType rtype);
1243 
1244   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1245   void update_byte_crc32(Register crc, Register val, Register table);
1246   void update_word_crc32(Register crc, Register v, Register tmp,
1247         Register table0, Register table1, Register table2, Register table3,
1248         bool upper = false);
1249 
1250   address has_negatives(Register ary1, Register len, Register result);
1251 
1252   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1253                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1254 
1255   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1256                      int elem_size);
1257 
1258   void fill_words(Register base, Register cnt, Register value);
1259   void zero_words(Register base, uint64_t cnt);
1260   address zero_words(Register ptr, Register cnt);
1261   void zero_dcache_blocks(Register base, Register cnt);
1262 
1263   static const int zero_words_block_size;
1264 
1265   address byte_array_inflate(Register src, Register dst, Register len,
1266                              FloatRegister vtmp1, FloatRegister vtmp2,
1267                              FloatRegister vtmp3, Register tmp4);
1268 
1269   void char_array_compress(Register src, Register dst, Register len,
1270                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1271                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1272                            Register result);
1273 
1274   void encode_iso_array(Register src, Register dst,
1275                         Register len, Register result,
1276                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1277                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1278   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1279                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1280                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1281                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1282                 Register tmp3, Register tmp4, Register tmp5);
1283   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1284       address pio2, address dsin_coef, address dcos_coef);
1285  private:
1286   // begin trigonometric functions support block
1287   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1288   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1289   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1290   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1291   // end trigonometric functions support block
1292   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1293                        Register src1, Register src2);
1294   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1295     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1296   }
1297   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1298                              Register y, Register y_idx, Register z,
1299                              Register carry, Register product,
1300                              Register idx, Register kdx);
1301   void multiply_128_x_128_loop(Register y, Register z,
1302                                Register carry, Register carry2,
1303                                Register idx, Register jdx,
1304                                Register yz_idx1, Register yz_idx2,
1305                                Register tmp, Register tmp3, Register tmp4,
1306                                Register tmp7, Register product_hi);
1307   void kernel_crc32_using_crc32(Register crc, Register buf,
1308         Register len, Register tmp0, Register tmp1, Register tmp2,
1309         Register tmp3);
1310   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1311         Register len, Register tmp0, Register tmp1, Register tmp2,
1312         Register tmp3);
1313 
1314   void ghash_modmul (FloatRegister result,
1315                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1316                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1317                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1318   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1319 public:
1320   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1321                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1322                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1323   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1324   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1325                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1326                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1327   void ghash_multiply_wide(int index,
1328                            FloatRegister result_lo, FloatRegister result_hi,
1329                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1330                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1331   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1332                     FloatRegister p, FloatRegister z, FloatRegister t1);
1333   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1334                     FloatRegister p, FloatRegister z, FloatRegister t1);
1335   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1336                                 Register data, Register blocks, int unrolls);
1337 
1338 
1339   void aesenc_loadkeys(Register key, Register keylen);
1340   void aesecb_encrypt(Register from, Register to, Register keylen,
1341                       FloatRegister data = v0, int unrolls = 1);
1342   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1343   void aes_round(FloatRegister input, FloatRegister subkey);
1344 
1345   // Place an ISB after code may have been modified due to a safepoint.
1346   void safepoint_isb();
1347 
1348 private:
1349   // Return the effective address r + (r1 << ext) + offset.
1350   // Uses rscratch2.
1351   Address offsetted_address(Register r, Register r1, Address::extend ext,
1352                             int offset, int size);
1353 
1354 private:
1355   // Returns an address on the stack which is reachable with a ldr/str of size
1356   // Uses rscratch2 if the address is not directly reachable
1357   Address spill_address(int size, int offset, Register tmp=rscratch2);
1358   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1359 
1360   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1361 
1362   // Check whether two loads/stores can be merged into ldp/stp.
1363   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1364 
1365   // Merge current load/store with previous load/store into ldp/stp.
1366   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1367 
1368   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1369   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1370 
1371 public:
1372   void spill(Register Rx, bool is64, int offset) {
1373     if (is64) {
1374       str(Rx, spill_address(8, offset));
1375     } else {
1376       strw(Rx, spill_address(4, offset));
1377     }
1378   }
1379   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1380     str(Vx, T, spill_address(1 << (int)T, offset));
1381   }
1382   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1383     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1384   }
1385   void unspill(Register Rx, bool is64, int offset) {
1386     if (is64) {
1387       ldr(Rx, spill_address(8, offset));
1388     } else {
1389       ldrw(Rx, spill_address(4, offset));
1390     }
1391   }
1392   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1393     ldr(Vx, T, spill_address(1 << (int)T, offset));
1394   }
1395   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1396     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1397   }
1398   void spill_copy128(int src_offset, int dst_offset,
1399                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1400     if (src_offset < 512 && (src_offset & 7) == 0 &&
1401         dst_offset < 512 && (dst_offset & 7) == 0) {
1402       ldp(tmp1, tmp2, Address(sp, src_offset));
1403       stp(tmp1, tmp2, Address(sp, dst_offset));
1404     } else {
1405       unspill(tmp1, true, src_offset);
1406       spill(tmp1, true, dst_offset);
1407       unspill(tmp1, true, src_offset+8);
1408       spill(tmp1, true, dst_offset+8);
1409     }
1410   }
1411   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1412                                             int sve_vec_reg_size_in_bytes) {
1413     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1414     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1415       spill_copy128(src_offset, dst_offset);
1416       src_offset += 16;
1417       dst_offset += 16;
1418     }
1419   }
1420   void cache_wb(Address line);
1421   void cache_wbsync(bool is_pre);
1422 
1423 private:
1424   // Check the current thread doesn't need a cross modify fence.
1425   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1426 
1427 };
1428 
1429 #ifdef ASSERT
1430 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1431 #endif
1432 
1433 /**
1434  * class SkipIfEqual:
1435  *
1436  * Instantiating this class will result in assembly code being output that will
1437  * jump around any code emitted between the creation of the instance and it's
1438  * automatic destruction at the end of a scope block, depending on the value of
1439  * the flag passed to the constructor, which will be checked at run-time.
1440  */
1441 class SkipIfEqual {
1442  private:
1443   MacroAssembler* _masm;
1444   Label _label;
1445 
1446  public:
1447    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1448    ~SkipIfEqual();
1449 };
1450 
1451 struct tableswitch {
1452   Register _reg;
1453   int _insn_index; jint _first_key; jint _last_key;
1454   Label _after;
1455   Label _branches;
1456 };
1457 
1458 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP