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src/hotspot/cpu/aarch64/nativeInst_aarch64.hpp

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 54   friend class Relocation;
 55   friend bool is_NativeCallTrampolineStub_at(address);
 56 public:
 57   enum {
 58     instruction_size = 4
 59   };
 60 
 61   juint encoding() const {
 62     return uint_at(0);
 63   }
 64 
 65   bool is_blr() const {
 66     // blr(register) or br(register)
 67     return (encoding() & 0xff9ffc1f) == 0xd61f0000;
 68   }
 69   bool is_adr_aligned() const {
 70     // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction).
 71     return (encoding() & 0xff000000) == 0x10000000;
 72   }
 73 
 74   inline bool is_nop();
 75   bool is_jump();
 76   bool is_general_jump();
 77   inline bool is_jump_or_nop();
 78   inline bool is_cond_jump();
 79   bool is_safepoint_poll();
 80   bool is_movz();
 81   bool is_movk();
 82   bool is_sigill_zombie_not_entrant();
 83   bool is_stop();
 84 
 85 protected:
 86   address addr_at(int offset) const { return address(this) + offset; }
 87 
 88   s_char sbyte_at(int offset) const { return *(s_char*)addr_at(offset); }
 89   u_char ubyte_at(int offset) const { return *(u_char*)addr_at(offset); }
 90   jint int_at(int offset) const { return *(jint*)addr_at(offset); }
 91   juint uint_at(int offset) const { return *(juint*)addr_at(offset); }
 92   address ptr_at(int offset) const { return *(address*)addr_at(offset); }
 93   oop oop_at(int offset) const { return *(oop*)addr_at(offset); }
 94 

526 public:
527   // Insert illegal opcode as specific address
528   static void insert(address code_pos);
529 };
530 
531 // return instruction that does not pop values of the stack
532 class NativeReturn: public NativeInstruction {
533 public:
534 };
535 
536 // return instruction that does pop values of the stack
537 class NativeReturnX: public NativeInstruction {
538 public:
539 };
540 
541 // Simple test vs memory
542 class NativeTstRegMem: public NativeInstruction {
543 public:
544 };
545 
546 inline bool NativeInstruction::is_nop() {
547   uint32_t insn = *(uint32_t*)addr_at(0);
548   return insn == 0xd503201f;
549 }
550 
551 inline bool NativeInstruction::is_jump() {
552   uint32_t insn = *(uint32_t*)addr_at(0);
553 
554   if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
555     // Unconditional branch (immediate)
556     return true;
557   } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
558     // Conditional branch (immediate)
559     return true;
560   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
561     // Compare & branch (immediate)
562     return true;
563   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
564     // Test & branch (immediate)
565     return true;
566   } else

649   bool is_not_pre_post_index() { return (is_ldst_ur() || is_ldst_unsigned_offset()); }
650   bool is_load() {
651     assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
652            Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
653 
654     return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01;
655   }
656   bool is_store() {
657     assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
658            Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
659 
660     return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00;
661   }
662 };
663 
664 inline NativeLdSt* NativeLdSt_at(address addr) {
665   assert(nativeInstruction_at(addr)->is_Imm_LdSt(), "no immediate load/store found");
666   return (NativeLdSt*)addr;
667 }
668 












































669 #endif // CPU_AARCH64_NATIVEINST_AARCH64_HPP

 54   friend class Relocation;
 55   friend bool is_NativeCallTrampolineStub_at(address);
 56 public:
 57   enum {
 58     instruction_size = 4
 59   };
 60 
 61   juint encoding() const {
 62     return uint_at(0);
 63   }
 64 
 65   bool is_blr() const {
 66     // blr(register) or br(register)
 67     return (encoding() & 0xff9ffc1f) == 0xd61f0000;
 68   }
 69   bool is_adr_aligned() const {
 70     // adr Xn, <label>, where label is aligned to 4 bytes (address of instruction).
 71     return (encoding() & 0xff000000) == 0x10000000;
 72   }
 73 
 74   inline bool is_nop() const;
 75   bool is_jump();
 76   bool is_general_jump();
 77   inline bool is_jump_or_nop();
 78   inline bool is_cond_jump();
 79   bool is_safepoint_poll();
 80   bool is_movz();
 81   bool is_movk();
 82   bool is_sigill_zombie_not_entrant();
 83   bool is_stop();
 84 
 85 protected:
 86   address addr_at(int offset) const { return address(this) + offset; }
 87 
 88   s_char sbyte_at(int offset) const { return *(s_char*)addr_at(offset); }
 89   u_char ubyte_at(int offset) const { return *(u_char*)addr_at(offset); }
 90   jint int_at(int offset) const { return *(jint*)addr_at(offset); }
 91   juint uint_at(int offset) const { return *(juint*)addr_at(offset); }
 92   address ptr_at(int offset) const { return *(address*)addr_at(offset); }
 93   oop oop_at(int offset) const { return *(oop*)addr_at(offset); }
 94 

526 public:
527   // Insert illegal opcode as specific address
528   static void insert(address code_pos);
529 };
530 
531 // return instruction that does not pop values of the stack
532 class NativeReturn: public NativeInstruction {
533 public:
534 };
535 
536 // return instruction that does pop values of the stack
537 class NativeReturnX: public NativeInstruction {
538 public:
539 };
540 
541 // Simple test vs memory
542 class NativeTstRegMem: public NativeInstruction {
543 public:
544 };
545 
546 inline bool NativeInstruction::is_nop() const{
547   uint32_t insn = *(uint32_t*)addr_at(0);
548   return insn == 0xd503201f;
549 }
550 
551 inline bool NativeInstruction::is_jump() {
552   uint32_t insn = *(uint32_t*)addr_at(0);
553 
554   if (Instruction_aarch64::extract(insn, 30, 26) == 0b00101) {
555     // Unconditional branch (immediate)
556     return true;
557   } else if (Instruction_aarch64::extract(insn, 31, 25) == 0b0101010) {
558     // Conditional branch (immediate)
559     return true;
560   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011010) {
561     // Compare & branch (immediate)
562     return true;
563   } else if (Instruction_aarch64::extract(insn, 30, 25) == 0b011011) {
564     // Test & branch (immediate)
565     return true;
566   } else

649   bool is_not_pre_post_index() { return (is_ldst_ur() || is_ldst_unsigned_offset()); }
650   bool is_load() {
651     assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
652            Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
653 
654     return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01;
655   }
656   bool is_store() {
657     assert(Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b01 ||
658            Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00, "must be ldr or str");
659 
660     return Instruction_aarch64::extract(uint_at(0), 23, 22) == 0b00;
661   }
662 };
663 
664 inline NativeLdSt* NativeLdSt_at(address addr) {
665   assert(nativeInstruction_at(addr)->is_Imm_LdSt(), "no immediate load/store found");
666   return (NativeLdSt*)addr;
667 }
668 
669 class NativePostCallNop: public NativeInstruction {
670 public:
671   bool check() const { return is_nop(); }
672   int displacement() const { return 0; }
673   void patch(jint diff);
674   void make_deopt();
675 };
676 
677 inline NativePostCallNop* nativePostCallNop_at(address address) {
678   NativePostCallNop* nop = (NativePostCallNop*) address;
679   if (nop->check()) {
680     return nop;
681   }
682   return NULL;
683 }
684 
685 inline NativePostCallNop* nativePostCallNop_unsafe_at(address address) {
686   NativePostCallNop* nop = (NativePostCallNop*) address;
687   assert (nop->check(), "");
688   return nop;
689 }
690 
691 class NativeDeoptInstruction: public NativeInstruction {
692  public:
693   enum {
694     instruction_size            =    4,
695     instruction_offset          =    0,
696   };
697 
698   address instruction_address() const       { return addr_at(instruction_offset); }
699   address next_instruction_address() const  { return addr_at(instruction_size); }
700 
701   void  verify();
702 
703   static bool is_deopt_at(address instr) {
704     assert (instr != NULL, "");
705     uint32_t value = *(uint32_t *) instr;
706     return value == 0xd4ade001;
707   }
708 
709   // MT-safe patching
710   static void insert(address code_pos);
711 };
712 
713 #endif // CPU_AARCH64_NATIVEINST_AARCH64_HPP
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