1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
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24 */
25
26 #ifndef CPU_AARCH64_VM_VERSION_AARCH64_HPP
27 #define CPU_AARCH64_VM_VERSION_AARCH64_HPP
28
29 #include "spin_wait_aarch64.hpp"
30 #include "runtime/abstract_vm_version.hpp"
31 #include "utilities/sizes.hpp"
32
33 class VM_Version : public Abstract_VM_Version {
34 friend class VMStructs;
35 friend class JVMCIVMStructs;
36
37 protected:
38 static int _cpu;
39 static int _model;
40 static int _model2;
41 static int _variant;
42 static int _revision;
43 static int _stepping;
44
45 static int _zva_length;
46 static int _dcache_line_size;
47 static int _icache_line_size;
48 static int _initial_sve_vector_length;
49 static bool _rop_protection;
50 static uintptr_t _pac_mask;
51
52 static SpinWait _spin_wait;
53
54 // Read additional info using OS-specific interfaces
55 static void get_os_cpu_info();
56
57 // Sets the SVE length and returns a new actual value or negative on error.
58 // If the len is larger than the system largest supported SVE vector length,
59 // the function sets the largest supported value.
60 static int set_and_get_current_sve_vector_length(int len);
61 static int get_current_sve_vector_length();
62
63 public:
64 // Initialization
65 static void initialize();
66 static void check_virtualizations();
67
68 static void print_platform_virtualization_info(outputStream*);
69
70 // Asserts
71 static void assert_is_initialized() {
72 }
73
74 static bool expensive_load(int ld_size, int scale) {
75 if (cpu_family() == CPU_ARM) {
76 // Half-word load with index shift by 1 (aka scale is 2) has
77 // extra cycle latency, e.g. ldrsh w0, [x1,w2,sxtw #1].
78 if (ld_size == 2 && scale == 2) {
79 return true;
80 }
81 }
82 return false;
83 }
84
85 // The CPU implementer codes can be found in
86 // ARM Architecture Reference Manual ARMv8, for ARMv8-A architecture profile
87 // https://developer.arm.com/docs/ddi0487/latest
88 // Arm can assign codes that are not published in the manual.
89 // Apple's code is defined in
90 // https://github.com/apple/darwin-xnu/blob/33eb983/osfmk/arm/cpuid.h#L62
91 enum Family {
92 CPU_AMPERE = 0xC0,
93 CPU_ARM = 'A',
94 CPU_BROADCOM = 'B',
95 CPU_CAVIUM = 'C',
96 CPU_DEC = 'D',
97 CPU_HISILICON = 'H',
98 CPU_INFINEON = 'I',
99 CPU_MOTOROLA = 'M',
100 CPU_NVIDIA = 'N',
101 CPU_AMCC = 'P',
102 CPU_QUALCOM = 'Q',
103 CPU_MARVELL = 'V',
104 CPU_INTEL = 'i',
105 CPU_APPLE = 'a',
106 };
107
108 enum Ampere_CPU_Model {
109 CPU_MODEL_EMAG = 0x0, /* CPU implementer is CPU_AMCC */
110 CPU_MODEL_ALTRA = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
111 CPU_MODEL_ALTRAMAX = 0xd0c, /* CPU implementer is CPU_ARM, Neoverse N1 */
112 CPU_MODEL_AMPERE_1 = 0xac3, /* CPU implementer is CPU_AMPERE */
113 CPU_MODEL_AMPERE_1A = 0xac4, /* CPU implementer is CPU_AMPERE */
114 CPU_MODEL_AMPERE_1B = 0xac5 /* AMPERE_1B core Implements ARMv8.7 with CSSC, MTE, SM3/SM4 extensions */
115 };
116
117 #define CPU_FEATURE_FLAGS(decl) \
118 decl(FP, fp, 0) \
119 decl(ASIMD, asimd, 1) \
120 decl(EVTSTRM, evtstrm, 2) \
121 decl(AES, aes, 3) \
122 decl(PMULL, pmull, 4) \
123 decl(SHA1, sha1, 5) \
124 decl(SHA2, sha256, 6) \
125 decl(CRC32, crc32, 7) \
126 decl(LSE, lse, 8) \
127 decl(DCPOP, dcpop, 16) \
128 decl(SHA3, sha3, 17) \
129 decl(SHA512, sha512, 21) \
130 decl(SVE, sve, 22) \
131 decl(PACA, paca, 30) \
132 /* flags above must follow Linux HWCAP */ \
133 decl(SVEBITPERM, svebitperm, 27) \
134 decl(SVE2, sve2, 28) \
135 decl(A53MAC, a53mac, 31)
136
137 enum Feature_Flag {
138 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1 << bit),
139 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
140 #undef DECLARE_CPU_FEATURE_FLAG
141 };
142
143 // Feature identification
144 #define CPU_FEATURE_DETECTION(id, name, bit) \
145 static bool supports_##name() { return (_features & CPU_##id) != 0; };
146 CPU_FEATURE_FLAGS(CPU_FEATURE_DETECTION)
147 #undef CPU_FEATURE_DETECTION
148
149 static int cpu_family() { return _cpu; }
150 static int cpu_model() { return _model; }
151 static int cpu_model2() { return _model2; }
152 static int cpu_variant() { return _variant; }
153 static int cpu_revision() { return _revision; }
154
155 static bool model_is(int cpu_model) {
156 return _model == cpu_model || _model2 == cpu_model;
157 }
158
159 static bool is_zva_enabled() { return 0 <= _zva_length; }
160 static int zva_length() {
161 assert(is_zva_enabled(), "ZVA not available");
162 return _zva_length;
163 }
164
165 static int icache_line_size() { return _icache_line_size; }
166 static int dcache_line_size() { return _dcache_line_size; }
167 static int get_initial_sve_vector_length() { return _initial_sve_vector_length; };
168
169 // Aarch64 supports fast class initialization checks
170 static bool supports_fast_class_init_checks() { return true; }
171 static bool supports_cont_preemption() { return true; }
172 constexpr static bool supports_stack_watermark_barrier() { return true; }
173 constexpr static bool supports_recursive_lightweight_locking() { return true; }
174
175 constexpr static bool supports_secondary_supers_table() { return true; }
176
177 static void get_compatible_board(char *buf, int buflen);
178
179 static const SpinWait& spin_wait_desc() { return _spin_wait; }
180
181 static bool supports_on_spin_wait() { return _spin_wait.inst() != SpinWait::NONE; }
182
183 static bool supports_float16() { return true; }
184
185 #ifdef __APPLE__
186 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
187 static bool is_cpu_emulated();
188 #endif
189
190 static void initialize_cpu_information(void);
191
192 static bool use_rop_protection() { return _rop_protection; }
193
194 // For common 64/128-bit unpredicated vector operations, we may prefer
195 // emitting NEON instructions rather than the corresponding SVE instructions.
196 static bool use_neon_for_vector(int vector_length_in_bytes) {
197 return vector_length_in_bytes <= 16;
198 }
199 };
200
201 #endif // CPU_AARCH64_VM_VERSION_AARCH64_HPP