1 /* 2 * Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved. 3 * Copyright (c) 2012, 2024 SAP SE. All rights reserved. 4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 * 6 * This code is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 only, as 8 * published by the Free Software Foundation. 9 * 10 * This code is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 * version 2 for more details (a copy is included in the LICENSE file that 14 * accompanied this code). 15 * 16 * You should have received a copy of the GNU General Public License version 17 * 2 along with this work; if not, write to the Free Software Foundation, 18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 * 20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 * or visit www.oracle.com if you need additional information or have any 22 * questions. 23 * 24 */ 25 26 #ifndef CPU_PPC_ASSEMBLER_PPC_HPP 27 #define CPU_PPC_ASSEMBLER_PPC_HPP 28 29 #include "asm/assembler.hpp" 30 #include "asm/register.hpp" 31 32 // Address is an abstraction used to represent a memory location 33 // as used in assembler instructions. 34 // PPC instructions grok either baseReg + indexReg or baseReg + disp. 35 class Address { 36 private: 37 Register _base; // Base register. 38 Register _index; // Index register. 39 intptr_t _disp; // Displacement. 40 41 public: 42 Address(Register b, Register i, address d = 0) 43 : _base(b), _index(i), _disp((intptr_t)d) { 44 assert(i == noreg || d == 0, "can't have both"); 45 } 46 47 Address(Register b, address d = 0) 48 : _base(b), _index(noreg), _disp((intptr_t)d) {} 49 50 Address(Register b, ByteSize d) 51 : _base(b), _index(noreg), _disp((intptr_t)d) {} 52 53 Address(Register b, intptr_t d) 54 : _base(b), _index(noreg), _disp(d) {} 55 56 Address(Register b, RegisterOrConstant roc) 57 : _base(b), _index(noreg), _disp(0) { 58 if (roc.is_constant()) _disp = roc.as_constant(); else _index = roc.as_register(); 59 } 60 61 Address() 62 : _base(noreg), _index(noreg), _disp(0) {} 63 64 // accessors 65 Register base() const { return _base; } 66 Register index() const { return _index; } 67 int disp() const { return (int)_disp; } 68 bool is_const() const { return _base == noreg && _index == noreg; } 69 }; 70 71 class AddressLiteral { 72 private: 73 address _address; 74 RelocationHolder _rspec; 75 76 RelocationHolder rspec_from_rtype(relocInfo::relocType rtype, address addr) { 77 switch (rtype) { 78 case relocInfo::external_word_type: 79 return external_word_Relocation::spec(addr); 80 case relocInfo::internal_word_type: 81 return internal_word_Relocation::spec(addr); 82 case relocInfo::opt_virtual_call_type: 83 return opt_virtual_call_Relocation::spec(); 84 case relocInfo::static_call_type: 85 return static_call_Relocation::spec(); 86 case relocInfo::runtime_call_type: 87 return runtime_call_Relocation::spec(); 88 case relocInfo::none: 89 return RelocationHolder(); 90 default: 91 ShouldNotReachHere(); 92 return RelocationHolder(); 93 } 94 } 95 96 protected: 97 // creation 98 AddressLiteral() : _address(nullptr), _rspec() {} 99 100 public: 101 AddressLiteral(address addr, RelocationHolder const& rspec) 102 : _address(addr), 103 _rspec(rspec) {} 104 105 AddressLiteral(address addr, relocInfo::relocType rtype = relocInfo::none) 106 : _address((address) addr), 107 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 108 109 AddressLiteral(oop* addr, relocInfo::relocType rtype = relocInfo::none) 110 : _address((address) addr), 111 _rspec(rspec_from_rtype(rtype, (address) addr)) {} 112 113 intptr_t value() const { return (intptr_t) _address; } 114 115 const RelocationHolder& rspec() const { return _rspec; } 116 }; 117 118 // Argument is an abstraction used to represent an outgoing 119 // actual argument or an incoming formal parameter, whether 120 // it resides in memory or in a register, in a manner consistent 121 // with the PPC Application Binary Interface, or ABI. This is 122 // often referred to as the native or C calling convention. 123 124 class Argument { 125 private: 126 int _number; // The number of the argument. 127 public: 128 enum { 129 // PPC C calling conventions. 130 // The first eight arguments are passed in int regs if they are int. 131 n_int_register_parameters_c = 8, 132 // The first thirteen float arguments are passed in float regs. 133 n_float_register_parameters_c = 13, 134 135 #ifdef VM_LITTLE_ENDIAN 136 // Floats are in the least significant word of an argument slot. 137 float_on_stack_offset_in_bytes_c = 0, 138 #else 139 // Although AIX runs on big endian CPU, float is in the most 140 // significant word of an argument slot. 141 float_on_stack_offset_in_bytes_c = AIX_ONLY(0) NOT_AIX(4), 142 #endif 143 144 n_int_register_parameters_j = 8, // duplicates num_java_iarg_registers 145 n_float_register_parameters_j = 13, // num_java_farg_registers 146 }; 147 // creation 148 Argument(int number) : _number(number) {} 149 150 int number() const { return _number; } 151 152 // Locating register-based arguments: 153 bool is_register() const { return _number < n_int_register_parameters_c; } 154 155 Register as_register() const { 156 assert(is_register(), "must be a register argument"); 157 return as_Register(number() + R3_ARG1->encoding()); 158 } 159 }; 160 161 #if !defined(ABI_ELFv2) 162 // A ppc64 function descriptor. 163 struct FunctionDescriptor { 164 private: 165 address _entry; 166 address _toc; 167 address _env; 168 169 public: 170 inline address entry() const { return _entry; } 171 inline address toc() const { return _toc; } 172 inline address env() const { return _env; } 173 174 inline void set_entry(address entry) { _entry = entry; } 175 inline void set_toc( address toc) { _toc = toc; } 176 inline void set_env( address env) { _env = env; } 177 178 inline static ByteSize entry_offset() { return byte_offset_of(FunctionDescriptor, _entry); } 179 inline static ByteSize toc_offset() { return byte_offset_of(FunctionDescriptor, _toc); } 180 inline static ByteSize env_offset() { return byte_offset_of(FunctionDescriptor, _env); } 181 182 // Friend functions can be called without loading toc and env. 183 enum { 184 friend_toc = 0xcafe, 185 friend_env = 0xc0de 186 }; 187 188 inline bool is_friend_function() const { 189 return (toc() == (address) friend_toc) && (env() == (address) friend_env); 190 } 191 192 // Constructor for stack-allocated instances. 193 FunctionDescriptor() { 194 _entry = (address) 0xbad; 195 _toc = (address) 0xbad; 196 _env = (address) 0xbad; 197 } 198 }; 199 #endif 200 201 202 // The PPC Assembler: Pure assembler doing NO optimizations on the 203 // instruction level; i.e., what you write is what you get. The 204 // Assembler is generating code into a CodeBuffer. 205 206 class Assembler : public AbstractAssembler { 207 protected: 208 // Displacement routines 209 static int patched_branch(int dest_pos, int inst, int inst_pos); 210 static int branch_destination(int inst, int pos); 211 212 friend class AbstractAssembler; 213 214 // Code patchers need various routines like inv_wdisp() 215 friend class NativeInstruction; 216 friend class NativeGeneralJump; 217 friend class Relocation; 218 219 public: 220 221 enum shifts { 222 XO_21_29_SHIFT = 2, 223 XO_21_30_SHIFT = 1, 224 XO_27_29_SHIFT = 2, 225 XO_30_31_SHIFT = 0, 226 SPR_5_9_SHIFT = 11u, // SPR_5_9 field in bits 11 -- 15 227 SPR_0_4_SHIFT = 16u, // SPR_0_4 field in bits 16 -- 20 228 RS_SHIFT = 21u, // RS field in bits 21 -- 25 229 OPCODE_SHIFT = 26u, // opcode in bits 26 -- 31 230 231 // Shift counts in prefix word 232 PRE_TYPE_SHIFT = 24u, // Prefix type in bits 24 -- 25 233 PRE_ST1_SHIFT = 23u, // ST1 field in bits 23 -- 23 234 PRE_R_SHIFT = 20u, // R-bit in bits 20 -- 20 235 PRE_ST4_SHIFT = 20u, // ST4 field in bits 23 -- 20 236 }; 237 238 enum opcdxos_masks { 239 XL_FORM_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 240 ANDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 241 ADDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 242 ADDIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 243 BXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 244 BCXX_OPCODE_MASK = (63u << OPCODE_SHIFT), 245 CMPLI_OPCODE_MASK = (63u << OPCODE_SHIFT), 246 // trap instructions 247 TDI_OPCODE_MASK = (63u << OPCODE_SHIFT), 248 TWI_OPCODE_MASK = (63u << OPCODE_SHIFT), 249 TD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 250 TW_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 251 LD_OPCODE_MASK = (63u << OPCODE_SHIFT) | (3u << XO_30_31_SHIFT), // DS-FORM 252 STD_OPCODE_MASK = LD_OPCODE_MASK, 253 STDU_OPCODE_MASK = STD_OPCODE_MASK, 254 STDX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 255 STDUX_OPCODE_MASK = STDX_OPCODE_MASK, 256 STW_OPCODE_MASK = (63u << OPCODE_SHIFT), 257 STWU_OPCODE_MASK = STW_OPCODE_MASK, 258 STWX_OPCODE_MASK = (63u << OPCODE_SHIFT) | (1023u << 1), 259 STWUX_OPCODE_MASK = STWX_OPCODE_MASK, 260 MTCTR_OPCODE_MASK = ~(31u << RS_SHIFT), 261 ORI_OPCODE_MASK = (63u << OPCODE_SHIFT), 262 ORIS_OPCODE_MASK = (63u << OPCODE_SHIFT), 263 RLDICR_OPCODE_MASK = (63u << OPCODE_SHIFT) | (7u << XO_27_29_SHIFT) 264 }; 265 266 enum opcdxos { 267 ADD_OPCODE = (31u << OPCODE_SHIFT | 266u << 1), 268 ADDC_OPCODE = (31u << OPCODE_SHIFT | 10u << 1), 269 ADDI_OPCODE = (14u << OPCODE_SHIFT), 270 ADDIS_OPCODE = (15u << OPCODE_SHIFT), 271 ADDIC__OPCODE = (13u << OPCODE_SHIFT), 272 ADDE_OPCODE = (31u << OPCODE_SHIFT | 138u << 1), 273 ADDME_OPCODE = (31u << OPCODE_SHIFT | 234u << 1), 274 ADDZE_OPCODE = (31u << OPCODE_SHIFT | 202u << 1), 275 SUBF_OPCODE = (31u << OPCODE_SHIFT | 40u << 1), 276 SUBFC_OPCODE = (31u << OPCODE_SHIFT | 8u << 1), 277 SUBFE_OPCODE = (31u << OPCODE_SHIFT | 136u << 1), 278 SUBFIC_OPCODE = (8u << OPCODE_SHIFT), 279 SUBFME_OPCODE = (31u << OPCODE_SHIFT | 232u << 1), 280 SUBFZE_OPCODE = (31u << OPCODE_SHIFT | 200u << 1), 281 DIVW_OPCODE = (31u << OPCODE_SHIFT | 491u << 1), 282 DIVWU_OPCODE = (31u << OPCODE_SHIFT | 459u << 1), 283 MULLW_OPCODE = (31u << OPCODE_SHIFT | 235u << 1), 284 MULHW_OPCODE = (31u << OPCODE_SHIFT | 75u << 1), 285 MULHWU_OPCODE = (31u << OPCODE_SHIFT | 11u << 1), 286 MULLI_OPCODE = (7u << OPCODE_SHIFT), 287 AND_OPCODE = (31u << OPCODE_SHIFT | 28u << 1), 288 ANDI_OPCODE = (28u << OPCODE_SHIFT), 289 ANDIS_OPCODE = (29u << OPCODE_SHIFT), 290 ANDC_OPCODE = (31u << OPCODE_SHIFT | 60u << 1), 291 ORC_OPCODE = (31u << OPCODE_SHIFT | 412u << 1), 292 OR_OPCODE = (31u << OPCODE_SHIFT | 444u << 1), 293 ORI_OPCODE = (24u << OPCODE_SHIFT), 294 ORIS_OPCODE = (25u << OPCODE_SHIFT), 295 XOR_OPCODE = (31u << OPCODE_SHIFT | 316u << 1), 296 XORI_OPCODE = (26u << OPCODE_SHIFT), 297 XORIS_OPCODE = (27u << OPCODE_SHIFT), 298 299 NEG_OPCODE = (31u << OPCODE_SHIFT | 104u << 1), 300 301 RLWINM_OPCODE = (21u << OPCODE_SHIFT), 302 CLRRWI_OPCODE = RLWINM_OPCODE, 303 CLRLWI_OPCODE = RLWINM_OPCODE, 304 305 RLWIMI_OPCODE = (20u << OPCODE_SHIFT), 306 307 SLW_OPCODE = (31u << OPCODE_SHIFT | 24u << 1), 308 SLWI_OPCODE = RLWINM_OPCODE, 309 SRW_OPCODE = (31u << OPCODE_SHIFT | 536u << 1), 310 SRWI_OPCODE = RLWINM_OPCODE, 311 SRAW_OPCODE = (31u << OPCODE_SHIFT | 792u << 1), 312 SRAWI_OPCODE = (31u << OPCODE_SHIFT | 824u << 1), 313 314 CMP_OPCODE = (31u << OPCODE_SHIFT | 0u << 1), 315 CMPI_OPCODE = (11u << OPCODE_SHIFT), 316 CMPL_OPCODE = (31u << OPCODE_SHIFT | 32u << 1), 317 CMPLI_OPCODE = (10u << OPCODE_SHIFT), 318 CMPRB_OPCODE = (31u << OPCODE_SHIFT | 192u << 1), 319 CMPEQB_OPCODE = (31u << OPCODE_SHIFT | 224u << 1), 320 321 ISEL_OPCODE = (31u << OPCODE_SHIFT | 15u << 1), 322 323 // Special purpose registers 324 MTSPR_OPCODE = (31u << OPCODE_SHIFT | 467u << 1), 325 MFSPR_OPCODE = (31u << OPCODE_SHIFT | 339u << 1), 326 327 MTXER_OPCODE = (MTSPR_OPCODE | 1 << SPR_0_4_SHIFT), 328 MFXER_OPCODE = (MFSPR_OPCODE | 1 << SPR_0_4_SHIFT), 329 330 MTDSCR_OPCODE = (MTSPR_OPCODE | 3 << SPR_0_4_SHIFT), 331 MFDSCR_OPCODE = (MFSPR_OPCODE | 3 << SPR_0_4_SHIFT), 332 333 MTLR_OPCODE = (MTSPR_OPCODE | 8 << SPR_0_4_SHIFT), 334 MFLR_OPCODE = (MFSPR_OPCODE | 8 << SPR_0_4_SHIFT), 335 336 MTCTR_OPCODE = (MTSPR_OPCODE | 9 << SPR_0_4_SHIFT), 337 MFCTR_OPCODE = (MFSPR_OPCODE | 9 << SPR_0_4_SHIFT), 338 339 // Attention: Higher and lower half are inserted in reversed order. 340 MTVRSAVE_OPCODE = (MTSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 341 MFVRSAVE_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 0 << SPR_0_4_SHIFT), 342 343 MFTB_OPCODE = (MFSPR_OPCODE | 8 << SPR_5_9_SHIFT | 12 << SPR_0_4_SHIFT), 344 345 MTCRF_OPCODE = (31u << OPCODE_SHIFT | 144u << 1), 346 MFCR_OPCODE = (31u << OPCODE_SHIFT | 19u << 1), 347 MCRF_OPCODE = (19u << OPCODE_SHIFT | 0u << 1), 348 MCRXRX_OPCODE = (31u << OPCODE_SHIFT | 576u << 1), 349 SETB_OPCODE = (31u << OPCODE_SHIFT | 128u << 1), 350 351 SETBC_OPCODE = (31u << OPCODE_SHIFT | 384u << 1), 352 SETNBC_OPCODE = (31u << OPCODE_SHIFT | 448u << 1), 353 SETBCR_OPCODE = (31u << OPCODE_SHIFT | 416u << 1), 354 355 // condition register logic instructions 356 CRAND_OPCODE = (19u << OPCODE_SHIFT | 257u << 1), 357 CRNAND_OPCODE = (19u << OPCODE_SHIFT | 225u << 1), 358 CROR_OPCODE = (19u << OPCODE_SHIFT | 449u << 1), 359 CRXOR_OPCODE = (19u << OPCODE_SHIFT | 193u << 1), 360 CRNOR_OPCODE = (19u << OPCODE_SHIFT | 33u << 1), 361 CREQV_OPCODE = (19u << OPCODE_SHIFT | 289u << 1), 362 CRANDC_OPCODE = (19u << OPCODE_SHIFT | 129u << 1), 363 CRORC_OPCODE = (19u << OPCODE_SHIFT | 417u << 1), 364 365 BCLR_OPCODE = (19u << OPCODE_SHIFT | 16u << 1), 366 BXX_OPCODE = (18u << OPCODE_SHIFT), 367 BCXX_OPCODE = (16u << OPCODE_SHIFT), 368 369 // CTR-related opcodes 370 BCCTR_OPCODE = (19u << OPCODE_SHIFT | 528u << 1), 371 372 LWZ_OPCODE = (32u << OPCODE_SHIFT), 373 LWZX_OPCODE = (31u << OPCODE_SHIFT | 23u << 1), 374 LWZU_OPCODE = (33u << OPCODE_SHIFT), 375 LWBRX_OPCODE = (31u << OPCODE_SHIFT | 534 << 1), 376 377 LHA_OPCODE = (42u << OPCODE_SHIFT), 378 LHAX_OPCODE = (31u << OPCODE_SHIFT | 343u << 1), 379 LHAU_OPCODE = (43u << OPCODE_SHIFT), 380 381 LHZ_OPCODE = (40u << OPCODE_SHIFT), 382 LHZX_OPCODE = (31u << OPCODE_SHIFT | 279u << 1), 383 LHZU_OPCODE = (41u << OPCODE_SHIFT), 384 LHBRX_OPCODE = (31u << OPCODE_SHIFT | 790 << 1), 385 386 LBZ_OPCODE = (34u << OPCODE_SHIFT), 387 LBZX_OPCODE = (31u << OPCODE_SHIFT | 87u << 1), 388 LBZU_OPCODE = (35u << OPCODE_SHIFT), 389 390 STW_OPCODE = (36u << OPCODE_SHIFT), 391 STWX_OPCODE = (31u << OPCODE_SHIFT | 151u << 1), 392 STWU_OPCODE = (37u << OPCODE_SHIFT), 393 STWUX_OPCODE = (31u << OPCODE_SHIFT | 183u << 1), 394 STWBRX_OPCODE = (31u << OPCODE_SHIFT | 662u << 1), 395 396 STH_OPCODE = (44u << OPCODE_SHIFT), 397 STHX_OPCODE = (31u << OPCODE_SHIFT | 407u << 1), 398 STHU_OPCODE = (45u << OPCODE_SHIFT), 399 STHBRX_OPCODE = (31u << OPCODE_SHIFT | 918u << 1), 400 401 STB_OPCODE = (38u << OPCODE_SHIFT), 402 STBX_OPCODE = (31u << OPCODE_SHIFT | 215u << 1), 403 STBU_OPCODE = (39u << OPCODE_SHIFT), 404 405 EXTSB_OPCODE = (31u << OPCODE_SHIFT | 954u << 1), 406 EXTSH_OPCODE = (31u << OPCODE_SHIFT | 922u << 1), 407 EXTSW_OPCODE = (31u << OPCODE_SHIFT | 986u << 1), // X-FORM 408 409 // 32 bit opcode encodings 410 411 LWA_OPCODE = (58u << OPCODE_SHIFT | 2u << XO_30_31_SHIFT), // DS-FORM 412 LWAX_OPCODE = (31u << OPCODE_SHIFT | 341u << XO_21_30_SHIFT), // X-FORM 413 414 CNTLZW_OPCODE = (31u << OPCODE_SHIFT | 26u << XO_21_30_SHIFT), // X-FORM 415 CNTTZW_OPCODE = (31u << OPCODE_SHIFT | 538u << XO_21_30_SHIFT), // X-FORM 416 417 // 64 bit opcode encodings 418 419 LD_OPCODE = (58u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 420 LDU_OPCODE = (58u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 421 LDX_OPCODE = (31u << OPCODE_SHIFT | 21u << XO_21_30_SHIFT), // X-FORM 422 LDBRX_OPCODE = (31u << OPCODE_SHIFT | 532u << 1), // X-FORM 423 424 STD_OPCODE = (62u << OPCODE_SHIFT | 0u << XO_30_31_SHIFT), // DS-FORM 425 STDU_OPCODE = (62u << OPCODE_SHIFT | 1u << XO_30_31_SHIFT), // DS-FORM 426 STDUX_OPCODE = (31u << OPCODE_SHIFT | 181u << 1), // X-FORM 427 STDX_OPCODE = (31u << OPCODE_SHIFT | 149u << XO_21_30_SHIFT), // X-FORM 428 STDBRX_OPCODE = (31u << OPCODE_SHIFT | 660u << 1), // X-FORM 429 430 RLDICR_OPCODE = (30u << OPCODE_SHIFT | 1u << XO_27_29_SHIFT), // MD-FORM 431 RLDICL_OPCODE = (30u << OPCODE_SHIFT | 0u << XO_27_29_SHIFT), // MD-FORM 432 RLDIC_OPCODE = (30u << OPCODE_SHIFT | 2u << XO_27_29_SHIFT), // MD-FORM 433 RLDIMI_OPCODE = (30u << OPCODE_SHIFT | 3u << XO_27_29_SHIFT), // MD-FORM 434 435 SRADI_OPCODE = (31u << OPCODE_SHIFT | 413u << XO_21_29_SHIFT), // XS-FORM 436 437 SLD_OPCODE = (31u << OPCODE_SHIFT | 27u << 1), // X-FORM 438 SRD_OPCODE = (31u << OPCODE_SHIFT | 539u << 1), // X-FORM 439 SRAD_OPCODE = (31u << OPCODE_SHIFT | 794u << 1), // X-FORM 440 441 MULLD_OPCODE = (31u << OPCODE_SHIFT | 233u << 1), // XO-FORM 442 MULHD_OPCODE = (31u << OPCODE_SHIFT | 73u << 1), // XO-FORM 443 MULHDU_OPCODE = (31u << OPCODE_SHIFT | 9u << 1), // XO-FORM 444 DIVD_OPCODE = (31u << OPCODE_SHIFT | 489u << 1), // XO-FORM 445 DIVDU_OPCODE = (31u << OPCODE_SHIFT | 457u << 1), // XO-FORM 446 447 CNTLZD_OPCODE = (31u << OPCODE_SHIFT | 58u << XO_21_30_SHIFT), // X-FORM 448 CNTTZD_OPCODE = (31u << OPCODE_SHIFT | 570u << XO_21_30_SHIFT), // X-FORM 449 NAND_OPCODE = (31u << OPCODE_SHIFT | 476u << XO_21_30_SHIFT), // X-FORM 450 NOR_OPCODE = (31u << OPCODE_SHIFT | 124u << XO_21_30_SHIFT), // X-FORM 451 452 // Byte reverse opcodes (introduced with Power10) 453 BRH_OPCODE = (31u << OPCODE_SHIFT | 219u << 1), // X-FORM 454 BRW_OPCODE = (31u << OPCODE_SHIFT | 155u << 1), // X-FORM 455 BRD_OPCODE = (31u << OPCODE_SHIFT | 187u << 1), // X-FORM 456 457 // opcodes only used for floating arithmetic 458 FADD_OPCODE = (63u << OPCODE_SHIFT | 21u << 1), 459 FADDS_OPCODE = (59u << OPCODE_SHIFT | 21u << 1), 460 FCMPU_OPCODE = (63u << OPCODE_SHIFT | 00u << 1), 461 FDIV_OPCODE = (63u << OPCODE_SHIFT | 18u << 1), 462 FDIVS_OPCODE = (59u << OPCODE_SHIFT | 18u << 1), 463 FMR_OPCODE = (63u << OPCODE_SHIFT | 72u << 1), 464 FRIN_OPCODE = (63u << OPCODE_SHIFT | 392u << 1), 465 FRIP_OPCODE = (63u << OPCODE_SHIFT | 456u << 1), 466 FRIM_OPCODE = (63u << OPCODE_SHIFT | 488u << 1), 467 // These are special Power6 opcodes, reused for "lfdepx" and "stfdepx" 468 // on Power7. Do not use. 469 // MFFGPR_OPCODE = (31u << OPCODE_SHIFT | 607u << 1), 470 // MFTGPR_OPCODE = (31u << OPCODE_SHIFT | 735u << 1), 471 CMPB_OPCODE = (31u << OPCODE_SHIFT | 508 << 1), 472 POPCNTB_OPCODE = (31u << OPCODE_SHIFT | 122 << 1), 473 POPCNTW_OPCODE = (31u << OPCODE_SHIFT | 378 << 1), 474 POPCNTD_OPCODE = (31u << OPCODE_SHIFT | 506 << 1), 475 FABS_OPCODE = (63u << OPCODE_SHIFT | 264u << 1), 476 FNABS_OPCODE = (63u << OPCODE_SHIFT | 136u << 1), 477 FMUL_OPCODE = (63u << OPCODE_SHIFT | 25u << 1), 478 FMULS_OPCODE = (59u << OPCODE_SHIFT | 25u << 1), 479 FNEG_OPCODE = (63u << OPCODE_SHIFT | 40u << 1), 480 FSUB_OPCODE = (63u << OPCODE_SHIFT | 20u << 1), 481 FSUBS_OPCODE = (59u << OPCODE_SHIFT | 20u << 1), 482 483 // PPC64-internal FPU conversion opcodes 484 FCFID_OPCODE = (63u << OPCODE_SHIFT | 846u << 1), 485 FCFIDS_OPCODE = (59u << OPCODE_SHIFT | 846u << 1), 486 FCTID_OPCODE = (63u << OPCODE_SHIFT | 814u << 1), 487 FCTIDZ_OPCODE = (63u << OPCODE_SHIFT | 815u << 1), 488 FCTIW_OPCODE = (63u << OPCODE_SHIFT | 14u << 1), 489 FCTIWZ_OPCODE = (63u << OPCODE_SHIFT | 15u << 1), 490 FRSP_OPCODE = (63u << OPCODE_SHIFT | 12u << 1), 491 492 // Fused multiply-accumulate instructions. 493 FMADD_OPCODE = (63u << OPCODE_SHIFT | 29u << 1), 494 FMADDS_OPCODE = (59u << OPCODE_SHIFT | 29u << 1), 495 FMSUB_OPCODE = (63u << OPCODE_SHIFT | 28u << 1), 496 FMSUBS_OPCODE = (59u << OPCODE_SHIFT | 28u << 1), 497 FNMADD_OPCODE = (63u << OPCODE_SHIFT | 31u << 1), 498 FNMADDS_OPCODE = (59u << OPCODE_SHIFT | 31u << 1), 499 FNMSUB_OPCODE = (63u << OPCODE_SHIFT | 30u << 1), 500 FNMSUBS_OPCODE = (59u << OPCODE_SHIFT | 30u << 1), 501 502 LFD_OPCODE = (50u << OPCODE_SHIFT | 00u << 1), 503 LFDU_OPCODE = (51u << OPCODE_SHIFT | 00u << 1), 504 LFDX_OPCODE = (31u << OPCODE_SHIFT | 599u << 1), 505 LFS_OPCODE = (48u << OPCODE_SHIFT | 00u << 1), 506 LFSU_OPCODE = (49u << OPCODE_SHIFT | 00u << 1), 507 LFSX_OPCODE = (31u << OPCODE_SHIFT | 535u << 1), 508 509 STFD_OPCODE = (54u << OPCODE_SHIFT | 00u << 1), 510 STFDU_OPCODE = (55u << OPCODE_SHIFT | 00u << 1), 511 STFDX_OPCODE = (31u << OPCODE_SHIFT | 727u << 1), 512 STFS_OPCODE = (52u << OPCODE_SHIFT | 00u << 1), 513 STFSU_OPCODE = (53u << OPCODE_SHIFT | 00u << 1), 514 STFSX_OPCODE = (31u << OPCODE_SHIFT | 663u << 1), 515 516 FSQRT_OPCODE = (63u << OPCODE_SHIFT | 22u << 1), // A-FORM 517 FSQRTS_OPCODE = (59u << OPCODE_SHIFT | 22u << 1), // A-FORM 518 519 // Vector instruction support for >= Power6 520 // Vector Storage Access 521 LVEBX_OPCODE = (31u << OPCODE_SHIFT | 7u << 1), 522 LVEHX_OPCODE = (31u << OPCODE_SHIFT | 39u << 1), 523 LVEWX_OPCODE = (31u << OPCODE_SHIFT | 71u << 1), 524 LVX_OPCODE = (31u << OPCODE_SHIFT | 103u << 1), 525 LVXL_OPCODE = (31u << OPCODE_SHIFT | 359u << 1), 526 STVEBX_OPCODE = (31u << OPCODE_SHIFT | 135u << 1), 527 STVEHX_OPCODE = (31u << OPCODE_SHIFT | 167u << 1), 528 STVEWX_OPCODE = (31u << OPCODE_SHIFT | 199u << 1), 529 STVX_OPCODE = (31u << OPCODE_SHIFT | 231u << 1), 530 STVXL_OPCODE = (31u << OPCODE_SHIFT | 487u << 1), 531 LVSL_OPCODE = (31u << OPCODE_SHIFT | 6u << 1), 532 LVSR_OPCODE = (31u << OPCODE_SHIFT | 38u << 1), 533 534 // Vector-Scalar (VSX) instruction support. 535 LXV_OPCODE = (61u << OPCODE_SHIFT | 1u ), 536 LXVL_OPCODE = (31u << OPCODE_SHIFT | 269u << 1), 537 STXV_OPCODE = (61u << OPCODE_SHIFT | 5u ), 538 STXVL_OPCODE = (31u << OPCODE_SHIFT | 397u << 1), 539 LXVD2X_OPCODE = (31u << OPCODE_SHIFT | 844u << 1), 540 STXVD2X_OPCODE = (31u << OPCODE_SHIFT | 972u << 1), 541 MTVSRD_OPCODE = (31u << OPCODE_SHIFT | 179u << 1), 542 MTVSRDD_OPCODE = (31u << OPCODE_SHIFT | 435u << 1), 543 MTVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 243u << 1), 544 MFVSRD_OPCODE = (31u << OPCODE_SHIFT | 51u << 1), 545 MTVSRWA_OPCODE = (31u << OPCODE_SHIFT | 211u << 1), 546 MFVSRWZ_OPCODE = (31u << OPCODE_SHIFT | 115u << 1), 547 XXPERMDI_OPCODE= (60u << OPCODE_SHIFT | 10u << 3), 548 XXMRGHW_OPCODE = (60u << OPCODE_SHIFT | 18u << 3), 549 XXMRGLW_OPCODE = (60u << OPCODE_SHIFT | 50u << 3), 550 XXSPLTW_OPCODE = (60u << OPCODE_SHIFT | 164u << 2), 551 XXLAND_OPCODE = (60u << OPCODE_SHIFT | 130u << 3), 552 XXLOR_OPCODE = (60u << OPCODE_SHIFT | 146u << 3), 553 XXLXOR_OPCODE = (60u << OPCODE_SHIFT | 154u << 3), 554 XXLEQV_OPCODE = (60u << OPCODE_SHIFT | 186u << 3), 555 XVDIVSP_OPCODE = (60u << OPCODE_SHIFT | 88u << 3), 556 XXBRD_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 23u << 16), // XX2-FORM 557 XXBRW_OPCODE = (60u << OPCODE_SHIFT | 475u << 2 | 15u << 16), // XX2-FORM 558 XXPERM_OPCODE = (60u << OPCODE_SHIFT | 26u << 3), 559 XXSEL_OPCODE = (60u << OPCODE_SHIFT | 3u << 4), 560 XXSPLTIB_OPCODE= (60u << OPCODE_SHIFT | 360u << 1), 561 XVDIVDP_OPCODE = (60u << OPCODE_SHIFT | 120u << 3), 562 XVABSSP_OPCODE = (60u << OPCODE_SHIFT | 409u << 2), 563 XVABSDP_OPCODE = (60u << OPCODE_SHIFT | 473u << 2), 564 XVNEGSP_OPCODE = (60u << OPCODE_SHIFT | 441u << 2), 565 XVNEGDP_OPCODE = (60u << OPCODE_SHIFT | 505u << 2), 566 XVSQRTSP_OPCODE= (60u << OPCODE_SHIFT | 139u << 2), 567 XVSQRTDP_OPCODE= (60u << OPCODE_SHIFT | 203u << 2), 568 XSCVDPSPN_OPCODE=(60u << OPCODE_SHIFT | 267u << 2), 569 XVADDDP_OPCODE = (60u << OPCODE_SHIFT | 96u << 3), 570 XVSUBDP_OPCODE = (60u << OPCODE_SHIFT | 104u << 3), 571 XVMULSP_OPCODE = (60u << OPCODE_SHIFT | 80u << 3), 572 XVMULDP_OPCODE = (60u << OPCODE_SHIFT | 112u << 3), 573 XVMADDASP_OPCODE=(60u << OPCODE_SHIFT | 65u << 3), 574 XVMADDADP_OPCODE=(60u << OPCODE_SHIFT | 97u << 3), 575 XVMSUBASP_OPCODE=(60u << OPCODE_SHIFT | 81u << 3), 576 XVMSUBADP_OPCODE=(60u << OPCODE_SHIFT | 113u << 3), 577 XVNMSUBASP_OPCODE=(60u<< OPCODE_SHIFT | 209u << 3), 578 XVNMSUBADP_OPCODE=(60u<< OPCODE_SHIFT | 241u << 3), 579 XVRDPI_OPCODE = (60u << OPCODE_SHIFT | 201u << 2), 580 XVRDPIC_OPCODE = (60u << OPCODE_SHIFT | 235u << 2), 581 XVRDPIM_OPCODE = (60u << OPCODE_SHIFT | 249u << 2), 582 XVRDPIP_OPCODE = (60u << OPCODE_SHIFT | 233u << 2), 583 584 // Deliver A Random Number (introduced with POWER9) 585 DARN_OPCODE = (31u << OPCODE_SHIFT | 755u << 1), 586 587 // Vector Permute and Formatting 588 VPKPX_OPCODE = (4u << OPCODE_SHIFT | 782u ), 589 VPKSHSS_OPCODE = (4u << OPCODE_SHIFT | 398u ), 590 VPKSWSS_OPCODE = (4u << OPCODE_SHIFT | 462u ), 591 VPKSHUS_OPCODE = (4u << OPCODE_SHIFT | 270u ), 592 VPKSWUS_OPCODE = (4u << OPCODE_SHIFT | 334u ), 593 VPKUHUM_OPCODE = (4u << OPCODE_SHIFT | 14u ), 594 VPKUWUM_OPCODE = (4u << OPCODE_SHIFT | 78u ), 595 VPKUHUS_OPCODE = (4u << OPCODE_SHIFT | 142u ), 596 VPKUWUS_OPCODE = (4u << OPCODE_SHIFT | 206u ), 597 VUPKHPX_OPCODE = (4u << OPCODE_SHIFT | 846u ), 598 VUPKHSB_OPCODE = (4u << OPCODE_SHIFT | 526u ), 599 VUPKHSH_OPCODE = (4u << OPCODE_SHIFT | 590u ), 600 VUPKLPX_OPCODE = (4u << OPCODE_SHIFT | 974u ), 601 VUPKLSB_OPCODE = (4u << OPCODE_SHIFT | 654u ), 602 VUPKLSH_OPCODE = (4u << OPCODE_SHIFT | 718u ), 603 604 VMRGHB_OPCODE = (4u << OPCODE_SHIFT | 12u ), 605 VMRGHW_OPCODE = (4u << OPCODE_SHIFT | 140u ), 606 VMRGHH_OPCODE = (4u << OPCODE_SHIFT | 76u ), 607 VMRGLB_OPCODE = (4u << OPCODE_SHIFT | 268u ), 608 VMRGLW_OPCODE = (4u << OPCODE_SHIFT | 396u ), 609 VMRGLH_OPCODE = (4u << OPCODE_SHIFT | 332u ), 610 611 VSPLT_OPCODE = (4u << OPCODE_SHIFT | 524u ), 612 VSPLTH_OPCODE = (4u << OPCODE_SHIFT | 588u ), 613 VSPLTW_OPCODE = (4u << OPCODE_SHIFT | 652u ), 614 VSPLTISB_OPCODE= (4u << OPCODE_SHIFT | 780u ), 615 VSPLTISH_OPCODE= (4u << OPCODE_SHIFT | 844u ), 616 VSPLTISW_OPCODE= (4u << OPCODE_SHIFT | 908u ), 617 618 VPEXTD_OPCODE = (4u << OPCODE_SHIFT | 1421u ), 619 VPERM_OPCODE = (4u << OPCODE_SHIFT | 43u ), 620 VSEL_OPCODE = (4u << OPCODE_SHIFT | 42u ), 621 622 VSL_OPCODE = (4u << OPCODE_SHIFT | 452u ), 623 VSLDOI_OPCODE = (4u << OPCODE_SHIFT | 44u ), 624 VSLO_OPCODE = (4u << OPCODE_SHIFT | 1036u ), 625 VSR_OPCODE = (4u << OPCODE_SHIFT | 708u ), 626 VSRO_OPCODE = (4u << OPCODE_SHIFT | 1100u ), 627 628 // Vector Integer 629 VADDCUW_OPCODE = (4u << OPCODE_SHIFT | 384u ), 630 VADDSHS_OPCODE = (4u << OPCODE_SHIFT | 832u ), 631 VADDSBS_OPCODE = (4u << OPCODE_SHIFT | 768u ), 632 VADDSWS_OPCODE = (4u << OPCODE_SHIFT | 896u ), 633 VADDUBM_OPCODE = (4u << OPCODE_SHIFT | 0u ), 634 VADDUWM_OPCODE = (4u << OPCODE_SHIFT | 128u ), 635 VADDUHM_OPCODE = (4u << OPCODE_SHIFT | 64u ), 636 VADDUDM_OPCODE = (4u << OPCODE_SHIFT | 192u ), 637 VADDUBS_OPCODE = (4u << OPCODE_SHIFT | 512u ), 638 VADDUWS_OPCODE = (4u << OPCODE_SHIFT | 640u ), 639 VADDUHS_OPCODE = (4u << OPCODE_SHIFT | 576u ), 640 VADDFP_OPCODE = (4u << OPCODE_SHIFT | 10u ), 641 VSUBCUW_OPCODE = (4u << OPCODE_SHIFT | 1408u ), 642 VSUBSHS_OPCODE = (4u << OPCODE_SHIFT | 1856u ), 643 VSUBSBS_OPCODE = (4u << OPCODE_SHIFT | 1792u ), 644 VSUBSWS_OPCODE = (4u << OPCODE_SHIFT | 1920u ), 645 VSUBUBM_OPCODE = (4u << OPCODE_SHIFT | 1024u ), 646 VSUBUWM_OPCODE = (4u << OPCODE_SHIFT | 1152u ), 647 VSUBUHM_OPCODE = (4u << OPCODE_SHIFT | 1088u ), 648 VSUBUDM_OPCODE = (4u << OPCODE_SHIFT | 1216u ), 649 VSUBUBS_OPCODE = (4u << OPCODE_SHIFT | 1536u ), 650 VSUBUWS_OPCODE = (4u << OPCODE_SHIFT | 1664u ), 651 VSUBUHS_OPCODE = (4u << OPCODE_SHIFT | 1600u ), 652 VSUBFP_OPCODE = (4u << OPCODE_SHIFT | 74u ), 653 654 VMULESB_OPCODE = (4u << OPCODE_SHIFT | 776u ), 655 VMULEUB_OPCODE = (4u << OPCODE_SHIFT | 520u ), 656 VMULESH_OPCODE = (4u << OPCODE_SHIFT | 840u ), 657 VMULEUH_OPCODE = (4u << OPCODE_SHIFT | 584u ), 658 VMULOSB_OPCODE = (4u << OPCODE_SHIFT | 264u ), 659 VMULOUB_OPCODE = (4u << OPCODE_SHIFT | 8u ), 660 VMULOSH_OPCODE = (4u << OPCODE_SHIFT | 328u ), 661 VMULOSW_OPCODE = (4u << OPCODE_SHIFT | 392u ), 662 VMULOUH_OPCODE = (4u << OPCODE_SHIFT | 72u ), 663 VMULUWM_OPCODE = (4u << OPCODE_SHIFT | 137u ), 664 VMHADDSHS_OPCODE=(4u << OPCODE_SHIFT | 32u ), 665 VMHRADDSHS_OPCODE=(4u << OPCODE_SHIFT | 33u ), 666 VMLADDUHM_OPCODE=(4u << OPCODE_SHIFT | 34u ), 667 VMSUBUHM_OPCODE= (4u << OPCODE_SHIFT | 36u ), 668 VMSUMMBM_OPCODE= (4u << OPCODE_SHIFT | 37u ), 669 VMSUMSHM_OPCODE= (4u << OPCODE_SHIFT | 40u ), 670 VMSUMSHS_OPCODE= (4u << OPCODE_SHIFT | 41u ), 671 VMSUMUHM_OPCODE= (4u << OPCODE_SHIFT | 38u ), 672 VMSUMUHS_OPCODE= (4u << OPCODE_SHIFT | 39u ), 673 VMADDFP_OPCODE = (4u << OPCODE_SHIFT | 46u ), 674 675 VSUMSWS_OPCODE = (4u << OPCODE_SHIFT | 1928u ), 676 VSUM2SWS_OPCODE= (4u << OPCODE_SHIFT | 1672u ), 677 VSUM4SBS_OPCODE= (4u << OPCODE_SHIFT | 1800u ), 678 VSUM4UBS_OPCODE= (4u << OPCODE_SHIFT | 1544u ), 679 VSUM4SHS_OPCODE= (4u << OPCODE_SHIFT | 1608u ), 680 681 VAVGSB_OPCODE = (4u << OPCODE_SHIFT | 1282u ), 682 VAVGSW_OPCODE = (4u << OPCODE_SHIFT | 1410u ), 683 VAVGSH_OPCODE = (4u << OPCODE_SHIFT | 1346u ), 684 VAVGUB_OPCODE = (4u << OPCODE_SHIFT | 1026u ), 685 VAVGUW_OPCODE = (4u << OPCODE_SHIFT | 1154u ), 686 VAVGUH_OPCODE = (4u << OPCODE_SHIFT | 1090u ), 687 688 VMAXSB_OPCODE = (4u << OPCODE_SHIFT | 258u ), 689 VMAXSW_OPCODE = (4u << OPCODE_SHIFT | 386u ), 690 VMAXSH_OPCODE = (4u << OPCODE_SHIFT | 322u ), 691 VMAXUB_OPCODE = (4u << OPCODE_SHIFT | 2u ), 692 VMAXUW_OPCODE = (4u << OPCODE_SHIFT | 130u ), 693 VMAXUH_OPCODE = (4u << OPCODE_SHIFT | 66u ), 694 VMINSB_OPCODE = (4u << OPCODE_SHIFT | 770u ), 695 VMINSW_OPCODE = (4u << OPCODE_SHIFT | 898u ), 696 VMINSH_OPCODE = (4u << OPCODE_SHIFT | 834u ), 697 VMINUB_OPCODE = (4u << OPCODE_SHIFT | 514u ), 698 VMINUW_OPCODE = (4u << OPCODE_SHIFT | 642u ), 699 VMINUH_OPCODE = (4u << OPCODE_SHIFT | 578u ), 700 701 VCMPEQUB_OPCODE= (4u << OPCODE_SHIFT | 6u ), 702 VCMPEQUH_OPCODE= (4u << OPCODE_SHIFT | 70u ), 703 VCMPEQUW_OPCODE= (4u << OPCODE_SHIFT | 134u ), 704 VCMPGTSH_OPCODE= (4u << OPCODE_SHIFT | 838u ), 705 VCMPGTSB_OPCODE= (4u << OPCODE_SHIFT | 774u ), 706 VCMPGTSW_OPCODE= (4u << OPCODE_SHIFT | 902u ), 707 VCMPGTUB_OPCODE= (4u << OPCODE_SHIFT | 518u ), 708 VCMPGTUH_OPCODE= (4u << OPCODE_SHIFT | 582u ), 709 VCMPGTUW_OPCODE= (4u << OPCODE_SHIFT | 646u ), 710 711 VAND_OPCODE = (4u << OPCODE_SHIFT | 1028u ), 712 VANDC_OPCODE = (4u << OPCODE_SHIFT | 1092u ), 713 VNOR_OPCODE = (4u << OPCODE_SHIFT | 1284u ), 714 VOR_OPCODE = (4u << OPCODE_SHIFT | 1156u ), 715 VXOR_OPCODE = (4u << OPCODE_SHIFT | 1220u ), 716 VRLD_OPCODE = (4u << OPCODE_SHIFT | 196u ), 717 VRLB_OPCODE = (4u << OPCODE_SHIFT | 4u ), 718 VRLW_OPCODE = (4u << OPCODE_SHIFT | 132u ), 719 VRLH_OPCODE = (4u << OPCODE_SHIFT | 68u ), 720 VSLB_OPCODE = (4u << OPCODE_SHIFT | 260u ), 721 VSKW_OPCODE = (4u << OPCODE_SHIFT | 388u ), 722 VSLH_OPCODE = (4u << OPCODE_SHIFT | 324u ), 723 VSRB_OPCODE = (4u << OPCODE_SHIFT | 516u ), 724 VSRW_OPCODE = (4u << OPCODE_SHIFT | 644u ), 725 VSRH_OPCODE = (4u << OPCODE_SHIFT | 580u ), 726 VSRAB_OPCODE = (4u << OPCODE_SHIFT | 772u ), 727 VSRAW_OPCODE = (4u << OPCODE_SHIFT | 900u ), 728 VSRAH_OPCODE = (4u << OPCODE_SHIFT | 836u ), 729 VPOPCNTB_OPCODE= (4u << OPCODE_SHIFT | 1795u ), 730 VPOPCNTH_OPCODE= (4u << OPCODE_SHIFT | 1859u ), 731 VPOPCNTW_OPCODE= (4u << OPCODE_SHIFT | 1923u ), 732 VPOPCNTD_OPCODE= (4u << OPCODE_SHIFT | 1987u ), 733 734 // Vector Floating-Point 735 // not implemented yet 736 737 // Vector Status and Control 738 MTVSCR_OPCODE = (4u << OPCODE_SHIFT | 1604u ), 739 MFVSCR_OPCODE = (4u << OPCODE_SHIFT | 1540u ), 740 741 // AES (introduced with Power 8) 742 VCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1288u), 743 VCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1289u), 744 VNCIPHER_OPCODE = (4u << OPCODE_SHIFT | 1352u), 745 VNCIPHERLAST_OPCODE = (4u << OPCODE_SHIFT | 1353u), 746 VSBOX_OPCODE = (4u << OPCODE_SHIFT | 1480u), 747 748 // SHA (introduced with Power 8) 749 VSHASIGMAD_OPCODE = (4u << OPCODE_SHIFT | 1730u), 750 VSHASIGMAW_OPCODE = (4u << OPCODE_SHIFT | 1666u), 751 752 // Vector Binary Polynomial Multiplication (introduced with Power 8) 753 VPMSUMB_OPCODE = (4u << OPCODE_SHIFT | 1032u), 754 VPMSUMD_OPCODE = (4u << OPCODE_SHIFT | 1224u), 755 VPMSUMH_OPCODE = (4u << OPCODE_SHIFT | 1096u), 756 VPMSUMW_OPCODE = (4u << OPCODE_SHIFT | 1160u), 757 758 // Vector Permute and Xor (introduced with Power 8) 759 VPERMXOR_OPCODE = (4u << OPCODE_SHIFT | 45u), 760 761 // Icache and dcache related instructions 762 DCBA_OPCODE = (31u << OPCODE_SHIFT | 758u << 1), 763 DCBZ_OPCODE = (31u << OPCODE_SHIFT | 1014u << 1), 764 DCBST_OPCODE = (31u << OPCODE_SHIFT | 54u << 1), 765 DCBF_OPCODE = (31u << OPCODE_SHIFT | 86u << 1), 766 767 DCBT_OPCODE = (31u << OPCODE_SHIFT | 278u << 1), 768 DCBTST_OPCODE = (31u << OPCODE_SHIFT | 246u << 1), 769 ICBI_OPCODE = (31u << OPCODE_SHIFT | 982u << 1), 770 771 // Instruction synchronization 772 ISYNC_OPCODE = (19u << OPCODE_SHIFT | 150u << 1), 773 // Memory barriers 774 SYNC_OPCODE = (31u << OPCODE_SHIFT | 598u << 1), 775 EIEIO_OPCODE = (31u << OPCODE_SHIFT | 854u << 1), 776 777 // Wait instructions for polling. 778 WAIT_OPCODE = (31u << OPCODE_SHIFT | 62u << 1), 779 780 // Trap instructions 781 TDI_OPCODE = (2u << OPCODE_SHIFT), 782 TWI_OPCODE = (3u << OPCODE_SHIFT), 783 TD_OPCODE = (31u << OPCODE_SHIFT | 68u << 1), 784 TW_OPCODE = (31u << OPCODE_SHIFT | 4u << 1), 785 786 // Atomics. 787 LBARX_OPCODE = (31u << OPCODE_SHIFT | 52u << 1), 788 LHARX_OPCODE = (31u << OPCODE_SHIFT | 116u << 1), 789 LWARX_OPCODE = (31u << OPCODE_SHIFT | 20u << 1), 790 LDARX_OPCODE = (31u << OPCODE_SHIFT | 84u << 1), 791 LQARX_OPCODE = (31u << OPCODE_SHIFT | 276u << 1), 792 STBCX_OPCODE = (31u << OPCODE_SHIFT | 694u << 1), 793 STHCX_OPCODE = (31u << OPCODE_SHIFT | 726u << 1), 794 STWCX_OPCODE = (31u << OPCODE_SHIFT | 150u << 1), 795 STDCX_OPCODE = (31u << OPCODE_SHIFT | 214u << 1), 796 STQCX_OPCODE = (31u << OPCODE_SHIFT | 182u << 1) 797 798 }; 799 800 enum opcdeos_mask { 801 // Mask for prefix primary opcode field 802 PREFIX_OPCODE_MASK = (63u << OPCODE_SHIFT), 803 // Mask for prefix opcode and type fields 804 PREFIX_OPCODE_TYPE_MASK = (63u << OPCODE_SHIFT) | (3u << PRE_TYPE_SHIFT), 805 // Masks for type 00/10 and type 01/11, including opcode, type, and st fieds 806 PREFIX_OPCODE_TYPEx0_MASK = PREFIX_OPCODE_TYPE_MASK | ( 1u << PRE_ST1_SHIFT), 807 PREFIX_OPCODE_TYPEx1_MASK = PREFIX_OPCODE_TYPE_MASK | (15u << PRE_ST4_SHIFT), 808 809 // Masks for each instructions 810 PADDI_PREFIX_OPCODE_MASK = PREFIX_OPCODE_TYPEx0_MASK, 811 PADDI_SUFFIX_OPCODE_MASK = ADDI_OPCODE_MASK, 812 }; 813 814 enum opcdeos { 815 PREFIX_PRIMARY_OPCODE = (1u << OPCODE_SHIFT), 816 817 // Prefixed addi/li 818 PADDI_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (2u << PRE_TYPE_SHIFT), 819 PADDI_SUFFIX_OPCODE = ADDI_OPCODE, 820 821 // xxpermx 822 XXPERMX_PREFIX_OPCODE = PREFIX_PRIMARY_OPCODE | (1u << PRE_TYPE_SHIFT), 823 XXPERMX_SUFFIX_OPCODE = (34u << OPCODE_SHIFT), 824 }; 825 826 // Trap instructions TO bits 827 enum trap_to_bits { 828 // single bits 829 traptoLessThanSigned = 1 << 4, // 0, left end 830 traptoGreaterThanSigned = 1 << 3, 831 traptoEqual = 1 << 2, 832 traptoLessThanUnsigned = 1 << 1, 833 traptoGreaterThanUnsigned = 1 << 0, // 4, right end 834 835 // compound ones 836 traptoUnconditional = (traptoLessThanSigned | 837 traptoGreaterThanSigned | 838 traptoEqual | 839 traptoLessThanUnsigned | 840 traptoGreaterThanUnsigned) 841 }; 842 843 // Branch hints BH field 844 enum branch_hint_bh { 845 // bclr cases: 846 bhintbhBCLRisReturn = 0, 847 bhintbhBCLRisNotReturnButSame = 1, 848 bhintbhBCLRisNotPredictable = 3, 849 850 // bcctr cases: 851 bhintbhBCCTRisNotReturnButSame = 0, 852 bhintbhBCCTRisNotPredictable = 3 853 }; 854 855 // Branch prediction hints AT field 856 enum branch_hint_at { 857 bhintatNoHint = 0, // at=00 858 bhintatIsNotTaken = 2, // at=10 859 bhintatIsTaken = 3 // at=11 860 }; 861 862 // Branch prediction hints 863 enum branch_hint_concept { 864 // Use the same encoding as branch_hint_at to simply code. 865 bhintNoHint = bhintatNoHint, 866 bhintIsNotTaken = bhintatIsNotTaken, 867 bhintIsTaken = bhintatIsTaken 868 }; 869 870 // Used in BO field of branch instruction. 871 enum branch_condition { 872 bcondCRbiIs0 = 4, // bo=001at 873 bcondCRbiIs1 = 12, // bo=011at 874 bcondAlways = 20 // bo=10100 875 }; 876 877 // Branch condition with combined prediction hints. 878 enum branch_condition_with_hint { 879 bcondCRbiIs0_bhintNoHint = bcondCRbiIs0 | bhintatNoHint, 880 bcondCRbiIs0_bhintIsNotTaken = bcondCRbiIs0 | bhintatIsNotTaken, 881 bcondCRbiIs0_bhintIsTaken = bcondCRbiIs0 | bhintatIsTaken, 882 bcondCRbiIs1_bhintNoHint = bcondCRbiIs1 | bhintatNoHint, 883 bcondCRbiIs1_bhintIsNotTaken = bcondCRbiIs1 | bhintatIsNotTaken, 884 bcondCRbiIs1_bhintIsTaken = bcondCRbiIs1 | bhintatIsTaken, 885 }; 886 887 // Elemental Memory Barriers (>=Power 8) 888 enum Elemental_Membar_mask_bits { 889 StoreStore = 1 << 0, 890 StoreLoad = 1 << 1, 891 LoadStore = 1 << 2, 892 LoadLoad = 1 << 3 893 }; 894 895 // Branch prediction hints. 896 inline static int add_bhint_to_boint(const int bhint, const int boint) { 897 switch (boint) { 898 case bcondCRbiIs0: 899 case bcondCRbiIs1: 900 // branch_hint and branch_hint_at have same encodings 901 assert( (int)bhintNoHint == (int)bhintatNoHint 902 && (int)bhintIsNotTaken == (int)bhintatIsNotTaken 903 && (int)bhintIsTaken == (int)bhintatIsTaken, 904 "wrong encodings"); 905 assert((bhint & 0x03) == bhint, "wrong encodings"); 906 return (boint & ~0x03) | bhint; 907 case bcondAlways: 908 // no branch_hint 909 return boint; 910 default: 911 ShouldNotReachHere(); 912 return 0; 913 } 914 } 915 916 // Extract bcond from boint. 917 inline static int inv_boint_bcond(const int boint) { 918 int r_bcond = boint & ~0x03; 919 assert(r_bcond == bcondCRbiIs0 || 920 r_bcond == bcondCRbiIs1 || 921 r_bcond == bcondAlways, 922 "bad branch condition"); 923 return r_bcond; 924 } 925 926 // Extract bhint from boint. 927 inline static int inv_boint_bhint(const int boint) { 928 int r_bhint = boint & 0x03; 929 assert(r_bhint == bhintatNoHint || 930 r_bhint == bhintatIsNotTaken || 931 r_bhint == bhintatIsTaken, 932 "bad branch hint"); 933 return r_bhint; 934 } 935 936 // Calculate opposite of given bcond. 937 inline static int opposite_bcond(const int bcond) { 938 switch (bcond) { 939 case bcondCRbiIs0: 940 return bcondCRbiIs1; 941 case bcondCRbiIs1: 942 return bcondCRbiIs0; 943 default: 944 ShouldNotReachHere(); 945 return 0; 946 } 947 } 948 949 // Calculate opposite of given bhint. 950 inline static int opposite_bhint(const int bhint) { 951 switch (bhint) { 952 case bhintatNoHint: 953 return bhintatNoHint; 954 case bhintatIsNotTaken: 955 return bhintatIsTaken; 956 case bhintatIsTaken: 957 return bhintatIsNotTaken; 958 default: 959 ShouldNotReachHere(); 960 return 0; 961 } 962 } 963 964 // PPC branch instructions 965 enum ppcops { 966 b_op = 18, 967 bc_op = 16, 968 bcr_op = 19 969 }; 970 971 enum Condition { 972 negative = 0, 973 less = 0, 974 positive = 1, 975 greater = 1, 976 zero = 2, 977 equal = 2, 978 summary_overflow = 3, 979 }; 980 981 public: 982 // Helper functions for groups of instructions 983 984 enum Predict { pt = 1, pn = 0 }; // pt = predict taken 985 986 //---< calculate length of instruction >--- 987 // With PPC64 being a RISC architecture, this always is BytesPerInstWord 988 // instruction must start at passed address 989 static unsigned int instr_len(unsigned char *instr) { return BytesPerInstWord; } 990 991 //---< longest instructions >--- 992 static unsigned int instr_maxlen() { return BytesPerInstWord; } 993 994 // Test if x is within signed immediate range for nbits. 995 static bool is_simm(int x, unsigned int nbits) { 996 assert(0 < nbits && nbits < 32, "out of bounds"); 997 const int min = -(((int)1) << (nbits-1)); 998 const int maxplus1 = (((int)1) << (nbits-1)); 999 return min <= x && x < maxplus1; 1000 } 1001 1002 static bool is_simm(jlong x, unsigned int nbits) { 1003 assert(0 < nbits && nbits < 64, "out of bounds"); 1004 const jlong min = -(((jlong)1) << (nbits-1)); 1005 const jlong maxplus1 = (((jlong)1) << (nbits-1)); 1006 return min <= x && x < maxplus1; 1007 } 1008 1009 // Test if x is within unsigned immediate range for nbits. 1010 static bool is_uimm(int x, unsigned int nbits) { 1011 assert(0 < nbits && nbits < 32, "out of bounds"); 1012 const unsigned int maxplus1 = (((unsigned int)1) << nbits); 1013 return (unsigned int)x < maxplus1; 1014 } 1015 1016 static bool is_uimm(jlong x, unsigned int nbits) { 1017 assert(0 < nbits && nbits < 64, "out of bounds"); 1018 const julong maxplus1 = (((julong)1) << nbits); 1019 return (julong)x < maxplus1; 1020 } 1021 1022 protected: 1023 // helpers 1024 1025 // X is supposed to fit in a field "nbits" wide 1026 // and be sign-extended. Check the range. 1027 static void assert_signed_range(intptr_t x, int nbits) { 1028 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))), 1029 "value out of range"); 1030 } 1031 1032 static void assert_signed_word_disp_range(intptr_t x, int nbits) { 1033 assert((x & 3) == 0, "not word aligned"); 1034 assert_signed_range(x, nbits + 2); 1035 } 1036 1037 static void assert_unsigned_const(int x, int nbits) { 1038 assert(juint(x) < juint(1 << nbits), "unsigned constant out of range"); 1039 } 1040 1041 static int fmask(juint hi_bit, juint lo_bit) { 1042 assert(hi_bit >= lo_bit && hi_bit < 32, "bad bits"); 1043 return (1 << ( hi_bit-lo_bit + 1 )) - 1; 1044 } 1045 1046 // inverse of u_field 1047 static int inv_u_field(int x, int hi_bit, int lo_bit) { 1048 juint r = juint(x) >> lo_bit; 1049 r &= fmask(hi_bit, lo_bit); 1050 return int(r); 1051 } 1052 1053 // signed version: extract from field and sign-extend 1054 static int inv_s_field_ppc(int x, int hi_bit, int lo_bit) { 1055 x = x << (31-hi_bit); 1056 x = x >> (31-hi_bit+lo_bit); 1057 return x; 1058 } 1059 1060 static int u_field(int x, int hi_bit, int lo_bit) { 1061 assert((x & ~fmask(hi_bit, lo_bit)) == 0, "value out of range"); 1062 int r = x << lo_bit; 1063 assert(inv_u_field(r, hi_bit, lo_bit) == x, "just checking"); 1064 return r; 1065 } 1066 1067 // Same as u_field for signed values 1068 static int s_field(int x, int hi_bit, int lo_bit) { 1069 int nbits = hi_bit - lo_bit + 1; 1070 assert(nbits == 32 || (-(1 << (nbits-1)) <= x && x < (1 << (nbits-1))), 1071 "value out of range"); 1072 x &= fmask(hi_bit, lo_bit); 1073 int r = x << lo_bit; 1074 return r; 1075 } 1076 1077 // inv_op for ppc instructions 1078 static int inv_op_ppc(int x) { return inv_u_field(x, 31, 26); } 1079 1080 // Determine target address from li, bd field of branch instruction. 1081 static intptr_t inv_li_field(int x) { 1082 intptr_t r = inv_s_field_ppc(x, 25, 2); 1083 r = (r << 2); 1084 return r; 1085 } 1086 static intptr_t inv_bd_field(int x, intptr_t pos) { 1087 intptr_t r = inv_s_field_ppc(x, 15, 2); 1088 r = (r << 2) + pos; 1089 return r; 1090 } 1091 1092 #define inv_opp_u_field(x, hi_bit, lo_bit) inv_u_field(x, 31-(lo_bit), 31-(hi_bit)) 1093 #define inv_opp_s_field(x, hi_bit, lo_bit) inv_s_field_ppc(x, 31-(lo_bit), 31-(hi_bit)) 1094 // Extract instruction fields from instruction words. 1095 public: 1096 static int inv_ra_field(int x) { return inv_opp_u_field(x, 15, 11); } 1097 static int inv_rb_field(int x) { return inv_opp_u_field(x, 20, 16); } 1098 static int inv_rt_field(int x) { return inv_opp_u_field(x, 10, 6); } 1099 static int inv_rta_field(int x) { return inv_opp_u_field(x, 15, 11); } 1100 static int inv_rs_field(int x) { return inv_opp_u_field(x, 10, 6); } 1101 // Ds uses opp_s_field(x, 31, 16), but lowest 2 bits must be 0. 1102 // Inv_ds_field uses range (x, 29, 16) but shifts by 2 to ensure that lowest bits are 0. 1103 static int inv_ds_field(int x) { return inv_opp_s_field(x, 29, 16) << 2; } 1104 static int inv_d1_field(int x) { return inv_opp_s_field(x, 31, 16); } 1105 static int inv_si_field(int x) { return inv_opp_s_field(x, 31, 16); } 1106 static int inv_to_field(int x) { return inv_opp_u_field(x, 10, 6); } 1107 static int inv_lk_field(int x) { return inv_opp_u_field(x, 31, 31); } 1108 static int inv_bo_field(int x) { return inv_opp_u_field(x, 10, 6); } 1109 static int inv_bi_field(int x) { return inv_opp_u_field(x, 15, 11); } 1110 1111 // For extended opcodes (prefixed instructions) introduced with Power 10 1112 static long inv_r_eo( int x) { return inv_opp_u_field(x, 11, 11); } 1113 static long inv_type( int x) { return inv_opp_u_field(x, 7, 6); } 1114 static long inv_st_x0( int x) { return inv_opp_u_field(x, 8, 8); } 1115 static long inv_st_x1( int x) { return inv_opp_u_field(x, 11, 8); } 1116 1117 // - 8LS:D/MLS:D Formats 1118 static long inv_d0_eo( long x) { return inv_opp_u_field(x, 31, 14); } 1119 1120 // - 8RR:XX4/8RR:D Formats 1121 static long inv_imm0_eo(int x) { return inv_opp_u_field(x, 31, 16); } 1122 static long inv_uimm_eo(int x) { return inv_opp_u_field(x, 31, 29); } 1123 static long inv_imm_eo( int x) { return inv_opp_u_field(x, 31, 24); } 1124 1125 #define opp_u_field(x, hi_bit, lo_bit) u_field(x, 31-(lo_bit), 31-(hi_bit)) 1126 #define opp_s_field(x, hi_bit, lo_bit) s_field(x, 31-(lo_bit), 31-(hi_bit)) 1127 1128 // instruction fields 1129 static int aa( int x) { return opp_u_field(x, 30, 30); } 1130 static int ba( int x) { return opp_u_field(x, 15, 11); } 1131 static int bb( int x) { return opp_u_field(x, 20, 16); } 1132 static int bc( int x) { return opp_u_field(x, 25, 21); } 1133 static int bd( int x) { return opp_s_field(x, 29, 16); } 1134 static int bf( ConditionRegister cr) { return bf(cr->encoding()); } 1135 static int bf( int x) { return opp_u_field(x, 8, 6); } 1136 static int bfa(ConditionRegister cr) { return bfa(cr->encoding()); } 1137 static int bfa( int x) { return opp_u_field(x, 13, 11); } 1138 static int bh( int x) { return opp_u_field(x, 20, 19); } 1139 static int bi( int x) { return opp_u_field(x, 15, 11); } 1140 static int bi0(ConditionRegister cr, Condition c) { return (cr->encoding() << 2) | c; } 1141 static int bo( int x) { return opp_u_field(x, 10, 6); } 1142 static int bt( int x) { return opp_u_field(x, 10, 6); } 1143 static int d1( int x) { return opp_s_field(x, 31, 16); } 1144 static int ds( int x) { assert((x & 0x3) == 0, "unaligned offset"); return opp_s_field(x, 31, 16); } 1145 static int eh( int x) { return opp_u_field(x, 31, 31); } 1146 static int flm( int x) { return opp_u_field(x, 14, 7); } 1147 static int fra( FloatRegister r) { return fra(r->encoding());} 1148 static int frb( FloatRegister r) { return frb(r->encoding());} 1149 static int frc( FloatRegister r) { return frc(r->encoding());} 1150 static int frs( FloatRegister r) { return frs(r->encoding());} 1151 static int frt( FloatRegister r) { return frt(r->encoding());} 1152 static int fra( int x) { return opp_u_field(x, 15, 11); } 1153 static int frb( int x) { return opp_u_field(x, 20, 16); } 1154 static int frc( int x) { return opp_u_field(x, 25, 21); } 1155 static int frs( int x) { return opp_u_field(x, 10, 6); } 1156 static int frt( int x) { return opp_u_field(x, 10, 6); } 1157 static int fxm( int x) { return opp_u_field(x, 19, 12); } 1158 static int imm8( int x) { return opp_u_field(uimm(x, 8), 20, 13); } 1159 static int l10( int x) { assert(x == 0 || x == 1, "must be 0 or 1"); return opp_u_field(x, 10, 10); } 1160 static int l14( int x) { return opp_u_field(x, 15, 14); } 1161 static int l15( int x) { return opp_u_field(x, 15, 15); } 1162 static int l910( int x) { return opp_u_field(x, 10, 9); } 1163 static int e1215( int x) { return opp_u_field(x, 15, 12); } 1164 static int lev( int x) { return opp_u_field(x, 26, 20); } 1165 static int li( int x) { return opp_s_field(x, 29, 6); } 1166 static int lk( int x) { return opp_u_field(x, 31, 31); } 1167 static int mb2125( int x) { return opp_u_field(x, 25, 21); } 1168 static int me2630( int x) { return opp_u_field(x, 30, 26); } 1169 static int mb2126( int x) { return opp_u_field(((x & 0x1f) << 1) | ((x & 0x20) >> 5), 26, 21); } 1170 static int me2126( int x) { return mb2126(x); } 1171 static int nb( int x) { return opp_u_field(x, 20, 16); } 1172 //static int opcd( int x) { return opp_u_field(x, 5, 0); } // is contained in our opcodes 1173 static int oe( int x) { return opp_u_field(x, 21, 21); } 1174 static int ra( Register r) { return ra(r->encoding()); } 1175 static int ra( int x) { return opp_u_field(x, 15, 11); } 1176 static int rb( Register r) { return rb(r->encoding()); } 1177 static int rb( int x) { return opp_u_field(x, 20, 16); } 1178 static int rc( int x) { return opp_u_field(x, 31, 31); } 1179 static int rs( Register r) { return rs(r->encoding()); } 1180 static int rs( int x) { return opp_u_field(x, 10, 6); } 1181 // we don't want to use R0 in memory accesses, because it has value `0' then 1182 static int ra0mem( Register r) { assert(r != R0, "cannot use register R0 in memory access"); return ra(r); } 1183 static int ra0mem( int x) { assert(x != 0, "cannot use register 0 in memory access"); return ra(x); } 1184 1185 // register r is target 1186 static int rt( Register r) { return rs(r); } 1187 static int rt( int x) { return rs(x); } 1188 static int rta( Register r) { return ra(r); } 1189 static int rta0mem( Register r) { rta(r); return ra0mem(r); } 1190 1191 static int sh1620( int x) { return opp_u_field(x, 20, 16); } 1192 static int sh30( int x) { return opp_u_field(x, 30, 30); } 1193 static int sh162030( int x) { return sh1620(x & 0x1f) | sh30((x & 0x20) >> 5); } 1194 static int si( int x) { return opp_s_field(x, 31, 16); } 1195 static int spr( int x) { return opp_u_field(x, 20, 11); } 1196 static int sr( int x) { return opp_u_field(x, 15, 12); } 1197 static int tbr( int x) { return opp_u_field(x, 20, 11); } 1198 static int th( int x) { return opp_u_field(x, 10, 7); } 1199 static int thct( int x) { assert((x&8) == 0, "must be valid cache specification"); return th(x); } 1200 static int thds( int x) { assert((x&8) == 8, "must be valid stream specification"); return th(x); } 1201 static int to( int x) { return opp_u_field(x, 10, 6); } 1202 static int u( int x) { return opp_u_field(x, 19, 16); } 1203 static int ui( int x) { return opp_u_field(x, 31, 16); } 1204 1205 // Support vector instructions for >= Power6. 1206 static int vra( int x) { return opp_u_field(x, 15, 11); } 1207 static int vrb( int x) { return opp_u_field(x, 20, 16); } 1208 static int vrc( int x) { return opp_u_field(x, 25, 21); } 1209 static int vrs( int x) { return opp_u_field(x, 10, 6); } 1210 static int vrt( int x) { return opp_u_field(x, 10, 6); } 1211 1212 static int vra( VectorRegister r) { return vra(r->encoding());} 1213 static int vrb( VectorRegister r) { return vrb(r->encoding());} 1214 static int vrc( VectorRegister r) { return vrc(r->encoding());} 1215 static int vrs( VectorRegister r) { return vrs(r->encoding());} 1216 static int vrt( VectorRegister r) { return vrt(r->encoding());} 1217 1218 // Only used on SHA sigma instructions (VX-form) 1219 static int vst( int x) { return opp_u_field(x, 16, 16); } 1220 static int vsix( int x) { return opp_u_field(x, 20, 17); } 1221 1222 // Support Vector-Scalar (VSX) instructions. 1223 static int vsra( int x) { return opp_u_field(x & 0x1F, 15, 11) | opp_u_field((x & 0x20) >> 5, 29, 29); } 1224 static int vsrb( int x) { return opp_u_field(x & 0x1F, 20, 16) | opp_u_field((x & 0x20) >> 5, 30, 30); } 1225 static int vsrc( int x) { return opp_u_field(x & 0x1F, 25, 21) | opp_u_field((x & 0x20) >> 5, 28, 28); } 1226 static int vsrs( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 31, 31); } 1227 static int vsrt( int x) { return vsrs(x); } 1228 static int vsdm( int x) { return opp_u_field(x, 23, 22); } 1229 static int vsrs_dq( int x) { return opp_u_field(x & 0x1F, 10, 6) | opp_u_field((x & 0x20) >> 5, 28, 28); } 1230 static int vsrt_dq( int x) { return vsrs_dq(x); } 1231 1232 static int vsra( VectorSRegister r) { return vsra(r->encoding());} 1233 static int vsrb( VectorSRegister r) { return vsrb(r->encoding());} 1234 static int vsrc( VectorSRegister r) { return vsrc(r->encoding());} 1235 static int vsrs( VectorSRegister r) { return vsrs(r->encoding());} 1236 static int vsrt( VectorSRegister r) { return vsrt(r->encoding());} 1237 static int vsrs_dq(VectorSRegister r) { return vsrs_dq(r->encoding());} 1238 static int vsrt_dq(VectorSRegister r) { return vsrt_dq(r->encoding());} 1239 1240 static int vsplt_uim( int x) { return opp_u_field(x, 15, 12); } // for vsplt* instructions 1241 static int vsplti_sim(int x) { return opp_u_field(x, 15, 11); } // for vsplti* instructions 1242 static int vsldoi_shb(int x) { return opp_u_field(x, 25, 22); } // for vsldoi instruction 1243 static int vcmp_rc( int x) { return opp_u_field(x, 21, 21); } // for vcmp* instructions 1244 static int xxsplt_uim(int x) { return opp_u_field(x, 15, 14); } // for xxsplt* instructions 1245 1246 // For extended opcodes (prefixed instructions) introduced with Power 10 1247 static long r_eo( int x) { return opp_u_field(x, 11, 11); } 1248 static long type( int x) { return opp_u_field(x, 7, 6); } 1249 static long st_x0( int x) { return opp_u_field(x, 8, 8); } 1250 static long st_x1( int x) { return opp_u_field(x, 11, 8); } 1251 1252 // - 8LS:D/MLS:D Formats 1253 static long d0_eo( long x) { return opp_u_field((x >> 16) & 0x3FFFF, 31, 14); } 1254 static long d1_eo( long x) { return opp_u_field(x & 0xFFFF, 31, 16); } 1255 static long s0_eo( long x) { return d0_eo(x); } 1256 static long s1_eo( long x) { return d1_eo(x); } 1257 1258 // - 8RR:XX4/8RR:D Formats 1259 static long imm0_eo( int x) { return opp_u_field(x >> 16, 31, 16); } 1260 static long imm1_eo( int x) { return opp_u_field(x & 0xFFFF, 31, 16); } 1261 static long uimm_eo( int x) { return opp_u_field(x, 31, 29); } 1262 static long imm_eo( int x) { return opp_u_field(x, 31, 24); } 1263 1264 //static int xo1( int x) { return opp_u_field(x, 29, 21); }// is contained in our opcodes 1265 //static int xo2( int x) { return opp_u_field(x, 30, 21); }// is contained in our opcodes 1266 //static int xo3( int x) { return opp_u_field(x, 30, 22); }// is contained in our opcodes 1267 //static int xo4( int x) { return opp_u_field(x, 30, 26); }// is contained in our opcodes 1268 //static int xo5( int x) { return opp_u_field(x, 29, 27); }// is contained in our opcodes 1269 //static int xo6( int x) { return opp_u_field(x, 30, 27); }// is contained in our opcodes 1270 //static int xo7( int x) { return opp_u_field(x, 31, 30); }// is contained in our opcodes 1271 1272 protected: 1273 // Compute relative address for branch. 1274 static intptr_t disp(intptr_t x, intptr_t off) { 1275 int xx = x - off; 1276 xx = xx >> 2; 1277 return xx; 1278 } 1279 1280 public: 1281 // signed immediate, in low bits, nbits long 1282 static int simm(int x, int nbits) { 1283 assert_signed_range(x, nbits); 1284 return x & ((1 << nbits) - 1); 1285 } 1286 1287 // unsigned immediate, in low bits, nbits long 1288 static int uimm(int x, int nbits) { 1289 assert_unsigned_const(x, nbits); 1290 return x & ((1 << nbits) - 1); 1291 } 1292 1293 static void set_imm(int* instr, short s) { 1294 // imm is always in the lower 16 bits of the instruction, 1295 // so this is endian-neutral. Same for the get_imm below. 1296 uint32_t w = *(uint32_t *)instr; 1297 *instr = (int)((w & ~0x0000FFFF) | (s & 0x0000FFFF)); 1298 } 1299 1300 static int get_imm(address a, int instruction_number) { 1301 return (short)((int *)a)[instruction_number]; 1302 } 1303 1304 static inline int hi16_signed( int x) { return (int)(int16_t)(x >> 16); } 1305 static inline int lo16_unsigned(int x) { return x & 0xffff; } 1306 1307 protected: 1308 1309 // Extract the top 32 bits in a 64 bit word. 1310 static int32_t hi32(int64_t x) { 1311 int32_t r = int32_t((uint64_t)x >> 32); 1312 return r; 1313 } 1314 1315 public: 1316 1317 static inline unsigned int align_addr(unsigned int addr, unsigned int a) { 1318 return ((addr + (a - 1)) & ~(a - 1)); 1319 } 1320 1321 static inline bool is_aligned(unsigned int addr, unsigned int a) { 1322 return (0 == addr % a); 1323 } 1324 1325 void flush() { 1326 AbstractAssembler::flush(); 1327 } 1328 1329 inline void emit_int32(int); // shadows AbstractAssembler::emit_int32 1330 inline void emit_data(int); 1331 inline void emit_data(int, RelocationHolder const&); 1332 inline void emit_data(int, relocInfo::relocType rtype); 1333 1334 // Emit an address. 1335 inline address emit_addr(const address addr = nullptr); 1336 1337 #if !defined(ABI_ELFv2) 1338 // Emit a function descriptor with the specified entry point, TOC, 1339 // and ENV. If the entry point is null, the descriptor will point 1340 // just past the descriptor. 1341 // Use values from friend functions as defaults. 1342 inline address emit_fd(address entry = nullptr, 1343 address toc = (address) FunctionDescriptor::friend_toc, 1344 address env = (address) FunctionDescriptor::friend_env); 1345 #endif 1346 1347 ///////////////////////////////////////////////////////////////////////////////////// 1348 // PPC instructions 1349 ///////////////////////////////////////////////////////////////////////////////////// 1350 1351 // Memory instructions use r0 as hard coded 0, e.g. to simulate loading 1352 // immediates. The normal instruction encoders enforce that r0 is not 1353 // passed to them. Use either extended mnemonics encoders or the special ra0 1354 // versions. 1355 1356 // Issue an illegal instruction. 1357 inline void illtrap(); 1358 static inline bool is_illtrap(address instr_addr); 1359 1360 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions 1361 inline void addi( Register d, Register a, int si16); 1362 inline void addis(Register d, Register a, int si16); 1363 1364 // Prefixed add immediate, introduced by POWER10 1365 inline void paddi(Register d, Register a, long si34, bool r); 1366 inline void pli( Register d, long si34); 1367 1368 private: 1369 inline void addi_r0ok( Register d, Register a, int si16); 1370 inline void addis_r0ok(Register d, Register a, int si16); 1371 inline void paddi_r0ok(Register d, Register a, long si34, bool r); 1372 public: 1373 inline void addic_( Register d, Register a, int si16); 1374 inline void subfic( Register d, Register a, int si16); 1375 inline void add( Register d, Register a, Register b); 1376 inline void add_( Register d, Register a, Register b); 1377 inline void subf( Register d, Register a, Register b); // d = b - a "Sub_from", as in ppc spec. 1378 inline void sub( Register d, Register a, Register b); // d = a - b Swap operands of subf for readability. 1379 inline void subf_( Register d, Register a, Register b); 1380 inline void addc( Register d, Register a, Register b); 1381 inline void addc_( Register d, Register a, Register b); 1382 inline void subfc( Register d, Register a, Register b); 1383 inline void subfc_( Register d, Register a, Register b); 1384 inline void adde( Register d, Register a, Register b); 1385 inline void adde_( Register d, Register a, Register b); 1386 inline void subfe( Register d, Register a, Register b); 1387 inline void subfe_( Register d, Register a, Register b); 1388 inline void addme( Register d, Register a); 1389 inline void addme_( Register d, Register a); 1390 inline void subfme( Register d, Register a); 1391 inline void subfme_(Register d, Register a); 1392 inline void addze( Register d, Register a); 1393 inline void addze_( Register d, Register a); 1394 inline void subfze( Register d, Register a); 1395 inline void subfze_(Register d, Register a); 1396 inline void neg( Register d, Register a); 1397 inline void neg_( Register d, Register a); 1398 inline void mulli( Register d, Register a, int si16); 1399 inline void mulld( Register d, Register a, Register b); 1400 inline void mulld_( Register d, Register a, Register b); 1401 inline void mullw( Register d, Register a, Register b); 1402 inline void mullw_( Register d, Register a, Register b); 1403 inline void mulhw( Register d, Register a, Register b); 1404 inline void mulhw_( Register d, Register a, Register b); 1405 inline void mulhwu( Register d, Register a, Register b); 1406 inline void mulhwu_(Register d, Register a, Register b); 1407 inline void mulhd( Register d, Register a, Register b); 1408 inline void mulhd_( Register d, Register a, Register b); 1409 inline void mulhdu( Register d, Register a, Register b); 1410 inline void mulhdu_(Register d, Register a, Register b); 1411 inline void divd( Register d, Register a, Register b); 1412 inline void divd_( Register d, Register a, Register b); 1413 inline void divw( Register d, Register a, Register b); 1414 inline void divw_( Register d, Register a, Register b); 1415 inline void divdu( Register d, Register a, Register b); 1416 inline void divdu_( Register d, Register a, Register b); 1417 inline void divwu( Register d, Register a, Register b); 1418 inline void divwu_( Register d, Register a, Register b); 1419 1420 // Fixed-Point Arithmetic Instructions with Overflow detection 1421 inline void addo( Register d, Register a, Register b); 1422 inline void addo_( Register d, Register a, Register b); 1423 inline void subfo( Register d, Register a, Register b); 1424 inline void subfo_( Register d, Register a, Register b); 1425 inline void addco( Register d, Register a, Register b); 1426 inline void addco_( Register d, Register a, Register b); 1427 inline void subfco( Register d, Register a, Register b); 1428 inline void subfco_( Register d, Register a, Register b); 1429 inline void addeo( Register d, Register a, Register b); 1430 inline void addeo_( Register d, Register a, Register b); 1431 inline void subfeo( Register d, Register a, Register b); 1432 inline void subfeo_( Register d, Register a, Register b); 1433 inline void addmeo( Register d, Register a); 1434 inline void addmeo_( Register d, Register a); 1435 inline void subfmeo( Register d, Register a); 1436 inline void subfmeo_(Register d, Register a); 1437 inline void addzeo( Register d, Register a); 1438 inline void addzeo_( Register d, Register a); 1439 inline void subfzeo( Register d, Register a); 1440 inline void subfzeo_(Register d, Register a); 1441 inline void nego( Register d, Register a); 1442 inline void nego_( Register d, Register a); 1443 inline void mulldo( Register d, Register a, Register b); 1444 inline void mulldo_( Register d, Register a, Register b); 1445 inline void mullwo( Register d, Register a, Register b); 1446 inline void mullwo_( Register d, Register a, Register b); 1447 inline void divdo( Register d, Register a, Register b); 1448 inline void divdo_( Register d, Register a, Register b); 1449 inline void divwo( Register d, Register a, Register b); 1450 inline void divwo_( Register d, Register a, Register b); 1451 1452 // extended mnemonics 1453 inline void li( Register d, int si16); 1454 inline void lis( Register d, int si16); 1455 inline void addir(Register d, int si16, Register a); 1456 inline void subi( Register d, Register a, int si16); 1457 1458 static bool is_addi(int x) { 1459 return ADDI_OPCODE == (x & ADDI_OPCODE_MASK); 1460 } 1461 static bool is_addis(int x) { 1462 return ADDIS_OPCODE == (x & ADDIS_OPCODE_MASK); 1463 } 1464 static bool is_andi(int x) { 1465 return ANDI_OPCODE == (x & ANDI_OPCODE_MASK); 1466 } 1467 static bool is_bxx(int x) { 1468 return BXX_OPCODE == (x & BXX_OPCODE_MASK); 1469 } 1470 static bool is_b(int x) { 1471 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 0; 1472 } 1473 static bool is_bl(int x) { 1474 return BXX_OPCODE == (x & BXX_OPCODE_MASK) && inv_lk_field(x) == 1; 1475 } 1476 static bool is_bcxx(int x) { 1477 return BCXX_OPCODE == (x & BCXX_OPCODE_MASK); 1478 } 1479 static bool is_bxx_or_bcxx(int x) { 1480 return is_bxx(x) || is_bcxx(x); 1481 } 1482 static bool is_bctrl(int x) { 1483 return x == 0x4e800421; 1484 } 1485 static bool is_bctr(int x) { 1486 return x == 0x4e800420; 1487 } 1488 static bool is_bclr(int x) { 1489 return BCLR_OPCODE == (x & XL_FORM_OPCODE_MASK); 1490 } 1491 static bool is_cmpli(int x) { 1492 return CMPLI_OPCODE == (x & CMPLI_OPCODE_MASK); 1493 } 1494 static bool is_li(int x) { 1495 return is_addi(x) && inv_ra_field(x)==0; 1496 } 1497 static bool is_lis(int x) { 1498 return is_addis(x) && inv_ra_field(x)==0; 1499 } 1500 static bool is_mtctr(int x) { 1501 return MTCTR_OPCODE == (x & MTCTR_OPCODE_MASK); 1502 } 1503 static bool is_ld(int x) { 1504 return LD_OPCODE == (x & LD_OPCODE_MASK); 1505 } 1506 static bool is_std(int x) { 1507 return STD_OPCODE == (x & STD_OPCODE_MASK); 1508 } 1509 static bool is_stdu(int x) { 1510 return STDU_OPCODE == (x & STDU_OPCODE_MASK); 1511 } 1512 static bool is_stdx(int x) { 1513 return STDX_OPCODE == (x & STDX_OPCODE_MASK); 1514 } 1515 static bool is_stdux(int x) { 1516 return STDUX_OPCODE == (x & STDUX_OPCODE_MASK); 1517 } 1518 static bool is_stwx(int x) { 1519 return STWX_OPCODE == (x & STWX_OPCODE_MASK); 1520 } 1521 static bool is_stwux(int x) { 1522 return STWUX_OPCODE == (x & STWUX_OPCODE_MASK); 1523 } 1524 static bool is_stw(int x) { 1525 return STW_OPCODE == (x & STW_OPCODE_MASK); 1526 } 1527 static bool is_stwu(int x) { 1528 return STWU_OPCODE == (x & STWU_OPCODE_MASK); 1529 } 1530 static bool is_ori(int x) { 1531 return ORI_OPCODE == (x & ORI_OPCODE_MASK); 1532 }; 1533 static bool is_oris(int x) { 1534 return ORIS_OPCODE == (x & ORIS_OPCODE_MASK); 1535 }; 1536 static bool is_rldicr(int x) { 1537 return (RLDICR_OPCODE == (x & RLDICR_OPCODE_MASK)); 1538 }; 1539 static bool is_nop(int x) { 1540 return x == 0x60000000; 1541 } 1542 // endgroup opcode for Power6 1543 static bool is_endgroup(int x) { 1544 return is_ori(x) && inv_ra_field(x) == 1 && inv_rs_field(x) == 1 && inv_d1_field(x) == 0; 1545 } 1546 1547 1548 private: 1549 // PPC 1, section 3.3.9, Fixed-Point Compare Instructions 1550 inline void cmpi( ConditionRegister bf, int l, Register a, int si16); 1551 inline void cmp( ConditionRegister bf, int l, Register a, Register b); 1552 inline void cmpli(ConditionRegister bf, int l, Register a, int ui16); 1553 inline void cmpl( ConditionRegister bf, int l, Register a, Register b); 1554 1555 public: 1556 // extended mnemonics of Compare Instructions 1557 inline void cmpwi( ConditionRegister crx, Register a, int si16); 1558 inline void cmpdi( ConditionRegister crx, Register a, int si16); 1559 inline void cmpw( ConditionRegister crx, Register a, Register b); 1560 inline void cmpd( ConditionRegister crx, Register a, Register b); 1561 inline void cmplwi(ConditionRegister crx, Register a, int ui16); 1562 inline void cmpldi(ConditionRegister crx, Register a, int ui16); 1563 inline void cmplw( ConditionRegister crx, Register a, Register b); 1564 inline void cmpld( ConditionRegister crx, Register a, Register b); 1565 1566 // >= Power9 1567 inline void cmprb( ConditionRegister bf, int l, Register a, Register b); 1568 inline void cmpeqb(ConditionRegister bf, Register a, Register b); 1569 1570 inline void isel( Register d, Register a, Register b, int bc); 1571 // Convenient version which takes: Condition register, Condition code and invert flag. Omit b to keep old value. 1572 inline void isel( Register d, ConditionRegister cr, Condition cc, bool inv, Register a, Register b = noreg); 1573 // Set d = 0 if (cr.cc) equals 1, otherwise b. 1574 inline void isel_0( Register d, ConditionRegister cr, Condition cc, Register b = noreg); 1575 1576 // PPC 1, section 3.3.11, Fixed-Point Logical Instructions 1577 void andi( Register a, Register s, long ui16); // optimized version 1578 inline void andi_( Register a, Register s, int ui16); 1579 inline void andis_( Register a, Register s, int ui16); 1580 inline void ori( Register a, Register s, int ui16); 1581 inline void oris( Register a, Register s, int ui16); 1582 inline void xori( Register a, Register s, int ui16); 1583 inline void xoris( Register a, Register s, int ui16); 1584 inline void andr( Register a, Register s, Register b); // suffixed by 'r' as 'and' is C++ keyword 1585 inline void and_( Register a, Register s, Register b); 1586 // Turn or0(rx,rx,rx) into a nop and avoid that we accidentally emit a 1587 // SMT-priority change instruction (see SMT instructions below). 1588 inline void or_unchecked(Register a, Register s, Register b); 1589 inline void orr( Register a, Register s, Register b); // suffixed by 'r' as 'or' is C++ keyword 1590 inline void or_( Register a, Register s, Register b); 1591 inline void xorr( Register a, Register s, Register b); // suffixed by 'r' as 'xor' is C++ keyword 1592 inline void xor_( Register a, Register s, Register b); 1593 inline void nand( Register a, Register s, Register b); 1594 inline void nand_( Register a, Register s, Register b); 1595 inline void nor( Register a, Register s, Register b); 1596 inline void nor_( Register a, Register s, Register b); 1597 inline void andc( Register a, Register s, Register b); 1598 inline void andc_( Register a, Register s, Register b); 1599 inline void orc( Register a, Register s, Register b); 1600 inline void orc_( Register a, Register s, Register b); 1601 inline void extsb( Register a, Register s); 1602 inline void extsb_( Register a, Register s); 1603 inline void extsh( Register a, Register s); 1604 inline void extsh_( Register a, Register s); 1605 inline void extsw( Register a, Register s); 1606 inline void extsw_( Register a, Register s); 1607 1608 // extended mnemonics 1609 inline void nop(); 1610 // NOP for FP and BR units (different versions to allow them to be in one group) 1611 inline void fpnop0(); 1612 inline void fpnop1(); 1613 inline void brnop0(); 1614 inline void brnop1(); 1615 inline void brnop2(); 1616 1617 inline void mr( Register d, Register s); 1618 inline void ori_opt( Register d, int ui16); 1619 inline void oris_opt(Register d, int ui16); 1620 1621 // endgroup opcode for Power6 1622 inline void endgroup(); 1623 1624 // count instructions 1625 inline void cntlzw( Register a, Register s); 1626 inline void cntlzw_( Register a, Register s); 1627 inline void cntlzd( Register a, Register s); 1628 inline void cntlzd_( Register a, Register s); 1629 inline void cnttzw( Register a, Register s); 1630 inline void cnttzw_( Register a, Register s); 1631 inline void cnttzd( Register a, Register s); 1632 inline void cnttzd_( Register a, Register s); 1633 1634 // PPC 1, section 3.3.12, Fixed-Point Rotate and Shift Instructions 1635 inline void sld( Register a, Register s, Register b); 1636 inline void sld_( Register a, Register s, Register b); 1637 inline void slw( Register a, Register s, Register b); 1638 inline void slw_( Register a, Register s, Register b); 1639 inline void srd( Register a, Register s, Register b); 1640 inline void srd_( Register a, Register s, Register b); 1641 inline void srw( Register a, Register s, Register b); 1642 inline void srw_( Register a, Register s, Register b); 1643 inline void srad( Register a, Register s, Register b); 1644 inline void srad_( Register a, Register s, Register b); 1645 inline void sraw( Register a, Register s, Register b); 1646 inline void sraw_( Register a, Register s, Register b); 1647 inline void sradi( Register a, Register s, int sh6); 1648 inline void sradi_( Register a, Register s, int sh6); 1649 inline void srawi( Register a, Register s, int sh5); 1650 inline void srawi_( Register a, Register s, int sh5); 1651 1652 // extended mnemonics for Shift Instructions 1653 inline void sldi( Register a, Register s, int sh6); 1654 inline void sldi_( Register a, Register s, int sh6); 1655 inline void slwi( Register a, Register s, int sh5); 1656 inline void slwi_( Register a, Register s, int sh5); 1657 inline void srdi( Register a, Register s, int sh6); 1658 inline void srdi_( Register a, Register s, int sh6); 1659 inline void srwi( Register a, Register s, int sh5); 1660 inline void srwi_( Register a, Register s, int sh5); 1661 1662 inline void clrrdi( Register a, Register s, int ui6); 1663 inline void clrrdi_( Register a, Register s, int ui6); 1664 inline void clrldi( Register a, Register s, int ui6); 1665 inline void clrldi_( Register a, Register s, int ui6); 1666 inline void clrlsldi(Register a, Register s, int clrl6, int shl6); 1667 inline void clrlsldi_(Register a, Register s, int clrl6, int shl6); 1668 inline void extrdi( Register a, Register s, int n, int b); 1669 // testbit with condition register 1670 inline void testbitdi(ConditionRegister cr, Register a, Register s, int ui6); 1671 1672 // Byte reverse instructions (introduced with Power10) 1673 inline void brh( Register a, Register s); 1674 inline void brw( Register a, Register s); 1675 inline void brd( Register a, Register s); 1676 1677 // rotate instructions 1678 inline void rotldi( Register a, Register s, int n); 1679 inline void rotrdi( Register a, Register s, int n); 1680 inline void rotlwi( Register a, Register s, int n); 1681 inline void rotrwi( Register a, Register s, int n); 1682 1683 // Rotate Instructions 1684 inline void rldic( Register a, Register s, int sh6, int mb6); 1685 inline void rldic_( Register a, Register s, int sh6, int mb6); 1686 inline void rldicr( Register a, Register s, int sh6, int mb6); 1687 inline void rldicr_( Register a, Register s, int sh6, int mb6); 1688 inline void rldicl( Register a, Register s, int sh6, int mb6); 1689 inline void rldicl_( Register a, Register s, int sh6, int mb6); 1690 inline void rlwinm( Register a, Register s, int sh5, int mb5, int me5); 1691 inline void rlwinm_( Register a, Register s, int sh5, int mb5, int me5); 1692 inline void rldimi( Register a, Register s, int sh6, int mb6); 1693 inline void rldimi_( Register a, Register s, int sh6, int mb6); 1694 inline void rlwimi( Register a, Register s, int sh5, int mb5, int me5); 1695 inline void insrdi( Register a, Register s, int n, int b); 1696 inline void insrwi( Register a, Register s, int n, int b); 1697 1698 // PPC 1, section 3.3.2 Fixed-Point Load Instructions 1699 // 4 bytes 1700 inline void lwzx( Register d, Register s1, Register s2); 1701 inline void lwz( Register d, int si16, Register s1); 1702 inline void lwzu( Register d, int si16, Register s1); 1703 1704 // 4 bytes 1705 inline void lwax( Register d, Register s1, Register s2); 1706 inline void lwa( Register d, int si16, Register s1); 1707 1708 // 4 bytes reversed 1709 inline void lwbrx( Register d, Register s1, Register s2); 1710 1711 // 2 bytes 1712 inline void lhzx( Register d, Register s1, Register s2); 1713 inline void lhz( Register d, int si16, Register s1); 1714 inline void lhzu( Register d, int si16, Register s1); 1715 1716 // 2 bytes reversed 1717 inline void lhbrx( Register d, Register s1, Register s2); 1718 1719 // 2 bytes 1720 inline void lhax( Register d, Register s1, Register s2); 1721 inline void lha( Register d, int si16, Register s1); 1722 inline void lhau( Register d, int si16, Register s1); 1723 1724 // 1 byte 1725 inline void lbzx( Register d, Register s1, Register s2); 1726 inline void lbz( Register d, int si16, Register s1); 1727 inline void lbzu( Register d, int si16, Register s1); 1728 1729 // 8 bytes 1730 inline void ldx( Register d, Register s1, Register s2); 1731 inline void ld( Register d, int si16, Register s1); 1732 inline void ld( Register d, ByteSize si16, Register s1); 1733 inline void ldu( Register d, int si16, Register s1); 1734 1735 // 8 bytes reversed 1736 inline void ldbrx( Register d, Register s1, Register s2); 1737 1738 // For convenience. Load pointer into d from b+s1. 1739 inline void ld_ptr(Register d, int b, Register s1); 1740 inline void ld_ptr(Register d, ByteSize b, Register s1); 1741 1742 // PPC 1, section 3.3.3 Fixed-Point Store Instructions 1743 inline void stwx( Register d, Register s1, Register s2); 1744 inline void stw( Register d, int si16, Register s1); 1745 inline void stwu( Register d, int si16, Register s1); 1746 inline void stwbrx( Register d, Register s1, Register s2); 1747 1748 inline void sthx( Register d, Register s1, Register s2); 1749 inline void sth( Register d, int si16, Register s1); 1750 inline void sthu( Register d, int si16, Register s1); 1751 inline void sthbrx( Register d, Register s1, Register s2); 1752 1753 inline void stbx( Register d, Register s1, Register s2); 1754 inline void stb( Register d, int si16, Register s1); 1755 inline void stbu( Register d, int si16, Register s1); 1756 1757 inline void stdx( Register d, Register s1, Register s2); 1758 inline void std( Register d, int si16, Register s1); 1759 inline void stdu( Register d, int si16, Register s1); 1760 inline void stdux(Register s, Register a, Register b); 1761 inline void stdbrx( Register d, Register s1, Register s2); 1762 1763 inline void st_ptr(Register d, int si16, Register s1); 1764 inline void st_ptr(Register d, ByteSize b, Register s1); 1765 1766 // PPC 1, section 3.3.13 Move To/From System Register Instructions 1767 inline void mtlr( Register s1); 1768 inline void mflr( Register d); 1769 inline void mtctr(Register s1); 1770 inline void mfctr(Register d); 1771 inline void mtcrf(int fxm, Register s); 1772 inline void mfcr( Register d); 1773 inline void mcrf( ConditionRegister crd, ConditionRegister cra); 1774 inline void mtcr( Register s); 1775 // >= Power9 1776 inline void mcrxrx(ConditionRegister cra); 1777 inline void setb( Register d, ConditionRegister cra); 1778 1779 // >= Power10 1780 inline void setbc( Register d, int biint); 1781 inline void setbc( Register d, ConditionRegister cr, Condition cc); 1782 inline void setnbc(Register d, int biint); 1783 inline void setnbc(Register d, ConditionRegister cr, Condition cc); 1784 inline void setbcr(Register d, int biint); 1785 inline void setbcr(Register d, ConditionRegister cr, Condition cc); 1786 1787 // Special purpose registers 1788 // Exception Register 1789 inline void mtxer(Register s1); 1790 inline void mfxer(Register d); 1791 // Vector Register Save Register 1792 inline void mtvrsave(Register s1); 1793 inline void mfvrsave(Register d); 1794 // Timebase 1795 inline void mftb(Register d); 1796 // Introduced with Power 8: 1797 // Data Stream Control Register 1798 inline void mtdscr(Register s1); 1799 inline void mfdscr(Register d ); 1800 1801 // PPC 1, section 2.4.1 Branch Instructions 1802 inline void b( address a, relocInfo::relocType rt = relocInfo::none); 1803 inline void b( Label& L); 1804 inline void bl( address a, relocInfo::relocType rt = relocInfo::none); 1805 inline void bl( Label& L); 1806 inline void bc( int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1807 inline void bc( int boint, int biint, Label& L); 1808 inline void bcl(int boint, int biint, address a, relocInfo::relocType rt = relocInfo::none); 1809 inline void bcl(int boint, int biint, Label& L); 1810 1811 inline void bclr( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1812 inline void bclrl( int boint, int biint, int bhint, relocInfo::relocType rt = relocInfo::none); 1813 inline void bcctr( int boint, int biint, int bhint = bhintbhBCCTRisNotReturnButSame, 1814 relocInfo::relocType rt = relocInfo::none); 1815 inline void bcctrl(int boint, int biint, int bhint = bhintbhBCLRisReturn, 1816 relocInfo::relocType rt = relocInfo::none); 1817 1818 // helper function for b, bcxx 1819 inline bool is_within_range_of_b(address a, address pc); 1820 inline bool is_within_range_of_bcxx(address a, address pc); 1821 1822 // get the destination of a bxx branch (b, bl, ba, bla) 1823 static inline address bxx_destination(address baddr); 1824 static inline address bxx_destination(int instr, address pc); 1825 static inline intptr_t bxx_destination_offset(int instr, intptr_t bxx_pos); 1826 1827 // extended mnemonics for branch instructions 1828 inline void blt(ConditionRegister crx, Label& L); 1829 inline void bgt(ConditionRegister crx, Label& L); 1830 inline void beq(ConditionRegister crx, Label& L); 1831 inline void bso(ConditionRegister crx, Label& L); 1832 inline void bge(ConditionRegister crx, Label& L); 1833 inline void ble(ConditionRegister crx, Label& L); 1834 inline void bne(ConditionRegister crx, Label& L); 1835 inline void bns(ConditionRegister crx, Label& L); 1836 1837 // Branch instructions with static prediction hints. 1838 inline void blt_predict_taken( ConditionRegister crx, Label& L); 1839 inline void bgt_predict_taken( ConditionRegister crx, Label& L); 1840 inline void beq_predict_taken( ConditionRegister crx, Label& L); 1841 inline void bso_predict_taken( ConditionRegister crx, Label& L); 1842 inline void bge_predict_taken( ConditionRegister crx, Label& L); 1843 inline void ble_predict_taken( ConditionRegister crx, Label& L); 1844 inline void bne_predict_taken( ConditionRegister crx, Label& L); 1845 inline void bns_predict_taken( ConditionRegister crx, Label& L); 1846 inline void blt_predict_not_taken(ConditionRegister crx, Label& L); 1847 inline void bgt_predict_not_taken(ConditionRegister crx, Label& L); 1848 inline void beq_predict_not_taken(ConditionRegister crx, Label& L); 1849 inline void bso_predict_not_taken(ConditionRegister crx, Label& L); 1850 inline void bge_predict_not_taken(ConditionRegister crx, Label& L); 1851 inline void ble_predict_not_taken(ConditionRegister crx, Label& L); 1852 inline void bne_predict_not_taken(ConditionRegister crx, Label& L); 1853 inline void bns_predict_not_taken(ConditionRegister crx, Label& L); 1854 1855 // for use in conjunction with testbitdi: 1856 inline void btrue( ConditionRegister crx, Label& L); 1857 inline void bfalse(ConditionRegister crx, Label& L); 1858 1859 inline void bltl(ConditionRegister crx, Label& L); 1860 inline void bgtl(ConditionRegister crx, Label& L); 1861 inline void beql(ConditionRegister crx, Label& L); 1862 inline void bsol(ConditionRegister crx, Label& L); 1863 inline void bgel(ConditionRegister crx, Label& L); 1864 inline void blel(ConditionRegister crx, Label& L); 1865 inline void bnel(ConditionRegister crx, Label& L); 1866 inline void bnsl(ConditionRegister crx, Label& L); 1867 1868 // extended mnemonics for Branch Instructions via LR 1869 // We use `blr' for returns. 1870 inline void blr(relocInfo::relocType rt = relocInfo::none); 1871 1872 // extended mnemonics for Branch Instructions with CTR 1873 // bdnz means `decrement CTR and jump to L if CTR is not zero' 1874 inline void bdnz(Label& L); 1875 // Decrement and branch if result is zero. 1876 inline void bdz(Label& L); 1877 // we use `bctr[l]' for jumps/calls in function descriptor glue 1878 // code, e.g. calls to runtime functions 1879 inline void bctr( relocInfo::relocType rt = relocInfo::none); 1880 inline void bctrl(relocInfo::relocType rt = relocInfo::none); 1881 // conditional jumps/branches via CTR 1882 inline void beqctr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1883 inline void beqctrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1884 inline void bnectr( ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1885 inline void bnectrl(ConditionRegister crx, relocInfo::relocType rt = relocInfo::none); 1886 1887 // condition register logic instructions 1888 // NOTE: There's a preferred form: d and s2 should point into the same condition register. 1889 inline void crand( int d, int s1, int s2); 1890 inline void crnand(int d, int s1, int s2); 1891 inline void cror( int d, int s1, int s2); 1892 inline void crxor( int d, int s1, int s2); 1893 inline void crnor( int d, int s1, int s2); 1894 inline void creqv( int d, int s1, int s2); 1895 inline void crandc(int d, int s1, int s2); 1896 inline void crorc( int d, int s1, int s2); 1897 1898 // More convenient version. 1899 int condition_register_bit(ConditionRegister cr, Condition c) { 1900 return 4 * cr.encoding() + c; 1901 } 1902 void crand( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1903 void crnand(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1904 void cror( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1905 void crxor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1906 void crnor( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1907 void creqv( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1908 void crandc(ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1909 void crorc( ConditionRegister crdst, Condition cdst, ConditionRegister crsrc, Condition csrc); 1910 1911 // icache and dcache related instructions 1912 inline void icbi( Register s1, Register s2); 1913 //inline void dcba(Register s1, Register s2); // Instruction for embedded processor only. 1914 inline void dcbz( Register s1, Register s2); 1915 inline void dcbst( Register s1, Register s2); 1916 inline void dcbf( Register s1, Register s2); 1917 1918 enum ct_cache_specification { 1919 ct_primary_cache = 0, 1920 ct_secondary_cache = 2 1921 }; 1922 // dcache read hint 1923 inline void dcbt( Register s1, Register s2); 1924 inline void dcbtct( Register s1, Register s2, int ct); 1925 inline void dcbtds( Register s1, Register s2, int ds); 1926 // dcache write hint 1927 inline void dcbtst( Register s1, Register s2); 1928 inline void dcbtstct(Register s1, Register s2, int ct); 1929 1930 // machine barrier instructions: 1931 // 1932 // - sync two-way memory barrier, aka fence 1933 // - lwsync orders Store|Store, 1934 // Load|Store, 1935 // Load|Load, 1936 // but not Store|Load 1937 // - eieio orders memory accesses for device memory (only) 1938 // - isync invalidates speculatively executed instructions 1939 // From the Power ISA 2.06 documentation: 1940 // "[...] an isync instruction prevents the execution of 1941 // instructions following the isync until instructions 1942 // preceding the isync have completed, [...]" 1943 // From IBM's AIX assembler reference: 1944 // "The isync [...] instructions causes the processor to 1945 // refetch any instructions that might have been fetched 1946 // prior to the isync instruction. The instruction isync 1947 // causes the processor to wait for all previous instructions 1948 // to complete. Then any instructions already fetched are 1949 // discarded and instruction processing continues in the 1950 // environment established by the previous instructions." 1951 // 1952 // semantic barrier instructions: 1953 // (as defined in orderAccess.hpp) 1954 // 1955 // - release orders Store|Store, (maps to lwsync) 1956 // Load|Store 1957 // - acquire orders Load|Store, (maps to lwsync) 1958 // Load|Load 1959 // - fence orders Store|Store, (maps to sync) 1960 // Load|Store, 1961 // Load|Load, 1962 // Store|Load 1963 // 1964 private: 1965 inline void sync(int l); 1966 public: 1967 inline void sync(); 1968 inline void lwsync(); 1969 inline void ptesync(); 1970 inline void eieio(); 1971 inline void isync(); 1972 inline void elemental_membar(int e); // Elemental Memory Barriers (>=Power 8) 1973 1974 // Wait instructions for polling. Attention: May result in SIGILL. 1975 inline void wait(); 1976 inline void waitrsv(); // >=Power7 1977 1978 // atomics 1979 inline void lbarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1980 inline void lharx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1981 inline void lwarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1982 inline void ldarx_unchecked(Register d, Register a, Register b, int eh1 = 0); 1983 inline void lqarx_unchecked(Register d, Register a, Register b, int eh1 = 0); // >=Power 8 1984 inline bool lxarx_hint_exclusive_access(); 1985 inline void lbarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1986 inline void lharx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1987 inline void lwarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1988 inline void ldarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1989 inline void lqarx( Register d, Register a, Register b, bool hint_exclusive_access = false); 1990 inline void stbcx_( Register s, Register a, Register b); 1991 inline void sthcx_( Register s, Register a, Register b); 1992 inline void stwcx_( Register s, Register a, Register b); 1993 inline void stdcx_( Register s, Register a, Register b); 1994 inline void stqcx_( Register s, Register a, Register b); 1995 1996 // Instructions for adjusting thread priority for simultaneous 1997 // multithreading (SMT) on Power5. 1998 private: 1999 inline void smt_prio_very_low(); 2000 inline void smt_prio_medium_high(); 2001 inline void smt_prio_high(); 2002 2003 public: 2004 inline void smt_prio_low(); 2005 inline void smt_prio_medium_low(); 2006 inline void smt_prio_medium(); 2007 // >= Power7 2008 inline void smt_yield(); 2009 inline void smt_mdoio(); 2010 inline void smt_mdoom(); 2011 // >= Power8 2012 inline void smt_miso(); 2013 2014 // trap instructions 2015 inline void twi_0(Register a); // for load with acquire semantics use load+twi_0+isync (trap can't occur) 2016 // NOT FOR DIRECT USE!! 2017 protected: 2018 inline void tdi_unchecked(int tobits, Register a, int si16); 2019 inline void twi_unchecked(int tobits, Register a, int si16); 2020 inline void tdi( int tobits, Register a, int si16); // asserts UseSIGTRAP 2021 inline void twi( int tobits, Register a, int si16); // asserts UseSIGTRAP 2022 inline void td( int tobits, Register a, Register b); // asserts UseSIGTRAP 2023 inline void tw( int tobits, Register a, Register b); // asserts UseSIGTRAP 2024 2025 public: 2026 static bool is_tdi(int x, int tobits, int ra, int si16) { 2027 return (TDI_OPCODE == (x & TDI_OPCODE_MASK)) 2028 && (tobits == inv_to_field(x)) 2029 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2030 && (si16 == inv_si_field(x)); 2031 } 2032 2033 static int tdi_get_si16(int x, int tobits, int ra) { 2034 if (TDI_OPCODE == (x & TDI_OPCODE_MASK) 2035 && (tobits == inv_to_field(x)) 2036 && (ra == -1/*any reg*/ || ra == inv_ra_field(x))) { 2037 return inv_si_field(x); 2038 } 2039 return -1; // No valid tdi instruction. 2040 } 2041 2042 static bool is_twi(int x, int tobits, int ra, int si16) { 2043 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 2044 && (tobits == inv_to_field(x)) 2045 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2046 && (si16 == inv_si_field(x)); 2047 } 2048 2049 static bool is_twi(int x, int tobits, int ra) { 2050 return (TWI_OPCODE == (x & TWI_OPCODE_MASK)) 2051 && (tobits == inv_to_field(x)) 2052 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)); 2053 } 2054 2055 static bool is_td(int x, int tobits, int ra, int rb) { 2056 return (TD_OPCODE == (x & TD_OPCODE_MASK)) 2057 && (tobits == inv_to_field(x)) 2058 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2059 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 2060 } 2061 2062 static bool is_tw(int x, int tobits, int ra, int rb) { 2063 return (TW_OPCODE == (x & TW_OPCODE_MASK)) 2064 && (tobits == inv_to_field(x)) 2065 && (ra == -1/*any reg*/ || ra == inv_ra_field(x)) 2066 && (rb == -1/*any reg*/ || rb == inv_rb_field(x)); 2067 } 2068 2069 // PPC floating point instructions 2070 // PPC 1, section 4.6.2 Floating-Point Load Instructions 2071 inline void lfs( FloatRegister d, int si16, Register a); 2072 inline void lfsu( FloatRegister d, int si16, Register a); 2073 inline void lfsx( FloatRegister d, Register a, Register b); 2074 inline void lfd( FloatRegister d, int si16, Register a); 2075 inline void lfdu( FloatRegister d, int si16, Register a); 2076 inline void lfdx( FloatRegister d, Register a, Register b); 2077 2078 // PPC 1, section 4.6.3 Floating-Point Store Instructions 2079 inline void stfs( FloatRegister s, int si16, Register a); 2080 inline void stfsu( FloatRegister s, int si16, Register a); 2081 inline void stfsx( FloatRegister s, Register a, Register b); 2082 inline void stfd( FloatRegister s, int si16, Register a); 2083 inline void stfdu( FloatRegister s, int si16, Register a); 2084 inline void stfdx( FloatRegister s, Register a, Register b); 2085 2086 // PPC 1, section 4.6.4 Floating-Point Move Instructions 2087 inline void fmr( FloatRegister d, FloatRegister b); 2088 inline void fmr_( FloatRegister d, FloatRegister b); 2089 2090 inline void frin( FloatRegister d, FloatRegister b); 2091 inline void frip( FloatRegister d, FloatRegister b); 2092 inline void frim( FloatRegister d, FloatRegister b); 2093 2094 // inline void mffgpr( FloatRegister d, Register b); 2095 // inline void mftgpr( Register d, FloatRegister b); 2096 inline void cmpb( Register a, Register s, Register b); 2097 inline void popcntb(Register a, Register s); 2098 inline void popcntw(Register a, Register s); 2099 inline void popcntd(Register a, Register s); 2100 2101 inline void fneg( FloatRegister d, FloatRegister b); 2102 inline void fneg_( FloatRegister d, FloatRegister b); 2103 inline void fabs( FloatRegister d, FloatRegister b); 2104 inline void fabs_( FloatRegister d, FloatRegister b); 2105 inline void fnabs( FloatRegister d, FloatRegister b); 2106 inline void fnabs_(FloatRegister d, FloatRegister b); 2107 2108 // PPC 1, section 4.6.5.1 Floating-Point Elementary Arithmetic Instructions 2109 inline void fadd( FloatRegister d, FloatRegister a, FloatRegister b); 2110 inline void fadd_( FloatRegister d, FloatRegister a, FloatRegister b); 2111 inline void fadds( FloatRegister d, FloatRegister a, FloatRegister b); 2112 inline void fadds_(FloatRegister d, FloatRegister a, FloatRegister b); 2113 inline void fsub( FloatRegister d, FloatRegister a, FloatRegister b); 2114 inline void fsub_( FloatRegister d, FloatRegister a, FloatRegister b); 2115 inline void fsubs( FloatRegister d, FloatRegister a, FloatRegister b); 2116 inline void fsubs_(FloatRegister d, FloatRegister a, FloatRegister b); 2117 inline void fmul( FloatRegister d, FloatRegister a, FloatRegister c); 2118 inline void fmul_( FloatRegister d, FloatRegister a, FloatRegister c); 2119 inline void fmuls( FloatRegister d, FloatRegister a, FloatRegister c); 2120 inline void fmuls_(FloatRegister d, FloatRegister a, FloatRegister c); 2121 inline void fdiv( FloatRegister d, FloatRegister a, FloatRegister b); 2122 inline void fdiv_( FloatRegister d, FloatRegister a, FloatRegister b); 2123 inline void fdivs( FloatRegister d, FloatRegister a, FloatRegister b); 2124 inline void fdivs_(FloatRegister d, FloatRegister a, FloatRegister b); 2125 2126 // Fused multiply-accumulate instructions. 2127 // WARNING: Use only when rounding between the 2 parts is not desired. 2128 // Some floating point tck tests will fail if used incorrectly. 2129 inline void fmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2130 inline void fmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2131 inline void fmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2132 inline void fmadds_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2133 inline void fmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2134 inline void fmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2135 inline void fmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2136 inline void fmsubs_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2137 inline void fnmadd( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2138 inline void fnmadd_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2139 inline void fnmadds( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2140 inline void fnmadds_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2141 inline void fnmsub( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2142 inline void fnmsub_( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2143 inline void fnmsubs( FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2144 inline void fnmsubs_(FloatRegister d, FloatRegister a, FloatRegister c, FloatRegister b); 2145 2146 // PPC 1, section 4.6.6 Floating-Point Rounding and Conversion Instructions 2147 inline void frsp( FloatRegister d, FloatRegister b); 2148 inline void fctid( FloatRegister d, FloatRegister b); 2149 inline void fctidz(FloatRegister d, FloatRegister b); 2150 inline void fctiw( FloatRegister d, FloatRegister b); 2151 inline void fctiwz(FloatRegister d, FloatRegister b); 2152 inline void fcfid( FloatRegister d, FloatRegister b); 2153 inline void fcfids(FloatRegister d, FloatRegister b); 2154 2155 // PPC 1, section 4.6.7 Floating-Point Compare Instructions 2156 inline void fcmpu( ConditionRegister crx, FloatRegister a, FloatRegister b); 2157 2158 inline void fsqrt( FloatRegister d, FloatRegister b); 2159 inline void fsqrts(FloatRegister d, FloatRegister b); 2160 2161 // Vector instructions for >= Power6. 2162 inline void lvebx( VectorRegister d, Register s1, Register s2); 2163 inline void lvehx( VectorRegister d, Register s1, Register s2); 2164 inline void lvewx( VectorRegister d, Register s1, Register s2); 2165 inline void lvx( VectorRegister d, Register s1, Register s2); 2166 inline void lvxl( VectorRegister d, Register s1, Register s2); 2167 inline void stvebx( VectorRegister d, Register s1, Register s2); 2168 inline void stvehx( VectorRegister d, Register s1, Register s2); 2169 inline void stvewx( VectorRegister d, Register s1, Register s2); 2170 inline void stvx( VectorRegister d, Register s1, Register s2); 2171 inline void stvxl( VectorRegister d, Register s1, Register s2); 2172 inline void lvsl( VectorRegister d, Register s1, Register s2); 2173 inline void lvsr( VectorRegister d, Register s1, Register s2); 2174 inline void vpkpx( VectorRegister d, VectorRegister a, VectorRegister b); 2175 inline void vpkshss( VectorRegister d, VectorRegister a, VectorRegister b); 2176 inline void vpkswss( VectorRegister d, VectorRegister a, VectorRegister b); 2177 inline void vpkshus( VectorRegister d, VectorRegister a, VectorRegister b); 2178 inline void vpkswus( VectorRegister d, VectorRegister a, VectorRegister b); 2179 inline void vpkuhum( VectorRegister d, VectorRegister a, VectorRegister b); 2180 inline void vpkuwum( VectorRegister d, VectorRegister a, VectorRegister b); 2181 inline void vpkuhus( VectorRegister d, VectorRegister a, VectorRegister b); 2182 inline void vpkuwus( VectorRegister d, VectorRegister a, VectorRegister b); 2183 inline void vupkhpx( VectorRegister d, VectorRegister b); 2184 inline void vupkhsb( VectorRegister d, VectorRegister b); 2185 inline void vupkhsh( VectorRegister d, VectorRegister b); 2186 inline void vupklpx( VectorRegister d, VectorRegister b); 2187 inline void vupklsb( VectorRegister d, VectorRegister b); 2188 inline void vupklsh( VectorRegister d, VectorRegister b); 2189 inline void vmrghb( VectorRegister d, VectorRegister a, VectorRegister b); 2190 inline void vmrghw( VectorRegister d, VectorRegister a, VectorRegister b); 2191 inline void vmrghh( VectorRegister d, VectorRegister a, VectorRegister b); 2192 inline void vmrglb( VectorRegister d, VectorRegister a, VectorRegister b); 2193 inline void vmrglw( VectorRegister d, VectorRegister a, VectorRegister b); 2194 inline void vmrglh( VectorRegister d, VectorRegister a, VectorRegister b); 2195 inline void vsplt( VectorRegister d, int ui4, VectorRegister b); 2196 inline void vsplth( VectorRegister d, int ui3, VectorRegister b); 2197 inline void vspltw( VectorRegister d, int ui2, VectorRegister b); 2198 inline void vspltisb( VectorRegister d, int si5); 2199 inline void vspltish( VectorRegister d, int si5); 2200 inline void vspltisw( VectorRegister d, int si5); 2201 inline void vperm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2202 inline void vpextd( VectorRegister d, VectorRegister a, VectorRegister b); 2203 inline void vsel( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2204 inline void vsl( VectorRegister d, VectorRegister a, VectorRegister b); 2205 inline void vsldoi( VectorRegister d, VectorRegister a, VectorRegister b, int ui4); 2206 inline void vslo( VectorRegister d, VectorRegister a, VectorRegister b); 2207 inline void vsr( VectorRegister d, VectorRegister a, VectorRegister b); 2208 inline void vsro( VectorRegister d, VectorRegister a, VectorRegister b); 2209 inline void vaddcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2210 inline void vaddshs( VectorRegister d, VectorRegister a, VectorRegister b); 2211 inline void vaddsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2212 inline void vaddsws( VectorRegister d, VectorRegister a, VectorRegister b); 2213 inline void vaddubm( VectorRegister d, VectorRegister a, VectorRegister b); 2214 inline void vadduwm( VectorRegister d, VectorRegister a, VectorRegister b); 2215 inline void vadduhm( VectorRegister d, VectorRegister a, VectorRegister b); 2216 inline void vaddudm( VectorRegister d, VectorRegister a, VectorRegister b); 2217 inline void vaddubs( VectorRegister d, VectorRegister a, VectorRegister b); 2218 inline void vadduws( VectorRegister d, VectorRegister a, VectorRegister b); 2219 inline void vadduhs( VectorRegister d, VectorRegister a, VectorRegister b); 2220 inline void vaddfp( VectorRegister d, VectorRegister a, VectorRegister b); 2221 inline void vsubcuw( VectorRegister d, VectorRegister a, VectorRegister b); 2222 inline void vsubshs( VectorRegister d, VectorRegister a, VectorRegister b); 2223 inline void vsubsbs( VectorRegister d, VectorRegister a, VectorRegister b); 2224 inline void vsubsws( VectorRegister d, VectorRegister a, VectorRegister b); 2225 inline void vsububm( VectorRegister d, VectorRegister a, VectorRegister b); 2226 inline void vsubuwm( VectorRegister d, VectorRegister a, VectorRegister b); 2227 inline void vsubuhm( VectorRegister d, VectorRegister a, VectorRegister b); 2228 inline void vsubudm( VectorRegister d, VectorRegister a, VectorRegister b); 2229 inline void vsububs( VectorRegister d, VectorRegister a, VectorRegister b); 2230 inline void vsubuws( VectorRegister d, VectorRegister a, VectorRegister b); 2231 inline void vsubuhs( VectorRegister d, VectorRegister a, VectorRegister b); 2232 inline void vsubfp( VectorRegister d, VectorRegister a, VectorRegister b); 2233 inline void vmulesb( VectorRegister d, VectorRegister a, VectorRegister b); 2234 inline void vmuleub( VectorRegister d, VectorRegister a, VectorRegister b); 2235 inline void vmulesh( VectorRegister d, VectorRegister a, VectorRegister b); 2236 inline void vmuleuh( VectorRegister d, VectorRegister a, VectorRegister b); 2237 inline void vmulosb( VectorRegister d, VectorRegister a, VectorRegister b); 2238 inline void vmuloub( VectorRegister d, VectorRegister a, VectorRegister b); 2239 inline void vmulosh( VectorRegister d, VectorRegister a, VectorRegister b); 2240 inline void vmulosw( VectorRegister d, VectorRegister a, VectorRegister b); 2241 inline void vmulouh( VectorRegister d, VectorRegister a, VectorRegister b); 2242 inline void vmuluwm( VectorRegister d, VectorRegister a, VectorRegister b); 2243 inline void vmhaddshs(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2244 inline void vmhraddshs(VectorRegister d,VectorRegister a, VectorRegister b, VectorRegister c); 2245 inline void vmladduhm(VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2246 inline void vmsubuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2247 inline void vmsummbm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2248 inline void vmsumshm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2249 inline void vmsumshs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2250 inline void vmsumuhm( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2251 inline void vmsumuhs( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2252 inline void vmaddfp( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2253 inline void vsumsws( VectorRegister d, VectorRegister a, VectorRegister b); 2254 inline void vsum2sws( VectorRegister d, VectorRegister a, VectorRegister b); 2255 inline void vsum4sbs( VectorRegister d, VectorRegister a, VectorRegister b); 2256 inline void vsum4ubs( VectorRegister d, VectorRegister a, VectorRegister b); 2257 inline void vsum4shs( VectorRegister d, VectorRegister a, VectorRegister b); 2258 inline void vavgsb( VectorRegister d, VectorRegister a, VectorRegister b); 2259 inline void vavgsw( VectorRegister d, VectorRegister a, VectorRegister b); 2260 inline void vavgsh( VectorRegister d, VectorRegister a, VectorRegister b); 2261 inline void vavgub( VectorRegister d, VectorRegister a, VectorRegister b); 2262 inline void vavguw( VectorRegister d, VectorRegister a, VectorRegister b); 2263 inline void vavguh( VectorRegister d, VectorRegister a, VectorRegister b); 2264 inline void vmaxsb( VectorRegister d, VectorRegister a, VectorRegister b); 2265 inline void vmaxsw( VectorRegister d, VectorRegister a, VectorRegister b); 2266 inline void vmaxsh( VectorRegister d, VectorRegister a, VectorRegister b); 2267 inline void vmaxub( VectorRegister d, VectorRegister a, VectorRegister b); 2268 inline void vmaxuw( VectorRegister d, VectorRegister a, VectorRegister b); 2269 inline void vmaxuh( VectorRegister d, VectorRegister a, VectorRegister b); 2270 inline void vminsb( VectorRegister d, VectorRegister a, VectorRegister b); 2271 inline void vminsw( VectorRegister d, VectorRegister a, VectorRegister b); 2272 inline void vminsh( VectorRegister d, VectorRegister a, VectorRegister b); 2273 inline void vminub( VectorRegister d, VectorRegister a, VectorRegister b); 2274 inline void vminuw( VectorRegister d, VectorRegister a, VectorRegister b); 2275 inline void vminuh( VectorRegister d, VectorRegister a, VectorRegister b); 2276 inline void vcmpequb( VectorRegister d, VectorRegister a, VectorRegister b); 2277 inline void vcmpequh( VectorRegister d, VectorRegister a, VectorRegister b); 2278 inline void vcmpequw( VectorRegister d, VectorRegister a, VectorRegister b); 2279 inline void vcmpgtsh( VectorRegister d, VectorRegister a, VectorRegister b); 2280 inline void vcmpgtsb( VectorRegister d, VectorRegister a, VectorRegister b); 2281 inline void vcmpgtsw( VectorRegister d, VectorRegister a, VectorRegister b); 2282 inline void vcmpgtub( VectorRegister d, VectorRegister a, VectorRegister b); 2283 inline void vcmpgtuh( VectorRegister d, VectorRegister a, VectorRegister b); 2284 inline void vcmpgtuw( VectorRegister d, VectorRegister a, VectorRegister b); 2285 inline void vcmpequb_(VectorRegister d, VectorRegister a, VectorRegister b); 2286 inline void vcmpequh_(VectorRegister d, VectorRegister a, VectorRegister b); 2287 inline void vcmpequw_(VectorRegister d, VectorRegister a, VectorRegister b); 2288 inline void vcmpgtsh_(VectorRegister d, VectorRegister a, VectorRegister b); 2289 inline void vcmpgtsb_(VectorRegister d, VectorRegister a, VectorRegister b); 2290 inline void vcmpgtsw_(VectorRegister d, VectorRegister a, VectorRegister b); 2291 inline void vcmpgtub_(VectorRegister d, VectorRegister a, VectorRegister b); 2292 inline void vcmpgtuh_(VectorRegister d, VectorRegister a, VectorRegister b); 2293 inline void vcmpgtuw_(VectorRegister d, VectorRegister a, VectorRegister b); 2294 inline void vand( VectorRegister d, VectorRegister a, VectorRegister b); 2295 inline void vandc( VectorRegister d, VectorRegister a, VectorRegister b); 2296 inline void vnor( VectorRegister d, VectorRegister a, VectorRegister b); 2297 inline void vor( VectorRegister d, VectorRegister a, VectorRegister b); 2298 inline void vmr( VectorRegister d, VectorRegister a); 2299 inline void vxor( VectorRegister d, VectorRegister a, VectorRegister b); 2300 inline void vrld( VectorRegister d, VectorRegister a, VectorRegister b); 2301 inline void vrlb( VectorRegister d, VectorRegister a, VectorRegister b); 2302 inline void vrlw( VectorRegister d, VectorRegister a, VectorRegister b); 2303 inline void vrlh( VectorRegister d, VectorRegister a, VectorRegister b); 2304 inline void vslb( VectorRegister d, VectorRegister a, VectorRegister b); 2305 inline void vskw( VectorRegister d, VectorRegister a, VectorRegister b); 2306 inline void vslh( VectorRegister d, VectorRegister a, VectorRegister b); 2307 inline void vsrb( VectorRegister d, VectorRegister a, VectorRegister b); 2308 inline void vsrw( VectorRegister d, VectorRegister a, VectorRegister b); 2309 inline void vsrh( VectorRegister d, VectorRegister a, VectorRegister b); 2310 inline void vsrab( VectorRegister d, VectorRegister a, VectorRegister b); 2311 inline void vsraw( VectorRegister d, VectorRegister a, VectorRegister b); 2312 inline void vsrah( VectorRegister d, VectorRegister a, VectorRegister b); 2313 inline void vpopcntb( VectorRegister d, VectorRegister b); 2314 inline void vpopcnth( VectorRegister d, VectorRegister b); 2315 inline void vpopcntw( VectorRegister d, VectorRegister b); 2316 inline void vpopcntd( VectorRegister d, VectorRegister b); 2317 // Vector Floating-Point not implemented yet 2318 inline void mtvscr( VectorRegister b); 2319 inline void mfvscr( VectorRegister d); 2320 2321 // Vector-Scalar (VSX) instructions. 2322 inline void lxv( VectorSRegister d, int si16, Register a); 2323 inline void stxv( VectorSRegister d, int si16, Register a); 2324 inline void lxvl( VectorSRegister d, Register a, Register b); 2325 inline void stxvl( VectorSRegister d, Register a, Register b); 2326 inline void lxvd2x( VectorSRegister d, Register a); 2327 inline void lxvd2x( VectorSRegister d, Register a, Register b); 2328 inline void stxvd2x( VectorSRegister d, Register a); 2329 inline void stxvd2x( VectorSRegister d, Register a, Register b); 2330 inline void mtvrwz( VectorRegister d, Register a); 2331 inline void mfvrwz( Register a, VectorRegister d); 2332 inline void mtvrd( VectorRegister d, Register a); 2333 inline void mfvrd( Register a, VectorRegister d); 2334 inline void xxperm( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2335 inline void xxpermx( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c, int ui3); 2336 inline void xxpermdi( VectorSRegister d, VectorSRegister a, VectorSRegister b, int dm); 2337 inline void xxmrghw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2338 inline void xxmrglw( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2339 inline void mtvsrd( VectorSRegister d, Register a); 2340 inline void mfvsrd( Register d, VectorSRegister a); 2341 inline void mtvsrdd( VectorSRegister d, Register a, Register b); 2342 inline void mtvsrwz( VectorSRegister d, Register a); 2343 inline void mfvsrwz( Register d, VectorSRegister a); 2344 inline void xxspltw( VectorSRegister d, VectorSRegister b, int ui2); 2345 inline void xxlor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2346 inline void xxlxor( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2347 inline void xxleqv( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2348 inline void xxbrd( VectorSRegister d, VectorSRegister b); 2349 inline void xxbrw( VectorSRegister d, VectorSRegister b); 2350 inline void xxland( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2351 inline void xxsel( VectorSRegister d, VectorSRegister a, VectorSRegister b, VectorSRegister c); 2352 inline void xxspltib( VectorSRegister d, int ui8); 2353 inline void xvdivsp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2354 inline void xvdivdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2355 inline void xvabssp( VectorSRegister d, VectorSRegister b); 2356 inline void xvabsdp( VectorSRegister d, VectorSRegister b); 2357 inline void xvnegsp( VectorSRegister d, VectorSRegister b); 2358 inline void xvnegdp( VectorSRegister d, VectorSRegister b); 2359 inline void xvsqrtsp( VectorSRegister d, VectorSRegister b); 2360 inline void xvsqrtdp( VectorSRegister d, VectorSRegister b); 2361 inline void xscvdpspn(VectorSRegister d, VectorSRegister b); 2362 inline void xvadddp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2363 inline void xvsubdp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2364 inline void xvmulsp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2365 inline void xvmuldp( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2366 inline void xvmaddasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2367 inline void xvmaddadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2368 inline void xvmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2369 inline void xvmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2370 inline void xvnmsubasp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2371 inline void xvnmsubadp(VectorSRegister d, VectorSRegister a, VectorSRegister b); 2372 inline void xvrdpi( VectorSRegister d, VectorSRegister b); 2373 inline void xvrdpic( VectorSRegister d, VectorSRegister b); 2374 inline void xvrdpim( VectorSRegister d, VectorSRegister b); 2375 inline void xvrdpip( VectorSRegister d, VectorSRegister b); 2376 2377 // VSX Extended Mnemonics 2378 inline void xxspltd( VectorSRegister d, VectorSRegister a, int x); 2379 inline void xxmrghd( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2380 inline void xxmrgld( VectorSRegister d, VectorSRegister a, VectorSRegister b); 2381 inline void xxswapd( VectorSRegister d, VectorSRegister a); 2382 2383 // Vector-Scalar (VSX) instructions. 2384 inline void mtfprd( FloatRegister d, Register a); 2385 inline void mtfprwa( FloatRegister d, Register a); 2386 inline void mffprd( Register a, FloatRegister d); 2387 2388 // Deliver A Random Number (introduced with POWER9) 2389 inline void darn( Register d, int l = 1 /*L=CRN*/); 2390 2391 // AES (introduced with Power 8) 2392 inline void vcipher( VectorRegister d, VectorRegister a, VectorRegister b); 2393 inline void vcipherlast( VectorRegister d, VectorRegister a, VectorRegister b); 2394 inline void vncipher( VectorRegister d, VectorRegister a, VectorRegister b); 2395 inline void vncipherlast(VectorRegister d, VectorRegister a, VectorRegister b); 2396 inline void vsbox( VectorRegister d, VectorRegister a); 2397 2398 // SHA (introduced with Power 8) 2399 inline void vshasigmad(VectorRegister d, VectorRegister a, bool st, int six); 2400 inline void vshasigmaw(VectorRegister d, VectorRegister a, bool st, int six); 2401 2402 // Vector Binary Polynomial Multiplication (introduced with Power 8) 2403 inline void vpmsumb( VectorRegister d, VectorRegister a, VectorRegister b); 2404 inline void vpmsumd( VectorRegister d, VectorRegister a, VectorRegister b); 2405 inline void vpmsumh( VectorRegister d, VectorRegister a, VectorRegister b); 2406 inline void vpmsumw( VectorRegister d, VectorRegister a, VectorRegister b); 2407 2408 // Vector Permute and Xor (introduced with Power 8) 2409 inline void vpermxor( VectorRegister d, VectorRegister a, VectorRegister b, VectorRegister c); 2410 2411 // The following encoders use r0 as second operand. These instructions 2412 // read r0 as '0'. 2413 inline void lwzx( Register d, Register s2); 2414 inline void lwz( Register d, int si16); 2415 inline void lwax( Register d, Register s2); 2416 inline void lwa( Register d, int si16); 2417 inline void lwbrx(Register d, Register s2); 2418 inline void lhzx( Register d, Register s2); 2419 inline void lhz( Register d, int si16); 2420 inline void lhax( Register d, Register s2); 2421 inline void lha( Register d, int si16); 2422 inline void lhbrx(Register d, Register s2); 2423 inline void lbzx( Register d, Register s2); 2424 inline void lbz( Register d, int si16); 2425 inline void ldx( Register d, Register s2); 2426 inline void ld( Register d, int si16); 2427 inline void ld( Register d, ByteSize si16); 2428 inline void ldbrx(Register d, Register s2); 2429 inline void stwx( Register d, Register s2); 2430 inline void stw( Register d, int si16); 2431 inline void stwbrx( Register d, Register s2); 2432 inline void sthx( Register d, Register s2); 2433 inline void sth( Register d, int si16); 2434 inline void sthbrx( Register d, Register s2); 2435 inline void stbx( Register d, Register s2); 2436 inline void stb( Register d, int si16); 2437 inline void stdx( Register d, Register s2); 2438 inline void std( Register d, int si16); 2439 inline void stdbrx( Register d, Register s2); 2440 2441 // PPC 2, section 3.2.1 Instruction Cache Instructions 2442 inline void icbi( Register s2); 2443 // PPC 2, section 3.2.2 Data Cache Instructions 2444 //inlinevoid dcba( Register s2); // Instruction for embedded processor only. 2445 inline void dcbz( Register s2); 2446 inline void dcbst( Register s2); 2447 inline void dcbf( Register s2); 2448 // dcache read hint 2449 inline void dcbt( Register s2); 2450 inline void dcbtct( Register s2, int ct); 2451 inline void dcbtds( Register s2, int ds); 2452 // dcache write hint 2453 inline void dcbtst( Register s2); 2454 inline void dcbtstct(Register s2, int ct); 2455 2456 // Atomics: use ra0mem to disallow R0 as base. 2457 inline void lbarx_unchecked(Register d, Register b, int eh1); 2458 inline void lharx_unchecked(Register d, Register b, int eh1); 2459 inline void lwarx_unchecked(Register d, Register b, int eh1); 2460 inline void ldarx_unchecked(Register d, Register b, int eh1); 2461 inline void lqarx_unchecked(Register d, Register b, int eh1); 2462 inline void lbarx( Register d, Register b, bool hint_exclusive_access); 2463 inline void lharx( Register d, Register b, bool hint_exclusive_access); 2464 inline void lwarx( Register d, Register b, bool hint_exclusive_access); 2465 inline void ldarx( Register d, Register b, bool hint_exclusive_access); 2466 inline void lqarx( Register d, Register b, bool hint_exclusive_access); 2467 inline void stbcx_(Register s, Register b); 2468 inline void sthcx_(Register s, Register b); 2469 inline void stwcx_(Register s, Register b); 2470 inline void stdcx_(Register s, Register b); 2471 inline void stqcx_(Register s, Register b); 2472 inline void lfs( FloatRegister d, int si16); 2473 inline void lfsx( FloatRegister d, Register b); 2474 inline void lfd( FloatRegister d, int si16); 2475 inline void lfdx( FloatRegister d, Register b); 2476 inline void stfs( FloatRegister s, int si16); 2477 inline void stfsx( FloatRegister s, Register b); 2478 inline void stfd( FloatRegister s, int si16); 2479 inline void stfdx( FloatRegister s, Register b); 2480 inline void lvebx( VectorRegister d, Register s2); 2481 inline void lvehx( VectorRegister d, Register s2); 2482 inline void lvewx( VectorRegister d, Register s2); 2483 inline void lvx( VectorRegister d, Register s2); 2484 inline void lvxl( VectorRegister d, Register s2); 2485 inline void stvebx(VectorRegister d, Register s2); 2486 inline void stvehx(VectorRegister d, Register s2); 2487 inline void stvewx(VectorRegister d, Register s2); 2488 inline void stvx( VectorRegister d, Register s2); 2489 inline void stvxl( VectorRegister d, Register s2); 2490 inline void lvsl( VectorRegister d, Register s2); 2491 inline void lvsr( VectorRegister d, Register s2); 2492 2493 // Endianness specific concatenation of 2 loaded vectors. 2494 inline void load_perm(VectorRegister perm, Register addr); 2495 inline void vec_perm(VectorRegister first_dest, VectorRegister second, VectorRegister perm); 2496 inline void vec_perm(VectorRegister dest, VectorRegister first, VectorRegister second, VectorRegister perm); 2497 2498 // RegisterOrConstant versions. 2499 // These emitters choose between the versions using two registers and 2500 // those with register and immediate, depending on the content of roc. 2501 // If the constant is not encodable as immediate, instructions to 2502 // load the constant are emitted beforehand. Store instructions need a 2503 // tmp reg if the constant is not encodable as immediate. 2504 // Size unpredictable. 2505 void ld( Register d, RegisterOrConstant roc, Register s1 = noreg); 2506 void lwa( Register d, RegisterOrConstant roc, Register s1 = noreg); 2507 void lwz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2508 void lha( Register d, RegisterOrConstant roc, Register s1 = noreg); 2509 void lhz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2510 void lbz( Register d, RegisterOrConstant roc, Register s1 = noreg); 2511 void std( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2512 void stw( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2513 void sth( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2514 void stb( Register d, RegisterOrConstant roc, Register s1 = noreg, Register tmp = noreg); 2515 void add( Register d, Register s, RegisterOrConstant roc); 2516 void add( Register d, RegisterOrConstant roc, Register s) { add(d, s, roc); } 2517 void sub( Register d, Register s, RegisterOrConstant roc); 2518 void xorr(Register d, Register s, RegisterOrConstant roc); 2519 void xorr(Register d, RegisterOrConstant roc, Register s) { xorr(d, s, roc); } 2520 void cmpw(ConditionRegister d, Register s, RegisterOrConstant roc); 2521 void cmpd(ConditionRegister d, Register s, RegisterOrConstant roc); 2522 // Load pointer d from s1+roc. 2523 void ld_ptr(Register d, RegisterOrConstant roc, Register s1 = noreg) { ld(d, roc, s1); } 2524 2525 // Emit several instructions to load a 64 bit constant. This issues a fixed 2526 // instruction pattern so that the constant can be patched later on. 2527 enum { 2528 load_const_size = 5 * BytesPerInstWord 2529 }; 2530 void load_const(Register d, long a, Register tmp = noreg); 2531 inline void load_const(Register d, void* a, Register tmp = noreg); 2532 inline void load_const(Register d, Label& L, Register tmp = noreg); 2533 inline void load_const(Register d, AddressLiteral& a, Register tmp = noreg); 2534 inline void load_const32(Register d, int i); // load signed int (patchable) 2535 2536 // Load a 64 bit constant, optimized, not identifiable. 2537 // Tmp can be used to increase ILP. Set return_simm16_rest = true to get a 2538 // 16 bit immediate offset. This is useful if the offset can be encoded in 2539 // a succeeding instruction. 2540 int load_const_optimized(Register d, long a, Register tmp = noreg, bool return_simm16_rest = false); 2541 inline int load_const_optimized(Register d, void* a, Register tmp = noreg, bool return_simm16_rest = false) { 2542 return load_const_optimized(d, (long)(unsigned long)a, tmp, return_simm16_rest); 2543 } 2544 2545 // If return_simm16_rest, the return value needs to get added afterwards. 2546 int add_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false); 2547 inline int add_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2548 return add_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2549 } 2550 2551 // If return_simm16_rest, the return value needs to get added afterwards. 2552 inline int sub_const_optimized(Register d, Register s, long x, Register tmp = R0, bool return_simm16_rest = false) { 2553 return add_const_optimized(d, s, -x, tmp, return_simm16_rest); 2554 } 2555 inline int sub_const_optimized(Register d, Register s, void* a, Register tmp = R0, bool return_simm16_rest = false) { 2556 return sub_const_optimized(d, s, (long)(unsigned long)a, tmp, return_simm16_rest); 2557 } 2558 2559 // Creation 2560 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 2561 #ifdef CHECK_DELAY 2562 delay_state = no_delay; 2563 #endif 2564 } 2565 2566 // Testing 2567 #ifndef PRODUCT 2568 void test_asm(); 2569 #endif 2570 }; 2571 2572 2573 #endif // CPU_PPC_ASSEMBLER_PPC_HPP