1 /*
2 * Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_HPP
28
29 #include "asm/assembler.hpp"
30 #include "oops/accessDecorators.hpp"
31 #include "utilities/macros.hpp"
32
33 // MacroAssembler extends Assembler by a few frequently used macros.
34
35 class ciTypeArray;
36 class OopMap;
37
38 class MacroAssembler: public Assembler {
39 public:
40 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
41
42 // Indicates whether and, if so, which registers must be preserved when calling runtime code.
43 enum PreservationLevel {
44 PRESERVATION_NONE,
45 PRESERVATION_FRAME_LR,
46 PRESERVATION_FRAME_LR_GP_REGS,
47 PRESERVATION_FRAME_LR_GP_FP_REGS
48 };
49
50 //
51 // Optimized instruction emitters
52 //
53
54 inline static int largeoffset_si16_si16_hi(int si31) { return (si31 + (1<<15)) >> 16; }
55 inline static int largeoffset_si16_si16_lo(int si31) { return si31 - (((si31 + (1<<15)) >> 16) << 16); }
56
57 // load d = *[a+si31]
58 // Emits several instructions if the offset is not encodable in one instruction.
59 void ld_largeoffset_unchecked(Register d, int si31, Register a, int emit_filler_nop);
60 void ld_largeoffset (Register d, int si31, Register a, int emit_filler_nop);
61 inline static bool is_ld_largeoffset(address a);
62 inline static int get_ld_largeoffset_offset(address a);
63
64 inline void round_to(Register r, int modulus);
65
66 // Load/store with type given by parameter.
67 void load_sized_value( Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes, bool is_signed);
68 void store_sized_value(Register dst, RegisterOrConstant offs, Register base, size_t size_in_bytes);
69
70 // Move register if destination register and target register are different
71 inline void mr_if_needed(Register rd, Register rs);
72 inline void fmr_if_needed(FloatRegister rd, FloatRegister rs);
73 // This is dedicated for emitting scheduled mach nodes. For better
74 // readability of the ad file I put it here.
75 // Endgroups are not needed if
76 // - the scheduler is off
77 // - the scheduler found that there is a natural group end, in that
78 // case it reduced the size of the instruction used in the test
79 // yielding 'needed'.
80 inline void endgroup_if_needed(bool needed);
81
82 // Memory barriers.
83 inline void membar(int bits);
84 inline void release();
85 inline void acquire();
86 inline void fence();
87
88 // nop padding
89 void align(int modulus, int max = 252, int rem = 0);
90
91 // Align prefix opcode to make sure it's not on the last word of a
92 // 64-byte block.
93 //
94 // Note: do not call align_prefix() in a .ad file (e.g. ppc.ad). Instead
95 // add ins_alignment(2) to the instruct definition and implement the
96 // compute_padding() method of the instruct node to use
97 // compute_prefix_padding(). See loadConI32Node::compute_padding() in
98 // ppc.ad for an example.
99 void align_prefix();
100
101 //
102 // Constants, loading constants, TOC support
103 //
104
105 // Address of the global TOC.
106 inline static address global_toc();
107 // Offset of given address to the global TOC.
108 inline static int offset_to_global_toc(const address addr);
109
110 // Address of TOC of the current method.
111 inline address method_toc();
112 // Offset of given address to TOC of the current method.
113 inline int offset_to_method_toc(const address addr);
114
115 // Global TOC.
116 void calculate_address_from_global_toc(Register dst, address addr,
117 bool hi16 = true, bool lo16 = true,
118 bool add_relocation = true, bool emit_dummy_addr = false,
119 bool add_addr_to_reloc = true);
120 void calculate_address_from_global_toc(Register dst, Label& addr,
121 bool hi16 = true, bool lo16 = true,
122 bool add_relocation = true, bool emit_dummy_addr = false) {
123 calculate_address_from_global_toc(dst, target(addr), hi16, lo16, add_relocation, emit_dummy_addr, false);
124 }
125 inline void calculate_address_from_global_toc_hi16only(Register dst, address addr) {
126 calculate_address_from_global_toc(dst, addr, true, false);
127 };
128 inline void calculate_address_from_global_toc_lo16only(Register dst, address addr) {
129 calculate_address_from_global_toc(dst, addr, false, true);
130 };
131
132 inline static bool is_calculate_address_from_global_toc_at(address a, address bound);
133 // Returns address of first instruction in sequence.
134 static address patch_calculate_address_from_global_toc_at(address a, address bound, address addr);
135 static address get_address_of_calculate_address_from_global_toc_at(address a, address addr);
136
137 #ifdef _LP64
138 // Patch narrow oop constant.
139 inline static bool is_set_narrow_oop(address a, address bound);
140 // Returns address of first instruction in sequence.
141 static address patch_set_narrow_oop(address a, address bound, narrowOop data);
142 static narrowOop get_narrow_oop(address a, address bound);
143 #endif
144
145 inline static bool is_load_const_at(address a);
146
147 // Emits an oop const to the constant pool, loads the constant, and
148 // sets a relocation info with address current_pc.
149 // Returns true if successful.
150 bool load_const_from_method_toc(Register dst, AddressLiteral& a, Register toc, bool fixed_size = false);
151
152 static bool is_load_const_from_method_toc_at(address a);
153 static int get_offset_of_load_const_from_method_toc_at(address a);
154
155 // Get the 64 bit constant from a `load_const' sequence.
156 static long get_const(address load_const);
157
158 // Patch the 64 bit constant of a `load_const' sequence. This is a
159 // low level procedure. It neither flushes the instruction cache nor
160 // is it atomic.
161 static void patch_const(address load_const, long x);
162
163 // Metadata in code that we have to keep track of.
164 AddressLiteral allocate_metadata_address(Metadata* obj); // allocate_index
165 AddressLiteral constant_metadata_address(Metadata* obj); // find_index
166 // Oops used directly in compiled code are stored in the constant pool,
167 // and loaded from there.
168 // Allocate new entry for oop in constant pool. Generate relocation.
169 AddressLiteral allocate_oop_address(jobject obj);
170 // Find oop obj in constant pool. Return relocation with it's index.
171 AddressLiteral constant_oop_address(jobject obj);
172
173 // Find oop in constant pool and emit instructions to load it.
174 // Uses constant_oop_address.
175 inline void set_oop_constant(jobject obj, Register d);
176 // Same as load_address.
177 inline void set_oop (AddressLiteral obj_addr, Register d);
178
179 //
180 // branch, jump
181 //
182 // set dst to -1, 0, +1 as follows: if CCR0bi is "greater than", dst is set to 1,
183 // if CCR0bi is "equal", dst is set to 0, otherwise it's set to -1.
184 void inline set_cmp3(Register dst);
185 // set dst to (treat_unordered_like_less ? -1 : +1)
186 void inline set_cmpu3(Register dst, bool treat_unordered_like_less);
187 // Branch-free implementation to convert !=0 to 1.
188 void inline normalize_bool(Register dst, Register temp = R0, bool is_64bit = false);
189
190 inline void pd_patch_instruction(address branch, address target, const char* file, int line);
191 NOT_PRODUCT(static void pd_print_patched_instruction(address branch);)
192
193 // Conditional far branch for destinations encodable in 24+2 bits.
194 // Same interface as bc, e.g. no inverse boint-field.
195 enum {
196 bc_far_optimize_not = 0,
197 bc_far_optimize_on_relocate = 1
198 };
199 // optimize: flag for telling the conditional far branch to optimize
200 // itself when relocated.
201 void bc_far(int boint, int biint, Label& dest, int optimize);
202 void bc_far_optimized(int boint, int biint, Label& dest); // 1 or 2 instructions
203 // Relocation of conditional far branches.
204 static bool is_bc_far_at(address instruction_addr);
205 static address get_dest_of_bc_far_at(address instruction_addr);
206 static void set_dest_of_bc_far_at(address instruction_addr, address dest);
207 private:
208 static bool inline is_bc_far_variant1_at(address instruction_addr);
209 static bool inline is_bc_far_variant2_at(address instruction_addr);
210 static bool inline is_bc_far_variant3_at(address instruction_addr);
211 public:
212
213 // Convenience bc_far versions.
214 inline void blt_far(ConditionRegister crx, Label& L, int optimize);
215 inline void bgt_far(ConditionRegister crx, Label& L, int optimize);
216 inline void beq_far(ConditionRegister crx, Label& L, int optimize);
217 inline void bso_far(ConditionRegister crx, Label& L, int optimize);
218 inline void bge_far(ConditionRegister crx, Label& L, int optimize);
219 inline void ble_far(ConditionRegister crx, Label& L, int optimize);
220 inline void bne_far(ConditionRegister crx, Label& L, int optimize);
221 inline void bns_far(ConditionRegister crx, Label& L, int optimize);
222
223 // Emit, identify and patch a NOT mt-safe patchable 64 bit absolute call/jump.
224 private:
225 enum {
226 bxx64_patchable_instruction_count = (2/*load_codecache_const*/ + 3/*5load_const*/ + 1/*mtctr*/ + 1/*bctrl*/),
227 bxx64_patchable_size = bxx64_patchable_instruction_count * BytesPerInstWord,
228 bxx64_patchable_ret_addr_offset = bxx64_patchable_size
229 };
230 void bxx64_patchable(address target, relocInfo::relocType rt, bool link);
231 static bool is_bxx64_patchable_at( address instruction_addr, bool link);
232 // Does the instruction use a pc-relative encoding of the destination?
233 static bool is_bxx64_patchable_pcrelative_at( address instruction_addr, bool link);
234 static bool is_bxx64_patchable_variant1_at( address instruction_addr, bool link);
235 // Load destination relative to global toc.
236 static bool is_bxx64_patchable_variant1b_at( address instruction_addr, bool link);
237 static bool is_bxx64_patchable_variant2_at( address instruction_addr, bool link);
238 static void set_dest_of_bxx64_patchable_at( address instruction_addr, address target, bool link);
239 static address get_dest_of_bxx64_patchable_at(address instruction_addr, bool link);
240
241 public:
242 // call
243 enum {
244 bl64_patchable_instruction_count = bxx64_patchable_instruction_count,
245 bl64_patchable_size = bxx64_patchable_size,
246 bl64_patchable_ret_addr_offset = bxx64_patchable_ret_addr_offset
247 };
248 inline void bl64_patchable(address target, relocInfo::relocType rt) {
249 bxx64_patchable(target, rt, /*link=*/true);
250 }
251 inline static bool is_bl64_patchable_at(address instruction_addr) {
252 return is_bxx64_patchable_at(instruction_addr, /*link=*/true);
253 }
254 inline static bool is_bl64_patchable_pcrelative_at(address instruction_addr) {
255 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/true);
256 }
257 inline static void set_dest_of_bl64_patchable_at(address instruction_addr, address target) {
258 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/true);
259 }
260 inline static address get_dest_of_bl64_patchable_at(address instruction_addr) {
261 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/true);
262 }
263 // jump
264 enum {
265 b64_patchable_instruction_count = bxx64_patchable_instruction_count,
266 b64_patchable_size = bxx64_patchable_size,
267 };
268 inline void b64_patchable(address target, relocInfo::relocType rt) {
269 bxx64_patchable(target, rt, /*link=*/false);
270 }
271 inline static bool is_b64_patchable_at(address instruction_addr) {
272 return is_bxx64_patchable_at(instruction_addr, /*link=*/false);
273 }
274 inline static bool is_b64_patchable_pcrelative_at(address instruction_addr) {
275 return is_bxx64_patchable_pcrelative_at(instruction_addr, /*link=*/false);
276 }
277 inline static void set_dest_of_b64_patchable_at(address instruction_addr, address target) {
278 set_dest_of_bxx64_patchable_at(instruction_addr, target, /*link=*/false);
279 }
280 inline static address get_dest_of_b64_patchable_at(address instruction_addr) {
281 return get_dest_of_bxx64_patchable_at(instruction_addr, /*link=*/false);
282 }
283
284 //
285 // Support for frame handling
286 //
287
288 // some ABI-related functions
289
290 // Clobbers all volatile, (non-floating-point) general-purpose registers for debugging purposes.
291 // This is especially useful for making calls to the JRT in places in which this hasn't been done before;
292 // e.g. with the introduction of LRBs (load reference barriers) for concurrent garbage collection.
293 void clobber_volatile_gprs(Register excluded_register = noreg) NOT_DEBUG_RETURN;
294 // Load bad values into registers that are nonvolatile according to the ABI except R16_thread and R29_TOC.
295 // This is done after vthread preemption and before vthread resume.
296 void clobber_nonvolatile_registers() NOT_DEBUG_RETURN;
297 void clobber_carg_stack_slots(Register tmp);
298
299 void save_nonvolatile_gprs( Register dst_base, int offset);
300 void restore_nonvolatile_gprs(Register src_base, int offset);
301
302 enum {
303 num_volatile_gp_regs = 11,
304 num_volatile_fp_regs = 14,
305 num_volatile_regs = num_volatile_gp_regs + num_volatile_fp_regs
306 };
307
308 void save_volatile_gprs( Register dst_base, int offset,
309 bool include_fp_regs = true, bool include_R3_RET_reg = true);
310 void restore_volatile_gprs(Register src_base, int offset,
311 bool include_fp_regs = true, bool include_R3_RET_reg = true);
312 void save_LR(Register tmp);
313 void restore_LR(Register tmp);
314 void save_LR_CR(Register tmp); // tmp contains LR on return.
315 void restore_LR_CR(Register tmp);
316
317 // Get current PC using bl-next-instruction trick.
318 address get_PC_trash_LR(Register result);
319
320 // Resize current frame either relatively wrt to current SP or absolute.
321 void resize_frame(Register offset, Register tmp);
322 void resize_frame(int offset, Register tmp);
323 void resize_frame_absolute(Register addr, Register tmp1, Register tmp2);
324
325 // Push a frame of size bytes.
326 void push_frame(Register bytes, Register tmp);
327
328 // Push a frame of size `bytes'. No abi space provided.
329 void push_frame(unsigned int bytes, Register tmp);
330
331 // Push a frame of size `bytes' plus native_abi_reg_args on top.
332 void push_frame_reg_args(unsigned int bytes, Register tmp);
333
334 // Setup up a new C frame with a spill area for non-volatile GPRs and additional
335 // space for local variables
336 void push_frame_reg_args_nonvolatiles(unsigned int bytes, Register tmp);
337
338 // pop current C frame
339 void pop_frame();
340
341 //
342 // Calls
343 //
344
345 private:
346 address _last_calls_return_pc;
347
348 #if defined(ABI_ELFv2)
349 // Generic version of a call to C function.
350 // Updates and returns _last_calls_return_pc.
351 address branch_to(Register function_entry, bool and_link);
352 #else
353 // Generic version of a call to C function via a function descriptor
354 // with variable support for C calling conventions (TOC, ENV, etc.).
355 // updates and returns _last_calls_return_pc.
356 address branch_to(Register function_descriptor, bool and_link, bool save_toc_before_call,
357 bool restore_toc_after_call, bool load_toc_of_callee, bool load_env_of_callee);
358 #endif
359
360 public:
361
362 // Get the pc where the last call will return to. returns _last_calls_return_pc.
363 inline address last_calls_return_pc();
364
365 #if defined(ABI_ELFv2)
366 // Call a C function via a function descriptor and use full C
367 // calling conventions. Updates and returns _last_calls_return_pc.
368 address call_c(Register function_entry);
369 // For tail calls: only branch, don't link, so callee returns to caller of this function.
370 address call_c_and_return_to_caller(Register function_entry);
371 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none);
372 #else
373 // Call a C function via a function descriptor and use full C
374 // calling conventions. Updates and returns _last_calls_return_pc.
375 address call_c(Register function_descriptor);
376 // For tail calls: only branch, don't link, so callee returns to caller of this function.
377 address call_c_and_return_to_caller(Register function_descriptor);
378 address call_c(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt);
379 address call_c(address function_entry, relocInfo::relocType rt = relocInfo::none) {
380 return call_c((const FunctionDescriptor*)function_entry, rt);
381 }
382 address call_c_using_toc(const FunctionDescriptor* function_descriptor, relocInfo::relocType rt,
383 Register toc);
384 #endif
385
386 static int ic_check_size();
387 int ic_check(int end_alignment);
388
389 protected:
390
391 // It is imperative that all calls into the VM are handled via the
392 // call_VM macros. They make sure that the stack linkage is setup
393 // correctly. call_VM's correspond to ENTRY/ENTRY_X entry points
394 // while call_VM_leaf's correspond to LEAF entry points.
395 //
396 // This is the base routine called by the different versions of
397 // call_VM. The interpreter may customize this version by overriding
398 // it for its purposes (e.g., to save/restore additional registers
399 // when doing a VM call).
400 //
401 // If no last_java_sp is specified (noreg) then SP will be used instead.
402 virtual void call_VM_base(
403 // where an oop-result ends up if any; use noreg otherwise
404 Register oop_result,
405 // to set up last_Java_frame in stubs; use noreg otherwise
406 Register last_java_sp,
407 // the entry point
408 address entry_point,
409 // flag which indicates if exception should be checked
410 bool check_exception = true,
411 Label* last_java_pc = nullptr
412 );
413
414 // Support for VM calls. This is the base routine called by the
415 // different versions of call_VM_leaf. The interpreter may customize
416 // this version by overriding it for its purposes (e.g., to
417 // save/restore additional registers when doing a VM call).
418 void call_VM_leaf_base(address entry_point);
419
420 public:
421 // Call into the VM.
422 // Passes the thread pointer (in R3_ARG1) as a prepended argument.
423 // Makes sure oop return values are visible to the GC.
424 void call_VM(Register oop_result, address entry_point, bool check_exceptions = true, Label* last_java_pc = nullptr);
425 void call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions = true);
426 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
427 void call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, Register arg3, bool check_exceptions = true);
428 void call_VM_leaf(address entry_point);
429 void call_VM_leaf(address entry_point, Register arg_1);
430 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
431 void call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
432
433 // Call a stub function via a function descriptor, but don't save
434 // TOC before call, don't setup TOC and ENV for call, and don't
435 // restore TOC after call. Updates and returns _last_calls_return_pc.
436 inline address call_stub(Register function_entry);
437 inline void call_stub_and_return_to(Register function_entry, Register return_pc);
438
439 void post_call_nop();
440 static bool is_post_call_nop(int instr_bits) {
441 const uint32_t nineth_bit = opp_u_field(1, 9, 9);
442 const uint32_t opcode_mask = 0b111110 << OPCODE_SHIFT;
443 const uint32_t pcn_mask = opcode_mask | nineth_bit;
444 return (instr_bits & pcn_mask) == (Assembler::CMPLI_OPCODE | nineth_bit);
445 }
446
447 //
448 // Java utilities
449 //
450
451 // Read from the polling page, its address is already in a register.
452 inline void load_from_polling_page(Register polling_page_address, int offset = 0);
453 // Check whether instruction is a read access to the polling page
454 // which was emitted by load_from_polling_page(..).
455 static bool is_load_from_polling_page(int instruction, void* ucontext/*may be nullptr*/,
456 address* polling_address_ptr = nullptr);
457
458 // Support for null-checks
459 //
460 // Generates code that causes a null OS exception if the content of reg is null.
461 // If the accessed location is M[reg + offset] and the offset is known, provide the
462 // offset. No explicit code generation is needed if the offset is within a certain
463 // range (0 <= offset <= page_size).
464
465 // Stack overflow checking
466 void bang_stack_with_offset(int offset);
467
468 // If instruction is a stack bang of the form ld, stdu, or
469 // stdux, return the banged address. Otherwise, return 0.
470 static address get_stack_bang_address(int instruction, void* ucontext);
471
472 // Check for reserved stack access in method being exited. If the reserved
473 // stack area was accessed, protect it again and throw StackOverflowError.
474 void reserved_stack_check(Register return_pc);
475
476 // Atomics
477 // CmpxchgX sets condition register to cmpX(current, compare).
478 // (flag == ne) => (dest_current_value != compare_value), (!swapped)
479 // (flag == eq) => (dest_current_value == compare_value), ( swapped)
480 static inline bool cmpxchgx_hint_acquire_lock() { return true; }
481 // The stxcx will probably not be succeeded by a releasing store.
482 static inline bool cmpxchgx_hint_release_lock() { return false; }
483 static inline bool cmpxchgx_hint_atomic_update() { return false; }
484
485 // Cmpxchg semantics
486 enum {
487 MemBarNone = 0,
488 MemBarRel = 1,
489 MemBarAcq = 2,
490 MemBarFenceAfter = 4 // use powers of 2
491 };
492 private:
493 // Helper functions for word/sub-word atomics.
494 void atomic_get_and_modify_generic(Register dest_current_value, Register exchange_value,
495 Register addr_base, Register tmp1, Register tmp2, Register tmp3,
496 bool cmpxchgx_hint, bool is_add, int size);
497 void cmpxchg_loop_body(ConditionRegister flag, Register dest_current_value,
498 RegisterOrConstant compare_value, Register exchange_value,
499 Register addr_base, Register tmp1, Register tmp2,
500 Label &retry, Label &failed, bool cmpxchgx_hint, int size);
501 void cmpxchg_generic(ConditionRegister flag, Register dest_current_value,
502 RegisterOrConstant compare_value, Register exchange_value,
503 Register addr_base, Register tmp1, Register tmp2,
504 int semantics, bool cmpxchgx_hint, Register int_flag_success,
505 Label* failed_ext, bool contention_hint, bool weak, int size);
506 public:
507 // Temps and addr_base are killed if processor does not support Power 8 instructions.
508 // Result will be sign extended.
509 void getandsetb(Register dest_current_value, Register exchange_value, Register addr_base,
510 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
511 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 1);
512 }
513 // Temps and addr_base are killed if processor does not support Power 8 instructions.
514 // Result will be sign extended.
515 void getandseth(Register dest_current_value, Register exchange_value, Register addr_base,
516 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
517 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, false, 2);
518 }
519 void getandsetw(Register dest_current_value, Register exchange_value, Register addr_base,
520 bool cmpxchgx_hint) {
521 atomic_get_and_modify_generic(dest_current_value, exchange_value, addr_base, noreg, noreg, noreg, cmpxchgx_hint, false, 4);
522 }
523 void getandsetd(Register dest_current_value, Register exchange_value, Register addr_base,
524 bool cmpxchgx_hint);
525 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
526 // Result will be sign extended.
527 void getandaddb(Register dest_current_value, Register inc_value, Register addr_base,
528 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
529 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 1);
530 }
531 // tmp2/3 and addr_base are killed if processor does not support Power 8 instructions (tmp1 is always needed).
532 // Result will be sign extended.
533 void getandaddh(Register dest_current_value, Register inc_value, Register addr_base,
534 Register tmp1, Register tmp2, Register tmp3, bool cmpxchgx_hint) {
535 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, tmp2, tmp3, cmpxchgx_hint, true, 2);
536 }
537 void getandaddw(Register dest_current_value, Register inc_value, Register addr_base,
538 Register tmp1, bool cmpxchgx_hint) {
539 atomic_get_and_modify_generic(dest_current_value, inc_value, addr_base, tmp1, noreg, noreg, cmpxchgx_hint, true, 4);
540 }
541 void getandaddd(Register dest_current_value, Register exchange_value, Register addr_base,
542 Register tmp, bool cmpxchgx_hint);
543 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
544 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
545 void cmpxchgb(ConditionRegister flag, Register dest_current_value,
546 RegisterOrConstant compare_value, Register exchange_value,
547 Register addr_base, Register tmp1, Register tmp2,
548 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
549 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
550 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, tmp1, tmp2,
551 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 1);
552 }
553 // Temps, addr_base and exchange_value are killed if processor does not support Power 8 instructions.
554 // compare_value must be at least 32 bit sign extended. Result will be sign extended.
555 void cmpxchgh(ConditionRegister flag, Register dest_current_value,
556 RegisterOrConstant compare_value, Register exchange_value,
557 Register addr_base, Register tmp1, Register tmp2,
558 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
559 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
560 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, tmp1, tmp2,
561 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 2);
562 }
563 void cmpxchgw(ConditionRegister flag, Register dest_current_value,
564 RegisterOrConstant compare_value, Register exchange_value,
565 Register addr_base,
566 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
567 Label* failed = nullptr, bool contention_hint = false, bool weak = false) {
568 cmpxchg_generic(flag, dest_current_value, compare_value, exchange_value, addr_base, noreg, noreg,
569 semantics, cmpxchgx_hint, int_flag_success, failed, contention_hint, weak, 4);
570 }
571 void cmpxchgd(ConditionRegister flag, Register dest_current_value,
572 RegisterOrConstant compare_value, Register exchange_value,
573 Register addr_base,
574 int semantics, bool cmpxchgx_hint = false, Register int_flag_success = noreg,
575 Label* failed = nullptr, bool contention_hint = false, bool weak = false);
576
577 // interface method calling
578 void lookup_interface_method(Register recv_klass,
579 Register intf_klass,
580 RegisterOrConstant itable_index,
581 Register method_result,
582 Register temp_reg, Register temp2_reg,
583 Label& no_such_interface,
584 bool return_method = true);
585
586 // virtual method calling
587 void lookup_virtual_method(Register recv_klass,
588 RegisterOrConstant vtable_index,
589 Register method_result);
590
591 // Test sub_klass against super_klass, with fast and slow paths.
592
593 // The fast path produces a tri-state answer: yes / no / maybe-slow.
594 // One of the three labels can be null, meaning take the fall-through.
595 // If super_check_offset is -1, the value is loaded up from super_klass.
596 // No registers are killed, except temp_reg and temp2_reg.
597 // If super_check_offset is not -1, temp2_reg is not used and can be noreg.
598 void check_klass_subtype_fast_path(Register sub_klass,
599 Register super_klass,
600 Register temp1_reg,
601 Register temp2_reg,
602 Label* L_success,
603 Label* L_failure,
604 Label* L_slow_path = nullptr, // default fall through
605 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
606
607 // The rest of the type check; must be wired to a corresponding fast path.
608 // It does not repeat the fast path logic, so don't use it standalone.
609 // The temp_reg can be noreg, if no temps are available.
610 // It can also be sub_klass or super_klass, meaning it's OK to kill that one.
611 // Updates the sub's secondary super cache as necessary.
612 void check_klass_subtype_slow_path(Register sub_klass,
613 Register super_klass,
614 Register temp1_reg,
615 Register temp2_reg,
616 Label* L_success = nullptr,
617 Register result_reg = noreg);
618
619 // Simplified, combined version, good for typical uses.
620 // Falls through on failure.
621 void check_klass_subtype(Register sub_klass,
622 Register super_klass,
623 Register temp1_reg,
624 Register temp2_reg,
625 Label& L_success);
626
627 void repne_scan(Register addr, Register value, Register count, Register scratch);
628
629 // As above, but with a constant super_klass.
630 // The result is in Register result, not the condition codes.
631 void lookup_secondary_supers_table(Register r_sub_klass,
632 Register r_super_klass,
633 Register temp1,
634 Register temp2,
635 Register temp3,
636 Register temp4,
637 Register result,
638 u1 super_klass_slot);
639
640 void verify_secondary_supers_table(Register r_sub_klass,
641 Register r_super_klass,
642 Register result,
643 Register temp1,
644 Register temp2,
645 Register temp3);
646
647 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
648 Register r_array_base,
649 Register r_array_index,
650 Register r_bitmap,
651 Register result,
652 Register temp1);
653
654 void clinit_barrier(Register klass,
655 Register thread,
656 Label* L_fast_path = nullptr,
657 Label* L_slow_path = nullptr);
658
659 // Method handle support (JSR 292).
660 RegisterOrConstant argument_offset(RegisterOrConstant arg_slot, Register temp_reg, int extra_slot_offset = 0);
661
662 void push_cont_fastpath();
663 void pop_cont_fastpath();
664 void inc_held_monitor_count(Register tmp);
665 void dec_held_monitor_count(Register tmp);
666 void atomically_flip_locked_state(bool is_unlock, Register obj, Register tmp, Label& failed, int semantics);
667 void lightweight_lock(Register box, Register obj, Register t1, Register t2, Label& slow);
668 void lightweight_unlock(Register obj, Register t1, Label& slow);
669
670 // allocation (for C1)
671 void tlab_allocate(
672 Register obj, // result: pointer to object after successful allocation
673 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
674 int con_size_in_bytes, // object size in bytes if known at compile time
675 Register t1, // temp register
676 Label& slow_case // continuation point if fast allocation fails
677 );
678
679 enum { trampoline_stub_size = 6 * 4 };
680 address emit_trampoline_stub(int destination_toc_offset, int insts_call_instruction_offset, Register Rtoc = noreg);
681
682 void compiler_fast_lock_object(ConditionRegister flag, Register oop, Register box,
683 Register tmp1, Register tmp2, Register tmp3);
684
685 void compiler_fast_unlock_object(ConditionRegister flag, Register oop, Register box,
686 Register tmp1, Register tmp2, Register tmp3);
687
688 void compiler_fast_lock_lightweight_object(ConditionRegister flag, Register oop, Register box,
689 Register tmp1, Register tmp2, Register tmp3);
690
691 void compiler_fast_unlock_lightweight_object(ConditionRegister flag, Register oop, Register box,
692 Register tmp1, Register tmp2, Register tmp3);
693
694 // Check if safepoint requested and if so branch
695 void safepoint_poll(Label& slow_path, Register temp, bool at_return, bool in_nmethod);
696
697 void resolve_jobject(Register value, Register tmp1, Register tmp2,
698 MacroAssembler::PreservationLevel preservation_level);
699 void resolve_global_jobject(Register value, Register tmp1, Register tmp2,
700 MacroAssembler::PreservationLevel preservation_level);
701
702 // Support for managing the JavaThread pointer (i.e.; the reference to
703 // thread-local information).
704
705 // Support for last Java frame (but use call_VM instead where possible):
706 // access R16_thread->last_Java_sp.
707 void set_last_Java_frame(Register last_java_sp, Register last_Java_pc);
708 void reset_last_Java_frame(bool check_last_java_sp = true);
709 void set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, Label* jpc = nullptr);
710
711 // Read vm result from thread: oop_result = R16_thread->result;
712 void get_vm_result (Register oop_result);
713 void get_vm_result_2(Register metadata_result);
714
715 static bool needs_explicit_null_check(intptr_t offset);
716 static bool uses_implicit_null_check(void* address);
717
718 // Trap-instruction-based checks.
719 // Range checks can be distinguished from zero checks as they check 32 bit,
720 // zero checks all 64 bits (tw, td).
721 inline void trap_null_check(Register a, trap_to_bits cmp = traptoEqual);
722 static bool is_trap_null_check(int x) {
723 return is_tdi(x, traptoEqual, -1/*any reg*/, 0) ||
724 is_tdi(x, traptoGreaterThanUnsigned, -1/*any reg*/, 0);
725 }
726
727 inline void trap_ic_miss_check(Register a, Register b);
728 static bool is_trap_ic_miss_check(int x) {
729 return is_td(x, traptoGreaterThanUnsigned | traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/);
730 }
731
732 // Implicit or explicit null check, jumps to static address exception_entry.
733 inline void null_check_throw(Register a, int offset, Register temp_reg, address exception_entry);
734 inline void null_check(Register a, int offset, Label *Lis_null); // implicit only if Lis_null not provided
735
736 // Access heap oop, handle encoding and GC barriers.
737 // Some GC barriers call C so use needs_frame = true if an extra frame is needed at the current call site.
738 inline void access_store_at(BasicType type, DecoratorSet decorators,
739 Register base, RegisterOrConstant ind_or_offs, Register val,
740 Register tmp1, Register tmp2, Register tmp3,
741 MacroAssembler::PreservationLevel preservation_level);
742 inline void access_load_at(BasicType type, DecoratorSet decorators,
743 Register base, RegisterOrConstant ind_or_offs, Register dst,
744 Register tmp1, Register tmp2,
745 MacroAssembler::PreservationLevel preservation_level, Label *L_handle_null = nullptr);
746
747 public:
748 // Specify tmp1 for better code in certain compressed oops cases. Specify Label to bail out on null oop.
749 // tmp1, tmp2 and needs_frame are used with decorators ON_PHANTOM_OOP_REF or ON_WEAK_OOP_REF.
750 inline void load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
751 Register tmp1, Register tmp2,
752 MacroAssembler::PreservationLevel preservation_level,
753 DecoratorSet decorators = 0, Label *L_handle_null = nullptr);
754
755 inline void store_heap_oop(Register d, RegisterOrConstant offs, Register s1,
756 Register tmp1, Register tmp2, Register tmp3,
757 MacroAssembler::PreservationLevel preservation_level, DecoratorSet decorators = 0);
758
759 // Encode/decode heap oop. Oop may not be null, else en/decoding goes wrong.
760 // src == d allowed.
761 inline Register encode_heap_oop_not_null(Register d, Register src = noreg);
762 inline Register decode_heap_oop_not_null(Register d, Register src = noreg);
763
764 // Null allowed.
765 inline Register encode_heap_oop(Register d, Register src); // Prefer null check in GC barrier!
766 inline void decode_heap_oop(Register d);
767
768 // Load/Store klass oop from klass field. Compress.
769 void load_klass(Register dst, Register src);
770 void load_klass_check_null(Register dst, Register src, Label* is_null = nullptr);
771 void store_klass(Register dst_oop, Register klass, Register tmp = R0);
772 void store_klass_gap(Register dst_oop, Register val = noreg); // Will store 0 if val not specified.
773
774 void resolve_oop_handle(Register result, Register tmp1, Register tmp2,
775 MacroAssembler::PreservationLevel preservation_level);
776 void resolve_weak_handle(Register result, Register tmp1, Register tmp2,
777 MacroAssembler::PreservationLevel preservation_level);
778 void load_method_holder(Register holder, Register method);
779
780 static int instr_size_for_decode_klass_not_null();
781 void decode_klass_not_null(Register dst, Register src = noreg);
782 Register encode_klass_not_null(Register dst, Register src = noreg);
783
784 // SIGTRAP-based range checks for arrays.
785 inline void trap_range_check_l(Register a, Register b);
786 inline void trap_range_check_l(Register a, int si16);
787 static bool is_trap_range_check_l(int x) {
788 return (is_tw (x, traptoLessThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
789 is_twi(x, traptoLessThanUnsigned, -1/*any reg*/) );
790 }
791 inline void trap_range_check_le(Register a, int si16);
792 static bool is_trap_range_check_le(int x) {
793 return is_twi(x, traptoEqual | traptoLessThanUnsigned, -1/*any reg*/);
794 }
795 inline void trap_range_check_g(Register a, int si16);
796 static bool is_trap_range_check_g(int x) {
797 return is_twi(x, traptoGreaterThanUnsigned, -1/*any reg*/);
798 }
799 inline void trap_range_check_ge(Register a, Register b);
800 inline void trap_range_check_ge(Register a, int si16);
801 static bool is_trap_range_check_ge(int x) {
802 return (is_tw (x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/, -1/*any reg*/) ||
803 is_twi(x, traptoEqual | traptoGreaterThanUnsigned, -1/*any reg*/) );
804 }
805 static bool is_trap_range_check(int x) {
806 return is_trap_range_check_l(x) || is_trap_range_check_le(x) ||
807 is_trap_range_check_g(x) || is_trap_range_check_ge(x);
808 }
809
810 void clear_memory_unrolled(Register base_ptr, int cnt_dwords, Register tmp = R0, int offset = 0);
811 void clear_memory_constlen(Register base_ptr, int cnt_dwords, Register tmp = R0);
812 void clear_memory_doubleword(Register base_ptr, Register cnt_dwords, Register tmp = R0, long const_cnt = -1);
813
814 // Emitters for BigInteger.multiplyToLen intrinsic.
815 inline void multiply64(Register dest_hi, Register dest_lo,
816 Register x, Register y);
817 void add2_with_carry(Register dest_hi, Register dest_lo,
818 Register src1, Register src2);
819 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
820 Register y, Register y_idx, Register z,
821 Register carry, Register product_high, Register product,
822 Register idx, Register kdx, Register tmp);
823 void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
824 Register yz_idx, Register idx, Register carry,
825 Register product_high, Register product, Register tmp,
826 int offset);
827 void multiply_128_x_128_loop(Register x_xstart,
828 Register y, Register z,
829 Register yz_idx, Register idx, Register carry,
830 Register product_high, Register product,
831 Register carry2, Register tmp);
832 void muladd(Register out, Register in, Register offset, Register len, Register k,
833 Register tmp1, Register tmp2, Register carry);
834 void multiply_to_len(Register x, Register xlen,
835 Register y, Register ylen,
836 Register z,
837 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5,
838 Register tmp6, Register tmp7, Register tmp8, Register tmp9, Register tmp10,
839 Register tmp11, Register tmp12, Register tmp13);
840
841 // Emitters for CRC32 calculation.
842 // A note on invertCRC:
843 // Unfortunately, internal representation of crc differs between CRC32 and CRC32C.
844 // CRC32 holds it's current crc value in the externally visible representation.
845 // CRC32C holds it's current crc value in internal format, ready for updating.
846 // Thus, the crc value must be bit-flipped before updating it in the CRC32 case.
847 // In the CRC32C case, it must be bit-flipped when it is given to the outside world (getValue()).
848 // The bool invertCRC parameter indicates whether bit-flipping is required before updates.
849 void load_reverse_32(Register dst, Register src);
850 int crc32_table_columns(Register table, Register tc0, Register tc1, Register tc2, Register tc3);
851 void fold_byte_crc32(Register crc, Register val, Register table, Register tmp);
852 void update_byte_crc32(Register crc, Register val, Register table);
853 void update_byteLoop_crc32(Register crc, Register buf, Register len, Register table,
854 Register data, bool loopAlignment);
855 void update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
856 Register t0, Register t1, Register t2, Register t3,
857 Register tc0, Register tc1, Register tc2, Register tc3);
858 void kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
859 Register t0, Register t1, Register t2, Register t3,
860 Register tc0, Register tc1, Register tc2, Register tc3,
861 bool invertCRC);
862 void kernel_crc32_vpmsum(Register crc, Register buf, Register len, Register constants,
863 Register t0, Register t1, Register t2, Register t3, Register t4,
864 Register t5, Register t6, bool invertCRC);
865 void kernel_crc32_vpmsum_aligned(Register crc, Register buf, Register len, Register constants,
866 Register t0, Register t1, Register t2, Register t3, Register t4,
867 Register t5, Register t6);
868 // Version which internally decides what to use.
869 void crc32(Register crc, Register buf, Register len, Register t0, Register t1, Register t2,
870 Register t3, Register t4, Register t5, Register t6, Register t7, bool is_crc32c);
871
872 void kernel_crc32_singleByteReg(Register crc, Register val, Register table,
873 bool invertCRC);
874
875 // SHA-2 auxiliary functions and public interfaces
876 private:
877 void sha256_deque(const VectorRegister src,
878 const VectorRegister dst1, const VectorRegister dst2, const VectorRegister dst3);
879 void sha256_load_h_vec(const VectorRegister a, const VectorRegister e, const Register hptr);
880 void sha256_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
881 void sha256_load_w_plus_k_vec(const Register buf_in, const VectorRegister* ws,
882 const int total_ws, const Register k, const VectorRegister* kpws,
883 const int total_kpws);
884 void sha256_calc_4w(const VectorRegister w0, const VectorRegister w1,
885 const VectorRegister w2, const VectorRegister w3, const VectorRegister kpw0,
886 const VectorRegister kpw1, const VectorRegister kpw2, const VectorRegister kpw3,
887 const Register j, const Register k);
888 void sha256_update_sha_state(const VectorRegister a, const VectorRegister b,
889 const VectorRegister c, const VectorRegister d, const VectorRegister e,
890 const VectorRegister f, const VectorRegister g, const VectorRegister h,
891 const Register hptr);
892
893 void sha512_load_w_vec(const Register buf_in, const VectorRegister* ws, const int total_ws);
894 void sha512_update_sha_state(const Register state, const VectorRegister* hs, const int total_hs);
895 void sha512_round(const VectorRegister* hs, const int total_hs, int& h_cnt, const VectorRegister kpw);
896 void sha512_load_h_vec(const Register state, const VectorRegister* hs, const int total_hs);
897 void sha512_calc_2w(const VectorRegister w0, const VectorRegister w1,
898 const VectorRegister w2, const VectorRegister w3,
899 const VectorRegister w4, const VectorRegister w5,
900 const VectorRegister w6, const VectorRegister w7,
901 const VectorRegister kpw0, const VectorRegister kpw1, const Register j,
902 const VectorRegister vRb, const Register k);
903
904 public:
905 void sha256(bool multi_block);
906 void sha512(bool multi_block);
907
908 void cache_wb(Address line);
909 void cache_wbsync(bool is_presync);
910
911 //
912 // Debugging
913 //
914
915 // assert on cr0
916 void asm_assert(bool check_equal, const char* msg);
917 void asm_assert_eq(const char* msg) { asm_assert(true, msg); }
918 void asm_assert_ne(const char* msg) { asm_assert(false, msg); }
919
920 private:
921 void asm_assert_mems_zero(bool check_equal, int size, int mem_offset, Register mem_base,
922 const char* msg) NOT_DEBUG_RETURN;
923
924 public:
925
926 void asm_assert_mem8_is_zero(int mem_offset, Register mem_base, const char* msg) {
927 asm_assert_mems_zero(true, 8, mem_offset, mem_base, msg);
928 }
929 void asm_assert_mem8_isnot_zero(int mem_offset, Register mem_base, const char* msg) {
930 asm_assert_mems_zero(false, 8, mem_offset, mem_base, msg);
931 }
932
933 // Calls verify_oop. If UseCompressedOops is on, decodes the oop.
934 // Preserves reg.
935 void verify_coop(Register reg, const char*);
936 // Emit code to verify that reg contains a valid oop if +VerifyOops is set.
937 void verify_oop(Register reg, const char* s = "broken oop");
938 void verify_oop_addr(RegisterOrConstant offs, Register base, const char* s = "contains broken oop");
939
940 // TODO: verify method and klass metadata (compare against vptr?)
941 void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
942 void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line) {}
943
944 // Convenience method returning function entry. For the ELFv1 case
945 // creates function descriptor at the current address and returns
946 // the pointer to it. For the ELFv2 case returns the current address.
947 inline address function_entry();
948
949 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
950 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
951
952 private:
953 void stop(int type, const char* msg);
954
955 public:
956 enum {
957 stop_stop = 0,
958 stop_untested = 1,
959 stop_unimplemented = 2,
960 stop_shouldnotreachhere = 3,
961 stop_msg_present = -0x8000
962 };
963
964 // Prints msg, dumps registers and stops execution.
965 void stop (const char* msg = nullptr) { stop(stop_stop, msg); }
966 void untested (const char* msg = nullptr) { stop(stop_untested, msg); }
967 void unimplemented (const char* msg = nullptr) { stop(stop_unimplemented, msg); }
968 void should_not_reach_here(const char* msg = nullptr) { stop(stop_shouldnotreachhere, msg); }
969
970 void zap_from_to(Register low, int before, Register high, int after, Register val, Register addr) PRODUCT_RETURN;
971 };
972
973 // class SkipIfEqualZero:
974 //
975 // Instantiating this class will result in assembly code being output that will
976 // jump around any code emitted between the creation of the instance and it's
977 // automatic destruction at the end of a scope block, depending on the value of
978 // the flag passed to the constructor, which will be checked at run-time.
979 class SkipIfEqualZero : public StackObj {
980 private:
981 MacroAssembler* _masm;
982 Label _label;
983
984 public:
985 // 'Temp' is a temp register that this object can use (and trash).
986 explicit SkipIfEqualZero(MacroAssembler*, Register temp, const bool* flag_addr);
987 static void skip_to_label_if_equal_zero(MacroAssembler*, Register temp,
988 const bool* flag_addr, Label& label);
989 ~SkipIfEqualZero();
990 };
991
992 #endif // CPU_PPC_MACROASSEMBLER_PPC_HPP