1 /*
2 * Copyright (c) 2002, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2012, 2024 SAP SE. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
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24 */
25
26 #ifndef CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP
27 #define CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP
28
29 #include "asm/assembler.inline.hpp"
30 #include "asm/macroAssembler.hpp"
31 #include "asm/codeBuffer.hpp"
32 #include "code/codeCache.hpp"
33 #include "gc/shared/barrierSet.hpp"
34 #include "gc/shared/barrierSetAssembler.hpp"
35 #include "oops/accessDecorators.hpp"
36 #include "oops/compressedOops.hpp"
37 #include "runtime/os.inline.hpp"
38 #include "runtime/safepointMechanism.hpp"
39 #include "runtime/vm_version.hpp"
40 #include "utilities/powerOfTwo.hpp"
41
42 inline bool MacroAssembler::is_ld_largeoffset(address a) {
43 const int inst1 = *(int *)a;
44 const int inst2 = *(int *)(a+4);
45 return (is_ld(inst1)) ||
46 (is_addis(inst1) && is_ld(inst2) && inv_ra_field(inst2) == inv_rt_field(inst1));
47 }
48
49 inline int MacroAssembler::get_ld_largeoffset_offset(address a) {
50 assert(MacroAssembler::is_ld_largeoffset(a), "must be ld with large offset");
51
52 const int inst1 = *(int *)a;
53 if (is_ld(inst1)) {
54 return inv_d1_field(inst1);
55 } else {
56 const int inst2 = *(int *)(a+4);
57 return (inv_d1_field(inst1) << 16) + inv_d1_field(inst2);
58 }
59 }
60
61 inline void MacroAssembler::round_to(Register r, int modulus) {
62 assert(is_power_of_2((jlong)modulus), "must be power of 2");
63 addi(r, r, modulus-1);
64 clrrdi(r, r, log2i_exact((jlong)modulus));
65 }
66
67 // Move register if destination register and target register are different.
68 inline void MacroAssembler::mr_if_needed(Register rd, Register rs) {
69 if (rs != rd) mr(rd, rs);
70 }
71 inline void MacroAssembler::fmr_if_needed(FloatRegister rd, FloatRegister rs) {
72 if (rs != rd) fmr(rd, rs);
73 }
74 inline void MacroAssembler::endgroup_if_needed(bool needed) {
75 if (needed) {
76 endgroup();
77 }
78 }
79
80 inline void MacroAssembler::membar(int bits) {
81 // Comment: Usage of elemental_membar(bits) is not recommended for Power 8.
82 // If elemental_membar(bits) is used, disable optimization of acquire-release
83 // (Matcher::post_membar_release where we use PPC64_ONLY(xop == Op_MemBarRelease ||))!
84 if (bits & StoreLoad) { sync(); }
85 else if (bits) { lwsync(); }
86 }
87 inline void MacroAssembler::release() { membar(LoadStore | StoreStore); }
88 inline void MacroAssembler::acquire() { membar(LoadLoad | LoadStore); }
89 inline void MacroAssembler::fence() { membar(LoadLoad | LoadStore | StoreLoad | StoreStore); }
90
91 // Address of the global TOC.
92 inline address MacroAssembler::global_toc() {
93 return CodeCache::low_bound();
94 }
95
96 // Offset of given address to the global TOC.
97 inline int MacroAssembler::offset_to_global_toc(const address addr) {
98 intptr_t offset = (intptr_t)addr - (intptr_t)MacroAssembler::global_toc();
99 assert(Assembler::is_uimm((long)offset, 31), "must be in range");
100 return (int)offset;
101 }
102
103 // Address of current method's TOC.
104 inline address MacroAssembler::method_toc() {
105 return code()->consts()->start();
106 }
107
108 // Offset of given address to current method's TOC.
109 inline int MacroAssembler::offset_to_method_toc(address addr) {
110 intptr_t offset = (intptr_t)addr - (intptr_t)method_toc();
111 assert(Assembler::is_uimm((long)offset, 31), "must be in range");
112 return (int)offset;
113 }
114
115 inline bool MacroAssembler::is_calculate_address_from_global_toc_at(address a, address bound) {
116 const address inst2_addr = a;
117 const int inst2 = *(int *) a;
118
119 // The relocation points to the second instruction, the addi.
120 if (!is_addi(inst2)) return false;
121
122 // The addi reads and writes the same register dst.
123 const int dst = inv_rt_field(inst2);
124 if (inv_ra_field(inst2) != dst) return false;
125
126 // Now, find the preceding addis which writes to dst.
127 int inst1 = 0;
128 address inst1_addr = inst2_addr - BytesPerInstWord;
129 while (inst1_addr >= bound) {
130 inst1 = *(int *) inst1_addr;
131 if (is_addis(inst1) && inv_rt_field(inst1) == dst) {
132 // stop, found the addis which writes dst
133 break;
134 }
135 inst1_addr -= BytesPerInstWord;
136 }
137
138 if (!(inst1 == 0 || inv_ra_field(inst1) == 29 /* R29 */)) return false;
139 return is_addis(inst1);
140 }
141
142 #ifdef _LP64
143 // Detect narrow oop constants.
144 inline bool MacroAssembler::is_set_narrow_oop(address a, address bound) {
145 const address inst2_addr = a;
146 const int inst2 = *(int *)a;
147 // The relocation points to the second instruction, the ori.
148 if (!is_ori(inst2)) return false;
149
150 // The ori reads and writes the same register dst.
151 const int dst = inv_rta_field(inst2);
152 if (inv_rs_field(inst2) != dst) return false;
153
154 // Now, find the preceding addis which writes to dst.
155 int inst1 = 0;
156 address inst1_addr = inst2_addr - BytesPerInstWord;
157 while (inst1_addr >= bound) {
158 inst1 = *(int *) inst1_addr;
159 if (is_lis(inst1) && inv_rs_field(inst1) == dst) return true;
160 inst1_addr -= BytesPerInstWord;
161 }
162 return false;
163 }
164 #endif
165
166
167 inline bool MacroAssembler::is_load_const_at(address a) {
168 const int* p_inst = (int *) a;
169 bool b = is_lis(*p_inst++);
170 if (is_ori(*p_inst)) {
171 p_inst++;
172 b = b && is_rldicr(*p_inst++); // TODO: could be made more precise: `sldi'!
173 b = b && is_oris(*p_inst++);
174 b = b && is_ori(*p_inst);
175 } else if (is_lis(*p_inst)) {
176 p_inst++;
177 b = b && is_ori(*p_inst++);
178 b = b && is_ori(*p_inst);
179 // TODO: could enhance reliability by adding is_insrdi
180 } else return false;
181 return b;
182 }
183
184 inline void MacroAssembler::set_oop_constant(jobject obj, Register d) {
185 set_oop(constant_oop_address(obj), d);
186 }
187
188 inline void MacroAssembler::set_oop(AddressLiteral obj_addr, Register d) {
189 assert(obj_addr.rspec().type() == relocInfo::oop_type, "must be an oop reloc");
190 load_const(d, obj_addr);
191 }
192
193 inline void MacroAssembler::pd_patch_instruction(address branch, address target, const char* file, int line) {
194 jint& stub_inst = *(jint*) branch;
195 stub_inst = patched_branch(target - branch, stub_inst, 0);
196 }
197
198 // Relocation of conditional far branches.
199 inline bool MacroAssembler::is_bc_far_variant1_at(address instruction_addr) {
200 // Variant 1, the 1st instruction contains the destination address:
201 //
202 // bcxx DEST
203 // nop
204 //
205 const int instruction_1 = *(int*)(instruction_addr);
206 const int instruction_2 = *(int*)(instruction_addr + 4);
207 return is_bcxx(instruction_1) &&
208 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) != (intptr_t)(instruction_addr + 2*4)) &&
209 is_nop(instruction_2);
210 }
211
212 // Relocation of conditional far branches.
213 inline bool MacroAssembler::is_bc_far_variant2_at(address instruction_addr) {
214 // Variant 2, the 2nd instruction contains the destination address:
215 //
216 // b!cxx SKIP
217 // bxx DEST
218 // SKIP:
219 //
220 const int instruction_1 = *(int*)(instruction_addr);
221 const int instruction_2 = *(int*)(instruction_addr + 4);
222 return is_bcxx(instruction_1) &&
223 (inv_bd_field(instruction_1, (intptr_t)instruction_addr) == (intptr_t)(instruction_addr + 2*4)) &&
224 is_bxx(instruction_2);
225 }
226
227 // Relocation for conditional branches
228 inline bool MacroAssembler::is_bc_far_variant3_at(address instruction_addr) {
229 // Variant 3, far cond branch to the next instruction, already patched to nops:
230 //
231 // nop
232 // endgroup
233 // SKIP/DEST:
234 //
235 const int instruction_1 = *(int*)(instruction_addr);
236 const int instruction_2 = *(int*)(instruction_addr + 4);
237 return is_nop(instruction_1) &&
238 is_endgroup(instruction_2);
239 }
240
241 // set dst to -1, 0, +1 as follows: if CCR0bi is "greater than", dst is set to 1,
242 // if CCR0bi is "equal", dst is set to 0, otherwise it's set to -1.
243 inline void MacroAssembler::set_cmp3(Register dst) {
244 assert_different_registers(dst, R0);
245 // P10, prefer using setbc instructions
246 if (VM_Version::has_brw()) {
247 setbc(R0, CCR0, Assembler::greater); // Set 1 to R0 if CCR0bi is "greater than", otherwise 0
248 setnbc(dst, CCR0, Assembler::less); // Set -1 to dst if CCR0bi is "less than", otherwise 0
249 } else {
250 mfcr(R0); // copy CR register to R0
251 srwi(dst, R0, 30); // copy the first two bits to dst
252 srawi(R0, R0, 31); // move the first bit to last position - sign extended
253 }
254 orr(dst, dst, R0); // dst | R0 will be -1, 0, or +1
255 }
256
257 // set dst to (treat_unordered_like_less ? -1 : +1)
258 inline void MacroAssembler::set_cmpu3(Register dst, bool treat_unordered_like_less) {
259 if (treat_unordered_like_less) {
260 cror(CCR0, Assembler::less, CCR0, Assembler::summary_overflow); // treat unordered like less
261 } else {
262 cror(CCR0, Assembler::greater, CCR0, Assembler::summary_overflow); // treat unordered like greater
263 }
264 set_cmp3(dst);
265 }
266
267 // Branch-free implementation to convert !=0 to 1
268 // Set register dst to 1 if dst is non-zero. Uses setbcr instruction on Power10.
269 inline void MacroAssembler::normalize_bool(Register dst, Register temp, bool is_64bit) {
270
271 if (VM_Version::has_brw()) {
272 if (is_64bit) {
273 cmpdi(CCR0, dst, 0);
274 } else {
275 cmpwi(CCR0, dst, 0);
276 }
277 setbcr(dst, CCR0, Assembler::equal);
278 } else {
279 assert_different_registers(temp, dst);
280 neg(temp, dst);
281 orr(temp, dst, temp);
282 if (is_64bit) {
283 srdi(dst, temp, 63);
284 } else {
285 srwi(dst, temp, 31);
286 }
287 }
288 }
289
290 // Convenience bc_far versions
291 inline void MacroAssembler::blt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, less), L, optimize); }
292 inline void MacroAssembler::bgt_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, greater), L, optimize); }
293 inline void MacroAssembler::beq_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, equal), L, optimize); }
294 inline void MacroAssembler::bso_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs1, bi0(crx, summary_overflow), L, optimize); }
295 inline void MacroAssembler::bge_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, less), L, optimize); }
296 inline void MacroAssembler::ble_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, greater), L, optimize); }
297 inline void MacroAssembler::bne_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, equal), L, optimize); }
298 inline void MacroAssembler::bns_far(ConditionRegister crx, Label& L, int optimize) { MacroAssembler::bc_far(bcondCRbiIs0, bi0(crx, summary_overflow), L, optimize); }
299
300 inline address MacroAssembler::call_stub(Register function_entry) {
301 mtctr(function_entry);
302 bctrl();
303 return pc();
304 }
305
306 inline void MacroAssembler::call_stub_and_return_to(Register function_entry, Register return_pc) {
307 assert_different_registers(function_entry, return_pc);
308 mtlr(return_pc);
309 mtctr(function_entry);
310 bctr();
311 }
312
313 // Get the pc where the last emitted call will return to.
314 inline address MacroAssembler::last_calls_return_pc() {
315 return _last_calls_return_pc;
316 }
317
318 // Read from the polling page, its address is already in a register.
319 inline void MacroAssembler::load_from_polling_page(Register polling_page_address, int offset) {
320 if (USE_POLL_BIT_ONLY) {
321 int encoding = SafepointMechanism::poll_bit();
322 tdi(traptoGreaterThanUnsigned | traptoEqual, polling_page_address, encoding);
323 } else {
324 ld(R0, offset, polling_page_address);
325 }
326 }
327
328 // Trap-instruction-based checks.
329
330 inline void MacroAssembler::trap_null_check(Register a, trap_to_bits cmp) {
331 assert(TrapBasedNullChecks, "sanity");
332 tdi(cmp, a/*reg a*/, 0);
333 }
334
335 inline void MacroAssembler::trap_ic_miss_check(Register a, Register b) {
336 td(traptoGreaterThanUnsigned | traptoLessThanUnsigned, a, b);
337 }
338
339 // Do an explicit null check if access to a+offset will not raise a SIGSEGV.
340 // Either issue a trap instruction that raises SIGTRAP, or do a compare that
341 // branches to exception_entry.
342 // No support for compressed oops (base page of heap). Does not distinguish
343 // loads and stores.
344 inline void MacroAssembler::null_check_throw(Register a, int offset, Register temp_reg,
345 address exception_entry) {
346 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) {
347 if (TrapBasedNullChecks) {
348 assert(UseSIGTRAP, "sanity");
349 trap_null_check(a);
350 } else {
351 Label ok;
352 cmpdi(CCR0, a, 0);
353 bne(CCR0, ok);
354 load_const_optimized(temp_reg, exception_entry);
355 mtctr(temp_reg);
356 bctr();
357 bind(ok);
358 }
359 }
360 }
361
362 inline void MacroAssembler::null_check(Register a, int offset, Label *Lis_null) {
363 if (!ImplicitNullChecks || needs_explicit_null_check(offset) || !os::zero_page_read_protected()) {
364 if (TrapBasedNullChecks) {
365 assert(UseSIGTRAP, "sanity");
366 trap_null_check(a);
367 } else if (Lis_null){
368 Label ok;
369 cmpdi(CCR0, a, 0);
370 beq(CCR0, *Lis_null);
371 }
372 }
373 }
374
375 inline void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators,
376 Register base, RegisterOrConstant ind_or_offs, Register val,
377 Register tmp1, Register tmp2, Register tmp3,
378 MacroAssembler::PreservationLevel preservation_level) {
379 assert((decorators & ~(AS_RAW | IN_HEAP | IN_NATIVE | IS_ARRAY | IS_NOT_NULL |
380 ON_UNKNOWN_OOP_REF | IS_DEST_UNINITIALIZED)) == 0, "unsupported decorator");
381 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
382 bool as_raw = (decorators & AS_RAW) != 0;
383 decorators = AccessInternal::decorator_fixup(decorators, type);
384 if (as_raw) {
385 bs->BarrierSetAssembler::store_at(this, decorators, type,
386 base, ind_or_offs, val,
387 tmp1, tmp2, tmp3, preservation_level);
388 } else {
389 bs->store_at(this, decorators, type,
390 base, ind_or_offs, val,
391 tmp1, tmp2, tmp3, preservation_level);
392 }
393 }
394
395 inline void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators,
396 Register base, RegisterOrConstant ind_or_offs, Register dst,
397 Register tmp1, Register tmp2,
398 MacroAssembler::PreservationLevel preservation_level,
399 Label *L_handle_null) {
400 assert((decorators & ~(AS_RAW | IN_HEAP | IN_NATIVE | IS_ARRAY | IS_NOT_NULL |
401 ON_PHANTOM_OOP_REF | ON_WEAK_OOP_REF)) == 0, "unsupported decorator");
402 BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
403 decorators = AccessInternal::decorator_fixup(decorators, type);
404 bool as_raw = (decorators & AS_RAW) != 0;
405 if (as_raw) {
406 bs->BarrierSetAssembler::load_at(this, decorators, type,
407 base, ind_or_offs, dst,
408 tmp1, tmp2, preservation_level, L_handle_null);
409 } else {
410 bs->load_at(this, decorators, type,
411 base, ind_or_offs, dst,
412 tmp1, tmp2, preservation_level, L_handle_null);
413 }
414 }
415
416 inline void MacroAssembler::load_heap_oop(Register d, RegisterOrConstant offs, Register s1,
417 Register tmp1, Register tmp2,
418 MacroAssembler::PreservationLevel preservation_level,
419 DecoratorSet decorators, Label *L_handle_null) {
420 access_load_at(T_OBJECT, decorators | IN_HEAP, s1, offs, d, tmp1, tmp2,
421 preservation_level, L_handle_null);
422 }
423
424 inline void MacroAssembler::store_heap_oop(Register val, RegisterOrConstant offs, Register base,
425 Register tmp1, Register tmp2, Register tmp3,
426 MacroAssembler::PreservationLevel preservation_level,
427 DecoratorSet decorators) {
428 access_store_at(T_OBJECT, decorators | IN_HEAP, base, offs, val, tmp1, tmp2, tmp3, preservation_level);
429 }
430
431 inline Register MacroAssembler::encode_heap_oop_not_null(Register d, Register src) {
432 Register current = (src != noreg) ? src : d; // Oop to be compressed is in d if no src provided.
433 if (CompressedOops::base_overlaps()) {
434 sub_const_optimized(d, current, CompressedOops::base(), R0);
435 current = d;
436 }
437 if (CompressedOops::shift() != 0) {
438 rldicl(d, current, 64-CompressedOops::shift(), 32); // Clears the upper bits.
439 current = d;
440 }
441 return current; // Encoded oop is in this register.
442 }
443
444 inline Register MacroAssembler::encode_heap_oop(Register d, Register src) {
445 if (CompressedOops::base() != nullptr) {
446 if (VM_Version::has_isel()) {
447 cmpdi(CCR0, src, 0);
448 Register co = encode_heap_oop_not_null(d, src);
449 assert(co == d, "sanity");
450 isel_0(d, CCR0, Assembler::equal);
451 } else {
452 Label isNull;
453 or_(d, src, src); // move and compare 0
454 beq(CCR0, isNull);
455 encode_heap_oop_not_null(d, src);
456 bind(isNull);
457 }
458 return d;
459 } else {
460 return encode_heap_oop_not_null(d, src);
461 }
462 }
463
464 inline Register MacroAssembler::decode_heap_oop_not_null(Register d, Register src) {
465 if (CompressedOops::base_disjoint() && src != noreg && src != d &&
466 CompressedOops::shift() != 0) {
467 load_const_optimized(d, CompressedOops::base(), R0);
468 rldimi(d, src, CompressedOops::shift(), 32-CompressedOops::shift());
469 return d;
470 }
471
472 Register current = (src != noreg) ? src : d; // Compressed oop is in d if no src provided.
473 if (CompressedOops::shift() != 0) {
474 sldi(d, current, CompressedOops::shift());
475 current = d;
476 }
477 if (CompressedOops::base() != nullptr) {
478 add_const_optimized(d, current, CompressedOops::base(), R0);
479 current = d;
480 }
481 return current; // Decoded oop is in this register.
482 }
483
484 inline void MacroAssembler::decode_heap_oop(Register d) {
485 Label isNull;
486 bool use_isel = false;
487 if (CompressedOops::base() != nullptr) {
488 cmpwi(CCR0, d, 0);
489 if (VM_Version::has_isel()) {
490 use_isel = true;
491 } else {
492 beq(CCR0, isNull);
493 }
494 }
495 decode_heap_oop_not_null(d);
496 if (use_isel) {
497 isel_0(d, CCR0, Assembler::equal);
498 }
499 bind(isNull);
500 }
501
502 // SIGTRAP-based range checks for arrays.
503 inline void MacroAssembler::trap_range_check_l(Register a, Register b) {
504 tw (traptoLessThanUnsigned, a/*reg a*/, b/*reg b*/);
505 }
506 inline void MacroAssembler::trap_range_check_l(Register a, int si16) {
507 twi(traptoLessThanUnsigned, a/*reg a*/, si16);
508 }
509 inline void MacroAssembler::trap_range_check_le(Register a, int si16) {
510 twi(traptoEqual | traptoLessThanUnsigned, a/*reg a*/, si16);
511 }
512 inline void MacroAssembler::trap_range_check_g(Register a, int si16) {
513 twi(traptoGreaterThanUnsigned, a/*reg a*/, si16);
514 }
515 inline void MacroAssembler::trap_range_check_ge(Register a, Register b) {
516 tw (traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, b/*reg b*/);
517 }
518 inline void MacroAssembler::trap_range_check_ge(Register a, int si16) {
519 twi(traptoEqual | traptoGreaterThanUnsigned, a/*reg a*/, si16);
520 }
521
522 // unsigned integer multiplication 64*64 -> 128 bits
523 inline void MacroAssembler::multiply64(Register dest_hi, Register dest_lo,
524 Register x, Register y) {
525 mulld(dest_lo, x, y);
526 mulhdu(dest_hi, x, y);
527 }
528
529 #if defined(ABI_ELFv2)
530 inline address MacroAssembler::function_entry() { return pc(); }
531 #else
532 inline address MacroAssembler::function_entry() { return emit_fd(); }
533 #endif
534
535 #endif // CPU_PPC_MACROASSEMBLER_PPC_INLINE_HPP