1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2020, Red Hat Inc. All rights reserved.
4 * Copyright (c) 2020, 2024, Huawei Technologies Co., Ltd. All rights reserved.
5 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
6 *
7 * This code is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 only, as
9 * published by the Free Software Foundation.
10 *
11 * This code is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * version 2 for more details (a copy is included in the LICENSE file that
15 * accompanied this code).
16 *
17 * You should have received a copy of the GNU General Public License version
18 * 2 along with this work; if not, write to the Free Software Foundation,
19 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
20 *
21 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
22 * or visit www.oracle.com if you need additional information or have any
23 * questions.
24 *
25 */
26
27 #ifndef CPU_RISCV_MACROASSEMBLER_RISCV_HPP
28 #define CPU_RISCV_MACROASSEMBLER_RISCV_HPP
29
30 #include "asm/assembler.inline.hpp"
31 #include "code/vmreg.hpp"
32 #include "metaprogramming/enableIf.hpp"
33 #include "oops/compressedOops.hpp"
34 #include "utilities/powerOfTwo.hpp"
35
36 // MacroAssembler extends Assembler by frequently used macros.
37 //
38 // Instructions for which a 'better' code sequence exists depending
39 // on arguments should also go in here.
40
41 class MacroAssembler: public Assembler {
42
43 public:
44
45 MacroAssembler(CodeBuffer* code) : Assembler(code) {}
46
47 void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
48
49 // Alignment
50 int align(int modulus, int extra_offset = 0);
51
52 static inline void assert_alignment(address pc, int alignment = MacroAssembler::instruction_size) {
53 assert(is_aligned(pc, alignment), "bad alignment");
54 }
55
56 // nop
57 void post_call_nop();
58
59 // Stack frame creation/removal
60 // Note that SP must be updated to the right place before saving/restoring RA and FP
61 // because signal based thread suspend/resume could happen asynchronously.
62 void enter() {
63 addi(sp, sp, - 2 * wordSize);
64 sd(ra, Address(sp, wordSize));
65 sd(fp, Address(sp));
66 addi(fp, sp, 2 * wordSize);
67 }
68
69 void leave() {
70 addi(sp, fp, - 2 * wordSize);
71 ld(fp, Address(sp));
72 ld(ra, Address(sp, wordSize));
73 addi(sp, sp, 2 * wordSize);
74 }
75
76
77 // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
78 // The pointer will be loaded into the thread register.
79 void get_thread(Register thread);
80
81 // Support for VM calls
82 //
83 // It is imperative that all calls into the VM are handled via the call_VM macros.
84 // They make sure that the stack linkage is setup correctly. call_VM's correspond
85 // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
86
87 void call_VM(Register oop_result,
88 address entry_point,
89 bool check_exceptions = true);
90 void call_VM(Register oop_result,
91 address entry_point,
92 Register arg_1,
93 bool check_exceptions = true);
94 void call_VM(Register oop_result,
95 address entry_point,
96 Register arg_1, Register arg_2,
97 bool check_exceptions = true);
98 void call_VM(Register oop_result,
99 address entry_point,
100 Register arg_1, Register arg_2, Register arg_3,
101 bool check_exceptions = true);
102
103 // Overloadings with last_Java_sp
104 void call_VM(Register oop_result,
105 Register last_java_sp,
106 address entry_point,
107 int number_of_arguments = 0,
108 bool check_exceptions = true);
109 void call_VM(Register oop_result,
110 Register last_java_sp,
111 address entry_point,
112 Register arg_1,
113 bool check_exceptions = true);
114 void call_VM(Register oop_result,
115 Register last_java_sp,
116 address entry_point,
117 Register arg_1, Register arg_2,
118 bool check_exceptions = true);
119 void call_VM(Register oop_result,
120 Register last_java_sp,
121 address entry_point,
122 Register arg_1, Register arg_2, Register arg_3,
123 bool check_exceptions = true);
124
125 void get_vm_result(Register oop_result, Register java_thread);
126 void get_vm_result_2(Register metadata_result, Register java_thread);
127
128 // These always tightly bind to MacroAssembler::call_VM_leaf_base
129 // bypassing the virtual implementation
130 void call_VM_leaf(address entry_point,
131 int number_of_arguments = 0);
132 void call_VM_leaf(address entry_point,
133 Register arg_0);
134 void call_VM_leaf(address entry_point,
135 Register arg_0, Register arg_1);
136 void call_VM_leaf(address entry_point,
137 Register arg_0, Register arg_1, Register arg_2);
138
139 // These always tightly bind to MacroAssembler::call_VM_base
140 // bypassing the virtual implementation
141 void super_call_VM_leaf(address entry_point, Register arg_0);
142 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1);
143 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2);
144 void super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3);
145
146 // last Java Frame (fills frame anchor)
147 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, address last_java_pc, Register tmp);
148 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Label &last_java_pc, Register tmp);
149 void set_last_Java_frame(Register last_java_sp, Register last_java_fp, Register last_java_pc);
150
151 // thread in the default location (xthread)
152 void reset_last_Java_frame(bool clear_fp);
153
154 virtual void call_VM_leaf_base(
155 address entry_point, // the entry point
156 int number_of_arguments, // the number of arguments to pop after the call
157 Label* retaddr = nullptr
158 );
159
160 virtual void call_VM_leaf_base(
161 address entry_point, // the entry point
162 int number_of_arguments, // the number of arguments to pop after the call
163 Label& retaddr) {
164 call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
165 }
166
167 virtual void call_VM_base( // returns the register containing the thread upon return
168 Register oop_result, // where an oop-result ends up if any; use noreg otherwise
169 Register java_thread, // the thread if computed before ; use noreg otherwise
170 Register last_java_sp, // to set up last_Java_frame in stubs; use noreg otherwise
171 address entry_point, // the entry point
172 int number_of_arguments, // the number of arguments (w/o thread) to pop after the call
173 bool check_exceptions // whether to check for pending exceptions after return
174 );
175
176 void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions);
177
178 virtual void check_and_handle_earlyret(Register java_thread);
179 virtual void check_and_handle_popframe(Register java_thread);
180
181 void resolve_weak_handle(Register result, Register tmp1, Register tmp2);
182 void resolve_oop_handle(Register result, Register tmp1, Register tmp2);
183 void resolve_jobject(Register value, Register tmp1, Register tmp2);
184 void resolve_global_jobject(Register value, Register tmp1, Register tmp2);
185
186 void movoop(Register dst, jobject obj);
187 void mov_metadata(Register dst, Metadata* obj);
188 void bang_stack_size(Register size, Register tmp);
189 void set_narrow_oop(Register dst, jobject obj);
190 void set_narrow_klass(Register dst, Klass* k);
191
192 void load_mirror(Register dst, Register method, Register tmp1, Register tmp2);
193 void access_load_at(BasicType type, DecoratorSet decorators, Register dst,
194 Address src, Register tmp1, Register tmp2);
195 void access_store_at(BasicType type, DecoratorSet decorators, Address dst,
196 Register val, Register tmp1, Register tmp2, Register tmp3);
197 void load_klass(Register dst, Register src, Register tmp = t0);
198 void store_klass(Register dst, Register src, Register tmp = t0);
199 void cmp_klass(Register oop, Register trial_klass, Register tmp1, Register tmp2, Label &L);
200
201 void encode_klass_not_null(Register r, Register tmp = t0);
202 void decode_klass_not_null(Register r, Register tmp = t0);
203 void encode_klass_not_null(Register dst, Register src, Register tmp);
204 void decode_klass_not_null(Register dst, Register src, Register tmp);
205 void decode_heap_oop_not_null(Register r);
206 void decode_heap_oop_not_null(Register dst, Register src);
207 void decode_heap_oop(Register d, Register s);
208 void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
209 void encode_heap_oop_not_null(Register r);
210 void encode_heap_oop_not_null(Register dst, Register src);
211 void encode_heap_oop(Register d, Register s);
212 void encode_heap_oop(Register r) { encode_heap_oop(r, r); };
213 void load_heap_oop(Register dst, Address src, Register tmp1,
214 Register tmp2, DecoratorSet decorators = 0);
215 void load_heap_oop_not_null(Register dst, Address src, Register tmp1,
216 Register tmp2, DecoratorSet decorators = 0);
217 void store_heap_oop(Address dst, Register val, Register tmp1,
218 Register tmp2, Register tmp3, DecoratorSet decorators = 0);
219
220 void store_klass_gap(Register dst, Register src);
221
222 // currently unimplemented
223 // Used for storing null. All other oop constants should be
224 // stored using routines that take a jobject.
225 void store_heap_oop_null(Address dst);
226
227 // This dummy is to prevent a call to store_heap_oop from
228 // converting a zero (linked null) into a Register by giving
229 // the compiler two choices it can't resolve
230
231 void store_heap_oop(Address dst, void* dummy);
232
233 // Support for null-checks
234 //
235 // Generates code that causes a null OS exception if the content of reg is null.
236 // If the accessed location is M[reg + offset] and the offset is known, provide the
237 // offset. No explicit code generateion is needed if the offset is within a certain
238 // range (0 <= offset <= page_size).
239
240 virtual void null_check(Register reg, int offset = -1);
241 static bool needs_explicit_null_check(intptr_t offset);
242 static bool uses_implicit_null_check(void* address);
243
244 // idiv variant which deals with MINLONG as dividend and -1 as divisor
245 int corrected_idivl(Register result, Register rs1, Register rs2,
246 bool want_remainder, bool is_signed);
247 int corrected_idivq(Register result, Register rs1, Register rs2,
248 bool want_remainder, bool is_signed);
249
250 // interface method calling
251 void lookup_interface_method(Register recv_klass,
252 Register intf_klass,
253 RegisterOrConstant itable_index,
254 Register method_result,
255 Register scan_tmp,
256 Label& no_such_interface,
257 bool return_method = true);
258
259 void lookup_interface_method_stub(Register recv_klass,
260 Register holder_klass,
261 Register resolved_klass,
262 Register method_result,
263 Register temp_reg,
264 Register temp_reg2,
265 int itable_index,
266 Label& L_no_such_interface);
267
268 // virtual method calling
269 // n.n. x86 allows RegisterOrConstant for vtable_index
270 void lookup_virtual_method(Register recv_klass,
271 RegisterOrConstant vtable_index,
272 Register method_result);
273
274 // Form an address from base + offset in Rd. Rd my or may not
275 // actually be used: you must use the Address that is returned. It
276 // is up to you to ensure that the shift provided matches the size
277 // of your data.
278 Address form_address(Register Rd, Register base, int64_t byte_offset);
279
280 // Sometimes we get misaligned loads and stores, usually from Unsafe
281 // accesses, and these can exceed the offset range.
282 Address legitimize_address(Register Rd, const Address &adr) {
283 if (adr.getMode() == Address::base_plus_offset) {
284 if (!is_simm12(adr.offset())) {
285 return form_address(Rd, adr.base(), adr.offset());
286 }
287 }
288 return adr;
289 }
290
291 // allocation
292 void tlab_allocate(
293 Register obj, // result: pointer to object after successful allocation
294 Register var_size_in_bytes, // object size in bytes if unknown at compile time; invalid otherwise
295 int con_size_in_bytes, // object size in bytes if known at compile time
296 Register tmp1, // temp register
297 Register tmp2, // temp register
298 Label& slow_case, // continuation point of fast allocation fails
299 bool is_far = false
300 );
301
302 // Test sub_klass against super_klass, with fast and slow paths.
303
304 // The fast path produces a tri-state answer: yes / no / maybe-slow.
305 // One of the three labels can be null, meaning take the fall-through.
306 // If super_check_offset is -1, the value is loaded up from super_klass.
307 // No registers are killed, except tmp_reg
308 void check_klass_subtype_fast_path(Register sub_klass,
309 Register super_klass,
310 Register tmp_reg,
311 Label* L_success,
312 Label* L_failure,
313 Label* L_slow_path,
314 Register super_check_offset = noreg);
315
316 // The reset of the type check; must be wired to a corresponding fast path.
317 // It does not repeat the fast path logic, so don't use it standalone.
318 // The tmp1_reg and tmp2_reg can be noreg, if no temps are available.
319 // Updates the sub's secondary super cache as necessary.
320 void check_klass_subtype_slow_path(Register sub_klass,
321 Register super_klass,
322 Register tmp1_reg,
323 Register tmp2_reg,
324 Label* L_success,
325 Label* L_failure);
326
327 void population_count(Register dst, Register src, Register tmp1, Register tmp2);
328
329 // As above, but with a constant super_klass.
330 // The result is in Register result, not the condition codes.
331 bool lookup_secondary_supers_table(Register r_sub_klass,
332 Register r_super_klass,
333 Register result,
334 Register tmp1,
335 Register tmp2,
336 Register tmp3,
337 Register tmp4,
338 u1 super_klass_slot,
339 bool stub_is_near = false);
340
341 void verify_secondary_supers_table(Register r_sub_klass,
342 Register r_super_klass,
343 Register result,
344 Register tmp1,
345 Register tmp2,
346 Register tmp3);
347
348 void lookup_secondary_supers_table_slow_path(Register r_super_klass,
349 Register r_array_base,
350 Register r_array_index,
351 Register r_bitmap,
352 Register result,
353 Register tmp1);
354
355 void check_klass_subtype(Register sub_klass,
356 Register super_klass,
357 Register tmp_reg,
358 Label& L_success);
359
360 Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
361
362 // only if +VerifyOops
363 void _verify_oop(Register reg, const char* s, const char* file, int line);
364 void _verify_oop_addr(Address addr, const char* s, const char* file, int line);
365
366 void _verify_oop_checked(Register reg, const char* s, const char* file, int line) {
367 if (VerifyOops) {
368 _verify_oop(reg, s, file, line);
369 }
370 }
371 void _verify_oop_addr_checked(Address reg, const char* s, const char* file, int line) {
372 if (VerifyOops) {
373 _verify_oop_addr(reg, s, file, line);
374 }
375 }
376
377 void _verify_method_ptr(Register reg, const char* msg, const char* file, int line) {}
378 void _verify_klass_ptr(Register reg, const char* msg, const char* file, int line) {}
379
380 #define verify_oop(reg) _verify_oop_checked(reg, "broken oop " #reg, __FILE__, __LINE__)
381 #define verify_oop_msg(reg, msg) _verify_oop_checked(reg, "broken oop " #reg ", " #msg, __FILE__, __LINE__)
382 #define verify_oop_addr(addr) _verify_oop_addr_checked(addr, "broken oop addr " #addr, __FILE__, __LINE__)
383 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
384 #define verify_klass_ptr(reg) _verify_method_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
385
386 // A more convenient access to fence for our purposes
387 // We used four bit to indicate the read and write bits in the predecessors and successors,
388 // and extended i for r, o for w if UseConservativeFence enabled.
389 enum Membar_mask_bits {
390 StoreStore = 0b0101, // (pred = ow + succ = ow)
391 LoadStore = 0b1001, // (pred = ir + succ = ow)
392 StoreLoad = 0b0110, // (pred = ow + succ = ir)
393 LoadLoad = 0b1010, // (pred = ir + succ = ir)
394 AnyAny = LoadStore | StoreLoad // (pred = iorw + succ = iorw)
395 };
396
397 void membar(uint32_t order_constraint);
398
399 static void membar_mask_to_pred_succ(uint32_t order_constraint,
400 uint32_t& predecessor, uint32_t& successor) {
401 predecessor = (order_constraint >> 2) & 0x3;
402 successor = order_constraint & 0x3;
403
404 // extend rw -> iorw:
405 // 01(w) -> 0101(ow)
406 // 10(r) -> 1010(ir)
407 // 11(rw)-> 1111(iorw)
408 if (UseConservativeFence) {
409 predecessor |= predecessor << 2;
410 successor |= successor << 2;
411 }
412 }
413
414 static int pred_succ_to_membar_mask(uint32_t predecessor, uint32_t successor) {
415 return ((predecessor & 0x3) << 2) | (successor & 0x3);
416 }
417
418 void fence(uint32_t predecessor, uint32_t successor) {
419 if (UseZtso) {
420 if ((pred_succ_to_membar_mask(predecessor, successor) & StoreLoad) == StoreLoad) {
421 // TSO allows for stores to be reordered after loads. When the compiler
422 // generates a fence to disallow that, we are required to generate the
423 // fence for correctness.
424 Assembler::fence(predecessor, successor);
425 } else {
426 // TSO guarantees other fences already.
427 }
428 } else {
429 // always generate fence for RVWMO
430 Assembler::fence(predecessor, successor);
431 }
432 }
433
434 void pause() {
435 Assembler::fence(w, 0);
436 }
437
438 // prints msg, dumps registers and stops execution
439 void stop(const char* msg);
440
441 static void debug64(char* msg, int64_t pc, int64_t regs[]);
442
443 void unimplemented(const char* what = "");
444
445 void should_not_reach_here() { stop("should not reach here"); }
446
447 static address target_addr_for_insn(address insn_addr);
448
449 // Required platform-specific helpers for Label::patch_instructions.
450 // They _shadow_ the declarations in AbstractAssembler, which are undefined.
451 static int pd_patch_instruction_size(address branch, address target);
452 static void pd_patch_instruction(address branch, address target, const char* file = nullptr, int line = 0) {
453 pd_patch_instruction_size(branch, target);
454 }
455 static address pd_call_destination(address branch) {
456 return target_addr_for_insn(branch);
457 }
458
459 static int patch_oop(address insn_addr, address o);
460
461 static address get_target_of_li32(address insn_addr);
462 static int patch_imm_in_li32(address branch, int32_t target);
463
464 // Return whether code is emitted to a scratch blob.
465 virtual bool in_scratch_emit_size() {
466 return false;
467 }
468
469 address emit_address_stub(int insts_call_instruction_offset, address target);
470 address emit_trampoline_stub(int insts_call_instruction_offset, address target);
471 static int max_reloc_call_stub_size();
472
473 void emit_static_call_stub();
474 static int static_call_stub_size();
475
476 // The following 4 methods return the offset of the appropriate move instruction
477
478 // Support for fast byte/short loading with zero extension (depending on particular CPU)
479 int load_unsigned_byte(Register dst, Address src);
480 int load_unsigned_short(Register dst, Address src);
481
482 // Support for fast byte/short loading with sign extension (depending on particular CPU)
483 int load_signed_byte(Register dst, Address src);
484 int load_signed_short(Register dst, Address src);
485
486 // Load and store values by size and signed-ness
487 void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed);
488 void store_sized_value(Address dst, Register src, size_t size_in_bytes);
489
490 // Misaligned loads, will use the best way, according to the AvoidUnalignedAccess flag
491 void load_short_misaligned(Register dst, Address src, Register tmp, bool is_signed, int granularity = 1);
492 void load_int_misaligned(Register dst, Address src, Register tmp, bool is_signed, int granularity = 1);
493 void load_long_misaligned(Register dst, Address src, Register tmp, int granularity = 1);
494
495 public:
496 // Standard pseudo instructions
497 inline void nop() {
498 addi(x0, x0, 0);
499 }
500
501 inline void mv(Register Rd, Register Rs) {
502 if (Rd != Rs) {
503 addi(Rd, Rs, 0);
504 }
505 }
506
507 inline void notr(Register Rd, Register Rs) {
508 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
509 c_not(Rd);
510 } else {
511 xori(Rd, Rs, -1);
512 }
513 }
514
515 inline void neg(Register Rd, Register Rs) {
516 sub(Rd, x0, Rs);
517 }
518
519 inline void negw(Register Rd, Register Rs) {
520 subw(Rd, x0, Rs);
521 }
522
523 inline void sext_w(Register Rd, Register Rs) {
524 addiw(Rd, Rs, 0);
525 }
526
527 inline void zext_b(Register Rd, Register Rs) {
528 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
529 c_zext_b(Rd);
530 } else {
531 andi(Rd, Rs, 0xFF);
532 }
533 }
534
535 inline void seqz(Register Rd, Register Rs) {
536 sltiu(Rd, Rs, 1);
537 }
538
539 inline void snez(Register Rd, Register Rs) {
540 sltu(Rd, x0, Rs);
541 }
542
543 inline void sltz(Register Rd, Register Rs) {
544 slt(Rd, Rs, x0);
545 }
546
547 inline void sgtz(Register Rd, Register Rs) {
548 slt(Rd, x0, Rs);
549 }
550
551 // Bit-manipulation extension pseudo instructions
552 // zero extend word
553 inline void zext_w(Register Rd, Register Rs) {
554 assert(UseZba, "must be");
555 if (do_compress_zcb(Rd, Rs) && (Rd == Rs)) {
556 c_zext_w(Rd);
557 } else {
558 add_uw(Rd, Rs, zr);
559 }
560 }
561
562 // Floating-point data-processing pseudo instructions
563 inline void fmv_s(FloatRegister Rd, FloatRegister Rs) {
564 if (Rd != Rs) {
565 fsgnj_s(Rd, Rs, Rs);
566 }
567 }
568
569 inline void fabs_s(FloatRegister Rd, FloatRegister Rs) {
570 fsgnjx_s(Rd, Rs, Rs);
571 }
572
573 inline void fneg_s(FloatRegister Rd, FloatRegister Rs) {
574 fsgnjn_s(Rd, Rs, Rs);
575 }
576
577 inline void fmv_d(FloatRegister Rd, FloatRegister Rs) {
578 if (Rd != Rs) {
579 fsgnj_d(Rd, Rs, Rs);
580 }
581 }
582
583 inline void fabs_d(FloatRegister Rd, FloatRegister Rs) {
584 fsgnjx_d(Rd, Rs, Rs);
585 }
586
587 inline void fneg_d(FloatRegister Rd, FloatRegister Rs) {
588 fsgnjn_d(Rd, Rs, Rs);
589 }
590
591 // Control and status pseudo instructions
592 void rdinstret(Register Rd); // read instruction-retired counter
593 void rdcycle(Register Rd); // read cycle counter
594 void rdtime(Register Rd); // read time
595 void csrr(Register Rd, unsigned csr); // read csr
596 void csrw(unsigned csr, Register Rs); // write csr
597 void csrs(unsigned csr, Register Rs); // set bits in csr
598 void csrc(unsigned csr, Register Rs); // clear bits in csr
599 void csrwi(unsigned csr, unsigned imm);
600 void csrsi(unsigned csr, unsigned imm);
601 void csrci(unsigned csr, unsigned imm);
602 void frcsr(Register Rd); // read float-point csr
603 void fscsr(Register Rd, Register Rs); // swap float-point csr
604 void fscsr(Register Rs); // write float-point csr
605 void frrm(Register Rd); // read float-point rounding mode
606 void fsrm(Register Rd, Register Rs); // swap float-point rounding mode
607 void fsrm(Register Rs); // write float-point rounding mode
608 void fsrmi(Register Rd, unsigned imm);
609 void fsrmi(unsigned imm);
610 void frflags(Register Rd); // read float-point exception flags
611 void fsflags(Register Rd, Register Rs); // swap float-point exception flags
612 void fsflags(Register Rs); // write float-point exception flags
613 void fsflagsi(Register Rd, unsigned imm);
614 void fsflagsi(unsigned imm);
615
616 // Restore cpu control state after JNI call
617 void restore_cpu_control_state_after_jni(Register tmp);
618
619 // Control transfer pseudo instructions
620 void beqz(Register Rs, const address dest);
621 void bnez(Register Rs, const address dest);
622 void blez(Register Rs, const address dest);
623 void bgez(Register Rs, const address dest);
624 void bltz(Register Rs, const address dest);
625 void bgtz(Register Rs, const address dest);
626
627 private:
628 void load_link_jump(const address source, Register temp = t0);
629 void jump_link(const address dest, Register temp);
630 public:
631 // We try to follow risc-v asm menomics.
632 // But as we don't layout a reachable GOT,
633 // we often need to resort to movptr, li <48imm>.
634 // https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
635
636 // jump: jal x0, offset
637 // For long reach uses temp register for:
638 // la + jr
639 void j(const address dest, Register temp = t0);
640 void j(const Address &adr, Register temp = t0);
641 void j(Label &l, Register temp = t0);
642
643 // jump register: jalr x0, offset(rs)
644 void jr(Register Rd, int32_t offset = 0);
645
646 // call: la + jalr x1
647 void call(const address dest, Register temp = t0);
648
649 // jalr: jalr x1, offset(rs)
650 void jalr(Register Rs, int32_t offset = 0);
651
652 // Emit a runtime call. Only invalidates the tmp register which
653 // is used to keep the entry address for jalr/movptr.
654 // Uses call() for intra code cache, else movptr + jalr.
655 void rt_call(address dest, Register tmp = t0);
656
657 // ret: jalr x0, 0(x1)
658 inline void ret() {
659 Assembler::jalr(x0, x1, 0);
660 }
661
662 //label
663 void beqz(Register Rs, Label &l, bool is_far = false);
664 void bnez(Register Rs, Label &l, bool is_far = false);
665 void blez(Register Rs, Label &l, bool is_far = false);
666 void bgez(Register Rs, Label &l, bool is_far = false);
667 void bltz(Register Rs, Label &l, bool is_far = false);
668 void bgtz(Register Rs, Label &l, bool is_far = false);
669
670 void beq (Register Rs1, Register Rs2, Label &L, bool is_far = false);
671 void bne (Register Rs1, Register Rs2, Label &L, bool is_far = false);
672 void blt (Register Rs1, Register Rs2, Label &L, bool is_far = false);
673 void bge (Register Rs1, Register Rs2, Label &L, bool is_far = false);
674 void bltu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
675 void bgeu(Register Rs1, Register Rs2, Label &L, bool is_far = false);
676
677 void bgt (Register Rs, Register Rt, const address dest);
678 void ble (Register Rs, Register Rt, const address dest);
679 void bgtu(Register Rs, Register Rt, const address dest);
680 void bleu(Register Rs, Register Rt, const address dest);
681
682 void bgt (Register Rs, Register Rt, Label &l, bool is_far = false);
683 void ble (Register Rs, Register Rt, Label &l, bool is_far = false);
684 void bgtu(Register Rs, Register Rt, Label &l, bool is_far = false);
685 void bleu(Register Rs, Register Rt, Label &l, bool is_far = false);
686
687 #define INSN_ENTRY_RELOC(result_type, header) \
688 result_type header { \
689 guarantee(rtype == relocInfo::internal_word_type, \
690 "only internal_word_type relocs make sense here"); \
691 relocate(InternalAddress(dest).rspec()); \
692 IncompressibleRegion ir(this); /* relocations */
693
694 #define INSN(NAME) \
695 void NAME(Register Rs1, Register Rs2, const address dest) { \
696 assert_cond(dest != nullptr); \
697 int64_t offset = dest - pc(); \
698 guarantee(is_simm13(offset) && is_even(offset), \
699 "offset is invalid: is_simm_13: %s offset: " INT64_FORMAT, \
700 BOOL_TO_STR(is_simm13(offset)), offset); \
701 Assembler::NAME(Rs1, Rs2, offset); \
702 } \
703 INSN_ENTRY_RELOC(void, NAME(Register Rs1, Register Rs2, address dest, relocInfo::relocType rtype)) \
704 NAME(Rs1, Rs2, dest); \
705 }
706
707 INSN(beq);
708 INSN(bne);
709 INSN(bge);
710 INSN(bgeu);
711 INSN(blt);
712 INSN(bltu);
713
714 #undef INSN
715
716 #undef INSN_ENTRY_RELOC
717
718 void float_beq(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
719 void float_bne(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
720 void float_ble(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
721 void float_bge(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
722 void float_blt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
723 void float_bgt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
724
725 void double_beq(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
726 void double_bne(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
727 void double_ble(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
728 void double_bge(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
729 void double_blt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
730 void double_bgt(FloatRegister Rs1, FloatRegister Rs2, Label &l, bool is_far = false, bool is_unordered = false);
731
732 private:
733 int push_reg(unsigned int bitset, Register stack);
734 int pop_reg(unsigned int bitset, Register stack);
735 int push_fp(unsigned int bitset, Register stack);
736 int pop_fp(unsigned int bitset, Register stack);
737 #ifdef COMPILER2
738 int push_v(unsigned int bitset, Register stack);
739 int pop_v(unsigned int bitset, Register stack);
740 #endif // COMPILER2
741
742 // The signed 20-bit upper imm can materialize at most negative 0xF...F80000000, two G.
743 // The following signed 12-bit imm can at max subtract 0x800, two K, from that previously loaded two G.
744 bool is_valid_32bit_offset(int64_t x) {
745 constexpr int64_t twoG = (2 * G);
746 constexpr int64_t twoK = (2 * K);
747 return x < (twoG - twoK) && x >= (-twoG - twoK);
748 }
749
750 // Ensure that the auipc can reach the destination at x from anywhere within
751 // the code cache so that if it is relocated we know it will still reach.
752 bool is_32bit_offset_from_codecache(int64_t x) {
753 int64_t low = (int64_t)CodeCache::low_bound();
754 int64_t high = (int64_t)CodeCache::high_bound();
755 return is_valid_32bit_offset(x - low) && is_valid_32bit_offset(x - high);
756 }
757
758 public:
759 void push_reg(Register Rs);
760 void pop_reg(Register Rd);
761 void push_reg(RegSet regs, Register stack) { if (regs.bits()) push_reg(regs.bits(), stack); }
762 void pop_reg(RegSet regs, Register stack) { if (regs.bits()) pop_reg(regs.bits(), stack); }
763 void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
764 void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
765 #ifdef COMPILER2
766 void push_v(VectorRegSet regs, Register stack) { if (regs.bits()) push_v(regs.bits(), stack); }
767 void pop_v(VectorRegSet regs, Register stack) { if (regs.bits()) pop_v(regs.bits(), stack); }
768 #endif // COMPILER2
769
770 // Push and pop everything that might be clobbered by a native
771 // runtime call except t0 and t1. (They are always
772 // temporary registers, so we don't have to protect them.)
773 // Additional registers can be excluded in a passed RegSet.
774 void push_call_clobbered_registers_except(RegSet exclude);
775 void pop_call_clobbered_registers_except(RegSet exclude);
776
777 void push_call_clobbered_registers() {
778 push_call_clobbered_registers_except(RegSet());
779 }
780 void pop_call_clobbered_registers() {
781 pop_call_clobbered_registers_except(RegSet());
782 }
783
784 void push_CPU_state(bool save_vectors = false, int vector_size_in_bytes = 0);
785 void pop_CPU_state(bool restore_vectors = false, int vector_size_in_bytes = 0);
786
787 void push_cont_fastpath(Register java_thread);
788 void pop_cont_fastpath(Register java_thread);
789
790 // if heap base register is used - reinit it with the correct value
791 void reinit_heapbase();
792
793 void bind(Label& L) {
794 Assembler::bind(L);
795 // fences across basic blocks should not be merged
796 code()->clear_last_insn();
797 }
798
799 typedef void (MacroAssembler::* compare_and_branch_insn)(Register Rs1, Register Rs2, const address dest);
800 typedef void (MacroAssembler::* compare_and_branch_label_insn)(Register Rs1, Register Rs2, Label &L, bool is_far);
801 typedef void (MacroAssembler::* jal_jalr_insn)(Register Rt, address dest);
802
803 void wrap_label(Register r, Label &L, jal_jalr_insn insn);
804 void wrap_label(Register r1, Register r2, Label &L,
805 compare_and_branch_insn insn,
806 compare_and_branch_label_insn neg_insn, bool is_far = false);
807
808 // la will use movptr instead of GOT when not in reach for auipc.
809 void la(Register Rd, Label &label);
810 void la(Register Rd, const address addr);
811 void la(Register Rd, const address addr, int32_t &offset);
812 void la(Register Rd, const Address &adr);
813
814 void li16u(Register Rd, uint16_t imm);
815 void li32(Register Rd, int32_t imm);
816 void li (Register Rd, int64_t imm); // optimized load immediate
817
818 // mv
819 void mv(Register Rd, address addr) { li(Rd, (int64_t)addr); }
820 void mv(Register Rd, address addr, int32_t &offset) {
821 // Split address into a lower 12-bit sign-extended offset and the remainder,
822 // so that the offset could be encoded in jalr or load/store instruction.
823 offset = ((int32_t)(int64_t)addr << 20) >> 20;
824 li(Rd, (int64_t)addr - offset);
825 }
826
827 template<typename T, ENABLE_IF(std::is_integral<T>::value)>
828 inline void mv(Register Rd, T o) { li(Rd, (int64_t)o); }
829
830 void mv(Register Rd, RegisterOrConstant src) {
831 if (src.is_register()) {
832 mv(Rd, src.as_register());
833 } else {
834 mv(Rd, src.as_constant());
835 }
836 }
837
838 // Generates a load of a 48-bit constant which can be
839 // patched to any 48-bit constant, i.e. address.
840 // If common case supply additional temp register
841 // to shorten the instruction sequence.
842 void movptr(Register Rd, address addr, Register tmp = noreg);
843 void movptr(Register Rd, address addr, int32_t &offset, Register tmp = noreg);
844 private:
845 void movptr1(Register Rd, uintptr_t addr, int32_t &offset);
846 void movptr2(Register Rd, uintptr_t addr, int32_t &offset, Register tmp);
847 public:
848
849 // arith
850 void add (Register Rd, Register Rn, int64_t increment, Register temp = t0);
851 void addw(Register Rd, Register Rn, int32_t increment, Register temp = t0);
852 void sub (Register Rd, Register Rn, int64_t decrement, Register temp = t0);
853 void subw(Register Rd, Register Rn, int32_t decrement, Register temp = t0);
854
855 #define INSN(NAME) \
856 inline void NAME(Register Rd, Register Rs1, Register Rs2) { \
857 Assembler::NAME(Rd, Rs1, Rs2); \
858 }
859
860 INSN(add);
861 INSN(addw);
862 INSN(sub);
863 INSN(subw);
864
865 #undef INSN
866
867 // logic
868 void andrw(Register Rd, Register Rs1, Register Rs2);
869 void orrw(Register Rd, Register Rs1, Register Rs2);
870 void xorrw(Register Rd, Register Rs1, Register Rs2);
871
872 // logic with negate
873 void andn(Register Rd, Register Rs1, Register Rs2);
874 void orn(Register Rd, Register Rs1, Register Rs2);
875
876 // revb
877 void revb_h_h(Register Rd, Register Rs, Register tmp = t0); // reverse bytes in halfword in lower 16 bits, sign-extend
878 void revb_w_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1); // reverse bytes in lower word, sign-extend
879 void revb_h_h_u(Register Rd, Register Rs, Register tmp = t0); // reverse bytes in halfword in lower 16 bits, zero-extend
880 void revb_h_w_u(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1); // reverse bytes in halfwords in lower 32 bits, zero-extend
881 void revb_h_helper(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1); // reverse bytes in upper 16 bits (48:63) and move to lower
882 void revb_h(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1); // reverse bytes in each halfword
883 void revb_w(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2= t1); // reverse bytes in each word
884 void revb(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1); // reverse bytes in doubleword
885
886 void ror_imm(Register dst, Register src, uint32_t shift, Register tmp = t0);
887 void rolw_imm(Register dst, Register src, uint32_t, Register tmp = t0);
888 void andi(Register Rd, Register Rn, int64_t imm, Register tmp = t0);
889 void orptr(Address adr, RegisterOrConstant src, Register tmp1 = t0, Register tmp2 = t1);
890
891 // Load and Store Instructions
892 #define INSN_ENTRY_RELOC(result_type, header) \
893 result_type header { \
894 guarantee(rtype == relocInfo::internal_word_type, \
895 "only internal_word_type relocs make sense here"); \
896 relocate(InternalAddress(dest).rspec()); \
897 IncompressibleRegion ir(this); /* relocations */
898
899 #define INSN(NAME) \
900 void NAME(Register Rd, address dest) { \
901 assert_cond(dest != nullptr); \
902 int64_t distance = dest - pc(); \
903 if (is_valid_32bit_offset(distance)) { \
904 auipc(Rd, (int32_t)distance + 0x800); \
905 Assembler::NAME(Rd, Rd, ((int32_t)distance << 20) >> 20); \
906 } else { \
907 int32_t offset = 0; \
908 movptr(Rd, dest, offset); \
909 Assembler::NAME(Rd, Rd, offset); \
910 } \
911 } \
912 INSN_ENTRY_RELOC(void, NAME(Register Rd, address dest, relocInfo::relocType rtype)) \
913 NAME(Rd, dest); \
914 } \
915 void NAME(Register Rd, const Address &adr, Register temp = t0) { \
916 switch (adr.getMode()) { \
917 case Address::literal: { \
918 relocate(adr.rspec(), [&] { \
919 NAME(Rd, adr.target()); \
920 }); \
921 break; \
922 } \
923 case Address::base_plus_offset: { \
924 if (is_simm12(adr.offset())) { \
925 Assembler::NAME(Rd, adr.base(), adr.offset()); \
926 } else { \
927 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
928 if (Rd == adr.base()) { \
929 la(temp, Address(adr.base(), adr.offset() - offset)); \
930 Assembler::NAME(Rd, temp, offset); \
931 } else { \
932 la(Rd, Address(adr.base(), adr.offset() - offset)); \
933 Assembler::NAME(Rd, Rd, offset); \
934 } \
935 } \
936 break; \
937 } \
938 default: \
939 ShouldNotReachHere(); \
940 } \
941 } \
942 void NAME(Register Rd, Label &L) { \
943 wrap_label(Rd, L, &MacroAssembler::NAME); \
944 }
945
946 INSN(lb);
947 INSN(lbu);
948 INSN(lh);
949 INSN(lhu);
950 INSN(lw);
951 INSN(lwu);
952 INSN(ld);
953
954 #undef INSN
955
956 #define INSN(NAME) \
957 void NAME(FloatRegister Rd, address dest, Register temp = t0) { \
958 assert_cond(dest != nullptr); \
959 int64_t distance = dest - pc(); \
960 if (is_valid_32bit_offset(distance)) { \
961 auipc(temp, (int32_t)distance + 0x800); \
962 Assembler::NAME(Rd, temp, ((int32_t)distance << 20) >> 20); \
963 } else { \
964 int32_t offset = 0; \
965 movptr(temp, dest, offset); \
966 Assembler::NAME(Rd, temp, offset); \
967 } \
968 } \
969 INSN_ENTRY_RELOC(void, NAME(FloatRegister Rd, address dest, \
970 relocInfo::relocType rtype, Register temp = t0)) \
971 NAME(Rd, dest, temp); \
972 } \
973 void NAME(FloatRegister Rd, const Address &adr, Register temp = t0) { \
974 switch (adr.getMode()) { \
975 case Address::literal: { \
976 relocate(adr.rspec(), [&] { \
977 NAME(Rd, adr.target(), temp); \
978 }); \
979 break; \
980 } \
981 case Address::base_plus_offset: { \
982 if (is_simm12(adr.offset())) { \
983 Assembler::NAME(Rd, adr.base(), adr.offset()); \
984 } else { \
985 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
986 la(temp, Address(adr.base(), adr.offset() - offset)); \
987 Assembler::NAME(Rd, temp, offset); \
988 } \
989 break; \
990 } \
991 default: \
992 ShouldNotReachHere(); \
993 } \
994 }
995
996 INSN(flw);
997 INSN(fld);
998
999 #undef INSN
1000
1001 #define INSN(NAME, REGISTER) \
1002 INSN_ENTRY_RELOC(void, NAME(REGISTER Rs, address dest, \
1003 relocInfo::relocType rtype, Register temp = t0)) \
1004 NAME(Rs, dest, temp); \
1005 }
1006
1007 INSN(sb, Register);
1008 INSN(sh, Register);
1009 INSN(sw, Register);
1010 INSN(sd, Register);
1011 INSN(fsw, FloatRegister);
1012 INSN(fsd, FloatRegister);
1013
1014 #undef INSN
1015
1016 #define INSN(NAME) \
1017 void NAME(Register Rs, address dest, Register temp = t0) { \
1018 assert_cond(dest != nullptr); \
1019 assert_different_registers(Rs, temp); \
1020 int64_t distance = dest - pc(); \
1021 if (is_valid_32bit_offset(distance)) { \
1022 auipc(temp, (int32_t)distance + 0x800); \
1023 Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
1024 } else { \
1025 int32_t offset = 0; \
1026 movptr(temp, dest, offset); \
1027 Assembler::NAME(Rs, temp, offset); \
1028 } \
1029 } \
1030 void NAME(Register Rs, const Address &adr, Register temp = t0) { \
1031 switch (adr.getMode()) { \
1032 case Address::literal: { \
1033 assert_different_registers(Rs, temp); \
1034 relocate(adr.rspec(), [&] { \
1035 NAME(Rs, adr.target(), temp); \
1036 }); \
1037 break; \
1038 } \
1039 case Address::base_plus_offset: { \
1040 if (is_simm12(adr.offset())) { \
1041 Assembler::NAME(Rs, adr.base(), adr.offset()); \
1042 } else { \
1043 assert_different_registers(Rs, temp); \
1044 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1045 la(temp, Address(adr.base(), adr.offset() - offset)); \
1046 Assembler::NAME(Rs, temp, offset); \
1047 } \
1048 break; \
1049 } \
1050 default: \
1051 ShouldNotReachHere(); \
1052 } \
1053 }
1054
1055 INSN(sb);
1056 INSN(sh);
1057 INSN(sw);
1058 INSN(sd);
1059
1060 #undef INSN
1061
1062 #define INSN(NAME) \
1063 void NAME(FloatRegister Rs, address dest, Register temp = t0) { \
1064 assert_cond(dest != nullptr); \
1065 int64_t distance = dest - pc(); \
1066 if (is_valid_32bit_offset(distance)) { \
1067 auipc(temp, (int32_t)distance + 0x800); \
1068 Assembler::NAME(Rs, temp, ((int32_t)distance << 20) >> 20); \
1069 } else { \
1070 int32_t offset = 0; \
1071 movptr(temp, dest, offset); \
1072 Assembler::NAME(Rs, temp, offset); \
1073 } \
1074 } \
1075 void NAME(FloatRegister Rs, const Address &adr, Register temp = t0) { \
1076 switch (adr.getMode()) { \
1077 case Address::literal: { \
1078 relocate(adr.rspec(), [&] { \
1079 NAME(Rs, adr.target(), temp); \
1080 }); \
1081 break; \
1082 } \
1083 case Address::base_plus_offset: { \
1084 if (is_simm12(adr.offset())) { \
1085 Assembler::NAME(Rs, adr.base(), adr.offset()); \
1086 } else { \
1087 int32_t offset = ((int32_t)adr.offset() << 20) >> 20; \
1088 la(temp, Address(adr.base(), adr.offset() - offset)); \
1089 Assembler::NAME(Rs, temp, offset); \
1090 } \
1091 break; \
1092 } \
1093 default: \
1094 ShouldNotReachHere(); \
1095 } \
1096 }
1097
1098 INSN(fsw);
1099 INSN(fsd);
1100
1101 #undef INSN
1102
1103 #undef INSN_ENTRY_RELOC
1104
1105 void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp, Label &succeed, Label *fail);
1106 void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp, Label &succeed, Label *fail);
1107 void cmpxchg(Register addr, Register expected,
1108 Register new_val,
1109 enum operand_size size,
1110 Assembler::Aqrl acquire, Assembler::Aqrl release,
1111 Register result, bool result_as_bool = false);
1112 void cmpxchg_weak(Register addr, Register expected,
1113 Register new_val,
1114 enum operand_size size,
1115 Assembler::Aqrl acquire, Assembler::Aqrl release,
1116 Register result);
1117 void cmpxchg_narrow_value_helper(Register addr, Register expected,
1118 Register new_val,
1119 enum operand_size size,
1120 Register tmp1, Register tmp2, Register tmp3);
1121 void cmpxchg_narrow_value(Register addr, Register expected,
1122 Register new_val,
1123 enum operand_size size,
1124 Assembler::Aqrl acquire, Assembler::Aqrl release,
1125 Register result, bool result_as_bool,
1126 Register tmp1, Register tmp2, Register tmp3);
1127 void weak_cmpxchg_narrow_value(Register addr, Register expected,
1128 Register new_val,
1129 enum operand_size size,
1130 Assembler::Aqrl acquire, Assembler::Aqrl release,
1131 Register result,
1132 Register tmp1, Register tmp2, Register tmp3);
1133
1134 void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1135 void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1136 void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1137 void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1138
1139 void atomic_xchg(Register prev, Register newv, Register addr);
1140 void atomic_xchgw(Register prev, Register newv, Register addr);
1141 void atomic_xchgal(Register prev, Register newv, Register addr);
1142 void atomic_xchgalw(Register prev, Register newv, Register addr);
1143 void atomic_xchgwu(Register prev, Register newv, Register addr);
1144 void atomic_xchgalwu(Register prev, Register newv, Register addr);
1145
1146 void atomic_cas(Register prev, Register newv, Register addr);
1147 void atomic_casw(Register prev, Register newv, Register addr);
1148 void atomic_casl(Register prev, Register newv, Register addr);
1149 void atomic_caslw(Register prev, Register newv, Register addr);
1150 void atomic_casal(Register prev, Register newv, Register addr);
1151 void atomic_casalw(Register prev, Register newv, Register addr);
1152 void atomic_caswu(Register prev, Register newv, Register addr);
1153 void atomic_caslwu(Register prev, Register newv, Register addr);
1154 void atomic_casalwu(Register prev, Register newv, Register addr);
1155
1156 void atomic_cas(Register prev, Register newv, Register addr, enum operand_size size,
1157 Assembler::Aqrl acquire = Assembler::relaxed, Assembler::Aqrl release = Assembler::relaxed);
1158
1159 // Emit a far call/jump. Only invalidates the tmp register which
1160 // is used to keep the entry address for jalr.
1161 // The address must be inside the code cache.
1162 // Supported entry.rspec():
1163 // - relocInfo::external_word_type
1164 // - relocInfo::runtime_call_type
1165 // - relocInfo::none
1166 void far_call(const Address &entry, Register tmp = t0);
1167 void far_jump(const Address &entry, Register tmp = t0);
1168
1169 static int far_branch_size() {
1170 return 2 * 4; // auipc + jalr, see far_call() & far_jump()
1171 }
1172
1173 void load_byte_map_base(Register reg);
1174
1175 void bang_stack_with_offset(int offset) {
1176 // stack grows down, caller passes positive offset
1177 assert(offset > 0, "must bang with negative offset");
1178 sub(t0, sp, offset);
1179 sd(zr, Address(t0));
1180 }
1181
1182 virtual void _call_Unimplemented(address call_site) {
1183 mv(t1, call_site);
1184 }
1185
1186 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
1187
1188 // Frame creation and destruction shared between JITs.
1189 void build_frame(int framesize);
1190 void remove_frame(int framesize);
1191
1192 void reserved_stack_check();
1193
1194 void get_polling_page(Register dest, relocInfo::relocType rtype);
1195 void read_polling_page(Register r, int32_t offset, relocInfo::relocType rtype);
1196
1197 // RISCV64 OpenJDK uses four different types of calls:
1198 // - direct call: jal pc_relative_offset
1199 // This is the shortest and the fastest, but the offset has the range: +/-1MB.
1200 //
1201 // - far call: auipc reg, pc_relative_offset; jalr ra, reg, offset
1202 // This is longer than a direct call. The offset has
1203 // the range [-(2G + 2K), 2G - 2K). Addresses out of the range in the code cache
1204 // requires indirect call.
1205 // If a jump is needed rather than a call, a far jump 'jalr x0, reg, offset' can
1206 // be used instead.
1207 // All instructions are embedded at a call site.
1208 //
1209 // - indirect call: movptr + jalr
1210 // This too can reach anywhere in the address space, but it cannot be
1211 // patched while code is running, so it must only be modified at a safepoint.
1212 // This form of call is most suitable for targets at fixed addresses, which
1213 // will never be patched.
1214 //
1215 // - reloc call:
1216 // This is only available in C1/C2-generated code (nmethod).
1217 //
1218 // [Main code section]
1219 // auipc
1220 // ld <address_from_stub_section>
1221 // jalr
1222 // [Stub section]
1223 // trampoline:
1224 // <64-bit destination address>
1225 //
1226 // To change the destination we simply atomically store the new
1227 // address in the stub section.
1228 //
1229 // - trampoline call (old reloc call / -XX:+UseTrampolines):
1230 // This is only available in C1/C2-generated code (nmethod). It is a combination
1231 // of a direct call, which is used if the destination of a call is in range,
1232 // and a register-indirect call. It has the advantages of reaching anywhere in
1233 // the RISCV address space and being patchable at runtime when the generated
1234 // code is being executed by other threads.
1235 //
1236 // [Main code section]
1237 // jal trampoline
1238 // [Stub code section]
1239 // trampoline:
1240 // ld reg, pc + 8 (auipc + ld)
1241 // jr reg
1242 // <64-bit destination address>
1243 //
1244 // If the destination is in range when the generated code is moved to the code
1245 // cache, 'jal trampoline' is replaced with 'jal destination' and the trampoline
1246 // is not used.
1247 // The optimization does not remove the trampoline from the stub section.
1248 //
1249 // This is necessary because the trampoline may well be redirected later when
1250 // code is patched, and the new destination may not be reachable by a simple JAL
1251 // instruction.
1252 //
1253 // To patch a trampoline call when the JAL can't reach, we first modify
1254 // the 64-bit destination address in the trampoline, then modify the
1255 // JAL to point to the trampoline, then flush the instruction cache to
1256 // broadcast the change to all executing threads. See
1257 // NativeCall::set_destination_mt_safe for the details.
1258 //
1259 // There is a benign race in that the other thread might observe the
1260 // modified JAL before it observes the modified 64-bit destination
1261 // address. That does not matter because the destination method has been
1262 // invalidated, so there will be a trap at its start.
1263 // For this to work, the destination address in the trampoline is
1264 // always updated, even if we're not using the trampoline.
1265 // --
1266
1267 // Emit a direct call if the entry address will always be in range,
1268 // otherwise a reloc call.
1269 // Supported entry.rspec():
1270 // - relocInfo::runtime_call_type
1271 // - relocInfo::opt_virtual_call_type
1272 // - relocInfo::static_call_type
1273 // - relocInfo::virtual_call_type
1274 //
1275 // Return: the call PC or null if CodeCache is full.
1276 address reloc_call(Address entry) {
1277 return UseTrampolines ? trampoline_call(entry) : load_and_call(entry);
1278 }
1279 private:
1280 address trampoline_call(Address entry);
1281 address load_and_call(Address entry);
1282 public:
1283
1284 address ic_call(address entry, jint method_index = 0);
1285 static int ic_check_size();
1286 int ic_check(int end_alignment = MacroAssembler::instruction_size);
1287
1288 // Support for memory inc/dec
1289 // n.b. increment/decrement calls with an Address destination will
1290 // need to use a scratch register to load the value to be
1291 // incremented. increment/decrement calls which add or subtract a
1292 // constant value other than sign-extended 12-bit immediate will need
1293 // to use a 2nd scratch register to hold the constant. so, an address
1294 // increment/decrement may trash both t0 and t1.
1295
1296 void increment(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1297 void incrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1298
1299 void decrement(const Address dst, int64_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1300 void decrementw(const Address dst, int32_t value = 1, Register tmp1 = t0, Register tmp2 = t1);
1301
1302 void cmpptr(Register src1, Address src2, Label& equal);
1303
1304 void clinit_barrier(Register klass, Register tmp, Label* L_fast_path = nullptr, Label* L_slow_path = nullptr);
1305 void load_method_holder_cld(Register result, Register method);
1306 void load_method_holder(Register holder, Register method);
1307
1308 void compute_index(Register str1, Register trailing_zeros, Register match_mask,
1309 Register result, Register char_tmp, Register tmp,
1310 bool haystack_isL);
1311 void compute_match_mask(Register src, Register pattern, Register match_mask,
1312 Register mask1, Register mask2);
1313
1314 // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1315 void kernel_crc32(Register crc, Register buf, Register len,
1316 Register table0, Register table1, Register table2, Register table3,
1317 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register tmp6);
1318 void update_word_crc32(Register crc, Register v, Register tmp1, Register tmp2, Register tmp3,
1319 Register table0, Register table1, Register table2, Register table3,
1320 bool upper);
1321 void update_byte_crc32(Register crc, Register val, Register table);
1322
1323 #ifdef COMPILER2
1324 void mul_add(Register out, Register in, Register offset,
1325 Register len, Register k, Register tmp);
1326 void wide_mul(Register prod_lo, Register prod_hi, Register n, Register m);
1327 void wide_madd(Register sum_lo, Register sum_hi, Register n,
1328 Register m, Register tmp1, Register tmp2);
1329 void cad(Register dst, Register src1, Register src2, Register carry);
1330 void cadc(Register dst, Register src1, Register src2, Register carry);
1331 void adc(Register dst, Register src1, Register src2, Register carry);
1332 void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1333 Register src1, Register src2, Register carry);
1334 void multiply_32_x_32_loop(Register x, Register xstart, Register x_xstart,
1335 Register y, Register y_idx, Register z,
1336 Register carry, Register product,
1337 Register idx, Register kdx);
1338 void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1339 Register y, Register y_idx, Register z,
1340 Register carry, Register product,
1341 Register idx, Register kdx);
1342 void multiply_128_x_128_loop(Register y, Register z,
1343 Register carry, Register carry2,
1344 Register idx, Register jdx,
1345 Register yz_idx1, Register yz_idx2,
1346 Register tmp, Register tmp3, Register tmp4,
1347 Register tmp6, Register product_hi);
1348 void multiply_to_len(Register x, Register xlen, Register y, Register ylen,
1349 Register z, Register tmp0,
1350 Register tmp1, Register tmp2, Register tmp3, Register tmp4,
1351 Register tmp5, Register tmp6, Register product_hi);
1352
1353 #endif
1354
1355 void inflate_lo32(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);
1356 void inflate_hi32(Register Rd, Register Rs, Register tmp1 = t0, Register tmp2 = t1);
1357
1358 void ctzc_bit(Register Rd, Register Rs, bool isLL = false, Register tmp1 = t0, Register tmp2 = t1);
1359
1360 void zero_words(Register base, uint64_t cnt);
1361 address zero_words(Register ptr, Register cnt);
1362 void fill_words(Register base, Register cnt, Register value);
1363 void zero_memory(Register addr, Register len, Register tmp);
1364 void zero_dcache_blocks(Register base, Register cnt, Register tmp1, Register tmp2);
1365
1366 // shift left by shamt and add
1367 void shadd(Register Rd, Register Rs1, Register Rs2, Register tmp, int shamt);
1368
1369 // test single bit in Rs, result is set to Rd
1370 void test_bit(Register Rd, Register Rs, uint32_t bit_pos);
1371
1372 // Here the float instructions with safe deal with some exceptions.
1373 // e.g. convert from NaN, +Inf, -Inf to int, float, double
1374 // will trigger exception, we need to deal with these situations
1375 // to get correct results.
1376 void fcvt_w_s_safe(Register dst, FloatRegister src, Register tmp = t0);
1377 void fcvt_l_s_safe(Register dst, FloatRegister src, Register tmp = t0);
1378 void fcvt_w_d_safe(Register dst, FloatRegister src, Register tmp = t0);
1379 void fcvt_l_d_safe(Register dst, FloatRegister src, Register tmp = t0);
1380
1381 void java_round_float(Register dst, FloatRegister src, FloatRegister ftmp);
1382 void java_round_double(Register dst, FloatRegister src, FloatRegister ftmp);
1383
1384 // vector load/store unit-stride instructions
1385 void vlex_v(VectorRegister vd, Register base, Assembler::SEW sew, VectorMask vm = unmasked) {
1386 switch (sew) {
1387 case Assembler::e64:
1388 vle64_v(vd, base, vm);
1389 break;
1390 case Assembler::e32:
1391 vle32_v(vd, base, vm);
1392 break;
1393 case Assembler::e16:
1394 vle16_v(vd, base, vm);
1395 break;
1396 case Assembler::e8: // fall through
1397 default:
1398 vle8_v(vd, base, vm);
1399 break;
1400 }
1401 }
1402
1403 void vsex_v(VectorRegister store_data, Register base, Assembler::SEW sew, VectorMask vm = unmasked) {
1404 switch (sew) {
1405 case Assembler::e64:
1406 vse64_v(store_data, base, vm);
1407 break;
1408 case Assembler::e32:
1409 vse32_v(store_data, base, vm);
1410 break;
1411 case Assembler::e16:
1412 vse16_v(store_data, base, vm);
1413 break;
1414 case Assembler::e8: // fall through
1415 default:
1416 vse8_v(store_data, base, vm);
1417 break;
1418 }
1419 }
1420
1421 // vector pseudo instructions
1422 // rotate vector register left with shift bits, 32-bit version
1423 inline void vrole32_vi(VectorRegister vd, uint32_t shift, VectorRegister tmp_vr) {
1424 vsrl_vi(tmp_vr, vd, 32 - shift);
1425 vsll_vi(vd, vd, shift);
1426 vor_vv(vd, vd, tmp_vr);
1427 }
1428
1429 inline void vl1r_v(VectorRegister vd, Register rs) {
1430 vl1re8_v(vd, rs);
1431 }
1432
1433 inline void vmnot_m(VectorRegister vd, VectorRegister vs) {
1434 vmnand_mm(vd, vs, vs);
1435 }
1436
1437 inline void vncvt_x_x_w(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1438 vnsrl_wx(vd, vs, x0, vm);
1439 }
1440
1441 inline void vneg_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1442 vrsub_vx(vd, vs, x0, vm);
1443 }
1444
1445 inline void vfneg_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1446 vfsgnjn_vv(vd, vs, vs, vm);
1447 }
1448
1449 inline void vfabs_v(VectorRegister vd, VectorRegister vs, VectorMask vm = unmasked) {
1450 vfsgnjx_vv(vd, vs, vs, vm);
1451 }
1452
1453 inline void vmsgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1454 vmslt_vv(vd, vs1, vs2, vm);
1455 }
1456
1457 inline void vmsgtu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1458 vmsltu_vv(vd, vs1, vs2, vm);
1459 }
1460
1461 inline void vmsge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1462 vmsle_vv(vd, vs1, vs2, vm);
1463 }
1464
1465 inline void vmsgeu_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1466 vmsleu_vv(vd, vs1, vs2, vm);
1467 }
1468
1469 inline void vmfgt_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1470 vmflt_vv(vd, vs1, vs2, vm);
1471 }
1472
1473 inline void vmfge_vv(VectorRegister vd, VectorRegister vs2, VectorRegister vs1, VectorMask vm = unmasked) {
1474 vmfle_vv(vd, vs1, vs2, vm);
1475 }
1476
1477 inline void vmsltu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
1478 guarantee(imm >= 1 && imm <= 16, "imm is invalid");
1479 vmsleu_vi(Vd, Vs2, imm-1, vm);
1480 }
1481
1482 inline void vmsgeu_vi(VectorRegister Vd, VectorRegister Vs2, uint32_t imm, VectorMask vm = unmasked) {
1483 guarantee(imm >= 1 && imm <= 16, "imm is invalid");
1484 vmsgtu_vi(Vd, Vs2, imm-1, vm);
1485 }
1486
1487 // Copy mask register
1488 inline void vmmv_m(VectorRegister vd, VectorRegister vs) {
1489 vmand_mm(vd, vs, vs);
1490 }
1491
1492 // Clear mask register
1493 inline void vmclr_m(VectorRegister vd) {
1494 vmxor_mm(vd, vd, vd);
1495 }
1496
1497 // Set mask register
1498 inline void vmset_m(VectorRegister vd) {
1499 vmxnor_mm(vd, vd, vd);
1500 }
1501
1502 inline void vnot_v(VectorRegister Vd, VectorRegister Vs, VectorMask vm = unmasked) {
1503 vxor_vi(Vd, Vs, -1, vm);
1504 }
1505
1506 static const int zero_words_block_size;
1507
1508 void cast_primitive_type(BasicType type, Register Rt) {
1509 switch (type) {
1510 case T_BOOLEAN:
1511 sltu(Rt, zr, Rt);
1512 break;
1513 case T_CHAR :
1514 zero_extend(Rt, Rt, 16);
1515 break;
1516 case T_BYTE :
1517 sign_extend(Rt, Rt, 8);
1518 break;
1519 case T_SHORT :
1520 sign_extend(Rt, Rt, 16);
1521 break;
1522 case T_INT :
1523 sign_extend(Rt, Rt, 32);
1524 break;
1525 case T_LONG : /* nothing to do */ break;
1526 case T_VOID : /* nothing to do */ break;
1527 case T_FLOAT : /* nothing to do */ break;
1528 case T_DOUBLE : /* nothing to do */ break;
1529 default: ShouldNotReachHere();
1530 }
1531 }
1532
1533 // float cmp with unordered_result
1534 void float_compare(Register result, FloatRegister Rs1, FloatRegister Rs2, int unordered_result);
1535 void double_compare(Register result, FloatRegister Rs1, FloatRegister Rs2, int unordered_result);
1536
1537 // Zero/Sign-extend
1538 void zero_extend(Register dst, Register src, int bits);
1539 void sign_extend(Register dst, Register src, int bits);
1540
1541 private:
1542 void cmp_x2i(Register dst, Register src1, Register src2, Register tmp, bool is_signed = true);
1543
1544 public:
1545 // compare src1 and src2 and get -1/0/1 in dst.
1546 // if [src1 > src2], dst = 1;
1547 // if [src1 == src2], dst = 0;
1548 // if [src1 < src2], dst = -1;
1549 void cmp_l2i(Register dst, Register src1, Register src2, Register tmp = t0);
1550 void cmp_ul2i(Register dst, Register src1, Register src2, Register tmp = t0);
1551 void cmp_uw2i(Register dst, Register src1, Register src2, Register tmp = t0);
1552
1553 // support for argument shuffling
1554 void move32_64(VMRegPair src, VMRegPair dst, Register tmp = t0);
1555 void float_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1556 void long_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1557 void double_move(VMRegPair src, VMRegPair dst, Register tmp = t0);
1558 void object_move(OopMap* map,
1559 int oop_handle_offset,
1560 int framesize_in_slots,
1561 VMRegPair src,
1562 VMRegPair dst,
1563 bool is_receiver,
1564 int* receiver_offset);
1565
1566 #ifdef ASSERT
1567 // Template short-hand support to clean-up after a failed call to trampoline
1568 // call generation (see trampoline_call() below), when a set of Labels must
1569 // be reset (before returning).
1570 template<typename Label, typename... More>
1571 void reset_labels(Label& lbl, More&... more) {
1572 lbl.reset(); reset_labels(more...);
1573 }
1574 template<typename Label>
1575 void reset_labels(Label& lbl) {
1576 lbl.reset();
1577 }
1578 #endif
1579
1580 private:
1581
1582 void repne_scan(Register addr, Register value, Register count, Register tmp);
1583
1584 void ld_constant(Register dest, const Address &const_addr) {
1585 if (NearCpool) {
1586 ld(dest, const_addr);
1587 } else {
1588 InternalAddress target(const_addr.target());
1589 relocate(target.rspec(), [&] {
1590 int32_t offset;
1591 la(dest, target.target(), offset);
1592 ld(dest, Address(dest, offset));
1593 });
1594 }
1595 }
1596
1597 int bitset_to_regs(unsigned int bitset, unsigned char* regs);
1598 Address add_memory_helper(const Address dst, Register tmp);
1599
1600 void load_reserved(Register dst, Register addr, enum operand_size size, Assembler::Aqrl acquire);
1601 void store_conditional(Register dst, Register new_val, Register addr, enum operand_size size, Assembler::Aqrl release);
1602
1603 public:
1604 void lightweight_lock(Register basic_lock, Register obj, Register tmp1, Register tmp2, Register tmp3, Label& slow);
1605 void lightweight_unlock(Register obj, Register tmp1, Register tmp2, Register tmp3, Label& slow);
1606
1607 public:
1608 enum {
1609 // movptr
1610 movptr1_instruction_size = 6 * instruction_size, // lui, addi, slli, addi, slli, addi. See movptr1().
1611 movptr2_instruction_size = 5 * instruction_size, // lui, lui, slli, add, addi. See movptr2().
1612 load_pc_relative_instruction_size = 2 * instruction_size // auipc, ld
1613 };
1614
1615 enum NativeShortCall {
1616 trampoline_size = 3 * instruction_size + wordSize,
1617 trampoline_data_offset = 3 * instruction_size
1618 };
1619
1620 static bool is_load_pc_relative_at(address branch);
1621 static bool is_li16u_at(address instr);
1622
1623 static bool is_jal_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1101111; }
1624 static bool is_jalr_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1100111 && extract_funct3(instr) == 0b000; }
1625 static bool is_branch_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b1100011; }
1626 static bool is_ld_at(address instr) { assert_cond(instr != nullptr); return is_load_at(instr) && extract_funct3(instr) == 0b011; }
1627 static bool is_load_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0000011; }
1628 static bool is_float_load_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0000111; }
1629 static bool is_auipc_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010111; }
1630 static bool is_jump_at(address instr) { assert_cond(instr != nullptr); return is_branch_at(instr) || is_jal_at(instr) || is_jalr_at(instr); }
1631 static bool is_add_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110011 && extract_funct3(instr) == 0b000; }
1632 static bool is_addi_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0010011 && extract_funct3(instr) == 0b000; }
1633 static bool is_addiw_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0011011 && extract_funct3(instr) == 0b000; }
1634 static bool is_addiw_to_zr_at(address instr){ assert_cond(instr != nullptr); return is_addiw_at(instr) && extract_rd(instr) == zr; }
1635 static bool is_lui_at(address instr) { assert_cond(instr != nullptr); return extract_opcode(instr) == 0b0110111; }
1636 static bool is_lui_to_zr_at(address instr) { assert_cond(instr != nullptr); return is_lui_at(instr) && extract_rd(instr) == zr; }
1637
1638 static bool is_srli_at(address instr) {
1639 assert_cond(instr != nullptr);
1640 return extract_opcode(instr) == 0b0010011 &&
1641 extract_funct3(instr) == 0b101 &&
1642 Assembler::extract(((unsigned*)instr)[0], 31, 26) == 0b000000;
1643 }
1644
1645 static bool is_slli_shift_at(address instr, uint32_t shift) {
1646 assert_cond(instr != nullptr);
1647 return (extract_opcode(instr) == 0b0010011 && // opcode field
1648 extract_funct3(instr) == 0b001 && // funct3 field, select the type of operation
1649 Assembler::extract(Assembler::ld_instr(instr), 25, 20) == shift); // shamt field
1650 }
1651
1652 static bool is_movptr1_at(address instr);
1653 static bool is_movptr2_at(address instr);
1654
1655 static bool is_lwu_to_zr(address instr);
1656
1657 static Register extract_rs1(address instr);
1658 static Register extract_rs2(address instr);
1659 static Register extract_rd(address instr);
1660 static uint32_t extract_opcode(address instr);
1661 static uint32_t extract_funct3(address instr);
1662
1663 // the instruction sequence of movptr is as below:
1664 // lui
1665 // addi
1666 // slli
1667 // addi
1668 // slli
1669 // addi/jalr/load
1670 static bool check_movptr1_data_dependency(address instr) {
1671 address lui = instr;
1672 address addi1 = lui + instruction_size;
1673 address slli1 = addi1 + instruction_size;
1674 address addi2 = slli1 + instruction_size;
1675 address slli2 = addi2 + instruction_size;
1676 address last_instr = slli2 + instruction_size;
1677 return extract_rs1(addi1) == extract_rd(lui) &&
1678 extract_rs1(addi1) == extract_rd(addi1) &&
1679 extract_rs1(slli1) == extract_rd(addi1) &&
1680 extract_rs1(slli1) == extract_rd(slli1) &&
1681 extract_rs1(addi2) == extract_rd(slli1) &&
1682 extract_rs1(addi2) == extract_rd(addi2) &&
1683 extract_rs1(slli2) == extract_rd(addi2) &&
1684 extract_rs1(slli2) == extract_rd(slli2) &&
1685 extract_rs1(last_instr) == extract_rd(slli2);
1686 }
1687
1688 // the instruction sequence of movptr2 is as below:
1689 // lui
1690 // lui
1691 // slli
1692 // add
1693 // addi/jalr/load
1694 static bool check_movptr2_data_dependency(address instr) {
1695 address lui1 = instr;
1696 address lui2 = lui1 + instruction_size;
1697 address slli = lui2 + instruction_size;
1698 address add = slli + instruction_size;
1699 address last_instr = add + instruction_size;
1700 return extract_rd(add) == extract_rd(lui2) &&
1701 extract_rs1(add) == extract_rd(lui2) &&
1702 extract_rs2(add) == extract_rd(slli) &&
1703 extract_rs1(slli) == extract_rd(lui1) &&
1704 extract_rd(slli) == extract_rd(lui1) &&
1705 extract_rs1(last_instr) == extract_rd(add);
1706 }
1707
1708 // the instruction sequence of li16u is as below:
1709 // lui
1710 // srli
1711 static bool check_li16u_data_dependency(address instr) {
1712 address lui = instr;
1713 address srli = lui + instruction_size;
1714
1715 return extract_rs1(srli) == extract_rd(lui) &&
1716 extract_rs1(srli) == extract_rd(srli);
1717 }
1718
1719 // the instruction sequence of li32 is as below:
1720 // lui
1721 // addiw
1722 static bool check_li32_data_dependency(address instr) {
1723 address lui = instr;
1724 address addiw = lui + instruction_size;
1725
1726 return extract_rs1(addiw) == extract_rd(lui) &&
1727 extract_rs1(addiw) == extract_rd(addiw);
1728 }
1729
1730 // the instruction sequence of pc-relative is as below:
1731 // auipc
1732 // jalr/addi/load/float_load
1733 static bool check_pc_relative_data_dependency(address instr) {
1734 address auipc = instr;
1735 address last_instr = auipc + instruction_size;
1736
1737 return extract_rs1(last_instr) == extract_rd(auipc);
1738 }
1739
1740 // the instruction sequence of load_label is as below:
1741 // auipc
1742 // load
1743 static bool check_load_pc_relative_data_dependency(address instr) {
1744 address auipc = instr;
1745 address load = auipc + instruction_size;
1746
1747 return extract_rd(load) == extract_rd(auipc) &&
1748 extract_rs1(load) == extract_rd(load);
1749 }
1750
1751 static bool is_li32_at(address instr);
1752 static bool is_pc_relative_at(address branch);
1753
1754 static bool is_membar(address addr) {
1755 return (Bytes::get_native_u4(addr) & 0x7f) == 0b1111 && extract_funct3(addr) == 0;
1756 }
1757 static uint32_t get_membar_kind(address addr);
1758 static void set_membar_kind(address addr, uint32_t order_kind);
1759 };
1760
1761 #ifdef ASSERT
1762 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1763 #endif
1764
1765 /**
1766 * class SkipIfEqual:
1767 *
1768 * Instantiating this class will result in assembly code being output that will
1769 * jump around any code emitted between the creation of the instance and it's
1770 * automatic destruction at the end of a scope block, depending on the value of
1771 * the flag passed to the constructor, which will be checked at run-time.
1772 */
1773 class SkipIfEqual {
1774 private:
1775 MacroAssembler* _masm;
1776 Label _label;
1777
1778 public:
1779 SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1780 ~SkipIfEqual();
1781 };
1782
1783 #endif // CPU_RISCV_MACROASSEMBLER_RISCV_HPP