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src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

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2424 #if INCLUDE_JVMCI
2425   if (EnableJVMCI) {
2426     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2427     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2428   }
2429 #endif
2430 }
2431 
2432 // Number of stack slots between incoming argument block and the start of
2433 // a new frame. The PROLOG must add this many slots to the stack. The
2434 // EPILOG must remove this many slots.
2435 // RISCV needs two words for RA (return address) and FP (frame pointer).
2436 uint SharedRuntime::in_preserve_stack_slots() {
2437   return 2 * VMRegImpl::slots_per_word;
2438 }
2439 
2440 uint SharedRuntime::out_preserve_stack_slots() {
2441   return 0;
2442 }
2443 





2444 #ifdef COMPILER2
2445 //------------------------------generate_uncommon_trap_blob--------------------
2446 void SharedRuntime::generate_uncommon_trap_blob() {
2447   // Allocate space for the code
2448   ResourceMark rm;
2449   // Setup code generation tools
2450   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2451   MacroAssembler* masm = new MacroAssembler(&buffer);
2452   assert_cond(masm != nullptr);
2453 
2454   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2455 
2456   address start = __ pc();
2457 
2458   // Push self-frame.  We get here with a return address in RA
2459   // and sp should be 16 byte aligned
2460   // push fp and retaddr by hand
2461   __ addi(sp, sp, -2 * wordSize);
2462   __ sd(ra, Address(sp, wordSize));
2463   __ sd(fp, Address(sp, 0));

2424 #if INCLUDE_JVMCI
2425   if (EnableJVMCI) {
2426     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2427     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2428   }
2429 #endif
2430 }
2431 
2432 // Number of stack slots between incoming argument block and the start of
2433 // a new frame. The PROLOG must add this many slots to the stack. The
2434 // EPILOG must remove this many slots.
2435 // RISCV needs two words for RA (return address) and FP (frame pointer).
2436 uint SharedRuntime::in_preserve_stack_slots() {
2437   return 2 * VMRegImpl::slots_per_word;
2438 }
2439 
2440 uint SharedRuntime::out_preserve_stack_slots() {
2441   return 0;
2442 }
2443 
2444 VMReg SharedRuntime::thread_register() {
2445   Unimplemented();
2446   return nullptr;
2447 }
2448 
2449 #ifdef COMPILER2
2450 //------------------------------generate_uncommon_trap_blob--------------------
2451 void SharedRuntime::generate_uncommon_trap_blob() {
2452   // Allocate space for the code
2453   ResourceMark rm;
2454   // Setup code generation tools
2455   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2456   MacroAssembler* masm = new MacroAssembler(&buffer);
2457   assert_cond(masm != nullptr);
2458 
2459   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2460 
2461   address start = __ pc();
2462 
2463   // Push self-frame.  We get here with a return address in RA
2464   // and sp should be 16 byte aligned
2465   // push fp and retaddr by hand
2466   __ addi(sp, sp, -2 * wordSize);
2467   __ sd(ra, Address(sp, wordSize));
2468   __ sd(fp, Address(sp, 0));
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