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src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

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2396 #if INCLUDE_JVMCI
2397   if (EnableJVMCI) {
2398     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2399     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2400   }
2401 #endif
2402 }
2403 
2404 // Number of stack slots between incoming argument block and the start of
2405 // a new frame. The PROLOG must add this many slots to the stack. The
2406 // EPILOG must remove this many slots.
2407 // RISCV needs two words for RA (return address) and FP (frame pointer).
2408 uint SharedRuntime::in_preserve_stack_slots() {
2409   return 2 * VMRegImpl::slots_per_word;
2410 }
2411 
2412 uint SharedRuntime::out_preserve_stack_slots() {
2413   return 0;
2414 }
2415 





2416 #ifdef COMPILER2
2417 //------------------------------generate_uncommon_trap_blob--------------------
2418 void SharedRuntime::generate_uncommon_trap_blob() {
2419   // Allocate space for the code
2420   ResourceMark rm;
2421   // Setup code generation tools
2422   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2423   MacroAssembler* masm = new MacroAssembler(&buffer);
2424   assert_cond(masm != nullptr);
2425 
2426   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2427 
2428   address start = __ pc();
2429 
2430   // Push self-frame.  We get here with a return address in RA
2431   // and sp should be 16 byte aligned
2432   // push fp and retaddr by hand
2433   __ addi(sp, sp, -2 * wordSize);
2434   __ sd(ra, Address(sp, wordSize));
2435   __ sd(fp, Address(sp, 0));

2396 #if INCLUDE_JVMCI
2397   if (EnableJVMCI) {
2398     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2399     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2400   }
2401 #endif
2402 }
2403 
2404 // Number of stack slots between incoming argument block and the start of
2405 // a new frame. The PROLOG must add this many slots to the stack. The
2406 // EPILOG must remove this many slots.
2407 // RISCV needs two words for RA (return address) and FP (frame pointer).
2408 uint SharedRuntime::in_preserve_stack_slots() {
2409   return 2 * VMRegImpl::slots_per_word;
2410 }
2411 
2412 uint SharedRuntime::out_preserve_stack_slots() {
2413   return 0;
2414 }
2415 
2416 VMReg SharedRuntime::thread_register() {
2417   Unimplemented();
2418   return nullptr;
2419 }
2420 
2421 #ifdef COMPILER2
2422 //------------------------------generate_uncommon_trap_blob--------------------
2423 void SharedRuntime::generate_uncommon_trap_blob() {
2424   // Allocate space for the code
2425   ResourceMark rm;
2426   // Setup code generation tools
2427   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2428   MacroAssembler* masm = new MacroAssembler(&buffer);
2429   assert_cond(masm != nullptr);
2430 
2431   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2432 
2433   address start = __ pc();
2434 
2435   // Push self-frame.  We get here with a return address in RA
2436   // and sp should be 16 byte aligned
2437   // push fp and retaddr by hand
2438   __ addi(sp, sp, -2 * wordSize);
2439   __ sd(ra, Address(sp, wordSize));
2440   __ sd(fp, Address(sp, 0));
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