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src/hotspot/cpu/riscv/sharedRuntime_riscv.cpp

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2434 #if INCLUDE_JVMCI
2435   if (EnableJVMCI) {
2436     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2437     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2438   }
2439 #endif
2440 }
2441 
2442 // Number of stack slots between incoming argument block and the start of
2443 // a new frame. The PROLOG must add this many slots to the stack. The
2444 // EPILOG must remove this many slots.
2445 // RISCV needs two words for RA (return address) and FP (frame pointer).
2446 uint SharedRuntime::in_preserve_stack_slots() {
2447   return 2 * VMRegImpl::slots_per_word;
2448 }
2449 
2450 uint SharedRuntime::out_preserve_stack_slots() {
2451   return 0;
2452 }
2453 





2454 #ifdef COMPILER2
2455 //------------------------------generate_uncommon_trap_blob--------------------
2456 void SharedRuntime::generate_uncommon_trap_blob() {
2457   // Allocate space for the code
2458   ResourceMark rm;
2459   // Setup code generation tools
2460   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2461   MacroAssembler* masm = new MacroAssembler(&buffer);
2462   assert_cond(masm != nullptr);
2463 
2464   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2465 
2466   address start = __ pc();
2467 
2468   // Push self-frame.  We get here with a return address in RA
2469   // and sp should be 16 byte aligned
2470   // push fp and retaddr by hand
2471   __ addi(sp, sp, -2 * wordSize);
2472   __ sd(ra, Address(sp, wordSize));
2473   __ sd(fp, Address(sp, 0));

2434 #if INCLUDE_JVMCI
2435   if (EnableJVMCI) {
2436     _deopt_blob->set_uncommon_trap_offset(uncommon_trap_offset);
2437     _deopt_blob->set_implicit_exception_uncommon_trap_offset(implicit_exception_uncommon_trap_offset);
2438   }
2439 #endif
2440 }
2441 
2442 // Number of stack slots between incoming argument block and the start of
2443 // a new frame. The PROLOG must add this many slots to the stack. The
2444 // EPILOG must remove this many slots.
2445 // RISCV needs two words for RA (return address) and FP (frame pointer).
2446 uint SharedRuntime::in_preserve_stack_slots() {
2447   return 2 * VMRegImpl::slots_per_word;
2448 }
2449 
2450 uint SharedRuntime::out_preserve_stack_slots() {
2451   return 0;
2452 }
2453 
2454 VMReg SharedRuntime::thread_register() {
2455   Unimplemented();
2456   return nullptr;
2457 }
2458 
2459 #ifdef COMPILER2
2460 //------------------------------generate_uncommon_trap_blob--------------------
2461 void SharedRuntime::generate_uncommon_trap_blob() {
2462   // Allocate space for the code
2463   ResourceMark rm;
2464   // Setup code generation tools
2465   CodeBuffer buffer("uncommon_trap_blob", 2048, 1024);
2466   MacroAssembler* masm = new MacroAssembler(&buffer);
2467   assert_cond(masm != nullptr);
2468 
2469   assert(SimpleRuntimeFrame::framesize % 4 == 0, "sp not 16-byte aligned");
2470 
2471   address start = __ pc();
2472 
2473   // Push self-frame.  We get here with a return address in RA
2474   // and sp should be 16 byte aligned
2475   // push fp and retaddr by hand
2476   __ addi(sp, sp, -2 * wordSize);
2477   __ sd(ra, Address(sp, wordSize));
2478   __ sd(fp, Address(sp, 0));
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