1 /*
  2  * Copyright (c) 2016, 2020, Oracle and/or its affiliates. All rights reserved.
  3  * Copyright (c) 2016 SAP SE. All rights reserved.
  4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  5  *
  6  * This code is free software; you can redistribute it and/or modify it
  7  * under the terms of the GNU General Public License version 2 only, as
  8  * published by the Free Software Foundation.
  9  *
 10  * This code is distributed in the hope that it will be useful, but WITHOUT
 11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 13  * version 2 for more details (a copy is included in the LICENSE file that
 14  * accompanied this code).
 15  *
 16  * You should have received a copy of the GNU General Public License version
 17  * 2 along with this work; if not, write to the Free Software Foundation,
 18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 19  *
 20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 21  * or visit www.oracle.com if you need additional information or have any
 22  * questions.
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 25 
 26 // Major contributions by AHa, JL, LS
 27 
 28 #ifndef CPU_S390_NATIVEINST_S390_HPP
 29 #define CPU_S390_NATIVEINST_S390_HPP
 30 
 31 #include "asm/macroAssembler.hpp"
 32 #include "runtime/icache.hpp"
 33 #include "runtime/os.hpp"
 34 
 35 class NativeCall;
 36 class NativeFarCall;
 37 class NativeMovConstReg;
 38 class NativeJump;
 39 #ifndef COMPILER2
 40 class NativeGeneralJump;
 41 class NativeMovRegMem;
 42 #endif
 43 class NativeInstruction;
 44 
 45 NativeCall* nativeCall_before(address return_address);
 46 NativeCall* nativeCall_at(address instr);
 47 NativeFarCall* nativeFarCall_before(address return_address);
 48 NativeFarCall* nativeFarCall_at(address instr);
 49 NativeMovConstReg* nativeMovConstReg_at(address address);
 50 NativeMovConstReg* nativeMovConstReg_before(address address);
 51 NativeJump* nativeJump_at(address address);
 52 #ifndef COMPILER2
 53 NativeMovRegMem* nativeMovRegMem_at (address address);
 54 NativeGeneralJump* nativeGeneralJump_at(address address);
 55 #endif
 56 NativeInstruction* nativeInstruction_at(address address);
 57 
 58 // We have interface for the following instructions:
 59 // - NativeInstruction
 60 //   - NativeCall
 61 //   - NativeFarCall
 62 //   - NativeMovConstReg
 63 //   - NativeMovRegMem
 64 //   - NativeJump
 65 //   - NativeGeneralJump
 66 //   - NativeIllegalInstruction
 67 // The base class for different kinds of native instruction abstractions.
 68 // Provides the primitive operations to manipulate code relative to this.
 69 
 70 //-------------------------------------
 71 //  N a t i v e I n s t r u c t i o n
 72 //-------------------------------------
 73 
 74 class NativeInstruction {
 75   friend class Relocation;
 76 
 77  public:
 78 
 79   enum z_specific_constants {
 80     nop_instruction_size = 2
 81   };
 82 
 83   bool is_illegal();
 84 
 85   // Bcrl is currently the only accepted instruction here.
 86   bool is_jump();
 87 
 88   // We use an illtrap for marking a method as not_entrant or zombie.
 89   bool is_sigill_zombie_not_entrant();
 90 
 91   bool is_safepoint_poll() {
 92     // Is the current instruction a POTENTIAL read access to the polling page?
 93     // The instruction's current arguments are not checked!
 94     return MacroAssembler::is_load_from_polling_page(addr_at(0));
 95   }
 96 
 97   address get_poll_address(void *ucontext) {
 98     // Extract poll address from instruction and ucontext.
 99     return MacroAssembler::get_poll_address(addr_at(0), ucontext);
100   }
101 
102   uint get_poll_register() {
103     // Extract poll register from instruction.
104     return MacroAssembler::get_poll_register(addr_at(0));
105   }
106 
107  public:
108 
109   // The output of __ breakpoint_trap().
110   static int illegal_instruction();
111 
112   // The address of the currently processed instruction.
113   address instruction_address() const { return addr_at(0); }
114 
115  protected:
116   address addr_at(int offset) const { return address(this) + offset; }
117 
118   // z/Architecture terminology
119   //   halfword   = 2 bytes
120   //   word       = 4 bytes
121   //   doubleword = 8 bytes
122   unsigned short halfword_at(int offset) const { return *(unsigned short*)addr_at(offset); }
123   int  word_at(int offset)               const { return *(jint*)addr_at(offset); }
124   long long_at(int offset)               const { return *(jlong*)addr_at(offset); }
125   void set_halfword_at(int offset, short i); // Deals with I-cache.
126   void set_word_at(int offset, int i);       // Deals with I-cache.
127   void set_jlong_at(int offset, jlong i);    // Deals with I-cache.
128   void set_addr_at(int offset, address x);   // Deals with I-cache.
129 
130   void print() const;
131   void print(const char* msg) const;
132   void dump() const;
133   void dump(const unsigned int range) const;
134   void dump(const unsigned int range, const char* msg) const;
135 
136  public:
137 
138   void verify();
139 
140   friend NativeInstruction* nativeInstruction_at(address address) {
141     NativeInstruction* inst = (NativeInstruction*)address;
142     #ifdef ASSERT
143       inst->verify();
144     #endif
145     return inst;
146   }
147 };
148 
149 //---------------------------------------------------
150 //  N a t i v e I l l e g a l I n s t r u c t i o n
151 //---------------------------------------------------
152 
153 class NativeIllegalInstruction: public NativeInstruction {
154  public:
155   enum z_specific_constants {
156     instruction_size = 2
157   };
158 
159   // Insert illegal opcode at specific address.
160   static void insert(address code_pos);
161 };
162 
163 //-----------------------
164 //  N a t i v e C a l l
165 //-----------------------
166 
167 // The NativeCall is an abstraction for accessing/manipulating call
168 // instructions. It is used to manipulate inline caches, primitive &
169 // dll calls, etc.
170 
171 // A native call, as defined by this abstraction layer, consists of
172 // all instructions required to set up for and actually make the call.
173 //
174 // On z/Architecture, there exist three different forms of native calls:
175 // 1) Call with pc-relative address, 1 instruction
176 //    The location of the target function is encoded as relative address
177 //    in the call instruction. The short form (BRAS) allows for a
178 //    16-bit signed relative address (in 2-byte units). The long form
179 //    (BRASL) allows for a 32-bit signed relative address (in 2-byte units).
180 // 2) Call with immediate address, 3 or 5 instructions.
181 //    The location of the target function is given by an immediate
182 //    constant which is loaded into a (scratch) register. Depending on
183 //    the hardware capabilities, this takes 2 or 4 instructions.
184 //    The call itself is then a "call by register"(BASR) instruction.
185 // 3) Call with address from constant pool, 2(3) instructions (with dynamic TOC)
186 //    The location of the target function is stored in the constant pool
187 //    during compilation. From there it is loaded into a (scratch) register.
188 //    The call itself is then a "call by register"(BASR) instruction.
189 //
190 // When initially generating a call, the compiler uses form 2) (not
191 // patchable, target address constant, e.g. runtime calls) or 3) (patchable,
192 // target address might eventually get relocated). Later in the process,
193 // a call could be transformed into form 1) (also patchable) during ShortenBranches.
194 //
195 // If a call is/has to be patchable, the instruction sequence generated for it
196 // has to be constant in length. Excessive space, created e.g. by ShortenBranches,
197 // is allocated to lower addresses and filled with nops. That is necessary to
198 // keep the return address constant, no matter what form the call has.
199 // Methods dealing with such calls have "patchable" as part of their name.
200 
201 class NativeCall: public NativeInstruction {
202  public:
203 
204   static int get_IC_pos_in_java_to_interp_stub() {
205     return 0;
206   }
207 
208   enum z_specific_constants {
209     instruction_size                           = 18, // Used in shared code for calls with reloc_info:
210                                                      // value correct if !has_long_displacement_fast().
211     call_far_pcrelative_displacement_offset    =  4, // Includes 2 bytes for the nop.
212     call_far_pcrelative_displacement_alignment =  4
213   };
214 
215 
216   // Maximum size (in bytes) of a call to an absolute address.
217   // Used when emitting call to deopt handler blob, which is a
218   // "load_const_call". The code pattern is:
219   //   tmpReg := load_const(address);   (* depends on CPU ArchLvl, but is otherwise constant *)
220   //   call(tmpReg);                    (* basr, 2 bytes *)
221   static unsigned int max_instruction_size() {
222     return MacroAssembler::load_const_size() + MacroAssembler::call_byregister_size();
223   }
224 
225   // address instruction_address() const { return addr_at(0); }
226 
227   // For the ordering of the checks see note at nativeCall_before.
228   address next_instruction_address() const  {
229     address iaddr = instruction_address();
230 
231     if (MacroAssembler::is_load_const_call(iaddr)) {
232       // Form 2): load_const, BASR
233       return addr_at(MacroAssembler::load_const_call_size());
234     }
235 
236     if (MacroAssembler::is_load_const_from_toc_call(iaddr)) {
237       // Form 3): load_const_from_toc (LARL+LG/LGRL), BASR.
238       return addr_at(MacroAssembler::load_const_from_toc_call_size());
239     }
240 
241     if (MacroAssembler::is_call_far_pcrelative(iaddr)) {
242       // Form 1): NOP, BRASL
243       // The BRASL (Branch Relative And Save Long) is patched into the space created
244       // by the load_const_from_toc_call sequence (typically (LARL-LG)/LGRL - BASR.
245       // The BRASL must be positioned such that it's end is FW (4-byte) aligned (for atomic patching).
246       // It is achieved by aligning the end of the entire sequence on a 4byte boundary, by inserting
247       // a nop, if required, at the very beginning of the instruction sequence. The nop needs to
248       // be accounted for when calculating the next instruction address. The alignment takes place
249       // already when generating the original instruction sequence. The alignment requirement
250       // makes the size depend on location.
251       // The return address of the call must always be at the end of the instruction sequence.
252       // Inserting the extra alignment nop (or anything else) at the end is not an option.
253       // The patched-in brasl instruction is prepended with a nop to make it easier to
254       // distinguish from a load_const_from_toc_call sequence.
255       return addr_at(MacroAssembler::call_far_pcrelative_size());
256     }
257 
258     ((NativeCall*)iaddr)->print();
259     guarantee(false, "Not a NativeCall site");
260     return NULL;
261   }
262 
263   address return_address() const {
264     return next_instruction_address();
265   }
266 
267   address destination() const;
268 
269   void set_destination_mt_safe(address dest);
270 
271   void verify_alignment() {} // Yet another real do nothing guy :)
272   void verify();
273 
274   // Creation.
275   friend NativeCall* nativeCall_at(address instr) {
276     NativeCall* call;
277 
278     // Make sure not to return garbage.
279     if (NativeCall::is_call_at(instr)) {
280       call = (NativeCall*)instr;
281     } else {
282       call = (NativeCall*)instr;
283       call->print();
284       guarantee(false, "Not a NativeCall site");
285     }
286 
287 #ifdef ASSERT
288     call->verify();
289 #endif
290     return call;
291   }
292 
293   // This is a very tricky function to implement. It involves stepping
294   // backwards in the instruction stream. On architectures with variable
295   // instruction length, this is a risky endeavor. From the return address,
296   // you do not know how far to step back to be at a location (your starting
297   // point) that will eventually bring you back to the return address.
298   // Furthermore, it may happen that there are multiple starting points.
299   //
300   // With only a few possible (allowed) code patterns, the risk is lower but
301   // does not diminish completely. Experience shows that there are code patterns
302   // which look like a load_const_from_toc_call @(return address-8), but in
303   // fact are a call_far_pcrelative @(return address-6). The other way around
304   // is possible as well, but was not knowingly observed so far.
305   //
306   // The unpredictability is caused by the pc-relative address field in both
307   // the call_far_pcrelative (BASR) and the load_const_from_toc (LGRL)
308   // instructions. This field can contain an arbitrary bit pattern.
309   //
310   // Here is a real-world example:
311   // Mnemonics: <not a valid sequence>   LGRL r10,<addr> BASR r14,r10
312   // Hex code:  eb01 9008 007a c498 ffff c4a8 c0e5 ffc1 0dea
313   // Mnemonics: AGSI <mem>,I8  LGRL r9,<addr> BRASL r14,<addr>  correct
314   //
315   // If you first check for a load_const_from_toc_call @(-8), you will find
316   // a false positive. In this example, it is obviously false, because the
317   // preceding bytes do not form a valid instruction pattern. If you first
318   // check for call_far_pcrelative @(-6), you get a true positive - in this
319   // case.
320   //
321   // The following remedy has been implemented/enforced:
322   // 1) Everywhere, the permissible code patterns are checked in the same
323   //    sequence: Form 2) - Form 3) - Form 1).
324   // 2) The call_far_pcrelative, which would ideally be just one BRASL
325   //    instruction, is always prepended with a NOP. This measure avoids
326   //    ambiguities with load_const_from_toc_call.
327   friend NativeCall* nativeCall_before(address return_address) {
328     NativeCall *call = NULL;
329 
330     // Make sure not to return garbage
331     address instp = return_address - MacroAssembler::load_const_call_size();
332     if (MacroAssembler::is_load_const_call(instp)) {                 // Form 2)
333       call = (NativeCall*)(instp);                                   // load_const + basr
334     } else {
335       instp = return_address - MacroAssembler::load_const_from_toc_call_size();
336       if (MacroAssembler::is_load_const_from_toc_call(instp)) {      // Form 3)
337         call = (NativeCall*)(instp);                                 // load_const_from_toc + basr
338       } else {
339         instp = return_address - MacroAssembler::call_far_pcrelative_size();
340         if (MacroAssembler::is_call_far_pcrelative(instp)) {         // Form 1)
341           call = (NativeCall*)(instp);                               // brasl (or nop + brasl)
342         } else {
343           call = (NativeCall*)(instp);
344           call->print();
345           guarantee(false, "Not a NativeCall site");
346         }
347       }
348     }
349 
350 #ifdef ASSERT
351     call->verify();
352 #endif
353     return call;
354   }
355 
356   // Ordering of checks 2) 3) 1) is relevant!
357   static bool is_call_at(address a) {
358     // Check plain instruction sequence. Do not care about filler or alignment nops.
359     bool b = MacroAssembler::is_load_const_call(a) ||           // load_const + basr
360              MacroAssembler::is_load_const_from_toc_call(a) ||  // load_const_from_toc + basr
361              MacroAssembler::is_call_far_pcrelative(a);         // nop + brasl
362     return b;
363   }
364 
365   // Ordering of checks 2) 3) 1) is relevant!
366   static bool is_call_before(address a) {
367     // check plain instruction sequence. Do not care about filler or alignment nops.
368     bool b = MacroAssembler::is_load_const_call(         a - MacroAssembler::load_const_call_size()) ||           // load_const + basr
369              MacroAssembler::is_load_const_from_toc_call(a - MacroAssembler::load_const_from_toc_call_size()) ||  // load_const_from_toc + basr
370              MacroAssembler::is_call_far_pcrelative(     a - MacroAssembler::call_far_pcrelative_size());         // nop+brasl
371     return b;
372   }
373 
374   static bool is_call_to(address instr, address target) {
375     // Check whether there is a `NativeCall' at the address `instr'
376     // calling to the address `target'.
377     return is_call_at(instr) && target == ((NativeCall *)instr)->destination();
378   }
379 
380   bool is_pcrelative() {
381     return MacroAssembler::is_call_far_pcrelative((address)this);
382   }
383 };
384 
385 //-----------------------------
386 //  N a t i v e F a r C a l l
387 //-----------------------------
388 
389 // The NativeFarCall is an abstraction for accessing/manipulating native
390 // call-anywhere instructions.
391 // Used to call native methods which may be loaded anywhere in the address
392 // space, possibly out of reach of a call instruction.
393 
394 // Refer to NativeCall for a description of the supported call forms.
395 
396 class NativeFarCall: public NativeInstruction {
397 
398  public:
399   // We use MacroAssembler::call_far_patchable() for implementing a
400   // call-anywhere instruction.
401 
402   static int instruction_size()      { return MacroAssembler::call_far_patchable_size(); }
403   static int return_address_offset() { return MacroAssembler::call_far_patchable_ret_addr_offset(); }
404 
405   // address instruction_address() const { return addr_at(0); }
406 
407   address next_instruction_address() const {
408     return addr_at(instruction_size());
409   }
410 
411   address return_address() const {
412     return addr_at(return_address_offset());
413   }
414 
415   // Returns the NativeFarCall's destination.
416   address destination();
417 
418   // Sets the NativeCall's destination, not necessarily mt-safe.
419   // Used when relocating code.
420   void set_destination(address dest, int toc_offset);
421 
422   // Checks whether instr points at a NativeFarCall instruction.
423   static bool is_far_call_at(address instr) {
424     // Use compound inspection function which, in addition to instruction sequence,
425     // also checks for expected nops and for instruction alignment.
426     return MacroAssembler::is_call_far_patchable_at(instr);
427   }
428 
429   // Does the NativeFarCall implementation use a pc-relative encoding
430   // of the call destination?
431   // Used when relocating code.
432   bool is_pcrelative() {
433     address iaddr = (address)this;
434     assert(is_far_call_at(iaddr), "unexpected call type");
435     return MacroAssembler::is_call_far_patchable_pcrelative_at(iaddr);
436   }
437 
438   void verify();
439 
440   // Instantiates a NativeFarCall object starting at the given instruction
441   // address and returns the NativeFarCall object.
442   inline friend NativeFarCall* nativeFarCall_at(address instr) {
443     NativeFarCall* call = (NativeFarCall*)instr;
444 #ifdef ASSERT
445     call->verify();
446 #endif
447     return call;
448   }
449 };
450 
451 
452 //-------------------------------------
453 //  N a t i v e M o v C o n s t R e g
454 //-------------------------------------
455 
456 // An interface for accessing/manipulating native set_oop imm, reg instructions.
457 // (Used to manipulate inlined data references, etc.)
458 
459 // A native move of a constant into a register, as defined by this abstraction layer,
460 // deals with instruction sequences that load "quasi constant" oops into registers
461 // for addressing. For multiple causes, those "quasi constant" oops eventually need
462 // to be changed (i.e. patched). The reason is quite simple: objects might get moved
463 // around in storage. Pc-relative oop addresses have to be patched also if the
464 // reference location is moved. That happens when executable code is relocated.
465 
466 class NativeMovConstReg: public NativeInstruction {
467  public:
468 
469   enum z_specific_constants {
470     instruction_size = 10 // Used in shared code for calls with reloc_info.
471   };
472 
473   // address instruction_address() const { return addr_at(0); }
474 
475   // The current instruction might be located at an offset.
476   address next_instruction_address(int offset = 0) const;
477 
478   // (The [set_]data accessor respects oop_type relocs also.)
479   intptr_t data() const;
480 
481   // Patch data in code stream.
482   address set_data_plain(intptr_t x, CodeBlob *code);
483   // Patch data in code stream and oop pool if necessary.
484   void set_data(intptr_t x, relocInfo::relocType expected_type = relocInfo::none);
485 
486   // Patch narrow oop constant in code stream.
487   void set_narrow_oop(intptr_t data);
488   void set_narrow_klass(intptr_t data);
489   void set_pcrel_addr(intptr_t addr, CompiledMethod *nm = NULL);
490   void set_pcrel_data(intptr_t data, CompiledMethod *nm = NULL);
491 
492   void verify();
493 
494   // Creation.
495   friend NativeMovConstReg* nativeMovConstReg_at(address address) {
496     NativeMovConstReg* test = (NativeMovConstReg*)address;
497     #ifdef ASSERT
498       test->verify();
499     #endif
500     return test;
501   }
502 };
503 
504 
505 #ifdef COMPILER1
506 //---------------------------------
507 //  N a t i v e M o v R e g M e m
508 //---------------------------------
509 
510 // Interface to manipulate a code sequence that performs a memory access (load/store).
511 // The code is the patchable version of memory accesses generated by
512 // LIR_Assembler::reg2mem() and LIR_Assembler::mem2reg().
513 //
514 // Loading the offset for the mem access is target of the manipulation.
515 //
516 // The instruction sequence looks like this:
517 //   iihf        %r1,$bits1              ; load offset for mem access
518 //   iilf        %r1,$bits2
519 //   [compress oop]                      ; optional, store only
520 //   load/store  %r2,0(%r1,%r2)          ; memory access
521 
522 class NativeMovRegMem;
523 inline NativeMovRegMem* nativeMovRegMem_at (address address);
524 class NativeMovRegMem: public NativeInstruction {
525  public:
526   enum z_specific_constants {
527     instruction_size = 12 // load_const used with access_field_id
528   };
529 
530   int num_bytes_to_end_of_patch() const { return instruction_size; }
531 
532   intptr_t offset() const {
533     return nativeMovConstReg_at(addr_at(0))->data();
534   }
535   void set_offset(intptr_t x) {
536     nativeMovConstReg_at(addr_at(0))->set_data(x);
537   }
538   void add_offset_in_bytes(intptr_t radd_offset) {
539     set_offset(offset() + radd_offset);
540   }
541   void verify();
542 
543  private:
544   friend inline NativeMovRegMem* nativeMovRegMem_at(address address) {
545     NativeMovRegMem* test = (NativeMovRegMem*)address;
546     #ifdef ASSERT
547       test->verify();
548     #endif
549     return test;
550   }
551 };
552 #endif // COMPILER1
553 
554 
555 //-----------------------
556 //  N a t i v e J u m p
557 //-----------------------
558 
559 
560 // An interface for accessing/manipulating native jumps
561 class NativeJump: public NativeInstruction {
562  public:
563   enum z_constants {
564     instruction_size = 2 // Size of z_illtrap().
565   };
566 
567   // Maximum size (in bytes) of a jump to an absolute address.
568   // Used when emitting branch to an exception handler which is a "load_const_optimized_branch".
569   // Thus, a pessimistic estimate is obtained when using load_const.
570   // code pattern is:
571   //   tmpReg := load_const(address);   (* varying size *)
572   //   jumpTo(tmpReg);                  (* bcr, 2 bytes *)
573   //
574   static unsigned int max_instruction_size() {
575     return MacroAssembler::load_const_size() + MacroAssembler::jump_byregister_size();
576   }
577 
578 
579 //  address instruction_address() const { return addr_at(0); }
580 
581   address jump_destination() const {
582     return (address)nativeMovConstReg_at(instruction_address())->data();
583   }
584 
585   void set_jump_destination(address dest) {
586     nativeMovConstReg_at(instruction_address())->set_data(((intptr_t)dest));
587   }
588 
589   // Creation
590   friend NativeJump* nativeJump_at(address address) {
591     NativeJump* jump = (NativeJump*)address;
592     #ifdef ASSERT
593       jump->verify();
594     #endif
595     return jump;
596   }
597 
598   static bool is_jump_at(address a) {
599     int off = 0;
600     bool b = (MacroAssembler::is_load_const_from_toc(a+off) &&
601               Assembler::is_z_br(*(short*)(a+off + MacroAssembler::load_const_from_toc_size())));
602     b = b || (MacroAssembler::is_load_const(a+off) &&
603               Assembler::is_z_br(*(short*)(a+off + MacroAssembler::load_const_size())));
604     return b;
605   }
606 
607   void verify();
608 
609   // Insertion of native jump instruction.
610   static void insert(address code_pos, address entry);
611 
612   // MT-safe insertion of native jump at verified method entry.
613   static void check_verified_entry_alignment(address entry, address verified_entry) { }
614 
615   static void patch_verified_entry(address entry, address verified_entry, address dest);
616 };
617 
618 //-------------------------------------
619 //  N a t i v e G e n e r a l J u m p
620 //-------------------------------------
621 
622 // Despite the name, handles only simple branches.
623 // On ZARCH_64 BRCL only.
624 class NativeGeneralJump;
625 inline NativeGeneralJump* nativeGeneralJump_at(address address);
626 class NativeGeneralJump: public NativeInstruction {
627  public:
628   enum ZARCH_specific_constants {
629     instruction_size = 6
630   };
631 
632   address instruction_address() const { return addr_at(0); }
633   address jump_destination()    const { return addr_at(0) + MacroAssembler::get_pcrel_offset(addr_at(0)); }
634 
635   // Creation
636   friend inline NativeGeneralJump* nativeGeneralJump_at(address addr) {
637     NativeGeneralJump* jump = (NativeGeneralJump*)(addr);
638 #ifdef ASSERT
639     jump->verify();
640 #endif
641     return jump;
642   }
643 
644   // Insertion of native general jump instruction.
645   static void insert_unconditional(address code_pos, address entry);
646 
647   void set_jump_destination(address dest) {
648     Unimplemented();
649     // set_word_at(MacroAssembler::call_far_pcrelative_size()-4, Assembler::z_pcrel_off(dest, addr_at(0)));
650   }
651 
652   static void replace_mt_safe(address instr_addr, address code_buffer);
653 
654   void verify() PRODUCT_RETURN;
655 };
656 
657 #endif // CPU_S390_NATIVEINST_S390_HPP