1 /*
   2  * Copyright (c) 2000, 2018, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/macroAssembler.hpp"
  27 #include "asm/macroAssembler.inline.hpp"
  28 #include "c1/c1_Compilation.hpp"
  29 #include "c1/c1_LIRAssembler.hpp"
  30 #include "c1/c1_MacroAssembler.hpp"
  31 #include "c1/c1_Runtime1.hpp"
  32 #include "c1/c1_ValueStack.hpp"
  33 #include "ci/ciArrayKlass.hpp"
  34 #include "ci/ciInstance.hpp"
  35 #include "gc/shared/barrierSet.hpp"
  36 #include "gc/shared/cardTableBarrierSet.hpp"
  37 #include "gc/shared/collectedHeap.hpp"
  38 #include "nativeInst_x86.hpp"
  39 #include "oops/objArrayKlass.hpp"
  40 #include "runtime/frame.inline.hpp"
  41 #include "runtime/safepointMechanism.hpp"
  42 #include "runtime/sharedRuntime.hpp"
  43 #include "vmreg_x86.inline.hpp"
  44 
  45 
  46 // These masks are used to provide 128-bit aligned bitmasks to the XMM
  47 // instructions, to allow sign-masking or sign-bit flipping.  They allow
  48 // fast versions of NegF/NegD and AbsF/AbsD.
  49 
  50 // Note: 'double' and 'long long' have 32-bits alignment on x86.
  51 static jlong* double_quadword(jlong *adr, jlong lo, jlong hi) {
  52   // Use the expression (adr)&(~0xF) to provide 128-bits aligned address
  53   // of 128-bits operands for SSE instructions.
  54   jlong *operand = (jlong*)(((intptr_t)adr) & ((intptr_t)(~0xF)));
  55   // Store the value to a 128-bits operand.
  56   operand[0] = lo;
  57   operand[1] = hi;
  58   return operand;
  59 }
  60 
  61 // Buffer for 128-bits masks used by SSE instructions.
  62 static jlong fp_signmask_pool[(4+1)*2]; // 4*128bits(data) + 128bits(alignment)
  63 
  64 // Static initialization during VM startup.
  65 static jlong *float_signmask_pool  = double_quadword(&fp_signmask_pool[1*2],         CONST64(0x7FFFFFFF7FFFFFFF),         CONST64(0x7FFFFFFF7FFFFFFF));
  66 static jlong *double_signmask_pool = double_quadword(&fp_signmask_pool[2*2],         CONST64(0x7FFFFFFFFFFFFFFF),         CONST64(0x7FFFFFFFFFFFFFFF));
  67 static jlong *float_signflip_pool  = double_quadword(&fp_signmask_pool[3*2], (jlong)UCONST64(0x8000000080000000), (jlong)UCONST64(0x8000000080000000));
  68 static jlong *double_signflip_pool = double_quadword(&fp_signmask_pool[4*2], (jlong)UCONST64(0x8000000000000000), (jlong)UCONST64(0x8000000000000000));
  69 
  70 
  71 NEEDS_CLEANUP // remove this definitions ?
  72 const Register IC_Klass    = rax;   // where the IC klass is cached
  73 const Register SYNC_header = rax;   // synchronization header
  74 const Register SHIFT_count = rcx;   // where count for shift operations must be
  75 
  76 #define __ _masm->
  77 
  78 
  79 static void select_different_registers(Register preserve,
  80                                        Register extra,
  81                                        Register &tmp1,
  82                                        Register &tmp2) {
  83   if (tmp1 == preserve) {
  84     assert_different_registers(tmp1, tmp2, extra);
  85     tmp1 = extra;
  86   } else if (tmp2 == preserve) {
  87     assert_different_registers(tmp1, tmp2, extra);
  88     tmp2 = extra;
  89   }
  90   assert_different_registers(preserve, tmp1, tmp2);
  91 }
  92 
  93 
  94 
  95 static void select_different_registers(Register preserve,
  96                                        Register extra,
  97                                        Register &tmp1,
  98                                        Register &tmp2,
  99                                        Register &tmp3) {
 100   if (tmp1 == preserve) {
 101     assert_different_registers(tmp1, tmp2, tmp3, extra);
 102     tmp1 = extra;
 103   } else if (tmp2 == preserve) {
 104     assert_different_registers(tmp1, tmp2, tmp3, extra);
 105     tmp2 = extra;
 106   } else if (tmp3 == preserve) {
 107     assert_different_registers(tmp1, tmp2, tmp3, extra);
 108     tmp3 = extra;
 109   }
 110   assert_different_registers(preserve, tmp1, tmp2, tmp3);
 111 }
 112 
 113 
 114 
 115 bool LIR_Assembler::is_small_constant(LIR_Opr opr) {
 116   if (opr->is_constant()) {
 117     LIR_Const* constant = opr->as_constant_ptr();
 118     switch (constant->type()) {
 119       case T_INT: {
 120         return true;
 121       }
 122 
 123       default:
 124         return false;
 125     }
 126   }
 127   return false;
 128 }
 129 
 130 
 131 LIR_Opr LIR_Assembler::receiverOpr() {
 132   return FrameMap::receiver_opr;
 133 }
 134 
 135 LIR_Opr LIR_Assembler::osrBufferPointer() {
 136   return FrameMap::as_pointer_opr(receiverOpr()->as_register());
 137 }
 138 
 139 //--------------fpu register translations-----------------------
 140 
 141 
 142 address LIR_Assembler::float_constant(float f) {
 143   address const_addr = __ float_constant(f);
 144   if (const_addr == NULL) {
 145     bailout("const section overflow");
 146     return __ code()->consts()->start();
 147   } else {
 148     return const_addr;
 149   }
 150 }
 151 
 152 
 153 address LIR_Assembler::double_constant(double d) {
 154   address const_addr = __ double_constant(d);
 155   if (const_addr == NULL) {
 156     bailout("const section overflow");
 157     return __ code()->consts()->start();
 158   } else {
 159     return const_addr;
 160   }
 161 }
 162 
 163 
 164 void LIR_Assembler::set_24bit_FPU() {
 165   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24()));
 166 }
 167 
 168 void LIR_Assembler::reset_FPU() {
 169   __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
 170 }
 171 
 172 void LIR_Assembler::fpop() {
 173   __ fpop();
 174 }
 175 
 176 void LIR_Assembler::fxch(int i) {
 177   __ fxch(i);
 178 }
 179 
 180 void LIR_Assembler::fld(int i) {
 181   __ fld_s(i);
 182 }
 183 
 184 void LIR_Assembler::ffree(int i) {
 185   __ ffree(i);
 186 }
 187 
 188 void LIR_Assembler::breakpoint() {
 189   __ int3();
 190 }
 191 
 192 void LIR_Assembler::push(LIR_Opr opr) {
 193   if (opr->is_single_cpu()) {
 194     __ push_reg(opr->as_register());
 195   } else if (opr->is_double_cpu()) {
 196     NOT_LP64(__ push_reg(opr->as_register_hi()));
 197     __ push_reg(opr->as_register_lo());
 198   } else if (opr->is_stack()) {
 199     __ push_addr(frame_map()->address_for_slot(opr->single_stack_ix()));
 200   } else if (opr->is_constant()) {
 201     LIR_Const* const_opr = opr->as_constant_ptr();
 202     if (const_opr->type() == T_OBJECT) {
 203       __ push_oop(const_opr->as_jobject());
 204     } else if (const_opr->type() == T_INT) {
 205       __ push_jint(const_opr->as_jint());
 206     } else {
 207       ShouldNotReachHere();
 208     }
 209 
 210   } else {
 211     ShouldNotReachHere();
 212   }
 213 }
 214 
 215 void LIR_Assembler::pop(LIR_Opr opr) {
 216   if (opr->is_single_cpu()) {
 217     __ pop_reg(opr->as_register());
 218   } else {
 219     ShouldNotReachHere();
 220   }
 221 }
 222 
 223 void LIR_Assembler::getfp(LIR_Opr opr) {
 224   __ lea(opr->as_register_lo(), Address(rsp, initial_frame_size_in_bytes() + wordSize)); // + wordSize seems to be required to handle the push rbp before the sub of rsp
 225 }
 226 
 227 void LIR_Assembler::getsp(LIR_Opr opr) {
 228   __ movptr(opr->as_register_lo(), rsp);
 229 }
 230 
 231 #if 0
 232 void LIR_Assembler::getpc(LIR_Opr opr) {
 233   const char *name + "cont_getPC";
 234   address entry = StubRoutines::cont_getPC();
 235   __ call_VM_leaf(entry, 0);
 236   __ movptr(opr->as_register_lo(), rax);
 237 }
 238 #endif
 239 
 240 bool LIR_Assembler::is_literal_address(LIR_Address* addr) {
 241   return addr->base()->is_illegal() && addr->index()->is_illegal();
 242 }
 243 
 244 //-------------------------------------------
 245 
 246 Address LIR_Assembler::as_Address(LIR_Address* addr) {
 247   return as_Address(addr, rscratch1);
 248 }
 249 
 250 Address LIR_Assembler::as_Address(LIR_Address* addr, Register tmp) {
 251   if (addr->base()->is_illegal()) {
 252     assert(addr->index()->is_illegal(), "must be illegal too");
 253     AddressLiteral laddr((address)addr->disp(), relocInfo::none);
 254     if (! __ reachable(laddr)) {
 255       __ movptr(tmp, laddr.addr());
 256       Address res(tmp, 0);
 257       return res;
 258     } else {
 259       return __ as_Address(laddr);
 260     }
 261   }
 262 
 263   Register base = addr->base()->as_pointer_register();
 264 
 265   if (addr->index()->is_illegal()) {
 266     return Address( base, addr->disp());
 267   } else if (addr->index()->is_cpu_register()) {
 268     Register index = addr->index()->as_pointer_register();
 269     return Address(base, index, (Address::ScaleFactor) addr->scale(), addr->disp());
 270   } else if (addr->index()->is_constant()) {
 271     intptr_t addr_offset = (addr->index()->as_constant_ptr()->as_jint() << addr->scale()) + addr->disp();
 272     assert(Assembler::is_simm32(addr_offset), "must be");
 273 
 274     return Address(base, addr_offset);
 275   } else {
 276     Unimplemented();
 277     return Address();
 278   }
 279 }
 280 
 281 
 282 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) {
 283   Address base = as_Address(addr);
 284   return Address(base._base, base._index, base._scale, base._disp + BytesPerWord);
 285 }
 286 
 287 
 288 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) {
 289   return as_Address(addr);
 290 }
 291 
 292 
 293 void LIR_Assembler::osr_entry() {
 294   offsets()->set_value(CodeOffsets::OSR_Entry, code_offset());
 295   BlockBegin* osr_entry = compilation()->hir()->osr_entry();
 296   ValueStack* entry_state = osr_entry->state();
 297   int number_of_locks = entry_state->locks_size();
 298 
 299   // we jump here if osr happens with the interpreter
 300   // state set up to continue at the beginning of the
 301   // loop that triggered osr - in particular, we have
 302   // the following registers setup:
 303   //
 304   // rcx: osr buffer
 305   //
 306 
 307   // build frame
 308   ciMethod* m = compilation()->method();
 309   __ build_frame(initial_frame_size_in_bytes(), bang_size_in_bytes());
 310 
 311   // OSR buffer is
 312   //
 313   // locals[nlocals-1..0]
 314   // monitors[0..number_of_locks]
 315   //
 316   // locals is a direct copy of the interpreter frame so in the osr buffer
 317   // so first slot in the local array is the last local from the interpreter
 318   // and last slot is local[0] (receiver) from the interpreter
 319   //
 320   // Similarly with locks. The first lock slot in the osr buffer is the nth lock
 321   // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock
 322   // in the interpreter frame (the method lock if a sync method)
 323 
 324   // Initialize monitors in the compiled activation.
 325   //   rcx: pointer to osr buffer
 326   //
 327   // All other registers are dead at this point and the locals will be
 328   // copied into place by code emitted in the IR.
 329 
 330   Register OSR_buf = osrBufferPointer()->as_pointer_register();
 331   { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below");
 332     int monitor_offset = BytesPerWord * method()->max_locals() +
 333       (BasicObjectLock::size() * BytesPerWord) * (number_of_locks - 1);
 334     // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in
 335     // the OSR buffer using 2 word entries: first the lock and then
 336     // the oop.
 337     for (int i = 0; i < number_of_locks; i++) {
 338       int slot_offset = monitor_offset - ((i * 2) * BytesPerWord);
 339 #ifdef ASSERT
 340       // verify the interpreter's monitor has a non-null object
 341       {
 342         Label L;
 343         __ cmpptr(Address(OSR_buf, slot_offset + 1*BytesPerWord), (int32_t)NULL_WORD);
 344         __ jcc(Assembler::notZero, L);
 345         __ stop("locked object is NULL");
 346         __ bind(L);
 347       }
 348 #endif
 349       __ movptr(rbx, Address(OSR_buf, slot_offset + 0));
 350       __ movptr(frame_map()->address_for_monitor_lock(i), rbx);
 351       __ movptr(rbx, Address(OSR_buf, slot_offset + 1*BytesPerWord));
 352       __ movptr(frame_map()->address_for_monitor_object(i), rbx);
 353     }
 354   }
 355 }
 356 
 357 
 358 // inline cache check; done before the frame is built.
 359 int LIR_Assembler::check_icache() {
 360   Register receiver = FrameMap::receiver_opr->as_register();
 361   Register ic_klass = IC_Klass;
 362   const int ic_cmp_size = LP64_ONLY(10) NOT_LP64(9);
 363   const bool do_post_padding = VerifyOops || UseCompressedClassPointers;
 364   if (!do_post_padding) {
 365     // insert some nops so that the verified entry point is aligned on CodeEntryAlignment
 366     __ align(CodeEntryAlignment, __ offset() + ic_cmp_size);
 367   }
 368   int offset = __ offset();
 369   __ inline_cache_check(receiver, IC_Klass);
 370   assert(__ offset() % CodeEntryAlignment == 0 || do_post_padding, "alignment must be correct");
 371   if (do_post_padding) {
 372     // force alignment after the cache check.
 373     // It's been verified to be aligned if !VerifyOops
 374     __ align(CodeEntryAlignment);
 375   }
 376   return offset;
 377 }
 378 
 379 void LIR_Assembler::clinit_barrier(ciMethod* method) {
 380   assert(VM_Version::supports_fast_class_init_checks(), "sanity");
 381   assert(!method->holder()->is_not_initialized(), "initialization should have been started");
 382 
 383   Label L_skip_barrier;
 384   Register klass = rscratch1;
 385   Register thread = LP64_ONLY( r15_thread ) NOT_LP64( noreg );
 386   assert(thread != noreg, "x86_32 not implemented");
 387 
 388   __ mov_metadata(klass, method->holder()->constant_encoding());
 389   __ clinit_barrier(klass, thread, &L_skip_barrier /*L_fast_path*/);
 390 
 391   __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub()));
 392 
 393   __ bind(L_skip_barrier);
 394 }
 395 
 396 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo* info) {
 397   jobject o = NULL;
 398   PatchingStub* patch = new PatchingStub(_masm, patching_id(info));
 399   __ movoop(reg, o);
 400   patching_epilog(patch, lir_patch_normal, reg, info);
 401 }
 402 
 403 void LIR_Assembler::klass2reg_with_patching(Register reg, CodeEmitInfo* info) {
 404   Metadata* o = NULL;
 405   PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id);
 406   __ mov_metadata(reg, o);
 407   patching_epilog(patch, lir_patch_normal, reg, info);
 408 }
 409 
 410 // This specifies the rsp decrement needed to build the frame
 411 int LIR_Assembler::initial_frame_size_in_bytes() const {
 412   // if rounding, must let FrameMap know!
 413 
 414   // The frame_map records size in slots (32bit word)
 415 
 416   // subtract two words to account for return address and link
 417   return (frame_map()->framesize() - (2*VMRegImpl::slots_per_word))  * VMRegImpl::stack_slot_size;
 418 }
 419 
 420 
 421 int LIR_Assembler::emit_exception_handler() {
 422   // if the last instruction is a call (typically to do a throw which
 423   // is coming at the end after block reordering) the return address
 424   // must still point into the code area in order to avoid assertion
 425   // failures when searching for the corresponding bci => add a nop
 426   // (was bug 5/14/1999 - gri)
 427   __ nop();
 428 
 429   // generate code for exception handler
 430   address handler_base = __ start_a_stub(exception_handler_size());
 431   if (handler_base == NULL) {
 432     // not enough space left for the handler
 433     bailout("exception handler overflow");
 434     return -1;
 435   }
 436 
 437   int offset = code_offset();
 438 
 439   // the exception oop and pc are in rax, and rdx
 440   // no other registers need to be preserved, so invalidate them
 441   __ invalidate_registers(false, true, true, false, true, true);
 442 
 443   // check that there is really an exception
 444   __ verify_not_null_oop(rax);
 445 
 446   // search an exception handler (rax: exception oop, rdx: throwing pc)
 447   __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::handle_exception_from_callee_id)));
 448   __ should_not_reach_here();
 449   guarantee(code_offset() - offset <= exception_handler_size(), "overflow");
 450   __ end_a_stub();
 451 
 452   return offset;
 453 }
 454 
 455 
 456 // Emit the code to remove the frame from the stack in the exception
 457 // unwind path.
 458 int LIR_Assembler::emit_unwind_handler() {
 459 #ifndef PRODUCT
 460   if (CommentedAssembly) {
 461     _masm->block_comment("Unwind handler");
 462   }
 463 #endif
 464 
 465   int offset = code_offset();
 466 
 467   // Fetch the exception from TLS and clear out exception related thread state
 468   Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
 469   NOT_LP64(__ get_thread(rsi));
 470   __ movptr(rax, Address(thread, JavaThread::exception_oop_offset()));
 471   __ movptr(Address(thread, JavaThread::exception_oop_offset()), (intptr_t)NULL_WORD);
 472   __ movptr(Address(thread, JavaThread::exception_pc_offset()), (intptr_t)NULL_WORD);
 473 
 474   __ bind(_unwind_handler_entry);
 475   __ verify_not_null_oop(rax);
 476   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 477     __ mov(rbx, rax);  // Preserve the exception (rbx is always callee-saved)
 478   }
 479 
 480   // Preform needed unlocking
 481   MonitorExitStub* stub = NULL;
 482   if (method()->is_synchronized()) {
 483     monitor_address(0, FrameMap::rax_opr);
 484     stub = new MonitorExitStub(FrameMap::rax_opr, true, 0);
 485     __ unlock_object(rdi, rsi, rax, *stub->entry());
 486     __ bind(*stub->continuation());
 487   }
 488 
 489   if (compilation()->env()->dtrace_method_probes()) {
 490 #ifdef _LP64
 491     __ mov(rdi, r15_thread);
 492     __ mov_metadata(rsi, method()->constant_encoding());
 493 #else
 494     __ get_thread(rax);
 495     __ movptr(Address(rsp, 0), rax);
 496     __ mov_metadata(Address(rsp, sizeof(void*)), method()->constant_encoding());
 497 #endif
 498     __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit)));
 499   }
 500 
 501   if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) {
 502     __ mov(rax, rbx);  // Restore the exception
 503   }
 504 
 505   // remove the activation and dispatch to the unwind handler
 506   __ remove_frame(initial_frame_size_in_bytes());
 507   __ jump(RuntimeAddress(Runtime1::entry_for(Runtime1::unwind_exception_id)));
 508 
 509   // Emit the slow path assembly
 510   if (stub != NULL) {
 511     stub->emit_code(this);
 512   }
 513 
 514   return offset;
 515 }
 516 
 517 
 518 int LIR_Assembler::emit_deopt_handler() {
 519   // if the last instruction is a call (typically to do a throw which
 520   // is coming at the end after block reordering) the return address
 521   // must still point into the code area in order to avoid assertion
 522   // failures when searching for the corresponding bci => add a nop
 523   // (was bug 5/14/1999 - gri)
 524   __ nop();
 525 
 526   // generate code for exception handler
 527   address handler_base = __ start_a_stub(deopt_handler_size());
 528   if (handler_base == NULL) {
 529     // not enough space left for the handler
 530     bailout("deopt handler overflow");
 531     return -1;
 532   }
 533 
 534   int offset = code_offset();
 535   InternalAddress here(__ pc());
 536 
 537   __ pushptr(here.addr());
 538   __ jump(RuntimeAddress(SharedRuntime::deopt_blob()->unpack()));
 539   guarantee(code_offset() - offset <= deopt_handler_size(), "overflow");
 540   __ end_a_stub();
 541 
 542   return offset;
 543 }
 544 
 545 
 546 void LIR_Assembler::return_op(LIR_Opr result) {
 547   assert(result->is_illegal() || !result->is_single_cpu() || result->as_register() == rax, "word returns are in rax,");
 548   if (!result->is_illegal() && result->is_float_kind() && !result->is_xmm_register()) {
 549     assert(result->fpu() == 0, "result must already be on TOS");
 550   }
 551 
 552   // Pop the stack before the safepoint code
 553   __ remove_frame(initial_frame_size_in_bytes());
 554 
 555   if (StackReservedPages > 0 && compilation()->has_reserved_stack_access()) {
 556     __ reserved_stack_check();
 557   }
 558 
 559   bool result_is_oop = result->is_valid() ? result->is_oop() : false;
 560 
 561   // Note: we do not need to round double result; float result has the right precision
 562   // the poll sets the condition code, but no data registers
 563 
 564   if (SafepointMechanism::uses_thread_local_poll()) {
 565 #ifdef _LP64
 566     const Register poll_addr = rscratch1;
 567     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 568 #else
 569     const Register poll_addr = rbx;
 570     assert(FrameMap::is_caller_save_register(poll_addr), "will overwrite");
 571     __ get_thread(poll_addr);
 572     __ movptr(poll_addr, Address(poll_addr, Thread::polling_page_offset()));
 573 #endif
 574     __ relocate(relocInfo::poll_return_type);
 575     __ testl(rax, Address(poll_addr, 0));
 576   } else {
 577     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
 578 
 579     if (Assembler::is_polling_page_far()) {
 580       __ lea(rscratch1, polling_page);
 581       __ relocate(relocInfo::poll_return_type);
 582       __ testl(rax, Address(rscratch1, 0));
 583     } else {
 584       __ testl(rax, polling_page);
 585     }
 586   }
 587   __ ret(0);
 588 }
 589 
 590 
 591 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) {
 592   guarantee(info != NULL, "Shouldn't be NULL");
 593   int offset = __ offset();
 594   if (SafepointMechanism::uses_thread_local_poll()) {
 595 #ifdef _LP64
 596     const Register poll_addr = rscratch1;
 597     __ movptr(poll_addr, Address(r15_thread, Thread::polling_page_offset()));
 598 #else
 599     assert(tmp->is_cpu_register(), "needed");
 600     const Register poll_addr = tmp->as_register();
 601     __ get_thread(poll_addr);
 602     __ movptr(poll_addr, Address(poll_addr, in_bytes(Thread::polling_page_offset())));
 603 #endif
 604     add_debug_info_for_branch(info);
 605     __ relocate(relocInfo::poll_type);
 606     address pre_pc = __ pc();
 607     __ testl(rax, Address(poll_addr, 0));
 608     address post_pc = __ pc();
 609     guarantee(pointer_delta(post_pc, pre_pc, 1) == 2 LP64_ONLY(+1), "must be exact length");
 610   } else {
 611     AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_type);
 612     if (Assembler::is_polling_page_far()) {
 613       __ lea(rscratch1, polling_page);
 614       offset = __ offset();
 615       add_debug_info_for_branch(info);
 616       __ relocate(relocInfo::poll_type);
 617       __ testl(rax, Address(rscratch1, 0));
 618     } else {
 619       add_debug_info_for_branch(info);
 620       __ testl(rax, polling_page);
 621     }
 622   }
 623   return offset;
 624 }
 625 
 626 
 627 void LIR_Assembler::move_regs(Register from_reg, Register to_reg) {
 628   if (from_reg != to_reg) __ mov(to_reg, from_reg);
 629 }
 630 
 631 void LIR_Assembler::swap_reg(Register a, Register b) {
 632   __ xchgptr(a, b);
 633 }
 634 
 635 
 636 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
 637   assert(src->is_constant(), "should not call otherwise");
 638   assert(dest->is_register(), "should not call otherwise");
 639   LIR_Const* c = src->as_constant_ptr();
 640 
 641   switch (c->type()) {
 642     case T_INT: {
 643       assert(patch_code == lir_patch_none, "no patching handled here");
 644       __ movl(dest->as_register(), c->as_jint());
 645       break;
 646     }
 647 
 648     case T_ADDRESS: {
 649       assert(patch_code == lir_patch_none, "no patching handled here");
 650       __ movptr(dest->as_register(), c->as_jint());
 651       break;
 652     }
 653 
 654     case T_LONG: {
 655       assert(patch_code == lir_patch_none, "no patching handled here");
 656 #ifdef _LP64
 657       __ movptr(dest->as_register_lo(), (intptr_t)c->as_jlong());
 658 #else
 659       __ movptr(dest->as_register_lo(), c->as_jint_lo());
 660       __ movptr(dest->as_register_hi(), c->as_jint_hi());
 661 #endif // _LP64
 662       break;
 663     }
 664 
 665     case T_OBJECT: {
 666       if (patch_code != lir_patch_none) {
 667         jobject2reg_with_patching(dest->as_register(), info);
 668       } else {
 669         __ movoop(dest->as_register(), c->as_jobject());
 670       }
 671       break;
 672     }
 673 
 674     case T_METADATA: {
 675       if (patch_code != lir_patch_none) {
 676         klass2reg_with_patching(dest->as_register(), info);
 677       } else {
 678         __ mov_metadata(dest->as_register(), c->as_metadata());
 679       }
 680       break;
 681     }
 682 
 683     case T_FLOAT: {
 684       if (dest->is_single_xmm()) {
 685         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_float()) {
 686           __ xorps(dest->as_xmm_float_reg(), dest->as_xmm_float_reg());
 687         } else {
 688           __ movflt(dest->as_xmm_float_reg(),
 689                    InternalAddress(float_constant(c->as_jfloat())));
 690         }
 691       } else {
 692         assert(dest->is_single_fpu(), "must be");
 693         assert(dest->fpu_regnr() == 0, "dest must be TOS");
 694         if (c->is_zero_float()) {
 695           __ fldz();
 696         } else if (c->is_one_float()) {
 697           __ fld1();
 698         } else {
 699           __ fld_s (InternalAddress(float_constant(c->as_jfloat())));
 700         }
 701       }
 702       break;
 703     }
 704 
 705     case T_DOUBLE: {
 706       if (dest->is_double_xmm()) {
 707         if (LP64_ONLY(UseAVX <= 2 &&) c->is_zero_double()) {
 708           __ xorpd(dest->as_xmm_double_reg(), dest->as_xmm_double_reg());
 709         } else {
 710           __ movdbl(dest->as_xmm_double_reg(),
 711                     InternalAddress(double_constant(c->as_jdouble())));
 712         }
 713       } else {
 714         assert(dest->is_double_fpu(), "must be");
 715         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
 716         if (c->is_zero_double()) {
 717           __ fldz();
 718         } else if (c->is_one_double()) {
 719           __ fld1();
 720         } else {
 721           __ fld_d (InternalAddress(double_constant(c->as_jdouble())));
 722         }
 723       }
 724       break;
 725     }
 726 
 727     default:
 728       ShouldNotReachHere();
 729   }
 730 }
 731 
 732 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) {
 733   assert(src->is_constant(), "should not call otherwise");
 734   assert(dest->is_stack(), "should not call otherwise");
 735   LIR_Const* c = src->as_constant_ptr();
 736 
 737   switch (c->type()) {
 738     case T_INT:  // fall through
 739     case T_FLOAT:
 740       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 741       break;
 742 
 743     case T_ADDRESS:
 744       __ movptr(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jint_bits());
 745       break;
 746 
 747     case T_OBJECT:
 748       __ movoop(frame_map()->address_for_slot(dest->single_stack_ix()), c->as_jobject());
 749       break;
 750 
 751     case T_LONG:  // fall through
 752     case T_DOUBLE:
 753 #ifdef _LP64
 754       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 755                                             lo_word_offset_in_bytes), (intptr_t)c->as_jlong_bits());
 756 #else
 757       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 758                                               lo_word_offset_in_bytes), c->as_jint_lo_bits());
 759       __ movptr(frame_map()->address_for_slot(dest->double_stack_ix(),
 760                                               hi_word_offset_in_bytes), c->as_jint_hi_bits());
 761 #endif // _LP64
 762       break;
 763 
 764     default:
 765       ShouldNotReachHere();
 766   }
 767 }
 768 
 769 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info, bool wide) {
 770   assert(src->is_constant(), "should not call otherwise");
 771   assert(dest->is_address(), "should not call otherwise");
 772   LIR_Const* c = src->as_constant_ptr();
 773   LIR_Address* addr = dest->as_address_ptr();
 774 
 775   int null_check_here = code_offset();
 776   switch (type) {
 777     case T_INT:    // fall through
 778     case T_FLOAT:
 779       __ movl(as_Address(addr), c->as_jint_bits());
 780       break;
 781 
 782     case T_ADDRESS:
 783       __ movptr(as_Address(addr), c->as_jint_bits());
 784       break;
 785 
 786     case T_OBJECT:  // fall through
 787     case T_ARRAY:
 788       if (c->as_jobject() == NULL) {
 789         if (UseCompressedOops && !wide) {
 790           __ movl(as_Address(addr), (int32_t)NULL_WORD);
 791         } else {
 792 #ifdef _LP64
 793           __ xorptr(rscratch1, rscratch1);
 794           null_check_here = code_offset();
 795           __ movptr(as_Address(addr), rscratch1);
 796 #else
 797           __ movptr(as_Address(addr), NULL_WORD);
 798 #endif
 799         }
 800       } else {
 801         if (is_literal_address(addr)) {
 802           ShouldNotReachHere();
 803           __ movoop(as_Address(addr, noreg), c->as_jobject());
 804         } else {
 805 #ifdef _LP64
 806           __ movoop(rscratch1, c->as_jobject());
 807           if (UseCompressedOops && !wide) {
 808             __ encode_heap_oop(rscratch1);
 809             null_check_here = code_offset();
 810             __ movl(as_Address_lo(addr), rscratch1);
 811           } else {
 812             null_check_here = code_offset();
 813             __ movptr(as_Address_lo(addr), rscratch1);
 814           }
 815 #else
 816           __ movoop(as_Address(addr), c->as_jobject());
 817 #endif
 818         }
 819       }
 820       break;
 821 
 822     case T_LONG:    // fall through
 823     case T_DOUBLE:
 824 #ifdef _LP64
 825       if (is_literal_address(addr)) {
 826         ShouldNotReachHere();
 827         __ movptr(as_Address(addr, r15_thread), (intptr_t)c->as_jlong_bits());
 828       } else {
 829         __ movptr(r10, (intptr_t)c->as_jlong_bits());
 830         null_check_here = code_offset();
 831         __ movptr(as_Address_lo(addr), r10);
 832       }
 833 #else
 834       // Always reachable in 32bit so this doesn't produce useless move literal
 835       __ movptr(as_Address_hi(addr), c->as_jint_hi_bits());
 836       __ movptr(as_Address_lo(addr), c->as_jint_lo_bits());
 837 #endif // _LP64
 838       break;
 839 
 840     case T_BOOLEAN: // fall through
 841     case T_BYTE:
 842       __ movb(as_Address(addr), c->as_jint() & 0xFF);
 843       break;
 844 
 845     case T_CHAR:    // fall through
 846     case T_SHORT:
 847       __ movw(as_Address(addr), c->as_jint() & 0xFFFF);
 848       break;
 849 
 850     default:
 851       ShouldNotReachHere();
 852   };
 853 
 854   if (info != NULL) {
 855     add_debug_info_for_null_check(null_check_here, info);
 856   }
 857 }
 858 
 859 
 860 void LIR_Assembler::reg2reg(LIR_Opr src, LIR_Opr dest) {
 861   assert(src->is_register(), "should not call otherwise");
 862   assert(dest->is_register(), "should not call otherwise");
 863 
 864   // move between cpu-registers
 865   if (dest->is_single_cpu()) {
 866 #ifdef _LP64
 867     if (src->type() == T_LONG) {
 868       // Can do LONG -> OBJECT
 869       move_regs(src->as_register_lo(), dest->as_register());
 870       return;
 871     }
 872 #endif
 873     assert(src->is_single_cpu(), "must match");
 874     if (src->type() == T_OBJECT) {
 875       __ verify_oop(src->as_register());
 876     }
 877     move_regs(src->as_register(), dest->as_register());
 878 
 879   } else if (dest->is_double_cpu()) {
 880 #ifdef _LP64
 881     if (src->type() == T_OBJECT || src->type() == T_ARRAY) {
 882       // Surprising to me but we can see move of a long to t_object
 883       __ verify_oop(src->as_register());
 884       move_regs(src->as_register(), dest->as_register_lo());
 885       return;
 886     }
 887 #endif
 888     assert(src->is_double_cpu(), "must match");
 889     Register f_lo = src->as_register_lo();
 890     Register f_hi = src->as_register_hi();
 891     Register t_lo = dest->as_register_lo();
 892     Register t_hi = dest->as_register_hi();
 893 #ifdef _LP64
 894     assert(f_hi == f_lo, "must be same");
 895     assert(t_hi == t_lo, "must be same");
 896     move_regs(f_lo, t_lo);
 897 #else
 898     assert(f_lo != f_hi && t_lo != t_hi, "invalid register allocation");
 899 
 900 
 901     if (f_lo == t_hi && f_hi == t_lo) {
 902       swap_reg(f_lo, f_hi);
 903     } else if (f_hi == t_lo) {
 904       assert(f_lo != t_hi, "overwriting register");
 905       move_regs(f_hi, t_hi);
 906       move_regs(f_lo, t_lo);
 907     } else {
 908       assert(f_hi != t_lo, "overwriting register");
 909       move_regs(f_lo, t_lo);
 910       move_regs(f_hi, t_hi);
 911     }
 912 #endif // LP64
 913 
 914     // special moves from fpu-register to xmm-register
 915     // necessary for method results
 916   } else if (src->is_single_xmm() && !dest->is_single_xmm()) {
 917     __ movflt(Address(rsp, 0), src->as_xmm_float_reg());
 918     __ fld_s(Address(rsp, 0));
 919   } else if (src->is_double_xmm() && !dest->is_double_xmm()) {
 920     __ movdbl(Address(rsp, 0), src->as_xmm_double_reg());
 921     __ fld_d(Address(rsp, 0));
 922   } else if (dest->is_single_xmm() && !src->is_single_xmm()) {
 923     __ fstp_s(Address(rsp, 0));
 924     __ movflt(dest->as_xmm_float_reg(), Address(rsp, 0));
 925   } else if (dest->is_double_xmm() && !src->is_double_xmm()) {
 926     __ fstp_d(Address(rsp, 0));
 927     __ movdbl(dest->as_xmm_double_reg(), Address(rsp, 0));
 928 
 929     // move between xmm-registers
 930   } else if (dest->is_single_xmm()) {
 931     assert(src->is_single_xmm(), "must match");
 932     __ movflt(dest->as_xmm_float_reg(), src->as_xmm_float_reg());
 933   } else if (dest->is_double_xmm()) {
 934     assert(src->is_double_xmm(), "must match");
 935     __ movdbl(dest->as_xmm_double_reg(), src->as_xmm_double_reg());
 936 
 937     // move between fpu-registers (no instruction necessary because of fpu-stack)
 938   } else if (dest->is_single_fpu() || dest->is_double_fpu()) {
 939     assert(src->is_single_fpu() || src->is_double_fpu(), "must match");
 940     assert(src->fpu() == dest->fpu(), "currently should be nothing to do");
 941   } else {
 942     ShouldNotReachHere();
 943   }
 944 }
 945 
 946 void LIR_Assembler::reg2stack(LIR_Opr src, LIR_Opr dest, BasicType type, bool pop_fpu_stack) {
 947   assert(src->is_register(), "should not call otherwise");
 948   assert(dest->is_stack(), "should not call otherwise");
 949 
 950   if (src->is_single_cpu()) {
 951     Address dst = frame_map()->address_for_slot(dest->single_stack_ix());
 952     if (type == T_OBJECT || type == T_ARRAY) {
 953       __ verify_oop(src->as_register());
 954       __ movptr (dst, src->as_register());
 955     } else if (type == T_METADATA) {
 956       __ movptr (dst, src->as_register());
 957     } else {
 958       __ movl (dst, src->as_register());
 959     }
 960 
 961   } else if (src->is_double_cpu()) {
 962     Address dstLO = frame_map()->address_for_slot(dest->double_stack_ix(), lo_word_offset_in_bytes);
 963     Address dstHI = frame_map()->address_for_slot(dest->double_stack_ix(), hi_word_offset_in_bytes);
 964     __ movptr (dstLO, src->as_register_lo());
 965     NOT_LP64(__ movptr (dstHI, src->as_register_hi()));
 966 
 967   } else if (src->is_single_xmm()) {
 968     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 969     __ movflt(dst_addr, src->as_xmm_float_reg());
 970 
 971   } else if (src->is_double_xmm()) {
 972     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 973     __ movdbl(dst_addr, src->as_xmm_double_reg());
 974 
 975   } else if (src->is_single_fpu()) {
 976     assert(src->fpu_regnr() == 0, "argument must be on TOS");
 977     Address dst_addr = frame_map()->address_for_slot(dest->single_stack_ix());
 978     if (pop_fpu_stack)     __ fstp_s (dst_addr);
 979     else                   __ fst_s  (dst_addr);
 980 
 981   } else if (src->is_double_fpu()) {
 982     assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
 983     Address dst_addr = frame_map()->address_for_slot(dest->double_stack_ix());
 984     if (pop_fpu_stack)     __ fstp_d (dst_addr);
 985     else                   __ fst_d  (dst_addr);
 986 
 987   } else {
 988     ShouldNotReachHere();
 989   }
 990 }
 991 
 992 
 993 void LIR_Assembler::reg2mem(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, bool wide, bool /* unaligned */) {
 994   LIR_Address* to_addr = dest->as_address_ptr();
 995   PatchingStub* patch = NULL;
 996   Register compressed_src = rscratch1;
 997 
 998   if (type == T_ARRAY || type == T_OBJECT) {
 999     __ verify_oop(src->as_register());
1000 #ifdef _LP64
1001     if (UseCompressedOops && !wide) {
1002       __ movptr(compressed_src, src->as_register());
1003       __ encode_heap_oop(compressed_src);
1004       if (patch_code != lir_patch_none) {
1005         info->oop_map()->set_narrowoop(compressed_src->as_VMReg());
1006       }
1007     }
1008 #endif
1009   }
1010 
1011   if (patch_code != lir_patch_none) {
1012     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1013     Address toa = as_Address(to_addr);
1014     assert(toa.disp() != 0, "must have");
1015   }
1016 
1017   int null_check_here = code_offset();
1018   switch (type) {
1019     case T_FLOAT: {
1020       if (src->is_single_xmm()) {
1021         __ movflt(as_Address(to_addr), src->as_xmm_float_reg());
1022       } else {
1023         assert(src->is_single_fpu(), "must be");
1024         assert(src->fpu_regnr() == 0, "argument must be on TOS");
1025         if (pop_fpu_stack)      __ fstp_s(as_Address(to_addr));
1026         else                    __ fst_s (as_Address(to_addr));
1027       }
1028       break;
1029     }
1030 
1031     case T_DOUBLE: {
1032       if (src->is_double_xmm()) {
1033         __ movdbl(as_Address(to_addr), src->as_xmm_double_reg());
1034       } else {
1035         assert(src->is_double_fpu(), "must be");
1036         assert(src->fpu_regnrLo() == 0, "argument must be on TOS");
1037         if (pop_fpu_stack)      __ fstp_d(as_Address(to_addr));
1038         else                    __ fst_d (as_Address(to_addr));
1039       }
1040       break;
1041     }
1042 
1043     case T_ARRAY:   // fall through
1044     case T_OBJECT:  // fall through
1045       if (UseCompressedOops && !wide) {
1046         __ movl(as_Address(to_addr), compressed_src);
1047       } else {
1048         __ movptr(as_Address(to_addr), src->as_register());
1049       }
1050       break;
1051     case T_METADATA:
1052       // We get here to store a method pointer to the stack to pass to
1053       // a dtrace runtime call. This can't work on 64 bit with
1054       // compressed klass ptrs: T_METADATA can be a compressed klass
1055       // ptr or a 64 bit method pointer.
1056       LP64_ONLY(ShouldNotReachHere());
1057       __ movptr(as_Address(to_addr), src->as_register());
1058       break;
1059     case T_ADDRESS:
1060       __ movptr(as_Address(to_addr), src->as_register());
1061       break;
1062     case T_INT:
1063       __ movl(as_Address(to_addr), src->as_register());
1064       break;
1065 
1066     case T_LONG: {
1067       Register from_lo = src->as_register_lo();
1068       Register from_hi = src->as_register_hi();
1069 #ifdef _LP64
1070       __ movptr(as_Address_lo(to_addr), from_lo);
1071 #else
1072       Register base = to_addr->base()->as_register();
1073       Register index = noreg;
1074       if (to_addr->index()->is_register()) {
1075         index = to_addr->index()->as_register();
1076       }
1077       if (base == from_lo || index == from_lo) {
1078         assert(base != from_hi, "can't be");
1079         assert(index == noreg || (index != base && index != from_hi), "can't handle this");
1080         __ movl(as_Address_hi(to_addr), from_hi);
1081         if (patch != NULL) {
1082           patching_epilog(patch, lir_patch_high, base, info);
1083           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1084           patch_code = lir_patch_low;
1085         }
1086         __ movl(as_Address_lo(to_addr), from_lo);
1087       } else {
1088         assert(index == noreg || (index != base && index != from_lo), "can't handle this");
1089         __ movl(as_Address_lo(to_addr), from_lo);
1090         if (patch != NULL) {
1091           patching_epilog(patch, lir_patch_low, base, info);
1092           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1093           patch_code = lir_patch_high;
1094         }
1095         __ movl(as_Address_hi(to_addr), from_hi);
1096       }
1097 #endif // _LP64
1098       break;
1099     }
1100 
1101     case T_BYTE:    // fall through
1102     case T_BOOLEAN: {
1103       Register src_reg = src->as_register();
1104       Address dst_addr = as_Address(to_addr);
1105       assert(VM_Version::is_P6() || src_reg->has_byte_register(), "must use byte registers if not P6");
1106       __ movb(dst_addr, src_reg);
1107       break;
1108     }
1109 
1110     case T_CHAR:    // fall through
1111     case T_SHORT:
1112       __ movw(as_Address(to_addr), src->as_register());
1113       break;
1114 
1115     default:
1116       ShouldNotReachHere();
1117   }
1118   if (info != NULL) {
1119     add_debug_info_for_null_check(null_check_here, info);
1120   }
1121 
1122   if (patch_code != lir_patch_none) {
1123     patching_epilog(patch, patch_code, to_addr->base()->as_register(), info);
1124   }
1125 }
1126 
1127 
1128 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) {
1129   assert(src->is_stack(), "should not call otherwise");
1130   assert(dest->is_register(), "should not call otherwise");
1131 
1132   if (dest->is_single_cpu()) {
1133     if (type == T_ARRAY || type == T_OBJECT) {
1134       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1135       __ verify_oop(dest->as_register());
1136     } else if (type == T_METADATA) {
1137       __ movptr(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1138     } else {
1139       __ movl(dest->as_register(), frame_map()->address_for_slot(src->single_stack_ix()));
1140     }
1141 
1142   } else if (dest->is_double_cpu()) {
1143     Address src_addr_LO = frame_map()->address_for_slot(src->double_stack_ix(), lo_word_offset_in_bytes);
1144     Address src_addr_HI = frame_map()->address_for_slot(src->double_stack_ix(), hi_word_offset_in_bytes);
1145     __ movptr(dest->as_register_lo(), src_addr_LO);
1146     NOT_LP64(__ movptr(dest->as_register_hi(), src_addr_HI));
1147 
1148   } else if (dest->is_single_xmm()) {
1149     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1150     __ movflt(dest->as_xmm_float_reg(), src_addr);
1151 
1152   } else if (dest->is_double_xmm()) {
1153     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1154     __ movdbl(dest->as_xmm_double_reg(), src_addr);
1155 
1156   } else if (dest->is_single_fpu()) {
1157     assert(dest->fpu_regnr() == 0, "dest must be TOS");
1158     Address src_addr = frame_map()->address_for_slot(src->single_stack_ix());
1159     __ fld_s(src_addr);
1160 
1161   } else if (dest->is_double_fpu()) {
1162     assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1163     Address src_addr = frame_map()->address_for_slot(src->double_stack_ix());
1164     __ fld_d(src_addr);
1165 
1166   } else {
1167     ShouldNotReachHere();
1168   }
1169 }
1170 
1171 
1172 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) {
1173   if (src->is_single_stack()) {
1174     if (type == T_OBJECT || type == T_ARRAY) {
1175       __ pushptr(frame_map()->address_for_slot(src ->single_stack_ix()));
1176       __ popptr (frame_map()->address_for_slot(dest->single_stack_ix()));
1177     } else {
1178 #ifndef _LP64
1179       __ pushl(frame_map()->address_for_slot(src ->single_stack_ix()));
1180       __ popl (frame_map()->address_for_slot(dest->single_stack_ix()));
1181 #else
1182       //no pushl on 64bits
1183       __ movl(rscratch1, frame_map()->address_for_slot(src ->single_stack_ix()));
1184       __ movl(frame_map()->address_for_slot(dest->single_stack_ix()), rscratch1);
1185 #endif
1186     }
1187 
1188   } else if (src->is_double_stack()) {
1189 #ifdef _LP64
1190     __ pushptr(frame_map()->address_for_slot(src ->double_stack_ix()));
1191     __ popptr (frame_map()->address_for_slot(dest->double_stack_ix()));
1192 #else
1193     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 0));
1194     // push and pop the part at src + wordSize, adding wordSize for the previous push
1195     __ pushl(frame_map()->address_for_slot(src ->double_stack_ix(), 2 * wordSize));
1196     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 2 * wordSize));
1197     __ popl (frame_map()->address_for_slot(dest->double_stack_ix(), 0));
1198 #endif // _LP64
1199 
1200   } else {
1201     ShouldNotReachHere();
1202   }
1203 }
1204 
1205 
1206 void LIR_Assembler::mem2reg(LIR_Opr src, LIR_Opr dest, BasicType type, LIR_PatchCode patch_code, CodeEmitInfo* info, bool wide, bool /* unaligned */) {
1207   assert(src->is_address(), "should not call otherwise");
1208   assert(dest->is_register(), "should not call otherwise");
1209 
1210   LIR_Address* addr = src->as_address_ptr();
1211   Address from_addr = as_Address(addr);
1212 
1213   if (addr->base()->type() == T_OBJECT) {
1214     __ verify_oop(addr->base()->as_pointer_register());
1215   }
1216 
1217   switch (type) {
1218     case T_BOOLEAN: // fall through
1219     case T_BYTE:    // fall through
1220     case T_CHAR:    // fall through
1221     case T_SHORT:
1222       if (!VM_Version::is_P6() && !from_addr.uses(dest->as_register())) {
1223         // on pre P6 processors we may get partial register stalls
1224         // so blow away the value of to_rinfo before loading a
1225         // partial word into it.  Do it here so that it precedes
1226         // the potential patch point below.
1227         __ xorptr(dest->as_register(), dest->as_register());
1228       }
1229       break;
1230    default:
1231      break;
1232   }
1233 
1234   PatchingStub* patch = NULL;
1235   if (patch_code != lir_patch_none) {
1236     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1237     assert(from_addr.disp() != 0, "must have");
1238   }
1239   if (info != NULL) {
1240     add_debug_info_for_null_check_here(info);
1241   }
1242 
1243   switch (type) {
1244     case T_FLOAT: {
1245       if (dest->is_single_xmm()) {
1246         __ movflt(dest->as_xmm_float_reg(), from_addr);
1247       } else {
1248         assert(dest->is_single_fpu(), "must be");
1249         assert(dest->fpu_regnr() == 0, "dest must be TOS");
1250         __ fld_s(from_addr);
1251       }
1252       break;
1253     }
1254 
1255     case T_DOUBLE: {
1256       if (dest->is_double_xmm()) {
1257         __ movdbl(dest->as_xmm_double_reg(), from_addr);
1258       } else {
1259         assert(dest->is_double_fpu(), "must be");
1260         assert(dest->fpu_regnrLo() == 0, "dest must be TOS");
1261         __ fld_d(from_addr);
1262       }
1263       break;
1264     }
1265 
1266     case T_OBJECT:  // fall through
1267     case T_ARRAY:   // fall through
1268       if (UseCompressedOops && !wide) {
1269         __ movl(dest->as_register(), from_addr);
1270       } else {
1271         __ movptr(dest->as_register(), from_addr);
1272       }
1273       break;
1274 
1275     case T_ADDRESS:
1276       if (UseCompressedClassPointers && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1277         __ movl(dest->as_register(), from_addr);
1278       } else {
1279         __ movptr(dest->as_register(), from_addr);
1280       }
1281       break;
1282     case T_INT:
1283       __ movl(dest->as_register(), from_addr);
1284       break;
1285 
1286     case T_LONG: {
1287       Register to_lo = dest->as_register_lo();
1288       Register to_hi = dest->as_register_hi();
1289 #ifdef _LP64
1290       __ movptr(to_lo, as_Address_lo(addr));
1291 #else
1292       Register base = addr->base()->as_register();
1293       Register index = noreg;
1294       if (addr->index()->is_register()) {
1295         index = addr->index()->as_register();
1296       }
1297       if ((base == to_lo && index == to_hi) ||
1298           (base == to_hi && index == to_lo)) {
1299         // addresses with 2 registers are only formed as a result of
1300         // array access so this code will never have to deal with
1301         // patches or null checks.
1302         assert(info == NULL && patch == NULL, "must be");
1303         __ lea(to_hi, as_Address(addr));
1304         __ movl(to_lo, Address(to_hi, 0));
1305         __ movl(to_hi, Address(to_hi, BytesPerWord));
1306       } else if (base == to_lo || index == to_lo) {
1307         assert(base != to_hi, "can't be");
1308         assert(index == noreg || (index != base && index != to_hi), "can't handle this");
1309         __ movl(to_hi, as_Address_hi(addr));
1310         if (patch != NULL) {
1311           patching_epilog(patch, lir_patch_high, base, info);
1312           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1313           patch_code = lir_patch_low;
1314         }
1315         __ movl(to_lo, as_Address_lo(addr));
1316       } else {
1317         assert(index == noreg || (index != base && index != to_lo), "can't handle this");
1318         __ movl(to_lo, as_Address_lo(addr));
1319         if (patch != NULL) {
1320           patching_epilog(patch, lir_patch_low, base, info);
1321           patch = new PatchingStub(_masm, PatchingStub::access_field_id);
1322           patch_code = lir_patch_high;
1323         }
1324         __ movl(to_hi, as_Address_hi(addr));
1325       }
1326 #endif // _LP64
1327       break;
1328     }
1329 
1330     case T_BOOLEAN: // fall through
1331     case T_BYTE: {
1332       Register dest_reg = dest->as_register();
1333       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1334       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1335         __ movsbl(dest_reg, from_addr);
1336       } else {
1337         __ movb(dest_reg, from_addr);
1338         __ shll(dest_reg, 24);
1339         __ sarl(dest_reg, 24);
1340       }
1341       break;
1342     }
1343 
1344     case T_CHAR: {
1345       Register dest_reg = dest->as_register();
1346       assert(VM_Version::is_P6() || dest_reg->has_byte_register(), "must use byte registers if not P6");
1347       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1348         __ movzwl(dest_reg, from_addr);
1349       } else {
1350         __ movw(dest_reg, from_addr);
1351       }
1352       break;
1353     }
1354 
1355     case T_SHORT: {
1356       Register dest_reg = dest->as_register();
1357       if (VM_Version::is_P6() || from_addr.uses(dest_reg)) {
1358         __ movswl(dest_reg, from_addr);
1359       } else {
1360         __ movw(dest_reg, from_addr);
1361         __ shll(dest_reg, 16);
1362         __ sarl(dest_reg, 16);
1363       }
1364       break;
1365     }
1366 
1367     default:
1368       ShouldNotReachHere();
1369   }
1370 
1371   if (patch != NULL) {
1372     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
1373   }
1374 
1375   if (type == T_ARRAY || type == T_OBJECT) {
1376 #ifdef _LP64
1377     if (UseCompressedOops && !wide) {
1378       __ decode_heap_oop(dest->as_register());
1379     }
1380 #endif
1381 
1382     // Load barrier has not yet been applied, so ZGC can't verify the oop here
1383     if (!UseZGC) {
1384       __ verify_oop(dest->as_register());
1385     }
1386   } else if (type == T_ADDRESS && addr->disp() == oopDesc::klass_offset_in_bytes()) {
1387 #ifdef _LP64
1388     if (UseCompressedClassPointers) {
1389       __ decode_klass_not_null(dest->as_register());
1390     }
1391 #endif
1392   }
1393 }
1394 
1395 
1396 NEEDS_CLEANUP; // This could be static?
1397 Address::ScaleFactor LIR_Assembler::array_element_size(BasicType type) const {
1398   int elem_size = type2aelembytes(type);
1399   switch (elem_size) {
1400     case 1: return Address::times_1;
1401     case 2: return Address::times_2;
1402     case 4: return Address::times_4;
1403     case 8: return Address::times_8;
1404   }
1405   ShouldNotReachHere();
1406   return Address::no_scale;
1407 }
1408 
1409 
1410 void LIR_Assembler::emit_op3(LIR_Op3* op) {
1411   switch (op->code()) {
1412     case lir_idiv:
1413     case lir_irem:
1414       arithmetic_idiv(op->code(),
1415                       op->in_opr1(),
1416                       op->in_opr2(),
1417                       op->in_opr3(),
1418                       op->result_opr(),
1419                       op->info());
1420       break;
1421     case lir_fmad:
1422       __ fmad(op->result_opr()->as_xmm_double_reg(),
1423               op->in_opr1()->as_xmm_double_reg(),
1424               op->in_opr2()->as_xmm_double_reg(),
1425               op->in_opr3()->as_xmm_double_reg());
1426       break;
1427     case lir_fmaf:
1428       __ fmaf(op->result_opr()->as_xmm_float_reg(),
1429               op->in_opr1()->as_xmm_float_reg(),
1430               op->in_opr2()->as_xmm_float_reg(),
1431               op->in_opr3()->as_xmm_float_reg());
1432       break;
1433     default:      ShouldNotReachHere(); break;
1434   }
1435 }
1436 
1437 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) {
1438 #ifdef ASSERT
1439   assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label");
1440   if (op->block() != NULL)  _branch_target_blocks.append(op->block());
1441   if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock());
1442 #endif
1443 
1444   if (op->cond() == lir_cond_always) {
1445     if (op->info() != NULL) add_debug_info_for_branch(op->info());
1446     __ jmp (*(op->label()));
1447   } else {
1448     Assembler::Condition acond = Assembler::zero;
1449     if (op->code() == lir_cond_float_branch) {
1450       assert(op->ublock() != NULL, "must have unordered successor");
1451       __ jcc(Assembler::parity, *(op->ublock()->label()));
1452       switch(op->cond()) {
1453         case lir_cond_equal:        acond = Assembler::equal;      break;
1454         case lir_cond_notEqual:     acond = Assembler::notEqual;   break;
1455         case lir_cond_less:         acond = Assembler::below;      break;
1456         case lir_cond_lessEqual:    acond = Assembler::belowEqual; break;
1457         case lir_cond_greaterEqual: acond = Assembler::aboveEqual; break;
1458         case lir_cond_greater:      acond = Assembler::above;      break;
1459         default:                         ShouldNotReachHere();
1460       }
1461     } else {
1462       switch (op->cond()) {
1463         case lir_cond_equal:        acond = Assembler::equal;       break;
1464         case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
1465         case lir_cond_less:         acond = Assembler::less;        break;
1466         case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
1467         case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
1468         case lir_cond_greater:      acond = Assembler::greater;     break;
1469         case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
1470         case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
1471         default:                         ShouldNotReachHere();
1472       }
1473     }
1474     __ jcc(acond,*(op->label()));
1475   }
1476 }
1477 
1478 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) {
1479   LIR_Opr src  = op->in_opr();
1480   LIR_Opr dest = op->result_opr();
1481 
1482   switch (op->bytecode()) {
1483     case Bytecodes::_i2l:
1484 #ifdef _LP64
1485       __ movl2ptr(dest->as_register_lo(), src->as_register());
1486 #else
1487       move_regs(src->as_register(), dest->as_register_lo());
1488       move_regs(src->as_register(), dest->as_register_hi());
1489       __ sarl(dest->as_register_hi(), 31);
1490 #endif // LP64
1491       break;
1492 
1493     case Bytecodes::_l2i:
1494 #ifdef _LP64
1495       __ movl(dest->as_register(), src->as_register_lo());
1496 #else
1497       move_regs(src->as_register_lo(), dest->as_register());
1498 #endif
1499       break;
1500 
1501     case Bytecodes::_i2b:
1502       move_regs(src->as_register(), dest->as_register());
1503       __ sign_extend_byte(dest->as_register());
1504       break;
1505 
1506     case Bytecodes::_i2c:
1507       move_regs(src->as_register(), dest->as_register());
1508       __ andl(dest->as_register(), 0xFFFF);
1509       break;
1510 
1511     case Bytecodes::_i2s:
1512       move_regs(src->as_register(), dest->as_register());
1513       __ sign_extend_short(dest->as_register());
1514       break;
1515 
1516 
1517     case Bytecodes::_f2d:
1518     case Bytecodes::_d2f:
1519       if (dest->is_single_xmm()) {
1520         __ cvtsd2ss(dest->as_xmm_float_reg(), src->as_xmm_double_reg());
1521       } else if (dest->is_double_xmm()) {
1522         __ cvtss2sd(dest->as_xmm_double_reg(), src->as_xmm_float_reg());
1523       } else {
1524         assert(src->fpu() == dest->fpu(), "register must be equal");
1525         // do nothing (float result is rounded later through spilling)
1526       }
1527       break;
1528 
1529     case Bytecodes::_i2f:
1530     case Bytecodes::_i2d:
1531       if (dest->is_single_xmm()) {
1532         __ cvtsi2ssl(dest->as_xmm_float_reg(), src->as_register());
1533       } else if (dest->is_double_xmm()) {
1534         __ cvtsi2sdl(dest->as_xmm_double_reg(), src->as_register());
1535       } else {
1536         assert(dest->fpu() == 0, "result must be on TOS");
1537         __ movl(Address(rsp, 0), src->as_register());
1538         __ fild_s(Address(rsp, 0));
1539       }
1540       break;
1541 
1542     case Bytecodes::_f2i:
1543     case Bytecodes::_d2i:
1544       if (src->is_single_xmm()) {
1545         __ cvttss2sil(dest->as_register(), src->as_xmm_float_reg());
1546       } else if (src->is_double_xmm()) {
1547         __ cvttsd2sil(dest->as_register(), src->as_xmm_double_reg());
1548       } else {
1549         assert(src->fpu() == 0, "input must be on TOS");
1550         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_trunc()));
1551         __ fist_s(Address(rsp, 0));
1552         __ movl(dest->as_register(), Address(rsp, 0));
1553         __ fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_std()));
1554       }
1555 
1556       // IA32 conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
1557       assert(op->stub() != NULL, "stub required");
1558       __ cmpl(dest->as_register(), 0x80000000);
1559       __ jcc(Assembler::equal, *op->stub()->entry());
1560       __ bind(*op->stub()->continuation());
1561       break;
1562 
1563     case Bytecodes::_l2f:
1564     case Bytecodes::_l2d:
1565       assert(!dest->is_xmm_register(), "result in xmm register not supported (no SSE instruction present)");
1566       assert(dest->fpu() == 0, "result must be on TOS");
1567 
1568       __ movptr(Address(rsp, 0),            src->as_register_lo());
1569       NOT_LP64(__ movl(Address(rsp, BytesPerWord), src->as_register_hi()));
1570       __ fild_d(Address(rsp, 0));
1571       // float result is rounded later through spilling
1572       break;
1573 
1574     case Bytecodes::_f2l:
1575     case Bytecodes::_d2l:
1576       assert(!src->is_xmm_register(), "input in xmm register not supported (no SSE instruction present)");
1577       assert(src->fpu() == 0, "input must be on TOS");
1578       assert(dest == FrameMap::long0_opr, "runtime stub places result in these registers");
1579 
1580       // instruction sequence too long to inline it here
1581       {
1582         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::fpu2long_stub_id)));
1583       }
1584       break;
1585 
1586     default: ShouldNotReachHere();
1587   }
1588 }
1589 
1590 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) {
1591   if (op->init_check()) {
1592     add_debug_info_for_null_check_here(op->stub()->info());
1593     __ cmpb(Address(op->klass()->as_register(),
1594                     InstanceKlass::init_state_offset()),
1595                     InstanceKlass::fully_initialized);
1596     __ jcc(Assembler::notEqual, *op->stub()->entry());
1597   }
1598   __ allocate_object(op->obj()->as_register(),
1599                      op->tmp1()->as_register(),
1600                      op->tmp2()->as_register(),
1601                      op->header_size(),
1602                      op->object_size(),
1603                      op->klass()->as_register(),
1604                      *op->stub()->entry());
1605   __ bind(*op->stub()->continuation());
1606 }
1607 
1608 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) {
1609   Register len =  op->len()->as_register();
1610   LP64_ONLY( __ movslq(len, len); )
1611 
1612   if (UseSlowPath ||
1613       (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) ||
1614       (!UseFastNewTypeArray   && (op->type() != T_OBJECT && op->type() != T_ARRAY))) {
1615     __ jmp(*op->stub()->entry());
1616   } else {
1617     Register tmp1 = op->tmp1()->as_register();
1618     Register tmp2 = op->tmp2()->as_register();
1619     Register tmp3 = op->tmp3()->as_register();
1620     if (len == tmp1) {
1621       tmp1 = tmp3;
1622     } else if (len == tmp2) {
1623       tmp2 = tmp3;
1624     } else if (len == tmp3) {
1625       // everything is ok
1626     } else {
1627       __ mov(tmp3, len);
1628     }
1629     __ allocate_array(op->obj()->as_register(),
1630                       len,
1631                       tmp1,
1632                       tmp2,
1633                       arrayOopDesc::header_size(op->type()),
1634                       array_element_size(op->type()),
1635                       op->klass()->as_register(),
1636                       *op->stub()->entry());
1637   }
1638   __ bind(*op->stub()->continuation());
1639 }
1640 
1641 void LIR_Assembler::type_profile_helper(Register mdo,
1642                                         ciMethodData *md, ciProfileData *data,
1643                                         Register recv, Label* update_done) {
1644   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1645     Label next_test;
1646     // See if the receiver is receiver[n].
1647     __ cmpptr(recv, Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i))));
1648     __ jccb(Assembler::notEqual, next_test);
1649     Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)));
1650     __ addptr(data_addr, DataLayout::counter_increment);
1651     __ jmp(*update_done);
1652     __ bind(next_test);
1653   }
1654 
1655   // Didn't find receiver; find next empty slot and fill it in
1656   for (uint i = 0; i < ReceiverTypeData::row_limit(); i++) {
1657     Label next_test;
1658     Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)));
1659     __ cmpptr(recv_addr, (intptr_t)NULL_WORD);
1660     __ jccb(Assembler::notEqual, next_test);
1661     __ movptr(recv_addr, recv);
1662     __ movptr(Address(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i))), DataLayout::counter_increment);
1663     __ jmp(*update_done);
1664     __ bind(next_test);
1665   }
1666 }
1667 
1668 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) {
1669   // we always need a stub for the failure case.
1670   CodeStub* stub = op->stub();
1671   Register obj = op->object()->as_register();
1672   Register k_RInfo = op->tmp1()->as_register();
1673   Register klass_RInfo = op->tmp2()->as_register();
1674   Register dst = op->result_opr()->as_register();
1675   ciKlass* k = op->klass();
1676   Register Rtmp1 = noreg;
1677 
1678   // check if it needs to be profiled
1679   ciMethodData* md = NULL;
1680   ciProfileData* data = NULL;
1681 
1682   if (op->should_profile()) {
1683     ciMethod* method = op->profiled_method();
1684     assert(method != NULL, "Should have method");
1685     int bci = op->profiled_bci();
1686     md = method->method_data_or_null();
1687     assert(md != NULL, "Sanity");
1688     data = md->bci_to_data(bci);
1689     assert(data != NULL,                "need data for type check");
1690     assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1691   }
1692   Label profile_cast_success, profile_cast_failure;
1693   Label *success_target = op->should_profile() ? &profile_cast_success : success;
1694   Label *failure_target = op->should_profile() ? &profile_cast_failure : failure;
1695 
1696   if (obj == k_RInfo) {
1697     k_RInfo = dst;
1698   } else if (obj == klass_RInfo) {
1699     klass_RInfo = dst;
1700   }
1701   if (k->is_loaded() && !UseCompressedClassPointers) {
1702     select_different_registers(obj, dst, k_RInfo, klass_RInfo);
1703   } else {
1704     Rtmp1 = op->tmp3()->as_register();
1705     select_different_registers(obj, dst, k_RInfo, klass_RInfo, Rtmp1);
1706   }
1707 
1708   assert_different_registers(obj, k_RInfo, klass_RInfo);
1709 
1710   __ cmpptr(obj, (int32_t)NULL_WORD);
1711   if (op->should_profile()) {
1712     Label not_null;
1713     __ jccb(Assembler::notEqual, not_null);
1714     // Object is null; update MDO and exit
1715     Register mdo  = klass_RInfo;
1716     __ mov_metadata(mdo, md->constant_encoding());
1717     Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1718     int header_bits = BitData::null_seen_byte_constant();
1719     __ orb(data_addr, header_bits);
1720     __ jmp(*obj_is_null);
1721     __ bind(not_null);
1722   } else {
1723     __ jcc(Assembler::equal, *obj_is_null);
1724   }
1725 
1726   if (!k->is_loaded()) {
1727     klass2reg_with_patching(k_RInfo, op->info_for_patch());
1728   } else {
1729 #ifdef _LP64
1730     __ mov_metadata(k_RInfo, k->constant_encoding());
1731 #endif // _LP64
1732   }
1733   __ verify_oop(obj);
1734 
1735   if (op->fast_check()) {
1736     // get object class
1737     // not a safepoint as obj null check happens earlier
1738 #ifdef _LP64
1739     if (UseCompressedClassPointers) {
1740       __ load_klass(Rtmp1, obj);
1741       __ cmpptr(k_RInfo, Rtmp1);
1742     } else {
1743       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1744     }
1745 #else
1746     if (k->is_loaded()) {
1747       __ cmpklass(Address(obj, oopDesc::klass_offset_in_bytes()), k->constant_encoding());
1748     } else {
1749       __ cmpptr(k_RInfo, Address(obj, oopDesc::klass_offset_in_bytes()));
1750     }
1751 #endif
1752     __ jcc(Assembler::notEqual, *failure_target);
1753     // successful cast, fall through to profile or jump
1754   } else {
1755     // get object class
1756     // not a safepoint as obj null check happens earlier
1757     __ load_klass(klass_RInfo, obj);
1758     if (k->is_loaded()) {
1759       // See if we get an immediate positive hit
1760 #ifdef _LP64
1761       __ cmpptr(k_RInfo, Address(klass_RInfo, k->super_check_offset()));
1762 #else
1763       __ cmpklass(Address(klass_RInfo, k->super_check_offset()), k->constant_encoding());
1764 #endif // _LP64
1765       if ((juint)in_bytes(Klass::secondary_super_cache_offset()) != k->super_check_offset()) {
1766         __ jcc(Assembler::notEqual, *failure_target);
1767         // successful cast, fall through to profile or jump
1768       } else {
1769         // See if we get an immediate positive hit
1770         __ jcc(Assembler::equal, *success_target);
1771         // check for self
1772 #ifdef _LP64
1773         __ cmpptr(klass_RInfo, k_RInfo);
1774 #else
1775         __ cmpklass(klass_RInfo, k->constant_encoding());
1776 #endif // _LP64
1777         __ jcc(Assembler::equal, *success_target);
1778 
1779         __ push(klass_RInfo);
1780 #ifdef _LP64
1781         __ push(k_RInfo);
1782 #else
1783         __ pushklass(k->constant_encoding());
1784 #endif // _LP64
1785         __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1786         __ pop(klass_RInfo);
1787         __ pop(klass_RInfo);
1788         // result is a boolean
1789         __ cmpl(klass_RInfo, 0);
1790         __ jcc(Assembler::equal, *failure_target);
1791         // successful cast, fall through to profile or jump
1792       }
1793     } else {
1794       // perform the fast part of the checking logic
1795       __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1796       // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1797       __ push(klass_RInfo);
1798       __ push(k_RInfo);
1799       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1800       __ pop(klass_RInfo);
1801       __ pop(k_RInfo);
1802       // result is a boolean
1803       __ cmpl(k_RInfo, 0);
1804       __ jcc(Assembler::equal, *failure_target);
1805       // successful cast, fall through to profile or jump
1806     }
1807   }
1808   if (op->should_profile()) {
1809     Register mdo  = klass_RInfo, recv = k_RInfo;
1810     __ bind(profile_cast_success);
1811     __ mov_metadata(mdo, md->constant_encoding());
1812     __ load_klass(recv, obj);
1813     type_profile_helper(mdo, md, data, recv, success);
1814     __ jmp(*success);
1815 
1816     __ bind(profile_cast_failure);
1817     __ mov_metadata(mdo, md->constant_encoding());
1818     Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1819     __ subptr(counter_addr, DataLayout::counter_increment);
1820     __ jmp(*failure);
1821   }
1822   __ jmp(*success);
1823 }
1824 
1825 
1826 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) {
1827   LIR_Code code = op->code();
1828   if (code == lir_store_check) {
1829     Register value = op->object()->as_register();
1830     Register array = op->array()->as_register();
1831     Register k_RInfo = op->tmp1()->as_register();
1832     Register klass_RInfo = op->tmp2()->as_register();
1833     Register Rtmp1 = op->tmp3()->as_register();
1834 
1835     CodeStub* stub = op->stub();
1836 
1837     // check if it needs to be profiled
1838     ciMethodData* md = NULL;
1839     ciProfileData* data = NULL;
1840 
1841     if (op->should_profile()) {
1842       ciMethod* method = op->profiled_method();
1843       assert(method != NULL, "Should have method");
1844       int bci = op->profiled_bci();
1845       md = method->method_data_or_null();
1846       assert(md != NULL, "Sanity");
1847       data = md->bci_to_data(bci);
1848       assert(data != NULL,                "need data for type check");
1849       assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check");
1850     }
1851     Label profile_cast_success, profile_cast_failure, done;
1852     Label *success_target = op->should_profile() ? &profile_cast_success : &done;
1853     Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry();
1854 
1855     __ cmpptr(value, (int32_t)NULL_WORD);
1856     if (op->should_profile()) {
1857       Label not_null;
1858       __ jccb(Assembler::notEqual, not_null);
1859       // Object is null; update MDO and exit
1860       Register mdo  = klass_RInfo;
1861       __ mov_metadata(mdo, md->constant_encoding());
1862       Address data_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()));
1863       int header_bits = BitData::null_seen_byte_constant();
1864       __ orb(data_addr, header_bits);
1865       __ jmp(done);
1866       __ bind(not_null);
1867     } else {
1868       __ jcc(Assembler::equal, done);
1869     }
1870 
1871     add_debug_info_for_null_check_here(op->info_for_exception());
1872     __ load_klass(k_RInfo, array);
1873     __ load_klass(klass_RInfo, value);
1874 
1875     // get instance klass (it's already uncompressed)
1876     __ movptr(k_RInfo, Address(k_RInfo, ObjArrayKlass::element_klass_offset()));
1877     // perform the fast part of the checking logic
1878     __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, success_target, failure_target, NULL);
1879     // call out-of-line instance of __ check_klass_subtype_slow_path(...):
1880     __ push(klass_RInfo);
1881     __ push(k_RInfo);
1882     __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
1883     __ pop(klass_RInfo);
1884     __ pop(k_RInfo);
1885     // result is a boolean
1886     __ cmpl(k_RInfo, 0);
1887     __ jcc(Assembler::equal, *failure_target);
1888     // fall through to the success case
1889 
1890     if (op->should_profile()) {
1891       Register mdo  = klass_RInfo, recv = k_RInfo;
1892       __ bind(profile_cast_success);
1893       __ mov_metadata(mdo, md->constant_encoding());
1894       __ load_klass(recv, value);
1895       type_profile_helper(mdo, md, data, recv, &done);
1896       __ jmpb(done);
1897 
1898       __ bind(profile_cast_failure);
1899       __ mov_metadata(mdo, md->constant_encoding());
1900       Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
1901       __ subptr(counter_addr, DataLayout::counter_increment);
1902       __ jmp(*stub->entry());
1903     }
1904 
1905     __ bind(done);
1906   } else
1907     if (code == lir_checkcast) {
1908       Register obj = op->object()->as_register();
1909       Register dst = op->result_opr()->as_register();
1910       Label success;
1911       emit_typecheck_helper(op, &success, op->stub()->entry(), &success);
1912       __ bind(success);
1913       if (dst != obj) {
1914         __ mov(dst, obj);
1915       }
1916     } else
1917       if (code == lir_instanceof) {
1918         Register obj = op->object()->as_register();
1919         Register dst = op->result_opr()->as_register();
1920         Label success, failure, done;
1921         emit_typecheck_helper(op, &success, &failure, &failure);
1922         __ bind(failure);
1923         __ xorptr(dst, dst);
1924         __ jmpb(done);
1925         __ bind(success);
1926         __ movptr(dst, 1);
1927         __ bind(done);
1928       } else {
1929         ShouldNotReachHere();
1930       }
1931 
1932 }
1933 
1934 
1935 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) {
1936   if (LP64_ONLY(false &&) op->code() == lir_cas_long && VM_Version::supports_cx8()) {
1937     assert(op->cmp_value()->as_register_lo() == rax, "wrong register");
1938     assert(op->cmp_value()->as_register_hi() == rdx, "wrong register");
1939     assert(op->new_value()->as_register_lo() == rbx, "wrong register");
1940     assert(op->new_value()->as_register_hi() == rcx, "wrong register");
1941     Register addr = op->addr()->as_register();
1942     __ lock();
1943     NOT_LP64(__ cmpxchg8(Address(addr, 0)));
1944 
1945   } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj ) {
1946     NOT_LP64(assert(op->addr()->is_single_cpu(), "must be single");)
1947     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1948     Register newval = op->new_value()->as_register();
1949     Register cmpval = op->cmp_value()->as_register();
1950     assert(cmpval == rax, "wrong register");
1951     assert(newval != NULL, "new val must be register");
1952     assert(cmpval != newval, "cmp and new values must be in different registers");
1953     assert(cmpval != addr, "cmp and addr must be in different registers");
1954     assert(newval != addr, "new value and addr must be in different registers");
1955 
1956     if ( op->code() == lir_cas_obj) {
1957 #ifdef _LP64
1958       if (UseCompressedOops) {
1959         __ encode_heap_oop(cmpval);
1960         __ mov(rscratch1, newval);
1961         __ encode_heap_oop(rscratch1);
1962         __ lock();
1963         // cmpval (rax) is implicitly used by this instruction
1964         __ cmpxchgl(rscratch1, Address(addr, 0));
1965       } else
1966 #endif
1967       {
1968         __ lock();
1969         __ cmpxchgptr(newval, Address(addr, 0));
1970       }
1971     } else {
1972       assert(op->code() == lir_cas_int, "lir_cas_int expected");
1973       __ lock();
1974       __ cmpxchgl(newval, Address(addr, 0));
1975     }
1976 #ifdef _LP64
1977   } else if (op->code() == lir_cas_long) {
1978     Register addr = (op->addr()->is_single_cpu() ? op->addr()->as_register() : op->addr()->as_register_lo());
1979     Register newval = op->new_value()->as_register_lo();
1980     Register cmpval = op->cmp_value()->as_register_lo();
1981     assert(cmpval == rax, "wrong register");
1982     assert(newval != NULL, "new val must be register");
1983     assert(cmpval != newval, "cmp and new values must be in different registers");
1984     assert(cmpval != addr, "cmp and addr must be in different registers");
1985     assert(newval != addr, "new value and addr must be in different registers");
1986     __ lock();
1987     __ cmpxchgq(newval, Address(addr, 0));
1988 #endif // _LP64
1989   } else {
1990     Unimplemented();
1991   }
1992 }
1993 
1994 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result, BasicType type) {
1995   Assembler::Condition acond, ncond;
1996   switch (condition) {
1997     case lir_cond_equal:        acond = Assembler::equal;        ncond = Assembler::notEqual;     break;
1998     case lir_cond_notEqual:     acond = Assembler::notEqual;     ncond = Assembler::equal;        break;
1999     case lir_cond_less:         acond = Assembler::less;         ncond = Assembler::greaterEqual; break;
2000     case lir_cond_lessEqual:    acond = Assembler::lessEqual;    ncond = Assembler::greater;      break;
2001     case lir_cond_greaterEqual: acond = Assembler::greaterEqual; ncond = Assembler::less;         break;
2002     case lir_cond_greater:      acond = Assembler::greater;      ncond = Assembler::lessEqual;    break;
2003     case lir_cond_belowEqual:   acond = Assembler::belowEqual;   ncond = Assembler::above;        break;
2004     case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;   ncond = Assembler::below;        break;
2005     default:                    acond = Assembler::equal;        ncond = Assembler::notEqual;
2006                                 ShouldNotReachHere();
2007   }
2008 
2009   if (opr1->is_cpu_register()) {
2010     reg2reg(opr1, result);
2011   } else if (opr1->is_stack()) {
2012     stack2reg(opr1, result, result->type());
2013   } else if (opr1->is_constant()) {
2014     const2reg(opr1, result, lir_patch_none, NULL);
2015   } else {
2016     ShouldNotReachHere();
2017   }
2018 
2019   if (VM_Version::supports_cmov() && !opr2->is_constant()) {
2020     // optimized version that does not require a branch
2021     if (opr2->is_single_cpu()) {
2022       assert(opr2->cpu_regnr() != result->cpu_regnr(), "opr2 already overwritten by previous move");
2023       __ cmov(ncond, result->as_register(), opr2->as_register());
2024     } else if (opr2->is_double_cpu()) {
2025       assert(opr2->cpu_regnrLo() != result->cpu_regnrLo() && opr2->cpu_regnrLo() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2026       assert(opr2->cpu_regnrHi() != result->cpu_regnrLo() && opr2->cpu_regnrHi() != result->cpu_regnrHi(), "opr2 already overwritten by previous move");
2027       __ cmovptr(ncond, result->as_register_lo(), opr2->as_register_lo());
2028       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), opr2->as_register_hi());)
2029     } else if (opr2->is_single_stack()) {
2030       __ cmovl(ncond, result->as_register(), frame_map()->address_for_slot(opr2->single_stack_ix()));
2031     } else if (opr2->is_double_stack()) {
2032       __ cmovptr(ncond, result->as_register_lo(), frame_map()->address_for_slot(opr2->double_stack_ix(), lo_word_offset_in_bytes));
2033       NOT_LP64(__ cmovptr(ncond, result->as_register_hi(), frame_map()->address_for_slot(opr2->double_stack_ix(), hi_word_offset_in_bytes));)
2034     } else {
2035       ShouldNotReachHere();
2036     }
2037 
2038   } else {
2039     Label skip;
2040     __ jcc (acond, skip);
2041     if (opr2->is_cpu_register()) {
2042       reg2reg(opr2, result);
2043     } else if (opr2->is_stack()) {
2044       stack2reg(opr2, result, result->type());
2045     } else if (opr2->is_constant()) {
2046       const2reg(opr2, result, lir_patch_none, NULL);
2047     } else {
2048       ShouldNotReachHere();
2049     }
2050     __ bind(skip);
2051   }
2052 }
2053 
2054 
2055 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) {
2056   assert(info == NULL, "should never be used, idiv/irem and ldiv/lrem not handled by this method");
2057 
2058   if (left->is_single_cpu()) {
2059     assert(left == dest, "left and dest must be equal");
2060     Register lreg = left->as_register();
2061 
2062     if (right->is_single_cpu()) {
2063       // cpu register - cpu register
2064       Register rreg = right->as_register();
2065       switch (code) {
2066         case lir_add: __ addl (lreg, rreg); break;
2067         case lir_sub: __ subl (lreg, rreg); break;
2068         case lir_mul: __ imull(lreg, rreg); break;
2069         default:      ShouldNotReachHere();
2070       }
2071 
2072     } else if (right->is_stack()) {
2073       // cpu register - stack
2074       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2075       switch (code) {
2076         case lir_add: __ addl(lreg, raddr); break;
2077         case lir_sub: __ subl(lreg, raddr); break;
2078         default:      ShouldNotReachHere();
2079       }
2080 
2081     } else if (right->is_constant()) {
2082       // cpu register - constant
2083       jint c = right->as_constant_ptr()->as_jint();
2084       switch (code) {
2085         case lir_add: {
2086           __ incrementl(lreg, c);
2087           break;
2088         }
2089         case lir_sub: {
2090           __ decrementl(lreg, c);
2091           break;
2092         }
2093         default: ShouldNotReachHere();
2094       }
2095 
2096     } else {
2097       ShouldNotReachHere();
2098     }
2099 
2100   } else if (left->is_double_cpu()) {
2101     assert(left == dest, "left and dest must be equal");
2102     Register lreg_lo = left->as_register_lo();
2103     Register lreg_hi = left->as_register_hi();
2104 
2105     if (right->is_double_cpu()) {
2106       // cpu register - cpu register
2107       Register rreg_lo = right->as_register_lo();
2108       Register rreg_hi = right->as_register_hi();
2109       NOT_LP64(assert_different_registers(lreg_lo, lreg_hi, rreg_lo, rreg_hi));
2110       LP64_ONLY(assert_different_registers(lreg_lo, rreg_lo));
2111       switch (code) {
2112         case lir_add:
2113           __ addptr(lreg_lo, rreg_lo);
2114           NOT_LP64(__ adcl(lreg_hi, rreg_hi));
2115           break;
2116         case lir_sub:
2117           __ subptr(lreg_lo, rreg_lo);
2118           NOT_LP64(__ sbbl(lreg_hi, rreg_hi));
2119           break;
2120         case lir_mul:
2121 #ifdef _LP64
2122           __ imulq(lreg_lo, rreg_lo);
2123 #else
2124           assert(lreg_lo == rax && lreg_hi == rdx, "must be");
2125           __ imull(lreg_hi, rreg_lo);
2126           __ imull(rreg_hi, lreg_lo);
2127           __ addl (rreg_hi, lreg_hi);
2128           __ mull (rreg_lo);
2129           __ addl (lreg_hi, rreg_hi);
2130 #endif // _LP64
2131           break;
2132         default:
2133           ShouldNotReachHere();
2134       }
2135 
2136     } else if (right->is_constant()) {
2137       // cpu register - constant
2138 #ifdef _LP64
2139       jlong c = right->as_constant_ptr()->as_jlong_bits();
2140       __ movptr(r10, (intptr_t) c);
2141       switch (code) {
2142         case lir_add:
2143           __ addptr(lreg_lo, r10);
2144           break;
2145         case lir_sub:
2146           __ subptr(lreg_lo, r10);
2147           break;
2148         default:
2149           ShouldNotReachHere();
2150       }
2151 #else
2152       jint c_lo = right->as_constant_ptr()->as_jint_lo();
2153       jint c_hi = right->as_constant_ptr()->as_jint_hi();
2154       switch (code) {
2155         case lir_add:
2156           __ addptr(lreg_lo, c_lo);
2157           __ adcl(lreg_hi, c_hi);
2158           break;
2159         case lir_sub:
2160           __ subptr(lreg_lo, c_lo);
2161           __ sbbl(lreg_hi, c_hi);
2162           break;
2163         default:
2164           ShouldNotReachHere();
2165       }
2166 #endif // _LP64
2167 
2168     } else {
2169       ShouldNotReachHere();
2170     }
2171 
2172   } else if (left->is_single_xmm()) {
2173     assert(left == dest, "left and dest must be equal");
2174     XMMRegister lreg = left->as_xmm_float_reg();
2175 
2176     if (right->is_single_xmm()) {
2177       XMMRegister rreg = right->as_xmm_float_reg();
2178       switch (code) {
2179         case lir_add: __ addss(lreg, rreg);  break;
2180         case lir_sub: __ subss(lreg, rreg);  break;
2181         case lir_mul_strictfp: // fall through
2182         case lir_mul: __ mulss(lreg, rreg);  break;
2183         case lir_div_strictfp: // fall through
2184         case lir_div: __ divss(lreg, rreg);  break;
2185         default: ShouldNotReachHere();
2186       }
2187     } else {
2188       Address raddr;
2189       if (right->is_single_stack()) {
2190         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2191       } else if (right->is_constant()) {
2192         // hack for now
2193         raddr = __ as_Address(InternalAddress(float_constant(right->as_jfloat())));
2194       } else {
2195         ShouldNotReachHere();
2196       }
2197       switch (code) {
2198         case lir_add: __ addss(lreg, raddr);  break;
2199         case lir_sub: __ subss(lreg, raddr);  break;
2200         case lir_mul_strictfp: // fall through
2201         case lir_mul: __ mulss(lreg, raddr);  break;
2202         case lir_div_strictfp: // fall through
2203         case lir_div: __ divss(lreg, raddr);  break;
2204         default: ShouldNotReachHere();
2205       }
2206     }
2207 
2208   } else if (left->is_double_xmm()) {
2209     assert(left == dest, "left and dest must be equal");
2210 
2211     XMMRegister lreg = left->as_xmm_double_reg();
2212     if (right->is_double_xmm()) {
2213       XMMRegister rreg = right->as_xmm_double_reg();
2214       switch (code) {
2215         case lir_add: __ addsd(lreg, rreg);  break;
2216         case lir_sub: __ subsd(lreg, rreg);  break;
2217         case lir_mul_strictfp: // fall through
2218         case lir_mul: __ mulsd(lreg, rreg);  break;
2219         case lir_div_strictfp: // fall through
2220         case lir_div: __ divsd(lreg, rreg);  break;
2221         default: ShouldNotReachHere();
2222       }
2223     } else {
2224       Address raddr;
2225       if (right->is_double_stack()) {
2226         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2227       } else if (right->is_constant()) {
2228         // hack for now
2229         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2230       } else {
2231         ShouldNotReachHere();
2232       }
2233       switch (code) {
2234         case lir_add: __ addsd(lreg, raddr);  break;
2235         case lir_sub: __ subsd(lreg, raddr);  break;
2236         case lir_mul_strictfp: // fall through
2237         case lir_mul: __ mulsd(lreg, raddr);  break;
2238         case lir_div_strictfp: // fall through
2239         case lir_div: __ divsd(lreg, raddr);  break;
2240         default: ShouldNotReachHere();
2241       }
2242     }
2243 
2244   } else if (left->is_single_fpu()) {
2245     assert(dest->is_single_fpu(),  "fpu stack allocation required");
2246 
2247     if (right->is_single_fpu()) {
2248       arith_fpu_implementation(code, left->fpu_regnr(), right->fpu_regnr(), dest->fpu_regnr(), pop_fpu_stack);
2249 
2250     } else {
2251       assert(left->fpu_regnr() == 0, "left must be on TOS");
2252       assert(dest->fpu_regnr() == 0, "dest must be on TOS");
2253 
2254       Address raddr;
2255       if (right->is_single_stack()) {
2256         raddr = frame_map()->address_for_slot(right->single_stack_ix());
2257       } else if (right->is_constant()) {
2258         address const_addr = float_constant(right->as_jfloat());
2259         assert(const_addr != NULL, "incorrect float/double constant maintainance");
2260         // hack for now
2261         raddr = __ as_Address(InternalAddress(const_addr));
2262       } else {
2263         ShouldNotReachHere();
2264       }
2265 
2266       switch (code) {
2267         case lir_add: __ fadd_s(raddr); break;
2268         case lir_sub: __ fsub_s(raddr); break;
2269         case lir_mul_strictfp: // fall through
2270         case lir_mul: __ fmul_s(raddr); break;
2271         case lir_div_strictfp: // fall through
2272         case lir_div: __ fdiv_s(raddr); break;
2273         default:      ShouldNotReachHere();
2274       }
2275     }
2276 
2277   } else if (left->is_double_fpu()) {
2278     assert(dest->is_double_fpu(),  "fpu stack allocation required");
2279 
2280     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2281       // Double values require special handling for strictfp mul/div on x86
2282       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias1()));
2283       __ fmulp(left->fpu_regnrLo() + 1);
2284     }
2285 
2286     if (right->is_double_fpu()) {
2287       arith_fpu_implementation(code, left->fpu_regnrLo(), right->fpu_regnrLo(), dest->fpu_regnrLo(), pop_fpu_stack);
2288 
2289     } else {
2290       assert(left->fpu_regnrLo() == 0, "left must be on TOS");
2291       assert(dest->fpu_regnrLo() == 0, "dest must be on TOS");
2292 
2293       Address raddr;
2294       if (right->is_double_stack()) {
2295         raddr = frame_map()->address_for_slot(right->double_stack_ix());
2296       } else if (right->is_constant()) {
2297         // hack for now
2298         raddr = __ as_Address(InternalAddress(double_constant(right->as_jdouble())));
2299       } else {
2300         ShouldNotReachHere();
2301       }
2302 
2303       switch (code) {
2304         case lir_add: __ fadd_d(raddr); break;
2305         case lir_sub: __ fsub_d(raddr); break;
2306         case lir_mul_strictfp: // fall through
2307         case lir_mul: __ fmul_d(raddr); break;
2308         case lir_div_strictfp: // fall through
2309         case lir_div: __ fdiv_d(raddr); break;
2310         default: ShouldNotReachHere();
2311       }
2312     }
2313 
2314     if (code == lir_mul_strictfp || code == lir_div_strictfp) {
2315       // Double values require special handling for strictfp mul/div on x86
2316       __ fld_x(ExternalAddress(StubRoutines::addr_fpu_subnormal_bias2()));
2317       __ fmulp(dest->fpu_regnrLo() + 1);
2318     }
2319 
2320   } else if (left->is_single_stack() || left->is_address()) {
2321     assert(left == dest, "left and dest must be equal");
2322 
2323     Address laddr;
2324     if (left->is_single_stack()) {
2325       laddr = frame_map()->address_for_slot(left->single_stack_ix());
2326     } else if (left->is_address()) {
2327       laddr = as_Address(left->as_address_ptr());
2328     } else {
2329       ShouldNotReachHere();
2330     }
2331 
2332     if (right->is_single_cpu()) {
2333       Register rreg = right->as_register();
2334       switch (code) {
2335         case lir_add: __ addl(laddr, rreg); break;
2336         case lir_sub: __ subl(laddr, rreg); break;
2337         default:      ShouldNotReachHere();
2338       }
2339     } else if (right->is_constant()) {
2340       jint c = right->as_constant_ptr()->as_jint();
2341       switch (code) {
2342         case lir_add: {
2343           __ incrementl(laddr, c);
2344           break;
2345         }
2346         case lir_sub: {
2347           __ decrementl(laddr, c);
2348           break;
2349         }
2350         default: ShouldNotReachHere();
2351       }
2352     } else {
2353       ShouldNotReachHere();
2354     }
2355 
2356   } else {
2357     ShouldNotReachHere();
2358   }
2359 }
2360 
2361 void LIR_Assembler::arith_fpu_implementation(LIR_Code code, int left_index, int right_index, int dest_index, bool pop_fpu_stack) {
2362   assert(pop_fpu_stack  || (left_index     == dest_index || right_index     == dest_index), "invalid LIR");
2363   assert(!pop_fpu_stack || (left_index - 1 == dest_index || right_index - 1 == dest_index), "invalid LIR");
2364   assert(left_index == 0 || right_index == 0, "either must be on top of stack");
2365 
2366   bool left_is_tos = (left_index == 0);
2367   bool dest_is_tos = (dest_index == 0);
2368   int non_tos_index = (left_is_tos ? right_index : left_index);
2369 
2370   switch (code) {
2371     case lir_add:
2372       if (pop_fpu_stack)       __ faddp(non_tos_index);
2373       else if (dest_is_tos)    __ fadd (non_tos_index);
2374       else                     __ fadda(non_tos_index);
2375       break;
2376 
2377     case lir_sub:
2378       if (left_is_tos) {
2379         if (pop_fpu_stack)     __ fsubrp(non_tos_index);
2380         else if (dest_is_tos)  __ fsub  (non_tos_index);
2381         else                   __ fsubra(non_tos_index);
2382       } else {
2383         if (pop_fpu_stack)     __ fsubp (non_tos_index);
2384         else if (dest_is_tos)  __ fsubr (non_tos_index);
2385         else                   __ fsuba (non_tos_index);
2386       }
2387       break;
2388 
2389     case lir_mul_strictfp: // fall through
2390     case lir_mul:
2391       if (pop_fpu_stack)       __ fmulp(non_tos_index);
2392       else if (dest_is_tos)    __ fmul (non_tos_index);
2393       else                     __ fmula(non_tos_index);
2394       break;
2395 
2396     case lir_div_strictfp: // fall through
2397     case lir_div:
2398       if (left_is_tos) {
2399         if (pop_fpu_stack)     __ fdivrp(non_tos_index);
2400         else if (dest_is_tos)  __ fdiv  (non_tos_index);
2401         else                   __ fdivra(non_tos_index);
2402       } else {
2403         if (pop_fpu_stack)     __ fdivp (non_tos_index);
2404         else if (dest_is_tos)  __ fdivr (non_tos_index);
2405         else                   __ fdiva (non_tos_index);
2406       }
2407       break;
2408 
2409     case lir_rem:
2410       assert(left_is_tos && dest_is_tos && right_index == 1, "must be guaranteed by FPU stack allocation");
2411       __ fremr(noreg);
2412       break;
2413 
2414     default:
2415       ShouldNotReachHere();
2416   }
2417 }
2418 
2419 
2420 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr tmp, LIR_Opr dest, LIR_Op* op) {
2421   if (value->is_double_xmm()) {
2422     switch(code) {
2423       case lir_abs :
2424         {
2425 #ifdef _LP64
2426           if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
2427             assert(tmp->is_valid(), "need temporary");
2428             __ vpandn(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), value->as_xmm_double_reg(), 2);
2429           } else
2430 #endif
2431           {
2432             if (dest->as_xmm_double_reg() != value->as_xmm_double_reg()) {
2433               __ movdbl(dest->as_xmm_double_reg(), value->as_xmm_double_reg());
2434             }
2435             assert(!tmp->is_valid(), "do not need temporary");
2436             __ andpd(dest->as_xmm_double_reg(),
2437                      ExternalAddress((address)double_signmask_pool));
2438           }
2439         }
2440         break;
2441 
2442       case lir_sqrt: __ sqrtsd(dest->as_xmm_double_reg(), value->as_xmm_double_reg()); break;
2443       // all other intrinsics are not available in the SSE instruction set, so FPU is used
2444       default      : ShouldNotReachHere();
2445     }
2446 
2447   } else if (value->is_double_fpu()) {
2448     assert(value->fpu_regnrLo() == 0 && dest->fpu_regnrLo() == 0, "both must be on TOS");
2449     switch(code) {
2450       case lir_abs   : __ fabs() ; break;
2451       case lir_sqrt  : __ fsqrt(); break;
2452       default      : ShouldNotReachHere();
2453     }
2454   } else {
2455     Unimplemented();
2456   }
2457 }
2458 
2459 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst) {
2460   // assert(left->destroys_register(), "check");
2461   if (left->is_single_cpu()) {
2462     Register reg = left->as_register();
2463     if (right->is_constant()) {
2464       int val = right->as_constant_ptr()->as_jint();
2465       switch (code) {
2466         case lir_logic_and: __ andl (reg, val); break;
2467         case lir_logic_or:  __ orl  (reg, val); break;
2468         case lir_logic_xor: __ xorl (reg, val); break;
2469         default: ShouldNotReachHere();
2470       }
2471     } else if (right->is_stack()) {
2472       // added support for stack operands
2473       Address raddr = frame_map()->address_for_slot(right->single_stack_ix());
2474       switch (code) {
2475         case lir_logic_and: __ andl (reg, raddr); break;
2476         case lir_logic_or:  __ orl  (reg, raddr); break;
2477         case lir_logic_xor: __ xorl (reg, raddr); break;
2478         default: ShouldNotReachHere();
2479       }
2480     } else {
2481       Register rright = right->as_register();
2482       switch (code) {
2483         case lir_logic_and: __ andptr (reg, rright); break;
2484         case lir_logic_or : __ orptr  (reg, rright); break;
2485         case lir_logic_xor: __ xorptr (reg, rright); break;
2486         default: ShouldNotReachHere();
2487       }
2488     }
2489     move_regs(reg, dst->as_register());
2490   } else {
2491     Register l_lo = left->as_register_lo();
2492     Register l_hi = left->as_register_hi();
2493     if (right->is_constant()) {
2494 #ifdef _LP64
2495       __ mov64(rscratch1, right->as_constant_ptr()->as_jlong());
2496       switch (code) {
2497         case lir_logic_and:
2498           __ andq(l_lo, rscratch1);
2499           break;
2500         case lir_logic_or:
2501           __ orq(l_lo, rscratch1);
2502           break;
2503         case lir_logic_xor:
2504           __ xorq(l_lo, rscratch1);
2505           break;
2506         default: ShouldNotReachHere();
2507       }
2508 #else
2509       int r_lo = right->as_constant_ptr()->as_jint_lo();
2510       int r_hi = right->as_constant_ptr()->as_jint_hi();
2511       switch (code) {
2512         case lir_logic_and:
2513           __ andl(l_lo, r_lo);
2514           __ andl(l_hi, r_hi);
2515           break;
2516         case lir_logic_or:
2517           __ orl(l_lo, r_lo);
2518           __ orl(l_hi, r_hi);
2519           break;
2520         case lir_logic_xor:
2521           __ xorl(l_lo, r_lo);
2522           __ xorl(l_hi, r_hi);
2523           break;
2524         default: ShouldNotReachHere();
2525       }
2526 #endif // _LP64
2527     } else {
2528 #ifdef _LP64
2529       Register r_lo;
2530       if (right->type() == T_OBJECT || right->type() == T_ARRAY) {
2531         r_lo = right->as_register();
2532       } else {
2533         r_lo = right->as_register_lo();
2534       }
2535 #else
2536       Register r_lo = right->as_register_lo();
2537       Register r_hi = right->as_register_hi();
2538       assert(l_lo != r_hi, "overwriting registers");
2539 #endif
2540       switch (code) {
2541         case lir_logic_and:
2542           __ andptr(l_lo, r_lo);
2543           NOT_LP64(__ andptr(l_hi, r_hi);)
2544           break;
2545         case lir_logic_or:
2546           __ orptr(l_lo, r_lo);
2547           NOT_LP64(__ orptr(l_hi, r_hi);)
2548           break;
2549         case lir_logic_xor:
2550           __ xorptr(l_lo, r_lo);
2551           NOT_LP64(__ xorptr(l_hi, r_hi);)
2552           break;
2553         default: ShouldNotReachHere();
2554       }
2555     }
2556 
2557     Register dst_lo = dst->as_register_lo();
2558     Register dst_hi = dst->as_register_hi();
2559 
2560 #ifdef _LP64
2561     move_regs(l_lo, dst_lo);
2562 #else
2563     if (dst_lo == l_hi) {
2564       assert(dst_hi != l_lo, "overwriting registers");
2565       move_regs(l_hi, dst_hi);
2566       move_regs(l_lo, dst_lo);
2567     } else {
2568       assert(dst_lo != l_hi, "overwriting registers");
2569       move_regs(l_lo, dst_lo);
2570       move_regs(l_hi, dst_hi);
2571     }
2572 #endif // _LP64
2573   }
2574 }
2575 
2576 
2577 // we assume that rax, and rdx can be overwritten
2578 void LIR_Assembler::arithmetic_idiv(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr temp, LIR_Opr result, CodeEmitInfo* info) {
2579 
2580   assert(left->is_single_cpu(),   "left must be register");
2581   assert(right->is_single_cpu() || right->is_constant(),  "right must be register or constant");
2582   assert(result->is_single_cpu(), "result must be register");
2583 
2584   //  assert(left->destroys_register(), "check");
2585   //  assert(right->destroys_register(), "check");
2586 
2587   Register lreg = left->as_register();
2588   Register dreg = result->as_register();
2589 
2590   if (right->is_constant()) {
2591     jint divisor = right->as_constant_ptr()->as_jint();
2592     assert(divisor > 0 && is_power_of_2(divisor), "must be");
2593     if (code == lir_idiv) {
2594       assert(lreg == rax, "must be rax,");
2595       assert(temp->as_register() == rdx, "tmp register must be rdx");
2596       __ cdql(); // sign extend into rdx:rax
2597       if (divisor == 2) {
2598         __ subl(lreg, rdx);
2599       } else {
2600         __ andl(rdx, divisor - 1);
2601         __ addl(lreg, rdx);
2602       }
2603       __ sarl(lreg, log2_jint(divisor));
2604       move_regs(lreg, dreg);
2605     } else if (code == lir_irem) {
2606       Label done;
2607       __ mov(dreg, lreg);
2608       __ andl(dreg, 0x80000000 | (divisor - 1));
2609       __ jcc(Assembler::positive, done);
2610       __ decrement(dreg);
2611       __ orl(dreg, ~(divisor - 1));
2612       __ increment(dreg);
2613       __ bind(done);
2614     } else {
2615       ShouldNotReachHere();
2616     }
2617   } else {
2618     Register rreg = right->as_register();
2619     assert(lreg == rax, "left register must be rax,");
2620     assert(rreg != rdx, "right register must not be rdx");
2621     assert(temp->as_register() == rdx, "tmp register must be rdx");
2622 
2623     move_regs(lreg, rax);
2624 
2625     int idivl_offset = __ corrected_idivl(rreg);
2626     if (ImplicitDiv0Checks) {
2627       add_debug_info_for_div0(idivl_offset, info);
2628     }
2629     if (code == lir_irem) {
2630       move_regs(rdx, dreg); // result is in rdx
2631     } else {
2632       move_regs(rax, dreg);
2633     }
2634   }
2635 }
2636 
2637 
2638 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) {
2639   if (opr1->is_single_cpu()) {
2640     Register reg1 = opr1->as_register();
2641     if (opr2->is_single_cpu()) {
2642       // cpu register - cpu register
2643       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2644         __ cmpoop(reg1, opr2->as_register());
2645       } else {
2646         assert(opr2->type() != T_OBJECT && opr2->type() != T_ARRAY, "cmp int, oop?");
2647         __ cmpl(reg1, opr2->as_register());
2648       }
2649     } else if (opr2->is_stack()) {
2650       // cpu register - stack
2651       if (opr1->type() == T_OBJECT || opr1->type() == T_ARRAY) {
2652         __ cmpoop(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2653       } else {
2654         __ cmpl(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2655       }
2656     } else if (opr2->is_constant()) {
2657       // cpu register - constant
2658       LIR_Const* c = opr2->as_constant_ptr();
2659       if (c->type() == T_INT) {
2660         __ cmpl(reg1, c->as_jint());
2661       } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2662         // In 64bit oops are single register
2663         jobject o = c->as_jobject();
2664         if (o == NULL) {
2665           __ cmpptr(reg1, (int32_t)NULL_WORD);
2666         } else {
2667           __ cmpoop(reg1, o);
2668         }
2669       } else {
2670         fatal("unexpected type: %s", basictype_to_str(c->type()));
2671       }
2672       // cpu register - address
2673     } else if (opr2->is_address()) {
2674       if (op->info() != NULL) {
2675         add_debug_info_for_null_check_here(op->info());
2676       }
2677       __ cmpl(reg1, as_Address(opr2->as_address_ptr()));
2678     } else {
2679       ShouldNotReachHere();
2680     }
2681 
2682   } else if(opr1->is_double_cpu()) {
2683     Register xlo = opr1->as_register_lo();
2684     Register xhi = opr1->as_register_hi();
2685     if (opr2->is_double_cpu()) {
2686 #ifdef _LP64
2687       __ cmpptr(xlo, opr2->as_register_lo());
2688 #else
2689       // cpu register - cpu register
2690       Register ylo = opr2->as_register_lo();
2691       Register yhi = opr2->as_register_hi();
2692       __ subl(xlo, ylo);
2693       __ sbbl(xhi, yhi);
2694       if (condition == lir_cond_equal || condition == lir_cond_notEqual) {
2695         __ orl(xhi, xlo);
2696       }
2697 #endif // _LP64
2698     } else if (opr2->is_constant()) {
2699       // cpu register - constant 0
2700       assert(opr2->as_jlong() == (jlong)0, "only handles zero");
2701 #ifdef _LP64
2702       __ cmpptr(xlo, (int32_t)opr2->as_jlong());
2703 #else
2704       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles equals case");
2705       __ orl(xhi, xlo);
2706 #endif // _LP64
2707     } else {
2708       ShouldNotReachHere();
2709     }
2710 
2711   } else if (opr1->is_single_xmm()) {
2712     XMMRegister reg1 = opr1->as_xmm_float_reg();
2713     if (opr2->is_single_xmm()) {
2714       // xmm register - xmm register
2715       __ ucomiss(reg1, opr2->as_xmm_float_reg());
2716     } else if (opr2->is_stack()) {
2717       // xmm register - stack
2718       __ ucomiss(reg1, frame_map()->address_for_slot(opr2->single_stack_ix()));
2719     } else if (opr2->is_constant()) {
2720       // xmm register - constant
2721       __ ucomiss(reg1, InternalAddress(float_constant(opr2->as_jfloat())));
2722     } else if (opr2->is_address()) {
2723       // xmm register - address
2724       if (op->info() != NULL) {
2725         add_debug_info_for_null_check_here(op->info());
2726       }
2727       __ ucomiss(reg1, as_Address(opr2->as_address_ptr()));
2728     } else {
2729       ShouldNotReachHere();
2730     }
2731 
2732   } else if (opr1->is_double_xmm()) {
2733     XMMRegister reg1 = opr1->as_xmm_double_reg();
2734     if (opr2->is_double_xmm()) {
2735       // xmm register - xmm register
2736       __ ucomisd(reg1, opr2->as_xmm_double_reg());
2737     } else if (opr2->is_stack()) {
2738       // xmm register - stack
2739       __ ucomisd(reg1, frame_map()->address_for_slot(opr2->double_stack_ix()));
2740     } else if (opr2->is_constant()) {
2741       // xmm register - constant
2742       __ ucomisd(reg1, InternalAddress(double_constant(opr2->as_jdouble())));
2743     } else if (opr2->is_address()) {
2744       // xmm register - address
2745       if (op->info() != NULL) {
2746         add_debug_info_for_null_check_here(op->info());
2747       }
2748       __ ucomisd(reg1, as_Address(opr2->pointer()->as_address()));
2749     } else {
2750       ShouldNotReachHere();
2751     }
2752 
2753   } else if(opr1->is_single_fpu() || opr1->is_double_fpu()) {
2754     assert(opr1->is_fpu_register() && opr1->fpu() == 0, "currently left-hand side must be on TOS (relax this restriction)");
2755     assert(opr2->is_fpu_register(), "both must be registers");
2756     __ fcmp(noreg, opr2->fpu(), op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2757 
2758   } else if (opr1->is_address() && opr2->is_constant()) {
2759     LIR_Const* c = opr2->as_constant_ptr();
2760 #ifdef _LP64
2761     if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2762       assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "need to reverse");
2763       __ movoop(rscratch1, c->as_jobject());
2764     }
2765 #endif // LP64
2766     if (op->info() != NULL) {
2767       add_debug_info_for_null_check_here(op->info());
2768     }
2769     // special case: address - constant
2770     LIR_Address* addr = opr1->as_address_ptr();
2771     if (c->type() == T_INT) {
2772       __ cmpl(as_Address(addr), c->as_jint());
2773     } else if (c->type() == T_OBJECT || c->type() == T_ARRAY) {
2774 #ifdef _LP64
2775       // %%% Make this explode if addr isn't reachable until we figure out a
2776       // better strategy by giving noreg as the temp for as_Address
2777       __ cmpoop(rscratch1, as_Address(addr, noreg));
2778 #else
2779       __ cmpoop(as_Address(addr), c->as_jobject());
2780 #endif // _LP64
2781     } else {
2782       ShouldNotReachHere();
2783     }
2784 
2785   } else {
2786     ShouldNotReachHere();
2787   }
2788 }
2789 
2790 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op) {
2791   if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) {
2792     if (left->is_single_xmm()) {
2793       assert(right->is_single_xmm(), "must match");
2794       __ cmpss2int(left->as_xmm_float_reg(), right->as_xmm_float_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2795     } else if (left->is_double_xmm()) {
2796       assert(right->is_double_xmm(), "must match");
2797       __ cmpsd2int(left->as_xmm_double_reg(), right->as_xmm_double_reg(), dst->as_register(), code == lir_ucmp_fd2i);
2798 
2799     } else {
2800       assert(left->is_single_fpu() || left->is_double_fpu(), "must be");
2801       assert(right->is_single_fpu() || right->is_double_fpu(), "must match");
2802 
2803       assert(left->fpu() == 0, "left must be on TOS");
2804       __ fcmp2int(dst->as_register(), code == lir_ucmp_fd2i, right->fpu(),
2805                   op->fpu_pop_count() > 0, op->fpu_pop_count() > 1);
2806     }
2807   } else {
2808     assert(code == lir_cmp_l2i, "check");
2809 #ifdef _LP64
2810     Label done;
2811     Register dest = dst->as_register();
2812     __ cmpptr(left->as_register_lo(), right->as_register_lo());
2813     __ movl(dest, -1);
2814     __ jccb(Assembler::less, done);
2815     __ set_byte_if_not_zero(dest);
2816     __ movzbl(dest, dest);
2817     __ bind(done);
2818 #else
2819     __ lcmp2int(left->as_register_hi(),
2820                 left->as_register_lo(),
2821                 right->as_register_hi(),
2822                 right->as_register_lo());
2823     move_regs(left->as_register_hi(), dst->as_register());
2824 #endif // _LP64
2825   }
2826 }
2827 
2828 
2829 void LIR_Assembler::align_call(LIR_Code code) {
2830   // make sure that the displacement word of the call ends up word aligned
2831   int offset = __ offset();
2832   switch (code) {
2833   case lir_static_call:
2834   case lir_optvirtual_call:
2835   case lir_dynamic_call:
2836     offset += NativeCall::displacement_offset;
2837     break;
2838   case lir_icvirtual_call:
2839     offset += NativeCall::displacement_offset + NativeMovConstReg::instruction_size;
2840     break;
2841   case lir_virtual_call:  // currently, sparc-specific for niagara
2842   default: ShouldNotReachHere();
2843   }
2844   __ align(BytesPerWord, offset);
2845 }
2846 
2847 
2848 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) {
2849   assert((__ offset() + NativeCall::displacement_offset) % BytesPerWord == 0,
2850          "must be aligned");
2851   __ call(AddressLiteral(op->addr(), rtype));
2852   add_call_info(code_offset(), op->info());
2853   __ oopmap_metadata(op->info());
2854   __ post_call_nop();
2855 }
2856 
2857 
2858 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) {
2859   __ ic_call(op->addr());
2860   add_call_info(code_offset(), op->info());
2861   __ oopmap_metadata(op->info());
2862   assert((__ offset() - NativeCall::instruction_size + NativeCall::displacement_offset) % BytesPerWord == 0,
2863          "must be aligned");
2864   __ post_call_nop();
2865 }
2866 
2867 
2868 /* Currently, vtable-dispatch is only enabled for sparc platforms */
2869 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) {
2870   ShouldNotReachHere();
2871 }
2872 
2873 
2874 void LIR_Assembler::emit_static_call_stub() {
2875   address call_pc = __ pc();
2876   address stub = __ start_a_stub(call_stub_size());
2877   if (stub == NULL) {
2878     bailout("static call stub overflow");
2879     return;
2880   }
2881 
2882   int start = __ offset();
2883 
2884   // make sure that the displacement word of the call ends up word aligned
2885   __ align(BytesPerWord, __ offset() + NativeMovConstReg::instruction_size + NativeCall::displacement_offset);
2886   __ relocate(static_stub_Relocation::spec(call_pc, false /* is_aot */));
2887   __ mov_metadata(rbx, (Metadata*)NULL);
2888   // must be set to -1 at code generation time
2889   assert(((__ offset() + 1) % BytesPerWord) == 0, "must be aligned");
2890   // On 64bit this will die since it will take a movq & jmp, must be only a jmp
2891   __ jump(RuntimeAddress(__ pc()));
2892 
2893   if (UseAOT) {
2894     // Trampoline to aot code
2895     __ relocate(static_stub_Relocation::spec(call_pc, true /* is_aot */));
2896 #ifdef _LP64
2897     __ mov64(rax, CONST64(0));  // address is zapped till fixup time.
2898 #else
2899     __ movl(rax, 0xdeadffff);  // address is zapped till fixup time.
2900 #endif
2901     __ jmp(rax);
2902   }
2903   assert(__ offset() - start <= call_stub_size(), "stub too big");
2904   __ end_a_stub();
2905 }
2906 
2907 
2908 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) {
2909   assert(exceptionOop->as_register() == rax, "must match");
2910   assert(exceptionPC->as_register() == rdx, "must match");
2911 
2912   // exception object is not added to oop map by LinearScan
2913   // (LinearScan assumes that no oops are in fixed registers)
2914   info->add_register_oop(exceptionOop);
2915   Runtime1::StubID unwind_id;
2916 
2917   // get current pc information
2918   // pc is only needed if the method has an exception handler, the unwind code does not need it.
2919   int pc_for_athrow_offset = __ offset();
2920   InternalAddress pc_for_athrow(__ pc());
2921   __ lea(exceptionPC->as_register(), pc_for_athrow);
2922   add_call_info(pc_for_athrow_offset, info); // for exception handler
2923 
2924   __ verify_not_null_oop(rax);
2925   // search an exception handler (rax: exception oop, rdx: throwing pc)
2926   if (compilation()->has_fpu_code()) {
2927     unwind_id = Runtime1::handle_exception_id;
2928   } else {
2929     unwind_id = Runtime1::handle_exception_nofpu_id;
2930   }
2931   __ call(RuntimeAddress(Runtime1::entry_for(unwind_id)));
2932 
2933   // enough room for two byte trap
2934   __ nop();
2935 }
2936 
2937 
2938 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) {
2939   assert(exceptionOop->as_register() == rax, "must match");
2940 
2941   __ jmp(_unwind_handler_entry);
2942 }
2943 
2944 
2945 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) {
2946 
2947   // optimized version for linear scan:
2948   // * count must be already in ECX (guaranteed by LinearScan)
2949   // * left and dest must be equal
2950   // * tmp must be unused
2951   assert(count->as_register() == SHIFT_count, "count must be in ECX");
2952   assert(left == dest, "left and dest must be equal");
2953   assert(tmp->is_illegal(), "wasting a register if tmp is allocated");
2954 
2955   if (left->is_single_cpu()) {
2956     Register value = left->as_register();
2957     assert(value != SHIFT_count, "left cannot be ECX");
2958 
2959     switch (code) {
2960       case lir_shl:  __ shll(value); break;
2961       case lir_shr:  __ sarl(value); break;
2962       case lir_ushr: __ shrl(value); break;
2963       default: ShouldNotReachHere();
2964     }
2965   } else if (left->is_double_cpu()) {
2966     Register lo = left->as_register_lo();
2967     Register hi = left->as_register_hi();
2968     assert(lo != SHIFT_count && hi != SHIFT_count, "left cannot be ECX");
2969 #ifdef _LP64
2970     switch (code) {
2971       case lir_shl:  __ shlptr(lo);        break;
2972       case lir_shr:  __ sarptr(lo);        break;
2973       case lir_ushr: __ shrptr(lo);        break;
2974       default: ShouldNotReachHere();
2975     }
2976 #else
2977 
2978     switch (code) {
2979       case lir_shl:  __ lshl(hi, lo);        break;
2980       case lir_shr:  __ lshr(hi, lo, true);  break;
2981       case lir_ushr: __ lshr(hi, lo, false); break;
2982       default: ShouldNotReachHere();
2983     }
2984 #endif // LP64
2985   } else {
2986     ShouldNotReachHere();
2987   }
2988 }
2989 
2990 
2991 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) {
2992   if (dest->is_single_cpu()) {
2993     // first move left into dest so that left is not destroyed by the shift
2994     Register value = dest->as_register();
2995     count = count & 0x1F; // Java spec
2996 
2997     move_regs(left->as_register(), value);
2998     switch (code) {
2999       case lir_shl:  __ shll(value, count); break;
3000       case lir_shr:  __ sarl(value, count); break;
3001       case lir_ushr: __ shrl(value, count); break;
3002       default: ShouldNotReachHere();
3003     }
3004   } else if (dest->is_double_cpu()) {
3005 #ifndef _LP64
3006     Unimplemented();
3007 #else
3008     // first move left into dest so that left is not destroyed by the shift
3009     Register value = dest->as_register_lo();
3010     count = count & 0x1F; // Java spec
3011 
3012     move_regs(left->as_register_lo(), value);
3013     switch (code) {
3014       case lir_shl:  __ shlptr(value, count); break;
3015       case lir_shr:  __ sarptr(value, count); break;
3016       case lir_ushr: __ shrptr(value, count); break;
3017       default: ShouldNotReachHere();
3018     }
3019 #endif // _LP64
3020   } else {
3021     ShouldNotReachHere();
3022   }
3023 }
3024 
3025 
3026 void LIR_Assembler::store_parameter(Register r, int offset_from_rsp_in_words) {
3027   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3028   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3029   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3030   __ movptr (Address(rsp, offset_from_rsp_in_bytes), r);
3031 }
3032 
3033 
3034 void LIR_Assembler::store_parameter(jint c,     int offset_from_rsp_in_words) {
3035   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3036   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3037   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3038   __ movptr (Address(rsp, offset_from_rsp_in_bytes), c);
3039 }
3040 
3041 
3042 void LIR_Assembler::store_parameter(jobject o,  int offset_from_rsp_in_words) {
3043   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3044   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3045   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3046   __ movoop (Address(rsp, offset_from_rsp_in_bytes), o);
3047 }
3048 
3049 
3050 void LIR_Assembler::store_parameter(Metadata* m,  int offset_from_rsp_in_words) {
3051   assert(offset_from_rsp_in_words >= 0, "invalid offset from rsp");
3052   int offset_from_rsp_in_bytes = offset_from_rsp_in_words * BytesPerWord;
3053   assert(offset_from_rsp_in_bytes < frame_map()->reserved_argument_area_size(), "invalid offset");
3054   __ mov_metadata(Address(rsp, offset_from_rsp_in_bytes), m);
3055 }
3056 
3057 
3058 // This code replaces a call to arraycopy; no exception may
3059 // be thrown in this code, they must be thrown in the System.arraycopy
3060 // activation frame; we could save some checks if this would not be the case
3061 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) {
3062   ciArrayKlass* default_type = op->expected_type();
3063   Register src = op->src()->as_register();
3064   Register dst = op->dst()->as_register();
3065   Register src_pos = op->src_pos()->as_register();
3066   Register dst_pos = op->dst_pos()->as_register();
3067   Register length  = op->length()->as_register();
3068   Register tmp = op->tmp()->as_register();
3069 
3070   __ resolve(ACCESS_READ, src);
3071   __ resolve(ACCESS_WRITE, dst);
3072 
3073   CodeStub* stub = op->stub();
3074   int flags = op->flags();
3075   BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL;
3076   if (basic_type == T_ARRAY) basic_type = T_OBJECT;
3077 
3078   // if we don't know anything, just go through the generic arraycopy
3079   if (default_type == NULL) {
3080     // save outgoing arguments on stack in case call to System.arraycopy is needed
3081     // HACK ALERT. This code used to push the parameters in a hardwired fashion
3082     // for interpreter calling conventions. Now we have to do it in new style conventions.
3083     // For the moment until C1 gets the new register allocator I just force all the
3084     // args to the right place (except the register args) and then on the back side
3085     // reload the register args properly if we go slow path. Yuck
3086 
3087     // These are proper for the calling convention
3088     store_parameter(length, 2);
3089     store_parameter(dst_pos, 1);
3090     store_parameter(dst, 0);
3091 
3092     // these are just temporary placements until we need to reload
3093     store_parameter(src_pos, 3);
3094     store_parameter(src, 4);
3095     NOT_LP64(assert(src == rcx && src_pos == rdx, "mismatch in calling convention");)
3096 
3097     address copyfunc_addr = StubRoutines::generic_arraycopy();
3098     assert(copyfunc_addr != NULL, "generic arraycopy stub required");
3099 
3100     // pass arguments: may push as this is not a safepoint; SP must be fix at each safepoint
3101 #ifdef _LP64
3102     // The arguments are in java calling convention so we can trivially shift them to C
3103     // convention
3104     assert_different_registers(c_rarg0, j_rarg1, j_rarg2, j_rarg3, j_rarg4);
3105     __ mov(c_rarg0, j_rarg0);
3106     assert_different_registers(c_rarg1, j_rarg2, j_rarg3, j_rarg4);
3107     __ mov(c_rarg1, j_rarg1);
3108     assert_different_registers(c_rarg2, j_rarg3, j_rarg4);
3109     __ mov(c_rarg2, j_rarg2);
3110     assert_different_registers(c_rarg3, j_rarg4);
3111     __ mov(c_rarg3, j_rarg3);
3112 #ifdef _WIN64
3113     // Allocate abi space for args but be sure to keep stack aligned
3114     __ subptr(rsp, 6*wordSize);
3115     store_parameter(j_rarg4, 4);
3116 #ifndef PRODUCT
3117     if (PrintC1Statistics) {
3118       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3119     }
3120 #endif
3121     __ call(RuntimeAddress(copyfunc_addr));
3122     __ addptr(rsp, 6*wordSize);
3123 #else
3124     __ mov(c_rarg4, j_rarg4);
3125 #ifndef PRODUCT
3126     if (PrintC1Statistics) {
3127       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3128     }
3129 #endif
3130     __ call(RuntimeAddress(copyfunc_addr));
3131 #endif // _WIN64
3132 #else
3133     __ push(length);
3134     __ push(dst_pos);
3135     __ push(dst);
3136     __ push(src_pos);
3137     __ push(src);
3138 
3139 #ifndef PRODUCT
3140     if (PrintC1Statistics) {
3141       __ incrementl(ExternalAddress((address)&Runtime1::_generic_arraycopystub_cnt));
3142     }
3143 #endif
3144     __ call_VM_leaf(copyfunc_addr, 5); // removes pushed parameter from the stack
3145 
3146 #endif // _LP64
3147 
3148     __ cmpl(rax, 0);
3149     __ jcc(Assembler::equal, *stub->continuation());
3150 
3151     __ mov(tmp, rax);
3152     __ xorl(tmp, -1);
3153 
3154     // Reload values from the stack so they are where the stub
3155     // expects them.
3156     __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3157     __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3158     __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3159     __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3160     __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3161 
3162     __ subl(length, tmp);
3163     __ addl(src_pos, tmp);
3164     __ addl(dst_pos, tmp);
3165     __ jmp(*stub->entry());
3166 
3167     __ bind(*stub->continuation());
3168     return;
3169   }
3170 
3171   assert(default_type != NULL && default_type->is_array_klass() && default_type->is_loaded(), "must be true at this point");
3172 
3173   int elem_size = type2aelembytes(basic_type);
3174   Address::ScaleFactor scale;
3175 
3176   switch (elem_size) {
3177     case 1 :
3178       scale = Address::times_1;
3179       break;
3180     case 2 :
3181       scale = Address::times_2;
3182       break;
3183     case 4 :
3184       scale = Address::times_4;
3185       break;
3186     case 8 :
3187       scale = Address::times_8;
3188       break;
3189     default:
3190       scale = Address::no_scale;
3191       ShouldNotReachHere();
3192   }
3193 
3194   Address src_length_addr = Address(src, arrayOopDesc::length_offset_in_bytes());
3195   Address dst_length_addr = Address(dst, arrayOopDesc::length_offset_in_bytes());
3196   Address src_klass_addr = Address(src, oopDesc::klass_offset_in_bytes());
3197   Address dst_klass_addr = Address(dst, oopDesc::klass_offset_in_bytes());
3198 
3199   // length and pos's are all sign extended at this point on 64bit
3200 
3201   // test for NULL
3202   if (flags & LIR_OpArrayCopy::src_null_check) {
3203     __ testptr(src, src);
3204     __ jcc(Assembler::zero, *stub->entry());
3205   }
3206   if (flags & LIR_OpArrayCopy::dst_null_check) {
3207     __ testptr(dst, dst);
3208     __ jcc(Assembler::zero, *stub->entry());
3209   }
3210 
3211   // If the compiler was not able to prove that exact type of the source or the destination
3212   // of the arraycopy is an array type, check at runtime if the source or the destination is
3213   // an instance type.
3214   if (flags & LIR_OpArrayCopy::type_check) {
3215     if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3216       __ load_klass(tmp, dst);
3217       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3218       __ jcc(Assembler::greaterEqual, *stub->entry());
3219     }
3220 
3221     if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3222       __ load_klass(tmp, src);
3223       __ cmpl(Address(tmp, in_bytes(Klass::layout_helper_offset())), Klass::_lh_neutral_value);
3224       __ jcc(Assembler::greaterEqual, *stub->entry());
3225     }
3226   }
3227 
3228   // check if negative
3229   if (flags & LIR_OpArrayCopy::src_pos_positive_check) {
3230     __ testl(src_pos, src_pos);
3231     __ jcc(Assembler::less, *stub->entry());
3232   }
3233   if (flags & LIR_OpArrayCopy::dst_pos_positive_check) {
3234     __ testl(dst_pos, dst_pos);
3235     __ jcc(Assembler::less, *stub->entry());
3236   }
3237 
3238   if (flags & LIR_OpArrayCopy::src_range_check) {
3239     __ lea(tmp, Address(src_pos, length, Address::times_1, 0));
3240     __ cmpl(tmp, src_length_addr);
3241     __ jcc(Assembler::above, *stub->entry());
3242   }
3243   if (flags & LIR_OpArrayCopy::dst_range_check) {
3244     __ lea(tmp, Address(dst_pos, length, Address::times_1, 0));
3245     __ cmpl(tmp, dst_length_addr);
3246     __ jcc(Assembler::above, *stub->entry());
3247   }
3248 
3249   if (flags & LIR_OpArrayCopy::length_positive_check) {
3250     __ testl(length, length);
3251     __ jcc(Assembler::less, *stub->entry());
3252   }
3253 
3254 #ifdef _LP64
3255   __ movl2ptr(src_pos, src_pos); //higher 32bits must be null
3256   __ movl2ptr(dst_pos, dst_pos); //higher 32bits must be null
3257 #endif
3258 
3259   if (flags & LIR_OpArrayCopy::type_check) {
3260     // We don't know the array types are compatible
3261     if (basic_type != T_OBJECT) {
3262       // Simple test for basic type arrays
3263       if (UseCompressedClassPointers) {
3264         __ movl(tmp, src_klass_addr);
3265         __ cmpl(tmp, dst_klass_addr);
3266       } else {
3267         __ movptr(tmp, src_klass_addr);
3268         __ cmpptr(tmp, dst_klass_addr);
3269       }
3270       __ jcc(Assembler::notEqual, *stub->entry());
3271     } else {
3272       // For object arrays, if src is a sub class of dst then we can
3273       // safely do the copy.
3274       Label cont, slow;
3275 
3276       __ push(src);
3277       __ push(dst);
3278 
3279       __ load_klass(src, src);
3280       __ load_klass(dst, dst);
3281 
3282       __ check_klass_subtype_fast_path(src, dst, tmp, &cont, &slow, NULL);
3283 
3284       __ push(src);
3285       __ push(dst);
3286       __ call(RuntimeAddress(Runtime1::entry_for(Runtime1::slow_subtype_check_id)));
3287       __ pop(dst);
3288       __ pop(src);
3289 
3290       __ cmpl(src, 0);
3291       __ jcc(Assembler::notEqual, cont);
3292 
3293       __ bind(slow);
3294       __ pop(dst);
3295       __ pop(src);
3296 
3297       address copyfunc_addr = StubRoutines::checkcast_arraycopy();
3298       if (copyfunc_addr != NULL) { // use stub if available
3299         // src is not a sub class of dst so we have to do a
3300         // per-element check.
3301 
3302         int mask = LIR_OpArrayCopy::src_objarray|LIR_OpArrayCopy::dst_objarray;
3303         if ((flags & mask) != mask) {
3304           // Check that at least both of them object arrays.
3305           assert(flags & mask, "one of the two should be known to be an object array");
3306 
3307           if (!(flags & LIR_OpArrayCopy::src_objarray)) {
3308             __ load_klass(tmp, src);
3309           } else if (!(flags & LIR_OpArrayCopy::dst_objarray)) {
3310             __ load_klass(tmp, dst);
3311           }
3312           int lh_offset = in_bytes(Klass::layout_helper_offset());
3313           Address klass_lh_addr(tmp, lh_offset);
3314           jint objArray_lh = Klass::array_layout_helper(T_OBJECT);
3315           __ cmpl(klass_lh_addr, objArray_lh);
3316           __ jcc(Assembler::notEqual, *stub->entry());
3317         }
3318 
3319        // Spill because stubs can use any register they like and it's
3320        // easier to restore just those that we care about.
3321        store_parameter(dst, 0);
3322        store_parameter(dst_pos, 1);
3323        store_parameter(length, 2);
3324        store_parameter(src_pos, 3);
3325        store_parameter(src, 4);
3326 
3327 #ifndef _LP64
3328         __ movptr(tmp, dst_klass_addr);
3329         __ movptr(tmp, Address(tmp, ObjArrayKlass::element_klass_offset()));
3330         __ push(tmp);
3331         __ movl(tmp, Address(tmp, Klass::super_check_offset_offset()));
3332         __ push(tmp);
3333         __ push(length);
3334         __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3335         __ push(tmp);
3336         __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3337         __ push(tmp);
3338 
3339         __ call_VM_leaf(copyfunc_addr, 5);
3340 #else
3341         __ movl2ptr(length, length); //higher 32bits must be null
3342 
3343         __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3344         assert_different_registers(c_rarg0, dst, dst_pos, length);
3345         __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3346         assert_different_registers(c_rarg1, dst, length);
3347 
3348         __ mov(c_rarg2, length);
3349         assert_different_registers(c_rarg2, dst);
3350 
3351 #ifdef _WIN64
3352         // Allocate abi space for args but be sure to keep stack aligned
3353         __ subptr(rsp, 6*wordSize);
3354         __ load_klass(c_rarg3, dst);
3355         __ movptr(c_rarg3, Address(c_rarg3, ObjArrayKlass::element_klass_offset()));
3356         store_parameter(c_rarg3, 4);
3357         __ movl(c_rarg3, Address(c_rarg3, Klass::super_check_offset_offset()));
3358         __ call(RuntimeAddress(copyfunc_addr));
3359         __ addptr(rsp, 6*wordSize);
3360 #else
3361         __ load_klass(c_rarg4, dst);
3362         __ movptr(c_rarg4, Address(c_rarg4, ObjArrayKlass::element_klass_offset()));
3363         __ movl(c_rarg3, Address(c_rarg4, Klass::super_check_offset_offset()));
3364         __ call(RuntimeAddress(copyfunc_addr));
3365 #endif
3366 
3367 #endif
3368 
3369 #ifndef PRODUCT
3370         if (PrintC1Statistics) {
3371           Label failed;
3372           __ testl(rax, rax);
3373           __ jcc(Assembler::notZero, failed);
3374           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_cnt));
3375           __ bind(failed);
3376         }
3377 #endif
3378 
3379         __ testl(rax, rax);
3380         __ jcc(Assembler::zero, *stub->continuation());
3381 
3382 #ifndef PRODUCT
3383         if (PrintC1Statistics) {
3384           __ incrementl(ExternalAddress((address)&Runtime1::_arraycopy_checkcast_attempt_cnt));
3385         }
3386 #endif
3387 
3388         __ mov(tmp, rax);
3389 
3390         __ xorl(tmp, -1);
3391 
3392         // Restore previously spilled arguments
3393         __ movptr   (dst,     Address(rsp, 0*BytesPerWord));
3394         __ movptr   (dst_pos, Address(rsp, 1*BytesPerWord));
3395         __ movptr   (length,  Address(rsp, 2*BytesPerWord));
3396         __ movptr   (src_pos, Address(rsp, 3*BytesPerWord));
3397         __ movptr   (src,     Address(rsp, 4*BytesPerWord));
3398 
3399 
3400         __ subl(length, tmp);
3401         __ addl(src_pos, tmp);
3402         __ addl(dst_pos, tmp);
3403       }
3404 
3405       __ jmp(*stub->entry());
3406 
3407       __ bind(cont);
3408       __ pop(dst);
3409       __ pop(src);
3410     }
3411   }
3412 
3413 #ifdef ASSERT
3414   if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) {
3415     // Sanity check the known type with the incoming class.  For the
3416     // primitive case the types must match exactly with src.klass and
3417     // dst.klass each exactly matching the default type.  For the
3418     // object array case, if no type check is needed then either the
3419     // dst type is exactly the expected type and the src type is a
3420     // subtype which we can't check or src is the same array as dst
3421     // but not necessarily exactly of type default_type.
3422     Label known_ok, halt;
3423     __ mov_metadata(tmp, default_type->constant_encoding());
3424 #ifdef _LP64
3425     if (UseCompressedClassPointers) {
3426       __ encode_klass_not_null(tmp);
3427     }
3428 #endif
3429 
3430     if (basic_type != T_OBJECT) {
3431 
3432       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3433       else                   __ cmpptr(tmp, dst_klass_addr);
3434       __ jcc(Assembler::notEqual, halt);
3435       if (UseCompressedClassPointers)          __ cmpl(tmp, src_klass_addr);
3436       else                   __ cmpptr(tmp, src_klass_addr);
3437       __ jcc(Assembler::equal, known_ok);
3438     } else {
3439       if (UseCompressedClassPointers)          __ cmpl(tmp, dst_klass_addr);
3440       else                   __ cmpptr(tmp, dst_klass_addr);
3441       __ jcc(Assembler::equal, known_ok);
3442       __ cmpptr(src, dst);
3443       __ jcc(Assembler::equal, known_ok);
3444     }
3445     __ bind(halt);
3446     __ stop("incorrect type information in arraycopy");
3447     __ bind(known_ok);
3448   }
3449 #endif
3450 
3451 #ifndef PRODUCT
3452   if (PrintC1Statistics) {
3453     __ incrementl(ExternalAddress(Runtime1::arraycopy_count_address(basic_type)));
3454   }
3455 #endif
3456 
3457 #ifdef _LP64
3458   assert_different_registers(c_rarg0, dst, dst_pos, length);
3459   __ lea(c_rarg0, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3460   assert_different_registers(c_rarg1, length);
3461   __ lea(c_rarg1, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3462   __ mov(c_rarg2, length);
3463 
3464 #else
3465   __ lea(tmp, Address(src, src_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3466   store_parameter(tmp, 0);
3467   __ lea(tmp, Address(dst, dst_pos, scale, arrayOopDesc::base_offset_in_bytes(basic_type)));
3468   store_parameter(tmp, 1);
3469   store_parameter(length, 2);
3470 #endif // _LP64
3471 
3472   bool disjoint = (flags & LIR_OpArrayCopy::overlapping) == 0;
3473   bool aligned = (flags & LIR_OpArrayCopy::unaligned) == 0;
3474   const char *name;
3475   address entry = StubRoutines::select_arraycopy_function(basic_type, aligned, disjoint, name, false);
3476   __ call_VM_leaf(entry, 0);
3477 
3478   __ bind(*stub->continuation());
3479 }
3480 
3481 void LIR_Assembler::emit_updatecrc32(LIR_OpUpdateCRC32* op) {
3482   assert(op->crc()->is_single_cpu(),  "crc must be register");
3483   assert(op->val()->is_single_cpu(),  "byte value must be register");
3484   assert(op->result_opr()->is_single_cpu(), "result must be register");
3485   Register crc = op->crc()->as_register();
3486   Register val = op->val()->as_register();
3487   Register res = op->result_opr()->as_register();
3488 
3489   assert_different_registers(val, crc, res);
3490 
3491   __ lea(res, ExternalAddress(StubRoutines::crc_table_addr()));
3492   __ notl(crc); // ~crc
3493   __ update_byte_crc32(crc, val, res);
3494   __ notl(crc); // ~crc
3495   __ mov(res, crc);
3496 }
3497 
3498 void LIR_Assembler::emit_lock(LIR_OpLock* op) {
3499   Register obj = op->obj_opr()->as_register();  // may not be an oop
3500   Register hdr = op->hdr_opr()->as_register();
3501   Register lock = op->lock_opr()->as_register();
3502   if (!UseFastLocking) {
3503     __ jmp(*op->stub()->entry());
3504   } else if (op->code() == lir_lock) {
3505     Register scratch = noreg;
3506     if (UseBiasedLocking) {
3507       scratch = op->scratch_opr()->as_register();
3508     }
3509     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3510     __ resolve(ACCESS_READ | ACCESS_WRITE, obj);
3511     // add debug info for NullPointerException only if one is possible
3512     int null_check_offset = __ lock_object(hdr, obj, lock, scratch, *op->stub()->entry());
3513     if (op->info() != NULL) {
3514       add_debug_info_for_null_check(null_check_offset, op->info());
3515     }
3516     // done
3517   } else if (op->code() == lir_unlock) {
3518     assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header");
3519     __ unlock_object(hdr, obj, lock, *op->stub()->entry());
3520   } else {
3521     Unimplemented();
3522   }
3523   __ bind(*op->stub()->continuation());
3524 }
3525 
3526 
3527 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) {
3528   ciMethod* method = op->profiled_method();
3529   int bci          = op->profiled_bci();
3530   ciMethod* callee = op->profiled_callee();
3531 
3532   // Update counter for all call types
3533   ciMethodData* md = method->method_data_or_null();
3534   assert(md != NULL, "Sanity");
3535   ciProfileData* data = md->bci_to_data(bci);
3536   assert(data != NULL && data->is_CounterData(), "need CounterData for calls");
3537   assert(op->mdo()->is_single_cpu(),  "mdo must be allocated");
3538   Register mdo  = op->mdo()->as_register();
3539   __ mov_metadata(mdo, md->constant_encoding());
3540   Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()));
3541   // Perform additional virtual call profiling for invokevirtual and
3542   // invokeinterface bytecodes
3543   if (op->should_profile_receiver_type()) {
3544     assert(op->recv()->is_single_cpu(), "recv must be allocated");
3545     Register recv = op->recv()->as_register();
3546     assert_different_registers(mdo, recv);
3547     assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls");
3548     ciKlass* known_klass = op->known_holder();
3549     if (C1OptimizeVirtualCallProfiling && known_klass != NULL) {
3550       // We know the type that will be seen at this call site; we can
3551       // statically update the MethodData* rather than needing to do
3552       // dynamic tests on the receiver type
3553 
3554       // NOTE: we should probably put a lock around this search to
3555       // avoid collisions by concurrent compilations
3556       ciVirtualCallData* vc_data = (ciVirtualCallData*) data;
3557       uint i;
3558       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3559         ciKlass* receiver = vc_data->receiver(i);
3560         if (known_klass->equals(receiver)) {
3561           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3562           __ addptr(data_addr, DataLayout::counter_increment);
3563           return;
3564         }
3565       }
3566 
3567       // Receiver type not found in profile data; select an empty slot
3568 
3569       // Note that this is less efficient than it should be because it
3570       // always does a write to the receiver part of the
3571       // VirtualCallData rather than just the first time
3572       for (i = 0; i < VirtualCallData::row_limit(); i++) {
3573         ciKlass* receiver = vc_data->receiver(i);
3574         if (receiver == NULL) {
3575           Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)));
3576           __ mov_metadata(recv_addr, known_klass->constant_encoding());
3577           Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)));
3578           __ addptr(data_addr, DataLayout::counter_increment);
3579           return;
3580         }
3581       }
3582     } else {
3583       __ load_klass(recv, recv);
3584       Label update_done;
3585       type_profile_helper(mdo, md, data, recv, &update_done);
3586       // Receiver did not match any saved receiver and there is no empty row for it.
3587       // Increment total counter to indicate polymorphic case.
3588       __ addptr(counter_addr, DataLayout::counter_increment);
3589 
3590       __ bind(update_done);
3591     }
3592   } else {
3593     // Static call
3594     __ addptr(counter_addr, DataLayout::counter_increment);
3595   }
3596 }
3597 
3598 void LIR_Assembler::emit_profile_type(LIR_OpProfileType* op) {
3599   Register obj = op->obj()->as_register();
3600   Register tmp = op->tmp()->as_pointer_register();
3601   Address mdo_addr = as_Address(op->mdp()->as_address_ptr());
3602   ciKlass* exact_klass = op->exact_klass();
3603   intptr_t current_klass = op->current_klass();
3604   bool not_null = op->not_null();
3605   bool no_conflict = op->no_conflict();
3606 
3607   Label update, next, none;
3608 
3609   bool do_null = !not_null;
3610   bool exact_klass_set = exact_klass != NULL && ciTypeEntries::valid_ciklass(current_klass) == exact_klass;
3611   bool do_update = !TypeEntries::is_type_unknown(current_klass) && !exact_klass_set;
3612 
3613   assert(do_null || do_update, "why are we here?");
3614   assert(!TypeEntries::was_null_seen(current_klass) || do_update, "why are we here?");
3615 
3616   __ verify_oop(obj);
3617 
3618   if (tmp != obj) {
3619     __ mov(tmp, obj);
3620   }
3621   if (do_null) {
3622     __ testptr(tmp, tmp);
3623     __ jccb(Assembler::notZero, update);
3624     if (!TypeEntries::was_null_seen(current_klass)) {
3625       __ orptr(mdo_addr, TypeEntries::null_seen);
3626     }
3627     if (do_update) {
3628 #ifndef ASSERT
3629       __ jmpb(next);
3630     }
3631 #else
3632       __ jmp(next);
3633     }
3634   } else {
3635     __ testptr(tmp, tmp);
3636     __ jcc(Assembler::notZero, update);
3637     __ stop("unexpect null obj");
3638 #endif
3639   }
3640 
3641   __ bind(update);
3642 
3643   if (do_update) {
3644 #ifdef ASSERT
3645     if (exact_klass != NULL) {
3646       Label ok;
3647       __ load_klass(tmp, tmp);
3648       __ push(tmp);
3649       __ mov_metadata(tmp, exact_klass->constant_encoding());
3650       __ cmpptr(tmp, Address(rsp, 0));
3651       __ jcc(Assembler::equal, ok);
3652       __ stop("exact klass and actual klass differ");
3653       __ bind(ok);
3654       __ pop(tmp);
3655     }
3656 #endif
3657     if (!no_conflict) {
3658       if (exact_klass == NULL || TypeEntries::is_type_none(current_klass)) {
3659         if (exact_klass != NULL) {
3660           __ mov_metadata(tmp, exact_klass->constant_encoding());
3661         } else {
3662           __ load_klass(tmp, tmp);
3663         }
3664 
3665         __ xorptr(tmp, mdo_addr);
3666         __ testptr(tmp, TypeEntries::type_klass_mask);
3667         // klass seen before, nothing to do. The unknown bit may have been
3668         // set already but no need to check.
3669         __ jccb(Assembler::zero, next);
3670 
3671         __ testptr(tmp, TypeEntries::type_unknown);
3672         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3673 
3674         if (TypeEntries::is_type_none(current_klass)) {
3675           __ cmpptr(mdo_addr, 0);
3676           __ jccb(Assembler::equal, none);
3677           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3678           __ jccb(Assembler::equal, none);
3679           // There is a chance that the checks above (re-reading profiling
3680           // data from memory) fail if another thread has just set the
3681           // profiling to this obj's klass
3682           __ xorptr(tmp, mdo_addr);
3683           __ testptr(tmp, TypeEntries::type_klass_mask);
3684           __ jccb(Assembler::zero, next);
3685         }
3686       } else {
3687         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3688                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "conflict only");
3689 
3690         __ movptr(tmp, mdo_addr);
3691         __ testptr(tmp, TypeEntries::type_unknown);
3692         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3693       }
3694 
3695       // different than before. Cannot keep accurate profile.
3696       __ orptr(mdo_addr, TypeEntries::type_unknown);
3697 
3698       if (TypeEntries::is_type_none(current_klass)) {
3699         __ jmpb(next);
3700 
3701         __ bind(none);
3702         // first time here. Set profile type.
3703         __ movptr(mdo_addr, tmp);
3704       }
3705     } else {
3706       // There's a single possible klass at this profile point
3707       assert(exact_klass != NULL, "should be");
3708       if (TypeEntries::is_type_none(current_klass)) {
3709         __ mov_metadata(tmp, exact_klass->constant_encoding());
3710         __ xorptr(tmp, mdo_addr);
3711         __ testptr(tmp, TypeEntries::type_klass_mask);
3712 #ifdef ASSERT
3713         __ jcc(Assembler::zero, next);
3714 
3715         {
3716           Label ok;
3717           __ push(tmp);
3718           __ cmpptr(mdo_addr, 0);
3719           __ jcc(Assembler::equal, ok);
3720           __ cmpptr(mdo_addr, TypeEntries::null_seen);
3721           __ jcc(Assembler::equal, ok);
3722           // may have been set by another thread
3723           __ mov_metadata(tmp, exact_klass->constant_encoding());
3724           __ xorptr(tmp, mdo_addr);
3725           __ testptr(tmp, TypeEntries::type_mask);
3726           __ jcc(Assembler::zero, ok);
3727 
3728           __ stop("unexpected profiling mismatch");
3729           __ bind(ok);
3730           __ pop(tmp);
3731         }
3732 #else
3733         __ jccb(Assembler::zero, next);
3734 #endif
3735         // first time here. Set profile type.
3736         __ movptr(mdo_addr, tmp);
3737       } else {
3738         assert(ciTypeEntries::valid_ciklass(current_klass) != NULL &&
3739                ciTypeEntries::valid_ciklass(current_klass) != exact_klass, "inconsistent");
3740 
3741         __ movptr(tmp, mdo_addr);
3742         __ testptr(tmp, TypeEntries::type_unknown);
3743         __ jccb(Assembler::notZero, next); // already unknown. Nothing to do anymore.
3744 
3745         __ orptr(mdo_addr, TypeEntries::type_unknown);
3746       }
3747     }
3748 
3749     __ bind(next);
3750   }
3751 }
3752 
3753 void LIR_Assembler::emit_delay(LIR_OpDelay*) {
3754   Unimplemented();
3755 }
3756 
3757 
3758 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst) {
3759   __ lea(dst->as_register(), frame_map()->address_for_monitor_lock(monitor_no));
3760 }
3761 
3762 
3763 void LIR_Assembler::align_backward_branch_target() {
3764   __ align(BytesPerWord);
3765 }
3766 
3767 
3768 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest, LIR_Opr tmp) {
3769   if (left->is_single_cpu()) {
3770     __ negl(left->as_register());
3771     move_regs(left->as_register(), dest->as_register());
3772 
3773   } else if (left->is_double_cpu()) {
3774     Register lo = left->as_register_lo();
3775 #ifdef _LP64
3776     Register dst = dest->as_register_lo();
3777     __ movptr(dst, lo);
3778     __ negptr(dst);
3779 #else
3780     Register hi = left->as_register_hi();
3781     __ lneg(hi, lo);
3782     if (dest->as_register_lo() == hi) {
3783       assert(dest->as_register_hi() != lo, "destroying register");
3784       move_regs(hi, dest->as_register_hi());
3785       move_regs(lo, dest->as_register_lo());
3786     } else {
3787       move_regs(lo, dest->as_register_lo());
3788       move_regs(hi, dest->as_register_hi());
3789     }
3790 #endif // _LP64
3791 
3792   } else if (dest->is_single_xmm()) {
3793 #ifdef _LP64
3794     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3795       assert(tmp->is_valid(), "need temporary");
3796       assert_different_registers(left->as_xmm_float_reg(), tmp->as_xmm_float_reg());
3797       __ vpxor(dest->as_xmm_float_reg(), tmp->as_xmm_float_reg(), left->as_xmm_float_reg(), 2);
3798     }
3799     else
3800 #endif
3801     {
3802       assert(!tmp->is_valid(), "do not need temporary");
3803       if (left->as_xmm_float_reg() != dest->as_xmm_float_reg()) {
3804         __ movflt(dest->as_xmm_float_reg(), left->as_xmm_float_reg());
3805       }
3806       __ xorps(dest->as_xmm_float_reg(),
3807                ExternalAddress((address)float_signflip_pool));
3808     }
3809   } else if (dest->is_double_xmm()) {
3810 #ifdef _LP64
3811     if (UseAVX > 2 && !VM_Version::supports_avx512vl()) {
3812       assert(tmp->is_valid(), "need temporary");
3813       assert_different_registers(left->as_xmm_double_reg(), tmp->as_xmm_double_reg());
3814       __ vpxor(dest->as_xmm_double_reg(), tmp->as_xmm_double_reg(), left->as_xmm_double_reg(), 2);
3815     }
3816     else
3817 #endif
3818     {
3819       assert(!tmp->is_valid(), "do not need temporary");
3820       if (left->as_xmm_double_reg() != dest->as_xmm_double_reg()) {
3821         __ movdbl(dest->as_xmm_double_reg(), left->as_xmm_double_reg());
3822       }
3823       __ xorpd(dest->as_xmm_double_reg(),
3824                ExternalAddress((address)double_signflip_pool));
3825     }
3826   } else if (left->is_single_fpu() || left->is_double_fpu()) {
3827     assert(left->fpu() == 0, "arg must be on TOS");
3828     assert(dest->fpu() == 0, "dest must be TOS");
3829     __ fchs();
3830 
3831   } else {
3832     ShouldNotReachHere();
3833   }
3834 }
3835 
3836 
3837 void LIR_Assembler::leal(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) {
3838   assert(src->is_address(), "must be an address");
3839   assert(dest->is_register(), "must be a register");
3840 
3841   PatchingStub* patch = NULL;
3842   if (patch_code != lir_patch_none) {
3843     patch = new PatchingStub(_masm, PatchingStub::access_field_id);
3844   }
3845 
3846   Register reg = dest->as_pointer_register();
3847   LIR_Address* addr = src->as_address_ptr();
3848   __ lea(reg, as_Address(addr));
3849 
3850   if (patch != NULL) {
3851     patching_epilog(patch, patch_code, addr->base()->as_register(), info);
3852   }
3853 }
3854 
3855 
3856 
3857 void LIR_Assembler::rt_call(LIR_Opr result, address dest, const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) {
3858   assert(!tmp->is_valid(), "don't need temporary");
3859   __ call(RuntimeAddress(dest));
3860   if (info != NULL) {
3861     add_call_info_here(info);
3862     __ oopmap_metadata(info);
3863   }
3864   __ post_call_nop();
3865 }
3866 
3867 
3868 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) {
3869   assert(type == T_LONG, "only for volatile long fields");
3870 
3871   if (info != NULL) {
3872     add_debug_info_for_null_check_here(info);
3873   }
3874 
3875   if (src->is_double_xmm()) {
3876     if (dest->is_double_cpu()) {
3877 #ifdef _LP64
3878       __ movdq(dest->as_register_lo(), src->as_xmm_double_reg());
3879 #else
3880       __ movdl(dest->as_register_lo(), src->as_xmm_double_reg());
3881       __ psrlq(src->as_xmm_double_reg(), 32);
3882       __ movdl(dest->as_register_hi(), src->as_xmm_double_reg());
3883 #endif // _LP64
3884     } else if (dest->is_double_stack()) {
3885       __ movdbl(frame_map()->address_for_slot(dest->double_stack_ix()), src->as_xmm_double_reg());
3886     } else if (dest->is_address()) {
3887       __ movdbl(as_Address(dest->as_address_ptr()), src->as_xmm_double_reg());
3888     } else {
3889       ShouldNotReachHere();
3890     }
3891 
3892   } else if (dest->is_double_xmm()) {
3893     if (src->is_double_stack()) {
3894       __ movdbl(dest->as_xmm_double_reg(), frame_map()->address_for_slot(src->double_stack_ix()));
3895     } else if (src->is_address()) {
3896       __ movdbl(dest->as_xmm_double_reg(), as_Address(src->as_address_ptr()));
3897     } else {
3898       ShouldNotReachHere();
3899     }
3900 
3901   } else if (src->is_double_fpu()) {
3902     assert(src->fpu_regnrLo() == 0, "must be TOS");
3903     if (dest->is_double_stack()) {
3904       __ fistp_d(frame_map()->address_for_slot(dest->double_stack_ix()));
3905     } else if (dest->is_address()) {
3906       __ fistp_d(as_Address(dest->as_address_ptr()));
3907     } else {
3908       ShouldNotReachHere();
3909     }
3910 
3911   } else if (dest->is_double_fpu()) {
3912     assert(dest->fpu_regnrLo() == 0, "must be TOS");
3913     if (src->is_double_stack()) {
3914       __ fild_d(frame_map()->address_for_slot(src->double_stack_ix()));
3915     } else if (src->is_address()) {
3916       __ fild_d(as_Address(src->as_address_ptr()));
3917     } else {
3918       ShouldNotReachHere();
3919     }
3920   } else {
3921     ShouldNotReachHere();
3922   }
3923 }
3924 
3925 #ifdef ASSERT
3926 // emit run-time assertion
3927 void LIR_Assembler::emit_assert(LIR_OpAssert* op) {
3928   assert(op->code() == lir_assert, "must be");
3929 
3930   if (op->in_opr1()->is_valid()) {
3931     assert(op->in_opr2()->is_valid(), "both operands must be valid");
3932     comp_op(op->condition(), op->in_opr1(), op->in_opr2(), op);
3933   } else {
3934     assert(op->in_opr2()->is_illegal(), "both operands must be illegal");
3935     assert(op->condition() == lir_cond_always, "no other conditions allowed");
3936   }
3937 
3938   Label ok;
3939   if (op->condition() != lir_cond_always) {
3940     Assembler::Condition acond = Assembler::zero;
3941     switch (op->condition()) {
3942       case lir_cond_equal:        acond = Assembler::equal;       break;
3943       case lir_cond_notEqual:     acond = Assembler::notEqual;    break;
3944       case lir_cond_less:         acond = Assembler::less;        break;
3945       case lir_cond_lessEqual:    acond = Assembler::lessEqual;   break;
3946       case lir_cond_greaterEqual: acond = Assembler::greaterEqual;break;
3947       case lir_cond_greater:      acond = Assembler::greater;     break;
3948       case lir_cond_belowEqual:   acond = Assembler::belowEqual;  break;
3949       case lir_cond_aboveEqual:   acond = Assembler::aboveEqual;  break;
3950       default:                    ShouldNotReachHere();
3951     }
3952     __ jcc(acond, ok);
3953   }
3954   if (op->halt()) {
3955     const char* str = __ code_string(op->msg());
3956     __ stop(str);
3957   } else {
3958     breakpoint();
3959   }
3960   __ bind(ok);
3961 }
3962 #endif
3963 
3964 void LIR_Assembler::membar() {
3965   // QQQ sparc TSO uses this,
3966   __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad));
3967 }
3968 
3969 void LIR_Assembler::membar_acquire() {
3970   // No x86 machines currently require load fences
3971 }
3972 
3973 void LIR_Assembler::membar_release() {
3974   // No x86 machines currently require store fences
3975 }
3976 
3977 void LIR_Assembler::membar_loadload() {
3978   // no-op
3979   //__ membar(Assembler::Membar_mask_bits(Assembler::loadload));
3980 }
3981 
3982 void LIR_Assembler::membar_storestore() {
3983   // no-op
3984   //__ membar(Assembler::Membar_mask_bits(Assembler::storestore));
3985 }
3986 
3987 void LIR_Assembler::membar_loadstore() {
3988   // no-op
3989   //__ membar(Assembler::Membar_mask_bits(Assembler::loadstore));
3990 }
3991 
3992 void LIR_Assembler::membar_storeload() {
3993   __ membar(Assembler::Membar_mask_bits(Assembler::StoreLoad));
3994 }
3995 
3996 void LIR_Assembler::on_spin_wait() {
3997   __ pause ();
3998 }
3999 
4000 void LIR_Assembler::get_thread(LIR_Opr result_reg) {
4001   assert(result_reg->is_register(), "check");
4002 #ifdef _LP64
4003   // __ get_thread(result_reg->as_register_lo());
4004   __ mov(result_reg->as_register(), r15_thread);
4005 #else
4006   __ get_thread(result_reg->as_register());
4007 #endif // _LP64
4008 }
4009 
4010 
4011 void LIR_Assembler::peephole(LIR_List*) {
4012   // do nothing for now
4013 }
4014 
4015 void LIR_Assembler::atomic_op(LIR_Code code, LIR_Opr src, LIR_Opr data, LIR_Opr dest, LIR_Opr tmp) {
4016   assert(data == dest, "xchg/xadd uses only 2 operands");
4017 
4018   if (data->type() == T_INT) {
4019     if (code == lir_xadd) {
4020       __ lock();
4021       __ xaddl(as_Address(src->as_address_ptr()), data->as_register());
4022     } else {
4023       __ xchgl(data->as_register(), as_Address(src->as_address_ptr()));
4024     }
4025   } else if (data->is_oop()) {
4026     assert (code == lir_xchg, "xadd for oops");
4027     Register obj = data->as_register();
4028 #ifdef _LP64
4029     if (UseCompressedOops) {
4030       __ encode_heap_oop(obj);
4031       __ xchgl(obj, as_Address(src->as_address_ptr()));
4032       __ decode_heap_oop(obj);
4033     } else {
4034       __ xchgptr(obj, as_Address(src->as_address_ptr()));
4035     }
4036 #else
4037     __ xchgl(obj, as_Address(src->as_address_ptr()));
4038 #endif
4039   } else if (data->type() == T_LONG) {
4040 #ifdef _LP64
4041     assert(data->as_register_lo() == data->as_register_hi(), "should be a single register");
4042     if (code == lir_xadd) {
4043       __ lock();
4044       __ xaddq(as_Address(src->as_address_ptr()), data->as_register_lo());
4045     } else {
4046       __ xchgq(data->as_register_lo(), as_Address(src->as_address_ptr()));
4047     }
4048 #else
4049     ShouldNotReachHere();
4050 #endif
4051   } else {
4052     ShouldNotReachHere();
4053   }
4054 }
4055 
4056 #undef __