1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/compiler_globals.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "gc/shared/barrierSet.hpp"
  32 #include "gc/shared/barrierSetAssembler.hpp"
  33 #include "gc/shared/collectedHeap.inline.hpp"
  34 #include "gc/shared/tlab_globals.hpp"
  35 #include "interpreter/bytecodeHistogram.hpp"
  36 #include "interpreter/interpreter.hpp"
  37 #include "memory/resourceArea.hpp"
  38 #include "memory/universe.hpp"
  39 #include "oops/accessDecorators.hpp"
  40 #include "oops/compressedOops.inline.hpp"
  41 #include "oops/klass.inline.hpp"
  42 #include "prims/methodHandles.hpp"
  43 #include "runtime/flags/flagSetting.hpp"
  44 #include "runtime/interfaceSupport.inline.hpp"
  45 #include "runtime/jniHandles.hpp"
  46 #include "runtime/objectMonitor.hpp"
  47 #include "runtime/os.hpp"
  48 #include "runtime/safepoint.hpp"
  49 #include "runtime/safepointMechanism.hpp"
  50 #include "runtime/sharedRuntime.hpp"
  51 #include "runtime/stubRoutines.hpp"
  52 #include "runtime/thread.hpp"
  53 #include "utilities/macros.hpp"
  54 #include "crc32c.h"
  55 
  56 #ifdef PRODUCT
  57 #define BLOCK_COMMENT(str) /* nothing */
  58 #define STOP(error) stop(error)
  59 #else
  60 #define BLOCK_COMMENT(str) block_comment(str)
  61 #define STOP(error) block_comment(error); stop(error)
  62 #endif
  63 
  64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  65 
  66 #ifdef ASSERT
  67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  68 #endif
  69 
  70 static Assembler::Condition reverse[] = {
  71     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  72     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  73     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  74     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  75     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  76     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  77     Assembler::above          /* belowEqual    = 0x6 */ ,
  78     Assembler::belowEqual     /* above         = 0x7 */ ,
  79     Assembler::positive       /* negative      = 0x8 */ ,
  80     Assembler::negative       /* positive      = 0x9 */ ,
  81     Assembler::noParity       /* parity        = 0xa */ ,
  82     Assembler::parity         /* noParity      = 0xb */ ,
  83     Assembler::greaterEqual   /* less          = 0xc */ ,
  84     Assembler::less           /* greaterEqual  = 0xd */ ,
  85     Assembler::greater        /* lessEqual     = 0xe */ ,
  86     Assembler::lessEqual      /* greater       = 0xf, */
  87 
  88 };
  89 
  90 
  91 // Implementation of MacroAssembler
  92 
  93 // First all the versions that have distinct versions depending on 32/64 bit
  94 // Unless the difference is trivial (1 line or so).
  95 
  96 #ifndef _LP64
  97 
  98 // 32bit versions
  99 
 100 Address MacroAssembler::as_Address(AddressLiteral adr) {
 101   return Address(adr.target(), adr.rspec());
 102 }
 103 
 104 Address MacroAssembler::as_Address(ArrayAddress adr) {
 105   return Address::make_array(adr);
 106 }
 107 
 108 void MacroAssembler::call_VM_leaf_base(address entry_point,
 109                                        int number_of_arguments) {
 110   call(RuntimeAddress(entry_point));
 111   increment(rsp, number_of_arguments * wordSize);
 112 }
 113 
 114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 115   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 116 }
 117 
 118 
 119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 120   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 121 }
 122 
 123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 124   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 125 }
 126 
 127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 128   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 129 }
 130 
 131 void MacroAssembler::extend_sign(Register hi, Register lo) {
 132   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 133   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 134     cdql();
 135   } else {
 136     movl(hi, lo);
 137     sarl(hi, 31);
 138   }
 139 }
 140 
 141 void MacroAssembler::jC2(Register tmp, Label& L) {
 142   // set parity bit if FPU flag C2 is set (via rax)
 143   save_rax(tmp);
 144   fwait(); fnstsw_ax();
 145   sahf();
 146   restore_rax(tmp);
 147   // branch
 148   jcc(Assembler::parity, L);
 149 }
 150 
 151 void MacroAssembler::jnC2(Register tmp, Label& L) {
 152   // set parity bit if FPU flag C2 is set (via rax)
 153   save_rax(tmp);
 154   fwait(); fnstsw_ax();
 155   sahf();
 156   restore_rax(tmp);
 157   // branch
 158   jcc(Assembler::noParity, L);
 159 }
 160 
 161 // 32bit can do a case table jump in one instruction but we no longer allow the base
 162 // to be installed in the Address class
 163 void MacroAssembler::jump(ArrayAddress entry) {
 164   jmp(as_Address(entry));
 165 }
 166 
 167 // Note: y_lo will be destroyed
 168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 169   // Long compare for Java (semantics as described in JVM spec.)
 170   Label high, low, done;
 171 
 172   cmpl(x_hi, y_hi);
 173   jcc(Assembler::less, low);
 174   jcc(Assembler::greater, high);
 175   // x_hi is the return register
 176   xorl(x_hi, x_hi);
 177   cmpl(x_lo, y_lo);
 178   jcc(Assembler::below, low);
 179   jcc(Assembler::equal, done);
 180 
 181   bind(high);
 182   xorl(x_hi, x_hi);
 183   increment(x_hi);
 184   jmp(done);
 185 
 186   bind(low);
 187   xorl(x_hi, x_hi);
 188   decrementl(x_hi);
 189 
 190   bind(done);
 191 }
 192 
 193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 194     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 195 }
 196 
 197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 198   // leal(dst, as_Address(adr));
 199   // see note in movl as to why we must use a move
 200   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 201 }
 202 
 203 void MacroAssembler::leave() {
 204   mov(rsp, rbp);
 205   pop(rbp);
 206 }
 207 
 208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 209   // Multiplication of two Java long values stored on the stack
 210   // as illustrated below. Result is in rdx:rax.
 211   //
 212   // rsp ---> [  ??  ] \               \
 213   //            ....    | y_rsp_offset  |
 214   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 215   //          [ y_hi ]                  | (in bytes)
 216   //            ....                    |
 217   //          [ x_lo ]                 /
 218   //          [ x_hi ]
 219   //            ....
 220   //
 221   // Basic idea: lo(result) = lo(x_lo * y_lo)
 222   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 223   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 224   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 225   Label quick;
 226   // load x_hi, y_hi and check if quick
 227   // multiplication is possible
 228   movl(rbx, x_hi);
 229   movl(rcx, y_hi);
 230   movl(rax, rbx);
 231   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 232   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 233   // do full multiplication
 234   // 1st step
 235   mull(y_lo);                                    // x_hi * y_lo
 236   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 237   // 2nd step
 238   movl(rax, x_lo);
 239   mull(rcx);                                     // x_lo * y_hi
 240   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 241   // 3rd step
 242   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 243   movl(rax, x_lo);
 244   mull(y_lo);                                    // x_lo * y_lo
 245   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 246 }
 247 
 248 void MacroAssembler::lneg(Register hi, Register lo) {
 249   negl(lo);
 250   adcl(hi, 0);
 251   negl(hi);
 252 }
 253 
 254 void MacroAssembler::lshl(Register hi, Register lo) {
 255   // Java shift left long support (semantics as described in JVM spec., p.305)
 256   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 257   // shift value is in rcx !
 258   assert(hi != rcx, "must not use rcx");
 259   assert(lo != rcx, "must not use rcx");
 260   const Register s = rcx;                        // shift count
 261   const int      n = BitsPerWord;
 262   Label L;
 263   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 264   cmpl(s, n);                                    // if (s < n)
 265   jcc(Assembler::less, L);                       // else (s >= n)
 266   movl(hi, lo);                                  // x := x << n
 267   xorl(lo, lo);
 268   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 269   bind(L);                                       // s (mod n) < n
 270   shldl(hi, lo);                                 // x := x << s
 271   shll(lo);
 272 }
 273 
 274 
 275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 276   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 277   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 278   assert(hi != rcx, "must not use rcx");
 279   assert(lo != rcx, "must not use rcx");
 280   const Register s = rcx;                        // shift count
 281   const int      n = BitsPerWord;
 282   Label L;
 283   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 284   cmpl(s, n);                                    // if (s < n)
 285   jcc(Assembler::less, L);                       // else (s >= n)
 286   movl(lo, hi);                                  // x := x >> n
 287   if (sign_extension) sarl(hi, 31);
 288   else                xorl(hi, hi);
 289   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 290   bind(L);                                       // s (mod n) < n
 291   shrdl(lo, hi);                                 // x := x >> s
 292   if (sign_extension) sarl(hi);
 293   else                shrl(hi);
 294 }
 295 
 296 void MacroAssembler::movoop(Register dst, jobject obj) {
 297   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 298 }
 299 
 300 void MacroAssembler::movoop(Address dst, jobject obj) {
 301   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 302 }
 303 
 304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 305   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 309   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 313   // scratch register is not used,
 314   // it is defined to match parameters of 64-bit version of this method.
 315   if (src.is_lval()) {
 316     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 317   } else {
 318     movl(dst, as_Address(src));
 319   }
 320 }
 321 
 322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 323   movl(as_Address(dst), src);
 324 }
 325 
 326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 327   movl(dst, as_Address(src));
 328 }
 329 
 330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 331 void MacroAssembler::movptr(Address dst, intptr_t src) {
 332   movl(dst, src);
 333 }
 334 
 335 
 336 void MacroAssembler::pop_callee_saved_registers() {
 337   pop(rcx);
 338   pop(rdx);
 339   pop(rdi);
 340   pop(rsi);
 341 }
 342 
 343 void MacroAssembler::push_callee_saved_registers() {
 344   push(rsi);
 345   push(rdi);
 346   push(rdx);
 347   push(rcx);
 348 }
 349 
 350 void MacroAssembler::pushoop(jobject obj) {
 351   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 352 }
 353 
 354 void MacroAssembler::pushklass(Metadata* obj) {
 355   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 356 }
 357 
 358 void MacroAssembler::pushptr(AddressLiteral src) {
 359   if (src.is_lval()) {
 360     push_literal32((int32_t)src.target(), src.rspec());
 361   } else {
 362     pushl(as_Address(src));
 363   }
 364 }
 365 
 366 static void pass_arg0(MacroAssembler* masm, Register arg) {
 367   masm->push(arg);
 368 }
 369 
 370 static void pass_arg1(MacroAssembler* masm, Register arg) {
 371   masm->push(arg);
 372 }
 373 
 374 static void pass_arg2(MacroAssembler* masm, Register arg) {
 375   masm->push(arg);
 376 }
 377 
 378 static void pass_arg3(MacroAssembler* masm, Register arg) {
 379   masm->push(arg);
 380 }
 381 
 382 #ifndef PRODUCT
 383 extern "C" void findpc(intptr_t x);
 384 #endif
 385 
 386 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 387   // In order to get locks to work, we need to fake a in_VM state
 388   JavaThread* thread = JavaThread::current();
 389   JavaThreadState saved_state = thread->thread_state();
 390   thread->set_thread_state(_thread_in_vm);
 391   if (ShowMessageBoxOnError) {
 392     JavaThread* thread = JavaThread::current();
 393     JavaThreadState saved_state = thread->thread_state();
 394     thread->set_thread_state(_thread_in_vm);
 395     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 396       ttyLocker ttyl;
 397       BytecodeCounter::print();
 398     }
 399     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 400     // This is the value of eip which points to where verify_oop will return.
 401     if (os::message_box(msg, "Execution stopped, print registers?")) {
 402       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 403       BREAKPOINT;
 404     }
 405   }
 406   fatal("DEBUG MESSAGE: %s", msg);
 407 }
 408 
 409 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 410   ttyLocker ttyl;
 411   FlagSetting fs(Debugging, true);
 412   tty->print_cr("eip = 0x%08x", eip);
 413 #ifndef PRODUCT
 414   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 415     tty->cr();
 416     findpc(eip);
 417     tty->cr();
 418   }
 419 #endif
 420 #define PRINT_REG(rax) \
 421   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 422   PRINT_REG(rax);
 423   PRINT_REG(rbx);
 424   PRINT_REG(rcx);
 425   PRINT_REG(rdx);
 426   PRINT_REG(rdi);
 427   PRINT_REG(rsi);
 428   PRINT_REG(rbp);
 429   PRINT_REG(rsp);
 430 #undef PRINT_REG
 431   // Print some words near top of staack.
 432   int* dump_sp = (int*) rsp;
 433   for (int col1 = 0; col1 < 8; col1++) {
 434     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 435     os::print_location(tty, *dump_sp++);
 436   }
 437   for (int row = 0; row < 16; row++) {
 438     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 439     for (int col = 0; col < 8; col++) {
 440       tty->print(" 0x%08x", *dump_sp++);
 441     }
 442     tty->cr();
 443   }
 444   // Print some instructions around pc:
 445   Disassembler::decode((address)eip-64, (address)eip);
 446   tty->print_cr("--------");
 447   Disassembler::decode((address)eip, (address)eip+32);
 448 }
 449 
 450 void MacroAssembler::stop(const char* msg) {
 451   ExternalAddress message((address)msg);
 452   // push address of message
 453   pushptr(message.addr());
 454   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 455   pusha();                                            // push registers
 456   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 457   hlt();
 458 }
 459 
 460 void MacroAssembler::warn(const char* msg) {
 461   push_CPU_state();
 462 
 463   ExternalAddress message((address) msg);
 464   // push address of message
 465   pushptr(message.addr());
 466 
 467   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 468   addl(rsp, wordSize);       // discard argument
 469   pop_CPU_state();
 470 }
 471 
 472 void MacroAssembler::print_state() {
 473   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 474   pusha();                                            // push registers
 475 
 476   push_CPU_state();
 477   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 478   pop_CPU_state();
 479 
 480   popa();
 481   addl(rsp, wordSize);
 482 }
 483 
 484 #else // _LP64
 485 
 486 // 64 bit versions
 487 
 488 Address MacroAssembler::as_Address(AddressLiteral adr) {
 489   // amd64 always does this as a pc-rel
 490   // we can be absolute or disp based on the instruction type
 491   // jmp/call are displacements others are absolute
 492   assert(!adr.is_lval(), "must be rval");
 493   assert(reachable(adr), "must be");
 494   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 495 
 496 }
 497 
 498 Address MacroAssembler::as_Address(ArrayAddress adr) {
 499   AddressLiteral base = adr.base();
 500   lea(rscratch1, base);
 501   Address index = adr.index();
 502   assert(index._disp == 0, "must not have disp"); // maybe it can?
 503   Address array(rscratch1, index._index, index._scale, index._disp);
 504   return array;
 505 }
 506 
 507 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 508   Label L, E;
 509 
 510 #ifdef _WIN64
 511   // Windows always allocates space for it's register args
 512   assert(num_args <= 4, "only register arguments supported");
 513   subq(rsp,  frame::arg_reg_save_area_bytes);
 514 #endif
 515 
 516   // Align stack if necessary
 517   testl(rsp, 15);
 518   jcc(Assembler::zero, L);
 519 
 520   subq(rsp, 8);
 521   {
 522     call(RuntimeAddress(entry_point));
 523     oopmap_metadata(-1);
 524   }
 525   addq(rsp, 8);
 526   jmp(E);
 527 
 528   bind(L);
 529   {
 530     call(RuntimeAddress(entry_point));
 531     oopmap_metadata(-1);
 532   }
 533 
 534   bind(E);
 535 
 536 #ifdef _WIN64
 537   // restore stack pointer
 538   addq(rsp, frame::arg_reg_save_area_bytes);
 539 #endif
 540 
 541 }
 542 
 543 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 544   assert(!src2.is_lval(), "should use cmpptr");
 545 
 546   if (reachable(src2)) {
 547     cmpq(src1, as_Address(src2));
 548   } else {
 549     lea(rscratch1, src2);
 550     Assembler::cmpq(src1, Address(rscratch1, 0));
 551   }
 552 }
 553 
 554 int MacroAssembler::corrected_idivq(Register reg) {
 555   // Full implementation of Java ldiv and lrem; checks for special
 556   // case as described in JVM spec., p.243 & p.271.  The function
 557   // returns the (pc) offset of the idivl instruction - may be needed
 558   // for implicit exceptions.
 559   //
 560   //         normal case                           special case
 561   //
 562   // input : rax: dividend                         min_long
 563   //         reg: divisor   (may not be eax/edx)   -1
 564   //
 565   // output: rax: quotient  (= rax idiv reg)       min_long
 566   //         rdx: remainder (= rax irem reg)       0
 567   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 568   static const int64_t min_long = 0x8000000000000000;
 569   Label normal_case, special_case;
 570 
 571   // check for special case
 572   cmp64(rax, ExternalAddress((address) &min_long));
 573   jcc(Assembler::notEqual, normal_case);
 574   xorl(rdx, rdx); // prepare rdx for possible special case (where
 575                   // remainder = 0)
 576   cmpq(reg, -1);
 577   jcc(Assembler::equal, special_case);
 578 
 579   // handle normal case
 580   bind(normal_case);
 581   cdqq();
 582   int idivq_offset = offset();
 583   idivq(reg);
 584 
 585   // normal and special case exit
 586   bind(special_case);
 587 
 588   return idivq_offset;
 589 }
 590 
 591 void MacroAssembler::decrementq(Register reg, int value) {
 592   if (value == min_jint) { subq(reg, value); return; }
 593   if (value <  0) { incrementq(reg, -value); return; }
 594   if (value == 0) {                        ; return; }
 595   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 596   /* else */      { subq(reg, value)       ; return; }
 597 }
 598 
 599 void MacroAssembler::decrementq(Address dst, int value) {
 600   if (value == min_jint) { subq(dst, value); return; }
 601   if (value <  0) { incrementq(dst, -value); return; }
 602   if (value == 0) {                        ; return; }
 603   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 604   /* else */      { subq(dst, value)       ; return; }
 605 }
 606 
 607 void MacroAssembler::incrementq(AddressLiteral dst) {
 608   if (reachable(dst)) {
 609     incrementq(as_Address(dst));
 610   } else {
 611     lea(rscratch1, dst);
 612     incrementq(Address(rscratch1, 0));
 613   }
 614 }
 615 
 616 void MacroAssembler::incrementq(Register reg, int value) {
 617   if (value == min_jint) { addq(reg, value); return; }
 618   if (value <  0) { decrementq(reg, -value); return; }
 619   if (value == 0) {                        ; return; }
 620   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 621   /* else */      { addq(reg, value)       ; return; }
 622 }
 623 
 624 void MacroAssembler::incrementq(Address dst, int value) {
 625   if (value == min_jint) { addq(dst, value); return; }
 626   if (value <  0) { decrementq(dst, -value); return; }
 627   if (value == 0) {                        ; return; }
 628   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 629   /* else */      { addq(dst, value)       ; return; }
 630 }
 631 
 632 // 32bit can do a case table jump in one instruction but we no longer allow the base
 633 // to be installed in the Address class
 634 void MacroAssembler::jump(ArrayAddress entry) {
 635   lea(rscratch1, entry.base());
 636   Address dispatch = entry.index();
 637   assert(dispatch._base == noreg, "must be");
 638   dispatch._base = rscratch1;
 639   jmp(dispatch);
 640 }
 641 
 642 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 643   ShouldNotReachHere(); // 64bit doesn't use two regs
 644   cmpq(x_lo, y_lo);
 645 }
 646 
 647 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 648     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 649 }
 650 
 651 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 652   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 653   movptr(dst, rscratch1);
 654 }
 655 
 656 void MacroAssembler::leave() {
 657   // %%% is this really better? Why not on 32bit too?
 658   emit_int8((unsigned char)0xC9); // LEAVE
 659 }
 660 
 661 void MacroAssembler::lneg(Register hi, Register lo) {
 662   ShouldNotReachHere(); // 64bit doesn't use two regs
 663   negq(lo);
 664 }
 665 
 666 void MacroAssembler::movoop(Register dst, jobject obj) {
 667   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 668 }
 669 
 670 void MacroAssembler::movoop(Address dst, jobject obj) {
 671   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 672   movq(dst, rscratch1);
 673 }
 674 
 675 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 676   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 677 }
 678 
 679 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 680   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 681   movq(dst, rscratch1);
 682 }
 683 
 684 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 685   if (src.is_lval()) {
 686     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 687   } else {
 688     if (reachable(src)) {
 689       movq(dst, as_Address(src));
 690     } else {
 691       lea(scratch, src);
 692       movq(dst, Address(scratch, 0));
 693     }
 694   }
 695 }
 696 
 697 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 698   movq(as_Address(dst), src);
 699 }
 700 
 701 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 702   movq(dst, as_Address(src));
 703 }
 704 
 705 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 706 void MacroAssembler::movptr(Address dst, intptr_t src) {
 707   if (is_simm32(src)) {
 708     movptr(dst, checked_cast<int32_t>(src));
 709   } else {
 710     mov64(rscratch1, src);
 711     movq(dst, rscratch1);
 712   }
 713 }
 714 
 715 // These are mostly for initializing NULL
 716 void MacroAssembler::movptr(Address dst, int32_t src) {
 717   movslq(dst, src);
 718 }
 719 
 720 void MacroAssembler::movptr(Register dst, int32_t src) {
 721   mov64(dst, (intptr_t)src);
 722 }
 723 
 724 void MacroAssembler::pushoop(jobject obj) {
 725   movoop(rscratch1, obj);
 726   push(rscratch1);
 727 }
 728 
 729 void MacroAssembler::pushklass(Metadata* obj) {
 730   mov_metadata(rscratch1, obj);
 731   push(rscratch1);
 732 }
 733 
 734 void MacroAssembler::pushptr(AddressLiteral src) {
 735   lea(rscratch1, src);
 736   if (src.is_lval()) {
 737     push(rscratch1);
 738   } else {
 739     pushq(Address(rscratch1, 0));
 740   }
 741 }
 742 
 743 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 744   reset_last_Java_frame(r15_thread, clear_fp);
 745 }
 746 
 747 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 748                                          Register last_java_fp,
 749                                          address  last_java_pc) {
 750   vzeroupper();
 751   // determine last_java_sp register
 752   if (!last_java_sp->is_valid()) {
 753     last_java_sp = rsp;
 754   }
 755 
 756   // last_java_fp is optional
 757   if (last_java_fp->is_valid()) {
 758     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 759            last_java_fp);
 760   }
 761 
 762   // last_java_pc is optional
 763   if (last_java_pc != NULL) {
 764     Address java_pc(r15_thread,
 765                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 766     lea(rscratch1, InternalAddress(last_java_pc));
 767     movptr(java_pc, rscratch1);
 768   }
 769 
 770   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 771 }
 772 
 773 static void pass_arg0(MacroAssembler* masm, Register arg) {
 774   if (c_rarg0 != arg ) {
 775     masm->mov(c_rarg0, arg);
 776   }
 777 }
 778 
 779 static void pass_arg1(MacroAssembler* masm, Register arg) {
 780   if (c_rarg1 != arg ) {
 781     masm->mov(c_rarg1, arg);
 782   }
 783 }
 784 
 785 static void pass_arg2(MacroAssembler* masm, Register arg) {
 786   if (c_rarg2 != arg ) {
 787     masm->mov(c_rarg2, arg);
 788   }
 789 }
 790 
 791 static void pass_arg3(MacroAssembler* masm, Register arg) {
 792   if (c_rarg3 != arg ) {
 793     masm->mov(c_rarg3, arg);
 794   }
 795 }
 796 
 797 void MacroAssembler::stop(const char* msg) {
 798   if (ShowMessageBoxOnError) {
 799     address rip = pc();
 800     pusha(); // get regs on stack
 801     lea(c_rarg1, InternalAddress(rip));
 802     movq(c_rarg2, rsp); // pass pointer to regs array
 803   }
 804   lea(c_rarg0, ExternalAddress((address) msg));
 805   andq(rsp, -16); // align stack as required by ABI
 806   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 807   hlt();
 808 }
 809 
 810 void MacroAssembler::warn(const char* msg) {
 811   push(rbp);
 812   movq(rbp, rsp);
 813   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 814   push_CPU_state();   // keeps alignment at 16 bytes
 815   lea(c_rarg0, ExternalAddress((address) msg));
 816   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 817   call(rax);
 818   pop_CPU_state();
 819   mov(rsp, rbp);
 820   pop(rbp);
 821 }
 822 
 823 void MacroAssembler::_assert_asm(Assembler::Condition cc, const char* msg) {
 824 #ifdef ASSERT
 825   Label OK;
 826   jcc(cc, OK);
 827   stop(msg);
 828   bind(OK);
 829 #endif
 830 }
 831 
 832 void MacroAssembler::print_state() {
 833   address rip = pc();
 834   pusha();            // get regs on stack
 835   push(rbp);
 836   movq(rbp, rsp);
 837   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 838   push_CPU_state();   // keeps alignment at 16 bytes
 839 
 840   lea(c_rarg0, InternalAddress(rip));
 841   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 842   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 843 
 844   pop_CPU_state();
 845   mov(rsp, rbp);
 846   pop(rbp);
 847   popa();
 848 }
 849 
 850 #ifndef PRODUCT
 851 extern "C" void findpc(intptr_t x);
 852 #endif
 853 
 854 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 855   // In order to get locks to work, we need to fake a in_VM state
 856   if (ShowMessageBoxOnError) {
 857     JavaThread* thread = JavaThread::current();
 858     JavaThreadState saved_state = thread->thread_state();
 859     thread->set_thread_state(_thread_in_vm);
 860 #ifndef PRODUCT
 861     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 862       ttyLocker ttyl;
 863       BytecodeCounter::print();
 864     }
 865 #endif
 866     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 867     // XXX correct this offset for amd64
 868     // This is the value of eip which points to where verify_oop will return.
 869     if (os::message_box(msg, "Execution stopped, print registers?")) {
 870       print_state64(pc, regs);
 871       BREAKPOINT;
 872     }
 873   }
 874   fatal("DEBUG MESSAGE: %s", msg);
 875 }
 876 
 877 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 878   ttyLocker ttyl;
 879   FlagSetting fs(Debugging, true);
 880   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 881 #ifndef PRODUCT
 882   tty->cr();
 883   findpc(pc);
 884   tty->cr();
 885 #endif
 886 #define PRINT_REG(rax, value) \
 887   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 888   PRINT_REG(rax, regs[15]);
 889   PRINT_REG(rbx, regs[12]);
 890   PRINT_REG(rcx, regs[14]);
 891   PRINT_REG(rdx, regs[13]);
 892   PRINT_REG(rdi, regs[8]);
 893   PRINT_REG(rsi, regs[9]);
 894   PRINT_REG(rbp, regs[10]);
 895   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
 896   PRINT_REG(rsp, (intptr_t)(&regs[16]));
 897   PRINT_REG(r8 , regs[7]);
 898   PRINT_REG(r9 , regs[6]);
 899   PRINT_REG(r10, regs[5]);
 900   PRINT_REG(r11, regs[4]);
 901   PRINT_REG(r12, regs[3]);
 902   PRINT_REG(r13, regs[2]);
 903   PRINT_REG(r14, regs[1]);
 904   PRINT_REG(r15, regs[0]);
 905 #undef PRINT_REG
 906   // Print some words near the top of the stack.
 907   int64_t* rsp = &regs[16];
 908   int64_t* dump_sp = rsp;
 909   for (int col1 = 0; col1 < 8; col1++) {
 910     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 911     os::print_location(tty, *dump_sp++);
 912   }
 913   for (int row = 0; row < 25; row++) {
 914     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 915     for (int col = 0; col < 4; col++) {
 916       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 917     }
 918     tty->cr();
 919   }
 920   // Print some instructions around pc:
 921   Disassembler::decode((address)pc-64, (address)pc);
 922   tty->print_cr("--------");
 923   Disassembler::decode((address)pc, (address)pc+32);
 924 }
 925 
 926 // The java_calling_convention describes stack locations as ideal slots on
 927 // a frame with no abi restrictions. Since we must observe abi restrictions
 928 // (like the placement of the register window) the slots must be biased by
 929 // the following value.
 930 static int reg2offset_in(VMReg r) {
 931   // Account for saved rbp and return address
 932   // This should really be in_preserve_stack_slots
 933   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 934 }
 935 
 936 static int reg2offset_out(VMReg r) {
 937   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 938 }
 939 
 940 // A long move
 941 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
 942 
 943   // The calling conventions assures us that each VMregpair is either
 944   // all really one physical register or adjacent stack slots.
 945 
 946   if (src.is_single_phys_reg() ) {
 947     if (dst.is_single_phys_reg()) {
 948       if (dst.first() != src.first()) {
 949         mov(dst.first()->as_Register(), src.first()->as_Register());
 950       }
 951     } else {
 952       assert(dst.is_single_reg(), "not a stack pair");
 953       movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
 954     }
 955   } else if (dst.is_single_phys_reg()) {
 956     assert(src.is_single_reg(),  "not a stack pair");
 957     movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
 958   } else {
 959     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 960     movq(rax, Address(rbp, reg2offset_in(src.first())));
 961     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 962   }
 963 }
 964 
 965 // A double move
 966 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
 967 
 968   // The calling conventions assures us that each VMregpair is either
 969   // all really one physical register or adjacent stack slots.
 970 
 971   if (src.is_single_phys_reg() ) {
 972     if (dst.is_single_phys_reg()) {
 973       // In theory these overlap but the ordering is such that this is likely a nop
 974       if ( src.first() != dst.first()) {
 975         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
 976       }
 977     } else {
 978       assert(dst.is_single_reg(), "not a stack pair");
 979       movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 980     }
 981   } else if (dst.is_single_phys_reg()) {
 982     assert(src.is_single_reg(),  "not a stack pair");
 983     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
 984   } else {
 985     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 986     movq(rax, Address(rbp, reg2offset_in(src.first())));
 987     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 988   }
 989 }
 990 
 991 
 992 // A float arg may have to do float reg int reg conversion
 993 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
 994   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
 995 
 996   // The calling conventions assures us that each VMregpair is either
 997   // all really one physical register or adjacent stack slots.
 998 
 999   if (src.first()->is_stack()) {
1000     if (dst.first()->is_stack()) {
1001       movl(rax, Address(rbp, reg2offset_in(src.first())));
1002       movptr(Address(rsp, reg2offset_out(dst.first())), rax);
1003     } else {
1004       // stack to reg
1005       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1006       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
1007     }
1008   } else if (dst.first()->is_stack()) {
1009     // reg to stack
1010     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1011     movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1012   } else {
1013     // reg to reg
1014     // In theory these overlap but the ordering is such that this is likely a nop
1015     if ( src.first() != dst.first()) {
1016       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
1017     }
1018   }
1019 }
1020 
1021 // On 64 bit we will store integer like items to the stack as
1022 // 64 bits items (x86_32/64 abi) even though java would only store
1023 // 32bits for a parameter. On 32bit it will simply be 32 bits
1024 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1025 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1026   if (src.first()->is_stack()) {
1027     if (dst.first()->is_stack()) {
1028       // stack to stack
1029       movslq(rax, Address(rbp, reg2offset_in(src.first())));
1030       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1031     } else {
1032       // stack to reg
1033       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1034     }
1035   } else if (dst.first()->is_stack()) {
1036     // reg to stack
1037     // Do we really have to sign extend???
1038     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1039     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1040   } else {
1041     // Do we really have to sign extend???
1042     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1043     if (dst.first() != src.first()) {
1044       movq(dst.first()->as_Register(), src.first()->as_Register());
1045     }
1046   }
1047 }
1048 
1049 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1050   if (src.first()->is_stack()) {
1051     if (dst.first()->is_stack()) {
1052       // stack to stack
1053       movq(rax, Address(rbp, reg2offset_in(src.first())));
1054       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1055     } else {
1056       // stack to reg
1057       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1058     }
1059   } else if (dst.first()->is_stack()) {
1060     // reg to stack
1061     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1062   } else {
1063     if (dst.first() != src.first()) {
1064       movq(dst.first()->as_Register(), src.first()->as_Register());
1065     }
1066   }
1067 }
1068 
1069 // An oop arg. Must pass a handle not the oop itself
1070 void MacroAssembler::object_move(OopMap* map,
1071                         int oop_handle_offset,
1072                         int framesize_in_slots,
1073                         VMRegPair src,
1074                         VMRegPair dst,
1075                         bool is_receiver,
1076                         int* receiver_offset) {
1077 
1078   // must pass a handle. First figure out the location we use as a handle
1079 
1080   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1081 
1082   // See if oop is NULL if it is we need no handle
1083 
1084   if (src.first()->is_stack()) {
1085 
1086     // Oop is already on the stack as an argument
1087     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1088     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1089     if (is_receiver) {
1090       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1091     }
1092 
1093     cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1094     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1095     // conditionally move a NULL
1096     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1097   } else {
1098 
1099     // Oop is in an a register we must store it to the space we reserve
1100     // on the stack for oop_handles and pass a handle if oop is non-NULL
1101 
1102     const Register rOop = src.first()->as_Register();
1103     int oop_slot;
1104     if (rOop == j_rarg0)
1105       oop_slot = 0;
1106     else if (rOop == j_rarg1)
1107       oop_slot = 1;
1108     else if (rOop == j_rarg2)
1109       oop_slot = 2;
1110     else if (rOop == j_rarg3)
1111       oop_slot = 3;
1112     else if (rOop == j_rarg4)
1113       oop_slot = 4;
1114     else {
1115       assert(rOop == j_rarg5, "wrong register");
1116       oop_slot = 5;
1117     }
1118 
1119     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1120     int offset = oop_slot*VMRegImpl::stack_slot_size;
1121 
1122     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1123     // Store oop in handle area, may be NULL
1124     movptr(Address(rsp, offset), rOop);
1125     if (is_receiver) {
1126       *receiver_offset = offset;
1127     }
1128 
1129     cmpptr(rOop, (int32_t)NULL_WORD);
1130     lea(rHandle, Address(rsp, offset));
1131     // conditionally move a NULL from the handle area where it was just stored
1132     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1133   }
1134 
1135   // If arg is on the stack then place it otherwise it is already in correct reg.
1136   if (dst.first()->is_stack()) {
1137     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1138   }
1139 }
1140 
1141 #endif // _LP64
1142 
1143 // Now versions that are common to 32/64 bit
1144 
1145 void MacroAssembler::oopmap_metadata(int index) {
1146   // if (index != -1) tty->print_cr("oopmap_metadata %d", index);
1147   // mov64(r10, 1234); // TODO: Add a new relocInfo with external semantics. see relocInfo::metadata_type
1148 }
1149 
1150 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1151   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1152 }
1153 
1154 void MacroAssembler::addptr(Register dst, Register src) {
1155   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1156 }
1157 
1158 void MacroAssembler::addptr(Address dst, Register src) {
1159   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1160 }
1161 
1162 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1163   if (reachable(src)) {
1164     Assembler::addsd(dst, as_Address(src));
1165   } else {
1166     lea(rscratch1, src);
1167     Assembler::addsd(dst, Address(rscratch1, 0));
1168   }
1169 }
1170 
1171 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1172   if (reachable(src)) {
1173     addss(dst, as_Address(src));
1174   } else {
1175     lea(rscratch1, src);
1176     addss(dst, Address(rscratch1, 0));
1177   }
1178 }
1179 
1180 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1181   if (reachable(src)) {
1182     Assembler::addpd(dst, as_Address(src));
1183   } else {
1184     lea(rscratch1, src);
1185     Assembler::addpd(dst, Address(rscratch1, 0));
1186   }
1187 }
1188 
1189 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
1190 // Stub code is generated once and never copied.
1191 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1192 void MacroAssembler::align64() {
1193   align(64, (unsigned long long) pc());
1194 }
1195 
1196 void MacroAssembler::align32() {
1197   align(32, (unsigned long long) pc());
1198 }
1199 
1200 void MacroAssembler::align(int modulus) {
1201   // 8273459: Ensure alignment is possible with current segment alignment
1202   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1203   align(modulus, offset());
1204 }
1205 
1206 void MacroAssembler::align(int modulus, int target) {
1207   if (target % modulus != 0) {
1208     nop(modulus - (target % modulus));
1209   }
1210 }
1211 
1212 void MacroAssembler::push_f(XMMRegister r) {
1213   subptr(rsp, wordSize);
1214   movflt(Address(rsp, 0), r);
1215 }
1216 
1217 void MacroAssembler::pop_f(XMMRegister r) {
1218   movflt(r, Address(rsp, 0));
1219   addptr(rsp, wordSize);
1220 }
1221 
1222 void MacroAssembler::push_d(XMMRegister r) {
1223   subptr(rsp, 2 * wordSize);
1224   movdbl(Address(rsp, 0), r);
1225 }
1226 
1227 void MacroAssembler::pop_d(XMMRegister r) {
1228   movdbl(r, Address(rsp, 0));
1229   addptr(rsp, 2 * Interpreter::stackElementSize);
1230 }
1231 
1232 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1233   // Used in sign-masking with aligned address.
1234   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1235   if (reachable(src)) {
1236     Assembler::andpd(dst, as_Address(src));
1237   } else {
1238     lea(scratch_reg, src);
1239     Assembler::andpd(dst, Address(scratch_reg, 0));
1240   }
1241 }
1242 
1243 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1244   // Used in sign-masking with aligned address.
1245   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1246   if (reachable(src)) {
1247     Assembler::andps(dst, as_Address(src));
1248   } else {
1249     lea(scratch_reg, src);
1250     Assembler::andps(dst, Address(scratch_reg, 0));
1251   }
1252 }
1253 
1254 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1255   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1256 }
1257 
1258 void MacroAssembler::atomic_incl(Address counter_addr) {
1259   lock();
1260   incrementl(counter_addr);
1261 }
1262 
1263 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1264   if (reachable(counter_addr)) {
1265     atomic_incl(as_Address(counter_addr));
1266   } else {
1267     lea(scr, counter_addr);
1268     atomic_incl(Address(scr, 0));
1269   }
1270 }
1271 
1272 #ifdef _LP64
1273 void MacroAssembler::atomic_incq(Address counter_addr) {
1274   lock();
1275   incrementq(counter_addr);
1276 }
1277 
1278 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1279   if (reachable(counter_addr)) {
1280     atomic_incq(as_Address(counter_addr));
1281   } else {
1282     lea(scr, counter_addr);
1283     atomic_incq(Address(scr, 0));
1284   }
1285 }
1286 #endif
1287 
1288 // Writes to stack successive pages until offset reached to check for
1289 // stack overflow + shadow pages.  This clobbers tmp.
1290 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1291   movptr(tmp, rsp);
1292   // Bang stack for total size given plus shadow page size.
1293   // Bang one page at a time because large size can bang beyond yellow and
1294   // red zones.
1295   Label loop;
1296   bind(loop);
1297   movl(Address(tmp, (-os::vm_page_size())), size );
1298   subptr(tmp, os::vm_page_size());
1299   subl(size, os::vm_page_size());
1300   jcc(Assembler::greater, loop);
1301 
1302   // Bang down shadow pages too.
1303   // At this point, (tmp-0) is the last address touched, so don't
1304   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1305   // was post-decremented.)  Skip this address by starting at i=1, and
1306   // touch a few more pages below.  N.B.  It is important to touch all
1307   // the way down including all pages in the shadow zone.
1308   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1309     // this could be any sized move but this is can be a debugging crumb
1310     // so the bigger the better.
1311     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1312   }
1313 }
1314 
1315 void MacroAssembler::reserved_stack_check() {
1316     // testing if reserved zone needs to be enabled
1317     Label no_reserved_zone_enabling;
1318     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1319     NOT_LP64(get_thread(rsi);)
1320 
1321     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1322     jcc(Assembler::below, no_reserved_zone_enabling);
1323 
1324     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1325     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1326     should_not_reach_here();
1327 
1328     bind(no_reserved_zone_enabling);
1329 }
1330 
1331 void MacroAssembler::c2bool(Register x) {
1332   // implements x == 0 ? 0 : 1
1333   // note: must only look at least-significant byte of x
1334   //       since C-style booleans are stored in one byte
1335   //       only! (was bug)
1336   andl(x, 0xFF);
1337   setb(Assembler::notZero, x);
1338 }
1339 
1340 // Wouldn't need if AddressLiteral version had new name
1341 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1342   Assembler::call(L, rtype);
1343 }
1344 
1345 void MacroAssembler::call(Register entry) {
1346   Assembler::call(entry);
1347 }
1348 
1349 void MacroAssembler::call(AddressLiteral entry) {
1350   if (reachable(entry)) {
1351     Assembler::call_literal(entry.target(), entry.rspec());
1352   } else {
1353     lea(rscratch1, entry);
1354     Assembler::call(rscratch1);
1355   }
1356 }
1357 
1358 void MacroAssembler::ic_call(address entry, jint method_index) {
1359   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1360   movptr(rax, (intptr_t)Universe::non_oop_word());
1361   call(AddressLiteral(entry, rh));
1362 }
1363 
1364 // Implementation of call_VM versions
1365 
1366 void MacroAssembler::call_VM(Register oop_result,
1367                              address entry_point,
1368                              bool check_exceptions) {
1369   Label C, E;
1370   call(C, relocInfo::none);
1371   jmp(E);
1372 
1373   bind(C);
1374   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1375   ret(0);
1376 
1377   bind(E);
1378 }
1379 
1380 void MacroAssembler::call_VM(Register oop_result,
1381                              address entry_point,
1382                              Register arg_1,
1383                              bool check_exceptions) {
1384   Label C, E;
1385   call(C, relocInfo::none);
1386   jmp(E);
1387 
1388   bind(C);
1389   pass_arg1(this, arg_1);
1390   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1391   ret(0);
1392 
1393   bind(E);
1394 }
1395 
1396 void MacroAssembler::call_VM(Register oop_result,
1397                              address entry_point,
1398                              Register arg_1,
1399                              Register arg_2,
1400                              bool check_exceptions) {
1401   Label C, E;
1402   call(C, relocInfo::none);
1403   jmp(E);
1404 
1405   bind(C);
1406 
1407   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1408 
1409   pass_arg2(this, arg_2);
1410   pass_arg1(this, arg_1);
1411   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1412   ret(0);
1413 
1414   bind(E);
1415 }
1416 
1417 void MacroAssembler::call_VM(Register oop_result,
1418                              address entry_point,
1419                              Register arg_1,
1420                              Register arg_2,
1421                              Register arg_3,
1422                              bool check_exceptions) {
1423   Label C, E;
1424   call(C, relocInfo::none);
1425   jmp(E);
1426 
1427   bind(C);
1428 
1429   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1430   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1431   pass_arg3(this, arg_3);
1432 
1433   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1434   pass_arg2(this, arg_2);
1435 
1436   pass_arg1(this, arg_1);
1437   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1438   ret(0);
1439 
1440   bind(E);
1441 }
1442 
1443 void MacroAssembler::call_VM(Register oop_result,
1444                              Register last_java_sp,
1445                              address entry_point,
1446                              int number_of_arguments,
1447                              bool check_exceptions) {
1448   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1449   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1450 }
1451 
1452 void MacroAssembler::call_VM(Register oop_result,
1453                              Register last_java_sp,
1454                              address entry_point,
1455                              Register arg_1,
1456                              bool check_exceptions) {
1457   pass_arg1(this, arg_1);
1458   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1459 }
1460 
1461 void MacroAssembler::call_VM(Register oop_result,
1462                              Register last_java_sp,
1463                              address entry_point,
1464                              Register arg_1,
1465                              Register arg_2,
1466                              bool check_exceptions) {
1467 
1468   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1469   pass_arg2(this, arg_2);
1470   pass_arg1(this, arg_1);
1471   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1472 }
1473 
1474 void MacroAssembler::call_VM(Register oop_result,
1475                              Register last_java_sp,
1476                              address entry_point,
1477                              Register arg_1,
1478                              Register arg_2,
1479                              Register arg_3,
1480                              bool check_exceptions) {
1481   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1482   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1483   pass_arg3(this, arg_3);
1484   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1485   pass_arg2(this, arg_2);
1486   pass_arg1(this, arg_1);
1487   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1488 }
1489 
1490 void MacroAssembler::super_call_VM(Register oop_result,
1491                                    Register last_java_sp,
1492                                    address entry_point,
1493                                    int number_of_arguments,
1494                                    bool check_exceptions) {
1495   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1496   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1497 }
1498 
1499 void MacroAssembler::super_call_VM(Register oop_result,
1500                                    Register last_java_sp,
1501                                    address entry_point,
1502                                    Register arg_1,
1503                                    bool check_exceptions) {
1504   pass_arg1(this, arg_1);
1505   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1506 }
1507 
1508 void MacroAssembler::super_call_VM(Register oop_result,
1509                                    Register last_java_sp,
1510                                    address entry_point,
1511                                    Register arg_1,
1512                                    Register arg_2,
1513                                    bool check_exceptions) {
1514 
1515   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1516   pass_arg2(this, arg_2);
1517   pass_arg1(this, arg_1);
1518   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1519 }
1520 
1521 void MacroAssembler::super_call_VM(Register oop_result,
1522                                    Register last_java_sp,
1523                                    address entry_point,
1524                                    Register arg_1,
1525                                    Register arg_2,
1526                                    Register arg_3,
1527                                    bool check_exceptions) {
1528   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1529   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1530   pass_arg3(this, arg_3);
1531   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1532   pass_arg2(this, arg_2);
1533   pass_arg1(this, arg_1);
1534   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1535 }
1536 
1537 void MacroAssembler::call_VM_base(Register oop_result,
1538                                   Register java_thread,
1539                                   Register last_java_sp,
1540                                   address  entry_point,
1541                                   int      number_of_arguments,
1542                                   bool     check_exceptions) {
1543   // determine java_thread register
1544   if (!java_thread->is_valid()) {
1545 #ifdef _LP64
1546     java_thread = r15_thread;
1547 #else
1548     java_thread = rdi;
1549     get_thread(java_thread);
1550 #endif // LP64
1551   }
1552   // determine last_java_sp register
1553   if (!last_java_sp->is_valid()) {
1554     last_java_sp = rsp;
1555   }
1556   // debugging support
1557   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1558   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1559 #ifdef ASSERT
1560   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1561   // r12 is the heapbase.
1562   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1563 #endif // ASSERT
1564 
1565   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1566   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1567 
1568   // push java thread (becomes first argument of C function)
1569 
1570   NOT_LP64(push(java_thread); number_of_arguments++);
1571   LP64_ONLY(mov(c_rarg0, r15_thread));
1572 
1573   // set last Java frame before call
1574   assert(last_java_sp != rbp, "can't use ebp/rbp");
1575 
1576   // Only interpreter should have to set fp
1577   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1578 
1579   // do the call, remove parameters
1580   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1581 
1582   // restore the thread (cannot use the pushed argument since arguments
1583   // may be overwritten by C code generated by an optimizing compiler);
1584   // however can use the register value directly if it is callee saved.
1585   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1586     // rdi & rsi (also r15) are callee saved -> nothing to do
1587 #ifdef ASSERT
1588     guarantee(java_thread != rax, "change this code");
1589     push(rax);
1590     { Label L;
1591       get_thread(rax);
1592       cmpptr(java_thread, rax);
1593       jcc(Assembler::equal, L);
1594       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1595       bind(L);
1596     }
1597     pop(rax);
1598 #endif
1599   } else {
1600     get_thread(java_thread);
1601   }
1602   // reset last Java frame
1603   // Only interpreter should have to clear fp
1604   reset_last_Java_frame(java_thread, true);
1605 
1606    // C++ interp handles this in the interpreter
1607   check_and_handle_popframe(java_thread);
1608   check_and_handle_earlyret(java_thread);
1609 
1610   if (check_exceptions) {
1611     // check for pending exceptions (java_thread is set upon return)
1612     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1613 #ifndef _LP64
1614     jump_cc(Assembler::notEqual,
1615             RuntimeAddress(StubRoutines::forward_exception_entry()));
1616 #else
1617     // This used to conditionally jump to forward_exception however it is
1618     // possible if we relocate that the branch will not reach. So we must jump
1619     // around so we can always reach
1620 
1621     Label ok;
1622     jcc(Assembler::equal, ok);
1623     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1624     bind(ok);
1625 #endif // LP64
1626   }
1627 
1628   // get oop result if there is one and reset the value in the thread
1629   if (oop_result->is_valid()) {
1630     get_vm_result(oop_result, java_thread);
1631   }
1632 }
1633 
1634 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1635 
1636   // Calculate the value for last_Java_sp
1637   // somewhat subtle. call_VM does an intermediate call
1638   // which places a return address on the stack just under the
1639   // stack pointer as the user finsihed with it. This allows
1640   // use to retrieve last_Java_pc from last_Java_sp[-1].
1641   // On 32bit we then have to push additional args on the stack to accomplish
1642   // the actual requested call. On 64bit call_VM only can use register args
1643   // so the only extra space is the return address that call_VM created.
1644   // This hopefully explains the calculations here.
1645 
1646 #ifdef _LP64
1647   // We've pushed one address, correct last_Java_sp
1648   lea(rax, Address(rsp, wordSize));
1649 #else
1650   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1651 #endif // LP64
1652 
1653   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1654 
1655 }
1656 
1657 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1658 void MacroAssembler::call_VM_leaf0(address entry_point) {
1659   MacroAssembler::call_VM_leaf_base(entry_point, 0);
1660 }
1661 
1662 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1663   call_VM_leaf_base(entry_point, number_of_arguments);
1664 }
1665 
1666 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1667   pass_arg0(this, arg_0);
1668   call_VM_leaf(entry_point, 1);
1669 }
1670 
1671 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1672 
1673   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1674   pass_arg1(this, arg_1);
1675   pass_arg0(this, arg_0);
1676   call_VM_leaf(entry_point, 2);
1677 }
1678 
1679 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1680   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1681   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1682   pass_arg2(this, arg_2);
1683   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1684   pass_arg1(this, arg_1);
1685   pass_arg0(this, arg_0);
1686   call_VM_leaf(entry_point, 3);
1687 }
1688 
1689 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1690   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1691   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1692   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1693   pass_arg3(this, arg_3);
1694   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1695   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1696   pass_arg2(this, arg_2);
1697   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1698   pass_arg1(this, arg_1);
1699   pass_arg0(this, arg_0);
1700   call_VM_leaf(entry_point, 3);
1701 }
1702 
1703 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1704   pass_arg0(this, arg_0);
1705   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1706 }
1707 
1708 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1709 
1710   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1711   pass_arg1(this, arg_1);
1712   pass_arg0(this, arg_0);
1713   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1714 }
1715 
1716 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1717   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1718   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1719   pass_arg2(this, arg_2);
1720   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1721   pass_arg1(this, arg_1);
1722   pass_arg0(this, arg_0);
1723   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1724 }
1725 
1726 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1727   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1728   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1729   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1730   pass_arg3(this, arg_3);
1731   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1732   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1733   pass_arg2(this, arg_2);
1734   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1735   pass_arg1(this, arg_1);
1736   pass_arg0(this, arg_0);
1737   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1738 }
1739 
1740 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1741   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1742   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1743   verify_oop_msg(oop_result, "broken oop in call_VM_base");
1744 }
1745 
1746 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1747   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1748   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1749 }
1750 
1751 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1752 }
1753 
1754 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1755 }
1756 
1757 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1758   if (reachable(src1)) {
1759     cmpl(as_Address(src1), imm);
1760   } else {
1761     lea(rscratch1, src1);
1762     cmpl(Address(rscratch1, 0), imm);
1763   }
1764 }
1765 
1766 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1767   assert(!src2.is_lval(), "use cmpptr");
1768   if (reachable(src2)) {
1769     cmpl(src1, as_Address(src2));
1770   } else {
1771     lea(rscratch1, src2);
1772     cmpl(src1, Address(rscratch1, 0));
1773   }
1774 }
1775 
1776 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1777   Assembler::cmpl(src1, imm);
1778 }
1779 
1780 void MacroAssembler::cmp32(Register src1, Address src2) {
1781   Assembler::cmpl(src1, src2);
1782 }
1783 
1784 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1785   ucomisd(opr1, opr2);
1786 
1787   Label L;
1788   if (unordered_is_less) {
1789     movl(dst, -1);
1790     jcc(Assembler::parity, L);
1791     jcc(Assembler::below , L);
1792     movl(dst, 0);
1793     jcc(Assembler::equal , L);
1794     increment(dst);
1795   } else { // unordered is greater
1796     movl(dst, 1);
1797     jcc(Assembler::parity, L);
1798     jcc(Assembler::above , L);
1799     movl(dst, 0);
1800     jcc(Assembler::equal , L);
1801     decrementl(dst);
1802   }
1803   bind(L);
1804 }
1805 
1806 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1807   ucomiss(opr1, opr2);
1808 
1809   Label L;
1810   if (unordered_is_less) {
1811     movl(dst, -1);
1812     jcc(Assembler::parity, L);
1813     jcc(Assembler::below , L);
1814     movl(dst, 0);
1815     jcc(Assembler::equal , L);
1816     increment(dst);
1817   } else { // unordered is greater
1818     movl(dst, 1);
1819     jcc(Assembler::parity, L);
1820     jcc(Assembler::above , L);
1821     movl(dst, 0);
1822     jcc(Assembler::equal , L);
1823     decrementl(dst);
1824   }
1825   bind(L);
1826 }
1827 
1828 
1829 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1830   if (reachable(src1)) {
1831     cmpb(as_Address(src1), imm);
1832   } else {
1833     lea(rscratch1, src1);
1834     cmpb(Address(rscratch1, 0), imm);
1835   }
1836 }
1837 
1838 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1839 #ifdef _LP64
1840   if (src2.is_lval()) {
1841     movptr(rscratch1, src2);
1842     Assembler::cmpq(src1, rscratch1);
1843   } else if (reachable(src2)) {
1844     cmpq(src1, as_Address(src2));
1845   } else {
1846     lea(rscratch1, src2);
1847     Assembler::cmpq(src1, Address(rscratch1, 0));
1848   }
1849 #else
1850   if (src2.is_lval()) {
1851     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1852   } else {
1853     cmpl(src1, as_Address(src2));
1854   }
1855 #endif // _LP64
1856 }
1857 
1858 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1859   assert(src2.is_lval(), "not a mem-mem compare");
1860 #ifdef _LP64
1861   // moves src2's literal address
1862   movptr(rscratch1, src2);
1863   Assembler::cmpq(src1, rscratch1);
1864 #else
1865   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1866 #endif // _LP64
1867 }
1868 
1869 void MacroAssembler::cmpoop(Register src1, Register src2) {
1870   cmpptr(src1, src2);
1871 }
1872 
1873 void MacroAssembler::cmpoop(Register src1, Address src2) {
1874   cmpptr(src1, src2);
1875 }
1876 
1877 #ifdef _LP64
1878 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1879   movoop(rscratch1, src2);
1880   cmpptr(src1, rscratch1);
1881 }
1882 #endif
1883 
1884 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1885   if (reachable(adr)) {
1886     lock();
1887     cmpxchgptr(reg, as_Address(adr));
1888   } else {
1889     lea(rscratch1, adr);
1890     lock();
1891     cmpxchgptr(reg, Address(rscratch1, 0));
1892   }
1893 }
1894 
1895 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1896   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1897 }
1898 
1899 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1900   if (reachable(src)) {
1901     Assembler::comisd(dst, as_Address(src));
1902   } else {
1903     lea(rscratch1, src);
1904     Assembler::comisd(dst, Address(rscratch1, 0));
1905   }
1906 }
1907 
1908 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1909   if (reachable(src)) {
1910     Assembler::comiss(dst, as_Address(src));
1911   } else {
1912     lea(rscratch1, src);
1913     Assembler::comiss(dst, Address(rscratch1, 0));
1914   }
1915 }
1916 
1917 
1918 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1919   Condition negated_cond = negate_condition(cond);
1920   Label L;
1921   jcc(negated_cond, L);
1922   pushf(); // Preserve flags
1923   atomic_incl(counter_addr);
1924   popf();
1925   bind(L);
1926 }
1927 
1928 int MacroAssembler::corrected_idivl(Register reg) {
1929   // Full implementation of Java idiv and irem; checks for
1930   // special case as described in JVM spec., p.243 & p.271.
1931   // The function returns the (pc) offset of the idivl
1932   // instruction - may be needed for implicit exceptions.
1933   //
1934   //         normal case                           special case
1935   //
1936   // input : rax,: dividend                         min_int
1937   //         reg: divisor   (may not be rax,/rdx)   -1
1938   //
1939   // output: rax,: quotient  (= rax, idiv reg)       min_int
1940   //         rdx: remainder (= rax, irem reg)       0
1941   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1942   const int min_int = 0x80000000;
1943   Label normal_case, special_case;
1944 
1945   // check for special case
1946   cmpl(rax, min_int);
1947   jcc(Assembler::notEqual, normal_case);
1948   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1949   cmpl(reg, -1);
1950   jcc(Assembler::equal, special_case);
1951 
1952   // handle normal case
1953   bind(normal_case);
1954   cdql();
1955   int idivl_offset = offset();
1956   idivl(reg);
1957 
1958   // normal and special case exit
1959   bind(special_case);
1960 
1961   return idivl_offset;
1962 }
1963 
1964 
1965 
1966 void MacroAssembler::decrementl(Register reg, int value) {
1967   if (value == min_jint) {subl(reg, value) ; return; }
1968   if (value <  0) { incrementl(reg, -value); return; }
1969   if (value == 0) {                        ; return; }
1970   if (value == 1 && UseIncDec) { decl(reg) ; return; }
1971   /* else */      { subl(reg, value)       ; return; }
1972 }
1973 
1974 void MacroAssembler::decrementl(Address dst, int value) {
1975   if (value == min_jint) {subl(dst, value) ; return; }
1976   if (value <  0) { incrementl(dst, -value); return; }
1977   if (value == 0) {                        ; return; }
1978   if (value == 1 && UseIncDec) { decl(dst) ; return; }
1979   /* else */      { subl(dst, value)       ; return; }
1980 }
1981 
1982 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1983   assert (shift_value > 0, "illegal shift value");
1984   Label _is_positive;
1985   testl (reg, reg);
1986   jcc (Assembler::positive, _is_positive);
1987   int offset = (1 << shift_value) - 1 ;
1988 
1989   if (offset == 1) {
1990     incrementl(reg);
1991   } else {
1992     addl(reg, offset);
1993   }
1994 
1995   bind (_is_positive);
1996   sarl(reg, shift_value);
1997 }
1998 
1999 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
2000   if (reachable(src)) {
2001     Assembler::divsd(dst, as_Address(src));
2002   } else {
2003     lea(rscratch1, src);
2004     Assembler::divsd(dst, Address(rscratch1, 0));
2005   }
2006 }
2007 
2008 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
2009   if (reachable(src)) {
2010     Assembler::divss(dst, as_Address(src));
2011   } else {
2012     lea(rscratch1, src);
2013     Assembler::divss(dst, Address(rscratch1, 0));
2014   }
2015 }
2016 
2017 void MacroAssembler::enter() {
2018   push(rbp);
2019   mov(rbp, rsp);
2020 }
2021 
2022 void MacroAssembler::post_call_nop() {
2023   emit_int8((int8_t)0x0f);
2024   emit_int8((int8_t)0x1f);
2025   emit_int8((int8_t)0x84);
2026   emit_int8((int8_t)0x00);
2027   emit_int32(0x00);
2028 }
2029 
2030 // A 5 byte nop that is safe for patching (see patch_verified_entry)
2031 void MacroAssembler::fat_nop() {
2032   if (UseAddressNop) {
2033     addr_nop_5();
2034   } else {
2035     emit_int8((int8_t)0x26); // es:
2036     emit_int8((int8_t)0x2e); // cs:
2037     emit_int8((int8_t)0x64); // fs:
2038     emit_int8((int8_t)0x65); // gs:
2039     emit_int8((int8_t)0x90);
2040   }
2041 }
2042 
2043 #ifndef _LP64
2044 void MacroAssembler::fcmp(Register tmp) {
2045   fcmp(tmp, 1, true, true);
2046 }
2047 
2048 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
2049   assert(!pop_right || pop_left, "usage error");
2050   if (VM_Version::supports_cmov()) {
2051     assert(tmp == noreg, "unneeded temp");
2052     if (pop_left) {
2053       fucomip(index);
2054     } else {
2055       fucomi(index);
2056     }
2057     if (pop_right) {
2058       fpop();
2059     }
2060   } else {
2061     assert(tmp != noreg, "need temp");
2062     if (pop_left) {
2063       if (pop_right) {
2064         fcompp();
2065       } else {
2066         fcomp(index);
2067       }
2068     } else {
2069       fcom(index);
2070     }
2071     // convert FPU condition into eflags condition via rax,
2072     save_rax(tmp);
2073     fwait(); fnstsw_ax();
2074     sahf();
2075     restore_rax(tmp);
2076   }
2077   // condition codes set as follows:
2078   //
2079   // CF (corresponds to C0) if x < y
2080   // PF (corresponds to C2) if unordered
2081   // ZF (corresponds to C3) if x = y
2082 }
2083 
2084 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2085   fcmp2int(dst, unordered_is_less, 1, true, true);
2086 }
2087 
2088 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2089   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2090   Label L;
2091   if (unordered_is_less) {
2092     movl(dst, -1);
2093     jcc(Assembler::parity, L);
2094     jcc(Assembler::below , L);
2095     movl(dst, 0);
2096     jcc(Assembler::equal , L);
2097     increment(dst);
2098   } else { // unordered is greater
2099     movl(dst, 1);
2100     jcc(Assembler::parity, L);
2101     jcc(Assembler::above , L);
2102     movl(dst, 0);
2103     jcc(Assembler::equal , L);
2104     decrementl(dst);
2105   }
2106   bind(L);
2107 }
2108 
2109 void MacroAssembler::fld_d(AddressLiteral src) {
2110   fld_d(as_Address(src));
2111 }
2112 
2113 void MacroAssembler::fld_s(AddressLiteral src) {
2114   fld_s(as_Address(src));
2115 }
2116 
2117 void MacroAssembler::fldcw(AddressLiteral src) {
2118   Assembler::fldcw(as_Address(src));
2119 }
2120 
2121 void MacroAssembler::fpop() {
2122   ffree();
2123   fincstp();
2124 }
2125 
2126 void MacroAssembler::fremr(Register tmp) {
2127   save_rax(tmp);
2128   { Label L;
2129     bind(L);
2130     fprem();
2131     fwait(); fnstsw_ax();
2132     sahf();
2133     jcc(Assembler::parity, L);
2134   }
2135   restore_rax(tmp);
2136   // Result is in ST0.
2137   // Note: fxch & fpop to get rid of ST1
2138   // (otherwise FPU stack could overflow eventually)
2139   fxch(1);
2140   fpop();
2141 }
2142 
2143 void MacroAssembler::empty_FPU_stack() {
2144   if (VM_Version::supports_mmx()) {
2145     emms();
2146   } else {
2147     for (int i = 8; i-- > 0; ) ffree(i);
2148   }
2149 }
2150 #endif // !LP64
2151 
2152 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2153   if (reachable(src)) {
2154     Assembler::mulpd(dst, as_Address(src));
2155   } else {
2156     lea(rscratch1, src);
2157     Assembler::mulpd(dst, Address(rscratch1, 0));
2158   }
2159 }
2160 
2161 void MacroAssembler::load_float(Address src) {
2162 #ifdef _LP64
2163   movflt(xmm0, src);
2164 #else
2165   if (UseSSE >= 1) {
2166     movflt(xmm0, src);
2167   } else {
2168     fld_s(src);
2169   }
2170 #endif // LP64
2171 }
2172 
2173 void MacroAssembler::store_float(Address dst) {
2174 #ifdef _LP64
2175   movflt(dst, xmm0);
2176 #else
2177   if (UseSSE >= 1) {
2178     movflt(dst, xmm0);
2179   } else {
2180     fstp_s(dst);
2181   }
2182 #endif // LP64
2183 }
2184 
2185 void MacroAssembler::load_double(Address src) {
2186 #ifdef _LP64
2187   movdbl(xmm0, src);
2188 #else
2189   if (UseSSE >= 2) {
2190     movdbl(xmm0, src);
2191   } else {
2192     fld_d(src);
2193   }
2194 #endif // LP64
2195 }
2196 
2197 void MacroAssembler::store_double(Address dst) {
2198 #ifdef _LP64
2199   movdbl(dst, xmm0);
2200 #else
2201   if (UseSSE >= 2) {
2202     movdbl(dst, xmm0);
2203   } else {
2204     fstp_d(dst);
2205   }
2206 #endif // LP64
2207 }
2208 
2209 // dst = c = a * b + c
2210 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2211   Assembler::vfmadd231sd(c, a, b);
2212   if (dst != c) {
2213     movdbl(dst, c);
2214   }
2215 }
2216 
2217 // dst = c = a * b + c
2218 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2219   Assembler::vfmadd231ss(c, a, b);
2220   if (dst != c) {
2221     movflt(dst, c);
2222   }
2223 }
2224 
2225 // dst = c = a * b + c
2226 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2227   Assembler::vfmadd231pd(c, a, b, vector_len);
2228   if (dst != c) {
2229     vmovdqu(dst, c);
2230   }
2231 }
2232 
2233 // dst = c = a * b + c
2234 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2235   Assembler::vfmadd231ps(c, a, b, vector_len);
2236   if (dst != c) {
2237     vmovdqu(dst, c);
2238   }
2239 }
2240 
2241 // dst = c = a * b + c
2242 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2243   Assembler::vfmadd231pd(c, a, b, vector_len);
2244   if (dst != c) {
2245     vmovdqu(dst, c);
2246   }
2247 }
2248 
2249 // dst = c = a * b + c
2250 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2251   Assembler::vfmadd231ps(c, a, b, vector_len);
2252   if (dst != c) {
2253     vmovdqu(dst, c);
2254   }
2255 }
2256 
2257 void MacroAssembler::incrementl(AddressLiteral dst) {
2258   if (reachable(dst)) {
2259     incrementl(as_Address(dst));
2260   } else {
2261     lea(rscratch1, dst);
2262     incrementl(Address(rscratch1, 0));
2263   }
2264 }
2265 
2266 void MacroAssembler::incrementl(ArrayAddress dst) {
2267   incrementl(as_Address(dst));
2268 }
2269 
2270 void MacroAssembler::incrementl(Register reg, int value) {
2271   if (value == min_jint) {addl(reg, value) ; return; }
2272   if (value <  0) { decrementl(reg, -value); return; }
2273   if (value == 0) {                        ; return; }
2274   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2275   /* else */      { addl(reg, value)       ; return; }
2276 }
2277 
2278 void MacroAssembler::incrementl(Address dst, int value) {
2279   if (value == min_jint) {addl(dst, value) ; return; }
2280   if (value <  0) { decrementl(dst, -value); return; }
2281   if (value == 0) {                        ; return; }
2282   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2283   /* else */      { addl(dst, value)       ; return; }
2284 }
2285 
2286 void MacroAssembler::jump(AddressLiteral dst) {
2287   if (reachable(dst)) {
2288     jmp_literal(dst.target(), dst.rspec());
2289   } else {
2290     lea(rscratch1, dst);
2291     jmp(rscratch1);
2292   }
2293 }
2294 
2295 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2296   if (reachable(dst)) {
2297     InstructionMark im(this);
2298     relocate(dst.reloc());
2299     const int short_size = 2;
2300     const int long_size = 6;
2301     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2302     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2303       // 0111 tttn #8-bit disp
2304       emit_int8(0x70 | cc);
2305       emit_int8((offs - short_size) & 0xFF);
2306     } else {
2307       // 0000 1111 1000 tttn #32-bit disp
2308       emit_int8(0x0F);
2309       emit_int8((unsigned char)(0x80 | cc));
2310       emit_int32(offs - long_size);
2311     }
2312   } else {
2313 #ifdef ASSERT
2314     warning("reversing conditional branch");
2315 #endif /* ASSERT */
2316     Label skip;
2317     jccb(reverse[cc], skip);
2318     lea(rscratch1, dst);
2319     Assembler::jmp(rscratch1);
2320     bind(skip);
2321   }
2322 }
2323 
2324 void MacroAssembler::fld_x(AddressLiteral src) {
2325   Assembler::fld_x(as_Address(src));
2326 }
2327 
2328 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2329   if (reachable(src)) {
2330     Assembler::ldmxcsr(as_Address(src));
2331   } else {
2332     lea(rscratch1, src);
2333     Assembler::ldmxcsr(Address(rscratch1, 0));
2334   }
2335 }
2336 
2337 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2338   int off;
2339   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2340     off = offset();
2341     movsbl(dst, src); // movsxb
2342   } else {
2343     off = load_unsigned_byte(dst, src);
2344     shll(dst, 24);
2345     sarl(dst, 24);
2346   }
2347   return off;
2348 }
2349 
2350 // Note: load_signed_short used to be called load_signed_word.
2351 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2352 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2353 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2354 int MacroAssembler::load_signed_short(Register dst, Address src) {
2355   int off;
2356   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2357     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2358     // version but this is what 64bit has always done. This seems to imply
2359     // that users are only using 32bits worth.
2360     off = offset();
2361     movswl(dst, src); // movsxw
2362   } else {
2363     off = load_unsigned_short(dst, src);
2364     shll(dst, 16);
2365     sarl(dst, 16);
2366   }
2367   return off;
2368 }
2369 
2370 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2371   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2372   // and "3.9 Partial Register Penalties", p. 22).
2373   int off;
2374   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2375     off = offset();
2376     movzbl(dst, src); // movzxb
2377   } else {
2378     xorl(dst, dst);
2379     off = offset();
2380     movb(dst, src);
2381   }
2382   return off;
2383 }
2384 
2385 // Note: load_unsigned_short used to be called load_unsigned_word.
2386 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2387   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2388   // and "3.9 Partial Register Penalties", p. 22).
2389   int off;
2390   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2391     off = offset();
2392     movzwl(dst, src); // movzxw
2393   } else {
2394     xorl(dst, dst);
2395     off = offset();
2396     movw(dst, src);
2397   }
2398   return off;
2399 }
2400 
2401 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2402   switch (size_in_bytes) {
2403 #ifndef _LP64
2404   case  8:
2405     assert(dst2 != noreg, "second dest register required");
2406     movl(dst,  src);
2407     movl(dst2, src.plus_disp(BytesPerInt));
2408     break;
2409 #else
2410   case  8:  movq(dst, src); break;
2411 #endif
2412   case  4:  movl(dst, src); break;
2413   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2414   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2415   default:  ShouldNotReachHere();
2416   }
2417 }
2418 
2419 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2420   switch (size_in_bytes) {
2421 #ifndef _LP64
2422   case  8:
2423     assert(src2 != noreg, "second source register required");
2424     movl(dst,                        src);
2425     movl(dst.plus_disp(BytesPerInt), src2);
2426     break;
2427 #else
2428   case  8:  movq(dst, src); break;
2429 #endif
2430   case  4:  movl(dst, src); break;
2431   case  2:  movw(dst, src); break;
2432   case  1:  movb(dst, src); break;
2433   default:  ShouldNotReachHere();
2434   }
2435 }
2436 
2437 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2438   if (reachable(dst)) {
2439     movl(as_Address(dst), src);
2440   } else {
2441     lea(rscratch1, dst);
2442     movl(Address(rscratch1, 0), src);
2443   }
2444 }
2445 
2446 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2447   if (reachable(src)) {
2448     movl(dst, as_Address(src));
2449   } else {
2450     lea(rscratch1, src);
2451     movl(dst, Address(rscratch1, 0));
2452   }
2453 }
2454 
2455 // C++ bool manipulation
2456 
2457 void MacroAssembler::movbool(Register dst, Address src) {
2458   if(sizeof(bool) == 1)
2459     movb(dst, src);
2460   else if(sizeof(bool) == 2)
2461     movw(dst, src);
2462   else if(sizeof(bool) == 4)
2463     movl(dst, src);
2464   else
2465     // unsupported
2466     ShouldNotReachHere();
2467 }
2468 
2469 void MacroAssembler::movbool(Address dst, bool boolconst) {
2470   if(sizeof(bool) == 1)
2471     movb(dst, (int) boolconst);
2472   else if(sizeof(bool) == 2)
2473     movw(dst, (int) boolconst);
2474   else if(sizeof(bool) == 4)
2475     movl(dst, (int) boolconst);
2476   else
2477     // unsupported
2478     ShouldNotReachHere();
2479 }
2480 
2481 void MacroAssembler::movbool(Address dst, Register src) {
2482   if(sizeof(bool) == 1)
2483     movb(dst, src);
2484   else if(sizeof(bool) == 2)
2485     movw(dst, src);
2486   else if(sizeof(bool) == 4)
2487     movl(dst, src);
2488   else
2489     // unsupported
2490     ShouldNotReachHere();
2491 }
2492 
2493 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2494   movb(as_Address(dst), src);
2495 }
2496 
2497 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2498   if (reachable(src)) {
2499     movdl(dst, as_Address(src));
2500   } else {
2501     lea(rscratch1, src);
2502     movdl(dst, Address(rscratch1, 0));
2503   }
2504 }
2505 
2506 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2507   if (reachable(src)) {
2508     movq(dst, as_Address(src));
2509   } else {
2510     lea(rscratch1, src);
2511     movq(dst, Address(rscratch1, 0));
2512   }
2513 }
2514 
2515 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2516   if (reachable(src)) {
2517     if (UseXmmLoadAndClearUpper) {
2518       movsd (dst, as_Address(src));
2519     } else {
2520       movlpd(dst, as_Address(src));
2521     }
2522   } else {
2523     lea(rscratch1, src);
2524     if (UseXmmLoadAndClearUpper) {
2525       movsd (dst, Address(rscratch1, 0));
2526     } else {
2527       movlpd(dst, Address(rscratch1, 0));
2528     }
2529   }
2530 }
2531 
2532 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2533   if (reachable(src)) {
2534     movss(dst, as_Address(src));
2535   } else {
2536     lea(rscratch1, src);
2537     movss(dst, Address(rscratch1, 0));
2538   }
2539 }
2540 
2541 void MacroAssembler::movptr(Register dst, Register src) {
2542   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2543 }
2544 
2545 void MacroAssembler::movptr(Register dst, Address src) {
2546   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2547 }
2548 
2549 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2550 void MacroAssembler::movptr(Register dst, intptr_t src) {
2551   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2552 }
2553 
2554 void MacroAssembler::movptr(Address dst, Register src) {
2555   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2556 }
2557 
2558 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2559     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2560     Assembler::movdqu(dst, src);
2561 }
2562 
2563 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2564     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2565     Assembler::movdqu(dst, src);
2566 }
2567 
2568 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2569     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2570     Assembler::movdqu(dst, src);
2571 }
2572 
2573 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2574   if (reachable(src)) {
2575     movdqu(dst, as_Address(src));
2576   } else {
2577     lea(scratchReg, src);
2578     movdqu(dst, Address(scratchReg, 0));
2579   }
2580 }
2581 
2582 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2583     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2584     Assembler::vmovdqu(dst, src);
2585 }
2586 
2587 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2588     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2589     Assembler::vmovdqu(dst, src);
2590 }
2591 
2592 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2593     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2594     Assembler::vmovdqu(dst, src);
2595 }
2596 
2597 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2598   if (reachable(src)) {
2599     vmovdqu(dst, as_Address(src));
2600   }
2601   else {
2602     lea(scratch_reg, src);
2603     vmovdqu(dst, Address(scratch_reg, 0));
2604   }
2605 }
2606 
2607 void MacroAssembler::kmov(KRegister dst, Address src) {
2608   if (VM_Version::supports_avx512bw()) {
2609     kmovql(dst, src);
2610   } else {
2611     assert(VM_Version::supports_evex(), "");
2612     kmovwl(dst, src);
2613   }
2614 }
2615 
2616 void MacroAssembler::kmov(Address dst, KRegister src) {
2617   if (VM_Version::supports_avx512bw()) {
2618     kmovql(dst, src);
2619   } else {
2620     assert(VM_Version::supports_evex(), "");
2621     kmovwl(dst, src);
2622   }
2623 }
2624 
2625 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2626   if (VM_Version::supports_avx512bw()) {
2627     kmovql(dst, src);
2628   } else {
2629     assert(VM_Version::supports_evex(), "");
2630     kmovwl(dst, src);
2631   }
2632 }
2633 
2634 void MacroAssembler::kmov(Register dst, KRegister src) {
2635   if (VM_Version::supports_avx512bw()) {
2636     kmovql(dst, src);
2637   } else {
2638     assert(VM_Version::supports_evex(), "");
2639     kmovwl(dst, src);
2640   }
2641 }
2642 
2643 void MacroAssembler::kmov(KRegister dst, Register src) {
2644   if (VM_Version::supports_avx512bw()) {
2645     kmovql(dst, src);
2646   } else {
2647     assert(VM_Version::supports_evex(), "");
2648     kmovwl(dst, src);
2649   }
2650 }
2651 
2652 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2653   if (reachable(src)) {
2654     kmovql(dst, as_Address(src));
2655   } else {
2656     lea(scratch_reg, src);
2657     kmovql(dst, Address(scratch_reg, 0));
2658   }
2659 }
2660 
2661 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2662   if (reachable(src)) {
2663     kmovwl(dst, as_Address(src));
2664   } else {
2665     lea(scratch_reg, src);
2666     kmovwl(dst, Address(scratch_reg, 0));
2667   }
2668 }
2669 
2670 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2671                                int vector_len, Register scratch_reg) {
2672   if (reachable(src)) {
2673     if (mask == k0) {
2674       Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2675     } else {
2676       Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2677     }
2678   } else {
2679     lea(scratch_reg, src);
2680     if (mask == k0) {
2681       Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2682     } else {
2683       Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2684     }
2685   }
2686 }
2687 
2688 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2689                                int vector_len, Register scratch_reg) {
2690   if (reachable(src)) {
2691     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2692   } else {
2693     lea(scratch_reg, src);
2694     Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2695   }
2696 }
2697 
2698 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2699                                int vector_len, Register scratch_reg) {
2700   if (reachable(src)) {
2701     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2702   } else {
2703     lea(scratch_reg, src);
2704     Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2705   }
2706 }
2707 
2708 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2709                                int vector_len, Register scratch_reg) {
2710   if (reachable(src)) {
2711     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2712   } else {
2713     lea(scratch_reg, src);
2714     Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2715   }
2716 }
2717 
2718 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2719   if (reachable(src)) {
2720     Assembler::evmovdquq(dst, as_Address(src), vector_len);
2721   } else {
2722     lea(rscratch, src);
2723     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2724   }
2725 }
2726 
2727 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2728   if (reachable(src)) {
2729     Assembler::movdqa(dst, as_Address(src));
2730   } else {
2731     lea(rscratch1, src);
2732     Assembler::movdqa(dst, Address(rscratch1, 0));
2733   }
2734 }
2735 
2736 #ifdef _LP64
2737   // Move Aligned, possibly non-temporal
2738   void MacroAssembler::movqa(Address dst, Register src, bool nt) {
2739     if (nt) {
2740       Assembler::movntq(dst, src);
2741     } else {
2742       Assembler::movq(dst, src);
2743     }
2744   }
2745 
2746   void MacroAssembler::movdqa(Address dst, XMMRegister src, bool nt) {
2747     if (nt) {
2748       Assembler::movntdq(dst, src);
2749     } else {
2750       Assembler::movdqu(dst, src);
2751     }
2752   }
2753   void MacroAssembler::vmovdqa(Address dst, XMMRegister src, bool nt) {
2754     if (nt) {
2755       Assembler::vmovntdq(dst, src);
2756     } else {
2757       Assembler::vmovdqu(dst, src);
2758     }
2759   }
2760   void MacroAssembler::evmovdqa(Address dst, XMMRegister src, int vector_len, bool nt) {
2761     if (nt) {
2762       Assembler::evmovntdq(dst, src, vector_len);
2763     } else {
2764       Assembler::evmovdqal(dst, src, vector_len);
2765     }
2766   }
2767 
2768   void MacroAssembler::movdqa(XMMRegister dst, Address src, bool nt) {
2769     if (nt) {
2770       Assembler::movntdqa(dst, src);
2771     } else {
2772       Assembler::movdqu(dst, src); // use unaligned load
2773     }
2774   }
2775   void MacroAssembler::vmovdqa(XMMRegister dst, Address src, bool nt) {
2776     if (nt) {
2777       Assembler::vmovntdqa(dst, src);
2778     } else {
2779       Assembler::vmovdqu(dst, src); // use unaligned load
2780     }
2781   }
2782   void MacroAssembler::evmovdqa(XMMRegister dst, Address src, int vector_len, bool nt) {
2783     if (nt) {
2784       Assembler::evmovntdqa(dst, src, vector_len);
2785     } else {
2786       Assembler::evmovdqul(dst, src, vector_len); // use unaligned load
2787     }
2788   }
2789 #endif
2790 
2791 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2792   if (reachable(src)) {
2793     Assembler::movsd(dst, as_Address(src));
2794   } else {
2795     lea(rscratch1, src);
2796     Assembler::movsd(dst, Address(rscratch1, 0));
2797   }
2798 }
2799 
2800 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2801   if (reachable(src)) {
2802     Assembler::movss(dst, as_Address(src));
2803   } else {
2804     lea(rscratch1, src);
2805     Assembler::movss(dst, Address(rscratch1, 0));
2806   }
2807 }
2808 
2809 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2810   if (reachable(src)) {
2811     Assembler::mulsd(dst, as_Address(src));
2812   } else {
2813     lea(rscratch1, src);
2814     Assembler::mulsd(dst, Address(rscratch1, 0));
2815   }
2816 }
2817 
2818 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2819   if (reachable(src)) {
2820     Assembler::mulss(dst, as_Address(src));
2821   } else {
2822     lea(rscratch1, src);
2823     Assembler::mulss(dst, Address(rscratch1, 0));
2824   }
2825 }
2826 
2827 void MacroAssembler::null_check(Register reg, int offset) {
2828   if (needs_explicit_null_check(offset)) {
2829     // provoke OS NULL exception if reg = NULL by
2830     // accessing M[reg] w/o changing any (non-CC) registers
2831     // NOTE: cmpl is plenty here to provoke a segv
2832     cmpptr(rax, Address(reg, 0));
2833     // Note: should probably use testl(rax, Address(reg, 0));
2834     //       may be shorter code (however, this version of
2835     //       testl needs to be implemented first)
2836   } else {
2837     // nothing to do, (later) access of M[reg + offset]
2838     // will provoke OS NULL exception if reg = NULL
2839   }
2840 }
2841 
2842 void MacroAssembler::os_breakpoint() {
2843   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2844   // (e.g., MSVC can't call ps() otherwise)
2845   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2846 }
2847 
2848 void MacroAssembler::unimplemented(const char* what) {
2849   const char* buf = NULL;
2850   {
2851     ResourceMark rm;
2852     stringStream ss;
2853     ss.print("unimplemented: %s", what);
2854     buf = code_string(ss.as_string());
2855   }
2856   stop(buf);
2857 }
2858 
2859 #ifdef _LP64
2860 #define XSTATE_BV 0x200
2861 #endif
2862 
2863 void MacroAssembler::pop_CPU_state() {
2864   pop_FPU_state();
2865   pop_IU_state();
2866 }
2867 
2868 void MacroAssembler::pop_FPU_state() {
2869 #ifndef _LP64
2870   frstor(Address(rsp, 0));
2871 #else
2872   fxrstor(Address(rsp, 0));
2873 #endif
2874   addptr(rsp, FPUStateSizeInWords * wordSize);
2875 }
2876 
2877 void MacroAssembler::pop_IU_state() {
2878   popa();
2879   LP64_ONLY(addq(rsp, 8));
2880   popf();
2881 }
2882 
2883 // Save Integer and Float state
2884 // Warning: Stack must be 16 byte aligned (64bit)
2885 void MacroAssembler::push_CPU_state() {
2886   push_IU_state();
2887   push_FPU_state();
2888 }
2889 
2890 void MacroAssembler::push_FPU_state() {
2891   subptr(rsp, FPUStateSizeInWords * wordSize);
2892 #ifndef _LP64
2893   fnsave(Address(rsp, 0));
2894   fwait();
2895 #else
2896   fxsave(Address(rsp, 0));
2897 #endif // LP64
2898 }
2899 
2900 void MacroAssembler::push_IU_state() {
2901   // Push flags first because pusha kills them
2902   pushf();
2903   // Make sure rsp stays 16-byte aligned
2904   LP64_ONLY(subq(rsp, 8));
2905   pusha();
2906 }
2907 
2908 void MacroAssembler::push_cont_fastpath(Register java_thread) {
2909   Label done;
2910   cmpptr(rsp, Address(java_thread, JavaThread::cont_fastpath_offset()));
2911   jccb(Assembler::belowEqual, done);
2912   movptr(Address(java_thread, JavaThread::cont_fastpath_offset()), rsp);
2913   bind(done);
2914 }
2915 
2916 void MacroAssembler::pop_cont_fastpath(Register java_thread) {
2917   Label done;
2918   cmpptr(rsp, Address(java_thread, JavaThread::cont_fastpath_offset()));
2919   jccb(Assembler::below, done);
2920   movptr(Address(java_thread, JavaThread::cont_fastpath_offset()), 0);
2921   bind(done);
2922 }
2923 
2924 void MacroAssembler::inc_held_monitor_count(Register java_thread) {
2925   incrementl(Address(java_thread, JavaThread::held_monitor_count_offset()));
2926 }
2927 
2928 void MacroAssembler::dec_held_monitor_count(Register java_thread) {
2929   decrementl(Address(java_thread, JavaThread::held_monitor_count_offset()));
2930 }
2931 
2932 void MacroAssembler::reset_held_monitor_count(Register java_thread) {
2933   movl(Address(java_thread, JavaThread::held_monitor_count_offset()), (int32_t)0);
2934 }
2935 
2936 #ifdef ASSERT
2937 void MacroAssembler::stop_if_in_cont(Register cont, const char* name) {
2938 #ifdef _LP64
2939   Label no_cont;
2940   movptr(cont, Address(r15_thread, JavaThread::cont_entry_offset()));
2941   testl(cont, cont);
2942   jcc(Assembler::zero, no_cont);
2943   stop(name);
2944   bind(no_cont);
2945 #else
2946   Unimplemented();
2947 #endif
2948 }
2949 #endif
2950 
2951 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2952   if (!java_thread->is_valid()) {
2953     java_thread = rdi;
2954     get_thread(java_thread);
2955   }
2956   // we must set sp to zero to clear frame
2957   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2958   // must clear fp, so that compiled frames are not confused; it is
2959   // possible that we need it only for debugging
2960   if (clear_fp) {
2961     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2962   }
2963   // Always clear the pc because it could have been set by make_walkable()
2964   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2965   vzeroupper();
2966 }
2967 
2968 void MacroAssembler::restore_rax(Register tmp) {
2969   if (tmp == noreg) pop(rax);
2970   else if (tmp != rax) mov(rax, tmp);
2971 }
2972 
2973 void MacroAssembler::round_to(Register reg, int modulus) {
2974   addptr(reg, modulus - 1);
2975   andptr(reg, -modulus);
2976 }
2977 
2978 void MacroAssembler::save_rax(Register tmp) {
2979   if (tmp == noreg) push(rax);
2980   else if (tmp != rax) mov(tmp, rax);
2981 }
2982 
2983 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2984   if (at_return) {
2985     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2986     // we may safely use rsp instead to perform the stack watermark check.
2987     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2988     jcc(Assembler::above, slow_path);
2989     return;
2990   }
2991   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2992   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2993 }
2994 
2995 // Calls to C land
2996 //
2997 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2998 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2999 // has to be reset to 0. This is required to allow proper stack traversal.
3000 void MacroAssembler::set_last_Java_frame(Register java_thread,
3001                                          Register last_java_sp,
3002                                          Register last_java_fp,
3003                                          address  last_java_pc) {
3004   vzeroupper();
3005   // determine java_thread register
3006   if (!java_thread->is_valid()) {
3007     java_thread = rdi;
3008     get_thread(java_thread);
3009   }
3010   // determine last_java_sp register
3011   if (!last_java_sp->is_valid()) {
3012     last_java_sp = rsp;
3013   }
3014 
3015   // last_java_fp is optional
3016 
3017   if (last_java_fp->is_valid()) {
3018     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
3019   }
3020 
3021   // last_java_pc is optional
3022 
3023   if (last_java_pc != NULL) {
3024     lea(Address(java_thread,
3025                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
3026         InternalAddress(last_java_pc));
3027 
3028   }
3029   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
3030 }
3031 
3032 void MacroAssembler::shlptr(Register dst, int imm8) {
3033   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
3034 }
3035 
3036 void MacroAssembler::shrptr(Register dst, int imm8) {
3037   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
3038 }
3039 
3040 void MacroAssembler::sign_extend_byte(Register reg) {
3041   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
3042     movsbl(reg, reg); // movsxb
3043   } else {
3044     shll(reg, 24);
3045     sarl(reg, 24);
3046   }
3047 }
3048 
3049 void MacroAssembler::sign_extend_short(Register reg) {
3050   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
3051     movswl(reg, reg); // movsxw
3052   } else {
3053     shll(reg, 16);
3054     sarl(reg, 16);
3055   }
3056 }
3057 
3058 void MacroAssembler::testl(Register dst, AddressLiteral src) {
3059   assert(reachable(src), "Address should be reachable");
3060   testl(dst, as_Address(src));
3061 }
3062 
3063 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3064   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3065   Assembler::pcmpeqb(dst, src);
3066 }
3067 
3068 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3069   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3070   Assembler::pcmpeqw(dst, src);
3071 }
3072 
3073 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3074   assert((dst->encoding() < 16),"XMM register should be 0-15");
3075   Assembler::pcmpestri(dst, src, imm8);
3076 }
3077 
3078 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3079   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3080   Assembler::pcmpestri(dst, src, imm8);
3081 }
3082 
3083 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
3084   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3085   Assembler::pmovzxbw(dst, src);
3086 }
3087 
3088 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
3089   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3090   Assembler::pmovzxbw(dst, src);
3091 }
3092 
3093 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
3094   assert((src->encoding() < 16),"XMM register should be 0-15");
3095   Assembler::pmovmskb(dst, src);
3096 }
3097 
3098 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
3099   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3100   Assembler::ptest(dst, src);
3101 }
3102 
3103 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
3104   if (reachable(src)) {
3105     Assembler::sqrtsd(dst, as_Address(src));
3106   } else {
3107     lea(rscratch1, src);
3108     Assembler::sqrtsd(dst, Address(rscratch1, 0));
3109   }
3110 }
3111 
3112 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
3113   if (reachable(src)) {
3114     Assembler::sqrtss(dst, as_Address(src));
3115   } else {
3116     lea(rscratch1, src);
3117     Assembler::sqrtss(dst, Address(rscratch1, 0));
3118   }
3119 }
3120 
3121 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
3122   if (reachable(src)) {
3123     Assembler::subsd(dst, as_Address(src));
3124   } else {
3125     lea(rscratch1, src);
3126     Assembler::subsd(dst, Address(rscratch1, 0));
3127   }
3128 }
3129 
3130 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
3131   if (reachable(src)) {
3132     Assembler::roundsd(dst, as_Address(src), rmode);
3133   } else {
3134     lea(scratch_reg, src);
3135     Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
3136   }
3137 }
3138 
3139 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
3140   if (reachable(src)) {
3141     Assembler::subss(dst, as_Address(src));
3142   } else {
3143     lea(rscratch1, src);
3144     Assembler::subss(dst, Address(rscratch1, 0));
3145   }
3146 }
3147 
3148 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
3149   if (reachable(src)) {
3150     Assembler::ucomisd(dst, as_Address(src));
3151   } else {
3152     lea(rscratch1, src);
3153     Assembler::ucomisd(dst, Address(rscratch1, 0));
3154   }
3155 }
3156 
3157 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3158   if (reachable(src)) {
3159     Assembler::ucomiss(dst, as_Address(src));
3160   } else {
3161     lea(rscratch1, src);
3162     Assembler::ucomiss(dst, Address(rscratch1, 0));
3163   }
3164 }
3165 
3166 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3167   // Used in sign-bit flipping with aligned address.
3168   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3169   if (reachable(src)) {
3170     Assembler::xorpd(dst, as_Address(src));
3171   } else {
3172     lea(scratch_reg, src);
3173     Assembler::xorpd(dst, Address(scratch_reg, 0));
3174   }
3175 }
3176 
3177 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3178   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3179     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3180   }
3181   else {
3182     Assembler::xorpd(dst, src);
3183   }
3184 }
3185 
3186 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3187   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3188     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3189   } else {
3190     Assembler::xorps(dst, src);
3191   }
3192 }
3193 
3194 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3195   // Used in sign-bit flipping with aligned address.
3196   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3197   if (reachable(src)) {
3198     Assembler::xorps(dst, as_Address(src));
3199   } else {
3200     lea(scratch_reg, src);
3201     Assembler::xorps(dst, Address(scratch_reg, 0));
3202   }
3203 }
3204 
3205 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3206   // Used in sign-bit flipping with aligned address.
3207   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3208   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3209   if (reachable(src)) {
3210     Assembler::pshufb(dst, as_Address(src));
3211   } else {
3212     lea(rscratch1, src);
3213     Assembler::pshufb(dst, Address(rscratch1, 0));
3214   }
3215 }
3216 
3217 // AVX 3-operands instructions
3218 
3219 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3220   if (reachable(src)) {
3221     vaddsd(dst, nds, as_Address(src));
3222   } else {
3223     lea(rscratch1, src);
3224     vaddsd(dst, nds, Address(rscratch1, 0));
3225   }
3226 }
3227 
3228 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3229   if (reachable(src)) {
3230     vaddss(dst, nds, as_Address(src));
3231   } else {
3232     lea(rscratch1, src);
3233     vaddss(dst, nds, Address(rscratch1, 0));
3234   }
3235 }
3236 
3237 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3238   assert(UseAVX > 0, "requires some form of AVX");
3239   if (reachable(src)) {
3240     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3241   } else {
3242     lea(rscratch, src);
3243     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3244   }
3245 }
3246 
3247 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3248   assert(UseAVX > 0, "requires some form of AVX");
3249   if (reachable(src)) {
3250     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3251   } else {
3252     lea(rscratch, src);
3253     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3254   }
3255 }
3256 
3257 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3258   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3259   vandps(dst, nds, negate_field, vector_len);
3260 }
3261 
3262 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3263   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3264   vandpd(dst, nds, negate_field, vector_len);
3265 }
3266 
3267 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3268   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3269   Assembler::vpaddb(dst, nds, src, vector_len);
3270 }
3271 
3272 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3273   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3274   Assembler::vpaddb(dst, nds, src, vector_len);
3275 }
3276 
3277 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3278   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3279   Assembler::vpaddw(dst, nds, src, vector_len);
3280 }
3281 
3282 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3283   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3284   Assembler::vpaddw(dst, nds, src, vector_len);
3285 }
3286 
3287 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3288   if (reachable(src)) {
3289     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3290   } else {
3291     lea(scratch_reg, src);
3292     Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3293   }
3294 }
3295 
3296 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3297   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3298   Assembler::vpbroadcastw(dst, src, vector_len);
3299 }
3300 
3301 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3302   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3303   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3304 }
3305 
3306 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3307   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3308   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3309 }
3310 
3311 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3312                                AddressLiteral src, int vector_len, Register scratch_reg) {
3313   if (reachable(src)) {
3314     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3315   } else {
3316     lea(scratch_reg, src);
3317     Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3318   }
3319 }
3320 
3321 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3322                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3323   if (reachable(src)) {
3324     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3325   } else {
3326     lea(scratch_reg, src);
3327     Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3328   }
3329 }
3330 
3331 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3332                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3333   if (reachable(src)) {
3334     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3335   } else {
3336     lea(scratch_reg, src);
3337     Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3338   }
3339 }
3340 
3341 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3342                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3343   if (reachable(src)) {
3344     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3345   } else {
3346     lea(scratch_reg, src);
3347     Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3348   }
3349 }
3350 
3351 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3352                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3353   if (reachable(src)) {
3354     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3355   } else {
3356     lea(scratch_reg, src);
3357     Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3358   }
3359 }
3360 
3361 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3362   if (width == Assembler::Q) {
3363     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3364   } else {
3365     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3366   }
3367 }
3368 
3369 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg) {
3370   int eq_cond_enc = 0x29;
3371   int gt_cond_enc = 0x37;
3372   if (width != Assembler::Q) {
3373     eq_cond_enc = 0x74 + width;
3374     gt_cond_enc = 0x64 + width;
3375   }
3376   switch (cond) {
3377   case eq:
3378     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3379     break;
3380   case neq:
3381     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3382     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3383     break;
3384   case le:
3385     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3386     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3387     break;
3388   case nlt:
3389     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3390     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3391     break;
3392   case lt:
3393     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3394     break;
3395   case nle:
3396     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3397     break;
3398   default:
3399     assert(false, "Should not reach here");
3400   }
3401 }
3402 
3403 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3404   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3405   Assembler::vpmovzxbw(dst, src, vector_len);
3406 }
3407 
3408 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3409   assert((src->encoding() < 16),"XMM register should be 0-15");
3410   Assembler::vpmovmskb(dst, src, vector_len);
3411 }
3412 
3413 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3414   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3415   Assembler::vpmullw(dst, nds, src, vector_len);
3416 }
3417 
3418 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3419   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3420   Assembler::vpmullw(dst, nds, src, vector_len);
3421 }
3422 
3423 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3424   assert((UseAVX > 0), "AVX support is needed");
3425   if (reachable(src)) {
3426     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3427   } else {
3428     lea(scratch_reg, src);
3429     Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3430   }
3431 }
3432 
3433 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3434   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3435   Assembler::vpsubb(dst, nds, src, vector_len);
3436 }
3437 
3438 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3439   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3440   Assembler::vpsubb(dst, nds, src, vector_len);
3441 }
3442 
3443 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3444   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3445   Assembler::vpsubw(dst, nds, src, vector_len);
3446 }
3447 
3448 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3449   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3450   Assembler::vpsubw(dst, nds, src, vector_len);
3451 }
3452 
3453 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3454   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3455   Assembler::vpsraw(dst, nds, shift, vector_len);
3456 }
3457 
3458 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3459   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3460   Assembler::vpsraw(dst, nds, shift, vector_len);
3461 }
3462 
3463 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3464   assert(UseAVX > 2,"");
3465   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3466      vector_len = 2;
3467   }
3468   Assembler::evpsraq(dst, nds, shift, vector_len);
3469 }
3470 
3471 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3472   assert(UseAVX > 2,"");
3473   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3474      vector_len = 2;
3475   }
3476   Assembler::evpsraq(dst, nds, shift, vector_len);
3477 }
3478 
3479 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3480   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3481   Assembler::vpsrlw(dst, nds, shift, vector_len);
3482 }
3483 
3484 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3485   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3486   Assembler::vpsrlw(dst, nds, shift, vector_len);
3487 }
3488 
3489 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3490   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3491   Assembler::vpsllw(dst, nds, shift, vector_len);
3492 }
3493 
3494 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3495   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3496   Assembler::vpsllw(dst, nds, shift, vector_len);
3497 }
3498 
3499 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3500   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3501   Assembler::vptest(dst, src);
3502 }
3503 
3504 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3505   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3506   Assembler::punpcklbw(dst, src);
3507 }
3508 
3509 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3510   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3511   Assembler::pshufd(dst, src, mode);
3512 }
3513 
3514 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3515   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3516   Assembler::pshuflw(dst, src, mode);
3517 }
3518 
3519 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3520   if (reachable(src)) {
3521     vandpd(dst, nds, as_Address(src), vector_len);
3522   } else {
3523     lea(scratch_reg, src);
3524     vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3525   }
3526 }
3527 
3528 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3529   if (reachable(src)) {
3530     vandps(dst, nds, as_Address(src), vector_len);
3531   } else {
3532     lea(scratch_reg, src);
3533     vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3534   }
3535 }
3536 
3537 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3538                             bool merge, int vector_len, Register scratch_reg) {
3539   if (reachable(src)) {
3540     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3541   } else {
3542     lea(scratch_reg, src);
3543     Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3544   }
3545 }
3546 
3547 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3548   if (reachable(src)) {
3549     vdivsd(dst, nds, as_Address(src));
3550   } else {
3551     lea(rscratch1, src);
3552     vdivsd(dst, nds, Address(rscratch1, 0));
3553   }
3554 }
3555 
3556 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3557   if (reachable(src)) {
3558     vdivss(dst, nds, as_Address(src));
3559   } else {
3560     lea(rscratch1, src);
3561     vdivss(dst, nds, Address(rscratch1, 0));
3562   }
3563 }
3564 
3565 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3566   if (reachable(src)) {
3567     vmulsd(dst, nds, as_Address(src));
3568   } else {
3569     lea(rscratch1, src);
3570     vmulsd(dst, nds, Address(rscratch1, 0));
3571   }
3572 }
3573 
3574 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3575   if (reachable(src)) {
3576     vmulss(dst, nds, as_Address(src));
3577   } else {
3578     lea(rscratch1, src);
3579     vmulss(dst, nds, Address(rscratch1, 0));
3580   }
3581 }
3582 
3583 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3584   if (reachable(src)) {
3585     vsubsd(dst, nds, as_Address(src));
3586   } else {
3587     lea(rscratch1, src);
3588     vsubsd(dst, nds, Address(rscratch1, 0));
3589   }
3590 }
3591 
3592 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3593   if (reachable(src)) {
3594     vsubss(dst, nds, as_Address(src));
3595   } else {
3596     lea(rscratch1, src);
3597     vsubss(dst, nds, Address(rscratch1, 0));
3598   }
3599 }
3600 
3601 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3602   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3603   vxorps(dst, nds, src, Assembler::AVX_128bit);
3604 }
3605 
3606 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3607   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3608   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3609 }
3610 
3611 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3612   if (reachable(src)) {
3613     vxorpd(dst, nds, as_Address(src), vector_len);
3614   } else {
3615     lea(scratch_reg, src);
3616     vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3617   }
3618 }
3619 
3620 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3621   if (reachable(src)) {
3622     vxorps(dst, nds, as_Address(src), vector_len);
3623   } else {
3624     lea(scratch_reg, src);
3625     vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3626   }
3627 }
3628 
3629 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3630   if (UseAVX > 1 || (vector_len < 1)) {
3631     if (reachable(src)) {
3632       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3633     } else {
3634       lea(scratch_reg, src);
3635       Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3636     }
3637   }
3638   else {
3639     MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3640   }
3641 }
3642 
3643 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3644   if (reachable(src)) {
3645     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3646   } else {
3647     lea(scratch_reg, src);
3648     Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3649   }
3650 }
3651 
3652 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3653   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3654   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3655   // The inverted mask is sign-extended
3656   andptr(possibly_jweak, inverted_jweak_mask);
3657 }
3658 
3659 void MacroAssembler::resolve_jobject(Register value,
3660                                      Register thread,
3661                                      Register tmp) {
3662   assert_different_registers(value, thread, tmp);
3663   Label done, not_weak;
3664   testptr(value, value);
3665   jcc(Assembler::zero, done);                // Use NULL as-is.
3666   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3667   jcc(Assembler::zero, not_weak);
3668   // Resolve jweak.
3669   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3670                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3671   verify_oop(value);
3672   jmp(done);
3673   bind(not_weak);
3674   // Resolve (untagged) jobject.
3675   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3676   verify_oop(value);
3677   bind(done);
3678 }
3679 
3680 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3681   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3682 }
3683 
3684 // Force generation of a 4 byte immediate value even if it fits into 8bit
3685 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3686   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3687 }
3688 
3689 void MacroAssembler::subptr(Register dst, Register src) {
3690   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3691 }
3692 
3693 // C++ bool manipulation
3694 void MacroAssembler::testbool(Register dst) {
3695   if(sizeof(bool) == 1)
3696     testb(dst, 0xff);
3697   else if(sizeof(bool) == 2) {
3698     // testw implementation needed for two byte bools
3699     ShouldNotReachHere();
3700   } else if(sizeof(bool) == 4)
3701     testl(dst, dst);
3702   else
3703     // unsupported
3704     ShouldNotReachHere();
3705 }
3706 
3707 void MacroAssembler::testptr(Register dst, Register src) {
3708   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3709 }
3710 
3711 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3712 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3713                                    Register var_size_in_bytes,
3714                                    int con_size_in_bytes,
3715                                    Register t1,
3716                                    Register t2,
3717                                    Label& slow_case) {
3718   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3719   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3720 }
3721 
3722 // Defines obj, preserves var_size_in_bytes
3723 void MacroAssembler::eden_allocate(Register thread, Register obj,
3724                                    Register var_size_in_bytes,
3725                                    int con_size_in_bytes,
3726                                    Register t1,
3727                                    Label& slow_case) {
3728   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3729   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3730 }
3731 
3732 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3733 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3734   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3735   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3736   Label done;
3737 
3738   testptr(length_in_bytes, length_in_bytes);
3739   jcc(Assembler::zero, done);
3740 
3741   // initialize topmost word, divide index by 2, check if odd and test if zero
3742   // note: for the remaining code to work, index must be a multiple of BytesPerWord
3743 #ifdef ASSERT
3744   {
3745     Label L;
3746     testptr(length_in_bytes, BytesPerWord - 1);
3747     jcc(Assembler::zero, L);
3748     stop("length must be a multiple of BytesPerWord");
3749     bind(L);
3750   }
3751 #endif
3752   Register index = length_in_bytes;
3753   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
3754   if (UseIncDec) {
3755     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
3756   } else {
3757     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
3758     shrptr(index, 1);
3759   }
3760 #ifndef _LP64
3761   // index could have not been a multiple of 8 (i.e., bit 2 was set)
3762   {
3763     Label even;
3764     // note: if index was a multiple of 8, then it cannot
3765     //       be 0 now otherwise it must have been 0 before
3766     //       => if it is even, we don't need to check for 0 again
3767     jcc(Assembler::carryClear, even);
3768     // clear topmost word (no jump would be needed if conditional assignment worked here)
3769     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3770     // index could be 0 now, must check again
3771     jcc(Assembler::zero, done);
3772     bind(even);
3773   }
3774 #endif // !_LP64
3775   // initialize remaining object fields: index is a multiple of 2 now
3776   {
3777     Label loop;
3778     bind(loop);
3779     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3780     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3781     decrement(index);
3782     jcc(Assembler::notZero, loop);
3783   }
3784 
3785   bind(done);
3786 }
3787 
3788 // Look up the method for a megamorphic invokeinterface call.
3789 // The target method is determined by <intf_klass, itable_index>.
3790 // The receiver klass is in recv_klass.
3791 // On success, the result will be in method_result, and execution falls through.
3792 // On failure, execution transfers to the given label.
3793 void MacroAssembler::lookup_interface_method(Register recv_klass,
3794                                              Register intf_klass,
3795                                              RegisterOrConstant itable_index,
3796                                              Register method_result,
3797                                              Register scan_temp,
3798                                              Label& L_no_such_interface,
3799                                              bool return_method) {
3800   assert_different_registers(recv_klass, intf_klass, scan_temp);
3801   assert_different_registers(method_result, intf_klass, scan_temp);
3802   assert(recv_klass != method_result || !return_method,
3803          "recv_klass can be destroyed when method isn't needed");
3804 
3805   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3806          "caller must use same register for non-constant itable index as for method");
3807 
3808   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3809   int vtable_base = in_bytes(Klass::vtable_start_offset());
3810   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3811   int scan_step   = itableOffsetEntry::size() * wordSize;
3812   int vte_size    = vtableEntry::size_in_bytes();
3813   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3814   assert(vte_size == wordSize, "else adjust times_vte_scale");
3815 
3816   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3817 
3818   // %%% Could store the aligned, prescaled offset in the klassoop.
3819   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3820 
3821   if (return_method) {
3822     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3823     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3824     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3825   }
3826 
3827   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3828   //   if (scan->interface() == intf) {
3829   //     result = (klass + scan->offset() + itable_index);
3830   //   }
3831   // }
3832   Label search, found_method;
3833 
3834   for (int peel = 1; peel >= 0; peel--) {
3835     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3836     cmpptr(intf_klass, method_result);
3837 
3838     if (peel) {
3839       jccb(Assembler::equal, found_method);
3840     } else {
3841       jccb(Assembler::notEqual, search);
3842       // (invert the test to fall through to found_method...)
3843     }
3844 
3845     if (!peel)  break;
3846 
3847     bind(search);
3848 
3849     // Check that the previous entry is non-null.  A null entry means that
3850     // the receiver class doesn't implement the interface, and wasn't the
3851     // same as when the caller was compiled.
3852     testptr(method_result, method_result);
3853     jcc(Assembler::zero, L_no_such_interface);
3854     addptr(scan_temp, scan_step);
3855   }
3856 
3857   bind(found_method);
3858 
3859   if (return_method) {
3860     // Got a hit.
3861     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
3862     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3863   }
3864 }
3865 
3866 
3867 // virtual method calling
3868 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3869                                            RegisterOrConstant vtable_index,
3870                                            Register method_result) {
3871   const int base = in_bytes(Klass::vtable_start_offset());
3872   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3873   Address vtable_entry_addr(recv_klass,
3874                             vtable_index, Address::times_ptr,
3875                             base + vtableEntry::method_offset_in_bytes());
3876   movptr(method_result, vtable_entry_addr);
3877 }
3878 
3879 
3880 void MacroAssembler::check_klass_subtype(Register sub_klass,
3881                            Register super_klass,
3882                            Register temp_reg,
3883                            Label& L_success) {
3884   Label L_failure;
3885   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
3886   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3887   bind(L_failure);
3888 }
3889 
3890 
3891 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3892                                                    Register super_klass,
3893                                                    Register temp_reg,
3894                                                    Label* L_success,
3895                                                    Label* L_failure,
3896                                                    Label* L_slow_path,
3897                                         RegisterOrConstant super_check_offset) {
3898   assert_different_registers(sub_klass, super_klass, temp_reg);
3899   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3900   if (super_check_offset.is_register()) {
3901     assert_different_registers(sub_klass, super_klass,
3902                                super_check_offset.as_register());
3903   } else if (must_load_sco) {
3904     assert(temp_reg != noreg, "supply either a temp or a register offset");
3905   }
3906 
3907   Label L_fallthrough;
3908   int label_nulls = 0;
3909   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3910   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3911   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3912   assert(label_nulls <= 1, "at most one NULL in the batch");
3913 
3914   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3915   int sco_offset = in_bytes(Klass::super_check_offset_offset());
3916   Address super_check_offset_addr(super_klass, sco_offset);
3917 
3918   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3919   // range of a jccb.  If this routine grows larger, reconsider at
3920   // least some of these.
3921 #define local_jcc(assembler_cond, label)                                \
3922   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
3923   else                             jcc( assembler_cond, label) /*omit semi*/
3924 
3925   // Hacked jmp, which may only be used just before L_fallthrough.
3926 #define final_jmp(label)                                                \
3927   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3928   else                            jmp(label)                /*omit semi*/
3929 
3930   // If the pointers are equal, we are done (e.g., String[] elements).
3931   // This self-check enables sharing of secondary supertype arrays among
3932   // non-primary types such as array-of-interface.  Otherwise, each such
3933   // type would need its own customized SSA.
3934   // We move this check to the front of the fast path because many
3935   // type checks are in fact trivially successful in this manner,
3936   // so we get a nicely predicted branch right at the start of the check.
3937   cmpptr(sub_klass, super_klass);
3938   local_jcc(Assembler::equal, *L_success);
3939 
3940   // Check the supertype display:
3941   if (must_load_sco) {
3942     // Positive movl does right thing on LP64.
3943     movl(temp_reg, super_check_offset_addr);
3944     super_check_offset = RegisterOrConstant(temp_reg);
3945   }
3946   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3947   cmpptr(super_klass, super_check_addr); // load displayed supertype
3948 
3949   // This check has worked decisively for primary supers.
3950   // Secondary supers are sought in the super_cache ('super_cache_addr').
3951   // (Secondary supers are interfaces and very deeply nested subtypes.)
3952   // This works in the same check above because of a tricky aliasing
3953   // between the super_cache and the primary super display elements.
3954   // (The 'super_check_addr' can address either, as the case requires.)
3955   // Note that the cache is updated below if it does not help us find
3956   // what we need immediately.
3957   // So if it was a primary super, we can just fail immediately.
3958   // Otherwise, it's the slow path for us (no success at this point).
3959 
3960   if (super_check_offset.is_register()) {
3961     local_jcc(Assembler::equal, *L_success);
3962     cmpl(super_check_offset.as_register(), sc_offset);
3963     if (L_failure == &L_fallthrough) {
3964       local_jcc(Assembler::equal, *L_slow_path);
3965     } else {
3966       local_jcc(Assembler::notEqual, *L_failure);
3967       final_jmp(*L_slow_path);
3968     }
3969   } else if (super_check_offset.as_constant() == sc_offset) {
3970     // Need a slow path; fast failure is impossible.
3971     if (L_slow_path == &L_fallthrough) {
3972       local_jcc(Assembler::equal, *L_success);
3973     } else {
3974       local_jcc(Assembler::notEqual, *L_slow_path);
3975       final_jmp(*L_success);
3976     }
3977   } else {
3978     // No slow path; it's a fast decision.
3979     if (L_failure == &L_fallthrough) {
3980       local_jcc(Assembler::equal, *L_success);
3981     } else {
3982       local_jcc(Assembler::notEqual, *L_failure);
3983       final_jmp(*L_success);
3984     }
3985   }
3986 
3987   bind(L_fallthrough);
3988 
3989 #undef local_jcc
3990 #undef final_jmp
3991 }
3992 
3993 
3994 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3995                                                    Register super_klass,
3996                                                    Register temp_reg,
3997                                                    Register temp2_reg,
3998                                                    Label* L_success,
3999                                                    Label* L_failure,
4000                                                    bool set_cond_codes) {
4001   assert_different_registers(sub_klass, super_klass, temp_reg);
4002   if (temp2_reg != noreg)
4003     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4004 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4005 
4006   Label L_fallthrough;
4007   int label_nulls = 0;
4008   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4009   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4010   assert(label_nulls <= 1, "at most one NULL in the batch");
4011 
4012   // a couple of useful fields in sub_klass:
4013   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4014   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4015   Address secondary_supers_addr(sub_klass, ss_offset);
4016   Address super_cache_addr(     sub_klass, sc_offset);
4017 
4018   // Do a linear scan of the secondary super-klass chain.
4019   // This code is rarely used, so simplicity is a virtue here.
4020   // The repne_scan instruction uses fixed registers, which we must spill.
4021   // Don't worry too much about pre-existing connections with the input regs.
4022 
4023   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4024   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4025 
4026   // Get super_klass value into rax (even if it was in rdi or rcx).
4027   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4028   if (super_klass != rax || UseCompressedOops) {
4029     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4030     mov(rax, super_klass);
4031   }
4032   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4033   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4034 
4035 #ifndef PRODUCT
4036   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4037   ExternalAddress pst_counter_addr((address) pst_counter);
4038   NOT_LP64(  incrementl(pst_counter_addr) );
4039   LP64_ONLY( lea(rcx, pst_counter_addr) );
4040   LP64_ONLY( incrementl(Address(rcx, 0)) );
4041 #endif //PRODUCT
4042 
4043   // We will consult the secondary-super array.
4044   movptr(rdi, secondary_supers_addr);
4045   // Load the array length.  (Positive movl does right thing on LP64.)
4046   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4047   // Skip to start of data.
4048   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4049 
4050   // Scan RCX words at [RDI] for an occurrence of RAX.
4051   // Set NZ/Z based on last compare.
4052   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4053   // not change flags (only scas instruction which is repeated sets flags).
4054   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4055 
4056     testptr(rax,rax); // Set Z = 0
4057     repne_scan();
4058 
4059   // Unspill the temp. registers:
4060   if (pushed_rdi)  pop(rdi);
4061   if (pushed_rcx)  pop(rcx);
4062   if (pushed_rax)  pop(rax);
4063 
4064   if (set_cond_codes) {
4065     // Special hack for the AD files:  rdi is guaranteed non-zero.
4066     assert(!pushed_rdi, "rdi must be left non-NULL");
4067     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4068   }
4069 
4070   if (L_failure == &L_fallthrough)
4071         jccb(Assembler::notEqual, *L_failure);
4072   else  jcc(Assembler::notEqual, *L_failure);
4073 
4074   // Success.  Cache the super we found and proceed in triumph.
4075   movptr(super_cache_addr, super_klass);
4076 
4077   if (L_success != &L_fallthrough) {
4078     jmp(*L_success);
4079   }
4080 
4081 #undef IS_A_TEMP
4082 
4083   bind(L_fallthrough);
4084 }
4085 
4086 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4087   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4088 
4089   Label L_fallthrough;
4090   if (L_fast_path == NULL) {
4091     L_fast_path = &L_fallthrough;
4092   } else if (L_slow_path == NULL) {
4093     L_slow_path = &L_fallthrough;
4094   }
4095 
4096   // Fast path check: class is fully initialized
4097   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4098   jcc(Assembler::equal, *L_fast_path);
4099 
4100   // Fast path check: current thread is initializer thread
4101   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4102   if (L_slow_path == &L_fallthrough) {
4103     jcc(Assembler::equal, *L_fast_path);
4104     bind(*L_slow_path);
4105   } else if (L_fast_path == &L_fallthrough) {
4106     jcc(Assembler::notEqual, *L_slow_path);
4107     bind(*L_fast_path);
4108   } else {
4109     Unimplemented();
4110   }
4111 }
4112 
4113 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4114   if (VM_Version::supports_cmov()) {
4115     cmovl(cc, dst, src);
4116   } else {
4117     Label L;
4118     jccb(negate_condition(cc), L);
4119     movl(dst, src);
4120     bind(L);
4121   }
4122 }
4123 
4124 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4125   if (VM_Version::supports_cmov()) {
4126     cmovl(cc, dst, src);
4127   } else {
4128     Label L;
4129     jccb(negate_condition(cc), L);
4130     movl(dst, src);
4131     bind(L);
4132   }
4133 }
4134 
4135 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4136   if (!VerifyOops) return;
4137 
4138   // Pass register number to verify_oop_subroutine
4139   const char* b = NULL;
4140   {
4141     ResourceMark rm;
4142     stringStream ss;
4143     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4144     b = code_string(ss.as_string());
4145   }
4146   BLOCK_COMMENT("verify_oop {");
4147 #ifdef _LP64
4148   push(rscratch1);                    // save r10, trashed by movptr()
4149 #endif
4150   push(rax);                          // save rax,
4151   push(reg);                          // pass register argument
4152   ExternalAddress buffer((address) b);
4153   // avoid using pushptr, as it modifies scratch registers
4154   // and our contract is not to modify anything
4155   movptr(rax, buffer.addr());
4156   push(rax);
4157   // call indirectly to solve generation ordering problem
4158   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4159   call(rax);
4160   // Caller pops the arguments (oop, message) and restores rax, r10
4161   BLOCK_COMMENT("} verify_oop");
4162 }
4163 
4164 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4165   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4166     vpternlogd(dst, 0xFF, dst, dst, vector_len);
4167   } else {
4168     assert(UseAVX > 0, "");
4169     vpcmpeqb(dst, dst, dst, vector_len);
4170   }
4171 }
4172 
4173 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4174                                          int extra_slot_offset) {
4175   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4176   int stackElementSize = Interpreter::stackElementSize;
4177   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4178 #ifdef ASSERT
4179   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4180   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4181 #endif
4182   Register             scale_reg    = noreg;
4183   Address::ScaleFactor scale_factor = Address::no_scale;
4184   if (arg_slot.is_constant()) {
4185     offset += arg_slot.as_constant() * stackElementSize;
4186   } else {
4187     scale_reg    = arg_slot.as_register();
4188     scale_factor = Address::times(stackElementSize);
4189   }
4190   offset += wordSize;           // return PC is on stack
4191   return Address(rsp, scale_reg, scale_factor, offset);
4192 }
4193 
4194 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4195   if (!VerifyOops) return;
4196 
4197   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4198   // Pass register number to verify_oop_subroutine
4199   const char* b = NULL;
4200   {
4201     ResourceMark rm;
4202     stringStream ss;
4203     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4204     b = code_string(ss.as_string());
4205   }
4206 #ifdef _LP64
4207   push(rscratch1);                    // save r10, trashed by movptr()
4208 #endif
4209   push(rax);                          // save rax,
4210   // addr may contain rsp so we will have to adjust it based on the push
4211   // we just did (and on 64 bit we do two pushes)
4212   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4213   // stores rax into addr which is backwards of what was intended.
4214   if (addr.uses(rsp)) {
4215     lea(rax, addr);
4216     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4217   } else {
4218     pushptr(addr);
4219   }
4220 
4221   ExternalAddress buffer((address) b);
4222   // pass msg argument
4223   // avoid using pushptr, as it modifies scratch registers
4224   // and our contract is not to modify anything
4225   movptr(rax, buffer.addr());
4226   push(rax);
4227 
4228   // call indirectly to solve generation ordering problem
4229   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4230   call(rax);
4231   // Caller pops the arguments (addr, message) and restores rax, r10.
4232 }
4233 
4234 void MacroAssembler::verify_tlab() {
4235 #ifdef ASSERT
4236   if (UseTLAB && VerifyOops) {
4237     Label next, ok;
4238     Register t1 = rsi;
4239     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4240 
4241     push(t1);
4242     NOT_LP64(push(thread_reg));
4243     NOT_LP64(get_thread(thread_reg));
4244 
4245     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4246     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4247     jcc(Assembler::aboveEqual, next);
4248     STOP("assert(top >= start)");
4249     should_not_reach_here();
4250 
4251     bind(next);
4252     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4253     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4254     jcc(Assembler::aboveEqual, ok);
4255     STOP("assert(top <= end)");
4256     should_not_reach_here();
4257 
4258     bind(ok);
4259     NOT_LP64(pop(thread_reg));
4260     pop(t1);
4261   }
4262 #endif
4263 }
4264 
4265 class ControlWord {
4266  public:
4267   int32_t _value;
4268 
4269   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4270   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4271   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4272   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4273   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4274   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4275   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4276   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4277 
4278   void print() const {
4279     // rounding control
4280     const char* rc;
4281     switch (rounding_control()) {
4282       case 0: rc = "round near"; break;
4283       case 1: rc = "round down"; break;
4284       case 2: rc = "round up  "; break;
4285       case 3: rc = "chop      "; break;
4286       default:
4287         rc = NULL; // silence compiler warnings
4288         fatal("Unknown rounding control: %d", rounding_control());
4289     };
4290     // precision control
4291     const char* pc;
4292     switch (precision_control()) {
4293       case 0: pc = "24 bits "; break;
4294       case 1: pc = "reserved"; break;
4295       case 2: pc = "53 bits "; break;
4296       case 3: pc = "64 bits "; break;
4297       default:
4298         pc = NULL; // silence compiler warnings
4299         fatal("Unknown precision control: %d", precision_control());
4300     };
4301     // flags
4302     char f[9];
4303     f[0] = ' ';
4304     f[1] = ' ';
4305     f[2] = (precision   ()) ? 'P' : 'p';
4306     f[3] = (underflow   ()) ? 'U' : 'u';
4307     f[4] = (overflow    ()) ? 'O' : 'o';
4308     f[5] = (zero_divide ()) ? 'Z' : 'z';
4309     f[6] = (denormalized()) ? 'D' : 'd';
4310     f[7] = (invalid     ()) ? 'I' : 'i';
4311     f[8] = '\x0';
4312     // output
4313     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4314   }
4315 
4316 };
4317 
4318 class StatusWord {
4319  public:
4320   int32_t _value;
4321 
4322   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4323   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4324   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4325   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4326   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4327   int  top() const                     { return  (_value >> 11) & 7      ; }
4328   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4329   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4330   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4331   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4332   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4333   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4334   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4335   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4336 
4337   void print() const {
4338     // condition codes
4339     char c[5];
4340     c[0] = (C3()) ? '3' : '-';
4341     c[1] = (C2()) ? '2' : '-';
4342     c[2] = (C1()) ? '1' : '-';
4343     c[3] = (C0()) ? '0' : '-';
4344     c[4] = '\x0';
4345     // flags
4346     char f[9];
4347     f[0] = (error_status()) ? 'E' : '-';
4348     f[1] = (stack_fault ()) ? 'S' : '-';
4349     f[2] = (precision   ()) ? 'P' : '-';
4350     f[3] = (underflow   ()) ? 'U' : '-';
4351     f[4] = (overflow    ()) ? 'O' : '-';
4352     f[5] = (zero_divide ()) ? 'Z' : '-';
4353     f[6] = (denormalized()) ? 'D' : '-';
4354     f[7] = (invalid     ()) ? 'I' : '-';
4355     f[8] = '\x0';
4356     // output
4357     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4358   }
4359 
4360 };
4361 
4362 class TagWord {
4363  public:
4364   int32_t _value;
4365 
4366   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4367 
4368   void print() const {
4369     printf("%04x", _value & 0xFFFF);
4370   }
4371 
4372 };
4373 
4374 class FPU_Register {
4375  public:
4376   int32_t _m0;
4377   int32_t _m1;
4378   int16_t _ex;
4379 
4380   bool is_indefinite() const           {
4381     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4382   }
4383 
4384   void print() const {
4385     char  sign = (_ex < 0) ? '-' : '+';
4386     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4387     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4388   };
4389 
4390 };
4391 
4392 class FPU_State {
4393  public:
4394   enum {
4395     register_size       = 10,
4396     number_of_registers =  8,
4397     register_mask       =  7
4398   };
4399 
4400   ControlWord  _control_word;
4401   StatusWord   _status_word;
4402   TagWord      _tag_word;
4403   int32_t      _error_offset;
4404   int32_t      _error_selector;
4405   int32_t      _data_offset;
4406   int32_t      _data_selector;
4407   int8_t       _register[register_size * number_of_registers];
4408 
4409   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4410   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4411 
4412   const char* tag_as_string(int tag) const {
4413     switch (tag) {
4414       case 0: return "valid";
4415       case 1: return "zero";
4416       case 2: return "special";
4417       case 3: return "empty";
4418     }
4419     ShouldNotReachHere();
4420     return NULL;
4421   }
4422 
4423   void print() const {
4424     // print computation registers
4425     { int t = _status_word.top();
4426       for (int i = 0; i < number_of_registers; i++) {
4427         int j = (i - t) & register_mask;
4428         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4429         st(j)->print();
4430         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4431       }
4432     }
4433     printf("\n");
4434     // print control registers
4435     printf("ctrl = "); _control_word.print(); printf("\n");
4436     printf("stat = "); _status_word .print(); printf("\n");
4437     printf("tags = "); _tag_word    .print(); printf("\n");
4438   }
4439 
4440 };
4441 
4442 class Flag_Register {
4443  public:
4444   int32_t _value;
4445 
4446   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4447   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4448   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4449   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4450   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4451   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4452   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4453 
4454   void print() const {
4455     // flags
4456     char f[8];
4457     f[0] = (overflow       ()) ? 'O' : '-';
4458     f[1] = (direction      ()) ? 'D' : '-';
4459     f[2] = (sign           ()) ? 'S' : '-';
4460     f[3] = (zero           ()) ? 'Z' : '-';
4461     f[4] = (auxiliary_carry()) ? 'A' : '-';
4462     f[5] = (parity         ()) ? 'P' : '-';
4463     f[6] = (carry          ()) ? 'C' : '-';
4464     f[7] = '\x0';
4465     // output
4466     printf("%08x  flags = %s", _value, f);
4467   }
4468 
4469 };
4470 
4471 class IU_Register {
4472  public:
4473   int32_t _value;
4474 
4475   void print() const {
4476     printf("%08x  %11d", _value, _value);
4477   }
4478 
4479 };
4480 
4481 class IU_State {
4482  public:
4483   Flag_Register _eflags;
4484   IU_Register   _rdi;
4485   IU_Register   _rsi;
4486   IU_Register   _rbp;
4487   IU_Register   _rsp;
4488   IU_Register   _rbx;
4489   IU_Register   _rdx;
4490   IU_Register   _rcx;
4491   IU_Register   _rax;
4492 
4493   void print() const {
4494     // computation registers
4495     printf("rax,  = "); _rax.print(); printf("\n");
4496     printf("rbx,  = "); _rbx.print(); printf("\n");
4497     printf("rcx  = "); _rcx.print(); printf("\n");
4498     printf("rdx  = "); _rdx.print(); printf("\n");
4499     printf("rdi  = "); _rdi.print(); printf("\n");
4500     printf("rsi  = "); _rsi.print(); printf("\n");
4501     printf("rbp,  = "); _rbp.print(); printf("\n");
4502     printf("rsp  = "); _rsp.print(); printf("\n");
4503     printf("\n");
4504     // control registers
4505     printf("flgs = "); _eflags.print(); printf("\n");
4506   }
4507 };
4508 
4509 
4510 class CPU_State {
4511  public:
4512   FPU_State _fpu_state;
4513   IU_State  _iu_state;
4514 
4515   void print() const {
4516     printf("--------------------------------------------------\n");
4517     _iu_state .print();
4518     printf("\n");
4519     _fpu_state.print();
4520     printf("--------------------------------------------------\n");
4521   }
4522 
4523 };
4524 
4525 
4526 static void _print_CPU_state(CPU_State* state) {
4527   state->print();
4528 };
4529 
4530 
4531 void MacroAssembler::print_CPU_state() {
4532   push_CPU_state();
4533   push(rsp);                // pass CPU state
4534   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4535   addptr(rsp, wordSize);       // discard argument
4536   pop_CPU_state();
4537 }
4538 
4539 
4540 #ifndef _LP64
4541 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4542   static int counter = 0;
4543   FPU_State* fs = &state->_fpu_state;
4544   counter++;
4545   // For leaf calls, only verify that the top few elements remain empty.
4546   // We only need 1 empty at the top for C2 code.
4547   if( stack_depth < 0 ) {
4548     if( fs->tag_for_st(7) != 3 ) {
4549       printf("FPR7 not empty\n");
4550       state->print();
4551       assert(false, "error");
4552       return false;
4553     }
4554     return true;                // All other stack states do not matter
4555   }
4556 
4557   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4558          "bad FPU control word");
4559 
4560   // compute stack depth
4561   int i = 0;
4562   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4563   int d = i;
4564   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4565   // verify findings
4566   if (i != FPU_State::number_of_registers) {
4567     // stack not contiguous
4568     printf("%s: stack not contiguous at ST%d\n", s, i);
4569     state->print();
4570     assert(false, "error");
4571     return false;
4572   }
4573   // check if computed stack depth corresponds to expected stack depth
4574   if (stack_depth < 0) {
4575     // expected stack depth is -stack_depth or less
4576     if (d > -stack_depth) {
4577       // too many elements on the stack
4578       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4579       state->print();
4580       assert(false, "error");
4581       return false;
4582     }
4583   } else {
4584     // expected stack depth is stack_depth
4585     if (d != stack_depth) {
4586       // wrong stack depth
4587       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4588       state->print();
4589       assert(false, "error");
4590       return false;
4591     }
4592   }
4593   // everything is cool
4594   return true;
4595 }
4596 
4597 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4598   if (!VerifyFPU) return;
4599   push_CPU_state();
4600   push(rsp);                // pass CPU state
4601   ExternalAddress msg((address) s);
4602   // pass message string s
4603   pushptr(msg.addr());
4604   push(stack_depth);        // pass stack depth
4605   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4606   addptr(rsp, 3 * wordSize);   // discard arguments
4607   // check for error
4608   { Label L;
4609     testl(rax, rax);
4610     jcc(Assembler::notZero, L);
4611     int3();                  // break if error condition
4612     bind(L);
4613   }
4614   pop_CPU_state();
4615 }
4616 #endif // _LP64
4617 
4618 void MacroAssembler::restore_cpu_control_state_after_jni() {
4619   // Either restore the MXCSR register after returning from the JNI Call
4620   // or verify that it wasn't changed (with -Xcheck:jni flag).
4621   if (VM_Version::supports_sse()) {
4622     if (RestoreMXCSROnJNICalls) {
4623       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4624     } else if (CheckJNICalls) {
4625       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4626     }
4627   }
4628   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4629   vzeroupper();
4630   // Reset k1 to 0xffff.
4631 
4632 #ifdef COMPILER2
4633   if (PostLoopMultiversioning && VM_Version::supports_evex()) {
4634     push(rcx);
4635     movl(rcx, 0xffff);
4636     kmovwl(k1, rcx);
4637     pop(rcx);
4638   }
4639 #endif // COMPILER2
4640 
4641 #ifndef _LP64
4642   // Either restore the x87 floating pointer control word after returning
4643   // from the JNI call or verify that it wasn't changed.
4644   if (CheckJNICalls) {
4645     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4646   }
4647 #endif // _LP64
4648 }
4649 
4650 // ((OopHandle)result).resolve();
4651 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4652   assert_different_registers(result, tmp);
4653 
4654   // Only 64 bit platforms support GCs that require a tmp register
4655   // Only IN_HEAP loads require a thread_tmp register
4656   // OopHandle::resolve is an indirection like jobject.
4657   access_load_at(T_OBJECT, IN_NATIVE,
4658                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4659 }
4660 
4661 // ((WeakHandle)result).resolve();
4662 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4663   assert_different_registers(rresult, rtmp);
4664   Label resolved;
4665 
4666   // A null weak handle resolves to null.
4667   cmpptr(rresult, 0);
4668   jcc(Assembler::equal, resolved);
4669 
4670   // Only 64 bit platforms support GCs that require a tmp register
4671   // Only IN_HEAP loads require a thread_tmp register
4672   // WeakHandle::resolve is an indirection like jweak.
4673   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4674                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4675   bind(resolved);
4676 }
4677 
4678 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4679   // get mirror
4680   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4681   load_method_holder(mirror, method);
4682   movptr(mirror, Address(mirror, mirror_offset));
4683   resolve_oop_handle(mirror, tmp);
4684 }
4685 
4686 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4687   load_method_holder(rresult, rmethod);
4688   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4689 }
4690 
4691 void MacroAssembler::load_method_holder(Register holder, Register method) {
4692   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
4693   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
4694   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4695 }
4696 
4697 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4698   assert_different_registers(src, tmp);
4699   assert_different_registers(dst, tmp);
4700 #ifdef _LP64
4701   if (UseCompressedClassPointers) {
4702     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4703     decode_klass_not_null(dst, tmp);
4704   } else
4705 #endif
4706     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4707 }
4708 
4709 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4710   assert_different_registers(src, tmp);
4711   assert_different_registers(dst, tmp);
4712 #ifdef _LP64
4713   if (UseCompressedClassPointers) {
4714     encode_klass_not_null(src, tmp);
4715     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4716   } else
4717 #endif
4718     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4719 }
4720 
4721 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4722                                     Register tmp1, Register thread_tmp) {
4723   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4724   decorators = AccessInternal::decorator_fixup(decorators);
4725   bool as_raw = (decorators & AS_RAW) != 0;
4726   if (as_raw) {
4727     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4728   } else {
4729     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4730   }
4731 }
4732 
4733 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4734                                      Register tmp1, Register tmp2) {
4735   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4736   decorators = AccessInternal::decorator_fixup(decorators);
4737   bool as_raw = (decorators & AS_RAW) != 0;
4738   if (as_raw) {
4739     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
4740   } else {
4741     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
4742   }
4743 }
4744 
4745 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4746                                    Register thread_tmp, DecoratorSet decorators) {
4747   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4748 }
4749 
4750 // Doesn't do verfication, generates fixed size code
4751 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4752                                             Register thread_tmp, DecoratorSet decorators) {
4753   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4754 }
4755 
4756 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4757                                     Register tmp2, DecoratorSet decorators) {
4758   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4759 }
4760 
4761 // Used for storing NULLs.
4762 void MacroAssembler::store_heap_oop_null(Address dst) {
4763   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4764 }
4765 
4766 #ifdef _LP64
4767 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4768   if (UseCompressedClassPointers) {
4769     // Store to klass gap in destination
4770     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4771   }
4772 }
4773 
4774 #ifdef ASSERT
4775 void MacroAssembler::verify_heapbase(const char* msg) {
4776   assert (UseCompressedOops, "should be compressed");
4777   assert (Universe::heap() != NULL, "java heap should be initialized");
4778   if (CheckCompressedOops) {
4779     Label ok;
4780     push(rscratch1); // cmpptr trashes rscratch1
4781     cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
4782     jcc(Assembler::equal, ok);
4783     STOP(msg);
4784     bind(ok);
4785     pop(rscratch1);
4786   }
4787 }
4788 #endif
4789 
4790 // Algorithm must match oop.inline.hpp encode_heap_oop.
4791 void MacroAssembler::encode_heap_oop(Register r) {
4792 #ifdef ASSERT
4793   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4794 #endif
4795   verify_oop_msg(r, "broken oop in encode_heap_oop");
4796   if (CompressedOops::base() == NULL) {
4797     if (CompressedOops::shift() != 0) {
4798       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4799       shrq(r, LogMinObjAlignmentInBytes);
4800     }
4801     return;
4802   }
4803   testq(r, r);
4804   cmovq(Assembler::equal, r, r12_heapbase);
4805   subq(r, r12_heapbase);
4806   shrq(r, LogMinObjAlignmentInBytes);
4807 }
4808 
4809 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4810 #ifdef ASSERT
4811   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4812   if (CheckCompressedOops) {
4813     Label ok;
4814     testq(r, r);
4815     jcc(Assembler::notEqual, ok);
4816     STOP("null oop passed to encode_heap_oop_not_null");
4817     bind(ok);
4818   }
4819 #endif
4820   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4821   if (CompressedOops::base() != NULL) {
4822     subq(r, r12_heapbase);
4823   }
4824   if (CompressedOops::shift() != 0) {
4825     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4826     shrq(r, LogMinObjAlignmentInBytes);
4827   }
4828 }
4829 
4830 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4831 #ifdef ASSERT
4832   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4833   if (CheckCompressedOops) {
4834     Label ok;
4835     testq(src, src);
4836     jcc(Assembler::notEqual, ok);
4837     STOP("null oop passed to encode_heap_oop_not_null2");
4838     bind(ok);
4839   }
4840 #endif
4841   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4842   if (dst != src) {
4843     movq(dst, src);
4844   }
4845   if (CompressedOops::base() != NULL) {
4846     subq(dst, r12_heapbase);
4847   }
4848   if (CompressedOops::shift() != 0) {
4849     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4850     shrq(dst, LogMinObjAlignmentInBytes);
4851   }
4852 }
4853 
4854 void  MacroAssembler::decode_heap_oop(Register r) {
4855 #ifdef ASSERT
4856   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4857 #endif
4858   if (CompressedOops::base() == NULL) {
4859     if (CompressedOops::shift() != 0) {
4860       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4861       shlq(r, LogMinObjAlignmentInBytes);
4862     }
4863   } else {
4864     Label done;
4865     shlq(r, LogMinObjAlignmentInBytes);
4866     jccb(Assembler::equal, done);
4867     addq(r, r12_heapbase);
4868     bind(done);
4869   }
4870   verify_oop_msg(r, "broken oop in decode_heap_oop");
4871 }
4872 
4873 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
4874   // Note: it will change flags
4875   assert (UseCompressedOops, "should only be used for compressed headers");
4876   assert (Universe::heap() != NULL, "java heap should be initialized");
4877   // Cannot assert, unverified entry point counts instructions (see .ad file)
4878   // vtableStubs also counts instructions in pd_code_size_limit.
4879   // Also do not verify_oop as this is called by verify_oop.
4880   if (CompressedOops::shift() != 0) {
4881     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4882     shlq(r, LogMinObjAlignmentInBytes);
4883     if (CompressedOops::base() != NULL) {
4884       addq(r, r12_heapbase);
4885     }
4886   } else {
4887     assert (CompressedOops::base() == NULL, "sanity");
4888   }
4889 }
4890 
4891 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4892   // Note: it will change flags
4893   assert (UseCompressedOops, "should only be used for compressed headers");
4894   assert (Universe::heap() != NULL, "java heap should be initialized");
4895   // Cannot assert, unverified entry point counts instructions (see .ad file)
4896   // vtableStubs also counts instructions in pd_code_size_limit.
4897   // Also do not verify_oop as this is called by verify_oop.
4898   if (CompressedOops::shift() != 0) {
4899     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4900     if (LogMinObjAlignmentInBytes == Address::times_8) {
4901       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
4902     } else {
4903       if (dst != src) {
4904         movq(dst, src);
4905       }
4906       shlq(dst, LogMinObjAlignmentInBytes);
4907       if (CompressedOops::base() != NULL) {
4908         addq(dst, r12_heapbase);
4909       }
4910     }
4911   } else {
4912     assert (CompressedOops::base() == NULL, "sanity");
4913     if (dst != src) {
4914       movq(dst, src);
4915     }
4916   }
4917 }
4918 
4919 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
4920   assert_different_registers(r, tmp);
4921   if (CompressedKlassPointers::base() != NULL) {
4922     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4923     subq(r, tmp);
4924   }
4925   if (CompressedKlassPointers::shift() != 0) {
4926     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4927     shrq(r, LogKlassAlignmentInBytes);
4928   }
4929 }
4930 
4931 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
4932   assert_different_registers(src, dst);
4933   if (CompressedKlassPointers::base() != NULL) {
4934     mov64(dst, -(int64_t)CompressedKlassPointers::base());
4935     addq(dst, src);
4936   } else {
4937     movptr(dst, src);
4938   }
4939   if (CompressedKlassPointers::shift() != 0) {
4940     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4941     shrq(dst, LogKlassAlignmentInBytes);
4942   }
4943 }
4944 
4945 // !!! If the instructions that get generated here change then function
4946 // instr_size_for_decode_klass_not_null() needs to get updated.
4947 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
4948   assert_different_registers(r, tmp);
4949   // Note: it will change flags
4950   assert(UseCompressedClassPointers, "should only be used for compressed headers");
4951   // Cannot assert, unverified entry point counts instructions (see .ad file)
4952   // vtableStubs also counts instructions in pd_code_size_limit.
4953   // Also do not verify_oop as this is called by verify_oop.
4954   if (CompressedKlassPointers::shift() != 0) {
4955     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4956     shlq(r, LogKlassAlignmentInBytes);
4957   }
4958   if (CompressedKlassPointers::base() != NULL) {
4959     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4960     addq(r, tmp);
4961   }
4962 }
4963 
4964 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
4965   assert_different_registers(src, dst);
4966   // Note: it will change flags
4967   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4968   // Cannot assert, unverified entry point counts instructions (see .ad file)
4969   // vtableStubs also counts instructions in pd_code_size_limit.
4970   // Also do not verify_oop as this is called by verify_oop.
4971 
4972   if (CompressedKlassPointers::base() == NULL &&
4973       CompressedKlassPointers::shift() == 0) {
4974     // The best case scenario is that there is no base or shift. Then it is already
4975     // a pointer that needs nothing but a register rename.
4976     movl(dst, src);
4977   } else {
4978     if (CompressedKlassPointers::base() != NULL) {
4979       mov64(dst, (int64_t)CompressedKlassPointers::base());
4980     } else {
4981       xorq(dst, dst);
4982     }
4983     if (CompressedKlassPointers::shift() != 0) {
4984       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4985       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
4986       leaq(dst, Address(dst, src, Address::times_8, 0));
4987     } else {
4988       addq(dst, src);
4989     }
4990   }
4991 }
4992 
4993 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
4994   assert (UseCompressedOops, "should only be used for compressed headers");
4995   assert (Universe::heap() != NULL, "java heap should be initialized");
4996   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4997   int oop_index = oop_recorder()->find_index(obj);
4998   RelocationHolder rspec = oop_Relocation::spec(oop_index);
4999   mov_narrow_oop(dst, oop_index, rspec);
5000 }
5001 
5002 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5003   assert (UseCompressedOops, "should only be used for compressed headers");
5004   assert (Universe::heap() != NULL, "java heap should be initialized");
5005   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5006   int oop_index = oop_recorder()->find_index(obj);
5007   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5008   mov_narrow_oop(dst, oop_index, rspec);
5009 }
5010 
5011 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5012   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5013   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5014   int klass_index = oop_recorder()->find_index(k);
5015   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5016   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5017 }
5018 
5019 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5020   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5021   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5022   int klass_index = oop_recorder()->find_index(k);
5023   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5024   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5025 }
5026 
5027 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5028   assert (UseCompressedOops, "should only be used for compressed headers");
5029   assert (Universe::heap() != NULL, "java heap should be initialized");
5030   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5031   int oop_index = oop_recorder()->find_index(obj);
5032   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5033   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5034 }
5035 
5036 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5037   assert (UseCompressedOops, "should only be used for compressed headers");
5038   assert (Universe::heap() != NULL, "java heap should be initialized");
5039   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5040   int oop_index = oop_recorder()->find_index(obj);
5041   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5042   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5043 }
5044 
5045 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5046   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5047   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5048   int klass_index = oop_recorder()->find_index(k);
5049   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5050   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5051 }
5052 
5053 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5054   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5055   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5056   int klass_index = oop_recorder()->find_index(k);
5057   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5058   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5059 }
5060 
5061 void MacroAssembler::reinit_heapbase() {
5062   if (UseCompressedOops) {
5063     if (Universe::heap() != NULL) {
5064       if (CompressedOops::base() == NULL) {
5065         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5066       } else {
5067         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5068       }
5069     } else {
5070       movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5071     }
5072   }
5073 }
5074 
5075 #endif // _LP64
5076 
5077 // C2 compiled method's prolog code.
5078 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5079 
5080   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5081   // NativeJump::patch_verified_entry will be able to patch out the entry
5082   // code safely. The push to verify stack depth is ok at 5 bytes,
5083   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5084   // stack bang then we must use the 6 byte frame allocation even if
5085   // we have no frame. :-(
5086   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5087 
5088   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5089   // Remove word for return addr
5090   framesize -= wordSize;
5091   stack_bang_size -= wordSize;
5092 
5093   // Calls to C2R adapters often do not accept exceptional returns.
5094   // We require that their callers must bang for them.  But be careful, because
5095   // some VM calls (such as call site linkage) can use several kilobytes of
5096   // stack.  But the stack safety zone should account for that.
5097   // See bugs 4446381, 4468289, 4497237.
5098   if (stack_bang_size > 0) {
5099     generate_stack_overflow_check(stack_bang_size);
5100 
5101     // We always push rbp, so that on return to interpreter rbp, will be
5102     // restored correctly and we can correct the stack.
5103     push(rbp);
5104     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5105     if (PreserveFramePointer) {
5106       mov(rbp, rsp);
5107     }
5108     // Remove word for ebp
5109     framesize -= wordSize;
5110 
5111     // Create frame
5112     if (framesize) {
5113       subptr(rsp, framesize);
5114     }
5115   } else {
5116     // Create frame (force generation of a 4 byte immediate value)
5117     subptr_imm32(rsp, framesize);
5118 
5119     // Save RBP register now.
5120     framesize -= wordSize;
5121     movptr(Address(rsp, framesize), rbp);
5122     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5123     if (PreserveFramePointer) {
5124       movptr(rbp, rsp);
5125       if (framesize > 0) {
5126         addptr(rbp, framesize);
5127       }
5128     }
5129   }
5130 
5131   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5132     framesize -= wordSize;
5133     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5134   }
5135 
5136 #ifndef _LP64
5137   // If method sets FPU control word do it now
5138   if (fp_mode_24b) {
5139     fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
5140   }
5141   if (UseSSE >= 2 && VerifyFPU) {
5142     verify_FPU(0, "FPU stack must be clean on entry");
5143   }
5144 #endif
5145 
5146 #ifdef ASSERT
5147   if (VerifyStackAtCalls) {
5148     Label L;
5149     push(rax);
5150     mov(rax, rsp);
5151     andptr(rax, StackAlignmentInBytes-1);
5152     cmpptr(rax, StackAlignmentInBytes-wordSize);
5153     pop(rax);
5154     jcc(Assembler::equal, L);
5155     STOP("Stack is not properly aligned!");
5156     bind(L);
5157   }
5158 #endif
5159 
5160   if (!is_stub) {
5161     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5162     bs->nmethod_entry_barrier(this);
5163   }
5164 }
5165 
5166 #if COMPILER2_OR_JVMCI
5167 
5168 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5169 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5170   // cnt - number of qwords (8-byte words).
5171   // base - start address, qword aligned.
5172   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5173   bool use64byteVector = MaxVectorSize == 64 && AVX3Threshold == 0;
5174   if (use64byteVector) {
5175     vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5176   } else if (MaxVectorSize >= 32) {
5177     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5178   } else {
5179     pxor(xtmp, xtmp);
5180   }
5181   jmp(L_zero_64_bytes);
5182 
5183   BIND(L_loop);
5184   if (MaxVectorSize >= 32) {
5185     fill64_avx(base, 0, xtmp, use64byteVector);
5186   } else {
5187     movdqu(Address(base,  0), xtmp);
5188     movdqu(Address(base, 16), xtmp);
5189     movdqu(Address(base, 32), xtmp);
5190     movdqu(Address(base, 48), xtmp);
5191   }
5192   addptr(base, 64);
5193 
5194   BIND(L_zero_64_bytes);
5195   subptr(cnt, 8);
5196   jccb(Assembler::greaterEqual, L_loop);
5197 
5198   // Copy trailing 64 bytes
5199   if (use64byteVector) {
5200     addptr(cnt, 8);
5201     jccb(Assembler::equal, L_end);
5202     fill64_masked_avx(3, base, 0, xtmp, mask, cnt, rtmp, true);
5203     jmp(L_end);
5204   } else {
5205     addptr(cnt, 4);
5206     jccb(Assembler::less, L_tail);
5207     if (MaxVectorSize >= 32) {
5208       vmovdqu(Address(base, 0), xtmp);
5209     } else {
5210       movdqu(Address(base,  0), xtmp);
5211       movdqu(Address(base, 16), xtmp);
5212     }
5213   }
5214   addptr(base, 32);
5215   subptr(cnt, 4);
5216 
5217   BIND(L_tail);
5218   addptr(cnt, 4);
5219   jccb(Assembler::lessEqual, L_end);
5220   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5221     fill32_masked_avx(3, base, 0, xtmp, mask, cnt, rtmp);
5222   } else {
5223     decrement(cnt);
5224 
5225     BIND(L_sloop);
5226     movq(Address(base, 0), xtmp);
5227     addptr(base, 8);
5228     decrement(cnt);
5229     jccb(Assembler::greaterEqual, L_sloop);
5230   }
5231   BIND(L_end);
5232 }
5233 
5234 // Clearing constant sized memory using YMM/ZMM registers.
5235 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5236   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5237   bool use64byteVector = MaxVectorSize > 32 && AVX3Threshold == 0;
5238 
5239   int vector64_count = (cnt & (~0x7)) >> 3;
5240   cnt = cnt & 0x7;
5241 
5242   // 64 byte initialization loop.
5243   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5244   for (int i = 0; i < vector64_count; i++) {
5245     fill64_avx(base, i * 64, xtmp, use64byteVector);
5246   }
5247 
5248   // Clear remaining 64 byte tail.
5249   int disp = vector64_count * 64;
5250   if (cnt) {
5251     switch (cnt) {
5252       case 1:
5253         movq(Address(base, disp), xtmp);
5254         break;
5255       case 2:
5256         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5257         break;
5258       case 3:
5259         movl(rtmp, 0x7);
5260         kmovwl(mask, rtmp);
5261         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5262         break;
5263       case 4:
5264         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5265         break;
5266       case 5:
5267         if (use64byteVector) {
5268           movl(rtmp, 0x1F);
5269           kmovwl(mask, rtmp);
5270           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5271         } else {
5272           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5273           movq(Address(base, disp + 32), xtmp);
5274         }
5275         break;
5276       case 6:
5277         if (use64byteVector) {
5278           movl(rtmp, 0x3F);
5279           kmovwl(mask, rtmp);
5280           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5281         } else {
5282           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5283           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5284         }
5285         break;
5286       case 7:
5287         if (use64byteVector) {
5288           movl(rtmp, 0x7F);
5289           kmovwl(mask, rtmp);
5290           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5291         } else {
5292           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5293           movl(rtmp, 0x7);
5294           kmovwl(mask, rtmp);
5295           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5296         }
5297         break;
5298       default:
5299         fatal("Unexpected length : %d\n",cnt);
5300         break;
5301     }
5302   }
5303 }
5304 
5305 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5306                                bool is_large, KRegister mask) {
5307   // cnt      - number of qwords (8-byte words).
5308   // base     - start address, qword aligned.
5309   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5310   assert(base==rdi, "base register must be edi for rep stos");
5311   assert(tmp==rax,   "tmp register must be eax for rep stos");
5312   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5313   assert(InitArrayShortSize % BytesPerLong == 0,
5314     "InitArrayShortSize should be the multiple of BytesPerLong");
5315 
5316   Label DONE;
5317   if (!is_large || !UseXMMForObjInit) {
5318     xorptr(tmp, tmp);
5319   }
5320 
5321   if (!is_large) {
5322     Label LOOP, LONG;
5323     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5324     jccb(Assembler::greater, LONG);
5325 
5326     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5327 
5328     decrement(cnt);
5329     jccb(Assembler::negative, DONE); // Zero length
5330 
5331     // Use individual pointer-sized stores for small counts:
5332     BIND(LOOP);
5333     movptr(Address(base, cnt, Address::times_ptr), tmp);
5334     decrement(cnt);
5335     jccb(Assembler::greaterEqual, LOOP);
5336     jmpb(DONE);
5337 
5338     BIND(LONG);
5339   }
5340 
5341   // Use longer rep-prefixed ops for non-small counts:
5342   if (UseFastStosb) {
5343     shlptr(cnt, 3); // convert to number of bytes
5344     rep_stosb();
5345   } else if (UseXMMForObjInit) {
5346     xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5347   } else {
5348     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5349     rep_stos();
5350   }
5351 
5352   BIND(DONE);
5353 }
5354 
5355 #endif //COMPILER2_OR_JVMCI
5356 
5357 
5358 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5359                                    Register to, Register value, Register count,
5360                                    Register rtmp, XMMRegister xtmp) {
5361   ShortBranchVerifier sbv(this);
5362   assert_different_registers(to, value, count, rtmp);
5363   Label L_exit;
5364   Label L_fill_2_bytes, L_fill_4_bytes;
5365 
5366   int shift = -1;
5367   switch (t) {
5368     case T_BYTE:
5369       shift = 2;
5370       break;
5371     case T_SHORT:
5372       shift = 1;
5373       break;
5374     case T_INT:
5375       shift = 0;
5376       break;
5377     default: ShouldNotReachHere();
5378   }
5379 
5380   if (t == T_BYTE) {
5381     andl(value, 0xff);
5382     movl(rtmp, value);
5383     shll(rtmp, 8);
5384     orl(value, rtmp);
5385   }
5386   if (t == T_SHORT) {
5387     andl(value, 0xffff);
5388   }
5389   if (t == T_BYTE || t == T_SHORT) {
5390     movl(rtmp, value);
5391     shll(rtmp, 16);
5392     orl(value, rtmp);
5393   }
5394 
5395   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5396   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5397   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5398     Label L_skip_align2;
5399     // align source address at 4 bytes address boundary
5400     if (t == T_BYTE) {
5401       Label L_skip_align1;
5402       // One byte misalignment happens only for byte arrays
5403       testptr(to, 1);
5404       jccb(Assembler::zero, L_skip_align1);
5405       movb(Address(to, 0), value);
5406       increment(to);
5407       decrement(count);
5408       BIND(L_skip_align1);
5409     }
5410     // Two bytes misalignment happens only for byte and short (char) arrays
5411     testptr(to, 2);
5412     jccb(Assembler::zero, L_skip_align2);
5413     movw(Address(to, 0), value);
5414     addptr(to, 2);
5415     subl(count, 1<<(shift-1));
5416     BIND(L_skip_align2);
5417   }
5418   if (UseSSE < 2) {
5419     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5420     // Fill 32-byte chunks
5421     subl(count, 8 << shift);
5422     jcc(Assembler::less, L_check_fill_8_bytes);
5423     align(16);
5424 
5425     BIND(L_fill_32_bytes_loop);
5426 
5427     for (int i = 0; i < 32; i += 4) {
5428       movl(Address(to, i), value);
5429     }
5430 
5431     addptr(to, 32);
5432     subl(count, 8 << shift);
5433     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5434     BIND(L_check_fill_8_bytes);
5435     addl(count, 8 << shift);
5436     jccb(Assembler::zero, L_exit);
5437     jmpb(L_fill_8_bytes);
5438 
5439     //
5440     // length is too short, just fill qwords
5441     //
5442     BIND(L_fill_8_bytes_loop);
5443     movl(Address(to, 0), value);
5444     movl(Address(to, 4), value);
5445     addptr(to, 8);
5446     BIND(L_fill_8_bytes);
5447     subl(count, 1 << (shift + 1));
5448     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5449     // fall through to fill 4 bytes
5450   } else {
5451     Label L_fill_32_bytes;
5452     if (!UseUnalignedLoadStores) {
5453       // align to 8 bytes, we know we are 4 byte aligned to start
5454       testptr(to, 4);
5455       jccb(Assembler::zero, L_fill_32_bytes);
5456       movl(Address(to, 0), value);
5457       addptr(to, 4);
5458       subl(count, 1<<shift);
5459     }
5460     BIND(L_fill_32_bytes);
5461     {
5462       assert( UseSSE >= 2, "supported cpu only" );
5463       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5464       movdl(xtmp, value);
5465       if (UseAVX >= 2 && UseUnalignedLoadStores) {
5466         Label L_check_fill_32_bytes;
5467         if (UseAVX > 2) {
5468           // Fill 64-byte chunks
5469           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
5470 
5471           // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
5472           cmpl(count, AVX3Threshold);
5473           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
5474 
5475           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
5476 
5477           subl(count, 16 << shift);
5478           jccb(Assembler::less, L_check_fill_32_bytes);
5479           align(16);
5480 
5481           BIND(L_fill_64_bytes_loop_avx3);
5482           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
5483           addptr(to, 64);
5484           subl(count, 16 << shift);
5485           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
5486           jmpb(L_check_fill_32_bytes);
5487 
5488           BIND(L_check_fill_64_bytes_avx2);
5489         }
5490         // Fill 64-byte chunks
5491         Label L_fill_64_bytes_loop;
5492         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
5493 
5494         subl(count, 16 << shift);
5495         jcc(Assembler::less, L_check_fill_32_bytes);
5496         align(16);
5497 
5498         BIND(L_fill_64_bytes_loop);
5499         vmovdqu(Address(to, 0), xtmp);
5500         vmovdqu(Address(to, 32), xtmp);
5501         addptr(to, 64);
5502         subl(count, 16 << shift);
5503         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
5504 
5505         BIND(L_check_fill_32_bytes);
5506         addl(count, 8 << shift);
5507         jccb(Assembler::less, L_check_fill_8_bytes);
5508         vmovdqu(Address(to, 0), xtmp);
5509         addptr(to, 32);
5510         subl(count, 8 << shift);
5511 
5512         BIND(L_check_fill_8_bytes);
5513         // clean upper bits of YMM registers
5514         movdl(xtmp, value);
5515         pshufd(xtmp, xtmp, 0);
5516       } else {
5517         // Fill 32-byte chunks
5518         pshufd(xtmp, xtmp, 0);
5519 
5520         subl(count, 8 << shift);
5521         jcc(Assembler::less, L_check_fill_8_bytes);
5522         align(16);
5523 
5524         BIND(L_fill_32_bytes_loop);
5525 
5526         if (UseUnalignedLoadStores) {
5527           movdqu(Address(to, 0), xtmp);
5528           movdqu(Address(to, 16), xtmp);
5529         } else {
5530           movq(Address(to, 0), xtmp);
5531           movq(Address(to, 8), xtmp);
5532           movq(Address(to, 16), xtmp);
5533           movq(Address(to, 24), xtmp);
5534         }
5535 
5536         addptr(to, 32);
5537         subl(count, 8 << shift);
5538         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5539 
5540         BIND(L_check_fill_8_bytes);
5541       }
5542       addl(count, 8 << shift);
5543       jccb(Assembler::zero, L_exit);
5544       jmpb(L_fill_8_bytes);
5545 
5546       //
5547       // length is too short, just fill qwords
5548       //
5549       BIND(L_fill_8_bytes_loop);
5550       movq(Address(to, 0), xtmp);
5551       addptr(to, 8);
5552       BIND(L_fill_8_bytes);
5553       subl(count, 1 << (shift + 1));
5554       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5555     }
5556   }
5557   // fill trailing 4 bytes
5558   BIND(L_fill_4_bytes);
5559   testl(count, 1<<shift);
5560   jccb(Assembler::zero, L_fill_2_bytes);
5561   movl(Address(to, 0), value);
5562   if (t == T_BYTE || t == T_SHORT) {
5563     Label L_fill_byte;
5564     addptr(to, 4);
5565     BIND(L_fill_2_bytes);
5566     // fill trailing 2 bytes
5567     testl(count, 1<<(shift-1));
5568     jccb(Assembler::zero, L_fill_byte);
5569     movw(Address(to, 0), value);
5570     if (t == T_BYTE) {
5571       addptr(to, 2);
5572       BIND(L_fill_byte);
5573       // fill trailing byte
5574       testl(count, 1);
5575       jccb(Assembler::zero, L_exit);
5576       movb(Address(to, 0), value);
5577     } else {
5578       BIND(L_fill_byte);
5579     }
5580   } else {
5581     BIND(L_fill_2_bytes);
5582   }
5583   BIND(L_exit);
5584 }
5585 
5586 // encode char[] to byte[] in ISO_8859_1 or ASCII
5587    //@IntrinsicCandidate
5588    //private static int implEncodeISOArray(byte[] sa, int sp,
5589    //byte[] da, int dp, int len) {
5590    //  int i = 0;
5591    //  for (; i < len; i++) {
5592    //    char c = StringUTF16.getChar(sa, sp++);
5593    //    if (c > '\u00FF')
5594    //      break;
5595    //    da[dp++] = (byte)c;
5596    //  }
5597    //  return i;
5598    //}
5599    //
5600    //@IntrinsicCandidate
5601    //private static int implEncodeAsciiArray(char[] sa, int sp,
5602    //    byte[] da, int dp, int len) {
5603    //  int i = 0;
5604    //  for (; i < len; i++) {
5605    //    char c = sa[sp++];
5606    //    if (c >= '\u0080')
5607    //      break;
5608    //    da[dp++] = (byte)c;
5609    //  }
5610    //  return i;
5611    //}
5612 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
5613   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
5614   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
5615   Register tmp5, Register result, bool ascii) {
5616 
5617   // rsi: src
5618   // rdi: dst
5619   // rdx: len
5620   // rcx: tmp5
5621   // rax: result
5622   ShortBranchVerifier sbv(this);
5623   assert_different_registers(src, dst, len, tmp5, result);
5624   Label L_done, L_copy_1_char, L_copy_1_char_exit;
5625 
5626   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
5627   int short_mask = ascii ? 0xff80 : 0xff00;
5628 
5629   // set result
5630   xorl(result, result);
5631   // check for zero length
5632   testl(len, len);
5633   jcc(Assembler::zero, L_done);
5634 
5635   movl(result, len);
5636 
5637   // Setup pointers
5638   lea(src, Address(src, len, Address::times_2)); // char[]
5639   lea(dst, Address(dst, len, Address::times_1)); // byte[]
5640   negptr(len);
5641 
5642   if (UseSSE42Intrinsics || UseAVX >= 2) {
5643     Label L_copy_8_chars, L_copy_8_chars_exit;
5644     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
5645 
5646     if (UseAVX >= 2) {
5647       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
5648       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5649       movdl(tmp1Reg, tmp5);
5650       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
5651       jmp(L_chars_32_check);
5652 
5653       bind(L_copy_32_chars);
5654       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
5655       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
5656       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5657       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5658       jccb(Assembler::notZero, L_copy_32_chars_exit);
5659       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5660       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
5661       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
5662 
5663       bind(L_chars_32_check);
5664       addptr(len, 32);
5665       jcc(Assembler::lessEqual, L_copy_32_chars);
5666 
5667       bind(L_copy_32_chars_exit);
5668       subptr(len, 16);
5669       jccb(Assembler::greater, L_copy_16_chars_exit);
5670 
5671     } else if (UseSSE42Intrinsics) {
5672       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5673       movdl(tmp1Reg, tmp5);
5674       pshufd(tmp1Reg, tmp1Reg, 0);
5675       jmpb(L_chars_16_check);
5676     }
5677 
5678     bind(L_copy_16_chars);
5679     if (UseAVX >= 2) {
5680       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
5681       vptest(tmp2Reg, tmp1Reg);
5682       jcc(Assembler::notZero, L_copy_16_chars_exit);
5683       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
5684       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
5685     } else {
5686       if (UseAVX > 0) {
5687         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5688         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5689         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
5690       } else {
5691         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5692         por(tmp2Reg, tmp3Reg);
5693         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5694         por(tmp2Reg, tmp4Reg);
5695       }
5696       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5697       jccb(Assembler::notZero, L_copy_16_chars_exit);
5698       packuswb(tmp3Reg, tmp4Reg);
5699     }
5700     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
5701 
5702     bind(L_chars_16_check);
5703     addptr(len, 16);
5704     jcc(Assembler::lessEqual, L_copy_16_chars);
5705 
5706     bind(L_copy_16_chars_exit);
5707     if (UseAVX >= 2) {
5708       // clean upper bits of YMM registers
5709       vpxor(tmp2Reg, tmp2Reg);
5710       vpxor(tmp3Reg, tmp3Reg);
5711       vpxor(tmp4Reg, tmp4Reg);
5712       movdl(tmp1Reg, tmp5);
5713       pshufd(tmp1Reg, tmp1Reg, 0);
5714     }
5715     subptr(len, 8);
5716     jccb(Assembler::greater, L_copy_8_chars_exit);
5717 
5718     bind(L_copy_8_chars);
5719     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
5720     ptest(tmp3Reg, tmp1Reg);
5721     jccb(Assembler::notZero, L_copy_8_chars_exit);
5722     packuswb(tmp3Reg, tmp1Reg);
5723     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
5724     addptr(len, 8);
5725     jccb(Assembler::lessEqual, L_copy_8_chars);
5726 
5727     bind(L_copy_8_chars_exit);
5728     subptr(len, 8);
5729     jccb(Assembler::zero, L_done);
5730   }
5731 
5732   bind(L_copy_1_char);
5733   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
5734   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
5735   jccb(Assembler::notZero, L_copy_1_char_exit);
5736   movb(Address(dst, len, Address::times_1, 0), tmp5);
5737   addptr(len, 1);
5738   jccb(Assembler::less, L_copy_1_char);
5739 
5740   bind(L_copy_1_char_exit);
5741   addptr(result, len); // len is negative count of not processed elements
5742 
5743   bind(L_done);
5744 }
5745 
5746 #ifdef _LP64
5747 /**
5748  * Helper for multiply_to_len().
5749  */
5750 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
5751   addq(dest_lo, src1);
5752   adcq(dest_hi, 0);
5753   addq(dest_lo, src2);
5754   adcq(dest_hi, 0);
5755 }
5756 
5757 /**
5758  * Multiply 64 bit by 64 bit first loop.
5759  */
5760 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
5761                                            Register y, Register y_idx, Register z,
5762                                            Register carry, Register product,
5763                                            Register idx, Register kdx) {
5764   //
5765   //  jlong carry, x[], y[], z[];
5766   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5767   //    huge_128 product = y[idx] * x[xstart] + carry;
5768   //    z[kdx] = (jlong)product;
5769   //    carry  = (jlong)(product >>> 64);
5770   //  }
5771   //  z[xstart] = carry;
5772   //
5773 
5774   Label L_first_loop, L_first_loop_exit;
5775   Label L_one_x, L_one_y, L_multiply;
5776 
5777   decrementl(xstart);
5778   jcc(Assembler::negative, L_one_x);
5779 
5780   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
5781   rorq(x_xstart, 32); // convert big-endian to little-endian
5782 
5783   bind(L_first_loop);
5784   decrementl(idx);
5785   jcc(Assembler::negative, L_first_loop_exit);
5786   decrementl(idx);
5787   jcc(Assembler::negative, L_one_y);
5788   movq(y_idx, Address(y, idx, Address::times_4,  0));
5789   rorq(y_idx, 32); // convert big-endian to little-endian
5790   bind(L_multiply);
5791   movq(product, x_xstart);
5792   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
5793   addq(product, carry);
5794   adcq(rdx, 0);
5795   subl(kdx, 2);
5796   movl(Address(z, kdx, Address::times_4,  4), product);
5797   shrq(product, 32);
5798   movl(Address(z, kdx, Address::times_4,  0), product);
5799   movq(carry, rdx);
5800   jmp(L_first_loop);
5801 
5802   bind(L_one_y);
5803   movl(y_idx, Address(y,  0));
5804   jmp(L_multiply);
5805 
5806   bind(L_one_x);
5807   movl(x_xstart, Address(x,  0));
5808   jmp(L_first_loop);
5809 
5810   bind(L_first_loop_exit);
5811 }
5812 
5813 /**
5814  * Multiply 64 bit by 64 bit and add 128 bit.
5815  */
5816 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
5817                                             Register yz_idx, Register idx,
5818                                             Register carry, Register product, int offset) {
5819   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
5820   //     z[kdx] = (jlong)product;
5821 
5822   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
5823   rorq(yz_idx, 32); // convert big-endian to little-endian
5824   movq(product, x_xstart);
5825   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
5826   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
5827   rorq(yz_idx, 32); // convert big-endian to little-endian
5828 
5829   add2_with_carry(rdx, product, carry, yz_idx);
5830 
5831   movl(Address(z, idx, Address::times_4,  offset+4), product);
5832   shrq(product, 32);
5833   movl(Address(z, idx, Address::times_4,  offset), product);
5834 
5835 }
5836 
5837 /**
5838  * Multiply 128 bit by 128 bit. Unrolled inner loop.
5839  */
5840 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
5841                                              Register yz_idx, Register idx, Register jdx,
5842                                              Register carry, Register product,
5843                                              Register carry2) {
5844   //   jlong carry, x[], y[], z[];
5845   //   int kdx = ystart+1;
5846   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5847   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
5848   //     z[kdx+idx+1] = (jlong)product;
5849   //     jlong carry2  = (jlong)(product >>> 64);
5850   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
5851   //     z[kdx+idx] = (jlong)product;
5852   //     carry  = (jlong)(product >>> 64);
5853   //   }
5854   //   idx += 2;
5855   //   if (idx > 0) {
5856   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
5857   //     z[kdx+idx] = (jlong)product;
5858   //     carry  = (jlong)(product >>> 64);
5859   //   }
5860   //
5861 
5862   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5863 
5864   movl(jdx, idx);
5865   andl(jdx, 0xFFFFFFFC);
5866   shrl(jdx, 2);
5867 
5868   bind(L_third_loop);
5869   subl(jdx, 1);
5870   jcc(Assembler::negative, L_third_loop_exit);
5871   subl(idx, 4);
5872 
5873   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
5874   movq(carry2, rdx);
5875 
5876   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
5877   movq(carry, rdx);
5878   jmp(L_third_loop);
5879 
5880   bind (L_third_loop_exit);
5881 
5882   andl (idx, 0x3);
5883   jcc(Assembler::zero, L_post_third_loop_done);
5884 
5885   Label L_check_1;
5886   subl(idx, 2);
5887   jcc(Assembler::negative, L_check_1);
5888 
5889   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
5890   movq(carry, rdx);
5891 
5892   bind (L_check_1);
5893   addl (idx, 0x2);
5894   andl (idx, 0x1);
5895   subl(idx, 1);
5896   jcc(Assembler::negative, L_post_third_loop_done);
5897 
5898   movl(yz_idx, Address(y, idx, Address::times_4,  0));
5899   movq(product, x_xstart);
5900   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5901   movl(yz_idx, Address(z, idx, Address::times_4,  0));
5902 
5903   add2_with_carry(rdx, product, yz_idx, carry);
5904 
5905   movl(Address(z, idx, Address::times_4,  0), product);
5906   shrq(product, 32);
5907 
5908   shlq(rdx, 32);
5909   orq(product, rdx);
5910   movq(carry, product);
5911 
5912   bind(L_post_third_loop_done);
5913 }
5914 
5915 /**
5916  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
5917  *
5918  */
5919 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
5920                                                   Register carry, Register carry2,
5921                                                   Register idx, Register jdx,
5922                                                   Register yz_idx1, Register yz_idx2,
5923                                                   Register tmp, Register tmp3, Register tmp4) {
5924   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
5925 
5926   //   jlong carry, x[], y[], z[];
5927   //   int kdx = ystart+1;
5928   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5929   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
5930   //     jlong carry2  = (jlong)(tmp3 >>> 64);
5931   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
5932   //     carry  = (jlong)(tmp4 >>> 64);
5933   //     z[kdx+idx+1] = (jlong)tmp3;
5934   //     z[kdx+idx] = (jlong)tmp4;
5935   //   }
5936   //   idx += 2;
5937   //   if (idx > 0) {
5938   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
5939   //     z[kdx+idx] = (jlong)yz_idx1;
5940   //     carry  = (jlong)(yz_idx1 >>> 64);
5941   //   }
5942   //
5943 
5944   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5945 
5946   movl(jdx, idx);
5947   andl(jdx, 0xFFFFFFFC);
5948   shrl(jdx, 2);
5949 
5950   bind(L_third_loop);
5951   subl(jdx, 1);
5952   jcc(Assembler::negative, L_third_loop_exit);
5953   subl(idx, 4);
5954 
5955   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
5956   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
5957   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
5958   rorxq(yz_idx2, yz_idx2, 32);
5959 
5960   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
5961   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
5962 
5963   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
5964   rorxq(yz_idx1, yz_idx1, 32);
5965   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
5966   rorxq(yz_idx2, yz_idx2, 32);
5967 
5968   if (VM_Version::supports_adx()) {
5969     adcxq(tmp3, carry);
5970     adoxq(tmp3, yz_idx1);
5971 
5972     adcxq(tmp4, tmp);
5973     adoxq(tmp4, yz_idx2);
5974 
5975     movl(carry, 0); // does not affect flags
5976     adcxq(carry2, carry);
5977     adoxq(carry2, carry);
5978   } else {
5979     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
5980     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
5981   }
5982   movq(carry, carry2);
5983 
5984   movl(Address(z, idx, Address::times_4, 12), tmp3);
5985   shrq(tmp3, 32);
5986   movl(Address(z, idx, Address::times_4,  8), tmp3);
5987 
5988   movl(Address(z, idx, Address::times_4,  4), tmp4);
5989   shrq(tmp4, 32);
5990   movl(Address(z, idx, Address::times_4,  0), tmp4);
5991 
5992   jmp(L_third_loop);
5993 
5994   bind (L_third_loop_exit);
5995 
5996   andl (idx, 0x3);
5997   jcc(Assembler::zero, L_post_third_loop_done);
5998 
5999   Label L_check_1;
6000   subl(idx, 2);
6001   jcc(Assembler::negative, L_check_1);
6002 
6003   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
6004   rorxq(yz_idx1, yz_idx1, 32);
6005   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
6006   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6007   rorxq(yz_idx2, yz_idx2, 32);
6008 
6009   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6010 
6011   movl(Address(z, idx, Address::times_4,  4), tmp3);
6012   shrq(tmp3, 32);
6013   movl(Address(z, idx, Address::times_4,  0), tmp3);
6014   movq(carry, tmp4);
6015 
6016   bind (L_check_1);
6017   addl (idx, 0x2);
6018   andl (idx, 0x1);
6019   subl(idx, 1);
6020   jcc(Assembler::negative, L_post_third_loop_done);
6021   movl(tmp4, Address(y, idx, Address::times_4,  0));
6022   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
6023   movl(tmp4, Address(z, idx, Address::times_4,  0));
6024 
6025   add2_with_carry(carry2, tmp3, tmp4, carry);
6026 
6027   movl(Address(z, idx, Address::times_4,  0), tmp3);
6028   shrq(tmp3, 32);
6029 
6030   shlq(carry2, 32);
6031   orq(tmp3, carry2);
6032   movq(carry, tmp3);
6033 
6034   bind(L_post_third_loop_done);
6035 }
6036 
6037 /**
6038  * Code for BigInteger::multiplyToLen() instrinsic.
6039  *
6040  * rdi: x
6041  * rax: xlen
6042  * rsi: y
6043  * rcx: ylen
6044  * r8:  z
6045  * r11: zlen
6046  * r12: tmp1
6047  * r13: tmp2
6048  * r14: tmp3
6049  * r15: tmp4
6050  * rbx: tmp5
6051  *
6052  */
6053 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
6054                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6055   ShortBranchVerifier sbv(this);
6056   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6057 
6058   push(tmp1);
6059   push(tmp2);
6060   push(tmp3);
6061   push(tmp4);
6062   push(tmp5);
6063 
6064   push(xlen);
6065   push(zlen);
6066 
6067   const Register idx = tmp1;
6068   const Register kdx = tmp2;
6069   const Register xstart = tmp3;
6070 
6071   const Register y_idx = tmp4;
6072   const Register carry = tmp5;
6073   const Register product  = xlen;
6074   const Register x_xstart = zlen;  // reuse register
6075 
6076   // First Loop.
6077   //
6078   //  final static long LONG_MASK = 0xffffffffL;
6079   //  int xstart = xlen - 1;
6080   //  int ystart = ylen - 1;
6081   //  long carry = 0;
6082   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6083   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6084   //    z[kdx] = (int)product;
6085   //    carry = product >>> 32;
6086   //  }
6087   //  z[xstart] = (int)carry;
6088   //
6089 
6090   movl(idx, ylen);      // idx = ylen;
6091   movl(kdx, zlen);      // kdx = xlen+ylen;
6092   xorq(carry, carry);   // carry = 0;
6093 
6094   Label L_done;
6095 
6096   movl(xstart, xlen);
6097   decrementl(xstart);
6098   jcc(Assembler::negative, L_done);
6099 
6100   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6101 
6102   Label L_second_loop;
6103   testl(kdx, kdx);
6104   jcc(Assembler::zero, L_second_loop);
6105 
6106   Label L_carry;
6107   subl(kdx, 1);
6108   jcc(Assembler::zero, L_carry);
6109 
6110   movl(Address(z, kdx, Address::times_4,  0), carry);
6111   shrq(carry, 32);
6112   subl(kdx, 1);
6113 
6114   bind(L_carry);
6115   movl(Address(z, kdx, Address::times_4,  0), carry);
6116 
6117   // Second and third (nested) loops.
6118   //
6119   // for (int i = xstart-1; i >= 0; i--) { // Second loop
6120   //   carry = 0;
6121   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6122   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6123   //                    (z[k] & LONG_MASK) + carry;
6124   //     z[k] = (int)product;
6125   //     carry = product >>> 32;
6126   //   }
6127   //   z[i] = (int)carry;
6128   // }
6129   //
6130   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6131 
6132   const Register jdx = tmp1;
6133 
6134   bind(L_second_loop);
6135   xorl(carry, carry);    // carry = 0;
6136   movl(jdx, ylen);       // j = ystart+1
6137 
6138   subl(xstart, 1);       // i = xstart-1;
6139   jcc(Assembler::negative, L_done);
6140 
6141   push (z);
6142 
6143   Label L_last_x;
6144   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6145   subl(xstart, 1);       // i = xstart-1;
6146   jcc(Assembler::negative, L_last_x);
6147 
6148   if (UseBMI2Instructions) {
6149     movq(rdx,  Address(x, xstart, Address::times_4,  0));
6150     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6151   } else {
6152     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6153     rorq(x_xstart, 32);  // convert big-endian to little-endian
6154   }
6155 
6156   Label L_third_loop_prologue;
6157   bind(L_third_loop_prologue);
6158 
6159   push (x);
6160   push (xstart);
6161   push (ylen);
6162 
6163 
6164   if (UseBMI2Instructions) {
6165     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6166   } else { // !UseBMI2Instructions
6167     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6168   }
6169 
6170   pop(ylen);
6171   pop(xlen);
6172   pop(x);
6173   pop(z);
6174 
6175   movl(tmp3, xlen);
6176   addl(tmp3, 1);
6177   movl(Address(z, tmp3, Address::times_4,  0), carry);
6178   subl(tmp3, 1);
6179   jccb(Assembler::negative, L_done);
6180 
6181   shrq(carry, 32);
6182   movl(Address(z, tmp3, Address::times_4,  0), carry);
6183   jmp(L_second_loop);
6184 
6185   // Next infrequent code is moved outside loops.
6186   bind(L_last_x);
6187   if (UseBMI2Instructions) {
6188     movl(rdx, Address(x,  0));
6189   } else {
6190     movl(x_xstart, Address(x,  0));
6191   }
6192   jmp(L_third_loop_prologue);
6193 
6194   bind(L_done);
6195 
6196   pop(zlen);
6197   pop(xlen);
6198 
6199   pop(tmp5);
6200   pop(tmp4);
6201   pop(tmp3);
6202   pop(tmp2);
6203   pop(tmp1);
6204 }
6205 
6206 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6207   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6208   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6209   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6210   Label VECTOR8_TAIL, VECTOR4_TAIL;
6211   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6212   Label SAME_TILL_END, DONE;
6213   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6214 
6215   //scale is in rcx in both Win64 and Unix
6216   ShortBranchVerifier sbv(this);
6217 
6218   shlq(length);
6219   xorq(result, result);
6220 
6221   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6222       VM_Version::supports_avx512vlbw()) {
6223     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6224 
6225     cmpq(length, 64);
6226     jcc(Assembler::less, VECTOR32_TAIL);
6227 
6228     movq(tmp1, length);
6229     andq(tmp1, 0x3F);      // tail count
6230     andq(length, ~(0x3F)); //vector count
6231 
6232     bind(VECTOR64_LOOP);
6233     // AVX512 code to compare 64 byte vectors.
6234     evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6235     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6236     kortestql(k7, k7);
6237     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
6238     addq(result, 64);
6239     subq(length, 64);
6240     jccb(Assembler::notZero, VECTOR64_LOOP);
6241 
6242     //bind(VECTOR64_TAIL);
6243     testq(tmp1, tmp1);
6244     jcc(Assembler::zero, SAME_TILL_END);
6245 
6246     //bind(VECTOR64_TAIL);
6247     // AVX512 code to compare upto 63 byte vectors.
6248     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6249     shlxq(tmp2, tmp2, tmp1);
6250     notq(tmp2);
6251     kmovql(k3, tmp2);
6252 
6253     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6254     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6255 
6256     ktestql(k7, k3);
6257     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
6258 
6259     bind(VECTOR64_NOT_EQUAL);
6260     kmovql(tmp1, k7);
6261     notq(tmp1);
6262     tzcntq(tmp1, tmp1);
6263     addq(result, tmp1);
6264     shrq(result);
6265     jmp(DONE);
6266     bind(VECTOR32_TAIL);
6267   }
6268 
6269   cmpq(length, 8);
6270   jcc(Assembler::equal, VECTOR8_LOOP);
6271   jcc(Assembler::less, VECTOR4_TAIL);
6272 
6273   if (UseAVX >= 2) {
6274     Label VECTOR16_TAIL, VECTOR32_LOOP;
6275 
6276     cmpq(length, 16);
6277     jcc(Assembler::equal, VECTOR16_LOOP);
6278     jcc(Assembler::less, VECTOR8_LOOP);
6279 
6280     cmpq(length, 32);
6281     jccb(Assembler::less, VECTOR16_TAIL);
6282 
6283     subq(length, 32);
6284     bind(VECTOR32_LOOP);
6285     vmovdqu(rymm0, Address(obja, result));
6286     vmovdqu(rymm1, Address(objb, result));
6287     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6288     vptest(rymm2, rymm2);
6289     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6290     addq(result, 32);
6291     subq(length, 32);
6292     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6293     addq(length, 32);
6294     jcc(Assembler::equal, SAME_TILL_END);
6295     //falling through if less than 32 bytes left //close the branch here.
6296 
6297     bind(VECTOR16_TAIL);
6298     cmpq(length, 16);
6299     jccb(Assembler::less, VECTOR8_TAIL);
6300     bind(VECTOR16_LOOP);
6301     movdqu(rymm0, Address(obja, result));
6302     movdqu(rymm1, Address(objb, result));
6303     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6304     ptest(rymm2, rymm2);
6305     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6306     addq(result, 16);
6307     subq(length, 16);
6308     jcc(Assembler::equal, SAME_TILL_END);
6309     //falling through if less than 16 bytes left
6310   } else {//regular intrinsics
6311 
6312     cmpq(length, 16);
6313     jccb(Assembler::less, VECTOR8_TAIL);
6314 
6315     subq(length, 16);
6316     bind(VECTOR16_LOOP);
6317     movdqu(rymm0, Address(obja, result));
6318     movdqu(rymm1, Address(objb, result));
6319     pxor(rymm0, rymm1);
6320     ptest(rymm0, rymm0);
6321     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6322     addq(result, 16);
6323     subq(length, 16);
6324     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6325     addq(length, 16);
6326     jcc(Assembler::equal, SAME_TILL_END);
6327     //falling through if less than 16 bytes left
6328   }
6329 
6330   bind(VECTOR8_TAIL);
6331   cmpq(length, 8);
6332   jccb(Assembler::less, VECTOR4_TAIL);
6333   bind(VECTOR8_LOOP);
6334   movq(tmp1, Address(obja, result));
6335   movq(tmp2, Address(objb, result));
6336   xorq(tmp1, tmp2);
6337   testq(tmp1, tmp1);
6338   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6339   addq(result, 8);
6340   subq(length, 8);
6341   jcc(Assembler::equal, SAME_TILL_END);
6342   //falling through if less than 8 bytes left
6343 
6344   bind(VECTOR4_TAIL);
6345   cmpq(length, 4);
6346   jccb(Assembler::less, BYTES_TAIL);
6347   bind(VECTOR4_LOOP);
6348   movl(tmp1, Address(obja, result));
6349   xorl(tmp1, Address(objb, result));
6350   testl(tmp1, tmp1);
6351   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6352   addq(result, 4);
6353   subq(length, 4);
6354   jcc(Assembler::equal, SAME_TILL_END);
6355   //falling through if less than 4 bytes left
6356 
6357   bind(BYTES_TAIL);
6358   bind(BYTES_LOOP);
6359   load_unsigned_byte(tmp1, Address(obja, result));
6360   load_unsigned_byte(tmp2, Address(objb, result));
6361   xorl(tmp1, tmp2);
6362   testl(tmp1, tmp1);
6363   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6364   decq(length);
6365   jcc(Assembler::zero, SAME_TILL_END);
6366   incq(result);
6367   load_unsigned_byte(tmp1, Address(obja, result));
6368   load_unsigned_byte(tmp2, Address(objb, result));
6369   xorl(tmp1, tmp2);
6370   testl(tmp1, tmp1);
6371   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6372   decq(length);
6373   jcc(Assembler::zero, SAME_TILL_END);
6374   incq(result);
6375   load_unsigned_byte(tmp1, Address(obja, result));
6376   load_unsigned_byte(tmp2, Address(objb, result));
6377   xorl(tmp1, tmp2);
6378   testl(tmp1, tmp1);
6379   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6380   jmp(SAME_TILL_END);
6381 
6382   if (UseAVX >= 2) {
6383     bind(VECTOR32_NOT_EQUAL);
6384     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6385     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6386     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6387     vpmovmskb(tmp1, rymm0);
6388     bsfq(tmp1, tmp1);
6389     addq(result, tmp1);
6390     shrq(result);
6391     jmp(DONE);
6392   }
6393 
6394   bind(VECTOR16_NOT_EQUAL);
6395   if (UseAVX >= 2) {
6396     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6397     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6398     pxor(rymm0, rymm2);
6399   } else {
6400     pcmpeqb(rymm2, rymm2);
6401     pxor(rymm0, rymm1);
6402     pcmpeqb(rymm0, rymm1);
6403     pxor(rymm0, rymm2);
6404   }
6405   pmovmskb(tmp1, rymm0);
6406   bsfq(tmp1, tmp1);
6407   addq(result, tmp1);
6408   shrq(result);
6409   jmpb(DONE);
6410 
6411   bind(VECTOR8_NOT_EQUAL);
6412   bind(VECTOR4_NOT_EQUAL);
6413   bsfq(tmp1, tmp1);
6414   shrq(tmp1, 3);
6415   addq(result, tmp1);
6416   bind(BYTES_NOT_EQUAL);
6417   shrq(result);
6418   jmpb(DONE);
6419 
6420   bind(SAME_TILL_END);
6421   mov64(result, -1);
6422 
6423   bind(DONE);
6424 }
6425 
6426 //Helper functions for square_to_len()
6427 
6428 /**
6429  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6430  * Preserves x and z and modifies rest of the registers.
6431  */
6432 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6433   // Perform square and right shift by 1
6434   // Handle odd xlen case first, then for even xlen do the following
6435   // jlong carry = 0;
6436   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6437   //     huge_128 product = x[j:j+1] * x[j:j+1];
6438   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6439   //     z[i+2:i+3] = (jlong)(product >>> 1);
6440   //     carry = (jlong)product;
6441   // }
6442 
6443   xorq(tmp5, tmp5);     // carry
6444   xorq(rdxReg, rdxReg);
6445   xorl(tmp1, tmp1);     // index for x
6446   xorl(tmp4, tmp4);     // index for z
6447 
6448   Label L_first_loop, L_first_loop_exit;
6449 
6450   testl(xlen, 1);
6451   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
6452 
6453   // Square and right shift by 1 the odd element using 32 bit multiply
6454   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
6455   imulq(raxReg, raxReg);
6456   shrq(raxReg, 1);
6457   adcq(tmp5, 0);
6458   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
6459   incrementl(tmp1);
6460   addl(tmp4, 2);
6461 
6462   // Square and  right shift by 1 the rest using 64 bit multiply
6463   bind(L_first_loop);
6464   cmpptr(tmp1, xlen);
6465   jccb(Assembler::equal, L_first_loop_exit);
6466 
6467   // Square
6468   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
6469   rorq(raxReg, 32);    // convert big-endian to little-endian
6470   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
6471 
6472   // Right shift by 1 and save carry
6473   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
6474   rcrq(rdxReg, 1);
6475   rcrq(raxReg, 1);
6476   adcq(tmp5, 0);
6477 
6478   // Store result in z
6479   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
6480   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
6481 
6482   // Update indices for x and z
6483   addl(tmp1, 2);
6484   addl(tmp4, 4);
6485   jmp(L_first_loop);
6486 
6487   bind(L_first_loop_exit);
6488 }
6489 
6490 
6491 /**
6492  * Perform the following multiply add operation using BMI2 instructions
6493  * carry:sum = sum + op1*op2 + carry
6494  * op2 should be in rdx
6495  * op2 is preserved, all other registers are modified
6496  */
6497 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
6498   // assert op2 is rdx
6499   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
6500   addq(sum, carry);
6501   adcq(tmp2, 0);
6502   addq(sum, op1);
6503   adcq(tmp2, 0);
6504   movq(carry, tmp2);
6505 }
6506 
6507 /**
6508  * Perform the following multiply add operation:
6509  * carry:sum = sum + op1*op2 + carry
6510  * Preserves op1, op2 and modifies rest of registers
6511  */
6512 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
6513   // rdx:rax = op1 * op2
6514   movq(raxReg, op2);
6515   mulq(op1);
6516 
6517   //  rdx:rax = sum + carry + rdx:rax
6518   addq(sum, carry);
6519   adcq(rdxReg, 0);
6520   addq(sum, raxReg);
6521   adcq(rdxReg, 0);
6522 
6523   // carry:sum = rdx:sum
6524   movq(carry, rdxReg);
6525 }
6526 
6527 /**
6528  * Add 64 bit long carry into z[] with carry propogation.
6529  * Preserves z and carry register values and modifies rest of registers.
6530  *
6531  */
6532 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
6533   Label L_fourth_loop, L_fourth_loop_exit;
6534 
6535   movl(tmp1, 1);
6536   subl(zlen, 2);
6537   addq(Address(z, zlen, Address::times_4, 0), carry);
6538 
6539   bind(L_fourth_loop);
6540   jccb(Assembler::carryClear, L_fourth_loop_exit);
6541   subl(zlen, 2);
6542   jccb(Assembler::negative, L_fourth_loop_exit);
6543   addq(Address(z, zlen, Address::times_4, 0), tmp1);
6544   jmp(L_fourth_loop);
6545   bind(L_fourth_loop_exit);
6546 }
6547 
6548 /**
6549  * Shift z[] left by 1 bit.
6550  * Preserves x, len, z and zlen registers and modifies rest of the registers.
6551  *
6552  */
6553 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
6554 
6555   Label L_fifth_loop, L_fifth_loop_exit;
6556 
6557   // Fifth loop
6558   // Perform primitiveLeftShift(z, zlen, 1)
6559 
6560   const Register prev_carry = tmp1;
6561   const Register new_carry = tmp4;
6562   const Register value = tmp2;
6563   const Register zidx = tmp3;
6564 
6565   // int zidx, carry;
6566   // long value;
6567   // carry = 0;
6568   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
6569   //    (carry:value)  = (z[i] << 1) | carry ;
6570   //    z[i] = value;
6571   // }
6572 
6573   movl(zidx, zlen);
6574   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
6575 
6576   bind(L_fifth_loop);
6577   decl(zidx);  // Use decl to preserve carry flag
6578   decl(zidx);
6579   jccb(Assembler::negative, L_fifth_loop_exit);
6580 
6581   if (UseBMI2Instructions) {
6582      movq(value, Address(z, zidx, Address::times_4, 0));
6583      rclq(value, 1);
6584      rorxq(value, value, 32);
6585      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6586   }
6587   else {
6588     // clear new_carry
6589     xorl(new_carry, new_carry);
6590 
6591     // Shift z[i] by 1, or in previous carry and save new carry
6592     movq(value, Address(z, zidx, Address::times_4, 0));
6593     shlq(value, 1);
6594     adcl(new_carry, 0);
6595 
6596     orq(value, prev_carry);
6597     rorq(value, 0x20);
6598     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6599 
6600     // Set previous carry = new carry
6601     movl(prev_carry, new_carry);
6602   }
6603   jmp(L_fifth_loop);
6604 
6605   bind(L_fifth_loop_exit);
6606 }
6607 
6608 
6609 /**
6610  * Code for BigInteger::squareToLen() intrinsic
6611  *
6612  * rdi: x
6613  * rsi: len
6614  * r8:  z
6615  * rcx: zlen
6616  * r12: tmp1
6617  * r13: tmp2
6618  * r14: tmp3
6619  * r15: tmp4
6620  * rbx: tmp5
6621  *
6622  */
6623 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6624 
6625   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
6626   push(tmp1);
6627   push(tmp2);
6628   push(tmp3);
6629   push(tmp4);
6630   push(tmp5);
6631 
6632   // First loop
6633   // Store the squares, right shifted one bit (i.e., divided by 2).
6634   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
6635 
6636   // Add in off-diagonal sums.
6637   //
6638   // Second, third (nested) and fourth loops.
6639   // zlen +=2;
6640   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
6641   //    carry = 0;
6642   //    long op2 = x[xidx:xidx+1];
6643   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
6644   //       k -= 2;
6645   //       long op1 = x[j:j+1];
6646   //       long sum = z[k:k+1];
6647   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
6648   //       z[k:k+1] = sum;
6649   //    }
6650   //    add_one_64(z, k, carry, tmp_regs);
6651   // }
6652 
6653   const Register carry = tmp5;
6654   const Register sum = tmp3;
6655   const Register op1 = tmp4;
6656   Register op2 = tmp2;
6657 
6658   push(zlen);
6659   push(len);
6660   addl(zlen,2);
6661   bind(L_second_loop);
6662   xorq(carry, carry);
6663   subl(zlen, 4);
6664   subl(len, 2);
6665   push(zlen);
6666   push(len);
6667   cmpl(len, 0);
6668   jccb(Assembler::lessEqual, L_second_loop_exit);
6669 
6670   // Multiply an array by one 64 bit long.
6671   if (UseBMI2Instructions) {
6672     op2 = rdxReg;
6673     movq(op2, Address(x, len, Address::times_4,  0));
6674     rorxq(op2, op2, 32);
6675   }
6676   else {
6677     movq(op2, Address(x, len, Address::times_4,  0));
6678     rorq(op2, 32);
6679   }
6680 
6681   bind(L_third_loop);
6682   decrementl(len);
6683   jccb(Assembler::negative, L_third_loop_exit);
6684   decrementl(len);
6685   jccb(Assembler::negative, L_last_x);
6686 
6687   movq(op1, Address(x, len, Address::times_4,  0));
6688   rorq(op1, 32);
6689 
6690   bind(L_multiply);
6691   subl(zlen, 2);
6692   movq(sum, Address(z, zlen, Address::times_4,  0));
6693 
6694   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
6695   if (UseBMI2Instructions) {
6696     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
6697   }
6698   else {
6699     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6700   }
6701 
6702   movq(Address(z, zlen, Address::times_4, 0), sum);
6703 
6704   jmp(L_third_loop);
6705   bind(L_third_loop_exit);
6706 
6707   // Fourth loop
6708   // Add 64 bit long carry into z with carry propogation.
6709   // Uses offsetted zlen.
6710   add_one_64(z, zlen, carry, tmp1);
6711 
6712   pop(len);
6713   pop(zlen);
6714   jmp(L_second_loop);
6715 
6716   // Next infrequent code is moved outside loops.
6717   bind(L_last_x);
6718   movl(op1, Address(x, 0));
6719   jmp(L_multiply);
6720 
6721   bind(L_second_loop_exit);
6722   pop(len);
6723   pop(zlen);
6724   pop(len);
6725   pop(zlen);
6726 
6727   // Fifth loop
6728   // Shift z left 1 bit.
6729   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
6730 
6731   // z[zlen-1] |= x[len-1] & 1;
6732   movl(tmp3, Address(x, len, Address::times_4, -4));
6733   andl(tmp3, 1);
6734   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
6735 
6736   pop(tmp5);
6737   pop(tmp4);
6738   pop(tmp3);
6739   pop(tmp2);
6740   pop(tmp1);
6741 }
6742 
6743 /**
6744  * Helper function for mul_add()
6745  * Multiply the in[] by int k and add to out[] starting at offset offs using
6746  * 128 bit by 32 bit multiply and return the carry in tmp5.
6747  * Only quad int aligned length of in[] is operated on in this function.
6748  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
6749  * This function preserves out, in and k registers.
6750  * len and offset point to the appropriate index in "in" & "out" correspondingly
6751  * tmp5 has the carry.
6752  * other registers are temporary and are modified.
6753  *
6754  */
6755 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
6756   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
6757   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6758 
6759   Label L_first_loop, L_first_loop_exit;
6760 
6761   movl(tmp1, len);
6762   shrl(tmp1, 2);
6763 
6764   bind(L_first_loop);
6765   subl(tmp1, 1);
6766   jccb(Assembler::negative, L_first_loop_exit);
6767 
6768   subl(len, 4);
6769   subl(offset, 4);
6770 
6771   Register op2 = tmp2;
6772   const Register sum = tmp3;
6773   const Register op1 = tmp4;
6774   const Register carry = tmp5;
6775 
6776   if (UseBMI2Instructions) {
6777     op2 = rdxReg;
6778   }
6779 
6780   movq(op1, Address(in, len, Address::times_4,  8));
6781   rorq(op1, 32);
6782   movq(sum, Address(out, offset, Address::times_4,  8));
6783   rorq(sum, 32);
6784   if (UseBMI2Instructions) {
6785     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6786   }
6787   else {
6788     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6789   }
6790   // Store back in big endian from little endian
6791   rorq(sum, 0x20);
6792   movq(Address(out, offset, Address::times_4,  8), sum);
6793 
6794   movq(op1, Address(in, len, Address::times_4,  0));
6795   rorq(op1, 32);
6796   movq(sum, Address(out, offset, Address::times_4,  0));
6797   rorq(sum, 32);
6798   if (UseBMI2Instructions) {
6799     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6800   }
6801   else {
6802     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6803   }
6804   // Store back in big endian from little endian
6805   rorq(sum, 0x20);
6806   movq(Address(out, offset, Address::times_4,  0), sum);
6807 
6808   jmp(L_first_loop);
6809   bind(L_first_loop_exit);
6810 }
6811 
6812 /**
6813  * Code for BigInteger::mulAdd() intrinsic
6814  *
6815  * rdi: out
6816  * rsi: in
6817  * r11: offs (out.length - offset)
6818  * rcx: len
6819  * r8:  k
6820  * r12: tmp1
6821  * r13: tmp2
6822  * r14: tmp3
6823  * r15: tmp4
6824  * rbx: tmp5
6825  * Multiply the in[] by word k and add to out[], return the carry in rax
6826  */
6827 void MacroAssembler::mul_add(Register out, Register in, Register offs,
6828    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
6829    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6830 
6831   Label L_carry, L_last_in, L_done;
6832 
6833 // carry = 0;
6834 // for (int j=len-1; j >= 0; j--) {
6835 //    long product = (in[j] & LONG_MASK) * kLong +
6836 //                   (out[offs] & LONG_MASK) + carry;
6837 //    out[offs--] = (int)product;
6838 //    carry = product >>> 32;
6839 // }
6840 //
6841   push(tmp1);
6842   push(tmp2);
6843   push(tmp3);
6844   push(tmp4);
6845   push(tmp5);
6846 
6847   Register op2 = tmp2;
6848   const Register sum = tmp3;
6849   const Register op1 = tmp4;
6850   const Register carry =  tmp5;
6851 
6852   if (UseBMI2Instructions) {
6853     op2 = rdxReg;
6854     movl(op2, k);
6855   }
6856   else {
6857     movl(op2, k);
6858   }
6859 
6860   xorq(carry, carry);
6861 
6862   //First loop
6863 
6864   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
6865   //The carry is in tmp5
6866   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
6867 
6868   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
6869   decrementl(len);
6870   jccb(Assembler::negative, L_carry);
6871   decrementl(len);
6872   jccb(Assembler::negative, L_last_in);
6873 
6874   movq(op1, Address(in, len, Address::times_4,  0));
6875   rorq(op1, 32);
6876 
6877   subl(offs, 2);
6878   movq(sum, Address(out, offs, Address::times_4,  0));
6879   rorq(sum, 32);
6880 
6881   if (UseBMI2Instructions) {
6882     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6883   }
6884   else {
6885     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6886   }
6887 
6888   // Store back in big endian from little endian
6889   rorq(sum, 0x20);
6890   movq(Address(out, offs, Address::times_4,  0), sum);
6891 
6892   testl(len, len);
6893   jccb(Assembler::zero, L_carry);
6894 
6895   //Multiply the last in[] entry, if any
6896   bind(L_last_in);
6897   movl(op1, Address(in, 0));
6898   movl(sum, Address(out, offs, Address::times_4,  -4));
6899 
6900   movl(raxReg, k);
6901   mull(op1); //tmp4 * eax -> edx:eax
6902   addl(sum, carry);
6903   adcl(rdxReg, 0);
6904   addl(sum, raxReg);
6905   adcl(rdxReg, 0);
6906   movl(carry, rdxReg);
6907 
6908   movl(Address(out, offs, Address::times_4,  -4), sum);
6909 
6910   bind(L_carry);
6911   //return tmp5/carry as carry in rax
6912   movl(rax, carry);
6913 
6914   bind(L_done);
6915   pop(tmp5);
6916   pop(tmp4);
6917   pop(tmp3);
6918   pop(tmp2);
6919   pop(tmp1);
6920 }
6921 #endif
6922 
6923 /**
6924  * Emits code to update CRC-32 with a byte value according to constants in table
6925  *
6926  * @param [in,out]crc   Register containing the crc.
6927  * @param [in]val       Register containing the byte to fold into the CRC.
6928  * @param [in]table     Register containing the table of crc constants.
6929  *
6930  * uint32_t crc;
6931  * val = crc_table[(val ^ crc) & 0xFF];
6932  * crc = val ^ (crc >> 8);
6933  *
6934  */
6935 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6936   xorl(val, crc);
6937   andl(val, 0xFF);
6938   shrl(crc, 8); // unsigned shift
6939   xorl(crc, Address(table, val, Address::times_4, 0));
6940 }
6941 
6942 /**
6943  * Fold 128-bit data chunk
6944  */
6945 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
6946   if (UseAVX > 0) {
6947     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
6948     vpclmulldq(xcrc, xK, xcrc); // [63:0]
6949     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
6950     pxor(xcrc, xtmp);
6951   } else {
6952     movdqa(xtmp, xcrc);
6953     pclmulhdq(xtmp, xK);   // [123:64]
6954     pclmulldq(xcrc, xK);   // [63:0]
6955     pxor(xcrc, xtmp);
6956     movdqu(xtmp, Address(buf, offset));
6957     pxor(xcrc, xtmp);
6958   }
6959 }
6960 
6961 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
6962   if (UseAVX > 0) {
6963     vpclmulhdq(xtmp, xK, xcrc);
6964     vpclmulldq(xcrc, xK, xcrc);
6965     pxor(xcrc, xbuf);
6966     pxor(xcrc, xtmp);
6967   } else {
6968     movdqa(xtmp, xcrc);
6969     pclmulhdq(xtmp, xK);
6970     pclmulldq(xcrc, xK);
6971     pxor(xcrc, xbuf);
6972     pxor(xcrc, xtmp);
6973   }
6974 }
6975 
6976 /**
6977  * 8-bit folds to compute 32-bit CRC
6978  *
6979  * uint64_t xcrc;
6980  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
6981  */
6982 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
6983   movdl(tmp, xcrc);
6984   andl(tmp, 0xFF);
6985   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
6986   psrldq(xcrc, 1); // unsigned shift one byte
6987   pxor(xcrc, xtmp);
6988 }
6989 
6990 /**
6991  * uint32_t crc;
6992  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6993  */
6994 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
6995   movl(tmp, crc);
6996   andl(tmp, 0xFF);
6997   shrl(crc, 8);
6998   xorl(crc, Address(table, tmp, Address::times_4, 0));
6999 }
7000 
7001 /**
7002  * @param crc   register containing existing CRC (32-bit)
7003  * @param buf   register pointing to input byte buffer (byte*)
7004  * @param len   register containing number of bytes
7005  * @param table register that will contain address of CRC table
7006  * @param tmp   scratch register
7007  */
7008 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7009   assert_different_registers(crc, buf, len, table, tmp, rax);
7010 
7011   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7012   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7013 
7014   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7015   // context for the registers used, where all instructions below are using 128-bit mode
7016   // On EVEX without VL and BW, these instructions will all be AVX.
7017   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7018   notl(crc); // ~crc
7019   cmpl(len, 16);
7020   jcc(Assembler::less, L_tail);
7021 
7022   // Align buffer to 16 bytes
7023   movl(tmp, buf);
7024   andl(tmp, 0xF);
7025   jccb(Assembler::zero, L_aligned);
7026   subl(tmp,  16);
7027   addl(len, tmp);
7028 
7029   align(4);
7030   BIND(L_align_loop);
7031   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7032   update_byte_crc32(crc, rax, table);
7033   increment(buf);
7034   incrementl(tmp);
7035   jccb(Assembler::less, L_align_loop);
7036 
7037   BIND(L_aligned);
7038   movl(tmp, len); // save
7039   shrl(len, 4);
7040   jcc(Assembler::zero, L_tail_restore);
7041 
7042   // Fold crc into first bytes of vector
7043   movdqa(xmm1, Address(buf, 0));
7044   movdl(rax, xmm1);
7045   xorl(crc, rax);
7046   if (VM_Version::supports_sse4_1()) {
7047     pinsrd(xmm1, crc, 0);
7048   } else {
7049     pinsrw(xmm1, crc, 0);
7050     shrl(crc, 16);
7051     pinsrw(xmm1, crc, 1);
7052   }
7053   addptr(buf, 16);
7054   subl(len, 4); // len > 0
7055   jcc(Assembler::less, L_fold_tail);
7056 
7057   movdqa(xmm2, Address(buf,  0));
7058   movdqa(xmm3, Address(buf, 16));
7059   movdqa(xmm4, Address(buf, 32));
7060   addptr(buf, 48);
7061   subl(len, 3);
7062   jcc(Assembler::lessEqual, L_fold_512b);
7063 
7064   // Fold total 512 bits of polynomial on each iteration,
7065   // 128 bits per each of 4 parallel streams.
7066   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7067 
7068   align32();
7069   BIND(L_fold_512b_loop);
7070   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7071   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7072   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7073   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7074   addptr(buf, 64);
7075   subl(len, 4);
7076   jcc(Assembler::greater, L_fold_512b_loop);
7077 
7078   // Fold 512 bits to 128 bits.
7079   BIND(L_fold_512b);
7080   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7081   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7082   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7083   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7084 
7085   // Fold the rest of 128 bits data chunks
7086   BIND(L_fold_tail);
7087   addl(len, 3);
7088   jccb(Assembler::lessEqual, L_fold_128b);
7089   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7090 
7091   BIND(L_fold_tail_loop);
7092   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7093   addptr(buf, 16);
7094   decrementl(len);
7095   jccb(Assembler::greater, L_fold_tail_loop);
7096 
7097   // Fold 128 bits in xmm1 down into 32 bits in crc register.
7098   BIND(L_fold_128b);
7099   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7100   if (UseAVX > 0) {
7101     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7102     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7103     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7104   } else {
7105     movdqa(xmm2, xmm0);
7106     pclmulqdq(xmm2, xmm1, 0x1);
7107     movdqa(xmm3, xmm0);
7108     pand(xmm3, xmm2);
7109     pclmulqdq(xmm0, xmm3, 0x1);
7110   }
7111   psrldq(xmm1, 8);
7112   psrldq(xmm2, 4);
7113   pxor(xmm0, xmm1);
7114   pxor(xmm0, xmm2);
7115 
7116   // 8 8-bit folds to compute 32-bit CRC.
7117   for (int j = 0; j < 4; j++) {
7118     fold_8bit_crc32(xmm0, table, xmm1, rax);
7119   }
7120   movdl(crc, xmm0); // mov 32 bits to general register
7121   for (int j = 0; j < 4; j++) {
7122     fold_8bit_crc32(crc, table, rax);
7123   }
7124 
7125   BIND(L_tail_restore);
7126   movl(len, tmp); // restore
7127   BIND(L_tail);
7128   andl(len, 0xf);
7129   jccb(Assembler::zero, L_exit);
7130 
7131   // Fold the rest of bytes
7132   align(4);
7133   BIND(L_tail_loop);
7134   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7135   update_byte_crc32(crc, rax, table);
7136   increment(buf);
7137   decrementl(len);
7138   jccb(Assembler::greater, L_tail_loop);
7139 
7140   BIND(L_exit);
7141   notl(crc); // ~c
7142 }
7143 
7144 #ifdef _LP64
7145 // Helper function for AVX 512 CRC32
7146 // Fold 512-bit data chunks
7147 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7148                                              Register pos, int offset) {
7149   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7150   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7151   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7152   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7153   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7154 }
7155 
7156 // Helper function for AVX 512 CRC32
7157 // Compute CRC32 for < 256B buffers
7158 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
7159                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7160                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7161 
7162   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7163   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7164   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7165 
7166   // check if there is enough buffer to be able to fold 16B at a time
7167   cmpl(len, 32);
7168   jcc(Assembler::less, L_less_than_32);
7169 
7170   // if there is, load the constants
7171   movdqu(xmm10, Address(key, 1 * 16));    //rk1 and rk2 in xmm10
7172   movdl(xmm0, crc);                        // get the initial crc value
7173   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7174   pxor(xmm7, xmm0);
7175 
7176   // update the buffer pointer
7177   addl(pos, 16);
7178   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7179   subl(len, 32);
7180   jmp(L_16B_reduction_loop);
7181 
7182   bind(L_less_than_32);
7183   //mov initial crc to the return value. this is necessary for zero - length buffers.
7184   movl(rax, crc);
7185   testl(len, len);
7186   jcc(Assembler::equal, L_cleanup);
7187 
7188   movdl(xmm0, crc);                        //get the initial crc value
7189 
7190   cmpl(len, 16);
7191   jcc(Assembler::equal, L_exact_16_left);
7192   jcc(Assembler::less, L_less_than_16_left);
7193 
7194   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7195   pxor(xmm7, xmm0);                       //xor the initial crc value
7196   addl(pos, 16);
7197   subl(len, 16);
7198   movdqu(xmm10, Address(key, 1 * 16));    // rk1 and rk2 in xmm10
7199   jmp(L_get_last_two_xmms);
7200 
7201   bind(L_less_than_16_left);
7202   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7203   pxor(xmm1, xmm1);
7204   movptr(tmp1, rsp);
7205   movdqu(Address(tmp1, 0 * 16), xmm1);
7206 
7207   cmpl(len, 4);
7208   jcc(Assembler::less, L_only_less_than_4);
7209 
7210   //backup the counter value
7211   movl(tmp2, len);
7212   cmpl(len, 8);
7213   jcc(Assembler::less, L_less_than_8_left);
7214 
7215   //load 8 Bytes
7216   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7217   movq(Address(tmp1, 0 * 16), rax);
7218   addptr(tmp1, 8);
7219   subl(len, 8);
7220   addl(pos, 8);
7221 
7222   bind(L_less_than_8_left);
7223   cmpl(len, 4);
7224   jcc(Assembler::less, L_less_than_4_left);
7225 
7226   //load 4 Bytes
7227   movl(rax, Address(buf, pos, Address::times_1, 0));
7228   movl(Address(tmp1, 0 * 16), rax);
7229   addptr(tmp1, 4);
7230   subl(len, 4);
7231   addl(pos, 4);
7232 
7233   bind(L_less_than_4_left);
7234   cmpl(len, 2);
7235   jcc(Assembler::less, L_less_than_2_left);
7236 
7237   // load 2 Bytes
7238   movw(rax, Address(buf, pos, Address::times_1, 0));
7239   movl(Address(tmp1, 0 * 16), rax);
7240   addptr(tmp1, 2);
7241   subl(len, 2);
7242   addl(pos, 2);
7243 
7244   bind(L_less_than_2_left);
7245   cmpl(len, 1);
7246   jcc(Assembler::less, L_zero_left);
7247 
7248   // load 1 Byte
7249   movb(rax, Address(buf, pos, Address::times_1, 0));
7250   movb(Address(tmp1, 0 * 16), rax);
7251 
7252   bind(L_zero_left);
7253   movdqu(xmm7, Address(rsp, 0));
7254   pxor(xmm7, xmm0);                       //xor the initial crc value
7255 
7256   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7257   movdqu(xmm0, Address(rax, tmp2));
7258   pshufb(xmm7, xmm0);
7259   jmp(L_128_done);
7260 
7261   bind(L_exact_16_left);
7262   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7263   pxor(xmm7, xmm0);                       //xor the initial crc value
7264   jmp(L_128_done);
7265 
7266   bind(L_only_less_than_4);
7267   cmpl(len, 3);
7268   jcc(Assembler::less, L_only_less_than_3);
7269 
7270   // load 3 Bytes
7271   movb(rax, Address(buf, pos, Address::times_1, 0));
7272   movb(Address(tmp1, 0), rax);
7273 
7274   movb(rax, Address(buf, pos, Address::times_1, 1));
7275   movb(Address(tmp1, 1), rax);
7276 
7277   movb(rax, Address(buf, pos, Address::times_1, 2));
7278   movb(Address(tmp1, 2), rax);
7279 
7280   movdqu(xmm7, Address(rsp, 0));
7281   pxor(xmm7, xmm0);                     //xor the initial crc value
7282 
7283   pslldq(xmm7, 0x5);
7284   jmp(L_barrett);
7285   bind(L_only_less_than_3);
7286   cmpl(len, 2);
7287   jcc(Assembler::less, L_only_less_than_2);
7288 
7289   // load 2 Bytes
7290   movb(rax, Address(buf, pos, Address::times_1, 0));
7291   movb(Address(tmp1, 0), rax);
7292 
7293   movb(rax, Address(buf, pos, Address::times_1, 1));
7294   movb(Address(tmp1, 1), rax);
7295 
7296   movdqu(xmm7, Address(rsp, 0));
7297   pxor(xmm7, xmm0);                     //xor the initial crc value
7298 
7299   pslldq(xmm7, 0x6);
7300   jmp(L_barrett);
7301 
7302   bind(L_only_less_than_2);
7303   //load 1 Byte
7304   movb(rax, Address(buf, pos, Address::times_1, 0));
7305   movb(Address(tmp1, 0), rax);
7306 
7307   movdqu(xmm7, Address(rsp, 0));
7308   pxor(xmm7, xmm0);                     //xor the initial crc value
7309 
7310   pslldq(xmm7, 0x7);
7311 }
7312 
7313 /**
7314 * Compute CRC32 using AVX512 instructions
7315 * param crc   register containing existing CRC (32-bit)
7316 * param buf   register pointing to input byte buffer (byte*)
7317 * param len   register containing number of bytes
7318 * param tmp1  scratch register
7319 * param tmp2  scratch register
7320 * return rax  result register
7321 */
7322 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register key, Register tmp1, Register tmp2) {
7323   assert_different_registers(crc, buf, len, key, tmp1, tmp2, rax);
7324 
7325   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7326   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7327   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7328   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7329   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7330 
7331   const Register pos = r12;
7332   push(r12);
7333   subptr(rsp, 16 * 2 + 8);
7334 
7335   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7336   // context for the registers used, where all instructions below are using 128-bit mode
7337   // On EVEX without VL and BW, these instructions will all be AVX.
7338   lea(key, ExternalAddress(StubRoutines::x86::crc_table_avx512_addr()));
7339   notl(crc);
7340   movl(pos, 0);
7341 
7342   // check if smaller than 256B
7343   cmpl(len, 256);
7344   jcc(Assembler::less, L_less_than_256);
7345 
7346   // load the initial crc value
7347   movdl(xmm10, crc);
7348 
7349   // receive the initial 64B data, xor the initial crc value
7350   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7351   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7352   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7353   evbroadcasti32x4(xmm10, Address(key, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7354 
7355   subl(len, 256);
7356   cmpl(len, 256);
7357   jcc(Assembler::less, L_fold_128_B_loop);
7358 
7359   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7360   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7361   evbroadcasti32x4(xmm16, Address(key, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7362   subl(len, 256);
7363 
7364   bind(L_fold_256_B_loop);
7365   addl(pos, 256);
7366   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7367   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7368   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7369   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7370 
7371   subl(len, 256);
7372   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7373 
7374   // Fold 256 into 128
7375   addl(pos, 256);
7376   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7377   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7378   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7379 
7380   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7381   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7382   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7383 
7384   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7385   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7386 
7387   addl(len, 128);
7388   jmp(L_fold_128_B_register);
7389 
7390   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7391   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7392 
7393   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7394   bind(L_fold_128_B_loop);
7395   addl(pos, 128);
7396   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7397   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7398 
7399   subl(len, 128);
7400   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7401 
7402   addl(pos, 128);
7403 
7404   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7405   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7406   bind(L_fold_128_B_register);
7407   evmovdquq(xmm16, Address(key, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7408   evmovdquq(xmm11, Address(key, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7409   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7410   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7411   // save last that has no multiplicand
7412   vextracti64x2(xmm7, xmm4, 3);
7413 
7414   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7415   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7416   // Needed later in reduction loop
7417   movdqu(xmm10, Address(key, 1 * 16));
7418   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7419   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7420 
7421   // Swap 1,0,3,2 - 01 00 11 10
7422   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7423   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7424   vextracti128(xmm5, xmm8, 1);
7425   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7426 
7427   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7428   // instead of a cmp instruction, we use the negative flag with the jl instruction
7429   addl(len, 128 - 16);
7430   jcc(Assembler::less, L_final_reduction_for_128);
7431 
7432   bind(L_16B_reduction_loop);
7433   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7434   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7435   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7436   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7437   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7438   addl(pos, 16);
7439   subl(len, 16);
7440   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7441 
7442   bind(L_final_reduction_for_128);
7443   addl(len, 16);
7444   jcc(Assembler::equal, L_128_done);
7445 
7446   bind(L_get_last_two_xmms);
7447   movdqu(xmm2, xmm7);
7448   addl(pos, len);
7449   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7450   subl(pos, len);
7451 
7452   // get rid of the extra data that was loaded before
7453   // load the shift constant
7454   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7455   movdqu(xmm0, Address(rax, len));
7456   addl(rax, len);
7457 
7458   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7459   //Change mask to 512
7460   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
7461   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
7462 
7463   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
7464   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7465   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7466   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7467   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
7468 
7469   bind(L_128_done);
7470   // compute crc of a 128-bit value
7471   movdqu(xmm10, Address(key, 3 * 16));
7472   movdqu(xmm0, xmm7);
7473 
7474   // 64b fold
7475   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
7476   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
7477   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7478 
7479   // 32b fold
7480   movdqu(xmm0, xmm7);
7481   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
7482   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7483   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7484   jmp(L_barrett);
7485 
7486   bind(L_less_than_256);
7487   kernel_crc32_avx512_256B(crc, buf, len, key, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
7488 
7489   //barrett reduction
7490   bind(L_barrett);
7491   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
7492   movdqu(xmm1, xmm7);
7493   movdqu(xmm2, xmm7);
7494   movdqu(xmm10, Address(key, 4 * 16));
7495 
7496   pclmulqdq(xmm7, xmm10, 0x0);
7497   pxor(xmm7, xmm2);
7498   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
7499   movdqu(xmm2, xmm7);
7500   pclmulqdq(xmm7, xmm10, 0x10);
7501   pxor(xmm7, xmm2);
7502   pxor(xmm7, xmm1);
7503   pextrd(crc, xmm7, 2);
7504 
7505   bind(L_cleanup);
7506   notl(crc); // ~c
7507   addptr(rsp, 16 * 2 + 8);
7508   pop(r12);
7509 }
7510 
7511 // S. Gueron / Information Processing Letters 112 (2012) 184
7512 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
7513 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
7514 // Output: the 64-bit carry-less product of B * CONST
7515 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
7516                                      Register tmp1, Register tmp2, Register tmp3) {
7517   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7518   if (n > 0) {
7519     addq(tmp3, n * 256 * 8);
7520   }
7521   //    Q1 = TABLEExt[n][B & 0xFF];
7522   movl(tmp1, in);
7523   andl(tmp1, 0x000000FF);
7524   shll(tmp1, 3);
7525   addq(tmp1, tmp3);
7526   movq(tmp1, Address(tmp1, 0));
7527 
7528   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7529   movl(tmp2, in);
7530   shrl(tmp2, 8);
7531   andl(tmp2, 0x000000FF);
7532   shll(tmp2, 3);
7533   addq(tmp2, tmp3);
7534   movq(tmp2, Address(tmp2, 0));
7535 
7536   shlq(tmp2, 8);
7537   xorq(tmp1, tmp2);
7538 
7539   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7540   movl(tmp2, in);
7541   shrl(tmp2, 16);
7542   andl(tmp2, 0x000000FF);
7543   shll(tmp2, 3);
7544   addq(tmp2, tmp3);
7545   movq(tmp2, Address(tmp2, 0));
7546 
7547   shlq(tmp2, 16);
7548   xorq(tmp1, tmp2);
7549 
7550   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7551   shrl(in, 24);
7552   andl(in, 0x000000FF);
7553   shll(in, 3);
7554   addq(in, tmp3);
7555   movq(in, Address(in, 0));
7556 
7557   shlq(in, 24);
7558   xorq(in, tmp1);
7559   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7560 }
7561 
7562 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7563                                       Register in_out,
7564                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7565                                       XMMRegister w_xtmp2,
7566                                       Register tmp1,
7567                                       Register n_tmp2, Register n_tmp3) {
7568   if (is_pclmulqdq_supported) {
7569     movdl(w_xtmp1, in_out); // modified blindly
7570 
7571     movl(tmp1, const_or_pre_comp_const_index);
7572     movdl(w_xtmp2, tmp1);
7573     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7574 
7575     movdq(in_out, w_xtmp1);
7576   } else {
7577     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
7578   }
7579 }
7580 
7581 // Recombination Alternative 2: No bit-reflections
7582 // T1 = (CRC_A * U1) << 1
7583 // T2 = (CRC_B * U2) << 1
7584 // C1 = T1 >> 32
7585 // C2 = T2 >> 32
7586 // T1 = T1 & 0xFFFFFFFF
7587 // T2 = T2 & 0xFFFFFFFF
7588 // T1 = CRC32(0, T1)
7589 // T2 = CRC32(0, T2)
7590 // C1 = C1 ^ T1
7591 // C2 = C2 ^ T2
7592 // CRC = C1 ^ C2 ^ CRC_C
7593 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7594                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7595                                      Register tmp1, Register tmp2,
7596                                      Register n_tmp3) {
7597   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7598   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7599   shlq(in_out, 1);
7600   movl(tmp1, in_out);
7601   shrq(in_out, 32);
7602   xorl(tmp2, tmp2);
7603   crc32(tmp2, tmp1, 4);
7604   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
7605   shlq(in1, 1);
7606   movl(tmp1, in1);
7607   shrq(in1, 32);
7608   xorl(tmp2, tmp2);
7609   crc32(tmp2, tmp1, 4);
7610   xorl(in1, tmp2);
7611   xorl(in_out, in1);
7612   xorl(in_out, in2);
7613 }
7614 
7615 // Set N to predefined value
7616 // Subtract from a lenght of a buffer
7617 // execute in a loop:
7618 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
7619 // for i = 1 to N do
7620 //  CRC_A = CRC32(CRC_A, A[i])
7621 //  CRC_B = CRC32(CRC_B, B[i])
7622 //  CRC_C = CRC32(CRC_C, C[i])
7623 // end for
7624 // Recombine
7625 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7626                                        Register in_out1, Register in_out2, Register in_out3,
7627                                        Register tmp1, Register tmp2, Register tmp3,
7628                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7629                                        Register tmp4, Register tmp5,
7630                                        Register n_tmp6) {
7631   Label L_processPartitions;
7632   Label L_processPartition;
7633   Label L_exit;
7634 
7635   bind(L_processPartitions);
7636   cmpl(in_out1, 3 * size);
7637   jcc(Assembler::less, L_exit);
7638     xorl(tmp1, tmp1);
7639     xorl(tmp2, tmp2);
7640     movq(tmp3, in_out2);
7641     addq(tmp3, size);
7642 
7643     bind(L_processPartition);
7644       crc32(in_out3, Address(in_out2, 0), 8);
7645       crc32(tmp1, Address(in_out2, size), 8);
7646       crc32(tmp2, Address(in_out2, size * 2), 8);
7647       addq(in_out2, 8);
7648       cmpq(in_out2, tmp3);
7649       jcc(Assembler::less, L_processPartition);
7650     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7651             w_xtmp1, w_xtmp2, w_xtmp3,
7652             tmp4, tmp5,
7653             n_tmp6);
7654     addq(in_out2, 2 * size);
7655     subl(in_out1, 3 * size);
7656     jmp(L_processPartitions);
7657 
7658   bind(L_exit);
7659 }
7660 #else
7661 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
7662                                      Register tmp1, Register tmp2, Register tmp3,
7663                                      XMMRegister xtmp1, XMMRegister xtmp2) {
7664   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7665   if (n > 0) {
7666     addl(tmp3, n * 256 * 8);
7667   }
7668   //    Q1 = TABLEExt[n][B & 0xFF];
7669   movl(tmp1, in_out);
7670   andl(tmp1, 0x000000FF);
7671   shll(tmp1, 3);
7672   addl(tmp1, tmp3);
7673   movq(xtmp1, Address(tmp1, 0));
7674 
7675   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7676   movl(tmp2, in_out);
7677   shrl(tmp2, 8);
7678   andl(tmp2, 0x000000FF);
7679   shll(tmp2, 3);
7680   addl(tmp2, tmp3);
7681   movq(xtmp2, Address(tmp2, 0));
7682 
7683   psllq(xtmp2, 8);
7684   pxor(xtmp1, xtmp2);
7685 
7686   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7687   movl(tmp2, in_out);
7688   shrl(tmp2, 16);
7689   andl(tmp2, 0x000000FF);
7690   shll(tmp2, 3);
7691   addl(tmp2, tmp3);
7692   movq(xtmp2, Address(tmp2, 0));
7693 
7694   psllq(xtmp2, 16);
7695   pxor(xtmp1, xtmp2);
7696 
7697   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7698   shrl(in_out, 24);
7699   andl(in_out, 0x000000FF);
7700   shll(in_out, 3);
7701   addl(in_out, tmp3);
7702   movq(xtmp2, Address(in_out, 0));
7703 
7704   psllq(xtmp2, 24);
7705   pxor(xtmp1, xtmp2); // Result in CXMM
7706   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7707 }
7708 
7709 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7710                                       Register in_out,
7711                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7712                                       XMMRegister w_xtmp2,
7713                                       Register tmp1,
7714                                       Register n_tmp2, Register n_tmp3) {
7715   if (is_pclmulqdq_supported) {
7716     movdl(w_xtmp1, in_out);
7717 
7718     movl(tmp1, const_or_pre_comp_const_index);
7719     movdl(w_xtmp2, tmp1);
7720     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7721     // Keep result in XMM since GPR is 32 bit in length
7722   } else {
7723     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
7724   }
7725 }
7726 
7727 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7728                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7729                                      Register tmp1, Register tmp2,
7730                                      Register n_tmp3) {
7731   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7732   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7733 
7734   psllq(w_xtmp1, 1);
7735   movdl(tmp1, w_xtmp1);
7736   psrlq(w_xtmp1, 32);
7737   movdl(in_out, w_xtmp1);
7738 
7739   xorl(tmp2, tmp2);
7740   crc32(tmp2, tmp1, 4);
7741   xorl(in_out, tmp2);
7742 
7743   psllq(w_xtmp2, 1);
7744   movdl(tmp1, w_xtmp2);
7745   psrlq(w_xtmp2, 32);
7746   movdl(in1, w_xtmp2);
7747 
7748   xorl(tmp2, tmp2);
7749   crc32(tmp2, tmp1, 4);
7750   xorl(in1, tmp2);
7751   xorl(in_out, in1);
7752   xorl(in_out, in2);
7753 }
7754 
7755 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7756                                        Register in_out1, Register in_out2, Register in_out3,
7757                                        Register tmp1, Register tmp2, Register tmp3,
7758                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7759                                        Register tmp4, Register tmp5,
7760                                        Register n_tmp6) {
7761   Label L_processPartitions;
7762   Label L_processPartition;
7763   Label L_exit;
7764 
7765   bind(L_processPartitions);
7766   cmpl(in_out1, 3 * size);
7767   jcc(Assembler::less, L_exit);
7768     xorl(tmp1, tmp1);
7769     xorl(tmp2, tmp2);
7770     movl(tmp3, in_out2);
7771     addl(tmp3, size);
7772 
7773     bind(L_processPartition);
7774       crc32(in_out3, Address(in_out2, 0), 4);
7775       crc32(tmp1, Address(in_out2, size), 4);
7776       crc32(tmp2, Address(in_out2, size*2), 4);
7777       crc32(in_out3, Address(in_out2, 0+4), 4);
7778       crc32(tmp1, Address(in_out2, size+4), 4);
7779       crc32(tmp2, Address(in_out2, size*2+4), 4);
7780       addl(in_out2, 8);
7781       cmpl(in_out2, tmp3);
7782       jcc(Assembler::less, L_processPartition);
7783 
7784         push(tmp3);
7785         push(in_out1);
7786         push(in_out2);
7787         tmp4 = tmp3;
7788         tmp5 = in_out1;
7789         n_tmp6 = in_out2;
7790 
7791       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7792             w_xtmp1, w_xtmp2, w_xtmp3,
7793             tmp4, tmp5,
7794             n_tmp6);
7795 
7796         pop(in_out2);
7797         pop(in_out1);
7798         pop(tmp3);
7799 
7800     addl(in_out2, 2 * size);
7801     subl(in_out1, 3 * size);
7802     jmp(L_processPartitions);
7803 
7804   bind(L_exit);
7805 }
7806 #endif //LP64
7807 
7808 #ifdef _LP64
7809 // Algorithm 2: Pipelined usage of the CRC32 instruction.
7810 // Input: A buffer I of L bytes.
7811 // Output: the CRC32C value of the buffer.
7812 // Notations:
7813 // Write L = 24N + r, with N = floor (L/24).
7814 // r = L mod 24 (0 <= r < 24).
7815 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
7816 // N quadwords, and R consists of r bytes.
7817 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
7818 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
7819 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
7820 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
7821 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7822                                           Register tmp1, Register tmp2, Register tmp3,
7823                                           Register tmp4, Register tmp5, Register tmp6,
7824                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7825                                           bool is_pclmulqdq_supported) {
7826   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7827   Label L_wordByWord;
7828   Label L_byteByByteProlog;
7829   Label L_byteByByte;
7830   Label L_exit;
7831 
7832   if (is_pclmulqdq_supported ) {
7833     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7834     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
7835 
7836     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7837     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7838 
7839     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7840     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7841     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
7842   } else {
7843     const_or_pre_comp_const_index[0] = 1;
7844     const_or_pre_comp_const_index[1] = 0;
7845 
7846     const_or_pre_comp_const_index[2] = 3;
7847     const_or_pre_comp_const_index[3] = 2;
7848 
7849     const_or_pre_comp_const_index[4] = 5;
7850     const_or_pre_comp_const_index[5] = 4;
7851    }
7852   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7853                     in2, in1, in_out,
7854                     tmp1, tmp2, tmp3,
7855                     w_xtmp1, w_xtmp2, w_xtmp3,
7856                     tmp4, tmp5,
7857                     tmp6);
7858   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7859                     in2, in1, in_out,
7860                     tmp1, tmp2, tmp3,
7861                     w_xtmp1, w_xtmp2, w_xtmp3,
7862                     tmp4, tmp5,
7863                     tmp6);
7864   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7865                     in2, in1, in_out,
7866                     tmp1, tmp2, tmp3,
7867                     w_xtmp1, w_xtmp2, w_xtmp3,
7868                     tmp4, tmp5,
7869                     tmp6);
7870   movl(tmp1, in2);
7871   andl(tmp1, 0x00000007);
7872   negl(tmp1);
7873   addl(tmp1, in2);
7874   addq(tmp1, in1);
7875 
7876   BIND(L_wordByWord);
7877   cmpq(in1, tmp1);
7878   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7879     crc32(in_out, Address(in1, 0), 4);
7880     addq(in1, 4);
7881     jmp(L_wordByWord);
7882 
7883   BIND(L_byteByByteProlog);
7884   andl(in2, 0x00000007);
7885   movl(tmp2, 1);
7886 
7887   BIND(L_byteByByte);
7888   cmpl(tmp2, in2);
7889   jccb(Assembler::greater, L_exit);
7890     crc32(in_out, Address(in1, 0), 1);
7891     incq(in1);
7892     incl(tmp2);
7893     jmp(L_byteByByte);
7894 
7895   BIND(L_exit);
7896 }
7897 #else
7898 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7899                                           Register tmp1, Register  tmp2, Register tmp3,
7900                                           Register tmp4, Register  tmp5, Register tmp6,
7901                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7902                                           bool is_pclmulqdq_supported) {
7903   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7904   Label L_wordByWord;
7905   Label L_byteByByteProlog;
7906   Label L_byteByByte;
7907   Label L_exit;
7908 
7909   if (is_pclmulqdq_supported) {
7910     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7911     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
7912 
7913     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7914     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7915 
7916     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7917     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7918   } else {
7919     const_or_pre_comp_const_index[0] = 1;
7920     const_or_pre_comp_const_index[1] = 0;
7921 
7922     const_or_pre_comp_const_index[2] = 3;
7923     const_or_pre_comp_const_index[3] = 2;
7924 
7925     const_or_pre_comp_const_index[4] = 5;
7926     const_or_pre_comp_const_index[5] = 4;
7927   }
7928   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7929                     in2, in1, in_out,
7930                     tmp1, tmp2, tmp3,
7931                     w_xtmp1, w_xtmp2, w_xtmp3,
7932                     tmp4, tmp5,
7933                     tmp6);
7934   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7935                     in2, in1, in_out,
7936                     tmp1, tmp2, tmp3,
7937                     w_xtmp1, w_xtmp2, w_xtmp3,
7938                     tmp4, tmp5,
7939                     tmp6);
7940   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7941                     in2, in1, in_out,
7942                     tmp1, tmp2, tmp3,
7943                     w_xtmp1, w_xtmp2, w_xtmp3,
7944                     tmp4, tmp5,
7945                     tmp6);
7946   movl(tmp1, in2);
7947   andl(tmp1, 0x00000007);
7948   negl(tmp1);
7949   addl(tmp1, in2);
7950   addl(tmp1, in1);
7951 
7952   BIND(L_wordByWord);
7953   cmpl(in1, tmp1);
7954   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7955     crc32(in_out, Address(in1,0), 4);
7956     addl(in1, 4);
7957     jmp(L_wordByWord);
7958 
7959   BIND(L_byteByByteProlog);
7960   andl(in2, 0x00000007);
7961   movl(tmp2, 1);
7962 
7963   BIND(L_byteByByte);
7964   cmpl(tmp2, in2);
7965   jccb(Assembler::greater, L_exit);
7966     movb(tmp1, Address(in1, 0));
7967     crc32(in_out, tmp1, 1);
7968     incl(in1);
7969     incl(tmp2);
7970     jmp(L_byteByByte);
7971 
7972   BIND(L_exit);
7973 }
7974 #endif // LP64
7975 #undef BIND
7976 #undef BLOCK_COMMENT
7977 
7978 // Compress char[] array to byte[].
7979 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
7980 //   @IntrinsicCandidate
7981 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
7982 //     for (int i = 0; i < len; i++) {
7983 //       int c = src[srcOff++];
7984 //       if (c >>> 8 != 0) {
7985 //         return 0;
7986 //       }
7987 //       dst[dstOff++] = (byte)c;
7988 //     }
7989 //     return len;
7990 //   }
7991 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
7992   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7993   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7994   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
7995   Label copy_chars_loop, return_length, return_zero, done;
7996 
7997   // rsi: src
7998   // rdi: dst
7999   // rdx: len
8000   // rcx: tmp5
8001   // rax: result
8002 
8003   // rsi holds start addr of source char[] to be compressed
8004   // rdi holds start addr of destination byte[]
8005   // rdx holds length
8006 
8007   assert(len != result, "");
8008 
8009   // save length for return
8010   push(len);
8011 
8012   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8013     VM_Version::supports_avx512vlbw() &&
8014     VM_Version::supports_bmi2()) {
8015 
8016     Label copy_32_loop, copy_loop_tail, below_threshold;
8017 
8018     // alignment
8019     Label post_alignment;
8020 
8021     // if length of the string is less than 16, handle it in an old fashioned way
8022     testl(len, -32);
8023     jcc(Assembler::zero, below_threshold);
8024 
8025     // First check whether a character is compressable ( <= 0xFF).
8026     // Create mask to test for Unicode chars inside zmm vector
8027     movl(result, 0x00FF);
8028     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
8029 
8030     testl(len, -64);
8031     jcc(Assembler::zero, post_alignment);
8032 
8033     movl(tmp5, dst);
8034     andl(tmp5, (32 - 1));
8035     negl(tmp5);
8036     andl(tmp5, (32 - 1));
8037 
8038     // bail out when there is nothing to be done
8039     testl(tmp5, 0xFFFFFFFF);
8040     jcc(Assembler::zero, post_alignment);
8041 
8042     // ~(~0 << len), where len is the # of remaining elements to process
8043     movl(result, 0xFFFFFFFF);
8044     shlxl(result, result, tmp5);
8045     notl(result);
8046     kmovdl(mask2, result);
8047 
8048     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8049     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8050     ktestd(mask1, mask2);
8051     jcc(Assembler::carryClear, return_zero);
8052 
8053     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8054 
8055     addptr(src, tmp5);
8056     addptr(src, tmp5);
8057     addptr(dst, tmp5);
8058     subl(len, tmp5);
8059 
8060     bind(post_alignment);
8061     // end of alignment
8062 
8063     movl(tmp5, len);
8064     andl(tmp5, (32 - 1));    // tail count (in chars)
8065     andl(len, ~(32 - 1));    // vector count (in chars)
8066     jcc(Assembler::zero, copy_loop_tail);
8067 
8068     lea(src, Address(src, len, Address::times_2));
8069     lea(dst, Address(dst, len, Address::times_1));
8070     negptr(len);
8071 
8072     bind(copy_32_loop);
8073     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
8074     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8075     kortestdl(mask1, mask1);
8076     jcc(Assembler::carryClear, return_zero);
8077 
8078     // All elements in current processed chunk are valid candidates for
8079     // compression. Write a truncated byte elements to the memory.
8080     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8081     addptr(len, 32);
8082     jcc(Assembler::notZero, copy_32_loop);
8083 
8084     bind(copy_loop_tail);
8085     // bail out when there is nothing to be done
8086     testl(tmp5, 0xFFFFFFFF);
8087     jcc(Assembler::zero, return_length);
8088 
8089     movl(len, tmp5);
8090 
8091     // ~(~0 << len), where len is the # of remaining elements to process
8092     movl(result, 0xFFFFFFFF);
8093     shlxl(result, result, len);
8094     notl(result);
8095 
8096     kmovdl(mask2, result);
8097 
8098     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8099     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8100     ktestd(mask1, mask2);
8101     jcc(Assembler::carryClear, return_zero);
8102 
8103     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8104     jmp(return_length);
8105 
8106     bind(below_threshold);
8107   }
8108 
8109   if (UseSSE42Intrinsics) {
8110     Label copy_32_loop, copy_16, copy_tail;
8111 
8112     movl(result, len);
8113 
8114     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
8115 
8116     // vectored compression
8117     andl(len, 0xfffffff0);    // vector count (in chars)
8118     andl(result, 0x0000000f);    // tail count (in chars)
8119     testl(len, len);
8120     jcc(Assembler::zero, copy_16);
8121 
8122     // compress 16 chars per iter
8123     movdl(tmp1Reg, tmp5);
8124     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8125     pxor(tmp4Reg, tmp4Reg);
8126 
8127     lea(src, Address(src, len, Address::times_2));
8128     lea(dst, Address(dst, len, Address::times_1));
8129     negptr(len);
8130 
8131     bind(copy_32_loop);
8132     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
8133     por(tmp4Reg, tmp2Reg);
8134     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8135     por(tmp4Reg, tmp3Reg);
8136     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
8137     jcc(Assembler::notZero, return_zero);
8138     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
8139     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8140     addptr(len, 16);
8141     jcc(Assembler::notZero, copy_32_loop);
8142 
8143     // compress next vector of 8 chars (if any)
8144     bind(copy_16);
8145     movl(len, result);
8146     andl(len, 0xfffffff8);    // vector count (in chars)
8147     andl(result, 0x00000007);    // tail count (in chars)
8148     testl(len, len);
8149     jccb(Assembler::zero, copy_tail);
8150 
8151     movdl(tmp1Reg, tmp5);
8152     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8153     pxor(tmp3Reg, tmp3Reg);
8154 
8155     movdqu(tmp2Reg, Address(src, 0));
8156     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
8157     jccb(Assembler::notZero, return_zero);
8158     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
8159     movq(Address(dst, 0), tmp2Reg);
8160     addptr(src, 16);
8161     addptr(dst, 8);
8162 
8163     bind(copy_tail);
8164     movl(len, result);
8165   }
8166   // compress 1 char per iter
8167   testl(len, len);
8168   jccb(Assembler::zero, return_length);
8169   lea(src, Address(src, len, Address::times_2));
8170   lea(dst, Address(dst, len, Address::times_1));
8171   negptr(len);
8172 
8173   bind(copy_chars_loop);
8174   load_unsigned_short(result, Address(src, len, Address::times_2));
8175   testl(result, 0xff00);      // check if Unicode char
8176   jccb(Assembler::notZero, return_zero);
8177   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
8178   increment(len);
8179   jcc(Assembler::notZero, copy_chars_loop);
8180 
8181   // if compression succeeded, return length
8182   bind(return_length);
8183   pop(result);
8184   jmpb(done);
8185 
8186   // if compression failed, return 0
8187   bind(return_zero);
8188   xorl(result, result);
8189   addptr(rsp, wordSize);
8190 
8191   bind(done);
8192 }
8193 
8194 // Inflate byte[] array to char[].
8195 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8196 //   @IntrinsicCandidate
8197 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8198 //     for (int i = 0; i < len; i++) {
8199 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8200 //     }
8201 //   }
8202 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8203   XMMRegister tmp1, Register tmp2, KRegister mask) {
8204   Label copy_chars_loop, done, below_threshold, avx3_threshold;
8205   // rsi: src
8206   // rdi: dst
8207   // rdx: len
8208   // rcx: tmp2
8209 
8210   // rsi holds start addr of source byte[] to be inflated
8211   // rdi holds start addr of destination char[]
8212   // rdx holds length
8213   assert_different_registers(src, dst, len, tmp2);
8214   movl(tmp2, len);
8215   if ((UseAVX > 2) && // AVX512
8216     VM_Version::supports_avx512vlbw() &&
8217     VM_Version::supports_bmi2()) {
8218 
8219     Label copy_32_loop, copy_tail;
8220     Register tmp3_aliased = len;
8221 
8222     // if length of the string is less than 16, handle it in an old fashioned way
8223     testl(len, -16);
8224     jcc(Assembler::zero, below_threshold);
8225 
8226     testl(len, -1 * AVX3Threshold);
8227     jcc(Assembler::zero, avx3_threshold);
8228 
8229     // In order to use only one arithmetic operation for the main loop we use
8230     // this pre-calculation
8231     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8232     andl(len, -32);     // vector count
8233     jccb(Assembler::zero, copy_tail);
8234 
8235     lea(src, Address(src, len, Address::times_1));
8236     lea(dst, Address(dst, len, Address::times_2));
8237     negptr(len);
8238 
8239 
8240     // inflate 32 chars per iter
8241     bind(copy_32_loop);
8242     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8243     evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8244     addptr(len, 32);
8245     jcc(Assembler::notZero, copy_32_loop);
8246 
8247     bind(copy_tail);
8248     // bail out when there is nothing to be done
8249     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8250     jcc(Assembler::zero, done);
8251 
8252     // ~(~0 << length), where length is the # of remaining elements to process
8253     movl(tmp3_aliased, -1);
8254     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8255     notl(tmp3_aliased);
8256     kmovdl(mask, tmp3_aliased);
8257     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8258     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8259 
8260     jmp(done);
8261     bind(avx3_threshold);
8262   }
8263   if (UseSSE42Intrinsics) {
8264     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8265 
8266     if (UseAVX > 1) {
8267       andl(tmp2, (16 - 1));
8268       andl(len, -16);
8269       jccb(Assembler::zero, copy_new_tail);
8270     } else {
8271       andl(tmp2, 0x00000007);   // tail count (in chars)
8272       andl(len, 0xfffffff8);    // vector count (in chars)
8273       jccb(Assembler::zero, copy_tail);
8274     }
8275 
8276     // vectored inflation
8277     lea(src, Address(src, len, Address::times_1));
8278     lea(dst, Address(dst, len, Address::times_2));
8279     negptr(len);
8280 
8281     if (UseAVX > 1) {
8282       bind(copy_16_loop);
8283       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8284       vmovdqu(Address(dst, len, Address::times_2), tmp1);
8285       addptr(len, 16);
8286       jcc(Assembler::notZero, copy_16_loop);
8287 
8288       bind(below_threshold);
8289       bind(copy_new_tail);
8290       movl(len, tmp2);
8291       andl(tmp2, 0x00000007);
8292       andl(len, 0xFFFFFFF8);
8293       jccb(Assembler::zero, copy_tail);
8294 
8295       pmovzxbw(tmp1, Address(src, 0));
8296       movdqu(Address(dst, 0), tmp1);
8297       addptr(src, 8);
8298       addptr(dst, 2 * 8);
8299 
8300       jmp(copy_tail, true);
8301     }
8302 
8303     // inflate 8 chars per iter
8304     bind(copy_8_loop);
8305     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
8306     movdqu(Address(dst, len, Address::times_2), tmp1);
8307     addptr(len, 8);
8308     jcc(Assembler::notZero, copy_8_loop);
8309 
8310     bind(copy_tail);
8311     movl(len, tmp2);
8312 
8313     cmpl(len, 4);
8314     jccb(Assembler::less, copy_bytes);
8315 
8316     movdl(tmp1, Address(src, 0));  // load 4 byte chars
8317     pmovzxbw(tmp1, tmp1);
8318     movq(Address(dst, 0), tmp1);
8319     subptr(len, 4);
8320     addptr(src, 4);
8321     addptr(dst, 8);
8322 
8323     bind(copy_bytes);
8324   } else {
8325     bind(below_threshold);
8326   }
8327 
8328   testl(len, len);
8329   jccb(Assembler::zero, done);
8330   lea(src, Address(src, len, Address::times_1));
8331   lea(dst, Address(dst, len, Address::times_2));
8332   negptr(len);
8333 
8334   // inflate 1 char per iter
8335   bind(copy_chars_loop);
8336   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
8337   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
8338   increment(len);
8339   jcc(Assembler::notZero, copy_chars_loop);
8340 
8341   bind(done);
8342 }
8343 
8344 
8345 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8346   switch(type) {
8347     case T_BYTE:
8348     case T_BOOLEAN:
8349       evmovdqub(dst, kmask, src, false, vector_len);
8350       break;
8351     case T_CHAR:
8352     case T_SHORT:
8353       evmovdquw(dst, kmask, src, false, vector_len);
8354       break;
8355     case T_INT:
8356     case T_FLOAT:
8357       evmovdqul(dst, kmask, src, false, vector_len);
8358       break;
8359     case T_LONG:
8360     case T_DOUBLE:
8361       evmovdquq(dst, kmask, src, false, vector_len);
8362       break;
8363     default:
8364       fatal("Unexpected type argument %s", type2name(type));
8365       break;
8366   }
8367 }
8368 
8369 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8370   switch(type) {
8371     case T_BYTE:
8372     case T_BOOLEAN:
8373       evmovdqub(dst, kmask, src, true, vector_len);
8374       break;
8375     case T_CHAR:
8376     case T_SHORT:
8377       evmovdquw(dst, kmask, src, true, vector_len);
8378       break;
8379     case T_INT:
8380     case T_FLOAT:
8381       evmovdqul(dst, kmask, src, true, vector_len);
8382       break;
8383     case T_LONG:
8384     case T_DOUBLE:
8385       evmovdquq(dst, kmask, src, true, vector_len);
8386       break;
8387     default:
8388       fatal("Unexpected type argument %s", type2name(type));
8389       break;
8390   }
8391 }
8392 
8393 #if COMPILER2_OR_JVMCI
8394 
8395 
8396 // Set memory operation for length "less than" 64 bytes.
8397 void MacroAssembler::fill64_masked_avx(uint shift, Register dst, int disp,
8398                                        XMMRegister xmm, KRegister mask, Register length,
8399                                        Register temp, bool use64byteVector) {
8400   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8401   assert(shift != 0, "shift value should be 1 (short),2(int) or 3(long)");
8402   BasicType type[] = { T_BYTE, T_SHORT,  T_INT,   T_LONG};
8403   if (!use64byteVector) {
8404     fill32_avx(dst, disp, xmm);
8405     subptr(length, 32 >> shift);
8406     fill32_masked_avx(shift, dst, disp + 32, xmm, mask, length, temp);
8407   } else {
8408     assert(MaxVectorSize == 64, "vector length != 64");
8409     movl(temp, 1);
8410     shlxl(temp, temp, length);
8411     subptr(temp, 1);
8412     kmovwl(mask, temp);
8413     evmovdqu(type[shift], mask, Address(dst, disp), xmm, Assembler::AVX_512bit);
8414   }
8415 }
8416 
8417 
8418 void MacroAssembler::fill32_masked_avx(uint shift, Register dst, int disp,
8419                                        XMMRegister xmm, KRegister mask, Register length,
8420                                        Register temp) {
8421   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8422   assert(shift != 0, "shift value should be 1 (short), 2(int) or 3(long)");
8423   BasicType type[] = { T_BYTE, T_SHORT,  T_INT,   T_LONG};
8424   movl(temp, 1);
8425   shlxl(temp, temp, length);
8426   subptr(temp, 1);
8427   kmovwl(mask, temp);
8428   evmovdqu(type[shift], mask, Address(dst, disp), xmm, Assembler::AVX_256bit);
8429 }
8430 
8431 
8432 void MacroAssembler::fill32_avx(Register dst, int disp, XMMRegister xmm) {
8433   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8434   vmovdqu(Address(dst, disp), xmm);
8435 }
8436 
8437 void MacroAssembler::fill64_avx(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8438   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8439   BasicType type[] = {T_BYTE,  T_SHORT,  T_INT,   T_LONG};
8440   if (!use64byteVector) {
8441     fill32_avx(dst, disp, xmm);
8442     fill32_avx(dst, disp + 32, xmm);
8443   } else {
8444     evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8445   }
8446 }
8447 
8448 #endif //COMPILER2_OR_JVMCI
8449 
8450 
8451 #ifdef _LP64
8452 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
8453   Label done;
8454   cvttss2sil(dst, src);
8455   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8456   cmpl(dst, 0x80000000); // float_sign_flip
8457   jccb(Assembler::notEqual, done);
8458   subptr(rsp, 8);
8459   movflt(Address(rsp, 0), src);
8460   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
8461   pop(dst);
8462   bind(done);
8463 }
8464 
8465 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
8466   Label done;
8467   cvttsd2sil(dst, src);
8468   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8469   cmpl(dst, 0x80000000); // float_sign_flip
8470   jccb(Assembler::notEqual, done);
8471   subptr(rsp, 8);
8472   movdbl(Address(rsp, 0), src);
8473   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
8474   pop(dst);
8475   bind(done);
8476 }
8477 
8478 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
8479   Label done;
8480   cvttss2siq(dst, src);
8481   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8482   jccb(Assembler::notEqual, done);
8483   subptr(rsp, 8);
8484   movflt(Address(rsp, 0), src);
8485   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
8486   pop(dst);
8487   bind(done);
8488 }
8489 
8490 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
8491   Label done;
8492   cvttsd2siq(dst, src);
8493   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8494   jccb(Assembler::notEqual, done);
8495   subptr(rsp, 8);
8496   movdbl(Address(rsp, 0), src);
8497   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
8498   pop(dst);
8499   bind(done);
8500 }
8501 
8502 void MacroAssembler::cache_wb(Address line)
8503 {
8504   // 64 bit cpus always support clflush
8505   assert(VM_Version::supports_clflush(), "clflush should be available");
8506   bool optimized = VM_Version::supports_clflushopt();
8507   bool no_evict = VM_Version::supports_clwb();
8508 
8509   // prefer clwb (writeback without evict) otherwise
8510   // prefer clflushopt (potentially parallel writeback with evict)
8511   // otherwise fallback on clflush (serial writeback with evict)
8512 
8513   if (optimized) {
8514     if (no_evict) {
8515       clwb(line);
8516     } else {
8517       clflushopt(line);
8518     }
8519   } else {
8520     // no need for fence when using CLFLUSH
8521     clflush(line);
8522   }
8523 }
8524 
8525 void MacroAssembler::cache_wbsync(bool is_pre)
8526 {
8527   assert(VM_Version::supports_clflush(), "clflush should be available");
8528   bool optimized = VM_Version::supports_clflushopt();
8529   bool no_evict = VM_Version::supports_clwb();
8530 
8531   // pick the correct implementation
8532 
8533   if (!is_pre && (optimized || no_evict)) {
8534     // need an sfence for post flush when using clflushopt or clwb
8535     // otherwise no no need for any synchroniaztion
8536 
8537     sfence();
8538   }
8539 }
8540 
8541 #endif // _LP64
8542 
8543 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8544   switch (cond) {
8545     // Note some conditions are synonyms for others
8546     case Assembler::zero:         return Assembler::notZero;
8547     case Assembler::notZero:      return Assembler::zero;
8548     case Assembler::less:         return Assembler::greaterEqual;
8549     case Assembler::lessEqual:    return Assembler::greater;
8550     case Assembler::greater:      return Assembler::lessEqual;
8551     case Assembler::greaterEqual: return Assembler::less;
8552     case Assembler::below:        return Assembler::aboveEqual;
8553     case Assembler::belowEqual:   return Assembler::above;
8554     case Assembler::above:        return Assembler::belowEqual;
8555     case Assembler::aboveEqual:   return Assembler::below;
8556     case Assembler::overflow:     return Assembler::noOverflow;
8557     case Assembler::noOverflow:   return Assembler::overflow;
8558     case Assembler::negative:     return Assembler::positive;
8559     case Assembler::positive:     return Assembler::negative;
8560     case Assembler::parity:       return Assembler::noParity;
8561     case Assembler::noParity:     return Assembler::parity;
8562   }
8563   ShouldNotReachHere(); return Assembler::overflow;
8564 }
8565 
8566 SkipIfEqual::SkipIfEqual(
8567     MacroAssembler* masm, const bool* flag_addr, bool value) {
8568   _masm = masm;
8569   _masm->cmp8(ExternalAddress((address)flag_addr), value);
8570   _masm->jcc(Assembler::equal, _label);
8571 }
8572 
8573 SkipIfEqual::~SkipIfEqual() {
8574   _masm->bind(_label);
8575 }
8576 
8577 // 32-bit Windows has its own fast-path implementation
8578 // of get_thread
8579 #if !defined(WIN32) || defined(_LP64)
8580 
8581 // This is simply a call to Thread::current()
8582 void MacroAssembler::get_thread(Register thread) {
8583   if (thread != rax) {
8584     push(rax);
8585   }
8586   LP64_ONLY(push(rdi);)
8587   LP64_ONLY(push(rsi);)
8588   push(rdx);
8589   push(rcx);
8590 #ifdef _LP64
8591   push(r8);
8592   push(r9);
8593   push(r10);
8594   push(r11);
8595 #endif
8596 
8597   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
8598 
8599 #ifdef _LP64
8600   pop(r11);
8601   pop(r10);
8602   pop(r9);
8603   pop(r8);
8604 #endif
8605   pop(rcx);
8606   pop(rdx);
8607   LP64_ONLY(pop(rsi);)
8608   LP64_ONLY(pop(rdi);)
8609   if (thread != rax) {
8610     mov(thread, rax);
8611     pop(rax);
8612   }
8613 }
8614 
8615 #endif // !WIN32 || _LP64