1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
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  22  *
  23  */
  24 
  25 #ifndef CPU_X86_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 // MacroAssembler extends Assembler by frequently used macros.
  33 //
  34 // Instructions for which a 'better' code sequence exists depending
  35 // on arguments should also go in here.
  36 
  37 class MacroAssembler: public Assembler {
  38   friend class LIR_Assembler;
  39   friend class Runtime1;      // as_Address()
  40 
  41  public:
  42   // Support for VM calls
  43   //
  44   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  45   // may customize this version by overriding it for its purposes (e.g., to save/restore
  46   // additional registers when doing a VM call).
  47 
  48   virtual void call_VM_leaf_base(
  49     address entry_point,               // the entry point
  50     int     number_of_arguments        // the number of arguments to pop after the call
  51   );
  52 
  53  protected:
  54   // This is the base routine called by the different versions of call_VM. The interpreter
  55   // may customize this version by overriding it for its purposes (e.g., to save/restore
  56   // additional registers when doing a VM call).
  57   //
  58   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  59   // returns the register which contains the thread upon return. If a thread register has been
  60   // specified, the return value will correspond to that register. If no last_java_sp is specified
  61   // (noreg) than rsp will be used instead.
  62   virtual void call_VM_base(           // returns the register containing the thread upon return
  63     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  64     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  65     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  66     address  entry_point,              // the entry point
  67     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  68     bool     check_exceptions          // whether to check for pending exceptions after return
  69   );
  70 
  71   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  72 
  73   // helpers for FPU flag access
  74   // tmp is a temporary register, if none is available use noreg
  75   void save_rax   (Register tmp);
  76   void restore_rax(Register tmp);
  77 
  78  public:
  79   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  80 
  81  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82  // The implementation is only non-empty for the InterpreterMacroAssembler,
  83  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84  virtual void check_and_handle_popframe(Register java_thread);
  85  virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   Address as_Address(AddressLiteral adr);
  88   Address as_Address(ArrayAddress adr);
  89 
  90   // Support for NULL-checks
  91   //
  92   // Generates code that causes a NULL OS exception if the content of reg is NULL.
  93   // If the accessed location is M[reg + offset] and the offset is known, provide the
  94   // offset. No explicit code generation is needed if the offset is within a certain
  95   // range (0 <= offset <= page_size).
  96 
  97   void null_check(Register reg, int offset = -1);
  98   static bool needs_explicit_null_check(intptr_t offset);
  99   static bool uses_implicit_null_check(void* address);
 100 
 101   // Required platform-specific helpers for Label::patch_instructions.
 102   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 103   void pd_patch_instruction(address branch, address target, const char* file, int line) {
 104     unsigned char op = branch[0];
 105     assert(op == 0xE8 /* call */ ||
 106         op == 0xE9 /* jmp */ ||
 107         op == 0xEB /* short jmp */ ||
 108         (op & 0xF0) == 0x70 /* short jcc */ ||
 109         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 110         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 111         "Invalid opcode at patch point");
 112 
 113     if (op == 0xEB || (op & 0xF0) == 0x70) {
 114       // short offset operators (jmp and jcc)
 115       char* disp = (char*) &branch[1];
 116       int imm8 = target - (address) &disp[1];
 117       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset at %s:%d", file, line);
 118       *disp = imm8;
 119     } else {
 120       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 121       int imm32 = target - (address) &disp[1];
 122       *disp = imm32;
 123     }
 124   }
 125 
 126   // The following 4 methods return the offset of the appropriate move instruction
 127 
 128   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 129   int load_unsigned_byte(Register dst, Address src);
 130   int load_unsigned_short(Register dst, Address src);
 131 
 132   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 133   int load_signed_byte(Register dst, Address src);
 134   int load_signed_short(Register dst, Address src);
 135 
 136   // Support for sign-extension (hi:lo = extend_sign(lo))
 137   void extend_sign(Register hi, Register lo);
 138 
 139   // Load and store values by size and signed-ness
 140   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 141   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 142 
 143   // Support for inc/dec with optimal instruction selection depending on value
 144 
 145   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 146   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 147 
 148   void decrementl(Address dst, int value = 1);
 149   void decrementl(Register reg, int value = 1);
 150 
 151   void decrementq(Register reg, int value = 1);
 152   void decrementq(Address dst, int value = 1);
 153 
 154   void incrementl(Address dst, int value = 1);
 155   void incrementl(Register reg, int value = 1);
 156 
 157   void incrementq(Register reg, int value = 1);
 158   void incrementq(Address dst, int value = 1);
 159 
 160 #ifdef COMPILER2
 161   // special instructions for EVEX
 162   void setvectmask(Register dst, Register src);
 163   void restorevectmask();
 164 #endif
 165 
 166   // Support optimal SSE move instructions.
 167   void movflt(XMMRegister dst, XMMRegister src) {
 168     if (dst-> encoding() == src->encoding()) return;
 169     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 170     else                       { movss (dst, src); return; }
 171   }
 172   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 173   void movflt(XMMRegister dst, AddressLiteral src);
 174   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 175 
 176   void movdbl(XMMRegister dst, XMMRegister src) {
 177     if (dst-> encoding() == src->encoding()) return;
 178     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 179     else                       { movsd (dst, src); return; }
 180   }
 181 
 182   void movdbl(XMMRegister dst, AddressLiteral src);
 183 
 184   void movdbl(XMMRegister dst, Address src) {
 185     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 186     else                         { movlpd(dst, src); return; }
 187   }
 188   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 189 
 190   void incrementl(AddressLiteral dst);
 191   void incrementl(ArrayAddress dst);
 192 
 193   void incrementq(AddressLiteral dst);
 194 
 195   // Alignment
 196   void align(int modulus);
 197   void align(int modulus, int target);
 198 
 199   void post_call_nop();
 200   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 201   void fat_nop();
 202 
 203   // Stack frame creation/removal
 204   void enter();
 205   void leave();
 206 
 207   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 208   // The pointer will be loaded into the thread register.
 209   void get_thread(Register thread);
 210 
 211 
 212   // Support for VM calls
 213   //
 214   // It is imperative that all calls into the VM are handled via the call_VM macros.
 215   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 216   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 217 
 218 
 219   void call_VM(Register oop_result,
 220                address entry_point,
 221                bool check_exceptions = true);
 222   void call_VM(Register oop_result,
 223                address entry_point,
 224                Register arg_1,
 225                bool check_exceptions = true);
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                Register arg_1, Register arg_2,
 229                bool check_exceptions = true);
 230   void call_VM(Register oop_result,
 231                address entry_point,
 232                Register arg_1, Register arg_2, Register arg_3,
 233                bool check_exceptions = true);
 234 
 235   // Overloadings with last_Java_sp
 236   void call_VM(Register oop_result,
 237                Register last_java_sp,
 238                address entry_point,
 239                int number_of_arguments = 0,
 240                bool check_exceptions = true);
 241   void call_VM(Register oop_result,
 242                Register last_java_sp,
 243                address entry_point,
 244                Register arg_1, bool
 245                check_exceptions = true);
 246   void call_VM(Register oop_result,
 247                Register last_java_sp,
 248                address entry_point,
 249                Register arg_1, Register arg_2,
 250                bool check_exceptions = true);
 251   void call_VM(Register oop_result,
 252                Register last_java_sp,
 253                address entry_point,
 254                Register arg_1, Register arg_2, Register arg_3,
 255                bool check_exceptions = true);
 256 
 257   void get_vm_result  (Register oop_result, Register thread);
 258   void get_vm_result_2(Register metadata_result, Register thread);
 259 
 260   // These always tightly bind to MacroAssembler::call_VM_base
 261   // bypassing the virtual implementation
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 263   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 264   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 265   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 266   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 267 
 268   void call_VM_leaf0(address entry_point);
 269   void call_VM_leaf(address entry_point,
 270                     int number_of_arguments = 0);
 271   void call_VM_leaf(address entry_point,
 272                     Register arg_1);
 273   void call_VM_leaf(address entry_point,
 274                     Register arg_1, Register arg_2);
 275   void call_VM_leaf(address entry_point,
 276                     Register arg_1, Register arg_2, Register arg_3);
 277 
 278   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 279   // bypassing the virtual implementation
 280   void super_call_VM_leaf(address entry_point);
 281   void super_call_VM_leaf(address entry_point, Register arg_1);
 282   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 283   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 284   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 285 
 286   // last Java Frame (fills frame anchor)
 287   void set_last_Java_frame(Register thread,
 288                            Register last_java_sp,
 289                            Register last_java_fp,
 290                            address last_java_pc);
 291 
 292   // thread in the default location (r15_thread on 64bit)
 293   void set_last_Java_frame(Register last_java_sp,
 294                            Register last_java_fp,
 295                            address last_java_pc);
 296 
 297   void reset_last_Java_frame(Register thread, bool clear_fp);
 298 
 299   // thread in the default location (r15_thread on 64bit)
 300   void reset_last_Java_frame(bool clear_fp);
 301 
 302   void oopmap_metadata(int index);
 303 
 304   // jobjects
 305   void clear_jweak_tag(Register possibly_jweak);
 306   void resolve_jobject(Register value, Register thread, Register tmp);
 307 
 308   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 309   void c2bool(Register x);
 310 
 311   // C++ bool manipulation
 312 
 313   void movbool(Register dst, Address src);
 314   void movbool(Address dst, bool boolconst);
 315   void movbool(Address dst, Register src);
 316   void testbool(Register dst);
 317 
 318   void resolve_oop_handle(Register result, Register tmp = rscratch2);
 319   void resolve_weak_handle(Register result, Register tmp);
 320   void load_mirror(Register mirror, Register method, Register tmp = rscratch2);
 321   void load_method_holder_cld(Register rresult, Register rmethod);
 322 
 323   void load_method_holder(Register holder, Register method);
 324 
 325   // oop manipulations
 326   void load_klass(Register dst, Register src);
 327   void store_klass(Register dst, Register src);
 328 
 329   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 330                       Register tmp1, Register thread_tmp);
 331   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 332                        Register tmp1, Register tmp2);
 333 
 334   // Resolves obj access. Result is placed in the same register.
 335   // All other registers are preserved.
 336   void resolve(DecoratorSet decorators, Register obj);
 337 
 338   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 339                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 340   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 341                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 342   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 343                       Register tmp2 = noreg, DecoratorSet decorators = 0);
 344 
 345   // Used for storing NULL. All other oop constants should be
 346   // stored using routines that take a jobject.
 347   void store_heap_oop_null(Address dst);
 348 
 349   void load_prototype_header(Register dst, Register src);
 350 
 351 #ifdef _LP64
 352   void store_klass_gap(Register dst, Register src);
 353 
 354   // This dummy is to prevent a call to store_heap_oop from
 355   // converting a zero (like NULL) into a Register by giving
 356   // the compiler two choices it can't resolve
 357 
 358   void store_heap_oop(Address dst, void* dummy);
 359 
 360   void encode_heap_oop(Register r);
 361   void decode_heap_oop(Register r);
 362   void encode_heap_oop_not_null(Register r);
 363   void decode_heap_oop_not_null(Register r);
 364   void encode_heap_oop_not_null(Register dst, Register src);
 365   void decode_heap_oop_not_null(Register dst, Register src);
 366 
 367   void set_narrow_oop(Register dst, jobject obj);
 368   void set_narrow_oop(Address dst, jobject obj);
 369   void cmp_narrow_oop(Register dst, jobject obj);
 370   void cmp_narrow_oop(Address dst, jobject obj);
 371 
 372   void encode_klass_not_null(Register r);
 373   void decode_klass_not_null(Register r);
 374   void encode_klass_not_null(Register dst, Register src);
 375   void decode_klass_not_null(Register dst, Register src);
 376   void set_narrow_klass(Register dst, Klass* k);
 377   void set_narrow_klass(Address dst, Klass* k);
 378   void cmp_narrow_klass(Register dst, Klass* k);
 379   void cmp_narrow_klass(Address dst, Klass* k);
 380 
 381   // Returns the byte size of the instructions generated by decode_klass_not_null()
 382   // when compressed klass pointers are being used.
 383   static int instr_size_for_decode_klass_not_null();
 384 
 385   // if heap base register is used - reinit it with the correct value
 386   void reinit_heapbase();
 387 
 388   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 389 
 390 #endif // _LP64
 391 
 392   // Int division/remainder for Java
 393   // (as idivl, but checks for special case as described in JVM spec.)
 394   // returns idivl instruction offset for implicit exception handling
 395   int corrected_idivl(Register reg);
 396 
 397   // Long division/remainder for Java
 398   // (as idivq, but checks for special case as described in JVM spec.)
 399   // returns idivq instruction offset for implicit exception handling
 400   int corrected_idivq(Register reg);
 401 
 402   void int3();
 403 
 404   // Long operation macros for a 32bit cpu
 405   // Long negation for Java
 406   void lneg(Register hi, Register lo);
 407 
 408   // Long multiplication for Java
 409   // (destroys contents of eax, ebx, ecx and edx)
 410   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 411 
 412   // Long shifts for Java
 413   // (semantics as described in JVM spec.)
 414   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 415   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 416 
 417   // Long compare for Java
 418   // (semantics as described in JVM spec.)
 419   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 420 
 421 
 422   // misc
 423 
 424   // Sign extension
 425   void sign_extend_short(Register reg);
 426   void sign_extend_byte(Register reg);
 427 
 428   // Division by power of 2, rounding towards 0
 429   void division_with_shift(Register reg, int shift_value);
 430 
 431   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 432   //
 433   // CF (corresponds to C0) if x < y
 434   // PF (corresponds to C2) if unordered
 435   // ZF (corresponds to C3) if x = y
 436   //
 437   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 438   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 439   void fcmp(Register tmp);
 440   // Variant of the above which allows y to be further down the stack
 441   // and which only pops x and y if specified. If pop_right is
 442   // specified then pop_left must also be specified.
 443   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 444 
 445   // Floating-point comparison for Java
 446   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 447   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 448   // (semantics as described in JVM spec.)
 449   void fcmp2int(Register dst, bool unordered_is_less);
 450   // Variant of the above which allows y to be further down the stack
 451   // and which only pops x and y if specified. If pop_right is
 452   // specified then pop_left must also be specified.
 453   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 454 
 455   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 456   // tmp is a temporary register, if none is available use noreg
 457   void fremr(Register tmp);
 458 
 459   // dst = c = a * b + c
 460   void fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 461   void fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c);
 462 
 463   void vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 464   void vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len);
 465   void vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 466   void vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len);
 467 
 468 
 469   // same as fcmp2int, but using SSE2
 470   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 471   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 472 
 473   // branch to L if FPU flag C2 is set/not set
 474   // tmp is a temporary register, if none is available use noreg
 475   void jC2 (Register tmp, Label& L);
 476   void jnC2(Register tmp, Label& L);
 477 
 478   // Pop ST (ffree & fincstp combined)
 479   void fpop();
 480 
 481   // Load float value from 'address'. If UseSSE >= 1, the value is loaded into
 482   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 483   void load_float(Address src);
 484 
 485   // Store float value to 'address'. If UseSSE >= 1, the value is stored
 486   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 487   void store_float(Address dst);
 488 
 489   // Load double value from 'address'. If UseSSE >= 2, the value is loaded into
 490   // register xmm0. Otherwise, the value is loaded onto the FPU stack.
 491   void load_double(Address src);
 492 
 493   // Store double value to 'address'. If UseSSE >= 2, the value is stored
 494   // from register xmm0. Otherwise, the value is stored from the FPU stack.
 495   void store_double(Address dst);
 496 
 497   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 498   void push_fTOS();
 499 
 500   // pops double TOS element from CPU stack and pushes on FPU stack
 501   void pop_fTOS();
 502 
 503   void empty_FPU_stack();
 504 
 505   void push_IU_state();
 506   void pop_IU_state();
 507 
 508   void push_FPU_state();
 509   void pop_FPU_state();
 510 
 511   void push_CPU_state();
 512   void pop_CPU_state();
 513 
 514   void get_cont_fastpath(Register java_thread, Register dst);
 515   void set_cont_fastpath(Register java_thread, int32_t imm);
 516   DEBUG_ONLY(void stop_if_in_cont(Register cont_reg, const char* name);)
 517 
 518   // Round up to a power of two
 519   void round_to(Register reg, int modulus);
 520 
 521   // Callee saved registers handling
 522   void push_callee_saved_registers();
 523   void pop_callee_saved_registers();
 524 
 525   // allocation
 526   void eden_allocate(
 527     Register thread,                   // Current thread
 528     Register obj,                      // result: pointer to object after successful allocation
 529     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 530     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 531     Register t1,                       // temp register
 532     Label&   slow_case                 // continuation point if fast allocation fails
 533   );
 534   void tlab_allocate(
 535     Register thread,                   // Current thread
 536     Register obj,                      // result: pointer to object after successful allocation
 537     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 538     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 539     Register t1,                       // temp register
 540     Register t2,                       // temp register
 541     Label&   slow_case                 // continuation point if fast allocation fails
 542   );
 543   void zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp);
 544 
 545   // interface method calling
 546   void lookup_interface_method(Register recv_klass,
 547                                Register intf_klass,
 548                                RegisterOrConstant itable_index,
 549                                Register method_result,
 550                                Register scan_temp,
 551                                Label& no_such_interface,
 552                                bool return_method = true);
 553 
 554   // virtual method calling
 555   void lookup_virtual_method(Register recv_klass,
 556                              RegisterOrConstant vtable_index,
 557                              Register method_result);
 558 
 559   // Test sub_klass against super_klass, with fast and slow paths.
 560 
 561   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 562   // One of the three labels can be NULL, meaning take the fall-through.
 563   // If super_check_offset is -1, the value is loaded up from super_klass.
 564   // No registers are killed, except temp_reg.
 565   void check_klass_subtype_fast_path(Register sub_klass,
 566                                      Register super_klass,
 567                                      Register temp_reg,
 568                                      Label* L_success,
 569                                      Label* L_failure,
 570                                      Label* L_slow_path,
 571                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 572 
 573   // The rest of the type check; must be wired to a corresponding fast path.
 574   // It does not repeat the fast path logic, so don't use it standalone.
 575   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 576   // Updates the sub's secondary super cache as necessary.
 577   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 578   void check_klass_subtype_slow_path(Register sub_klass,
 579                                      Register super_klass,
 580                                      Register temp_reg,
 581                                      Register temp2_reg,
 582                                      Label* L_success,
 583                                      Label* L_failure,
 584                                      bool set_cond_codes = false);
 585 
 586   // Simplified, combined version, good for typical uses.
 587   // Falls through on failure.
 588   void check_klass_subtype(Register sub_klass,
 589                            Register super_klass,
 590                            Register temp_reg,
 591                            Label& L_success);
 592 
 593   void clinit_barrier(Register klass,
 594                       Register thread,
 595                       Label* L_fast_path = NULL,
 596                       Label* L_slow_path = NULL);
 597 
 598   // method handles (JSR 292)
 599   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 600 
 601   //----
 602   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 603 
 604   // Debugging
 605 
 606   // only if +VerifyOops
 607   // TODO: Make these macros with file and line like sparc version!
 608   void verify_oop(Register reg, const char* s = "broken oop");
 609   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 610 
 611   // TODO: verify method and klass metadata (compare against vptr?)
 612   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 613   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 614 
 615 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 616 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 617 
 618   // only if +VerifyFPU
 619   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 620 
 621   // Verify or restore cpu control state after JNI call
 622   void restore_cpu_control_state_after_jni();
 623 
 624   // prints msg, dumps registers and stops execution
 625   void stop(const char* msg);
 626 
 627   // prints msg and continues
 628   void warn(const char* msg);
 629 
 630   // dumps registers and other state
 631   void print_state();
 632 
 633   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 634   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 635   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 636   static void print_state64(int64_t pc, int64_t regs[]);
 637 
 638   void os_breakpoint();
 639 
 640   void untested()                                { stop("untested"); }
 641 
 642   void unimplemented(const char* what = "");
 643 
 644   void should_not_reach_here()                   { stop("should not reach here"); }
 645 
 646   void print_CPU_state();
 647 
 648   // Stack overflow checking
 649   void bang_stack_with_offset(int offset) {
 650     // stack grows down, caller passes positive offset
 651     assert(offset > 0, "must bang with negative offset");
 652     movl(Address(rsp, (-offset)), rax);
 653   }
 654 
 655   // Writes to stack successive pages until offset reached to check for
 656   // stack overflow + shadow pages.  Also, clobbers tmp
 657   void bang_stack_size(Register size, Register tmp);
 658 
 659   // Check for reserved stack access in method being exited (for JIT)
 660   void reserved_stack_check();
 661 
 662   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 663                                                 Register tmp,
 664                                                 int offset);
 665 
 666   // If thread_reg is != noreg the code assumes the register passed contains
 667   // the thread (required on 64 bit).
 668   void safepoint_poll(Label& slow_path, Register thread_reg, Register temp_reg);
 669 
 670   void verify_tlab();
 671 
 672   // Biased locking support
 673   // lock_reg and obj_reg must be loaded up with the appropriate values.
 674   // swap_reg must be rax, and is killed.
 675   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 676   // be killed; if not supplied, push/pop will be used internally to
 677   // allocate a temporary (inefficient, avoid if possible).
 678   // Optional slow case is for implementations (interpreter and C1) which branch to
 679   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 680   // Returns offset of first potentially-faulting instruction for null
 681   // check info (currently consumed only by C1). If
 682   // swap_reg_contains_mark is true then returns -1 as it is assumed
 683   // the calling code has already passed any potential faults.
 684   int biased_locking_enter(Register lock_reg, Register obj_reg,
 685                            Register swap_reg, Register tmp_reg,
 686                            bool swap_reg_contains_mark,
 687                            Label& done, Label* slow_case = NULL,
 688                            BiasedLockingCounters* counters = NULL);
 689   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 690 #ifdef COMPILER2
 691   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 692   // See full desription in macroAssembler_x86.cpp.
 693   void fast_lock(Register obj, Register box, Register tmp,
 694                  Register scr, Register cx1, Register cx2,
 695                  BiasedLockingCounters* counters,
 696                  RTMLockingCounters* rtm_counters,
 697                  RTMLockingCounters* stack_rtm_counters,
 698                  Metadata* method_data,
 699                  bool use_rtm, bool profile_rtm);
 700   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 701 #if INCLUDE_RTM_OPT
 702   void rtm_counters_update(Register abort_status, Register rtm_counters);
 703   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 704   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 705                                    RTMLockingCounters* rtm_counters,
 706                                    Metadata* method_data);
 707   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 708                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 709   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 710   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 711   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 712                          Register retry_on_abort_count,
 713                          RTMLockingCounters* stack_rtm_counters,
 714                          Metadata* method_data, bool profile_rtm,
 715                          Label& DONE_LABEL, Label& IsInflated);
 716   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 717                             Register scr, Register retry_on_busy_count,
 718                             Register retry_on_abort_count,
 719                             RTMLockingCounters* rtm_counters,
 720                             Metadata* method_data, bool profile_rtm,
 721                             Label& DONE_LABEL);
 722 #endif
 723 #endif
 724 
 725   Condition negate_condition(Condition cond);
 726 
 727   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 728   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 729   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 730   // here in MacroAssembler. The major exception to this rule is call
 731 
 732   // Arithmetics
 733 
 734 
 735   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 736   void addptr(Address dst, Register src);
 737 
 738   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 739   void addptr(Register dst, int32_t src);
 740   void addptr(Register dst, Register src);
 741   void addptr(Register dst, RegisterOrConstant src) {
 742     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 743     else                   addptr(dst,       src.as_register());
 744   }
 745 
 746   void andptr(Register dst, int32_t src);
 747   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 748 
 749   void cmp8(AddressLiteral src1, int imm);
 750 
 751   // renamed to drag out the casting of address to int32_t/intptr_t
 752   void cmp32(Register src1, int32_t imm);
 753 
 754   void cmp32(AddressLiteral src1, int32_t imm);
 755   // compare reg - mem, or reg - &mem
 756   void cmp32(Register src1, AddressLiteral src2);
 757 
 758   void cmp32(Register src1, Address src2);
 759 
 760 #ifndef _LP64
 761   void cmpklass(Address dst, Metadata* obj);
 762   void cmpklass(Register dst, Metadata* obj);
 763   void cmpoop(Address dst, jobject obj);
 764   void cmpoop_raw(Address dst, jobject obj);
 765 #endif // _LP64
 766 
 767   void cmpoop(Register src1, Register src2);
 768   void cmpoop(Register src1, Address src2);
 769   void cmpoop(Register dst, jobject obj);
 770   void cmpoop_raw(Register dst, jobject obj);
 771 
 772   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 773   void cmpptr(Address src1, AddressLiteral src2);
 774 
 775   void cmpptr(Register src1, AddressLiteral src2);
 776 
 777   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 778   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 779   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 780 
 781   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 782   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 783 
 784   // cmp64 to avoild hiding cmpq
 785   void cmp64(Register src1, AddressLiteral src);
 786 
 787   void cmpxchgptr(Register reg, Address adr);
 788 
 789   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 790 
 791 
 792   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 793   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 794 
 795 
 796   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 797 
 798   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 799 
 800   void shlptr(Register dst, int32_t shift);
 801   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 802 
 803   void shrptr(Register dst, int32_t shift);
 804   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 805 
 806   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 807   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 808 
 809   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 810 
 811   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 812   void subptr(Register dst, int32_t src);
 813   // Force generation of a 4 byte immediate value even if it fits into 8bit
 814   void subptr_imm32(Register dst, int32_t src);
 815   void subptr(Register dst, Register src);
 816   void subptr(Register dst, RegisterOrConstant src) {
 817     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 818     else                   subptr(dst,       src.as_register());
 819   }
 820 
 821   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 822   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 823 
 824   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 825   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 826 
 827   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 828 
 829 
 830 
 831   // Helper functions for statistics gathering.
 832   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 833   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 834   // Unconditional atomic increment.
 835   void atomic_incl(Address counter_addr);
 836   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 837 #ifdef _LP64
 838   void atomic_incq(Address counter_addr);
 839   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 840 #endif
 841   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 842   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 843 
 844   void lea(Register dst, AddressLiteral adr);
 845   void lea(Address dst, AddressLiteral adr);
 846   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 847 
 848   void leal32(Register dst, Address src) { leal(dst, src); }
 849 
 850   // Import other testl() methods from the parent class or else
 851   // they will be hidden by the following overriding declaration.
 852   using Assembler::testl;
 853   void testl(Register dst, AddressLiteral src);
 854 
 855   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 856   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 857   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 858   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 859 
 860   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 861   void testptr(Register src1, Address src2) { LP64_ONLY(testq(src1, src2)) NOT_LP64(testl(src1, src2)); }
 862   void testptr(Register src1, Register src2);
 863 
 864   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 865   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 866 
 867   // Calls
 868 
 869   void call(Label& L, relocInfo::relocType rtype);
 870   void call(Register entry);
 871 
 872   // NOTE: this call transfers to the effective address of entry NOT
 873   // the address contained by entry. This is because this is more natural
 874   // for jumps/calls.
 875   void call(AddressLiteral entry);
 876 
 877   // Emit the CompiledIC call idiom
 878   void ic_call(address entry, jint method_index = 0);
 879 
 880   // Jumps
 881 
 882   // NOTE: these jumps tranfer to the effective address of dst NOT
 883   // the address contained by dst. This is because this is more natural
 884   // for jumps/calls.
 885   void jump(AddressLiteral dst);
 886   void jump_cc(Condition cc, AddressLiteral dst);
 887 
 888   // 32bit can do a case table jump in one instruction but we no longer allow the base
 889   // to be installed in the Address class. This jump will tranfers to the address
 890   // contained in the location described by entry (not the address of entry)
 891   void jump(ArrayAddress entry);
 892 
 893   // Floating
 894 
 895   void push_f(XMMRegister r);
 896   void pop_f(XMMRegister r);
 897   void push_d(XMMRegister r);
 898   void pop_d(XMMRegister r);
 899 
 900   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 901   void andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
 902   void andpd(XMMRegister dst, XMMRegister src) { Assembler::andpd(dst, src); }
 903 
 904   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 905   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 906   void andps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
 907 
 908   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 909   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 910   void comiss(XMMRegister dst, AddressLiteral src);
 911 
 912   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 913   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 914   void comisd(XMMRegister dst, AddressLiteral src);
 915 
 916   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 917   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 918 
 919   void fldcw(Address src) { Assembler::fldcw(src); }
 920   void fldcw(AddressLiteral src);
 921 
 922   void fld_s(int index)   { Assembler::fld_s(index); }
 923   void fld_s(Address src) { Assembler::fld_s(src); }
 924   void fld_s(AddressLiteral src);
 925 
 926   void fld_d(Address src) { Assembler::fld_d(src); }
 927   void fld_d(AddressLiteral src);
 928 
 929   void fld_x(Address src) { Assembler::fld_x(src); }
 930   void fld_x(AddressLiteral src);
 931 
 932   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 933   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 934 
 935   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 936   void ldmxcsr(AddressLiteral src);
 937 
 938 #ifdef _LP64
 939  private:
 940   void sha256_AVX2_one_round_compute(
 941     Register  reg_old_h,
 942     Register  reg_a,
 943     Register  reg_b,
 944     Register  reg_c,
 945     Register  reg_d,
 946     Register  reg_e,
 947     Register  reg_f,
 948     Register  reg_g,
 949     Register  reg_h,
 950     int iter);
 951   void sha256_AVX2_four_rounds_compute_first(int start);
 952   void sha256_AVX2_four_rounds_compute_last(int start);
 953   void sha256_AVX2_one_round_and_sched(
 954         XMMRegister xmm_0,     /* == ymm4 on 0, 1, 2, 3 iterations, then rotate 4 registers left on 4, 8, 12 iterations */
 955         XMMRegister xmm_1,     /* ymm5 */  /* full cycle is 16 iterations */
 956         XMMRegister xmm_2,     /* ymm6 */
 957         XMMRegister xmm_3,     /* ymm7 */
 958         Register    reg_a,      /* == eax on 0 iteration, then rotate 8 register right on each next iteration */
 959         Register    reg_b,      /* ebx */    /* full cycle is 8 iterations */
 960         Register    reg_c,      /* edi */
 961         Register    reg_d,      /* esi */
 962         Register    reg_e,      /* r8d */
 963         Register    reg_f,      /* r9d */
 964         Register    reg_g,      /* r10d */
 965         Register    reg_h,      /* r11d */
 966         int iter);
 967 
 968   void addm(int disp, Register r1, Register r2);
 969   void gfmul(XMMRegister tmp0, XMMRegister t);
 970   void schoolbookAAD(int i, Register subkeyH, XMMRegister data, XMMRegister tmp0,
 971                      XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3);
 972   void generateHtbl_one_block(Register htbl);
 973   void generateHtbl_eight_blocks(Register htbl);
 974  public:
 975   void sha256_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 976                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 977                    Register buf, Register state, Register ofs, Register limit, Register rsp,
 978                    bool multi_block, XMMRegister shuf_mask);
 979   void avx_ghash(Register state, Register htbl, Register data, Register blocks);
 980 #endif
 981 
 982 #ifdef _LP64
 983  private:
 984   void sha512_AVX2_one_round_compute(Register old_h, Register a, Register b, Register c, Register d,
 985                                      Register e, Register f, Register g, Register h, int iteration);
 986 
 987   void sha512_AVX2_one_round_and_schedule(XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
 988                                           Register a, Register b, Register c, Register d, Register e, Register f,
 989                                           Register g, Register h, int iteration);
 990 
 991   void addmq(int disp, Register r1, Register r2);
 992  public:
 993   void sha512_AVX2(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
 994                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
 995                    Register buf, Register state, Register ofs, Register limit, Register rsp, bool multi_block,
 996                    XMMRegister shuf_mask);
 997 #endif
 998 
 999   void fast_sha1(XMMRegister abcd, XMMRegister e0, XMMRegister e1, XMMRegister msg0,
1000                  XMMRegister msg1, XMMRegister msg2, XMMRegister msg3, XMMRegister shuf_mask,
1001                  Register buf, Register state, Register ofs, Register limit, Register rsp,
1002                  bool multi_block);
1003 
1004 #ifdef _LP64
1005   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1006                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1007                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1008                    bool multi_block, XMMRegister shuf_mask);
1009 #else
1010   void fast_sha256(XMMRegister msg, XMMRegister state0, XMMRegister state1, XMMRegister msgtmp0,
1011                    XMMRegister msgtmp1, XMMRegister msgtmp2, XMMRegister msgtmp3, XMMRegister msgtmp4,
1012                    Register buf, Register state, Register ofs, Register limit, Register rsp,
1013                    bool multi_block);
1014 #endif
1015 
1016   void fast_exp(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1017                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1018                 Register rax, Register rcx, Register rdx, Register tmp);
1019 
1020 #ifdef _LP64
1021   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1022                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1023                 Register rax, Register rcx, Register rdx, Register tmp1, Register tmp2);
1024 
1025   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1026                   XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1027                   Register rax, Register rcx, Register rdx, Register r11);
1028 
1029   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1030                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1031                 Register rdx, Register tmp1, Register tmp2, Register tmp3, Register tmp4);
1032 
1033   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1034                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1035                 Register rax, Register rbx, Register rcx, Register rdx, Register tmp1, Register tmp2,
1036                 Register tmp3, Register tmp4);
1037 
1038   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1039                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1040                 Register rax, Register rcx, Register rdx, Register tmp1,
1041                 Register tmp2, Register tmp3, Register tmp4);
1042   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1043                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1044                 Register rax, Register rcx, Register rdx, Register tmp1,
1045                 Register tmp2, Register tmp3, Register tmp4);
1046 #else
1047   void fast_log(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1048                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1049                 Register rax, Register rcx, Register rdx, Register tmp1);
1050 
1051   void fast_log10(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1052                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1053                 Register rax, Register rcx, Register rdx, Register tmp);
1054 
1055   void fast_pow(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3, XMMRegister xmm4,
1056                 XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7, Register rax, Register rcx,
1057                 Register rdx, Register tmp);
1058 
1059   void fast_sin(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1060                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1061                 Register rax, Register rbx, Register rdx);
1062 
1063   void fast_cos(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1064                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1065                 Register rax, Register rcx, Register rdx, Register tmp);
1066 
1067   void libm_sincos_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1068                         Register edx, Register ebx, Register esi, Register edi,
1069                         Register ebp, Register esp);
1070 
1071   void libm_reduce_pi04l(Register eax, Register ecx, Register edx, Register ebx,
1072                          Register esi, Register edi, Register ebp, Register esp);
1073 
1074   void libm_tancot_huge(XMMRegister xmm0, XMMRegister xmm1, Register eax, Register ecx,
1075                         Register edx, Register ebx, Register esi, Register edi,
1076                         Register ebp, Register esp);
1077 
1078   void fast_tan(XMMRegister xmm0, XMMRegister xmm1, XMMRegister xmm2, XMMRegister xmm3,
1079                 XMMRegister xmm4, XMMRegister xmm5, XMMRegister xmm6, XMMRegister xmm7,
1080                 Register rax, Register rcx, Register rdx, Register tmp);
1081 #endif
1082 
1083   void increase_precision();
1084   void restore_precision();
1085 
1086 private:
1087 
1088   // these are private because users should be doing movflt/movdbl
1089 
1090   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
1091   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
1092   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
1093   void movss(XMMRegister dst, AddressLiteral src);
1094 
1095   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
1096   void movlpd(XMMRegister dst, AddressLiteral src);
1097 
1098 public:
1099 
1100   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
1101   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
1102   void addsd(XMMRegister dst, AddressLiteral src);
1103 
1104   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
1105   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
1106   void addss(XMMRegister dst, AddressLiteral src);
1107 
1108   void addpd(XMMRegister dst, XMMRegister src)    { Assembler::addpd(dst, src); }
1109   void addpd(XMMRegister dst, Address src)        { Assembler::addpd(dst, src); }
1110   void addpd(XMMRegister dst, AddressLiteral src);
1111 
1112   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
1113   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
1114   void divsd(XMMRegister dst, AddressLiteral src);
1115 
1116   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
1117   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
1118   void divss(XMMRegister dst, AddressLiteral src);
1119 
1120   // Move Unaligned Double Quadword
1121   void movdqu(Address     dst, XMMRegister src);
1122   void movdqu(XMMRegister dst, Address src);
1123   void movdqu(XMMRegister dst, XMMRegister src);
1124   void movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg = rscratch1);
1125   // AVX Unaligned forms
1126   void vmovdqu(Address     dst, XMMRegister src);
1127   void vmovdqu(XMMRegister dst, Address src);
1128   void vmovdqu(XMMRegister dst, XMMRegister src);
1129   void vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1130   void evmovdquq(XMMRegister dst, Address src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1131   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1132   void evmovdquq(Address dst, XMMRegister src, int vector_len) { Assembler::evmovdquq(dst, src, vector_len); }
1133   void evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch);
1134 
1135   // Move Aligned Double Quadword
1136   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
1137   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
1138   void movdqa(XMMRegister dst, AddressLiteral src);
1139 
1140   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
1141   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
1142   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
1143   void movsd(XMMRegister dst, AddressLiteral src);
1144 
1145   void mulpd(XMMRegister dst, XMMRegister src)    { Assembler::mulpd(dst, src); }
1146   void mulpd(XMMRegister dst, Address src)        { Assembler::mulpd(dst, src); }
1147   void mulpd(XMMRegister dst, AddressLiteral src);
1148 
1149   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
1150   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
1151   void mulsd(XMMRegister dst, AddressLiteral src);
1152 
1153   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
1154   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
1155   void mulss(XMMRegister dst, AddressLiteral src);
1156 
1157   // Carry-Less Multiplication Quadword
1158   void pclmulldq(XMMRegister dst, XMMRegister src) {
1159     // 0x00 - multiply lower 64 bits [0:63]
1160     Assembler::pclmulqdq(dst, src, 0x00);
1161   }
1162   void pclmulhdq(XMMRegister dst, XMMRegister src) {
1163     // 0x11 - multiply upper 64 bits [64:127]
1164     Assembler::pclmulqdq(dst, src, 0x11);
1165   }
1166 
1167   void pcmpeqb(XMMRegister dst, XMMRegister src);
1168   void pcmpeqw(XMMRegister dst, XMMRegister src);
1169 
1170   void pcmpestri(XMMRegister dst, Address src, int imm8);
1171   void pcmpestri(XMMRegister dst, XMMRegister src, int imm8);
1172 
1173   void pmovzxbw(XMMRegister dst, XMMRegister src);
1174   void pmovzxbw(XMMRegister dst, Address src);
1175 
1176   void pmovmskb(Register dst, XMMRegister src);
1177 
1178   void ptest(XMMRegister dst, XMMRegister src);
1179 
1180   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
1181   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
1182   void sqrtsd(XMMRegister dst, AddressLiteral src);
1183 
1184   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
1185   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
1186   void sqrtss(XMMRegister dst, AddressLiteral src);
1187 
1188   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
1189   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
1190   void subsd(XMMRegister dst, AddressLiteral src);
1191 
1192   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
1193   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
1194   void subss(XMMRegister dst, AddressLiteral src);
1195 
1196   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
1197   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
1198   void ucomiss(XMMRegister dst, AddressLiteral src);
1199 
1200   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
1201   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
1202   void ucomisd(XMMRegister dst, AddressLiteral src);
1203 
1204   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1205   void xorpd(XMMRegister dst, XMMRegister src);
1206   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1207   void xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1208 
1209   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1210   void xorps(XMMRegister dst, XMMRegister src);
1211   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1212   void xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg = rscratch1);
1213 
1214   // Shuffle Bytes
1215   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1216   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1217   void pshufb(XMMRegister dst, AddressLiteral src);
1218   // AVX 3-operands instructions
1219 
1220   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1221   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1222   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1223 
1224   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1225   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1226   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1227 
1228   void vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1229   void vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len);
1230 
1231   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1232   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1233 
1234   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1235   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1236 
1237   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1238   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vpand(dst, nds, src, vector_len); }
1239   void vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1240 
1241   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
1242   void vpbroadcastw(XMMRegister dst, Address src, int vector_len) { Assembler::vpbroadcastw(dst, src, vector_len); }
1243 
1244   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1245 
1246   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1247 
1248   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1249   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) { Assembler::vpmovzxbw(dst, src, vector_len); }
1250 
1251   void vpmovmskb(Register dst, XMMRegister src);
1252 
1253   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1254   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1255 
1256   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1257   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1258 
1259   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1260   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1261 
1262   void vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1263   void vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1264 
1265   void evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1266   void evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1267 
1268   void vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1269   void vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1270 
1271   void vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len);
1272   void vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len);
1273 
1274   void vptest(XMMRegister dst, XMMRegister src);
1275 
1276   void punpcklbw(XMMRegister dst, XMMRegister src);
1277   void punpcklbw(XMMRegister dst, Address src) { Assembler::punpcklbw(dst, src); }
1278 
1279   void pshufd(XMMRegister dst, Address src, int mode);
1280   void pshufd(XMMRegister dst, XMMRegister src, int mode) { Assembler::pshufd(dst, src, mode); }
1281 
1282   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1283   void pshuflw(XMMRegister dst, Address src, int mode) { Assembler::pshuflw(dst, src, mode); }
1284 
1285   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandpd(dst, nds, src, vector_len); }
1286   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandpd(dst, nds, src, vector_len); }
1287   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1288 
1289   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vandps(dst, nds, src, vector_len); }
1290   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len)     { Assembler::vandps(dst, nds, src, vector_len); }
1291   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1292 
1293   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1294   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1295   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1296 
1297   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1298   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1299   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1300 
1301   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1302   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1303   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1304 
1305   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1306   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1307   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1308 
1309   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1310   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1311   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1312 
1313   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1314   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1315   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1316 
1317   void vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1318   void vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1319 
1320   // AVX Vector instructions
1321 
1322   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1323   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorpd(dst, nds, src, vector_len); }
1324   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1325 
1326   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1327   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { Assembler::vxorps(dst, nds, src, vector_len); }
1328   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1329 
1330   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1331     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1332       Assembler::vpxor(dst, nds, src, vector_len);
1333     else
1334       Assembler::vxorpd(dst, nds, src, vector_len);
1335   }
1336   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
1337     if (UseAVX > 1 || (vector_len < 1)) // vpxor 256 bit is available only in AVX2
1338       Assembler::vpxor(dst, nds, src, vector_len);
1339     else
1340       Assembler::vxorpd(dst, nds, src, vector_len);
1341   }
1342   void vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg = rscratch1);
1343 
1344   // Simple version for AVX2 256bit vectors
1345   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1346   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1347 
1348   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
1349     if (UseAVX > 2) {
1350       Assembler::vinserti32x4(dst, dst, src, imm8);
1351     } else if (UseAVX > 1) {
1352       // vinserti128 is available only in AVX2
1353       Assembler::vinserti128(dst, nds, src, imm8);
1354     } else {
1355       Assembler::vinsertf128(dst, nds, src, imm8);
1356     }
1357   }
1358 
1359   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
1360     if (UseAVX > 2) {
1361       Assembler::vinserti32x4(dst, dst, src, imm8);
1362     } else if (UseAVX > 1) {
1363       // vinserti128 is available only in AVX2
1364       Assembler::vinserti128(dst, nds, src, imm8);
1365     } else {
1366       Assembler::vinsertf128(dst, nds, src, imm8);
1367     }
1368   }
1369 
1370   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
1371     if (UseAVX > 2) {
1372       Assembler::vextracti32x4(dst, src, imm8);
1373     } else if (UseAVX > 1) {
1374       // vextracti128 is available only in AVX2
1375       Assembler::vextracti128(dst, src, imm8);
1376     } else {
1377       Assembler::vextractf128(dst, src, imm8);
1378     }
1379   }
1380 
1381   void vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
1382     if (UseAVX > 2) {
1383       Assembler::vextracti32x4(dst, src, imm8);
1384     } else if (UseAVX > 1) {
1385       // vextracti128 is available only in AVX2
1386       Assembler::vextracti128(dst, src, imm8);
1387     } else {
1388       Assembler::vextractf128(dst, src, imm8);
1389     }
1390   }
1391 
1392   // 128bit copy to/from high 128 bits of 256bit (YMM) vector registers
1393   void vinserti128_high(XMMRegister dst, XMMRegister src) {
1394     vinserti128(dst, dst, src, 1);
1395   }
1396   void vinserti128_high(XMMRegister dst, Address src) {
1397     vinserti128(dst, dst, src, 1);
1398   }
1399   void vextracti128_high(XMMRegister dst, XMMRegister src) {
1400     vextracti128(dst, src, 1);
1401   }
1402   void vextracti128_high(Address dst, XMMRegister src) {
1403     vextracti128(dst, src, 1);
1404   }
1405 
1406   void vinsertf128_high(XMMRegister dst, XMMRegister src) {
1407     if (UseAVX > 2) {
1408       Assembler::vinsertf32x4(dst, dst, src, 1);
1409     } else {
1410       Assembler::vinsertf128(dst, dst, src, 1);
1411     }
1412   }
1413 
1414   void vinsertf128_high(XMMRegister dst, Address src) {
1415     if (UseAVX > 2) {
1416       Assembler::vinsertf32x4(dst, dst, src, 1);
1417     } else {
1418       Assembler::vinsertf128(dst, dst, src, 1);
1419     }
1420   }
1421 
1422   void vextractf128_high(XMMRegister dst, XMMRegister src) {
1423     if (UseAVX > 2) {
1424       Assembler::vextractf32x4(dst, src, 1);
1425     } else {
1426       Assembler::vextractf128(dst, src, 1);
1427     }
1428   }
1429 
1430   void vextractf128_high(Address dst, XMMRegister src) {
1431     if (UseAVX > 2) {
1432       Assembler::vextractf32x4(dst, src, 1);
1433     } else {
1434       Assembler::vextractf128(dst, src, 1);
1435     }
1436   }
1437 
1438   // 256bit copy to/from high 256 bits of 512bit (ZMM) vector registers
1439   void vinserti64x4_high(XMMRegister dst, XMMRegister src) {
1440     Assembler::vinserti64x4(dst, dst, src, 1);
1441   }
1442   void vinsertf64x4_high(XMMRegister dst, XMMRegister src) {
1443     Assembler::vinsertf64x4(dst, dst, src, 1);
1444   }
1445   void vextracti64x4_high(XMMRegister dst, XMMRegister src) {
1446     Assembler::vextracti64x4(dst, src, 1);
1447   }
1448   void vextractf64x4_high(XMMRegister dst, XMMRegister src) {
1449     Assembler::vextractf64x4(dst, src, 1);
1450   }
1451   void vextractf64x4_high(Address dst, XMMRegister src) {
1452     Assembler::vextractf64x4(dst, src, 1);
1453   }
1454   void vinsertf64x4_high(XMMRegister dst, Address src) {
1455     Assembler::vinsertf64x4(dst, dst, src, 1);
1456   }
1457 
1458   // 128bit copy to/from low 128 bits of 256bit (YMM) vector registers
1459   void vinserti128_low(XMMRegister dst, XMMRegister src) {
1460     vinserti128(dst, dst, src, 0);
1461   }
1462   void vinserti128_low(XMMRegister dst, Address src) {
1463     vinserti128(dst, dst, src, 0);
1464   }
1465   void vextracti128_low(XMMRegister dst, XMMRegister src) {
1466     vextracti128(dst, src, 0);
1467   }
1468   void vextracti128_low(Address dst, XMMRegister src) {
1469     vextracti128(dst, src, 0);
1470   }
1471 
1472   void vinsertf128_low(XMMRegister dst, XMMRegister src) {
1473     if (UseAVX > 2) {
1474       Assembler::vinsertf32x4(dst, dst, src, 0);
1475     } else {
1476       Assembler::vinsertf128(dst, dst, src, 0);
1477     }
1478   }
1479 
1480   void vinsertf128_low(XMMRegister dst, Address src) {
1481     if (UseAVX > 2) {
1482       Assembler::vinsertf32x4(dst, dst, src, 0);
1483     } else {
1484       Assembler::vinsertf128(dst, dst, src, 0);
1485     }
1486   }
1487 
1488   void vextractf128_low(XMMRegister dst, XMMRegister src) {
1489     if (UseAVX > 2) {
1490       Assembler::vextractf32x4(dst, src, 0);
1491     } else {
1492       Assembler::vextractf128(dst, src, 0);
1493     }
1494   }
1495 
1496   void vextractf128_low(Address dst, XMMRegister src) {
1497     if (UseAVX > 2) {
1498       Assembler::vextractf32x4(dst, src, 0);
1499     } else {
1500       Assembler::vextractf128(dst, src, 0);
1501     }
1502   }
1503 
1504   // 256bit copy to/from low 256 bits of 512bit (ZMM) vector registers
1505   void vinserti64x4_low(XMMRegister dst, XMMRegister src) {
1506     Assembler::vinserti64x4(dst, dst, src, 0);
1507   }
1508   void vinsertf64x4_low(XMMRegister dst, XMMRegister src) {
1509     Assembler::vinsertf64x4(dst, dst, src, 0);
1510   }
1511   void vextracti64x4_low(XMMRegister dst, XMMRegister src) {
1512     Assembler::vextracti64x4(dst, src, 0);
1513   }
1514   void vextractf64x4_low(XMMRegister dst, XMMRegister src) {
1515     Assembler::vextractf64x4(dst, src, 0);
1516   }
1517   void vextractf64x4_low(Address dst, XMMRegister src) {
1518     Assembler::vextractf64x4(dst, src, 0);
1519   }
1520   void vinsertf64x4_low(XMMRegister dst, Address src) {
1521     Assembler::vinsertf64x4(dst, dst, src, 0);
1522   }
1523 
1524   // Carry-Less Multiplication Quadword
1525   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1526     // 0x00 - multiply lower 64 bits [0:63]
1527     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1528   }
1529   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1530     // 0x11 - multiply upper 64 bits [64:127]
1531     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1532   }
1533   void vpclmullqhqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1534     // 0x10 - multiply nds[0:63] and src[64:127]
1535     Assembler::vpclmulqdq(dst, nds, src, 0x10);
1536   }
1537   void vpclmulhqlqdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1538     //0x01 - multiply nds[64:127] and src[0:63]
1539     Assembler::vpclmulqdq(dst, nds, src, 0x01);
1540   }
1541 
1542   void evpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1543     // 0x00 - multiply lower 64 bits [0:63]
1544     Assembler::evpclmulqdq(dst, nds, src, 0x00, vector_len);
1545   }
1546   void evpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1547     // 0x11 - multiply upper 64 bits [64:127]
1548     Assembler::evpclmulqdq(dst, nds, src, 0x11, vector_len);
1549   }
1550 
1551   // Data
1552 
1553   void cmov32( Condition cc, Register dst, Address  src);
1554   void cmov32( Condition cc, Register dst, Register src);
1555 
1556   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1557 
1558   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1559   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1560 
1561   void movoop(Register dst, jobject obj);
1562   void movoop(Address dst, jobject obj);
1563 
1564   void mov_metadata(Register dst, Metadata* obj);
1565   void mov_metadata(Address dst, Metadata* obj);
1566 
1567   void movptr(ArrayAddress dst, Register src);
1568   // can this do an lea?
1569   void movptr(Register dst, ArrayAddress src);
1570 
1571   void movptr(Register dst, Address src);
1572 
1573 #ifdef _LP64
1574   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1575 #else
1576   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1577 #endif
1578 
1579   void movptr(Register dst, intptr_t src);
1580   void movptr(Register dst, Register src);
1581   void movptr(Address dst, intptr_t src);
1582 
1583   void movptr(Address dst, Register src);
1584 
1585   void movptr(Register dst, RegisterOrConstant src) {
1586     if (src.is_constant()) movptr(dst, src.as_constant());
1587     else                   movptr(dst, src.as_register());
1588   }
1589 
1590 #ifdef _LP64
1591   // Generally the next two are only used for moving NULL
1592   // Although there are situations in initializing the mark word where
1593   // they could be used. They are dangerous.
1594 
1595   // They only exist on LP64 so that int32_t and intptr_t are not the same
1596   // and we have ambiguous declarations.
1597 
1598   void movptr(Address dst, int32_t imm32);
1599   void movptr(Register dst, int32_t imm32);
1600 #endif // _LP64
1601 
1602   // to avoid hiding movl
1603   void mov32(AddressLiteral dst, Register src);
1604   void mov32(Register dst, AddressLiteral src);
1605 
1606   // to avoid hiding movb
1607   void movbyte(ArrayAddress dst, int src);
1608 
1609   // Import other mov() methods from the parent class or else
1610   // they will be hidden by the following overriding declaration.
1611   using Assembler::movdl;
1612   using Assembler::movq;
1613   void movdl(XMMRegister dst, AddressLiteral src);
1614   void movq(XMMRegister dst, AddressLiteral src);
1615 
1616   // Can push value or effective address
1617   void pushptr(AddressLiteral src);
1618 
1619   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1620   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1621 
1622   void pushoop(jobject obj);
1623   void pushklass(Metadata* obj);
1624 
1625   // sign extend as need a l to ptr sized element
1626   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1627   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1628 
1629 #ifdef COMPILER2
1630   // Generic instructions support for use in .ad files C2 code generation
1631   void vabsnegd(int opcode, XMMRegister dst, Register scr);
1632   void vabsnegd(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1633   void vabsnegf(int opcode, XMMRegister dst, Register scr);
1634   void vabsnegf(int opcode, XMMRegister dst, XMMRegister src, int vector_len, Register scr);
1635   void vextendbw(bool sign, XMMRegister dst, XMMRegister src, int vector_len);
1636   void vextendbw(bool sign, XMMRegister dst, XMMRegister src);
1637   void vshiftd(int opcode, XMMRegister dst, XMMRegister src);
1638   void vshiftd(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1639   void vshiftw(int opcode, XMMRegister dst, XMMRegister src);
1640   void vshiftw(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1641   void vshiftq(int opcode, XMMRegister dst, XMMRegister src);
1642   void vshiftq(int opcode, XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1643 #endif
1644 
1645   // C2 compiled method's prolog code.
1646   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub);
1647 
1648   // clear memory of size 'cnt' qwords, starting at 'base';
1649   // if 'is_large' is set, do not try to produce short loop
1650   void clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, bool is_large);
1651 
1652   // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM registers
1653   void xmm_clear_mem(Register base, Register cnt, XMMRegister xtmp);
1654 
1655 #ifdef COMPILER2
1656   void string_indexof_char(Register str1, Register cnt1, Register ch, Register result,
1657                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp);
1658 
1659   // IndexOf strings.
1660   // Small strings are loaded through stack if they cross page boundary.
1661   void string_indexof(Register str1, Register str2,
1662                       Register cnt1, Register cnt2,
1663                       int int_cnt2,  Register result,
1664                       XMMRegister vec, Register tmp,
1665                       int ae);
1666 
1667   // IndexOf for constant substrings with size >= 8 elements
1668   // which don't need to be loaded through stack.
1669   void string_indexofC8(Register str1, Register str2,
1670                       Register cnt1, Register cnt2,
1671                       int int_cnt2,  Register result,
1672                       XMMRegister vec, Register tmp,
1673                       int ae);
1674 
1675     // Smallest code: we don't need to load through stack,
1676     // check string tail.
1677 
1678   // helper function for string_compare
1679   void load_next_elements(Register elem1, Register elem2, Register str1, Register str2,
1680                           Address::ScaleFactor scale, Address::ScaleFactor scale1,
1681                           Address::ScaleFactor scale2, Register index, int ae);
1682   // Compare strings.
1683   void string_compare(Register str1, Register str2,
1684                       Register cnt1, Register cnt2, Register result,
1685                       XMMRegister vec1, int ae);
1686 
1687   // Search for Non-ASCII character (Negative byte value) in a byte array,
1688   // return true if it has any and false otherwise.
1689   void has_negatives(Register ary1, Register len,
1690                      Register result, Register tmp1,
1691                      XMMRegister vec1, XMMRegister vec2);
1692 
1693   // Compare char[] or byte[] arrays.
1694   void arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1695                      Register limit, Register result, Register chr,
1696                      XMMRegister vec1, XMMRegister vec2, bool is_char);
1697 
1698 #endif
1699 
1700   // Fill primitive arrays
1701   void generate_fill(BasicType t, bool aligned,
1702                      Register to, Register value, Register count,
1703                      Register rtmp, XMMRegister xtmp);
1704 
1705   void encode_iso_array(Register src, Register dst, Register len,
1706                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1707                         XMMRegister tmp4, Register tmp5, Register result);
1708 
1709 #ifdef _LP64
1710   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1711   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1712                              Register y, Register y_idx, Register z,
1713                              Register carry, Register product,
1714                              Register idx, Register kdx);
1715   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1716                               Register yz_idx, Register idx,
1717                               Register carry, Register product, int offset);
1718   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1719                                     Register carry, Register carry2,
1720                                     Register idx, Register jdx,
1721                                     Register yz_idx1, Register yz_idx2,
1722                                     Register tmp, Register tmp3, Register tmp4);
1723   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1724                                Register yz_idx, Register idx, Register jdx,
1725                                Register carry, Register product,
1726                                Register carry2);
1727   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1728                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1729   void square_rshift(Register x, Register len, Register z, Register tmp1, Register tmp3,
1730                      Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1731   void multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry,
1732                             Register tmp2);
1733   void multiply_add_64(Register sum, Register op1, Register op2, Register carry,
1734                        Register rdxReg, Register raxReg);
1735   void add_one_64(Register z, Register zlen, Register carry, Register tmp1);
1736   void lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1737                        Register tmp3, Register tmp4);
1738   void square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2,
1739                      Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg);
1740 
1741   void mul_add_128_x_32_loop(Register out, Register in, Register offset, Register len, Register tmp1,
1742                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1743                Register raxReg);
1744   void mul_add(Register out, Register in, Register offset, Register len, Register k, Register tmp1,
1745                Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg,
1746                Register raxReg);
1747   void vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
1748                            Register result, Register tmp1, Register tmp2,
1749                            XMMRegister vec1, XMMRegister vec2, XMMRegister vec3);
1750 #endif
1751 
1752   // CRC32 code for java.util.zip.CRC32::updateBytes() intrinsic.
1753   void update_byte_crc32(Register crc, Register val, Register table);
1754   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1755   // CRC32C code for java.util.zip.CRC32C::updateBytes() intrinsic
1756   // Note on a naming convention:
1757   // Prefix w = register only used on a Westmere+ architecture
1758   // Prefix n = register only used on a Nehalem architecture
1759 #ifdef _LP64
1760   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1761                        Register tmp1, Register tmp2, Register tmp3);
1762 #else
1763   void crc32c_ipl_alg4(Register in_out, uint32_t n,
1764                        Register tmp1, Register tmp2, Register tmp3,
1765                        XMMRegister xtmp1, XMMRegister xtmp2);
1766 #endif
1767   void crc32c_pclmulqdq(XMMRegister w_xtmp1,
1768                         Register in_out,
1769                         uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
1770                         XMMRegister w_xtmp2,
1771                         Register tmp1,
1772                         Register n_tmp2, Register n_tmp3);
1773   void crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
1774                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1775                        Register tmp1, Register tmp2,
1776                        Register n_tmp3);
1777   void crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
1778                          Register in_out1, Register in_out2, Register in_out3,
1779                          Register tmp1, Register tmp2, Register tmp3,
1780                          XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1781                          Register tmp4, Register tmp5,
1782                          Register n_tmp6);
1783   void crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
1784                             Register tmp1, Register tmp2, Register tmp3,
1785                             Register tmp4, Register tmp5, Register tmp6,
1786                             XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
1787                             bool is_pclmulqdq_supported);
1788   // Fold 128-bit data chunk
1789   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1790   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1791   // Fold 8-bit data
1792   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1793   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1794   void fold_128bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1795 
1796   // Compress char[] array to byte[].
1797   void char_array_compress(Register src, Register dst, Register len,
1798                            XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1799                            XMMRegister tmp4, Register tmp5, Register result);
1800 
1801   // Inflate byte[] array to char[].
1802   void byte_array_inflate(Register src, Register dst, Register len,
1803                           XMMRegister tmp1, Register tmp2);
1804 
1805 };
1806 
1807 /**
1808  * class SkipIfEqual:
1809  *
1810  * Instantiating this class will result in assembly code being output that will
1811  * jump around any code emitted between the creation of the instance and it's
1812  * automatic destruction at the end of a scope block, depending on the value of
1813  * the flag passed to the constructor, which will be checked at run-time.
1814  */
1815 class SkipIfEqual {
1816  private:
1817   MacroAssembler* _masm;
1818   Label _label;
1819 
1820  public:
1821    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1822    ~SkipIfEqual();
1823 };
1824 
1825 #endif // CPU_X86_MACROASSEMBLER_X86_HPP