1 /*
  2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
  3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  4  *
  5  * This code is free software; you can redistribute it and/or modify it
  6  * under the terms of the GNU General Public License version 2 only, as
  7  * published by the Free Software Foundation.
  8  *
  9  * This code is distributed in the hope that it will be useful, but WITHOUT
 10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 12  * version 2 for more details (a copy is included in the LICENSE file that
 13  * accompanied this code).
 14  *
 15  * You should have received a copy of the GNU General Public License version
 16  * 2 along with this work; if not, write to the Free Software Foundation,
 17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
 18  *
 19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
 20  * or visit www.oracle.com if you need additional information or have any
 21  * questions.
 22  *
 23  */
 24 
 25 #include "precompiled.hpp"
 26 #include "asm/macroAssembler.hpp"
 27 #include "code/compiledIC.hpp"
 28 #include "memory/resourceArea.hpp"
 29 #include "nativeInst_x86.hpp"
 30 #include "oops/oop.inline.hpp"
 31 #include "runtime/handles.hpp"
 32 #include "runtime/safepoint.hpp"
 33 #include "runtime/sharedRuntime.hpp"
 34 #include "runtime/stubRoutines.hpp"
 35 #include "utilities/ostream.hpp"
 36 #ifdef COMPILER1
 37 #include "c1/c1_Runtime1.hpp"
 38 #endif
 39 
 40 void NativeInstruction::wrote(int offset) {
 41   ICache::invalidate_word(addr_at(offset));
 42 }
 43 
 44 #ifdef ASSERT
 45 void NativeLoadGot::report_and_fail() const {
 46   tty->print_cr("Addr: " INTPTR_FORMAT " Code: %x %x %x", p2i(instruction_address()),
 47                   (has_rex ? ubyte_at(0) : 0), ubyte_at(rex_size), ubyte_at(rex_size + 1));
 48   fatal("not a indirect rip mov to rbx");
 49 }
 50 
 51 void NativeLoadGot::verify() const {
 52   if (has_rex) {
 53     int rex = ubyte_at(0);
 54     if (rex != rex_prefix && rex != rex_b_prefix) {
 55       report_and_fail();
 56     }
 57   }
 58 
 59   int inst = ubyte_at(rex_size);
 60   if (inst != instruction_code) {
 61     report_and_fail();
 62   }
 63   int modrm = ubyte_at(rex_size + 1);
 64   if (modrm != modrm_rbx_code && modrm != modrm_rax_code) {
 65     report_and_fail();
 66   }
 67 }
 68 #endif
 69 
 70 intptr_t NativeLoadGot::data() const {
 71   return *(intptr_t *) got_address();
 72 }
 73 
 74 address NativePltCall::destination() const {
 75   NativeGotJump* jump = nativeGotJump_at(plt_jump());
 76   return jump->destination();
 77 }
 78 
 79 address NativePltCall::plt_entry() const {
 80   return return_address() + displacement();
 81 }
 82 
 83 address NativePltCall::plt_jump() const {
 84   address entry = plt_entry();
 85   // Virtual PLT code has move instruction first
 86   if (((NativeGotJump*)entry)->is_GotJump()) {
 87     return entry;
 88   } else {
 89     return nativeLoadGot_at(entry)->next_instruction_address();
 90   }
 91 }
 92 
 93 address NativePltCall::plt_load_got() const {
 94   address entry = plt_entry();
 95   if (!((NativeGotJump*)entry)->is_GotJump()) {
 96     // Virtual PLT code has move instruction first
 97     return entry;
 98   } else {
 99     // Static PLT code has move instruction second (from c2i stub)
100     return nativeGotJump_at(entry)->next_instruction_address();
101   }
102 }
103 
104 address NativePltCall::plt_c2i_stub() const {
105   address entry = plt_load_got();
106   // This method should be called only for static calls which has C2I stub.
107   NativeLoadGot* load = nativeLoadGot_at(entry);
108   return entry;
109 }
110 
111 address NativePltCall::plt_resolve_call() const {
112   NativeGotJump* jump = nativeGotJump_at(plt_jump());
113   address entry = jump->next_instruction_address();
114   if (((NativeGotJump*)entry)->is_GotJump()) {
115     return entry;
116   } else {
117     // c2i stub 2 instructions
118     entry = nativeLoadGot_at(entry)->next_instruction_address();
119     return nativeGotJump_at(entry)->next_instruction_address();
120   }
121 }
122 
123 void NativePltCall::reset_to_plt_resolve_call() {
124   set_destination_mt_safe(plt_resolve_call());
125 }
126 
127 void NativePltCall::set_destination_mt_safe(address dest) {
128   // rewriting the value in the GOT, it should always be aligned
129   NativeGotJump* jump = nativeGotJump_at(plt_jump());
130   address* got = (address *) jump->got_address();
131   *got = dest;
132 }
133 
134 void NativePltCall::set_stub_to_clean() {
135   NativeLoadGot* method_loader = nativeLoadGot_at(plt_c2i_stub());
136   NativeGotJump* jump          = nativeGotJump_at(method_loader->next_instruction_address());
137   method_loader->set_data(0);
138   jump->set_jump_destination((address)-1);
139 }
140 
141 void NativePltCall::verify() const {
142   // Make sure code pattern is actually a call rip+off32 instruction.
143   int inst = ubyte_at(0);
144   if (inst != instruction_code) {
145     tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", p2i(instruction_address()),
146                                                         inst);
147     fatal("not a call rip+off32");
148   }
149 }
150 
151 address NativeGotJump::destination() const {
152   address *got_entry = (address *) got_address();
153   return *got_entry;
154 }
155 
156 #ifdef ASSERT
157 void NativeGotJump::report_and_fail() const {
158   tty->print_cr("Addr: " INTPTR_FORMAT " Code: %x %x %x", p2i(instruction_address()),
159                  (has_rex() ? ubyte_at(0) : 0), ubyte_at(rex_size()), ubyte_at(rex_size() + 1));
160   fatal("not a indirect rip jump");
161 }
162 
163 void NativeGotJump::verify() const {
164   if (has_rex()) {
165     int rex = ubyte_at(0);
166     if (rex != rex_prefix) {
167       report_and_fail();
168     }
169   }
170   int inst = ubyte_at(rex_size());
171   if (inst != instruction_code) {
172     report_and_fail();
173   }
174   int modrm = ubyte_at(rex_size() + 1);
175   if (modrm != modrm_code) {
176     report_and_fail();
177   }
178 }
179 #endif
180 
181 void NativeCall::verify() {
182   // Make sure code pattern is actually a call imm32 instruction.
183   int inst = ubyte_at(0);
184   if (inst != instruction_code) {
185     tty->print_cr("Addr: " INTPTR_FORMAT " Code: 0x%x", p2i(instruction_address()),
186                                                         inst);
187     fatal("not a call disp32");
188   }
189 }
190 
191 address NativeCall::destination() const {
192   // Getting the destination of a call isn't safe because that call can
193   // be getting patched while you're calling this.  There's only special
194   // places where this can be called but not automatically verifiable by
195   // checking which locks are held.  The solution is true atomic patching
196   // on x86, nyi.
197   return return_address() + displacement();
198 }
199 
200 void NativeCall::print() {
201   tty->print_cr(PTR_FORMAT ": call " PTR_FORMAT,
202                 p2i(instruction_address()), p2i(destination()));
203 }
204 
205 // Inserts a native call instruction at a given pc
206 void NativeCall::insert(address code_pos, address entry) {
207   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
208 #ifdef AMD64
209   guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
210 #endif // AMD64
211   *code_pos = instruction_code;
212   *((int32_t *)(code_pos+1)) = (int32_t) disp;
213   ICache::invalidate_range(code_pos, instruction_size);
214 }
215 
216 // MT-safe patching of a call instruction.
217 // First patches first word of instruction to two jmp's that jmps to them
218 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
219 // the jmp's with the first 4 byte of the new instruction.
220 void NativeCall::replace_mt_safe(address instr_addr, address code_buffer) {
221   assert(Patching_lock->is_locked() ||
222          SafepointSynchronize::is_at_safepoint(), "concurrent code patching");
223   assert (instr_addr != NULL, "illegal address for code patching");
224 
225   NativeCall* n_call =  nativeCall_at (instr_addr); // checking that it is a call
226   guarantee((intptr_t)instr_addr % BytesPerWord == 0, "must be aligned");
227 
228   // First patch dummy jmp in place
229   unsigned char patch[4];
230   assert(sizeof(patch)==sizeof(jint), "sanity check");
231   patch[0] = 0xEB;       // jmp rel8
232   patch[1] = 0xFE;       // jmp to self
233   patch[2] = 0xEB;
234   patch[3] = 0xFE;
235 
236   // First patch dummy jmp in place
237   *(jint*)instr_addr = *(jint *)patch;
238 
239   // Invalidate.  Opteron requires a flush after every write.
240   n_call->wrote(0);
241 
242   // Patch 4th byte
243   instr_addr[4] = code_buffer[4];
244 
245   n_call->wrote(4);
246 
247   // Patch bytes 0-3
248   *(jint*)instr_addr = *(jint *)code_buffer;
249 
250   n_call->wrote(0);
251 
252 #ifdef ASSERT
253    // verify patching
254    for ( int i = 0; i < instruction_size; i++) {
255      address ptr = (address)((intptr_t)code_buffer + i);
256      int a_byte = (*ptr) & 0xFF;
257      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
258    }
259 #endif
260 
261 }
262 
263 
264 // Similar to replace_mt_safe, but just changes the destination.  The
265 // important thing is that free-running threads are able to execute this
266 // call instruction at all times.  If the displacement field is aligned
267 // we can simply rely on atomicity of 32-bit writes to make sure other threads
268 // will see no intermediate states.  Otherwise, the first two bytes of the
269 // call are guaranteed to be aligned, and can be atomically patched to a
270 // self-loop to guard the instruction while we change the other bytes.
271 
272 // We cannot rely on locks here, since the free-running threads must run at
273 // full speed.
274 //
275 // Used in the runtime linkage of calls; see class CompiledIC.
276 // (Cf. 4506997 and 4479829, where threads witnessed garbage displacements.)
277 void NativeCall::set_destination_mt_safe(address dest) {
278   debug_only(verify());
279   // Make sure patching code is locked.  No two threads can patch at the same
280   // time but one may be executing this code.
281   assert(Patching_lock->is_locked() || SafepointSynchronize::is_at_safepoint() ||
282          CompiledICLocker::is_safe(instruction_address()), "concurrent code patching");
283   // Both C1 and C2 should now be generating code which aligns the patched address
284   // to be within a single cache line.
285   bool is_aligned = ((uintptr_t)displacement_address() + 0) / cache_line_size ==
286                     ((uintptr_t)displacement_address() + 3) / cache_line_size;
287 
288   guarantee(is_aligned, "destination must be aligned");
289 
290   // The destination lies within a single cache line.
291   set_destination(dest);
292 }
293 
294 
295 void NativeMovConstReg::verify() {
296 #ifdef AMD64
297   // make sure code pattern is actually a mov reg64, imm64 instruction
298   if ((ubyte_at(0) != Assembler::REX_W && ubyte_at(0) != Assembler::REX_WB) ||
299       (ubyte_at(1) & (0xff ^ register_mask)) != 0xB8) {
300     print();
301     fatal("not a REX.W[B] mov reg64, imm64");
302   }
303 #else
304   // make sure code pattern is actually a mov reg, imm32 instruction
305   u_char test_byte = *(u_char*)instruction_address();
306   u_char test_byte_2 = test_byte & ( 0xff ^ register_mask);
307   if (test_byte_2 != instruction_code) fatal("not a mov reg, imm32");
308 #endif // AMD64
309 }
310 
311 
312 void NativeMovConstReg::print() {
313   tty->print_cr(PTR_FORMAT ": mov reg, " INTPTR_FORMAT,
314                 p2i(instruction_address()), data());
315 }
316 
317 //-------------------------------------------------------------------
318 
319 int NativeMovRegMem::instruction_start() const {
320   int off = 0;
321   u_char instr_0 = ubyte_at(off);
322 
323   // See comment in Assembler::locate_operand() about VEX prefixes.
324   if (instr_0 == instruction_VEX_prefix_2bytes) {
325     assert((UseAVX > 0), "shouldn't have VEX prefix");
326     NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
327     return 2;
328   }
329   if (instr_0 == instruction_VEX_prefix_3bytes) {
330     assert((UseAVX > 0), "shouldn't have VEX prefix");
331     NOT_LP64(assert((0xC0 & ubyte_at(1)) == 0xC0, "shouldn't have LDS and LES instructions"));
332     return 3;
333   }
334   if (instr_0 == instruction_EVEX_prefix_4bytes) {
335     assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
336     return 4;
337   }
338 
339   // First check to see if we have a (prefixed or not) xor
340   if (instr_0 >= instruction_prefix_wide_lo && // 0x40
341       instr_0 <= instruction_prefix_wide_hi) { // 0x4f
342     off++;
343     instr_0 = ubyte_at(off);
344   }
345 
346   if (instr_0 == instruction_code_xor) {
347     off += 2;
348     instr_0 = ubyte_at(off);
349   }
350 
351   // Now look for the real instruction and the many prefix/size specifiers.
352 
353   if (instr_0 == instruction_operandsize_prefix ) {  // 0x66
354     off++; // Not SSE instructions
355     instr_0 = ubyte_at(off);
356   }
357 
358   if ( instr_0 == instruction_code_xmm_ss_prefix || // 0xf3
359        instr_0 == instruction_code_xmm_sd_prefix) { // 0xf2
360     off++;
361     instr_0 = ubyte_at(off);
362   }
363 
364   if ( instr_0 >= instruction_prefix_wide_lo && // 0x40
365        instr_0 <= instruction_prefix_wide_hi) { // 0x4f
366     off++;
367     instr_0 = ubyte_at(off);
368   }
369 
370 
371   if (instr_0 == instruction_extended_prefix ) {  // 0x0f
372     off++;
373   }
374 
375   return off;
376 }
377 
378 int NativeMovRegMem::patch_offset() const {
379   int off = data_offset + instruction_start();
380   u_char mod_rm = *(u_char*)(instruction_address() + 1);
381   // nnnn(r12|rsp) isn't coded as simple mod/rm since that is
382   // the encoding to use an SIB byte. Which will have the nnnn
383   // field off by one byte
384   if ((mod_rm & 7) == 0x4) {
385     off++;
386   }
387   return off;
388 }
389 
390 void NativeMovRegMem::verify() {
391   // make sure code pattern is actually a mov [reg+offset], reg instruction
392   u_char test_byte = *(u_char*)instruction_address();
393   switch (test_byte) {
394     case instruction_code_reg2memb:  // 0x88 movb a, r
395     case instruction_code_reg2mem:   // 0x89 movl a, r (can be movq in 64bit)
396     case instruction_code_mem2regb:  // 0x8a movb r, a
397     case instruction_code_mem2reg:   // 0x8b movl r, a (can be movq in 64bit)
398       break;
399 
400     case instruction_code_mem2reg_movslq: // 0x63 movsql r, a
401     case instruction_code_mem2reg_movzxb: // 0xb6 movzbl r, a (movzxb)
402     case instruction_code_mem2reg_movzxw: // 0xb7 movzwl r, a (movzxw)
403     case instruction_code_mem2reg_movsxb: // 0xbe movsbl r, a (movsxb)
404     case instruction_code_mem2reg_movsxw: // 0xbf  movswl r, a (movsxw)
405       break;
406 
407     case instruction_code_float_s:   // 0xd9 fld_s a
408     case instruction_code_float_d:   // 0xdd fld_d a
409     case instruction_code_xmm_load:  // 0x10 movsd xmm, a
410     case instruction_code_xmm_store: // 0x11 movsd a, xmm
411     case instruction_code_xmm_lpd:   // 0x12 movlpd xmm, a
412       break;
413 
414     case instruction_code_lea:       // 0x8d lea r, a
415       break;
416 
417     default:
418           fatal ("not a mov [reg+offs], reg instruction");
419   }
420 }
421 
422 
423 void NativeMovRegMem::print() {
424   tty->print_cr(PTR_FORMAT ": mov reg, [reg + %x]", p2i(instruction_address()), offset());
425 }
426 
427 //-------------------------------------------------------------------
428 
429 void NativeLoadAddress::verify() {
430   // make sure code pattern is actually a mov [reg+offset], reg instruction
431   u_char test_byte = *(u_char*)instruction_address();
432 #ifdef _LP64
433   if ( (test_byte == instruction_prefix_wide ||
434         test_byte == instruction_prefix_wide_extended) ) {
435     test_byte = *(u_char*)(instruction_address() + 1);
436   }
437 #endif // _LP64
438   if ( ! ((test_byte == lea_instruction_code)
439           LP64_ONLY(|| (test_byte == mov64_instruction_code) ))) {
440     fatal ("not a lea reg, [reg+offs] instruction");
441   }
442 }
443 
444 
445 void NativeLoadAddress::print() {
446   tty->print_cr(PTR_FORMAT ": lea [reg + %x], reg", p2i(instruction_address()), offset());
447 }
448 
449 //--------------------------------------------------------------------------------
450 
451 void NativeJump::verify() {
452   if (*(u_char*)instruction_address() != instruction_code) {
453     // far jump
454     NativeMovConstReg* mov = nativeMovConstReg_at(instruction_address());
455     NativeInstruction* jmp = nativeInstruction_at(mov->next_instruction_address());
456     if (!jmp->is_jump_reg()) {
457       fatal("not a jump instruction");
458     }
459   }
460 }
461 
462 
463 void NativeJump::insert(address code_pos, address entry) {
464   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
465 #ifdef AMD64
466   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
467 #endif // AMD64
468 
469   *code_pos = instruction_code;
470   *((int32_t*)(code_pos + 1)) = (int32_t)disp;
471 
472   ICache::invalidate_range(code_pos, instruction_size);
473 }
474 
475 void NativeJump::check_verified_entry_alignment(address entry, address verified_entry) {
476   // Patching to not_entrant can happen while activations of the method are
477   // in use. The patching in that instance must happen only when certain
478   // alignment restrictions are true. These guarantees check those
479   // conditions.
480 #ifdef AMD64
481   const int linesize = 64;
482 #else
483   const int linesize = 32;
484 #endif // AMD64
485 
486   // Must be wordSize aligned
487   guarantee(((uintptr_t) verified_entry & (wordSize -1)) == 0,
488             "illegal address for code patching 2");
489   // First 5 bytes must be within the same cache line - 4827828
490   guarantee((uintptr_t) verified_entry / linesize ==
491             ((uintptr_t) verified_entry + 4) / linesize,
492             "illegal address for code patching 3");
493 }
494 
495 
496 // MT safe inserting of a jump over an unknown instruction sequence (used by nmethod::makeZombie)
497 // The problem: jmp <dest> is a 5-byte instruction. Atomical write can be only with 4 bytes.
498 // First patches the first word atomically to be a jump to itself.
499 // Then patches the last byte  and then atomically patches the first word (4-bytes),
500 // thus inserting the desired jump
501 // This code is mt-safe with the following conditions: entry point is 4 byte aligned,
502 // entry point is in same cache line as unverified entry point, and the instruction being
503 // patched is >= 5 byte (size of patch).
504 //
505 // In C2 the 5+ byte sized instruction is enforced by code in MachPrologNode::emit.
506 // In C1 the restriction is enforced by CodeEmitter::method_entry
507 // In JVMCI, the restriction is enforced by HotSpotFrameContext.enter(...)
508 //
509 void NativeJump::patch_verified_entry(address entry, address verified_entry, address dest) {
510   // complete jump instruction (to be inserted) is in code_buffer;
511   unsigned char code_buffer[5];
512   code_buffer[0] = instruction_code;
513   intptr_t disp = (intptr_t)dest - ((intptr_t)verified_entry + 1 + 4);
514 #ifdef AMD64
515   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
516 #endif // AMD64
517   *(int32_t*)(code_buffer + 1) = (int32_t)disp;
518 
519   check_verified_entry_alignment(entry, verified_entry);
520 
521   // Can't call nativeJump_at() because it's asserts jump exists
522   NativeJump* n_jump = (NativeJump*) verified_entry;
523 
524   //First patch dummy jmp in place
525 
526   unsigned char patch[4];
527   assert(sizeof(patch)==sizeof(int32_t), "sanity check");
528   patch[0] = 0xEB;       // jmp rel8
529   patch[1] = 0xFE;       // jmp to self
530   patch[2] = 0xEB;
531   patch[3] = 0xFE;
532 
533   // First patch dummy jmp in place
534   *(int32_t*)verified_entry = *(int32_t *)patch;
535 
536   n_jump->wrote(0);
537 
538   // Patch 5th byte (from jump instruction)
539   verified_entry[4] = code_buffer[4];
540 
541   n_jump->wrote(4);
542 
543   // Patch bytes 0-3 (from jump instruction)
544   *(int32_t*)verified_entry = *(int32_t *)code_buffer;
545   // Invalidate.  Opteron requires a flush after every write.
546   n_jump->wrote(0);
547 
548 }
549 
550 address NativeFarJump::jump_destination() const          {
551   NativeMovConstReg* mov = nativeMovConstReg_at(addr_at(0));
552   return (address)mov->data();
553 }
554 
555 void NativeFarJump::verify() {
556   if (is_far_jump()) {
557     NativeMovConstReg* mov = nativeMovConstReg_at(addr_at(0));
558     NativeInstruction* jmp = nativeInstruction_at(mov->next_instruction_address());
559     if (jmp->is_jump_reg()) return;
560   }
561   fatal("not a jump instruction");
562 }
563 
564 void NativePopReg::insert(address code_pos, Register reg) {
565   assert(reg->encoding() < 8, "no space for REX");
566   assert(NativePopReg::instruction_size == sizeof(char), "right address unit for update");
567   *code_pos = (u_char)(instruction_code | reg->encoding());
568   ICache::invalidate_range(code_pos, instruction_size);
569 }
570 
571 
572 void NativeIllegalInstruction::insert(address code_pos) {
573   assert(NativeIllegalInstruction::instruction_size == sizeof(short), "right address unit for update");
574   *(short *)code_pos = instruction_code;
575   ICache::invalidate_range(code_pos, instruction_size);
576 }
577 
578 void NativeGeneralJump::verify() {
579   assert(((NativeInstruction *)this)->is_jump() ||
580          ((NativeInstruction *)this)->is_cond_jump(), "not a general jump instruction");
581 }
582 
583 
584 void NativeGeneralJump::insert_unconditional(address code_pos, address entry) {
585   intptr_t disp = (intptr_t)entry - ((intptr_t)code_pos + 1 + 4);
586 #ifdef AMD64
587   guarantee(disp == (intptr_t)(int32_t)disp, "must be 32-bit offset");
588 #endif // AMD64
589 
590   *code_pos = unconditional_long_jump;
591   *((int32_t *)(code_pos+1)) = (int32_t) disp;
592   ICache::invalidate_range(code_pos, instruction_size);
593 }
594 
595 
596 // MT-safe patching of a long jump instruction.
597 // First patches first word of instruction to two jmp's that jmps to them
598 // selfs (spinlock). Then patches the last byte, and then atomicly replaces
599 // the jmp's with the first 4 byte of the new instruction.
600 void NativeGeneralJump::replace_mt_safe(address instr_addr, address code_buffer) {
601    assert (instr_addr != NULL, "illegal address for code patching (4)");
602    NativeGeneralJump* n_jump =  nativeGeneralJump_at (instr_addr); // checking that it is a jump
603 
604    // Temporary code
605    unsigned char patch[4];
606    assert(sizeof(patch)==sizeof(int32_t), "sanity check");
607    patch[0] = 0xEB;       // jmp rel8
608    patch[1] = 0xFE;       // jmp to self
609    patch[2] = 0xEB;
610    patch[3] = 0xFE;
611 
612    // First patch dummy jmp in place
613    *(int32_t*)instr_addr = *(int32_t *)patch;
614     n_jump->wrote(0);
615 
616    // Patch 4th byte
617    instr_addr[4] = code_buffer[4];
618 
619     n_jump->wrote(4);
620 
621    // Patch bytes 0-3
622    *(jint*)instr_addr = *(jint *)code_buffer;
623 
624     n_jump->wrote(0);
625 
626 #ifdef ASSERT
627    // verify patching
628    for ( int i = 0; i < instruction_size; i++) {
629      address ptr = (address)((intptr_t)code_buffer + i);
630      int a_byte = (*ptr) & 0xFF;
631      assert(*((address)((intptr_t)instr_addr + i)) == a_byte, "mt safe patching failed");
632    }
633 #endif
634 
635 }
636 
637 
638 
639 address NativeGeneralJump::jump_destination() const {
640   int op_code = ubyte_at(0);
641   bool is_rel32off = (op_code == 0xE9 || op_code == 0x0F);
642   int  offset  = (op_code == 0x0F)  ? 2 : 1;
643   int  length  = offset + ((is_rel32off) ? 4 : 1);
644 
645   if (is_rel32off)
646     return addr_at(0) + length + int_at(offset);
647   else
648     return addr_at(0) + length + sbyte_at(offset);
649 }