1 /*
   2  * Copyright (c) 1997, 2019, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
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  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
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  24 
  25 #ifndef CPU_X86_NATIVEINST_X86_HPP
  26 #define CPU_X86_NATIVEINST_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "runtime/icache.hpp"
  30 #include "runtime/os.hpp"
  31 #include "runtime/safepointMechanism.hpp"
  32 
  33 #include "runtime/continuation.hpp" // TODO LOOM remove after testing CONT_DOUBLE_NOP
  34 
  35 // We have interfaces for the following instructions:
  36 // - NativeInstruction
  37 // - - NativeCall
  38 // - - NativeMovConstReg
  39 // - - NativeMovConstRegPatching
  40 // - - NativeMovRegMem
  41 // - - NativeMovRegMemPatching
  42 // - - NativeJump
  43 // - - NativeFarJump
  44 // - - NativeIllegalOpCode
  45 // - - NativeGeneralJump
  46 // - - NativeReturn
  47 // - - NativeReturnX (return with argument)
  48 // - - NativePushConst
  49 // - - NativeTstRegMem
  50 
  51 // The base class for different kinds of native instruction abstractions.
  52 // Provides the primitive operations to manipulate code relative to this.
  53 
  54 class NativeInstruction {
  55   friend class Relocation;
  56 
  57  public:
  58   enum Intel_specific_constants {
  59     nop_instruction_code        = 0x90,
  60     nop_instruction_size        =    1
  61   };
  62 
  63   bool is_nop()                        { return ubyte_at(0) == nop_instruction_code; }
  64   inline bool is_call();
  65   inline bool is_call_reg();
  66   inline bool is_illegal();
  67   inline bool is_return();
  68   inline bool is_jump();
  69   inline bool is_jump_reg();
  70   inline bool is_far_jump();
  71   inline bool is_cond_jump();
  72   inline bool is_safepoint_poll();
  73   inline bool is_mov_literal64();
  74 
  75  protected:
  76   address addr_at(int offset) const    { return address(this) + offset; }
  77 
  78   s_char sbyte_at(int offset) const    { return *(s_char*) addr_at(offset); }
  79   u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
  80 
  81   jint int_at(int offset) const         { return *(jint*) addr_at(offset); }
  82 
  83   intptr_t ptr_at(int offset) const    { return *(intptr_t*) addr_at(offset); }
  84 
  85   oop  oop_at (int offset) const       { return *(oop*) addr_at(offset); }
  86 
  87 
  88   void set_char_at(int offset, char c)        { *addr_at(offset) = (u_char)c; wrote(offset); }
  89   void set_int_at(int offset, jint  i)        { *(jint*)addr_at(offset) = i;  wrote(offset); }
  90   void set_ptr_at (int offset, intptr_t  ptr) { *(intptr_t*) addr_at(offset) = ptr;  wrote(offset); }
  91   void set_oop_at (int offset, oop  o)        { *(oop*) addr_at(offset) = o;  wrote(offset); }
  92 
  93   // This doesn't really do anything on Intel, but it is the place where
  94   // cache invalidation belongs, generically:
  95   void wrote(int offset);
  96 
  97  public:
  98 
  99   // unit test stuff
 100   static void test() {}                 // override for testing
 101 
 102   inline friend NativeInstruction* nativeInstruction_at(address address);
 103 };
 104 
 105 inline NativeInstruction* nativeInstruction_at(address address) {
 106   NativeInstruction* inst = (NativeInstruction*)address;
 107 #ifdef ASSERT
 108   //inst->verify();
 109 #endif
 110   return inst;
 111 }
 112 
 113 class NativePltCall: public NativeInstruction {
 114 public:
 115   enum Intel_specific_constants {
 116     instruction_code           = 0xE8,
 117     instruction_size           =    5,
 118     instruction_offset         =    0,
 119     displacement_offset        =    1,
 120     return_address_offset      =    5
 121   };
 122   address instruction_address() const { return addr_at(instruction_offset); }
 123   address next_instruction_address() const { return addr_at(return_address_offset); }
 124   address displacement_address() const { return addr_at(displacement_offset); }
 125   int displacement() const { return (jint) int_at(displacement_offset); }
 126   address return_address() const { return addr_at(return_address_offset); }
 127   address destination() const;
 128   address plt_entry() const;
 129   address plt_jump() const;
 130   address plt_load_got() const;
 131   address plt_resolve_call() const;
 132   address plt_c2i_stub() const;
 133   void set_stub_to_clean();
 134 
 135   void  reset_to_plt_resolve_call();
 136   void  set_destination_mt_safe(address dest);
 137 
 138   void verify() const;
 139 };
 140 
 141 inline NativePltCall* nativePltCall_at(address address) {
 142   NativePltCall* call = (NativePltCall*) address;
 143 #ifdef ASSERT
 144   call->verify();
 145 #endif
 146   return call;
 147 }
 148 
 149 inline NativePltCall* nativePltCall_before(address addr) {
 150   address at = addr - NativePltCall::instruction_size;
 151   return nativePltCall_at(at);
 152 }
 153 
 154 class NativeCall;
 155 inline NativeCall* nativeCall_at(address address);
 156 // The NativeCall is an abstraction for accessing/manipulating native call imm32/rel32off
 157 // instructions (used to manipulate inline caches, primitive & dll calls, etc.).
 158 
 159 class NativeCall: public NativeInstruction {
 160  public:
 161   enum Intel_specific_constants {
 162     instruction_code            = 0xE8,
 163     instruction_size            =    5,
 164     instruction_offset          =    0,
 165     displacement_offset         =    1,
 166     return_address_offset       =    5
 167   };
 168 
 169   enum { cache_line_size = BytesPerWord };  // conservative estimate!
 170 
 171   address instruction_address() const       { return addr_at(instruction_offset); }
 172   address next_instruction_address() const  { return addr_at(return_address_offset); }
 173   int   displacement() const                { return (jint) int_at(displacement_offset); }
 174   address displacement_address() const      { return addr_at(displacement_offset); }
 175   address return_address() const            { return addr_at(return_address_offset); }
 176   address destination() const;
 177   void  set_destination(address dest)       {
 178 #ifdef AMD64
 179     intptr_t disp = dest - return_address();
 180     guarantee(disp == (intptr_t)(jint)disp, "must be 32-bit offset");
 181 #endif // AMD64
 182     set_int_at(displacement_offset, dest - return_address());
 183   }
 184   void  set_destination_mt_safe(address dest);
 185 
 186   void  verify_alignment() { assert((intptr_t)addr_at(displacement_offset) % BytesPerInt == 0, "must be aligned"); }
 187   void  verify();
 188   void  print();
 189 
 190   // Creation
 191   inline friend NativeCall* nativeCall_at(address address);
 192   inline friend NativeCall* nativeCall_before(address return_address);
 193 
 194   static bool is_call_at(address instr) {
 195     return ((*instr) & 0xFF) == NativeCall::instruction_code;
 196   }
 197 
 198   static bool is_call_before(address return_address) {
 199     return is_call_at(return_address - NativeCall::return_address_offset);
 200   }
 201 
 202   static bool is_call_to(address instr, address target) {
 203     return nativeInstruction_at(instr)->is_call() &&
 204       nativeCall_at(instr)->destination() == target;
 205   }
 206 
 207 #if INCLUDE_AOT
 208   static bool is_far_call(address instr, address target) {
 209     intptr_t disp = target - (instr + sizeof(int32_t));
 210     return !Assembler::is_simm32(disp);
 211   }
 212 #endif
 213 
 214   // MT-safe patching of a call instruction.
 215   static void insert(address code_pos, address entry);
 216 
 217   static void replace_mt_safe(address instr_addr, address code_buffer);
 218 };
 219 
 220 inline NativeCall* nativeCall_at(address address) {
 221   NativeCall* call = (NativeCall*)(address - NativeCall::instruction_offset);
 222 #ifdef ASSERT
 223   call->verify();
 224 #endif
 225   return call;
 226 }
 227 
 228 inline NativeCall* nativeCall_before(address return_address) {
 229   NativeCall* call = (NativeCall*)(return_address - NativeCall::return_address_offset);
 230 #ifdef ASSERT
 231   call->verify();
 232 #endif
 233   return call;
 234 }
 235 
 236 class NativeCallReg: public NativeInstruction {
 237  public:
 238   enum Intel_specific_constants {
 239     instruction_code            = 0xFF,
 240     instruction_offset          =    0,
 241     return_address_offset_norex =    2,
 242     return_address_offset_rex   =    3
 243   };
 244 
 245   int next_instruction_offset() const  {
 246     if (ubyte_at(0) == NativeCallReg::instruction_code) {
 247       return return_address_offset_norex;
 248     } else {
 249       return return_address_offset_rex;
 250     }
 251   }
 252 };
 253 
 254 // An interface for accessing/manipulating native mov reg, imm32 instructions.
 255 // (used to manipulate inlined 32bit data dll calls, etc.)
 256 class NativeMovConstReg: public NativeInstruction {
 257 #ifdef AMD64
 258   static const bool has_rex = true;
 259   static const int rex_size = 1;
 260 #else
 261   static const bool has_rex = false;
 262   static const int rex_size = 0;
 263 #endif // AMD64
 264  public:
 265   enum Intel_specific_constants {
 266     instruction_code            = 0xB8,
 267     instruction_size            =    1 + rex_size + wordSize,
 268     instruction_offset          =    0,
 269     data_offset                 =    1 + rex_size,
 270     next_instruction_offset     =    instruction_size,
 271     register_mask               = 0x07
 272   };
 273 
 274   address instruction_address() const       { return addr_at(instruction_offset); }
 275   address next_instruction_address() const  { return addr_at(next_instruction_offset); }
 276   intptr_t data() const                     { return ptr_at(data_offset); }
 277   void  set_data(intptr_t x)                { set_ptr_at(data_offset, x); }
 278 
 279   void  verify();
 280   void  print();
 281 
 282   // unit test stuff
 283   static void test() {}
 284 
 285   // Creation
 286   inline friend NativeMovConstReg* nativeMovConstReg_at(address address);
 287   inline friend NativeMovConstReg* nativeMovConstReg_before(address address);
 288 };
 289 
 290 inline NativeMovConstReg* nativeMovConstReg_at(address address) {
 291   NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_offset);
 292 #ifdef ASSERT
 293   test->verify();
 294 #endif
 295   return test;
 296 }
 297 
 298 inline NativeMovConstReg* nativeMovConstReg_before(address address) {
 299   NativeMovConstReg* test = (NativeMovConstReg*)(address - NativeMovConstReg::instruction_size - NativeMovConstReg::instruction_offset);
 300 #ifdef ASSERT
 301   test->verify();
 302 #endif
 303   return test;
 304 }
 305 
 306 class NativeMovConstRegPatching: public NativeMovConstReg {
 307  private:
 308     friend NativeMovConstRegPatching* nativeMovConstRegPatching_at(address address) {
 309     NativeMovConstRegPatching* test = (NativeMovConstRegPatching*)(address - instruction_offset);
 310     #ifdef ASSERT
 311       test->verify();
 312     #endif
 313     return test;
 314   }
 315 };
 316 
 317 // An interface for accessing/manipulating native moves of the form:
 318 //      mov[b/w/l/q] [reg + offset], reg   (instruction_code_reg2mem)
 319 //      mov[b/w/l/q] reg, [reg+offset]     (instruction_code_mem2reg
 320 //      mov[s/z]x[w/b/q] [reg + offset], reg
 321 //      fld_s  [reg+offset]
 322 //      fld_d  [reg+offset]
 323 //      fstp_s [reg + offset]
 324 //      fstp_d [reg + offset]
 325 //      mov_literal64  scratch,<pointer> ; mov[b/w/l/q] 0(scratch),reg | mov[b/w/l/q] reg,0(scratch)
 326 //
 327 // Warning: These routines must be able to handle any instruction sequences
 328 // that are generated as a result of the load/store byte,word,long
 329 // macros.  For example: The load_unsigned_byte instruction generates
 330 // an xor reg,reg inst prior to generating the movb instruction.  This
 331 // class must skip the xor instruction.
 332 
 333 class NativeMovRegMem: public NativeInstruction {
 334  public:
 335   enum Intel_specific_constants {
 336     instruction_prefix_wide_lo          = Assembler::REX,
 337     instruction_prefix_wide_hi          = Assembler::REX_WRXB,
 338     instruction_code_xor                = 0x33,
 339     instruction_extended_prefix         = 0x0F,
 340     instruction_code_mem2reg_movslq     = 0x63,
 341     instruction_code_mem2reg_movzxb     = 0xB6,
 342     instruction_code_mem2reg_movsxb     = 0xBE,
 343     instruction_code_mem2reg_movzxw     = 0xB7,
 344     instruction_code_mem2reg_movsxw     = 0xBF,
 345     instruction_operandsize_prefix      = 0x66,
 346     instruction_code_reg2mem            = 0x89,
 347     instruction_code_mem2reg            = 0x8b,
 348     instruction_code_reg2memb           = 0x88,
 349     instruction_code_mem2regb           = 0x8a,
 350     instruction_code_float_s            = 0xd9,
 351     instruction_code_float_d            = 0xdd,
 352     instruction_code_long_volatile      = 0xdf,
 353     instruction_code_xmm_ss_prefix      = 0xf3,
 354     instruction_code_xmm_sd_prefix      = 0xf2,
 355     instruction_code_xmm_code           = 0x0f,
 356     instruction_code_xmm_load           = 0x10,
 357     instruction_code_xmm_store          = 0x11,
 358     instruction_code_xmm_lpd            = 0x12,
 359 
 360     instruction_code_lea                = 0x8d,
 361 
 362     instruction_VEX_prefix_2bytes       = Assembler::VEX_2bytes,
 363     instruction_VEX_prefix_3bytes       = Assembler::VEX_3bytes,
 364     instruction_EVEX_prefix_4bytes      = Assembler::EVEX_4bytes,
 365 
 366     instruction_size                    = 4,
 367     instruction_offset                  = 0,
 368     data_offset                         = 2,
 369     next_instruction_offset             = 4
 370   };
 371 
 372   // helper
 373   int instruction_start() const;
 374 
 375   address instruction_address() const;
 376 
 377   address next_instruction_address() const;
 378 
 379   int   offset() const;
 380 
 381   void  set_offset(int x);
 382 
 383   void  add_offset_in_bytes(int add_offset)     { set_offset ( ( offset() + add_offset ) ); }
 384 
 385   void verify();
 386   void print ();
 387 
 388   // unit test stuff
 389   static void test() {}
 390 
 391  private:
 392   inline friend NativeMovRegMem* nativeMovRegMem_at (address address);
 393 };
 394 
 395 inline NativeMovRegMem* nativeMovRegMem_at (address address) {
 396   NativeMovRegMem* test = (NativeMovRegMem*)(address - NativeMovRegMem::instruction_offset);
 397 #ifdef ASSERT
 398   test->verify();
 399 #endif
 400   return test;
 401 }
 402 
 403 
 404 // An interface for accessing/manipulating native leal instruction of form:
 405 //        leal reg, [reg + offset]
 406 
 407 class NativeLoadAddress: public NativeMovRegMem {
 408 #ifdef AMD64
 409   static const bool has_rex = true;
 410   static const int rex_size = 1;
 411 #else
 412   static const bool has_rex = false;
 413   static const int rex_size = 0;
 414 #endif // AMD64
 415  public:
 416   enum Intel_specific_constants {
 417     instruction_prefix_wide             = Assembler::REX_W,
 418     instruction_prefix_wide_extended    = Assembler::REX_WB,
 419     lea_instruction_code                = 0x8D,
 420     mov64_instruction_code              = 0xB8
 421   };
 422 
 423   void verify();
 424   void print ();
 425 
 426   // unit test stuff
 427   static void test() {}
 428 
 429  private:
 430   friend NativeLoadAddress* nativeLoadAddress_at (address address) {
 431     NativeLoadAddress* test = (NativeLoadAddress*)(address - instruction_offset);
 432     #ifdef ASSERT
 433       test->verify();
 434     #endif
 435     return test;
 436   }
 437 };
 438 
 439 // destination is rbx or rax
 440 // mov rbx, [rip + offset]
 441 class NativeLoadGot: public NativeInstruction {
 442 #ifdef AMD64
 443   static const bool has_rex = true;
 444   static const int rex_size = 1;
 445 #else
 446   static const bool has_rex = false;
 447   static const int rex_size = 0;
 448 #endif
 449 public:
 450   enum Intel_specific_constants {
 451     rex_prefix = 0x48,
 452     instruction_code = 0x8b,
 453     modrm_rbx_code = 0x1d,
 454     modrm_rax_code = 0x05,
 455     instruction_length = 6 + rex_size,
 456     offset_offset = 2 + rex_size
 457   };
 458 
 459   address instruction_address() const { return addr_at(0); }
 460   address rip_offset_address() const { return addr_at(offset_offset); }
 461   int rip_offset() const { return int_at(offset_offset); }
 462   address return_address() const { return addr_at(instruction_length); }
 463   address got_address() const { return return_address() + rip_offset(); }
 464   address next_instruction_address() const { return return_address(); }
 465   intptr_t data() const;
 466   void set_data(intptr_t data) {
 467     intptr_t *addr = (intptr_t *) got_address();
 468     *addr = data;
 469   }
 470 
 471   void verify() const;
 472 private:
 473   void report_and_fail() const;
 474 };
 475 
 476 inline NativeLoadGot* nativeLoadGot_at(address addr) {
 477   NativeLoadGot* load = (NativeLoadGot*) addr;
 478 #ifdef ASSERT
 479   load->verify();
 480 #endif
 481   return load;
 482 }
 483 
 484 // jump rel32off
 485 
 486 class NativeJump: public NativeInstruction {
 487  public:
 488   enum Intel_specific_constants {
 489     instruction_code            = 0xe9,
 490     instruction_size            =    5,
 491     instruction_offset          =    0,
 492     data_offset                 =    1,
 493     next_instruction_offset     =    5
 494   };
 495 
 496   address instruction_address() const       { return addr_at(instruction_offset); }
 497   address next_instruction_address() const  { return addr_at(next_instruction_offset); }
 498   address jump_destination() const          {
 499      address dest = (int_at(data_offset)+next_instruction_address());
 500      // 32bit used to encode unresolved jmp as jmp -1
 501      // 64bit can't produce this so it used jump to self.
 502      // Now 32bit and 64bit use jump to self as the unresolved address
 503      // which the inline cache code (and relocs) know about
 504 
 505      // return -1 if jump to self
 506     dest = (dest == (address) this) ? (address) -1 : dest;
 507     return dest;
 508   }
 509 
 510   void  set_jump_destination(address dest)  {
 511     intptr_t val = dest - next_instruction_address();
 512     if (dest == (address) -1) {
 513       val = -5; // jump to self
 514     }
 515 #ifdef AMD64
 516     assert((labs(val)  & 0xFFFFFFFF00000000) == 0 || dest == (address)-1, "must be 32bit offset or -1");
 517 #endif // AMD64
 518     set_int_at(data_offset, (jint)val);
 519   }
 520 
 521   // Creation
 522   inline friend NativeJump* nativeJump_at(address address);
 523 
 524   void verify();
 525 
 526   // Unit testing stuff
 527   static void test() {}
 528 
 529   // Insertion of native jump instruction
 530   static void insert(address code_pos, address entry);
 531   // MT-safe insertion of native jump at verified method entry
 532   static void check_verified_entry_alignment(address entry, address verified_entry);
 533   static void patch_verified_entry(address entry, address verified_entry, address dest);
 534 };
 535 
 536 inline NativeJump* nativeJump_at(address address) {
 537   NativeJump* jump = (NativeJump*)(address - NativeJump::instruction_offset);
 538 #ifdef ASSERT
 539   jump->verify();
 540 #endif
 541   return jump;
 542 }
 543 
 544 // far jump reg
 545 class NativeFarJump: public NativeInstruction {
 546  public:
 547   address jump_destination() const;
 548 
 549   // Creation
 550   inline friend NativeFarJump* nativeFarJump_at(address address);
 551 
 552   void verify();
 553 
 554   // Unit testing stuff
 555   static void test() {}
 556 
 557 };
 558 
 559 inline NativeFarJump* nativeFarJump_at(address address) {
 560   NativeFarJump* jump = (NativeFarJump*)(address);
 561 #ifdef ASSERT
 562   jump->verify();
 563 #endif
 564   return jump;
 565 }
 566 
 567 // Handles all kinds of jump on Intel. Long/far, conditional/unconditional
 568 class NativeGeneralJump: public NativeInstruction {
 569  public:
 570   enum Intel_specific_constants {
 571     // Constants does not apply, since the lengths and offsets depends on the actual jump
 572     // used
 573     // Instruction codes:
 574     //   Unconditional jumps: 0xE9    (rel32off), 0xEB (rel8off)
 575     //   Conditional jumps:   0x0F8x  (rel32off), 0x7x (rel8off)
 576     unconditional_long_jump  = 0xe9,
 577     unconditional_short_jump = 0xeb,
 578     instruction_size = 5
 579   };
 580 
 581   address instruction_address() const       { return addr_at(0); }
 582   address jump_destination()    const;
 583 
 584   // Creation
 585   inline friend NativeGeneralJump* nativeGeneralJump_at(address address);
 586 
 587   // Insertion of native general jump instruction
 588   static void insert_unconditional(address code_pos, address entry);
 589   static void replace_mt_safe(address instr_addr, address code_buffer);
 590 
 591   void verify();
 592 };
 593 
 594 inline NativeGeneralJump* nativeGeneralJump_at(address address) {
 595   NativeGeneralJump* jump = (NativeGeneralJump*)(address);
 596   debug_only(jump->verify();)
 597   return jump;
 598 }
 599 
 600 class NativeGotJump: public NativeInstruction {
 601 public:
 602   enum Intel_specific_constants {
 603     instruction_code = 0xff,
 604     instruction_offset = 0,
 605     instruction_size = 6,
 606     rip_offset = 2
 607   };
 608 
 609   void verify() const;
 610   address instruction_address() const { return addr_at(instruction_offset); }
 611   address destination() const;
 612   address return_address() const { return addr_at(instruction_size); }
 613   int got_offset() const { return (jint) int_at(rip_offset); }
 614   address got_address() const { return return_address() + got_offset(); }
 615   address next_instruction_address() const { return addr_at(instruction_size); }
 616   bool is_GotJump() const { return ubyte_at(0) == instruction_code; }
 617 
 618   void set_jump_destination(address dest)  {
 619     address *got_entry = (address *) got_address();
 620     *got_entry = dest;
 621   }
 622 };
 623 
 624 inline NativeGotJump* nativeGotJump_at(address addr) {
 625   NativeGotJump* jump = (NativeGotJump*)(addr);
 626   debug_only(jump->verify());
 627   return jump;
 628 }
 629 
 630 class NativePopReg : public NativeInstruction {
 631  public:
 632   enum Intel_specific_constants {
 633     instruction_code            = 0x58,
 634     instruction_size            =    1,
 635     instruction_offset          =    0,
 636     data_offset                 =    1,
 637     next_instruction_offset     =    1
 638   };
 639 
 640   // Insert a pop instruction
 641   static void insert(address code_pos, Register reg);
 642 };
 643 
 644 
 645 class NativeIllegalInstruction: public NativeInstruction {
 646  public:
 647   enum Intel_specific_constants {
 648     instruction_code            = 0x0B0F,    // Real byte order is: 0x0F, 0x0B
 649     instruction_size            =    2,
 650     instruction_offset          =    0,
 651     next_instruction_offset     =    2
 652   };
 653 
 654   // Insert illegal opcode as specific address
 655   static void insert(address code_pos);
 656 };
 657 
 658 // return instruction that does not pop values of the stack
 659 class NativeReturn: public NativeInstruction {
 660  public:
 661   enum Intel_specific_constants {
 662     instruction_code            = 0xC3,
 663     instruction_size            =    1,
 664     instruction_offset          =    0,
 665     next_instruction_offset     =    1
 666   };
 667 };
 668 
 669 // return instruction that does pop values of the stack
 670 class NativeReturnX: public NativeInstruction {
 671  public:
 672   enum Intel_specific_constants {
 673     instruction_code            = 0xC2,
 674     instruction_size            =    2,
 675     instruction_offset          =    0,
 676     next_instruction_offset     =    2
 677   };
 678 };
 679 
 680 // Simple test vs memory
 681 class NativeTstRegMem: public NativeInstruction {
 682  public:
 683   enum Intel_specific_constants {
 684     instruction_rex_prefix_mask = 0xF0,
 685     instruction_rex_prefix      = Assembler::REX,
 686     instruction_rex_b_prefix    = Assembler::REX_B,
 687     instruction_code_memXregl   = 0x85,
 688     modrm_mask                  = 0x38, // select reg from the ModRM byte
 689     modrm_reg                   = 0x00  // rax
 690   };
 691 };
 692 
 693 inline bool NativeInstruction::is_illegal()      { return (short)int_at(0) == (short)NativeIllegalInstruction::instruction_code; }
 694 inline bool NativeInstruction::is_call()         { return ubyte_at(0) == NativeCall::instruction_code; }
 695 inline bool NativeInstruction::is_call_reg()     { return ubyte_at(0) == NativeCallReg::instruction_code ||
 696                                                           (ubyte_at(1) == NativeCallReg::instruction_code &&
 697                                                            (ubyte_at(0) == Assembler::REX || ubyte_at(0) == Assembler::REX_B)); }
 698 inline bool NativeInstruction::is_return()       { return ubyte_at(0) == NativeReturn::instruction_code ||
 699                                                           ubyte_at(0) == NativeReturnX::instruction_code; }
 700 inline bool NativeInstruction::is_jump()         { return ubyte_at(0) == NativeJump::instruction_code ||
 701                                                           ubyte_at(0) == 0xEB; /* short jump */ }
 702 inline bool NativeInstruction::is_jump_reg()     {
 703   int pos = 0;
 704   if (ubyte_at(0) == Assembler::REX_B) pos = 1;
 705   return ubyte_at(pos) == 0xFF && (ubyte_at(pos + 1) & 0xF0) == 0xE0;
 706 }
 707 inline bool NativeInstruction::is_far_jump()     { return is_mov_literal64(); }
 708 inline bool NativeInstruction::is_cond_jump()    { return (int_at(0) & 0xF0FF) == 0x800F /* long jump */ ||
 709                                                           (ubyte_at(0) & 0xF0) == 0x70;  /* short jump */ }
 710 inline bool NativeInstruction::is_safepoint_poll() {
 711   if (SafepointMechanism::uses_thread_local_poll()) {
 712 #ifdef AMD64
 713     const bool has_rex_prefix = ubyte_at(0) == NativeTstRegMem::instruction_rex_b_prefix;
 714     const int test_offset = has_rex_prefix ? 1 : 0;
 715 #else
 716     const int test_offset = 0;
 717 #endif
 718     const bool is_test_opcode = ubyte_at(test_offset) == NativeTstRegMem::instruction_code_memXregl;
 719     const bool is_rax_target = (ubyte_at(test_offset + 1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg;
 720     return is_test_opcode && is_rax_target;
 721   }
 722 #ifdef AMD64
 723   // Try decoding a near safepoint first:
 724   if (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
 725       ubyte_at(1) == 0x05) { // 00 rax 101
 726     address fault = addr_at(6) + int_at(2);
 727     NOT_JVMCI(assert(!Assembler::is_polling_page_far(), "unexpected poll encoding");)
 728     return os::is_poll_address(fault);
 729   }
 730   // Now try decoding a far safepoint:
 731   // two cases, depending on the choice of the base register in the address.
 732   if (((ubyte_at(0) & NativeTstRegMem::instruction_rex_prefix_mask) == NativeTstRegMem::instruction_rex_prefix &&
 733        ubyte_at(1) == NativeTstRegMem::instruction_code_memXregl &&
 734        (ubyte_at(2) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg) ||
 735       (ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl &&
 736        (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg)) {
 737     NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");)
 738     return true;
 739   }
 740   return false;
 741 #else
 742   return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
 743            ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
 744            (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
 745            (os::is_poll_address((address)int_at(2)));
 746 #endif // AMD64
 747 }
 748 
 749 inline bool NativeInstruction::is_mov_literal64() {
 750 #ifdef AMD64
 751   return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
 752           (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
 753 #else
 754   return false;
 755 #endif // AMD64
 756 }
 757 
 758 class NativePostCallNop: public NativeInstruction {
 759 public:
 760   enum Intel_specific_constants {
 761     instruction_code = 0x0f,
 762     instruction_size = 8,
 763     instruction_offset = 0,
 764     displacement_offset = 4
 765   };
 766 
 767   bool check() const {
 768   #ifdef CONT_DOUBLE_NOP
 769     return check1() && int2_data() == 0;
 770   #else
 771     return int_at(0) == 0x841f0f; 
 772   #endif
 773   }
 774   int displacement() const { return (jint) int_at(displacement_offset); }
 775   void patch(jint diff);
 776 
 777 #ifdef CONT_DOUBLE_NOP
 778   bool check1() const { return (int_at(0) & 0xffffff) == 0x841f0f && (int_at(8) & 0xffffff) == 0x841f0f; }
 779   uint16_t short_data() const { return (uint16_t)((ubyte_at(3) << 8) | ubyte_at(11)); }
 780   uint32_t int1_data()  const { return (uint32_t)int_at(4); }
 781   uint32_t int2_data()  const { return (uint32_t)int_at(12); }
 782   void patch(uint32_t int1, uint32_t int2);
 783   void patch_int1(uint32_t int1);
 784   void patch_int2(uint32_t int2);
 785 
 786   // int mode() {
 787   //   assert (int2_data() == 0 || int1_data() != 0, "");
 788   //   return static_cast<bool>(int1_data()) + static_cast<bool>(int2_data());
 789   // }
 790 
 791   bool is_mode2() { return int2_data() != 0; } // mode2 is used for fast continuation freeze/thaw metadata
 792 #endif
 793 };
 794 
 795 inline NativePostCallNop* nativePostCallNop_at(address address) {
 796   NativePostCallNop* nop = (NativePostCallNop*) address;
 797 #ifdef CONT_DOUBLE_NOP
 798   if (nop->check1()) {
 799 #else
 800   if (nop->check()) {
 801 #endif
 802     return nop;
 803   }
 804   return NULL;
 805 }
 806 
 807 inline NativePostCallNop* nativePostCallNop_unsafe_at(address address) {
 808   NativePostCallNop* nop = (NativePostCallNop*) address;
 809 #ifdef CONT_DOUBLE_NOP
 810   assert (nop->check1(), "");
 811 #else
 812   assert (nop->check(), "");
 813 #endif
 814   return nop;
 815 }
 816 
 817 #endif // CPU_X86_NATIVEINST_X86_HPP