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src/hotspot/cpu/x86/nativeInst_x86.hpp

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 65   inline bool is_jump();
 66   inline bool is_jump_reg();
 67   inline bool is_far_jump();
 68   inline bool is_cond_jump();
 69   inline bool is_safepoint_poll();
 70   inline bool is_mov_literal64();
 71 
 72  protected:
 73   address addr_at(int offset) const    { return address(this) + offset; }
 74 
 75   s_char sbyte_at(int offset) const    { return *(s_char*) addr_at(offset); }
 76   u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
 77 
 78   jint int_at(int offset) const         { return *(jint*) addr_at(offset); }
 79 
 80   intptr_t ptr_at(int offset) const    { return *(intptr_t*) addr_at(offset); }
 81 
 82   oop  oop_at (int offset) const       { return *(oop*) addr_at(offset); }
 83 
 84 
 85   void set_char_at(int offset, char c)        { *addr_at(offset) = (u_char)c; wrote(offset); }
 86   void set_int_at(int offset, jint  i)        { *(jint*)addr_at(offset) = i;  wrote(offset); }
 87   void set_ptr_at (int offset, intptr_t  ptr) { *(intptr_t*) addr_at(offset) = ptr;  wrote(offset); }
 88   void set_oop_at (int offset, oop  o)        { *(oop*) addr_at(offset) = o;  wrote(offset); }
 89 
 90   // This doesn't really do anything on Intel, but it is the place where
 91   // cache invalidation belongs, generically:
 92   void wrote(int offset);
 93 
 94  public:
 95 
 96   inline friend NativeInstruction* nativeInstruction_at(address address);
 97 };
 98 
 99 inline NativeInstruction* nativeInstruction_at(address address) {
100   NativeInstruction* inst = (NativeInstruction*)address;
101 #ifdef ASSERT
102   //inst->verify();
103 #endif
104   return inst;
105 }

708 #ifdef AMD64
709   const bool has_rex_prefix = ubyte_at(0) == NativeTstRegMem::instruction_rex_b_prefix;
710   const int test_offset = has_rex_prefix ? 1 : 0;
711 #else
712   const int test_offset = 0;
713 #endif
714   const bool is_test_opcode = ubyte_at(test_offset) == NativeTstRegMem::instruction_code_memXregl;
715   const bool is_rax_target = (ubyte_at(test_offset + 1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg;
716   return is_test_opcode && is_rax_target;
717 }
718 
719 inline bool NativeInstruction::is_mov_literal64() {
720 #ifdef AMD64
721   return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
722           (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
723 #else
724   return false;
725 #endif // AMD64
726 }
727 




















































728 #endif // CPU_X86_NATIVEINST_X86_HPP

 65   inline bool is_jump();
 66   inline bool is_jump_reg();
 67   inline bool is_far_jump();
 68   inline bool is_cond_jump();
 69   inline bool is_safepoint_poll();
 70   inline bool is_mov_literal64();
 71 
 72  protected:
 73   address addr_at(int offset) const    { return address(this) + offset; }
 74 
 75   s_char sbyte_at(int offset) const    { return *(s_char*) addr_at(offset); }
 76   u_char ubyte_at(int offset) const    { return *(u_char*) addr_at(offset); }
 77 
 78   jint int_at(int offset) const         { return *(jint*) addr_at(offset); }
 79 
 80   intptr_t ptr_at(int offset) const    { return *(intptr_t*) addr_at(offset); }
 81 
 82   oop  oop_at (int offset) const       { return *(oop*) addr_at(offset); }
 83 
 84 
 85   void set_char_at(int offset, u_char c)        { *addr_at(offset) = c; wrote(offset); }
 86   void set_int_at(int offset, jint  i)        { *(jint*)addr_at(offset) = i;  wrote(offset); }
 87   void set_ptr_at (int offset, intptr_t  ptr) { *(intptr_t*) addr_at(offset) = ptr;  wrote(offset); }
 88   void set_oop_at (int offset, oop  o)        { *(oop*) addr_at(offset) = o;  wrote(offset); }
 89 
 90   // This doesn't really do anything on Intel, but it is the place where
 91   // cache invalidation belongs, generically:
 92   void wrote(int offset);
 93 
 94  public:
 95 
 96   inline friend NativeInstruction* nativeInstruction_at(address address);
 97 };
 98 
 99 inline NativeInstruction* nativeInstruction_at(address address) {
100   NativeInstruction* inst = (NativeInstruction*)address;
101 #ifdef ASSERT
102   //inst->verify();
103 #endif
104   return inst;
105 }

708 #ifdef AMD64
709   const bool has_rex_prefix = ubyte_at(0) == NativeTstRegMem::instruction_rex_b_prefix;
710   const int test_offset = has_rex_prefix ? 1 : 0;
711 #else
712   const int test_offset = 0;
713 #endif
714   const bool is_test_opcode = ubyte_at(test_offset) == NativeTstRegMem::instruction_code_memXregl;
715   const bool is_rax_target = (ubyte_at(test_offset + 1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg;
716   return is_test_opcode && is_rax_target;
717 }
718 
719 inline bool NativeInstruction::is_mov_literal64() {
720 #ifdef AMD64
721   return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
722           (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
723 #else
724   return false;
725 #endif // AMD64
726 }
727 
728 class NativePostCallNop: public NativeInstruction {
729 public:
730   enum Intel_specific_constants {
731     instruction_code = 0x0f,
732     instruction_size = 8,
733     instruction_offset = 0,
734     displacement_offset = 4
735   };
736 
737   bool check() const { return int_at(0) == 0x841f0f; }
738   int displacement() const { return (jint) int_at(displacement_offset); }
739   void patch(jint diff);
740   void make_deopt();
741 };
742 
743 inline NativePostCallNop* nativePostCallNop_at(address address) {
744   NativePostCallNop* nop = (NativePostCallNop*) address;
745   if (nop->check()) {
746     return nop;
747   }
748   return NULL;
749 }
750 
751 inline NativePostCallNop* nativePostCallNop_unsafe_at(address address) {
752   NativePostCallNop* nop = (NativePostCallNop*) address;
753   assert (nop->check(), "");
754   return nop;
755 }
756 
757 class NativeDeoptInstruction: public NativeInstruction {
758  public:
759   enum Intel_specific_constants {
760     instruction_prefix          = 0x0F,
761     instruction_code            = 0xFF,
762     instruction_size            =    2,
763     instruction_offset          =    0,
764   };
765 
766   address instruction_address() const       { return addr_at(instruction_offset); }
767   address next_instruction_address() const  { return addr_at(instruction_size); }
768 
769   void  verify();
770 
771   static bool is_deopt_at(address instr) {
772     return ((*instr) & 0xFF) == NativeDeoptInstruction::instruction_prefix && 
773       ((*(instr+1)) & 0xFF) == NativeDeoptInstruction::instruction_code;
774   }
775 
776   // MT-safe patching
777   static void insert(address code_pos);
778 };
779 
780 #endif // CPU_X86_NATIVEINST_X86_HPP
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