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src/hotspot/cpu/x86/nativeInst_x86.hpp

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  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_NATIVEINST_X86_HPP
  26 #define CPU_X86_NATIVEINST_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "runtime/icache.hpp"
  30 #include "runtime/os.hpp"
  31 #include "runtime/safepointMechanism.hpp"
  32 


  33 // We have interfaces for the following instructions:
  34 // - NativeInstruction
  35 // - - NativeCall
  36 // - - NativeMovConstReg
  37 // - - NativeMovConstRegPatching
  38 // - - NativeMovRegMem
  39 // - - NativeMovRegMemPatching
  40 // - - NativeJump
  41 // - - NativeFarJump
  42 // - - NativeIllegalOpCode
  43 // - - NativeGeneralJump
  44 // - - NativeReturn
  45 // - - NativeReturnX (return with argument)
  46 // - - NativePushConst
  47 // - - NativeTstRegMem
  48 
  49 // The base class for different kinds of native instruction abstractions.
  50 // Provides the primitive operations to manipulate code relative to this.
  51 
  52 class NativeInstruction {


 734        (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg)) {
 735     NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");)
 736     return true;
 737   }
 738   return false;
 739 #else
 740   return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
 741            ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
 742            (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
 743            (os::is_poll_address((address)int_at(2)));
 744 #endif // AMD64
 745 }
 746 
 747 inline bool NativeInstruction::is_mov_literal64() {
 748 #ifdef AMD64
 749   return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
 750           (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
 751 #else
 752   return false;
 753 #endif // AMD64



























































 754 }
 755 
 756 #endif // CPU_X86_NATIVEINST_X86_HPP


  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_NATIVEINST_X86_HPP
  26 #define CPU_X86_NATIVEINST_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "runtime/icache.hpp"
  30 #include "runtime/os.hpp"
  31 #include "runtime/safepointMechanism.hpp"
  32 
  33 #include "runtime/continuation.hpp" // TODO LOOM remove after testing CONT_DOUBLE_NOP
  34 
  35 // We have interfaces for the following instructions:
  36 // - NativeInstruction
  37 // - - NativeCall
  38 // - - NativeMovConstReg
  39 // - - NativeMovConstRegPatching
  40 // - - NativeMovRegMem
  41 // - - NativeMovRegMemPatching
  42 // - - NativeJump
  43 // - - NativeFarJump
  44 // - - NativeIllegalOpCode
  45 // - - NativeGeneralJump
  46 // - - NativeReturn
  47 // - - NativeReturnX (return with argument)
  48 // - - NativePushConst
  49 // - - NativeTstRegMem
  50 
  51 // The base class for different kinds of native instruction abstractions.
  52 // Provides the primitive operations to manipulate code relative to this.
  53 
  54 class NativeInstruction {


 736        (ubyte_at(1) & NativeTstRegMem::modrm_mask) == NativeTstRegMem::modrm_reg)) {
 737     NOT_JVMCI(assert(Assembler::is_polling_page_far(), "unexpected poll encoding");)
 738     return true;
 739   }
 740   return false;
 741 #else
 742   return ( ubyte_at(0) == NativeMovRegMem::instruction_code_mem2reg ||
 743            ubyte_at(0) == NativeTstRegMem::instruction_code_memXregl ) &&
 744            (ubyte_at(1)&0xC7) == 0x05 && /* Mod R/M == disp32 */
 745            (os::is_poll_address((address)int_at(2)));
 746 #endif // AMD64
 747 }
 748 
 749 inline bool NativeInstruction::is_mov_literal64() {
 750 #ifdef AMD64
 751   return ((ubyte_at(0) == Assembler::REX_W || ubyte_at(0) == Assembler::REX_WB) &&
 752           (ubyte_at(1) & (0xff ^ NativeMovConstReg::register_mask)) == 0xB8);
 753 #else
 754   return false;
 755 #endif // AMD64
 756 }
 757 
 758 class NativePostCallNop: public NativeInstruction {
 759 public:
 760   enum Intel_specific_constants {
 761     instruction_code = 0x0f,
 762     instruction_size = 8,
 763     instruction_offset = 0,
 764     displacement_offset = 4
 765   };
 766 
 767   bool check() const {
 768   #ifdef CONT_DOUBLE_NOP
 769     return check1() && int2_data() == 0;
 770   #else
 771     return int_at(0) == 0x841f0f; 
 772   #endif
 773   }
 774   int displacement() const { return (jint) int_at(displacement_offset); }
 775   void patch(jint diff);
 776 
 777 #ifdef CONT_DOUBLE_NOP
 778   bool check1() const { return (int_at(0) & 0xffffff) == 0x841f0f && (int_at(8) & 0xffffff) == 0x841f0f; }
 779   uint16_t short_data() const { return (uint16_t)((ubyte_at(3) << 8) | ubyte_at(11)); }
 780   uint32_t int1_data()  const { return (uint32_t)int_at(4); }
 781   uint32_t int2_data()  const { return (uint32_t)int_at(12); }
 782   void patch(uint32_t int1, uint32_t int2);
 783   void patch_int1(uint32_t int1);
 784   void patch_int2(uint32_t int2);
 785 
 786   // int mode() {
 787   //   assert (int2_data() == 0 || int1_data() != 0, "");
 788   //   return static_cast<bool>(int1_data()) + static_cast<bool>(int2_data());
 789   // }
 790 
 791   bool is_mode2() { return int2_data() != 0; } // mode2 is used for fast continuation freeze/thaw metadata
 792 #endif
 793 };
 794 
 795 inline NativePostCallNop* nativePostCallNop_at(address address) {
 796   NativePostCallNop* nop = (NativePostCallNop*) address;
 797 #ifdef CONT_DOUBLE_NOP
 798   if (nop->check1()) {
 799 #else
 800   if (nop->check()) {
 801 #endif
 802     return nop;
 803   }
 804   return NULL;
 805 }
 806 
 807 inline NativePostCallNop* nativePostCallNop_unsafe_at(address address) {
 808   NativePostCallNop* nop = (NativePostCallNop*) address;
 809 #ifdef CONT_DOUBLE_NOP
 810   assert (nop->check1(), "");
 811 #else
 812   assert (nop->check(), "");
 813 #endif
 814   return nop;
 815 }
 816 
 817 #endif // CPU_X86_NATIVEINST_X86_HPP
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