1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_VERSION_X86_HPP
  26 #define CPU_X86_VM_VERSION_X86_HPP
  27 
  28 #include "runtime/abstract_vm_version.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "utilities/sizes.hpp"
  31 
  32 class VM_Version : public Abstract_VM_Version {
  33   friend class VMStructs;
  34   friend class JVMCIVMStructs;
  35 
  36  public:
  37   // cpuid result register layouts.  These are all unions of a uint32_t
  38   // (in case anyone wants access to the register as a whole) and a bitfield.
  39 
  40   union StdCpuid1Eax {
  41     uint32_t value;
  42     struct {
  43       uint32_t stepping   : 4,
  44                model      : 4,
  45                family     : 4,
  46                proc_type  : 2,
  47                           : 2,
  48                ext_model  : 4,
  49                ext_family : 8,
  50                           : 4;
  51     } bits;
  52   };
  53 
  54   union StdCpuid1Ebx { // example, unused
  55     uint32_t value;
  56     struct {
  57       uint32_t brand_id         : 8,
  58                clflush_size     : 8,
  59                threads_per_cpu  : 8,
  60                apic_id          : 8;
  61     } bits;
  62   };
  63 
  64   union StdCpuid1Ecx {
  65     uint32_t value;
  66     struct {
  67       uint32_t sse3     : 1,
  68                clmul    : 1,
  69                         : 1,
  70                monitor  : 1,
  71                         : 1,
  72                vmx      : 1,
  73                         : 1,
  74                est      : 1,
  75                         : 1,
  76                ssse3    : 1,
  77                cid      : 1,
  78                         : 1,
  79                fma      : 1,
  80                cmpxchg16: 1,
  81                         : 4,
  82                dca      : 1,
  83                sse4_1   : 1,
  84                sse4_2   : 1,
  85                         : 2,
  86                popcnt   : 1,
  87                         : 1,
  88                aes      : 1,
  89                         : 1,
  90                osxsave  : 1,
  91                avx      : 1,
  92                         : 2,
  93                hv       : 1;
  94     } bits;
  95   };
  96 
  97   union StdCpuid1Edx {
  98     uint32_t value;
  99     struct {
 100       uint32_t          : 4,
 101                tsc      : 1,
 102                         : 3,
 103                cmpxchg8 : 1,
 104                         : 6,
 105                cmov     : 1,
 106                         : 3,
 107                clflush  : 1,
 108                         : 3,
 109                mmx      : 1,
 110                fxsr     : 1,
 111                sse      : 1,
 112                sse2     : 1,
 113                         : 1,
 114                ht       : 1,
 115                         : 3;
 116     } bits;
 117   };
 118 
 119   union DcpCpuid4Eax {
 120     uint32_t value;
 121     struct {
 122       uint32_t cache_type    : 5,
 123                              : 21,
 124                cores_per_cpu : 6;
 125     } bits;
 126   };
 127 
 128   union DcpCpuid4Ebx {
 129     uint32_t value;
 130     struct {
 131       uint32_t L1_line_size  : 12,
 132                partitions    : 10,
 133                associativity : 10;
 134     } bits;
 135   };
 136 
 137   union TplCpuidBEbx {
 138     uint32_t value;
 139     struct {
 140       uint32_t logical_cpus : 16,
 141                             : 16;
 142     } bits;
 143   };
 144 
 145   union ExtCpuid1Ecx {
 146     uint32_t value;
 147     struct {
 148       uint32_t LahfSahf     : 1,
 149                CmpLegacy    : 1,
 150                             : 3,
 151                lzcnt_intel  : 1,
 152                lzcnt        : 1,
 153                sse4a        : 1,
 154                misalignsse  : 1,
 155                prefetchw    : 1,
 156                             : 22;
 157     } bits;
 158   };
 159 
 160   union ExtCpuid1Edx {
 161     uint32_t value;
 162     struct {
 163       uint32_t           : 22,
 164                mmx_amd   : 1,
 165                mmx       : 1,
 166                fxsr      : 1,
 167                          : 4,
 168                long_mode : 1,
 169                tdnow2    : 1,
 170                tdnow     : 1;
 171     } bits;
 172   };
 173 
 174   union ExtCpuid5Ex {
 175     uint32_t value;
 176     struct {
 177       uint32_t L1_line_size : 8,
 178                L1_tag_lines : 8,
 179                L1_assoc     : 8,
 180                L1_size      : 8;
 181     } bits;
 182   };
 183 
 184   union ExtCpuid7Edx {
 185     uint32_t value;
 186     struct {
 187       uint32_t               : 8,
 188               tsc_invariance : 1,
 189                              : 23;
 190     } bits;
 191   };
 192 
 193   union ExtCpuid8Ecx {
 194     uint32_t value;
 195     struct {
 196       uint32_t cores_per_cpu : 8,
 197                              : 24;
 198     } bits;
 199   };
 200 
 201   union SefCpuid7Eax {
 202     uint32_t value;
 203   };
 204 
 205   union SefCpuid7Ebx {
 206     uint32_t value;
 207     struct {
 208       uint32_t fsgsbase : 1,
 209                         : 2,
 210                    bmi1 : 1,
 211                         : 1,
 212                    avx2 : 1,
 213                         : 2,
 214                    bmi2 : 1,
 215                    erms : 1,
 216                         : 1,
 217                     rtm : 1,
 218                         : 4,
 219                 avx512f : 1,
 220                avx512dq : 1,
 221                         : 1,
 222                     adx : 1,
 223                         : 3,
 224              clflushopt : 1,
 225                    clwb : 1,
 226                         : 1,
 227                avx512pf : 1,
 228                avx512er : 1,
 229                avx512cd : 1,
 230                     sha : 1,
 231                avx512bw : 1,
 232                avx512vl : 1;
 233     } bits;
 234   };
 235 
 236   union SefCpuid7Ecx {
 237     uint32_t value;
 238     struct {
 239       uint32_t prefetchwt1 : 1,
 240                avx512_vbmi : 1,
 241                       umip : 1,
 242                        pku : 1,
 243                      ospke : 1,
 244                            : 1,
 245               avx512_vbmi2 : 1,
 246                            : 1,
 247                       gfni : 1,
 248                       vaes : 1,
 249          avx512_vpclmulqdq : 1,
 250                avx512_vnni : 1,
 251              avx512_bitalg : 1,
 252                            : 1,
 253           avx512_vpopcntdq : 1,
 254                            : 17;
 255     } bits;
 256   };
 257 
 258   union SefCpuid7Edx {
 259     uint32_t value;
 260     struct {
 261       uint32_t             : 2,
 262              avx512_4vnniw : 1,
 263              avx512_4fmaps : 1,
 264                            : 10,
 265                  serialize : 1,
 266                            : 17;
 267     } bits;
 268   };
 269 
 270   union ExtCpuid1EEbx {
 271     uint32_t value;
 272     struct {
 273       uint32_t                  : 8,
 274                threads_per_core : 8,
 275                                 : 16;
 276     } bits;
 277   };
 278 
 279   union XemXcr0Eax {
 280     uint32_t value;
 281     struct {
 282       uint32_t x87     : 1,
 283                sse     : 1,
 284                ymm     : 1,
 285                bndregs : 1,
 286                bndcsr  : 1,
 287                opmask  : 1,
 288                zmm512  : 1,
 289                zmm32   : 1,
 290                        : 24;
 291     } bits;
 292   };
 293 
 294 protected:
 295   static int _cpu;
 296   static int _model;
 297   static int _stepping;
 298 
 299   static bool _has_intel_jcc_erratum;
 300 
 301   static address   _cpuinfo_segv_addr; // address of instruction which causes SEGV
 302   static address   _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
 303 
 304   enum Feature_Flag : uint64_t {
 305 #define CPU_FEATURE_FLAGS(decl) \
 306     decl(CX8,               "cx8",               0)  /*  next bits are from cpuid 1 (EDX) */ \
 307     decl(CMOV,              "cmov",              1)  \
 308     decl(FXSR,              "fxsr",              2)  \
 309     decl(HT,                "ht",                3)  \
 310                                                      \
 311     decl(MMX,               "mmx",               4)  \
 312     decl(3DNOW_PREFETCH,    "3dnowpref",         5)  /* Processor supports 3dnow prefetch and prefetchw instructions */ \
 313                                                      /* may not necessarily support other 3dnow instructions */ \
 314     decl(SSE,               "sse",               6)  \
 315     decl(SSE2,              "sse2",              7)  \
 316                                                      \
 317     decl(SSE3,              "sse3",              8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
 318     decl(SSSE3,             "ssse3",             9 ) \
 319     decl(SSE4A,             "sse4a",             10) \
 320     decl(SSE4_1,            "sse4.1",            11) \
 321                                                      \
 322     decl(SSE4_2,            "sse4.2",            12) \
 323     decl(POPCNT,            "popcnt",            13) \
 324     decl(LZCNT,             "lzcnt",             14) \
 325     decl(TSC,               "tsc",               15) \
 326                                                      \
 327     decl(TSCINV_BIT,        "tscinvbit",         16) \
 328     decl(TSCINV,            "tscinv",            17) \
 329     decl(AVX,               "avx",               18) \
 330     decl(AVX2,              "avx2",              19) \
 331                                                      \
 332     decl(AES,               "aes",               20) \
 333     decl(ERMS,              "erms",              21) /* enhanced 'rep movsb/stosb' instructions */ \
 334     decl(CLMUL,             "clmul",             22) /* carryless multiply for CRC */ \
 335     decl(BMI1,              "bmi1",              23) \
 336                                                      \
 337     decl(BMI2,              "bmi2",              24) \
 338     decl(RTM,               "rtm",               25) /* Restricted Transactional Memory instructions */ \
 339     decl(ADX,               "adx",               26) \
 340     decl(AVX512F,           "avx512f",           27) /* AVX 512bit foundation instructions */ \
 341                                                      \
 342     decl(AVX512DQ,          "avx512dq",          28) \
 343     decl(AVX512PF,          "avx512pf",          29) \
 344     decl(AVX512ER,          "avx512er",          30) \
 345     decl(AVX512CD,          "avx512cd",          31) \
 346                                                      \
 347     decl(AVX512BW,          "avx512bw",          32) /* Byte and word vector instructions */ \
 348     decl(AVX512VL,          "avx512vl",          33) /* EVEX instructions with smaller vector length */ \
 349     decl(SHA,               "sha",               34) /* SHA instructions */ \
 350     decl(FMA,               "fma",               35) /* FMA instructions */ \
 351                                                      \
 352     decl(VZEROUPPER,        "vzeroupper",        36) /* Vzeroupper instruction */ \
 353     decl(AVX512_VPOPCNTDQ,  "avx512_vpopcntdq",  37) /* Vector popcount */ \
 354     decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
 355     decl(AVX512_VAES,       "avx512_vaes",       39) /* Vector AES instruction */ \
 356                                                      \
 357     decl(AVX512_VNNI,       "avx512_vnni",       40) /* Vector Neural Network Instructions */ \
 358     decl(FLUSH,             "clflush",           41) /* flush instruction */ \
 359     decl(FLUSHOPT,          "clflushopt",        42) /* flusopth instruction */ \
 360     decl(CLWB,              "clwb",              43) /* clwb instruction */ \
 361                                                      \
 362     decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
 363     decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
 364     decl(HV,                "hv",                46) /* Hypervisor instructions */ \
 365     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */
 366 
 367 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
 368     CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
 369 #undef DECLARE_CPU_FEATURE_FLAG
 370   };
 371 
 372   static const char* _features_names[];
 373 
 374 enum Extended_Family {
 375     // AMD
 376     CPU_FAMILY_AMD_11H       = 0x11,
 377     // ZX
 378     CPU_FAMILY_ZX_CORE_F6    = 6,
 379     CPU_FAMILY_ZX_CORE_F7    = 7,
 380     // Intel
 381     CPU_FAMILY_INTEL_CORE    = 6,
 382     CPU_MODEL_NEHALEM        = 0x1e,
 383     CPU_MODEL_NEHALEM_EP     = 0x1a,
 384     CPU_MODEL_NEHALEM_EX     = 0x2e,
 385     CPU_MODEL_WESTMERE       = 0x25,
 386     CPU_MODEL_WESTMERE_EP    = 0x2c,
 387     CPU_MODEL_WESTMERE_EX    = 0x2f,
 388     CPU_MODEL_SANDYBRIDGE    = 0x2a,
 389     CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
 390     CPU_MODEL_IVYBRIDGE_EP   = 0x3a,
 391     CPU_MODEL_HASWELL_E3     = 0x3c,
 392     CPU_MODEL_HASWELL_E7     = 0x3f,
 393     CPU_MODEL_BROADWELL      = 0x3d,
 394     CPU_MODEL_SKYLAKE        = 0x55
 395   };
 396 
 397   // cpuid information block.  All info derived from executing cpuid with
 398   // various function numbers is stored here.  Intel and AMD info is
 399   // merged in this block: accessor methods disentangle it.
 400   //
 401   // The info block is laid out in subblocks of 4 dwords corresponding to
 402   // eax, ebx, ecx and edx, whether or not they contain anything useful.
 403   struct CpuidInfo {
 404     // cpuid function 0
 405     uint32_t std_max_function;
 406     uint32_t std_vendor_name_0;
 407     uint32_t std_vendor_name_1;
 408     uint32_t std_vendor_name_2;
 409 
 410     // cpuid function 1
 411     StdCpuid1Eax std_cpuid1_eax;
 412     StdCpuid1Ebx std_cpuid1_ebx;
 413     StdCpuid1Ecx std_cpuid1_ecx;
 414     StdCpuid1Edx std_cpuid1_edx;
 415 
 416     // cpuid function 4 (deterministic cache parameters)
 417     DcpCpuid4Eax dcp_cpuid4_eax;
 418     DcpCpuid4Ebx dcp_cpuid4_ebx;
 419     uint32_t     dcp_cpuid4_ecx; // unused currently
 420     uint32_t     dcp_cpuid4_edx; // unused currently
 421 
 422     // cpuid function 7 (structured extended features)
 423     SefCpuid7Eax sef_cpuid7_eax;
 424     SefCpuid7Ebx sef_cpuid7_ebx;
 425     SefCpuid7Ecx sef_cpuid7_ecx;
 426     SefCpuid7Edx sef_cpuid7_edx;
 427 
 428     // cpuid function 0xB (processor topology)
 429     // ecx = 0
 430     uint32_t     tpl_cpuidB0_eax;
 431     TplCpuidBEbx tpl_cpuidB0_ebx;
 432     uint32_t     tpl_cpuidB0_ecx; // unused currently
 433     uint32_t     tpl_cpuidB0_edx; // unused currently
 434 
 435     // ecx = 1
 436     uint32_t     tpl_cpuidB1_eax;
 437     TplCpuidBEbx tpl_cpuidB1_ebx;
 438     uint32_t     tpl_cpuidB1_ecx; // unused currently
 439     uint32_t     tpl_cpuidB1_edx; // unused currently
 440 
 441     // ecx = 2
 442     uint32_t     tpl_cpuidB2_eax;
 443     TplCpuidBEbx tpl_cpuidB2_ebx;
 444     uint32_t     tpl_cpuidB2_ecx; // unused currently
 445     uint32_t     tpl_cpuidB2_edx; // unused currently
 446 
 447     // cpuid function 0x80000000 // example, unused
 448     uint32_t ext_max_function;
 449     uint32_t ext_vendor_name_0;
 450     uint32_t ext_vendor_name_1;
 451     uint32_t ext_vendor_name_2;
 452 
 453     // cpuid function 0x80000001
 454     uint32_t     ext_cpuid1_eax; // reserved
 455     uint32_t     ext_cpuid1_ebx; // reserved
 456     ExtCpuid1Ecx ext_cpuid1_ecx;
 457     ExtCpuid1Edx ext_cpuid1_edx;
 458 
 459     // cpuid functions 0x80000002 thru 0x80000004: example, unused
 460     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
 461     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
 462     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
 463 
 464     // cpuid function 0x80000005 // AMD L1, Intel reserved
 465     uint32_t     ext_cpuid5_eax; // unused currently
 466     uint32_t     ext_cpuid5_ebx; // reserved
 467     ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
 468     ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
 469 
 470     // cpuid function 0x80000007
 471     uint32_t     ext_cpuid7_eax; // reserved
 472     uint32_t     ext_cpuid7_ebx; // reserved
 473     uint32_t     ext_cpuid7_ecx; // reserved
 474     ExtCpuid7Edx ext_cpuid7_edx; // tscinv
 475 
 476     // cpuid function 0x80000008
 477     uint32_t     ext_cpuid8_eax; // unused currently
 478     uint32_t     ext_cpuid8_ebx; // reserved
 479     ExtCpuid8Ecx ext_cpuid8_ecx;
 480     uint32_t     ext_cpuid8_edx; // reserved
 481 
 482     // cpuid function 0x8000001E // AMD 17h
 483     uint32_t      ext_cpuid1E_eax;
 484     ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
 485     uint32_t      ext_cpuid1E_ecx;
 486     uint32_t      ext_cpuid1E_edx; // unused currently
 487 
 488     // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
 489     XemXcr0Eax   xem_xcr0_eax;
 490     uint32_t     xem_xcr0_edx; // reserved
 491 
 492     // Space to save ymm registers after signal handle
 493     int          ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
 494 
 495     // Space to save zmm registers after signal handle
 496     int          zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
 497   };
 498 
 499   // The actual cpuid info block
 500   static CpuidInfo _cpuid_info;
 501 
 502   // Extractors and predicates
 503   static uint32_t extended_cpu_family() {
 504     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
 505     result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
 506     return result;
 507   }
 508 
 509   static uint32_t extended_cpu_model() {
 510     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
 511     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 512     return result;
 513   }
 514 
 515   static uint32_t cpu_stepping() {
 516     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 517     return result;
 518   }
 519 
 520   static uint logical_processor_count() {
 521     uint result = threads_per_core();
 522     return result;
 523   }
 524 
 525   static bool compute_has_intel_jcc_erratum();
 526 
 527   static uint64_t feature_flags() {
 528     uint64_t result = 0;
 529     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 530       result |= CPU_CX8;
 531     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 532       result |= CPU_CMOV;
 533     if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0)
 534       result |= CPU_FLUSH;
 535 #ifdef _LP64
 536     // clflush should always be available on x86_64
 537     // if not we are in real trouble because we rely on it
 538     // to flush the code cache.
 539     assert ((result & CPU_FLUSH) != 0, "clflush should be available");
 540 #endif
 541     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
 542         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 543       result |= CPU_FXSR;
 544     // HT flag is set for multi-core processors also.
 545     if (threads_per_core() > 1)
 546       result |= CPU_HT;
 547     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
 548         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 549       result |= CPU_MMX;
 550     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 551       result |= CPU_SSE;
 552     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 553       result |= CPU_SSE2;
 554     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 555       result |= CPU_SSE3;
 556     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 557       result |= CPU_SSSE3;
 558     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 559       result |= CPU_SSE4_1;
 560     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 561       result |= CPU_SSE4_2;
 562     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 563       result |= CPU_POPCNT;
 564     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 565         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 566         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 567         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
 568       result |= CPU_AVX;
 569       result |= CPU_VZEROUPPER;
 570       if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
 571         result |= CPU_AVX2;
 572       if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
 573           _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
 574           _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
 575           _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
 576         result |= CPU_AVX512F;
 577         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
 578           result |= CPU_AVX512CD;
 579         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 580           result |= CPU_AVX512DQ;
 581         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 582           result |= CPU_AVX512PF;
 583         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 584           result |= CPU_AVX512ER;
 585         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 586           result |= CPU_AVX512BW;
 587         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 588           result |= CPU_AVX512VL;
 589         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
 590           result |= CPU_AVX512_VPOPCNTDQ;
 591         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0)
 592           result |= CPU_AVX512_VPCLMULQDQ;
 593         if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
 594           result |= CPU_AVX512_VAES;
 595         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 596           result |= CPU_AVX512_VNNI;
 597         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
 598           result |= CPU_AVX512_VBMI;
 599         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
 600           result |= CPU_AVX512_VBMI2;
 601       }
 602     }
 603     if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
 604       result |= CPU_HV;
 605     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 606       result |= CPU_BMI1;
 607     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 608       result |= CPU_TSC;
 609     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 610       result |= CPU_TSCINV_BIT;
 611     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 612       result |= CPU_AES;
 613     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 614       result |= CPU_ERMS;
 615     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 616       result |= CPU_CLMUL;
 617     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 618       result |= CPU_RTM;
 619     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 620        result |= CPU_ADX;
 621     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 622       result |= CPU_BMI2;
 623     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 624       result |= CPU_SHA;
 625     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 626       result |= CPU_FMA;
 627     if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
 628       result |= CPU_FLUSHOPT;
 629 
 630     // AMD|Hygon features.
 631     if (is_amd_family()) {
 632       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 633           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 634         result |= CPU_3DNOW_PREFETCH;
 635       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 636         result |= CPU_LZCNT;
 637       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 638         result |= CPU_SSE4A;
 639     }
 640 
 641     // Intel features.
 642     if (is_intel()) {
 643       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 644         result |= CPU_LZCNT;
 645       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 646       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 647         result |= CPU_3DNOW_PREFETCH;
 648       }
 649       if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
 650         result |= CPU_CLWB;
 651       }
 652       if (_cpuid_info.sef_cpuid7_edx.bits.serialize != 0)
 653         result |= CPU_SERIALIZE;
 654     }
 655 
 656     // ZX features.
 657     if (is_zx()) {
 658       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 659         result |= CPU_LZCNT;
 660       // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 661       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 662         result |= CPU_3DNOW_PREFETCH;
 663       }
 664     }
 665 
 666     // Composite features.
 667     if (supports_tscinv_bit() &&
 668         ((is_amd_family() && !is_amd_Barcelona()) ||
 669          is_intel_tsc_synched_at_init())) {
 670       result |= CPU_TSCINV;
 671     }
 672 
 673     return result;
 674   }
 675 
 676   static bool os_supports_avx_vectors() {
 677     bool retVal = false;
 678     int nreg = 2 LP64_ONLY(+2);
 679     if (supports_evex()) {
 680       // Verify that OS save/restore all bits of EVEX registers
 681       // during signal processing.
 682       retVal = true;
 683       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 684         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 685           retVal = false;
 686           break;
 687         }
 688       }
 689     } else if (supports_avx()) {
 690       // Verify that OS save/restore all bits of AVX registers
 691       // during signal processing.
 692       retVal = true;
 693       for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
 694         if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
 695           retVal = false;
 696           break;
 697         }
 698       }
 699       // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
 700       if (retVal == false) {
 701         // Verify that OS save/restore all bits of EVEX registers
 702         // during signal processing.
 703         retVal = true;
 704         for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 705           if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 706             retVal = false;
 707             break;
 708           }
 709         }
 710       }
 711     }
 712     return retVal;
 713   }
 714 
 715   static void get_processor_features();
 716 
 717 public:
 718   // Offsets for cpuid asm stub
 719   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
 720   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
 721   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
 722   static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
 723   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
 724   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
 725   static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
 726   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
 727   static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
 728   static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
 729   static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
 730   static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
 731   static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
 732   static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
 733   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 734 
 735   // The value used to check ymm register after signal handle
 736   static int ymm_test_value()    { return 0xCAFEBABE; }
 737 
 738   static void get_cpu_info_wrapper();
 739   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 740   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 741   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 742   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 743 
 744   static void clean_cpuFeatures()   { _features = 0; }
 745   static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
 746   static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
 747 
 748 
 749   // Initialization
 750   static void initialize();
 751 
 752   // Override Abstract_VM_Version implementation
 753   static void print_platform_virtualization_info(outputStream*);
 754 
 755   // Asserts
 756   static void assert_is_initialized() {
 757     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 758   }
 759 
 760   //
 761   // Processor family:
 762   //       3   -  386
 763   //       4   -  486
 764   //       5   -  Pentium
 765   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 766   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 767   //    family 6 model:   9,        13,       14,        15
 768   //    0x0f   -  Pentium 4, Opteron
 769   //
 770   // Note: The cpu family should be used to select between
 771   //       instruction sequences which are valid on all Intel
 772   //       processors.  Use the feature test functions below to
 773   //       determine whether a particular instruction is supported.
 774   //
 775   static int  cpu_family()        { return _cpu;}
 776   static bool is_P6()             { return cpu_family() >= 6; }
 777   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
 778   static bool is_hygon()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
 779   static bool is_amd_family()     { return is_amd() || is_hygon(); }
 780   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 781   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
 782   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
 783   static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
 784 
 785   static bool supports_processor_topology() {
 786     return (_cpuid_info.std_max_function >= 0xB) &&
 787            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 788            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 789            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 790   }
 791 
 792   static uint cores_per_cpu()  {
 793     uint result = 1;
 794     if (is_intel()) {
 795       bool supports_topology = supports_processor_topology();
 796       if (supports_topology) {
 797         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 798                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 799       }
 800       if (!supports_topology || result == 0) {
 801         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 802       }
 803     } else if (is_amd_family()) {
 804       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 805     } else if (is_zx()) {
 806       bool supports_topology = supports_processor_topology();
 807       if (supports_topology) {
 808         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 809                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 810       }
 811       if (!supports_topology || result == 0) {
 812         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 813       }
 814     }
 815     return result;
 816   }
 817 
 818   static uint threads_per_core()  {
 819     uint result = 1;
 820     if (is_intel() && supports_processor_topology()) {
 821       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 822     } else if (is_zx() && supports_processor_topology()) {
 823       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 824     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 825       if (cpu_family() >= 0x17) {
 826         result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
 827       } else {
 828         result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 829                  cores_per_cpu();
 830       }
 831     }
 832     return (result == 0 ? 1 : result);
 833   }
 834 
 835   static intx L1_line_size()  {
 836     intx result = 0;
 837     if (is_intel()) {
 838       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 839     } else if (is_amd_family()) {
 840       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 841     } else if (is_zx()) {
 842       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 843     }
 844     if (result < 32) // not defined ?
 845       result = 32;   // 32 bytes by default on x86 and other x64
 846     return result;
 847   }
 848 
 849   static intx prefetch_data_size()  {
 850     return L1_line_size();
 851   }
 852 
 853   //
 854   // Feature identification
 855   //
 856   static bool supports_cpuid()        { return _features  != 0; }
 857   static bool supports_cmpxchg8()     { return (_features & CPU_CX8) != 0; }
 858   static bool supports_cmov()         { return (_features & CPU_CMOV) != 0; }
 859   static bool supports_fxsr()         { return (_features & CPU_FXSR) != 0; }
 860   static bool supports_ht()           { return (_features & CPU_HT) != 0; }
 861   static bool supports_mmx()          { return (_features & CPU_MMX) != 0; }
 862   static bool supports_sse()          { return (_features & CPU_SSE) != 0; }
 863   static bool supports_sse2()         { return (_features & CPU_SSE2) != 0; }
 864   static bool supports_sse3()         { return (_features & CPU_SSE3) != 0; }
 865   static bool supports_ssse3()        { return (_features & CPU_SSSE3)!= 0; }
 866   static bool supports_sse4_1()       { return (_features & CPU_SSE4_1) != 0; }
 867   static bool supports_sse4_2()       { return (_features & CPU_SSE4_2) != 0; }
 868   static bool supports_popcnt()       { return (_features & CPU_POPCNT) != 0; }
 869   static bool supports_avx()          { return (_features & CPU_AVX) != 0; }
 870   static bool supports_avx2()         { return (_features & CPU_AVX2) != 0; }
 871   static bool supports_tsc()          { return (_features & CPU_TSC) != 0; }
 872   static bool supports_aes()          { return (_features & CPU_AES) != 0; }
 873   static bool supports_erms()         { return (_features & CPU_ERMS) != 0; }
 874   static bool supports_clmul()        { return (_features & CPU_CLMUL) != 0; }
 875   static bool supports_rtm()          { return (_features & CPU_RTM) != 0; }
 876   static bool supports_bmi1()         { return (_features & CPU_BMI1) != 0; }
 877   static bool supports_bmi2()         { return (_features & CPU_BMI2) != 0; }
 878   static bool supports_adx()          { return (_features & CPU_ADX) != 0; }
 879   static bool supports_evex()         { return (_features & CPU_AVX512F) != 0; }
 880   static bool supports_avx512dq()     { return (_features & CPU_AVX512DQ) != 0; }
 881   static bool supports_avx512pf()     { return (_features & CPU_AVX512PF) != 0; }
 882   static bool supports_avx512er()     { return (_features & CPU_AVX512ER) != 0; }
 883   static bool supports_avx512cd()     { return (_features & CPU_AVX512CD) != 0; }
 884   static bool supports_avx512bw()     { return (_features & CPU_AVX512BW) != 0; }
 885   static bool supports_avx512vl()     { return (_features & CPU_AVX512VL) != 0; }
 886   static bool supports_avx512vlbw()   { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
 887   static bool supports_avx512vldq()   { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
 888   static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
 889                                                 supports_avx512bw() && supports_avx512dq()); }
 890   static bool supports_avx512novl()   { return (supports_evex() && !supports_avx512vl()); }
 891   static bool supports_avx512nobw()   { return (supports_evex() && !supports_avx512bw()); }
 892   static bool supports_avx256only()   { return (supports_avx2() && !supports_evex()); }
 893   static bool supports_avxonly()      { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
 894   static bool supports_sha()          { return (_features & CPU_SHA) != 0; }
 895   static bool supports_fma()          { return (_features & CPU_FMA) != 0 && supports_avx(); }
 896   static bool supports_vzeroupper()   { return (_features & CPU_VZEROUPPER) != 0; }
 897   static bool supports_avx512_vpopcntdq()  { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
 898   static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
 899   static bool supports_avx512_vaes()  { return (_features & CPU_AVX512_VAES) != 0; }
 900   static bool supports_avx512_vnni()  { return (_features & CPU_AVX512_VNNI) != 0; }
 901   static bool supports_avx512_vbmi()  { return (_features & CPU_AVX512_VBMI) != 0; }
 902   static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
 903   static bool supports_hv()           { return (_features & CPU_HV) != 0; }
 904   static bool supports_serialize()    { return (_features & CPU_SERIALIZE) != 0; }
 905 
 906   // Intel features
 907   static bool is_intel_family_core() { return is_intel() &&
 908                                        extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
 909 
 910   static bool is_intel_skylake() { return is_intel_family_core() &&
 911                                           extended_cpu_model() == CPU_MODEL_SKYLAKE; }
 912 
 913   static bool is_intel_tsc_synched_at_init()  {
 914     if (is_intel_family_core()) {
 915       uint32_t ext_model = extended_cpu_model();
 916       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 917           ext_model == CPU_MODEL_WESTMERE_EP    ||
 918           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 919           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 920         // <= 2-socket invariant tsc support. EX versions are usually used
 921         // in > 2-socket systems and likely don't synchronize tscs at
 922         // initialization.
 923         // Code that uses tsc values must be prepared for them to arbitrarily
 924         // jump forward or backward.
 925         return true;
 926       }
 927     }
 928     return false;
 929   }
 930 
 931   // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
 932   // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
 933   // mitigation causes regressions when jumps or fused conditional branches cross or end at
 934   // 32 byte boundaries.
 935   static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
 936 
 937   // AMD features
 938   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
 939   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
 940   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 941 
 942   static bool is_amd_Barcelona()  { return is_amd() &&
 943                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 944 
 945   // Intel and AMD newer cores support fast timestamps well
 946   static bool supports_tscinv_bit() {
 947     return (_features & CPU_TSCINV_BIT) != 0;
 948   }
 949   static bool supports_tscinv() {
 950     return (_features & CPU_TSCINV) != 0;
 951   }
 952 
 953   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 954   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 955                                            supports_sse3() && _model != 0x1C; }
 956 
 957   static bool supports_compare_and_exchange() { return true; }
 958 
 959   static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
 960     // Hardware prefetching (distance/size in bytes):
 961     // Pentium 3 -  64 /  32
 962     // Pentium 4 - 256 / 128
 963     // Athlon    -  64 /  32 ????
 964     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 965     // Core      - 128 /  64
 966     //
 967     // Software prefetching (distance in bytes / instruction with best score):
 968     // Pentium 3 - 128 / prefetchnta
 969     // Pentium 4 - 512 / prefetchnta
 970     // Athlon    - 128 / prefetchnta
 971     // Opteron   - 256 / prefetchnta
 972     // Core      - 256 / prefetchnta
 973     // It will be used only when AllocatePrefetchStyle > 0
 974 
 975     if (is_amd_family()) { // AMD | Hygon
 976       if (supports_sse2()) {
 977         return 256; // Opteron
 978       } else {
 979         return 128; // Athlon
 980       }
 981     } else { // Intel
 982       if (supports_sse3() && cpu_family() == 6) {
 983         if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
 984           return 192;
 985         } else if (use_watermark_prefetch) { // watermark prefetching on Core
 986 #ifdef _LP64
 987           return 384;
 988 #else
 989           return 320;
 990 #endif
 991         }
 992       }
 993       if (supports_sse2()) {
 994         if (cpu_family() == 6) {
 995           return 256; // Pentium M, Core, Core2
 996         } else {
 997           return 512; // Pentium 4
 998         }
 999       } else {
1000         return 128; // Pentium 3 (and all other old CPUs)
1001       }
1002     }
1003   }
1004 
1005   // SSE2 and later processors implement a 'pause' instruction
1006   // that can be used for efficient implementation of
1007   // the intrinsic for java.lang.Thread.onSpinWait()
1008   static bool supports_on_spin_wait() { return supports_sse2(); }
1009 
1010   // x86_64 supports fast class initialization checks for static methods.
1011   static bool supports_fast_class_init_checks() {
1012     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
1013   }
1014 
1015   constexpr static bool supports_stack_watermark_barrier() {
1016     return true;
1017   }
1018 
1019   // there are several insns to force cache line sync to memory which
1020   // we can use to ensure mapped non-volatile memory is up to date with
1021   // pending in-cache changes.
1022   //
1023   // 64 bit cpus always support clflush which writes back and evicts
1024   // on 32 bit cpus support is recorded via a feature flag
1025   //
1026   // clflushopt is optional and acts like clflush except it does
1027   // not synchronize with other memory ops. it needs a preceding
1028   // and trailing StoreStore fence
1029   //
1030   // clwb is an optional intel-specific instruction which
1031   // writes back without evicting the line. it also does not
1032   // synchronize with other memory ops. so, it needs preceding
1033   // and trailing StoreStore fences.
1034 
1035 #ifdef _LP64
1036 
1037   static bool supports_clflush(); // Can't inline due to header file conflict
1038 #else
1039   static bool supports_clflush() { return  ((_features & CPU_FLUSH) != 0); }
1040 #endif // _LP64
1041   // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
1042   static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
1043   static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
1044 
1045 #ifdef __APPLE__
1046   // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
1047   static bool is_cpu_emulated();
1048 #endif
1049 
1050   // support functions for virtualization detection
1051  private:
1052   static void check_virtualizations();
1053 };
1054 
1055 #endif // CPU_X86_VM_VERSION_X86_HPP