1 /*
2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_X86_VM_VERSION_X86_HPP
26 #define CPU_X86_VM_VERSION_X86_HPP
27
28 #include "runtime/abstract_vm_version.hpp"
29 #include "utilities/debug.hpp"
30 #include "utilities/macros.hpp"
31 #include "utilities/sizes.hpp"
32
33 class VM_Version : public Abstract_VM_Version {
34 friend class VMStructs;
35 friend class JVMCIVMStructs;
36
37 public:
38 // cpuid result register layouts. These are all unions of a uint32_t
39 // (in case anyone wants access to the register as a whole) and a bitfield.
40
41 union StdCpuid1Eax {
42 uint32_t value;
43 struct {
44 uint32_t stepping : 4,
45 model : 4,
46 family : 4,
47 proc_type : 2,
48 : 2,
49 ext_model : 4,
50 ext_family : 8,
51 : 4;
52 } bits;
53 };
54
55 union StdCpuid1Ebx { // example, unused
56 uint32_t value;
57 struct {
58 uint32_t brand_id : 8,
59 clflush_size : 8,
60 threads_per_cpu : 8,
61 apic_id : 8;
62 } bits;
63 };
64
65 union StdCpuid1Ecx {
66 uint32_t value;
67 struct {
68 uint32_t sse3 : 1,
69 clmul : 1,
70 : 1,
71 monitor : 1,
72 : 1,
73 vmx : 1,
74 : 1,
75 est : 1,
76 : 1,
77 ssse3 : 1,
78 cid : 1,
79 : 1,
80 fma : 1,
81 cmpxchg16: 1,
82 : 4,
83 dca : 1,
84 sse4_1 : 1,
85 sse4_2 : 1,
86 : 2,
87 popcnt : 1,
88 : 1,
89 aes : 1,
90 : 1,
91 osxsave : 1,
92 avx : 1,
93 f16c : 1,
94 : 1,
95 hv : 1;
96 } bits;
97 };
98
99 union StdCpuid1Edx {
100 uint32_t value;
101 struct {
102 uint32_t : 4,
103 tsc : 1,
104 : 3,
105 cmpxchg8 : 1,
106 : 6,
107 cmov : 1,
108 : 3,
109 clflush : 1,
110 : 3,
111 mmx : 1,
112 fxsr : 1,
113 sse : 1,
114 sse2 : 1,
115 : 1,
116 ht : 1,
117 : 3;
118 } bits;
119 };
120
121 union DcpCpuid4Eax {
122 uint32_t value;
123 struct {
124 uint32_t cache_type : 5,
125 : 21,
126 cores_per_cpu : 6;
127 } bits;
128 };
129
130 union DcpCpuid4Ebx {
131 uint32_t value;
132 struct {
133 uint32_t L1_line_size : 12,
134 partitions : 10,
135 associativity : 10;
136 } bits;
137 };
138
139 union TplCpuidBEbx {
140 uint32_t value;
141 struct {
142 uint32_t logical_cpus : 16,
143 : 16;
144 } bits;
145 };
146
147 union ExtCpuid1Ecx {
148 uint32_t value;
149 struct {
150 uint32_t LahfSahf : 1,
151 CmpLegacy : 1,
152 : 3,
153 lzcnt : 1,
154 sse4a : 1,
155 misalignsse : 1,
156 prefetchw : 1,
157 : 23;
158 } bits;
159 };
160
161 union ExtCpuid1Edx {
162 uint32_t value;
163 struct {
164 uint32_t : 22,
165 mmx_amd : 1,
166 mmx : 1,
167 fxsr : 1,
168 fxsr_opt : 1,
169 pdpe1gb : 1,
170 rdtscp : 1,
171 : 1,
172 long_mode : 1,
173 tdnow2 : 1,
174 tdnow : 1;
175 } bits;
176 };
177
178 union ExtCpuid5Ex {
179 uint32_t value;
180 struct {
181 uint32_t L1_line_size : 8,
182 L1_tag_lines : 8,
183 L1_assoc : 8,
184 L1_size : 8;
185 } bits;
186 };
187
188 union ExtCpuid7Edx {
189 uint32_t value;
190 struct {
191 uint32_t : 8,
192 tsc_invariance : 1,
193 : 23;
194 } bits;
195 };
196
197 union ExtCpuid8Ecx {
198 uint32_t value;
199 struct {
200 uint32_t cores_per_cpu : 8,
201 : 24;
202 } bits;
203 };
204
205 union SefCpuid7Eax {
206 uint32_t value;
207 };
208
209 union SefCpuid7Ebx {
210 uint32_t value;
211 struct {
212 uint32_t fsgsbase : 1,
213 : 2,
214 bmi1 : 1,
215 : 1,
216 avx2 : 1,
217 : 2,
218 bmi2 : 1,
219 erms : 1,
220 : 1,
221 rtm : 1,
222 : 4,
223 avx512f : 1,
224 avx512dq : 1,
225 : 1,
226 adx : 1,
227 : 1,
228 avx512ifma : 1,
229 : 1,
230 clflushopt : 1,
231 clwb : 1,
232 : 1,
233 avx512pf : 1,
234 avx512er : 1,
235 avx512cd : 1,
236 sha : 1,
237 avx512bw : 1,
238 avx512vl : 1;
239 } bits;
240 };
241
242 union SefCpuid7Ecx {
243 uint32_t value;
244 struct {
245 uint32_t prefetchwt1 : 1,
246 avx512_vbmi : 1,
247 umip : 1,
248 pku : 1,
249 ospke : 1,
250 : 1,
251 avx512_vbmi2 : 1,
252 cet_ss : 1,
253 gfni : 1,
254 vaes : 1,
255 avx512_vpclmulqdq : 1,
256 avx512_vnni : 1,
257 avx512_bitalg : 1,
258 : 1,
259 avx512_vpopcntdq : 1,
260 : 1,
261 : 1,
262 mawau : 5,
263 rdpid : 1,
264 : 9;
265 } bits;
266 };
267
268 union SefCpuid7Edx {
269 uint32_t value;
270 struct {
271 uint32_t : 2,
272 avx512_4vnniw : 1,
273 avx512_4fmaps : 1,
274 fast_short_rep_mov : 1,
275 : 9,
276 serialize : 1,
277 : 5,
278 cet_ibt : 1,
279 : 11;
280 } bits;
281 };
282
283 union SefCpuid7SubLeaf1Eax {
284 uint32_t value;
285 struct {
286 uint32_t : 23,
287 avx_ifma : 1,
288 : 8;
289 } bits;
290 };
291
292 union SefCpuid7SubLeaf1Edx {
293 uint32_t value;
294 struct {
295 uint32_t : 21,
296 apx_f : 1,
297 : 10;
298 } bits;
299 };
300
301 union ExtCpuid1EEbx {
302 uint32_t value;
303 struct {
304 uint32_t : 8,
305 threads_per_core : 8,
306 : 16;
307 } bits;
308 };
309
310 union XemXcr0Eax {
311 uint32_t value;
312 struct {
313 uint32_t x87 : 1,
314 sse : 1,
315 ymm : 1,
316 bndregs : 1,
317 bndcsr : 1,
318 opmask : 1,
319 zmm512 : 1,
320 zmm32 : 1,
321 : 11,
322 apx_f : 1,
323 : 12;
324 } bits;
325 };
326
327 protected:
328 static int _cpu;
329 static int _model;
330 static int _stepping;
331
332 static bool _has_intel_jcc_erratum;
333
334 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV
335 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
336 static address _cpuinfo_segv_addr_apx; // address of instruction which causes APX specific SEGV
337 static address _cpuinfo_cont_addr_apx; // address of instruction after the one which causes APX specific SEGV
338
339 /*
340 * Update following files when declaring new flags:
341 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java
342 * src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.amd64/src/jdk/vm/ci/amd64/AMD64.java
343 */
344 enum Feature_Flag : uint64_t {
345 #define CPU_FEATURE_FLAGS(decl) \
346 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \
347 decl(CMOV, "cmov", 1) \
348 decl(FXSR, "fxsr", 2) \
349 decl(HT, "ht", 3) \
350 \
351 decl(MMX, "mmx", 4) \
352 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \
353 /* may not necessarily support other 3dnow instructions */ \
354 decl(SSE, "sse", 6) \
355 decl(SSE2, "sse2", 7) \
356 \
357 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
358 decl(SSSE3, "ssse3", 9 ) \
359 decl(SSE4A, "sse4a", 10) \
360 decl(SSE4_1, "sse4.1", 11) \
361 \
362 decl(SSE4_2, "sse4.2", 12) \
363 decl(POPCNT, "popcnt", 13) \
364 decl(LZCNT, "lzcnt", 14) \
365 decl(TSC, "tsc", 15) \
366 \
367 decl(TSCINV_BIT, "tscinvbit", 16) \
368 decl(TSCINV, "tscinv", 17) \
369 decl(AVX, "avx", 18) \
370 decl(AVX2, "avx2", 19) \
371 \
372 decl(AES, "aes", 20) \
373 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \
374 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \
375 decl(BMI1, "bmi1", 23) \
376 \
377 decl(BMI2, "bmi2", 24) \
378 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \
379 decl(ADX, "adx", 26) \
380 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \
381 \
382 decl(AVX512DQ, "avx512dq", 28) \
383 decl(AVX512PF, "avx512pf", 29) \
384 decl(AVX512ER, "avx512er", 30) \
385 decl(AVX512CD, "avx512cd", 31) \
386 \
387 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \
388 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \
389 decl(SHA, "sha", 34) /* SHA instructions */ \
390 decl(FMA, "fma", 35) /* FMA instructions */ \
391 \
392 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \
393 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \
394 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
395 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \
396 \
397 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \
398 decl(FLUSH, "clflush", 41) /* flush instruction */ \
399 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \
400 decl(CLWB, "clwb", 43) /* clwb instruction */ \
401 \
402 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \
403 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \
404 decl(HV, "hv", 46) /* Hypervisor instructions */ \
405 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \
406 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \
407 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \
408 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \
409 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \
410 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\
411 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \
412 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \
413 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \
414 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \
415 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \
416 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \
417 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ \
418 decl(APX_F, "apx_f", 60) /* Intel Advanced Performance Extensions*/
419
420 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
421 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
422 #undef DECLARE_CPU_FEATURE_FLAG
423 };
424
425 static const char* _features_names[];
426
427 enum Extended_Family {
428 // AMD
429 CPU_FAMILY_AMD_11H = 0x11,
430 // ZX
431 CPU_FAMILY_ZX_CORE_F6 = 6,
432 CPU_FAMILY_ZX_CORE_F7 = 7,
433 // Intel
434 CPU_FAMILY_INTEL_CORE = 6,
435 CPU_MODEL_NEHALEM = 0x1e,
436 CPU_MODEL_NEHALEM_EP = 0x1a,
437 CPU_MODEL_NEHALEM_EX = 0x2e,
438 CPU_MODEL_WESTMERE = 0x25,
439 CPU_MODEL_WESTMERE_EP = 0x2c,
440 CPU_MODEL_WESTMERE_EX = 0x2f,
441 CPU_MODEL_SANDYBRIDGE = 0x2a,
442 CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
443 CPU_MODEL_IVYBRIDGE_EP = 0x3a,
444 CPU_MODEL_HASWELL_E3 = 0x3c,
445 CPU_MODEL_HASWELL_E7 = 0x3f,
446 CPU_MODEL_BROADWELL = 0x3d,
447 CPU_MODEL_SKYLAKE = 0x55
448 };
449
450 // cpuid information block. All info derived from executing cpuid with
451 // various function numbers is stored here. Intel and AMD info is
452 // merged in this block: accessor methods disentangle it.
453 //
454 // The info block is laid out in subblocks of 4 dwords corresponding to
455 // eax, ebx, ecx and edx, whether or not they contain anything useful.
456 class CpuidInfo {
457 public:
458 // cpuid function 0
459 uint32_t std_max_function;
460 uint32_t std_vendor_name_0;
461 uint32_t std_vendor_name_1;
462 uint32_t std_vendor_name_2;
463
464 // cpuid function 1
465 StdCpuid1Eax std_cpuid1_eax;
466 StdCpuid1Ebx std_cpuid1_ebx;
467 StdCpuid1Ecx std_cpuid1_ecx;
468 StdCpuid1Edx std_cpuid1_edx;
469
470 // cpuid function 4 (deterministic cache parameters)
471 DcpCpuid4Eax dcp_cpuid4_eax;
472 DcpCpuid4Ebx dcp_cpuid4_ebx;
473 uint32_t dcp_cpuid4_ecx; // unused currently
474 uint32_t dcp_cpuid4_edx; // unused currently
475
476 // cpuid function 7 (structured extended features enumeration leaf)
477 // eax = 7, ecx = 0
478 SefCpuid7Eax sef_cpuid7_eax;
479 SefCpuid7Ebx sef_cpuid7_ebx;
480 SefCpuid7Ecx sef_cpuid7_ecx;
481 SefCpuid7Edx sef_cpuid7_edx;
482
483 // cpuid function 7 (structured extended features enumeration sub-leaf 1)
484 // eax = 7, ecx = 1
485 SefCpuid7SubLeaf1Eax sefsl1_cpuid7_eax;
486 SefCpuid7SubLeaf1Edx sefsl1_cpuid7_edx;
487
488 // cpuid function 0xB (processor topology)
489 // ecx = 0
490 uint32_t tpl_cpuidB0_eax;
491 TplCpuidBEbx tpl_cpuidB0_ebx;
492 uint32_t tpl_cpuidB0_ecx; // unused currently
493 uint32_t tpl_cpuidB0_edx; // unused currently
494
495 // ecx = 1
496 uint32_t tpl_cpuidB1_eax;
497 TplCpuidBEbx tpl_cpuidB1_ebx;
498 uint32_t tpl_cpuidB1_ecx; // unused currently
499 uint32_t tpl_cpuidB1_edx; // unused currently
500
501 // ecx = 2
502 uint32_t tpl_cpuidB2_eax;
503 TplCpuidBEbx tpl_cpuidB2_ebx;
504 uint32_t tpl_cpuidB2_ecx; // unused currently
505 uint32_t tpl_cpuidB2_edx; // unused currently
506
507 // cpuid function 0x80000000 // example, unused
508 uint32_t ext_max_function;
509 uint32_t ext_vendor_name_0;
510 uint32_t ext_vendor_name_1;
511 uint32_t ext_vendor_name_2;
512
513 // cpuid function 0x80000001
514 uint32_t ext_cpuid1_eax; // reserved
515 uint32_t ext_cpuid1_ebx; // reserved
516 ExtCpuid1Ecx ext_cpuid1_ecx;
517 ExtCpuid1Edx ext_cpuid1_edx;
518
519 // cpuid functions 0x80000002 thru 0x80000004: example, unused
520 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
521 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
522 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
523
524 // cpuid function 0x80000005 // AMD L1, Intel reserved
525 uint32_t ext_cpuid5_eax; // unused currently
526 uint32_t ext_cpuid5_ebx; // reserved
527 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD)
528 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD)
529
530 // cpuid function 0x80000007
531 uint32_t ext_cpuid7_eax; // reserved
532 uint32_t ext_cpuid7_ebx; // reserved
533 uint32_t ext_cpuid7_ecx; // reserved
534 ExtCpuid7Edx ext_cpuid7_edx; // tscinv
535
536 // cpuid function 0x80000008
537 uint32_t ext_cpuid8_eax; // unused currently
538 uint32_t ext_cpuid8_ebx; // reserved
539 ExtCpuid8Ecx ext_cpuid8_ecx;
540 uint32_t ext_cpuid8_edx; // reserved
541
542 // cpuid function 0x8000001E // AMD 17h
543 uint32_t ext_cpuid1E_eax;
544 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
545 uint32_t ext_cpuid1E_ecx;
546 uint32_t ext_cpuid1E_edx; // unused currently
547
548 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
549 XemXcr0Eax xem_xcr0_eax;
550 uint32_t xem_xcr0_edx; // reserved
551
552 // Space to save ymm registers after signal handle
553 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
554
555 // Space to save zmm registers after signal handle
556 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
557
558 // Space to save apx registers after signal handle
559 jlong apx_save[2]; // Save r16 and r31
560
561 uint64_t feature_flags() const;
562
563 // Asserts
564 void assert_is_initialized() const {
565 assert(std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
566 }
567
568 // Extractors
569 uint32_t extended_cpu_family() const {
570 uint32_t result = std_cpuid1_eax.bits.family;
571 result += std_cpuid1_eax.bits.ext_family;
572 return result;
573 }
574
575 uint32_t extended_cpu_model() const {
576 uint32_t result = std_cpuid1_eax.bits.model;
577 result |= std_cpuid1_eax.bits.ext_model << 4;
578 return result;
579 }
580
581 uint32_t cpu_stepping() const {
582 uint32_t result = std_cpuid1_eax.bits.stepping;
583 return result;
584 }
585 };
586
587 private:
588 // The actual cpuid info block
589 static CpuidInfo _cpuid_info;
590
591 // Extractors and predicates
592 static uint logical_processor_count() {
593 uint result = threads_per_core();
594 return result;
595 }
596
597 static bool compute_has_intel_jcc_erratum();
598
599 static bool os_supports_avx_vectors();
600 static bool os_supports_apx_egprs();
601 static void get_processor_features();
602
603 public:
604 // Offsets for cpuid asm stub
605 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
606 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
607 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
608 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
609 static ByteSize sefsl1_cpuid7_offset() { return byte_offset_of(CpuidInfo, sefsl1_cpuid7_eax); }
610 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
611 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
612 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
613 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
614 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
615 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
616 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
617 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
618 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
619 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
620 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
621 static ByteSize apx_save_offset() { return byte_offset_of(CpuidInfo, apx_save); }
622
623 // The value used to check ymm register after signal handle
624 static int ymm_test_value() { return 0xCAFEBABE; }
625 static jlong egpr_test_value() { return 0xCAFEBABECAFEBABELL; }
626
627 static void get_cpu_info_wrapper();
628 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
629 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
630 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
631 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; }
632
633 static void set_cpuinfo_segv_addr_apx(address pc) { _cpuinfo_segv_addr_apx = pc; }
634 static bool is_cpuinfo_segv_addr_apx(address pc) { return _cpuinfo_segv_addr_apx == pc; }
635 static void set_cpuinfo_cont_addr_apx(address pc) { _cpuinfo_cont_addr_apx = pc; }
636 static address cpuinfo_cont_addr_apx() { return _cpuinfo_cont_addr_apx; }
637
638 LP64_ONLY(static void clear_apx_test_state());
639
640 static void clean_cpuFeatures() { _features = 0; }
641 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
642 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
643 static void set_apx_cpuFeatures() { _features |= CPU_APX_F; }
644
645 // Initialization
646 static void initialize();
647
648 // Override Abstract_VM_Version implementation
649 static void print_platform_virtualization_info(outputStream*);
650
651 //
652 // Processor family:
653 // 3 - 386
654 // 4 - 486
655 // 5 - Pentium
656 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
657 // Pentium M, Core Solo, Core Duo, Core2 Duo
658 // family 6 model: 9, 13, 14, 15
659 // 0x0f - Pentium 4, Opteron
660 //
661 // Note: The cpu family should be used to select between
662 // instruction sequences which are valid on all Intel
663 // processors. Use the feature test functions below to
664 // determine whether a particular instruction is supported.
665 //
666 static void assert_is_initialized() { _cpuid_info.assert_is_initialized(); }
667 static uint32_t extended_cpu_family() { return _cpuid_info.extended_cpu_family(); }
668 static uint32_t extended_cpu_model() { return _cpuid_info.extended_cpu_model(); }
669 static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); }
670 static int cpu_family() { return _cpu;}
671 static bool is_P6() { return cpu_family() >= 6; }
672 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
673 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
674 static bool is_amd_family() { return is_amd() || is_hygon(); }
675 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
676 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS '
677 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
678 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
679
680 static bool supports_processor_topology() {
681 return (_cpuid_info.std_max_function >= 0xB) &&
682 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
683 // Some cpus have max cpuid >= 0xB but do not support processor topology.
684 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
685 }
686
687 static uint cores_per_cpu();
688 static uint threads_per_core();
689 static uint L1_line_size();
690
691 static uint prefetch_data_size() {
692 return L1_line_size();
693 }
694
695 //
696 // Feature identification which can be affected by VM settings
697 //
698 static bool supports_cpuid() { return _features != 0; }
699 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; }
700 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; }
701 static bool supports_ht() { return (_features & CPU_HT) != 0; }
702 static bool supports_mmx() { return (_features & CPU_MMX) != 0; }
703 static bool supports_sse() { return (_features & CPU_SSE) != 0; }
704 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; }
705 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; }
706 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; }
707 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; }
708 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; }
709 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; }
710 static bool supports_avx() { return (_features & CPU_AVX) != 0; }
711 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; }
712 static bool supports_tsc() { return (_features & CPU_TSC) != 0; }
713 static bool supports_rdtscp() { return (_features & CPU_RDTSCP) != 0; }
714 static bool supports_rdpid() { return (_features & CPU_RDPID) != 0; }
715 static bool supports_aes() { return (_features & CPU_AES) != 0; }
716 static bool supports_erms() { return (_features & CPU_ERMS) != 0; }
717 static bool supports_fsrm() { return (_features & CPU_FSRM) != 0; }
718 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; }
719 static bool supports_rtm() { return (_features & CPU_RTM) != 0; }
720 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; }
721 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; }
722 static bool supports_adx() { return (_features & CPU_ADX) != 0; }
723 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; }
724 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; }
725 static bool supports_avx512ifma() { return (_features & CPU_AVX512_IFMA) != 0; }
726 static bool supports_avxifma() { return (_features & CPU_AVX_IFMA) != 0; }
727 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; }
728 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; }
729 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; }
730 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; }
731 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; }
732 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
733 static bool supports_avx512bwdq() { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); }
734 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
735 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
736 supports_avx512bw() && supports_avx512dq()); }
737 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); }
738 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); }
739 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); }
740 static bool supports_apx_f() { return (_features & CPU_APX_F) != 0; }
741 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
742 static bool supports_sha() { return (_features & CPU_SHA) != 0; }
743 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); }
744 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; }
745 static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
746 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
747 static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; }
748 static bool supports_gfni() { return (_features & CPU_GFNI) != 0; }
749 static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; }
750 static bool supports_avx512_bitalg() { return (_features & CPU_AVX512_BITALG) != 0; }
751 static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; }
752 static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
753 static bool supports_hv() { return (_features & CPU_HV) != 0; }
754 static bool supports_serialize() { return (_features & CPU_SERIALIZE) != 0; }
755 static bool supports_f16c() { return (_features & CPU_F16C) != 0; }
756 static bool supports_pku() { return (_features & CPU_PKU) != 0; }
757 static bool supports_ospke() { return (_features & CPU_OSPKE) != 0; }
758 static bool supports_cet_ss() { return (_features & CPU_CET_SS) != 0; }
759 static bool supports_cet_ibt() { return (_features & CPU_CET_IBT) != 0; }
760
761 //
762 // Feature identification not affected by VM flags
763 //
764 static bool cpu_supports_evex() { return (_cpu_features & CPU_AVX512F) != 0; }
765
766 // Intel features
767 static bool is_intel_family_core() { return is_intel() &&
768 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
769
770 static bool is_intel_skylake() { return is_intel_family_core() &&
771 extended_cpu_model() == CPU_MODEL_SKYLAKE; }
772
773 #ifdef COMPILER2
774 // Determine if it's running on Cascade Lake using default options.
775 static bool is_default_intel_cascade_lake();
776 #endif
777
778 static bool is_intel_cascade_lake();
779
780 static int avx3_threshold();
781
782 static bool is_intel_tsc_synched_at_init();
783
784 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
785 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
786 // mitigation causes regressions when jumps or fused conditional branches cross or end at
787 // 32 byte boundaries.
788 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
789
790 // AMD features
791 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; }
792 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; }
793 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; }
794
795 static bool is_amd_Barcelona() { return is_amd() &&
796 extended_cpu_family() == CPU_FAMILY_AMD_11H; }
797
798 // Intel and AMD newer cores support fast timestamps well
799 static bool supports_tscinv_bit() {
800 return (_features & CPU_TSCINV_BIT) != 0;
801 }
802 static bool supports_tscinv() {
803 return (_features & CPU_TSCINV) != 0;
804 }
805
806 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
807 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 &&
808 supports_sse3() && _model != 0x1C; }
809
810 static bool supports_compare_and_exchange() { return true; }
811
812 static int allocate_prefetch_distance(bool use_watermark_prefetch);
813
814 // SSE2 and later processors implement a 'pause' instruction
815 // that can be used for efficient implementation of
816 // the intrinsic for java.lang.Thread.onSpinWait()
817 static bool supports_on_spin_wait() { return supports_sse2(); }
818
819 // x86_64 supports fast class initialization checks
820 static bool supports_fast_class_init_checks() {
821 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
822 }
823
824 // x86_64 supports secondary supers table
825 constexpr static bool supports_secondary_supers_table() {
826 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
827 }
828
829 constexpr static bool supports_stack_watermark_barrier() {
830 return true;
831 }
832
833 constexpr static bool supports_recursive_lightweight_locking() {
834 return true;
835 }
836
837 // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
838 static bool supports_float16() {
839 return supports_f16c() || supports_avx512vl();
840 }
841
842 // Check intrinsic support
843 static bool is_intrinsic_supported(vmIntrinsicID id);
844
845 // there are several insns to force cache line sync to memory which
846 // we can use to ensure mapped non-volatile memory is up to date with
847 // pending in-cache changes.
848 //
849 // 64 bit cpus always support clflush which writes back and evicts
850 // on 32 bit cpus support is recorded via a feature flag
851 //
852 // clflushopt is optional and acts like clflush except it does
853 // not synchronize with other memory ops. it needs a preceding
854 // and trailing StoreStore fence
855 //
856 // clwb is an optional intel-specific instruction which
857 // writes back without evicting the line. it also does not
858 // synchronize with other memory ops. so, it needs preceding
859 // and trailing StoreStore fences.
860
861 #ifdef _LP64
862 static bool supports_clflush(); // Can't inline due to header file conflict
863 #else
864 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); }
865 #endif // _LP64
866
867 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
868 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
869 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
870
871 // Old CPUs perform lea on AGU which causes additional latency transferring the
872 // value from/to ALU for other operations
873 static bool supports_fast_2op_lea() {
874 return (is_intel() && supports_avx()) || // Sandy Bridge and above
875 (is_amd() && supports_avx()); // Jaguar and Bulldozer and above
876 }
877
878 // Pre Icelake Intels suffer inefficiency regarding 3-operand lea, which contains
879 // all of base register, index register and displacement immediate, with 3 latency.
880 // Note that when the address contains no displacement but the base register is
881 // rbp or r13, the machine code must contain a zero displacement immediate,
882 // effectively transform a 2-operand lea into a 3-operand lea. This can be
883 // replaced by add-add or lea-add
884 static bool supports_fast_3op_lea() {
885 return supports_fast_2op_lea() &&
886 ((is_intel() && supports_clwb() && !is_intel_skylake()) || // Icelake and above
887 is_amd());
888 }
889
890 #ifdef __APPLE__
891 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
892 static bool is_cpu_emulated();
893 #endif
894
895 // support functions for virtualization detection
896 private:
897 static void check_virtualizations();
898
899 static const char* cpu_family_description(void);
900 static const char* cpu_model_description(void);
901 static const char* cpu_brand(void);
902 static const char* cpu_brand_string(void);
903
904 static int cpu_type_description(char* const buf, size_t buf_len);
905 static int cpu_detailed_description(char* const buf, size_t buf_len);
906 static int cpu_extended_brand_string(char* const buf, size_t buf_len);
907
908 static bool cpu_is_em64t(void);
909 static bool is_netburst(void);
910
911 // Returns bytes written excluding termninating null byte.
912 static size_t cpu_write_support_string(char* const buf, size_t buf_len);
913 static void resolve_cpu_information_details(void);
914 static int64_t max_qualified_cpu_freq_from_brand_string(void);
915
916 public:
917 // Offsets for cpuid asm stub brand string
918 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); }
919 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); }
920 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); }
921 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); }
922 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); }
923 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); }
924 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); }
925 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); }
926 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); }
927 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); }
928 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); }
929 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); }
930
931 static int64_t maximum_qualified_cpu_frequency(void);
932
933 static bool supports_tscinv_ext(void);
934
935 static void initialize_tsc();
936 static void initialize_cpu_information(void);
937 };
938
939 #endif // CPU_X86_VM_VERSION_X86_HPP