< prev index next >

src/hotspot/cpu/x86/vm_version_x86.hpp

Print this page
*** 162,11 ***
      struct {
        uint32_t           : 22,
                 mmx_amd   : 1,
                 mmx       : 1,
                 fxsr      : 1,
!                          : 4,
                 long_mode : 1,
                 tdnow2    : 1,
                 tdnow     : 1;
      } bits;
    };
--- 162,14 ---
      struct {
        uint32_t           : 22,
                 mmx_amd   : 1,
                 mmx       : 1,
                 fxsr      : 1,
!                fxsr_opt  : 1,
+                pdpe1gb   : 1,
+                rdtscp    : 1,
+                          : 1,
                 long_mode : 1,
                 tdnow2    : 1,
                 tdnow     : 1;
      } bits;
    };

*** 249,21 ***
           avx512_vpclmulqdq : 1,
                 avx512_vnni : 1,
               avx512_bitalg : 1,
                             : 1,
            avx512_vpopcntdq : 1,
!                            : 17;
      } bits;
    };
  
    union SefCpuid7Edx {
      uint32_t value;
      struct {
        uint32_t             : 2,
               avx512_4vnniw : 1,
               avx512_4fmaps : 1,
!                            : 10,
                   serialize : 1,
                             : 17;
      } bits;
    };
  
--- 252,26 ---
           avx512_vpclmulqdq : 1,
                 avx512_vnni : 1,
               avx512_bitalg : 1,
                             : 1,
            avx512_vpopcntdq : 1,
!                            : 1,
+                            : 1,
+                      mawau : 5,
+                      rdpid : 1,
+                            : 9;
      } bits;
    };
  
    union SefCpuid7Edx {
      uint32_t value;
      struct {
        uint32_t             : 2,
               avx512_4vnniw : 1,
               avx512_4fmaps : 1,
!         fast_short_rep_mov : 1,
+                            : 9,
                   serialize : 1,
                             : 17;
      } bits;
    };
  

*** 360,11 ***
      decl(CLWB,              "clwb",              43) /* clwb instruction */ \
                                                       \
      decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
      decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
      decl(HV,                "hv",                46) /* Hypervisor instructions */ \
!     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */
  
  #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
      CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
  #undef DECLARE_CPU_FEATURE_FLAG
    };
--- 368,15 ---
      decl(CLWB,              "clwb",              43) /* clwb instruction */ \
                                                       \
      decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
      decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
      decl(HV,                "hv",                46) /* Hypervisor instructions */ \
!     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */ \
+                                                      \
+     decl(RDTSCP,            "rdtscp",            48) /* RDTSCP instruction */ \
+     decl(RDPID,             "rdpid",             49) /* RDPID instruction */ \
+     decl(FSRM,              "fsrm",              50) /* Fast Short REP MOV */
  
  #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
      CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
  #undef DECLARE_CPU_FEATURE_FLAG
    };

*** 610,10 ***
--- 622,12 ---
        result |= CPU_TSCINV_BIT;
      if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
        result |= CPU_AES;
      if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
        result |= CPU_ERMS;
+     if (_cpuid_info.sef_cpuid7_edx.bits.fast_short_rep_mov != 0)
+       result |= CPU_FSRM;
      if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
        result |= CPU_CLMUL;
      if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
        result |= CPU_RTM;
      if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)

*** 624,10 ***
--- 638,14 ---
        result |= CPU_SHA;
      if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
        result |= CPU_FMA;
      if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
        result |= CPU_FLUSHOPT;
+     if (_cpuid_info.ext_cpuid1_edx.bits.rdtscp != 0)
+       result |= CPU_RDTSCP;
+     if (_cpuid_info.sef_cpuid7_ecx.bits.rdpid != 0)
+       result |= CPU_RDPID;
  
      // AMD|Hygon features.
      if (is_amd_family()) {
        if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
            (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))

*** 867,12 ***
--- 885,15 ---
    static bool supports_sse4_2()       { return (_features & CPU_SSE4_2) != 0; }
    static bool supports_popcnt()       { return (_features & CPU_POPCNT) != 0; }
    static bool supports_avx()          { return (_features & CPU_AVX) != 0; }
    static bool supports_avx2()         { return (_features & CPU_AVX2) != 0; }
    static bool supports_tsc()          { return (_features & CPU_TSC) != 0; }
+   static bool supports_rdtscp()       { return (_features & CPU_RDTSCP) != 0; }
+   static bool supports_rdpid()        { return (_features & CPU_RDPID) != 0; }
    static bool supports_aes()          { return (_features & CPU_AES) != 0; }
    static bool supports_erms()         { return (_features & CPU_ERMS) != 0; }
+   static bool supports_fsrm()         { return (_features & CPU_FSRM) != 0; }
    static bool supports_clmul()        { return (_features & CPU_CLMUL) != 0; }
    static bool supports_rtm()          { return (_features & CPU_RTM) != 0; }
    static bool supports_bmi1()         { return (_features & CPU_BMI1) != 0; }
    static bool supports_bmi2()         { return (_features & CPU_BMI2) != 0; }
    static bool supports_adx()          { return (_features & CPU_ADX) != 0; }
< prev index next >