1 /* 2 * Copyright (c) 1997, 2024, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_VM_VERSION_X86_HPP 26 #define CPU_X86_VM_VERSION_X86_HPP 27 28 #include "runtime/abstract_vm_version.hpp" 29 #include "utilities/macros.hpp" 30 #include "utilities/sizes.hpp" 31 32 class VM_Version : public Abstract_VM_Version { 33 friend class VMStructs; 34 friend class JVMCIVMStructs; 35 36 public: 37 // cpuid result register layouts. These are all unions of a uint32_t 38 // (in case anyone wants access to the register as a whole) and a bitfield. 39 40 union StdCpuid1Eax { 41 uint32_t value; 42 struct { 43 uint32_t stepping : 4, 44 model : 4, 45 family : 4, 46 proc_type : 2, 47 : 2, 48 ext_model : 4, 49 ext_family : 8, 50 : 4; 51 } bits; 52 }; 53 54 union StdCpuid1Ebx { // example, unused 55 uint32_t value; 56 struct { 57 uint32_t brand_id : 8, 58 clflush_size : 8, 59 threads_per_cpu : 8, 60 apic_id : 8; 61 } bits; 62 }; 63 64 union StdCpuid1Ecx { 65 uint32_t value; 66 struct { 67 uint32_t sse3 : 1, 68 clmul : 1, 69 : 1, 70 monitor : 1, 71 : 1, 72 vmx : 1, 73 : 1, 74 est : 1, 75 : 1, 76 ssse3 : 1, 77 cid : 1, 78 : 1, 79 fma : 1, 80 cmpxchg16: 1, 81 : 4, 82 dca : 1, 83 sse4_1 : 1, 84 sse4_2 : 1, 85 : 2, 86 popcnt : 1, 87 : 1, 88 aes : 1, 89 : 1, 90 osxsave : 1, 91 avx : 1, 92 f16c : 1, 93 : 1, 94 hv : 1; 95 } bits; 96 }; 97 98 union StdCpuid1Edx { 99 uint32_t value; 100 struct { 101 uint32_t : 4, 102 tsc : 1, 103 : 3, 104 cmpxchg8 : 1, 105 : 6, 106 cmov : 1, 107 : 3, 108 clflush : 1, 109 : 3, 110 mmx : 1, 111 fxsr : 1, 112 sse : 1, 113 sse2 : 1, 114 : 1, 115 ht : 1, 116 : 3; 117 } bits; 118 }; 119 120 union DcpCpuid4Eax { 121 uint32_t value; 122 struct { 123 uint32_t cache_type : 5, 124 : 21, 125 cores_per_cpu : 6; 126 } bits; 127 }; 128 129 union DcpCpuid4Ebx { 130 uint32_t value; 131 struct { 132 uint32_t L1_line_size : 12, 133 partitions : 10, 134 associativity : 10; 135 } bits; 136 }; 137 138 union TplCpuidBEbx { 139 uint32_t value; 140 struct { 141 uint32_t logical_cpus : 16, 142 : 16; 143 } bits; 144 }; 145 146 union ExtCpuid1Ecx { 147 uint32_t value; 148 struct { 149 uint32_t LahfSahf : 1, 150 CmpLegacy : 1, 151 : 3, 152 lzcnt : 1, 153 sse4a : 1, 154 misalignsse : 1, 155 prefetchw : 1, 156 : 23; 157 } bits; 158 }; 159 160 union ExtCpuid1Edx { 161 uint32_t value; 162 struct { 163 uint32_t : 22, 164 mmx_amd : 1, 165 mmx : 1, 166 fxsr : 1, 167 fxsr_opt : 1, 168 pdpe1gb : 1, 169 rdtscp : 1, 170 : 1, 171 long_mode : 1, 172 tdnow2 : 1, 173 tdnow : 1; 174 } bits; 175 }; 176 177 union ExtCpuid5Ex { 178 uint32_t value; 179 struct { 180 uint32_t L1_line_size : 8, 181 L1_tag_lines : 8, 182 L1_assoc : 8, 183 L1_size : 8; 184 } bits; 185 }; 186 187 union ExtCpuid7Edx { 188 uint32_t value; 189 struct { 190 uint32_t : 8, 191 tsc_invariance : 1, 192 : 23; 193 } bits; 194 }; 195 196 union ExtCpuid8Ecx { 197 uint32_t value; 198 struct { 199 uint32_t cores_per_cpu : 8, 200 : 24; 201 } bits; 202 }; 203 204 union SefCpuid7Eax { 205 uint32_t value; 206 }; 207 208 union SefCpuid7Ebx { 209 uint32_t value; 210 struct { 211 uint32_t fsgsbase : 1, 212 : 2, 213 bmi1 : 1, 214 : 1, 215 avx2 : 1, 216 : 2, 217 bmi2 : 1, 218 erms : 1, 219 : 1, 220 rtm : 1, 221 : 4, 222 avx512f : 1, 223 avx512dq : 1, 224 : 1, 225 adx : 1, 226 : 1, 227 avx512ifma : 1, 228 : 1, 229 clflushopt : 1, 230 clwb : 1, 231 : 1, 232 avx512pf : 1, 233 avx512er : 1, 234 avx512cd : 1, 235 sha : 1, 236 avx512bw : 1, 237 avx512vl : 1; 238 } bits; 239 }; 240 241 union SefCpuid7Ecx { 242 uint32_t value; 243 struct { 244 uint32_t prefetchwt1 : 1, 245 avx512_vbmi : 1, 246 umip : 1, 247 pku : 1, 248 ospke : 1, 249 : 1, 250 avx512_vbmi2 : 1, 251 cet_ss : 1, 252 gfni : 1, 253 vaes : 1, 254 avx512_vpclmulqdq : 1, 255 avx512_vnni : 1, 256 avx512_bitalg : 1, 257 : 1, 258 avx512_vpopcntdq : 1, 259 : 1, 260 : 1, 261 mawau : 5, 262 rdpid : 1, 263 : 9; 264 } bits; 265 }; 266 267 union SefCpuid7Edx { 268 uint32_t value; 269 struct { 270 uint32_t : 2, 271 avx512_4vnniw : 1, 272 avx512_4fmaps : 1, 273 fast_short_rep_mov : 1, 274 : 9, 275 serialize : 1, 276 : 5, 277 cet_ibt : 1, 278 : 11; 279 } bits; 280 }; 281 282 union SefCpuid7Ecx1Eax { 283 uint32_t value; 284 struct { 285 uint32_t : 23, 286 avx_ifma : 1, 287 : 8; 288 } bits; 289 }; 290 291 union ExtCpuid1EEbx { 292 uint32_t value; 293 struct { 294 uint32_t : 8, 295 threads_per_core : 8, 296 : 16; 297 } bits; 298 }; 299 300 union XemXcr0Eax { 301 uint32_t value; 302 struct { 303 uint32_t x87 : 1, 304 sse : 1, 305 ymm : 1, 306 bndregs : 1, 307 bndcsr : 1, 308 opmask : 1, 309 zmm512 : 1, 310 zmm32 : 1, 311 : 24; 312 } bits; 313 }; 314 315 protected: 316 static int _cpu; 317 static int _model; 318 static int _stepping; 319 320 static bool _has_intel_jcc_erratum; 321 322 static address _cpuinfo_segv_addr; // address of instruction which causes SEGV 323 static address _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV 324 325 /* 326 * Update following files when declaring new flags: 327 * test/lib-test/jdk/test/whitebox/CPUInfoTest.java 328 * src/jdk.internal.vm.ci/share/classes/jdk.vm.ci.amd64/src/jdk/vm/ci/amd64/AMD64.java 329 */ 330 enum Feature_Flag : uint64_t { 331 #define CPU_FEATURE_FLAGS(decl) \ 332 decl(CX8, "cx8", 0) /* next bits are from cpuid 1 (EDX) */ \ 333 decl(CMOV, "cmov", 1) \ 334 decl(FXSR, "fxsr", 2) \ 335 decl(HT, "ht", 3) \ 336 \ 337 decl(MMX, "mmx", 4) \ 338 decl(3DNOW_PREFETCH, "3dnowpref", 5) /* Processor supports 3dnow prefetch and prefetchw instructions */ \ 339 /* may not necessarily support other 3dnow instructions */ \ 340 decl(SSE, "sse", 6) \ 341 decl(SSE2, "sse2", 7) \ 342 \ 343 decl(SSE3, "sse3", 8 ) /* SSE3 comes from cpuid 1 (ECX) */ \ 344 decl(SSSE3, "ssse3", 9 ) \ 345 decl(SSE4A, "sse4a", 10) \ 346 decl(SSE4_1, "sse4.1", 11) \ 347 \ 348 decl(SSE4_2, "sse4.2", 12) \ 349 decl(POPCNT, "popcnt", 13) \ 350 decl(LZCNT, "lzcnt", 14) \ 351 decl(TSC, "tsc", 15) \ 352 \ 353 decl(TSCINV_BIT, "tscinvbit", 16) \ 354 decl(TSCINV, "tscinv", 17) \ 355 decl(AVX, "avx", 18) \ 356 decl(AVX2, "avx2", 19) \ 357 \ 358 decl(AES, "aes", 20) \ 359 decl(ERMS, "erms", 21) /* enhanced 'rep movsb/stosb' instructions */ \ 360 decl(CLMUL, "clmul", 22) /* carryless multiply for CRC */ \ 361 decl(BMI1, "bmi1", 23) \ 362 \ 363 decl(BMI2, "bmi2", 24) \ 364 decl(RTM, "rtm", 25) /* Restricted Transactional Memory instructions */ \ 365 decl(ADX, "adx", 26) \ 366 decl(AVX512F, "avx512f", 27) /* AVX 512bit foundation instructions */ \ 367 \ 368 decl(AVX512DQ, "avx512dq", 28) \ 369 decl(AVX512PF, "avx512pf", 29) \ 370 decl(AVX512ER, "avx512er", 30) \ 371 decl(AVX512CD, "avx512cd", 31) \ 372 \ 373 decl(AVX512BW, "avx512bw", 32) /* Byte and word vector instructions */ \ 374 decl(AVX512VL, "avx512vl", 33) /* EVEX instructions with smaller vector length */ \ 375 decl(SHA, "sha", 34) /* SHA instructions */ \ 376 decl(FMA, "fma", 35) /* FMA instructions */ \ 377 \ 378 decl(VZEROUPPER, "vzeroupper", 36) /* Vzeroupper instruction */ \ 379 decl(AVX512_VPOPCNTDQ, "avx512_vpopcntdq", 37) /* Vector popcount */ \ 380 decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \ 381 decl(AVX512_VAES, "avx512_vaes", 39) /* Vector AES instruction */ \ 382 \ 383 decl(AVX512_VNNI, "avx512_vnni", 40) /* Vector Neural Network Instructions */ \ 384 decl(FLUSH, "clflush", 41) /* flush instruction */ \ 385 decl(FLUSHOPT, "clflushopt", 42) /* flusopth instruction */ \ 386 decl(CLWB, "clwb", 43) /* clwb instruction */ \ 387 \ 388 decl(AVX512_VBMI2, "avx512_vbmi2", 44) /* VBMI2 shift left double instructions */ \ 389 decl(AVX512_VBMI, "avx512_vbmi", 45) /* Vector BMI instructions */ \ 390 decl(HV, "hv", 46) /* Hypervisor instructions */ \ 391 decl(SERIALIZE, "serialize", 47) /* CPU SERIALIZE */ \ 392 decl(RDTSCP, "rdtscp", 48) /* RDTSCP instruction */ \ 393 decl(RDPID, "rdpid", 49) /* RDPID instruction */ \ 394 decl(FSRM, "fsrm", 50) /* Fast Short REP MOV */ \ 395 decl(GFNI, "gfni", 51) /* Vector GFNI instructions */ \ 396 decl(AVX512_BITALG, "avx512_bitalg", 52) /* Vector sub-word popcount and bit gather instructions */\ 397 decl(F16C, "f16c", 53) /* Half-precision and single precision FP conversion instructions*/ \ 398 decl(PKU, "pku", 54) /* Protection keys for user-mode pages */ \ 399 decl(OSPKE, "ospke", 55) /* OS enables protection keys */ \ 400 decl(CET_IBT, "cet_ibt", 56) /* Control Flow Enforcement - Indirect Branch Tracking */ \ 401 decl(CET_SS, "cet_ss", 57) /* Control Flow Enforcement - Shadow Stack */ \ 402 decl(AVX512_IFMA, "avx512_ifma", 58) /* Integer Vector FMA instructions*/ \ 403 decl(AVX_IFMA, "avx_ifma", 59) /* 256-bit VEX-coded variant of AVX512-IFMA*/ 404 405 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit), 406 CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG) 407 #undef DECLARE_CPU_FEATURE_FLAG 408 }; 409 410 static const char* _features_names[]; 411 412 enum Extended_Family { 413 // AMD 414 CPU_FAMILY_AMD_11H = 0x11, 415 // ZX 416 CPU_FAMILY_ZX_CORE_F6 = 6, 417 CPU_FAMILY_ZX_CORE_F7 = 7, 418 // Intel 419 CPU_FAMILY_INTEL_CORE = 6, 420 CPU_MODEL_NEHALEM = 0x1e, 421 CPU_MODEL_NEHALEM_EP = 0x1a, 422 CPU_MODEL_NEHALEM_EX = 0x2e, 423 CPU_MODEL_WESTMERE = 0x25, 424 CPU_MODEL_WESTMERE_EP = 0x2c, 425 CPU_MODEL_WESTMERE_EX = 0x2f, 426 CPU_MODEL_SANDYBRIDGE = 0x2a, 427 CPU_MODEL_SANDYBRIDGE_EP = 0x2d, 428 CPU_MODEL_IVYBRIDGE_EP = 0x3a, 429 CPU_MODEL_HASWELL_E3 = 0x3c, 430 CPU_MODEL_HASWELL_E7 = 0x3f, 431 CPU_MODEL_BROADWELL = 0x3d, 432 CPU_MODEL_SKYLAKE = 0x55 433 }; 434 435 // cpuid information block. All info derived from executing cpuid with 436 // various function numbers is stored here. Intel and AMD info is 437 // merged in this block: accessor methods disentangle it. 438 // 439 // The info block is laid out in subblocks of 4 dwords corresponding to 440 // eax, ebx, ecx and edx, whether or not they contain anything useful. 441 class CpuidInfo { 442 public: 443 // cpuid function 0 444 uint32_t std_max_function; 445 uint32_t std_vendor_name_0; 446 uint32_t std_vendor_name_1; 447 uint32_t std_vendor_name_2; 448 449 // cpuid function 1 450 StdCpuid1Eax std_cpuid1_eax; 451 StdCpuid1Ebx std_cpuid1_ebx; 452 StdCpuid1Ecx std_cpuid1_ecx; 453 StdCpuid1Edx std_cpuid1_edx; 454 455 // cpuid function 4 (deterministic cache parameters) 456 DcpCpuid4Eax dcp_cpuid4_eax; 457 DcpCpuid4Ebx dcp_cpuid4_ebx; 458 uint32_t dcp_cpuid4_ecx; // unused currently 459 uint32_t dcp_cpuid4_edx; // unused currently 460 461 // cpuid function 7 (structured extended features) 462 // ECX = 0 before calling cpuid() 463 SefCpuid7Eax sef_cpuid7_eax; 464 SefCpuid7Ebx sef_cpuid7_ebx; 465 SefCpuid7Ecx sef_cpuid7_ecx; 466 SefCpuid7Edx sef_cpuid7_edx; 467 // ECX = 1 before calling cpuid() 468 SefCpuid7Ecx1Eax sef_cpuid7_ecx1_eax; 469 470 // cpuid function 0xB (processor topology) 471 // ecx = 0 472 uint32_t tpl_cpuidB0_eax; 473 TplCpuidBEbx tpl_cpuidB0_ebx; 474 uint32_t tpl_cpuidB0_ecx; // unused currently 475 uint32_t tpl_cpuidB0_edx; // unused currently 476 477 // ecx = 1 478 uint32_t tpl_cpuidB1_eax; 479 TplCpuidBEbx tpl_cpuidB1_ebx; 480 uint32_t tpl_cpuidB1_ecx; // unused currently 481 uint32_t tpl_cpuidB1_edx; // unused currently 482 483 // ecx = 2 484 uint32_t tpl_cpuidB2_eax; 485 TplCpuidBEbx tpl_cpuidB2_ebx; 486 uint32_t tpl_cpuidB2_ecx; // unused currently 487 uint32_t tpl_cpuidB2_edx; // unused currently 488 489 // cpuid function 0x80000000 // example, unused 490 uint32_t ext_max_function; 491 uint32_t ext_vendor_name_0; 492 uint32_t ext_vendor_name_1; 493 uint32_t ext_vendor_name_2; 494 495 // cpuid function 0x80000001 496 uint32_t ext_cpuid1_eax; // reserved 497 uint32_t ext_cpuid1_ebx; // reserved 498 ExtCpuid1Ecx ext_cpuid1_ecx; 499 ExtCpuid1Edx ext_cpuid1_edx; 500 501 // cpuid functions 0x80000002 thru 0x80000004: example, unused 502 uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3; 503 uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7; 504 uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11; 505 506 // cpuid function 0x80000005 // AMD L1, Intel reserved 507 uint32_t ext_cpuid5_eax; // unused currently 508 uint32_t ext_cpuid5_ebx; // reserved 509 ExtCpuid5Ex ext_cpuid5_ecx; // L1 data cache info (AMD) 510 ExtCpuid5Ex ext_cpuid5_edx; // L1 instruction cache info (AMD) 511 512 // cpuid function 0x80000007 513 uint32_t ext_cpuid7_eax; // reserved 514 uint32_t ext_cpuid7_ebx; // reserved 515 uint32_t ext_cpuid7_ecx; // reserved 516 ExtCpuid7Edx ext_cpuid7_edx; // tscinv 517 518 // cpuid function 0x80000008 519 uint32_t ext_cpuid8_eax; // unused currently 520 uint32_t ext_cpuid8_ebx; // reserved 521 ExtCpuid8Ecx ext_cpuid8_ecx; 522 uint32_t ext_cpuid8_edx; // reserved 523 524 // cpuid function 0x8000001E // AMD 17h 525 uint32_t ext_cpuid1E_eax; 526 ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h) 527 uint32_t ext_cpuid1E_ecx; 528 uint32_t ext_cpuid1E_edx; // unused currently 529 530 // extended control register XCR0 (the XFEATURE_ENABLED_MASK register) 531 XemXcr0Eax xem_xcr0_eax; 532 uint32_t xem_xcr0_edx; // reserved 533 534 // Space to save ymm registers after signal handle 535 int ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15 536 537 // Space to save zmm registers after signal handle 538 int zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31 539 540 uint64_t feature_flags() const; 541 542 // Asserts 543 void assert_is_initialized() const { 544 assert(std_cpuid1_eax.bits.family != 0, "VM_Version not initialized"); 545 } 546 547 // Extractors 548 uint32_t extended_cpu_family() const { 549 uint32_t result = std_cpuid1_eax.bits.family; 550 result += std_cpuid1_eax.bits.ext_family; 551 return result; 552 } 553 554 uint32_t extended_cpu_model() const { 555 uint32_t result = std_cpuid1_eax.bits.model; 556 result |= std_cpuid1_eax.bits.ext_model << 4; 557 return result; 558 } 559 560 uint32_t cpu_stepping() const { 561 uint32_t result = std_cpuid1_eax.bits.stepping; 562 return result; 563 } 564 }; 565 566 private: 567 // The actual cpuid info block 568 static CpuidInfo _cpuid_info; 569 570 // Extractors and predicates 571 static uint logical_processor_count() { 572 uint result = threads_per_core(); 573 return result; 574 } 575 576 static bool compute_has_intel_jcc_erratum(); 577 578 static bool os_supports_avx_vectors(); 579 static void get_processor_features(); 580 581 public: 582 // Offsets for cpuid asm stub 583 static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); } 584 static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); } 585 static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); } 586 static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); } 587 static ByteSize sef_cpuid7_ecx1_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_ecx1_eax); } 588 static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); } 589 static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); } 590 static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); } 591 static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); } 592 static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); } 593 static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); } 594 static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); } 595 static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); } 596 static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); } 597 static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); } 598 static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); } 599 600 // The value used to check ymm register after signal handle 601 static int ymm_test_value() { return 0xCAFEBABE; } 602 603 static void get_cpu_info_wrapper(); 604 static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; } 605 static bool is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; } 606 static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; } 607 static address cpuinfo_cont_addr() { return _cpuinfo_cont_addr; } 608 609 static void clean_cpuFeatures() { _features = 0; } 610 static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); } 611 static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); } 612 613 // Initialization 614 static void initialize(); 615 616 // Override Abstract_VM_Version implementation 617 static void print_platform_virtualization_info(outputStream*); 618 619 // 620 // Processor family: 621 // 3 - 386 622 // 4 - 486 623 // 5 - Pentium 624 // 6 - PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon, 625 // Pentium M, Core Solo, Core Duo, Core2 Duo 626 // family 6 model: 9, 13, 14, 15 627 // 0x0f - Pentium 4, Opteron 628 // 629 // Note: The cpu family should be used to select between 630 // instruction sequences which are valid on all Intel 631 // processors. Use the feature test functions below to 632 // determine whether a particular instruction is supported. 633 // 634 static void assert_is_initialized() { _cpuid_info.assert_is_initialized(); } 635 static uint32_t extended_cpu_family() { return _cpuid_info.extended_cpu_family(); } 636 static uint32_t extended_cpu_model() { return _cpuid_info.extended_cpu_model(); } 637 static uint32_t cpu_stepping() { return _cpuid_info.cpu_stepping(); } 638 static int cpu_family() { return _cpu;} 639 static bool is_P6() { return cpu_family() >= 6; } 640 static bool is_amd() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA' 641 static bool is_hygon() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH' 642 static bool is_amd_family() { return is_amd() || is_hygon(); } 643 static bool is_intel() { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG' 644 static bool is_zx() { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS ' 645 static bool is_atom_family() { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton 646 static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi 647 648 static bool supports_processor_topology() { 649 return (_cpuid_info.std_max_function >= 0xB) && 650 // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level. 651 // Some cpus have max cpuid >= 0xB but do not support processor topology. 652 (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0); 653 } 654 655 static uint cores_per_cpu(); 656 static uint threads_per_core(); 657 static uint L1_line_size(); 658 659 static uint prefetch_data_size() { 660 return L1_line_size(); 661 } 662 663 // 664 // Feature identification which can be affected by VM settings 665 // 666 static bool supports_cpuid() { return _features != 0; } 667 static bool supports_cmov() { return (_features & CPU_CMOV) != 0; } 668 static bool supports_fxsr() { return (_features & CPU_FXSR) != 0; } 669 static bool supports_ht() { return (_features & CPU_HT) != 0; } 670 static bool supports_mmx() { return (_features & CPU_MMX) != 0; } 671 static bool supports_sse() { return (_features & CPU_SSE) != 0; } 672 static bool supports_sse2() { return (_features & CPU_SSE2) != 0; } 673 static bool supports_sse3() { return (_features & CPU_SSE3) != 0; } 674 static bool supports_ssse3() { return (_features & CPU_SSSE3)!= 0; } 675 static bool supports_sse4_1() { return (_features & CPU_SSE4_1) != 0; } 676 static bool supports_sse4_2() { return (_features & CPU_SSE4_2) != 0; } 677 static bool supports_popcnt() { return (_features & CPU_POPCNT) != 0; } 678 static bool supports_avx() { return (_features & CPU_AVX) != 0; } 679 static bool supports_avx2() { return (_features & CPU_AVX2) != 0; } 680 static bool supports_tsc() { return (_features & CPU_TSC) != 0; } 681 static bool supports_rdtscp() { return (_features & CPU_RDTSCP) != 0; } 682 static bool supports_rdpid() { return (_features & CPU_RDPID) != 0; } 683 static bool supports_aes() { return (_features & CPU_AES) != 0; } 684 static bool supports_erms() { return (_features & CPU_ERMS) != 0; } 685 static bool supports_fsrm() { return (_features & CPU_FSRM) != 0; } 686 static bool supports_clmul() { return (_features & CPU_CLMUL) != 0; } 687 static bool supports_rtm() { return (_features & CPU_RTM) != 0; } 688 static bool supports_bmi1() { return (_features & CPU_BMI1) != 0; } 689 static bool supports_bmi2() { return (_features & CPU_BMI2) != 0; } 690 static bool supports_adx() { return (_features & CPU_ADX) != 0; } 691 static bool supports_evex() { return (_features & CPU_AVX512F) != 0; } 692 static bool supports_avx512dq() { return (_features & CPU_AVX512DQ) != 0; } 693 static bool supports_avx512ifma() { return (_features & CPU_AVX512_IFMA) != 0; } 694 static bool supports_avxifma() { return (_features & CPU_AVX_IFMA) != 0; } 695 static bool supports_avx512pf() { return (_features & CPU_AVX512PF) != 0; } 696 static bool supports_avx512er() { return (_features & CPU_AVX512ER) != 0; } 697 static bool supports_avx512cd() { return (_features & CPU_AVX512CD) != 0; } 698 static bool supports_avx512bw() { return (_features & CPU_AVX512BW) != 0; } 699 static bool supports_avx512vl() { return (_features & CPU_AVX512VL) != 0; } 700 static bool supports_avx512vlbw() { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); } 701 static bool supports_avx512bwdq() { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); } 702 static bool supports_avx512vldq() { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); } 703 static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() && 704 supports_avx512bw() && supports_avx512dq()); } 705 static bool supports_avx512novl() { return (supports_evex() && !supports_avx512vl()); } 706 static bool supports_avx512nobw() { return (supports_evex() && !supports_avx512bw()); } 707 static bool supports_avx256only() { return (supports_avx2() && !supports_evex()); } 708 static bool supports_avxonly() { return ((supports_avx2() || supports_avx()) && !supports_evex()); } 709 static bool supports_sha() { return (_features & CPU_SHA) != 0; } 710 static bool supports_fma() { return (_features & CPU_FMA) != 0 && supports_avx(); } 711 static bool supports_vzeroupper() { return (_features & CPU_VZEROUPPER) != 0; } 712 static bool supports_avx512_vpopcntdq() { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; } 713 static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; } 714 static bool supports_avx512_vaes() { return (_features & CPU_AVX512_VAES) != 0; } 715 static bool supports_gfni() { return (_features & CPU_GFNI) != 0; } 716 static bool supports_avx512_vnni() { return (_features & CPU_AVX512_VNNI) != 0; } 717 static bool supports_avx512_bitalg() { return (_features & CPU_AVX512_BITALG) != 0; } 718 static bool supports_avx512_vbmi() { return (_features & CPU_AVX512_VBMI) != 0; } 719 static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; } 720 static bool supports_hv() { return (_features & CPU_HV) != 0; } 721 static bool supports_serialize() { return (_features & CPU_SERIALIZE) != 0; } 722 static bool supports_f16c() { return (_features & CPU_F16C) != 0; } 723 static bool supports_pku() { return (_features & CPU_PKU) != 0; } 724 static bool supports_ospke() { return (_features & CPU_OSPKE) != 0; } 725 static bool supports_cet_ss() { return (_features & CPU_CET_SS) != 0; } 726 static bool supports_cet_ibt() { return (_features & CPU_CET_IBT) != 0; } 727 728 // 729 // Feature identification not affected by VM flags 730 // 731 static bool cpu_supports_evex() { return (_cpu_features & CPU_AVX512F) != 0; } 732 733 // Intel features 734 static bool is_intel_family_core() { return is_intel() && 735 extended_cpu_family() == CPU_FAMILY_INTEL_CORE; } 736 737 static bool is_intel_skylake() { return is_intel_family_core() && 738 extended_cpu_model() == CPU_MODEL_SKYLAKE; } 739 740 #ifdef COMPILER2 741 // Determine if it's running on Cascade Lake using default options. 742 static bool is_default_intel_cascade_lake(); 743 #endif 744 745 static bool is_intel_cascade_lake(); 746 747 static int avx3_threshold(); 748 749 static bool is_intel_tsc_synched_at_init(); 750 751 // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102) 752 // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode 753 // mitigation causes regressions when jumps or fused conditional branches cross or end at 754 // 32 byte boundaries. 755 static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; } 756 757 // AMD features 758 static bool supports_3dnow_prefetch() { return (_features & CPU_3DNOW_PREFETCH) != 0; } 759 static bool supports_lzcnt() { return (_features & CPU_LZCNT) != 0; } 760 static bool supports_sse4a() { return (_features & CPU_SSE4A) != 0; } 761 762 static bool is_amd_Barcelona() { return is_amd() && 763 extended_cpu_family() == CPU_FAMILY_AMD_11H; } 764 765 // Intel and AMD newer cores support fast timestamps well 766 static bool supports_tscinv_bit() { 767 return (_features & CPU_TSCINV_BIT) != 0; 768 } 769 static bool supports_tscinv() { 770 return (_features & CPU_TSCINV) != 0; 771 } 772 773 // Intel Core and newer cpus have fast IDIV instruction (excluding Atom). 774 static bool has_fast_idiv() { return is_intel() && cpu_family() == 6 && 775 supports_sse3() && _model != 0x1C; } 776 777 static bool supports_compare_and_exchange() { return true; } 778 779 static int allocate_prefetch_distance(bool use_watermark_prefetch); 780 781 // SSE2 and later processors implement a 'pause' instruction 782 // that can be used for efficient implementation of 783 // the intrinsic for java.lang.Thread.onSpinWait() 784 static bool supports_on_spin_wait() { return supports_sse2(); } 785 786 // x86_64 supports fast class initialization checks 787 static bool supports_fast_class_init_checks() { 788 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32 789 } 790 791 static bool supports_cont_preemption() { return true; } 792 793 // x86_64 supports secondary supers table 794 constexpr static bool supports_secondary_supers_table() { 795 return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32 796 } 797 798 constexpr static bool supports_stack_watermark_barrier() { 799 return true; 800 } 801 802 constexpr static bool supports_recursive_lightweight_locking() { 803 return true; 804 } 805 806 // For AVX CPUs only. f16c support is disabled if UseAVX == 0. 807 static bool supports_float16() { 808 return supports_f16c() || supports_avx512vl(); 809 } 810 811 // Check intrinsic support 812 static bool is_intrinsic_supported(vmIntrinsicID id); 813 814 // there are several insns to force cache line sync to memory which 815 // we can use to ensure mapped non-volatile memory is up to date with 816 // pending in-cache changes. 817 // 818 // 64 bit cpus always support clflush which writes back and evicts 819 // on 32 bit cpus support is recorded via a feature flag 820 // 821 // clflushopt is optional and acts like clflush except it does 822 // not synchronize with other memory ops. it needs a preceding 823 // and trailing StoreStore fence 824 // 825 // clwb is an optional intel-specific instruction which 826 // writes back without evicting the line. it also does not 827 // synchronize with other memory ops. so, it needs preceding 828 // and trailing StoreStore fences. 829 830 #ifdef _LP64 831 static bool supports_clflush(); // Can't inline due to header file conflict 832 #else 833 static bool supports_clflush() { return ((_features & CPU_FLUSH) != 0); } 834 #endif // _LP64 835 836 // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit 837 static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); } 838 static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); } 839 840 // Old CPUs perform lea on AGU which causes additional latency transferring the 841 // value from/to ALU for other operations 842 static bool supports_fast_2op_lea() { 843 return (is_intel() && supports_avx()) || // Sandy Bridge and above 844 (is_amd() && supports_avx()); // Jaguar and Bulldozer and above 845 } 846 847 // Pre Icelake Intels suffer inefficiency regarding 3-operand lea, which contains 848 // all of base register, index register and displacement immediate, with 3 latency. 849 // Note that when the address contains no displacement but the base register is 850 // rbp or r13, the machine code must contain a zero displacement immediate, 851 // effectively transform a 2-operand lea into a 3-operand lea. This can be 852 // replaced by add-add or lea-add 853 static bool supports_fast_3op_lea() { 854 return supports_fast_2op_lea() && 855 ((is_intel() && supports_clwb() && !is_intel_skylake()) || // Icelake and above 856 is_amd()); 857 } 858 859 #ifdef __APPLE__ 860 // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64) 861 static bool is_cpu_emulated(); 862 #endif 863 864 // support functions for virtualization detection 865 private: 866 static void check_virtualizations(); 867 868 static const char* cpu_family_description(void); 869 static const char* cpu_model_description(void); 870 static const char* cpu_brand(void); 871 static const char* cpu_brand_string(void); 872 873 static int cpu_type_description(char* const buf, size_t buf_len); 874 static int cpu_detailed_description(char* const buf, size_t buf_len); 875 static int cpu_extended_brand_string(char* const buf, size_t buf_len); 876 877 static bool cpu_is_em64t(void); 878 static bool is_netburst(void); 879 880 // Returns bytes written excluding termninating null byte. 881 static size_t cpu_write_support_string(char* const buf, size_t buf_len); 882 static void resolve_cpu_information_details(void); 883 static int64_t max_qualified_cpu_freq_from_brand_string(void); 884 885 public: 886 // Offsets for cpuid asm stub brand string 887 static ByteSize proc_name_0_offset() { return byte_offset_of(CpuidInfo, proc_name_0); } 888 static ByteSize proc_name_1_offset() { return byte_offset_of(CpuidInfo, proc_name_1); } 889 static ByteSize proc_name_2_offset() { return byte_offset_of(CpuidInfo, proc_name_2); } 890 static ByteSize proc_name_3_offset() { return byte_offset_of(CpuidInfo, proc_name_3); } 891 static ByteSize proc_name_4_offset() { return byte_offset_of(CpuidInfo, proc_name_4); } 892 static ByteSize proc_name_5_offset() { return byte_offset_of(CpuidInfo, proc_name_5); } 893 static ByteSize proc_name_6_offset() { return byte_offset_of(CpuidInfo, proc_name_6); } 894 static ByteSize proc_name_7_offset() { return byte_offset_of(CpuidInfo, proc_name_7); } 895 static ByteSize proc_name_8_offset() { return byte_offset_of(CpuidInfo, proc_name_8); } 896 static ByteSize proc_name_9_offset() { return byte_offset_of(CpuidInfo, proc_name_9); } 897 static ByteSize proc_name_10_offset() { return byte_offset_of(CpuidInfo, proc_name_10); } 898 static ByteSize proc_name_11_offset() { return byte_offset_of(CpuidInfo, proc_name_11); } 899 900 static int64_t maximum_qualified_cpu_frequency(void); 901 902 static bool supports_tscinv_ext(void); 903 904 static void initialize_tsc(); 905 static void initialize_cpu_information(void); 906 }; 907 908 #endif // CPU_X86_VM_VERSION_X86_HPP