1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_VERSION_X86_HPP
  26 #define CPU_X86_VM_VERSION_X86_HPP
  27 
  28 #include "runtime/abstract_vm_version.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "utilities/sizes.hpp"
  31 
  32 class VM_Version : public Abstract_VM_Version {
  33   friend class VMStructs;
  34   friend class JVMCIVMStructs;
  35 
  36  public:
  37   // cpuid result register layouts.  These are all unions of a uint32_t
  38   // (in case anyone wants access to the register as a whole) and a bitfield.
  39 
  40   union StdCpuid1Eax {
  41     uint32_t value;
  42     struct {
  43       uint32_t stepping   : 4,
  44                model      : 4,
  45                family     : 4,
  46                proc_type  : 2,
  47                           : 2,
  48                ext_model  : 4,
  49                ext_family : 8,
  50                           : 4;
  51     } bits;
  52   };
  53 
  54   union StdCpuid1Ebx { // example, unused
  55     uint32_t value;
  56     struct {
  57       uint32_t brand_id         : 8,
  58                clflush_size     : 8,
  59                threads_per_cpu  : 8,
  60                apic_id          : 8;
  61     } bits;
  62   };
  63 
  64   union StdCpuid1Ecx {
  65     uint32_t value;
  66     struct {
  67       uint32_t sse3     : 1,
  68                clmul    : 1,
  69                         : 1,
  70                monitor  : 1,
  71                         : 1,
  72                vmx      : 1,
  73                         : 1,
  74                est      : 1,
  75                         : 1,
  76                ssse3    : 1,
  77                cid      : 1,
  78                         : 1,
  79                fma      : 1,
  80                cmpxchg16: 1,
  81                         : 4,
  82                dca      : 1,
  83                sse4_1   : 1,
  84                sse4_2   : 1,
  85                         : 2,
  86                popcnt   : 1,
  87                         : 1,
  88                aes      : 1,
  89                         : 1,
  90                osxsave  : 1,
  91                avx      : 1,
  92                         : 2,
  93                hv       : 1;
  94     } bits;
  95   };
  96 
  97   union StdCpuid1Edx {
  98     uint32_t value;
  99     struct {
 100       uint32_t          : 4,
 101                tsc      : 1,
 102                         : 3,
 103                cmpxchg8 : 1,
 104                         : 6,
 105                cmov     : 1,
 106                         : 3,
 107                clflush  : 1,
 108                         : 3,
 109                mmx      : 1,
 110                fxsr     : 1,
 111                sse      : 1,
 112                sse2     : 1,
 113                         : 1,
 114                ht       : 1,
 115                         : 3;
 116     } bits;
 117   };
 118 
 119   union DcpCpuid4Eax {
 120     uint32_t value;
 121     struct {
 122       uint32_t cache_type    : 5,
 123                              : 21,
 124                cores_per_cpu : 6;
 125     } bits;
 126   };
 127 
 128   union DcpCpuid4Ebx {
 129     uint32_t value;
 130     struct {
 131       uint32_t L1_line_size  : 12,
 132                partitions    : 10,
 133                associativity : 10;
 134     } bits;
 135   };
 136 
 137   union TplCpuidBEbx {
 138     uint32_t value;
 139     struct {
 140       uint32_t logical_cpus : 16,
 141                             : 16;
 142     } bits;
 143   };
 144 
 145   union ExtCpuid1Ecx {
 146     uint32_t value;
 147     struct {
 148       uint32_t LahfSahf     : 1,
 149                CmpLegacy    : 1,
 150                             : 3,
 151                lzcnt_intel  : 1,
 152                lzcnt        : 1,
 153                sse4a        : 1,
 154                misalignsse  : 1,
 155                prefetchw    : 1,
 156                             : 22;
 157     } bits;
 158   };
 159 
 160   union ExtCpuid1Edx {
 161     uint32_t value;
 162     struct {
 163       uint32_t           : 22,
 164                mmx_amd   : 1,
 165                mmx       : 1,
 166                fxsr      : 1,
 167                fxsr_opt  : 1,
 168                pdpe1gb   : 1,
 169                rdtscp    : 1,
 170                          : 1,
 171                long_mode : 1,
 172                tdnow2    : 1,
 173                tdnow     : 1;
 174     } bits;
 175   };
 176 
 177   union ExtCpuid5Ex {
 178     uint32_t value;
 179     struct {
 180       uint32_t L1_line_size : 8,
 181                L1_tag_lines : 8,
 182                L1_assoc     : 8,
 183                L1_size      : 8;
 184     } bits;
 185   };
 186 
 187   union ExtCpuid7Edx {
 188     uint32_t value;
 189     struct {
 190       uint32_t               : 8,
 191               tsc_invariance : 1,
 192                              : 23;
 193     } bits;
 194   };
 195 
 196   union ExtCpuid8Ecx {
 197     uint32_t value;
 198     struct {
 199       uint32_t cores_per_cpu : 8,
 200                              : 24;
 201     } bits;
 202   };
 203 
 204   union SefCpuid7Eax {
 205     uint32_t value;
 206   };
 207 
 208   union SefCpuid7Ebx {
 209     uint32_t value;
 210     struct {
 211       uint32_t fsgsbase : 1,
 212                         : 2,
 213                    bmi1 : 1,
 214                         : 1,
 215                    avx2 : 1,
 216                         : 2,
 217                    bmi2 : 1,
 218                    erms : 1,
 219                         : 1,
 220                     rtm : 1,
 221                         : 4,
 222                 avx512f : 1,
 223                avx512dq : 1,
 224                         : 1,
 225                     adx : 1,
 226                         : 3,
 227              clflushopt : 1,
 228                    clwb : 1,
 229                         : 1,
 230                avx512pf : 1,
 231                avx512er : 1,
 232                avx512cd : 1,
 233                     sha : 1,
 234                avx512bw : 1,
 235                avx512vl : 1;
 236     } bits;
 237   };
 238 
 239   union SefCpuid7Ecx {
 240     uint32_t value;
 241     struct {
 242       uint32_t prefetchwt1 : 1,
 243                avx512_vbmi : 1,
 244                       umip : 1,
 245                        pku : 1,
 246                      ospke : 1,
 247                            : 1,
 248               avx512_vbmi2 : 1,
 249                            : 1,
 250                       gfni : 1,
 251                       vaes : 1,
 252          avx512_vpclmulqdq : 1,
 253                avx512_vnni : 1,
 254              avx512_bitalg : 1,
 255                            : 1,
 256           avx512_vpopcntdq : 1,
 257                            : 1,
 258                            : 1,
 259                      mawau : 5,
 260                      rdpid : 1,
 261                            : 9;
 262     } bits;
 263   };
 264 
 265   union SefCpuid7Edx {
 266     uint32_t value;
 267     struct {
 268       uint32_t             : 2,
 269              avx512_4vnniw : 1,
 270              avx512_4fmaps : 1,
 271         fast_short_rep_mov : 1,
 272                            : 9,
 273                  serialize : 1,
 274                            : 17;
 275     } bits;
 276   };
 277 
 278   union ExtCpuid1EEbx {
 279     uint32_t value;
 280     struct {
 281       uint32_t                  : 8,
 282                threads_per_core : 8,
 283                                 : 16;
 284     } bits;
 285   };
 286 
 287   union XemXcr0Eax {
 288     uint32_t value;
 289     struct {
 290       uint32_t x87     : 1,
 291                sse     : 1,
 292                ymm     : 1,
 293                bndregs : 1,
 294                bndcsr  : 1,
 295                opmask  : 1,
 296                zmm512  : 1,
 297                zmm32   : 1,
 298                        : 24;
 299     } bits;
 300   };
 301 
 302 protected:
 303   static int _cpu;
 304   static int _model;
 305   static int _stepping;
 306 
 307   static bool _has_intel_jcc_erratum;
 308 
 309   static address   _cpuinfo_segv_addr; // address of instruction which causes SEGV
 310   static address   _cpuinfo_cont_addr; // address of instruction after the one which causes SEGV
 311 
 312   enum Feature_Flag : uint64_t {
 313 #define CPU_FEATURE_FLAGS(decl) \
 314     decl(CX8,               "cx8",               0)  /*  next bits are from cpuid 1 (EDX) */ \
 315     decl(CMOV,              "cmov",              1)  \
 316     decl(FXSR,              "fxsr",              2)  \
 317     decl(HT,                "ht",                3)  \
 318                                                      \
 319     decl(MMX,               "mmx",               4)  \
 320     decl(3DNOW_PREFETCH,    "3dnowpref",         5)  /* Processor supports 3dnow prefetch and prefetchw instructions */ \
 321                                                      /* may not necessarily support other 3dnow instructions */ \
 322     decl(SSE,               "sse",               6)  \
 323     decl(SSE2,              "sse2",              7)  \
 324                                                      \
 325     decl(SSE3,              "sse3",              8 ) /* SSE3 comes from cpuid 1 (ECX) */ \
 326     decl(SSSE3,             "ssse3",             9 ) \
 327     decl(SSE4A,             "sse4a",             10) \
 328     decl(SSE4_1,            "sse4.1",            11) \
 329                                                      \
 330     decl(SSE4_2,            "sse4.2",            12) \
 331     decl(POPCNT,            "popcnt",            13) \
 332     decl(LZCNT,             "lzcnt",             14) \
 333     decl(TSC,               "tsc",               15) \
 334                                                      \
 335     decl(TSCINV_BIT,        "tscinvbit",         16) \
 336     decl(TSCINV,            "tscinv",            17) \
 337     decl(AVX,               "avx",               18) \
 338     decl(AVX2,              "avx2",              19) \
 339                                                      \
 340     decl(AES,               "aes",               20) \
 341     decl(ERMS,              "erms",              21) /* enhanced 'rep movsb/stosb' instructions */ \
 342     decl(CLMUL,             "clmul",             22) /* carryless multiply for CRC */ \
 343     decl(BMI1,              "bmi1",              23) \
 344                                                      \
 345     decl(BMI2,              "bmi2",              24) \
 346     decl(RTM,               "rtm",               25) /* Restricted Transactional Memory instructions */ \
 347     decl(ADX,               "adx",               26) \
 348     decl(AVX512F,           "avx512f",           27) /* AVX 512bit foundation instructions */ \
 349                                                      \
 350     decl(AVX512DQ,          "avx512dq",          28) \
 351     decl(AVX512PF,          "avx512pf",          29) \
 352     decl(AVX512ER,          "avx512er",          30) \
 353     decl(AVX512CD,          "avx512cd",          31) \
 354                                                      \
 355     decl(AVX512BW,          "avx512bw",          32) /* Byte and word vector instructions */ \
 356     decl(AVX512VL,          "avx512vl",          33) /* EVEX instructions with smaller vector length */ \
 357     decl(SHA,               "sha",               34) /* SHA instructions */ \
 358     decl(FMA,               "fma",               35) /* FMA instructions */ \
 359                                                      \
 360     decl(VZEROUPPER,        "vzeroupper",        36) /* Vzeroupper instruction */ \
 361     decl(AVX512_VPOPCNTDQ,  "avx512_vpopcntdq",  37) /* Vector popcount */ \
 362     decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
 363     decl(AVX512_VAES,       "avx512_vaes",       39) /* Vector AES instruction */ \
 364                                                      \
 365     decl(AVX512_VNNI,       "avx512_vnni",       40) /* Vector Neural Network Instructions */ \
 366     decl(FLUSH,             "clflush",           41) /* flush instruction */ \
 367     decl(FLUSHOPT,          "clflushopt",        42) /* flusopth instruction */ \
 368     decl(CLWB,              "clwb",              43) /* clwb instruction */ \
 369                                                      \
 370     decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
 371     decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
 372     decl(HV,                "hv",                46) /* Hypervisor instructions */ \
 373     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */ \
 374                                                      \
 375     decl(RDTSCP,            "rdtscp",            48) /* RDTSCP instruction */ \
 376     decl(RDPID,             "rdpid",             49) /* RDPID instruction */ \
 377     decl(FSRM,              "fsrm",              50) /* Fast Short REP MOV */
 378 
 379 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
 380     CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
 381 #undef DECLARE_CPU_FEATURE_FLAG
 382   };
 383 
 384   static const char* _features_names[];
 385 
 386 enum Extended_Family {
 387     // AMD
 388     CPU_FAMILY_AMD_11H       = 0x11,
 389     // ZX
 390     CPU_FAMILY_ZX_CORE_F6    = 6,
 391     CPU_FAMILY_ZX_CORE_F7    = 7,
 392     // Intel
 393     CPU_FAMILY_INTEL_CORE    = 6,
 394     CPU_MODEL_NEHALEM        = 0x1e,
 395     CPU_MODEL_NEHALEM_EP     = 0x1a,
 396     CPU_MODEL_NEHALEM_EX     = 0x2e,
 397     CPU_MODEL_WESTMERE       = 0x25,
 398     CPU_MODEL_WESTMERE_EP    = 0x2c,
 399     CPU_MODEL_WESTMERE_EX    = 0x2f,
 400     CPU_MODEL_SANDYBRIDGE    = 0x2a,
 401     CPU_MODEL_SANDYBRIDGE_EP = 0x2d,
 402     CPU_MODEL_IVYBRIDGE_EP   = 0x3a,
 403     CPU_MODEL_HASWELL_E3     = 0x3c,
 404     CPU_MODEL_HASWELL_E7     = 0x3f,
 405     CPU_MODEL_BROADWELL      = 0x3d,
 406     CPU_MODEL_SKYLAKE        = 0x55
 407   };
 408 
 409   // cpuid information block.  All info derived from executing cpuid with
 410   // various function numbers is stored here.  Intel and AMD info is
 411   // merged in this block: accessor methods disentangle it.
 412   //
 413   // The info block is laid out in subblocks of 4 dwords corresponding to
 414   // eax, ebx, ecx and edx, whether or not they contain anything useful.
 415   struct CpuidInfo {
 416     // cpuid function 0
 417     uint32_t std_max_function;
 418     uint32_t std_vendor_name_0;
 419     uint32_t std_vendor_name_1;
 420     uint32_t std_vendor_name_2;
 421 
 422     // cpuid function 1
 423     StdCpuid1Eax std_cpuid1_eax;
 424     StdCpuid1Ebx std_cpuid1_ebx;
 425     StdCpuid1Ecx std_cpuid1_ecx;
 426     StdCpuid1Edx std_cpuid1_edx;
 427 
 428     // cpuid function 4 (deterministic cache parameters)
 429     DcpCpuid4Eax dcp_cpuid4_eax;
 430     DcpCpuid4Ebx dcp_cpuid4_ebx;
 431     uint32_t     dcp_cpuid4_ecx; // unused currently
 432     uint32_t     dcp_cpuid4_edx; // unused currently
 433 
 434     // cpuid function 7 (structured extended features)
 435     SefCpuid7Eax sef_cpuid7_eax;
 436     SefCpuid7Ebx sef_cpuid7_ebx;
 437     SefCpuid7Ecx sef_cpuid7_ecx;
 438     SefCpuid7Edx sef_cpuid7_edx;
 439 
 440     // cpuid function 0xB (processor topology)
 441     // ecx = 0
 442     uint32_t     tpl_cpuidB0_eax;
 443     TplCpuidBEbx tpl_cpuidB0_ebx;
 444     uint32_t     tpl_cpuidB0_ecx; // unused currently
 445     uint32_t     tpl_cpuidB0_edx; // unused currently
 446 
 447     // ecx = 1
 448     uint32_t     tpl_cpuidB1_eax;
 449     TplCpuidBEbx tpl_cpuidB1_ebx;
 450     uint32_t     tpl_cpuidB1_ecx; // unused currently
 451     uint32_t     tpl_cpuidB1_edx; // unused currently
 452 
 453     // ecx = 2
 454     uint32_t     tpl_cpuidB2_eax;
 455     TplCpuidBEbx tpl_cpuidB2_ebx;
 456     uint32_t     tpl_cpuidB2_ecx; // unused currently
 457     uint32_t     tpl_cpuidB2_edx; // unused currently
 458 
 459     // cpuid function 0x80000000 // example, unused
 460     uint32_t ext_max_function;
 461     uint32_t ext_vendor_name_0;
 462     uint32_t ext_vendor_name_1;
 463     uint32_t ext_vendor_name_2;
 464 
 465     // cpuid function 0x80000001
 466     uint32_t     ext_cpuid1_eax; // reserved
 467     uint32_t     ext_cpuid1_ebx; // reserved
 468     ExtCpuid1Ecx ext_cpuid1_ecx;
 469     ExtCpuid1Edx ext_cpuid1_edx;
 470 
 471     // cpuid functions 0x80000002 thru 0x80000004: example, unused
 472     uint32_t proc_name_0, proc_name_1, proc_name_2, proc_name_3;
 473     uint32_t proc_name_4, proc_name_5, proc_name_6, proc_name_7;
 474     uint32_t proc_name_8, proc_name_9, proc_name_10,proc_name_11;
 475 
 476     // cpuid function 0x80000005 // AMD L1, Intel reserved
 477     uint32_t     ext_cpuid5_eax; // unused currently
 478     uint32_t     ext_cpuid5_ebx; // reserved
 479     ExtCpuid5Ex  ext_cpuid5_ecx; // L1 data cache info (AMD)
 480     ExtCpuid5Ex  ext_cpuid5_edx; // L1 instruction cache info (AMD)
 481 
 482     // cpuid function 0x80000007
 483     uint32_t     ext_cpuid7_eax; // reserved
 484     uint32_t     ext_cpuid7_ebx; // reserved
 485     uint32_t     ext_cpuid7_ecx; // reserved
 486     ExtCpuid7Edx ext_cpuid7_edx; // tscinv
 487 
 488     // cpuid function 0x80000008
 489     uint32_t     ext_cpuid8_eax; // unused currently
 490     uint32_t     ext_cpuid8_ebx; // reserved
 491     ExtCpuid8Ecx ext_cpuid8_ecx;
 492     uint32_t     ext_cpuid8_edx; // reserved
 493 
 494     // cpuid function 0x8000001E // AMD 17h
 495     uint32_t      ext_cpuid1E_eax;
 496     ExtCpuid1EEbx ext_cpuid1E_ebx; // threads per core (AMD17h)
 497     uint32_t      ext_cpuid1E_ecx;
 498     uint32_t      ext_cpuid1E_edx; // unused currently
 499 
 500     // extended control register XCR0 (the XFEATURE_ENABLED_MASK register)
 501     XemXcr0Eax   xem_xcr0_eax;
 502     uint32_t     xem_xcr0_edx; // reserved
 503 
 504     // Space to save ymm registers after signal handle
 505     int          ymm_save[8*4]; // Save ymm0, ymm7, ymm8, ymm15
 506 
 507     // Space to save zmm registers after signal handle
 508     int          zmm_save[16*4]; // Save zmm0, zmm7, zmm8, zmm31
 509   };
 510 
 511   // The actual cpuid info block
 512   static CpuidInfo _cpuid_info;
 513 
 514   // Extractors and predicates
 515   static uint32_t extended_cpu_family() {
 516     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.family;
 517     result += _cpuid_info.std_cpuid1_eax.bits.ext_family;
 518     return result;
 519   }
 520 
 521   static uint32_t extended_cpu_model() {
 522     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.model;
 523     result |= _cpuid_info.std_cpuid1_eax.bits.ext_model << 4;
 524     return result;
 525   }
 526 
 527   static uint32_t cpu_stepping() {
 528     uint32_t result = _cpuid_info.std_cpuid1_eax.bits.stepping;
 529     return result;
 530   }
 531 
 532   static uint logical_processor_count() {
 533     uint result = threads_per_core();
 534     return result;
 535   }
 536 
 537   static bool compute_has_intel_jcc_erratum();
 538 
 539   static uint64_t feature_flags() {
 540     uint64_t result = 0;
 541     if (_cpuid_info.std_cpuid1_edx.bits.cmpxchg8 != 0)
 542       result |= CPU_CX8;
 543     if (_cpuid_info.std_cpuid1_edx.bits.cmov != 0)
 544       result |= CPU_CMOV;
 545     if (_cpuid_info.std_cpuid1_edx.bits.clflush != 0)
 546       result |= CPU_FLUSH;
 547 #ifdef _LP64
 548     // clflush should always be available on x86_64
 549     // if not we are in real trouble because we rely on it
 550     // to flush the code cache.
 551     assert ((result & CPU_FLUSH) != 0, "clflush should be available");
 552 #endif
 553     if (_cpuid_info.std_cpuid1_edx.bits.fxsr != 0 || (is_amd_family() &&
 554         _cpuid_info.ext_cpuid1_edx.bits.fxsr != 0))
 555       result |= CPU_FXSR;
 556     // HT flag is set for multi-core processors also.
 557     if (threads_per_core() > 1)
 558       result |= CPU_HT;
 559     if (_cpuid_info.std_cpuid1_edx.bits.mmx != 0 || (is_amd_family() &&
 560         _cpuid_info.ext_cpuid1_edx.bits.mmx != 0))
 561       result |= CPU_MMX;
 562     if (_cpuid_info.std_cpuid1_edx.bits.sse != 0)
 563       result |= CPU_SSE;
 564     if (_cpuid_info.std_cpuid1_edx.bits.sse2 != 0)
 565       result |= CPU_SSE2;
 566     if (_cpuid_info.std_cpuid1_ecx.bits.sse3 != 0)
 567       result |= CPU_SSE3;
 568     if (_cpuid_info.std_cpuid1_ecx.bits.ssse3 != 0)
 569       result |= CPU_SSSE3;
 570     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_1 != 0)
 571       result |= CPU_SSE4_1;
 572     if (_cpuid_info.std_cpuid1_ecx.bits.sse4_2 != 0)
 573       result |= CPU_SSE4_2;
 574     if (_cpuid_info.std_cpuid1_ecx.bits.popcnt != 0)
 575       result |= CPU_POPCNT;
 576     if (_cpuid_info.std_cpuid1_ecx.bits.avx != 0 &&
 577         _cpuid_info.std_cpuid1_ecx.bits.osxsave != 0 &&
 578         _cpuid_info.xem_xcr0_eax.bits.sse != 0 &&
 579         _cpuid_info.xem_xcr0_eax.bits.ymm != 0) {
 580       result |= CPU_AVX;
 581       result |= CPU_VZEROUPPER;
 582       if (_cpuid_info.sef_cpuid7_ebx.bits.avx2 != 0)
 583         result |= CPU_AVX2;
 584       if (_cpuid_info.sef_cpuid7_ebx.bits.avx512f != 0 &&
 585           _cpuid_info.xem_xcr0_eax.bits.opmask != 0 &&
 586           _cpuid_info.xem_xcr0_eax.bits.zmm512 != 0 &&
 587           _cpuid_info.xem_xcr0_eax.bits.zmm32 != 0) {
 588         result |= CPU_AVX512F;
 589         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512cd != 0)
 590           result |= CPU_AVX512CD;
 591         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512dq != 0)
 592           result |= CPU_AVX512DQ;
 593         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512pf != 0)
 594           result |= CPU_AVX512PF;
 595         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512er != 0)
 596           result |= CPU_AVX512ER;
 597         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512bw != 0)
 598           result |= CPU_AVX512BW;
 599         if (_cpuid_info.sef_cpuid7_ebx.bits.avx512vl != 0)
 600           result |= CPU_AVX512VL;
 601         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpopcntdq != 0)
 602           result |= CPU_AVX512_VPOPCNTDQ;
 603         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vpclmulqdq != 0)
 604           result |= CPU_AVX512_VPCLMULQDQ;
 605         if (_cpuid_info.sef_cpuid7_ecx.bits.vaes != 0)
 606           result |= CPU_AVX512_VAES;
 607         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 608           result |= CPU_AVX512_VNNI;
 609         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
 610           result |= CPU_AVX512_VBMI;
 611         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
 612           result |= CPU_AVX512_VBMI2;
 613       }
 614     }
 615     if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
 616       result |= CPU_HV;
 617     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 618       result |= CPU_BMI1;
 619     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 620       result |= CPU_TSC;
 621     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 622       result |= CPU_TSCINV_BIT;
 623     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 624       result |= CPU_AES;
 625     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 626       result |= CPU_ERMS;
 627     if (_cpuid_info.sef_cpuid7_edx.bits.fast_short_rep_mov != 0)
 628       result |= CPU_FSRM;
 629     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 630       result |= CPU_CLMUL;
 631     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 632       result |= CPU_RTM;
 633     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 634        result |= CPU_ADX;
 635     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 636       result |= CPU_BMI2;
 637     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 638       result |= CPU_SHA;
 639     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 640       result |= CPU_FMA;
 641     if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
 642       result |= CPU_FLUSHOPT;
 643     if (_cpuid_info.ext_cpuid1_edx.bits.rdtscp != 0)
 644       result |= CPU_RDTSCP;
 645     if (_cpuid_info.sef_cpuid7_ecx.bits.rdpid != 0)
 646       result |= CPU_RDPID;
 647 
 648     // AMD|Hygon features.
 649     if (is_amd_family()) {
 650       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 651           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 652         result |= CPU_3DNOW_PREFETCH;
 653       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 654         result |= CPU_LZCNT;
 655       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 656         result |= CPU_SSE4A;
 657     }
 658 
 659     // Intel features.
 660     if (is_intel()) {
 661       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 662         result |= CPU_LZCNT;
 663       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 664       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 665         result |= CPU_3DNOW_PREFETCH;
 666       }
 667       if (_cpuid_info.sef_cpuid7_ebx.bits.clwb != 0) {
 668         result |= CPU_CLWB;
 669       }
 670       if (_cpuid_info.sef_cpuid7_edx.bits.serialize != 0)
 671         result |= CPU_SERIALIZE;
 672     }
 673 
 674     // ZX features.
 675     if (is_zx()) {
 676       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 677         result |= CPU_LZCNT;
 678       // for ZX, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 679       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 680         result |= CPU_3DNOW_PREFETCH;
 681       }
 682     }
 683 
 684     // Composite features.
 685     if (supports_tscinv_bit() &&
 686         ((is_amd_family() && !is_amd_Barcelona()) ||
 687          is_intel_tsc_synched_at_init())) {
 688       result |= CPU_TSCINV;
 689     }
 690 
 691     return result;
 692   }
 693 
 694   static bool os_supports_avx_vectors() {
 695     bool retVal = false;
 696     int nreg = 2 LP64_ONLY(+2);
 697     if (supports_evex()) {
 698       // Verify that OS save/restore all bits of EVEX registers
 699       // during signal processing.
 700       retVal = true;
 701       for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 702         if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 703           retVal = false;
 704           break;
 705         }
 706       }
 707     } else if (supports_avx()) {
 708       // Verify that OS save/restore all bits of AVX registers
 709       // during signal processing.
 710       retVal = true;
 711       for (int i = 0; i < 8 * nreg; i++) { // 32 bytes per ymm register
 712         if (_cpuid_info.ymm_save[i] != ymm_test_value()) {
 713           retVal = false;
 714           break;
 715         }
 716       }
 717       // zmm_save will be set on a EVEX enabled machine even if we choose AVX code gen
 718       if (retVal == false) {
 719         // Verify that OS save/restore all bits of EVEX registers
 720         // during signal processing.
 721         retVal = true;
 722         for (int i = 0; i < 16 * nreg; i++) { // 64 bytes per zmm register
 723           if (_cpuid_info.zmm_save[i] != ymm_test_value()) {
 724             retVal = false;
 725             break;
 726           }
 727         }
 728       }
 729     }
 730     return retVal;
 731   }
 732 
 733   static void get_processor_features();
 734 
 735 public:
 736   // Offsets for cpuid asm stub
 737   static ByteSize std_cpuid0_offset() { return byte_offset_of(CpuidInfo, std_max_function); }
 738   static ByteSize std_cpuid1_offset() { return byte_offset_of(CpuidInfo, std_cpuid1_eax); }
 739   static ByteSize dcp_cpuid4_offset() { return byte_offset_of(CpuidInfo, dcp_cpuid4_eax); }
 740   static ByteSize sef_cpuid7_offset() { return byte_offset_of(CpuidInfo, sef_cpuid7_eax); }
 741   static ByteSize ext_cpuid1_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1_eax); }
 742   static ByteSize ext_cpuid5_offset() { return byte_offset_of(CpuidInfo, ext_cpuid5_eax); }
 743   static ByteSize ext_cpuid7_offset() { return byte_offset_of(CpuidInfo, ext_cpuid7_eax); }
 744   static ByteSize ext_cpuid8_offset() { return byte_offset_of(CpuidInfo, ext_cpuid8_eax); }
 745   static ByteSize ext_cpuid1E_offset() { return byte_offset_of(CpuidInfo, ext_cpuid1E_eax); }
 746   static ByteSize tpl_cpuidB0_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB0_eax); }
 747   static ByteSize tpl_cpuidB1_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB1_eax); }
 748   static ByteSize tpl_cpuidB2_offset() { return byte_offset_of(CpuidInfo, tpl_cpuidB2_eax); }
 749   static ByteSize xem_xcr0_offset() { return byte_offset_of(CpuidInfo, xem_xcr0_eax); }
 750   static ByteSize ymm_save_offset() { return byte_offset_of(CpuidInfo, ymm_save); }
 751   static ByteSize zmm_save_offset() { return byte_offset_of(CpuidInfo, zmm_save); }
 752 
 753   // The value used to check ymm register after signal handle
 754   static int ymm_test_value()    { return 0xCAFEBABE; }
 755 
 756   static void get_cpu_info_wrapper();
 757   static void set_cpuinfo_segv_addr(address pc) { _cpuinfo_segv_addr = pc; }
 758   static bool  is_cpuinfo_segv_addr(address pc) { return _cpuinfo_segv_addr == pc; }
 759   static void set_cpuinfo_cont_addr(address pc) { _cpuinfo_cont_addr = pc; }
 760   static address  cpuinfo_cont_addr()           { return _cpuinfo_cont_addr; }
 761 
 762   static void clean_cpuFeatures()   { _features = 0; }
 763   static void set_avx_cpuFeatures() { _features = (CPU_SSE | CPU_SSE2 | CPU_AVX | CPU_VZEROUPPER ); }
 764   static void set_evex_cpuFeatures() { _features = (CPU_AVX512F | CPU_SSE | CPU_SSE2 | CPU_VZEROUPPER ); }
 765 
 766 
 767   // Initialization
 768   static void initialize();
 769 
 770   // Override Abstract_VM_Version implementation
 771   static void print_platform_virtualization_info(outputStream*);
 772 
 773   // Asserts
 774   static void assert_is_initialized() {
 775     assert(_cpuid_info.std_cpuid1_eax.bits.family != 0, "VM_Version not initialized");
 776   }
 777 
 778   //
 779   // Processor family:
 780   //       3   -  386
 781   //       4   -  486
 782   //       5   -  Pentium
 783   //       6   -  PentiumPro, Pentium II, Celeron, Xeon, Pentium III, Athlon,
 784   //              Pentium M, Core Solo, Core Duo, Core2 Duo
 785   //    family 6 model:   9,        13,       14,        15
 786   //    0x0f   -  Pentium 4, Opteron
 787   //
 788   // Note: The cpu family should be used to select between
 789   //       instruction sequences which are valid on all Intel
 790   //       processors.  Use the feature test functions below to
 791   //       determine whether a particular instruction is supported.
 792   //
 793   static int  cpu_family()        { return _cpu;}
 794   static bool is_P6()             { return cpu_family() >= 6; }
 795   static bool is_amd()            { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x68747541; } // 'htuA'
 796   static bool is_hygon()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x6F677948; } // 'ogyH'
 797   static bool is_amd_family()     { return is_amd() || is_hygon(); }
 798   static bool is_intel()          { assert_is_initialized(); return _cpuid_info.std_vendor_name_0 == 0x756e6547; } // 'uneG'
 799   static bool is_zx()             { assert_is_initialized(); return (_cpuid_info.std_vendor_name_0 == 0x746e6543) || (_cpuid_info.std_vendor_name_0 == 0x68532020); } // 'tneC'||'hS  '
 800   static bool is_atom_family()    { return ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x36) || (extended_cpu_model() == 0x37) || (extended_cpu_model() == 0x4D))); } //Silvermont and Centerton
 801   static bool is_knights_family() { return UseKNLSetting || ((cpu_family() == 0x06) && ((extended_cpu_model() == 0x57) || (extended_cpu_model() == 0x85))); } // Xeon Phi 3200/5200/7200 and Future Xeon Phi
 802 
 803   static bool supports_processor_topology() {
 804     return (_cpuid_info.std_max_function >= 0xB) &&
 805            // eax[4:0] | ebx[0:15] == 0 indicates invalid topology level.
 806            // Some cpus have max cpuid >= 0xB but do not support processor topology.
 807            (((_cpuid_info.tpl_cpuidB0_eax & 0x1f) | _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus) != 0);
 808   }
 809 
 810   static uint cores_per_cpu()  {
 811     uint result = 1;
 812     if (is_intel()) {
 813       bool supports_topology = supports_processor_topology();
 814       if (supports_topology) {
 815         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 816                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 817       }
 818       if (!supports_topology || result == 0) {
 819         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 820       }
 821     } else if (is_amd_family()) {
 822       result = (_cpuid_info.ext_cpuid8_ecx.bits.cores_per_cpu + 1);
 823     } else if (is_zx()) {
 824       bool supports_topology = supports_processor_topology();
 825       if (supports_topology) {
 826         result = _cpuid_info.tpl_cpuidB1_ebx.bits.logical_cpus /
 827                  _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 828       }
 829       if (!supports_topology || result == 0) {
 830         result = (_cpuid_info.dcp_cpuid4_eax.bits.cores_per_cpu + 1);
 831       }
 832     }
 833     return result;
 834   }
 835 
 836   static uint threads_per_core()  {
 837     uint result = 1;
 838     if (is_intel() && supports_processor_topology()) {
 839       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 840     } else if (is_zx() && supports_processor_topology()) {
 841       result = _cpuid_info.tpl_cpuidB0_ebx.bits.logical_cpus;
 842     } else if (_cpuid_info.std_cpuid1_edx.bits.ht != 0) {
 843       if (cpu_family() >= 0x17) {
 844         result = _cpuid_info.ext_cpuid1E_ebx.bits.threads_per_core + 1;
 845       } else {
 846         result = _cpuid_info.std_cpuid1_ebx.bits.threads_per_cpu /
 847                  cores_per_cpu();
 848       }
 849     }
 850     return (result == 0 ? 1 : result);
 851   }
 852 
 853   static intx L1_line_size()  {
 854     intx result = 0;
 855     if (is_intel()) {
 856       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 857     } else if (is_amd_family()) {
 858       result = _cpuid_info.ext_cpuid5_ecx.bits.L1_line_size;
 859     } else if (is_zx()) {
 860       result = (_cpuid_info.dcp_cpuid4_ebx.bits.L1_line_size + 1);
 861     }
 862     if (result < 32) // not defined ?
 863       result = 32;   // 32 bytes by default on x86 and other x64
 864     return result;
 865   }
 866 
 867   static intx prefetch_data_size()  {
 868     return L1_line_size();
 869   }
 870 
 871   //
 872   // Feature identification
 873   //
 874   static bool supports_cpuid()        { return _features  != 0; }
 875   static bool supports_cmpxchg8()     { return (_features & CPU_CX8) != 0; }
 876   static bool supports_cmov()         { return (_features & CPU_CMOV) != 0; }
 877   static bool supports_fxsr()         { return (_features & CPU_FXSR) != 0; }
 878   static bool supports_ht()           { return (_features & CPU_HT) != 0; }
 879   static bool supports_mmx()          { return (_features & CPU_MMX) != 0; }
 880   static bool supports_sse()          { return (_features & CPU_SSE) != 0; }
 881   static bool supports_sse2()         { return (_features & CPU_SSE2) != 0; }
 882   static bool supports_sse3()         { return (_features & CPU_SSE3) != 0; }
 883   static bool supports_ssse3()        { return (_features & CPU_SSSE3)!= 0; }
 884   static bool supports_sse4_1()       { return (_features & CPU_SSE4_1) != 0; }
 885   static bool supports_sse4_2()       { return (_features & CPU_SSE4_2) != 0; }
 886   static bool supports_popcnt()       { return (_features & CPU_POPCNT) != 0; }
 887   static bool supports_avx()          { return (_features & CPU_AVX) != 0; }
 888   static bool supports_avx2()         { return (_features & CPU_AVX2) != 0; }
 889   static bool supports_tsc()          { return (_features & CPU_TSC) != 0; }
 890   static bool supports_rdtscp()       { return (_features & CPU_RDTSCP) != 0; }
 891   static bool supports_rdpid()        { return (_features & CPU_RDPID) != 0; }
 892   static bool supports_aes()          { return (_features & CPU_AES) != 0; }
 893   static bool supports_erms()         { return (_features & CPU_ERMS) != 0; }
 894   static bool supports_fsrm()         { return (_features & CPU_FSRM) != 0; }
 895   static bool supports_clmul()        { return (_features & CPU_CLMUL) != 0; }
 896   static bool supports_rtm()          { return (_features & CPU_RTM) != 0; }
 897   static bool supports_bmi1()         { return (_features & CPU_BMI1) != 0; }
 898   static bool supports_bmi2()         { return (_features & CPU_BMI2) != 0; }
 899   static bool supports_adx()          { return (_features & CPU_ADX) != 0; }
 900   static bool supports_evex()         { return (_features & CPU_AVX512F) != 0; }
 901   static bool supports_avx512dq()     { return (_features & CPU_AVX512DQ) != 0; }
 902   static bool supports_avx512pf()     { return (_features & CPU_AVX512PF) != 0; }
 903   static bool supports_avx512er()     { return (_features & CPU_AVX512ER) != 0; }
 904   static bool supports_avx512cd()     { return (_features & CPU_AVX512CD) != 0; }
 905   static bool supports_avx512bw()     { return (_features & CPU_AVX512BW) != 0; }
 906   static bool supports_avx512vl()     { return (_features & CPU_AVX512VL) != 0; }
 907   static bool supports_avx512vlbw()   { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
 908   static bool supports_avx512bwdq()   { return (supports_evex() && supports_avx512bw() && supports_avx512dq()); }
 909   static bool supports_avx512vldq()   { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
 910   static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
 911                                                 supports_avx512bw() && supports_avx512dq()); }
 912   static bool supports_avx512novl()   { return (supports_evex() && !supports_avx512vl()); }
 913   static bool supports_avx512nobw()   { return (supports_evex() && !supports_avx512bw()); }
 914   static bool supports_avx256only()   { return (supports_avx2() && !supports_evex()); }
 915   static bool supports_avxonly()      { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
 916   static bool supports_sha()          { return (_features & CPU_SHA) != 0; }
 917   static bool supports_fma()          { return (_features & CPU_FMA) != 0 && supports_avx(); }
 918   static bool supports_vzeroupper()   { return (_features & CPU_VZEROUPPER) != 0; }
 919   static bool supports_avx512_vpopcntdq()  { return (_features & CPU_AVX512_VPOPCNTDQ) != 0; }
 920   static bool supports_avx512_vpclmulqdq() { return (_features & CPU_AVX512_VPCLMULQDQ) != 0; }
 921   static bool supports_avx512_vaes()  { return (_features & CPU_AVX512_VAES) != 0; }
 922   static bool supports_avx512_vnni()  { return (_features & CPU_AVX512_VNNI) != 0; }
 923   static bool supports_avx512_vbmi()  { return (_features & CPU_AVX512_VBMI) != 0; }
 924   static bool supports_avx512_vbmi2() { return (_features & CPU_AVX512_VBMI2) != 0; }
 925   static bool supports_hv()           { return (_features & CPU_HV) != 0; }
 926   static bool supports_serialize()    { return (_features & CPU_SERIALIZE) != 0; }
 927 
 928   // Intel features
 929   static bool is_intel_family_core() { return is_intel() &&
 930                                        extended_cpu_family() == CPU_FAMILY_INTEL_CORE; }
 931 
 932   static bool is_intel_skylake() { return is_intel_family_core() &&
 933                                           extended_cpu_model() == CPU_MODEL_SKYLAKE; }
 934 
 935   static bool is_intel_tsc_synched_at_init()  {
 936     if (is_intel_family_core()) {
 937       uint32_t ext_model = extended_cpu_model();
 938       if (ext_model == CPU_MODEL_NEHALEM_EP     ||
 939           ext_model == CPU_MODEL_WESTMERE_EP    ||
 940           ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
 941           ext_model == CPU_MODEL_IVYBRIDGE_EP) {
 942         // <= 2-socket invariant tsc support. EX versions are usually used
 943         // in > 2-socket systems and likely don't synchronize tscs at
 944         // initialization.
 945         // Code that uses tsc values must be prepared for them to arbitrarily
 946         // jump forward or backward.
 947         return true;
 948       }
 949     }
 950     return false;
 951   }
 952 
 953   // This checks if the JVM is potentially affected by an erratum on Intel CPUs (SKX102)
 954   // that causes unpredictable behaviour when jcc crosses 64 byte boundaries. Its microcode
 955   // mitigation causes regressions when jumps or fused conditional branches cross or end at
 956   // 32 byte boundaries.
 957   static bool has_intel_jcc_erratum() { return _has_intel_jcc_erratum; }
 958 
 959   // AMD features
 960   static bool supports_3dnow_prefetch()    { return (_features & CPU_3DNOW_PREFETCH) != 0; }
 961   static bool supports_lzcnt()    { return (_features & CPU_LZCNT) != 0; }
 962   static bool supports_sse4a()    { return (_features & CPU_SSE4A) != 0; }
 963 
 964   static bool is_amd_Barcelona()  { return is_amd() &&
 965                                            extended_cpu_family() == CPU_FAMILY_AMD_11H; }
 966 
 967   // Intel and AMD newer cores support fast timestamps well
 968   static bool supports_tscinv_bit() {
 969     return (_features & CPU_TSCINV_BIT) != 0;
 970   }
 971   static bool supports_tscinv() {
 972     return (_features & CPU_TSCINV) != 0;
 973   }
 974 
 975   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
 976   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
 977                                            supports_sse3() && _model != 0x1C; }
 978 
 979   static bool supports_compare_and_exchange() { return true; }
 980 
 981   static intx allocate_prefetch_distance(bool use_watermark_prefetch) {
 982     // Hardware prefetching (distance/size in bytes):
 983     // Pentium 3 -  64 /  32
 984     // Pentium 4 - 256 / 128
 985     // Athlon    -  64 /  32 ????
 986     // Opteron   - 128 /  64 only when 2 sequential cache lines accessed
 987     // Core      - 128 /  64
 988     //
 989     // Software prefetching (distance in bytes / instruction with best score):
 990     // Pentium 3 - 128 / prefetchnta
 991     // Pentium 4 - 512 / prefetchnta
 992     // Athlon    - 128 / prefetchnta
 993     // Opteron   - 256 / prefetchnta
 994     // Core      - 256 / prefetchnta
 995     // It will be used only when AllocatePrefetchStyle > 0
 996 
 997     if (is_amd_family()) { // AMD | Hygon
 998       if (supports_sse2()) {
 999         return 256; // Opteron
1000       } else {
1001         return 128; // Athlon
1002       }
1003     } else { // Intel
1004       if (supports_sse3() && cpu_family() == 6) {
1005         if (supports_sse4_2() && supports_ht()) { // Nehalem based cpus
1006           return 192;
1007         } else if (use_watermark_prefetch) { // watermark prefetching on Core
1008 #ifdef _LP64
1009           return 384;
1010 #else
1011           return 320;
1012 #endif
1013         }
1014       }
1015       if (supports_sse2()) {
1016         if (cpu_family() == 6) {
1017           return 256; // Pentium M, Core, Core2
1018         } else {
1019           return 512; // Pentium 4
1020         }
1021       } else {
1022         return 128; // Pentium 3 (and all other old CPUs)
1023       }
1024     }
1025   }
1026 
1027   // SSE2 and later processors implement a 'pause' instruction
1028   // that can be used for efficient implementation of
1029   // the intrinsic for java.lang.Thread.onSpinWait()
1030   static bool supports_on_spin_wait() { return supports_sse2(); }
1031 
1032   // x86_64 supports fast class initialization checks for static methods.
1033   static bool supports_fast_class_init_checks() {
1034     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
1035   }
1036 
1037   constexpr static bool supports_stack_watermark_barrier() {
1038     return true;
1039   }
1040 
1041   // there are several insns to force cache line sync to memory which
1042   // we can use to ensure mapped non-volatile memory is up to date with
1043   // pending in-cache changes.
1044   //
1045   // 64 bit cpus always support clflush which writes back and evicts
1046   // on 32 bit cpus support is recorded via a feature flag
1047   //
1048   // clflushopt is optional and acts like clflush except it does
1049   // not synchronize with other memory ops. it needs a preceding
1050   // and trailing StoreStore fence
1051   //
1052   // clwb is an optional intel-specific instruction which
1053   // writes back without evicting the line. it also does not
1054   // synchronize with other memory ops. so, it needs preceding
1055   // and trailing StoreStore fences.
1056 
1057 #ifdef _LP64
1058 
1059   static bool supports_clflush(); // Can't inline due to header file conflict
1060 #else
1061   static bool supports_clflush() { return  ((_features & CPU_FLUSH) != 0); }
1062 #endif // _LP64
1063   // Note: CPU_FLUSHOPT and CPU_CLWB bits should always be zero for 32-bit
1064   static bool supports_clflushopt() { return ((_features & CPU_FLUSHOPT) != 0); }
1065   static bool supports_clwb() { return ((_features & CPU_CLWB) != 0); }
1066 
1067 #ifdef __APPLE__
1068   // Is the CPU running emulated (for example macOS Rosetta running x86_64 code on M1 ARM (aarch64)
1069   static bool is_cpu_emulated();
1070 #endif
1071 
1072   // support functions for virtualization detection
1073  private:
1074   static void check_virtualizations();
1075 };
1076 
1077 #endif // CPU_X86_VM_VERSION_X86_HPP
--- EOF ---