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src/hotspot/cpu/x86/vm_version_x86.hpp

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749   }
750 
751   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
752   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
753                                            supports_sse3() && _model != 0x1C; }
754 
755   static bool supports_compare_and_exchange() { return true; }
756 
757   static int allocate_prefetch_distance(bool use_watermark_prefetch);
758 
759   // SSE2 and later processors implement a 'pause' instruction
760   // that can be used for efficient implementation of
761   // the intrinsic for java.lang.Thread.onSpinWait()
762   static bool supports_on_spin_wait() { return supports_sse2(); }
763 
764   // x86_64 supports fast class initialization checks
765   static bool supports_fast_class_init_checks() {
766     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
767   }
768 


769   constexpr static bool supports_stack_watermark_barrier() {
770     return true;
771   }
772 
773   // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
774   static bool supports_float16() {
775     return supports_f16c() || supports_avx512vl();
776   }
777 
778   // Check intrinsic support
779   static bool is_intrinsic_supported(vmIntrinsicID id);
780 
781   // there are several insns to force cache line sync to memory which
782   // we can use to ensure mapped non-volatile memory is up to date with
783   // pending in-cache changes.
784   //
785   // 64 bit cpus always support clflush which writes back and evicts
786   // on 32 bit cpus support is recorded via a feature flag
787   //
788   // clflushopt is optional and acts like clflush except it does

749   }
750 
751   // Intel Core and newer cpus have fast IDIV instruction (excluding Atom).
752   static bool has_fast_idiv()     { return is_intel() && cpu_family() == 6 &&
753                                            supports_sse3() && _model != 0x1C; }
754 
755   static bool supports_compare_and_exchange() { return true; }
756 
757   static int allocate_prefetch_distance(bool use_watermark_prefetch);
758 
759   // SSE2 and later processors implement a 'pause' instruction
760   // that can be used for efficient implementation of
761   // the intrinsic for java.lang.Thread.onSpinWait()
762   static bool supports_on_spin_wait() { return supports_sse2(); }
763 
764   // x86_64 supports fast class initialization checks
765   static bool supports_fast_class_init_checks() {
766     return LP64_ONLY(true) NOT_LP64(false); // not implemented on x86_32
767   }
768 
769   static bool supports_cont_preemption() { return true; }
770 
771   constexpr static bool supports_stack_watermark_barrier() {
772     return true;
773   }
774 
775   // For AVX CPUs only. f16c support is disabled if UseAVX == 0.
776   static bool supports_float16() {
777     return supports_f16c() || supports_avx512vl();
778   }
779 
780   // Check intrinsic support
781   static bool is_intrinsic_supported(vmIntrinsicID id);
782 
783   // there are several insns to force cache line sync to memory which
784   // we can use to ensure mapped non-volatile memory is up to date with
785   // pending in-cache changes.
786   //
787   // 64 bit cpus always support clflush which writes back and evicts
788   // on 32 bit cpus support is recorded via a feature flag
789   //
790   // clflushopt is optional and acts like clflush except it does
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