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src/hotspot/cpu/x86/vm_version_x86.hpp

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 147     struct {
 148       uint32_t LahfSahf     : 1,
 149                CmpLegacy    : 1,
 150                             : 3,
 151                lzcnt_intel  : 1,
 152                lzcnt        : 1,
 153                sse4a        : 1,
 154                misalignsse  : 1,
 155                prefetchw    : 1,
 156                             : 22;
 157     } bits;
 158   };
 159 
 160   union ExtCpuid1Edx {
 161     uint32_t value;
 162     struct {
 163       uint32_t           : 22,
 164                mmx_amd   : 1,
 165                mmx       : 1,
 166                fxsr      : 1,
 167                          : 4,



 168                long_mode : 1,
 169                tdnow2    : 1,
 170                tdnow     : 1;
 171     } bits;
 172   };
 173 
 174   union ExtCpuid5Ex {
 175     uint32_t value;
 176     struct {
 177       uint32_t L1_line_size : 8,
 178                L1_tag_lines : 8,
 179                L1_assoc     : 8,
 180                L1_size      : 8;
 181     } bits;
 182   };
 183 
 184   union ExtCpuid7Edx {
 185     uint32_t value;
 186     struct {
 187       uint32_t               : 8,

 234   };
 235 
 236   union SefCpuid7Ecx {
 237     uint32_t value;
 238     struct {
 239       uint32_t prefetchwt1 : 1,
 240                avx512_vbmi : 1,
 241                       umip : 1,
 242                        pku : 1,
 243                      ospke : 1,
 244                            : 1,
 245               avx512_vbmi2 : 1,
 246                            : 1,
 247                       gfni : 1,
 248                       vaes : 1,
 249          avx512_vpclmulqdq : 1,
 250                avx512_vnni : 1,
 251              avx512_bitalg : 1,
 252                            : 1,
 253           avx512_vpopcntdq : 1,
 254                            : 17;




 255     } bits;
 256   };
 257 
 258   union SefCpuid7Edx {
 259     uint32_t value;
 260     struct {
 261       uint32_t             : 2,
 262              avx512_4vnniw : 1,
 263              avx512_4fmaps : 1,
 264                            : 10,

 265                  serialize : 1,
 266                            : 17;
 267     } bits;
 268   };
 269 
 270   union ExtCpuid1EEbx {
 271     uint32_t value;
 272     struct {
 273       uint32_t                  : 8,
 274                threads_per_core : 8,
 275                                 : 16;
 276     } bits;
 277   };
 278 
 279   union XemXcr0Eax {
 280     uint32_t value;
 281     struct {
 282       uint32_t x87     : 1,
 283                sse     : 1,
 284                ymm     : 1,

 345     decl(AVX512CD,          "avx512cd",          31) \
 346                                                      \
 347     decl(AVX512BW,          "avx512bw",          32) /* Byte and word vector instructions */ \
 348     decl(AVX512VL,          "avx512vl",          33) /* EVEX instructions with smaller vector length */ \
 349     decl(SHA,               "sha",               34) /* SHA instructions */ \
 350     decl(FMA,               "fma",               35) /* FMA instructions */ \
 351                                                      \
 352     decl(VZEROUPPER,        "vzeroupper",        36) /* Vzeroupper instruction */ \
 353     decl(AVX512_VPOPCNTDQ,  "avx512_vpopcntdq",  37) /* Vector popcount */ \
 354     decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
 355     decl(AVX512_VAES,       "avx512_vaes",       39) /* Vector AES instruction */ \
 356                                                      \
 357     decl(AVX512_VNNI,       "avx512_vnni",       40) /* Vector Neural Network Instructions */ \
 358     decl(FLUSH,             "clflush",           41) /* flush instruction */ \
 359     decl(FLUSHOPT,          "clflushopt",        42) /* flusopth instruction */ \
 360     decl(CLWB,              "clwb",              43) /* clwb instruction */ \
 361                                                      \
 362     decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
 363     decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
 364     decl(HV,                "hv",                46) /* Hypervisor instructions */ \
 365     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */




 366 
 367 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
 368     CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
 369 #undef DECLARE_CPU_FEATURE_FLAG
 370   };
 371 
 372   static const char* _features_names[];
 373 
 374 enum Extended_Family {
 375     // AMD
 376     CPU_FAMILY_AMD_11H       = 0x11,
 377     // ZX
 378     CPU_FAMILY_ZX_CORE_F6    = 6,
 379     CPU_FAMILY_ZX_CORE_F7    = 7,
 380     // Intel
 381     CPU_FAMILY_INTEL_CORE    = 6,
 382     CPU_MODEL_NEHALEM        = 0x1e,
 383     CPU_MODEL_NEHALEM_EP     = 0x1a,
 384     CPU_MODEL_NEHALEM_EX     = 0x2e,
 385     CPU_MODEL_WESTMERE       = 0x25,

 595         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 596           result |= CPU_AVX512_VNNI;
 597         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
 598           result |= CPU_AVX512_VBMI;
 599         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
 600           result |= CPU_AVX512_VBMI2;
 601       }
 602     }
 603     if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
 604       result |= CPU_HV;
 605     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 606       result |= CPU_BMI1;
 607     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 608       result |= CPU_TSC;
 609     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 610       result |= CPU_TSCINV_BIT;
 611     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 612       result |= CPU_AES;
 613     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 614       result |= CPU_ERMS;


 615     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 616       result |= CPU_CLMUL;
 617     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 618       result |= CPU_RTM;
 619     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 620        result |= CPU_ADX;
 621     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 622       result |= CPU_BMI2;
 623     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 624       result |= CPU_SHA;
 625     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 626       result |= CPU_FMA;
 627     if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
 628       result |= CPU_FLUSHOPT;




 629 
 630     // AMD|Hygon features.
 631     if (is_amd_family()) {
 632       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 633           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 634         result |= CPU_3DNOW_PREFETCH;
 635       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 636         result |= CPU_LZCNT;
 637       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 638         result |= CPU_SSE4A;
 639     }
 640 
 641     // Intel features.
 642     if (is_intel()) {
 643       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 644         result |= CPU_LZCNT;
 645       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 646       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 647         result |= CPU_3DNOW_PREFETCH;
 648       }

 852 
 853   //
 854   // Feature identification
 855   //
 856   static bool supports_cpuid()        { return _features  != 0; }
 857   static bool supports_cmpxchg8()     { return (_features & CPU_CX8) != 0; }
 858   static bool supports_cmov()         { return (_features & CPU_CMOV) != 0; }
 859   static bool supports_fxsr()         { return (_features & CPU_FXSR) != 0; }
 860   static bool supports_ht()           { return (_features & CPU_HT) != 0; }
 861   static bool supports_mmx()          { return (_features & CPU_MMX) != 0; }
 862   static bool supports_sse()          { return (_features & CPU_SSE) != 0; }
 863   static bool supports_sse2()         { return (_features & CPU_SSE2) != 0; }
 864   static bool supports_sse3()         { return (_features & CPU_SSE3) != 0; }
 865   static bool supports_ssse3()        { return (_features & CPU_SSSE3)!= 0; }
 866   static bool supports_sse4_1()       { return (_features & CPU_SSE4_1) != 0; }
 867   static bool supports_sse4_2()       { return (_features & CPU_SSE4_2) != 0; }
 868   static bool supports_popcnt()       { return (_features & CPU_POPCNT) != 0; }
 869   static bool supports_avx()          { return (_features & CPU_AVX) != 0; }
 870   static bool supports_avx2()         { return (_features & CPU_AVX2) != 0; }
 871   static bool supports_tsc()          { return (_features & CPU_TSC) != 0; }


 872   static bool supports_aes()          { return (_features & CPU_AES) != 0; }
 873   static bool supports_erms()         { return (_features & CPU_ERMS) != 0; }

 874   static bool supports_clmul()        { return (_features & CPU_CLMUL) != 0; }
 875   static bool supports_rtm()          { return (_features & CPU_RTM) != 0; }
 876   static bool supports_bmi1()         { return (_features & CPU_BMI1) != 0; }
 877   static bool supports_bmi2()         { return (_features & CPU_BMI2) != 0; }
 878   static bool supports_adx()          { return (_features & CPU_ADX) != 0; }
 879   static bool supports_evex()         { return (_features & CPU_AVX512F) != 0; }
 880   static bool supports_avx512dq()     { return (_features & CPU_AVX512DQ) != 0; }
 881   static bool supports_avx512pf()     { return (_features & CPU_AVX512PF) != 0; }
 882   static bool supports_avx512er()     { return (_features & CPU_AVX512ER) != 0; }
 883   static bool supports_avx512cd()     { return (_features & CPU_AVX512CD) != 0; }
 884   static bool supports_avx512bw()     { return (_features & CPU_AVX512BW) != 0; }
 885   static bool supports_avx512vl()     { return (_features & CPU_AVX512VL) != 0; }
 886   static bool supports_avx512vlbw()   { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
 887   static bool supports_avx512vldq()   { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
 888   static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
 889                                                 supports_avx512bw() && supports_avx512dq()); }
 890   static bool supports_avx512novl()   { return (supports_evex() && !supports_avx512vl()); }
 891   static bool supports_avx512nobw()   { return (supports_evex() && !supports_avx512bw()); }
 892   static bool supports_avx256only()   { return (supports_avx2() && !supports_evex()); }
 893   static bool supports_avxonly()      { return ((supports_avx2() || supports_avx()) && !supports_evex()); }

 147     struct {
 148       uint32_t LahfSahf     : 1,
 149                CmpLegacy    : 1,
 150                             : 3,
 151                lzcnt_intel  : 1,
 152                lzcnt        : 1,
 153                sse4a        : 1,
 154                misalignsse  : 1,
 155                prefetchw    : 1,
 156                             : 22;
 157     } bits;
 158   };
 159 
 160   union ExtCpuid1Edx {
 161     uint32_t value;
 162     struct {
 163       uint32_t           : 22,
 164                mmx_amd   : 1,
 165                mmx       : 1,
 166                fxsr      : 1,
 167                fxsr_opt  : 1,
 168                pdpe1gb   : 1,
 169                rdtscp    : 1,
 170                          : 1,
 171                long_mode : 1,
 172                tdnow2    : 1,
 173                tdnow     : 1;
 174     } bits;
 175   };
 176 
 177   union ExtCpuid5Ex {
 178     uint32_t value;
 179     struct {
 180       uint32_t L1_line_size : 8,
 181                L1_tag_lines : 8,
 182                L1_assoc     : 8,
 183                L1_size      : 8;
 184     } bits;
 185   };
 186 
 187   union ExtCpuid7Edx {
 188     uint32_t value;
 189     struct {
 190       uint32_t               : 8,

 237   };
 238 
 239   union SefCpuid7Ecx {
 240     uint32_t value;
 241     struct {
 242       uint32_t prefetchwt1 : 1,
 243                avx512_vbmi : 1,
 244                       umip : 1,
 245                        pku : 1,
 246                      ospke : 1,
 247                            : 1,
 248               avx512_vbmi2 : 1,
 249                            : 1,
 250                       gfni : 1,
 251                       vaes : 1,
 252          avx512_vpclmulqdq : 1,
 253                avx512_vnni : 1,
 254              avx512_bitalg : 1,
 255                            : 1,
 256           avx512_vpopcntdq : 1,
 257                            : 1,
 258                            : 1,
 259                      mawau : 5,
 260                      rdpid : 1,
 261                            : 9;
 262     } bits;
 263   };
 264 
 265   union SefCpuid7Edx {
 266     uint32_t value;
 267     struct {
 268       uint32_t             : 2,
 269              avx512_4vnniw : 1,
 270              avx512_4fmaps : 1,
 271         fast_short_rep_mov : 1,
 272                            : 9,
 273                  serialize : 1,
 274                            : 17;
 275     } bits;
 276   };
 277 
 278   union ExtCpuid1EEbx {
 279     uint32_t value;
 280     struct {
 281       uint32_t                  : 8,
 282                threads_per_core : 8,
 283                                 : 16;
 284     } bits;
 285   };
 286 
 287   union XemXcr0Eax {
 288     uint32_t value;
 289     struct {
 290       uint32_t x87     : 1,
 291                sse     : 1,
 292                ymm     : 1,

 353     decl(AVX512CD,          "avx512cd",          31) \
 354                                                      \
 355     decl(AVX512BW,          "avx512bw",          32) /* Byte and word vector instructions */ \
 356     decl(AVX512VL,          "avx512vl",          33) /* EVEX instructions with smaller vector length */ \
 357     decl(SHA,               "sha",               34) /* SHA instructions */ \
 358     decl(FMA,               "fma",               35) /* FMA instructions */ \
 359                                                      \
 360     decl(VZEROUPPER,        "vzeroupper",        36) /* Vzeroupper instruction */ \
 361     decl(AVX512_VPOPCNTDQ,  "avx512_vpopcntdq",  37) /* Vector popcount */ \
 362     decl(AVX512_VPCLMULQDQ, "avx512_vpclmulqdq", 38) /* Vector carryless multiplication */ \
 363     decl(AVX512_VAES,       "avx512_vaes",       39) /* Vector AES instruction */ \
 364                                                      \
 365     decl(AVX512_VNNI,       "avx512_vnni",       40) /* Vector Neural Network Instructions */ \
 366     decl(FLUSH,             "clflush",           41) /* flush instruction */ \
 367     decl(FLUSHOPT,          "clflushopt",        42) /* flusopth instruction */ \
 368     decl(CLWB,              "clwb",              43) /* clwb instruction */ \
 369                                                      \
 370     decl(AVX512_VBMI2,      "avx512_vbmi2",      44) /* VBMI2 shift left double instructions */ \
 371     decl(AVX512_VBMI,       "avx512_vbmi",       45) /* Vector BMI instructions */ \
 372     decl(HV,                "hv",                46) /* Hypervisor instructions */ \
 373     decl(SERIALIZE,         "serialize",         47) /* CPU SERIALIZE */ \
 374                                                      \
 375     decl(RDTSCP,            "rdtscp",            48) /* RDTSCP instruction */ \
 376     decl(RDPID,             "rdpid",             49) /* RDPID instruction */ \
 377     decl(FSRM,              "fsrm",              50) /* Fast Short REP MOV */
 378 
 379 #define DECLARE_CPU_FEATURE_FLAG(id, name, bit) CPU_##id = (1ULL << bit),
 380     CPU_FEATURE_FLAGS(DECLARE_CPU_FEATURE_FLAG)
 381 #undef DECLARE_CPU_FEATURE_FLAG
 382   };
 383 
 384   static const char* _features_names[];
 385 
 386 enum Extended_Family {
 387     // AMD
 388     CPU_FAMILY_AMD_11H       = 0x11,
 389     // ZX
 390     CPU_FAMILY_ZX_CORE_F6    = 6,
 391     CPU_FAMILY_ZX_CORE_F7    = 7,
 392     // Intel
 393     CPU_FAMILY_INTEL_CORE    = 6,
 394     CPU_MODEL_NEHALEM        = 0x1e,
 395     CPU_MODEL_NEHALEM_EP     = 0x1a,
 396     CPU_MODEL_NEHALEM_EX     = 0x2e,
 397     CPU_MODEL_WESTMERE       = 0x25,

 607         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vnni != 0)
 608           result |= CPU_AVX512_VNNI;
 609         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi != 0)
 610           result |= CPU_AVX512_VBMI;
 611         if (_cpuid_info.sef_cpuid7_ecx.bits.avx512_vbmi2 != 0)
 612           result |= CPU_AVX512_VBMI2;
 613       }
 614     }
 615     if (_cpuid_info.std_cpuid1_ecx.bits.hv != 0)
 616       result |= CPU_HV;
 617     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi1 != 0)
 618       result |= CPU_BMI1;
 619     if (_cpuid_info.std_cpuid1_edx.bits.tsc != 0)
 620       result |= CPU_TSC;
 621     if (_cpuid_info.ext_cpuid7_edx.bits.tsc_invariance != 0)
 622       result |= CPU_TSCINV_BIT;
 623     if (_cpuid_info.std_cpuid1_ecx.bits.aes != 0)
 624       result |= CPU_AES;
 625     if (_cpuid_info.sef_cpuid7_ebx.bits.erms != 0)
 626       result |= CPU_ERMS;
 627     if (_cpuid_info.sef_cpuid7_edx.bits.fast_short_rep_mov != 0)
 628       result |= CPU_FSRM;
 629     if (_cpuid_info.std_cpuid1_ecx.bits.clmul != 0)
 630       result |= CPU_CLMUL;
 631     if (_cpuid_info.sef_cpuid7_ebx.bits.rtm != 0)
 632       result |= CPU_RTM;
 633     if (_cpuid_info.sef_cpuid7_ebx.bits.adx != 0)
 634        result |= CPU_ADX;
 635     if (_cpuid_info.sef_cpuid7_ebx.bits.bmi2 != 0)
 636       result |= CPU_BMI2;
 637     if (_cpuid_info.sef_cpuid7_ebx.bits.sha != 0)
 638       result |= CPU_SHA;
 639     if (_cpuid_info.std_cpuid1_ecx.bits.fma != 0)
 640       result |= CPU_FMA;
 641     if (_cpuid_info.sef_cpuid7_ebx.bits.clflushopt != 0)
 642       result |= CPU_FLUSHOPT;
 643     if (_cpuid_info.ext_cpuid1_edx.bits.rdtscp != 0)
 644       result |= CPU_RDTSCP;
 645     if (_cpuid_info.sef_cpuid7_ecx.bits.rdpid != 0)
 646       result |= CPU_RDPID;
 647 
 648     // AMD|Hygon features.
 649     if (is_amd_family()) {
 650       if ((_cpuid_info.ext_cpuid1_edx.bits.tdnow != 0) ||
 651           (_cpuid_info.ext_cpuid1_ecx.bits.prefetchw != 0))
 652         result |= CPU_3DNOW_PREFETCH;
 653       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt != 0)
 654         result |= CPU_LZCNT;
 655       if (_cpuid_info.ext_cpuid1_ecx.bits.sse4a != 0)
 656         result |= CPU_SSE4A;
 657     }
 658 
 659     // Intel features.
 660     if (is_intel()) {
 661       if (_cpuid_info.ext_cpuid1_ecx.bits.lzcnt_intel != 0)
 662         result |= CPU_LZCNT;
 663       // for Intel, ecx.bits.misalignsse bit (bit 8) indicates support for prefetchw
 664       if (_cpuid_info.ext_cpuid1_ecx.bits.misalignsse != 0) {
 665         result |= CPU_3DNOW_PREFETCH;
 666       }

 870 
 871   //
 872   // Feature identification
 873   //
 874   static bool supports_cpuid()        { return _features  != 0; }
 875   static bool supports_cmpxchg8()     { return (_features & CPU_CX8) != 0; }
 876   static bool supports_cmov()         { return (_features & CPU_CMOV) != 0; }
 877   static bool supports_fxsr()         { return (_features & CPU_FXSR) != 0; }
 878   static bool supports_ht()           { return (_features & CPU_HT) != 0; }
 879   static bool supports_mmx()          { return (_features & CPU_MMX) != 0; }
 880   static bool supports_sse()          { return (_features & CPU_SSE) != 0; }
 881   static bool supports_sse2()         { return (_features & CPU_SSE2) != 0; }
 882   static bool supports_sse3()         { return (_features & CPU_SSE3) != 0; }
 883   static bool supports_ssse3()        { return (_features & CPU_SSSE3)!= 0; }
 884   static bool supports_sse4_1()       { return (_features & CPU_SSE4_1) != 0; }
 885   static bool supports_sse4_2()       { return (_features & CPU_SSE4_2) != 0; }
 886   static bool supports_popcnt()       { return (_features & CPU_POPCNT) != 0; }
 887   static bool supports_avx()          { return (_features & CPU_AVX) != 0; }
 888   static bool supports_avx2()         { return (_features & CPU_AVX2) != 0; }
 889   static bool supports_tsc()          { return (_features & CPU_TSC) != 0; }
 890   static bool supports_rdtscp()       { return (_features & CPU_RDTSCP) != 0; }
 891   static bool supports_rdpid()        { return (_features & CPU_RDPID) != 0; }
 892   static bool supports_aes()          { return (_features & CPU_AES) != 0; }
 893   static bool supports_erms()         { return (_features & CPU_ERMS) != 0; }
 894   static bool supports_fsrm()         { return (_features & CPU_FSRM) != 0; }
 895   static bool supports_clmul()        { return (_features & CPU_CLMUL) != 0; }
 896   static bool supports_rtm()          { return (_features & CPU_RTM) != 0; }
 897   static bool supports_bmi1()         { return (_features & CPU_BMI1) != 0; }
 898   static bool supports_bmi2()         { return (_features & CPU_BMI2) != 0; }
 899   static bool supports_adx()          { return (_features & CPU_ADX) != 0; }
 900   static bool supports_evex()         { return (_features & CPU_AVX512F) != 0; }
 901   static bool supports_avx512dq()     { return (_features & CPU_AVX512DQ) != 0; }
 902   static bool supports_avx512pf()     { return (_features & CPU_AVX512PF) != 0; }
 903   static bool supports_avx512er()     { return (_features & CPU_AVX512ER) != 0; }
 904   static bool supports_avx512cd()     { return (_features & CPU_AVX512CD) != 0; }
 905   static bool supports_avx512bw()     { return (_features & CPU_AVX512BW) != 0; }
 906   static bool supports_avx512vl()     { return (_features & CPU_AVX512VL) != 0; }
 907   static bool supports_avx512vlbw()   { return (supports_evex() && supports_avx512bw() && supports_avx512vl()); }
 908   static bool supports_avx512vldq()   { return (supports_evex() && supports_avx512dq() && supports_avx512vl()); }
 909   static bool supports_avx512vlbwdq() { return (supports_evex() && supports_avx512vl() &&
 910                                                 supports_avx512bw() && supports_avx512dq()); }
 911   static bool supports_avx512novl()   { return (supports_evex() && !supports_avx512vl()); }
 912   static bool supports_avx512nobw()   { return (supports_evex() && !supports_avx512bw()); }
 913   static bool supports_avx256only()   { return (supports_avx2() && !supports_evex()); }
 914   static bool supports_avxonly()      { return ((supports_avx2() || supports_avx()) && !supports_evex()); }
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