1 //
    2 // Copyright (c) 2003, 2021, Oracle and/or its affiliates. All rights reserved.
    3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    4 //
    5 // This code is free software; you can redistribute it and/or modify it
    6 // under the terms of the GNU General Public License version 2 only, as
    7 // published by the Free Software Foundation.
    8 //
    9 // This code is distributed in the hope that it will be useful, but WITHOUT
   10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   12 // version 2 for more details (a copy is included in the LICENSE file that
   13 // accompanied this code).
   14 //
   15 // You should have received a copy of the GNU General Public License version
   16 // 2 along with this work; if not, write to the Free Software Foundation,
   17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   18 //
   19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   20 // or visit www.oracle.com if you need additional information or have any
   21 // questions.
   22 //
   23 //
   24 
   25 // AMD64 Architecture Description File
   26 
   27 //----------REGISTER DEFINITION BLOCK------------------------------------------
   28 // This information is used by the matcher and the register allocator to
   29 // describe individual registers and classes of registers within the target
   30 // archtecture.
   31 
   32 register %{
   33 //----------Architecture Description Register Definitions----------------------
   34 // General Registers
   35 // "reg_def"  name ( register save type, C convention save type,
   36 //                   ideal register type, encoding );
   37 // Register Save Types:
   38 //
   39 // NS  = No-Save:       The register allocator assumes that these registers
   40 //                      can be used without saving upon entry to the method, &
   41 //                      that they do not need to be saved at call sites.
   42 //
   43 // SOC = Save-On-Call:  The register allocator assumes that these registers
   44 //                      can be used without saving upon entry to the method,
   45 //                      but that they must be saved at call sites.
   46 //
   47 // SOE = Save-On-Entry: The register allocator assumes that these registers
   48 //                      must be saved before using them upon entry to the
   49 //                      method, but they do not need to be saved at call
   50 //                      sites.
   51 //
   52 // AS  = Always-Save:   The register allocator assumes that these registers
   53 //                      must be saved before using them upon entry to the
   54 //                      method, & that they must be saved at call sites.
   55 //
   56 // Ideal Register Type is used to determine how to save & restore a
   57 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   58 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
   59 //
   60 // The encoding number is the actual bit-pattern placed into the opcodes.
   61 
   62 // General Registers
   63 // R8-R15 must be encoded with REX.  (RSP, RBP, RSI, RDI need REX when
   64 // used as byte registers)
   65 
   66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
   67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
   68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
   69 
   70 reg_def RAX  (SOC, SOC, Op_RegI,  0, rax->as_VMReg());
   71 reg_def RAX_H(SOC, SOC, Op_RegI,  0, rax->as_VMReg()->next());
   72 
   73 reg_def RCX  (SOC, SOC, Op_RegI,  1, rcx->as_VMReg());
   74 reg_def RCX_H(SOC, SOC, Op_RegI,  1, rcx->as_VMReg()->next());
   75 
   76 reg_def RDX  (SOC, SOC, Op_RegI,  2, rdx->as_VMReg());
   77 reg_def RDX_H(SOC, SOC, Op_RegI,  2, rdx->as_VMReg()->next());
   78 
   79 reg_def RBX  (SOC, SOE, Op_RegI,  3, rbx->as_VMReg());
   80 reg_def RBX_H(SOC, SOE, Op_RegI,  3, rbx->as_VMReg()->next());
   81 
   82 reg_def RSP  (NS,  NS,  Op_RegI,  4, rsp->as_VMReg());
   83 reg_def RSP_H(NS,  NS,  Op_RegI,  4, rsp->as_VMReg()->next());
   84 
   85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
   86 reg_def RBP  (NS, SOE, Op_RegI,  5, rbp->as_VMReg());
   87 reg_def RBP_H(NS, SOE, Op_RegI,  5, rbp->as_VMReg()->next());
   88 
   89 #ifdef _WIN64
   90 
   91 reg_def RSI  (SOC, SOE, Op_RegI,  6, rsi->as_VMReg());
   92 reg_def RSI_H(SOC, SOE, Op_RegI,  6, rsi->as_VMReg()->next());
   93 
   94 reg_def RDI  (SOC, SOE, Op_RegI,  7, rdi->as_VMReg());
   95 reg_def RDI_H(SOC, SOE, Op_RegI,  7, rdi->as_VMReg()->next());
   96 
   97 #else
   98 
   99 reg_def RSI  (SOC, SOC, Op_RegI,  6, rsi->as_VMReg());
  100 reg_def RSI_H(SOC, SOC, Op_RegI,  6, rsi->as_VMReg()->next());
  101 
  102 reg_def RDI  (SOC, SOC, Op_RegI,  7, rdi->as_VMReg());
  103 reg_def RDI_H(SOC, SOC, Op_RegI,  7, rdi->as_VMReg()->next());
  104 
  105 #endif
  106 
  107 reg_def R8   (SOC, SOC, Op_RegI,  8, r8->as_VMReg());
  108 reg_def R8_H (SOC, SOC, Op_RegI,  8, r8->as_VMReg()->next());
  109 
  110 reg_def R9   (SOC, SOC, Op_RegI,  9, r9->as_VMReg());
  111 reg_def R9_H (SOC, SOC, Op_RegI,  9, r9->as_VMReg()->next());
  112 
  113 reg_def R10  (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
  114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
  115 
  116 reg_def R11  (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
  117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
  118 
  119 reg_def R12  (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
  120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
  121 
  122 reg_def R13  (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
  123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
  124 
  125 reg_def R14  (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
  126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
  127 
  128 reg_def R15  (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
  129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
  130 
  131 
  132 // Floating Point Registers
  133 
  134 // Specify priority of register selection within phases of register
  135 // allocation.  Highest priority is first.  A useful heuristic is to
  136 // give registers a low priority when they are required by machine
  137 // instructions, like EAX and EDX on I486, and choose no-save registers
  138 // before save-on-call, & save-on-call before save-on-entry.  Registers
  139 // which participate in fixed calling sequences should come last.
  140 // Registers which are used as pairs must fall on an even boundary.
  141 
  142 alloc_class chunk0(R10,         R10_H,
  143                    R11,         R11_H,
  144                    R8,          R8_H,
  145                    R9,          R9_H,
  146                    R12,         R12_H,
  147                    RCX,         RCX_H,
  148                    RBX,         RBX_H,
  149                    RDI,         RDI_H,
  150                    RDX,         RDX_H,
  151                    RSI,         RSI_H,
  152                    RAX,         RAX_H,
  153                    RBP,         RBP_H,
  154                    R13,         R13_H,
  155                    R14,         R14_H,
  156                    R15,         R15_H,
  157                    RSP,         RSP_H);
  158 
  159 
  160 //----------Architecture Description Register Classes--------------------------
  161 // Several register classes are automatically defined based upon information in
  162 // this architecture description.
  163 // 1) reg_class inline_cache_reg           ( /* as def'd in frame section */ )
  164 // 2) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
  165 //
  166 
  167 // Empty register class.
  168 reg_class no_reg();
  169 
  170 // Class for all pointer/long registers
  171 reg_class all_reg(RAX, RAX_H,
  172                   RDX, RDX_H,
  173                   RBP, RBP_H,
  174                   RDI, RDI_H,
  175                   RSI, RSI_H,
  176                   RCX, RCX_H,
  177                   RBX, RBX_H,
  178                   RSP, RSP_H,
  179                   R8,  R8_H,
  180                   R9,  R9_H,
  181                   R10, R10_H,
  182                   R11, R11_H,
  183                   R12, R12_H,
  184                   R13, R13_H,
  185                   R14, R14_H,
  186                   R15, R15_H);
  187 
  188 // Class for all int registers
  189 reg_class all_int_reg(RAX
  190                       RDX,
  191                       RBP,
  192                       RDI,
  193                       RSI,
  194                       RCX,
  195                       RBX,
  196                       R8,
  197                       R9,
  198                       R10,
  199                       R11,
  200                       R12,
  201                       R13,
  202                       R14);
  203 
  204 // Class for all pointer registers
  205 reg_class any_reg %{
  206   return _ANY_REG_mask;
  207 %}
  208 
  209 // Class for all pointer registers (excluding RSP)
  210 reg_class ptr_reg %{
  211   return _PTR_REG_mask;
  212 %}
  213 
  214 // Class for all pointer registers (excluding RSP and RBP)
  215 reg_class ptr_reg_no_rbp %{
  216   return _PTR_REG_NO_RBP_mask;
  217 %}
  218 
  219 // Class for all pointer registers (excluding RAX and RSP)
  220 reg_class ptr_no_rax_reg %{
  221   return _PTR_NO_RAX_REG_mask;
  222 %}
  223 
  224 // Class for all pointer registers (excluding RAX, RBX, and RSP)
  225 reg_class ptr_no_rax_rbx_reg %{
  226   return _PTR_NO_RAX_RBX_REG_mask;
  227 %}
  228 
  229 // Class for all long registers (excluding RSP)
  230 reg_class long_reg %{
  231   return _LONG_REG_mask;
  232 %}
  233 
  234 // Class for all long registers (excluding RAX, RDX and RSP)
  235 reg_class long_no_rax_rdx_reg %{
  236   return _LONG_NO_RAX_RDX_REG_mask;
  237 %}
  238 
  239 // Class for all long registers (excluding RCX and RSP)
  240 reg_class long_no_rcx_reg %{
  241   return _LONG_NO_RCX_REG_mask;
  242 %}
  243 
  244 // Class for all int registers (excluding RSP)
  245 reg_class int_reg %{
  246   return _INT_REG_mask;
  247 %}
  248 
  249 // Class for all int registers (excluding RAX, RDX, and RSP)
  250 reg_class int_no_rax_rdx_reg %{
  251   return _INT_NO_RAX_RDX_REG_mask;
  252 %}
  253 
  254 // Class for all int registers (excluding RCX and RSP)
  255 reg_class int_no_rcx_reg %{
  256   return _INT_NO_RCX_REG_mask;
  257 %}
  258 
  259 // Singleton class for RAX pointer register
  260 reg_class ptr_rax_reg(RAX, RAX_H);
  261 
  262 // Singleton class for RBX pointer register
  263 reg_class ptr_rbx_reg(RBX, RBX_H);
  264 
  265 // Singleton class for RSI pointer register
  266 reg_class ptr_rsi_reg(RSI, RSI_H);
  267 
  268 // Singleton class for RBP pointer register
  269 reg_class ptr_rbp_reg(RBP, RBP_H);
  270 
  271 // Singleton class for RDI pointer register
  272 reg_class ptr_rdi_reg(RDI, RDI_H);
  273 
  274 // Singleton class for stack pointer
  275 reg_class ptr_rsp_reg(RSP, RSP_H);
  276 
  277 // Singleton class for TLS pointer
  278 reg_class ptr_r15_reg(R15, R15_H);
  279 
  280 // Singleton class for RAX long register
  281 reg_class long_rax_reg(RAX, RAX_H);
  282 
  283 // Singleton class for RCX long register
  284 reg_class long_rcx_reg(RCX, RCX_H);
  285 
  286 // Singleton class for RDX long register
  287 reg_class long_rdx_reg(RDX, RDX_H);
  288 
  289 // Singleton class for RAX int register
  290 reg_class int_rax_reg(RAX);
  291 
  292 // Singleton class for RBX int register
  293 reg_class int_rbx_reg(RBX);
  294 
  295 // Singleton class for RCX int register
  296 reg_class int_rcx_reg(RCX);
  297 
  298 // Singleton class for RCX int register
  299 reg_class int_rdx_reg(RDX);
  300 
  301 // Singleton class for RCX int register
  302 reg_class int_rdi_reg(RDI);
  303 
  304 // Singleton class for instruction pointer
  305 // reg_class ip_reg(RIP);
  306 
  307 %}
  308 
  309 //----------SOURCE BLOCK-------------------------------------------------------
  310 // This is a block of C++ code which provides values, functions, and
  311 // definitions necessary in the rest of the architecture description
  312 source_hpp %{
  313 
  314 extern RegMask _ANY_REG_mask;
  315 extern RegMask _PTR_REG_mask;
  316 extern RegMask _PTR_REG_NO_RBP_mask;
  317 extern RegMask _PTR_NO_RAX_REG_mask;
  318 extern RegMask _PTR_NO_RAX_RBX_REG_mask;
  319 extern RegMask _LONG_REG_mask;
  320 extern RegMask _LONG_NO_RAX_RDX_REG_mask;
  321 extern RegMask _LONG_NO_RCX_REG_mask;
  322 extern RegMask _INT_REG_mask;
  323 extern RegMask _INT_NO_RAX_RDX_REG_mask;
  324 extern RegMask _INT_NO_RCX_REG_mask;
  325 extern RegMask _FLOAT_REG_mask;
  326 
  327 extern RegMask _STACK_OR_PTR_REG_mask;
  328 extern RegMask _STACK_OR_LONG_REG_mask;
  329 extern RegMask _STACK_OR_INT_REG_mask;
  330 
  331 inline const RegMask& STACK_OR_PTR_REG_mask()  { return _STACK_OR_PTR_REG_mask;  }
  332 inline const RegMask& STACK_OR_LONG_REG_mask() { return _STACK_OR_LONG_REG_mask; }
  333 inline const RegMask& STACK_OR_INT_REG_mask()  { return _STACK_OR_INT_REG_mask;  }
  334 
  335 %}
  336 
  337 source %{
  338 #define   RELOC_IMM64    Assembler::imm_operand
  339 #define   RELOC_DISP32   Assembler::disp32_operand
  340 
  341 #define __ _masm.
  342 
  343 RegMask _ANY_REG_mask;
  344 RegMask _PTR_REG_mask;
  345 RegMask _PTR_REG_NO_RBP_mask;
  346 RegMask _PTR_NO_RAX_REG_mask;
  347 RegMask _PTR_NO_RAX_RBX_REG_mask;
  348 RegMask _LONG_REG_mask;
  349 RegMask _LONG_NO_RAX_RDX_REG_mask;
  350 RegMask _LONG_NO_RCX_REG_mask;
  351 RegMask _INT_REG_mask;
  352 RegMask _INT_NO_RAX_RDX_REG_mask;
  353 RegMask _INT_NO_RCX_REG_mask;
  354 RegMask _FLOAT_REG_mask;
  355 RegMask _STACK_OR_PTR_REG_mask;
  356 RegMask _STACK_OR_LONG_REG_mask;
  357 RegMask _STACK_OR_INT_REG_mask;
  358 
  359 static bool need_r12_heapbase() {
  360   return UseCompressedOops;
  361 }
  362 
  363 void reg_mask_init() {
  364   // _ALL_REG_mask is generated by adlc from the all_reg register class below.
  365   // We derive a number of subsets from it.
  366   _ANY_REG_mask = _ALL_REG_mask;
  367 
  368   if (PreserveFramePointer) {
  369     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  370     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  371   }
  372   if (need_r12_heapbase()) {
  373     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  374     _ANY_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()->next()));
  375   }
  376 
  377   _PTR_REG_mask = _ANY_REG_mask;
  378   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()));
  379   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(rsp->as_VMReg()->next()));
  380   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()));
  381   _PTR_REG_mask.Remove(OptoReg::as_OptoReg(r15->as_VMReg()->next()));
  382 
  383   _STACK_OR_PTR_REG_mask = _PTR_REG_mask;
  384   _STACK_OR_PTR_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  385 
  386   _PTR_REG_NO_RBP_mask = _PTR_REG_mask;
  387   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  388   _PTR_REG_NO_RBP_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()->next()));
  389 
  390   _PTR_NO_RAX_REG_mask = _PTR_REG_mask;
  391   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  392   _PTR_NO_RAX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  393 
  394   _PTR_NO_RAX_RBX_REG_mask = _PTR_NO_RAX_REG_mask;
  395   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()));
  396   _PTR_NO_RAX_RBX_REG_mask.Remove(OptoReg::as_OptoReg(rbx->as_VMReg()->next()));
  397 
  398   _LONG_REG_mask = _PTR_REG_mask;
  399   _STACK_OR_LONG_REG_mask = _LONG_REG_mask;
  400   _STACK_OR_LONG_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  401 
  402   _LONG_NO_RAX_RDX_REG_mask = _LONG_REG_mask;
  403   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  404   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()->next()));
  405   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  406   _LONG_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()->next()));
  407 
  408   _LONG_NO_RCX_REG_mask = _LONG_REG_mask;
  409   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  410   _LONG_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()->next()));
  411 
  412   _INT_REG_mask = _ALL_INT_REG_mask;
  413   if (PreserveFramePointer) {
  414     _INT_REG_mask.Remove(OptoReg::as_OptoReg(rbp->as_VMReg()));
  415   }
  416   if (need_r12_heapbase()) {
  417     _INT_REG_mask.Remove(OptoReg::as_OptoReg(r12->as_VMReg()));
  418   }
  419 
  420   _STACK_OR_INT_REG_mask = _INT_REG_mask;
  421   _STACK_OR_INT_REG_mask.OR(STACK_OR_STACK_SLOTS_mask());
  422 
  423   _INT_NO_RAX_RDX_REG_mask = _INT_REG_mask;
  424   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rax->as_VMReg()));
  425   _INT_NO_RAX_RDX_REG_mask.Remove(OptoReg::as_OptoReg(rdx->as_VMReg()));
  426 
  427   _INT_NO_RCX_REG_mask = _INT_REG_mask;
  428   _INT_NO_RCX_REG_mask.Remove(OptoReg::as_OptoReg(rcx->as_VMReg()));
  429 
  430   // _FLOAT_REG_LEGACY_mask/_FLOAT_REG_EVEX_mask is generated by adlc
  431   // from the float_reg_legacy/float_reg_evex register class.
  432   _FLOAT_REG_mask = VM_Version::supports_evex() ? _FLOAT_REG_EVEX_mask : _FLOAT_REG_LEGACY_mask;
  433 
  434   if (Matcher::has_predicated_vectors()) {
  435     // Post-loop multi-versioning expects mask to be present in K1 register, till the time
  436     // its fixed, RA should not be allocting K1 register, this shall prevent any accidental
  437     // curruption of value held in K1 register.
  438     if (PostLoopMultiversioning) {
  439       const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()));
  440       const_cast<RegMask*>(&_VECTMASK_REG_mask)->Remove(OptoReg::as_OptoReg(k1->as_VMReg()->next()));
  441     }
  442   }
  443 }
  444 
  445 static bool generate_vzeroupper(Compile* C) {
  446   return (VM_Version::supports_vzeroupper() && (C->max_vector_size() > 16 || C->clear_upper_avx() == true)) ? true: false;  // Generate vzeroupper
  447 }
  448 
  449 static int clear_avx_size() {
  450   return generate_vzeroupper(Compile::current()) ? 3: 0;  // vzeroupper
  451 }
  452 
  453 // !!!!! Special hack to get all types of calls to specify the byte offset
  454 //       from the start of the call to the point where the return address
  455 //       will point.
  456 int MachCallStaticJavaNode::ret_addr_offset()
  457 {
  458   int offset = 5; // 5 bytes from start of call to where return address points
  459   offset += clear_avx_size();
  460   return offset;
  461 }
  462 
  463 int MachCallDynamicJavaNode::ret_addr_offset()
  464 {
  465   int offset = 15; // 15 bytes from start of call to where return address points
  466   offset += clear_avx_size();
  467   return offset;
  468 }
  469 
  470 int MachCallRuntimeNode::ret_addr_offset() {
  471   int offset = 13; // movq r10,#addr; callq (r10)
  472   if (this->ideal_Opcode() != Op_CallLeafVector) {
  473     offset += clear_avx_size();
  474   }
  475   return offset;
  476 }
  477 
  478 int MachCallNativeNode::ret_addr_offset() {
  479   int offset = 13; // movq r10,#addr; callq (r10)
  480   offset += clear_avx_size();
  481   return offset;
  482 }
  483 //
  484 // Compute padding required for nodes which need alignment
  485 //
  486 
  487 // The address of the call instruction needs to be 4-byte aligned to
  488 // ensure that it does not span a cache line so that it can be patched.
  489 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
  490 {
  491   current_offset += clear_avx_size(); // skip vzeroupper
  492   current_offset += 1; // skip call opcode byte
  493   return align_up(current_offset, alignment_required()) - current_offset;
  494 }
  495 
  496 // The address of the call instruction needs to be 4-byte aligned to
  497 // ensure that it does not span a cache line so that it can be patched.
  498 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
  499 {
  500   current_offset += clear_avx_size(); // skip vzeroupper
  501   current_offset += 11; // skip movq instruction + call opcode byte
  502   return align_up(current_offset, alignment_required()) - current_offset;
  503 }
  504 
  505 // EMIT_RM()
  506 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
  507   unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
  508   cbuf.insts()->emit_int8(c);
  509 }
  510 
  511 // EMIT_CC()
  512 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
  513   unsigned char c = (unsigned char) (f1 | f2);
  514   cbuf.insts()->emit_int8(c);
  515 }
  516 
  517 // EMIT_OPCODE()
  518 void emit_opcode(CodeBuffer &cbuf, int code) {
  519   cbuf.insts()->emit_int8((unsigned char) code);
  520 }
  521 
  522 // EMIT_OPCODE() w/ relocation information
  523 void emit_opcode(CodeBuffer &cbuf,
  524                  int code, relocInfo::relocType reloc, int offset, int format)
  525 {
  526   cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
  527   emit_opcode(cbuf, code);
  528 }
  529 
  530 // EMIT_D8()
  531 void emit_d8(CodeBuffer &cbuf, int d8) {
  532   cbuf.insts()->emit_int8((unsigned char) d8);
  533 }
  534 
  535 // EMIT_D16()
  536 void emit_d16(CodeBuffer &cbuf, int d16) {
  537   cbuf.insts()->emit_int16(d16);
  538 }
  539 
  540 // EMIT_D32()
  541 void emit_d32(CodeBuffer &cbuf, int d32) {
  542   cbuf.insts()->emit_int32(d32);
  543 }
  544 
  545 // EMIT_D64()
  546 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
  547   cbuf.insts()->emit_int64(d64);
  548 }
  549 
  550 // emit 32 bit value and construct relocation entry from relocInfo::relocType
  551 void emit_d32_reloc(CodeBuffer& cbuf,
  552                     int d32,
  553                     relocInfo::relocType reloc,
  554                     int format)
  555 {
  556   assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
  557   cbuf.relocate(cbuf.insts_mark(), reloc, format);
  558   cbuf.insts()->emit_int32(d32);
  559 }
  560 
  561 // emit 32 bit value and construct relocation entry from RelocationHolder
  562 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
  563 #ifdef ASSERT
  564   if (rspec.reloc()->type() == relocInfo::oop_type &&
  565       d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
  566     assert(Universe::heap()->is_in((address)(intptr_t)d32), "should be real oop");
  567     assert(oopDesc::is_oop(cast_to_oop((intptr_t)d32)), "cannot embed broken oops in code");
  568   }
  569 #endif
  570   cbuf.relocate(cbuf.insts_mark(), rspec, format);
  571   cbuf.insts()->emit_int32(d32);
  572 }
  573 
  574 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
  575   address next_ip = cbuf.insts_end() + 4;
  576   emit_d32_reloc(cbuf, (int) (addr - next_ip),
  577                  external_word_Relocation::spec(addr),
  578                  RELOC_DISP32);
  579 }
  580 
  581 
  582 // emit 64 bit value and construct relocation entry from relocInfo::relocType
  583 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
  584   cbuf.relocate(cbuf.insts_mark(), reloc, format);
  585   cbuf.insts()->emit_int64(d64);
  586 }
  587 
  588 // emit 64 bit value and construct relocation entry from RelocationHolder
  589 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
  590 #ifdef ASSERT
  591   if (rspec.reloc()->type() == relocInfo::oop_type &&
  592       d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
  593     assert(Universe::heap()->is_in((address)d64), "should be real oop");
  594     assert(oopDesc::is_oop(cast_to_oop(d64)), "cannot embed broken oops in code");
  595   }
  596 #endif
  597   cbuf.relocate(cbuf.insts_mark(), rspec, format);
  598   cbuf.insts()->emit_int64(d64);
  599 }
  600 
  601 // Access stack slot for load or store
  602 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
  603 {
  604   emit_opcode(cbuf, opcode);                  // (e.g., FILD   [RSP+src])
  605   if (-0x80 <= disp && disp < 0x80) {
  606     emit_rm(cbuf, 0x01, rm_field, RSP_enc);   // R/M byte
  607     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
  608     emit_d8(cbuf, disp);     // Displacement  // R/M byte
  609   } else {
  610     emit_rm(cbuf, 0x02, rm_field, RSP_enc);   // R/M byte
  611     emit_rm(cbuf, 0x00, RSP_enc, RSP_enc);    // SIB byte
  612     emit_d32(cbuf, disp);     // Displacement // R/M byte
  613   }
  614 }
  615 
  616    // rRegI ereg, memory mem) %{    // emit_reg_mem
  617 void encode_RegMem(CodeBuffer &cbuf,
  618                    int reg,
  619                    int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
  620 {
  621   assert(disp_reloc == relocInfo::none, "cannot have disp");
  622   int regenc = reg & 7;
  623   int baseenc = base & 7;
  624   int indexenc = index & 7;
  625 
  626   // There is no index & no scale, use form without SIB byte
  627   if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
  628     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
  629     if (disp == 0 && base != RBP_enc && base != R13_enc) {
  630       emit_rm(cbuf, 0x0, regenc, baseenc); // *
  631     } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
  632       // If 8-bit displacement, mode 0x1
  633       emit_rm(cbuf, 0x1, regenc, baseenc); // *
  634       emit_d8(cbuf, disp);
  635     } else {
  636       // If 32-bit displacement
  637       if (base == -1) { // Special flag for absolute address
  638         emit_rm(cbuf, 0x0, regenc, 0x5); // *
  639         if (disp_reloc != relocInfo::none) {
  640           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  641         } else {
  642           emit_d32(cbuf, disp);
  643         }
  644       } else {
  645         // Normal base + offset
  646         emit_rm(cbuf, 0x2, regenc, baseenc); // *
  647         if (disp_reloc != relocInfo::none) {
  648           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  649         } else {
  650           emit_d32(cbuf, disp);
  651         }
  652       }
  653     }
  654   } else {
  655     // Else, encode with the SIB byte
  656     // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
  657     if (disp == 0 && base != RBP_enc && base != R13_enc) {
  658       // If no displacement
  659       emit_rm(cbuf, 0x0, regenc, 0x4); // *
  660       emit_rm(cbuf, scale, indexenc, baseenc);
  661     } else {
  662       if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
  663         // If 8-bit displacement, mode 0x1
  664         emit_rm(cbuf, 0x1, regenc, 0x4); // *
  665         emit_rm(cbuf, scale, indexenc, baseenc);
  666         emit_d8(cbuf, disp);
  667       } else {
  668         // If 32-bit displacement
  669         if (base == 0x04 ) {
  670           emit_rm(cbuf, 0x2, regenc, 0x4);
  671           emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
  672         } else {
  673           emit_rm(cbuf, 0x2, regenc, 0x4);
  674           emit_rm(cbuf, scale, indexenc, baseenc); // *
  675         }
  676         if (disp_reloc != relocInfo::none) {
  677           emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
  678         } else {
  679           emit_d32(cbuf, disp);
  680         }
  681       }
  682     }
  683   }
  684 }
  685 
  686 // This could be in MacroAssembler but it's fairly C2 specific
  687 void emit_cmpfp_fixup(MacroAssembler& _masm) {
  688   Label exit;
  689   __ jccb(Assembler::noParity, exit);
  690   __ pushf();
  691   //
  692   // comiss/ucomiss instructions set ZF,PF,CF flags and
  693   // zero OF,AF,SF for NaN values.
  694   // Fixup flags by zeroing ZF,PF so that compare of NaN
  695   // values returns 'less than' result (CF is set).
  696   // Leave the rest of flags unchanged.
  697   //
  698   //    7 6 5 4 3 2 1 0
  699   //   |S|Z|r|A|r|P|r|C|  (r - reserved bit)
  700   //    0 0 1 0 1 0 1 1   (0x2B)
  701   //
  702   __ andq(Address(rsp, 0), 0xffffff2b);
  703   __ popf();
  704   __ bind(exit);
  705 }
  706 
  707 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
  708   Label done;
  709   __ movl(dst, -1);
  710   __ jcc(Assembler::parity, done);
  711   __ jcc(Assembler::below, done);
  712   __ setb(Assembler::notEqual, dst);
  713   __ movzbl(dst, dst);
  714   __ bind(done);
  715 }
  716 
  717 // Math.min()    # Math.max()
  718 // --------------------------
  719 // ucomis[s/d]   #
  720 // ja   -> b     # a
  721 // jp   -> NaN   # NaN
  722 // jb   -> a     # b
  723 // je            #
  724 // |-jz -> a | b # a & b
  725 // |    -> a     #
  726 void emit_fp_min_max(MacroAssembler& _masm, XMMRegister dst,
  727                      XMMRegister a, XMMRegister b,
  728                      XMMRegister xmmt, Register rt,
  729                      bool min, bool single) {
  730 
  731   Label nan, zero, below, above, done;
  732 
  733   if (single)
  734     __ ucomiss(a, b);
  735   else
  736     __ ucomisd(a, b);
  737 
  738   if (dst->encoding() != (min ? b : a)->encoding())
  739     __ jccb(Assembler::above, above); // CF=0 & ZF=0
  740   else
  741     __ jccb(Assembler::above, done);
  742 
  743   __ jccb(Assembler::parity, nan);  // PF=1
  744   __ jccb(Assembler::below, below); // CF=1
  745 
  746   // equal
  747   __ vpxor(xmmt, xmmt, xmmt, Assembler::AVX_128bit);
  748   if (single) {
  749     __ ucomiss(a, xmmt);
  750     __ jccb(Assembler::equal, zero);
  751 
  752     __ movflt(dst, a);
  753     __ jmp(done);
  754   }
  755   else {
  756     __ ucomisd(a, xmmt);
  757     __ jccb(Assembler::equal, zero);
  758 
  759     __ movdbl(dst, a);
  760     __ jmp(done);
  761   }
  762 
  763   __ bind(zero);
  764   if (min)
  765     __ vpor(dst, a, b, Assembler::AVX_128bit);
  766   else
  767     __ vpand(dst, a, b, Assembler::AVX_128bit);
  768 
  769   __ jmp(done);
  770 
  771   __ bind(above);
  772   if (single)
  773     __ movflt(dst, min ? b : a);
  774   else
  775     __ movdbl(dst, min ? b : a);
  776 
  777   __ jmp(done);
  778 
  779   __ bind(nan);
  780   if (single) {
  781     __ movl(rt, 0x7fc00000); // Float.NaN
  782     __ movdl(dst, rt);
  783   }
  784   else {
  785     __ mov64(rt, 0x7ff8000000000000L); // Double.NaN
  786     __ movdq(dst, rt);
  787   }
  788   __ jmp(done);
  789 
  790   __ bind(below);
  791   if (single)
  792     __ movflt(dst, min ? a : b);
  793   else
  794     __ movdbl(dst, min ? a : b);
  795 
  796   __ bind(done);
  797 }
  798 
  799 //=============================================================================
  800 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
  801 
  802 int ConstantTable::calculate_table_base_offset() const {
  803   return 0;  // absolute addressing, no offset
  804 }
  805 
  806 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
  807 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
  808   ShouldNotReachHere();
  809 }
  810 
  811 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
  812   // Empty encoding
  813 }
  814 
  815 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
  816   return 0;
  817 }
  818 
  819 #ifndef PRODUCT
  820 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  821   st->print("# MachConstantBaseNode (empty encoding)");
  822 }
  823 #endif
  824 
  825 
  826 //=============================================================================
  827 #ifndef PRODUCT
  828 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  829   Compile* C = ra_->C;
  830 
  831   int framesize = C->output()->frame_size_in_bytes();
  832   int bangsize = C->output()->bang_size_in_bytes();
  833   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  834   // Remove wordSize for return addr which is already pushed.
  835   framesize -= wordSize;
  836 
  837   if (C->output()->need_stack_bang(bangsize)) {
  838     framesize -= wordSize;
  839     st->print("# stack bang (%d bytes)", bangsize);
  840     st->print("\n\t");
  841     st->print("pushq   rbp\t# Save rbp");
  842     if (PreserveFramePointer) {
  843         st->print("\n\t");
  844         st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  845     }
  846     if (framesize) {
  847       st->print("\n\t");
  848       st->print("subq    rsp, #%d\t# Create frame",framesize);
  849     }
  850   } else {
  851     st->print("subq    rsp, #%d\t# Create frame",framesize);
  852     st->print("\n\t");
  853     framesize -= wordSize;
  854     st->print("movq    [rsp + #%d], rbp\t# Save rbp",framesize);
  855     if (PreserveFramePointer) {
  856       st->print("\n\t");
  857       st->print("movq    rbp, rsp\t# Save the caller's SP into rbp");
  858       if (framesize > 0) {
  859         st->print("\n\t");
  860         st->print("addq    rbp, #%d", framesize);
  861       }
  862     }
  863   }
  864 
  865   if (VerifyStackAtCalls) {
  866     st->print("\n\t");
  867     framesize -= wordSize;
  868     st->print("movq    [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
  869 #ifdef ASSERT
  870     st->print("\n\t");
  871     st->print("# stack alignment check");
  872 #endif
  873   }
  874   if (C->stub_function() != NULL && BarrierSet::barrier_set()->barrier_set_nmethod() != NULL) {
  875     st->print("\n\t");
  876     st->print("cmpl    [r15_thread + #disarmed_offset], #disarmed_value\t");
  877     st->print("\n\t");
  878     st->print("je      fast_entry\t");
  879     st->print("\n\t");
  880     st->print("call    #nmethod_entry_barrier_stub\t");
  881     st->print("\n\tfast_entry:");
  882   }
  883   st->cr();
  884 }
  885 #endif
  886 
  887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  888   Compile* C = ra_->C;
  889   MacroAssembler _masm(&cbuf);
  890 
  891   int framesize = C->output()->frame_size_in_bytes();
  892   int bangsize = C->output()->bang_size_in_bytes();
  893 
  894   if (C->clinit_barrier_on_entry()) {
  895     assert(VM_Version::supports_fast_class_init_checks(), "sanity");
  896     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
  897 
  898     Label L_skip_barrier;
  899     Register klass = rscratch1;
  900 
  901     __ mov_metadata(klass, C->method()->holder()->constant_encoding());
  902     __ clinit_barrier(klass, r15_thread, &L_skip_barrier /*L_fast_path*/);
  903 
  904     __ jump(RuntimeAddress(SharedRuntime::get_handle_wrong_method_stub())); // slow path
  905 
  906     __ bind(L_skip_barrier);
  907   }
  908 
  909   __ verified_entry(framesize, C->output()->need_stack_bang(bangsize)?bangsize:0, false, C->stub_function() != NULL);
  910 
  911   C->output()->set_frame_complete(cbuf.insts_size());
  912 
  913   if (C->has_mach_constant_base_node()) {
  914     // NOTE: We set the table base offset here because users might be
  915     // emitted before MachConstantBaseNode.
  916     ConstantTable& constant_table = C->output()->constant_table();
  917     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
  918   }
  919 }
  920 
  921 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
  922 {
  923   return MachNode::size(ra_); // too many variables; just compute it
  924                               // the hard way
  925 }
  926 
  927 int MachPrologNode::reloc() const
  928 {
  929   return 0; // a large enough number
  930 }
  931 
  932 //=============================================================================
  933 #ifndef PRODUCT
  934 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
  935 {
  936   Compile* C = ra_->C;
  937   if (generate_vzeroupper(C)) {
  938     st->print("vzeroupper");
  939     st->cr(); st->print("\t");
  940   }
  941 
  942   int framesize = C->output()->frame_size_in_bytes();
  943   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  944   // Remove word for return adr already pushed
  945   // and RBP
  946   framesize -= 2*wordSize;
  947 
  948   if (framesize) {
  949     st->print_cr("addq    rsp, %d\t# Destroy frame", framesize);
  950     st->print("\t");
  951   }
  952 
  953   st->print_cr("popq    rbp");
  954   if (do_polling() && C->is_method_compilation()) {
  955     st->print("\t");
  956     st->print_cr("cmpq     rsp, poll_offset[r15_thread] \n\t"
  957                  "ja       #safepoint_stub\t"
  958                  "# Safepoint: poll for GC");
  959   }
  960 }
  961 #endif
  962 
  963 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
  964 {
  965   Compile* C = ra_->C;
  966   MacroAssembler _masm(&cbuf);
  967 
  968   if (generate_vzeroupper(C)) {
  969     // Clear upper bits of YMM registers when current compiled code uses
  970     // wide vectors to avoid AVX <-> SSE transition penalty during call.
  971     __ vzeroupper();
  972   }
  973 
  974   int framesize = C->output()->frame_size_in_bytes();
  975   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
  976   // Remove word for return adr already pushed
  977   // and RBP
  978   framesize -= 2*wordSize;
  979 
  980   // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
  981 
  982   if (framesize) {
  983     emit_opcode(cbuf, Assembler::REX_W);
  984     if (framesize < 0x80) {
  985       emit_opcode(cbuf, 0x83); // addq rsp, #framesize
  986       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
  987       emit_d8(cbuf, framesize);
  988     } else {
  989       emit_opcode(cbuf, 0x81); // addq rsp, #framesize
  990       emit_rm(cbuf, 0x3, 0x00, RSP_enc);
  991       emit_d32(cbuf, framesize);
  992     }
  993   }
  994 
  995   // popq rbp
  996   emit_opcode(cbuf, 0x58 | RBP_enc);
  997 
  998   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
  999     __ reserved_stack_check();
 1000   }
 1001 
 1002   if (do_polling() && C->is_method_compilation()) {
 1003     MacroAssembler _masm(&cbuf);
 1004     Label dummy_label;
 1005     Label* code_stub = &dummy_label;
 1006     if (!C->output()->in_scratch_emit_size()) {
 1007       code_stub = &C->output()->safepoint_poll_table()->add_safepoint(__ offset());
 1008     }
 1009     __ relocate(relocInfo::poll_return_type);
 1010     __ safepoint_poll(*code_stub, r15_thread, true /* at_return */, true /* in_nmethod */);
 1011   }
 1012 }
 1013 
 1014 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
 1015 {
 1016   return MachNode::size(ra_); // too many variables; just compute it
 1017                               // the hard way
 1018 }
 1019 
 1020 int MachEpilogNode::reloc() const
 1021 {
 1022   return 2; // a large enough number
 1023 }
 1024 
 1025 const Pipeline* MachEpilogNode::pipeline() const
 1026 {
 1027   return MachNode::pipeline_class();
 1028 }
 1029 
 1030 //=============================================================================
 1031 
 1032 enum RC {
 1033   rc_bad,
 1034   rc_int,
 1035   rc_kreg,
 1036   rc_float,
 1037   rc_stack
 1038 };
 1039 
 1040 static enum RC rc_class(OptoReg::Name reg)
 1041 {
 1042   if( !OptoReg::is_valid(reg)  ) return rc_bad;
 1043 
 1044   if (OptoReg::is_stack(reg)) return rc_stack;
 1045 
 1046   VMReg r = OptoReg::as_VMReg(reg);
 1047 
 1048   if (r->is_Register()) return rc_int;
 1049 
 1050   if (r->is_KRegister()) return rc_kreg;
 1051 
 1052   assert(r->is_XMMRegister(), "must be");
 1053   return rc_float;
 1054 }
 1055 
 1056 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
 1057 static void vec_mov_helper(CodeBuffer *cbuf, int src_lo, int dst_lo,
 1058                           int src_hi, int dst_hi, uint ireg, outputStream* st);
 1059 
 1060 void vec_spill_helper(CodeBuffer *cbuf, bool is_load,
 1061                      int stack_offset, int reg, uint ireg, outputStream* st);
 1062 
 1063 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
 1064                                       int dst_offset, uint ireg, outputStream* st) {
 1065   if (cbuf) {
 1066     MacroAssembler _masm(cbuf);
 1067     switch (ireg) {
 1068     case Op_VecS:
 1069       __ movq(Address(rsp, -8), rax);
 1070       __ movl(rax, Address(rsp, src_offset));
 1071       __ movl(Address(rsp, dst_offset), rax);
 1072       __ movq(rax, Address(rsp, -8));
 1073       break;
 1074     case Op_VecD:
 1075       __ pushq(Address(rsp, src_offset));
 1076       __ popq (Address(rsp, dst_offset));
 1077       break;
 1078     case Op_VecX:
 1079       __ pushq(Address(rsp, src_offset));
 1080       __ popq (Address(rsp, dst_offset));
 1081       __ pushq(Address(rsp, src_offset+8));
 1082       __ popq (Address(rsp, dst_offset+8));
 1083       break;
 1084     case Op_VecY:
 1085       __ vmovdqu(Address(rsp, -32), xmm0);
 1086       __ vmovdqu(xmm0, Address(rsp, src_offset));
 1087       __ vmovdqu(Address(rsp, dst_offset), xmm0);
 1088       __ vmovdqu(xmm0, Address(rsp, -32));
 1089       break;
 1090     case Op_VecZ:
 1091       __ evmovdquq(Address(rsp, -64), xmm0, 2);
 1092       __ evmovdquq(xmm0, Address(rsp, src_offset), 2);
 1093       __ evmovdquq(Address(rsp, dst_offset), xmm0, 2);
 1094       __ evmovdquq(xmm0, Address(rsp, -64), 2);
 1095       break;
 1096     default:
 1097       ShouldNotReachHere();
 1098     }
 1099 #ifndef PRODUCT
 1100   } else {
 1101     switch (ireg) {
 1102     case Op_VecS:
 1103       st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1104                 "movl    rax, [rsp + #%d]\n\t"
 1105                 "movl    [rsp + #%d], rax\n\t"
 1106                 "movq    rax, [rsp - #8]",
 1107                 src_offset, dst_offset);
 1108       break;
 1109     case Op_VecD:
 1110       st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1111                 "popq    [rsp + #%d]",
 1112                 src_offset, dst_offset);
 1113       break;
 1114      case Op_VecX:
 1115       st->print("pushq   [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
 1116                 "popq    [rsp + #%d]\n\t"
 1117                 "pushq   [rsp + #%d]\n\t"
 1118                 "popq    [rsp + #%d]",
 1119                 src_offset, dst_offset, src_offset+8, dst_offset+8);
 1120       break;
 1121     case Op_VecY:
 1122       st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
 1123                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1124                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1125                 "vmovdqu xmm0, [rsp - #32]",
 1126                 src_offset, dst_offset);
 1127       break;
 1128     case Op_VecZ:
 1129       st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
 1130                 "vmovdqu xmm0, [rsp + #%d]\n\t"
 1131                 "vmovdqu [rsp + #%d], xmm0\n\t"
 1132                 "vmovdqu xmm0, [rsp - #64]",
 1133                 src_offset, dst_offset);
 1134       break;
 1135     default:
 1136       ShouldNotReachHere();
 1137     }
 1138 #endif
 1139   }
 1140 }
 1141 
 1142 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
 1143                                        PhaseRegAlloc* ra_,
 1144                                        bool do_size,
 1145                                        outputStream* st) const {
 1146   assert(cbuf != NULL || st  != NULL, "sanity");
 1147   // Get registers to move
 1148   OptoReg::Name src_second = ra_->get_reg_second(in(1));
 1149   OptoReg::Name src_first = ra_->get_reg_first(in(1));
 1150   OptoReg::Name dst_second = ra_->get_reg_second(this);
 1151   OptoReg::Name dst_first = ra_->get_reg_first(this);
 1152 
 1153   enum RC src_second_rc = rc_class(src_second);
 1154   enum RC src_first_rc = rc_class(src_first);
 1155   enum RC dst_second_rc = rc_class(dst_second);
 1156   enum RC dst_first_rc = rc_class(dst_first);
 1157 
 1158   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
 1159          "must move at least 1 register" );
 1160 
 1161   if (src_first == dst_first && src_second == dst_second) {
 1162     // Self copy, no move
 1163     return 0;
 1164   }
 1165   if (bottom_type()->isa_vect() != NULL && bottom_type()->isa_vectmask() == NULL) {
 1166     uint ireg = ideal_reg();
 1167     assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
 1168     assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
 1169     if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
 1170       // mem -> mem
 1171       int src_offset = ra_->reg2offset(src_first);
 1172       int dst_offset = ra_->reg2offset(dst_first);
 1173       vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
 1174     } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
 1175       vec_mov_helper(cbuf, src_first, dst_first, src_second, dst_second, ireg, st);
 1176     } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
 1177       int stack_offset = ra_->reg2offset(dst_first);
 1178       vec_spill_helper(cbuf, false, stack_offset, src_first, ireg, st);
 1179     } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
 1180       int stack_offset = ra_->reg2offset(src_first);
 1181       vec_spill_helper(cbuf, true,  stack_offset, dst_first, ireg, st);
 1182     } else {
 1183       ShouldNotReachHere();
 1184     }
 1185     return 0;
 1186   }
 1187   if (src_first_rc == rc_stack) {
 1188     // mem ->
 1189     if (dst_first_rc == rc_stack) {
 1190       // mem -> mem
 1191       assert(src_second != dst_first, "overlap");
 1192       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1193           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1194         // 64-bit
 1195         int src_offset = ra_->reg2offset(src_first);
 1196         int dst_offset = ra_->reg2offset(dst_first);
 1197         if (cbuf) {
 1198           MacroAssembler _masm(cbuf);
 1199           __ pushq(Address(rsp, src_offset));
 1200           __ popq (Address(rsp, dst_offset));
 1201 #ifndef PRODUCT
 1202         } else {
 1203           st->print("pushq   [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
 1204                     "popq    [rsp + #%d]",
 1205                      src_offset, dst_offset);
 1206 #endif
 1207         }
 1208       } else {
 1209         // 32-bit
 1210         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1211         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1212         // No pushl/popl, so:
 1213         int src_offset = ra_->reg2offset(src_first);
 1214         int dst_offset = ra_->reg2offset(dst_first);
 1215         if (cbuf) {
 1216           MacroAssembler _masm(cbuf);
 1217           __ movq(Address(rsp, -8), rax);
 1218           __ movl(rax, Address(rsp, src_offset));
 1219           __ movl(Address(rsp, dst_offset), rax);
 1220           __ movq(rax, Address(rsp, -8));
 1221 #ifndef PRODUCT
 1222         } else {
 1223           st->print("movq    [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
 1224                     "movl    rax, [rsp + #%d]\n\t"
 1225                     "movl    [rsp + #%d], rax\n\t"
 1226                     "movq    rax, [rsp - #8]",
 1227                      src_offset, dst_offset);
 1228 #endif
 1229         }
 1230       }
 1231       return 0;
 1232     } else if (dst_first_rc == rc_int) {
 1233       // mem -> gpr
 1234       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1235           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1236         // 64-bit
 1237         int offset = ra_->reg2offset(src_first);
 1238         if (cbuf) {
 1239           MacroAssembler _masm(cbuf);
 1240           __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1241 #ifndef PRODUCT
 1242         } else {
 1243           st->print("movq    %s, [rsp + #%d]\t# spill",
 1244                      Matcher::regName[dst_first],
 1245                      offset);
 1246 #endif
 1247         }
 1248       } else {
 1249         // 32-bit
 1250         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1251         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1252         int offset = ra_->reg2offset(src_first);
 1253         if (cbuf) {
 1254           MacroAssembler _masm(cbuf);
 1255           __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1256 #ifndef PRODUCT
 1257         } else {
 1258           st->print("movl    %s, [rsp + #%d]\t# spill",
 1259                      Matcher::regName[dst_first],
 1260                      offset);
 1261 #endif
 1262         }
 1263       }
 1264       return 0;
 1265     } else if (dst_first_rc == rc_float) {
 1266       // mem-> xmm
 1267       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1268           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1269         // 64-bit
 1270         int offset = ra_->reg2offset(src_first);
 1271         if (cbuf) {
 1272           MacroAssembler _masm(cbuf);
 1273           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1274 #ifndef PRODUCT
 1275         } else {
 1276           st->print("%s  %s, [rsp + #%d]\t# spill",
 1277                      UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
 1278                      Matcher::regName[dst_first],
 1279                      offset);
 1280 #endif
 1281         }
 1282       } else {
 1283         // 32-bit
 1284         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1285         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1286         int offset = ra_->reg2offset(src_first);
 1287         if (cbuf) {
 1288           MacroAssembler _masm(cbuf);
 1289           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1290 #ifndef PRODUCT
 1291         } else {
 1292           st->print("movss   %s, [rsp + #%d]\t# spill",
 1293                      Matcher::regName[dst_first],
 1294                      offset);
 1295 #endif
 1296         }
 1297       }
 1298       return 0;
 1299     } else if (dst_first_rc == rc_kreg) {
 1300       // mem -> kreg
 1301       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1302           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1303         // 64-bit
 1304         int offset = ra_->reg2offset(src_first);
 1305         if (cbuf) {
 1306           MacroAssembler _masm(cbuf);
 1307           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
 1308 #ifndef PRODUCT
 1309         } else {
 1310           st->print("kmovq   %s, [rsp + #%d]\t# spill",
 1311                      Matcher::regName[dst_first],
 1312                      offset);
 1313 #endif
 1314         }
 1315       }
 1316       return 0;
 1317     }
 1318   } else if (src_first_rc == rc_int) {
 1319     // gpr ->
 1320     if (dst_first_rc == rc_stack) {
 1321       // gpr -> mem
 1322       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1323           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1324         // 64-bit
 1325         int offset = ra_->reg2offset(dst_first);
 1326         if (cbuf) {
 1327           MacroAssembler _masm(cbuf);
 1328           __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1329 #ifndef PRODUCT
 1330         } else {
 1331           st->print("movq    [rsp + #%d], %s\t# spill",
 1332                      offset,
 1333                      Matcher::regName[src_first]);
 1334 #endif
 1335         }
 1336       } else {
 1337         // 32-bit
 1338         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1339         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1340         int offset = ra_->reg2offset(dst_first);
 1341         if (cbuf) {
 1342           MacroAssembler _masm(cbuf);
 1343           __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
 1344 #ifndef PRODUCT
 1345         } else {
 1346           st->print("movl    [rsp + #%d], %s\t# spill",
 1347                      offset,
 1348                      Matcher::regName[src_first]);
 1349 #endif
 1350         }
 1351       }
 1352       return 0;
 1353     } else if (dst_first_rc == rc_int) {
 1354       // gpr -> gpr
 1355       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1356           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1357         // 64-bit
 1358         if (cbuf) {
 1359           MacroAssembler _masm(cbuf);
 1360           __ movq(as_Register(Matcher::_regEncode[dst_first]),
 1361                   as_Register(Matcher::_regEncode[src_first]));
 1362 #ifndef PRODUCT
 1363         } else {
 1364           st->print("movq    %s, %s\t# spill",
 1365                      Matcher::regName[dst_first],
 1366                      Matcher::regName[src_first]);
 1367 #endif
 1368         }
 1369         return 0;
 1370       } else {
 1371         // 32-bit
 1372         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1373         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1374         if (cbuf) {
 1375           MacroAssembler _masm(cbuf);
 1376           __ movl(as_Register(Matcher::_regEncode[dst_first]),
 1377                   as_Register(Matcher::_regEncode[src_first]));
 1378 #ifndef PRODUCT
 1379         } else {
 1380           st->print("movl    %s, %s\t# spill",
 1381                      Matcher::regName[dst_first],
 1382                      Matcher::regName[src_first]);
 1383 #endif
 1384         }
 1385         return 0;
 1386       }
 1387     } else if (dst_first_rc == rc_float) {
 1388       // gpr -> xmm
 1389       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1390           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1391         // 64-bit
 1392         if (cbuf) {
 1393           MacroAssembler _masm(cbuf);
 1394           __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1395 #ifndef PRODUCT
 1396         } else {
 1397           st->print("movdq   %s, %s\t# spill",
 1398                      Matcher::regName[dst_first],
 1399                      Matcher::regName[src_first]);
 1400 #endif
 1401         }
 1402       } else {
 1403         // 32-bit
 1404         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1405         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1406         if (cbuf) {
 1407           MacroAssembler _masm(cbuf);
 1408           __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1409 #ifndef PRODUCT
 1410         } else {
 1411           st->print("movdl   %s, %s\t# spill",
 1412                      Matcher::regName[dst_first],
 1413                      Matcher::regName[src_first]);
 1414 #endif
 1415         }
 1416       }
 1417       return 0;
 1418     } else if (dst_first_rc == rc_kreg) {
 1419       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1420           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1421         // 64-bit
 1422         if (cbuf) {
 1423           MacroAssembler _masm(cbuf);
 1424           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
 1425   #ifndef PRODUCT
 1426         } else {
 1427            st->print("kmovq   %s, %s\t# spill",
 1428                        Matcher::regName[dst_first],
 1429                        Matcher::regName[src_first]);
 1430   #endif
 1431         }
 1432       }
 1433       Unimplemented();
 1434       return 0;
 1435     }
 1436   } else if (src_first_rc == rc_float) {
 1437     // xmm ->
 1438     if (dst_first_rc == rc_stack) {
 1439       // xmm -> mem
 1440       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1441           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1442         // 64-bit
 1443         int offset = ra_->reg2offset(dst_first);
 1444         if (cbuf) {
 1445           MacroAssembler _masm(cbuf);
 1446           __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1447 #ifndef PRODUCT
 1448         } else {
 1449           st->print("movsd   [rsp + #%d], %s\t# spill",
 1450                      offset,
 1451                      Matcher::regName[src_first]);
 1452 #endif
 1453         }
 1454       } else {
 1455         // 32-bit
 1456         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1457         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1458         int offset = ra_->reg2offset(dst_first);
 1459         if (cbuf) {
 1460           MacroAssembler _masm(cbuf);
 1461           __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
 1462 #ifndef PRODUCT
 1463         } else {
 1464           st->print("movss   [rsp + #%d], %s\t# spill",
 1465                      offset,
 1466                      Matcher::regName[src_first]);
 1467 #endif
 1468         }
 1469       }
 1470       return 0;
 1471     } else if (dst_first_rc == rc_int) {
 1472       // xmm -> gpr
 1473       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1474           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1475         // 64-bit
 1476         if (cbuf) {
 1477           MacroAssembler _masm(cbuf);
 1478           __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1479 #ifndef PRODUCT
 1480         } else {
 1481           st->print("movdq   %s, %s\t# spill",
 1482                      Matcher::regName[dst_first],
 1483                      Matcher::regName[src_first]);
 1484 #endif
 1485         }
 1486       } else {
 1487         // 32-bit
 1488         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1489         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1490         if (cbuf) {
 1491           MacroAssembler _masm(cbuf);
 1492           __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1493 #ifndef PRODUCT
 1494         } else {
 1495           st->print("movdl   %s, %s\t# spill",
 1496                      Matcher::regName[dst_first],
 1497                      Matcher::regName[src_first]);
 1498 #endif
 1499         }
 1500       }
 1501       return 0;
 1502     } else if (dst_first_rc == rc_float) {
 1503       // xmm -> xmm
 1504       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1505           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1506         // 64-bit
 1507         if (cbuf) {
 1508           MacroAssembler _masm(cbuf);
 1509           __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1510 #ifndef PRODUCT
 1511         } else {
 1512           st->print("%s  %s, %s\t# spill",
 1513                      UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
 1514                      Matcher::regName[dst_first],
 1515                      Matcher::regName[src_first]);
 1516 #endif
 1517         }
 1518       } else {
 1519         // 32-bit
 1520         assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
 1521         assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
 1522         if (cbuf) {
 1523           MacroAssembler _masm(cbuf);
 1524           __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
 1525 #ifndef PRODUCT
 1526         } else {
 1527           st->print("%s  %s, %s\t# spill",
 1528                      UseXmmRegToRegMoveAll ? "movaps" : "movss ",
 1529                      Matcher::regName[dst_first],
 1530                      Matcher::regName[src_first]);
 1531 #endif
 1532         }
 1533       }
 1534       return 0;
 1535     } else if (dst_first_rc == rc_kreg) {
 1536       assert(false, "Illegal spilling");
 1537       return 0;
 1538     }
 1539   } else if (src_first_rc == rc_kreg) {
 1540     if (dst_first_rc == rc_stack) {
 1541       // mem -> kreg
 1542       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1543           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1544         // 64-bit
 1545         int offset = ra_->reg2offset(dst_first);
 1546         if (cbuf) {
 1547           MacroAssembler _masm(cbuf);
 1548           __ kmov(Address(rsp, offset), as_KRegister(Matcher::_regEncode[src_first]));
 1549 #ifndef PRODUCT
 1550         } else {
 1551           st->print("kmovq   [rsp + #%d] , %s\t# spill",
 1552                      offset,
 1553                      Matcher::regName[src_first]);
 1554 #endif
 1555         }
 1556       }
 1557       return 0;
 1558     } else if (dst_first_rc == rc_int) {
 1559       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1560           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1561         // 64-bit
 1562         if (cbuf) {
 1563           MacroAssembler _masm(cbuf);
 1564           __ kmov(as_Register(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1565 #ifndef PRODUCT
 1566         } else {
 1567          st->print("kmovq   %s, %s\t# spill",
 1568                      Matcher::regName[dst_first],
 1569                      Matcher::regName[src_first]);
 1570 #endif
 1571         }
 1572       }
 1573       Unimplemented();
 1574       return 0;
 1575     } else if (dst_first_rc == rc_kreg) {
 1576       if ((src_first & 1) == 0 && src_first + 1 == src_second &&
 1577           (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
 1578         // 64-bit
 1579         if (cbuf) {
 1580           MacroAssembler _masm(cbuf);
 1581           __ kmov(as_KRegister(Matcher::_regEncode[dst_first]), as_KRegister(Matcher::_regEncode[src_first]));
 1582 #ifndef PRODUCT
 1583         } else {
 1584          st->print("kmovq   %s, %s\t# spill",
 1585                      Matcher::regName[dst_first],
 1586                      Matcher::regName[src_first]);
 1587 #endif
 1588         }
 1589       }
 1590       return 0;
 1591     } else if (dst_first_rc == rc_float) {
 1592       assert(false, "Illegal spill");
 1593       return 0;
 1594     }
 1595   }
 1596 
 1597   assert(0," foo ");
 1598   Unimplemented();
 1599   return 0;
 1600 }
 1601 
 1602 #ifndef PRODUCT
 1603 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
 1604   implementation(NULL, ra_, false, st);
 1605 }
 1606 #endif
 1607 
 1608 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1609   implementation(&cbuf, ra_, false, NULL);
 1610 }
 1611 
 1612 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1613   return MachNode::size(ra_);
 1614 }
 1615 
 1616 //=============================================================================
 1617 #ifndef PRODUCT
 1618 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1619 {
 1620   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1621   int reg = ra_->get_reg_first(this);
 1622   st->print("leaq    %s, [rsp + #%d]\t# box lock",
 1623             Matcher::regName[reg], offset);
 1624 }
 1625 #endif
 1626 
 1627 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1628 {
 1629   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1630   int reg = ra_->get_encode(this);
 1631   if (offset >= 0x80) {
 1632     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
 1633     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
 1634     emit_rm(cbuf, 0x2, reg & 7, 0x04);
 1635     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
 1636     emit_d32(cbuf, offset);
 1637   } else {
 1638     emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
 1639     emit_opcode(cbuf, 0x8D); // LEA  reg,[SP+offset]
 1640     emit_rm(cbuf, 0x1, reg & 7, 0x04);
 1641     emit_rm(cbuf, 0x0, 0x04, RSP_enc);
 1642     emit_d8(cbuf, offset);
 1643   }
 1644 }
 1645 
 1646 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
 1647 {
 1648   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1649   return (offset < 0x80) ? 5 : 8; // REX
 1650 }
 1651 
 1652 //=============================================================================
 1653 #ifndef PRODUCT
 1654 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
 1655 {
 1656   if (UseCompressedClassPointers) {
 1657     st->print_cr("movl    rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
 1658     st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
 1659     st->print_cr("\tcmpq    rax, rscratch1\t # Inline cache check");
 1660   } else {
 1661     st->print_cr("\tcmpq    rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
 1662                  "# Inline cache check");
 1663   }
 1664   st->print_cr("\tjne     SharedRuntime::_ic_miss_stub");
 1665   st->print_cr("\tnop\t# nops to align entry point");
 1666 }
 1667 #endif
 1668 
 1669 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
 1670 {
 1671   MacroAssembler masm(&cbuf);
 1672   uint insts_size = cbuf.insts_size();
 1673   if (UseCompressedClassPointers) {
 1674     masm.load_klass(rscratch1, j_rarg0, rscratch2);
 1675     masm.cmpptr(rax, rscratch1);
 1676   } else {
 1677     masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
 1678   }
 1679 
 1680   masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
 1681 
 1682   /* WARNING these NOPs are critical so that verified entry point is properly
 1683      4 bytes aligned for patching by NativeJump::patch_verified_entry() */
 1684   int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
 1685   if (OptoBreakpoint) {
 1686     // Leave space for int3
 1687     nops_cnt -= 1;
 1688   }
 1689   nops_cnt &= 0x3; // Do not add nops if code is aligned.
 1690   if (nops_cnt > 0)
 1691     masm.nop(nops_cnt);
 1692 }
 1693 
 1694 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
 1695 {
 1696   return MachNode::size(ra_); // too many variables; just compute it
 1697                               // the hard way
 1698 }
 1699 
 1700 
 1701 //=============================================================================
 1702 
 1703 const bool Matcher::supports_vector_calling_convention(void) {
 1704   if (EnableVectorSupport && UseVectorStubs) {
 1705     return true;
 1706   }
 1707   return false;
 1708 }
 1709 
 1710 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1711   assert(EnableVectorSupport && UseVectorStubs, "sanity");
 1712   int lo = XMM0_num;
 1713   int hi = XMM0b_num;
 1714   if (ideal_reg == Op_VecX) hi = XMM0d_num;
 1715   else if (ideal_reg == Op_VecY) hi = XMM0h_num;
 1716   else if (ideal_reg == Op_VecZ) hi = XMM0p_num;
 1717   return OptoRegPair(hi, lo);
 1718 }
 1719 
 1720 // Is this branch offset short enough that a short branch can be used?
 1721 //
 1722 // NOTE: If the platform does not provide any short branch variants, then
 1723 //       this method should return false for offset 0.
 1724 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1725   // The passed offset is relative to address of the branch.
 1726   // On 86 a branch displacement is calculated relative to address
 1727   // of a next instruction.
 1728   offset -= br_size;
 1729 
 1730   // the short version of jmpConUCF2 contains multiple branches,
 1731   // making the reach slightly less
 1732   if (rule == jmpConUCF2_rule)
 1733     return (-126 <= offset && offset <= 125);
 1734   return (-128 <= offset && offset <= 127);
 1735 }
 1736 
 1737 // Return whether or not this register is ever used as an argument.
 1738 // This function is used on startup to build the trampoline stubs in
 1739 // generateOptoStub.  Registers not mentioned will be killed by the VM
 1740 // call in the trampoline, and arguments in those registers not be
 1741 // available to the callee.
 1742 bool Matcher::can_be_java_arg(int reg)
 1743 {
 1744   return
 1745     reg ==  RDI_num || reg == RDI_H_num ||
 1746     reg ==  RSI_num || reg == RSI_H_num ||
 1747     reg ==  RDX_num || reg == RDX_H_num ||
 1748     reg ==  RCX_num || reg == RCX_H_num ||
 1749     reg ==   R8_num || reg ==  R8_H_num ||
 1750     reg ==   R9_num || reg ==  R9_H_num ||
 1751     reg ==  R12_num || reg == R12_H_num ||
 1752     reg == XMM0_num || reg == XMM0b_num ||
 1753     reg == XMM1_num || reg == XMM1b_num ||
 1754     reg == XMM2_num || reg == XMM2b_num ||
 1755     reg == XMM3_num || reg == XMM3b_num ||
 1756     reg == XMM4_num || reg == XMM4b_num ||
 1757     reg == XMM5_num || reg == XMM5b_num ||
 1758     reg == XMM6_num || reg == XMM6b_num ||
 1759     reg == XMM7_num || reg == XMM7b_num;
 1760 }
 1761 
 1762 bool Matcher::is_spillable_arg(int reg)
 1763 {
 1764   return can_be_java_arg(reg);
 1765 }
 1766 
 1767 uint Matcher::int_pressure_limit()
 1768 {
 1769   return (INTPRESSURE == -1) ? _INT_REG_mask.Size() : INTPRESSURE;
 1770 }
 1771 
 1772 uint Matcher::float_pressure_limit()
 1773 {
 1774   // After experiment around with different values, the following default threshold
 1775   // works best for LCM's register pressure scheduling on x64.
 1776   uint dec_count  = VM_Version::supports_evex() ? 4 : 2;
 1777   uint default_float_pressure_threshold = _FLOAT_REG_mask.Size() - dec_count;
 1778   return (FLOATPRESSURE == -1) ? default_float_pressure_threshold : FLOATPRESSURE;
 1779 }
 1780 
 1781 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
 1782   // In 64 bit mode a code which use multiply when
 1783   // devisor is constant is faster than hardware
 1784   // DIV instruction (it uses MulHiL).
 1785   return false;
 1786 }
 1787 
 1788 // Register for DIVI projection of divmodI
 1789 RegMask Matcher::divI_proj_mask() {
 1790   return INT_RAX_REG_mask();
 1791 }
 1792 
 1793 // Register for MODI projection of divmodI
 1794 RegMask Matcher::modI_proj_mask() {
 1795   return INT_RDX_REG_mask();
 1796 }
 1797 
 1798 // Register for DIVL projection of divmodL
 1799 RegMask Matcher::divL_proj_mask() {
 1800   return LONG_RAX_REG_mask();
 1801 }
 1802 
 1803 // Register for MODL projection of divmodL
 1804 RegMask Matcher::modL_proj_mask() {
 1805   return LONG_RDX_REG_mask();
 1806 }
 1807 
 1808 // Register for saving SP into on method handle invokes. Not used on x86_64.
 1809 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1810     return NO_REG_mask();
 1811 }
 1812 
 1813 %}
 1814 
 1815 //----------ENCODING BLOCK-----------------------------------------------------
 1816 // This block specifies the encoding classes used by the compiler to
 1817 // output byte streams.  Encoding classes are parameterized macros
 1818 // used by Machine Instruction Nodes in order to generate the bit
 1819 // encoding of the instruction.  Operands specify their base encoding
 1820 // interface with the interface keyword.  There are currently
 1821 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
 1822 // COND_INTER.  REG_INTER causes an operand to generate a function
 1823 // which returns its register number when queried.  CONST_INTER causes
 1824 // an operand to generate a function which returns the value of the
 1825 // constant when queried.  MEMORY_INTER causes an operand to generate
 1826 // four functions which return the Base Register, the Index Register,
 1827 // the Scale Value, and the Offset Value of the operand when queried.
 1828 // COND_INTER causes an operand to generate six functions which return
 1829 // the encoding code (ie - encoding bits for the instruction)
 1830 // associated with each basic boolean condition for a conditional
 1831 // instruction.
 1832 //
 1833 // Instructions specify two basic values for encoding.  Again, a
 1834 // function is available to check if the constant displacement is an
 1835 // oop. They use the ins_encode keyword to specify their encoding
 1836 // classes (which must be a sequence of enc_class names, and their
 1837 // parameters, specified in the encoding block), and they use the
 1838 // opcode keyword to specify, in order, their primary, secondary, and
 1839 // tertiary opcode.  Only the opcode sections which a particular
 1840 // instruction needs for encoding need to be specified.
 1841 encode %{
 1842   // Build emit functions for each basic byte or larger field in the
 1843   // intel encoding scheme (opcode, rm, sib, immediate), and call them
 1844   // from C++ code in the enc_class source block.  Emit functions will
 1845   // live in the main source block for now.  In future, we can
 1846   // generalize this by adding a syntax that specifies the sizes of
 1847   // fields in an order, so that the adlc can build the emit functions
 1848   // automagically
 1849 
 1850   // Emit primary opcode
 1851   enc_class OpcP
 1852   %{
 1853     emit_opcode(cbuf, $primary);
 1854   %}
 1855 
 1856   // Emit secondary opcode
 1857   enc_class OpcS
 1858   %{
 1859     emit_opcode(cbuf, $secondary);
 1860   %}
 1861 
 1862   // Emit tertiary opcode
 1863   enc_class OpcT
 1864   %{
 1865     emit_opcode(cbuf, $tertiary);
 1866   %}
 1867 
 1868   // Emit opcode directly
 1869   enc_class Opcode(immI d8)
 1870   %{
 1871     emit_opcode(cbuf, $d8$$constant);
 1872   %}
 1873 
 1874   // Emit size prefix
 1875   enc_class SizePrefix
 1876   %{
 1877     emit_opcode(cbuf, 0x66);
 1878   %}
 1879 
 1880   enc_class reg(rRegI reg)
 1881   %{
 1882     emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
 1883   %}
 1884 
 1885   enc_class reg_reg(rRegI dst, rRegI src)
 1886   %{
 1887     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
 1888   %}
 1889 
 1890   enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
 1891   %{
 1892     emit_opcode(cbuf, $opcode$$constant);
 1893     emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
 1894   %}
 1895 
 1896   enc_class cdql_enc(no_rax_rdx_RegI div)
 1897   %{
 1898     // Full implementation of Java idiv and irem; checks for
 1899     // special case as described in JVM spec., p.243 & p.271.
 1900     //
 1901     //         normal case                           special case
 1902     //
 1903     // input : rax: dividend                         min_int
 1904     //         reg: divisor                          -1
 1905     //
 1906     // output: rax: quotient  (= rax idiv reg)       min_int
 1907     //         rdx: remainder (= rax irem reg)       0
 1908     //
 1909     //  Code sequnce:
 1910     //
 1911     //    0:   3d 00 00 00 80          cmp    $0x80000000,%eax
 1912     //    5:   75 07/08                jne    e <normal>
 1913     //    7:   33 d2                   xor    %edx,%edx
 1914     //  [div >= 8 -> offset + 1]
 1915     //  [REX_B]
 1916     //    9:   83 f9 ff                cmp    $0xffffffffffffffff,$div
 1917     //    c:   74 03/04                je     11 <done>
 1918     // 000000000000000e <normal>:
 1919     //    e:   99                      cltd
 1920     //  [div >= 8 -> offset + 1]
 1921     //  [REX_B]
 1922     //    f:   f7 f9                   idiv   $div
 1923     // 0000000000000011 <done>:
 1924     MacroAssembler _masm(&cbuf);
 1925     Label normal;
 1926     Label done;
 1927 
 1928     // cmp    $0x80000000,%eax
 1929     __ cmp(as_Register(RAX_enc), 0x80000000);
 1930 
 1931     // jne    e <normal>
 1932     __ jccb(Assembler::notEqual, normal);
 1933 
 1934     // xor    %edx,%edx
 1935     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1936 
 1937     // cmp    $0xffffffffffffffff,%ecx
 1938     __ cmpl($div$$Register, -1);
 1939 
 1940     // je     11 <done>
 1941     __ jccb(Assembler::equal, done);
 1942 
 1943     // <normal>
 1944     // cltd
 1945     __ bind(normal);
 1946     __ cdql();
 1947 
 1948     // idivl
 1949     // <done>
 1950     __ idivl($div$$Register);
 1951     __ bind(done);
 1952   %}
 1953 
 1954   enc_class cdqq_enc(no_rax_rdx_RegL div)
 1955   %{
 1956     // Full implementation of Java ldiv and lrem; checks for
 1957     // special case as described in JVM spec., p.243 & p.271.
 1958     //
 1959     //         normal case                           special case
 1960     //
 1961     // input : rax: dividend                         min_long
 1962     //         reg: divisor                          -1
 1963     //
 1964     // output: rax: quotient  (= rax idiv reg)       min_long
 1965     //         rdx: remainder (= rax irem reg)       0
 1966     //
 1967     //  Code sequnce:
 1968     //
 1969     //    0:   48 ba 00 00 00 00 00    mov    $0x8000000000000000,%rdx
 1970     //    7:   00 00 80
 1971     //    a:   48 39 d0                cmp    %rdx,%rax
 1972     //    d:   75 08                   jne    17 <normal>
 1973     //    f:   33 d2                   xor    %edx,%edx
 1974     //   11:   48 83 f9 ff             cmp    $0xffffffffffffffff,$div
 1975     //   15:   74 05                   je     1c <done>
 1976     // 0000000000000017 <normal>:
 1977     //   17:   48 99                   cqto
 1978     //   19:   48 f7 f9                idiv   $div
 1979     // 000000000000001c <done>:
 1980     MacroAssembler _masm(&cbuf);
 1981     Label normal;
 1982     Label done;
 1983 
 1984     // mov    $0x8000000000000000,%rdx
 1985     __ mov64(as_Register(RDX_enc), 0x8000000000000000);
 1986 
 1987     // cmp    %rdx,%rax
 1988     __ cmpq(as_Register(RAX_enc), as_Register(RDX_enc));
 1989 
 1990     // jne    17 <normal>
 1991     __ jccb(Assembler::notEqual, normal);
 1992 
 1993     // xor    %edx,%edx
 1994     __ xorl(as_Register(RDX_enc), as_Register(RDX_enc));
 1995 
 1996     // cmp    $0xffffffffffffffff,$div
 1997     __ cmpq($div$$Register, -1);
 1998 
 1999     // je     1e <done>
 2000     __ jccb(Assembler::equal, done);
 2001 
 2002     // <normal>
 2003     // cqto
 2004     __ bind(normal);
 2005     __ cdqq();
 2006 
 2007     // idivq (note: must be emitted by the user of this rule)
 2008     // <done>
 2009     __ idivq($div$$Register);
 2010     __ bind(done);
 2011   %}
 2012 
 2013   // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
 2014   enc_class OpcSE(immI imm)
 2015   %{
 2016     // Emit primary opcode and set sign-extend bit
 2017     // Check for 8-bit immediate, and set sign extend bit in opcode
 2018     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2019       emit_opcode(cbuf, $primary | 0x02);
 2020     } else {
 2021       // 32-bit immediate
 2022       emit_opcode(cbuf, $primary);
 2023     }
 2024   %}
 2025 
 2026   enc_class OpcSErm(rRegI dst, immI imm)
 2027   %{
 2028     // OpcSEr/m
 2029     int dstenc = $dst$$reg;
 2030     if (dstenc >= 8) {
 2031       emit_opcode(cbuf, Assembler::REX_B);
 2032       dstenc -= 8;
 2033     }
 2034     // Emit primary opcode and set sign-extend bit
 2035     // Check for 8-bit immediate, and set sign extend bit in opcode
 2036     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2037       emit_opcode(cbuf, $primary | 0x02);
 2038     } else {
 2039       // 32-bit immediate
 2040       emit_opcode(cbuf, $primary);
 2041     }
 2042     // Emit r/m byte with secondary opcode, after primary opcode.
 2043     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2044   %}
 2045 
 2046   enc_class OpcSErm_wide(rRegL dst, immI imm)
 2047   %{
 2048     // OpcSEr/m
 2049     int dstenc = $dst$$reg;
 2050     if (dstenc < 8) {
 2051       emit_opcode(cbuf, Assembler::REX_W);
 2052     } else {
 2053       emit_opcode(cbuf, Assembler::REX_WB);
 2054       dstenc -= 8;
 2055     }
 2056     // Emit primary opcode and set sign-extend bit
 2057     // Check for 8-bit immediate, and set sign extend bit in opcode
 2058     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2059       emit_opcode(cbuf, $primary | 0x02);
 2060     } else {
 2061       // 32-bit immediate
 2062       emit_opcode(cbuf, $primary);
 2063     }
 2064     // Emit r/m byte with secondary opcode, after primary opcode.
 2065     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2066   %}
 2067 
 2068   enc_class Con8or32(immI imm)
 2069   %{
 2070     // Check for 8-bit immediate, and set sign extend bit in opcode
 2071     if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
 2072       $$$emit8$imm$$constant;
 2073     } else {
 2074       // 32-bit immediate
 2075       $$$emit32$imm$$constant;
 2076     }
 2077   %}
 2078 
 2079   enc_class opc2_reg(rRegI dst)
 2080   %{
 2081     // BSWAP
 2082     emit_cc(cbuf, $secondary, $dst$$reg);
 2083   %}
 2084 
 2085   enc_class opc3_reg(rRegI dst)
 2086   %{
 2087     // BSWAP
 2088     emit_cc(cbuf, $tertiary, $dst$$reg);
 2089   %}
 2090 
 2091   enc_class reg_opc(rRegI div)
 2092   %{
 2093     // INC, DEC, IDIV, IMOD, JMP indirect, ...
 2094     emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
 2095   %}
 2096 
 2097   enc_class enc_cmov(cmpOp cop)
 2098   %{
 2099     // CMOV
 2100     $$$emit8$primary;
 2101     emit_cc(cbuf, $secondary, $cop$$cmpcode);
 2102   %}
 2103 
 2104   enc_class enc_PartialSubtypeCheck()
 2105   %{
 2106     Register Rrdi = as_Register(RDI_enc); // result register
 2107     Register Rrax = as_Register(RAX_enc); // super class
 2108     Register Rrcx = as_Register(RCX_enc); // killed
 2109     Register Rrsi = as_Register(RSI_enc); // sub class
 2110     Label miss;
 2111     const bool set_cond_codes = true;
 2112 
 2113     MacroAssembler _masm(&cbuf);
 2114     __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
 2115                                      NULL, &miss,
 2116                                      /*set_cond_codes:*/ true);
 2117     if ($primary) {
 2118       __ xorptr(Rrdi, Rrdi);
 2119     }
 2120     __ bind(miss);
 2121   %}
 2122 
 2123   enc_class clear_avx %{
 2124     debug_only(int off0 = cbuf.insts_size());
 2125     if (generate_vzeroupper(Compile::current())) {
 2126       // Clear upper bits of YMM registers to avoid AVX <-> SSE transition penalty
 2127       // Clear upper bits of YMM registers when current compiled code uses
 2128       // wide vectors to avoid AVX <-> SSE transition penalty during call.
 2129       MacroAssembler _masm(&cbuf);
 2130       __ vzeroupper();
 2131     }
 2132     debug_only(int off1 = cbuf.insts_size());
 2133     assert(off1 - off0 == clear_avx_size(), "correct size prediction");
 2134   %}
 2135 
 2136   enc_class Java_To_Runtime(method meth) %{
 2137     // No relocation needed
 2138     MacroAssembler _masm(&cbuf);
 2139     __ mov64(r10, (int64_t) $meth$$method);
 2140     __ call(r10);

 2141   %}
 2142 
 2143   enc_class Java_To_Interpreter(method meth)
 2144   %{
 2145     // CALL Java_To_Interpreter
 2146     // This is the instruction starting address for relocation info.
 2147     cbuf.set_insts_mark();
 2148     $$$emit8$primary;
 2149     // CALL directly to the runtime
 2150     emit_d32_reloc(cbuf,
 2151                    (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2152                    runtime_call_Relocation::spec(),
 2153                    RELOC_DISP32);

 2154   %}
 2155 
 2156   enc_class Java_Static_Call(method meth)
 2157   %{
 2158     // JAVA STATIC CALL
 2159     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to
 2160     // determine who we intended to call.

 2161     cbuf.set_insts_mark();
 2162     $$$emit8$primary;
 2163 
 2164     if (!_method) {
 2165       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2166                      runtime_call_Relocation::spec(),
 2167                      RELOC_DISP32);
 2168     } else {
 2169       int method_index = resolved_method_index(cbuf);
 2170       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
 2171                                                   : static_call_Relocation::spec(method_index);
 2172       emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
 2173                      rspec, RELOC_DISP32);
 2174       // Emit stubs for static call.
 2175       address mark = cbuf.insts_mark();
 2176       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
 2177       if (stub == NULL) {
 2178         ciEnv::current()->record_failure("CodeCache is full");
 2179         return;
 2180       }
 2181     }

 2182   %}
 2183 
 2184   enc_class Java_Dynamic_Call(method meth) %{
 2185     MacroAssembler _masm(&cbuf);
 2186     __ ic_call((address)$meth$$method, resolved_method_index(cbuf));

 2187   %}
 2188 
 2189   enc_class Java_Compiled_Call(method meth)
 2190   %{
 2191     // JAVA COMPILED CALL
 2192     int disp = in_bytes(Method:: from_compiled_offset());
 2193 
 2194     // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
 2195     // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
 2196 
 2197     // callq *disp(%rax)

 2198     cbuf.set_insts_mark();
 2199     $$$emit8$primary;
 2200     if (disp < 0x80) {
 2201       emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
 2202       emit_d8(cbuf, disp); // Displacement
 2203     } else {
 2204       emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
 2205       emit_d32(cbuf, disp); // Displacement
 2206     }

 2207   %}
 2208 
 2209   enc_class reg_opc_imm(rRegI dst, immI8 shift)
 2210   %{
 2211     // SAL, SAR, SHR
 2212     int dstenc = $dst$$reg;
 2213     if (dstenc >= 8) {
 2214       emit_opcode(cbuf, Assembler::REX_B);
 2215       dstenc -= 8;
 2216     }
 2217     $$$emit8$primary;
 2218     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2219     $$$emit8$shift$$constant;
 2220   %}
 2221 
 2222   enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
 2223   %{
 2224     // SAL, SAR, SHR
 2225     int dstenc = $dst$$reg;
 2226     if (dstenc < 8) {
 2227       emit_opcode(cbuf, Assembler::REX_W);
 2228     } else {
 2229       emit_opcode(cbuf, Assembler::REX_WB);
 2230       dstenc -= 8;
 2231     }
 2232     $$$emit8$primary;
 2233     emit_rm(cbuf, 0x3, $secondary, dstenc);
 2234     $$$emit8$shift$$constant;
 2235   %}
 2236 
 2237   enc_class load_immI(rRegI dst, immI src)
 2238   %{
 2239     int dstenc = $dst$$reg;
 2240     if (dstenc >= 8) {
 2241       emit_opcode(cbuf, Assembler::REX_B);
 2242       dstenc -= 8;
 2243     }
 2244     emit_opcode(cbuf, 0xB8 | dstenc);
 2245     $$$emit32$src$$constant;
 2246   %}
 2247 
 2248   enc_class load_immL(rRegL dst, immL src)
 2249   %{
 2250     int dstenc = $dst$$reg;
 2251     if (dstenc < 8) {
 2252       emit_opcode(cbuf, Assembler::REX_W);
 2253     } else {
 2254       emit_opcode(cbuf, Assembler::REX_WB);
 2255       dstenc -= 8;
 2256     }
 2257     emit_opcode(cbuf, 0xB8 | dstenc);
 2258     emit_d64(cbuf, $src$$constant);
 2259   %}
 2260 
 2261   enc_class load_immUL32(rRegL dst, immUL32 src)
 2262   %{
 2263     // same as load_immI, but this time we care about zeroes in the high word
 2264     int dstenc = $dst$$reg;
 2265     if (dstenc >= 8) {
 2266       emit_opcode(cbuf, Assembler::REX_B);
 2267       dstenc -= 8;
 2268     }
 2269     emit_opcode(cbuf, 0xB8 | dstenc);
 2270     $$$emit32$src$$constant;
 2271   %}
 2272 
 2273   enc_class load_immL32(rRegL dst, immL32 src)
 2274   %{
 2275     int dstenc = $dst$$reg;
 2276     if (dstenc < 8) {
 2277       emit_opcode(cbuf, Assembler::REX_W);
 2278     } else {
 2279       emit_opcode(cbuf, Assembler::REX_WB);
 2280       dstenc -= 8;
 2281     }
 2282     emit_opcode(cbuf, 0xC7);
 2283     emit_rm(cbuf, 0x03, 0x00, dstenc);
 2284     $$$emit32$src$$constant;
 2285   %}
 2286 
 2287   enc_class load_immP31(rRegP dst, immP32 src)
 2288   %{
 2289     // same as load_immI, but this time we care about zeroes in the high word
 2290     int dstenc = $dst$$reg;
 2291     if (dstenc >= 8) {
 2292       emit_opcode(cbuf, Assembler::REX_B);
 2293       dstenc -= 8;
 2294     }
 2295     emit_opcode(cbuf, 0xB8 | dstenc);
 2296     $$$emit32$src$$constant;
 2297   %}
 2298 
 2299   enc_class load_immP(rRegP dst, immP src)
 2300   %{
 2301     int dstenc = $dst$$reg;
 2302     if (dstenc < 8) {
 2303       emit_opcode(cbuf, Assembler::REX_W);
 2304     } else {
 2305       emit_opcode(cbuf, Assembler::REX_WB);
 2306       dstenc -= 8;
 2307     }
 2308     emit_opcode(cbuf, 0xB8 | dstenc);
 2309     // This next line should be generated from ADLC
 2310     if ($src->constant_reloc() != relocInfo::none) {
 2311       emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
 2312     } else {
 2313       emit_d64(cbuf, $src$$constant);
 2314     }
 2315   %}
 2316 
 2317   enc_class Con32(immI src)
 2318   %{
 2319     // Output immediate
 2320     $$$emit32$src$$constant;
 2321   %}
 2322 
 2323   enc_class Con32F_as_bits(immF src)
 2324   %{
 2325     // Output Float immediate bits
 2326     jfloat jf = $src$$constant;
 2327     jint jf_as_bits = jint_cast(jf);
 2328     emit_d32(cbuf, jf_as_bits);
 2329   %}
 2330 
 2331   enc_class Con16(immI src)
 2332   %{
 2333     // Output immediate
 2334     $$$emit16$src$$constant;
 2335   %}
 2336 
 2337   // How is this different from Con32??? XXX
 2338   enc_class Con_d32(immI src)
 2339   %{
 2340     emit_d32(cbuf,$src$$constant);
 2341   %}
 2342 
 2343   enc_class conmemref (rRegP t1) %{    // Con32(storeImmI)
 2344     // Output immediate memory reference
 2345     emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
 2346     emit_d32(cbuf, 0x00);
 2347   %}
 2348 
 2349   enc_class lock_prefix()
 2350   %{
 2351     emit_opcode(cbuf, 0xF0); // lock
 2352   %}
 2353 
 2354   enc_class REX_mem(memory mem)
 2355   %{
 2356     if ($mem$$base >= 8) {
 2357       if ($mem$$index < 8) {
 2358         emit_opcode(cbuf, Assembler::REX_B);
 2359       } else {
 2360         emit_opcode(cbuf, Assembler::REX_XB);
 2361       }
 2362     } else {
 2363       if ($mem$$index >= 8) {
 2364         emit_opcode(cbuf, Assembler::REX_X);
 2365       }
 2366     }
 2367   %}
 2368 
 2369   enc_class REX_mem_wide(memory mem)
 2370   %{
 2371     if ($mem$$base >= 8) {
 2372       if ($mem$$index < 8) {
 2373         emit_opcode(cbuf, Assembler::REX_WB);
 2374       } else {
 2375         emit_opcode(cbuf, Assembler::REX_WXB);
 2376       }
 2377     } else {
 2378       if ($mem$$index < 8) {
 2379         emit_opcode(cbuf, Assembler::REX_W);
 2380       } else {
 2381         emit_opcode(cbuf, Assembler::REX_WX);
 2382       }
 2383     }
 2384   %}
 2385 
 2386   // for byte regs
 2387   enc_class REX_breg(rRegI reg)
 2388   %{
 2389     if ($reg$$reg >= 4) {
 2390       emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
 2391     }
 2392   %}
 2393 
 2394   // for byte regs
 2395   enc_class REX_reg_breg(rRegI dst, rRegI src)
 2396   %{
 2397     if ($dst$$reg < 8) {
 2398       if ($src$$reg >= 4) {
 2399         emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
 2400       }
 2401     } else {
 2402       if ($src$$reg < 8) {
 2403         emit_opcode(cbuf, Assembler::REX_R);
 2404       } else {
 2405         emit_opcode(cbuf, Assembler::REX_RB);
 2406       }
 2407     }
 2408   %}
 2409 
 2410   // for byte regs
 2411   enc_class REX_breg_mem(rRegI reg, memory mem)
 2412   %{
 2413     if ($reg$$reg < 8) {
 2414       if ($mem$$base < 8) {
 2415         if ($mem$$index >= 8) {
 2416           emit_opcode(cbuf, Assembler::REX_X);
 2417         } else if ($reg$$reg >= 4) {
 2418           emit_opcode(cbuf, Assembler::REX);
 2419         }
 2420       } else {
 2421         if ($mem$$index < 8) {
 2422           emit_opcode(cbuf, Assembler::REX_B);
 2423         } else {
 2424           emit_opcode(cbuf, Assembler::REX_XB);
 2425         }
 2426       }
 2427     } else {
 2428       if ($mem$$base < 8) {
 2429         if ($mem$$index < 8) {
 2430           emit_opcode(cbuf, Assembler::REX_R);
 2431         } else {
 2432           emit_opcode(cbuf, Assembler::REX_RX);
 2433         }
 2434       } else {
 2435         if ($mem$$index < 8) {
 2436           emit_opcode(cbuf, Assembler::REX_RB);
 2437         } else {
 2438           emit_opcode(cbuf, Assembler::REX_RXB);
 2439         }
 2440       }
 2441     }
 2442   %}
 2443 
 2444   enc_class REX_reg(rRegI reg)
 2445   %{
 2446     if ($reg$$reg >= 8) {
 2447       emit_opcode(cbuf, Assembler::REX_B);
 2448     }
 2449   %}
 2450 
 2451   enc_class REX_reg_wide(rRegI reg)
 2452   %{
 2453     if ($reg$$reg < 8) {
 2454       emit_opcode(cbuf, Assembler::REX_W);
 2455     } else {
 2456       emit_opcode(cbuf, Assembler::REX_WB);
 2457     }
 2458   %}
 2459 
 2460   enc_class REX_reg_reg(rRegI dst, rRegI src)
 2461   %{
 2462     if ($dst$$reg < 8) {
 2463       if ($src$$reg >= 8) {
 2464         emit_opcode(cbuf, Assembler::REX_B);
 2465       }
 2466     } else {
 2467       if ($src$$reg < 8) {
 2468         emit_opcode(cbuf, Assembler::REX_R);
 2469       } else {
 2470         emit_opcode(cbuf, Assembler::REX_RB);
 2471       }
 2472     }
 2473   %}
 2474 
 2475   enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
 2476   %{
 2477     if ($dst$$reg < 8) {
 2478       if ($src$$reg < 8) {
 2479         emit_opcode(cbuf, Assembler::REX_W);
 2480       } else {
 2481         emit_opcode(cbuf, Assembler::REX_WB);
 2482       }
 2483     } else {
 2484       if ($src$$reg < 8) {
 2485         emit_opcode(cbuf, Assembler::REX_WR);
 2486       } else {
 2487         emit_opcode(cbuf, Assembler::REX_WRB);
 2488       }
 2489     }
 2490   %}
 2491 
 2492   enc_class REX_reg_mem(rRegI reg, memory mem)
 2493   %{
 2494     if ($reg$$reg < 8) {
 2495       if ($mem$$base < 8) {
 2496         if ($mem$$index >= 8) {
 2497           emit_opcode(cbuf, Assembler::REX_X);
 2498         }
 2499       } else {
 2500         if ($mem$$index < 8) {
 2501           emit_opcode(cbuf, Assembler::REX_B);
 2502         } else {
 2503           emit_opcode(cbuf, Assembler::REX_XB);
 2504         }
 2505       }
 2506     } else {
 2507       if ($mem$$base < 8) {
 2508         if ($mem$$index < 8) {
 2509           emit_opcode(cbuf, Assembler::REX_R);
 2510         } else {
 2511           emit_opcode(cbuf, Assembler::REX_RX);
 2512         }
 2513       } else {
 2514         if ($mem$$index < 8) {
 2515           emit_opcode(cbuf, Assembler::REX_RB);
 2516         } else {
 2517           emit_opcode(cbuf, Assembler::REX_RXB);
 2518         }
 2519       }
 2520     }
 2521   %}
 2522 
 2523   enc_class REX_reg_mem_wide(rRegL reg, memory mem)
 2524   %{
 2525     if ($reg$$reg < 8) {
 2526       if ($mem$$base < 8) {
 2527         if ($mem$$index < 8) {
 2528           emit_opcode(cbuf, Assembler::REX_W);
 2529         } else {
 2530           emit_opcode(cbuf, Assembler::REX_WX);
 2531         }
 2532       } else {
 2533         if ($mem$$index < 8) {
 2534           emit_opcode(cbuf, Assembler::REX_WB);
 2535         } else {
 2536           emit_opcode(cbuf, Assembler::REX_WXB);
 2537         }
 2538       }
 2539     } else {
 2540       if ($mem$$base < 8) {
 2541         if ($mem$$index < 8) {
 2542           emit_opcode(cbuf, Assembler::REX_WR);
 2543         } else {
 2544           emit_opcode(cbuf, Assembler::REX_WRX);
 2545         }
 2546       } else {
 2547         if ($mem$$index < 8) {
 2548           emit_opcode(cbuf, Assembler::REX_WRB);
 2549         } else {
 2550           emit_opcode(cbuf, Assembler::REX_WRXB);
 2551         }
 2552       }
 2553     }
 2554   %}
 2555 
 2556   enc_class reg_mem(rRegI ereg, memory mem)
 2557   %{
 2558     // High registers handle in encode_RegMem
 2559     int reg = $ereg$$reg;
 2560     int base = $mem$$base;
 2561     int index = $mem$$index;
 2562     int scale = $mem$$scale;
 2563     int disp = $mem$$disp;
 2564     relocInfo::relocType disp_reloc = $mem->disp_reloc();
 2565 
 2566     encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
 2567   %}
 2568 
 2569   enc_class RM_opc_mem(immI rm_opcode, memory mem)
 2570   %{
 2571     int rm_byte_opcode = $rm_opcode$$constant;
 2572 
 2573     // High registers handle in encode_RegMem
 2574     int base = $mem$$base;
 2575     int index = $mem$$index;
 2576     int scale = $mem$$scale;
 2577     int displace = $mem$$disp;
 2578 
 2579     relocInfo::relocType disp_reloc = $mem->disp_reloc();       // disp-as-oop when
 2580                                             // working with static
 2581                                             // globals
 2582     encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
 2583                   disp_reloc);
 2584   %}
 2585 
 2586   enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
 2587   %{
 2588     int reg_encoding = $dst$$reg;
 2589     int base         = $src0$$reg;      // 0xFFFFFFFF indicates no base
 2590     int index        = 0x04;            // 0x04 indicates no index
 2591     int scale        = 0x00;            // 0x00 indicates no scale
 2592     int displace     = $src1$$constant; // 0x00 indicates no displacement
 2593     relocInfo::relocType disp_reloc = relocInfo::none;
 2594     encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
 2595                   disp_reloc);
 2596   %}
 2597 
 2598   enc_class neg_reg(rRegI dst)
 2599   %{
 2600     int dstenc = $dst$$reg;
 2601     if (dstenc >= 8) {
 2602       emit_opcode(cbuf, Assembler::REX_B);
 2603       dstenc -= 8;
 2604     }
 2605     // NEG $dst
 2606     emit_opcode(cbuf, 0xF7);
 2607     emit_rm(cbuf, 0x3, 0x03, dstenc);
 2608   %}
 2609 
 2610   enc_class neg_reg_wide(rRegI dst)
 2611   %{
 2612     int dstenc = $dst$$reg;
 2613     if (dstenc < 8) {
 2614       emit_opcode(cbuf, Assembler::REX_W);
 2615     } else {
 2616       emit_opcode(cbuf, Assembler::REX_WB);
 2617       dstenc -= 8;
 2618     }
 2619     // NEG $dst
 2620     emit_opcode(cbuf, 0xF7);
 2621     emit_rm(cbuf, 0x3, 0x03, dstenc);
 2622   %}
 2623 
 2624   enc_class setLT_reg(rRegI dst)
 2625   %{
 2626     int dstenc = $dst$$reg;
 2627     if (dstenc >= 8) {
 2628       emit_opcode(cbuf, Assembler::REX_B);
 2629       dstenc -= 8;
 2630     } else if (dstenc >= 4) {
 2631       emit_opcode(cbuf, Assembler::REX);
 2632     }
 2633     // SETLT $dst
 2634     emit_opcode(cbuf, 0x0F);
 2635     emit_opcode(cbuf, 0x9C);
 2636     emit_rm(cbuf, 0x3, 0x0, dstenc);
 2637   %}
 2638 
 2639   enc_class setNZ_reg(rRegI dst)
 2640   %{
 2641     int dstenc = $dst$$reg;
 2642     if (dstenc >= 8) {
 2643       emit_opcode(cbuf, Assembler::REX_B);
 2644       dstenc -= 8;
 2645     } else if (dstenc >= 4) {
 2646       emit_opcode(cbuf, Assembler::REX);
 2647     }
 2648     // SETNZ $dst
 2649     emit_opcode(cbuf, 0x0F);
 2650     emit_opcode(cbuf, 0x95);
 2651     emit_rm(cbuf, 0x3, 0x0, dstenc);
 2652   %}
 2653 
 2654 
 2655   // Compare the lonogs and set -1, 0, or 1 into dst
 2656   enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
 2657   %{
 2658     int src1enc = $src1$$reg;
 2659     int src2enc = $src2$$reg;
 2660     int dstenc = $dst$$reg;
 2661 
 2662     // cmpq $src1, $src2
 2663     if (src1enc < 8) {
 2664       if (src2enc < 8) {
 2665         emit_opcode(cbuf, Assembler::REX_W);
 2666       } else {
 2667         emit_opcode(cbuf, Assembler::REX_WB);
 2668       }
 2669     } else {
 2670       if (src2enc < 8) {
 2671         emit_opcode(cbuf, Assembler::REX_WR);
 2672       } else {
 2673         emit_opcode(cbuf, Assembler::REX_WRB);
 2674       }
 2675     }
 2676     emit_opcode(cbuf, 0x3B);
 2677     emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
 2678 
 2679     // movl $dst, -1
 2680     if (dstenc >= 8) {
 2681       emit_opcode(cbuf, Assembler::REX_B);
 2682     }
 2683     emit_opcode(cbuf, 0xB8 | (dstenc & 7));
 2684     emit_d32(cbuf, -1);
 2685 
 2686     // jl,s done
 2687     emit_opcode(cbuf, 0x7C);
 2688     emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
 2689 
 2690     // setne $dst
 2691     if (dstenc >= 4) {
 2692       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
 2693     }
 2694     emit_opcode(cbuf, 0x0F);
 2695     emit_opcode(cbuf, 0x95);
 2696     emit_opcode(cbuf, 0xC0 | (dstenc & 7));
 2697 
 2698     // movzbl $dst, $dst
 2699     if (dstenc >= 4) {
 2700       emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
 2701     }
 2702     emit_opcode(cbuf, 0x0F);
 2703     emit_opcode(cbuf, 0xB6);
 2704     emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
 2705   %}
 2706 
 2707   enc_class Push_ResultXD(regD dst) %{
 2708     MacroAssembler _masm(&cbuf);
 2709     __ fstp_d(Address(rsp, 0));
 2710     __ movdbl($dst$$XMMRegister, Address(rsp, 0));
 2711     __ addptr(rsp, 8);
 2712   %}
 2713 
 2714   enc_class Push_SrcXD(regD src) %{
 2715     MacroAssembler _masm(&cbuf);
 2716     __ subptr(rsp, 8);
 2717     __ movdbl(Address(rsp, 0), $src$$XMMRegister);
 2718     __ fld_d(Address(rsp, 0));
 2719   %}
 2720 
 2721 
 2722   enc_class enc_rethrow()
 2723   %{
 2724     cbuf.set_insts_mark();
 2725     emit_opcode(cbuf, 0xE9); // jmp entry
 2726     emit_d32_reloc(cbuf,
 2727                    (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
 2728                    runtime_call_Relocation::spec(),
 2729                    RELOC_DISP32);
 2730   %}
 2731 
 2732 %}
 2733 
 2734 
 2735 
 2736 //----------FRAME--------------------------------------------------------------
 2737 // Definition of frame structure and management information.
 2738 //
 2739 //  S T A C K   L A Y O U T    Allocators stack-slot number
 2740 //                             |   (to get allocators register number
 2741 //  G  Owned by    |        |  v    add OptoReg::stack0())
 2742 //  r   CALLER     |        |
 2743 //  o     |        +--------+      pad to even-align allocators stack-slot
 2744 //  w     V        |  pad0  |        numbers; owned by CALLER
 2745 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
 2746 //  h     ^        |   in   |  5
 2747 //        |        |  args  |  4   Holes in incoming args owned by SELF
 2748 //  |     |        |        |  3
 2749 //  |     |        +--------+
 2750 //  V     |        | old out|      Empty on Intel, window on Sparc
 2751 //        |    old |preserve|      Must be even aligned.
 2752 //        |     SP-+--------+----> Matcher::_old_SP, even aligned
 2753 //        |        |   in   |  3   area for Intel ret address
 2754 //     Owned by    |preserve|      Empty on Sparc.
 2755 //       SELF      +--------+
 2756 //        |        |  pad2  |  2   pad to align old SP
 2757 //        |        +--------+  1
 2758 //        |        | locks  |  0
 2759 //        |        +--------+----> OptoReg::stack0(), even aligned
 2760 //        |        |  pad1  | 11   pad to align new SP
 2761 //        |        +--------+
 2762 //        |        |        | 10
 2763 //        |        | spills |  9   spills
 2764 //        V        |        |  8   (pad0 slot for callee)
 2765 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
 2766 //        ^        |  out   |  7
 2767 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
 2768 //     Owned by    +--------+
 2769 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
 2770 //        |    new |preserve|      Must be even-aligned.
 2771 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
 2772 //        |        |        |
 2773 //
 2774 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
 2775 //         known from SELF's arguments and the Java calling convention.
 2776 //         Region 6-7 is determined per call site.
 2777 // Note 2: If the calling convention leaves holes in the incoming argument
 2778 //         area, those holes are owned by SELF.  Holes in the outgoing area
 2779 //         are owned by the CALLEE.  Holes should not be nessecary in the
 2780 //         incoming area, as the Java calling convention is completely under
 2781 //         the control of the AD file.  Doubles can be sorted and packed to
 2782 //         avoid holes.  Holes in the outgoing arguments may be nessecary for
 2783 //         varargs C calling conventions.
 2784 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
 2785 //         even aligned with pad0 as needed.
 2786 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
 2787 //         region 6-11 is even aligned; it may be padded out more so that
 2788 //         the region from SP to FP meets the minimum stack alignment.
 2789 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
 2790 //         alignment.  Region 11, pad1, may be dynamically extended so that
 2791 //         SP meets the minimum alignment.
 2792 
 2793 frame
 2794 %{
 2795   // These three registers define part of the calling convention
 2796   // between compiled code and the interpreter.
 2797   inline_cache_reg(RAX);                // Inline Cache Register
 2798 
 2799   // Optional: name the operand used by cisc-spilling to access
 2800   // [stack_pointer + offset]
 2801   cisc_spilling_operand_name(indOffset32);
 2802 
 2803   // Number of stack slots consumed by locking an object
 2804   sync_stack_slots(2);
 2805 
 2806   // Compiled code's Frame Pointer
 2807   frame_pointer(RSP);
 2808 
 2809   // Interpreter stores its frame pointer in a register which is
 2810   // stored to the stack by I2CAdaptors.
 2811   // I2CAdaptors convert from interpreted java to compiled java.
 2812   interpreter_frame_pointer(RBP);
 2813 
 2814   // Stack alignment requirement
 2815   stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
 2816 
 2817   // Number of outgoing stack slots killed above the out_preserve_stack_slots
 2818   // for calls to C.  Supports the var-args backing area for register parms.
 2819   varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
 2820 
 2821   // The after-PROLOG location of the return address.  Location of
 2822   // return address specifies a type (REG or STACK) and a number
 2823   // representing the register number (i.e. - use a register name) or
 2824   // stack slot.
 2825   // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
 2826   // Otherwise, it is above the locks and verification slot and alignment word
 2827   return_addr(STACK - 2 +
 2828               align_up((Compile::current()->in_preserve_stack_slots() +
 2829                         Compile::current()->fixed_slots()),
 2830                        stack_alignment_in_slots()));
 2831 
 2832   // Location of compiled Java return values.  Same as C for now.
 2833   return_value
 2834   %{
 2835     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
 2836            "only return normal values");
 2837 
 2838     static const int lo[Op_RegL + 1] = {
 2839       0,
 2840       0,
 2841       RAX_num,  // Op_RegN
 2842       RAX_num,  // Op_RegI
 2843       RAX_num,  // Op_RegP
 2844       XMM0_num, // Op_RegF
 2845       XMM0_num, // Op_RegD
 2846       RAX_num   // Op_RegL
 2847     };
 2848     static const int hi[Op_RegL + 1] = {
 2849       0,
 2850       0,
 2851       OptoReg::Bad, // Op_RegN
 2852       OptoReg::Bad, // Op_RegI
 2853       RAX_H_num,    // Op_RegP
 2854       OptoReg::Bad, // Op_RegF
 2855       XMM0b_num,    // Op_RegD
 2856       RAX_H_num     // Op_RegL
 2857     };
 2858     // Excluded flags and vector registers.
 2859     assert(ARRAY_SIZE(hi) == _last_machine_leaf - 8, "missing type");
 2860     return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
 2861   %}
 2862 %}
 2863 
 2864 //----------ATTRIBUTES---------------------------------------------------------
 2865 //----------Operand Attributes-------------------------------------------------
 2866 op_attrib op_cost(0);        // Required cost attribute
 2867 
 2868 //----------Instruction Attributes---------------------------------------------
 2869 ins_attrib ins_cost(100);       // Required cost attribute
 2870 ins_attrib ins_size(8);         // Required size attribute (in bits)
 2871 ins_attrib ins_short_branch(0); // Required flag: is this instruction
 2872                                 // a non-matching short branch variant
 2873                                 // of some long branch?
 2874 ins_attrib ins_alignment(1);    // Required alignment attribute (must
 2875                                 // be a power of 2) specifies the
 2876                                 // alignment that some part of the
 2877                                 // instruction (not necessarily the
 2878                                 // start) requires.  If > 1, a
 2879                                 // compute_padding() function must be
 2880                                 // provided for the instruction
 2881 
 2882 //----------OPERANDS-----------------------------------------------------------
 2883 // Operand definitions must precede instruction definitions for correct parsing
 2884 // in the ADLC because operands constitute user defined types which are used in
 2885 // instruction definitions.
 2886 
 2887 //----------Simple Operands----------------------------------------------------
 2888 // Immediate Operands
 2889 // Integer Immediate
 2890 operand immI()
 2891 %{
 2892   match(ConI);
 2893 
 2894   op_cost(10);
 2895   format %{ %}
 2896   interface(CONST_INTER);
 2897 %}
 2898 
 2899 // Constant for test vs zero
 2900 operand immI_0()
 2901 %{
 2902   predicate(n->get_int() == 0);
 2903   match(ConI);
 2904 
 2905   op_cost(0);
 2906   format %{ %}
 2907   interface(CONST_INTER);
 2908 %}
 2909 
 2910 // Constant for increment
 2911 operand immI_1()
 2912 %{
 2913   predicate(n->get_int() == 1);
 2914   match(ConI);
 2915 
 2916   op_cost(0);
 2917   format %{ %}
 2918   interface(CONST_INTER);
 2919 %}
 2920 
 2921 // Constant for decrement
 2922 operand immI_M1()
 2923 %{
 2924   predicate(n->get_int() == -1);
 2925   match(ConI);
 2926 
 2927   op_cost(0);
 2928   format %{ %}
 2929   interface(CONST_INTER);
 2930 %}
 2931 
 2932 operand immI_2()
 2933 %{
 2934   predicate(n->get_int() == 2);
 2935   match(ConI);
 2936 
 2937   op_cost(0);
 2938   format %{ %}
 2939   interface(CONST_INTER);
 2940 %}
 2941 
 2942 operand immI_4()
 2943 %{
 2944   predicate(n->get_int() == 4);
 2945   match(ConI);
 2946 
 2947   op_cost(0);
 2948   format %{ %}
 2949   interface(CONST_INTER);
 2950 %}
 2951 
 2952 operand immI_8()
 2953 %{
 2954   predicate(n->get_int() == 8);
 2955   match(ConI);
 2956 
 2957   op_cost(0);
 2958   format %{ %}
 2959   interface(CONST_INTER);
 2960 %}
 2961 
 2962 // Valid scale values for addressing modes
 2963 operand immI2()
 2964 %{
 2965   predicate(0 <= n->get_int() && (n->get_int() <= 3));
 2966   match(ConI);
 2967 
 2968   format %{ %}
 2969   interface(CONST_INTER);
 2970 %}
 2971 
 2972 operand immU7()
 2973 %{
 2974   predicate((0 <= n->get_int()) && (n->get_int() <= 0x7F));
 2975   match(ConI);
 2976 
 2977   op_cost(5);
 2978   format %{ %}
 2979   interface(CONST_INTER);
 2980 %}
 2981 
 2982 operand immI8()
 2983 %{
 2984   predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
 2985   match(ConI);
 2986 
 2987   op_cost(5);
 2988   format %{ %}
 2989   interface(CONST_INTER);
 2990 %}
 2991 
 2992 operand immU8()
 2993 %{
 2994   predicate((0 <= n->get_int()) && (n->get_int() <= 255));
 2995   match(ConI);
 2996 
 2997   op_cost(5);
 2998   format %{ %}
 2999   interface(CONST_INTER);
 3000 %}
 3001 
 3002 operand immI16()
 3003 %{
 3004   predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
 3005   match(ConI);
 3006 
 3007   op_cost(10);
 3008   format %{ %}
 3009   interface(CONST_INTER);
 3010 %}
 3011 
 3012 // Int Immediate non-negative
 3013 operand immU31()
 3014 %{
 3015   predicate(n->get_int() >= 0);
 3016   match(ConI);
 3017 
 3018   op_cost(0);
 3019   format %{ %}
 3020   interface(CONST_INTER);
 3021 %}
 3022 
 3023 // Constant for long shifts
 3024 operand immI_32()
 3025 %{
 3026   predicate( n->get_int() == 32 );
 3027   match(ConI);
 3028 
 3029   op_cost(0);
 3030   format %{ %}
 3031   interface(CONST_INTER);
 3032 %}
 3033 
 3034 // Constant for long shifts
 3035 operand immI_64()
 3036 %{
 3037   predicate( n->get_int() == 64 );
 3038   match(ConI);
 3039 
 3040   op_cost(0);
 3041   format %{ %}
 3042   interface(CONST_INTER);
 3043 %}
 3044 
 3045 // Pointer Immediate
 3046 operand immP()
 3047 %{
 3048   match(ConP);
 3049 
 3050   op_cost(10);
 3051   format %{ %}
 3052   interface(CONST_INTER);
 3053 %}
 3054 
 3055 // NULL Pointer Immediate
 3056 operand immP0()
 3057 %{
 3058   predicate(n->get_ptr() == 0);
 3059   match(ConP);
 3060 
 3061   op_cost(5);
 3062   format %{ %}
 3063   interface(CONST_INTER);
 3064 %}
 3065 
 3066 // Pointer Immediate
 3067 operand immN() %{
 3068   match(ConN);
 3069 
 3070   op_cost(10);
 3071   format %{ %}
 3072   interface(CONST_INTER);
 3073 %}
 3074 
 3075 operand immNKlass() %{
 3076   match(ConNKlass);
 3077 
 3078   op_cost(10);
 3079   format %{ %}
 3080   interface(CONST_INTER);
 3081 %}
 3082 
 3083 // NULL Pointer Immediate
 3084 operand immN0() %{
 3085   predicate(n->get_narrowcon() == 0);
 3086   match(ConN);
 3087 
 3088   op_cost(5);
 3089   format %{ %}
 3090   interface(CONST_INTER);
 3091 %}
 3092 
 3093 operand immP31()
 3094 %{
 3095   predicate(n->as_Type()->type()->reloc() == relocInfo::none
 3096             && (n->get_ptr() >> 31) == 0);
 3097   match(ConP);
 3098 
 3099   op_cost(5);
 3100   format %{ %}
 3101   interface(CONST_INTER);
 3102 %}
 3103 
 3104 
 3105 // Long Immediate
 3106 operand immL()
 3107 %{
 3108   match(ConL);
 3109 
 3110   op_cost(20);
 3111   format %{ %}
 3112   interface(CONST_INTER);
 3113 %}
 3114 
 3115 // Long Immediate 8-bit
 3116 operand immL8()
 3117 %{
 3118   predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
 3119   match(ConL);
 3120 
 3121   op_cost(5);
 3122   format %{ %}
 3123   interface(CONST_INTER);
 3124 %}
 3125 
 3126 // Long Immediate 32-bit unsigned
 3127 operand immUL32()
 3128 %{
 3129   predicate(n->get_long() == (unsigned int) (n->get_long()));
 3130   match(ConL);
 3131 
 3132   op_cost(10);
 3133   format %{ %}
 3134   interface(CONST_INTER);
 3135 %}
 3136 
 3137 // Long Immediate 32-bit signed
 3138 operand immL32()
 3139 %{
 3140   predicate(n->get_long() == (int) (n->get_long()));
 3141   match(ConL);
 3142 
 3143   op_cost(15);
 3144   format %{ %}
 3145   interface(CONST_INTER);
 3146 %}
 3147 
 3148 operand immL_Pow2()
 3149 %{
 3150   predicate(is_power_of_2((julong)n->get_long()));
 3151   match(ConL);
 3152 
 3153   op_cost(15);
 3154   format %{ %}
 3155   interface(CONST_INTER);
 3156 %}
 3157 
 3158 operand immL_NotPow2()
 3159 %{
 3160   predicate(is_power_of_2((julong)~n->get_long()));
 3161   match(ConL);
 3162 
 3163   op_cost(15);
 3164   format %{ %}
 3165   interface(CONST_INTER);
 3166 %}
 3167 
 3168 // Long Immediate zero
 3169 operand immL0()
 3170 %{
 3171   predicate(n->get_long() == 0L);
 3172   match(ConL);
 3173 
 3174   op_cost(10);
 3175   format %{ %}
 3176   interface(CONST_INTER);
 3177 %}
 3178 
 3179 // Constant for increment
 3180 operand immL1()
 3181 %{
 3182   predicate(n->get_long() == 1);
 3183   match(ConL);
 3184 
 3185   format %{ %}
 3186   interface(CONST_INTER);
 3187 %}
 3188 
 3189 // Constant for decrement
 3190 operand immL_M1()
 3191 %{
 3192   predicate(n->get_long() == -1);
 3193   match(ConL);
 3194 
 3195   format %{ %}
 3196   interface(CONST_INTER);
 3197 %}
 3198 
 3199 // Long Immediate: the value 10
 3200 operand immL10()
 3201 %{
 3202   predicate(n->get_long() == 10);
 3203   match(ConL);
 3204 
 3205   format %{ %}
 3206   interface(CONST_INTER);
 3207 %}
 3208 
 3209 // Long immediate from 0 to 127.
 3210 // Used for a shorter form of long mul by 10.
 3211 operand immL_127()
 3212 %{
 3213   predicate(0 <= n->get_long() && n->get_long() < 0x80);
 3214   match(ConL);
 3215 
 3216   op_cost(10);
 3217   format %{ %}
 3218   interface(CONST_INTER);
 3219 %}
 3220 
 3221 // Long Immediate: low 32-bit mask
 3222 operand immL_32bits()
 3223 %{
 3224   predicate(n->get_long() == 0xFFFFFFFFL);
 3225   match(ConL);
 3226   op_cost(20);
 3227 
 3228   format %{ %}
 3229   interface(CONST_INTER);
 3230 %}
 3231 
 3232 // Int Immediate: 2^n-1, postive
 3233 operand immI_Pow2M1()
 3234 %{
 3235   predicate((n->get_int() > 0)
 3236             && is_power_of_2(n->get_int() + 1));
 3237   match(ConI);
 3238 
 3239   op_cost(20);
 3240   format %{ %}
 3241   interface(CONST_INTER);
 3242 %}
 3243 
 3244 // Float Immediate zero
 3245 operand immF0()
 3246 %{
 3247   predicate(jint_cast(n->getf()) == 0);
 3248   match(ConF);
 3249 
 3250   op_cost(5);
 3251   format %{ %}
 3252   interface(CONST_INTER);
 3253 %}
 3254 
 3255 // Float Immediate
 3256 operand immF()
 3257 %{
 3258   match(ConF);
 3259 
 3260   op_cost(15);
 3261   format %{ %}
 3262   interface(CONST_INTER);
 3263 %}
 3264 
 3265 // Double Immediate zero
 3266 operand immD0()
 3267 %{
 3268   predicate(jlong_cast(n->getd()) == 0);
 3269   match(ConD);
 3270 
 3271   op_cost(5);
 3272   format %{ %}
 3273   interface(CONST_INTER);
 3274 %}
 3275 
 3276 // Double Immediate
 3277 operand immD()
 3278 %{
 3279   match(ConD);
 3280 
 3281   op_cost(15);
 3282   format %{ %}
 3283   interface(CONST_INTER);
 3284 %}
 3285 
 3286 // Immediates for special shifts (sign extend)
 3287 
 3288 // Constants for increment
 3289 operand immI_16()
 3290 %{
 3291   predicate(n->get_int() == 16);
 3292   match(ConI);
 3293 
 3294   format %{ %}
 3295   interface(CONST_INTER);
 3296 %}
 3297 
 3298 operand immI_24()
 3299 %{
 3300   predicate(n->get_int() == 24);
 3301   match(ConI);
 3302 
 3303   format %{ %}
 3304   interface(CONST_INTER);
 3305 %}
 3306 
 3307 // Constant for byte-wide masking
 3308 operand immI_255()
 3309 %{
 3310   predicate(n->get_int() == 255);
 3311   match(ConI);
 3312 
 3313   format %{ %}
 3314   interface(CONST_INTER);
 3315 %}
 3316 
 3317 // Constant for short-wide masking
 3318 operand immI_65535()
 3319 %{
 3320   predicate(n->get_int() == 65535);
 3321   match(ConI);
 3322 
 3323   format %{ %}
 3324   interface(CONST_INTER);
 3325 %}
 3326 
 3327 // Constant for byte-wide masking
 3328 operand immL_255()
 3329 %{
 3330   predicate(n->get_long() == 255);
 3331   match(ConL);
 3332 
 3333   format %{ %}
 3334   interface(CONST_INTER);
 3335 %}
 3336 
 3337 // Constant for short-wide masking
 3338 operand immL_65535()
 3339 %{
 3340   predicate(n->get_long() == 65535);
 3341   match(ConL);
 3342 
 3343   format %{ %}
 3344   interface(CONST_INTER);
 3345 %}
 3346 
 3347 operand kReg()
 3348 %{
 3349   constraint(ALLOC_IN_RC(vectmask_reg));
 3350   match(RegVectMask);
 3351   format %{%}
 3352   interface(REG_INTER);
 3353 %}
 3354 
 3355 operand kReg_K1()
 3356 %{
 3357   constraint(ALLOC_IN_RC(vectmask_reg_K1));
 3358   match(RegVectMask);
 3359   format %{%}
 3360   interface(REG_INTER);
 3361 %}
 3362 
 3363 operand kReg_K2()
 3364 %{
 3365   constraint(ALLOC_IN_RC(vectmask_reg_K2));
 3366   match(RegVectMask);
 3367   format %{%}
 3368   interface(REG_INTER);
 3369 %}
 3370 
 3371 // Special Registers
 3372 operand kReg_K3()
 3373 %{
 3374   constraint(ALLOC_IN_RC(vectmask_reg_K3));
 3375   match(RegVectMask);
 3376   format %{%}
 3377   interface(REG_INTER);
 3378 %}
 3379 
 3380 operand kReg_K4()
 3381 %{
 3382   constraint(ALLOC_IN_RC(vectmask_reg_K4));
 3383   match(RegVectMask);
 3384   format %{%}
 3385   interface(REG_INTER);
 3386 %}
 3387 
 3388 operand kReg_K5()
 3389 %{
 3390   constraint(ALLOC_IN_RC(vectmask_reg_K5));
 3391   match(RegVectMask);
 3392   format %{%}
 3393   interface(REG_INTER);
 3394 %}
 3395 
 3396 operand kReg_K6()
 3397 %{
 3398   constraint(ALLOC_IN_RC(vectmask_reg_K6));
 3399   match(RegVectMask);
 3400   format %{%}
 3401   interface(REG_INTER);
 3402 %}
 3403 
 3404 // Special Registers
 3405 operand kReg_K7()
 3406 %{
 3407   constraint(ALLOC_IN_RC(vectmask_reg_K7));
 3408   match(RegVectMask);
 3409   format %{%}
 3410   interface(REG_INTER);
 3411 %}
 3412 
 3413 // Register Operands
 3414 // Integer Register
 3415 operand rRegI()
 3416 %{
 3417   constraint(ALLOC_IN_RC(int_reg));
 3418   match(RegI);
 3419 
 3420   match(rax_RegI);
 3421   match(rbx_RegI);
 3422   match(rcx_RegI);
 3423   match(rdx_RegI);
 3424   match(rdi_RegI);
 3425 
 3426   format %{ %}
 3427   interface(REG_INTER);
 3428 %}
 3429 
 3430 // Special Registers
 3431 operand rax_RegI()
 3432 %{
 3433   constraint(ALLOC_IN_RC(int_rax_reg));
 3434   match(RegI);
 3435   match(rRegI);
 3436 
 3437   format %{ "RAX" %}
 3438   interface(REG_INTER);
 3439 %}
 3440 
 3441 // Special Registers
 3442 operand rbx_RegI()
 3443 %{
 3444   constraint(ALLOC_IN_RC(int_rbx_reg));
 3445   match(RegI);
 3446   match(rRegI);
 3447 
 3448   format %{ "RBX" %}
 3449   interface(REG_INTER);
 3450 %}
 3451 
 3452 operand rcx_RegI()
 3453 %{
 3454   constraint(ALLOC_IN_RC(int_rcx_reg));
 3455   match(RegI);
 3456   match(rRegI);
 3457 
 3458   format %{ "RCX" %}
 3459   interface(REG_INTER);
 3460 %}
 3461 
 3462 operand rdx_RegI()
 3463 %{
 3464   constraint(ALLOC_IN_RC(int_rdx_reg));
 3465   match(RegI);
 3466   match(rRegI);
 3467 
 3468   format %{ "RDX" %}
 3469   interface(REG_INTER);
 3470 %}
 3471 
 3472 operand rdi_RegI()
 3473 %{
 3474   constraint(ALLOC_IN_RC(int_rdi_reg));
 3475   match(RegI);
 3476   match(rRegI);
 3477 
 3478   format %{ "RDI" %}
 3479   interface(REG_INTER);
 3480 %}
 3481 
 3482 operand no_rax_rdx_RegI()
 3483 %{
 3484   constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
 3485   match(RegI);
 3486   match(rbx_RegI);
 3487   match(rcx_RegI);
 3488   match(rdi_RegI);
 3489 
 3490   format %{ %}
 3491   interface(REG_INTER);
 3492 %}
 3493 
 3494 // Pointer Register
 3495 operand any_RegP()
 3496 %{
 3497   constraint(ALLOC_IN_RC(any_reg));
 3498   match(RegP);
 3499   match(rax_RegP);
 3500   match(rbx_RegP);
 3501   match(rdi_RegP);
 3502   match(rsi_RegP);
 3503   match(rbp_RegP);
 3504   match(r15_RegP);
 3505   match(rRegP);
 3506 
 3507   format %{ %}
 3508   interface(REG_INTER);
 3509 %}
 3510 
 3511 operand rRegP()
 3512 %{
 3513   constraint(ALLOC_IN_RC(ptr_reg));
 3514   match(RegP);
 3515   match(rax_RegP);
 3516   match(rbx_RegP);
 3517   match(rdi_RegP);
 3518   match(rsi_RegP);
 3519   match(rbp_RegP);  // See Q&A below about
 3520   match(r15_RegP);  // r15_RegP and rbp_RegP.
 3521 
 3522   format %{ %}
 3523   interface(REG_INTER);
 3524 %}
 3525 
 3526 operand rRegN() %{
 3527   constraint(ALLOC_IN_RC(int_reg));
 3528   match(RegN);
 3529 
 3530   format %{ %}
 3531   interface(REG_INTER);
 3532 %}
 3533 
 3534 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
 3535 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
 3536 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
 3537 // The output of an instruction is controlled by the allocator, which respects
 3538 // register class masks, not match rules.  Unless an instruction mentions
 3539 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
 3540 // by the allocator as an input.
 3541 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
 3542 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
 3543 // result, RBP is not included in the output of the instruction either.
 3544 
 3545 operand no_rax_RegP()
 3546 %{
 3547   constraint(ALLOC_IN_RC(ptr_no_rax_reg));
 3548   match(RegP);
 3549   match(rbx_RegP);
 3550   match(rsi_RegP);
 3551   match(rdi_RegP);
 3552 
 3553   format %{ %}
 3554   interface(REG_INTER);
 3555 %}
 3556 
 3557 // This operand is not allowed to use RBP even if
 3558 // RBP is not used to hold the frame pointer.
 3559 operand no_rbp_RegP()
 3560 %{
 3561   constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
 3562   match(RegP);
 3563   match(rbx_RegP);
 3564   match(rsi_RegP);
 3565   match(rdi_RegP);
 3566 
 3567   format %{ %}
 3568   interface(REG_INTER);
 3569 %}
 3570 
 3571 operand no_rax_rbx_RegP()
 3572 %{
 3573   constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
 3574   match(RegP);
 3575   match(rsi_RegP);
 3576   match(rdi_RegP);
 3577 
 3578   format %{ %}
 3579   interface(REG_INTER);
 3580 %}
 3581 
 3582 // Special Registers
 3583 // Return a pointer value
 3584 operand rax_RegP()
 3585 %{
 3586   constraint(ALLOC_IN_RC(ptr_rax_reg));
 3587   match(RegP);
 3588   match(rRegP);
 3589 
 3590   format %{ %}
 3591   interface(REG_INTER);
 3592 %}
 3593 
 3594 // Special Registers
 3595 // Return a compressed pointer value
 3596 operand rax_RegN()
 3597 %{
 3598   constraint(ALLOC_IN_RC(int_rax_reg));
 3599   match(RegN);
 3600   match(rRegN);
 3601 
 3602   format %{ %}
 3603   interface(REG_INTER);
 3604 %}
 3605 
 3606 // Used in AtomicAdd
 3607 operand rbx_RegP()
 3608 %{
 3609   constraint(ALLOC_IN_RC(ptr_rbx_reg));
 3610   match(RegP);
 3611   match(rRegP);
 3612 
 3613   format %{ %}
 3614   interface(REG_INTER);
 3615 %}
 3616 
 3617 operand rsi_RegP()
 3618 %{
 3619   constraint(ALLOC_IN_RC(ptr_rsi_reg));
 3620   match(RegP);
 3621   match(rRegP);
 3622 
 3623   format %{ %}
 3624   interface(REG_INTER);
 3625 %}
 3626 
 3627 operand rbp_RegP()
 3628 %{
 3629   constraint(ALLOC_IN_RC(ptr_rbp_reg));
 3630   match(RegP);
 3631   match(rRegP);
 3632 
 3633   format %{ %}
 3634   interface(REG_INTER);
 3635 %}
 3636 
 3637 // Used in rep stosq
 3638 operand rdi_RegP()
 3639 %{
 3640   constraint(ALLOC_IN_RC(ptr_rdi_reg));
 3641   match(RegP);
 3642   match(rRegP);
 3643 
 3644   format %{ %}
 3645   interface(REG_INTER);
 3646 %}
 3647 
 3648 operand r15_RegP()
 3649 %{
 3650   constraint(ALLOC_IN_RC(ptr_r15_reg));
 3651   match(RegP);
 3652   match(rRegP);
 3653 
 3654   format %{ %}
 3655   interface(REG_INTER);
 3656 %}
 3657 
 3658 operand rRegL()
 3659 %{
 3660   constraint(ALLOC_IN_RC(long_reg));
 3661   match(RegL);
 3662   match(rax_RegL);
 3663   match(rdx_RegL);
 3664 
 3665   format %{ %}
 3666   interface(REG_INTER);
 3667 %}
 3668 
 3669 // Special Registers
 3670 operand no_rax_rdx_RegL()
 3671 %{
 3672   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
 3673   match(RegL);
 3674   match(rRegL);
 3675 
 3676   format %{ %}
 3677   interface(REG_INTER);
 3678 %}
 3679 
 3680 operand no_rax_RegL()
 3681 %{
 3682   constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
 3683   match(RegL);
 3684   match(rRegL);
 3685   match(rdx_RegL);
 3686 
 3687   format %{ %}
 3688   interface(REG_INTER);
 3689 %}
 3690 
 3691 operand rax_RegL()
 3692 %{
 3693   constraint(ALLOC_IN_RC(long_rax_reg));
 3694   match(RegL);
 3695   match(rRegL);
 3696 
 3697   format %{ "RAX" %}
 3698   interface(REG_INTER);
 3699 %}
 3700 
 3701 operand rcx_RegL()
 3702 %{
 3703   constraint(ALLOC_IN_RC(long_rcx_reg));
 3704   match(RegL);
 3705   match(rRegL);
 3706 
 3707   format %{ %}
 3708   interface(REG_INTER);
 3709 %}
 3710 
 3711 operand rdx_RegL()
 3712 %{
 3713   constraint(ALLOC_IN_RC(long_rdx_reg));
 3714   match(RegL);
 3715   match(rRegL);
 3716 
 3717   format %{ %}
 3718   interface(REG_INTER);
 3719 %}
 3720 
 3721 // Flags register, used as output of compare instructions
 3722 operand rFlagsReg()
 3723 %{
 3724   constraint(ALLOC_IN_RC(int_flags));
 3725   match(RegFlags);
 3726 
 3727   format %{ "RFLAGS" %}
 3728   interface(REG_INTER);
 3729 %}
 3730 
 3731 // Flags register, used as output of FLOATING POINT compare instructions
 3732 operand rFlagsRegU()
 3733 %{
 3734   constraint(ALLOC_IN_RC(int_flags));
 3735   match(RegFlags);
 3736 
 3737   format %{ "RFLAGS_U" %}
 3738   interface(REG_INTER);
 3739 %}
 3740 
 3741 operand rFlagsRegUCF() %{
 3742   constraint(ALLOC_IN_RC(int_flags));
 3743   match(RegFlags);
 3744   predicate(false);
 3745 
 3746   format %{ "RFLAGS_U_CF" %}
 3747   interface(REG_INTER);
 3748 %}
 3749 
 3750 // Float register operands
 3751 operand regF() %{
 3752    constraint(ALLOC_IN_RC(float_reg));
 3753    match(RegF);
 3754 
 3755    format %{ %}
 3756    interface(REG_INTER);
 3757 %}
 3758 
 3759 // Float register operands
 3760 operand legRegF() %{
 3761    constraint(ALLOC_IN_RC(float_reg_legacy));
 3762    match(RegF);
 3763 
 3764    format %{ %}
 3765    interface(REG_INTER);
 3766 %}
 3767 
 3768 // Float register operands
 3769 operand vlRegF() %{
 3770    constraint(ALLOC_IN_RC(float_reg_vl));
 3771    match(RegF);
 3772 
 3773    format %{ %}
 3774    interface(REG_INTER);
 3775 %}
 3776 
 3777 // Double register operands
 3778 operand regD() %{
 3779    constraint(ALLOC_IN_RC(double_reg));
 3780    match(RegD);
 3781 
 3782    format %{ %}
 3783    interface(REG_INTER);
 3784 %}
 3785 
 3786 // Double register operands
 3787 operand legRegD() %{
 3788    constraint(ALLOC_IN_RC(double_reg_legacy));
 3789    match(RegD);
 3790 
 3791    format %{ %}
 3792    interface(REG_INTER);
 3793 %}
 3794 
 3795 // Double register operands
 3796 operand vlRegD() %{
 3797    constraint(ALLOC_IN_RC(double_reg_vl));
 3798    match(RegD);
 3799 
 3800    format %{ %}
 3801    interface(REG_INTER);
 3802 %}
 3803 
 3804 //----------Memory Operands----------------------------------------------------
 3805 // Direct Memory Operand
 3806 // operand direct(immP addr)
 3807 // %{
 3808 //   match(addr);
 3809 
 3810 //   format %{ "[$addr]" %}
 3811 //   interface(MEMORY_INTER) %{
 3812 //     base(0xFFFFFFFF);
 3813 //     index(0x4);
 3814 //     scale(0x0);
 3815 //     disp($addr);
 3816 //   %}
 3817 // %}
 3818 
 3819 // Indirect Memory Operand
 3820 operand indirect(any_RegP reg)
 3821 %{
 3822   constraint(ALLOC_IN_RC(ptr_reg));
 3823   match(reg);
 3824 
 3825   format %{ "[$reg]" %}
 3826   interface(MEMORY_INTER) %{
 3827     base($reg);
 3828     index(0x4);
 3829     scale(0x0);
 3830     disp(0x0);
 3831   %}
 3832 %}
 3833 
 3834 // Indirect Memory Plus Short Offset Operand
 3835 operand indOffset8(any_RegP reg, immL8 off)
 3836 %{
 3837   constraint(ALLOC_IN_RC(ptr_reg));
 3838   match(AddP reg off);
 3839 
 3840   format %{ "[$reg + $off (8-bit)]" %}
 3841   interface(MEMORY_INTER) %{
 3842     base($reg);
 3843     index(0x4);
 3844     scale(0x0);
 3845     disp($off);
 3846   %}
 3847 %}
 3848 
 3849 // Indirect Memory Plus Long Offset Operand
 3850 operand indOffset32(any_RegP reg, immL32 off)
 3851 %{
 3852   constraint(ALLOC_IN_RC(ptr_reg));
 3853   match(AddP reg off);
 3854 
 3855   format %{ "[$reg + $off (32-bit)]" %}
 3856   interface(MEMORY_INTER) %{
 3857     base($reg);
 3858     index(0x4);
 3859     scale(0x0);
 3860     disp($off);
 3861   %}
 3862 %}
 3863 
 3864 // Indirect Memory Plus Index Register Plus Offset Operand
 3865 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
 3866 %{
 3867   constraint(ALLOC_IN_RC(ptr_reg));
 3868   match(AddP (AddP reg lreg) off);
 3869 
 3870   op_cost(10);
 3871   format %{"[$reg + $off + $lreg]" %}
 3872   interface(MEMORY_INTER) %{
 3873     base($reg);
 3874     index($lreg);
 3875     scale(0x0);
 3876     disp($off);
 3877   %}
 3878 %}
 3879 
 3880 // Indirect Memory Plus Index Register Plus Offset Operand
 3881 operand indIndex(any_RegP reg, rRegL lreg)
 3882 %{
 3883   constraint(ALLOC_IN_RC(ptr_reg));
 3884   match(AddP reg lreg);
 3885 
 3886   op_cost(10);
 3887   format %{"[$reg + $lreg]" %}
 3888   interface(MEMORY_INTER) %{
 3889     base($reg);
 3890     index($lreg);
 3891     scale(0x0);
 3892     disp(0x0);
 3893   %}
 3894 %}
 3895 
 3896 // Indirect Memory Times Scale Plus Index Register
 3897 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
 3898 %{
 3899   constraint(ALLOC_IN_RC(ptr_reg));
 3900   match(AddP reg (LShiftL lreg scale));
 3901 
 3902   op_cost(10);
 3903   format %{"[$reg + $lreg << $scale]" %}
 3904   interface(MEMORY_INTER) %{
 3905     base($reg);
 3906     index($lreg);
 3907     scale($scale);
 3908     disp(0x0);
 3909   %}
 3910 %}
 3911 
 3912 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
 3913 %{
 3914   constraint(ALLOC_IN_RC(ptr_reg));
 3915   predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3916   match(AddP reg (LShiftL (ConvI2L idx) scale));
 3917 
 3918   op_cost(10);
 3919   format %{"[$reg + pos $idx << $scale]" %}
 3920   interface(MEMORY_INTER) %{
 3921     base($reg);
 3922     index($idx);
 3923     scale($scale);
 3924     disp(0x0);
 3925   %}
 3926 %}
 3927 
 3928 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 3929 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
 3930 %{
 3931   constraint(ALLOC_IN_RC(ptr_reg));
 3932   match(AddP (AddP reg (LShiftL lreg scale)) off);
 3933 
 3934   op_cost(10);
 3935   format %{"[$reg + $off + $lreg << $scale]" %}
 3936   interface(MEMORY_INTER) %{
 3937     base($reg);
 3938     index($lreg);
 3939     scale($scale);
 3940     disp($off);
 3941   %}
 3942 %}
 3943 
 3944 // Indirect Memory Plus Positive Index Register Plus Offset Operand
 3945 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
 3946 %{
 3947   constraint(ALLOC_IN_RC(ptr_reg));
 3948   predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 3949   match(AddP (AddP reg (ConvI2L idx)) off);
 3950 
 3951   op_cost(10);
 3952   format %{"[$reg + $off + $idx]" %}
 3953   interface(MEMORY_INTER) %{
 3954     base($reg);
 3955     index($idx);
 3956     scale(0x0);
 3957     disp($off);
 3958   %}
 3959 %}
 3960 
 3961 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 3962 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
 3963 %{
 3964   constraint(ALLOC_IN_RC(ptr_reg));
 3965   predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 3966   match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
 3967 
 3968   op_cost(10);
 3969   format %{"[$reg + $off + $idx << $scale]" %}
 3970   interface(MEMORY_INTER) %{
 3971     base($reg);
 3972     index($idx);
 3973     scale($scale);
 3974     disp($off);
 3975   %}
 3976 %}
 3977 
 3978 // Indirect Narrow Oop Plus Offset Operand
 3979 // Note: x86 architecture doesn't support "scale * index + offset" without a base
 3980 // we can't free r12 even with CompressedOops::base() == NULL.
 3981 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
 3982   predicate(UseCompressedOops && (CompressedOops::shift() == Address::times_8));
 3983   constraint(ALLOC_IN_RC(ptr_reg));
 3984   match(AddP (DecodeN reg) off);
 3985 
 3986   op_cost(10);
 3987   format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
 3988   interface(MEMORY_INTER) %{
 3989     base(0xc); // R12
 3990     index($reg);
 3991     scale(0x3);
 3992     disp($off);
 3993   %}
 3994 %}
 3995 
 3996 // Indirect Memory Operand
 3997 operand indirectNarrow(rRegN reg)
 3998 %{
 3999   predicate(CompressedOops::shift() == 0);
 4000   constraint(ALLOC_IN_RC(ptr_reg));
 4001   match(DecodeN reg);
 4002 
 4003   format %{ "[$reg]" %}
 4004   interface(MEMORY_INTER) %{
 4005     base($reg);
 4006     index(0x4);
 4007     scale(0x0);
 4008     disp(0x0);
 4009   %}
 4010 %}
 4011 
 4012 // Indirect Memory Plus Short Offset Operand
 4013 operand indOffset8Narrow(rRegN reg, immL8 off)
 4014 %{
 4015   predicate(CompressedOops::shift() == 0);
 4016   constraint(ALLOC_IN_RC(ptr_reg));
 4017   match(AddP (DecodeN reg) off);
 4018 
 4019   format %{ "[$reg + $off (8-bit)]" %}
 4020   interface(MEMORY_INTER) %{
 4021     base($reg);
 4022     index(0x4);
 4023     scale(0x0);
 4024     disp($off);
 4025   %}
 4026 %}
 4027 
 4028 // Indirect Memory Plus Long Offset Operand
 4029 operand indOffset32Narrow(rRegN reg, immL32 off)
 4030 %{
 4031   predicate(CompressedOops::shift() == 0);
 4032   constraint(ALLOC_IN_RC(ptr_reg));
 4033   match(AddP (DecodeN reg) off);
 4034 
 4035   format %{ "[$reg + $off (32-bit)]" %}
 4036   interface(MEMORY_INTER) %{
 4037     base($reg);
 4038     index(0x4);
 4039     scale(0x0);
 4040     disp($off);
 4041   %}
 4042 %}
 4043 
 4044 // Indirect Memory Plus Index Register Plus Offset Operand
 4045 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
 4046 %{
 4047   predicate(CompressedOops::shift() == 0);
 4048   constraint(ALLOC_IN_RC(ptr_reg));
 4049   match(AddP (AddP (DecodeN reg) lreg) off);
 4050 
 4051   op_cost(10);
 4052   format %{"[$reg + $off + $lreg]" %}
 4053   interface(MEMORY_INTER) %{
 4054     base($reg);
 4055     index($lreg);
 4056     scale(0x0);
 4057     disp($off);
 4058   %}
 4059 %}
 4060 
 4061 // Indirect Memory Plus Index Register Plus Offset Operand
 4062 operand indIndexNarrow(rRegN reg, rRegL lreg)
 4063 %{
 4064   predicate(CompressedOops::shift() == 0);
 4065   constraint(ALLOC_IN_RC(ptr_reg));
 4066   match(AddP (DecodeN reg) lreg);
 4067 
 4068   op_cost(10);
 4069   format %{"[$reg + $lreg]" %}
 4070   interface(MEMORY_INTER) %{
 4071     base($reg);
 4072     index($lreg);
 4073     scale(0x0);
 4074     disp(0x0);
 4075   %}
 4076 %}
 4077 
 4078 // Indirect Memory Times Scale Plus Index Register
 4079 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
 4080 %{
 4081   predicate(CompressedOops::shift() == 0);
 4082   constraint(ALLOC_IN_RC(ptr_reg));
 4083   match(AddP (DecodeN reg) (LShiftL lreg scale));
 4084 
 4085   op_cost(10);
 4086   format %{"[$reg + $lreg << $scale]" %}
 4087   interface(MEMORY_INTER) %{
 4088     base($reg);
 4089     index($lreg);
 4090     scale($scale);
 4091     disp(0x0);
 4092   %}
 4093 %}
 4094 
 4095 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
 4096 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
 4097 %{
 4098   predicate(CompressedOops::shift() == 0);
 4099   constraint(ALLOC_IN_RC(ptr_reg));
 4100   match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
 4101 
 4102   op_cost(10);
 4103   format %{"[$reg + $off + $lreg << $scale]" %}
 4104   interface(MEMORY_INTER) %{
 4105     base($reg);
 4106     index($lreg);
 4107     scale($scale);
 4108     disp($off);
 4109   %}
 4110 %}
 4111 
 4112 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
 4113 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
 4114 %{
 4115   constraint(ALLOC_IN_RC(ptr_reg));
 4116   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
 4117   match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
 4118 
 4119   op_cost(10);
 4120   format %{"[$reg + $off + $idx]" %}
 4121   interface(MEMORY_INTER) %{
 4122     base($reg);
 4123     index($idx);
 4124     scale(0x0);
 4125     disp($off);
 4126   %}
 4127 %}
 4128 
 4129 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
 4130 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
 4131 %{
 4132   constraint(ALLOC_IN_RC(ptr_reg));
 4133   predicate(CompressedOops::shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
 4134   match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
 4135 
 4136   op_cost(10);
 4137   format %{"[$reg + $off + $idx << $scale]" %}
 4138   interface(MEMORY_INTER) %{
 4139     base($reg);
 4140     index($idx);
 4141     scale($scale);
 4142     disp($off);
 4143   %}
 4144 %}
 4145 
 4146 //----------Special Memory Operands--------------------------------------------
 4147 // Stack Slot Operand - This operand is used for loading and storing temporary
 4148 //                      values on the stack where a match requires a value to
 4149 //                      flow through memory.
 4150 operand stackSlotP(sRegP reg)
 4151 %{
 4152   constraint(ALLOC_IN_RC(stack_slots));
 4153   // No match rule because this operand is only generated in matching
 4154 
 4155   format %{ "[$reg]" %}
 4156   interface(MEMORY_INTER) %{
 4157     base(0x4);   // RSP
 4158     index(0x4);  // No Index
 4159     scale(0x0);  // No Scale
 4160     disp($reg);  // Stack Offset
 4161   %}
 4162 %}
 4163 
 4164 operand stackSlotI(sRegI reg)
 4165 %{
 4166   constraint(ALLOC_IN_RC(stack_slots));
 4167   // No match rule because this operand is only generated in matching
 4168 
 4169   format %{ "[$reg]" %}
 4170   interface(MEMORY_INTER) %{
 4171     base(0x4);   // RSP
 4172     index(0x4);  // No Index
 4173     scale(0x0);  // No Scale
 4174     disp($reg);  // Stack Offset
 4175   %}
 4176 %}
 4177 
 4178 operand stackSlotF(sRegF reg)
 4179 %{
 4180   constraint(ALLOC_IN_RC(stack_slots));
 4181   // No match rule because this operand is only generated in matching
 4182 
 4183   format %{ "[$reg]" %}
 4184   interface(MEMORY_INTER) %{
 4185     base(0x4);   // RSP
 4186     index(0x4);  // No Index
 4187     scale(0x0);  // No Scale
 4188     disp($reg);  // Stack Offset
 4189   %}
 4190 %}
 4191 
 4192 operand stackSlotD(sRegD reg)
 4193 %{
 4194   constraint(ALLOC_IN_RC(stack_slots));
 4195   // No match rule because this operand is only generated in matching
 4196 
 4197   format %{ "[$reg]" %}
 4198   interface(MEMORY_INTER) %{
 4199     base(0x4);   // RSP
 4200     index(0x4);  // No Index
 4201     scale(0x0);  // No Scale
 4202     disp($reg);  // Stack Offset
 4203   %}
 4204 %}
 4205 operand stackSlotL(sRegL reg)
 4206 %{
 4207   constraint(ALLOC_IN_RC(stack_slots));
 4208   // No match rule because this operand is only generated in matching
 4209 
 4210   format %{ "[$reg]" %}
 4211   interface(MEMORY_INTER) %{
 4212     base(0x4);   // RSP
 4213     index(0x4);  // No Index
 4214     scale(0x0);  // No Scale
 4215     disp($reg);  // Stack Offset
 4216   %}
 4217 %}
 4218 
 4219 //----------Conditional Branch Operands----------------------------------------
 4220 // Comparison Op  - This is the operation of the comparison, and is limited to
 4221 //                  the following set of codes:
 4222 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 4223 //
 4224 // Other attributes of the comparison, such as unsignedness, are specified
 4225 // by the comparison instruction that sets a condition code flags register.
 4226 // That result is represented by a flags operand whose subtype is appropriate
 4227 // to the unsignedness (etc.) of the comparison.
 4228 //
 4229 // Later, the instruction which matches both the Comparison Op (a Bool) and
 4230 // the flags (produced by the Cmp) specifies the coding of the comparison op
 4231 // by matching a specific subtype of Bool operand below, such as cmpOpU.
 4232 
 4233 // Comparision Code
 4234 operand cmpOp()
 4235 %{
 4236   match(Bool);
 4237 
 4238   format %{ "" %}
 4239   interface(COND_INTER) %{
 4240     equal(0x4, "e");
 4241     not_equal(0x5, "ne");
 4242     less(0xC, "l");
 4243     greater_equal(0xD, "ge");
 4244     less_equal(0xE, "le");
 4245     greater(0xF, "g");
 4246     overflow(0x0, "o");
 4247     no_overflow(0x1, "no");
 4248   %}
 4249 %}
 4250 
 4251 // Comparison Code, unsigned compare.  Used by FP also, with
 4252 // C2 (unordered) turned into GT or LT already.  The other bits
 4253 // C0 and C3 are turned into Carry & Zero flags.
 4254 operand cmpOpU()
 4255 %{
 4256   match(Bool);
 4257 
 4258   format %{ "" %}
 4259   interface(COND_INTER) %{
 4260     equal(0x4, "e");
 4261     not_equal(0x5, "ne");
 4262     less(0x2, "b");
 4263     greater_equal(0x3, "nb");
 4264     less_equal(0x6, "be");
 4265     greater(0x7, "nbe");
 4266     overflow(0x0, "o");
 4267     no_overflow(0x1, "no");
 4268   %}
 4269 %}
 4270 
 4271 
 4272 // Floating comparisons that don't require any fixup for the unordered case
 4273 operand cmpOpUCF() %{
 4274   match(Bool);
 4275   predicate(n->as_Bool()->_test._test == BoolTest::lt ||
 4276             n->as_Bool()->_test._test == BoolTest::ge ||
 4277             n->as_Bool()->_test._test == BoolTest::le ||
 4278             n->as_Bool()->_test._test == BoolTest::gt);
 4279   format %{ "" %}
 4280   interface(COND_INTER) %{
 4281     equal(0x4, "e");
 4282     not_equal(0x5, "ne");
 4283     less(0x2, "b");
 4284     greater_equal(0x3, "nb");
 4285     less_equal(0x6, "be");
 4286     greater(0x7, "nbe");
 4287     overflow(0x0, "o");
 4288     no_overflow(0x1, "no");
 4289   %}
 4290 %}
 4291 
 4292 
 4293 // Floating comparisons that can be fixed up with extra conditional jumps
 4294 operand cmpOpUCF2() %{
 4295   match(Bool);
 4296   predicate(n->as_Bool()->_test._test == BoolTest::ne ||
 4297             n->as_Bool()->_test._test == BoolTest::eq);
 4298   format %{ "" %}
 4299   interface(COND_INTER) %{
 4300     equal(0x4, "e");
 4301     not_equal(0x5, "ne");
 4302     less(0x2, "b");
 4303     greater_equal(0x3, "nb");
 4304     less_equal(0x6, "be");
 4305     greater(0x7, "nbe");
 4306     overflow(0x0, "o");
 4307     no_overflow(0x1, "no");
 4308   %}
 4309 %}
 4310 
 4311 //----------OPERAND CLASSES----------------------------------------------------
 4312 // Operand Classes are groups of operands that are used as to simplify
 4313 // instruction definitions by not requiring the AD writer to specify separate
 4314 // instructions for every form of operand when the instruction accepts
 4315 // multiple operand types with the same basic encoding and format.  The classic
 4316 // case of this is memory operands.
 4317 
 4318 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
 4319                indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
 4320                indCompressedOopOffset,
 4321                indirectNarrow, indOffset8Narrow, indOffset32Narrow,
 4322                indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
 4323                indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
 4324 
 4325 //----------PIPELINE-----------------------------------------------------------
 4326 // Rules which define the behavior of the target architectures pipeline.
 4327 pipeline %{
 4328 
 4329 //----------ATTRIBUTES---------------------------------------------------------
 4330 attributes %{
 4331   variable_size_instructions;        // Fixed size instructions
 4332   max_instructions_per_bundle = 3;   // Up to 3 instructions per bundle
 4333   instruction_unit_size = 1;         // An instruction is 1 bytes long
 4334   instruction_fetch_unit_size = 16;  // The processor fetches one line
 4335   instruction_fetch_units = 1;       // of 16 bytes
 4336 
 4337   // List of nop instructions
 4338   nops( MachNop );
 4339 %}
 4340 
 4341 //----------RESOURCES----------------------------------------------------------
 4342 // Resources are the functional units available to the machine
 4343 
 4344 // Generic P2/P3 pipeline
 4345 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
 4346 // 3 instructions decoded per cycle.
 4347 // 2 load/store ops per cycle, 1 branch, 1 FPU,
 4348 // 3 ALU op, only ALU0 handles mul instructions.
 4349 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
 4350            MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
 4351            BR, FPU,
 4352            ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
 4353 
 4354 //----------PIPELINE DESCRIPTION-----------------------------------------------
 4355 // Pipeline Description specifies the stages in the machine's pipeline
 4356 
 4357 // Generic P2/P3 pipeline
 4358 pipe_desc(S0, S1, S2, S3, S4, S5);
 4359 
 4360 //----------PIPELINE CLASSES---------------------------------------------------
 4361 // Pipeline Classes describe the stages in which input and output are
 4362 // referenced by the hardware pipeline.
 4363 
 4364 // Naming convention: ialu or fpu
 4365 // Then: _reg
 4366 // Then: _reg if there is a 2nd register
 4367 // Then: _long if it's a pair of instructions implementing a long
 4368 // Then: _fat if it requires the big decoder
 4369 //   Or: _mem if it requires the big decoder and a memory unit.
 4370 
 4371 // Integer ALU reg operation
 4372 pipe_class ialu_reg(rRegI dst)
 4373 %{
 4374     single_instruction;
 4375     dst    : S4(write);
 4376     dst    : S3(read);
 4377     DECODE : S0;        // any decoder
 4378     ALU    : S3;        // any alu
 4379 %}
 4380 
 4381 // Long ALU reg operation
 4382 pipe_class ialu_reg_long(rRegL dst)
 4383 %{
 4384     instruction_count(2);
 4385     dst    : S4(write);
 4386     dst    : S3(read);
 4387     DECODE : S0(2);     // any 2 decoders
 4388     ALU    : S3(2);     // both alus
 4389 %}
 4390 
 4391 // Integer ALU reg operation using big decoder
 4392 pipe_class ialu_reg_fat(rRegI dst)
 4393 %{
 4394     single_instruction;
 4395     dst    : S4(write);
 4396     dst    : S3(read);
 4397     D0     : S0;        // big decoder only
 4398     ALU    : S3;        // any alu
 4399 %}
 4400 
 4401 // Integer ALU reg-reg operation
 4402 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
 4403 %{
 4404     single_instruction;
 4405     dst    : S4(write);
 4406     src    : S3(read);
 4407     DECODE : S0;        // any decoder
 4408     ALU    : S3;        // any alu
 4409 %}
 4410 
 4411 // Integer ALU reg-reg operation
 4412 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
 4413 %{
 4414     single_instruction;
 4415     dst    : S4(write);
 4416     src    : S3(read);
 4417     D0     : S0;        // big decoder only
 4418     ALU    : S3;        // any alu
 4419 %}
 4420 
 4421 // Integer ALU reg-mem operation
 4422 pipe_class ialu_reg_mem(rRegI dst, memory mem)
 4423 %{
 4424     single_instruction;
 4425     dst    : S5(write);
 4426     mem    : S3(read);
 4427     D0     : S0;        // big decoder only
 4428     ALU    : S4;        // any alu
 4429     MEM    : S3;        // any mem
 4430 %}
 4431 
 4432 // Integer mem operation (prefetch)
 4433 pipe_class ialu_mem(memory mem)
 4434 %{
 4435     single_instruction;
 4436     mem    : S3(read);
 4437     D0     : S0;        // big decoder only
 4438     MEM    : S3;        // any mem
 4439 %}
 4440 
 4441 // Integer Store to Memory
 4442 pipe_class ialu_mem_reg(memory mem, rRegI src)
 4443 %{
 4444     single_instruction;
 4445     mem    : S3(read);
 4446     src    : S5(read);
 4447     D0     : S0;        // big decoder only
 4448     ALU    : S4;        // any alu
 4449     MEM    : S3;
 4450 %}
 4451 
 4452 // // Long Store to Memory
 4453 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
 4454 // %{
 4455 //     instruction_count(2);
 4456 //     mem    : S3(read);
 4457 //     src    : S5(read);
 4458 //     D0     : S0(2);          // big decoder only; twice
 4459 //     ALU    : S4(2);     // any 2 alus
 4460 //     MEM    : S3(2);  // Both mems
 4461 // %}
 4462 
 4463 // Integer Store to Memory
 4464 pipe_class ialu_mem_imm(memory mem)
 4465 %{
 4466     single_instruction;
 4467     mem    : S3(read);
 4468     D0     : S0;        // big decoder only
 4469     ALU    : S4;        // any alu
 4470     MEM    : S3;
 4471 %}
 4472 
 4473 // Integer ALU0 reg-reg operation
 4474 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
 4475 %{
 4476     single_instruction;
 4477     dst    : S4(write);
 4478     src    : S3(read);
 4479     D0     : S0;        // Big decoder only
 4480     ALU0   : S3;        // only alu0
 4481 %}
 4482 
 4483 // Integer ALU0 reg-mem operation
 4484 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
 4485 %{
 4486     single_instruction;
 4487     dst    : S5(write);
 4488     mem    : S3(read);
 4489     D0     : S0;        // big decoder only
 4490     ALU0   : S4;        // ALU0 only
 4491     MEM    : S3;        // any mem
 4492 %}
 4493 
 4494 // Integer ALU reg-reg operation
 4495 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
 4496 %{
 4497     single_instruction;
 4498     cr     : S4(write);
 4499     src1   : S3(read);
 4500     src2   : S3(read);
 4501     DECODE : S0;        // any decoder
 4502     ALU    : S3;        // any alu
 4503 %}
 4504 
 4505 // Integer ALU reg-imm operation
 4506 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
 4507 %{
 4508     single_instruction;
 4509     cr     : S4(write);
 4510     src1   : S3(read);
 4511     DECODE : S0;        // any decoder
 4512     ALU    : S3;        // any alu
 4513 %}
 4514 
 4515 // Integer ALU reg-mem operation
 4516 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
 4517 %{
 4518     single_instruction;
 4519     cr     : S4(write);
 4520     src1   : S3(read);
 4521     src2   : S3(read);
 4522     D0     : S0;        // big decoder only
 4523     ALU    : S4;        // any alu
 4524     MEM    : S3;
 4525 %}
 4526 
 4527 // Conditional move reg-reg
 4528 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
 4529 %{
 4530     instruction_count(4);
 4531     y      : S4(read);
 4532     q      : S3(read);
 4533     p      : S3(read);
 4534     DECODE : S0(4);     // any decoder
 4535 %}
 4536 
 4537 // Conditional move reg-reg
 4538 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
 4539 %{
 4540     single_instruction;
 4541     dst    : S4(write);
 4542     src    : S3(read);
 4543     cr     : S3(read);
 4544     DECODE : S0;        // any decoder
 4545 %}
 4546 
 4547 // Conditional move reg-mem
 4548 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
 4549 %{
 4550     single_instruction;
 4551     dst    : S4(write);
 4552     src    : S3(read);
 4553     cr     : S3(read);
 4554     DECODE : S0;        // any decoder
 4555     MEM    : S3;
 4556 %}
 4557 
 4558 // Conditional move reg-reg long
 4559 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
 4560 %{
 4561     single_instruction;
 4562     dst    : S4(write);
 4563     src    : S3(read);
 4564     cr     : S3(read);
 4565     DECODE : S0(2);     // any 2 decoders
 4566 %}
 4567 
 4568 // XXX
 4569 // // Conditional move double reg-reg
 4570 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
 4571 // %{
 4572 //     single_instruction;
 4573 //     dst    : S4(write);
 4574 //     src    : S3(read);
 4575 //     cr     : S3(read);
 4576 //     DECODE : S0;     // any decoder
 4577 // %}
 4578 
 4579 // Float reg-reg operation
 4580 pipe_class fpu_reg(regD dst)
 4581 %{
 4582     instruction_count(2);
 4583     dst    : S3(read);
 4584     DECODE : S0(2);     // any 2 decoders
 4585     FPU    : S3;
 4586 %}
 4587 
 4588 // Float reg-reg operation
 4589 pipe_class fpu_reg_reg(regD dst, regD src)
 4590 %{
 4591     instruction_count(2);
 4592     dst    : S4(write);
 4593     src    : S3(read);
 4594     DECODE : S0(2);     // any 2 decoders
 4595     FPU    : S3;
 4596 %}
 4597 
 4598 // Float reg-reg operation
 4599 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
 4600 %{
 4601     instruction_count(3);
 4602     dst    : S4(write);
 4603     src1   : S3(read);
 4604     src2   : S3(read);
 4605     DECODE : S0(3);     // any 3 decoders
 4606     FPU    : S3(2);
 4607 %}
 4608 
 4609 // Float reg-reg operation
 4610 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
 4611 %{
 4612     instruction_count(4);
 4613     dst    : S4(write);
 4614     src1   : S3(read);
 4615     src2   : S3(read);
 4616     src3   : S3(read);
 4617     DECODE : S0(4);     // any 3 decoders
 4618     FPU    : S3(2);
 4619 %}
 4620 
 4621 // Float reg-reg operation
 4622 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
 4623 %{
 4624     instruction_count(4);
 4625     dst    : S4(write);
 4626     src1   : S3(read);
 4627     src2   : S3(read);
 4628     src3   : S3(read);
 4629     DECODE : S1(3);     // any 3 decoders
 4630     D0     : S0;        // Big decoder only
 4631     FPU    : S3(2);
 4632     MEM    : S3;
 4633 %}
 4634 
 4635 // Float reg-mem operation
 4636 pipe_class fpu_reg_mem(regD dst, memory mem)
 4637 %{
 4638     instruction_count(2);
 4639     dst    : S5(write);
 4640     mem    : S3(read);
 4641     D0     : S0;        // big decoder only
 4642     DECODE : S1;        // any decoder for FPU POP
 4643     FPU    : S4;
 4644     MEM    : S3;        // any mem
 4645 %}
 4646 
 4647 // Float reg-mem operation
 4648 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
 4649 %{
 4650     instruction_count(3);
 4651     dst    : S5(write);
 4652     src1   : S3(read);
 4653     mem    : S3(read);
 4654     D0     : S0;        // big decoder only
 4655     DECODE : S1(2);     // any decoder for FPU POP
 4656     FPU    : S4;
 4657     MEM    : S3;        // any mem
 4658 %}
 4659 
 4660 // Float mem-reg operation
 4661 pipe_class fpu_mem_reg(memory mem, regD src)
 4662 %{
 4663     instruction_count(2);
 4664     src    : S5(read);
 4665     mem    : S3(read);
 4666     DECODE : S0;        // any decoder for FPU PUSH
 4667     D0     : S1;        // big decoder only
 4668     FPU    : S4;
 4669     MEM    : S3;        // any mem
 4670 %}
 4671 
 4672 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
 4673 %{
 4674     instruction_count(3);
 4675     src1   : S3(read);
 4676     src2   : S3(read);
 4677     mem    : S3(read);
 4678     DECODE : S0(2);     // any decoder for FPU PUSH
 4679     D0     : S1;        // big decoder only
 4680     FPU    : S4;
 4681     MEM    : S3;        // any mem
 4682 %}
 4683 
 4684 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
 4685 %{
 4686     instruction_count(3);
 4687     src1   : S3(read);
 4688     src2   : S3(read);
 4689     mem    : S4(read);
 4690     DECODE : S0;        // any decoder for FPU PUSH
 4691     D0     : S0(2);     // big decoder only
 4692     FPU    : S4;
 4693     MEM    : S3(2);     // any mem
 4694 %}
 4695 
 4696 pipe_class fpu_mem_mem(memory dst, memory src1)
 4697 %{
 4698     instruction_count(2);
 4699     src1   : S3(read);
 4700     dst    : S4(read);
 4701     D0     : S0(2);     // big decoder only
 4702     MEM    : S3(2);     // any mem
 4703 %}
 4704 
 4705 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
 4706 %{
 4707     instruction_count(3);
 4708     src1   : S3(read);
 4709     src2   : S3(read);
 4710     dst    : S4(read);
 4711     D0     : S0(3);     // big decoder only
 4712     FPU    : S4;
 4713     MEM    : S3(3);     // any mem
 4714 %}
 4715 
 4716 pipe_class fpu_mem_reg_con(memory mem, regD src1)
 4717 %{
 4718     instruction_count(3);
 4719     src1   : S4(read);
 4720     mem    : S4(read);
 4721     DECODE : S0;        // any decoder for FPU PUSH
 4722     D0     : S0(2);     // big decoder only
 4723     FPU    : S4;
 4724     MEM    : S3(2);     // any mem
 4725 %}
 4726 
 4727 // Float load constant
 4728 pipe_class fpu_reg_con(regD dst)
 4729 %{
 4730     instruction_count(2);
 4731     dst    : S5(write);
 4732     D0     : S0;        // big decoder only for the load
 4733     DECODE : S1;        // any decoder for FPU POP
 4734     FPU    : S4;
 4735     MEM    : S3;        // any mem
 4736 %}
 4737 
 4738 // Float load constant
 4739 pipe_class fpu_reg_reg_con(regD dst, regD src)
 4740 %{
 4741     instruction_count(3);
 4742     dst    : S5(write);
 4743     src    : S3(read);
 4744     D0     : S0;        // big decoder only for the load
 4745     DECODE : S1(2);     // any decoder for FPU POP
 4746     FPU    : S4;
 4747     MEM    : S3;        // any mem
 4748 %}
 4749 
 4750 // UnConditional branch
 4751 pipe_class pipe_jmp(label labl)
 4752 %{
 4753     single_instruction;
 4754     BR   : S3;
 4755 %}
 4756 
 4757 // Conditional branch
 4758 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
 4759 %{
 4760     single_instruction;
 4761     cr    : S1(read);
 4762     BR    : S3;
 4763 %}
 4764 
 4765 // Allocation idiom
 4766 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
 4767 %{
 4768     instruction_count(1); force_serialization;
 4769     fixed_latency(6);
 4770     heap_ptr : S3(read);
 4771     DECODE   : S0(3);
 4772     D0       : S2;
 4773     MEM      : S3;
 4774     ALU      : S3(2);
 4775     dst      : S5(write);
 4776     BR       : S5;
 4777 %}
 4778 
 4779 // Generic big/slow expanded idiom
 4780 pipe_class pipe_slow()
 4781 %{
 4782     instruction_count(10); multiple_bundles; force_serialization;
 4783     fixed_latency(100);
 4784     D0  : S0(2);
 4785     MEM : S3(2);
 4786 %}
 4787 
 4788 // The real do-nothing guy
 4789 pipe_class empty()
 4790 %{
 4791     instruction_count(0);
 4792 %}
 4793 
 4794 // Define the class for the Nop node
 4795 define
 4796 %{
 4797    MachNop = empty;
 4798 %}
 4799 
 4800 %}
 4801 
 4802 //----------INSTRUCTIONS-------------------------------------------------------
 4803 //
 4804 // match      -- States which machine-independent subtree may be replaced
 4805 //               by this instruction.
 4806 // ins_cost   -- The estimated cost of this instruction is used by instruction
 4807 //               selection to identify a minimum cost tree of machine
 4808 //               instructions that matches a tree of machine-independent
 4809 //               instructions.
 4810 // format     -- A string providing the disassembly for this instruction.
 4811 //               The value of an instruction's operand may be inserted
 4812 //               by referring to it with a '$' prefix.
 4813 // opcode     -- Three instruction opcodes may be provided.  These are referred
 4814 //               to within an encode class as $primary, $secondary, and $tertiary
 4815 //               rrspectively.  The primary opcode is commonly used to
 4816 //               indicate the type of machine instruction, while secondary
 4817 //               and tertiary are often used for prefix options or addressing
 4818 //               modes.
 4819 // ins_encode -- A list of encode classes with parameters. The encode class
 4820 //               name must have been defined in an 'enc_class' specification
 4821 //               in the encode section of the architecture description.
 4822 
 4823 // Dummy reg-to-reg vector moves. Removed during post-selection cleanup.
 4824 // Load Float
 4825 instruct MoveF2VL(vlRegF dst, regF src) %{
 4826   match(Set dst src);
 4827   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 4828   ins_encode %{
 4829     ShouldNotReachHere();
 4830   %}
 4831   ins_pipe( fpu_reg_reg );
 4832 %}
 4833 
 4834 // Load Float
 4835 instruct MoveF2LEG(legRegF dst, regF src) %{
 4836   match(Set dst src);
 4837   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 4838   ins_encode %{
 4839     ShouldNotReachHere();
 4840   %}
 4841   ins_pipe( fpu_reg_reg );
 4842 %}
 4843 
 4844 // Load Float
 4845 instruct MoveVL2F(regF dst, vlRegF src) %{
 4846   match(Set dst src);
 4847   format %{ "movss $dst,$src\t! load float (4 bytes)" %}
 4848   ins_encode %{
 4849     ShouldNotReachHere();
 4850   %}
 4851   ins_pipe( fpu_reg_reg );
 4852 %}
 4853 
 4854 // Load Float
 4855 instruct MoveLEG2F(regF dst, legRegF src) %{
 4856   match(Set dst src);
 4857   format %{ "movss $dst,$src\t# if src != dst load float (4 bytes)" %}
 4858   ins_encode %{
 4859     ShouldNotReachHere();
 4860   %}
 4861   ins_pipe( fpu_reg_reg );
 4862 %}
 4863 
 4864 // Load Double
 4865 instruct MoveD2VL(vlRegD dst, regD src) %{
 4866   match(Set dst src);
 4867   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 4868   ins_encode %{
 4869     ShouldNotReachHere();
 4870   %}
 4871   ins_pipe( fpu_reg_reg );
 4872 %}
 4873 
 4874 // Load Double
 4875 instruct MoveD2LEG(legRegD dst, regD src) %{
 4876   match(Set dst src);
 4877   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 4878   ins_encode %{
 4879     ShouldNotReachHere();
 4880   %}
 4881   ins_pipe( fpu_reg_reg );
 4882 %}
 4883 
 4884 // Load Double
 4885 instruct MoveVL2D(regD dst, vlRegD src) %{
 4886   match(Set dst src);
 4887   format %{ "movsd $dst,$src\t! load double (8 bytes)" %}
 4888   ins_encode %{
 4889     ShouldNotReachHere();
 4890   %}
 4891   ins_pipe( fpu_reg_reg );
 4892 %}
 4893 
 4894 // Load Double
 4895 instruct MoveLEG2D(regD dst, legRegD src) %{
 4896   match(Set dst src);
 4897   format %{ "movsd $dst,$src\t# if src != dst load double (8 bytes)" %}
 4898   ins_encode %{
 4899     ShouldNotReachHere();
 4900   %}
 4901   ins_pipe( fpu_reg_reg );
 4902 %}
 4903 
 4904 //----------Load/Store/Move Instructions---------------------------------------
 4905 //----------Load Instructions--------------------------------------------------
 4906 
 4907 // Load Byte (8 bit signed)
 4908 instruct loadB(rRegI dst, memory mem)
 4909 %{
 4910   match(Set dst (LoadB mem));
 4911 
 4912   ins_cost(125);
 4913   format %{ "movsbl  $dst, $mem\t# byte" %}
 4914 
 4915   ins_encode %{
 4916     __ movsbl($dst$$Register, $mem$$Address);
 4917   %}
 4918 
 4919   ins_pipe(ialu_reg_mem);
 4920 %}
 4921 
 4922 // Load Byte (8 bit signed) into Long Register
 4923 instruct loadB2L(rRegL dst, memory mem)
 4924 %{
 4925   match(Set dst (ConvI2L (LoadB mem)));
 4926 
 4927   ins_cost(125);
 4928   format %{ "movsbq  $dst, $mem\t# byte -> long" %}
 4929 
 4930   ins_encode %{
 4931     __ movsbq($dst$$Register, $mem$$Address);
 4932   %}
 4933 
 4934   ins_pipe(ialu_reg_mem);
 4935 %}
 4936 
 4937 // Load Unsigned Byte (8 bit UNsigned)
 4938 instruct loadUB(rRegI dst, memory mem)
 4939 %{
 4940   match(Set dst (LoadUB mem));
 4941 
 4942   ins_cost(125);
 4943   format %{ "movzbl  $dst, $mem\t# ubyte" %}
 4944 
 4945   ins_encode %{
 4946     __ movzbl($dst$$Register, $mem$$Address);
 4947   %}
 4948 
 4949   ins_pipe(ialu_reg_mem);
 4950 %}
 4951 
 4952 // Load Unsigned Byte (8 bit UNsigned) into Long Register
 4953 instruct loadUB2L(rRegL dst, memory mem)
 4954 %{
 4955   match(Set dst (ConvI2L (LoadUB mem)));
 4956 
 4957   ins_cost(125);
 4958   format %{ "movzbq  $dst, $mem\t# ubyte -> long" %}
 4959 
 4960   ins_encode %{
 4961     __ movzbq($dst$$Register, $mem$$Address);
 4962   %}
 4963 
 4964   ins_pipe(ialu_reg_mem);
 4965 %}
 4966 
 4967 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
 4968 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 4969   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
 4970   effect(KILL cr);
 4971 
 4972   format %{ "movzbq  $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
 4973             "andl    $dst, right_n_bits($mask, 8)" %}
 4974   ins_encode %{
 4975     Register Rdst = $dst$$Register;
 4976     __ movzbq(Rdst, $mem$$Address);
 4977     __ andl(Rdst, $mask$$constant & right_n_bits(8));
 4978   %}
 4979   ins_pipe(ialu_reg_mem);
 4980 %}
 4981 
 4982 // Load Short (16 bit signed)
 4983 instruct loadS(rRegI dst, memory mem)
 4984 %{
 4985   match(Set dst (LoadS mem));
 4986 
 4987   ins_cost(125);
 4988   format %{ "movswl $dst, $mem\t# short" %}
 4989 
 4990   ins_encode %{
 4991     __ movswl($dst$$Register, $mem$$Address);
 4992   %}
 4993 
 4994   ins_pipe(ialu_reg_mem);
 4995 %}
 4996 
 4997 // Load Short (16 bit signed) to Byte (8 bit signed)
 4998 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 4999   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
 5000 
 5001   ins_cost(125);
 5002   format %{ "movsbl $dst, $mem\t# short -> byte" %}
 5003   ins_encode %{
 5004     __ movsbl($dst$$Register, $mem$$Address);
 5005   %}
 5006   ins_pipe(ialu_reg_mem);
 5007 %}
 5008 
 5009 // Load Short (16 bit signed) into Long Register
 5010 instruct loadS2L(rRegL dst, memory mem)
 5011 %{
 5012   match(Set dst (ConvI2L (LoadS mem)));
 5013 
 5014   ins_cost(125);
 5015   format %{ "movswq $dst, $mem\t# short -> long" %}
 5016 
 5017   ins_encode %{
 5018     __ movswq($dst$$Register, $mem$$Address);
 5019   %}
 5020 
 5021   ins_pipe(ialu_reg_mem);
 5022 %}
 5023 
 5024 // Load Unsigned Short/Char (16 bit UNsigned)
 5025 instruct loadUS(rRegI dst, memory mem)
 5026 %{
 5027   match(Set dst (LoadUS mem));
 5028 
 5029   ins_cost(125);
 5030   format %{ "movzwl  $dst, $mem\t# ushort/char" %}
 5031 
 5032   ins_encode %{
 5033     __ movzwl($dst$$Register, $mem$$Address);
 5034   %}
 5035 
 5036   ins_pipe(ialu_reg_mem);
 5037 %}
 5038 
 5039 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
 5040 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 5041   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
 5042 
 5043   ins_cost(125);
 5044   format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
 5045   ins_encode %{
 5046     __ movsbl($dst$$Register, $mem$$Address);
 5047   %}
 5048   ins_pipe(ialu_reg_mem);
 5049 %}
 5050 
 5051 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
 5052 instruct loadUS2L(rRegL dst, memory mem)
 5053 %{
 5054   match(Set dst (ConvI2L (LoadUS mem)));
 5055 
 5056   ins_cost(125);
 5057   format %{ "movzwq  $dst, $mem\t# ushort/char -> long" %}
 5058 
 5059   ins_encode %{
 5060     __ movzwq($dst$$Register, $mem$$Address);
 5061   %}
 5062 
 5063   ins_pipe(ialu_reg_mem);
 5064 %}
 5065 
 5066 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
 5067 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 5068   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 5069 
 5070   format %{ "movzbq  $dst, $mem\t# ushort/char & 0xFF -> long" %}
 5071   ins_encode %{
 5072     __ movzbq($dst$$Register, $mem$$Address);
 5073   %}
 5074   ins_pipe(ialu_reg_mem);
 5075 %}
 5076 
 5077 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
 5078 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
 5079   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
 5080   effect(KILL cr);
 5081 
 5082   format %{ "movzwq  $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
 5083             "andl    $dst, right_n_bits($mask, 16)" %}
 5084   ins_encode %{
 5085     Register Rdst = $dst$$Register;
 5086     __ movzwq(Rdst, $mem$$Address);
 5087     __ andl(Rdst, $mask$$constant & right_n_bits(16));
 5088   %}
 5089   ins_pipe(ialu_reg_mem);
 5090 %}
 5091 
 5092 // Load Integer
 5093 instruct loadI(rRegI dst, memory mem)
 5094 %{
 5095   match(Set dst (LoadI mem));
 5096 
 5097   ins_cost(125);
 5098   format %{ "movl    $dst, $mem\t# int" %}
 5099 
 5100   ins_encode %{
 5101     __ movl($dst$$Register, $mem$$Address);
 5102   %}
 5103 
 5104   ins_pipe(ialu_reg_mem);
 5105 %}
 5106 
 5107 // Load Integer (32 bit signed) to Byte (8 bit signed)
 5108 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
 5109   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
 5110 
 5111   ins_cost(125);
 5112   format %{ "movsbl  $dst, $mem\t# int -> byte" %}
 5113   ins_encode %{
 5114     __ movsbl($dst$$Register, $mem$$Address);
 5115   %}
 5116   ins_pipe(ialu_reg_mem);
 5117 %}
 5118 
 5119 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
 5120 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
 5121   match(Set dst (AndI (LoadI mem) mask));
 5122 
 5123   ins_cost(125);
 5124   format %{ "movzbl  $dst, $mem\t# int -> ubyte" %}
 5125   ins_encode %{
 5126     __ movzbl($dst$$Register, $mem$$Address);
 5127   %}
 5128   ins_pipe(ialu_reg_mem);
 5129 %}
 5130 
 5131 // Load Integer (32 bit signed) to Short (16 bit signed)
 5132 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
 5133   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
 5134 
 5135   ins_cost(125);
 5136   format %{ "movswl  $dst, $mem\t# int -> short" %}
 5137   ins_encode %{
 5138     __ movswl($dst$$Register, $mem$$Address);
 5139   %}
 5140   ins_pipe(ialu_reg_mem);
 5141 %}
 5142 
 5143 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
 5144 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
 5145   match(Set dst (AndI (LoadI mem) mask));
 5146 
 5147   ins_cost(125);
 5148   format %{ "movzwl  $dst, $mem\t# int -> ushort/char" %}
 5149   ins_encode %{
 5150     __ movzwl($dst$$Register, $mem$$Address);
 5151   %}
 5152   ins_pipe(ialu_reg_mem);
 5153 %}
 5154 
 5155 // Load Integer into Long Register
 5156 instruct loadI2L(rRegL dst, memory mem)
 5157 %{
 5158   match(Set dst (ConvI2L (LoadI mem)));
 5159 
 5160   ins_cost(125);
 5161   format %{ "movslq  $dst, $mem\t# int -> long" %}
 5162 
 5163   ins_encode %{
 5164     __ movslq($dst$$Register, $mem$$Address);
 5165   %}
 5166 
 5167   ins_pipe(ialu_reg_mem);
 5168 %}
 5169 
 5170 // Load Integer with mask 0xFF into Long Register
 5171 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
 5172   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5173 
 5174   format %{ "movzbq  $dst, $mem\t# int & 0xFF -> long" %}
 5175   ins_encode %{
 5176     __ movzbq($dst$$Register, $mem$$Address);
 5177   %}
 5178   ins_pipe(ialu_reg_mem);
 5179 %}
 5180 
 5181 // Load Integer with mask 0xFFFF into Long Register
 5182 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
 5183   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5184 
 5185   format %{ "movzwq  $dst, $mem\t# int & 0xFFFF -> long" %}
 5186   ins_encode %{
 5187     __ movzwq($dst$$Register, $mem$$Address);
 5188   %}
 5189   ins_pipe(ialu_reg_mem);
 5190 %}
 5191 
 5192 // Load Integer with a 31-bit mask into Long Register
 5193 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
 5194   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
 5195   effect(KILL cr);
 5196 
 5197   format %{ "movl    $dst, $mem\t# int & 31-bit mask -> long\n\t"
 5198             "andl    $dst, $mask" %}
 5199   ins_encode %{
 5200     Register Rdst = $dst$$Register;
 5201     __ movl(Rdst, $mem$$Address);
 5202     __ andl(Rdst, $mask$$constant);
 5203   %}
 5204   ins_pipe(ialu_reg_mem);
 5205 %}
 5206 
 5207 // Load Unsigned Integer into Long Register
 5208 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
 5209 %{
 5210   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 5211 
 5212   ins_cost(125);
 5213   format %{ "movl    $dst, $mem\t# uint -> long" %}
 5214 
 5215   ins_encode %{
 5216     __ movl($dst$$Register, $mem$$Address);
 5217   %}
 5218 
 5219   ins_pipe(ialu_reg_mem);
 5220 %}
 5221 
 5222 // Load Long
 5223 instruct loadL(rRegL dst, memory mem)
 5224 %{
 5225   match(Set dst (LoadL mem));
 5226 
 5227   ins_cost(125);
 5228   format %{ "movq    $dst, $mem\t# long" %}
 5229 
 5230   ins_encode %{
 5231     __ movq($dst$$Register, $mem$$Address);
 5232   %}
 5233 
 5234   ins_pipe(ialu_reg_mem); // XXX
 5235 %}
 5236 
 5237 // Load Range
 5238 instruct loadRange(rRegI dst, memory mem)
 5239 %{
 5240   match(Set dst (LoadRange mem));
 5241 
 5242   ins_cost(125); // XXX
 5243   format %{ "movl    $dst, $mem\t# range" %}
 5244   ins_encode %{
 5245     __ movl($dst$$Register, $mem$$Address);
 5246   %}
 5247   ins_pipe(ialu_reg_mem);
 5248 %}
 5249 
 5250 // Load Pointer
 5251 instruct loadP(rRegP dst, memory mem)
 5252 %{
 5253   match(Set dst (LoadP mem));
 5254   predicate(n->as_Load()->barrier_data() == 0);
 5255 
 5256   ins_cost(125); // XXX
 5257   format %{ "movq    $dst, $mem\t# ptr" %}
 5258   ins_encode %{
 5259     __ movq($dst$$Register, $mem$$Address);
 5260   %}
 5261   ins_pipe(ialu_reg_mem); // XXX
 5262 %}
 5263 
 5264 // Load Compressed Pointer
 5265 instruct loadN(rRegN dst, memory mem)
 5266 %{
 5267    match(Set dst (LoadN mem));
 5268 
 5269    ins_cost(125); // XXX
 5270    format %{ "movl    $dst, $mem\t# compressed ptr" %}
 5271    ins_encode %{
 5272      __ movl($dst$$Register, $mem$$Address);
 5273    %}
 5274    ins_pipe(ialu_reg_mem); // XXX
 5275 %}
 5276 
 5277 
 5278 // Load Klass Pointer
 5279 instruct loadKlass(rRegP dst, memory mem)
 5280 %{
 5281   match(Set dst (LoadKlass mem));
 5282 
 5283   ins_cost(125); // XXX
 5284   format %{ "movq    $dst, $mem\t# class" %}
 5285   ins_encode %{
 5286     __ movq($dst$$Register, $mem$$Address);
 5287   %}
 5288   ins_pipe(ialu_reg_mem); // XXX
 5289 %}
 5290 
 5291 // Load narrow Klass Pointer
 5292 instruct loadNKlass(rRegN dst, memory mem)
 5293 %{
 5294   match(Set dst (LoadNKlass mem));
 5295 
 5296   ins_cost(125); // XXX
 5297   format %{ "movl    $dst, $mem\t# compressed klass ptr" %}
 5298   ins_encode %{
 5299     __ movl($dst$$Register, $mem$$Address);
 5300   %}
 5301   ins_pipe(ialu_reg_mem); // XXX
 5302 %}
 5303 
 5304 // Load Float
 5305 instruct loadF(regF dst, memory mem)
 5306 %{
 5307   match(Set dst (LoadF mem));
 5308 
 5309   ins_cost(145); // XXX
 5310   format %{ "movss   $dst, $mem\t# float" %}
 5311   ins_encode %{
 5312     __ movflt($dst$$XMMRegister, $mem$$Address);
 5313   %}
 5314   ins_pipe(pipe_slow); // XXX
 5315 %}
 5316 
 5317 // Load Double
 5318 instruct loadD_partial(regD dst, memory mem)
 5319 %{
 5320   predicate(!UseXmmLoadAndClearUpper);
 5321   match(Set dst (LoadD mem));
 5322 
 5323   ins_cost(145); // XXX
 5324   format %{ "movlpd  $dst, $mem\t# double" %}
 5325   ins_encode %{
 5326     __ movdbl($dst$$XMMRegister, $mem$$Address);
 5327   %}
 5328   ins_pipe(pipe_slow); // XXX
 5329 %}
 5330 
 5331 instruct loadD(regD dst, memory mem)
 5332 %{
 5333   predicate(UseXmmLoadAndClearUpper);
 5334   match(Set dst (LoadD mem));
 5335 
 5336   ins_cost(145); // XXX
 5337   format %{ "movsd   $dst, $mem\t# double" %}
 5338   ins_encode %{
 5339     __ movdbl($dst$$XMMRegister, $mem$$Address);
 5340   %}
 5341   ins_pipe(pipe_slow); // XXX
 5342 %}
 5343 
 5344 
 5345 // Following pseudo code describes the algorithm for max[FD]:
 5346 // Min algorithm is on similar lines
 5347 //  btmp = (b < +0.0) ? a : b
 5348 //  atmp = (b < +0.0) ? b : a
 5349 //  Tmp  = Max_Float(atmp , btmp)
 5350 //  Res  = (atmp == NaN) ? atmp : Tmp
 5351 
 5352 // max = java.lang.Math.max(float a, float b)
 5353 instruct maxF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 5354   predicate(UseAVX > 0 && !n->is_reduction());
 5355   match(Set dst (MaxF a b));
 5356   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5357   format %{
 5358      "vblendvps        $btmp,$b,$a,$b           \n\t"
 5359      "vblendvps        $atmp,$a,$b,$b           \n\t"
 5360      "vmaxss           $tmp,$atmp,$btmp         \n\t"
 5361      "vcmpps.unordered $btmp,$atmp,$atmp        \n\t"
 5362      "vblendvps        $dst,$tmp,$atmp,$btmp    \n\t"
 5363   %}
 5364   ins_encode %{
 5365     int vector_len = Assembler::AVX_128bit;
 5366     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
 5367     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
 5368     __ vmaxss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5369     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5370     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5371  %}
 5372   ins_pipe( pipe_slow );
 5373 %}
 5374 
 5375 instruct maxF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
 5376   predicate(UseAVX > 0 && n->is_reduction());
 5377   match(Set dst (MaxF a b));
 5378   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5379 
 5380   format %{ "$dst = max($a, $b)\t# intrinsic (float)" %}
 5381   ins_encode %{
 5382     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5383                     false /*min*/, true /*single*/);
 5384   %}
 5385   ins_pipe( pipe_slow );
 5386 %}
 5387 
 5388 // max = java.lang.Math.max(double a, double b)
 5389 instruct maxD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 5390   predicate(UseAVX > 0 && !n->is_reduction());
 5391   match(Set dst (MaxD a b));
 5392   effect(USE a, USE b, TEMP atmp, TEMP btmp, TEMP tmp);
 5393   format %{
 5394      "vblendvpd        $btmp,$b,$a,$b            \n\t"
 5395      "vblendvpd        $atmp,$a,$b,$b            \n\t"
 5396      "vmaxsd           $tmp,$atmp,$btmp          \n\t"
 5397      "vcmppd.unordered $btmp,$atmp,$atmp         \n\t"
 5398      "vblendvpd        $dst,$tmp,$atmp,$btmp     \n\t"
 5399   %}
 5400   ins_encode %{
 5401     int vector_len = Assembler::AVX_128bit;
 5402     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, vector_len);
 5403     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $b$$XMMRegister, vector_len);
 5404     __ vmaxsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5405     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5406     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5407   %}
 5408   ins_pipe( pipe_slow );
 5409 %}
 5410 
 5411 instruct maxD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
 5412   predicate(UseAVX > 0 && n->is_reduction());
 5413   match(Set dst (MaxD a b));
 5414   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5415 
 5416   format %{ "$dst = max($a, $b)\t# intrinsic (double)" %}
 5417   ins_encode %{
 5418     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5419                     false /*min*/, false /*single*/);
 5420   %}
 5421   ins_pipe( pipe_slow );
 5422 %}
 5423 
 5424 // min = java.lang.Math.min(float a, float b)
 5425 instruct minF_reg(legRegF dst, legRegF a, legRegF b, legRegF tmp, legRegF atmp, legRegF btmp) %{
 5426   predicate(UseAVX > 0 && !n->is_reduction());
 5427   match(Set dst (MinF a b));
 5428   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5429   format %{
 5430      "vblendvps        $atmp,$a,$b,$a             \n\t"
 5431      "vblendvps        $btmp,$b,$a,$a             \n\t"
 5432      "vminss           $tmp,$atmp,$btmp           \n\t"
 5433      "vcmpps.unordered $btmp,$atmp,$atmp          \n\t"
 5434      "vblendvps        $dst,$tmp,$atmp,$btmp      \n\t"
 5435   %}
 5436   ins_encode %{
 5437     int vector_len = Assembler::AVX_128bit;
 5438     __ vblendvps($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
 5439     __ vblendvps($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
 5440     __ vminss($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5441     __ vcmpps($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5442     __ vblendvps($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5443   %}
 5444   ins_pipe( pipe_slow );
 5445 %}
 5446 
 5447 instruct minF_reduction_reg(legRegF dst, legRegF a, legRegF b, legRegF xmmt, rRegI tmp, rFlagsReg cr) %{
 5448   predicate(UseAVX > 0 && n->is_reduction());
 5449   match(Set dst (MinF a b));
 5450   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5451 
 5452   format %{ "$dst = min($a, $b)\t# intrinsic (float)" %}
 5453   ins_encode %{
 5454     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5455                     true /*min*/, true /*single*/);
 5456   %}
 5457   ins_pipe( pipe_slow );
 5458 %}
 5459 
 5460 // min = java.lang.Math.min(double a, double b)
 5461 instruct minD_reg(legRegD dst, legRegD a, legRegD b, legRegD tmp, legRegD atmp, legRegD btmp) %{
 5462   predicate(UseAVX > 0 && !n->is_reduction());
 5463   match(Set dst (MinD a b));
 5464   effect(USE a, USE b, TEMP tmp, TEMP atmp, TEMP btmp);
 5465   format %{
 5466      "vblendvpd        $atmp,$a,$b,$a           \n\t"
 5467      "vblendvpd        $btmp,$b,$a,$a           \n\t"
 5468      "vminsd           $tmp,$atmp,$btmp         \n\t"
 5469      "vcmppd.unordered $btmp,$atmp,$atmp        \n\t"
 5470      "vblendvpd        $dst,$tmp,$atmp,$btmp    \n\t"
 5471   %}
 5472   ins_encode %{
 5473     int vector_len = Assembler::AVX_128bit;
 5474     __ vblendvpd($atmp$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, vector_len);
 5475     __ vblendvpd($btmp$$XMMRegister, $b$$XMMRegister, $a$$XMMRegister, $a$$XMMRegister, vector_len);
 5476     __ vminsd($tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister);
 5477     __ vcmppd($btmp$$XMMRegister, $atmp$$XMMRegister, $atmp$$XMMRegister, Assembler::_false, vector_len);
 5478     __ vblendvpd($dst$$XMMRegister, $tmp$$XMMRegister, $atmp$$XMMRegister, $btmp$$XMMRegister, vector_len);
 5479   %}
 5480   ins_pipe( pipe_slow );
 5481 %}
 5482 
 5483 instruct minD_reduction_reg(legRegD dst, legRegD a, legRegD b, legRegD xmmt, rRegL tmp, rFlagsReg cr) %{
 5484   predicate(UseAVX > 0 && n->is_reduction());
 5485   match(Set dst (MinD a b));
 5486   effect(USE a, USE b, TEMP xmmt, TEMP tmp, KILL cr);
 5487 
 5488   format %{ "$dst = min($a, $b)\t# intrinsic (double)" %}
 5489   ins_encode %{
 5490     emit_fp_min_max(_masm, $dst$$XMMRegister, $a$$XMMRegister, $b$$XMMRegister, $xmmt$$XMMRegister, $tmp$$Register,
 5491                     true /*min*/, false /*single*/);
 5492   %}
 5493   ins_pipe( pipe_slow );
 5494 %}
 5495 
 5496 // Load Effective Address
 5497 instruct leaP8(rRegP dst, indOffset8 mem)
 5498 %{
 5499   match(Set dst mem);
 5500 
 5501   ins_cost(110); // XXX
 5502   format %{ "leaq    $dst, $mem\t# ptr 8" %}
 5503   ins_encode %{
 5504     __ leaq($dst$$Register, $mem$$Address);
 5505   %}
 5506   ins_pipe(ialu_reg_reg_fat);
 5507 %}
 5508 
 5509 instruct leaP32(rRegP dst, indOffset32 mem)
 5510 %{
 5511   match(Set dst mem);
 5512 
 5513   ins_cost(110);
 5514   format %{ "leaq    $dst, $mem\t# ptr 32" %}
 5515   ins_encode %{
 5516     __ leaq($dst$$Register, $mem$$Address);
 5517   %}
 5518   ins_pipe(ialu_reg_reg_fat);
 5519 %}
 5520 
 5521 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
 5522 %{
 5523   match(Set dst mem);
 5524 
 5525   ins_cost(110);
 5526   format %{ "leaq    $dst, $mem\t# ptr idxoff" %}
 5527   ins_encode %{
 5528     __ leaq($dst$$Register, $mem$$Address);
 5529   %}
 5530   ins_pipe(ialu_reg_reg_fat);
 5531 %}
 5532 
 5533 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
 5534 %{
 5535   match(Set dst mem);
 5536 
 5537   ins_cost(110);
 5538   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 5539   ins_encode %{
 5540     __ leaq($dst$$Register, $mem$$Address);
 5541   %}
 5542   ins_pipe(ialu_reg_reg_fat);
 5543 %}
 5544 
 5545 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
 5546 %{
 5547   match(Set dst mem);
 5548 
 5549   ins_cost(110);
 5550   format %{ "leaq    $dst, $mem\t# ptr idxscale" %}
 5551   ins_encode %{
 5552     __ leaq($dst$$Register, $mem$$Address);
 5553   %}
 5554   ins_pipe(ialu_reg_reg_fat);
 5555 %}
 5556 
 5557 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
 5558 %{
 5559   match(Set dst mem);
 5560 
 5561   ins_cost(110);
 5562   format %{ "leaq    $dst, $mem\t# ptr idxscaleoff" %}
 5563   ins_encode %{
 5564     __ leaq($dst$$Register, $mem$$Address);
 5565   %}
 5566   ins_pipe(ialu_reg_reg_fat);
 5567 %}
 5568 
 5569 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
 5570 %{
 5571   match(Set dst mem);
 5572 
 5573   ins_cost(110);
 5574   format %{ "leaq    $dst, $mem\t# ptr posidxoff" %}
 5575   ins_encode %{
 5576     __ leaq($dst$$Register, $mem$$Address);
 5577   %}
 5578   ins_pipe(ialu_reg_reg_fat);
 5579 %}
 5580 
 5581 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
 5582 %{
 5583   match(Set dst mem);
 5584 
 5585   ins_cost(110);
 5586   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoff" %}
 5587   ins_encode %{
 5588     __ leaq($dst$$Register, $mem$$Address);
 5589   %}
 5590   ins_pipe(ialu_reg_reg_fat);
 5591 %}
 5592 
 5593 // Load Effective Address which uses Narrow (32-bits) oop
 5594 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
 5595 %{
 5596   predicate(UseCompressedOops && (CompressedOops::shift() != 0));
 5597   match(Set dst mem);
 5598 
 5599   ins_cost(110);
 5600   format %{ "leaq    $dst, $mem\t# ptr compressedoopoff32" %}
 5601   ins_encode %{
 5602     __ leaq($dst$$Register, $mem$$Address);
 5603   %}
 5604   ins_pipe(ialu_reg_reg_fat);
 5605 %}
 5606 
 5607 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
 5608 %{
 5609   predicate(CompressedOops::shift() == 0);
 5610   match(Set dst mem);
 5611 
 5612   ins_cost(110); // XXX
 5613   format %{ "leaq    $dst, $mem\t# ptr off8narrow" %}
 5614   ins_encode %{
 5615     __ leaq($dst$$Register, $mem$$Address);
 5616   %}
 5617   ins_pipe(ialu_reg_reg_fat);
 5618 %}
 5619 
 5620 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
 5621 %{
 5622   predicate(CompressedOops::shift() == 0);
 5623   match(Set dst mem);
 5624 
 5625   ins_cost(110);
 5626   format %{ "leaq    $dst, $mem\t# ptr off32narrow" %}
 5627   ins_encode %{
 5628     __ leaq($dst$$Register, $mem$$Address);
 5629   %}
 5630   ins_pipe(ialu_reg_reg_fat);
 5631 %}
 5632 
 5633 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
 5634 %{
 5635   predicate(CompressedOops::shift() == 0);
 5636   match(Set dst mem);
 5637 
 5638   ins_cost(110);
 5639   format %{ "leaq    $dst, $mem\t# ptr idxoffnarrow" %}
 5640   ins_encode %{
 5641     __ leaq($dst$$Register, $mem$$Address);
 5642   %}
 5643   ins_pipe(ialu_reg_reg_fat);
 5644 %}
 5645 
 5646 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
 5647 %{
 5648   predicate(CompressedOops::shift() == 0);
 5649   match(Set dst mem);
 5650 
 5651   ins_cost(110);
 5652   format %{ "leaq    $dst, $mem\t# ptr idxscalenarrow" %}
 5653   ins_encode %{
 5654     __ leaq($dst$$Register, $mem$$Address);
 5655   %}
 5656   ins_pipe(ialu_reg_reg_fat);
 5657 %}
 5658 
 5659 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
 5660 %{
 5661   predicate(CompressedOops::shift() == 0);
 5662   match(Set dst mem);
 5663 
 5664   ins_cost(110);
 5665   format %{ "leaq    $dst, $mem\t# ptr idxscaleoffnarrow" %}
 5666   ins_encode %{
 5667     __ leaq($dst$$Register, $mem$$Address);
 5668   %}
 5669   ins_pipe(ialu_reg_reg_fat);
 5670 %}
 5671 
 5672 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
 5673 %{
 5674   predicate(CompressedOops::shift() == 0);
 5675   match(Set dst mem);
 5676 
 5677   ins_cost(110);
 5678   format %{ "leaq    $dst, $mem\t# ptr posidxoffnarrow" %}
 5679   ins_encode %{
 5680     __ leaq($dst$$Register, $mem$$Address);
 5681   %}
 5682   ins_pipe(ialu_reg_reg_fat);
 5683 %}
 5684 
 5685 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
 5686 %{
 5687   predicate(CompressedOops::shift() == 0);
 5688   match(Set dst mem);
 5689 
 5690   ins_cost(110);
 5691   format %{ "leaq    $dst, $mem\t# ptr posidxscaleoffnarrow" %}
 5692   ins_encode %{
 5693     __ leaq($dst$$Register, $mem$$Address);
 5694   %}
 5695   ins_pipe(ialu_reg_reg_fat);
 5696 %}
 5697 
 5698 instruct loadConI(rRegI dst, immI src)
 5699 %{
 5700   match(Set dst src);
 5701 
 5702   format %{ "movl    $dst, $src\t# int" %}
 5703   ins_encode %{
 5704     __ movl($dst$$Register, $src$$constant);
 5705   %}
 5706   ins_pipe(ialu_reg_fat); // XXX
 5707 %}
 5708 
 5709 instruct loadConI0(rRegI dst, immI_0 src, rFlagsReg cr)
 5710 %{
 5711   match(Set dst src);
 5712   effect(KILL cr);
 5713 
 5714   ins_cost(50);
 5715   format %{ "xorl    $dst, $dst\t# int" %}
 5716   ins_encode %{
 5717     __ xorl($dst$$Register, $dst$$Register);
 5718   %}
 5719   ins_pipe(ialu_reg);
 5720 %}
 5721 
 5722 instruct loadConL(rRegL dst, immL src)
 5723 %{
 5724   match(Set dst src);
 5725 
 5726   ins_cost(150);
 5727   format %{ "movq    $dst, $src\t# long" %}
 5728   ins_encode %{
 5729     __ mov64($dst$$Register, $src$$constant);
 5730   %}
 5731   ins_pipe(ialu_reg);
 5732 %}
 5733 
 5734 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
 5735 %{
 5736   match(Set dst src);
 5737   effect(KILL cr);
 5738 
 5739   ins_cost(50);
 5740   format %{ "xorl    $dst, $dst\t# long" %}
 5741   ins_encode %{
 5742     __ xorl($dst$$Register, $dst$$Register);
 5743   %}
 5744   ins_pipe(ialu_reg); // XXX
 5745 %}
 5746 
 5747 instruct loadConUL32(rRegL dst, immUL32 src)
 5748 %{
 5749   match(Set dst src);
 5750 
 5751   ins_cost(60);
 5752   format %{ "movl    $dst, $src\t# long (unsigned 32-bit)" %}
 5753   ins_encode %{
 5754     __ movl($dst$$Register, $src$$constant);
 5755   %}
 5756   ins_pipe(ialu_reg);
 5757 %}
 5758 
 5759 instruct loadConL32(rRegL dst, immL32 src)
 5760 %{
 5761   match(Set dst src);
 5762 
 5763   ins_cost(70);
 5764   format %{ "movq    $dst, $src\t# long (32-bit)" %}
 5765   ins_encode %{
 5766     __ movq($dst$$Register, $src$$constant);
 5767   %}
 5768   ins_pipe(ialu_reg);
 5769 %}
 5770 
 5771 instruct loadConP(rRegP dst, immP con) %{
 5772   match(Set dst con);
 5773 
 5774   format %{ "movq    $dst, $con\t# ptr" %}
 5775   ins_encode %{
 5776     __ mov64($dst$$Register, $con$$constant, $con->constant_reloc(), RELOC_IMM64);
 5777   %}
 5778   ins_pipe(ialu_reg_fat); // XXX
 5779 %}
 5780 
 5781 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
 5782 %{
 5783   match(Set dst src);
 5784   effect(KILL cr);
 5785 
 5786   ins_cost(50);
 5787   format %{ "xorl    $dst, $dst\t# ptr" %}
 5788   ins_encode %{
 5789     __ xorl($dst$$Register, $dst$$Register);
 5790   %}
 5791   ins_pipe(ialu_reg);
 5792 %}
 5793 
 5794 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
 5795 %{
 5796   match(Set dst src);
 5797   effect(KILL cr);
 5798 
 5799   ins_cost(60);
 5800   format %{ "movl    $dst, $src\t# ptr (positive 32-bit)" %}
 5801   ins_encode %{
 5802     __ movl($dst$$Register, $src$$constant);
 5803   %}
 5804   ins_pipe(ialu_reg);
 5805 %}
 5806 
 5807 instruct loadConF(regF dst, immF con) %{
 5808   match(Set dst con);
 5809   ins_cost(125);
 5810   format %{ "movss   $dst, [$constantaddress]\t# load from constant table: float=$con" %}
 5811   ins_encode %{
 5812     __ movflt($dst$$XMMRegister, $constantaddress($con));
 5813   %}
 5814   ins_pipe(pipe_slow);
 5815 %}
 5816 
 5817 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
 5818   match(Set dst src);
 5819   effect(KILL cr);
 5820   format %{ "xorq    $dst, $src\t# compressed NULL ptr" %}
 5821   ins_encode %{
 5822     __ xorq($dst$$Register, $dst$$Register);
 5823   %}
 5824   ins_pipe(ialu_reg);
 5825 %}
 5826 
 5827 instruct loadConN(rRegN dst, immN src) %{
 5828   match(Set dst src);
 5829 
 5830   ins_cost(125);
 5831   format %{ "movl    $dst, $src\t# compressed ptr" %}
 5832   ins_encode %{
 5833     address con = (address)$src$$constant;
 5834     if (con == NULL) {
 5835       ShouldNotReachHere();
 5836     } else {
 5837       __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
 5838     }
 5839   %}
 5840   ins_pipe(ialu_reg_fat); // XXX
 5841 %}
 5842 
 5843 instruct loadConNKlass(rRegN dst, immNKlass src) %{
 5844   match(Set dst src);
 5845 
 5846   ins_cost(125);
 5847   format %{ "movl    $dst, $src\t# compressed klass ptr" %}
 5848   ins_encode %{
 5849     address con = (address)$src$$constant;
 5850     if (con == NULL) {
 5851       ShouldNotReachHere();
 5852     } else {
 5853       __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
 5854     }
 5855   %}
 5856   ins_pipe(ialu_reg_fat); // XXX
 5857 %}
 5858 
 5859 instruct loadConF0(regF dst, immF0 src)
 5860 %{
 5861   match(Set dst src);
 5862   ins_cost(100);
 5863 
 5864   format %{ "xorps   $dst, $dst\t# float 0.0" %}
 5865   ins_encode %{
 5866     __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
 5867   %}
 5868   ins_pipe(pipe_slow);
 5869 %}
 5870 
 5871 // Use the same format since predicate() can not be used here.
 5872 instruct loadConD(regD dst, immD con) %{
 5873   match(Set dst con);
 5874   ins_cost(125);
 5875   format %{ "movsd   $dst, [$constantaddress]\t# load from constant table: double=$con" %}
 5876   ins_encode %{
 5877     __ movdbl($dst$$XMMRegister, $constantaddress($con));
 5878   %}
 5879   ins_pipe(pipe_slow);
 5880 %}
 5881 
 5882 instruct loadConD0(regD dst, immD0 src)
 5883 %{
 5884   match(Set dst src);
 5885   ins_cost(100);
 5886 
 5887   format %{ "xorpd   $dst, $dst\t# double 0.0" %}
 5888   ins_encode %{
 5889     __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
 5890   %}
 5891   ins_pipe(pipe_slow);
 5892 %}
 5893 
 5894 instruct loadSSI(rRegI dst, stackSlotI src)
 5895 %{
 5896   match(Set dst src);
 5897 
 5898   ins_cost(125);
 5899   format %{ "movl    $dst, $src\t# int stk" %}
 5900   opcode(0x8B);
 5901   ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
 5902   ins_pipe(ialu_reg_mem);
 5903 %}
 5904 
 5905 instruct loadSSL(rRegL dst, stackSlotL src)
 5906 %{
 5907   match(Set dst src);
 5908 
 5909   ins_cost(125);
 5910   format %{ "movq    $dst, $src\t# long stk" %}
 5911   opcode(0x8B);
 5912   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
 5913   ins_pipe(ialu_reg_mem);
 5914 %}
 5915 
 5916 instruct loadSSP(rRegP dst, stackSlotP src)
 5917 %{
 5918   match(Set dst src);
 5919 
 5920   ins_cost(125);
 5921   format %{ "movq    $dst, $src\t# ptr stk" %}
 5922   opcode(0x8B);
 5923   ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
 5924   ins_pipe(ialu_reg_mem);
 5925 %}
 5926 
 5927 instruct loadSSF(regF dst, stackSlotF src)
 5928 %{
 5929   match(Set dst src);
 5930 
 5931   ins_cost(125);
 5932   format %{ "movss   $dst, $src\t# float stk" %}
 5933   ins_encode %{
 5934     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
 5935   %}
 5936   ins_pipe(pipe_slow); // XXX
 5937 %}
 5938 
 5939 // Use the same format since predicate() can not be used here.
 5940 instruct loadSSD(regD dst, stackSlotD src)
 5941 %{
 5942   match(Set dst src);
 5943 
 5944   ins_cost(125);
 5945   format %{ "movsd   $dst, $src\t# double stk" %}
 5946   ins_encode  %{
 5947     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
 5948   %}
 5949   ins_pipe(pipe_slow); // XXX
 5950 %}
 5951 
 5952 // Prefetch instructions for allocation.
 5953 // Must be safe to execute with invalid address (cannot fault).
 5954 
 5955 instruct prefetchAlloc( memory mem ) %{
 5956   predicate(AllocatePrefetchInstr==3);
 5957   match(PrefetchAllocation mem);
 5958   ins_cost(125);
 5959 
 5960   format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
 5961   ins_encode %{
 5962     __ prefetchw($mem$$Address);
 5963   %}
 5964   ins_pipe(ialu_mem);
 5965 %}
 5966 
 5967 instruct prefetchAllocNTA( memory mem ) %{
 5968   predicate(AllocatePrefetchInstr==0);
 5969   match(PrefetchAllocation mem);
 5970   ins_cost(125);
 5971 
 5972   format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
 5973   ins_encode %{
 5974     __ prefetchnta($mem$$Address);
 5975   %}
 5976   ins_pipe(ialu_mem);
 5977 %}
 5978 
 5979 instruct prefetchAllocT0( memory mem ) %{
 5980   predicate(AllocatePrefetchInstr==1);
 5981   match(PrefetchAllocation mem);
 5982   ins_cost(125);
 5983 
 5984   format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
 5985   ins_encode %{
 5986     __ prefetcht0($mem$$Address);
 5987   %}
 5988   ins_pipe(ialu_mem);
 5989 %}
 5990 
 5991 instruct prefetchAllocT2( memory mem ) %{
 5992   predicate(AllocatePrefetchInstr==2);
 5993   match(PrefetchAllocation mem);
 5994   ins_cost(125);
 5995 
 5996   format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
 5997   ins_encode %{
 5998     __ prefetcht2($mem$$Address);
 5999   %}
 6000   ins_pipe(ialu_mem);
 6001 %}
 6002 
 6003 //----------Store Instructions-------------------------------------------------
 6004 
 6005 // Store Byte
 6006 instruct storeB(memory mem, rRegI src)
 6007 %{
 6008   match(Set mem (StoreB mem src));
 6009 
 6010   ins_cost(125); // XXX
 6011   format %{ "movb    $mem, $src\t# byte" %}
 6012   ins_encode %{
 6013     __ movb($mem$$Address, $src$$Register);
 6014   %}
 6015   ins_pipe(ialu_mem_reg);
 6016 %}
 6017 
 6018 // Store Char/Short
 6019 instruct storeC(memory mem, rRegI src)
 6020 %{
 6021   match(Set mem (StoreC mem src));
 6022 
 6023   ins_cost(125); // XXX
 6024   format %{ "movw    $mem, $src\t# char/short" %}
 6025   ins_encode %{
 6026     __ movw($mem$$Address, $src$$Register);
 6027   %}
 6028   ins_pipe(ialu_mem_reg);
 6029 %}
 6030 
 6031 // Store Integer
 6032 instruct storeI(memory mem, rRegI src)
 6033 %{
 6034   match(Set mem (StoreI mem src));
 6035 
 6036   ins_cost(125); // XXX
 6037   format %{ "movl    $mem, $src\t# int" %}
 6038   ins_encode %{
 6039     __ movl($mem$$Address, $src$$Register);
 6040   %}
 6041   ins_pipe(ialu_mem_reg);
 6042 %}
 6043 
 6044 // Store Long
 6045 instruct storeL(memory mem, rRegL src)
 6046 %{
 6047   match(Set mem (StoreL mem src));
 6048 
 6049   ins_cost(125); // XXX
 6050   format %{ "movq    $mem, $src\t# long" %}
 6051   ins_encode %{
 6052     __ movq($mem$$Address, $src$$Register);
 6053   %}
 6054   ins_pipe(ialu_mem_reg); // XXX
 6055 %}
 6056 
 6057 // Store Pointer
 6058 instruct storeP(memory mem, any_RegP src)
 6059 %{
 6060   match(Set mem (StoreP mem src));
 6061 
 6062   ins_cost(125); // XXX
 6063   format %{ "movq    $mem, $src\t# ptr" %}
 6064   ins_encode %{
 6065     __ movq($mem$$Address, $src$$Register);
 6066   %}
 6067   ins_pipe(ialu_mem_reg);
 6068 %}
 6069 
 6070 instruct storeImmP0(memory mem, immP0 zero)
 6071 %{
 6072   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6073   match(Set mem (StoreP mem zero));
 6074 
 6075   ins_cost(125); // XXX
 6076   format %{ "movq    $mem, R12\t# ptr (R12_heapbase==0)" %}
 6077   ins_encode %{
 6078     __ movq($mem$$Address, r12);
 6079   %}
 6080   ins_pipe(ialu_mem_reg);
 6081 %}
 6082 
 6083 // Store NULL Pointer, mark word, or other simple pointer constant.
 6084 instruct storeImmP(memory mem, immP31 src)
 6085 %{
 6086   match(Set mem (StoreP mem src));
 6087 
 6088   ins_cost(150); // XXX
 6089   format %{ "movq    $mem, $src\t# ptr" %}
 6090   ins_encode %{
 6091     __ movq($mem$$Address, $src$$constant);
 6092   %}
 6093   ins_pipe(ialu_mem_imm);
 6094 %}
 6095 
 6096 // Store Compressed Pointer
 6097 instruct storeN(memory mem, rRegN src)
 6098 %{
 6099   match(Set mem (StoreN mem src));
 6100 
 6101   ins_cost(125); // XXX
 6102   format %{ "movl    $mem, $src\t# compressed ptr" %}
 6103   ins_encode %{
 6104     __ movl($mem$$Address, $src$$Register);
 6105   %}
 6106   ins_pipe(ialu_mem_reg);
 6107 %}
 6108 
 6109 instruct storeNKlass(memory mem, rRegN src)
 6110 %{
 6111   match(Set mem (StoreNKlass mem src));
 6112 
 6113   ins_cost(125); // XXX
 6114   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 6115   ins_encode %{
 6116     __ movl($mem$$Address, $src$$Register);
 6117   %}
 6118   ins_pipe(ialu_mem_reg);
 6119 %}
 6120 
 6121 instruct storeImmN0(memory mem, immN0 zero)
 6122 %{
 6123   predicate(CompressedOops::base() == NULL);
 6124   match(Set mem (StoreN mem zero));
 6125 
 6126   ins_cost(125); // XXX
 6127   format %{ "movl    $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
 6128   ins_encode %{
 6129     __ movl($mem$$Address, r12);
 6130   %}
 6131   ins_pipe(ialu_mem_reg);
 6132 %}
 6133 
 6134 instruct storeImmN(memory mem, immN src)
 6135 %{
 6136   match(Set mem (StoreN mem src));
 6137 
 6138   ins_cost(150); // XXX
 6139   format %{ "movl    $mem, $src\t# compressed ptr" %}
 6140   ins_encode %{
 6141     address con = (address)$src$$constant;
 6142     if (con == NULL) {
 6143       __ movl($mem$$Address, (int32_t)0);
 6144     } else {
 6145       __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
 6146     }
 6147   %}
 6148   ins_pipe(ialu_mem_imm);
 6149 %}
 6150 
 6151 instruct storeImmNKlass(memory mem, immNKlass src)
 6152 %{
 6153   match(Set mem (StoreNKlass mem src));
 6154 
 6155   ins_cost(150); // XXX
 6156   format %{ "movl    $mem, $src\t# compressed klass ptr" %}
 6157   ins_encode %{
 6158     __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
 6159   %}
 6160   ins_pipe(ialu_mem_imm);
 6161 %}
 6162 
 6163 // Store Integer Immediate
 6164 instruct storeImmI0(memory mem, immI_0 zero)
 6165 %{
 6166   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6167   match(Set mem (StoreI mem zero));
 6168 
 6169   ins_cost(125); // XXX
 6170   format %{ "movl    $mem, R12\t# int (R12_heapbase==0)" %}
 6171   ins_encode %{
 6172     __ movl($mem$$Address, r12);
 6173   %}
 6174   ins_pipe(ialu_mem_reg);
 6175 %}
 6176 
 6177 instruct storeImmI(memory mem, immI src)
 6178 %{
 6179   match(Set mem (StoreI mem src));
 6180 
 6181   ins_cost(150);
 6182   format %{ "movl    $mem, $src\t# int" %}
 6183   ins_encode %{
 6184     __ movl($mem$$Address, $src$$constant);
 6185   %}
 6186   ins_pipe(ialu_mem_imm);
 6187 %}
 6188 
 6189 // Store Long Immediate
 6190 instruct storeImmL0(memory mem, immL0 zero)
 6191 %{
 6192   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6193   match(Set mem (StoreL mem zero));
 6194 
 6195   ins_cost(125); // XXX
 6196   format %{ "movq    $mem, R12\t# long (R12_heapbase==0)" %}
 6197   ins_encode %{
 6198     __ movq($mem$$Address, r12);
 6199   %}
 6200   ins_pipe(ialu_mem_reg);
 6201 %}
 6202 
 6203 instruct storeImmL(memory mem, immL32 src)
 6204 %{
 6205   match(Set mem (StoreL mem src));
 6206 
 6207   ins_cost(150);
 6208   format %{ "movq    $mem, $src\t# long" %}
 6209   ins_encode %{
 6210     __ movq($mem$$Address, $src$$constant);
 6211   %}
 6212   ins_pipe(ialu_mem_imm);
 6213 %}
 6214 
 6215 // Store Short/Char Immediate
 6216 instruct storeImmC0(memory mem, immI_0 zero)
 6217 %{
 6218   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6219   match(Set mem (StoreC mem zero));
 6220 
 6221   ins_cost(125); // XXX
 6222   format %{ "movw    $mem, R12\t# short/char (R12_heapbase==0)" %}
 6223   ins_encode %{
 6224     __ movw($mem$$Address, r12);
 6225   %}
 6226   ins_pipe(ialu_mem_reg);
 6227 %}
 6228 
 6229 instruct storeImmI16(memory mem, immI16 src)
 6230 %{
 6231   predicate(UseStoreImmI16);
 6232   match(Set mem (StoreC mem src));
 6233 
 6234   ins_cost(150);
 6235   format %{ "movw    $mem, $src\t# short/char" %}
 6236   ins_encode %{
 6237     __ movw($mem$$Address, $src$$constant);
 6238   %}
 6239   ins_pipe(ialu_mem_imm);
 6240 %}
 6241 
 6242 // Store Byte Immediate
 6243 instruct storeImmB0(memory mem, immI_0 zero)
 6244 %{
 6245   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6246   match(Set mem (StoreB mem zero));
 6247 
 6248   ins_cost(125); // XXX
 6249   format %{ "movb    $mem, R12\t# short/char (R12_heapbase==0)" %}
 6250   ins_encode %{
 6251     __ movb($mem$$Address, r12);
 6252   %}
 6253   ins_pipe(ialu_mem_reg);
 6254 %}
 6255 
 6256 instruct storeImmB(memory mem, immI8 src)
 6257 %{
 6258   match(Set mem (StoreB mem src));
 6259 
 6260   ins_cost(150); // XXX
 6261   format %{ "movb    $mem, $src\t# byte" %}
 6262   ins_encode %{
 6263     __ movb($mem$$Address, $src$$constant);
 6264   %}
 6265   ins_pipe(ialu_mem_imm);
 6266 %}
 6267 
 6268 // Store CMS card-mark Immediate
 6269 instruct storeImmCM0_reg(memory mem, immI_0 zero)
 6270 %{
 6271   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6272   match(Set mem (StoreCM mem zero));
 6273 
 6274   ins_cost(125); // XXX
 6275   format %{ "movb    $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
 6276   ins_encode %{
 6277     __ movb($mem$$Address, r12);
 6278   %}
 6279   ins_pipe(ialu_mem_reg);
 6280 %}
 6281 
 6282 instruct storeImmCM0(memory mem, immI_0 src)
 6283 %{
 6284   match(Set mem (StoreCM mem src));
 6285 
 6286   ins_cost(150); // XXX
 6287   format %{ "movb    $mem, $src\t# CMS card-mark byte 0" %}
 6288   ins_encode %{
 6289     __ movb($mem$$Address, $src$$constant);
 6290   %}
 6291   ins_pipe(ialu_mem_imm);
 6292 %}
 6293 
 6294 // Store Float
 6295 instruct storeF(memory mem, regF src)
 6296 %{
 6297   match(Set mem (StoreF mem src));
 6298 
 6299   ins_cost(95); // XXX
 6300   format %{ "movss   $mem, $src\t# float" %}
 6301   ins_encode %{
 6302     __ movflt($mem$$Address, $src$$XMMRegister);
 6303   %}
 6304   ins_pipe(pipe_slow); // XXX
 6305 %}
 6306 
 6307 // Store immediate Float value (it is faster than store from XMM register)
 6308 instruct storeF0(memory mem, immF0 zero)
 6309 %{
 6310   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6311   match(Set mem (StoreF mem zero));
 6312 
 6313   ins_cost(25); // XXX
 6314   format %{ "movl    $mem, R12\t# float 0. (R12_heapbase==0)" %}
 6315   ins_encode %{
 6316     __ movl($mem$$Address, r12);
 6317   %}
 6318   ins_pipe(ialu_mem_reg);
 6319 %}
 6320 
 6321 instruct storeF_imm(memory mem, immF src)
 6322 %{
 6323   match(Set mem (StoreF mem src));
 6324 
 6325   ins_cost(50);
 6326   format %{ "movl    $mem, $src\t# float" %}
 6327   ins_encode %{
 6328     __ movl($mem$$Address, jint_cast($src$$constant));
 6329   %}
 6330   ins_pipe(ialu_mem_imm);
 6331 %}
 6332 
 6333 // Store Double
 6334 instruct storeD(memory mem, regD src)
 6335 %{
 6336   match(Set mem (StoreD mem src));
 6337 
 6338   ins_cost(95); // XXX
 6339   format %{ "movsd   $mem, $src\t# double" %}
 6340   ins_encode %{
 6341     __ movdbl($mem$$Address, $src$$XMMRegister);
 6342   %}
 6343   ins_pipe(pipe_slow); // XXX
 6344 %}
 6345 
 6346 // Store immediate double 0.0 (it is faster than store from XMM register)
 6347 instruct storeD0_imm(memory mem, immD0 src)
 6348 %{
 6349   predicate(!UseCompressedOops || (CompressedOops::base() != NULL));
 6350   match(Set mem (StoreD mem src));
 6351 
 6352   ins_cost(50);
 6353   format %{ "movq    $mem, $src\t# double 0." %}
 6354   ins_encode %{
 6355     __ movq($mem$$Address, $src$$constant);
 6356   %}
 6357   ins_pipe(ialu_mem_imm);
 6358 %}
 6359 
 6360 instruct storeD0(memory mem, immD0 zero)
 6361 %{
 6362   predicate(UseCompressedOops && (CompressedOops::base() == NULL));
 6363   match(Set mem (StoreD mem zero));
 6364 
 6365   ins_cost(25); // XXX
 6366   format %{ "movq    $mem, R12\t# double 0. (R12_heapbase==0)" %}
 6367   ins_encode %{
 6368     __ movq($mem$$Address, r12);
 6369   %}
 6370   ins_pipe(ialu_mem_reg);
 6371 %}
 6372 
 6373 instruct storeSSI(stackSlotI dst, rRegI src)
 6374 %{
 6375   match(Set dst src);
 6376 
 6377   ins_cost(100);
 6378   format %{ "movl    $dst, $src\t# int stk" %}
 6379   opcode(0x89);
 6380   ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
 6381   ins_pipe( ialu_mem_reg );
 6382 %}
 6383 
 6384 instruct storeSSL(stackSlotL dst, rRegL src)
 6385 %{
 6386   match(Set dst src);
 6387 
 6388   ins_cost(100);
 6389   format %{ "movq    $dst, $src\t# long stk" %}
 6390   opcode(0x89);
 6391   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
 6392   ins_pipe(ialu_mem_reg);
 6393 %}
 6394 
 6395 instruct storeSSP(stackSlotP dst, rRegP src)
 6396 %{
 6397   match(Set dst src);
 6398 
 6399   ins_cost(100);
 6400   format %{ "movq    $dst, $src\t# ptr stk" %}
 6401   opcode(0x89);
 6402   ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
 6403   ins_pipe(ialu_mem_reg);
 6404 %}
 6405 
 6406 instruct storeSSF(stackSlotF dst, regF src)
 6407 %{
 6408   match(Set dst src);
 6409 
 6410   ins_cost(95); // XXX
 6411   format %{ "movss   $dst, $src\t# float stk" %}
 6412   ins_encode %{
 6413     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
 6414   %}
 6415   ins_pipe(pipe_slow); // XXX
 6416 %}
 6417 
 6418 instruct storeSSD(stackSlotD dst, regD src)
 6419 %{
 6420   match(Set dst src);
 6421 
 6422   ins_cost(95); // XXX
 6423   format %{ "movsd   $dst, $src\t# double stk" %}
 6424   ins_encode %{
 6425     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
 6426   %}
 6427   ins_pipe(pipe_slow); // XXX
 6428 %}
 6429 
 6430 instruct cacheWB(indirect addr)
 6431 %{
 6432   predicate(VM_Version::supports_data_cache_line_flush());
 6433   match(CacheWB addr);
 6434 
 6435   ins_cost(100);
 6436   format %{"cache wb $addr" %}
 6437   ins_encode %{
 6438     assert($addr->index_position() < 0, "should be");
 6439     assert($addr$$disp == 0, "should be");
 6440     __ cache_wb(Address($addr$$base$$Register, 0));
 6441   %}
 6442   ins_pipe(pipe_slow); // XXX
 6443 %}
 6444 
 6445 instruct cacheWBPreSync()
 6446 %{
 6447   predicate(VM_Version::supports_data_cache_line_flush());
 6448   match(CacheWBPreSync);
 6449 
 6450   ins_cost(100);
 6451   format %{"cache wb presync" %}
 6452   ins_encode %{
 6453     __ cache_wbsync(true);
 6454   %}
 6455   ins_pipe(pipe_slow); // XXX
 6456 %}
 6457 
 6458 instruct cacheWBPostSync()
 6459 %{
 6460   predicate(VM_Version::supports_data_cache_line_flush());
 6461   match(CacheWBPostSync);
 6462 
 6463   ins_cost(100);
 6464   format %{"cache wb postsync" %}
 6465   ins_encode %{
 6466     __ cache_wbsync(false);
 6467   %}
 6468   ins_pipe(pipe_slow); // XXX
 6469 %}
 6470 
 6471 //----------BSWAP Instructions-------------------------------------------------
 6472 instruct bytes_reverse_int(rRegI dst) %{
 6473   match(Set dst (ReverseBytesI dst));
 6474 
 6475   format %{ "bswapl  $dst" %}
 6476   ins_encode %{
 6477     __ bswapl($dst$$Register);
 6478   %}
 6479   ins_pipe( ialu_reg );
 6480 %}
 6481 
 6482 instruct bytes_reverse_long(rRegL dst) %{
 6483   match(Set dst (ReverseBytesL dst));
 6484 
 6485   format %{ "bswapq  $dst" %}
 6486   ins_encode %{
 6487     __ bswapq($dst$$Register);
 6488   %}
 6489   ins_pipe( ialu_reg);
 6490 %}
 6491 
 6492 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
 6493   match(Set dst (ReverseBytesUS dst));
 6494   effect(KILL cr);
 6495 
 6496   format %{ "bswapl  $dst\n\t"
 6497             "shrl    $dst,16\n\t" %}
 6498   ins_encode %{
 6499     __ bswapl($dst$$Register);
 6500     __ shrl($dst$$Register, 16);
 6501   %}
 6502   ins_pipe( ialu_reg );
 6503 %}
 6504 
 6505 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
 6506   match(Set dst (ReverseBytesS dst));
 6507   effect(KILL cr);
 6508 
 6509   format %{ "bswapl  $dst\n\t"
 6510             "sar     $dst,16\n\t" %}
 6511   ins_encode %{
 6512     __ bswapl($dst$$Register);
 6513     __ sarl($dst$$Register, 16);
 6514   %}
 6515   ins_pipe( ialu_reg );
 6516 %}
 6517 
 6518 //---------- Zeros Count Instructions ------------------------------------------
 6519 
 6520 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6521   predicate(UseCountLeadingZerosInstruction);
 6522   match(Set dst (CountLeadingZerosI src));
 6523   effect(KILL cr);
 6524 
 6525   format %{ "lzcntl  $dst, $src\t# count leading zeros (int)" %}
 6526   ins_encode %{
 6527     __ lzcntl($dst$$Register, $src$$Register);
 6528   %}
 6529   ins_pipe(ialu_reg);
 6530 %}
 6531 
 6532 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
 6533   predicate(!UseCountLeadingZerosInstruction);
 6534   match(Set dst (CountLeadingZerosI src));
 6535   effect(KILL cr);
 6536 
 6537   format %{ "bsrl    $dst, $src\t# count leading zeros (int)\n\t"
 6538             "jnz     skip\n\t"
 6539             "movl    $dst, -1\n"
 6540       "skip:\n\t"
 6541             "negl    $dst\n\t"
 6542             "addl    $dst, 31" %}
 6543   ins_encode %{
 6544     Register Rdst = $dst$$Register;
 6545     Register Rsrc = $src$$Register;
 6546     Label skip;
 6547     __ bsrl(Rdst, Rsrc);
 6548     __ jccb(Assembler::notZero, skip);
 6549     __ movl(Rdst, -1);
 6550     __ bind(skip);
 6551     __ negl(Rdst);
 6552     __ addl(Rdst, BitsPerInt - 1);
 6553   %}
 6554   ins_pipe(ialu_reg);
 6555 %}
 6556 
 6557 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6558   predicate(UseCountLeadingZerosInstruction);
 6559   match(Set dst (CountLeadingZerosL src));
 6560   effect(KILL cr);
 6561 
 6562   format %{ "lzcntq  $dst, $src\t# count leading zeros (long)" %}
 6563   ins_encode %{
 6564     __ lzcntq($dst$$Register, $src$$Register);
 6565   %}
 6566   ins_pipe(ialu_reg);
 6567 %}
 6568 
 6569 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
 6570   predicate(!UseCountLeadingZerosInstruction);
 6571   match(Set dst (CountLeadingZerosL src));
 6572   effect(KILL cr);
 6573 
 6574   format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
 6575             "jnz     skip\n\t"
 6576             "movl    $dst, -1\n"
 6577       "skip:\n\t"
 6578             "negl    $dst\n\t"
 6579             "addl    $dst, 63" %}
 6580   ins_encode %{
 6581     Register Rdst = $dst$$Register;
 6582     Register Rsrc = $src$$Register;
 6583     Label skip;
 6584     __ bsrq(Rdst, Rsrc);
 6585     __ jccb(Assembler::notZero, skip);
 6586     __ movl(Rdst, -1);
 6587     __ bind(skip);
 6588     __ negl(Rdst);
 6589     __ addl(Rdst, BitsPerLong - 1);
 6590   %}
 6591   ins_pipe(ialu_reg);
 6592 %}
 6593 
 6594 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6595   predicate(UseCountTrailingZerosInstruction);
 6596   match(Set dst (CountTrailingZerosI src));
 6597   effect(KILL cr);
 6598 
 6599   format %{ "tzcntl    $dst, $src\t# count trailing zeros (int)" %}
 6600   ins_encode %{
 6601     __ tzcntl($dst$$Register, $src$$Register);
 6602   %}
 6603   ins_pipe(ialu_reg);
 6604 %}
 6605 
 6606 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
 6607   predicate(!UseCountTrailingZerosInstruction);
 6608   match(Set dst (CountTrailingZerosI src));
 6609   effect(KILL cr);
 6610 
 6611   format %{ "bsfl    $dst, $src\t# count trailing zeros (int)\n\t"
 6612             "jnz     done\n\t"
 6613             "movl    $dst, 32\n"
 6614       "done:" %}
 6615   ins_encode %{
 6616     Register Rdst = $dst$$Register;
 6617     Label done;
 6618     __ bsfl(Rdst, $src$$Register);
 6619     __ jccb(Assembler::notZero, done);
 6620     __ movl(Rdst, BitsPerInt);
 6621     __ bind(done);
 6622   %}
 6623   ins_pipe(ialu_reg);
 6624 %}
 6625 
 6626 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6627   predicate(UseCountTrailingZerosInstruction);
 6628   match(Set dst (CountTrailingZerosL src));
 6629   effect(KILL cr);
 6630 
 6631   format %{ "tzcntq    $dst, $src\t# count trailing zeros (long)" %}
 6632   ins_encode %{
 6633     __ tzcntq($dst$$Register, $src$$Register);
 6634   %}
 6635   ins_pipe(ialu_reg);
 6636 %}
 6637 
 6638 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
 6639   predicate(!UseCountTrailingZerosInstruction);
 6640   match(Set dst (CountTrailingZerosL src));
 6641   effect(KILL cr);
 6642 
 6643   format %{ "bsfq    $dst, $src\t# count trailing zeros (long)\n\t"
 6644             "jnz     done\n\t"
 6645             "movl    $dst, 64\n"
 6646       "done:" %}
 6647   ins_encode %{
 6648     Register Rdst = $dst$$Register;
 6649     Label done;
 6650     __ bsfq(Rdst, $src$$Register);
 6651     __ jccb(Assembler::notZero, done);
 6652     __ movl(Rdst, BitsPerLong);
 6653     __ bind(done);
 6654   %}
 6655   ins_pipe(ialu_reg);
 6656 %}
 6657 
 6658 
 6659 //---------- Population Count Instructions -------------------------------------
 6660 
 6661 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
 6662   predicate(UsePopCountInstruction);
 6663   match(Set dst (PopCountI src));
 6664   effect(KILL cr);
 6665 
 6666   format %{ "popcnt  $dst, $src" %}
 6667   ins_encode %{
 6668     __ popcntl($dst$$Register, $src$$Register);
 6669   %}
 6670   ins_pipe(ialu_reg);
 6671 %}
 6672 
 6673 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 6674   predicate(UsePopCountInstruction);
 6675   match(Set dst (PopCountI (LoadI mem)));
 6676   effect(KILL cr);
 6677 
 6678   format %{ "popcnt  $dst, $mem" %}
 6679   ins_encode %{
 6680     __ popcntl($dst$$Register, $mem$$Address);
 6681   %}
 6682   ins_pipe(ialu_reg);
 6683 %}
 6684 
 6685 // Note: Long.bitCount(long) returns an int.
 6686 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
 6687   predicate(UsePopCountInstruction);
 6688   match(Set dst (PopCountL src));
 6689   effect(KILL cr);
 6690 
 6691   format %{ "popcnt  $dst, $src" %}
 6692   ins_encode %{
 6693     __ popcntq($dst$$Register, $src$$Register);
 6694   %}
 6695   ins_pipe(ialu_reg);
 6696 %}
 6697 
 6698 // Note: Long.bitCount(long) returns an int.
 6699 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
 6700   predicate(UsePopCountInstruction);
 6701   match(Set dst (PopCountL (LoadL mem)));
 6702   effect(KILL cr);
 6703 
 6704   format %{ "popcnt  $dst, $mem" %}
 6705   ins_encode %{
 6706     __ popcntq($dst$$Register, $mem$$Address);
 6707   %}
 6708   ins_pipe(ialu_reg);
 6709 %}
 6710 
 6711 
 6712 //----------MemBar Instructions-----------------------------------------------
 6713 // Memory barrier flavors
 6714 
 6715 instruct membar_acquire()
 6716 %{
 6717   match(MemBarAcquire);
 6718   match(LoadFence);
 6719   ins_cost(0);
 6720 
 6721   size(0);
 6722   format %{ "MEMBAR-acquire ! (empty encoding)" %}
 6723   ins_encode();
 6724   ins_pipe(empty);
 6725 %}
 6726 
 6727 instruct membar_acquire_lock()
 6728 %{
 6729   match(MemBarAcquireLock);
 6730   ins_cost(0);
 6731 
 6732   size(0);
 6733   format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
 6734   ins_encode();
 6735   ins_pipe(empty);
 6736 %}
 6737 
 6738 instruct membar_release()
 6739 %{
 6740   match(MemBarRelease);
 6741   match(StoreFence);
 6742   ins_cost(0);
 6743 
 6744   size(0);
 6745   format %{ "MEMBAR-release ! (empty encoding)" %}
 6746   ins_encode();
 6747   ins_pipe(empty);
 6748 %}
 6749 
 6750 instruct membar_release_lock()
 6751 %{
 6752   match(MemBarReleaseLock);
 6753   ins_cost(0);
 6754 
 6755   size(0);
 6756   format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
 6757   ins_encode();
 6758   ins_pipe(empty);
 6759 %}
 6760 
 6761 instruct membar_volatile(rFlagsReg cr) %{
 6762   match(MemBarVolatile);
 6763   effect(KILL cr);
 6764   ins_cost(400);
 6765 
 6766   format %{
 6767     $$template
 6768     $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
 6769   %}
 6770   ins_encode %{
 6771     __ membar(Assembler::StoreLoad);
 6772   %}
 6773   ins_pipe(pipe_slow);
 6774 %}
 6775 
 6776 instruct unnecessary_membar_volatile()
 6777 %{
 6778   match(MemBarVolatile);
 6779   predicate(Matcher::post_store_load_barrier(n));
 6780   ins_cost(0);
 6781 
 6782   size(0);
 6783   format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
 6784   ins_encode();
 6785   ins_pipe(empty);
 6786 %}
 6787 
 6788 instruct membar_storestore() %{
 6789   match(MemBarStoreStore);
 6790   match(StoreStoreFence);
 6791   ins_cost(0);
 6792 
 6793   size(0);
 6794   format %{ "MEMBAR-storestore (empty encoding)" %}
 6795   ins_encode( );
 6796   ins_pipe(empty);
 6797 %}
 6798 
 6799 //----------Move Instructions--------------------------------------------------
 6800 
 6801 instruct castX2P(rRegP dst, rRegL src)
 6802 %{
 6803   match(Set dst (CastX2P src));
 6804 
 6805   format %{ "movq    $dst, $src\t# long->ptr" %}
 6806   ins_encode %{
 6807     if ($dst$$reg != $src$$reg) {
 6808       __ movptr($dst$$Register, $src$$Register);
 6809     }
 6810   %}
 6811   ins_pipe(ialu_reg_reg); // XXX
 6812 %}
 6813 
 6814 instruct castP2X(rRegL dst, rRegP src)
 6815 %{
 6816   match(Set dst (CastP2X src));
 6817 
 6818   format %{ "movq    $dst, $src\t# ptr -> long" %}
 6819   ins_encode %{
 6820     if ($dst$$reg != $src$$reg) {
 6821       __ movptr($dst$$Register, $src$$Register);
 6822     }
 6823   %}
 6824   ins_pipe(ialu_reg_reg); // XXX
 6825 %}
 6826 
 6827 // Convert oop into int for vectors alignment masking
 6828 instruct convP2I(rRegI dst, rRegP src)
 6829 %{
 6830   match(Set dst (ConvL2I (CastP2X src)));
 6831 
 6832   format %{ "movl    $dst, $src\t# ptr -> int" %}
 6833   ins_encode %{
 6834     __ movl($dst$$Register, $src$$Register);
 6835   %}
 6836   ins_pipe(ialu_reg_reg); // XXX
 6837 %}
 6838 
 6839 // Convert compressed oop into int for vectors alignment masking
 6840 // in case of 32bit oops (heap < 4Gb).
 6841 instruct convN2I(rRegI dst, rRegN src)
 6842 %{
 6843   predicate(CompressedOops::shift() == 0);
 6844   match(Set dst (ConvL2I (CastP2X (DecodeN src))));
 6845 
 6846   format %{ "movl    $dst, $src\t# compressed ptr -> int" %}
 6847   ins_encode %{
 6848     __ movl($dst$$Register, $src$$Register);
 6849   %}
 6850   ins_pipe(ialu_reg_reg); // XXX
 6851 %}
 6852 
 6853 // Convert oop pointer into compressed form
 6854 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
 6855   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
 6856   match(Set dst (EncodeP src));
 6857   effect(KILL cr);
 6858   format %{ "encode_heap_oop $dst,$src" %}
 6859   ins_encode %{
 6860     Register s = $src$$Register;
 6861     Register d = $dst$$Register;
 6862     if (s != d) {
 6863       __ movq(d, s);
 6864     }
 6865     __ encode_heap_oop(d);
 6866   %}
 6867   ins_pipe(ialu_reg_long);
 6868 %}
 6869 
 6870 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6871   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
 6872   match(Set dst (EncodeP src));
 6873   effect(KILL cr);
 6874   format %{ "encode_heap_oop_not_null $dst,$src" %}
 6875   ins_encode %{
 6876     __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
 6877   %}
 6878   ins_pipe(ialu_reg_long);
 6879 %}
 6880 
 6881 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
 6882   predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
 6883             n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
 6884   match(Set dst (DecodeN src));
 6885   effect(KILL cr);
 6886   format %{ "decode_heap_oop $dst,$src" %}
 6887   ins_encode %{
 6888     Register s = $src$$Register;
 6889     Register d = $dst$$Register;
 6890     if (s != d) {
 6891       __ movq(d, s);
 6892     }
 6893     __ decode_heap_oop(d);
 6894   %}
 6895   ins_pipe(ialu_reg_long);
 6896 %}
 6897 
 6898 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6899   predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
 6900             n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
 6901   match(Set dst (DecodeN src));
 6902   effect(KILL cr);
 6903   format %{ "decode_heap_oop_not_null $dst,$src" %}
 6904   ins_encode %{
 6905     Register s = $src$$Register;
 6906     Register d = $dst$$Register;
 6907     if (s != d) {
 6908       __ decode_heap_oop_not_null(d, s);
 6909     } else {
 6910       __ decode_heap_oop_not_null(d);
 6911     }
 6912   %}
 6913   ins_pipe(ialu_reg_long);
 6914 %}
 6915 
 6916 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
 6917   match(Set dst (EncodePKlass src));
 6918   effect(TEMP dst, KILL cr);
 6919   format %{ "encode_and_move_klass_not_null $dst,$src" %}
 6920   ins_encode %{
 6921     __ encode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6922   %}
 6923   ins_pipe(ialu_reg_long);
 6924 %}
 6925 
 6926 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
 6927   match(Set dst (DecodeNKlass src));
 6928   effect(TEMP dst, KILL cr);
 6929   format %{ "decode_and_move_klass_not_null $dst,$src" %}
 6930   ins_encode %{
 6931     __ decode_and_move_klass_not_null($dst$$Register, $src$$Register);
 6932   %}
 6933   ins_pipe(ialu_reg_long);
 6934 %}
 6935 
 6936 //----------Conditional Move---------------------------------------------------
 6937 // Jump
 6938 // dummy instruction for generating temp registers
 6939 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
 6940   match(Jump (LShiftL switch_val shift));
 6941   ins_cost(350);
 6942   predicate(false);
 6943   effect(TEMP dest);
 6944 
 6945   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6946             "jmp     [$dest + $switch_val << $shift]\n\t" %}
 6947   ins_encode %{
 6948     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6949     // to do that and the compiler is using that register as one it can allocate.
 6950     // So we build it all by hand.
 6951     // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
 6952     // ArrayAddress dispatch(table, index);
 6953     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
 6954     __ lea($dest$$Register, $constantaddress);
 6955     __ jmp(dispatch);
 6956   %}
 6957   ins_pipe(pipe_jmp);
 6958 %}
 6959 
 6960 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
 6961   match(Jump (AddL (LShiftL switch_val shift) offset));
 6962   ins_cost(350);
 6963   effect(TEMP dest);
 6964 
 6965   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6966             "jmp     [$dest + $switch_val << $shift + $offset]\n\t" %}
 6967   ins_encode %{
 6968     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6969     // to do that and the compiler is using that register as one it can allocate.
 6970     // So we build it all by hand.
 6971     // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6972     // ArrayAddress dispatch(table, index);
 6973     Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
 6974     __ lea($dest$$Register, $constantaddress);
 6975     __ jmp(dispatch);
 6976   %}
 6977   ins_pipe(pipe_jmp);
 6978 %}
 6979 
 6980 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
 6981   match(Jump switch_val);
 6982   ins_cost(350);
 6983   effect(TEMP dest);
 6984 
 6985   format %{ "leaq    $dest, [$constantaddress]\n\t"
 6986             "jmp     [$dest + $switch_val]\n\t" %}
 6987   ins_encode %{
 6988     // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
 6989     // to do that and the compiler is using that register as one it can allocate.
 6990     // So we build it all by hand.
 6991     // Address index(noreg, switch_reg, Address::times_1);
 6992     // ArrayAddress dispatch(table, index);
 6993     Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
 6994     __ lea($dest$$Register, $constantaddress);
 6995     __ jmp(dispatch);
 6996   %}
 6997   ins_pipe(pipe_jmp);
 6998 %}
 6999 
 7000 // Conditional move
 7001 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
 7002 %{
 7003   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 7004 
 7005   ins_cost(200); // XXX
 7006   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 7007   ins_encode %{
 7008     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7009   %}
 7010   ins_pipe(pipe_cmov_reg);
 7011 %}
 7012 
 7013 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
 7014   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 7015 
 7016   ins_cost(200); // XXX
 7017   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 7018   ins_encode %{
 7019     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7020   %}
 7021   ins_pipe(pipe_cmov_reg);
 7022 %}
 7023 
 7024 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
 7025   match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
 7026   ins_cost(200);
 7027   expand %{
 7028     cmovI_regU(cop, cr, dst, src);
 7029   %}
 7030 %}
 7031 
 7032 // Conditional move
 7033 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
 7034   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7035 
 7036   ins_cost(250); // XXX
 7037   format %{ "cmovl$cop $dst, $src\t# signed, int" %}
 7038   ins_encode %{
 7039     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7040   %}
 7041   ins_pipe(pipe_cmov_mem);
 7042 %}
 7043 
 7044 // Conditional move
 7045 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
 7046 %{
 7047   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7048 
 7049   ins_cost(250); // XXX
 7050   format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
 7051   ins_encode %{
 7052     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7053   %}
 7054   ins_pipe(pipe_cmov_mem);
 7055 %}
 7056 
 7057 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
 7058   match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
 7059   ins_cost(250);
 7060   expand %{
 7061     cmovI_memU(cop, cr, dst, src);
 7062   %}
 7063 %}
 7064 
 7065 // Conditional move
 7066 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
 7067 %{
 7068   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7069 
 7070   ins_cost(200); // XXX
 7071   format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
 7072   ins_encode %{
 7073     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7074   %}
 7075   ins_pipe(pipe_cmov_reg);
 7076 %}
 7077 
 7078 // Conditional move
 7079 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
 7080 %{
 7081   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7082 
 7083   ins_cost(200); // XXX
 7084   format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
 7085   ins_encode %{
 7086     __ cmovl((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7087   %}
 7088   ins_pipe(pipe_cmov_reg);
 7089 %}
 7090 
 7091 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
 7092   match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
 7093   ins_cost(200);
 7094   expand %{
 7095     cmovN_regU(cop, cr, dst, src);
 7096   %}
 7097 %}
 7098 
 7099 // Conditional move
 7100 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
 7101 %{
 7102   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7103 
 7104   ins_cost(200); // XXX
 7105   format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
 7106   ins_encode %{
 7107     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7108   %}
 7109   ins_pipe(pipe_cmov_reg);  // XXX
 7110 %}
 7111 
 7112 // Conditional move
 7113 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
 7114 %{
 7115   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7116 
 7117   ins_cost(200); // XXX
 7118   format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
 7119   ins_encode %{
 7120     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7121   %}
 7122   ins_pipe(pipe_cmov_reg); // XXX
 7123 %}
 7124 
 7125 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
 7126   match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
 7127   ins_cost(200);
 7128   expand %{
 7129     cmovP_regU(cop, cr, dst, src);
 7130   %}
 7131 %}
 7132 
 7133 // DISABLED: Requires the ADLC to emit a bottom_type call that
 7134 // correctly meets the two pointer arguments; one is an incoming
 7135 // register but the other is a memory operand.  ALSO appears to
 7136 // be buggy with implicit null checks.
 7137 //
 7138 //// Conditional move
 7139 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
 7140 //%{
 7141 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
 7142 //  ins_cost(250);
 7143 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
 7144 //  opcode(0x0F,0x40);
 7145 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
 7146 //  ins_pipe( pipe_cmov_mem );
 7147 //%}
 7148 //
 7149 //// Conditional move
 7150 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
 7151 //%{
 7152 //  match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
 7153 //  ins_cost(250);
 7154 //  format %{ "CMOV$cop $dst,$src\t# ptr" %}
 7155 //  opcode(0x0F,0x40);
 7156 //  ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
 7157 //  ins_pipe( pipe_cmov_mem );
 7158 //%}
 7159 
 7160 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
 7161 %{
 7162   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7163 
 7164   ins_cost(200); // XXX
 7165   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 7166   ins_encode %{
 7167     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7168   %}
 7169   ins_pipe(pipe_cmov_reg);  // XXX
 7170 %}
 7171 
 7172 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
 7173 %{
 7174   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7175 
 7176   ins_cost(200); // XXX
 7177   format %{ "cmovq$cop $dst, $src\t# signed, long" %}
 7178   ins_encode %{
 7179     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7180   %}
 7181   ins_pipe(pipe_cmov_mem);  // XXX
 7182 %}
 7183 
 7184 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
 7185 %{
 7186   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7187 
 7188   ins_cost(200); // XXX
 7189   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 7190   ins_encode %{
 7191     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Register);
 7192   %}
 7193   ins_pipe(pipe_cmov_reg); // XXX
 7194 %}
 7195 
 7196 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
 7197   match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
 7198   ins_cost(200);
 7199   expand %{
 7200     cmovL_regU(cop, cr, dst, src);
 7201   %}
 7202 %}
 7203 
 7204 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
 7205 %{
 7206   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7207 
 7208   ins_cost(200); // XXX
 7209   format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
 7210   ins_encode %{
 7211     __ cmovq((Assembler::Condition)($cop$$cmpcode), $dst$$Register, $src$$Address);
 7212   %}
 7213   ins_pipe(pipe_cmov_mem); // XXX
 7214 %}
 7215 
 7216 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
 7217   match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
 7218   ins_cost(200);
 7219   expand %{
 7220     cmovL_memU(cop, cr, dst, src);
 7221   %}
 7222 %}
 7223 
 7224 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
 7225 %{
 7226   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7227 
 7228   ins_cost(200); // XXX
 7229   format %{ "jn$cop    skip\t# signed cmove float\n\t"
 7230             "movss     $dst, $src\n"
 7231     "skip:" %}
 7232   ins_encode %{
 7233     Label Lskip;
 7234     // Invert sense of branch from sense of CMOV
 7235     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7236     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 7237     __ bind(Lskip);
 7238   %}
 7239   ins_pipe(pipe_slow);
 7240 %}
 7241 
 7242 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
 7243 // %{
 7244 //   match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
 7245 
 7246 //   ins_cost(200); // XXX
 7247 //   format %{ "jn$cop    skip\t# signed cmove float\n\t"
 7248 //             "movss     $dst, $src\n"
 7249 //     "skip:" %}
 7250 //   ins_encode(enc_cmovf_mem_branch(cop, dst, src));
 7251 //   ins_pipe(pipe_slow);
 7252 // %}
 7253 
 7254 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
 7255 %{
 7256   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7257 
 7258   ins_cost(200); // XXX
 7259   format %{ "jn$cop    skip\t# unsigned cmove float\n\t"
 7260             "movss     $dst, $src\n"
 7261     "skip:" %}
 7262   ins_encode %{
 7263     Label Lskip;
 7264     // Invert sense of branch from sense of CMOV
 7265     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7266     __ movflt($dst$$XMMRegister, $src$$XMMRegister);
 7267     __ bind(Lskip);
 7268   %}
 7269   ins_pipe(pipe_slow);
 7270 %}
 7271 
 7272 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
 7273   match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
 7274   ins_cost(200);
 7275   expand %{
 7276     cmovF_regU(cop, cr, dst, src);
 7277   %}
 7278 %}
 7279 
 7280 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
 7281 %{
 7282   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7283 
 7284   ins_cost(200); // XXX
 7285   format %{ "jn$cop    skip\t# signed cmove double\n\t"
 7286             "movsd     $dst, $src\n"
 7287     "skip:" %}
 7288   ins_encode %{
 7289     Label Lskip;
 7290     // Invert sense of branch from sense of CMOV
 7291     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7292     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 7293     __ bind(Lskip);
 7294   %}
 7295   ins_pipe(pipe_slow);
 7296 %}
 7297 
 7298 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
 7299 %{
 7300   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7301 
 7302   ins_cost(200); // XXX
 7303   format %{ "jn$cop    skip\t# unsigned cmove double\n\t"
 7304             "movsd     $dst, $src\n"
 7305     "skip:" %}
 7306   ins_encode %{
 7307     Label Lskip;
 7308     // Invert sense of branch from sense of CMOV
 7309     __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
 7310     __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
 7311     __ bind(Lskip);
 7312   %}
 7313   ins_pipe(pipe_slow);
 7314 %}
 7315 
 7316 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
 7317   match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
 7318   ins_cost(200);
 7319   expand %{
 7320     cmovD_regU(cop, cr, dst, src);
 7321   %}
 7322 %}
 7323 
 7324 //----------Arithmetic Instructions--------------------------------------------
 7325 //----------Addition Instructions----------------------------------------------
 7326 
 7327 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 7328 %{
 7329   match(Set dst (AddI dst src));
 7330   effect(KILL cr);
 7331 
 7332   format %{ "addl    $dst, $src\t# int" %}
 7333   ins_encode %{
 7334     __ addl($dst$$Register, $src$$Register);
 7335   %}
 7336   ins_pipe(ialu_reg_reg);
 7337 %}
 7338 
 7339 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 7340 %{
 7341   match(Set dst (AddI dst src));
 7342   effect(KILL cr);
 7343 
 7344   format %{ "addl    $dst, $src\t# int" %}
 7345   ins_encode %{
 7346     __ addl($dst$$Register, $src$$constant);
 7347   %}
 7348   ins_pipe( ialu_reg );
 7349 %}
 7350 
 7351 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 7352 %{
 7353   match(Set dst (AddI dst (LoadI src)));
 7354   effect(KILL cr);
 7355 
 7356   ins_cost(125); // XXX
 7357   format %{ "addl    $dst, $src\t# int" %}
 7358   ins_encode %{
 7359     __ addl($dst$$Register, $src$$Address);
 7360   %}
 7361   ins_pipe(ialu_reg_mem);
 7362 %}
 7363 
 7364 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 7365 %{
 7366   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7367   effect(KILL cr);
 7368 
 7369   ins_cost(150); // XXX
 7370   format %{ "addl    $dst, $src\t# int" %}
 7371   ins_encode %{
 7372     __ addl($dst$$Address, $src$$Register);
 7373   %}
 7374   ins_pipe(ialu_mem_reg);
 7375 %}
 7376 
 7377 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
 7378 %{
 7379   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7380   effect(KILL cr);
 7381 
 7382   ins_cost(125); // XXX
 7383   format %{ "addl    $dst, $src\t# int" %}
 7384   ins_encode %{
 7385     __ addl($dst$$Address, $src$$constant);
 7386   %}
 7387   ins_pipe(ialu_mem_imm);
 7388 %}
 7389 
 7390 instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
 7391 %{
 7392   predicate(UseIncDec);
 7393   match(Set dst (AddI dst src));
 7394   effect(KILL cr);
 7395 
 7396   format %{ "incl    $dst\t# int" %}
 7397   ins_encode %{
 7398     __ incrementl($dst$$Register);
 7399   %}
 7400   ins_pipe(ialu_reg);
 7401 %}
 7402 
 7403 instruct incI_mem(memory dst, immI_1 src, rFlagsReg cr)
 7404 %{
 7405   predicate(UseIncDec);
 7406   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7407   effect(KILL cr);
 7408 
 7409   ins_cost(125); // XXX
 7410   format %{ "incl    $dst\t# int" %}
 7411   ins_encode %{
 7412     __ incrementl($dst$$Address);
 7413   %}
 7414   ins_pipe(ialu_mem_imm);
 7415 %}
 7416 
 7417 // XXX why does that use AddI
 7418 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
 7419 %{
 7420   predicate(UseIncDec);
 7421   match(Set dst (AddI dst src));
 7422   effect(KILL cr);
 7423 
 7424   format %{ "decl    $dst\t# int" %}
 7425   ins_encode %{
 7426     __ decrementl($dst$$Register);
 7427   %}
 7428   ins_pipe(ialu_reg);
 7429 %}
 7430 
 7431 // XXX why does that use AddI
 7432 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
 7433 %{
 7434   predicate(UseIncDec);
 7435   match(Set dst (StoreI dst (AddI (LoadI dst) src)));
 7436   effect(KILL cr);
 7437 
 7438   ins_cost(125); // XXX
 7439   format %{ "decl    $dst\t# int" %}
 7440   ins_encode %{
 7441     __ decrementl($dst$$Address);
 7442   %}
 7443   ins_pipe(ialu_mem_imm);
 7444 %}
 7445 
 7446 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
 7447 %{
 7448   match(Set dst (AddI src0 src1));
 7449 
 7450   ins_cost(110);
 7451   format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
 7452   ins_encode %{
 7453     __ leal($dst$$Register, Address($src0$$Register, $src1$$constant));
 7454   %}
 7455   ins_pipe(ialu_reg_reg);
 7456 %}
 7457 
 7458 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 7459 %{
 7460   match(Set dst (AddL dst src));
 7461   effect(KILL cr);
 7462 
 7463   format %{ "addq    $dst, $src\t# long" %}
 7464   ins_encode %{
 7465     __ addq($dst$$Register, $src$$Register);
 7466   %}
 7467   ins_pipe(ialu_reg_reg);
 7468 %}
 7469 
 7470 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
 7471 %{
 7472   match(Set dst (AddL dst src));
 7473   effect(KILL cr);
 7474 
 7475   format %{ "addq    $dst, $src\t# long" %}
 7476   ins_encode %{
 7477     __ addq($dst$$Register, $src$$constant);
 7478   %}
 7479   ins_pipe( ialu_reg );
 7480 %}
 7481 
 7482 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 7483 %{
 7484   match(Set dst (AddL dst (LoadL src)));
 7485   effect(KILL cr);
 7486 
 7487   ins_cost(125); // XXX
 7488   format %{ "addq    $dst, $src\t# long" %}
 7489   ins_encode %{
 7490     __ addq($dst$$Register, $src$$Address);
 7491   %}
 7492   ins_pipe(ialu_reg_mem);
 7493 %}
 7494 
 7495 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 7496 %{
 7497   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7498   effect(KILL cr);
 7499 
 7500   ins_cost(150); // XXX
 7501   format %{ "addq    $dst, $src\t# long" %}
 7502   ins_encode %{
 7503     __ addq($dst$$Address, $src$$Register);
 7504   %}
 7505   ins_pipe(ialu_mem_reg);
 7506 %}
 7507 
 7508 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 7509 %{
 7510   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7511   effect(KILL cr);
 7512 
 7513   ins_cost(125); // XXX
 7514   format %{ "addq    $dst, $src\t# long" %}
 7515   ins_encode %{
 7516     __ addq($dst$$Address, $src$$constant);
 7517   %}
 7518   ins_pipe(ialu_mem_imm);
 7519 %}
 7520 
 7521 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
 7522 %{
 7523   predicate(UseIncDec);
 7524   match(Set dst (AddL dst src));
 7525   effect(KILL cr);
 7526 
 7527   format %{ "incq    $dst\t# long" %}
 7528   ins_encode %{
 7529     __ incrementq($dst$$Register);
 7530   %}
 7531   ins_pipe(ialu_reg);
 7532 %}
 7533 
 7534 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
 7535 %{
 7536   predicate(UseIncDec);
 7537   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7538   effect(KILL cr);
 7539 
 7540   ins_cost(125); // XXX
 7541   format %{ "incq    $dst\t# long" %}
 7542   ins_encode %{
 7543     __ incrementq($dst$$Address);
 7544   %}
 7545   ins_pipe(ialu_mem_imm);
 7546 %}
 7547 
 7548 // XXX why does that use AddL
 7549 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
 7550 %{
 7551   predicate(UseIncDec);
 7552   match(Set dst (AddL dst src));
 7553   effect(KILL cr);
 7554 
 7555   format %{ "decq    $dst\t# long" %}
 7556   ins_encode %{
 7557     __ decrementq($dst$$Register);
 7558   %}
 7559   ins_pipe(ialu_reg);
 7560 %}
 7561 
 7562 // XXX why does that use AddL
 7563 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
 7564 %{
 7565   predicate(UseIncDec);
 7566   match(Set dst (StoreL dst (AddL (LoadL dst) src)));
 7567   effect(KILL cr);
 7568 
 7569   ins_cost(125); // XXX
 7570   format %{ "decq    $dst\t# long" %}
 7571   ins_encode %{
 7572     __ decrementq($dst$$Address);
 7573   %}
 7574   ins_pipe(ialu_mem_imm);
 7575 %}
 7576 
 7577 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
 7578 %{
 7579   match(Set dst (AddL src0 src1));
 7580 
 7581   ins_cost(110);
 7582   format %{ "leaq    $dst, [$src0 + $src1]\t# long" %}
 7583   ins_encode %{
 7584     __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
 7585   %}
 7586   ins_pipe(ialu_reg_reg);
 7587 %}
 7588 
 7589 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
 7590 %{
 7591   match(Set dst (AddP dst src));
 7592   effect(KILL cr);
 7593 
 7594   format %{ "addq    $dst, $src\t# ptr" %}
 7595   ins_encode %{
 7596     __ addq($dst$$Register, $src$$Register);
 7597   %}
 7598   ins_pipe(ialu_reg_reg);
 7599 %}
 7600 
 7601 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
 7602 %{
 7603   match(Set dst (AddP dst src));
 7604   effect(KILL cr);
 7605 
 7606   format %{ "addq    $dst, $src\t# ptr" %}
 7607   ins_encode %{
 7608     __ addq($dst$$Register, $src$$constant);
 7609   %}
 7610   ins_pipe( ialu_reg );
 7611 %}
 7612 
 7613 // XXX addP mem ops ????
 7614 
 7615 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
 7616 %{
 7617   match(Set dst (AddP src0 src1));
 7618 
 7619   ins_cost(110);
 7620   format %{ "leaq    $dst, [$src0 + $src1]\t# ptr" %}
 7621   ins_encode %{
 7622     __ leaq($dst$$Register, Address($src0$$Register, $src1$$constant));
 7623   %}
 7624   ins_pipe(ialu_reg_reg);
 7625 %}
 7626 
 7627 instruct checkCastPP(rRegP dst)
 7628 %{
 7629   match(Set dst (CheckCastPP dst));
 7630 
 7631   size(0);
 7632   format %{ "# checkcastPP of $dst" %}
 7633   ins_encode(/* empty encoding */);
 7634   ins_pipe(empty);
 7635 %}
 7636 
 7637 instruct castPP(rRegP dst)
 7638 %{
 7639   match(Set dst (CastPP dst));
 7640 
 7641   size(0);
 7642   format %{ "# castPP of $dst" %}
 7643   ins_encode(/* empty encoding */);
 7644   ins_pipe(empty);
 7645 %}
 7646 
 7647 instruct castII(rRegI dst)
 7648 %{
 7649   match(Set dst (CastII dst));
 7650 
 7651   size(0);
 7652   format %{ "# castII of $dst" %}
 7653   ins_encode(/* empty encoding */);
 7654   ins_cost(0);
 7655   ins_pipe(empty);
 7656 %}
 7657 
 7658 instruct castLL(rRegL dst)
 7659 %{
 7660   match(Set dst (CastLL dst));
 7661 
 7662   size(0);
 7663   format %{ "# castLL of $dst" %}
 7664   ins_encode(/* empty encoding */);
 7665   ins_cost(0);
 7666   ins_pipe(empty);
 7667 %}
 7668 
 7669 instruct castFF(regF dst)
 7670 %{
 7671   match(Set dst (CastFF dst));
 7672 
 7673   size(0);
 7674   format %{ "# castFF of $dst" %}
 7675   ins_encode(/* empty encoding */);
 7676   ins_cost(0);
 7677   ins_pipe(empty);
 7678 %}
 7679 
 7680 instruct castDD(regD dst)
 7681 %{
 7682   match(Set dst (CastDD dst));
 7683 
 7684   size(0);
 7685   format %{ "# castDD of $dst" %}
 7686   ins_encode(/* empty encoding */);
 7687   ins_cost(0);
 7688   ins_pipe(empty);
 7689 %}
 7690 
 7691 // LoadP-locked same as a regular LoadP when used with compare-swap
 7692 instruct loadPLocked(rRegP dst, memory mem)
 7693 %{
 7694   match(Set dst (LoadPLocked mem));
 7695 
 7696   ins_cost(125); // XXX
 7697   format %{ "movq    $dst, $mem\t# ptr locked" %}
 7698   ins_encode %{
 7699     __ movq($dst$$Register, $mem$$Address);
 7700   %}
 7701   ins_pipe(ialu_reg_mem); // XXX
 7702 %}
 7703 
 7704 // Conditional-store of the updated heap-top.
 7705 // Used during allocation of the shared heap.
 7706 // Sets flags (EQ) on success.  Implemented with a CMPXCHG on Intel.
 7707 
 7708 instruct storePConditional(memory heap_top_ptr,
 7709                            rax_RegP oldval, rRegP newval,
 7710                            rFlagsReg cr)
 7711 %{
 7712   predicate(n->as_LoadStore()->barrier_data() == 0);
 7713   match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
 7714 
 7715   format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
 7716             "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
 7717   ins_encode %{
 7718     __ lock();
 7719     __ cmpxchgq($newval$$Register, $heap_top_ptr$$Address);
 7720   %}
 7721   ins_pipe(pipe_cmpxchg);
 7722 %}
 7723 
 7724 // Conditional-store of an int value.
 7725 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
 7726 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
 7727 %{
 7728   match(Set cr (StoreIConditional mem (Binary oldval newval)));
 7729   effect(KILL oldval);
 7730 
 7731   format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
 7732   opcode(0x0F, 0xB1);
 7733   ins_encode(lock_prefix,
 7734              REX_reg_mem(newval, mem),
 7735              OpcP, OpcS,
 7736              reg_mem(newval, mem));
 7737   ins_pipe(pipe_cmpxchg);
 7738 %}
 7739 
 7740 // Conditional-store of a long value.
 7741 // ZF flag is set on success, reset otherwise.  Implemented with a CMPXCHG.
 7742 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
 7743 %{
 7744   match(Set cr (StoreLConditional mem (Binary oldval newval)));
 7745   effect(KILL oldval);
 7746 
 7747   format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
 7748   ins_encode %{
 7749     __ lock();
 7750     __ cmpxchgq($newval$$Register, $mem$$Address);
 7751   %}
 7752   ins_pipe(pipe_cmpxchg);
 7753 %}
 7754 
 7755 
 7756 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
 7757 instruct compareAndSwapP(rRegI res,
 7758                          memory mem_ptr,
 7759                          rax_RegP oldval, rRegP newval,
 7760                          rFlagsReg cr)
 7761 %{
 7762   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
 7763   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
 7764   match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
 7765   effect(KILL cr, KILL oldval);
 7766 
 7767   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7768             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7769             "sete    $res\n\t"
 7770             "movzbl  $res, $res" %}
 7771   ins_encode %{
 7772     __ lock();
 7773     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7774     __ sete($res$$Register);
 7775     __ movzbl($res$$Register, $res$$Register);
 7776   %}
 7777   ins_pipe( pipe_cmpxchg );
 7778 %}
 7779 
 7780 instruct compareAndSwapL(rRegI res,
 7781                          memory mem_ptr,
 7782                          rax_RegL oldval, rRegL newval,
 7783                          rFlagsReg cr)
 7784 %{
 7785   predicate(VM_Version::supports_cx8());
 7786   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
 7787   match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
 7788   effect(KILL cr, KILL oldval);
 7789 
 7790   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7791             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7792             "sete    $res\n\t"
 7793             "movzbl  $res, $res" %}
 7794   ins_encode %{
 7795     __ lock();
 7796     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7797     __ sete($res$$Register);
 7798     __ movzbl($res$$Register, $res$$Register);
 7799   %}
 7800   ins_pipe( pipe_cmpxchg );
 7801 %}
 7802 
 7803 instruct compareAndSwapI(rRegI res,
 7804                          memory mem_ptr,
 7805                          rax_RegI oldval, rRegI newval,
 7806                          rFlagsReg cr)
 7807 %{
 7808   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
 7809   match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
 7810   effect(KILL cr, KILL oldval);
 7811 
 7812   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7813             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7814             "sete    $res\n\t"
 7815             "movzbl  $res, $res" %}
 7816   ins_encode %{
 7817     __ lock();
 7818     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7819     __ sete($res$$Register);
 7820     __ movzbl($res$$Register, $res$$Register);
 7821   %}
 7822   ins_pipe( pipe_cmpxchg );
 7823 %}
 7824 
 7825 instruct compareAndSwapB(rRegI res,
 7826                          memory mem_ptr,
 7827                          rax_RegI oldval, rRegI newval,
 7828                          rFlagsReg cr)
 7829 %{
 7830   match(Set res (CompareAndSwapB mem_ptr (Binary oldval newval)));
 7831   match(Set res (WeakCompareAndSwapB mem_ptr (Binary oldval newval)));
 7832   effect(KILL cr, KILL oldval);
 7833 
 7834   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7835             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7836             "sete    $res\n\t"
 7837             "movzbl  $res, $res" %}
 7838   ins_encode %{
 7839     __ lock();
 7840     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7841     __ sete($res$$Register);
 7842     __ movzbl($res$$Register, $res$$Register);
 7843   %}
 7844   ins_pipe( pipe_cmpxchg );
 7845 %}
 7846 
 7847 instruct compareAndSwapS(rRegI res,
 7848                          memory mem_ptr,
 7849                          rax_RegI oldval, rRegI newval,
 7850                          rFlagsReg cr)
 7851 %{
 7852   match(Set res (CompareAndSwapS mem_ptr (Binary oldval newval)));
 7853   match(Set res (WeakCompareAndSwapS mem_ptr (Binary oldval newval)));
 7854   effect(KILL cr, KILL oldval);
 7855 
 7856   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7857             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7858             "sete    $res\n\t"
 7859             "movzbl  $res, $res" %}
 7860   ins_encode %{
 7861     __ lock();
 7862     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7863     __ sete($res$$Register);
 7864     __ movzbl($res$$Register, $res$$Register);
 7865   %}
 7866   ins_pipe( pipe_cmpxchg );
 7867 %}
 7868 
 7869 instruct compareAndSwapN(rRegI res,
 7870                           memory mem_ptr,
 7871                           rax_RegN oldval, rRegN newval,
 7872                           rFlagsReg cr) %{
 7873   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
 7874   match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
 7875   effect(KILL cr, KILL oldval);
 7876 
 7877   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7878             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
 7879             "sete    $res\n\t"
 7880             "movzbl  $res, $res" %}
 7881   ins_encode %{
 7882     __ lock();
 7883     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7884     __ sete($res$$Register);
 7885     __ movzbl($res$$Register, $res$$Register);
 7886   %}
 7887   ins_pipe( pipe_cmpxchg );
 7888 %}
 7889 
 7890 instruct compareAndExchangeB(
 7891                          memory mem_ptr,
 7892                          rax_RegI oldval, rRegI newval,
 7893                          rFlagsReg cr)
 7894 %{
 7895   match(Set oldval (CompareAndExchangeB mem_ptr (Binary oldval newval)));
 7896   effect(KILL cr);
 7897 
 7898   format %{ "cmpxchgb $mem_ptr,$newval\t# "
 7899             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7900   ins_encode %{
 7901     __ lock();
 7902     __ cmpxchgb($newval$$Register, $mem_ptr$$Address);
 7903   %}
 7904   ins_pipe( pipe_cmpxchg );
 7905 %}
 7906 
 7907 instruct compareAndExchangeS(
 7908                          memory mem_ptr,
 7909                          rax_RegI oldval, rRegI newval,
 7910                          rFlagsReg cr)
 7911 %{
 7912   match(Set oldval (CompareAndExchangeS mem_ptr (Binary oldval newval)));
 7913   effect(KILL cr);
 7914 
 7915   format %{ "cmpxchgw $mem_ptr,$newval\t# "
 7916             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7917   ins_encode %{
 7918     __ lock();
 7919     __ cmpxchgw($newval$$Register, $mem_ptr$$Address);
 7920   %}
 7921   ins_pipe( pipe_cmpxchg );
 7922 %}
 7923 
 7924 instruct compareAndExchangeI(
 7925                          memory mem_ptr,
 7926                          rax_RegI oldval, rRegI newval,
 7927                          rFlagsReg cr)
 7928 %{
 7929   match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
 7930   effect(KILL cr);
 7931 
 7932   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7933             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7934   ins_encode %{
 7935     __ lock();
 7936     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7937   %}
 7938   ins_pipe( pipe_cmpxchg );
 7939 %}
 7940 
 7941 instruct compareAndExchangeL(
 7942                          memory mem_ptr,
 7943                          rax_RegL oldval, rRegL newval,
 7944                          rFlagsReg cr)
 7945 %{
 7946   predicate(VM_Version::supports_cx8());
 7947   match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
 7948   effect(KILL cr);
 7949 
 7950   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7951             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"  %}
 7952   ins_encode %{
 7953     __ lock();
 7954     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7955   %}
 7956   ins_pipe( pipe_cmpxchg );
 7957 %}
 7958 
 7959 instruct compareAndExchangeN(
 7960                           memory mem_ptr,
 7961                           rax_RegN oldval, rRegN newval,
 7962                           rFlagsReg cr) %{
 7963   match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
 7964   effect(KILL cr);
 7965 
 7966   format %{ "cmpxchgl $mem_ptr,$newval\t# "
 7967             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7968   ins_encode %{
 7969     __ lock();
 7970     __ cmpxchgl($newval$$Register, $mem_ptr$$Address);
 7971   %}
 7972   ins_pipe( pipe_cmpxchg );
 7973 %}
 7974 
 7975 instruct compareAndExchangeP(
 7976                          memory mem_ptr,
 7977                          rax_RegP oldval, rRegP newval,
 7978                          rFlagsReg cr)
 7979 %{
 7980   predicate(VM_Version::supports_cx8() && n->as_LoadStore()->barrier_data() == 0);
 7981   match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
 7982   effect(KILL cr);
 7983 
 7984   format %{ "cmpxchgq $mem_ptr,$newval\t# "
 7985             "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
 7986   ins_encode %{
 7987     __ lock();
 7988     __ cmpxchgq($newval$$Register, $mem_ptr$$Address);
 7989   %}
 7990   ins_pipe( pipe_cmpxchg );
 7991 %}
 7992 
 7993 instruct xaddB_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 7994   predicate(n->as_LoadStore()->result_not_used());
 7995   match(Set dummy (GetAndAddB mem add));
 7996   effect(KILL cr);
 7997   format %{ "ADDB  [$mem],$add" %}
 7998   ins_encode %{
 7999     __ lock();
 8000     __ addb($mem$$Address, $add$$constant);
 8001   %}
 8002   ins_pipe( pipe_cmpxchg );
 8003 %}
 8004 
 8005 instruct xaddB( memory mem, rRegI newval, rFlagsReg cr) %{
 8006   match(Set newval (GetAndAddB mem newval));
 8007   effect(KILL cr);
 8008   format %{ "XADDB  [$mem],$newval" %}
 8009   ins_encode %{
 8010     __ lock();
 8011     __ xaddb($mem$$Address, $newval$$Register);
 8012   %}
 8013   ins_pipe( pipe_cmpxchg );
 8014 %}
 8015 
 8016 instruct xaddS_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 8017   predicate(n->as_LoadStore()->result_not_used());
 8018   match(Set dummy (GetAndAddS mem add));
 8019   effect(KILL cr);
 8020   format %{ "ADDW  [$mem],$add" %}
 8021   ins_encode %{
 8022     __ lock();
 8023     __ addw($mem$$Address, $add$$constant);
 8024   %}
 8025   ins_pipe( pipe_cmpxchg );
 8026 %}
 8027 
 8028 instruct xaddS( memory mem, rRegI newval, rFlagsReg cr) %{
 8029   match(Set newval (GetAndAddS mem newval));
 8030   effect(KILL cr);
 8031   format %{ "XADDW  [$mem],$newval" %}
 8032   ins_encode %{
 8033     __ lock();
 8034     __ xaddw($mem$$Address, $newval$$Register);
 8035   %}
 8036   ins_pipe( pipe_cmpxchg );
 8037 %}
 8038 
 8039 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
 8040   predicate(n->as_LoadStore()->result_not_used());
 8041   match(Set dummy (GetAndAddI mem add));
 8042   effect(KILL cr);
 8043   format %{ "ADDL  [$mem],$add" %}
 8044   ins_encode %{
 8045     __ lock();
 8046     __ addl($mem$$Address, $add$$constant);
 8047   %}
 8048   ins_pipe( pipe_cmpxchg );
 8049 %}
 8050 
 8051 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
 8052   match(Set newval (GetAndAddI mem newval));
 8053   effect(KILL cr);
 8054   format %{ "XADDL  [$mem],$newval" %}
 8055   ins_encode %{
 8056     __ lock();
 8057     __ xaddl($mem$$Address, $newval$$Register);
 8058   %}
 8059   ins_pipe( pipe_cmpxchg );
 8060 %}
 8061 
 8062 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
 8063   predicate(n->as_LoadStore()->result_not_used());
 8064   match(Set dummy (GetAndAddL mem add));
 8065   effect(KILL cr);
 8066   format %{ "ADDQ  [$mem],$add" %}
 8067   ins_encode %{
 8068     __ lock();
 8069     __ addq($mem$$Address, $add$$constant);
 8070   %}
 8071   ins_pipe( pipe_cmpxchg );
 8072 %}
 8073 
 8074 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
 8075   match(Set newval (GetAndAddL mem newval));
 8076   effect(KILL cr);
 8077   format %{ "XADDQ  [$mem],$newval" %}
 8078   ins_encode %{
 8079     __ lock();
 8080     __ xaddq($mem$$Address, $newval$$Register);
 8081   %}
 8082   ins_pipe( pipe_cmpxchg );
 8083 %}
 8084 
 8085 instruct xchgB( memory mem, rRegI newval) %{
 8086   match(Set newval (GetAndSetB mem newval));
 8087   format %{ "XCHGB  $newval,[$mem]" %}
 8088   ins_encode %{
 8089     __ xchgb($newval$$Register, $mem$$Address);
 8090   %}
 8091   ins_pipe( pipe_cmpxchg );
 8092 %}
 8093 
 8094 instruct xchgS( memory mem, rRegI newval) %{
 8095   match(Set newval (GetAndSetS mem newval));
 8096   format %{ "XCHGW  $newval,[$mem]" %}
 8097   ins_encode %{
 8098     __ xchgw($newval$$Register, $mem$$Address);
 8099   %}
 8100   ins_pipe( pipe_cmpxchg );
 8101 %}
 8102 
 8103 instruct xchgI( memory mem, rRegI newval) %{
 8104   match(Set newval (GetAndSetI mem newval));
 8105   format %{ "XCHGL  $newval,[$mem]" %}
 8106   ins_encode %{
 8107     __ xchgl($newval$$Register, $mem$$Address);
 8108   %}
 8109   ins_pipe( pipe_cmpxchg );
 8110 %}
 8111 
 8112 instruct xchgL( memory mem, rRegL newval) %{
 8113   match(Set newval (GetAndSetL mem newval));
 8114   format %{ "XCHGL  $newval,[$mem]" %}
 8115   ins_encode %{
 8116     __ xchgq($newval$$Register, $mem$$Address);
 8117   %}
 8118   ins_pipe( pipe_cmpxchg );
 8119 %}
 8120 
 8121 instruct xchgP( memory mem, rRegP newval) %{
 8122   match(Set newval (GetAndSetP mem newval));
 8123   predicate(n->as_LoadStore()->barrier_data() == 0);
 8124   format %{ "XCHGQ  $newval,[$mem]" %}
 8125   ins_encode %{
 8126     __ xchgq($newval$$Register, $mem$$Address);
 8127   %}
 8128   ins_pipe( pipe_cmpxchg );
 8129 %}
 8130 
 8131 instruct xchgN( memory mem, rRegN newval) %{
 8132   match(Set newval (GetAndSetN mem newval));
 8133   format %{ "XCHGL  $newval,$mem]" %}
 8134   ins_encode %{
 8135     __ xchgl($newval$$Register, $mem$$Address);
 8136   %}
 8137   ins_pipe( pipe_cmpxchg );
 8138 %}
 8139 
 8140 //----------Abs Instructions-------------------------------------------
 8141 
 8142 // Integer Absolute Instructions
 8143 instruct absI_rReg(rRegI dst, rRegI src, rRegI tmp, rFlagsReg cr)
 8144 %{
 8145   match(Set dst (AbsI src));
 8146   effect(TEMP dst, TEMP tmp, KILL cr);
 8147   format %{ "movl $tmp, $src\n\t"
 8148             "sarl $tmp, 31\n\t"
 8149             "movl $dst, $src\n\t"
 8150             "xorl $dst, $tmp\n\t"
 8151             "subl $dst, $tmp\n"
 8152           %}
 8153   ins_encode %{
 8154     __ movl($tmp$$Register, $src$$Register);
 8155     __ sarl($tmp$$Register, 31);
 8156     __ movl($dst$$Register, $src$$Register);
 8157     __ xorl($dst$$Register, $tmp$$Register);
 8158     __ subl($dst$$Register, $tmp$$Register);
 8159   %}
 8160 
 8161   ins_pipe(ialu_reg_reg);
 8162 %}
 8163 
 8164 // Long Absolute Instructions
 8165 instruct absL_rReg(rRegL dst, rRegL src, rRegL tmp, rFlagsReg cr)
 8166 %{
 8167   match(Set dst (AbsL src));
 8168   effect(TEMP dst, TEMP tmp, KILL cr);
 8169   format %{ "movq $tmp, $src\n\t"
 8170             "sarq $tmp, 63\n\t"
 8171             "movq $dst, $src\n\t"
 8172             "xorq $dst, $tmp\n\t"
 8173             "subq $dst, $tmp\n"
 8174           %}
 8175   ins_encode %{
 8176     __ movq($tmp$$Register, $src$$Register);
 8177     __ sarq($tmp$$Register, 63);
 8178     __ movq($dst$$Register, $src$$Register);
 8179     __ xorq($dst$$Register, $tmp$$Register);
 8180     __ subq($dst$$Register, $tmp$$Register);
 8181   %}
 8182 
 8183   ins_pipe(ialu_reg_reg);
 8184 %}
 8185 
 8186 //----------Subtraction Instructions-------------------------------------------
 8187 
 8188 // Integer Subtraction Instructions
 8189 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8190 %{
 8191   match(Set dst (SubI dst src));
 8192   effect(KILL cr);
 8193 
 8194   format %{ "subl    $dst, $src\t# int" %}
 8195   ins_encode %{
 8196     __ subl($dst$$Register, $src$$Register);
 8197   %}
 8198   ins_pipe(ialu_reg_reg);
 8199 %}
 8200 
 8201 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 8202 %{
 8203   match(Set dst (SubI dst src));
 8204   effect(KILL cr);
 8205 
 8206   format %{ "subl    $dst, $src\t# int" %}
 8207   ins_encode %{
 8208     __ subl($dst$$Register, $src$$constant);
 8209   %}
 8210   ins_pipe(ialu_reg);
 8211 %}
 8212 
 8213 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 8214 %{
 8215   match(Set dst (SubI dst (LoadI src)));
 8216   effect(KILL cr);
 8217 
 8218   ins_cost(125);
 8219   format %{ "subl    $dst, $src\t# int" %}
 8220   ins_encode %{
 8221     __ subl($dst$$Register, $src$$Address);
 8222   %}
 8223   ins_pipe(ialu_reg_mem);
 8224 %}
 8225 
 8226 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 8227 %{
 8228   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
 8229   effect(KILL cr);
 8230 
 8231   ins_cost(150);
 8232   format %{ "subl    $dst, $src\t# int" %}
 8233   ins_encode %{
 8234     __ subl($dst$$Address, $src$$Register);
 8235   %}
 8236   ins_pipe(ialu_mem_reg);
 8237 %}
 8238 
 8239 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
 8240 %{
 8241   match(Set dst (StoreI dst (SubI (LoadI dst) src)));
 8242   effect(KILL cr);
 8243 
 8244   ins_cost(125); // XXX
 8245   format %{ "subl    $dst, $src\t# int" %}
 8246   ins_encode %{
 8247     __ subl($dst$$Address, $src$$constant);
 8248   %}
 8249   ins_pipe(ialu_mem_imm);
 8250 %}
 8251 
 8252 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8253 %{
 8254   match(Set dst (SubL dst src));
 8255   effect(KILL cr);
 8256 
 8257   format %{ "subq    $dst, $src\t# long" %}
 8258   ins_encode %{
 8259     __ subq($dst$$Register, $src$$Register);
 8260   %}
 8261   ins_pipe(ialu_reg_reg);
 8262 %}
 8263 
 8264 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
 8265 %{
 8266   match(Set dst (SubL dst src));
 8267   effect(KILL cr);
 8268 
 8269   format %{ "subq    $dst, $src\t# long" %}
 8270   ins_encode %{
 8271     __ subq($dst$$Register, $src$$constant);
 8272   %}
 8273   ins_pipe(ialu_reg);
 8274 %}
 8275 
 8276 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 8277 %{
 8278   match(Set dst (SubL dst (LoadL src)));
 8279   effect(KILL cr);
 8280 
 8281   ins_cost(125);
 8282   format %{ "subq    $dst, $src\t# long" %}
 8283   ins_encode %{
 8284     __ subq($dst$$Register, $src$$Address);
 8285   %}
 8286   ins_pipe(ialu_reg_mem);
 8287 %}
 8288 
 8289 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 8290 %{
 8291   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
 8292   effect(KILL cr);
 8293 
 8294   ins_cost(150);
 8295   format %{ "subq    $dst, $src\t# long" %}
 8296   ins_encode %{
 8297     __ subq($dst$$Address, $src$$Register);
 8298   %}
 8299   ins_pipe(ialu_mem_reg);
 8300 %}
 8301 
 8302 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 8303 %{
 8304   match(Set dst (StoreL dst (SubL (LoadL dst) src)));
 8305   effect(KILL cr);
 8306 
 8307   ins_cost(125); // XXX
 8308   format %{ "subq    $dst, $src\t# long" %}
 8309   ins_encode %{
 8310     __ subq($dst$$Address, $src$$constant);
 8311   %}
 8312   ins_pipe(ialu_mem_imm);
 8313 %}
 8314 
 8315 // Subtract from a pointer
 8316 // XXX hmpf???
 8317 instruct subP_rReg(rRegP dst, rRegI src, immI_0 zero, rFlagsReg cr)
 8318 %{
 8319   match(Set dst (AddP dst (SubI zero src)));
 8320   effect(KILL cr);
 8321 
 8322   format %{ "subq    $dst, $src\t# ptr - int" %}
 8323   opcode(0x2B);
 8324   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
 8325   ins_pipe(ialu_reg_reg);
 8326 %}
 8327 
 8328 instruct negI_rReg(rRegI dst, immI_0 zero, rFlagsReg cr)
 8329 %{
 8330   match(Set dst (SubI zero dst));
 8331   effect(KILL cr);
 8332 
 8333   format %{ "negl    $dst\t# int" %}
 8334   ins_encode %{
 8335     __ negl($dst$$Register);
 8336   %}
 8337   ins_pipe(ialu_reg);
 8338 %}
 8339 
 8340 instruct negI_rReg_2(rRegI dst, rFlagsReg cr)
 8341 %{
 8342   match(Set dst (NegI dst));
 8343   effect(KILL cr);
 8344 
 8345   format %{ "negl    $dst\t# int" %}
 8346   ins_encode %{
 8347     __ negl($dst$$Register);
 8348   %}
 8349   ins_pipe(ialu_reg);
 8350 %}
 8351 
 8352 instruct negI_mem(memory dst, immI_0 zero, rFlagsReg cr)
 8353 %{
 8354   match(Set dst (StoreI dst (SubI zero (LoadI dst))));
 8355   effect(KILL cr);
 8356 
 8357   format %{ "negl    $dst\t# int" %}
 8358   ins_encode %{
 8359     __ negl($dst$$Address);
 8360   %}
 8361   ins_pipe(ialu_reg);
 8362 %}
 8363 
 8364 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
 8365 %{
 8366   match(Set dst (SubL zero dst));
 8367   effect(KILL cr);
 8368 
 8369   format %{ "negq    $dst\t# long" %}
 8370   ins_encode %{
 8371     __ negq($dst$$Register);
 8372   %}
 8373   ins_pipe(ialu_reg);
 8374 %}
 8375 
 8376 instruct negL_rReg_2(rRegL dst, rFlagsReg cr)
 8377 %{
 8378   match(Set dst (NegL dst));
 8379   effect(KILL cr);
 8380 
 8381   format %{ "negq    $dst\t# int" %}
 8382   ins_encode %{
 8383     __ negq($dst$$Register);
 8384   %}
 8385   ins_pipe(ialu_reg);
 8386 %}
 8387 
 8388 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
 8389 %{
 8390   match(Set dst (StoreL dst (SubL zero (LoadL dst))));
 8391   effect(KILL cr);
 8392 
 8393   format %{ "negq    $dst\t# long" %}
 8394   ins_encode %{
 8395     __ negq($dst$$Address);
 8396   %}
 8397   ins_pipe(ialu_reg);
 8398 %}
 8399 
 8400 //----------Multiplication/Division Instructions-------------------------------
 8401 // Integer Multiplication Instructions
 8402 // Multiply Register
 8403 
 8404 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 8405 %{
 8406   match(Set dst (MulI dst src));
 8407   effect(KILL cr);
 8408 
 8409   ins_cost(300);
 8410   format %{ "imull   $dst, $src\t# int" %}
 8411   ins_encode %{
 8412     __ imull($dst$$Register, $src$$Register);
 8413   %}
 8414   ins_pipe(ialu_reg_reg_alu0);
 8415 %}
 8416 
 8417 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
 8418 %{
 8419   match(Set dst (MulI src imm));
 8420   effect(KILL cr);
 8421 
 8422   ins_cost(300);
 8423   format %{ "imull   $dst, $src, $imm\t# int" %}
 8424   ins_encode %{
 8425     __ imull($dst$$Register, $src$$Register, $imm$$constant);
 8426   %}
 8427   ins_pipe(ialu_reg_reg_alu0);
 8428 %}
 8429 
 8430 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
 8431 %{
 8432   match(Set dst (MulI dst (LoadI src)));
 8433   effect(KILL cr);
 8434 
 8435   ins_cost(350);
 8436   format %{ "imull   $dst, $src\t# int" %}
 8437   ins_encode %{
 8438     __ imull($dst$$Register, $src$$Address);
 8439   %}
 8440   ins_pipe(ialu_reg_mem_alu0);
 8441 %}
 8442 
 8443 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
 8444 %{
 8445   match(Set dst (MulI (LoadI src) imm));
 8446   effect(KILL cr);
 8447 
 8448   ins_cost(300);
 8449   format %{ "imull   $dst, $src, $imm\t# int" %}
 8450   ins_encode %{
 8451     __ imull($dst$$Register, $src$$Address, $imm$$constant);
 8452   %}
 8453   ins_pipe(ialu_reg_mem_alu0);
 8454 %}
 8455 
 8456 instruct mulAddS2I_rReg(rRegI dst, rRegI src1, rRegI src2, rRegI src3, rFlagsReg cr)
 8457 %{
 8458   match(Set dst (MulAddS2I (Binary dst src1) (Binary src2 src3)));
 8459   effect(KILL cr, KILL src2);
 8460 
 8461   expand %{ mulI_rReg(dst, src1, cr);
 8462            mulI_rReg(src2, src3, cr);
 8463            addI_rReg(dst, src2, cr); %}
 8464 %}
 8465 
 8466 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 8467 %{
 8468   match(Set dst (MulL dst src));
 8469   effect(KILL cr);
 8470 
 8471   ins_cost(300);
 8472   format %{ "imulq   $dst, $src\t# long" %}
 8473   ins_encode %{
 8474     __ imulq($dst$$Register, $src$$Register);
 8475   %}
 8476   ins_pipe(ialu_reg_reg_alu0);
 8477 %}
 8478 
 8479 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
 8480 %{
 8481   match(Set dst (MulL src imm));
 8482   effect(KILL cr);
 8483 
 8484   ins_cost(300);
 8485   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8486   ins_encode %{
 8487     __ imulq($dst$$Register, $src$$Register, $imm$$constant);
 8488   %}
 8489   ins_pipe(ialu_reg_reg_alu0);
 8490 %}
 8491 
 8492 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
 8493 %{
 8494   match(Set dst (MulL dst (LoadL src)));
 8495   effect(KILL cr);
 8496 
 8497   ins_cost(350);
 8498   format %{ "imulq   $dst, $src\t# long" %}
 8499   ins_encode %{
 8500     __ imulq($dst$$Register, $src$$Address);
 8501   %}
 8502   ins_pipe(ialu_reg_mem_alu0);
 8503 %}
 8504 
 8505 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
 8506 %{
 8507   match(Set dst (MulL (LoadL src) imm));
 8508   effect(KILL cr);
 8509 
 8510   ins_cost(300);
 8511   format %{ "imulq   $dst, $src, $imm\t# long" %}
 8512   ins_encode %{
 8513     __ imulq($dst$$Register, $src$$Address, $imm$$constant);
 8514   %}
 8515   ins_pipe(ialu_reg_mem_alu0);
 8516 %}
 8517 
 8518 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
 8519 %{
 8520   match(Set dst (MulHiL src rax));
 8521   effect(USE_KILL rax, KILL cr);
 8522 
 8523   ins_cost(300);
 8524   format %{ "imulq   RDX:RAX, RAX, $src\t# mulhi" %}
 8525   ins_encode %{
 8526     __ imulq($src$$Register);
 8527   %}
 8528   ins_pipe(ialu_reg_reg_alu0);
 8529 %}
 8530 
 8531 instruct umulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
 8532 %{
 8533   match(Set dst (UMulHiL src rax));
 8534   effect(USE_KILL rax, KILL cr);
 8535 
 8536   ins_cost(300);
 8537   format %{ "mulq   RDX:RAX, RAX, $src\t# umulhi" %}
 8538   ins_encode %{
 8539     __ mulq($src$$Register);
 8540   %}
 8541   ins_pipe(ialu_reg_reg_alu0);
 8542 %}
 8543 
 8544 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8545                    rFlagsReg cr)
 8546 %{
 8547   match(Set rax (DivI rax div));
 8548   effect(KILL rdx, KILL cr);
 8549 
 8550   ins_cost(30*100+10*100); // XXX
 8551   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8552             "jne,s   normal\n\t"
 8553             "xorl    rdx, rdx\n\t"
 8554             "cmpl    $div, -1\n\t"
 8555             "je,s    done\n"
 8556     "normal: cdql\n\t"
 8557             "idivl   $div\n"
 8558     "done:"        %}
 8559   ins_encode(cdql_enc(div));
 8560   ins_pipe(ialu_reg_reg_alu0);
 8561 %}
 8562 
 8563 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8564                    rFlagsReg cr)
 8565 %{
 8566   match(Set rax (DivL rax div));
 8567   effect(KILL rdx, KILL cr);
 8568 
 8569   ins_cost(30*100+10*100); // XXX
 8570   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8571             "cmpq    rax, rdx\n\t"
 8572             "jne,s   normal\n\t"
 8573             "xorl    rdx, rdx\n\t"
 8574             "cmpq    $div, -1\n\t"
 8575             "je,s    done\n"
 8576     "normal: cdqq\n\t"
 8577             "idivq   $div\n"
 8578     "done:"        %}
 8579   ins_encode(cdqq_enc(div));
 8580   ins_pipe(ialu_reg_reg_alu0);
 8581 %}
 8582 
 8583 // Integer DIVMOD with Register, both quotient and mod results
 8584 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
 8585                              rFlagsReg cr)
 8586 %{
 8587   match(DivModI rax div);
 8588   effect(KILL cr);
 8589 
 8590   ins_cost(30*100+10*100); // XXX
 8591   format %{ "cmpl    rax, 0x80000000\t# idiv\n\t"
 8592             "jne,s   normal\n\t"
 8593             "xorl    rdx, rdx\n\t"
 8594             "cmpl    $div, -1\n\t"
 8595             "je,s    done\n"
 8596     "normal: cdql\n\t"
 8597             "idivl   $div\n"
 8598     "done:"        %}
 8599   ins_encode(cdql_enc(div));
 8600   ins_pipe(pipe_slow);
 8601 %}
 8602 
 8603 // Long DIVMOD with Register, both quotient and mod results
 8604 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
 8605                              rFlagsReg cr)
 8606 %{
 8607   match(DivModL rax div);
 8608   effect(KILL cr);
 8609 
 8610   ins_cost(30*100+10*100); // XXX
 8611   format %{ "movq    rdx, 0x8000000000000000\t# ldiv\n\t"
 8612             "cmpq    rax, rdx\n\t"
 8613             "jne,s   normal\n\t"
 8614             "xorl    rdx, rdx\n\t"
 8615             "cmpq    $div, -1\n\t"
 8616             "je,s    done\n"
 8617     "normal: cdqq\n\t"
 8618             "idivq   $div\n"
 8619     "done:"        %}
 8620   ins_encode(cdqq_enc(div));
 8621   ins_pipe(pipe_slow);
 8622 %}
 8623 
 8624 //----------- DivL-By-Constant-Expansions--------------------------------------
 8625 // DivI cases are handled by the compiler
 8626 
 8627 // Magic constant, reciprocal of 10
 8628 instruct loadConL_0x6666666666666667(rRegL dst)
 8629 %{
 8630   effect(DEF dst);
 8631 
 8632   format %{ "movq    $dst, #0x666666666666667\t# Used in div-by-10" %}
 8633   ins_encode(load_immL(dst, 0x6666666666666667));
 8634   ins_pipe(ialu_reg);
 8635 %}
 8636 
 8637 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
 8638 %{
 8639   effect(DEF dst, USE src, USE_KILL rax, KILL cr);
 8640 
 8641   format %{ "imulq   rdx:rax, rax, $src\t# Used in div-by-10" %}
 8642   ins_encode %{
 8643     __ imulq($src$$Register);
 8644   %}
 8645   ins_pipe(ialu_reg_reg_alu0);
 8646 %}
 8647 
 8648 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
 8649 %{
 8650   effect(USE_DEF dst, KILL cr);
 8651 
 8652   format %{ "sarq    $dst, #63\t# Used in div-by-10" %}
 8653   ins_encode %{
 8654     __ sarq($dst$$Register, 63);
 8655   %}
 8656   ins_pipe(ialu_reg);
 8657 %}
 8658 
 8659 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
 8660 %{
 8661   effect(USE_DEF dst, KILL cr);
 8662 
 8663   format %{ "sarq    $dst, #2\t# Used in div-by-10" %}
 8664   ins_encode %{
 8665     __ sarq($dst$$Register, 2);
 8666   %}
 8667   ins_pipe(ialu_reg);
 8668 %}
 8669 
 8670 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
 8671 %{
 8672   match(Set dst (DivL src div));
 8673 
 8674   ins_cost((5+8)*100);
 8675   expand %{
 8676     rax_RegL rax;                     // Killed temp
 8677     rFlagsReg cr;                     // Killed
 8678     loadConL_0x6666666666666667(rax); // movq  rax, 0x6666666666666667
 8679     mul_hi(dst, src, rax, cr);        // mulq  rdx:rax <= rax * $src
 8680     sarL_rReg_63(src, cr);            // sarq  src, 63
 8681     sarL_rReg_2(dst, cr);             // sarq  rdx, 2
 8682     subL_rReg(dst, src, cr);          // subl  rdx, src
 8683   %}
 8684 %}
 8685 
 8686 //-----------------------------------------------------------------------------
 8687 
 8688 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
 8689                    rFlagsReg cr)
 8690 %{
 8691   match(Set rdx (ModI rax div));
 8692   effect(KILL rax, KILL cr);
 8693 
 8694   ins_cost(300); // XXX
 8695   format %{ "cmpl    rax, 0x80000000\t# irem\n\t"
 8696             "jne,s   normal\n\t"
 8697             "xorl    rdx, rdx\n\t"
 8698             "cmpl    $div, -1\n\t"
 8699             "je,s    done\n"
 8700     "normal: cdql\n\t"
 8701             "idivl   $div\n"
 8702     "done:"        %}
 8703   ins_encode(cdql_enc(div));
 8704   ins_pipe(ialu_reg_reg_alu0);
 8705 %}
 8706 
 8707 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
 8708                    rFlagsReg cr)
 8709 %{
 8710   match(Set rdx (ModL rax div));
 8711   effect(KILL rax, KILL cr);
 8712 
 8713   ins_cost(300); // XXX
 8714   format %{ "movq    rdx, 0x8000000000000000\t# lrem\n\t"
 8715             "cmpq    rax, rdx\n\t"
 8716             "jne,s   normal\n\t"
 8717             "xorl    rdx, rdx\n\t"
 8718             "cmpq    $div, -1\n\t"
 8719             "je,s    done\n"
 8720     "normal: cdqq\n\t"
 8721             "idivq   $div\n"
 8722     "done:"        %}
 8723   ins_encode(cdqq_enc(div));
 8724   ins_pipe(ialu_reg_reg_alu0);
 8725 %}
 8726 
 8727 // Integer Shift Instructions
 8728 // Shift Left by one
 8729 instruct salI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8730 %{
 8731   match(Set dst (LShiftI dst shift));
 8732   effect(KILL cr);
 8733 
 8734   format %{ "sall    $dst, $shift" %}
 8735   ins_encode %{
 8736     __ sall($dst$$Register, $shift$$constant);
 8737   %}
 8738   ins_pipe(ialu_reg);
 8739 %}
 8740 
 8741 // Shift Left by one
 8742 instruct salI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8743 %{
 8744   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8745   effect(KILL cr);
 8746 
 8747   format %{ "sall    $dst, $shift\t" %}
 8748   ins_encode %{
 8749     __ sall($dst$$Address, $shift$$constant);
 8750   %}
 8751   ins_pipe(ialu_mem_imm);
 8752 %}
 8753 
 8754 // Shift Left by 8-bit immediate
 8755 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8756 %{
 8757   match(Set dst (LShiftI dst shift));
 8758   effect(KILL cr);
 8759 
 8760   format %{ "sall    $dst, $shift" %}
 8761   ins_encode %{
 8762     __ sall($dst$$Register, $shift$$constant);
 8763   %}
 8764   ins_pipe(ialu_reg);
 8765 %}
 8766 
 8767 // Shift Left by 8-bit immediate
 8768 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8769 %{
 8770   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8771   effect(KILL cr);
 8772 
 8773   format %{ "sall    $dst, $shift" %}
 8774   ins_encode %{
 8775     __ sall($dst$$Address, $shift$$constant);
 8776   %}
 8777   ins_pipe(ialu_mem_imm);
 8778 %}
 8779 
 8780 // Shift Left by variable
 8781 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8782 %{
 8783   match(Set dst (LShiftI dst shift));
 8784   effect(KILL cr);
 8785 
 8786   format %{ "sall    $dst, $shift" %}
 8787   ins_encode %{
 8788     __ sall($dst$$Register);
 8789   %}
 8790   ins_pipe(ialu_reg_reg);
 8791 %}
 8792 
 8793 // Shift Left by variable
 8794 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8795 %{
 8796   match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
 8797   effect(KILL cr);
 8798 
 8799   format %{ "sall    $dst, $shift" %}
 8800   ins_encode %{
 8801     __ sall($dst$$Address);
 8802   %}
 8803   ins_pipe(ialu_mem_reg);
 8804 %}
 8805 
 8806 // Arithmetic shift right by one
 8807 instruct sarI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8808 %{
 8809   match(Set dst (RShiftI dst shift));
 8810   effect(KILL cr);
 8811 
 8812   format %{ "sarl    $dst, $shift" %}
 8813   ins_encode %{
 8814     __ sarl($dst$$Register, $shift$$constant);
 8815   %}
 8816   ins_pipe(ialu_reg);
 8817 %}
 8818 
 8819 // Arithmetic shift right by one
 8820 instruct sarI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8821 %{
 8822   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8823   effect(KILL cr);
 8824 
 8825   format %{ "sarl    $dst, $shift" %}
 8826   ins_encode %{
 8827     __ sarl($dst$$Address, $shift$$constant);
 8828   %}
 8829   ins_pipe(ialu_mem_imm);
 8830 %}
 8831 
 8832 // Arithmetic Shift Right by 8-bit immediate
 8833 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8834 %{
 8835   match(Set dst (RShiftI dst shift));
 8836   effect(KILL cr);
 8837 
 8838   format %{ "sarl    $dst, $shift" %}
 8839   ins_encode %{
 8840     __ sarl($dst$$Register, $shift$$constant);
 8841   %}
 8842   ins_pipe(ialu_mem_imm);
 8843 %}
 8844 
 8845 // Arithmetic Shift Right by 8-bit immediate
 8846 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8847 %{
 8848   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8849   effect(KILL cr);
 8850 
 8851   format %{ "sarl    $dst, $shift" %}
 8852   ins_encode %{
 8853     __ sarl($dst$$Address, $shift$$constant);
 8854   %}
 8855   ins_pipe(ialu_mem_imm);
 8856 %}
 8857 
 8858 // Arithmetic Shift Right by variable
 8859 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8860 %{
 8861   match(Set dst (RShiftI dst shift));
 8862   effect(KILL cr);
 8863   format %{ "sarl    $dst, $shift" %}
 8864   ins_encode %{
 8865     __ sarl($dst$$Register);
 8866   %}
 8867   ins_pipe(ialu_reg_reg);
 8868 %}
 8869 
 8870 // Arithmetic Shift Right by variable
 8871 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8872 %{
 8873   match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
 8874   effect(KILL cr);
 8875 
 8876   format %{ "sarl    $dst, $shift" %}
 8877   ins_encode %{
 8878     __ sarl($dst$$Address);
 8879   %}
 8880   ins_pipe(ialu_mem_reg);
 8881 %}
 8882 
 8883 // Logical shift right by one
 8884 instruct shrI_rReg_1(rRegI dst, immI_1 shift, rFlagsReg cr)
 8885 %{
 8886   match(Set dst (URShiftI dst shift));
 8887   effect(KILL cr);
 8888 
 8889   format %{ "shrl    $dst, $shift" %}
 8890   ins_encode %{
 8891     __ shrl($dst$$Register, $shift$$constant);
 8892   %}
 8893   ins_pipe(ialu_reg);
 8894 %}
 8895 
 8896 // Logical shift right by one
 8897 instruct shrI_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8898 %{
 8899   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8900   effect(KILL cr);
 8901 
 8902   format %{ "shrl    $dst, $shift" %}
 8903   ins_encode %{
 8904     __ shrl($dst$$Address, $shift$$constant);
 8905   %}
 8906   ins_pipe(ialu_mem_imm);
 8907 %}
 8908 
 8909 // Logical Shift Right by 8-bit immediate
 8910 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 8911 %{
 8912   match(Set dst (URShiftI dst shift));
 8913   effect(KILL cr);
 8914 
 8915   format %{ "shrl    $dst, $shift" %}
 8916   ins_encode %{
 8917     __ shrl($dst$$Register, $shift$$constant);
 8918   %}
 8919   ins_pipe(ialu_reg);
 8920 %}
 8921 
 8922 // Logical Shift Right by 8-bit immediate
 8923 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 8924 %{
 8925   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8926   effect(KILL cr);
 8927 
 8928   format %{ "shrl    $dst, $shift" %}
 8929   ins_encode %{
 8930     __ shrl($dst$$Address, $shift$$constant);
 8931   %}
 8932   ins_pipe(ialu_mem_imm);
 8933 %}
 8934 
 8935 // Logical Shift Right by variable
 8936 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 8937 %{
 8938   match(Set dst (URShiftI dst shift));
 8939   effect(KILL cr);
 8940 
 8941   format %{ "shrl    $dst, $shift" %}
 8942   ins_encode %{
 8943     __ shrl($dst$$Register);
 8944   %}
 8945   ins_pipe(ialu_reg_reg);
 8946 %}
 8947 
 8948 // Logical Shift Right by variable
 8949 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 8950 %{
 8951   match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
 8952   effect(KILL cr);
 8953 
 8954   format %{ "shrl    $dst, $shift" %}
 8955   ins_encode %{
 8956     __ shrl($dst$$Address);
 8957   %}
 8958   ins_pipe(ialu_mem_reg);
 8959 %}
 8960 
 8961 // Long Shift Instructions
 8962 // Shift Left by one
 8963 instruct salL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 8964 %{
 8965   match(Set dst (LShiftL dst shift));
 8966   effect(KILL cr);
 8967 
 8968   format %{ "salq    $dst, $shift" %}
 8969   ins_encode %{
 8970     __ salq($dst$$Register, $shift$$constant);
 8971   %}
 8972   ins_pipe(ialu_reg);
 8973 %}
 8974 
 8975 // Shift Left by one
 8976 instruct salL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 8977 %{
 8978   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 8979   effect(KILL cr);
 8980 
 8981   format %{ "salq    $dst, $shift" %}
 8982   ins_encode %{
 8983     __ salq($dst$$Address, $shift$$constant);
 8984   %}
 8985   ins_pipe(ialu_mem_imm);
 8986 %}
 8987 
 8988 // Shift Left by 8-bit immediate
 8989 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 8990 %{
 8991   match(Set dst (LShiftL dst shift));
 8992   effect(KILL cr);
 8993 
 8994   format %{ "salq    $dst, $shift" %}
 8995   ins_encode %{
 8996     __ salq($dst$$Register, $shift$$constant);
 8997   %}
 8998   ins_pipe(ialu_reg);
 8999 %}
 9000 
 9001 // Shift Left by 8-bit immediate
 9002 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9003 %{
 9004   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 9005   effect(KILL cr);
 9006 
 9007   format %{ "salq    $dst, $shift" %}
 9008   ins_encode %{
 9009     __ salq($dst$$Address, $shift$$constant);
 9010   %}
 9011   ins_pipe(ialu_mem_imm);
 9012 %}
 9013 
 9014 // Shift Left by variable
 9015 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9016 %{
 9017   match(Set dst (LShiftL dst shift));
 9018   effect(KILL cr);
 9019 
 9020   format %{ "salq    $dst, $shift" %}
 9021   ins_encode %{
 9022     __ salq($dst$$Register);
 9023   %}
 9024   ins_pipe(ialu_reg_reg);
 9025 %}
 9026 
 9027 // Shift Left by variable
 9028 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9029 %{
 9030   match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
 9031   effect(KILL cr);
 9032 
 9033   format %{ "salq    $dst, $shift" %}
 9034   ins_encode %{
 9035     __ salq($dst$$Address);
 9036   %}
 9037   ins_pipe(ialu_mem_reg);
 9038 %}
 9039 
 9040 // Arithmetic shift right by one
 9041 instruct sarL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 9042 %{
 9043   match(Set dst (RShiftL dst shift));
 9044   effect(KILL cr);
 9045 
 9046   format %{ "sarq    $dst, $shift" %}
 9047   ins_encode %{
 9048     __ sarq($dst$$Register, $shift$$constant);
 9049   %}
 9050   ins_pipe(ialu_reg);
 9051 %}
 9052 
 9053 // Arithmetic shift right by one
 9054 instruct sarL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 9055 %{
 9056   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9057   effect(KILL cr);
 9058 
 9059   format %{ "sarq    $dst, $shift" %}
 9060   ins_encode %{
 9061     __ sarq($dst$$Address, $shift$$constant);
 9062   %}
 9063   ins_pipe(ialu_mem_imm);
 9064 %}
 9065 
 9066 // Arithmetic Shift Right by 8-bit immediate
 9067 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9068 %{
 9069   match(Set dst (RShiftL dst shift));
 9070   effect(KILL cr);
 9071 
 9072   format %{ "sarq    $dst, $shift" %}
 9073   ins_encode %{
 9074     __ sarq($dst$$Register, (unsigned char)($shift$$constant & 0x3F));
 9075   %}
 9076   ins_pipe(ialu_mem_imm);
 9077 %}
 9078 
 9079 // Arithmetic Shift Right by 8-bit immediate
 9080 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9081 %{
 9082   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9083   effect(KILL cr);
 9084 
 9085   format %{ "sarq    $dst, $shift" %}
 9086   ins_encode %{
 9087     __ sarq($dst$$Address, (unsigned char)($shift$$constant & 0x3F));
 9088   %}
 9089   ins_pipe(ialu_mem_imm);
 9090 %}
 9091 
 9092 // Arithmetic Shift Right by variable
 9093 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9094 %{
 9095   match(Set dst (RShiftL dst shift));
 9096   effect(KILL cr);
 9097 
 9098   format %{ "sarq    $dst, $shift" %}
 9099   ins_encode %{
 9100     __ sarq($dst$$Register);
 9101   %}
 9102   ins_pipe(ialu_reg_reg);
 9103 %}
 9104 
 9105 // Arithmetic Shift Right by variable
 9106 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9107 %{
 9108   match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
 9109   effect(KILL cr);
 9110 
 9111   format %{ "sarq    $dst, $shift" %}
 9112   ins_encode %{
 9113     __ sarq($dst$$Address);
 9114   %}
 9115   ins_pipe(ialu_mem_reg);
 9116 %}
 9117 
 9118 // Logical shift right by one
 9119 instruct shrL_rReg_1(rRegL dst, immI_1 shift, rFlagsReg cr)
 9120 %{
 9121   match(Set dst (URShiftL dst shift));
 9122   effect(KILL cr);
 9123 
 9124   format %{ "shrq    $dst, $shift" %}
 9125   ins_encode %{
 9126     __ shrq($dst$$Register, $shift$$constant);
 9127   %}
 9128   ins_pipe(ialu_reg);
 9129 %}
 9130 
 9131 // Logical shift right by one
 9132 instruct shrL_mem_1(memory dst, immI_1 shift, rFlagsReg cr)
 9133 %{
 9134   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9135   effect(KILL cr);
 9136 
 9137   format %{ "shrq    $dst, $shift" %}
 9138   ins_encode %{
 9139     __ shrq($dst$$Address, $shift$$constant);
 9140   %}
 9141   ins_pipe(ialu_mem_imm);
 9142 %}
 9143 
 9144 // Logical Shift Right by 8-bit immediate
 9145 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
 9146 %{
 9147   match(Set dst (URShiftL dst shift));
 9148   effect(KILL cr);
 9149 
 9150   format %{ "shrq    $dst, $shift" %}
 9151   ins_encode %{
 9152     __ shrq($dst$$Register, $shift$$constant);
 9153   %}
 9154   ins_pipe(ialu_reg);
 9155 %}
 9156 
 9157 // Logical Shift Right by 8-bit immediate
 9158 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
 9159 %{
 9160   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9161   effect(KILL cr);
 9162 
 9163   format %{ "shrq    $dst, $shift" %}
 9164   ins_encode %{
 9165     __ shrq($dst$$Address, $shift$$constant);
 9166   %}
 9167   ins_pipe(ialu_mem_imm);
 9168 %}
 9169 
 9170 // Logical Shift Right by variable
 9171 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9172 %{
 9173   match(Set dst (URShiftL dst shift));
 9174   effect(KILL cr);
 9175 
 9176   format %{ "shrq    $dst, $shift" %}
 9177   ins_encode %{
 9178     __ shrq($dst$$Register);
 9179   %}
 9180   ins_pipe(ialu_reg_reg);
 9181 %}
 9182 
 9183 // Logical Shift Right by variable
 9184 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
 9185 %{
 9186   match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
 9187   effect(KILL cr);
 9188 
 9189   format %{ "shrq    $dst, $shift" %}
 9190   ins_encode %{
 9191     __ shrq($dst$$Address);
 9192   %}
 9193   ins_pipe(ialu_mem_reg);
 9194 %}
 9195 
 9196 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
 9197 // This idiom is used by the compiler for the i2b bytecode.
 9198 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
 9199 %{
 9200   match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
 9201 
 9202   format %{ "movsbl  $dst, $src\t# i2b" %}
 9203   ins_encode %{
 9204     __ movsbl($dst$$Register, $src$$Register);
 9205   %}
 9206   ins_pipe(ialu_reg_reg);
 9207 %}
 9208 
 9209 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
 9210 // This idiom is used by the compiler the i2s bytecode.
 9211 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
 9212 %{
 9213   match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
 9214 
 9215   format %{ "movswl  $dst, $src\t# i2s" %}
 9216   ins_encode %{
 9217     __ movswl($dst$$Register, $src$$Register);
 9218   %}
 9219   ins_pipe(ialu_reg_reg);
 9220 %}
 9221 
 9222 // ROL/ROR instructions
 9223 
 9224 // Rotate left by constant.
 9225 instruct rolI_imm(rRegI dst, immI8 shift, rFlagsReg cr)
 9226 %{
 9227   predicate(n->bottom_type()->basic_type() == T_INT);
 9228   match(Set dst (RotateLeft dst shift));
 9229   effect(KILL cr);
 9230   format %{ "roll    $dst, $shift" %}
 9231   ins_encode %{
 9232     __ roll($dst$$Register, $shift$$constant);
 9233   %}
 9234   ins_pipe(ialu_reg);
 9235 %}
 9236 
 9237 // Rotate Left by variable
 9238 instruct rolI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9239 %{
 9240   predicate(n->bottom_type()->basic_type() == T_INT);
 9241   match(Set dst (RotateLeft dst shift));
 9242   effect(KILL cr);
 9243   format %{ "roll    $dst, $shift" %}
 9244   ins_encode %{
 9245     __ roll($dst$$Register);
 9246   %}
 9247   ins_pipe(ialu_reg_reg);
 9248 %}
 9249 
 9250 // Rotate Right by constant.
 9251 instruct rorI_immI8_legacy(rRegI dst, immI8 shift, rFlagsReg cr)
 9252 %{
 9253   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9254   match(Set dst (RotateRight dst shift));
 9255   effect(KILL cr);
 9256   format %{ "rorl    $dst, $shift" %}
 9257   ins_encode %{
 9258     __ rorl($dst$$Register, $shift$$constant);
 9259   %}
 9260   ins_pipe(ialu_reg);
 9261 %}
 9262 
 9263 // Rotate Right by constant.
 9264 instruct rorI_immI8(rRegI dst, immI8 shift)
 9265 %{
 9266   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_INT);
 9267   match(Set dst (RotateRight dst shift));
 9268   format %{ "rorxd     $dst, $shift" %}
 9269   ins_encode %{
 9270     __ rorxd($dst$$Register, $dst$$Register, $shift$$constant);
 9271   %}
 9272   ins_pipe(ialu_reg_reg);
 9273 %}
 9274 
 9275 // Rotate Right by variable
 9276 instruct rorI_rReg_Var(rRegI dst, rcx_RegI shift, rFlagsReg cr)
 9277 %{
 9278   predicate(n->bottom_type()->basic_type() == T_INT);
 9279   match(Set dst (RotateRight dst shift));
 9280   effect(KILL cr);
 9281   format %{ "rorl    $dst, $shift" %}
 9282   ins_encode %{
 9283     __ rorl($dst$$Register);
 9284   %}
 9285   ins_pipe(ialu_reg_reg);
 9286 %}
 9287 
 9288 
 9289 // Rotate Left by constant.
 9290 instruct rolL_immI8(rRegL dst, immI8 shift, rFlagsReg cr)
 9291 %{
 9292   predicate(n->bottom_type()->basic_type() == T_LONG);
 9293   match(Set dst (RotateLeft dst shift));
 9294   effect(KILL cr);
 9295   format %{ "rolq    $dst, $shift" %}
 9296   ins_encode %{
 9297     __ rolq($dst$$Register, $shift$$constant);
 9298   %}
 9299   ins_pipe(ialu_reg);
 9300 %}
 9301 
 9302 // Rotate Left by variable
 9303 instruct rolL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9304 %{
 9305   predicate(n->bottom_type()->basic_type() == T_LONG);
 9306   match(Set dst (RotateLeft dst shift));
 9307   effect(KILL cr);
 9308   format %{ "rolq    $dst, $shift" %}
 9309   ins_encode %{
 9310     __ rolq($dst$$Register);
 9311   %}
 9312   ins_pipe(ialu_reg_reg);
 9313 %}
 9314 
 9315 
 9316 // Rotate Right by constant.
 9317 instruct rorL_immI8_legacy(rRegL dst, immI8 shift, rFlagsReg cr)
 9318 %{
 9319   predicate(!VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9320   match(Set dst (RotateRight dst shift));
 9321   effect(KILL cr);
 9322   format %{ "rorq    $dst, $shift" %}
 9323   ins_encode %{
 9324     __ rorq($dst$$Register, $shift$$constant);
 9325   %}
 9326   ins_pipe(ialu_reg);
 9327 %}
 9328 
 9329 
 9330 // Rotate Right by constant
 9331 instruct rorL_immI8(rRegL dst, immI8 shift)
 9332 %{
 9333   predicate(VM_Version::supports_bmi2() && n->bottom_type()->basic_type() == T_LONG);
 9334   match(Set dst (RotateRight dst shift));
 9335   format %{ "rorxq    $dst, $shift" %}
 9336   ins_encode %{
 9337     __ rorxq($dst$$Register, $dst$$Register, $shift$$constant);
 9338   %}
 9339   ins_pipe(ialu_reg_reg);
 9340 %}
 9341 
 9342 // Rotate Right by variable
 9343 instruct rorL_rReg_Var(rRegL dst, rcx_RegI shift, rFlagsReg cr)
 9344 %{
 9345   predicate(n->bottom_type()->basic_type() == T_LONG);
 9346   match(Set dst (RotateRight dst shift));
 9347   effect(KILL cr);
 9348   format %{ "rorq    $dst, $shift" %}
 9349   ins_encode %{
 9350     __ rorq($dst$$Register);
 9351   %}
 9352   ins_pipe(ialu_reg_reg);
 9353 %}
 9354 
 9355 
 9356 // Logical Instructions
 9357 
 9358 // Integer Logical Instructions
 9359 
 9360 // And Instructions
 9361 // And Register with Register
 9362 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9363 %{
 9364   match(Set dst (AndI dst src));
 9365   effect(KILL cr);
 9366 
 9367   format %{ "andl    $dst, $src\t# int" %}
 9368   ins_encode %{
 9369     __ andl($dst$$Register, $src$$Register);
 9370   %}
 9371   ins_pipe(ialu_reg_reg);
 9372 %}
 9373 
 9374 // And Register with Immediate 255
 9375 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
 9376 %{
 9377   match(Set dst (AndI dst src));
 9378 
 9379   format %{ "movzbl  $dst, $dst\t# int & 0xFF" %}
 9380   ins_encode %{
 9381     __ movzbl($dst$$Register, $dst$$Register);
 9382   %}
 9383   ins_pipe(ialu_reg);
 9384 %}
 9385 
 9386 // And Register with Immediate 255 and promote to long
 9387 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
 9388 %{
 9389   match(Set dst (ConvI2L (AndI src mask)));
 9390 
 9391   format %{ "movzbl  $dst, $src\t# int & 0xFF -> long" %}
 9392   ins_encode %{
 9393     __ movzbl($dst$$Register, $src$$Register);
 9394   %}
 9395   ins_pipe(ialu_reg);
 9396 %}
 9397 
 9398 // And Register with Immediate 65535
 9399 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
 9400 %{
 9401   match(Set dst (AndI dst src));
 9402 
 9403   format %{ "movzwl  $dst, $dst\t# int & 0xFFFF" %}
 9404   ins_encode %{
 9405     __ movzwl($dst$$Register, $dst$$Register);
 9406   %}
 9407   ins_pipe(ialu_reg);
 9408 %}
 9409 
 9410 // And Register with Immediate 65535 and promote to long
 9411 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
 9412 %{
 9413   match(Set dst (ConvI2L (AndI src mask)));
 9414 
 9415   format %{ "movzwl  $dst, $src\t# int & 0xFFFF -> long" %}
 9416   ins_encode %{
 9417     __ movzwl($dst$$Register, $src$$Register);
 9418   %}
 9419   ins_pipe(ialu_reg);
 9420 %}
 9421 
 9422 // Can skip int2long conversions after AND with small bitmask
 9423 instruct convI2LAndI_reg_immIbitmask(rRegL dst, rRegI src,  immI_Pow2M1 mask, rRegI tmp, rFlagsReg cr)
 9424 %{
 9425   predicate(VM_Version::supports_bmi2());
 9426   ins_cost(125);
 9427   effect(TEMP tmp, KILL cr);
 9428   match(Set dst (ConvI2L (AndI src mask)));
 9429   format %{ "bzhiq $dst, $src, $mask \t# using $tmp as TEMP, int &  immI_Pow2M1 -> long" %}
 9430   ins_encode %{
 9431     __ movl($tmp$$Register, exact_log2($mask$$constant + 1));
 9432     __ bzhiq($dst$$Register, $src$$Register, $tmp$$Register);
 9433   %}
 9434   ins_pipe(ialu_reg_reg);
 9435 %}
 9436 
 9437 // And Register with Immediate
 9438 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9439 %{
 9440   match(Set dst (AndI dst src));
 9441   effect(KILL cr);
 9442 
 9443   format %{ "andl    $dst, $src\t# int" %}
 9444   ins_encode %{
 9445     __ andl($dst$$Register, $src$$constant);
 9446   %}
 9447   ins_pipe(ialu_reg);
 9448 %}
 9449 
 9450 // And Register with Memory
 9451 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9452 %{
 9453   match(Set dst (AndI dst (LoadI src)));
 9454   effect(KILL cr);
 9455 
 9456   ins_cost(125);
 9457   format %{ "andl    $dst, $src\t# int" %}
 9458   ins_encode %{
 9459     __ andl($dst$$Register, $src$$Address);
 9460   %}
 9461   ins_pipe(ialu_reg_mem);
 9462 %}
 9463 
 9464 // And Memory with Register
 9465 instruct andB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9466 %{
 9467   match(Set dst (StoreB dst (AndI (LoadB dst) src)));
 9468   effect(KILL cr);
 9469 
 9470   ins_cost(150);
 9471   format %{ "andb    $dst, $src\t# byte" %}
 9472   ins_encode %{
 9473     __ andb($dst$$Address, $src$$Register);
 9474   %}
 9475   ins_pipe(ialu_mem_reg);
 9476 %}
 9477 
 9478 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9479 %{
 9480   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
 9481   effect(KILL cr);
 9482 
 9483   ins_cost(150);
 9484   format %{ "andl    $dst, $src\t# int" %}
 9485   ins_encode %{
 9486     __ andl($dst$$Address, $src$$Register);
 9487   %}
 9488   ins_pipe(ialu_mem_reg);
 9489 %}
 9490 
 9491 // And Memory with Immediate
 9492 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9493 %{
 9494   match(Set dst (StoreI dst (AndI (LoadI dst) src)));
 9495   effect(KILL cr);
 9496 
 9497   ins_cost(125);
 9498   format %{ "andl    $dst, $src\t# int" %}
 9499   ins_encode %{
 9500     __ andl($dst$$Address, $src$$constant);
 9501   %}
 9502   ins_pipe(ialu_mem_imm);
 9503 %}
 9504 
 9505 // BMI1 instructions
 9506 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
 9507   match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
 9508   predicate(UseBMI1Instructions);
 9509   effect(KILL cr);
 9510 
 9511   ins_cost(125);
 9512   format %{ "andnl  $dst, $src1, $src2" %}
 9513 
 9514   ins_encode %{
 9515     __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
 9516   %}
 9517   ins_pipe(ialu_reg_mem);
 9518 %}
 9519 
 9520 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
 9521   match(Set dst (AndI (XorI src1 minus_1) src2));
 9522   predicate(UseBMI1Instructions);
 9523   effect(KILL cr);
 9524 
 9525   format %{ "andnl  $dst, $src1, $src2" %}
 9526 
 9527   ins_encode %{
 9528     __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
 9529   %}
 9530   ins_pipe(ialu_reg);
 9531 %}
 9532 
 9533 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI_0 imm_zero, rFlagsReg cr) %{
 9534   match(Set dst (AndI (SubI imm_zero src) src));
 9535   predicate(UseBMI1Instructions);
 9536   effect(KILL cr);
 9537 
 9538   format %{ "blsil  $dst, $src" %}
 9539 
 9540   ins_encode %{
 9541     __ blsil($dst$$Register, $src$$Register);
 9542   %}
 9543   ins_pipe(ialu_reg);
 9544 %}
 9545 
 9546 instruct blsiI_rReg_mem(rRegI dst, memory src, immI_0 imm_zero, rFlagsReg cr) %{
 9547   match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
 9548   predicate(UseBMI1Instructions);
 9549   effect(KILL cr);
 9550 
 9551   ins_cost(125);
 9552   format %{ "blsil  $dst, $src" %}
 9553 
 9554   ins_encode %{
 9555     __ blsil($dst$$Register, $src$$Address);
 9556   %}
 9557   ins_pipe(ialu_reg_mem);
 9558 %}
 9559 
 9560 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
 9561 %{
 9562   match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
 9563   predicate(UseBMI1Instructions);
 9564   effect(KILL cr);
 9565 
 9566   ins_cost(125);
 9567   format %{ "blsmskl $dst, $src" %}
 9568 
 9569   ins_encode %{
 9570     __ blsmskl($dst$$Register, $src$$Address);
 9571   %}
 9572   ins_pipe(ialu_reg_mem);
 9573 %}
 9574 
 9575 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
 9576 %{
 9577   match(Set dst (XorI (AddI src minus_1) src));
 9578   predicate(UseBMI1Instructions);
 9579   effect(KILL cr);
 9580 
 9581   format %{ "blsmskl $dst, $src" %}
 9582 
 9583   ins_encode %{
 9584     __ blsmskl($dst$$Register, $src$$Register);
 9585   %}
 9586 
 9587   ins_pipe(ialu_reg);
 9588 %}
 9589 
 9590 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
 9591 %{
 9592   match(Set dst (AndI (AddI src minus_1) src) );
 9593   predicate(UseBMI1Instructions);
 9594   effect(KILL cr);
 9595 
 9596   format %{ "blsrl  $dst, $src" %}
 9597 
 9598   ins_encode %{
 9599     __ blsrl($dst$$Register, $src$$Register);
 9600   %}
 9601 
 9602   ins_pipe(ialu_reg_mem);
 9603 %}
 9604 
 9605 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
 9606 %{
 9607   match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
 9608   predicate(UseBMI1Instructions);
 9609   effect(KILL cr);
 9610 
 9611   ins_cost(125);
 9612   format %{ "blsrl  $dst, $src" %}
 9613 
 9614   ins_encode %{
 9615     __ blsrl($dst$$Register, $src$$Address);
 9616   %}
 9617 
 9618   ins_pipe(ialu_reg);
 9619 %}
 9620 
 9621 // Or Instructions
 9622 // Or Register with Register
 9623 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9624 %{
 9625   match(Set dst (OrI dst src));
 9626   effect(KILL cr);
 9627 
 9628   format %{ "orl     $dst, $src\t# int" %}
 9629   ins_encode %{
 9630     __ orl($dst$$Register, $src$$Register);
 9631   %}
 9632   ins_pipe(ialu_reg_reg);
 9633 %}
 9634 
 9635 // Or Register with Immediate
 9636 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9637 %{
 9638   match(Set dst (OrI dst src));
 9639   effect(KILL cr);
 9640 
 9641   format %{ "orl     $dst, $src\t# int" %}
 9642   ins_encode %{
 9643     __ orl($dst$$Register, $src$$constant);
 9644   %}
 9645   ins_pipe(ialu_reg);
 9646 %}
 9647 
 9648 // Or Register with Memory
 9649 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9650 %{
 9651   match(Set dst (OrI dst (LoadI src)));
 9652   effect(KILL cr);
 9653 
 9654   ins_cost(125);
 9655   format %{ "orl     $dst, $src\t# int" %}
 9656   ins_encode %{
 9657     __ orl($dst$$Register, $src$$Address);
 9658   %}
 9659   ins_pipe(ialu_reg_mem);
 9660 %}
 9661 
 9662 // Or Memory with Register
 9663 instruct orB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9664 %{
 9665   match(Set dst (StoreB dst (OrI (LoadB dst) src)));
 9666   effect(KILL cr);
 9667 
 9668   ins_cost(150);
 9669   format %{ "orb    $dst, $src\t# byte" %}
 9670   ins_encode %{
 9671     __ orb($dst$$Address, $src$$Register);
 9672   %}
 9673   ins_pipe(ialu_mem_reg);
 9674 %}
 9675 
 9676 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9677 %{
 9678   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
 9679   effect(KILL cr);
 9680 
 9681   ins_cost(150);
 9682   format %{ "orl     $dst, $src\t# int" %}
 9683   ins_encode %{
 9684     __ orl($dst$$Address, $src$$Register);
 9685   %}
 9686   ins_pipe(ialu_mem_reg);
 9687 %}
 9688 
 9689 // Or Memory with Immediate
 9690 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9691 %{
 9692   match(Set dst (StoreI dst (OrI (LoadI dst) src)));
 9693   effect(KILL cr);
 9694 
 9695   ins_cost(125);
 9696   format %{ "orl     $dst, $src\t# int" %}
 9697   ins_encode %{
 9698     __ orl($dst$$Address, $src$$constant);
 9699   %}
 9700   ins_pipe(ialu_mem_imm);
 9701 %}
 9702 
 9703 // Xor Instructions
 9704 // Xor Register with Register
 9705 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
 9706 %{
 9707   match(Set dst (XorI dst src));
 9708   effect(KILL cr);
 9709 
 9710   format %{ "xorl    $dst, $src\t# int" %}
 9711   ins_encode %{
 9712     __ xorl($dst$$Register, $src$$Register);
 9713   %}
 9714   ins_pipe(ialu_reg_reg);
 9715 %}
 9716 
 9717 // Xor Register with Immediate -1
 9718 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
 9719   match(Set dst (XorI dst imm));
 9720 
 9721   format %{ "not    $dst" %}
 9722   ins_encode %{
 9723      __ notl($dst$$Register);
 9724   %}
 9725   ins_pipe(ialu_reg);
 9726 %}
 9727 
 9728 // Xor Register with Immediate
 9729 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
 9730 %{
 9731   match(Set dst (XorI dst src));
 9732   effect(KILL cr);
 9733 
 9734   format %{ "xorl    $dst, $src\t# int" %}
 9735   ins_encode %{
 9736     __ xorl($dst$$Register, $src$$constant);
 9737   %}
 9738   ins_pipe(ialu_reg);
 9739 %}
 9740 
 9741 // Xor Register with Memory
 9742 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
 9743 %{
 9744   match(Set dst (XorI dst (LoadI src)));
 9745   effect(KILL cr);
 9746 
 9747   ins_cost(125);
 9748   format %{ "xorl    $dst, $src\t# int" %}
 9749   ins_encode %{
 9750     __ xorl($dst$$Register, $src$$Address);
 9751   %}
 9752   ins_pipe(ialu_reg_mem);
 9753 %}
 9754 
 9755 // Xor Memory with Register
 9756 instruct xorB_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9757 %{
 9758   match(Set dst (StoreB dst (XorI (LoadB dst) src)));
 9759   effect(KILL cr);
 9760 
 9761   ins_cost(150);
 9762   format %{ "xorb    $dst, $src\t# byte" %}
 9763   ins_encode %{
 9764     __ xorb($dst$$Address, $src$$Register);
 9765   %}
 9766   ins_pipe(ialu_mem_reg);
 9767 %}
 9768 
 9769 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
 9770 %{
 9771   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
 9772   effect(KILL cr);
 9773 
 9774   ins_cost(150);
 9775   format %{ "xorl    $dst, $src\t# int" %}
 9776   ins_encode %{
 9777     __ xorl($dst$$Address, $src$$Register);
 9778   %}
 9779   ins_pipe(ialu_mem_reg);
 9780 %}
 9781 
 9782 // Xor Memory with Immediate
 9783 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
 9784 %{
 9785   match(Set dst (StoreI dst (XorI (LoadI dst) src)));
 9786   effect(KILL cr);
 9787 
 9788   ins_cost(125);
 9789   format %{ "xorl    $dst, $src\t# int" %}
 9790   ins_encode %{
 9791     __ xorl($dst$$Address, $src$$constant);
 9792   %}
 9793   ins_pipe(ialu_mem_imm);
 9794 %}
 9795 
 9796 
 9797 // Long Logical Instructions
 9798 
 9799 // And Instructions
 9800 // And Register with Register
 9801 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
 9802 %{
 9803   match(Set dst (AndL dst src));
 9804   effect(KILL cr);
 9805 
 9806   format %{ "andq    $dst, $src\t# long" %}
 9807   ins_encode %{
 9808     __ andq($dst$$Register, $src$$Register);
 9809   %}
 9810   ins_pipe(ialu_reg_reg);
 9811 %}
 9812 
 9813 // And Register with Immediate 255
 9814 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
 9815 %{
 9816   match(Set dst (AndL dst src));
 9817 
 9818   format %{ "movzbq  $dst, $dst\t# long & 0xFF" %}
 9819   ins_encode %{
 9820     __ movzbq($dst$$Register, $dst$$Register);
 9821   %}
 9822   ins_pipe(ialu_reg);
 9823 %}
 9824 
 9825 // And Register with Immediate 65535
 9826 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
 9827 %{
 9828   match(Set dst (AndL dst src));
 9829 
 9830   format %{ "movzwq  $dst, $dst\t# long & 0xFFFF" %}
 9831   ins_encode %{
 9832     __ movzwq($dst$$Register, $dst$$Register);
 9833   %}
 9834   ins_pipe(ialu_reg);
 9835 %}
 9836 
 9837 // And Register with Immediate
 9838 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
 9839 %{
 9840   match(Set dst (AndL dst src));
 9841   effect(KILL cr);
 9842 
 9843   format %{ "andq    $dst, $src\t# long" %}
 9844   ins_encode %{
 9845     __ andq($dst$$Register, $src$$constant);
 9846   %}
 9847   ins_pipe(ialu_reg);
 9848 %}
 9849 
 9850 // And Register with Memory
 9851 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
 9852 %{
 9853   match(Set dst (AndL dst (LoadL src)));
 9854   effect(KILL cr);
 9855 
 9856   ins_cost(125);
 9857   format %{ "andq    $dst, $src\t# long" %}
 9858   ins_encode %{
 9859     __ andq($dst$$Register, $src$$Address);
 9860   %}
 9861   ins_pipe(ialu_reg_mem);
 9862 %}
 9863 
 9864 // And Memory with Register
 9865 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
 9866 %{
 9867   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
 9868   effect(KILL cr);
 9869 
 9870   ins_cost(150);
 9871   format %{ "andq    $dst, $src\t# long" %}
 9872   ins_encode %{
 9873     __ andq($dst$$Address, $src$$Register);
 9874   %}
 9875   ins_pipe(ialu_mem_reg);
 9876 %}
 9877 
 9878 // And Memory with Immediate
 9879 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
 9880 %{
 9881   match(Set dst (StoreL dst (AndL (LoadL dst) src)));
 9882   effect(KILL cr);
 9883 
 9884   ins_cost(125);
 9885   format %{ "andq    $dst, $src\t# long" %}
 9886   ins_encode %{
 9887     __ andq($dst$$Address, $src$$constant);
 9888   %}
 9889   ins_pipe(ialu_mem_imm);
 9890 %}
 9891 
 9892 instruct btrL_mem_imm(memory dst, immL_NotPow2 con, rFlagsReg cr)
 9893 %{
 9894   // con should be a pure 64-bit immediate given that not(con) is a power of 2
 9895   // because AND/OR works well enough for 8/32-bit values.
 9896   predicate(log2i_graceful(~n->in(3)->in(2)->get_long()) > 30);
 9897 
 9898   match(Set dst (StoreL dst (AndL (LoadL dst) con)));
 9899   effect(KILL cr);
 9900 
 9901   ins_cost(125);
 9902   format %{ "btrq    $dst, log2(not($con))\t# long" %}
 9903   ins_encode %{
 9904     __ btrq($dst$$Address, log2i_exact((julong)~$con$$constant));
 9905   %}
 9906   ins_pipe(ialu_mem_imm);
 9907 %}
 9908 
 9909 // BMI1 instructions
 9910 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
 9911   match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
 9912   predicate(UseBMI1Instructions);
 9913   effect(KILL cr);
 9914 
 9915   ins_cost(125);
 9916   format %{ "andnq  $dst, $src1, $src2" %}
 9917 
 9918   ins_encode %{
 9919     __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
 9920   %}
 9921   ins_pipe(ialu_reg_mem);
 9922 %}
 9923 
 9924 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
 9925   match(Set dst (AndL (XorL src1 minus_1) src2));
 9926   predicate(UseBMI1Instructions);
 9927   effect(KILL cr);
 9928 
 9929   format %{ "andnq  $dst, $src1, $src2" %}
 9930 
 9931   ins_encode %{
 9932   __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
 9933   %}
 9934   ins_pipe(ialu_reg_mem);
 9935 %}
 9936 
 9937 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
 9938   match(Set dst (AndL (SubL imm_zero src) src));
 9939   predicate(UseBMI1Instructions);
 9940   effect(KILL cr);
 9941 
 9942   format %{ "blsiq  $dst, $src" %}
 9943 
 9944   ins_encode %{
 9945     __ blsiq($dst$$Register, $src$$Register);
 9946   %}
 9947   ins_pipe(ialu_reg);
 9948 %}
 9949 
 9950 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
 9951   match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
 9952   predicate(UseBMI1Instructions);
 9953   effect(KILL cr);
 9954 
 9955   ins_cost(125);
 9956   format %{ "blsiq  $dst, $src" %}
 9957 
 9958   ins_encode %{
 9959     __ blsiq($dst$$Register, $src$$Address);
 9960   %}
 9961   ins_pipe(ialu_reg_mem);
 9962 %}
 9963 
 9964 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
 9965 %{
 9966   match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
 9967   predicate(UseBMI1Instructions);
 9968   effect(KILL cr);
 9969 
 9970   ins_cost(125);
 9971   format %{ "blsmskq $dst, $src" %}
 9972 
 9973   ins_encode %{
 9974     __ blsmskq($dst$$Register, $src$$Address);
 9975   %}
 9976   ins_pipe(ialu_reg_mem);
 9977 %}
 9978 
 9979 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
 9980 %{
 9981   match(Set dst (XorL (AddL src minus_1) src));
 9982   predicate(UseBMI1Instructions);
 9983   effect(KILL cr);
 9984 
 9985   format %{ "blsmskq $dst, $src" %}
 9986 
 9987   ins_encode %{
 9988     __ blsmskq($dst$$Register, $src$$Register);
 9989   %}
 9990 
 9991   ins_pipe(ialu_reg);
 9992 %}
 9993 
 9994 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
 9995 %{
 9996   match(Set dst (AndL (AddL src minus_1) src) );
 9997   predicate(UseBMI1Instructions);
 9998   effect(KILL cr);
 9999 
10000   format %{ "blsrq  $dst, $src" %}
10001 
10002   ins_encode %{
10003     __ blsrq($dst$$Register, $src$$Register);
10004   %}
10005 
10006   ins_pipe(ialu_reg);
10007 %}
10008 
10009 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
10010 %{
10011   match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
10012   predicate(UseBMI1Instructions);
10013   effect(KILL cr);
10014 
10015   ins_cost(125);
10016   format %{ "blsrq  $dst, $src" %}
10017 
10018   ins_encode %{
10019     __ blsrq($dst$$Register, $src$$Address);
10020   %}
10021 
10022   ins_pipe(ialu_reg);
10023 %}
10024 
10025 // Or Instructions
10026 // Or Register with Register
10027 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10028 %{
10029   match(Set dst (OrL dst src));
10030   effect(KILL cr);
10031 
10032   format %{ "orq     $dst, $src\t# long" %}
10033   ins_encode %{
10034     __ orq($dst$$Register, $src$$Register);
10035   %}
10036   ins_pipe(ialu_reg_reg);
10037 %}
10038 
10039 // Use any_RegP to match R15 (TLS register) without spilling.
10040 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
10041   match(Set dst (OrL dst (CastP2X src)));
10042   effect(KILL cr);
10043 
10044   format %{ "orq     $dst, $src\t# long" %}
10045   ins_encode %{
10046     __ orq($dst$$Register, $src$$Register);
10047   %}
10048   ins_pipe(ialu_reg_reg);
10049 %}
10050 
10051 
10052 // Or Register with Immediate
10053 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10054 %{
10055   match(Set dst (OrL dst src));
10056   effect(KILL cr);
10057 
10058   format %{ "orq     $dst, $src\t# long" %}
10059   ins_encode %{
10060     __ orq($dst$$Register, $src$$constant);
10061   %}
10062   ins_pipe(ialu_reg);
10063 %}
10064 
10065 // Or Register with Memory
10066 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10067 %{
10068   match(Set dst (OrL dst (LoadL src)));
10069   effect(KILL cr);
10070 
10071   ins_cost(125);
10072   format %{ "orq     $dst, $src\t# long" %}
10073   ins_encode %{
10074     __ orq($dst$$Register, $src$$Address);
10075   %}
10076   ins_pipe(ialu_reg_mem);
10077 %}
10078 
10079 // Or Memory with Register
10080 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10081 %{
10082   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10083   effect(KILL cr);
10084 
10085   ins_cost(150);
10086   format %{ "orq     $dst, $src\t# long" %}
10087   ins_encode %{
10088     __ orq($dst$$Address, $src$$Register);
10089   %}
10090   ins_pipe(ialu_mem_reg);
10091 %}
10092 
10093 // Or Memory with Immediate
10094 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10095 %{
10096   match(Set dst (StoreL dst (OrL (LoadL dst) src)));
10097   effect(KILL cr);
10098 
10099   ins_cost(125);
10100   format %{ "orq     $dst, $src\t# long" %}
10101   ins_encode %{
10102     __ orq($dst$$Address, $src$$constant);
10103   %}
10104   ins_pipe(ialu_mem_imm);
10105 %}
10106 
10107 instruct btsL_mem_imm(memory dst, immL_Pow2 con, rFlagsReg cr)
10108 %{
10109   // con should be a pure 64-bit power of 2 immediate
10110   // because AND/OR works well enough for 8/32-bit values.
10111   predicate(log2i_graceful(n->in(3)->in(2)->get_long()) > 31);
10112 
10113   match(Set dst (StoreL dst (OrL (LoadL dst) con)));
10114   effect(KILL cr);
10115 
10116   ins_cost(125);
10117   format %{ "btsq    $dst, log2($con)\t# long" %}
10118   ins_encode %{
10119     __ btsq($dst$$Address, log2i_exact((julong)$con$$constant));
10120   %}
10121   ins_pipe(ialu_mem_imm);
10122 %}
10123 
10124 // Xor Instructions
10125 // Xor Register with Register
10126 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
10127 %{
10128   match(Set dst (XorL dst src));
10129   effect(KILL cr);
10130 
10131   format %{ "xorq    $dst, $src\t# long" %}
10132   ins_encode %{
10133     __ xorq($dst$$Register, $src$$Register);
10134   %}
10135   ins_pipe(ialu_reg_reg);
10136 %}
10137 
10138 // Xor Register with Immediate -1
10139 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
10140   match(Set dst (XorL dst imm));
10141 
10142   format %{ "notq   $dst" %}
10143   ins_encode %{
10144      __ notq($dst$$Register);
10145   %}
10146   ins_pipe(ialu_reg);
10147 %}
10148 
10149 // Xor Register with Immediate
10150 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
10151 %{
10152   match(Set dst (XorL dst src));
10153   effect(KILL cr);
10154 
10155   format %{ "xorq    $dst, $src\t# long" %}
10156   ins_encode %{
10157     __ xorq($dst$$Register, $src$$constant);
10158   %}
10159   ins_pipe(ialu_reg);
10160 %}
10161 
10162 // Xor Register with Memory
10163 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
10164 %{
10165   match(Set dst (XorL dst (LoadL src)));
10166   effect(KILL cr);
10167 
10168   ins_cost(125);
10169   format %{ "xorq    $dst, $src\t# long" %}
10170   ins_encode %{
10171     __ xorq($dst$$Register, $src$$Address);
10172   %}
10173   ins_pipe(ialu_reg_mem);
10174 %}
10175 
10176 // Xor Memory with Register
10177 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
10178 %{
10179   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10180   effect(KILL cr);
10181 
10182   ins_cost(150);
10183   format %{ "xorq    $dst, $src\t# long" %}
10184   ins_encode %{
10185     __ xorq($dst$$Address, $src$$Register);
10186   %}
10187   ins_pipe(ialu_mem_reg);
10188 %}
10189 
10190 // Xor Memory with Immediate
10191 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
10192 %{
10193   match(Set dst (StoreL dst (XorL (LoadL dst) src)));
10194   effect(KILL cr);
10195 
10196   ins_cost(125);
10197   format %{ "xorq    $dst, $src\t# long" %}
10198   ins_encode %{
10199     __ xorq($dst$$Address, $src$$constant);
10200   %}
10201   ins_pipe(ialu_mem_imm);
10202 %}
10203 
10204 // Convert Int to Boolean
10205 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
10206 %{
10207   match(Set dst (Conv2B src));
10208   effect(KILL cr);
10209 
10210   format %{ "testl   $src, $src\t# ci2b\n\t"
10211             "setnz   $dst\n\t"
10212             "movzbl  $dst, $dst" %}
10213   ins_encode %{
10214     __ testl($src$$Register, $src$$Register);
10215     __ set_byte_if_not_zero($dst$$Register);
10216     __ movzbl($dst$$Register, $dst$$Register);
10217   %}
10218   ins_pipe(pipe_slow); // XXX
10219 %}
10220 
10221 // Convert Pointer to Boolean
10222 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
10223 %{
10224   match(Set dst (Conv2B src));
10225   effect(KILL cr);
10226 
10227   format %{ "testq   $src, $src\t# cp2b\n\t"
10228             "setnz   $dst\n\t"
10229             "movzbl  $dst, $dst" %}
10230   ins_encode %{
10231     __ testq($src$$Register, $src$$Register);
10232     __ set_byte_if_not_zero($dst$$Register);
10233     __ movzbl($dst$$Register, $dst$$Register);
10234   %}
10235   ins_pipe(pipe_slow); // XXX
10236 %}
10237 
10238 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
10239 %{
10240   match(Set dst (CmpLTMask p q));
10241   effect(KILL cr);
10242 
10243   ins_cost(400);
10244   format %{ "cmpl    $p, $q\t# cmpLTMask\n\t"
10245             "setlt   $dst\n\t"
10246             "movzbl  $dst, $dst\n\t"
10247             "negl    $dst" %}
10248   ins_encode %{
10249     __ cmpl($p$$Register, $q$$Register);
10250     __ setl($dst$$Register);
10251     __ movzbl($dst$$Register, $dst$$Register);
10252     __ negl($dst$$Register);
10253   %}
10254   ins_pipe(pipe_slow);
10255 %}
10256 
10257 instruct cmpLTMask0(rRegI dst, immI_0 zero, rFlagsReg cr)
10258 %{
10259   match(Set dst (CmpLTMask dst zero));
10260   effect(KILL cr);
10261 
10262   ins_cost(100);
10263   format %{ "sarl    $dst, #31\t# cmpLTMask0" %}
10264   ins_encode %{
10265     __ sarl($dst$$Register, 31);
10266   %}
10267   ins_pipe(ialu_reg);
10268 %}
10269 
10270 /* Better to save a register than avoid a branch */
10271 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10272 %{
10273   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
10274   effect(KILL cr);
10275   ins_cost(300);
10276   format %{ "subl    $p,$q\t# cadd_cmpLTMask\n\t"
10277             "jge     done\n\t"
10278             "addl    $p,$y\n"
10279             "done:   " %}
10280   ins_encode %{
10281     Register Rp = $p$$Register;
10282     Register Rq = $q$$Register;
10283     Register Ry = $y$$Register;
10284     Label done;
10285     __ subl(Rp, Rq);
10286     __ jccb(Assembler::greaterEqual, done);
10287     __ addl(Rp, Ry);
10288     __ bind(done);
10289   %}
10290   ins_pipe(pipe_cmplt);
10291 %}
10292 
10293 /* Better to save a register than avoid a branch */
10294 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
10295 %{
10296   match(Set y (AndI (CmpLTMask p q) y));
10297   effect(KILL cr);
10298 
10299   ins_cost(300);
10300 
10301   format %{ "cmpl    $p, $q\t# and_cmpLTMask\n\t"
10302             "jlt     done\n\t"
10303             "xorl    $y, $y\n"
10304             "done:   " %}
10305   ins_encode %{
10306     Register Rp = $p$$Register;
10307     Register Rq = $q$$Register;
10308     Register Ry = $y$$Register;
10309     Label done;
10310     __ cmpl(Rp, Rq);
10311     __ jccb(Assembler::less, done);
10312     __ xorl(Ry, Ry);
10313     __ bind(done);
10314   %}
10315   ins_pipe(pipe_cmplt);
10316 %}
10317 
10318 
10319 //---------- FP Instructions------------------------------------------------
10320 
10321 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
10322 %{
10323   match(Set cr (CmpF src1 src2));
10324 
10325   ins_cost(145);
10326   format %{ "ucomiss $src1, $src2\n\t"
10327             "jnp,s   exit\n\t"
10328             "pushfq\t# saw NaN, set CF\n\t"
10329             "andq    [rsp], #0xffffff2b\n\t"
10330             "popfq\n"
10331     "exit:" %}
10332   ins_encode %{
10333     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10334     emit_cmpfp_fixup(_masm);
10335   %}
10336   ins_pipe(pipe_slow);
10337 %}
10338 
10339 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
10340   match(Set cr (CmpF src1 src2));
10341 
10342   ins_cost(100);
10343   format %{ "ucomiss $src1, $src2" %}
10344   ins_encode %{
10345     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10346   %}
10347   ins_pipe(pipe_slow);
10348 %}
10349 
10350 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
10351 %{
10352   match(Set cr (CmpF src1 (LoadF src2)));
10353 
10354   ins_cost(145);
10355   format %{ "ucomiss $src1, $src2\n\t"
10356             "jnp,s   exit\n\t"
10357             "pushfq\t# saw NaN, set CF\n\t"
10358             "andq    [rsp], #0xffffff2b\n\t"
10359             "popfq\n"
10360     "exit:" %}
10361   ins_encode %{
10362     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10363     emit_cmpfp_fixup(_masm);
10364   %}
10365   ins_pipe(pipe_slow);
10366 %}
10367 
10368 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
10369   match(Set cr (CmpF src1 (LoadF src2)));
10370 
10371   ins_cost(100);
10372   format %{ "ucomiss $src1, $src2" %}
10373   ins_encode %{
10374     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10375   %}
10376   ins_pipe(pipe_slow);
10377 %}
10378 
10379 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
10380   match(Set cr (CmpF src con));
10381 
10382   ins_cost(145);
10383   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10384             "jnp,s   exit\n\t"
10385             "pushfq\t# saw NaN, set CF\n\t"
10386             "andq    [rsp], #0xffffff2b\n\t"
10387             "popfq\n"
10388     "exit:" %}
10389   ins_encode %{
10390     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10391     emit_cmpfp_fixup(_masm);
10392   %}
10393   ins_pipe(pipe_slow);
10394 %}
10395 
10396 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
10397   match(Set cr (CmpF src con));
10398   ins_cost(100);
10399   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
10400   ins_encode %{
10401     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10402   %}
10403   ins_pipe(pipe_slow);
10404 %}
10405 
10406 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
10407 %{
10408   match(Set cr (CmpD src1 src2));
10409 
10410   ins_cost(145);
10411   format %{ "ucomisd $src1, $src2\n\t"
10412             "jnp,s   exit\n\t"
10413             "pushfq\t# saw NaN, set CF\n\t"
10414             "andq    [rsp], #0xffffff2b\n\t"
10415             "popfq\n"
10416     "exit:" %}
10417   ins_encode %{
10418     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10419     emit_cmpfp_fixup(_masm);
10420   %}
10421   ins_pipe(pipe_slow);
10422 %}
10423 
10424 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
10425   match(Set cr (CmpD src1 src2));
10426 
10427   ins_cost(100);
10428   format %{ "ucomisd $src1, $src2 test" %}
10429   ins_encode %{
10430     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10431   %}
10432   ins_pipe(pipe_slow);
10433 %}
10434 
10435 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
10436 %{
10437   match(Set cr (CmpD src1 (LoadD src2)));
10438 
10439   ins_cost(145);
10440   format %{ "ucomisd $src1, $src2\n\t"
10441             "jnp,s   exit\n\t"
10442             "pushfq\t# saw NaN, set CF\n\t"
10443             "andq    [rsp], #0xffffff2b\n\t"
10444             "popfq\n"
10445     "exit:" %}
10446   ins_encode %{
10447     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10448     emit_cmpfp_fixup(_masm);
10449   %}
10450   ins_pipe(pipe_slow);
10451 %}
10452 
10453 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
10454   match(Set cr (CmpD src1 (LoadD src2)));
10455 
10456   ins_cost(100);
10457   format %{ "ucomisd $src1, $src2" %}
10458   ins_encode %{
10459     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10460   %}
10461   ins_pipe(pipe_slow);
10462 %}
10463 
10464 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
10465   match(Set cr (CmpD src con));
10466 
10467   ins_cost(145);
10468   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10469             "jnp,s   exit\n\t"
10470             "pushfq\t# saw NaN, set CF\n\t"
10471             "andq    [rsp], #0xffffff2b\n\t"
10472             "popfq\n"
10473     "exit:" %}
10474   ins_encode %{
10475     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10476     emit_cmpfp_fixup(_masm);
10477   %}
10478   ins_pipe(pipe_slow);
10479 %}
10480 
10481 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
10482   match(Set cr (CmpD src con));
10483   ins_cost(100);
10484   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
10485   ins_encode %{
10486     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10487   %}
10488   ins_pipe(pipe_slow);
10489 %}
10490 
10491 // Compare into -1,0,1
10492 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
10493 %{
10494   match(Set dst (CmpF3 src1 src2));
10495   effect(KILL cr);
10496 
10497   ins_cost(275);
10498   format %{ "ucomiss $src1, $src2\n\t"
10499             "movl    $dst, #-1\n\t"
10500             "jp,s    done\n\t"
10501             "jb,s    done\n\t"
10502             "setne   $dst\n\t"
10503             "movzbl  $dst, $dst\n"
10504     "done:" %}
10505   ins_encode %{
10506     __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
10507     emit_cmpfp3(_masm, $dst$$Register);
10508   %}
10509   ins_pipe(pipe_slow);
10510 %}
10511 
10512 // Compare into -1,0,1
10513 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
10514 %{
10515   match(Set dst (CmpF3 src1 (LoadF src2)));
10516   effect(KILL cr);
10517 
10518   ins_cost(275);
10519   format %{ "ucomiss $src1, $src2\n\t"
10520             "movl    $dst, #-1\n\t"
10521             "jp,s    done\n\t"
10522             "jb,s    done\n\t"
10523             "setne   $dst\n\t"
10524             "movzbl  $dst, $dst\n"
10525     "done:" %}
10526   ins_encode %{
10527     __ ucomiss($src1$$XMMRegister, $src2$$Address);
10528     emit_cmpfp3(_masm, $dst$$Register);
10529   %}
10530   ins_pipe(pipe_slow);
10531 %}
10532 
10533 // Compare into -1,0,1
10534 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
10535   match(Set dst (CmpF3 src con));
10536   effect(KILL cr);
10537 
10538   ins_cost(275);
10539   format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
10540             "movl    $dst, #-1\n\t"
10541             "jp,s    done\n\t"
10542             "jb,s    done\n\t"
10543             "setne   $dst\n\t"
10544             "movzbl  $dst, $dst\n"
10545     "done:" %}
10546   ins_encode %{
10547     __ ucomiss($src$$XMMRegister, $constantaddress($con));
10548     emit_cmpfp3(_masm, $dst$$Register);
10549   %}
10550   ins_pipe(pipe_slow);
10551 %}
10552 
10553 // Compare into -1,0,1
10554 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
10555 %{
10556   match(Set dst (CmpD3 src1 src2));
10557   effect(KILL cr);
10558 
10559   ins_cost(275);
10560   format %{ "ucomisd $src1, $src2\n\t"
10561             "movl    $dst, #-1\n\t"
10562             "jp,s    done\n\t"
10563             "jb,s    done\n\t"
10564             "setne   $dst\n\t"
10565             "movzbl  $dst, $dst\n"
10566     "done:" %}
10567   ins_encode %{
10568     __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
10569     emit_cmpfp3(_masm, $dst$$Register);
10570   %}
10571   ins_pipe(pipe_slow);
10572 %}
10573 
10574 // Compare into -1,0,1
10575 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
10576 %{
10577   match(Set dst (CmpD3 src1 (LoadD src2)));
10578   effect(KILL cr);
10579 
10580   ins_cost(275);
10581   format %{ "ucomisd $src1, $src2\n\t"
10582             "movl    $dst, #-1\n\t"
10583             "jp,s    done\n\t"
10584             "jb,s    done\n\t"
10585             "setne   $dst\n\t"
10586             "movzbl  $dst, $dst\n"
10587     "done:" %}
10588   ins_encode %{
10589     __ ucomisd($src1$$XMMRegister, $src2$$Address);
10590     emit_cmpfp3(_masm, $dst$$Register);
10591   %}
10592   ins_pipe(pipe_slow);
10593 %}
10594 
10595 // Compare into -1,0,1
10596 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
10597   match(Set dst (CmpD3 src con));
10598   effect(KILL cr);
10599 
10600   ins_cost(275);
10601   format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
10602             "movl    $dst, #-1\n\t"
10603             "jp,s    done\n\t"
10604             "jb,s    done\n\t"
10605             "setne   $dst\n\t"
10606             "movzbl  $dst, $dst\n"
10607     "done:" %}
10608   ins_encode %{
10609     __ ucomisd($src$$XMMRegister, $constantaddress($con));
10610     emit_cmpfp3(_masm, $dst$$Register);
10611   %}
10612   ins_pipe(pipe_slow);
10613 %}
10614 
10615 //----------Arithmetic Conversion Instructions---------------------------------
10616 
10617 instruct convF2D_reg_reg(regD dst, regF src)
10618 %{
10619   match(Set dst (ConvF2D src));
10620 
10621   format %{ "cvtss2sd $dst, $src" %}
10622   ins_encode %{
10623     __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
10624   %}
10625   ins_pipe(pipe_slow); // XXX
10626 %}
10627 
10628 instruct convF2D_reg_mem(regD dst, memory src)
10629 %{
10630   match(Set dst (ConvF2D (LoadF src)));
10631 
10632   format %{ "cvtss2sd $dst, $src" %}
10633   ins_encode %{
10634     __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
10635   %}
10636   ins_pipe(pipe_slow); // XXX
10637 %}
10638 
10639 instruct convD2F_reg_reg(regF dst, regD src)
10640 %{
10641   match(Set dst (ConvD2F src));
10642 
10643   format %{ "cvtsd2ss $dst, $src" %}
10644   ins_encode %{
10645     __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
10646   %}
10647   ins_pipe(pipe_slow); // XXX
10648 %}
10649 
10650 instruct convD2F_reg_mem(regF dst, memory src)
10651 %{
10652   match(Set dst (ConvD2F (LoadD src)));
10653 
10654   format %{ "cvtsd2ss $dst, $src" %}
10655   ins_encode %{
10656     __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
10657   %}
10658   ins_pipe(pipe_slow); // XXX
10659 %}
10660 
10661 // XXX do mem variants
10662 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
10663 %{
10664   match(Set dst (ConvF2I src));
10665   effect(KILL cr);
10666   format %{ "convert_f2i $dst,$src" %}
10667   ins_encode %{
10668     __ convert_f2i($dst$$Register, $src$$XMMRegister);
10669   %}
10670   ins_pipe(pipe_slow);
10671 %}
10672 
10673 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10674 %{
10675   match(Set dst (ConvF2L src));
10676   effect(KILL cr);
10677   format %{ "convert_f2l $dst,$src"%}
10678   ins_encode %{
10679     __ convert_f2l($dst$$Register, $src$$XMMRegister);
10680   %}
10681   ins_pipe(pipe_slow);
10682 %}
10683 
10684 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10685 %{
10686   match(Set dst (ConvD2I src));
10687   effect(KILL cr);
10688   format %{ "convert_d2i $dst,$src"%}
10689   ins_encode %{
10690     __ convert_d2i($dst$$Register, $src$$XMMRegister);
10691   %}
10692   ins_pipe(pipe_slow);
10693 %}
10694 
10695 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10696 %{
10697   match(Set dst (ConvD2L src));
10698   effect(KILL cr);
10699   format %{ "convert_d2l $dst,$src"%}
10700   ins_encode %{
10701     __ convert_d2l($dst$$Register, $src$$XMMRegister);
10702   %}
10703   ins_pipe(pipe_slow);
10704 %}
10705 
10706 instruct convI2F_reg_reg(regF dst, rRegI src)
10707 %{
10708   predicate(!UseXmmI2F);
10709   match(Set dst (ConvI2F src));
10710 
10711   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10712   ins_encode %{
10713     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10714   %}
10715   ins_pipe(pipe_slow); // XXX
10716 %}
10717 
10718 instruct convI2F_reg_mem(regF dst, memory src)
10719 %{
10720   match(Set dst (ConvI2F (LoadI src)));
10721 
10722   format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10723   ins_encode %{
10724     __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10725   %}
10726   ins_pipe(pipe_slow); // XXX
10727 %}
10728 
10729 instruct convI2D_reg_reg(regD dst, rRegI src)
10730 %{
10731   predicate(!UseXmmI2D);
10732   match(Set dst (ConvI2D src));
10733 
10734   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10735   ins_encode %{
10736     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10737   %}
10738   ins_pipe(pipe_slow); // XXX
10739 %}
10740 
10741 instruct convI2D_reg_mem(regD dst, memory src)
10742 %{
10743   match(Set dst (ConvI2D (LoadI src)));
10744 
10745   format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10746   ins_encode %{
10747     __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10748   %}
10749   ins_pipe(pipe_slow); // XXX
10750 %}
10751 
10752 instruct convXI2F_reg(regF dst, rRegI src)
10753 %{
10754   predicate(UseXmmI2F);
10755   match(Set dst (ConvI2F src));
10756 
10757   format %{ "movdl $dst, $src\n\t"
10758             "cvtdq2psl $dst, $dst\t# i2f" %}
10759   ins_encode %{
10760     __ movdl($dst$$XMMRegister, $src$$Register);
10761     __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10762   %}
10763   ins_pipe(pipe_slow); // XXX
10764 %}
10765 
10766 instruct convXI2D_reg(regD dst, rRegI src)
10767 %{
10768   predicate(UseXmmI2D);
10769   match(Set dst (ConvI2D src));
10770 
10771   format %{ "movdl $dst, $src\n\t"
10772             "cvtdq2pdl $dst, $dst\t# i2d" %}
10773   ins_encode %{
10774     __ movdl($dst$$XMMRegister, $src$$Register);
10775     __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10776   %}
10777   ins_pipe(pipe_slow); // XXX
10778 %}
10779 
10780 instruct convL2F_reg_reg(regF dst, rRegL src)
10781 %{
10782   match(Set dst (ConvL2F src));
10783 
10784   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10785   ins_encode %{
10786     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10787   %}
10788   ins_pipe(pipe_slow); // XXX
10789 %}
10790 
10791 instruct convL2F_reg_mem(regF dst, memory src)
10792 %{
10793   match(Set dst (ConvL2F (LoadL src)));
10794 
10795   format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10796   ins_encode %{
10797     __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10798   %}
10799   ins_pipe(pipe_slow); // XXX
10800 %}
10801 
10802 instruct convL2D_reg_reg(regD dst, rRegL src)
10803 %{
10804   match(Set dst (ConvL2D src));
10805 
10806   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10807   ins_encode %{
10808     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10809   %}
10810   ins_pipe(pipe_slow); // XXX
10811 %}
10812 
10813 instruct convL2D_reg_mem(regD dst, memory src)
10814 %{
10815   match(Set dst (ConvL2D (LoadL src)));
10816 
10817   format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10818   ins_encode %{
10819     __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10820   %}
10821   ins_pipe(pipe_slow); // XXX
10822 %}
10823 
10824 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10825 %{
10826   match(Set dst (ConvI2L src));
10827 
10828   ins_cost(125);
10829   format %{ "movslq  $dst, $src\t# i2l" %}
10830   ins_encode %{
10831     __ movslq($dst$$Register, $src$$Register);
10832   %}
10833   ins_pipe(ialu_reg_reg);
10834 %}
10835 
10836 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10837 // %{
10838 //   match(Set dst (ConvI2L src));
10839 // //   predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10840 // //             _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10841 //   predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10842 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10843 //             ((const TypeNode*) n)->type()->is_long()->_lo ==
10844 //             (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10845 
10846 //   format %{ "movl    $dst, $src\t# unsigned i2l" %}
10847 //   ins_encode(enc_copy(dst, src));
10848 // //   opcode(0x63); // needs REX.W
10849 // //   ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10850 //   ins_pipe(ialu_reg_reg);
10851 // %}
10852 
10853 // Zero-extend convert int to long
10854 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10855 %{
10856   match(Set dst (AndL (ConvI2L src) mask));
10857 
10858   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10859   ins_encode %{
10860     if ($dst$$reg != $src$$reg) {
10861       __ movl($dst$$Register, $src$$Register);
10862     }
10863   %}
10864   ins_pipe(ialu_reg_reg);
10865 %}
10866 
10867 // Zero-extend convert int to long
10868 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10869 %{
10870   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10871 
10872   format %{ "movl    $dst, $src\t# i2l zero-extend\n\t" %}
10873   ins_encode %{
10874     __ movl($dst$$Register, $src$$Address);
10875   %}
10876   ins_pipe(ialu_reg_mem);
10877 %}
10878 
10879 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10880 %{
10881   match(Set dst (AndL src mask));
10882 
10883   format %{ "movl    $dst, $src\t# zero-extend long" %}
10884   ins_encode %{
10885     __ movl($dst$$Register, $src$$Register);
10886   %}
10887   ins_pipe(ialu_reg_reg);
10888 %}
10889 
10890 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10891 %{
10892   match(Set dst (ConvL2I src));
10893 
10894   format %{ "movl    $dst, $src\t# l2i" %}
10895   ins_encode %{
10896     __ movl($dst$$Register, $src$$Register);
10897   %}
10898   ins_pipe(ialu_reg_reg);
10899 %}
10900 
10901 
10902 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10903   match(Set dst (MoveF2I src));
10904   effect(DEF dst, USE src);
10905 
10906   ins_cost(125);
10907   format %{ "movl    $dst, $src\t# MoveF2I_stack_reg" %}
10908   ins_encode %{
10909     __ movl($dst$$Register, Address(rsp, $src$$disp));
10910   %}
10911   ins_pipe(ialu_reg_mem);
10912 %}
10913 
10914 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10915   match(Set dst (MoveI2F src));
10916   effect(DEF dst, USE src);
10917 
10918   ins_cost(125);
10919   format %{ "movss   $dst, $src\t# MoveI2F_stack_reg" %}
10920   ins_encode %{
10921     __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10922   %}
10923   ins_pipe(pipe_slow);
10924 %}
10925 
10926 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10927   match(Set dst (MoveD2L src));
10928   effect(DEF dst, USE src);
10929 
10930   ins_cost(125);
10931   format %{ "movq    $dst, $src\t# MoveD2L_stack_reg" %}
10932   ins_encode %{
10933     __ movq($dst$$Register, Address(rsp, $src$$disp));
10934   %}
10935   ins_pipe(ialu_reg_mem);
10936 %}
10937 
10938 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10939   predicate(!UseXmmLoadAndClearUpper);
10940   match(Set dst (MoveL2D src));
10941   effect(DEF dst, USE src);
10942 
10943   ins_cost(125);
10944   format %{ "movlpd  $dst, $src\t# MoveL2D_stack_reg" %}
10945   ins_encode %{
10946     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10947   %}
10948   ins_pipe(pipe_slow);
10949 %}
10950 
10951 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10952   predicate(UseXmmLoadAndClearUpper);
10953   match(Set dst (MoveL2D src));
10954   effect(DEF dst, USE src);
10955 
10956   ins_cost(125);
10957   format %{ "movsd   $dst, $src\t# MoveL2D_stack_reg" %}
10958   ins_encode %{
10959     __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10960   %}
10961   ins_pipe(pipe_slow);
10962 %}
10963 
10964 
10965 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10966   match(Set dst (MoveF2I src));
10967   effect(DEF dst, USE src);
10968 
10969   ins_cost(95); // XXX
10970   format %{ "movss   $dst, $src\t# MoveF2I_reg_stack" %}
10971   ins_encode %{
10972     __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10973   %}
10974   ins_pipe(pipe_slow);
10975 %}
10976 
10977 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10978   match(Set dst (MoveI2F src));
10979   effect(DEF dst, USE src);
10980 
10981   ins_cost(100);
10982   format %{ "movl    $dst, $src\t# MoveI2F_reg_stack" %}
10983   ins_encode %{
10984     __ movl(Address(rsp, $dst$$disp), $src$$Register);
10985   %}
10986   ins_pipe( ialu_mem_reg );
10987 %}
10988 
10989 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10990   match(Set dst (MoveD2L src));
10991   effect(DEF dst, USE src);
10992 
10993   ins_cost(95); // XXX
10994   format %{ "movsd   $dst, $src\t# MoveL2D_reg_stack" %}
10995   ins_encode %{
10996     __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10997   %}
10998   ins_pipe(pipe_slow);
10999 %}
11000 
11001 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
11002   match(Set dst (MoveL2D src));
11003   effect(DEF dst, USE src);
11004 
11005   ins_cost(100);
11006   format %{ "movq    $dst, $src\t# MoveL2D_reg_stack" %}
11007   ins_encode %{
11008     __ movq(Address(rsp, $dst$$disp), $src$$Register);
11009   %}
11010   ins_pipe(ialu_mem_reg);
11011 %}
11012 
11013 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
11014   match(Set dst (MoveF2I src));
11015   effect(DEF dst, USE src);
11016   ins_cost(85);
11017   format %{ "movd    $dst,$src\t# MoveF2I" %}
11018   ins_encode %{
11019     __ movdl($dst$$Register, $src$$XMMRegister);
11020   %}
11021   ins_pipe( pipe_slow );
11022 %}
11023 
11024 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
11025   match(Set dst (MoveD2L src));
11026   effect(DEF dst, USE src);
11027   ins_cost(85);
11028   format %{ "movd    $dst,$src\t# MoveD2L" %}
11029   ins_encode %{
11030     __ movdq($dst$$Register, $src$$XMMRegister);
11031   %}
11032   ins_pipe( pipe_slow );
11033 %}
11034 
11035 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
11036   match(Set dst (MoveI2F src));
11037   effect(DEF dst, USE src);
11038   ins_cost(100);
11039   format %{ "movd    $dst,$src\t# MoveI2F" %}
11040   ins_encode %{
11041     __ movdl($dst$$XMMRegister, $src$$Register);
11042   %}
11043   ins_pipe( pipe_slow );
11044 %}
11045 
11046 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
11047   match(Set dst (MoveL2D src));
11048   effect(DEF dst, USE src);
11049   ins_cost(100);
11050   format %{ "movd    $dst,$src\t# MoveL2D" %}
11051   ins_encode %{
11052      __ movdq($dst$$XMMRegister, $src$$Register);
11053   %}
11054   ins_pipe( pipe_slow );
11055 %}
11056 
11057 // Fast clearing of an array
11058 // Small ClearArray non-AVX512.
11059 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11060                   Universe dummy, rFlagsReg cr)
11061 %{
11062   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX <= 2));
11063   match(Set dummy (ClearArray cnt base));
11064   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11065 
11066   format %{ $$template
11067     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11068     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
11069     $$emit$$"jg      LARGE\n\t"
11070     $$emit$$"dec     rcx\n\t"
11071     $$emit$$"js      DONE\t# Zero length\n\t"
11072     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
11073     $$emit$$"dec     rcx\n\t"
11074     $$emit$$"jge     LOOP\n\t"
11075     $$emit$$"jmp     DONE\n\t"
11076     $$emit$$"# LARGE:\n\t"
11077     if (UseFastStosb) {
11078        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11079        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
11080     } else if (UseXMMForObjInit) {
11081        $$emit$$"mov     rdi,rax\n\t"
11082        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11083        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11084        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11085        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11086        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11087        $$emit$$"add     0x40,rax\n\t"
11088        $$emit$$"# L_zero_64_bytes:\n\t"
11089        $$emit$$"sub     0x8,rcx\n\t"
11090        $$emit$$"jge     L_loop\n\t"
11091        $$emit$$"add     0x4,rcx\n\t"
11092        $$emit$$"jl      L_tail\n\t"
11093        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11094        $$emit$$"add     0x20,rax\n\t"
11095        $$emit$$"sub     0x4,rcx\n\t"
11096        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11097        $$emit$$"add     0x4,rcx\n\t"
11098        $$emit$$"jle     L_end\n\t"
11099        $$emit$$"dec     rcx\n\t"
11100        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11101        $$emit$$"vmovq   xmm0,(rax)\n\t"
11102        $$emit$$"add     0x8,rax\n\t"
11103        $$emit$$"dec     rcx\n\t"
11104        $$emit$$"jge     L_sloop\n\t"
11105        $$emit$$"# L_end:\n\t"
11106     } else {
11107        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11108     }
11109     $$emit$$"# DONE"
11110   %}
11111   ins_encode %{
11112     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11113                  $tmp$$XMMRegister, false, knoreg);
11114   %}
11115   ins_pipe(pipe_slow);
11116 %}
11117 
11118 // Small ClearArray AVX512 non-constant length.
11119 instruct rep_stos_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11120                        Universe dummy, rFlagsReg cr)
11121 %{
11122   predicate(!((ClearArrayNode*)n)->is_large() && (UseAVX > 2));
11123   match(Set dummy (ClearArray cnt base));
11124   ins_cost(125);
11125   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11126 
11127   format %{ $$template
11128     $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11129     $$emit$$"cmp     InitArrayShortSize,rcx\n\t"
11130     $$emit$$"jg      LARGE\n\t"
11131     $$emit$$"dec     rcx\n\t"
11132     $$emit$$"js      DONE\t# Zero length\n\t"
11133     $$emit$$"mov     rax,(rdi,rcx,8)\t# LOOP\n\t"
11134     $$emit$$"dec     rcx\n\t"
11135     $$emit$$"jge     LOOP\n\t"
11136     $$emit$$"jmp     DONE\n\t"
11137     $$emit$$"# LARGE:\n\t"
11138     if (UseFastStosb) {
11139        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11140        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--\n\t"
11141     } else if (UseXMMForObjInit) {
11142        $$emit$$"mov     rdi,rax\n\t"
11143        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11144        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11145        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11146        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11147        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11148        $$emit$$"add     0x40,rax\n\t"
11149        $$emit$$"# L_zero_64_bytes:\n\t"
11150        $$emit$$"sub     0x8,rcx\n\t"
11151        $$emit$$"jge     L_loop\n\t"
11152        $$emit$$"add     0x4,rcx\n\t"
11153        $$emit$$"jl      L_tail\n\t"
11154        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11155        $$emit$$"add     0x20,rax\n\t"
11156        $$emit$$"sub     0x4,rcx\n\t"
11157        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11158        $$emit$$"add     0x4,rcx\n\t"
11159        $$emit$$"jle     L_end\n\t"
11160        $$emit$$"dec     rcx\n\t"
11161        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11162        $$emit$$"vmovq   xmm0,(rax)\n\t"
11163        $$emit$$"add     0x8,rax\n\t"
11164        $$emit$$"dec     rcx\n\t"
11165        $$emit$$"jge     L_sloop\n\t"
11166        $$emit$$"# L_end:\n\t"
11167     } else {
11168        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--\n\t"
11169     }
11170     $$emit$$"# DONE"
11171   %}
11172   ins_encode %{
11173     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11174                  $tmp$$XMMRegister, false, $ktmp$$KRegister);
11175   %}
11176   ins_pipe(pipe_slow);
11177 %}
11178 
11179 // Large ClearArray non-AVX512.
11180 instruct rep_stos_large(rcx_RegL cnt, rdi_RegP base, regD tmp, rax_RegI zero,
11181                         Universe dummy, rFlagsReg cr)
11182 %{
11183   predicate((UseAVX <=2) && ((ClearArrayNode*)n)->is_large());
11184   match(Set dummy (ClearArray cnt base));
11185   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, KILL zero, KILL cr);
11186 
11187   format %{ $$template
11188     if (UseFastStosb) {
11189        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11190        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11191        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11192     } else if (UseXMMForObjInit) {
11193        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11194        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11195        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11196        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11197        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11198        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11199        $$emit$$"add     0x40,rax\n\t"
11200        $$emit$$"# L_zero_64_bytes:\n\t"
11201        $$emit$$"sub     0x8,rcx\n\t"
11202        $$emit$$"jge     L_loop\n\t"
11203        $$emit$$"add     0x4,rcx\n\t"
11204        $$emit$$"jl      L_tail\n\t"
11205        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11206        $$emit$$"add     0x20,rax\n\t"
11207        $$emit$$"sub     0x4,rcx\n\t"
11208        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11209        $$emit$$"add     0x4,rcx\n\t"
11210        $$emit$$"jle     L_end\n\t"
11211        $$emit$$"dec     rcx\n\t"
11212        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11213        $$emit$$"vmovq   xmm0,(rax)\n\t"
11214        $$emit$$"add     0x8,rax\n\t"
11215        $$emit$$"dec     rcx\n\t"
11216        $$emit$$"jge     L_sloop\n\t"
11217        $$emit$$"# L_end:\n\t"
11218     } else {
11219        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11220        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11221     }
11222   %}
11223   ins_encode %{
11224     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11225                  $tmp$$XMMRegister, true, knoreg);
11226   %}
11227   ins_pipe(pipe_slow);
11228 %}
11229 
11230 // Large ClearArray AVX512.
11231 instruct rep_stos_large_evex(rcx_RegL cnt, rdi_RegP base, legRegD tmp, kReg ktmp, rax_RegI zero,
11232                              Universe dummy, rFlagsReg cr)
11233 %{
11234   predicate((UseAVX > 2) && ((ClearArrayNode*)n)->is_large());
11235   match(Set dummy (ClearArray cnt base));
11236   effect(USE_KILL cnt, USE_KILL base, TEMP tmp, TEMP ktmp, KILL zero, KILL cr);
11237 
11238   format %{ $$template
11239     if (UseFastStosb) {
11240        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11241        $$emit$$"shlq    rcx,3\t# Convert doublewords to bytes\n\t"
11242        $$emit$$"rep     stosb\t# Store rax to *rdi++ while rcx--"
11243     } else if (UseXMMForObjInit) {
11244        $$emit$$"mov     rdi,rax\t# ClearArray:\n\t"
11245        $$emit$$"vpxor   ymm0,ymm0,ymm0\n\t"
11246        $$emit$$"jmpq    L_zero_64_bytes\n\t"
11247        $$emit$$"# L_loop:\t# 64-byte LOOP\n\t"
11248        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11249        $$emit$$"vmovdqu ymm0,0x20(rax)\n\t"
11250        $$emit$$"add     0x40,rax\n\t"
11251        $$emit$$"# L_zero_64_bytes:\n\t"
11252        $$emit$$"sub     0x8,rcx\n\t"
11253        $$emit$$"jge     L_loop\n\t"
11254        $$emit$$"add     0x4,rcx\n\t"
11255        $$emit$$"jl      L_tail\n\t"
11256        $$emit$$"vmovdqu ymm0,(rax)\n\t"
11257        $$emit$$"add     0x20,rax\n\t"
11258        $$emit$$"sub     0x4,rcx\n\t"
11259        $$emit$$"# L_tail:\t# Clearing tail bytes\n\t"
11260        $$emit$$"add     0x4,rcx\n\t"
11261        $$emit$$"jle     L_end\n\t"
11262        $$emit$$"dec     rcx\n\t"
11263        $$emit$$"# L_sloop:\t# 8-byte short loop\n\t"
11264        $$emit$$"vmovq   xmm0,(rax)\n\t"
11265        $$emit$$"add     0x8,rax\n\t"
11266        $$emit$$"dec     rcx\n\t"
11267        $$emit$$"jge     L_sloop\n\t"
11268        $$emit$$"# L_end:\n\t"
11269     } else {
11270        $$emit$$"xorq    rax, rax\t# ClearArray:\n\t"
11271        $$emit$$"rep     stosq\t# Store rax to *rdi++ while rcx--"
11272     }
11273   %}
11274   ins_encode %{
11275     __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register,
11276                  $tmp$$XMMRegister, true, $ktmp$$KRegister);
11277   %}
11278   ins_pipe(pipe_slow);
11279 %}
11280 
11281 // Small ClearArray AVX512 constant length.
11282 instruct rep_stos_im(immL cnt, rRegP base, regD tmp, rRegI zero, kReg ktmp, Universe dummy, rFlagsReg cr)
11283 %{
11284   predicate(!((ClearArrayNode*)n)->is_large() &&
11285               ((UseAVX > 2) && VM_Version::supports_avx512vlbw()));
11286   match(Set dummy (ClearArray cnt base));
11287   ins_cost(100);
11288   effect(TEMP tmp, TEMP zero, TEMP ktmp, KILL cr);
11289   format %{ "clear_mem_imm $base , $cnt  \n\t" %}
11290   ins_encode %{
11291    __ clear_mem($base$$Register, $cnt$$constant, $zero$$Register, $tmp$$XMMRegister, $ktmp$$KRegister);
11292   %}
11293   ins_pipe(pipe_slow);
11294 %}
11295 
11296 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11297                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11298 %{
11299   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11300   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11301   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11302 
11303   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11304   ins_encode %{
11305     __ string_compare($str1$$Register, $str2$$Register,
11306                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11307                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, knoreg);
11308   %}
11309   ins_pipe( pipe_slow );
11310 %}
11311 
11312 instruct string_compareL_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11313                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11314 %{
11315   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
11316   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11317   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11318 
11319   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11320   ins_encode %{
11321     __ string_compare($str1$$Register, $str2$$Register,
11322                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11323                       $tmp1$$XMMRegister, StrIntrinsicNode::LL, $ktmp$$KRegister);
11324   %}
11325   ins_pipe( pipe_slow );
11326 %}
11327 
11328 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11329                          rax_RegI result, legRegD tmp1, rFlagsReg cr)
11330 %{
11331   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11332   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11333   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11334 
11335   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11336   ins_encode %{
11337     __ string_compare($str1$$Register, $str2$$Register,
11338                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11339                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, knoreg);
11340   %}
11341   ins_pipe( pipe_slow );
11342 %}
11343 
11344 instruct string_compareU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11345                               rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11346 %{
11347   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
11348   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11349   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11350 
11351   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11352   ins_encode %{
11353     __ string_compare($str1$$Register, $str2$$Register,
11354                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11355                       $tmp1$$XMMRegister, StrIntrinsicNode::UU, $ktmp$$KRegister);
11356   %}
11357   ins_pipe( pipe_slow );
11358 %}
11359 
11360 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11361                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11362 %{
11363   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11364   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11365   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11366 
11367   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11368   ins_encode %{
11369     __ string_compare($str1$$Register, $str2$$Register,
11370                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11371                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, knoreg);
11372   %}
11373   ins_pipe( pipe_slow );
11374 %}
11375 
11376 instruct string_compareLU_evex(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
11377                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11378 %{
11379   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
11380   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11381   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11382 
11383   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11384   ins_encode %{
11385     __ string_compare($str1$$Register, $str2$$Register,
11386                       $cnt1$$Register, $cnt2$$Register, $result$$Register,
11387                       $tmp1$$XMMRegister, StrIntrinsicNode::LU, $ktmp$$KRegister);
11388   %}
11389   ins_pipe( pipe_slow );
11390 %}
11391 
11392 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11393                           rax_RegI result, legRegD tmp1, rFlagsReg cr)
11394 %{
11395   predicate(!VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11396   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11397   effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11398 
11399   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11400   ins_encode %{
11401     __ string_compare($str2$$Register, $str1$$Register,
11402                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11403                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, knoreg);
11404   %}
11405   ins_pipe( pipe_slow );
11406 %}
11407 
11408 instruct string_compareUL_evex(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
11409                                rax_RegI result, legRegD tmp1, kReg ktmp, rFlagsReg cr)
11410 %{
11411   predicate(VM_Version::supports_avx512vlbw() && ((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
11412   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
11413   effect(TEMP tmp1, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
11414 
11415   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1" %}
11416   ins_encode %{
11417     __ string_compare($str2$$Register, $str1$$Register,
11418                       $cnt2$$Register, $cnt1$$Register, $result$$Register,
11419                       $tmp1$$XMMRegister, StrIntrinsicNode::UL, $ktmp$$KRegister);
11420   %}
11421   ins_pipe( pipe_slow );
11422 %}
11423 
11424 // fast search of substring with known size.
11425 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11426                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11427 %{
11428   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11429   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11430   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11431 
11432   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11433   ins_encode %{
11434     int icnt2 = (int)$int_cnt2$$constant;
11435     if (icnt2 >= 16) {
11436       // IndexOf for constant substrings with size >= 16 elements
11437       // which don't need to be loaded through stack.
11438       __ string_indexofC8($str1$$Register, $str2$$Register,
11439                           $cnt1$$Register, $cnt2$$Register,
11440                           icnt2, $result$$Register,
11441                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11442     } else {
11443       // Small strings are loaded through stack if they cross page boundary.
11444       __ string_indexof($str1$$Register, $str2$$Register,
11445                         $cnt1$$Register, $cnt2$$Register,
11446                         icnt2, $result$$Register,
11447                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11448     }
11449   %}
11450   ins_pipe( pipe_slow );
11451 %}
11452 
11453 // fast search of substring with known size.
11454 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11455                              rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11456 %{
11457   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11458   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11459   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11460 
11461   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11462   ins_encode %{
11463     int icnt2 = (int)$int_cnt2$$constant;
11464     if (icnt2 >= 8) {
11465       // IndexOf for constant substrings with size >= 8 elements
11466       // which don't need to be loaded through stack.
11467       __ string_indexofC8($str1$$Register, $str2$$Register,
11468                           $cnt1$$Register, $cnt2$$Register,
11469                           icnt2, $result$$Register,
11470                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11471     } else {
11472       // Small strings are loaded through stack if they cross page boundary.
11473       __ string_indexof($str1$$Register, $str2$$Register,
11474                         $cnt1$$Register, $cnt2$$Register,
11475                         icnt2, $result$$Register,
11476                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11477     }
11478   %}
11479   ins_pipe( pipe_slow );
11480 %}
11481 
11482 // fast search of substring with known size.
11483 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
11484                               rbx_RegI result, legRegD tmp_vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
11485 %{
11486   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11487   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
11488   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
11489 
11490   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result   // KILL $tmp_vec, $cnt1, $cnt2, $tmp" %}
11491   ins_encode %{
11492     int icnt2 = (int)$int_cnt2$$constant;
11493     if (icnt2 >= 8) {
11494       // IndexOf for constant substrings with size >= 8 elements
11495       // which don't need to be loaded through stack.
11496       __ string_indexofC8($str1$$Register, $str2$$Register,
11497                           $cnt1$$Register, $cnt2$$Register,
11498                           icnt2, $result$$Register,
11499                           $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11500     } else {
11501       // Small strings are loaded through stack if they cross page boundary.
11502       __ string_indexof($str1$$Register, $str2$$Register,
11503                         $cnt1$$Register, $cnt2$$Register,
11504                         icnt2, $result$$Register,
11505                         $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11506     }
11507   %}
11508   ins_pipe( pipe_slow );
11509 %}
11510 
11511 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11512                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11513 %{
11514   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
11515   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11516   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11517 
11518   format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11519   ins_encode %{
11520     __ string_indexof($str1$$Register, $str2$$Register,
11521                       $cnt1$$Register, $cnt2$$Register,
11522                       (-1), $result$$Register,
11523                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
11524   %}
11525   ins_pipe( pipe_slow );
11526 %}
11527 
11528 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11529                          rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11530 %{
11531   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
11532   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11533   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11534 
11535   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11536   ins_encode %{
11537     __ string_indexof($str1$$Register, $str2$$Register,
11538                       $cnt1$$Register, $cnt2$$Register,
11539                       (-1), $result$$Register,
11540                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
11541   %}
11542   ins_pipe( pipe_slow );
11543 %}
11544 
11545 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
11546                           rbx_RegI result, legRegD tmp_vec, rcx_RegI tmp, rFlagsReg cr)
11547 %{
11548   predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
11549   match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
11550   effect(TEMP tmp_vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
11551 
11552   format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL all" %}
11553   ins_encode %{
11554     __ string_indexof($str1$$Register, $str2$$Register,
11555                       $cnt1$$Register, $cnt2$$Register,
11556                       (-1), $result$$Register,
11557                       $tmp_vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
11558   %}
11559   ins_pipe( pipe_slow );
11560 %}
11561 
11562 instruct string_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11563                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11564 %{
11565   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U));
11566   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11567   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11568   format %{ "StringUTF16 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11569   ins_encode %{
11570     __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11571                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11572   %}
11573   ins_pipe( pipe_slow );
11574 %}
11575 
11576 instruct stringL_indexof_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
11577                               rbx_RegI result, legRegD tmp_vec1, legRegD tmp_vec2, legRegD tmp_vec3, rcx_RegI tmp, rFlagsReg cr)
11578 %{
11579   predicate(UseSSE42Intrinsics && (((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L));
11580   match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
11581   effect(TEMP tmp_vec1, TEMP tmp_vec2, TEMP tmp_vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
11582   format %{ "StringLatin1 IndexOf char[] $str1,$cnt1,$ch -> $result   // KILL all" %}
11583   ins_encode %{
11584     __ stringL_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
11585                            $tmp_vec1$$XMMRegister, $tmp_vec2$$XMMRegister, $tmp_vec3$$XMMRegister, $tmp$$Register);
11586   %}
11587   ins_pipe( pipe_slow );
11588 %}
11589 
11590 // fast string equals
11591 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11592                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr)
11593 %{
11594   predicate(!VM_Version::supports_avx512vlbw());
11595   match(Set result (StrEquals (Binary str1 str2) cnt));
11596   effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11597 
11598   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11599   ins_encode %{
11600     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11601                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11602                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11603   %}
11604   ins_pipe( pipe_slow );
11605 %}
11606 
11607 instruct string_equals_evex(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
11608                            legRegD tmp1, legRegD tmp2, kReg ktmp, rbx_RegI tmp3, rFlagsReg cr)
11609 %{
11610   predicate(VM_Version::supports_avx512vlbw());
11611   match(Set result (StrEquals (Binary str1 str2) cnt));
11612   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
11613 
11614   format %{ "String Equals $str1,$str2,$cnt -> $result    // KILL $tmp1, $tmp2, $tmp3" %}
11615   ins_encode %{
11616     __ arrays_equals(false, $str1$$Register, $str2$$Register,
11617                      $cnt$$Register, $result$$Register, $tmp3$$Register,
11618                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11619   %}
11620   ins_pipe( pipe_slow );
11621 %}
11622 
11623 // fast array equals
11624 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11625                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11626 %{
11627   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11628   match(Set result (AryEq ary1 ary2));
11629   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11630 
11631   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11632   ins_encode %{
11633     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11634                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11635                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, knoreg);
11636   %}
11637   ins_pipe( pipe_slow );
11638 %}
11639 
11640 instruct array_equalsB_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11641                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11642 %{
11643   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
11644   match(Set result (AryEq ary1 ary2));
11645   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11646 
11647   format %{ "Array Equals byte[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11648   ins_encode %{
11649     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11650                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11651                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */, $ktmp$$KRegister);
11652   %}
11653   ins_pipe( pipe_slow );
11654 %}
11655 
11656 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11657                        legRegD tmp1, legRegD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11658 %{
11659   predicate(!VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11660   match(Set result (AryEq ary1 ary2));
11661   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11662 
11663   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11664   ins_encode %{
11665     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11666                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11667                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, knoreg);
11668   %}
11669   ins_pipe( pipe_slow );
11670 %}
11671 
11672 instruct array_equalsC_evex(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
11673                             legRegD tmp1, legRegD tmp2, kReg ktmp, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
11674 %{
11675   predicate(VM_Version::supports_avx512vlbw() && ((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
11676   match(Set result (AryEq ary1 ary2));
11677   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
11678 
11679   format %{ "Array Equals char[] $ary1,$ary2 -> $result   // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
11680   ins_encode %{
11681     __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
11682                      $tmp3$$Register, $result$$Register, $tmp4$$Register,
11683                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */, $ktmp$$KRegister);
11684   %}
11685   ins_pipe( pipe_slow );
11686 %}
11687 
11688 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11689                        legRegD tmp1, legRegD tmp2, rbx_RegI tmp3, rFlagsReg cr,)
11690 %{
11691   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11692   match(Set result (HasNegatives ary1 len));
11693   effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11694 
11695   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11696   ins_encode %{
11697     __ has_negatives($ary1$$Register, $len$$Register,
11698                      $result$$Register, $tmp3$$Register,
11699                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, knoreg, knoreg);
11700   %}
11701   ins_pipe( pipe_slow );
11702 %}
11703 
11704 instruct has_negatives_evex(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
11705                             legRegD tmp1, legRegD tmp2, kReg ktmp1, kReg ktmp2, rbx_RegI tmp3, rFlagsReg cr,)
11706 %{
11707   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11708   match(Set result (HasNegatives ary1 len));
11709   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp1, TEMP ktmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
11710 
11711   format %{ "has negatives byte[] $ary1,$len -> $result   // KILL $tmp1, $tmp2, $tmp3" %}
11712   ins_encode %{
11713     __ has_negatives($ary1$$Register, $len$$Register,
11714                      $result$$Register, $tmp3$$Register,
11715                      $tmp1$$XMMRegister, $tmp2$$XMMRegister, $ktmp1$$KRegister, $ktmp2$$KRegister);
11716   %}
11717   ins_pipe( pipe_slow );
11718 %}
11719 
11720 // fast char[] to byte[] compression
11721 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11722                          legRegD tmp4, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11723   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11724   match(Set result (StrCompressedCopy src (Binary dst len)));
11725   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst,
11726          USE_KILL len, KILL tmp5, KILL cr);
11727 
11728   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11729   ins_encode %{
11730     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11731                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11732                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11733                            knoreg, knoreg);
11734   %}
11735   ins_pipe( pipe_slow );
11736 %}
11737 
11738 instruct string_compress_evex(rsi_RegP src, rdi_RegP dst, rdx_RegI len, legRegD tmp1, legRegD tmp2, legRegD tmp3,
11739                               legRegD tmp4, kReg ktmp1, kReg ktmp2, rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11740   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11741   match(Set result (StrCompressedCopy src (Binary dst len)));
11742   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ktmp1, TEMP ktmp2, USE_KILL src, USE_KILL dst,
11743          USE_KILL len, KILL tmp5, KILL cr);
11744 
11745   format %{ "String Compress $src,$dst -> $result    // KILL RAX, RCX, RDX" %}
11746   ins_encode %{
11747     __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
11748                            $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11749                            $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register,
11750                            $ktmp1$$KRegister, $ktmp2$$KRegister);
11751   %}
11752   ins_pipe( pipe_slow );
11753 %}
11754 // fast byte[] to char[] inflation
11755 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11756                         legRegD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
11757   predicate(!VM_Version::supports_avx512vlbw() || !VM_Version::supports_bmi2());
11758   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11759   effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11760 
11761   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11762   ins_encode %{
11763     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11764                           $tmp1$$XMMRegister, $tmp2$$Register, knoreg);
11765   %}
11766   ins_pipe( pipe_slow );
11767 %}
11768 
11769 instruct string_inflate_evex(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11770                              legRegD tmp1, kReg ktmp, rcx_RegI tmp2, rFlagsReg cr) %{
11771   predicate(VM_Version::supports_avx512vlbw() && VM_Version::supports_bmi2());
11772   match(Set dummy (StrInflatedCopy src (Binary dst len)));
11773   effect(TEMP tmp1, TEMP tmp2, TEMP ktmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
11774 
11775   format %{ "String Inflate $src,$dst    // KILL $tmp1, $tmp2" %}
11776   ins_encode %{
11777     __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
11778                           $tmp1$$XMMRegister, $tmp2$$Register, $ktmp$$KRegister);
11779   %}
11780   ins_pipe( pipe_slow );
11781 %}
11782 
11783 // encode char[] to byte[] in ISO_8859_1
11784 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11785                           legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11786                           rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11787   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
11788   match(Set result (EncodeISOArray src (Binary dst len)));
11789   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11790 
11791   format %{ "Encode iso array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11792   ins_encode %{
11793     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11794                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11795                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, false);
11796   %}
11797   ins_pipe( pipe_slow );
11798 %}
11799 
11800 // encode char[] to byte[] in ASCII
11801 instruct encode_ascii_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
11802                             legRegD tmp1, legRegD tmp2, legRegD tmp3, legRegD tmp4,
11803                             rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
11804   predicate(((EncodeISOArrayNode*)n)->is_ascii());
11805   match(Set result (EncodeISOArray src (Binary dst len)));
11806   effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
11807 
11808   format %{ "Encode ascii array $src,$dst,$len -> $result    // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
11809   ins_encode %{
11810     __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
11811                         $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
11812                         $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register, true);
11813   %}
11814   ins_pipe( pipe_slow );
11815 %}
11816 
11817 //----------Overflow Math Instructions-----------------------------------------
11818 
11819 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11820 %{
11821   match(Set cr (OverflowAddI op1 op2));
11822   effect(DEF cr, USE_KILL op1, USE op2);
11823 
11824   format %{ "addl    $op1, $op2\t# overflow check int" %}
11825 
11826   ins_encode %{
11827     __ addl($op1$$Register, $op2$$Register);
11828   %}
11829   ins_pipe(ialu_reg_reg);
11830 %}
11831 
11832 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
11833 %{
11834   match(Set cr (OverflowAddI op1 op2));
11835   effect(DEF cr, USE_KILL op1, USE op2);
11836 
11837   format %{ "addl    $op1, $op2\t# overflow check int" %}
11838 
11839   ins_encode %{
11840     __ addl($op1$$Register, $op2$$constant);
11841   %}
11842   ins_pipe(ialu_reg_reg);
11843 %}
11844 
11845 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11846 %{
11847   match(Set cr (OverflowAddL op1 op2));
11848   effect(DEF cr, USE_KILL op1, USE op2);
11849 
11850   format %{ "addq    $op1, $op2\t# overflow check long" %}
11851   ins_encode %{
11852     __ addq($op1$$Register, $op2$$Register);
11853   %}
11854   ins_pipe(ialu_reg_reg);
11855 %}
11856 
11857 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
11858 %{
11859   match(Set cr (OverflowAddL op1 op2));
11860   effect(DEF cr, USE_KILL op1, USE op2);
11861 
11862   format %{ "addq    $op1, $op2\t# overflow check long" %}
11863   ins_encode %{
11864     __ addq($op1$$Register, $op2$$constant);
11865   %}
11866   ins_pipe(ialu_reg_reg);
11867 %}
11868 
11869 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11870 %{
11871   match(Set cr (OverflowSubI op1 op2));
11872 
11873   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11874   ins_encode %{
11875     __ cmpl($op1$$Register, $op2$$Register);
11876   %}
11877   ins_pipe(ialu_reg_reg);
11878 %}
11879 
11880 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11881 %{
11882   match(Set cr (OverflowSubI op1 op2));
11883 
11884   format %{ "cmpl    $op1, $op2\t# overflow check int" %}
11885   ins_encode %{
11886     __ cmpl($op1$$Register, $op2$$constant);
11887   %}
11888   ins_pipe(ialu_reg_reg);
11889 %}
11890 
11891 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11892 %{
11893   match(Set cr (OverflowSubL op1 op2));
11894 
11895   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11896   ins_encode %{
11897     __ cmpq($op1$$Register, $op2$$Register);
11898   %}
11899   ins_pipe(ialu_reg_reg);
11900 %}
11901 
11902 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11903 %{
11904   match(Set cr (OverflowSubL op1 op2));
11905 
11906   format %{ "cmpq    $op1, $op2\t# overflow check long" %}
11907   ins_encode %{
11908     __ cmpq($op1$$Register, $op2$$constant);
11909   %}
11910   ins_pipe(ialu_reg_reg);
11911 %}
11912 
11913 instruct overflowNegI_rReg(rFlagsReg cr, immI_0 zero, rax_RegI op2)
11914 %{
11915   match(Set cr (OverflowSubI zero op2));
11916   effect(DEF cr, USE_KILL op2);
11917 
11918   format %{ "negl    $op2\t# overflow check int" %}
11919   ins_encode %{
11920     __ negl($op2$$Register);
11921   %}
11922   ins_pipe(ialu_reg_reg);
11923 %}
11924 
11925 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
11926 %{
11927   match(Set cr (OverflowSubL zero op2));
11928   effect(DEF cr, USE_KILL op2);
11929 
11930   format %{ "negq    $op2\t# overflow check long" %}
11931   ins_encode %{
11932     __ negq($op2$$Register);
11933   %}
11934   ins_pipe(ialu_reg_reg);
11935 %}
11936 
11937 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
11938 %{
11939   match(Set cr (OverflowMulI op1 op2));
11940   effect(DEF cr, USE_KILL op1, USE op2);
11941 
11942   format %{ "imull    $op1, $op2\t# overflow check int" %}
11943   ins_encode %{
11944     __ imull($op1$$Register, $op2$$Register);
11945   %}
11946   ins_pipe(ialu_reg_reg_alu0);
11947 %}
11948 
11949 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
11950 %{
11951   match(Set cr (OverflowMulI op1 op2));
11952   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11953 
11954   format %{ "imull    $tmp, $op1, $op2\t# overflow check int" %}
11955   ins_encode %{
11956     __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
11957   %}
11958   ins_pipe(ialu_reg_reg_alu0);
11959 %}
11960 
11961 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
11962 %{
11963   match(Set cr (OverflowMulL op1 op2));
11964   effect(DEF cr, USE_KILL op1, USE op2);
11965 
11966   format %{ "imulq    $op1, $op2\t# overflow check long" %}
11967   ins_encode %{
11968     __ imulq($op1$$Register, $op2$$Register);
11969   %}
11970   ins_pipe(ialu_reg_reg_alu0);
11971 %}
11972 
11973 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
11974 %{
11975   match(Set cr (OverflowMulL op1 op2));
11976   effect(DEF cr, TEMP tmp, USE op1, USE op2);
11977 
11978   format %{ "imulq    $tmp, $op1, $op2\t# overflow check long" %}
11979   ins_encode %{
11980     __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
11981   %}
11982   ins_pipe(ialu_reg_reg_alu0);
11983 %}
11984 
11985 
11986 //----------Control Flow Instructions------------------------------------------
11987 // Signed compare Instructions
11988 
11989 // XXX more variants!!
11990 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
11991 %{
11992   match(Set cr (CmpI op1 op2));
11993   effect(DEF cr, USE op1, USE op2);
11994 
11995   format %{ "cmpl    $op1, $op2" %}
11996   ins_encode %{
11997     __ cmpl($op1$$Register, $op2$$Register);
11998   %}
11999   ins_pipe(ialu_cr_reg_reg);
12000 %}
12001 
12002 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
12003 %{
12004   match(Set cr (CmpI op1 op2));
12005 
12006   format %{ "cmpl    $op1, $op2" %}
12007   ins_encode %{
12008     __ cmpl($op1$$Register, $op2$$constant);
12009   %}
12010   ins_pipe(ialu_cr_reg_imm);
12011 %}
12012 
12013 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
12014 %{
12015   match(Set cr (CmpI op1 (LoadI op2)));
12016 
12017   ins_cost(500); // XXX
12018   format %{ "cmpl    $op1, $op2" %}
12019   ins_encode %{
12020     __ cmpl($op1$$Register, $op2$$Address);
12021   %}
12022   ins_pipe(ialu_cr_reg_mem);
12023 %}
12024 
12025 instruct testI_reg(rFlagsReg cr, rRegI src, immI_0 zero)
12026 %{
12027   match(Set cr (CmpI src zero));
12028 
12029   format %{ "testl   $src, $src" %}
12030   ins_encode %{
12031     __ testl($src$$Register, $src$$Register);
12032   %}
12033   ins_pipe(ialu_cr_reg_imm);
12034 %}
12035 
12036 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI_0 zero)
12037 %{
12038   match(Set cr (CmpI (AndI src con) zero));
12039 
12040   format %{ "testl   $src, $con" %}
12041   ins_encode %{
12042     __ testl($src$$Register, $con$$constant);
12043   %}
12044   ins_pipe(ialu_cr_reg_imm);
12045 %}
12046 
12047 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI_0 zero)
12048 %{
12049   match(Set cr (CmpI (AndI src (LoadI mem)) zero));
12050 
12051   format %{ "testl   $src, $mem" %}
12052   ins_encode %{
12053     __ testl($src$$Register, $mem$$Address);
12054   %}
12055   ins_pipe(ialu_cr_reg_mem);
12056 %}
12057 
12058 // Unsigned compare Instructions; really, same as signed except they
12059 // produce an rFlagsRegU instead of rFlagsReg.
12060 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
12061 %{
12062   match(Set cr (CmpU op1 op2));
12063 
12064   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12065   ins_encode %{
12066     __ cmpl($op1$$Register, $op2$$Register);
12067   %}
12068   ins_pipe(ialu_cr_reg_reg);
12069 %}
12070 
12071 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
12072 %{
12073   match(Set cr (CmpU op1 op2));
12074 
12075   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12076   ins_encode %{
12077     __ cmpl($op1$$Register, $op2$$constant);
12078   %}
12079   ins_pipe(ialu_cr_reg_imm);
12080 %}
12081 
12082 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
12083 %{
12084   match(Set cr (CmpU op1 (LoadI op2)));
12085 
12086   ins_cost(500); // XXX
12087   format %{ "cmpl    $op1, $op2\t# unsigned" %}
12088   ins_encode %{
12089     __ cmpl($op1$$Register, $op2$$Address);
12090   %}
12091   ins_pipe(ialu_cr_reg_mem);
12092 %}
12093 
12094 // // // Cisc-spilled version of cmpU_rReg
12095 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
12096 // //%{
12097 // //  match(Set cr (CmpU (LoadI op1) op2));
12098 // //
12099 // //  format %{ "CMPu   $op1,$op2" %}
12100 // //  ins_cost(500);
12101 // //  opcode(0x39);  /* Opcode 39 /r */
12102 // //  ins_encode( OpcP, reg_mem( op1, op2) );
12103 // //%}
12104 
12105 instruct testU_reg(rFlagsRegU cr, rRegI src, immI_0 zero)
12106 %{
12107   match(Set cr (CmpU src zero));
12108 
12109   format %{ "testl   $src, $src\t# unsigned" %}
12110   ins_encode %{
12111     __ testl($src$$Register, $src$$Register);
12112   %}
12113   ins_pipe(ialu_cr_reg_imm);
12114 %}
12115 
12116 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
12117 %{
12118   match(Set cr (CmpP op1 op2));
12119 
12120   format %{ "cmpq    $op1, $op2\t# ptr" %}
12121   ins_encode %{
12122     __ cmpq($op1$$Register, $op2$$Register);
12123   %}
12124   ins_pipe(ialu_cr_reg_reg);
12125 %}
12126 
12127 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
12128 %{
12129   match(Set cr (CmpP op1 (LoadP op2)));
12130   predicate(n->in(2)->as_Load()->barrier_data() == 0);
12131 
12132   ins_cost(500); // XXX
12133   format %{ "cmpq    $op1, $op2\t# ptr" %}
12134   ins_encode %{
12135     __ cmpq($op1$$Register, $op2$$Address);
12136   %}
12137   ins_pipe(ialu_cr_reg_mem);
12138 %}
12139 
12140 // // // Cisc-spilled version of cmpP_rReg
12141 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
12142 // //%{
12143 // //  match(Set cr (CmpP (LoadP op1) op2));
12144 // //
12145 // //  format %{ "CMPu   $op1,$op2" %}
12146 // //  ins_cost(500);
12147 // //  opcode(0x39);  /* Opcode 39 /r */
12148 // //  ins_encode( OpcP, reg_mem( op1, op2) );
12149 // //%}
12150 
12151 // XXX this is generalized by compP_rReg_mem???
12152 // Compare raw pointer (used in out-of-heap check).
12153 // Only works because non-oop pointers must be raw pointers
12154 // and raw pointers have no anti-dependencies.
12155 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
12156 %{
12157   predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none &&
12158             n->in(2)->as_Load()->barrier_data() == 0);
12159   match(Set cr (CmpP op1 (LoadP op2)));
12160 
12161   format %{ "cmpq    $op1, $op2\t# raw ptr" %}
12162   ins_encode %{
12163     __ cmpq($op1$$Register, $op2$$Address);
12164   %}
12165   ins_pipe(ialu_cr_reg_mem);
12166 %}
12167 
12168 // This will generate a signed flags result. This should be OK since
12169 // any compare to a zero should be eq/neq.
12170 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
12171 %{
12172   match(Set cr (CmpP src zero));
12173 
12174   format %{ "testq   $src, $src\t# ptr" %}
12175   ins_encode %{
12176     __ testq($src$$Register, $src$$Register);
12177   %}
12178   ins_pipe(ialu_cr_reg_imm);
12179 %}
12180 
12181 // This will generate a signed flags result. This should be OK since
12182 // any compare to a zero should be eq/neq.
12183 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
12184 %{
12185   predicate((!UseCompressedOops || (CompressedOops::base() != NULL)) &&
12186             n->in(1)->as_Load()->barrier_data() == 0);
12187   match(Set cr (CmpP (LoadP op) zero));
12188 
12189   ins_cost(500); // XXX
12190   format %{ "testq   $op, 0xffffffffffffffff\t# ptr" %}
12191   ins_encode %{
12192     __ testq($op$$Address, 0xFFFFFFFF);
12193   %}
12194   ins_pipe(ialu_cr_reg_imm);
12195 %}
12196 
12197 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
12198 %{
12199   predicate(UseCompressedOops && (CompressedOops::base() == NULL) &&
12200             n->in(1)->as_Load()->barrier_data() == 0);
12201   match(Set cr (CmpP (LoadP mem) zero));
12202 
12203   format %{ "cmpq    R12, $mem\t# ptr (R12_heapbase==0)" %}
12204   ins_encode %{
12205     __ cmpq(r12, $mem$$Address);
12206   %}
12207   ins_pipe(ialu_cr_reg_mem);
12208 %}
12209 
12210 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
12211 %{
12212   match(Set cr (CmpN op1 op2));
12213 
12214   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
12215   ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
12216   ins_pipe(ialu_cr_reg_reg);
12217 %}
12218 
12219 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
12220 %{
12221   match(Set cr (CmpN src (LoadN mem)));
12222 
12223   format %{ "cmpl    $src, $mem\t# compressed ptr" %}
12224   ins_encode %{
12225     __ cmpl($src$$Register, $mem$$Address);
12226   %}
12227   ins_pipe(ialu_cr_reg_mem);
12228 %}
12229 
12230 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
12231   match(Set cr (CmpN op1 op2));
12232 
12233   format %{ "cmpl    $op1, $op2\t# compressed ptr" %}
12234   ins_encode %{
12235     __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
12236   %}
12237   ins_pipe(ialu_cr_reg_imm);
12238 %}
12239 
12240 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
12241 %{
12242   match(Set cr (CmpN src (LoadN mem)));
12243 
12244   format %{ "cmpl    $mem, $src\t# compressed ptr" %}
12245   ins_encode %{
12246     __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
12247   %}
12248   ins_pipe(ialu_cr_reg_mem);
12249 %}
12250 
12251 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
12252   match(Set cr (CmpN op1 op2));
12253 
12254   format %{ "cmpl    $op1, $op2\t# compressed klass ptr" %}
12255   ins_encode %{
12256     __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
12257   %}
12258   ins_pipe(ialu_cr_reg_imm);
12259 %}
12260 
12261 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
12262 %{
12263   match(Set cr (CmpN src (LoadNKlass mem)));
12264 
12265   format %{ "cmpl    $mem, $src\t# compressed klass ptr" %}
12266   ins_encode %{
12267     __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
12268   %}
12269   ins_pipe(ialu_cr_reg_mem);
12270 %}
12271 
12272 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
12273   match(Set cr (CmpN src zero));
12274 
12275   format %{ "testl   $src, $src\t# compressed ptr" %}
12276   ins_encode %{ __ testl($src$$Register, $src$$Register); %}
12277   ins_pipe(ialu_cr_reg_imm);
12278 %}
12279 
12280 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
12281 %{
12282   predicate(CompressedOops::base() != NULL);
12283   match(Set cr (CmpN (LoadN mem) zero));
12284 
12285   ins_cost(500); // XXX
12286   format %{ "testl   $mem, 0xffffffff\t# compressed ptr" %}
12287   ins_encode %{
12288     __ cmpl($mem$$Address, (int)0xFFFFFFFF);
12289   %}
12290   ins_pipe(ialu_cr_reg_mem);
12291 %}
12292 
12293 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
12294 %{
12295   predicate(CompressedOops::base() == NULL);
12296   match(Set cr (CmpN (LoadN mem) zero));
12297 
12298   format %{ "cmpl    R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
12299   ins_encode %{
12300     __ cmpl(r12, $mem$$Address);
12301   %}
12302   ins_pipe(ialu_cr_reg_mem);
12303 %}
12304 
12305 // Yanked all unsigned pointer compare operations.
12306 // Pointer compares are done with CmpP which is already unsigned.
12307 
12308 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
12309 %{
12310   match(Set cr (CmpL op1 op2));
12311 
12312   format %{ "cmpq    $op1, $op2" %}
12313   ins_encode %{
12314     __ cmpq($op1$$Register, $op2$$Register);
12315   %}
12316   ins_pipe(ialu_cr_reg_reg);
12317 %}
12318 
12319 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
12320 %{
12321   match(Set cr (CmpL op1 op2));
12322 
12323   format %{ "cmpq    $op1, $op2" %}
12324   ins_encode %{
12325     __ cmpq($op1$$Register, $op2$$constant);
12326   %}
12327   ins_pipe(ialu_cr_reg_imm);
12328 %}
12329 
12330 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
12331 %{
12332   match(Set cr (CmpL op1 (LoadL op2)));
12333 
12334   format %{ "cmpq    $op1, $op2" %}
12335   ins_encode %{
12336     __ cmpq($op1$$Register, $op2$$Address);
12337   %}
12338   ins_pipe(ialu_cr_reg_mem);
12339 %}
12340 
12341 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
12342 %{
12343   match(Set cr (CmpL src zero));
12344 
12345   format %{ "testq   $src, $src" %}
12346   ins_encode %{
12347     __ testq($src$$Register, $src$$Register);
12348   %}
12349   ins_pipe(ialu_cr_reg_imm);
12350 %}
12351 
12352 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
12353 %{
12354   match(Set cr (CmpL (AndL src con) zero));
12355 
12356   format %{ "testq   $src, $con\t# long" %}
12357   ins_encode %{
12358     __ testq($src$$Register, $con$$constant);
12359   %}
12360   ins_pipe(ialu_cr_reg_imm);
12361 %}
12362 
12363 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
12364 %{
12365   match(Set cr (CmpL (AndL src (LoadL mem)) zero));
12366 
12367   format %{ "testq   $src, $mem" %}
12368   ins_encode %{
12369     __ testq($src$$Register, $mem$$Address);
12370   %}
12371   ins_pipe(ialu_cr_reg_mem);
12372 %}
12373 
12374 instruct testL_reg_mem2(rFlagsReg cr, rRegP src, memory mem, immL0 zero)
12375 %{
12376   match(Set cr (CmpL (AndL (CastP2X src) (LoadL mem)) zero));
12377 
12378   format %{ "testq   $src, $mem" %}
12379   ins_encode %{
12380     __ testq($src$$Register, $mem$$Address);
12381   %}
12382   ins_pipe(ialu_cr_reg_mem);
12383 %}
12384 
12385 // Manifest a CmpL result in an integer register.  Very painful.
12386 // This is the test to avoid.
12387 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
12388 %{
12389   match(Set dst (CmpL3 src1 src2));
12390   effect(KILL flags);
12391 
12392   ins_cost(275); // XXX
12393   format %{ "cmpq    $src1, $src2\t# CmpL3\n\t"
12394             "movl    $dst, -1\n\t"
12395             "jl,s    done\n\t"
12396             "setne   $dst\n\t"
12397             "movzbl  $dst, $dst\n\t"
12398     "done:" %}
12399   ins_encode %{
12400     Label done;
12401     __ cmpq($src1$$Register, $src2$$Register);
12402     __ movl($dst$$Register, -1);
12403     __ jccb(Assembler::less, done);
12404     __ setne($dst$$Register);
12405     __ movzbl($dst$$Register, $dst$$Register);
12406     __ bind(done);
12407   %}
12408   ins_pipe(pipe_slow);
12409 %}
12410 
12411 // Unsigned long compare Instructions; really, same as signed long except they
12412 // produce an rFlagsRegU instead of rFlagsReg.
12413 instruct compUL_rReg(rFlagsRegU cr, rRegL op1, rRegL op2)
12414 %{
12415   match(Set cr (CmpUL op1 op2));
12416 
12417   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12418   ins_encode %{
12419     __ cmpq($op1$$Register, $op2$$Register);
12420   %}
12421   ins_pipe(ialu_cr_reg_reg);
12422 %}
12423 
12424 instruct compUL_rReg_imm(rFlagsRegU cr, rRegL op1, immL32 op2)
12425 %{
12426   match(Set cr (CmpUL op1 op2));
12427 
12428   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12429   ins_encode %{
12430     __ cmpq($op1$$Register, $op2$$constant);
12431   %}
12432   ins_pipe(ialu_cr_reg_imm);
12433 %}
12434 
12435 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
12436 %{
12437   match(Set cr (CmpUL op1 (LoadL op2)));
12438 
12439   format %{ "cmpq    $op1, $op2\t# unsigned" %}
12440   ins_encode %{
12441     __ cmpq($op1$$Register, $op2$$Address);
12442   %}
12443   ins_pipe(ialu_cr_reg_mem);
12444 %}
12445 
12446 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
12447 %{
12448   match(Set cr (CmpUL src zero));
12449 
12450   format %{ "testq   $src, $src\t# unsigned" %}
12451   ins_encode %{
12452     __ testq($src$$Register, $src$$Register);
12453   %}
12454   ins_pipe(ialu_cr_reg_imm);
12455 %}
12456 
12457 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
12458 %{
12459   match(Set cr (CmpI (LoadB mem) imm));
12460 
12461   ins_cost(125);
12462   format %{ "cmpb    $mem, $imm" %}
12463   ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
12464   ins_pipe(ialu_cr_reg_mem);
12465 %}
12466 
12467 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU7 imm, immI_0 zero)
12468 %{
12469   match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
12470 
12471   ins_cost(125);
12472   format %{ "testb   $mem, $imm\t# ubyte" %}
12473   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12474   ins_pipe(ialu_cr_reg_mem);
12475 %}
12476 
12477 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI_0 zero)
12478 %{
12479   match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
12480 
12481   ins_cost(125);
12482   format %{ "testb   $mem, $imm\t# byte" %}
12483   ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
12484   ins_pipe(ialu_cr_reg_mem);
12485 %}
12486 
12487 //----------Max and Min--------------------------------------------------------
12488 // Min Instructions
12489 
12490 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
12491 %{
12492   effect(USE_DEF dst, USE src, USE cr);
12493 
12494   format %{ "cmovlgt $dst, $src\t# min" %}
12495   ins_encode %{
12496     __ cmovl(Assembler::greater, $dst$$Register, $src$$Register);
12497   %}
12498   ins_pipe(pipe_cmov_reg);
12499 %}
12500 
12501 
12502 instruct minI_rReg(rRegI dst, rRegI src)
12503 %{
12504   match(Set dst (MinI dst src));
12505 
12506   ins_cost(200);
12507   expand %{
12508     rFlagsReg cr;
12509     compI_rReg(cr, dst, src);
12510     cmovI_reg_g(dst, src, cr);
12511   %}
12512 %}
12513 
12514 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
12515 %{
12516   effect(USE_DEF dst, USE src, USE cr);
12517 
12518   format %{ "cmovllt $dst, $src\t# max" %}
12519   ins_encode %{
12520     __ cmovl(Assembler::less, $dst$$Register, $src$$Register);
12521   %}
12522   ins_pipe(pipe_cmov_reg);
12523 %}
12524 
12525 
12526 instruct maxI_rReg(rRegI dst, rRegI src)
12527 %{
12528   match(Set dst (MaxI dst src));
12529 
12530   ins_cost(200);
12531   expand %{
12532     rFlagsReg cr;
12533     compI_rReg(cr, dst, src);
12534     cmovI_reg_l(dst, src, cr);
12535   %}
12536 %}
12537 
12538 // ============================================================================
12539 // Branch Instructions
12540 
12541 // Jump Direct - Label defines a relative address from JMP+1
12542 instruct jmpDir(label labl)
12543 %{
12544   match(Goto);
12545   effect(USE labl);
12546 
12547   ins_cost(300);
12548   format %{ "jmp     $labl" %}
12549   size(5);
12550   ins_encode %{
12551     Label* L = $labl$$label;
12552     __ jmp(*L, false); // Always long jump
12553   %}
12554   ins_pipe(pipe_jmp);
12555 %}
12556 
12557 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12558 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
12559 %{
12560   match(If cop cr);
12561   effect(USE labl);
12562 
12563   ins_cost(300);
12564   format %{ "j$cop     $labl" %}
12565   size(6);
12566   ins_encode %{
12567     Label* L = $labl$$label;
12568     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12569   %}
12570   ins_pipe(pipe_jcc);
12571 %}
12572 
12573 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12574 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
12575 %{
12576   predicate(!n->has_vector_mask_set());
12577   match(CountedLoopEnd cop cr);
12578   effect(USE labl);
12579 
12580   ins_cost(300);
12581   format %{ "j$cop     $labl\t# loop end" %}
12582   size(6);
12583   ins_encode %{
12584     Label* L = $labl$$label;
12585     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12586   %}
12587   ins_pipe(pipe_jcc);
12588 %}
12589 
12590 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12591 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12592   predicate(!n->has_vector_mask_set());
12593   match(CountedLoopEnd cop cmp);
12594   effect(USE labl);
12595 
12596   ins_cost(300);
12597   format %{ "j$cop,u   $labl\t# loop end" %}
12598   size(6);
12599   ins_encode %{
12600     Label* L = $labl$$label;
12601     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12602   %}
12603   ins_pipe(pipe_jcc);
12604 %}
12605 
12606 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12607   predicate(!n->has_vector_mask_set());
12608   match(CountedLoopEnd cop cmp);
12609   effect(USE labl);
12610 
12611   ins_cost(200);
12612   format %{ "j$cop,u   $labl\t# loop end" %}
12613   size(6);
12614   ins_encode %{
12615     Label* L = $labl$$label;
12616     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12617   %}
12618   ins_pipe(pipe_jcc);
12619 %}
12620 
12621 // mask version
12622 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12623 // Bounded mask operand used in following patten is needed for
12624 // post-loop multiversioning.
12625 instruct jmpLoopEnd_and_restoreMask(cmpOp cop, kReg_K1 ktmp, rFlagsReg cr, label labl)
12626 %{
12627   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12628   match(CountedLoopEnd cop cr);
12629   effect(USE labl, TEMP ktmp);
12630 
12631   ins_cost(400);
12632   format %{ "j$cop     $labl\t# loop end\n\t"
12633             "restorevectmask \t# vector mask restore for loops" %}
12634   size(10);
12635   ins_encode %{
12636     Label* L = $labl$$label;
12637     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12638     __ restorevectmask($ktmp$$KRegister);
12639   %}
12640   ins_pipe(pipe_jcc);
12641 %}
12642 
12643 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12644 // Bounded mask operand used in following patten is needed for
12645 // post-loop multiversioning.
12646 instruct jmpLoopEndU_and_restoreMask(cmpOpU cop, kReg_K1 ktmp, rFlagsRegU cmp, label labl) %{
12647   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12648   match(CountedLoopEnd cop cmp);
12649   effect(USE labl, TEMP ktmp);
12650 
12651   ins_cost(400);
12652   format %{ "j$cop,u   $labl\t# loop end\n\t"
12653             "restorevectmask \t# vector mask restore for loops" %}
12654   size(10);
12655   ins_encode %{
12656     Label* L = $labl$$label;
12657     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12658     __ restorevectmask($ktmp$$KRegister);
12659   %}
12660   ins_pipe(pipe_jcc);
12661 %}
12662 
12663 // Bounded mask operand used in following patten is needed for
12664 // post-loop multiversioning.
12665 instruct jmpLoopEndUCF_and_restoreMask(cmpOpUCF cop, kReg_K1 ktmp, rFlagsRegUCF cmp, label labl) %{
12666   predicate(PostLoopMultiversioning && n->has_vector_mask_set());
12667   match(CountedLoopEnd cop cmp);
12668   effect(USE labl, TEMP ktmp);
12669 
12670   ins_cost(300);
12671   format %{ "j$cop,u   $labl\t# loop end\n\t"
12672             "restorevectmask \t# vector mask restore for loops" %}
12673   size(10);
12674   ins_encode %{
12675     Label* L = $labl$$label;
12676     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12677     __ restorevectmask($ktmp$$KRegister);
12678   %}
12679   ins_pipe(pipe_jcc);
12680 %}
12681 
12682 // Jump Direct Conditional - using unsigned comparison
12683 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12684   match(If cop cmp);
12685   effect(USE labl);
12686 
12687   ins_cost(300);
12688   format %{ "j$cop,u   $labl" %}
12689   size(6);
12690   ins_encode %{
12691     Label* L = $labl$$label;
12692     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12693   %}
12694   ins_pipe(pipe_jcc);
12695 %}
12696 
12697 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12698   match(If cop cmp);
12699   effect(USE labl);
12700 
12701   ins_cost(200);
12702   format %{ "j$cop,u   $labl" %}
12703   size(6);
12704   ins_encode %{
12705     Label* L = $labl$$label;
12706     __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
12707   %}
12708   ins_pipe(pipe_jcc);
12709 %}
12710 
12711 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12712   match(If cop cmp);
12713   effect(USE labl);
12714 
12715   ins_cost(200);
12716   format %{ $$template
12717     if ($cop$$cmpcode == Assembler::notEqual) {
12718       $$emit$$"jp,u    $labl\n\t"
12719       $$emit$$"j$cop,u   $labl"
12720     } else {
12721       $$emit$$"jp,u    done\n\t"
12722       $$emit$$"j$cop,u   $labl\n\t"
12723       $$emit$$"done:"
12724     }
12725   %}
12726   ins_encode %{
12727     Label* l = $labl$$label;
12728     if ($cop$$cmpcode == Assembler::notEqual) {
12729       __ jcc(Assembler::parity, *l, false);
12730       __ jcc(Assembler::notEqual, *l, false);
12731     } else if ($cop$$cmpcode == Assembler::equal) {
12732       Label done;
12733       __ jccb(Assembler::parity, done);
12734       __ jcc(Assembler::equal, *l, false);
12735       __ bind(done);
12736     } else {
12737        ShouldNotReachHere();
12738     }
12739   %}
12740   ins_pipe(pipe_jcc);
12741 %}
12742 
12743 // ============================================================================
12744 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary
12745 // superklass array for an instance of the superklass.  Set a hidden
12746 // internal cache on a hit (cache is checked with exposed code in
12747 // gen_subtype_check()).  Return NZ for a miss or zero for a hit.  The
12748 // encoding ALSO sets flags.
12749 
12750 instruct partialSubtypeCheck(rdi_RegP result,
12751                              rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12752                              rFlagsReg cr)
12753 %{
12754   match(Set result (PartialSubtypeCheck sub super));
12755   effect(KILL rcx, KILL cr);
12756 
12757   ins_cost(1100);  // slightly larger than the next version
12758   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12759             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12760             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12761             "repne   scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
12762             "jne,s   miss\t\t# Missed: rdi not-zero\n\t"
12763             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12764             "xorq    $result, $result\t\t Hit: rdi zero\n\t"
12765     "miss:\t" %}
12766 
12767   opcode(0x1); // Force a XOR of RDI
12768   ins_encode(enc_PartialSubtypeCheck());
12769   ins_pipe(pipe_slow);
12770 %}
12771 
12772 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
12773                                      rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
12774                                      immP0 zero,
12775                                      rdi_RegP result)
12776 %{
12777   match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
12778   effect(KILL rcx, KILL result);
12779 
12780   ins_cost(1000);
12781   format %{ "movq    rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
12782             "movl    rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
12783             "addq    rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
12784             "repne   scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
12785             "jne,s   miss\t\t# Missed: flags nz\n\t"
12786             "movq    [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
12787     "miss:\t" %}
12788 
12789   opcode(0x0); // No need to XOR RDI
12790   ins_encode(enc_PartialSubtypeCheck());
12791   ins_pipe(pipe_slow);
12792 %}
12793 
12794 // ============================================================================
12795 // Branch Instructions -- short offset versions
12796 //
12797 // These instructions are used to replace jumps of a long offset (the default
12798 // match) with jumps of a shorter offset.  These instructions are all tagged
12799 // with the ins_short_branch attribute, which causes the ADLC to suppress the
12800 // match rules in general matching.  Instead, the ADLC generates a conversion
12801 // method in the MachNode which can be used to do in-place replacement of the
12802 // long variant with the shorter variant.  The compiler will determine if a
12803 // branch can be taken by the is_short_branch_offset() predicate in the machine
12804 // specific code section of the file.
12805 
12806 // Jump Direct - Label defines a relative address from JMP+1
12807 instruct jmpDir_short(label labl) %{
12808   match(Goto);
12809   effect(USE labl);
12810 
12811   ins_cost(300);
12812   format %{ "jmp,s   $labl" %}
12813   size(2);
12814   ins_encode %{
12815     Label* L = $labl$$label;
12816     __ jmpb(*L);
12817   %}
12818   ins_pipe(pipe_jmp);
12819   ins_short_branch(1);
12820 %}
12821 
12822 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12823 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
12824   match(If cop cr);
12825   effect(USE labl);
12826 
12827   ins_cost(300);
12828   format %{ "j$cop,s   $labl" %}
12829   size(2);
12830   ins_encode %{
12831     Label* L = $labl$$label;
12832     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12833   %}
12834   ins_pipe(pipe_jcc);
12835   ins_short_branch(1);
12836 %}
12837 
12838 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12839 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
12840   match(CountedLoopEnd cop cr);
12841   effect(USE labl);
12842 
12843   ins_cost(300);
12844   format %{ "j$cop,s   $labl\t# loop end" %}
12845   size(2);
12846   ins_encode %{
12847     Label* L = $labl$$label;
12848     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12849   %}
12850   ins_pipe(pipe_jcc);
12851   ins_short_branch(1);
12852 %}
12853 
12854 // Jump Direct Conditional - Label defines a relative address from Jcc+1
12855 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12856   match(CountedLoopEnd cop cmp);
12857   effect(USE labl);
12858 
12859   ins_cost(300);
12860   format %{ "j$cop,us  $labl\t# loop end" %}
12861   size(2);
12862   ins_encode %{
12863     Label* L = $labl$$label;
12864     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12865   %}
12866   ins_pipe(pipe_jcc);
12867   ins_short_branch(1);
12868 %}
12869 
12870 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12871   match(CountedLoopEnd cop cmp);
12872   effect(USE labl);
12873 
12874   ins_cost(300);
12875   format %{ "j$cop,us  $labl\t# loop end" %}
12876   size(2);
12877   ins_encode %{
12878     Label* L = $labl$$label;
12879     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12880   %}
12881   ins_pipe(pipe_jcc);
12882   ins_short_branch(1);
12883 %}
12884 
12885 // Jump Direct Conditional - using unsigned comparison
12886 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
12887   match(If cop cmp);
12888   effect(USE labl);
12889 
12890   ins_cost(300);
12891   format %{ "j$cop,us  $labl" %}
12892   size(2);
12893   ins_encode %{
12894     Label* L = $labl$$label;
12895     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12896   %}
12897   ins_pipe(pipe_jcc);
12898   ins_short_branch(1);
12899 %}
12900 
12901 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
12902   match(If cop cmp);
12903   effect(USE labl);
12904 
12905   ins_cost(300);
12906   format %{ "j$cop,us  $labl" %}
12907   size(2);
12908   ins_encode %{
12909     Label* L = $labl$$label;
12910     __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
12911   %}
12912   ins_pipe(pipe_jcc);
12913   ins_short_branch(1);
12914 %}
12915 
12916 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
12917   match(If cop cmp);
12918   effect(USE labl);
12919 
12920   ins_cost(300);
12921   format %{ $$template
12922     if ($cop$$cmpcode == Assembler::notEqual) {
12923       $$emit$$"jp,u,s  $labl\n\t"
12924       $$emit$$"j$cop,u,s  $labl"
12925     } else {
12926       $$emit$$"jp,u,s  done\n\t"
12927       $$emit$$"j$cop,u,s  $labl\n\t"
12928       $$emit$$"done:"
12929     }
12930   %}
12931   size(4);
12932   ins_encode %{
12933     Label* l = $labl$$label;
12934     if ($cop$$cmpcode == Assembler::notEqual) {
12935       __ jccb(Assembler::parity, *l);
12936       __ jccb(Assembler::notEqual, *l);
12937     } else if ($cop$$cmpcode == Assembler::equal) {
12938       Label done;
12939       __ jccb(Assembler::parity, done);
12940       __ jccb(Assembler::equal, *l);
12941       __ bind(done);
12942     } else {
12943        ShouldNotReachHere();
12944     }
12945   %}
12946   ins_pipe(pipe_jcc);
12947   ins_short_branch(1);
12948 %}
12949 
12950 // ============================================================================
12951 // inlined locking and unlocking
12952 
12953 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
12954   predicate(Compile::current()->use_rtm());
12955   match(Set cr (FastLock object box));
12956   effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
12957   ins_cost(300);
12958   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
12959   ins_encode %{
12960     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12961                  $scr$$Register, $cx1$$Register, $cx2$$Register,
12962                  _rtm_counters, _stack_rtm_counters,
12963                  ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
12964                  true, ra_->C->profile_rtm());
12965   %}
12966   ins_pipe(pipe_slow);
12967 %}
12968 
12969 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr, rRegP cx1) %{
12970   predicate(!Compile::current()->use_rtm());
12971   match(Set cr (FastLock object box));
12972   effect(TEMP tmp, TEMP scr, TEMP cx1, USE_KILL box);
12973   ins_cost(300);
12974   format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
12975   ins_encode %{
12976     __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
12977                  $scr$$Register, $cx1$$Register, noreg, NULL, NULL, NULL, false, false);
12978   %}
12979   ins_pipe(pipe_slow);
12980 %}
12981 
12982 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
12983   match(Set cr (FastUnlock object box));
12984   effect(TEMP tmp, USE_KILL box);
12985   ins_cost(300);
12986   format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
12987   ins_encode %{
12988     __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
12989   %}
12990   ins_pipe(pipe_slow);
12991 %}
12992 
12993 
12994 // ============================================================================
12995 // Safepoint Instructions
12996 instruct safePoint_poll_tls(rFlagsReg cr, rRegP poll)
12997 %{
12998   match(SafePoint poll);
12999   effect(KILL cr, USE poll);
13000 
13001   format %{ "testl   rax, [$poll]\t"
13002             "# Safepoint: poll for GC" %}
13003   ins_cost(125);
13004   size(4); /* setting an explicit size will cause debug builds to assert if size is incorrect */
13005   ins_encode %{
13006     __ relocate(relocInfo::poll_type);
13007     address pre_pc = __ pc();
13008     __ testl(rax, Address($poll$$Register, 0));
13009     assert(nativeInstruction_at(pre_pc)->is_safepoint_poll(), "must emit test %%eax [reg]");
13010   %}
13011   ins_pipe(ialu_reg_mem);
13012 %}
13013 
13014 // ============================================================================
13015 // Procedure Call/Return Instructions
13016 // Call Java Static Instruction
13017 // Note: If this code changes, the corresponding ret_addr_offset() and
13018 //       compute_padding() functions will have to be adjusted.
13019 instruct CallStaticJavaDirect(method meth) %{
13020   match(CallStaticJava);
13021   effect(USE meth);
13022 
13023   ins_cost(300);
13024   format %{ "call,static " %}
13025   opcode(0xE8); /* E8 cd */
13026   ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
13027   ins_pipe(pipe_slow);
13028   ins_alignment(4);
13029 %}
13030 
13031 // Call Java Dynamic Instruction
13032 // Note: If this code changes, the corresponding ret_addr_offset() and
13033 //       compute_padding() functions will have to be adjusted.
13034 instruct CallDynamicJavaDirect(method meth)
13035 %{
13036   match(CallDynamicJava);
13037   effect(USE meth);
13038 
13039   ins_cost(300);
13040   format %{ "movq    rax, #Universe::non_oop_word()\n\t"
13041             "call,dynamic " %}
13042   ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
13043   ins_pipe(pipe_slow);
13044   ins_alignment(4);
13045 %}
13046 
13047 // Call Runtime Instruction
13048 instruct CallRuntimeDirect(method meth)
13049 %{
13050   match(CallRuntime);
13051   effect(USE meth);
13052 
13053   ins_cost(300);
13054   format %{ "call,runtime " %}
13055   ins_encode(clear_avx, Java_To_Runtime(meth));
13056   ins_pipe(pipe_slow);
13057 %}
13058 
13059 // Call runtime without safepoint
13060 instruct CallLeafDirect(method meth)
13061 %{
13062   match(CallLeaf);
13063   effect(USE meth);
13064 
13065   ins_cost(300);
13066   format %{ "call_leaf,runtime " %}
13067   ins_encode(clear_avx, Java_To_Runtime(meth));
13068   ins_pipe(pipe_slow);
13069 %}
13070 
13071 // Call runtime without safepoint and with vector arguments
13072 instruct CallLeafDirectVector(method meth)
13073 %{
13074   match(CallLeafVector);
13075   effect(USE meth);
13076 
13077   ins_cost(300);
13078   format %{ "call_leaf,vector " %}
13079   ins_encode(Java_To_Runtime(meth));
13080   ins_pipe(pipe_slow);
13081 %}
13082 
13083 //
13084 instruct CallNativeDirect(method meth)
13085 %{
13086   match(CallNative);
13087   effect(USE meth);
13088 
13089   ins_cost(300);
13090   format %{ "call_native " %}
13091   ins_encode(clear_avx, Java_To_Runtime(meth));
13092   ins_pipe(pipe_slow);
13093 %}
13094 
13095 // Call runtime without safepoint
13096 instruct CallLeafNoFPDirect(method meth)
13097 %{
13098   match(CallLeafNoFP);
13099   effect(USE meth);
13100 
13101   ins_cost(300);
13102   format %{ "call_leaf_nofp,runtime " %}
13103   ins_encode(clear_avx, Java_To_Runtime(meth));
13104   ins_pipe(pipe_slow);
13105 %}
13106 
13107 // Return Instruction
13108 // Remove the return address & jump to it.
13109 // Notice: We always emit a nop after a ret to make sure there is room
13110 // for safepoint patching
13111 instruct Ret()
13112 %{
13113   match(Return);
13114 
13115   format %{ "ret" %}
13116   ins_encode %{
13117     __ ret(0);
13118   %}
13119   ins_pipe(pipe_jmp);
13120 %}
13121 
13122 // Tail Call; Jump from runtime stub to Java code.
13123 // Also known as an 'interprocedural jump'.
13124 // Target of jump will eventually return to caller.
13125 // TailJump below removes the return address.
13126 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_ptr)
13127 %{
13128   match(TailCall jump_target method_ptr);
13129 
13130   ins_cost(300);
13131   format %{ "jmp     $jump_target\t# rbx holds method" %}
13132   ins_encode %{
13133     __ jmp($jump_target$$Register);
13134   %}
13135   ins_pipe(pipe_jmp);
13136 %}
13137 
13138 // Tail Jump; remove the return address; jump to target.
13139 // TailCall above leaves the return address around.
13140 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
13141 %{
13142   match(TailJump jump_target ex_oop);
13143 
13144   ins_cost(300);
13145   format %{ "popq    rdx\t# pop return address\n\t"
13146             "jmp     $jump_target" %}
13147   ins_encode %{
13148     __ popq(as_Register(RDX_enc));
13149     __ jmp($jump_target$$Register);
13150   %}
13151   ins_pipe(pipe_jmp);
13152 %}
13153 
13154 // Create exception oop: created by stack-crawling runtime code.
13155 // Created exception is now available to this handler, and is setup
13156 // just prior to jumping to this handler.  No code emitted.
13157 instruct CreateException(rax_RegP ex_oop)
13158 %{
13159   match(Set ex_oop (CreateEx));
13160 
13161   size(0);
13162   // use the following format syntax
13163   format %{ "# exception oop is in rax; no code emitted" %}
13164   ins_encode();
13165   ins_pipe(empty);
13166 %}
13167 
13168 // Rethrow exception:
13169 // The exception oop will come in the first argument position.
13170 // Then JUMP (not call) to the rethrow stub code.
13171 instruct RethrowException()
13172 %{
13173   match(Rethrow);
13174 
13175   // use the following format syntax
13176   format %{ "jmp     rethrow_stub" %}
13177   ins_encode(enc_rethrow);
13178   ins_pipe(pipe_jmp);
13179 %}
13180 
13181 // ============================================================================
13182 // This name is KNOWN by the ADLC and cannot be changed.
13183 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
13184 // for this guy.
13185 instruct tlsLoadP(r15_RegP dst) %{
13186   match(Set dst (ThreadLocal));
13187   effect(DEF dst);
13188 
13189   size(0);
13190   format %{ "# TLS is in R15" %}
13191   ins_encode( /*empty encoding*/ );
13192   ins_pipe(ialu_reg_reg);
13193 %}
13194 
13195 
13196 //----------PEEPHOLE RULES-----------------------------------------------------
13197 // These must follow all instruction definitions as they use the names
13198 // defined in the instructions definitions.
13199 //
13200 // peepmatch ( root_instr_name [preceding_instruction]* );
13201 //
13202 // peepconstraint %{
13203 // (instruction_number.operand_name relational_op instruction_number.operand_name
13204 //  [, ...] );
13205 // // instruction numbers are zero-based using left to right order in peepmatch
13206 //
13207 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
13208 // // provide an instruction_number.operand_name for each operand that appears
13209 // // in the replacement instruction's match rule
13210 //
13211 // ---------VM FLAGS---------------------------------------------------------
13212 //
13213 // All peephole optimizations can be turned off using -XX:-OptoPeephole
13214 //
13215 // Each peephole rule is given an identifying number starting with zero and
13216 // increasing by one in the order seen by the parser.  An individual peephole
13217 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
13218 // on the command-line.
13219 //
13220 // ---------CURRENT LIMITATIONS----------------------------------------------
13221 //
13222 // Only match adjacent instructions in same basic block
13223 // Only equality constraints
13224 // Only constraints between operands, not (0.dest_reg == RAX_enc)
13225 // Only one replacement instruction
13226 //
13227 // ---------EXAMPLE----------------------------------------------------------
13228 //
13229 // // pertinent parts of existing instructions in architecture description
13230 // instruct movI(rRegI dst, rRegI src)
13231 // %{
13232 //   match(Set dst (CopyI src));
13233 // %}
13234 //
13235 // instruct incI_rReg(rRegI dst, immI_1 src, rFlagsReg cr)
13236 // %{
13237 //   match(Set dst (AddI dst src));
13238 //   effect(KILL cr);
13239 // %}
13240 //
13241 // // Change (inc mov) to lea
13242 // peephole %{
13243 //   // increment preceeded by register-register move
13244 //   peepmatch ( incI_rReg movI );
13245 //   // require that the destination register of the increment
13246 //   // match the destination register of the move
13247 //   peepconstraint ( 0.dst == 1.dst );
13248 //   // construct a replacement instruction that sets
13249 //   // the destination to ( move's source register + one )
13250 //   peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
13251 // %}
13252 //
13253 
13254 // Implementation no longer uses movX instructions since
13255 // machine-independent system no longer uses CopyX nodes.
13256 //
13257 // peephole
13258 // %{
13259 //   peepmatch (incI_rReg movI);
13260 //   peepconstraint (0.dst == 1.dst);
13261 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13262 // %}
13263 
13264 // peephole
13265 // %{
13266 //   peepmatch (decI_rReg movI);
13267 //   peepconstraint (0.dst == 1.dst);
13268 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13269 // %}
13270 
13271 // peephole
13272 // %{
13273 //   peepmatch (addI_rReg_imm movI);
13274 //   peepconstraint (0.dst == 1.dst);
13275 //   peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
13276 // %}
13277 
13278 // peephole
13279 // %{
13280 //   peepmatch (incL_rReg movL);
13281 //   peepconstraint (0.dst == 1.dst);
13282 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13283 // %}
13284 
13285 // peephole
13286 // %{
13287 //   peepmatch (decL_rReg movL);
13288 //   peepconstraint (0.dst == 1.dst);
13289 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13290 // %}
13291 
13292 // peephole
13293 // %{
13294 //   peepmatch (addL_rReg_imm movL);
13295 //   peepconstraint (0.dst == 1.dst);
13296 //   peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
13297 // %}
13298 
13299 // peephole
13300 // %{
13301 //   peepmatch (addP_rReg_imm movP);
13302 //   peepconstraint (0.dst == 1.dst);
13303 //   peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
13304 // %}
13305 
13306 // // Change load of spilled value to only a spill
13307 // instruct storeI(memory mem, rRegI src)
13308 // %{
13309 //   match(Set mem (StoreI mem src));
13310 // %}
13311 //
13312 // instruct loadI(rRegI dst, memory mem)
13313 // %{
13314 //   match(Set dst (LoadI mem));
13315 // %}
13316 //
13317 
13318 peephole
13319 %{
13320   peepmatch (loadI storeI);
13321   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13322   peepreplace (storeI(1.mem 1.mem 1.src));
13323 %}
13324 
13325 peephole
13326 %{
13327   peepmatch (loadL storeL);
13328   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
13329   peepreplace (storeL(1.mem 1.mem 1.src));
13330 %}
13331 
13332 //----------SMARTSPILL RULES---------------------------------------------------
13333 // These must follow all instruction definitions as they use the names
13334 // defined in the instructions definitions.
--- EOF ---