1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "memory/universe.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/objectMonitor.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/sharedRuntime.hpp"
36 #include "runtime/stubRoutines.hpp"
37 #include "runtime/vm_version.hpp"
38 #include "utilities/checkedCast.hpp"
39 #include "utilities/macros.hpp"
40
41 #ifdef PRODUCT
42 #define BLOCK_COMMENT(str) /* nothing */
43 #define STOP(error) stop(error)
44 #else
45 #define BLOCK_COMMENT(str) block_comment(str)
46 #define STOP(error) block_comment(error); stop(error)
47 #endif
48
49 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
50 // Implementation of AddressLiteral
51
52 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
53 static const unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
54 // -----------------Table 4.5 -------------------- //
55 16, 32, 64, // EVEX_FV(0)
56 4, 4, 4, // EVEX_FV(1) - with Evex.b
57 16, 32, 64, // EVEX_FV(2) - with Evex.w
58 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
59 8, 16, 32, // EVEX_HV(0)
60 4, 4, 4, // EVEX_HV(1) - with Evex.b
61 // -----------------Table 4.6 -------------------- //
62 16, 32, 64, // EVEX_FVM(0)
63 1, 1, 1, // EVEX_T1S(0)
64 2, 2, 2, // EVEX_T1S(1)
65 4, 4, 4, // EVEX_T1S(2)
66 8, 8, 8, // EVEX_T1S(3)
67 4, 4, 4, // EVEX_T1F(0)
68 8, 8, 8, // EVEX_T1F(1)
69 8, 8, 8, // EVEX_T2(0)
70 0, 16, 16, // EVEX_T2(1)
71 0, 16, 16, // EVEX_T4(0)
72 0, 0, 32, // EVEX_T4(1)
73 0, 0, 32, // EVEX_T8(0)
74 8, 16, 32, // EVEX_HVM(0)
75 4, 8, 16, // EVEX_QVM(0)
76 2, 4, 8, // EVEX_OVM(0)
77 16, 16, 16, // EVEX_M128(0)
78 8, 32, 64, // EVEX_DUP(0)
79 0, 0, 0 // EVEX_NTUP
80 };
81
82 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
83 _is_lval = false;
84 _target = target;
85 switch (rtype) {
86 case relocInfo::oop_type:
87 case relocInfo::metadata_type:
88 // Oops are a special case. Normally they would be their own section
89 // but in cases like icBuffer they are literals in the code stream that
90 // we don't have a section for. We use none so that we get a literal address
91 // which is always patchable.
92 break;
93 case relocInfo::external_word_type:
94 _rspec = external_word_Relocation::spec(target);
95 break;
96 case relocInfo::internal_word_type:
97 _rspec = internal_word_Relocation::spec(target);
98 break;
99 case relocInfo::opt_virtual_call_type:
100 _rspec = opt_virtual_call_Relocation::spec();
101 break;
102 case relocInfo::static_call_type:
103 _rspec = static_call_Relocation::spec();
104 break;
105 case relocInfo::runtime_call_type:
106 _rspec = runtime_call_Relocation::spec();
107 break;
108 case relocInfo::poll_type:
109 case relocInfo::poll_return_type:
110 _rspec = Relocation::spec_simple(rtype);
111 break;
112 case relocInfo::none:
113 break;
114 default:
115 ShouldNotReachHere();
116 break;
117 }
118 }
119
120 // Implementation of Address
121
122 #ifdef _LP64
123
124 Address Address::make_array(ArrayAddress adr) {
125 // Not implementable on 64bit machines
126 // Should have been handled higher up the call chain.
127 ShouldNotReachHere();
128 return Address();
129 }
130
131 // exceedingly dangerous constructor
132 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
133 _base = noreg;
134 _index = noreg;
135 _scale = no_scale;
136 _disp = disp;
137 _xmmindex = xnoreg;
138 _isxmmindex = false;
139 switch (rtype) {
140 case relocInfo::external_word_type:
141 _rspec = external_word_Relocation::spec(loc);
142 break;
143 case relocInfo::internal_word_type:
144 _rspec = internal_word_Relocation::spec(loc);
145 break;
146 case relocInfo::runtime_call_type:
147 // HMM
148 _rspec = runtime_call_Relocation::spec();
149 break;
150 case relocInfo::poll_type:
151 case relocInfo::poll_return_type:
152 _rspec = Relocation::spec_simple(rtype);
153 break;
154 case relocInfo::none:
155 break;
156 default:
157 ShouldNotReachHere();
158 }
159 }
160 #else // LP64
161
162 Address Address::make_array(ArrayAddress adr) {
163 AddressLiteral base = adr.base();
164 Address index = adr.index();
165 assert(index._disp == 0, "must not have disp"); // maybe it can?
166 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
167 array._rspec = base._rspec;
168 return array;
169 }
170
171 // exceedingly dangerous constructor
172 Address::Address(address loc, RelocationHolder spec) {
173 _base = noreg;
174 _index = noreg;
175 _scale = no_scale;
176 _disp = (intptr_t) loc;
177 _rspec = spec;
178 _xmmindex = xnoreg;
179 _isxmmindex = false;
180 }
181
182 #endif // _LP64
183
184
185
186 // Convert the raw encoding form into the form expected by the constructor for
187 // Address. An index of 4 (rsp) corresponds to having no index, so convert
188 // that to noreg for the Address constructor.
189 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
190 RelocationHolder rspec = RelocationHolder::none;
191 if (disp_reloc != relocInfo::none) {
192 rspec = Relocation::spec_simple(disp_reloc);
193 }
194 bool valid_index = index != rsp->encoding();
195 if (valid_index) {
196 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
197 madr._rspec = rspec;
198 return madr;
199 } else {
200 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
201 madr._rspec = rspec;
202 return madr;
203 }
204 }
205
206 // Implementation of Assembler
207
208 int AbstractAssembler::code_fill_byte() {
209 return (u_char)'\xF4'; // hlt
210 }
211
212 void Assembler::init_attributes(void) {
213 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
214 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
215 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
216 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
217 NOT_LP64(_is_managed = false;)
218 _attributes = nullptr;
219 }
220
221 void Assembler::set_attributes(InstructionAttr* attributes) {
222 // Record the assembler in the attributes, so the attributes destructor can
223 // clear the assembler's attributes, cleaning up the otherwise dangling
224 // pointer. gcc13 has a false positive warning, because it doesn't tie that
225 // cleanup to the assignment of _attributes here.
226 attributes->set_current_assembler(this);
227 PRAGMA_DIAG_PUSH
228 PRAGMA_DANGLING_POINTER_IGNORED
229 _attributes = attributes;
230 PRAGMA_DIAG_POP
231 }
232
233 void Assembler::membar(Membar_mask_bits order_constraint) {
234 // We only have to handle StoreLoad
235 if (order_constraint & StoreLoad) {
236 // All usable chips support "locked" instructions which suffice
237 // as barriers, and are much faster than the alternative of
238 // using cpuid instruction. We use here a locked add [esp-C],0.
239 // This is conveniently otherwise a no-op except for blowing
240 // flags, and introducing a false dependency on target memory
241 // location. We can't do anything with flags, but we can avoid
242 // memory dependencies in the current method by locked-adding
243 // somewhere else on the stack. Doing [esp+C] will collide with
244 // something on stack in current method, hence we go for [esp-C].
245 // It is convenient since it is almost always in data cache, for
246 // any small C. We need to step back from SP to avoid data
247 // dependencies with other things on below SP (callee-saves, for
248 // example). Without a clear way to figure out the minimal safe
249 // distance from SP, it makes sense to step back the complete
250 // cache line, as this will also avoid possible second-order effects
251 // with locked ops against the cache line. Our choice of offset
252 // is bounded by x86 operand encoding, which should stay within
253 // [-128; +127] to have the 8-byte displacement encoding.
254 //
255 // Any change to this code may need to revisit other places in
256 // the code where this idiom is used, in particular the
257 // orderAccess code.
258
259 int offset = -VM_Version::L1_line_size();
260 if (offset < -128) {
261 offset = -128;
262 }
263
264 lock();
265 addl(Address(rsp, offset), 0);// Assert the lock# signal here
266 }
267 }
268
269 // make this go away someday
270 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
271 if (rtype == relocInfo::none)
272 emit_int32(data);
273 else
274 emit_data(data, Relocation::spec_simple(rtype), format);
275 }
276
277 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
278 assert(imm_operand == 0, "default format must be immediate in this file");
279 assert(inst_mark() != nullptr, "must be inside InstructionMark");
280 if (rspec.type() != relocInfo::none) {
281 #ifdef ASSERT
282 check_relocation(rspec, format);
283 #endif
284 // Do not use AbstractAssembler::relocate, which is not intended for
285 // embedded words. Instead, relocate to the enclosing instruction.
286
287 // hack. call32 is too wide for mask so use disp32
288 if (format == call32_operand)
289 code_section()->relocate(inst_mark(), rspec, disp32_operand);
290 else
291 code_section()->relocate(inst_mark(), rspec, format);
292 }
293 emit_int32(data);
294 }
295
296 static int encode(Register r) {
297 int enc = r->encoding();
298 if (enc >= 8) {
299 enc -= 8;
300 }
301 return enc;
302 }
303
304 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
305 assert(dst->has_byte_register(), "must have byte register");
306 assert(isByte(op1) && isByte(op2), "wrong opcode");
307 assert(isByte(imm8), "not a byte");
308 assert((op1 & 0x01) == 0, "should be 8bit operation");
309 emit_int24(op1, (op2 | encode(dst)), imm8);
310 }
311
312
313 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
314 assert(isByte(op1) && isByte(op2), "wrong opcode");
315 assert(op1 == 0x81, "Unexpected opcode");
316 if (is8bit(imm32)) {
317 emit_int24(op1 | 0x02, // set sign bit
318 op2 | encode(dst),
319 imm32 & 0xFF);
320 } else if (dst == rax) {
321 switch (op2) {
322 case 0xD0: emit_int8(0x15); break; // adc
323 case 0xC0: emit_int8(0x05); break; // add
324 case 0xE0: emit_int8(0x25); break; // and
325 case 0xF8: emit_int8(0x3D); break; // cmp
326 case 0xC8: emit_int8(0x0D); break; // or
327 case 0xD8: emit_int8(0x1D); break; // sbb
328 case 0xE8: emit_int8(0x2D); break; // sub
329 case 0xF0: emit_int8(0x35); break; // xor
330 default: ShouldNotReachHere();
331 }
332 emit_int32(imm32);
333 } else {
334 emit_int16(op1, (op2 | encode(dst)));
335 emit_int32(imm32);
336 }
337 }
338
339 // Force generation of a 4 byte immediate value even if it fits into 8bit
340 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
341 assert(isByte(op1) && isByte(op2), "wrong opcode");
342 assert((op1 & 0x01) == 1, "should be 32bit operation");
343 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
344 emit_int16(op1, (op2 | encode(dst)));
345 emit_int32(imm32);
346 }
347
348 // immediate-to-memory forms
349 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
350 assert((op1 & 0x01) == 1, "should be 32bit operation");
351 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
352 if (is8bit(imm32)) {
353 emit_int8(op1 | 0x02); // set sign bit
354 emit_operand(rm, adr, 1);
355 emit_int8(imm32 & 0xFF);
356 } else {
357 emit_int8(op1);
358 emit_operand(rm, adr, 4);
359 emit_int32(imm32);
360 }
361 }
362
363 void Assembler::emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32) {
364 assert(op1 == 0x81, "unexpected opcode");
365 emit_int8(op1);
366 emit_operand(rm, adr, 4);
367 emit_int32(imm32);
368 }
369
370 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
371 assert(isByte(op1) && isByte(op2), "wrong opcode");
372 emit_int16(op1, (op2 | encode(dst) << 3 | encode(src)));
373 }
374
375
376 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
377 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
378 int mod_idx = 0;
379 // We will test if the displacement fits the compressed format and if so
380 // apply the compression to the displacement iff the result is8bit.
381 if (VM_Version::supports_evex() && is_evex_inst) {
382 switch (cur_tuple_type) {
383 case EVEX_FV:
384 if ((cur_encoding & VEX_W) == VEX_W) {
385 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
386 } else {
387 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
388 }
389 break;
390
391 case EVEX_HV:
392 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
393 break;
394
395 case EVEX_FVM:
396 break;
397
398 case EVEX_T1S:
399 switch (in_size_in_bits) {
400 case EVEX_8bit:
401 break;
402
403 case EVEX_16bit:
404 mod_idx = 1;
405 break;
406
407 case EVEX_32bit:
408 mod_idx = 2;
409 break;
410
411 case EVEX_64bit:
412 mod_idx = 3;
413 break;
414 }
415 break;
416
417 case EVEX_T1F:
418 case EVEX_T2:
419 case EVEX_T4:
420 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
421 break;
422
423 case EVEX_T8:
424 break;
425
426 case EVEX_HVM:
427 break;
428
429 case EVEX_QVM:
430 break;
431
432 case EVEX_OVM:
433 break;
434
435 case EVEX_M128:
436 break;
437
438 case EVEX_DUP:
439 break;
440
441 default:
442 assert(0, "no valid evex tuple_table entry");
443 break;
444 }
445
446 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
447 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
448 if ((disp % disp_factor) == 0) {
449 int new_disp = disp / disp_factor;
450 if ((-0x80 <= new_disp && new_disp < 0x80)) {
451 disp = new_disp;
452 }
453 } else {
454 return false;
455 }
456 }
457 }
458 return (-0x80 <= disp && disp < 0x80);
459 }
460
461
462 bool Assembler::emit_compressed_disp_byte(int &disp) {
463 int mod_idx = 0;
464 // We will test if the displacement fits the compressed format and if so
465 // apply the compression to the displacement iff the result is8bit.
466 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
467 int evex_encoding = _attributes->get_evex_encoding();
468 int tuple_type = _attributes->get_tuple_type();
469 switch (tuple_type) {
470 case EVEX_FV:
471 if ((evex_encoding & VEX_W) == VEX_W) {
472 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
473 } else {
474 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
475 }
476 break;
477
478 case EVEX_HV:
479 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
480 break;
481
482 case EVEX_FVM:
483 break;
484
485 case EVEX_T1S:
486 switch (_attributes->get_input_size()) {
487 case EVEX_8bit:
488 break;
489
490 case EVEX_16bit:
491 mod_idx = 1;
492 break;
493
494 case EVEX_32bit:
495 mod_idx = 2;
496 break;
497
498 case EVEX_64bit:
499 mod_idx = 3;
500 break;
501 }
502 break;
503
504 case EVEX_T1F:
505 case EVEX_T2:
506 case EVEX_T4:
507 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
508 break;
509
510 case EVEX_T8:
511 break;
512
513 case EVEX_HVM:
514 break;
515
516 case EVEX_QVM:
517 break;
518
519 case EVEX_OVM:
520 break;
521
522 case EVEX_M128:
523 break;
524
525 case EVEX_DUP:
526 break;
527
528 default:
529 assert(0, "no valid evex tuple_table entry");
530 break;
531 }
532
533 int vector_len = _attributes->get_vector_len();
534 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
535 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
536 if ((disp % disp_factor) == 0) {
537 int new_disp = disp / disp_factor;
538 if (is8bit(new_disp)) {
539 disp = new_disp;
540 }
541 } else {
542 return false;
543 }
544 }
545 }
546 return is8bit(disp);
547 }
548
549 static bool is_valid_encoding(int reg_enc) {
550 return reg_enc >= 0;
551 }
552
553 static int raw_encode(Register reg) {
554 assert(reg == noreg || reg->is_valid(), "sanity");
555 int reg_enc = reg->raw_encoding();
556 assert(reg_enc == -1 || is_valid_encoding(reg_enc), "sanity");
557 return reg_enc;
558 }
559
560 static int raw_encode(XMMRegister xmmreg) {
561 assert(xmmreg == xnoreg || xmmreg->is_valid(), "sanity");
562 int xmmreg_enc = xmmreg->raw_encoding();
563 assert(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc), "sanity");
564 return xmmreg_enc;
565 }
566
567 static int raw_encode(KRegister kreg) {
568 assert(kreg == knoreg || kreg->is_valid(), "sanity");
569 int kreg_enc = kreg->raw_encoding();
570 assert(kreg_enc == -1 || is_valid_encoding(kreg_enc), "sanity");
571 return kreg_enc;
572 }
573
574 static int modrm_encoding(int mod, int dst_enc, int src_enc) {
575 return (mod & 3) << 6 | (dst_enc & 7) << 3 | (src_enc & 7);
576 }
577
578 static int sib_encoding(Address::ScaleFactor scale, int index_enc, int base_enc) {
579 return (scale & 3) << 6 | (index_enc & 7) << 3 | (base_enc & 7);
580 }
581
582 inline void Assembler::emit_modrm(int mod, int dst_enc, int src_enc) {
583 assert((mod & 3) != 0b11, "forbidden");
584 int modrm = modrm_encoding(mod, dst_enc, src_enc);
585 emit_int8(modrm);
586 }
587
588 inline void Assembler::emit_modrm_disp8(int mod, int dst_enc, int src_enc,
589 int disp) {
590 int modrm = modrm_encoding(mod, dst_enc, src_enc);
591 emit_int16(modrm, disp & 0xFF);
592 }
593
594 inline void Assembler::emit_modrm_sib(int mod, int dst_enc, int src_enc,
595 Address::ScaleFactor scale, int index_enc, int base_enc) {
596 int modrm = modrm_encoding(mod, dst_enc, src_enc);
597 int sib = sib_encoding(scale, index_enc, base_enc);
598 emit_int16(modrm, sib);
599 }
600
601 inline void Assembler::emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
602 Address::ScaleFactor scale, int index_enc, int base_enc,
603 int disp) {
604 int modrm = modrm_encoding(mod, dst_enc, src_enc);
605 int sib = sib_encoding(scale, index_enc, base_enc);
606 emit_int24(modrm, sib, disp & 0xFF);
607 }
608
609 void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc,
610 Address::ScaleFactor scale, int disp,
611 RelocationHolder const& rspec,
612 int post_addr_length) {
613 bool no_relocation = (rspec.type() == relocInfo::none);
614
615 if (is_valid_encoding(base_enc)) {
616 if (is_valid_encoding(index_enc)) {
617 assert(scale != Address::no_scale, "inconsistent address");
618 // [base + index*scale + disp]
619 if (disp == 0 && no_relocation &&
620 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
621 // [base + index*scale]
622 // [00 reg 100][ss index base]
623 emit_modrm_sib(0b00, reg_enc, 0b100,
624 scale, index_enc, base_enc);
625 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
626 // [base + index*scale + imm8]
627 // [01 reg 100][ss index base] imm8
628 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
629 scale, index_enc, base_enc,
630 disp);
631 } else {
632 // [base + index*scale + disp32]
633 // [10 reg 100][ss index base] disp32
634 emit_modrm_sib(0b10, reg_enc, 0b100,
635 scale, index_enc, base_enc);
636 emit_data(disp, rspec, disp32_operand);
637 }
638 } else if (base_enc == rsp->encoding() LP64_ONLY(|| base_enc == r12->encoding())) {
639 // [rsp + disp]
640 if (disp == 0 && no_relocation) {
641 // [rsp]
642 // [00 reg 100][00 100 100]
643 emit_modrm_sib(0b00, reg_enc, 0b100,
644 Address::times_1, 0b100, 0b100);
645 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
646 // [rsp + imm8]
647 // [01 reg 100][00 100 100] disp8
648 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
649 Address::times_1, 0b100, 0b100,
650 disp);
651 } else {
652 // [rsp + imm32]
653 // [10 reg 100][00 100 100] disp32
654 emit_modrm_sib(0b10, reg_enc, 0b100,
655 Address::times_1, 0b100, 0b100);
656 emit_data(disp, rspec, disp32_operand);
657 }
658 } else {
659 // [base + disp]
660 assert(base_enc != rsp->encoding() LP64_ONLY(&& base_enc != r12->encoding()), "illegal addressing mode");
661 if (disp == 0 && no_relocation &&
662 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
663 // [base]
664 // [00 reg base]
665 emit_modrm(0, reg_enc, base_enc);
666 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
667 // [base + disp8]
668 // [01 reg base] disp8
669 emit_modrm_disp8(0b01, reg_enc, base_enc,
670 disp);
671 } else {
672 // [base + disp32]
673 // [10 reg base] disp32
674 emit_modrm(0b10, reg_enc, base_enc);
675 emit_data(disp, rspec, disp32_operand);
676 }
677 }
678 } else {
679 if (is_valid_encoding(index_enc)) {
680 assert(scale != Address::no_scale, "inconsistent address");
681 // base == noreg
682 // [index*scale + disp]
683 // [00 reg 100][ss index 101] disp32
684 emit_modrm_sib(0b00, reg_enc, 0b100,
685 scale, index_enc, 0b101 /* no base */);
686 emit_data(disp, rspec, disp32_operand);
687 } else if (!no_relocation) {
688 // base == noreg, index == noreg
689 // [disp] (64bit) RIP-RELATIVE (32bit) abs
690 // [00 reg 101] disp32
691
692 emit_modrm(0b00, reg_enc, 0b101 /* no base */);
693 // Note that the RIP-rel. correction applies to the generated
694 // disp field, but _not_ to the target address in the rspec.
695
696 // disp was created by converting the target address minus the pc
697 // at the start of the instruction. That needs more correction here.
698 // intptr_t disp = target - next_ip;
699 assert(inst_mark() != nullptr, "must be inside InstructionMark");
700 address next_ip = pc() + sizeof(int32_t) + post_addr_length;
701 int64_t adjusted = disp;
702 // Do rip-rel adjustment for 64bit
703 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
704 assert(is_simm32(adjusted),
705 "must be 32bit offset (RIP relative address)");
706 emit_data((int32_t) adjusted, rspec, disp32_operand);
707
708 } else {
709 // base == noreg, index == noreg, no_relocation == true
710 // 32bit never did this, did everything as the rip-rel/disp code above
711 // [disp] ABSOLUTE
712 // [00 reg 100][00 100 101] disp32
713 emit_modrm_sib(0b00, reg_enc, 0b100 /* no base */,
714 Address::times_1, 0b100, 0b101);
715 emit_data(disp, rspec, disp32_operand);
716 }
717 }
718 }
719
720 void Assembler::emit_operand(Register reg, Register base, Register index,
721 Address::ScaleFactor scale, int disp,
722 RelocationHolder const& rspec,
723 int post_addr_length) {
724 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
725 emit_operand_helper(raw_encode(reg), raw_encode(base), raw_encode(index),
726 scale, disp, rspec, post_addr_length);
727
728 }
729 void Assembler::emit_operand(XMMRegister xmmreg, Register base, Register index,
730 Address::ScaleFactor scale, int disp,
731 RelocationHolder const& rspec,
732 int post_addr_length) {
733 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
734 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
735 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(index),
736 scale, disp, rspec, post_addr_length);
737 }
738
739 void Assembler::emit_operand(XMMRegister xmmreg, Register base, XMMRegister xmmindex,
740 Address::ScaleFactor scale, int disp,
741 RelocationHolder const& rspec,
742 int post_addr_length) {
743 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
744 assert(xmmindex->encoding() < 16 || UseAVX > 2, "not supported");
745 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(xmmindex),
746 scale, disp, rspec, post_addr_length);
747 }
748
749 void Assembler::emit_operand(KRegister kreg, Address adr,
750 int post_addr_length) {
751 emit_operand(kreg, adr._base, adr._index, adr._scale, adr._disp,
752 adr._rspec,
753 post_addr_length);
754 }
755
756 void Assembler::emit_operand(KRegister kreg, Register base, Register index,
757 Address::ScaleFactor scale, int disp,
758 RelocationHolder const& rspec,
759 int post_addr_length) {
760 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
761 emit_operand_helper(raw_encode(kreg), raw_encode(base), raw_encode(index),
762 scale, disp, rspec, post_addr_length);
763 }
764
765 // Secret local extension to Assembler::WhichOperand:
766 #define end_pc_operand (_WhichOperand_limit)
767
768 address Assembler::locate_operand(address inst, WhichOperand which) {
769 // Decode the given instruction, and return the address of
770 // an embedded 32-bit operand word.
771
772 // If "which" is disp32_operand, selects the displacement portion
773 // of an effective address specifier.
774 // If "which" is imm64_operand, selects the trailing immediate constant.
775 // If "which" is call32_operand, selects the displacement of a call or jump.
776 // Caller is responsible for ensuring that there is such an operand,
777 // and that it is 32/64 bits wide.
778
779 // If "which" is end_pc_operand, find the end of the instruction.
780
781 address ip = inst;
782 bool is_64bit = false;
783
784 debug_only(bool has_disp32 = false);
785 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
786
787 again_after_prefix:
788 switch (0xFF & *ip++) {
789
790 // These convenience macros generate groups of "case" labels for the switch.
791 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
792 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
793 case (x)+4: case (x)+5: case (x)+6: case (x)+7
794 #define REP16(x) REP8((x)+0): \
795 case REP8((x)+8)
796
797 case CS_segment:
798 case SS_segment:
799 case DS_segment:
800 case ES_segment:
801 case FS_segment:
802 case GS_segment:
803 // Seems dubious
804 LP64_ONLY(assert(false, "shouldn't have that prefix"));
805 assert(ip == inst+1, "only one prefix allowed");
806 goto again_after_prefix;
807
808 case 0x67:
809 case REX:
810 case REX_B:
811 case REX_X:
812 case REX_XB:
813 case REX_R:
814 case REX_RB:
815 case REX_RX:
816 case REX_RXB:
817 NOT_LP64(assert(false, "64bit prefixes"));
818 goto again_after_prefix;
819
820 case REX_W:
821 case REX_WB:
822 case REX_WX:
823 case REX_WXB:
824 case REX_WR:
825 case REX_WRB:
826 case REX_WRX:
827 case REX_WRXB:
828 NOT_LP64(assert(false, "64bit prefixes"));
829 is_64bit = true;
830 goto again_after_prefix;
831
832 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
833 case 0x88: // movb a, r
834 case 0x89: // movl a, r
835 case 0x8A: // movb r, a
836 case 0x8B: // movl r, a
837 case 0x8F: // popl a
838 debug_only(has_disp32 = true);
839 break;
840
841 case 0x68: // pushq #32
842 if (which == end_pc_operand) {
843 return ip + 4;
844 }
845 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
846 return ip; // not produced by emit_operand
847
848 case 0x66: // movw ... (size prefix)
849 again_after_size_prefix2:
850 switch (0xFF & *ip++) {
851 case REX:
852 case REX_B:
853 case REX_X:
854 case REX_XB:
855 case REX_R:
856 case REX_RB:
857 case REX_RX:
858 case REX_RXB:
859 case REX_W:
860 case REX_WB:
861 case REX_WX:
862 case REX_WXB:
863 case REX_WR:
864 case REX_WRB:
865 case REX_WRX:
866 case REX_WRXB:
867 NOT_LP64(assert(false, "64bit prefix found"));
868 goto again_after_size_prefix2;
869 case 0x8B: // movw r, a
870 case 0x89: // movw a, r
871 debug_only(has_disp32 = true);
872 break;
873 case 0xC7: // movw a, #16
874 debug_only(has_disp32 = true);
875 tail_size = 2; // the imm16
876 break;
877 case 0x0F: // several SSE/SSE2 variants
878 ip--; // reparse the 0x0F
879 goto again_after_prefix;
880 default:
881 ShouldNotReachHere();
882 }
883 break;
884
885 case REP8(0xB8): // movl/q r, #32/#64(oop?)
886 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
887 // these asserts are somewhat nonsensical
888 #ifndef _LP64
889 assert(which == imm_operand || which == disp32_operand,
890 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
891 #else
892 assert((which == call32_operand || which == imm_operand) && is_64bit ||
893 which == narrow_oop_operand && !is_64bit,
894 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
895 #endif // _LP64
896 return ip;
897
898 case 0x69: // imul r, a, #32
899 case 0xC7: // movl a, #32(oop?)
900 tail_size = 4;
901 debug_only(has_disp32 = true); // has both kinds of operands!
902 break;
903
904 case 0x0F: // movx..., etc.
905 switch (0xFF & *ip++) {
906 case 0x3A: // pcmpestri
907 tail_size = 1;
908 case 0x38: // ptest, pmovzxbw
909 ip++; // skip opcode
910 debug_only(has_disp32 = true); // has both kinds of operands!
911 break;
912
913 case 0x70: // pshufd r, r/a, #8
914 debug_only(has_disp32 = true); // has both kinds of operands!
915 case 0x73: // psrldq r, #8
916 tail_size = 1;
917 break;
918
919 case 0x10: // movups
920 case 0x11: // movups
921 case 0x12: // movlps
922 case 0x28: // movaps
923 case 0x2E: // ucomiss
924 case 0x2F: // comiss
925 case 0x54: // andps
926 case 0x55: // andnps
927 case 0x56: // orps
928 case 0x57: // xorps
929 case 0x58: // addpd
930 case 0x59: // mulpd
931 case 0x6E: // movd
932 case 0x7E: // movd
933 case 0x6F: // movdq
934 case 0x7F: // movdq
935 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
936 case 0xFE: // paddd
937 debug_only(has_disp32 = true);
938 break;
939
940 case 0xAD: // shrd r, a, %cl
941 case 0xAF: // imul r, a
942 case 0xBE: // movsbl r, a (movsxb)
943 case 0xBF: // movswl r, a (movsxw)
944 case 0xB6: // movzbl r, a (movzxb)
945 case 0xB7: // movzwl r, a (movzxw)
946 case REP16(0x40): // cmovl cc, r, a
947 case 0xB0: // cmpxchgb
948 case 0xB1: // cmpxchg
949 case 0xC1: // xaddl
950 case 0xC7: // cmpxchg8
951 case REP16(0x90): // setcc a
952 debug_only(has_disp32 = true);
953 // fall out of the switch to decode the address
954 break;
955
956 case 0xC4: // pinsrw r, a, #8
957 debug_only(has_disp32 = true);
958 case 0xC5: // pextrw r, r, #8
959 tail_size = 1; // the imm8
960 break;
961
962 case 0xAC: // shrd r, a, #8
963 debug_only(has_disp32 = true);
964 tail_size = 1; // the imm8
965 break;
966
967 case REP16(0x80): // jcc rdisp32
968 if (which == end_pc_operand) return ip + 4;
969 assert(which == call32_operand, "jcc has no disp32 or imm");
970 return ip;
971 default:
972 ShouldNotReachHere();
973 }
974 break;
975
976 case 0x81: // addl a, #32; addl r, #32
977 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
978 // on 32bit in the case of cmpl, the imm might be an oop
979 tail_size = 4;
980 debug_only(has_disp32 = true); // has both kinds of operands!
981 break;
982
983 case 0x83: // addl a, #8; addl r, #8
984 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
985 debug_only(has_disp32 = true); // has both kinds of operands!
986 tail_size = 1;
987 break;
988
989 case 0x15: // adc rax, #32
990 case 0x05: // add rax, #32
991 case 0x25: // and rax, #32
992 case 0x3D: // cmp rax, #32
993 case 0x0D: // or rax, #32
994 case 0x1D: // sbb rax, #32
995 case 0x2D: // sub rax, #32
996 case 0x35: // xor rax, #32
997 return which == end_pc_operand ? ip + 4 : ip;
998
999 case 0x9B:
1000 switch (0xFF & *ip++) {
1001 case 0xD9: // fnstcw a
1002 debug_only(has_disp32 = true);
1003 break;
1004 default:
1005 ShouldNotReachHere();
1006 }
1007 break;
1008
1009 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
1010 case REP4(0x10): // adc...
1011 case REP4(0x20): // and...
1012 case REP4(0x30): // xor...
1013 case REP4(0x08): // or...
1014 case REP4(0x18): // sbb...
1015 case REP4(0x28): // sub...
1016 case 0xF7: // mull a
1017 case 0x8D: // lea r, a
1018 case 0x87: // xchg r, a
1019 case REP4(0x38): // cmp...
1020 case 0x85: // test r, a
1021 debug_only(has_disp32 = true); // has both kinds of operands!
1022 break;
1023
1024 case 0xA8: // testb rax, #8
1025 return which == end_pc_operand ? ip + 1 : ip;
1026 case 0xA9: // testl/testq rax, #32
1027 return which == end_pc_operand ? ip + 4 : ip;
1028
1029 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
1030 case 0xC6: // movb a, #8
1031 case 0x80: // cmpb a, #8
1032 case 0x6B: // imul r, a, #8
1033 debug_only(has_disp32 = true); // has both kinds of operands!
1034 tail_size = 1; // the imm8
1035 break;
1036
1037 case 0xC4: // VEX_3bytes
1038 case 0xC5: // VEX_2bytes
1039 assert((UseAVX > 0), "shouldn't have VEX prefix");
1040 assert(ip == inst+1, "no prefixes allowed");
1041 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
1042 // but they have prefix 0x0F and processed when 0x0F processed above.
1043 //
1044 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
1045 // instructions (these instructions are not supported in 64-bit mode).
1046 // To distinguish them bits [7:6] are set in the VEX second byte since
1047 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
1048 // those VEX bits REX and vvvv bits are inverted.
1049 //
1050 // Fortunately C2 doesn't generate these instructions so we don't need
1051 // to check for them in product version.
1052
1053 // Check second byte
1054 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
1055
1056 int vex_opcode;
1057 // First byte
1058 if ((0xFF & *inst) == VEX_3bytes) {
1059 vex_opcode = VEX_OPCODE_MASK & *ip;
1060 ip++; // third byte
1061 is_64bit = ((VEX_W & *ip) == VEX_W);
1062 } else {
1063 vex_opcode = VEX_OPCODE_0F;
1064 }
1065 ip++; // opcode
1066 // To find the end of instruction (which == end_pc_operand).
1067 switch (vex_opcode) {
1068 case VEX_OPCODE_0F:
1069 switch (0xFF & *ip) {
1070 case 0x70: // pshufd r, r/a, #8
1071 case 0x71: // ps[rl|ra|ll]w r, #8
1072 case 0x72: // ps[rl|ra|ll]d r, #8
1073 case 0x73: // ps[rl|ra|ll]q r, #8
1074 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
1075 case 0xC4: // pinsrw r, r, r/a, #8
1076 case 0xC5: // pextrw r/a, r, #8
1077 case 0xC6: // shufp[s|d] r, r, r/a, #8
1078 tail_size = 1; // the imm8
1079 break;
1080 }
1081 break;
1082 case VEX_OPCODE_0F_3A:
1083 tail_size = 1;
1084 break;
1085 }
1086 ip++; // skip opcode
1087 debug_only(has_disp32 = true); // has both kinds of operands!
1088 break;
1089
1090 case 0x62: // EVEX_4bytes
1091 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
1092 assert(ip == inst+1, "no prefixes allowed");
1093 // no EVEX collisions, all instructions that have 0x62 opcodes
1094 // have EVEX versions and are subopcodes of 0x66
1095 ip++; // skip P0 and examine W in P1
1096 is_64bit = ((VEX_W & *ip) == VEX_W);
1097 ip++; // move to P2
1098 ip++; // skip P2, move to opcode
1099 // To find the end of instruction (which == end_pc_operand).
1100 switch (0xFF & *ip) {
1101 case 0x22: // pinsrd r, r/a, #8
1102 case 0x61: // pcmpestri r, r/a, #8
1103 case 0x70: // pshufd r, r/a, #8
1104 case 0x73: // psrldq r, #8
1105 case 0x1f: // evpcmpd/evpcmpq
1106 case 0x3f: // evpcmpb/evpcmpw
1107 tail_size = 1; // the imm8
1108 break;
1109 default:
1110 break;
1111 }
1112 ip++; // skip opcode
1113 debug_only(has_disp32 = true); // has both kinds of operands!
1114 break;
1115
1116 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
1117 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
1118 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
1119 case 0xDD: // fld_d a; fst_d a; fstp_d a
1120 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
1121 case 0xDF: // fild_d a; fistp_d a
1122 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
1123 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
1124 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
1125 debug_only(has_disp32 = true);
1126 break;
1127
1128 case 0xE8: // call rdisp32
1129 case 0xE9: // jmp rdisp32
1130 if (which == end_pc_operand) return ip + 4;
1131 assert(which == call32_operand, "call has no disp32 or imm");
1132 return ip;
1133
1134 case 0xF0: // Lock
1135 goto again_after_prefix;
1136
1137 case 0xF3: // For SSE
1138 case 0xF2: // For SSE2
1139 switch (0xFF & *ip++) {
1140 case REX:
1141 case REX_B:
1142 case REX_X:
1143 case REX_XB:
1144 case REX_R:
1145 case REX_RB:
1146 case REX_RX:
1147 case REX_RXB:
1148 case REX_W:
1149 case REX_WB:
1150 case REX_WX:
1151 case REX_WXB:
1152 case REX_WR:
1153 case REX_WRB:
1154 case REX_WRX:
1155 case REX_WRXB:
1156 NOT_LP64(assert(false, "found 64bit prefix"));
1157 ip++;
1158 default:
1159 ip++;
1160 }
1161 debug_only(has_disp32 = true); // has both kinds of operands!
1162 break;
1163
1164 default:
1165 ShouldNotReachHere();
1166
1167 #undef REP8
1168 #undef REP16
1169 }
1170
1171 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1172 #ifdef _LP64
1173 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1174 #else
1175 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1176 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1177 #endif // LP64
1178 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1179
1180 // parse the output of emit_operand
1181 int op2 = 0xFF & *ip++;
1182 int base = op2 & 0x07;
1183 int op3 = -1;
1184 const int b100 = 4;
1185 const int b101 = 5;
1186 if (base == b100 && (op2 >> 6) != 3) {
1187 op3 = 0xFF & *ip++;
1188 base = op3 & 0x07; // refetch the base
1189 }
1190 // now ip points at the disp (if any)
1191
1192 switch (op2 >> 6) {
1193 case 0:
1194 // [00 reg 100][ss index base]
1195 // [00 reg 100][00 100 esp]
1196 // [00 reg base]
1197 // [00 reg 100][ss index 101][disp32]
1198 // [00 reg 101] [disp32]
1199
1200 if (base == b101) {
1201 if (which == disp32_operand)
1202 return ip; // caller wants the disp32
1203 ip += 4; // skip the disp32
1204 }
1205 break;
1206
1207 case 1:
1208 // [01 reg 100][ss index base][disp8]
1209 // [01 reg 100][00 100 esp][disp8]
1210 // [01 reg base] [disp8]
1211 ip += 1; // skip the disp8
1212 break;
1213
1214 case 2:
1215 // [10 reg 100][ss index base][disp32]
1216 // [10 reg 100][00 100 esp][disp32]
1217 // [10 reg base] [disp32]
1218 if (which == disp32_operand)
1219 return ip; // caller wants the disp32
1220 ip += 4; // skip the disp32
1221 break;
1222
1223 case 3:
1224 // [11 reg base] (not a memory addressing mode)
1225 break;
1226 }
1227
1228 if (which == end_pc_operand) {
1229 return ip + tail_size;
1230 }
1231
1232 #ifdef _LP64
1233 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1234 #else
1235 assert(which == imm_operand, "instruction has only an imm field");
1236 #endif // LP64
1237 return ip;
1238 }
1239
1240 address Assembler::locate_next_instruction(address inst) {
1241 // Secretly share code with locate_operand:
1242 return locate_operand(inst, end_pc_operand);
1243 }
1244
1245
1246 #ifdef ASSERT
1247 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1248 address inst = inst_mark();
1249 assert(inst != nullptr && inst < pc(), "must point to beginning of instruction");
1250 address opnd;
1251
1252 Relocation* r = rspec.reloc();
1253 if (r->type() == relocInfo::none) {
1254 return;
1255 } else if (r->is_call() || format == call32_operand) {
1256 // assert(format == imm32_operand, "cannot specify a nonzero format");
1257 opnd = locate_operand(inst, call32_operand);
1258 } else if (r->is_data()) {
1259 assert(format == imm_operand || format == disp32_operand
1260 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1261 opnd = locate_operand(inst, (WhichOperand)format);
1262 } else {
1263 assert(format == imm_operand, "cannot specify a format");
1264 return;
1265 }
1266 assert(opnd == pc(), "must put operand where relocs can find it");
1267 }
1268 #endif // ASSERT
1269
1270 void Assembler::emit_operand(Register reg, Address adr, int post_addr_length) {
1271 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1272 }
1273
1274 void Assembler::emit_operand(XMMRegister reg, Address adr, int post_addr_length) {
1275 if (adr.isxmmindex()) {
1276 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec, post_addr_length);
1277 } else {
1278 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1279 }
1280 }
1281
1282 // Now the Assembler instructions (identical for 32/64 bits)
1283
1284 void Assembler::adcl(Address dst, int32_t imm32) {
1285 InstructionMark im(this);
1286 prefix(dst);
1287 emit_arith_operand(0x81, rdx, dst, imm32);
1288 }
1289
1290 void Assembler::adcl(Address dst, Register src) {
1291 InstructionMark im(this);
1292 prefix(dst, src);
1293 emit_int8(0x11);
1294 emit_operand(src, dst, 0);
1295 }
1296
1297 void Assembler::adcl(Register dst, int32_t imm32) {
1298 prefix(dst);
1299 emit_arith(0x81, 0xD0, dst, imm32);
1300 }
1301
1302 void Assembler::adcl(Register dst, Address src) {
1303 InstructionMark im(this);
1304 prefix(src, dst);
1305 emit_int8(0x13);
1306 emit_operand(dst, src, 0);
1307 }
1308
1309 void Assembler::adcl(Register dst, Register src) {
1310 (void) prefix_and_encode(dst->encoding(), src->encoding());
1311 emit_arith(0x13, 0xC0, dst, src);
1312 }
1313
1314 void Assembler::addl(Address dst, int32_t imm32) {
1315 InstructionMark im(this);
1316 prefix(dst);
1317 emit_arith_operand(0x81, rax, dst, imm32);
1318 }
1319
1320 void Assembler::addb(Address dst, int imm8) {
1321 InstructionMark im(this);
1322 prefix(dst);
1323 emit_int8((unsigned char)0x80);
1324 emit_operand(rax, dst, 1);
1325 emit_int8(imm8);
1326 }
1327
1328 void Assembler::addb(Address dst, Register src) {
1329 InstructionMark im(this);
1330 prefix(dst, src);
1331 emit_int8(0x00);
1332 emit_operand(src, dst, 0);
1333 }
1334
1335 void Assembler::addb(Register dst, int imm8) {
1336 (void) prefix_and_encode(dst->encoding(), true);
1337 emit_arith_b(0x80, 0xC0, dst, imm8);
1338 }
1339
1340 void Assembler::addw(Register dst, Register src) {
1341 emit_int8(0x66);
1342 (void)prefix_and_encode(dst->encoding(), src->encoding());
1343 emit_arith(0x03, 0xC0, dst, src);
1344 }
1345
1346 void Assembler::addw(Address dst, int imm16) {
1347 InstructionMark im(this);
1348 emit_int8(0x66);
1349 prefix(dst);
1350 emit_int8((unsigned char)0x81);
1351 emit_operand(rax, dst, 2);
1352 emit_int16(imm16);
1353 }
1354
1355 void Assembler::addw(Address dst, Register src) {
1356 InstructionMark im(this);
1357 emit_int8(0x66);
1358 prefix(dst, src);
1359 emit_int8(0x01);
1360 emit_operand(src, dst, 0);
1361 }
1362
1363 void Assembler::addl(Address dst, Register src) {
1364 InstructionMark im(this);
1365 prefix(dst, src);
1366 emit_int8(0x01);
1367 emit_operand(src, dst, 0);
1368 }
1369
1370 void Assembler::addl(Register dst, int32_t imm32) {
1371 prefix(dst);
1372 emit_arith(0x81, 0xC0, dst, imm32);
1373 }
1374
1375 void Assembler::addl(Register dst, Address src) {
1376 InstructionMark im(this);
1377 prefix(src, dst);
1378 emit_int8(0x03);
1379 emit_operand(dst, src, 0);
1380 }
1381
1382 void Assembler::addl(Register dst, Register src) {
1383 (void) prefix_and_encode(dst->encoding(), src->encoding());
1384 emit_arith(0x03, 0xC0, dst, src);
1385 }
1386
1387 void Assembler::addr_nop_4() {
1388 assert(UseAddressNop, "no CPU support");
1389 // 4 bytes: NOP DWORD PTR [EAX+0]
1390 emit_int32(0x0F,
1391 0x1F,
1392 0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1393 0); // 8-bits offset (1 byte)
1394 }
1395
1396 void Assembler::addr_nop_5() {
1397 assert(UseAddressNop, "no CPU support");
1398 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1399 emit_int32(0x0F,
1400 0x1F,
1401 0x44, // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1402 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1403 emit_int8(0); // 8-bits offset (1 byte)
1404 }
1405
1406 void Assembler::addr_nop_7() {
1407 assert(UseAddressNop, "no CPU support");
1408 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1409 emit_int24(0x0F,
1410 0x1F,
1411 (unsigned char)0x80);
1412 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1413 emit_int32(0); // 32-bits offset (4 bytes)
1414 }
1415
1416 void Assembler::addr_nop_8() {
1417 assert(UseAddressNop, "no CPU support");
1418 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1419 emit_int32(0x0F,
1420 0x1F,
1421 (unsigned char)0x84,
1422 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1423 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1424 emit_int32(0); // 32-bits offset (4 bytes)
1425 }
1426
1427 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1428 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1429 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1430 attributes.set_rex_vex_w_reverted();
1431 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1432 emit_int16(0x58, (0xC0 | encode));
1433 }
1434
1435 void Assembler::addsd(XMMRegister dst, Address src) {
1436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1437 InstructionMark im(this);
1438 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1439 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1440 attributes.set_rex_vex_w_reverted();
1441 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1442 emit_int8(0x58);
1443 emit_operand(dst, src, 0);
1444 }
1445
1446 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1447 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1449 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1450 emit_int16(0x58, (0xC0 | encode));
1451 }
1452
1453 void Assembler::addss(XMMRegister dst, Address src) {
1454 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1455 InstructionMark im(this);
1456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1457 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1458 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1459 emit_int8(0x58);
1460 emit_operand(dst, src, 0);
1461 }
1462
1463 void Assembler::aesdec(XMMRegister dst, Address src) {
1464 assert(VM_Version::supports_aes(), "");
1465 InstructionMark im(this);
1466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1467 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1468 emit_int8((unsigned char)0xDE);
1469 emit_operand(dst, src, 0);
1470 }
1471
1472 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1473 assert(VM_Version::supports_aes(), "");
1474 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1475 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1476 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1477 }
1478
1479 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1480 assert(VM_Version::supports_avx512_vaes(), "");
1481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1482 attributes.set_is_evex_instruction();
1483 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1484 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1485 }
1486
1487
1488 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1489 assert(VM_Version::supports_aes(), "");
1490 InstructionMark im(this);
1491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1492 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1493 emit_int8((unsigned char)0xDF);
1494 emit_operand(dst, src, 0);
1495 }
1496
1497 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1498 assert(VM_Version::supports_aes(), "");
1499 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1501 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1502 }
1503
1504 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1505 assert(VM_Version::supports_avx512_vaes(), "");
1506 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1507 attributes.set_is_evex_instruction();
1508 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1509 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1510 }
1511
1512 void Assembler::aesenc(XMMRegister dst, Address src) {
1513 assert(VM_Version::supports_aes(), "");
1514 InstructionMark im(this);
1515 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1516 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1517 emit_int8((unsigned char)0xDC);
1518 emit_operand(dst, src, 0);
1519 }
1520
1521 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1522 assert(VM_Version::supports_aes(), "");
1523 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1524 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1525 emit_int16((unsigned char)0xDC, 0xC0 | encode);
1526 }
1527
1528 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1529 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1530 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1531 attributes.set_is_evex_instruction();
1532 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1533 emit_int16((unsigned char)0xDC, (0xC0 | encode));
1534 }
1535
1536 void Assembler::aesenclast(XMMRegister dst, Address src) {
1537 assert(VM_Version::supports_aes(), "");
1538 InstructionMark im(this);
1539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1540 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1541 emit_int8((unsigned char)0xDD);
1542 emit_operand(dst, src, 0);
1543 }
1544
1545 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1546 assert(VM_Version::supports_aes(), "");
1547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1548 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1549 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1550 }
1551
1552 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1553 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1555 attributes.set_is_evex_instruction();
1556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1557 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1558 }
1559
1560 void Assembler::andb(Address dst, Register src) {
1561 InstructionMark im(this);
1562 prefix(dst, src, true);
1563 emit_int8(0x20);
1564 emit_operand(src, dst, 0);
1565 }
1566
1567 void Assembler::andw(Register dst, Register src) {
1568 (void)prefix_and_encode(dst->encoding(), src->encoding());
1569 emit_arith(0x23, 0xC0, dst, src);
1570 }
1571
1572 void Assembler::andl(Address dst, int32_t imm32) {
1573 InstructionMark im(this);
1574 prefix(dst);
1575 emit_arith_operand(0x81, as_Register(4), dst, imm32);
1576 }
1577
1578 void Assembler::andl(Register dst, int32_t imm32) {
1579 prefix(dst);
1580 emit_arith(0x81, 0xE0, dst, imm32);
1581 }
1582
1583 void Assembler::andl(Address dst, Register src) {
1584 InstructionMark im(this);
1585 prefix(dst, src);
1586 emit_int8(0x21);
1587 emit_operand(src, dst, 0);
1588 }
1589
1590 void Assembler::andl(Register dst, Address src) {
1591 InstructionMark im(this);
1592 prefix(src, dst);
1593 emit_int8(0x23);
1594 emit_operand(dst, src, 0);
1595 }
1596
1597 void Assembler::andl(Register dst, Register src) {
1598 (void) prefix_and_encode(dst->encoding(), src->encoding());
1599 emit_arith(0x23, 0xC0, dst, src);
1600 }
1601
1602 void Assembler::andnl(Register dst, Register src1, Register src2) {
1603 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1605 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1606 emit_int16((unsigned char)0xF2, (0xC0 | encode));
1607 }
1608
1609 void Assembler::andnl(Register dst, Register src1, Address src2) {
1610 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1611 InstructionMark im(this);
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1613 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1614 emit_int8((unsigned char)0xF2);
1615 emit_operand(dst, src2, 0);
1616 }
1617
1618 void Assembler::bsfl(Register dst, Register src) {
1619 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1620 emit_int24(0x0F,
1621 (unsigned char)0xBC,
1622 0xC0 | encode);
1623 }
1624
1625 void Assembler::bsrl(Register dst, Register src) {
1626 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1627 emit_int24(0x0F,
1628 (unsigned char)0xBD,
1629 0xC0 | encode);
1630 }
1631
1632 void Assembler::bswapl(Register reg) { // bswap
1633 int encode = prefix_and_encode(reg->encoding());
1634 emit_int16(0x0F, (0xC8 | encode));
1635 }
1636
1637 void Assembler::blsil(Register dst, Register src) {
1638 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1639 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1640 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1641 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1642 }
1643
1644 void Assembler::blsil(Register dst, Address src) {
1645 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1646 InstructionMark im(this);
1647 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1648 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1649 emit_int8((unsigned char)0xF3);
1650 emit_operand(rbx, src, 0);
1651 }
1652
1653 void Assembler::blsmskl(Register dst, Register src) {
1654 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1655 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1656 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1657 emit_int16((unsigned char)0xF3,
1658 0xC0 | encode);
1659 }
1660
1661 void Assembler::blsmskl(Register dst, Address src) {
1662 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1663 InstructionMark im(this);
1664 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1665 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1666 emit_int8((unsigned char)0xF3);
1667 emit_operand(rdx, src, 0);
1668 }
1669
1670 void Assembler::blsrl(Register dst, Register src) {
1671 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1672 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1673 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1674 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1675 }
1676
1677 void Assembler::blsrl(Register dst, Address src) {
1678 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1679 InstructionMark im(this);
1680 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1681 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1682 emit_int8((unsigned char)0xF3);
1683 emit_operand(rcx, src, 0);
1684 }
1685
1686 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1687 // suspect disp32 is always good
1688 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1689
1690 if (L.is_bound()) {
1691 const int long_size = 5;
1692 int offs = (int)( target(L) - pc() );
1693 assert(offs <= 0, "assembler error");
1694 InstructionMark im(this);
1695 // 1110 1000 #32-bit disp
1696 emit_int8((unsigned char)0xE8);
1697 emit_data(offs - long_size, rtype, operand);
1698 } else {
1699 InstructionMark im(this);
1700 // 1110 1000 #32-bit disp
1701 L.add_patch_at(code(), locator());
1702
1703 emit_int8((unsigned char)0xE8);
1704 emit_data(int(0), rtype, operand);
1705 }
1706 }
1707
1708 void Assembler::call(Register dst) {
1709 int encode = prefix_and_encode(dst->encoding());
1710 emit_int16((unsigned char)0xFF, (0xD0 | encode));
1711 }
1712
1713
1714 void Assembler::call(Address adr) {
1715 InstructionMark im(this);
1716 prefix(adr);
1717 emit_int8((unsigned char)0xFF);
1718 emit_operand(rdx, adr, 0);
1719 }
1720
1721 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1722 InstructionMark im(this);
1723 emit_int8((unsigned char)0xE8);
1724 intptr_t disp = entry - (pc() + sizeof(int32_t));
1725 // Entry is null in case of a scratch emit.
1726 assert(entry == nullptr || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1727 // Technically, should use call32_operand, but this format is
1728 // implied by the fact that we're emitting a call instruction.
1729
1730 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1731 emit_data((int) disp, rspec, operand);
1732 }
1733
1734 void Assembler::cdql() {
1735 emit_int8((unsigned char)0x99);
1736 }
1737
1738 void Assembler::cld() {
1739 emit_int8((unsigned char)0xFC);
1740 }
1741
1742 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1743 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1744 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1745 emit_int24(0x0F,
1746 0x40 | cc,
1747 0xC0 | encode);
1748 }
1749
1750
1751 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1752 InstructionMark im(this);
1753 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1754 prefix(src, dst);
1755 emit_int16(0x0F, (0x40 | cc));
1756 emit_operand(dst, src, 0);
1757 }
1758
1759 void Assembler::cmpb(Address dst, int imm8) {
1760 InstructionMark im(this);
1761 prefix(dst);
1762 emit_int8((unsigned char)0x80);
1763 emit_operand(rdi, dst, 1);
1764 emit_int8(imm8);
1765 }
1766
1767 void Assembler::cmpl(Address dst, int32_t imm32) {
1768 InstructionMark im(this);
1769 prefix(dst);
1770 emit_arith_operand(0x81, as_Register(7), dst, imm32);
1771 }
1772
1773 void Assembler::cmpl(Register dst, int32_t imm32) {
1774 prefix(dst);
1775 emit_arith(0x81, 0xF8, dst, imm32);
1776 }
1777
1778 void Assembler::cmpl(Register dst, Register src) {
1779 (void) prefix_and_encode(dst->encoding(), src->encoding());
1780 emit_arith(0x3B, 0xC0, dst, src);
1781 }
1782
1783 void Assembler::cmpl(Register dst, Address src) {
1784 InstructionMark im(this);
1785 prefix(src, dst);
1786 emit_int8(0x3B);
1787 emit_operand(dst, src, 0);
1788 }
1789
1790 void Assembler::cmpl_imm32(Address dst, int32_t imm32) {
1791 InstructionMark im(this);
1792 prefix(dst);
1793 emit_arith_operand_imm32(0x81, as_Register(7), dst, imm32);
1794 }
1795
1796 void Assembler::cmpw(Address dst, int imm16) {
1797 InstructionMark im(this);
1798 emit_int8(0x66);
1799 prefix(dst);
1800 emit_int8((unsigned char)0x81);
1801 emit_operand(rdi, dst, 2);
1802 emit_int16(imm16);
1803 }
1804
1805 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1806 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1807 // The ZF is set if the compared values were equal, and cleared otherwise.
1808 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1809 InstructionMark im(this);
1810 prefix(adr, reg);
1811 emit_int16(0x0F, (unsigned char)0xB1);
1812 emit_operand(reg, adr, 0);
1813 }
1814
1815 void Assembler::cmpxchgw(Register reg, Address adr) { // cmpxchg
1816 InstructionMark im(this);
1817 size_prefix();
1818 prefix(adr, reg);
1819 emit_int16(0x0F, (unsigned char)0xB1);
1820 emit_operand(reg, adr, 0);
1821 }
1822
1823 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1824 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1825 // The ZF is set if the compared values were equal, and cleared otherwise.
1826 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1827 InstructionMark im(this);
1828 prefix(adr, reg, true);
1829 emit_int16(0x0F, (unsigned char)0xB0);
1830 emit_operand(reg, adr, 0);
1831 }
1832
1833 void Assembler::comisd(XMMRegister dst, Address src) {
1834 // NOTE: dbx seems to decode this as comiss even though the
1835 // 0x66 is there. Strangely ucomisd comes out correct
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1840 attributes.set_rex_vex_w_reverted();
1841 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x2F);
1843 emit_operand(dst, src, 0);
1844 }
1845
1846 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1849 attributes.set_rex_vex_w_reverted();
1850 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1851 emit_int16(0x2F, (0xC0 | encode));
1852 }
1853
1854 void Assembler::comiss(XMMRegister dst, Address src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1859 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x2F);
1861 emit_operand(dst, src, 0);
1862 }
1863
1864 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1867 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1868 emit_int16(0x2F, (0xC0 | encode));
1869 }
1870
1871 void Assembler::cpuid() {
1872 emit_int16(0x0F, (unsigned char)0xA2);
1873 }
1874
1875 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1876 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1877 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1878 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1879 //
1880 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1881 //
1882 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1883 //
1884 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1885 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1886 assert(VM_Version::supports_sse4_2(), "");
1887 int8_t w = 0x01;
1888 Prefix p = Prefix_EMPTY;
1889
1890 emit_int8((unsigned char)0xF2);
1891 switch (sizeInBytes) {
1892 case 1:
1893 w = 0;
1894 break;
1895 case 2:
1896 case 4:
1897 break;
1898 LP64_ONLY(case 8:)
1899 // This instruction is not valid in 32 bits
1900 // Note:
1901 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1902 //
1903 // Page B - 72 Vol. 2C says
1904 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1905 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1906 // F0!!!
1907 // while 3 - 208 Vol. 2A
1908 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1909 //
1910 // the 0 on a last bit is reserved for a different flavor of this instruction :
1911 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1912 p = REX_W;
1913 break;
1914 default:
1915 assert(0, "Unsupported value for a sizeInBytes argument");
1916 break;
1917 }
1918 LP64_ONLY(prefix(crc, v, p);)
1919 emit_int32(0x0F,
1920 0x38,
1921 0xF0 | w,
1922 0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1923 }
1924
1925 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1926 assert(VM_Version::supports_sse4_2(), "");
1927 InstructionMark im(this);
1928 int8_t w = 0x01;
1929 Prefix p = Prefix_EMPTY;
1930
1931 emit_int8((uint8_t)0xF2);
1932 switch (sizeInBytes) {
1933 case 1:
1934 w = 0;
1935 break;
1936 case 2:
1937 case 4:
1938 break;
1939 LP64_ONLY(case 8:)
1940 // This instruction is not valid in 32 bits
1941 p = REX_W;
1942 break;
1943 default:
1944 assert(0, "Unsupported value for a sizeInBytes argument");
1945 break;
1946 }
1947 LP64_ONLY(prefix(crc, adr, p);)
1948 emit_int24(0x0F, 0x38, (0xF0 | w));
1949 emit_operand(crc, adr, 0);
1950 }
1951
1952 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1955 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1956 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1957 }
1958
1959 void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1960 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
1961 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1962 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1963 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1964 }
1965
1966 void Assembler::vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
1967 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1968 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1969 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1970 emit_int24(0x1D, (0xC0 | encode), imm8);
1971 }
1972
1973 void Assembler::evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len) {
1974 assert(VM_Version::supports_evex(), "");
1975 InstructionMark im(this);
1976 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
1977 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_64bit);
1978 attributes.reset_is_clear_context();
1979 attributes.set_embedded_opmask_register_specifier(mask);
1980 attributes.set_is_evex_instruction();
1981 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1982 emit_int8(0x1D);
1983 emit_operand(src, dst, 1);
1984 emit_int8(imm8);
1985 }
1986
1987 void Assembler::vcvtps2ph(Address dst, XMMRegister src, int imm8, int vector_len) {
1988 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1989 InstructionMark im(this);
1990 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1991 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
1992 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1993 emit_int8(0x1D);
1994 emit_operand(src, dst, 1);
1995 emit_int8(imm8);
1996 }
1997
1998 void Assembler::vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1999 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
2000 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ true);
2001 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2002 emit_int16(0x13, (0xC0 | encode));
2003 }
2004
2005 void Assembler::vcvtph2ps(XMMRegister dst, Address src, int vector_len) {
2006 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
2007 InstructionMark im(this);
2008 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
2009 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
2010 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2011 emit_int8(0x13);
2012 emit_operand(dst, src, 0);
2013 }
2014
2015 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
2016 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2017 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2018 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2019 emit_int16(0x5B, (0xC0 | encode));
2020 }
2021
2022 void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2023 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2024 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2025 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2026 emit_int16(0x5B, (0xC0 | encode));
2027 }
2028
2029 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
2030 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2031 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2032 attributes.set_rex_vex_w_reverted();
2033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2034 emit_int16(0x5A, (0xC0 | encode));
2035 }
2036
2037 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
2038 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2039 InstructionMark im(this);
2040 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2041 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2042 attributes.set_rex_vex_w_reverted();
2043 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2044 emit_int8(0x5A);
2045 emit_operand(dst, src, 0);
2046 }
2047
2048 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
2049 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2050 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2051 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2052 emit_int16(0x2A, (0xC0 | encode));
2053 }
2054
2055 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
2056 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2057 InstructionMark im(this);
2058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2059 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2060 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2061 emit_int8(0x2A);
2062 emit_operand(dst, src, 0);
2063 }
2064
2065 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
2066 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2067 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2068 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2069 emit_int16(0x2A, (0xC0 | encode));
2070 }
2071
2072 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
2073 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2074 InstructionMark im(this);
2075 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2076 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2077 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2078 emit_int8(0x2A);
2079 emit_operand(dst, src, 0);
2080 }
2081
2082 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
2083 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2084 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2085 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2086 emit_int16(0x2A, (0xC0 | encode));
2087 }
2088
2089 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
2090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2091 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2092 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2093 emit_int16(0x5A, (0xC0 | encode));
2094 }
2095
2096 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
2097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2098 InstructionMark im(this);
2099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2100 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2101 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2102 emit_int8(0x5A);
2103 emit_operand(dst, src, 0);
2104 }
2105
2106
2107 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
2108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2109 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2110 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2111 emit_int16(0x2C, (0xC0 | encode));
2112 }
2113
2114 void Assembler::cvtss2sil(Register dst, XMMRegister src) {
2115 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2116 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2117 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2118 emit_int16(0x2D, (0xC0 | encode));
2119 }
2120
2121 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2123 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2124 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2125 emit_int16(0x2C, (0xC0 | encode));
2126 }
2127
2128 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
2129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2130 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2131 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2132 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2133 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2134 }
2135
2136 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
2137 assert(VM_Version::supports_ssse3(), "");
2138 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2139 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2140 emit_int16(0x1C, (0xC0 | encode));
2141 }
2142
2143 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
2144 assert(VM_Version::supports_ssse3(), "");
2145 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2146 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2147 emit_int16(0x1D, (0xC0 | encode));
2148 }
2149
2150 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
2151 assert(VM_Version::supports_ssse3(), "");
2152 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2153 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2154 emit_int16(0x1E, (0xC0 | encode));
2155 }
2156
2157 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
2158 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2159 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2160 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
2161 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2162 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2163 emit_int16(0x1C, (0xC0 | encode));
2164 }
2165
2166 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
2167 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2168 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2169 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "");
2170 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2171 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2172 emit_int16(0x1D, (0xC0 | encode));
2173 }
2174
2175 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
2176 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
2177 vector_len == AVX_256bit? VM_Version::supports_avx2() :
2178 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
2179 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2180 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2181 emit_int16(0x1E, (0xC0 | encode));
2182 }
2183
2184 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
2185 assert(UseAVX > 2, "");
2186 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2187 attributes.set_is_evex_instruction();
2188 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2189 emit_int16(0x1F, (0xC0 | encode));
2190 }
2191
2192 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2193 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2194 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2195 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2196 emit_int16(0x5A, (0xC0 | encode));
2197 }
2198
2199 void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2200 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2203 attributes.set_rex_vex_w_reverted();
2204 emit_int16(0x5A, (0xC0 | encode));
2205 }
2206
2207 void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2208 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2211 emit_int16(0x5B, (0xC0 | encode));
2212 }
2213
2214 void Assembler::vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2215 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2216 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2217 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2218 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2219 }
2220
2221 void Assembler::vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2222 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2223 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2225 emit_int16(0x5B, (0xC0 | encode));
2226 }
2227
2228 void Assembler::evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2229 assert(VM_Version::supports_avx512dq(), "");
2230 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2231 attributes.set_is_evex_instruction();
2232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2233 emit_int16(0x7A, (0xC0 | encode));
2234 }
2235
2236 void Assembler::evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2237 assert(VM_Version::supports_avx512dq(), "");
2238 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2239 attributes.set_is_evex_instruction();
2240 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2241 emit_int16(0x7B, (0xC0 | encode));
2242 }
2243
2244 void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2245 assert(VM_Version::supports_avx512dq(), "");
2246 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2247 attributes.set_is_evex_instruction();
2248 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2249 emit_int16(0x5B, (0xC0 | encode));
2250 }
2251
2252 void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2253 assert(VM_Version::supports_avx512dq(), "");
2254 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2255 attributes.set_is_evex_instruction();
2256 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2257 emit_int16(0x7A, (0xC0 | encode));
2258 }
2259
2260 void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2261 assert(VM_Version::supports_avx512dq(), "");
2262 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2263 attributes.set_is_evex_instruction();
2264 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2265 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2266 }
2267
2268 void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
2269 assert(VM_Version::supports_avx512bw(), "");
2270 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2271 attributes.set_is_evex_instruction();
2272 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2273 emit_int16(0x30, (0xC0 | encode));
2274 }
2275
2276 void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
2277 assert(UseAVX > 2, "");
2278 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2279 attributes.set_is_evex_instruction();
2280 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2281 emit_int16(0x33, (0xC0 | encode));
2282 }
2283
2284 void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
2285 assert(UseAVX > 2, "");
2286 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2287 attributes.set_is_evex_instruction();
2288 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2289 emit_int16(0x31, (0xC0 | encode));
2290 }
2291
2292 void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
2293 assert(UseAVX > 2, "");
2294 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2295 attributes.set_is_evex_instruction();
2296 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2297 emit_int16(0x35, (0xC0 | encode));
2298 }
2299
2300 void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
2301 assert(UseAVX > 2, "");
2302 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2303 attributes.set_is_evex_instruction();
2304 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2305 emit_int16(0x32, (0xC0 | encode));
2306 }
2307
2308 void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
2309 assert(UseAVX > 2, "");
2310 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2311 attributes.set_is_evex_instruction();
2312 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2313 emit_int16(0x34, (0xC0 | encode));
2314 }
2315
2316 void Assembler::evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len) {
2317 assert(UseAVX > 2, "");
2318 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2319 attributes.set_is_evex_instruction();
2320 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2321 emit_int16(0x25, (0xC0 | encode));
2322 }
2323
2324 void Assembler::decl(Address dst) {
2325 // Don't use it directly. Use MacroAssembler::decrement() instead.
2326 InstructionMark im(this);
2327 prefix(dst);
2328 emit_int8((unsigned char)0xFF);
2329 emit_operand(rcx, dst, 0);
2330 }
2331
2332 void Assembler::divsd(XMMRegister dst, Address src) {
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 InstructionMark im(this);
2335 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2336 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2337 attributes.set_rex_vex_w_reverted();
2338 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2339 emit_int8(0x5E);
2340 emit_operand(dst, src, 0);
2341 }
2342
2343 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2346 attributes.set_rex_vex_w_reverted();
2347 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2348 emit_int16(0x5E, (0xC0 | encode));
2349 }
2350
2351 void Assembler::divss(XMMRegister dst, Address src) {
2352 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2353 InstructionMark im(this);
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2355 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2356 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2357 emit_int8(0x5E);
2358 emit_operand(dst, src, 0);
2359 }
2360
2361 void Assembler::divss(XMMRegister dst, XMMRegister src) {
2362 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2365 emit_int16(0x5E, (0xC0 | encode));
2366 }
2367
2368 void Assembler::hlt() {
2369 emit_int8((unsigned char)0xF4);
2370 }
2371
2372 void Assembler::idivl(Register src) {
2373 int encode = prefix_and_encode(src->encoding());
2374 emit_int16((unsigned char)0xF7, (0xF8 | encode));
2375 }
2376
2377 void Assembler::divl(Register src) { // Unsigned
2378 int encode = prefix_and_encode(src->encoding());
2379 emit_int16((unsigned char)0xF7, (0xF0 | encode));
2380 }
2381
2382 void Assembler::imull(Register src) {
2383 int encode = prefix_and_encode(src->encoding());
2384 emit_int16((unsigned char)0xF7, (0xE8 | encode));
2385 }
2386
2387 void Assembler::imull(Register dst, Register src) {
2388 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2389 emit_int24(0x0F,
2390 (unsigned char)0xAF,
2391 (0xC0 | encode));
2392 }
2393
2394 void Assembler::imull(Register dst, Address src, int32_t value) {
2395 InstructionMark im(this);
2396 prefix(src, dst);
2397 if (is8bit(value)) {
2398 emit_int8((unsigned char)0x6B);
2399 emit_operand(dst, src, 1);
2400 emit_int8(value);
2401 } else {
2402 emit_int8((unsigned char)0x69);
2403 emit_operand(dst, src, 4);
2404 emit_int32(value);
2405 }
2406 }
2407
2408 void Assembler::imull(Register dst, Register src, int value) {
2409 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2410 if (is8bit(value)) {
2411 emit_int24(0x6B, (0xC0 | encode), value & 0xFF);
2412 } else {
2413 emit_int16(0x69, (0xC0 | encode));
2414 emit_int32(value);
2415 }
2416 }
2417
2418 void Assembler::imull(Register dst, Address src) {
2419 InstructionMark im(this);
2420 prefix(src, dst);
2421 emit_int16(0x0F, (unsigned char)0xAF);
2422 emit_operand(dst, src, 0);
2423 }
2424
2425
2426 void Assembler::incl(Address dst) {
2427 // Don't use it directly. Use MacroAssembler::increment() instead.
2428 InstructionMark im(this);
2429 prefix(dst);
2430 emit_int8((unsigned char)0xFF);
2431 emit_operand(rax, dst, 0);
2432 }
2433
2434 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2435 InstructionMark im(this);
2436 assert((0 <= cc) && (cc < 16), "illegal cc");
2437 if (L.is_bound()) {
2438 address dst = target(L);
2439 assert(dst != nullptr, "jcc most probably wrong");
2440
2441 const int short_size = 2;
2442 const int long_size = 6;
2443 int offs = checked_cast<int>((intptr_t)dst - (intptr_t)pc());
2444 if (maybe_short && is8bit(offs - short_size)) {
2445 // 0111 tttn #8-bit disp
2446 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2447 } else {
2448 // 0000 1111 1000 tttn #32-bit disp
2449 assert(is_simm32(offs - long_size),
2450 "must be 32bit offset (call4)");
2451 emit_int16(0x0F, (0x80 | cc));
2452 emit_int32(offs - long_size);
2453 }
2454 } else {
2455 // Note: could eliminate cond. jumps to this jump if condition
2456 // is the same however, seems to be rather unlikely case.
2457 // Note: use jccb() if label to be bound is very close to get
2458 // an 8-bit displacement
2459 L.add_patch_at(code(), locator());
2460 emit_int16(0x0F, (0x80 | cc));
2461 emit_int32(0);
2462 }
2463 }
2464
2465 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2466 if (L.is_bound()) {
2467 const int short_size = 2;
2468 address entry = target(L);
2469 #ifdef ASSERT
2470 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2471 int delta = short_branch_delta();
2472 if (delta != 0) {
2473 dist += (dist < 0 ? (-delta) :delta);
2474 }
2475 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2476 #endif
2477 int offs = checked_cast<int>((intptr_t)entry - (intptr_t)pc());
2478 // 0111 tttn #8-bit disp
2479 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2480 } else {
2481 InstructionMark im(this);
2482 L.add_patch_at(code(), locator(), file, line);
2483 emit_int16(0x70 | cc, 0);
2484 }
2485 }
2486
2487 void Assembler::jmp(Address adr) {
2488 InstructionMark im(this);
2489 prefix(adr);
2490 emit_int8((unsigned char)0xFF);
2491 emit_operand(rsp, adr, 0);
2492 }
2493
2494 void Assembler::jmp(Label& L, bool maybe_short) {
2495 if (L.is_bound()) {
2496 address entry = target(L);
2497 assert(entry != nullptr, "jmp most probably wrong");
2498 InstructionMark im(this);
2499 const int short_size = 2;
2500 const int long_size = 5;
2501 int offs = checked_cast<int>(entry - pc());
2502 if (maybe_short && is8bit(offs - short_size)) {
2503 emit_int16((unsigned char)0xEB, ((offs - short_size) & 0xFF));
2504 } else {
2505 emit_int8((unsigned char)0xE9);
2506 emit_int32(offs - long_size);
2507 }
2508 } else {
2509 // By default, forward jumps are always 32-bit displacements, since
2510 // we can't yet know where the label will be bound. If you're sure that
2511 // the forward jump will not run beyond 256 bytes, use jmpb to
2512 // force an 8-bit displacement.
2513 InstructionMark im(this);
2514 L.add_patch_at(code(), locator());
2515 emit_int8((unsigned char)0xE9);
2516 emit_int32(0);
2517 }
2518 }
2519
2520 void Assembler::jmp(Register entry) {
2521 int encode = prefix_and_encode(entry->encoding());
2522 emit_int16((unsigned char)0xFF, (0xE0 | encode));
2523 }
2524
2525 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2526 InstructionMark im(this);
2527 emit_int8((unsigned char)0xE9);
2528 assert(dest != nullptr, "must have a target");
2529 intptr_t disp = dest - (pc() + sizeof(int32_t));
2530 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2531 emit_data(checked_cast<int32_t>(disp), rspec, call32_operand);
2532 }
2533
2534 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2535 if (L.is_bound()) {
2536 const int short_size = 2;
2537 address entry = target(L);
2538 assert(entry != nullptr, "jmp most probably wrong");
2539 #ifdef ASSERT
2540 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2541 int delta = short_branch_delta();
2542 if (delta != 0) {
2543 dist += (dist < 0 ? (-delta) :delta);
2544 }
2545 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2546 #endif
2547 intptr_t offs = entry - pc();
2548 emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
2549 } else {
2550 InstructionMark im(this);
2551 L.add_patch_at(code(), locator(), file, line);
2552 emit_int16((unsigned char)0xEB, 0);
2553 }
2554 }
2555
2556 void Assembler::ldmxcsr( Address src) {
2557 if (UseAVX > 0 ) {
2558 InstructionMark im(this);
2559 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2560 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2561 emit_int8((unsigned char)0xAE);
2562 emit_operand(as_Register(2), src, 0);
2563 } else {
2564 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2565 InstructionMark im(this);
2566 prefix(src);
2567 emit_int16(0x0F, (unsigned char)0xAE);
2568 emit_operand(as_Register(2), src, 0);
2569 }
2570 }
2571
2572 void Assembler::leal(Register dst, Address src) {
2573 InstructionMark im(this);
2574 prefix(src, dst);
2575 emit_int8((unsigned char)0x8D);
2576 emit_operand(dst, src, 0);
2577 }
2578
2579 void Assembler::lfence() {
2580 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
2581 }
2582
2583 void Assembler::lock() {
2584 emit_int8((unsigned char)0xF0);
2585 }
2586
2587 void Assembler::size_prefix() {
2588 emit_int8(0x66);
2589 }
2590
2591 void Assembler::lzcntl(Register dst, Register src) {
2592 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2593 emit_int8((unsigned char)0xF3);
2594 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2595 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
2596 }
2597
2598 void Assembler::lzcntl(Register dst, Address src) {
2599 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2600 InstructionMark im(this);
2601 emit_int8((unsigned char)0xF3);
2602 prefix(src, dst);
2603 emit_int16(0x0F, (unsigned char)0xBD);
2604 emit_operand(dst, src, 0);
2605 }
2606
2607 // Emit mfence instruction
2608 void Assembler::mfence() {
2609 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2610 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
2611 }
2612
2613 // Emit sfence instruction
2614 void Assembler::sfence() {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2616 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
2617 }
2618
2619 void Assembler::mov(Register dst, Register src) {
2620 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2621 }
2622
2623 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2624 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2625 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2626 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2627 attributes.set_rex_vex_w_reverted();
2628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2629 emit_int16(0x28, (0xC0 | encode));
2630 }
2631
2632 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2633 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2634 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2635 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2636 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2637 emit_int16(0x28, (0xC0 | encode));
2638 }
2639
2640 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2641 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2643 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2644 emit_int16(0x16, (0xC0 | encode));
2645 }
2646
2647 void Assembler::movb(Register dst, Address src) {
2648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2649 InstructionMark im(this);
2650 prefix(src, dst, true);
2651 emit_int8((unsigned char)0x8A);
2652 emit_operand(dst, src, 0);
2653 }
2654
2655 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2656 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2657 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2658 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2659 attributes.set_rex_vex_w_reverted();
2660 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2661 emit_int16(0x12, 0xC0 | encode);
2662 }
2663
2664 void Assembler::movddup(XMMRegister dst, Address src) {
2665 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2666 InstructionMark im(this);
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2669 attributes.set_rex_vex_w_reverted();
2670 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2671 emit_int8(0x12);
2672 emit_operand(dst, src, 0);
2673 }
2674
2675 void Assembler::vmovddup(XMMRegister dst, Address src, int vector_len) {
2676 assert(VM_Version::supports_avx(), "");
2677 InstructionMark im(this);
2678 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2679 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2680 attributes.set_rex_vex_w_reverted();
2681 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2682 emit_int8(0x12);
2683 emit_operand(dst, src, 0);
2684 }
2685
2686 void Assembler::kmovbl(KRegister dst, KRegister src) {
2687 assert(VM_Version::supports_avx512dq(), "");
2688 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2689 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2690 emit_int16((unsigned char)0x90, (0xC0 | encode));
2691 }
2692
2693 void Assembler::kmovbl(KRegister dst, Register src) {
2694 assert(VM_Version::supports_avx512dq(), "");
2695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2696 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2697 emit_int16((unsigned char)0x92, (0xC0 | encode));
2698 }
2699
2700 void Assembler::kmovbl(Register dst, KRegister src) {
2701 assert(VM_Version::supports_avx512dq(), "");
2702 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2703 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2704 emit_int16((unsigned char)0x93, (0xC0 | encode));
2705 }
2706
2707 void Assembler::kmovwl(KRegister dst, Register src) {
2708 assert(VM_Version::supports_evex(), "");
2709 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2710 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2711 emit_int16((unsigned char)0x92, (0xC0 | encode));
2712 }
2713
2714 void Assembler::kmovwl(Register dst, KRegister src) {
2715 assert(VM_Version::supports_evex(), "");
2716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2717 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2718 emit_int16((unsigned char)0x93, (0xC0 | encode));
2719 }
2720
2721 void Assembler::kmovwl(KRegister dst, Address src) {
2722 assert(VM_Version::supports_evex(), "");
2723 InstructionMark im(this);
2724 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2725 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2726 emit_int8((unsigned char)0x90);
2727 emit_operand(dst, src, 0);
2728 }
2729
2730 void Assembler::kmovwl(Address dst, KRegister src) {
2731 assert(VM_Version::supports_evex(), "");
2732 InstructionMark im(this);
2733 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2734 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2735 emit_int8((unsigned char)0x91);
2736 emit_operand(src, dst, 0);
2737 }
2738
2739 void Assembler::kmovwl(KRegister dst, KRegister src) {
2740 assert(VM_Version::supports_evex(), "");
2741 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2742 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2743 emit_int16((unsigned char)0x90, (0xC0 | encode));
2744 }
2745
2746 void Assembler::kmovdl(KRegister dst, Register src) {
2747 assert(VM_Version::supports_avx512bw(), "");
2748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2749 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2750 emit_int16((unsigned char)0x92, (0xC0 | encode));
2751 }
2752
2753 void Assembler::kmovdl(Register dst, KRegister src) {
2754 assert(VM_Version::supports_avx512bw(), "");
2755 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2756 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2757 emit_int16((unsigned char)0x93, (0xC0 | encode));
2758 }
2759
2760 void Assembler::kmovql(KRegister dst, KRegister src) {
2761 assert(VM_Version::supports_avx512bw(), "");
2762 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2763 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2764 emit_int16((unsigned char)0x90, (0xC0 | encode));
2765 }
2766
2767 void Assembler::kmovql(KRegister dst, Address src) {
2768 assert(VM_Version::supports_avx512bw(), "");
2769 InstructionMark im(this);
2770 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2771 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2772 emit_int8((unsigned char)0x90);
2773 emit_operand(dst, src, 0);
2774 }
2775
2776 void Assembler::kmovql(Address dst, KRegister src) {
2777 assert(VM_Version::supports_avx512bw(), "");
2778 InstructionMark im(this);
2779 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2780 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2781 emit_int8((unsigned char)0x91);
2782 emit_operand(src, dst, 0);
2783 }
2784
2785 void Assembler::kmovql(KRegister dst, Register src) {
2786 assert(VM_Version::supports_avx512bw(), "");
2787 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2788 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2789 emit_int16((unsigned char)0x92, (0xC0 | encode));
2790 }
2791
2792 void Assembler::kmovql(Register dst, KRegister src) {
2793 assert(VM_Version::supports_avx512bw(), "");
2794 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2795 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2796 emit_int16((unsigned char)0x93, (0xC0 | encode));
2797 }
2798
2799 void Assembler::knotwl(KRegister dst, KRegister src) {
2800 assert(VM_Version::supports_evex(), "");
2801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2802 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2803 emit_int16(0x44, (0xC0 | encode));
2804 }
2805
2806 void Assembler::knotbl(KRegister dst, KRegister src) {
2807 assert(VM_Version::supports_evex(), "");
2808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2809 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2810 emit_int16(0x44, (0xC0 | encode));
2811 }
2812
2813 void Assembler::korbl(KRegister dst, KRegister src1, KRegister src2) {
2814 assert(VM_Version::supports_avx512dq(), "");
2815 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2816 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2817 emit_int16(0x45, (0xC0 | encode));
2818 }
2819
2820 void Assembler::korwl(KRegister dst, KRegister src1, KRegister src2) {
2821 assert(VM_Version::supports_evex(), "");
2822 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2823 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2824 emit_int16(0x45, (0xC0 | encode));
2825 }
2826
2827 void Assembler::kordl(KRegister dst, KRegister src1, KRegister src2) {
2828 assert(VM_Version::supports_avx512bw(), "");
2829 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2830 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2831 emit_int16(0x45, (0xC0 | encode));
2832 }
2833
2834 void Assembler::korql(KRegister dst, KRegister src1, KRegister src2) {
2835 assert(VM_Version::supports_avx512bw(), "");
2836 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2837 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2838 emit_int16(0x45, (0xC0 | encode));
2839 }
2840
2841 void Assembler::kxorbl(KRegister dst, KRegister src1, KRegister src2) {
2842 assert(VM_Version::supports_avx512dq(), "");
2843 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2844 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2845 emit_int16(0x47, (0xC0 | encode));
2846 }
2847
2848 void Assembler::kxorwl(KRegister dst, KRegister src1, KRegister src2) {
2849 assert(VM_Version::supports_evex(), "");
2850 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2851 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2852 emit_int16(0x47, (0xC0 | encode));
2853 }
2854
2855 void Assembler::kxordl(KRegister dst, KRegister src1, KRegister src2) {
2856 assert(VM_Version::supports_avx512bw(), "");
2857 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2858 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2859 emit_int16(0x47, (0xC0 | encode));
2860 }
2861
2862 void Assembler::kxorql(KRegister dst, KRegister src1, KRegister src2) {
2863 assert(VM_Version::supports_avx512bw(), "");
2864 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2865 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2866 emit_int16(0x47, (0xC0 | encode));
2867 }
2868
2869 void Assembler::kandbl(KRegister dst, KRegister src1, KRegister src2) {
2870 assert(VM_Version::supports_avx512dq(), "");
2871 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2872 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2873 emit_int16(0x41, (0xC0 | encode));
2874 }
2875
2876 void Assembler::kandwl(KRegister dst, KRegister src1, KRegister src2) {
2877 assert(VM_Version::supports_evex(), "");
2878 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2879 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2880 emit_int16(0x41, (0xC0 | encode));
2881 }
2882
2883 void Assembler::kanddl(KRegister dst, KRegister src1, KRegister src2) {
2884 assert(VM_Version::supports_avx512bw(), "");
2885 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2886 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2887 emit_int16(0x41, (0xC0 | encode));
2888 }
2889
2890 void Assembler::kandql(KRegister dst, KRegister src1, KRegister src2) {
2891 assert(VM_Version::supports_avx512bw(), "");
2892 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2893 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2894 emit_int16(0x41, (0xC0 | encode));
2895 }
2896
2897 void Assembler::knotdl(KRegister dst, KRegister src) {
2898 assert(VM_Version::supports_avx512bw(), "");
2899 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2900 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2901 emit_int16(0x44, (0xC0 | encode));
2902 }
2903
2904 void Assembler::knotql(KRegister dst, KRegister src) {
2905 assert(VM_Version::supports_avx512bw(), "");
2906 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2907 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2908 emit_int16(0x44, (0xC0 | encode));
2909 }
2910
2911 // This instruction produces ZF or CF flags
2912 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2913 assert(VM_Version::supports_avx512dq(), "");
2914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2915 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2916 emit_int16((unsigned char)0x98, (0xC0 | encode));
2917 }
2918
2919 // This instruction produces ZF or CF flags
2920 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2921 assert(VM_Version::supports_evex(), "");
2922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2923 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2924 emit_int16((unsigned char)0x98, (0xC0 | encode));
2925 }
2926
2927 // This instruction produces ZF or CF flags
2928 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2929 assert(VM_Version::supports_avx512bw(), "");
2930 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2931 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2932 emit_int16((unsigned char)0x98, (0xC0 | encode));
2933 }
2934
2935 // This instruction produces ZF or CF flags
2936 void Assembler::kortestql(KRegister src1, KRegister src2) {
2937 assert(VM_Version::supports_avx512bw(), "");
2938 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2939 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2940 emit_int16((unsigned char)0x98, (0xC0 | encode));
2941 }
2942
2943 // This instruction produces ZF or CF flags
2944 void Assembler::ktestql(KRegister src1, KRegister src2) {
2945 assert(VM_Version::supports_avx512bw(), "");
2946 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2947 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2948 emit_int16((unsigned char)0x99, (0xC0 | encode));
2949 }
2950
2951 void Assembler::ktestdl(KRegister src1, KRegister src2) {
2952 assert(VM_Version::supports_avx512bw(), "");
2953 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2954 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2955 emit_int16((unsigned char)0x99, (0xC0 | encode));
2956 }
2957
2958 void Assembler::ktestwl(KRegister src1, KRegister src2) {
2959 assert(VM_Version::supports_avx512dq(), "");
2960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2961 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2962 emit_int16((unsigned char)0x99, (0xC0 | encode));
2963 }
2964
2965 void Assembler::ktestbl(KRegister src1, KRegister src2) {
2966 assert(VM_Version::supports_avx512dq(), "");
2967 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2968 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2969 emit_int16((unsigned char)0x99, (0xC0 | encode));
2970 }
2971
2972 void Assembler::ktestq(KRegister src1, KRegister src2) {
2973 assert(VM_Version::supports_avx512bw(), "");
2974 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2975 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2976 emit_int16((unsigned char)0x99, (0xC0 | encode));
2977 }
2978
2979 void Assembler::ktestd(KRegister src1, KRegister src2) {
2980 assert(VM_Version::supports_avx512bw(), "");
2981 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2982 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2983 emit_int16((unsigned char)0x99, (0xC0 | encode));
2984 }
2985
2986 void Assembler::kxnorbl(KRegister dst, KRegister src1, KRegister src2) {
2987 assert(VM_Version::supports_avx512dq(), "");
2988 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2989 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2990 emit_int16(0x46, (0xC0 | encode));
2991 }
2992
2993 void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) {
2994 assert(VM_Version::supports_avx512dq(), "");
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2996 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
2997 emit_int16(0x32, (0xC0 | encode));
2998 emit_int8(imm8);
2999 }
3000
3001 void Assembler::kshiftlql(KRegister dst, KRegister src, int imm8) {
3002 assert(VM_Version::supports_avx512bw(), "");
3003 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3004 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3005 emit_int16(0x33, (0xC0 | encode));
3006 emit_int8(imm8);
3007 }
3008
3009
3010 void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) {
3011 assert(VM_Version::supports_avx512dq(), "");
3012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3013 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3014 emit_int16(0x30, (0xC0 | encode));
3015 }
3016
3017 void Assembler::kshiftrwl(KRegister dst, KRegister src, int imm8) {
3018 assert(VM_Version::supports_evex(), "");
3019 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3020 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3021 emit_int16(0x30, (0xC0 | encode));
3022 emit_int8(imm8);
3023 }
3024
3025 void Assembler::kshiftrdl(KRegister dst, KRegister src, int imm8) {
3026 assert(VM_Version::supports_avx512bw(), "");
3027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3028 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3029 emit_int16(0x31, (0xC0 | encode));
3030 emit_int8(imm8);
3031 }
3032
3033 void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) {
3034 assert(VM_Version::supports_avx512bw(), "");
3035 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3036 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3037 emit_int16(0x31, (0xC0 | encode));
3038 emit_int8(imm8);
3039 }
3040
3041 void Assembler::kunpckdql(KRegister dst, KRegister src1, KRegister src2) {
3042 assert(VM_Version::supports_avx512bw(), "");
3043 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3044 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3045 emit_int16(0x4B, (0xC0 | encode));
3046 }
3047
3048 void Assembler::movb(Address dst, int imm8) {
3049 InstructionMark im(this);
3050 prefix(dst);
3051 emit_int8((unsigned char)0xC6);
3052 emit_operand(rax, dst, 1);
3053 emit_int8(imm8);
3054 }
3055
3056
3057 void Assembler::movb(Address dst, Register src) {
3058 assert(src->has_byte_register(), "must have byte register");
3059 InstructionMark im(this);
3060 prefix(dst, src, true);
3061 emit_int8((unsigned char)0x88);
3062 emit_operand(src, dst, 0);
3063 }
3064
3065 void Assembler::movdl(XMMRegister dst, Register src) {
3066 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3067 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3068 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3069 emit_int16(0x6E, (0xC0 | encode));
3070 }
3071
3072 void Assembler::movdl(Register dst, XMMRegister src) {
3073 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3074 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3075 // swap src/dst to get correct prefix
3076 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3077 emit_int16(0x7E, (0xC0 | encode));
3078 }
3079
3080 void Assembler::movdl(XMMRegister dst, Address src) {
3081 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3082 InstructionMark im(this);
3083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3084 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3085 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3086 emit_int8(0x6E);
3087 emit_operand(dst, src, 0);
3088 }
3089
3090 void Assembler::movdl(Address dst, XMMRegister src) {
3091 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3092 InstructionMark im(this);
3093 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3094 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3095 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3096 emit_int8(0x7E);
3097 emit_operand(src, dst, 0);
3098 }
3099
3100 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
3101 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3102 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3103 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3104 emit_int16(0x6F, (0xC0 | encode));
3105 }
3106
3107 void Assembler::movdqa(XMMRegister dst, Address src) {
3108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3109 InstructionMark im(this);
3110 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3111 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3112 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3113 emit_int8(0x6F);
3114 emit_operand(dst, src, 0);
3115 }
3116
3117 void Assembler::movdqu(XMMRegister dst, Address src) {
3118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3119 InstructionMark im(this);
3120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3121 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3122 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3123 emit_int8(0x6F);
3124 emit_operand(dst, src, 0);
3125 }
3126
3127 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
3128 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3129 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3131 emit_int16(0x6F, (0xC0 | encode));
3132 }
3133
3134 void Assembler::movdqu(Address dst, XMMRegister src) {
3135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3136 InstructionMark im(this);
3137 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3138 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3139 attributes.reset_is_clear_context();
3140 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3141 emit_int8(0x7F);
3142 emit_operand(src, dst, 0);
3143 }
3144
3145 // Move Unaligned 256bit Vector
3146 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3147 assert(UseAVX > 0, "");
3148 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3149 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3150 emit_int16(0x6F, (0xC0 | encode));
3151 }
3152
3153 void Assembler::vmovdqu(XMMRegister dst, Address src) {
3154 assert(UseAVX > 0, "");
3155 InstructionMark im(this);
3156 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3157 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3158 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3159 emit_int8(0x6F);
3160 emit_operand(dst, src, 0);
3161 }
3162
3163 void Assembler::vmovdqu(Address dst, XMMRegister src) {
3164 assert(UseAVX > 0, "");
3165 InstructionMark im(this);
3166 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3167 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3168 attributes.reset_is_clear_context();
3169 // swap src<->dst for encoding
3170 assert(src != xnoreg, "sanity");
3171 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3172 emit_int8(0x7F);
3173 emit_operand(src, dst, 0);
3174 }
3175
3176 void Assembler::vpmaskmovd(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3177 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3178 InstructionMark im(this);
3179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3180 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3181 emit_int8((unsigned char)0x8C);
3182 emit_operand(dst, src, 0);
3183 }
3184
3185 void Assembler::vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3186 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3187 InstructionMark im(this);
3188 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3189 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3190 emit_int8((unsigned char)0x8C);
3191 emit_operand(dst, src, 0);
3192 }
3193
3194 void Assembler::vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3195 assert(UseAVX > 0, "requires some form of AVX");
3196 InstructionMark im(this);
3197 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3198 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3199 emit_int8(0x2C);
3200 emit_operand(dst, src, 0);
3201 }
3202
3203 void Assembler::vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3204 assert(UseAVX > 0, "requires some form of AVX");
3205 InstructionMark im(this);
3206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3207 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3208 emit_int8(0x2D);
3209 emit_operand(dst, src, 0);
3210 }
3211
3212 void Assembler::vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3213 assert(UseAVX > 0, "");
3214 InstructionMark im(this);
3215 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3216 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3217 emit_int8(0x2E);
3218 emit_operand(src, dst, 0);
3219 }
3220
3221 void Assembler::vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3222 assert(UseAVX > 0, "");
3223 InstructionMark im(this);
3224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3225 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3226 emit_int8(0x2F);
3227 emit_operand(src, dst, 0);
3228 }
3229
3230 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
3231 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3232 assert(VM_Version::supports_avx512vlbw(), "");
3233 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3234 attributes.set_embedded_opmask_register_specifier(mask);
3235 attributes.set_is_evex_instruction();
3236 if (merge) {
3237 attributes.reset_is_clear_context();
3238 }
3239 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3240 emit_int16(0x6F, (0xC0 | encode));
3241 }
3242
3243 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
3244 // Unmasked instruction
3245 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3246 }
3247
3248 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3249 assert(VM_Version::supports_avx512vlbw(), "");
3250 InstructionMark im(this);
3251 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3252 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3253 attributes.set_embedded_opmask_register_specifier(mask);
3254 attributes.set_is_evex_instruction();
3255 if (merge) {
3256 attributes.reset_is_clear_context();
3257 }
3258 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3259 emit_int8(0x6F);
3260 emit_operand(dst, src, 0);
3261 }
3262
3263 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
3264 // Unmasked instruction
3265 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3266 }
3267
3268 void Assembler::evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3269 assert(VM_Version::supports_avx512vlbw(), "");
3270 assert(src != xnoreg, "sanity");
3271 InstructionMark im(this);
3272 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3273 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3274 attributes.set_embedded_opmask_register_specifier(mask);
3275 attributes.set_is_evex_instruction();
3276 if (merge) {
3277 attributes.reset_is_clear_context();
3278 }
3279 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3280 emit_int8(0x7F);
3281 emit_operand(src, dst, 0);
3282 }
3283
3284 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
3285 // Unmasked instruction
3286 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3287 }
3288
3289 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3290 assert(VM_Version::supports_avx512vlbw(), "");
3291 InstructionMark im(this);
3292 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3293 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3294 attributes.set_embedded_opmask_register_specifier(mask);
3295 attributes.set_is_evex_instruction();
3296 if (merge) {
3297 attributes.reset_is_clear_context();
3298 }
3299 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3300 emit_int8(0x6F);
3301 emit_operand(dst, src, 0);
3302 }
3303
3304 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
3305 // Unmasked instruction
3306 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3307 }
3308
3309 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3310 assert(VM_Version::supports_avx512vlbw(), "");
3311 assert(src != xnoreg, "sanity");
3312 InstructionMark im(this);
3313 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3314 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3315 attributes.set_embedded_opmask_register_specifier(mask);
3316 attributes.set_is_evex_instruction();
3317 if (merge) {
3318 attributes.reset_is_clear_context();
3319 }
3320 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3321 emit_int8(0x7F);
3322 emit_operand(src, dst, 0);
3323 }
3324
3325 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
3326 // Unmasked instruction
3327 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3328 }
3329
3330 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3331 assert(VM_Version::supports_evex(), "");
3332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3333 attributes.set_embedded_opmask_register_specifier(mask);
3334 attributes.set_is_evex_instruction();
3335 if (merge) {
3336 attributes.reset_is_clear_context();
3337 }
3338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3339 emit_int16(0x6F, (0xC0 | encode));
3340 }
3341
3342 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
3343 // Unmasked instruction
3344 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3345 }
3346
3347 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3348 assert(VM_Version::supports_evex(), "");
3349 InstructionMark im(this);
3350 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
3351 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3352 attributes.set_embedded_opmask_register_specifier(mask);
3353 attributes.set_is_evex_instruction();
3354 if (merge) {
3355 attributes.reset_is_clear_context();
3356 }
3357 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3358 emit_int8(0x6F);
3359 emit_operand(dst, src, 0);
3360 }
3361
3362 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
3363 // Unmasked isntruction
3364 evmovdqul(dst, k0, src, /*merge*/ true, vector_len);
3365 }
3366
3367 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3368 assert(VM_Version::supports_evex(), "");
3369 assert(src != xnoreg, "sanity");
3370 InstructionMark im(this);
3371 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3372 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3373 attributes.set_embedded_opmask_register_specifier(mask);
3374 attributes.set_is_evex_instruction();
3375 if (merge) {
3376 attributes.reset_is_clear_context();
3377 }
3378 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3379 emit_int8(0x7F);
3380 emit_operand(src, dst, 0);
3381 }
3382
3383 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
3384 // Unmasked instruction
3385 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3386 }
3387
3388 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3389 assert(VM_Version::supports_evex(), "");
3390 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3391 attributes.set_embedded_opmask_register_specifier(mask);
3392 attributes.set_is_evex_instruction();
3393 if (merge) {
3394 attributes.reset_is_clear_context();
3395 }
3396 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3397 emit_int16(0x6F, (0xC0 | encode));
3398 }
3399
3400 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
3401 // Unmasked instruction
3402 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3403 }
3404
3405 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3406 assert(VM_Version::supports_evex(), "");
3407 InstructionMark im(this);
3408 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3409 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3410 attributes.set_embedded_opmask_register_specifier(mask);
3411 attributes.set_is_evex_instruction();
3412 if (merge) {
3413 attributes.reset_is_clear_context();
3414 }
3415 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3416 emit_int8(0x6F);
3417 emit_operand(dst, src, 0);
3418 }
3419
3420 void Assembler::evmovntdquq(Address dst, XMMRegister src, int vector_len) {
3421 // Unmasked instruction
3422 evmovntdquq(dst, k0, src, /*merge*/ true, vector_len);
3423 }
3424
3425 void Assembler::evmovntdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3426 assert(VM_Version::supports_evex(), "");
3427 assert(src != xnoreg, "sanity");
3428 InstructionMark im(this);
3429 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3430 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3431 attributes.set_embedded_opmask_register_specifier(mask);
3432 if (merge) {
3433 attributes.reset_is_clear_context();
3434 }
3435 attributes.set_is_evex_instruction();
3436 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3437 emit_int8(0xE7);
3438 emit_operand(src, dst, 0);
3439 }
3440
3441 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
3442 // Unmasked instruction
3443 evmovdquq(dst, k0, src, /*merge*/ true, vector_len);
3444 }
3445
3446 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3447 assert(VM_Version::supports_evex(), "");
3448 assert(src != xnoreg, "sanity");
3449 InstructionMark im(this);
3450 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3451 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3452 attributes.set_embedded_opmask_register_specifier(mask);
3453 if (merge) {
3454 attributes.reset_is_clear_context();
3455 }
3456 attributes.set_is_evex_instruction();
3457 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3458 emit_int8(0x7F);
3459 emit_operand(src, dst, 0);
3460 }
3461
3462 // Uses zero extension on 64bit
3463
3464 void Assembler::movl(Register dst, int32_t imm32) {
3465 int encode = prefix_and_encode(dst->encoding());
3466 emit_int8(0xB8 | encode);
3467 emit_int32(imm32);
3468 }
3469
3470 void Assembler::movl(Register dst, Register src) {
3471 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3472 emit_int16((unsigned char)0x8B, (0xC0 | encode));
3473 }
3474
3475 void Assembler::movl(Register dst, Address src) {
3476 InstructionMark im(this);
3477 prefix(src, dst);
3478 emit_int8((unsigned char)0x8B);
3479 emit_operand(dst, src, 0);
3480 }
3481
3482 void Assembler::movl(Address dst, int32_t imm32) {
3483 InstructionMark im(this);
3484 prefix(dst);
3485 emit_int8((unsigned char)0xC7);
3486 emit_operand(rax, dst, 4);
3487 emit_int32(imm32);
3488 }
3489
3490 void Assembler::movl(Address dst, Register src) {
3491 InstructionMark im(this);
3492 prefix(dst, src);
3493 emit_int8((unsigned char)0x89);
3494 emit_operand(src, dst, 0);
3495 }
3496
3497 // New cpus require to use movsd and movss to avoid partial register stall
3498 // when loading from memory. But for old Opteron use movlpd instead of movsd.
3499 // The selection is done in MacroAssembler::movdbl() and movflt().
3500 void Assembler::movlpd(XMMRegister dst, Address src) {
3501 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3502 InstructionMark im(this);
3503 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3504 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3505 attributes.set_rex_vex_w_reverted();
3506 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3507 emit_int8(0x12);
3508 emit_operand(dst, src, 0);
3509 }
3510
3511 void Assembler::movq(XMMRegister dst, Address src) {
3512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3513 InstructionMark im(this);
3514 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3515 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3516 attributes.set_rex_vex_w_reverted();
3517 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3518 emit_int8(0x7E);
3519 emit_operand(dst, src, 0);
3520 }
3521
3522 void Assembler::movq(Address dst, XMMRegister src) {
3523 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3524 InstructionMark im(this);
3525 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3526 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3527 attributes.set_rex_vex_w_reverted();
3528 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3529 emit_int8((unsigned char)0xD6);
3530 emit_operand(src, dst, 0);
3531 }
3532
3533 void Assembler::movq(XMMRegister dst, XMMRegister src) {
3534 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3535 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3536 attributes.set_rex_vex_w_reverted();
3537 int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3538 emit_int16((unsigned char)0xD6, (0xC0 | encode));
3539 }
3540
3541 void Assembler::movq(Register dst, XMMRegister src) {
3542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3543 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3544 // swap src/dst to get correct prefix
3545 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3546 emit_int16(0x7E, (0xC0 | encode));
3547 }
3548
3549 void Assembler::movq(XMMRegister dst, Register src) {
3550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3551 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3552 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3553 emit_int16(0x6E, (0xC0 | encode));
3554 }
3555
3556 void Assembler::movsbl(Register dst, Address src) { // movsxb
3557 InstructionMark im(this);
3558 prefix(src, dst);
3559 emit_int16(0x0F, (unsigned char)0xBE);
3560 emit_operand(dst, src, 0);
3561 }
3562
3563 void Assembler::movsbl(Register dst, Register src) { // movsxb
3564 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3565 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3566 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
3567 }
3568
3569 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
3570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3571 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3572 attributes.set_rex_vex_w_reverted();
3573 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3574 emit_int16(0x10, (0xC0 | encode));
3575 }
3576
3577 void Assembler::movsd(XMMRegister dst, Address src) {
3578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3579 InstructionMark im(this);
3580 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3581 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3582 attributes.set_rex_vex_w_reverted();
3583 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3584 emit_int8(0x10);
3585 emit_operand(dst, src, 0);
3586 }
3587
3588 void Assembler::movsd(Address dst, XMMRegister src) {
3589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3590 InstructionMark im(this);
3591 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3592 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3593 attributes.reset_is_clear_context();
3594 attributes.set_rex_vex_w_reverted();
3595 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3596 emit_int8(0x11);
3597 emit_operand(src, dst, 0);
3598 }
3599
3600 void Assembler::vmovsd(XMMRegister dst, XMMRegister src, XMMRegister src2) {
3601 assert(UseAVX > 0, "Requires some form of AVX");
3602 InstructionMark im(this);
3603 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3604 int encode = vex_prefix_and_encode(src2->encoding(), src->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3605 emit_int16(0x11, (0xC0 | encode));
3606 }
3607
3608 void Assembler::movss(XMMRegister dst, XMMRegister src) {
3609 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3610 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3611 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3612 emit_int16(0x10, (0xC0 | encode));
3613 }
3614
3615 void Assembler::movss(XMMRegister dst, Address src) {
3616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3617 InstructionMark im(this);
3618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3620 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3621 emit_int8(0x10);
3622 emit_operand(dst, src, 0);
3623 }
3624
3625 void Assembler::movss(Address dst, XMMRegister src) {
3626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3627 InstructionMark im(this);
3628 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3629 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3630 attributes.reset_is_clear_context();
3631 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3632 emit_int8(0x11);
3633 emit_operand(src, dst, 0);
3634 }
3635
3636 void Assembler::movswl(Register dst, Address src) { // movsxw
3637 InstructionMark im(this);
3638 prefix(src, dst);
3639 emit_int16(0x0F, (unsigned char)0xBF);
3640 emit_operand(dst, src, 0);
3641 }
3642
3643 void Assembler::movswl(Register dst, Register src) { // movsxw
3644 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3645 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
3646 }
3647
3648 void Assembler::movups(XMMRegister dst, Address src) {
3649 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3650 InstructionMark im(this);
3651 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3652 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3653 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3654 emit_int8(0x10);
3655 emit_operand(dst, src, 0);
3656 }
3657
3658 void Assembler::vmovups(XMMRegister dst, Address src, int vector_len) {
3659 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3660 InstructionMark im(this);
3661 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3662 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3663 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3664 emit_int8(0x10);
3665 emit_operand(dst, src, 0);
3666 }
3667
3668 void Assembler::movups(Address dst, XMMRegister src) {
3669 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3670 InstructionMark im(this);
3671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3672 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3673 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3674 emit_int8(0x11);
3675 emit_operand(src, dst, 0);
3676 }
3677
3678 void Assembler::vmovups(Address dst, XMMRegister src, int vector_len) {
3679 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3680 InstructionMark im(this);
3681 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3682 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3683 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3684 emit_int8(0x11);
3685 emit_operand(src, dst, 0);
3686 }
3687
3688 void Assembler::movw(Address dst, int imm16) {
3689 InstructionMark im(this);
3690
3691 emit_int8(0x66); // switch to 16-bit mode
3692 prefix(dst);
3693 emit_int8((unsigned char)0xC7);
3694 emit_operand(rax, dst, 2);
3695 emit_int16(imm16);
3696 }
3697
3698 void Assembler::movw(Register dst, Address src) {
3699 InstructionMark im(this);
3700 emit_int8(0x66);
3701 prefix(src, dst);
3702 emit_int8((unsigned char)0x8B);
3703 emit_operand(dst, src, 0);
3704 }
3705
3706 void Assembler::movw(Address dst, Register src) {
3707 InstructionMark im(this);
3708 emit_int8(0x66);
3709 prefix(dst, src);
3710 emit_int8((unsigned char)0x89);
3711 emit_operand(src, dst, 0);
3712 }
3713
3714 void Assembler::movzbl(Register dst, Address src) { // movzxb
3715 InstructionMark im(this);
3716 prefix(src, dst);
3717 emit_int16(0x0F, (unsigned char)0xB6);
3718 emit_operand(dst, src, 0);
3719 }
3720
3721 void Assembler::movzbl(Register dst, Register src) { // movzxb
3722 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3723 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3724 emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
3725 }
3726
3727 void Assembler::movzwl(Register dst, Address src) { // movzxw
3728 InstructionMark im(this);
3729 prefix(src, dst);
3730 emit_int16(0x0F, (unsigned char)0xB7);
3731 emit_operand(dst, src, 0);
3732 }
3733
3734 void Assembler::movzwl(Register dst, Register src) { // movzxw
3735 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3736 emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode);
3737 }
3738
3739 void Assembler::mull(Address src) {
3740 InstructionMark im(this);
3741 prefix(src);
3742 emit_int8((unsigned char)0xF7);
3743 emit_operand(rsp, src, 0);
3744 }
3745
3746 void Assembler::mull(Register src) {
3747 int encode = prefix_and_encode(src->encoding());
3748 emit_int16((unsigned char)0xF7, (0xE0 | encode));
3749 }
3750
3751 void Assembler::mulsd(XMMRegister dst, Address src) {
3752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3753 InstructionMark im(this);
3754 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3756 attributes.set_rex_vex_w_reverted();
3757 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3758 emit_int8(0x59);
3759 emit_operand(dst, src, 0);
3760 }
3761
3762 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3763 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3764 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3765 attributes.set_rex_vex_w_reverted();
3766 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3767 emit_int16(0x59, (0xC0 | encode));
3768 }
3769
3770 void Assembler::mulss(XMMRegister dst, Address src) {
3771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3772 InstructionMark im(this);
3773 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3774 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3775 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3776 emit_int8(0x59);
3777 emit_operand(dst, src, 0);
3778 }
3779
3780 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3781 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3783 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3784 emit_int16(0x59, (0xC0 | encode));
3785 }
3786
3787 void Assembler::negl(Register dst) {
3788 int encode = prefix_and_encode(dst->encoding());
3789 emit_int16((unsigned char)0xF7, (0xD8 | encode));
3790 }
3791
3792 void Assembler::negl(Address dst) {
3793 InstructionMark im(this);
3794 prefix(dst);
3795 emit_int8((unsigned char)0xF7);
3796 emit_operand(as_Register(3), dst, 0);
3797 }
3798
3799 void Assembler::nop(int i) {
3800 #ifdef ASSERT
3801 assert(i > 0, " ");
3802 // The fancy nops aren't currently recognized by debuggers making it a
3803 // pain to disassemble code while debugging. If asserts are on clearly
3804 // speed is not an issue so simply use the single byte traditional nop
3805 // to do alignment.
3806
3807 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3808 return;
3809
3810 #endif // ASSERT
3811
3812 if (UseAddressNop && VM_Version::is_intel()) {
3813 //
3814 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3815 // 1: 0x90
3816 // 2: 0x66 0x90
3817 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3818 // 4: 0x0F 0x1F 0x40 0x00
3819 // 5: 0x0F 0x1F 0x44 0x00 0x00
3820 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3821 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3822 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3823 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3824 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3825 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3826
3827 // The rest coding is Intel specific - don't use consecutive address nops
3828
3829 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3830 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3831 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3832 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3833
3834 while(i >= 15) {
3835 // For Intel don't generate consecutive address nops (mix with regular nops)
3836 i -= 15;
3837 emit_int24(0x66, 0x66, 0x66);
3838 addr_nop_8();
3839 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3840 }
3841 switch (i) {
3842 case 14:
3843 emit_int8(0x66); // size prefix
3844 case 13:
3845 emit_int8(0x66); // size prefix
3846 case 12:
3847 addr_nop_8();
3848 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3849 break;
3850 case 11:
3851 emit_int8(0x66); // size prefix
3852 case 10:
3853 emit_int8(0x66); // size prefix
3854 case 9:
3855 emit_int8(0x66); // size prefix
3856 case 8:
3857 addr_nop_8();
3858 break;
3859 case 7:
3860 addr_nop_7();
3861 break;
3862 case 6:
3863 emit_int8(0x66); // size prefix
3864 case 5:
3865 addr_nop_5();
3866 break;
3867 case 4:
3868 addr_nop_4();
3869 break;
3870 case 3:
3871 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3872 emit_int8(0x66); // size prefix
3873 case 2:
3874 emit_int8(0x66); // size prefix
3875 case 1:
3876 emit_int8((unsigned char)0x90);
3877 // nop
3878 break;
3879 default:
3880 assert(i == 0, " ");
3881 }
3882 return;
3883 }
3884 if (UseAddressNop && VM_Version::is_amd_family()) {
3885 //
3886 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3887 // 1: 0x90
3888 // 2: 0x66 0x90
3889 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3890 // 4: 0x0F 0x1F 0x40 0x00
3891 // 5: 0x0F 0x1F 0x44 0x00 0x00
3892 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3893 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3894 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3895 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3896 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3897 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3898
3899 // The rest coding is AMD specific - use consecutive address nops
3900
3901 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3902 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3903 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3904 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3905 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3906 // Size prefixes (0x66) are added for larger sizes
3907
3908 while(i >= 22) {
3909 i -= 11;
3910 emit_int24(0x66, 0x66, 0x66);
3911 addr_nop_8();
3912 }
3913 // Generate first nop for size between 21-12
3914 switch (i) {
3915 case 21:
3916 i -= 1;
3917 emit_int8(0x66); // size prefix
3918 case 20:
3919 case 19:
3920 i -= 1;
3921 emit_int8(0x66); // size prefix
3922 case 18:
3923 case 17:
3924 i -= 1;
3925 emit_int8(0x66); // size prefix
3926 case 16:
3927 case 15:
3928 i -= 8;
3929 addr_nop_8();
3930 break;
3931 case 14:
3932 case 13:
3933 i -= 7;
3934 addr_nop_7();
3935 break;
3936 case 12:
3937 i -= 6;
3938 emit_int8(0x66); // size prefix
3939 addr_nop_5();
3940 break;
3941 default:
3942 assert(i < 12, " ");
3943 }
3944
3945 // Generate second nop for size between 11-1
3946 switch (i) {
3947 case 11:
3948 emit_int8(0x66); // size prefix
3949 case 10:
3950 emit_int8(0x66); // size prefix
3951 case 9:
3952 emit_int8(0x66); // size prefix
3953 case 8:
3954 addr_nop_8();
3955 break;
3956 case 7:
3957 addr_nop_7();
3958 break;
3959 case 6:
3960 emit_int8(0x66); // size prefix
3961 case 5:
3962 addr_nop_5();
3963 break;
3964 case 4:
3965 addr_nop_4();
3966 break;
3967 case 3:
3968 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3969 emit_int8(0x66); // size prefix
3970 case 2:
3971 emit_int8(0x66); // size prefix
3972 case 1:
3973 emit_int8((unsigned char)0x90);
3974 // nop
3975 break;
3976 default:
3977 assert(i == 0, " ");
3978 }
3979 return;
3980 }
3981
3982 if (UseAddressNop && VM_Version::is_zx()) {
3983 //
3984 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3985 // 1: 0x90
3986 // 2: 0x66 0x90
3987 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3988 // 4: 0x0F 0x1F 0x40 0x00
3989 // 5: 0x0F 0x1F 0x44 0x00 0x00
3990 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3991 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3992 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3993 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3994 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3995 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3996
3997 // The rest coding is ZX specific - don't use consecutive address nops
3998
3999 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4000 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4001 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4002 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4003
4004 while (i >= 15) {
4005 // For ZX don't generate consecutive address nops (mix with regular nops)
4006 i -= 15;
4007 emit_int24(0x66, 0x66, 0x66);
4008 addr_nop_8();
4009 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4010 }
4011 switch (i) {
4012 case 14:
4013 emit_int8(0x66); // size prefix
4014 case 13:
4015 emit_int8(0x66); // size prefix
4016 case 12:
4017 addr_nop_8();
4018 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4019 break;
4020 case 11:
4021 emit_int8(0x66); // size prefix
4022 case 10:
4023 emit_int8(0x66); // size prefix
4024 case 9:
4025 emit_int8(0x66); // size prefix
4026 case 8:
4027 addr_nop_8();
4028 break;
4029 case 7:
4030 addr_nop_7();
4031 break;
4032 case 6:
4033 emit_int8(0x66); // size prefix
4034 case 5:
4035 addr_nop_5();
4036 break;
4037 case 4:
4038 addr_nop_4();
4039 break;
4040 case 3:
4041 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
4042 emit_int8(0x66); // size prefix
4043 case 2:
4044 emit_int8(0x66); // size prefix
4045 case 1:
4046 emit_int8((unsigned char)0x90);
4047 // nop
4048 break;
4049 default:
4050 assert(i == 0, " ");
4051 }
4052 return;
4053 }
4054
4055 // Using nops with size prefixes "0x66 0x90".
4056 // From AMD Optimization Guide:
4057 // 1: 0x90
4058 // 2: 0x66 0x90
4059 // 3: 0x66 0x66 0x90
4060 // 4: 0x66 0x66 0x66 0x90
4061 // 5: 0x66 0x66 0x90 0x66 0x90
4062 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
4063 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
4064 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
4065 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4066 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4067 //
4068 while (i > 12) {
4069 i -= 4;
4070 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4071 }
4072 // 1 - 12 nops
4073 if (i > 8) {
4074 if (i > 9) {
4075 i -= 1;
4076 emit_int8(0x66);
4077 }
4078 i -= 3;
4079 emit_int24(0x66, 0x66, (unsigned char)0x90);
4080 }
4081 // 1 - 8 nops
4082 if (i > 4) {
4083 if (i > 6) {
4084 i -= 1;
4085 emit_int8(0x66);
4086 }
4087 i -= 3;
4088 emit_int24(0x66, 0x66, (unsigned char)0x90);
4089 }
4090 switch (i) {
4091 case 4:
4092 emit_int8(0x66);
4093 case 3:
4094 emit_int8(0x66);
4095 case 2:
4096 emit_int8(0x66);
4097 case 1:
4098 emit_int8((unsigned char)0x90);
4099 break;
4100 default:
4101 assert(i == 0, " ");
4102 }
4103 }
4104
4105 void Assembler::notl(Register dst) {
4106 int encode = prefix_and_encode(dst->encoding());
4107 emit_int16((unsigned char)0xF7, (0xD0 | encode));
4108 }
4109
4110 void Assembler::orw(Register dst, Register src) {
4111 (void)prefix_and_encode(dst->encoding(), src->encoding());
4112 emit_arith(0x0B, 0xC0, dst, src);
4113 }
4114
4115 void Assembler::orl(Address dst, int32_t imm32) {
4116 InstructionMark im(this);
4117 prefix(dst);
4118 emit_arith_operand(0x81, rcx, dst, imm32);
4119 }
4120
4121 void Assembler::orl(Register dst, int32_t imm32) {
4122 prefix(dst);
4123 emit_arith(0x81, 0xC8, dst, imm32);
4124 }
4125
4126 void Assembler::orl(Register dst, Address src) {
4127 InstructionMark im(this);
4128 prefix(src, dst);
4129 emit_int8(0x0B);
4130 emit_operand(dst, src, 0);
4131 }
4132
4133 void Assembler::orl(Register dst, Register src) {
4134 (void) prefix_and_encode(dst->encoding(), src->encoding());
4135 emit_arith(0x0B, 0xC0, dst, src);
4136 }
4137
4138 void Assembler::orl(Address dst, Register src) {
4139 InstructionMark im(this);
4140 prefix(dst, src);
4141 emit_int8(0x09);
4142 emit_operand(src, dst, 0);
4143 }
4144
4145 void Assembler::orb(Address dst, int imm8) {
4146 InstructionMark im(this);
4147 prefix(dst);
4148 emit_int8((unsigned char)0x80);
4149 emit_operand(rcx, dst, 1);
4150 emit_int8(imm8);
4151 }
4152
4153 void Assembler::orb(Address dst, Register src) {
4154 InstructionMark im(this);
4155 prefix(dst, src, true);
4156 emit_int8(0x08);
4157 emit_operand(src, dst, 0);
4158 }
4159
4160 void Assembler::packsswb(XMMRegister dst, XMMRegister src) {
4161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4162 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4163 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4164 emit_int16(0x63, (0xC0 | encode));
4165 }
4166
4167 void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4168 assert(UseAVX > 0, "some form of AVX must be enabled");
4169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4170 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4171 emit_int16(0x63, (0xC0 | encode));
4172 }
4173
4174 void Assembler::packssdw(XMMRegister dst, XMMRegister src) {
4175 assert(VM_Version::supports_sse2(), "");
4176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4178 emit_int16(0x6B, (0xC0 | encode));
4179 }
4180
4181 void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4182 assert(UseAVX > 0, "some form of AVX must be enabled");
4183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4184 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4185 emit_int16(0x6B, (0xC0 | encode));
4186 }
4187
4188 void Assembler::packuswb(XMMRegister dst, Address src) {
4189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4190 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4191 InstructionMark im(this);
4192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4193 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4194 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4195 emit_int8(0x67);
4196 emit_operand(dst, src, 0);
4197 }
4198
4199 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
4200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4202 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4203 emit_int16(0x67, (0xC0 | encode));
4204 }
4205
4206 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4207 assert(UseAVX > 0, "some form of AVX must be enabled");
4208 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4209 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4210 emit_int16(0x67, (0xC0 | encode));
4211 }
4212
4213 void Assembler::packusdw(XMMRegister dst, XMMRegister src) {
4214 assert(VM_Version::supports_sse4_1(), "");
4215 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4216 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4217 emit_int16(0x2B, (0xC0 | encode));
4218 }
4219
4220 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4221 assert(UseAVX > 0, "some form of AVX must be enabled");
4222 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4223 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4224 emit_int16(0x2B, (0xC0 | encode));
4225 }
4226
4227 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4228 assert(VM_Version::supports_avx2(), "");
4229 assert(vector_len != AVX_128bit, "");
4230 // VEX.256.66.0F3A.W1 00 /r ib
4231 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4233 emit_int24(0x00, (0xC0 | encode), imm8);
4234 }
4235
4236 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4237 assert(vector_len == AVX_256bit ? VM_Version::supports_avx512vl() :
4238 vector_len == AVX_512bit ? VM_Version::supports_evex() : false, "not supported");
4239 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4240 attributes.set_is_evex_instruction();
4241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4242 emit_int16(0x36, (0xC0 | encode));
4243 }
4244
4245 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4246 assert(VM_Version::supports_avx512_vbmi(), "");
4247 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4248 attributes.set_is_evex_instruction();
4249 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4250 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4251 }
4252
4253 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4254 assert(VM_Version::supports_avx512_vbmi(), "");
4255 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4256 attributes.set_is_evex_instruction();
4257 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4258 emit_int8((unsigned char)0x8D);
4259 emit_operand(dst, src, 0);
4260 }
4261
4262 void Assembler::vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4263 assert(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() :
4264 vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() :
4265 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
4266 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4267 attributes.set_is_evex_instruction();
4268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4269 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4270 }
4271
4272 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4273 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4274 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4275 // VEX.NDS.256.66.0F38.W0 36 /r
4276 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4278 emit_int16(0x36, (0xC0 | encode));
4279 }
4280
4281 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4282 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4283 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4284 // VEX.NDS.256.66.0F38.W0 36 /r
4285 InstructionMark im(this);
4286 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4287 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4288 emit_int8(0x36);
4289 emit_operand(dst, src, 0);
4290 }
4291
4292 void Assembler::vpermps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4293 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4294 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4295 // VEX.NDS.XXX.66.0F38.W0 16 /r
4296 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4297 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4298 emit_int16(0x16, (0xC0 | encode));
4299 }
4300
4301 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4302 assert(VM_Version::supports_avx2(), "");
4303 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4304 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4305 emit_int24(0x46, (0xC0 | encode), imm8);
4306 }
4307
4308 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4309 assert(VM_Version::supports_avx(), "");
4310 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4312 emit_int24(0x06, (0xC0 | encode), imm8);
4313 }
4314
4315 void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4316 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4317 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4318 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4319 emit_int24(0x04, (0xC0 | encode), imm8);
4320 }
4321
4322 void Assembler::vpermilps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4323 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4324 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4325 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4326 emit_int16(0x0C, (0xC0 | encode));
4327 }
4328
4329 void Assembler::vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4330 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4331 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(),/* legacy_mode */ false,/* no_mask_reg */ true, /* uses_vl */ false);
4332 attributes.set_rex_vex_w_reverted();
4333 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4334 emit_int24(0x05, (0xC0 | encode), imm8);
4335 }
4336
4337 void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4338 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
4339 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ false);
4340 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4341 emit_int24(0x01, (0xC0 | encode), imm8);
4342 }
4343
4344 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4345 assert(VM_Version::supports_evex(), "");
4346 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4347 attributes.set_is_evex_instruction();
4348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4349 emit_int16(0x76, (0xC0 | encode));
4350 }
4351
4352 void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4353 assert(VM_Version::supports_avx512_vbmi(), "");
4354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4355 attributes.set_is_evex_instruction();
4356 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4357 emit_int16(0x7D, (0xC0 | encode));
4358 }
4359
4360 void Assembler::evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) {
4361 assert(VM_Version::supports_avx512_vbmi(), "");
4362 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4363 attributes.set_is_evex_instruction();
4364 int encode = vex_prefix_and_encode(dst->encoding(), ctl->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4365 emit_int16((unsigned char)0x83, (unsigned char)(0xC0 | encode));
4366 }
4367
4368 void Assembler::pause() {
4369 emit_int16((unsigned char)0xF3, (unsigned char)0x90);
4370 }
4371
4372 void Assembler::ud2() {
4373 emit_int16(0x0F, 0x0B);
4374 }
4375
4376 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
4377 assert(VM_Version::supports_sse4_2(), "");
4378 InstructionMark im(this);
4379 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4380 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4381 emit_int8(0x61);
4382 emit_operand(dst, src, 1);
4383 emit_int8(imm8);
4384 }
4385
4386 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
4387 assert(VM_Version::supports_sse4_2(), "");
4388 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4389 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4390 emit_int24(0x61, (0xC0 | encode), imm8);
4391 }
4392
4393 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4394 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
4395 assert(VM_Version::supports_sse2(), "");
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4398 emit_int16(0x74, (0xC0 | encode));
4399 }
4400
4401 void Assembler::vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4402 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4403 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4404 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4405 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4406 emit_int16(cond_encoding, (0xC0 | encode));
4407 }
4408
4409 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4410 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4411 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4412 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4413 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4414 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4415 emit_int16(0x74, (0xC0 | encode));
4416 }
4417
4418 // In this context, kdst is written the mask used to process the equal components
4419 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4420 assert(VM_Version::supports_avx512bw(), "");
4421 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4422 attributes.set_is_evex_instruction();
4423 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4424 emit_int16(0x74, (0xC0 | encode));
4425 }
4426
4427 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4428 assert(VM_Version::supports_avx512vlbw(), "");
4429 InstructionMark im(this);
4430 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4431 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4432 attributes.set_is_evex_instruction();
4433 int dst_enc = kdst->encoding();
4434 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4435 emit_int8(0x64);
4436 emit_operand(as_Register(dst_enc), src, 0);
4437 }
4438
4439 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4440 assert(VM_Version::supports_avx512vlbw(), "");
4441 InstructionMark im(this);
4442 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4443 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4444 attributes.reset_is_clear_context();
4445 attributes.set_embedded_opmask_register_specifier(mask);
4446 attributes.set_is_evex_instruction();
4447 int dst_enc = kdst->encoding();
4448 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x64);
4450 emit_operand(as_Register(dst_enc), src, 0);
4451 }
4452
4453 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4454 assert(VM_Version::supports_avx512vlbw(), "");
4455 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4456 attributes.set_is_evex_instruction();
4457 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4458 emit_int24(0x3E, (0xC0 | encode), vcc);
4459 }
4460
4461 void Assembler::evpcmpuq(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4462 assert(VM_Version::supports_avx512vl(), "");
4463 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4464 attributes.set_is_evex_instruction();
4465 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4466 emit_int24(0x1E, (0xC0 | encode), vcc);
4467 }
4468
4469 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
4470 assert(VM_Version::supports_avx512vlbw(), "");
4471 InstructionMark im(this);
4472 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4473 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4474 attributes.set_is_evex_instruction();
4475 int dst_enc = kdst->encoding();
4476 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4477 emit_int8(0x3E);
4478 emit_operand(as_Register(dst_enc), src, 1);
4479 emit_int8(vcc);
4480 }
4481
4482 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4483 assert(VM_Version::supports_avx512bw(), "");
4484 InstructionMark im(this);
4485 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4486 attributes.set_is_evex_instruction();
4487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4488 int dst_enc = kdst->encoding();
4489 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4490 emit_int8(0x74);
4491 emit_operand(as_Register(dst_enc), src, 0);
4492 }
4493
4494 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4495 assert(VM_Version::supports_avx512vlbw(), "");
4496 InstructionMark im(this);
4497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4498 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4499 attributes.reset_is_clear_context();
4500 attributes.set_embedded_opmask_register_specifier(mask);
4501 attributes.set_is_evex_instruction();
4502 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4503 emit_int8(0x74);
4504 emit_operand(as_Register(kdst->encoding()), src, 0);
4505 }
4506
4507 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4508 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
4509 assert(VM_Version::supports_sse2(), "");
4510 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4511 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4512 emit_int16(0x75, (0xC0 | encode));
4513 }
4514
4515 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4516 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4517 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4518 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4519 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4520 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4521 emit_int16(0x75, (0xC0 | encode));
4522 }
4523
4524 // In this context, kdst is written the mask used to process the equal components
4525 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4526 assert(VM_Version::supports_avx512bw(), "");
4527 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4528 attributes.set_is_evex_instruction();
4529 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4530 emit_int16(0x75, (0xC0 | encode));
4531 }
4532
4533 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4534 assert(VM_Version::supports_avx512bw(), "");
4535 InstructionMark im(this);
4536 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4537 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4538 attributes.set_is_evex_instruction();
4539 int dst_enc = kdst->encoding();
4540 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4541 emit_int8(0x75);
4542 emit_operand(as_Register(dst_enc), src, 0);
4543 }
4544
4545 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4546 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
4547 assert(VM_Version::supports_sse2(), "");
4548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4549 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4550 emit_int16(0x76, (0xC0 | encode));
4551 }
4552
4553 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4554 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4555 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4556 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4558 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4559 emit_int16(0x76, (0xC0 | encode));
4560 }
4561
4562 // In this context, kdst is written the mask used to process the equal components
4563 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4564 assert(VM_Version::supports_evex(), "");
4565 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4566 attributes.set_is_evex_instruction();
4567 attributes.reset_is_clear_context();
4568 attributes.set_embedded_opmask_register_specifier(mask);
4569 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4570 emit_int16(0x76, (0xC0 | encode));
4571 }
4572
4573 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4574 assert(VM_Version::supports_evex(), "");
4575 InstructionMark im(this);
4576 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4577 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4578 attributes.set_is_evex_instruction();
4579 attributes.reset_is_clear_context();
4580 attributes.set_embedded_opmask_register_specifier(mask);
4581 int dst_enc = kdst->encoding();
4582 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4583 emit_int8(0x76);
4584 emit_operand(as_Register(dst_enc), src, 0);
4585 }
4586
4587 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4588 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
4589 assert(VM_Version::supports_sse4_1(), "");
4590 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4591 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4592 emit_int16(0x29, (0xC0 | encode));
4593 }
4594
4595 void Assembler::evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4596 assert(VM_Version::supports_evex(), "");
4597 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4598 attributes.set_is_evex_instruction();
4599 attributes.reset_is_clear_context();
4600 attributes.set_embedded_opmask_register_specifier(mask);
4601 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4602 emit_int16(0x29, (0xC0 | encode));
4603 }
4604
4605 void Assembler::vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4606 assert(VM_Version::supports_avx(), "");
4607 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4608 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4609 emit_int16(cond_encoding, (0xC0 | encode));
4610 }
4611
4612 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4613 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4614 assert(VM_Version::supports_avx(), "");
4615 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4616 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4617 emit_int16(0x29, (0xC0 | encode));
4618 }
4619
4620 // In this context, kdst is written the mask used to process the equal components
4621 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4622 assert(VM_Version::supports_evex(), "");
4623 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4624 attributes.reset_is_clear_context();
4625 attributes.set_is_evex_instruction();
4626 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4627 emit_int16(0x29, (0xC0 | encode));
4628 }
4629
4630 // In this context, kdst is written the mask used to process the equal components
4631 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4632 assert(VM_Version::supports_evex(), "");
4633 InstructionMark im(this);
4634 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4635 attributes.reset_is_clear_context();
4636 attributes.set_is_evex_instruction();
4637 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4638 int dst_enc = kdst->encoding();
4639 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4640 emit_int8(0x29);
4641 emit_operand(as_Register(dst_enc), src, 0);
4642 }
4643
4644 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
4645 assert(VM_Version::supports_sse4_1(), "");
4646 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4647 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4648 emit_int16(0x37, (0xC0 | encode));
4649 }
4650
4651 void Assembler::pmovmskb(Register dst, XMMRegister src) {
4652 assert(VM_Version::supports_sse2(), "");
4653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4654 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4655 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4656 }
4657
4658 void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
4659 assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||
4660 (VM_Version::supports_avx2() && vec_enc == AVX_256bit), "");
4661 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4662 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4663 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4664 }
4665
4666 void Assembler::vmovmskps(Register dst, XMMRegister src, int vec_enc) {
4667 assert(VM_Version::supports_avx(), "");
4668 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4669 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4670 emit_int16(0x50, (0xC0 | encode));
4671 }
4672
4673 void Assembler::vmovmskpd(Register dst, XMMRegister src, int vec_enc) {
4674 assert(VM_Version::supports_avx(), "");
4675 InstructionAttr attributes(vec_enc, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4676 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4677 emit_int16(0x50, (0xC0 | encode));
4678 }
4679
4680
4681 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
4682 assert(VM_Version::supports_sse4_1(), "");
4683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4684 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4685 emit_int24(0x16, (0xC0 | encode), imm8);
4686 }
4687
4688 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
4689 assert(VM_Version::supports_sse4_1(), "");
4690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4692 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4693 emit_int8(0x16);
4694 emit_operand(src, dst, 1);
4695 emit_int8(imm8);
4696 }
4697
4698 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
4699 assert(VM_Version::supports_sse4_1(), "");
4700 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4701 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4702 emit_int24(0x16, (0xC0 | encode), imm8);
4703 }
4704
4705 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
4706 assert(VM_Version::supports_sse4_1(), "");
4707 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4708 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4709 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4710 emit_int8(0x16);
4711 emit_operand(src, dst, 1);
4712 emit_int8(imm8);
4713 }
4714
4715 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
4716 assert(VM_Version::supports_sse2(), "");
4717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4718 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4719 emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
4720 }
4721
4722 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
4723 assert(VM_Version::supports_sse4_1(), "");
4724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4725 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4726 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4727 emit_int8(0x15);
4728 emit_operand(src, dst, 1);
4729 emit_int8(imm8);
4730 }
4731
4732 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
4733 assert(VM_Version::supports_sse4_1(), "");
4734 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4735 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4736 emit_int24(0x14, (0xC0 | encode), imm8);
4737 }
4738
4739 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
4740 assert(VM_Version::supports_sse4_1(), "");
4741 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4742 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4743 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4744 emit_int8(0x14);
4745 emit_operand(src, dst, 1);
4746 emit_int8(imm8);
4747 }
4748
4749 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
4750 assert(VM_Version::supports_sse4_1(), "");
4751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4752 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4753 emit_int24(0x22, (0xC0 | encode), imm8);
4754 }
4755
4756 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
4757 assert(VM_Version::supports_sse4_1(), "");
4758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4759 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4760 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4761 emit_int8(0x22);
4762 emit_operand(dst, src, 1);
4763 emit_int8(imm8);
4764 }
4765
4766 void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4767 assert(VM_Version::supports_avx(), "");
4768 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4769 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4770 emit_int24(0x22, (0xC0 | encode), imm8);
4771 }
4772
4773 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
4774 assert(VM_Version::supports_sse4_1(), "");
4775 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4776 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4777 emit_int24(0x22, (0xC0 | encode), imm8);
4778 }
4779
4780 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
4781 assert(VM_Version::supports_sse4_1(), "");
4782 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4784 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4785 emit_int8(0x22);
4786 emit_operand(dst, src, 1);
4787 emit_int8(imm8);
4788 }
4789
4790 void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4791 assert(VM_Version::supports_avx(), "");
4792 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4793 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4794 emit_int24(0x22, (0xC0 | encode), imm8);
4795 }
4796
4797 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
4798 assert(VM_Version::supports_sse2(), "");
4799 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4800 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4801 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4802 }
4803
4804 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
4805 assert(VM_Version::supports_sse2(), "");
4806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4808 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4809 emit_int8((unsigned char)0xC4);
4810 emit_operand(dst, src, 1);
4811 emit_int8(imm8);
4812 }
4813
4814 void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4815 assert(VM_Version::supports_avx(), "");
4816 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4818 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4819 }
4820
4821 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
4822 assert(VM_Version::supports_sse4_1(), "");
4823 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4824 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4825 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4826 emit_int8(0x20);
4827 emit_operand(dst, src, 1);
4828 emit_int8(imm8);
4829 }
4830
4831 void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) {
4832 assert(VM_Version::supports_sse4_1(), "");
4833 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4834 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4835 emit_int24(0x20, (0xC0 | encode), imm8);
4836 }
4837
4838 void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4839 assert(VM_Version::supports_avx(), "");
4840 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4841 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4842 emit_int24(0x20, (0xC0 | encode), imm8);
4843 }
4844
4845 void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) {
4846 assert(VM_Version::supports_sse4_1(), "");
4847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4848 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4849 emit_int24(0x21, (0xC0 | encode), imm8);
4850 }
4851
4852 void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4853 assert(VM_Version::supports_avx(), "");
4854 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4855 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4856 emit_int24(0x21, (0xC0 | encode), imm8);
4857 }
4858
4859 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
4860 assert(VM_Version::supports_sse4_1(), "");
4861 InstructionMark im(this);
4862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4863 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4864 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4865 emit_int8(0x30);
4866 emit_operand(dst, src, 0);
4867 }
4868
4869 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4870 assert(VM_Version::supports_sse4_1(), "");
4871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4872 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4873 emit_int16(0x30, (0xC0 | encode));
4874 }
4875
4876 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
4877 assert(VM_Version::supports_sse4_1(), "");
4878 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4879 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4880 emit_int16(0x20, (0xC0 | encode));
4881 }
4882
4883 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
4884 assert(VM_Version::supports_sse4_1(), "");
4885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4886 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4887 emit_int16(0x35, (0xC0 | encode));
4888 }
4889
4890 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
4891 assert(VM_Version::supports_sse4_1(), "");
4892 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4894 emit_int16(0x21, (0xC0 | encode));
4895 }
4896
4897 void Assembler::pmovzxbd(XMMRegister dst, XMMRegister src) {
4898 assert(VM_Version::supports_sse4_1(), "");
4899 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4900 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4901 emit_int16(0x31, (0xC0 | encode));
4902 }
4903
4904 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
4905 assert(VM_Version::supports_sse4_1(), "");
4906 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4907 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4908 emit_int16(0x22, (0xC0 | encode));
4909 }
4910
4911 void Assembler::pmovsxwd(XMMRegister dst, XMMRegister src) {
4912 assert(VM_Version::supports_sse4_1(), "");
4913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4914 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4915 emit_int16(0x23, (0xC0 | encode));
4916 }
4917
4918 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4919 assert(VM_Version::supports_avx(), "");
4920 InstructionMark im(this);
4921 assert(dst != xnoreg, "sanity");
4922 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4923 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4924 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4925 emit_int8(0x30);
4926 emit_operand(dst, src, 0);
4927 }
4928
4929 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4930 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4931 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4932 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4933 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4934 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4935 emit_int16(0x30, (unsigned char) (0xC0 | encode));
4936 }
4937
4938 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4939 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4940 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4941 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4942 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4943 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4944 emit_int16(0x20, (0xC0 | encode));
4945 }
4946
4947 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4948 assert(VM_Version::supports_avx512vlbw(), "");
4949 assert(dst != xnoreg, "sanity");
4950 InstructionMark im(this);
4951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4952 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4953 attributes.set_embedded_opmask_register_specifier(mask);
4954 attributes.set_is_evex_instruction();
4955 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4956 emit_int8(0x30);
4957 emit_operand(dst, src, 0);
4958 }
4959
4960 void Assembler::evpmovzxbd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4961 assert(VM_Version::supports_avx512vl(), "");
4962 assert(dst != xnoreg, "sanity");
4963 InstructionMark im(this);
4964 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4965 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4966 attributes.set_embedded_opmask_register_specifier(mask);
4967 attributes.set_is_evex_instruction();
4968 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4969 emit_int8(0x31);
4970 emit_operand(dst, src, 0);
4971 }
4972
4973 void Assembler::evpmovzxbd(XMMRegister dst, Address src, int vector_len) {
4974 evpmovzxbd(dst, k0, src, vector_len);
4975 }
4976
4977 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
4978 assert(VM_Version::supports_evex(), "");
4979 // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
4980 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4981 attributes.set_is_evex_instruction();
4982 attributes.set_embedded_opmask_register_specifier(mask);
4983 if (merge) {
4984 attributes.reset_is_clear_context();
4985 }
4986 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4987 emit_int16((unsigned char)0xDB, (0xC0 | encode));
4988 }
4989
4990 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4991 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4992 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4993 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4994 emit_int16(0x35, (0xC0 | encode));
4995 }
4996
4997 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4998 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4999 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5000 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5001 emit_int16(0x31, (0xC0 | encode));
5002 }
5003
5004 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
5005 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
5006 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5007 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5008 emit_int16(0x32, (0xC0 | encode));
5009 }
5010
5011 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
5012 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5013 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5014 VM_Version::supports_evex(), "");
5015 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5016 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5017 emit_int16(0x21, (0xC0 | encode));
5018 }
5019
5020 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
5021 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5022 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5023 VM_Version::supports_evex(), "");
5024 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5025 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5026 emit_int16(0x22, (0xC0 | encode));
5027 }
5028
5029 void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5030 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5031 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5032 VM_Version::supports_evex(), "");
5033 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5034 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5035 emit_int16(0x23, (0xC0 | encode));
5036 }
5037
5038 void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5039 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5040 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5041 VM_Version::supports_evex(), "");
5042 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5043 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5044 emit_int16(0x24, (0xC0 | encode));
5045 }
5046
5047 void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
5048 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5049 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5050 VM_Version::supports_evex(), "");
5051 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5052 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5053 emit_int16(0x25, (0xC0 | encode));
5054 }
5055
5056 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
5057 assert(VM_Version::supports_avx512vlbw(), "");
5058 assert(src != xnoreg, "sanity");
5059 InstructionMark im(this);
5060 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5061 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5062 attributes.set_is_evex_instruction();
5063 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5064 emit_int8(0x30);
5065 emit_operand(src, dst, 0);
5066 }
5067
5068 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
5069 assert(VM_Version::supports_avx512vlbw(), "");
5070 assert(src != xnoreg, "sanity");
5071 InstructionMark im(this);
5072 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5073 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5074 attributes.reset_is_clear_context();
5075 attributes.set_embedded_opmask_register_specifier(mask);
5076 attributes.set_is_evex_instruction();
5077 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5078 emit_int8(0x30);
5079 emit_operand(src, dst, 0);
5080 }
5081
5082 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
5083 assert(VM_Version::supports_evex(), "");
5084 assert(src != xnoreg, "sanity");
5085 InstructionMark im(this);
5086 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5087 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
5088 attributes.set_is_evex_instruction();
5089 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5090 emit_int8(0x31);
5091 emit_operand(src, dst, 0);
5092 }
5093
5094 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5095 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5096 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5097 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5098 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5099 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5100 emit_int16(0x33, (0xC0 | encode));
5101 }
5102
5103 void Assembler::vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5104 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5105 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5106 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5107 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5108 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5109 emit_int16(0x34, (0xC0 | encode));
5110 }
5111
5112 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5116 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5117 }
5118
5119 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5120 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5121 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5122 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
5123 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5124 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5125 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5126 }
5127
5128 void Assembler::vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5129 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5130 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5131 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5132 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5133 int encode = simd_prefix_and_encode(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5134 emit_int16(0x04, (0xC0 | encode));
5135 }
5136
5137 void Assembler::evpmadd52luq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5138 evpmadd52luq(dst, k0, src1, src2, false, vector_len);
5139 }
5140
5141 void Assembler::evpmadd52luq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5142 assert(VM_Version::supports_avx512ifma(), "");
5143 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 attributes.set_is_evex_instruction();
5145 attributes.set_embedded_opmask_register_specifier(mask);
5146 if (merge) {
5147 attributes.reset_is_clear_context();
5148 }
5149
5150 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5151 emit_int16((unsigned char)0xB4, (0xC0 | encode));
5152 }
5153
5154 void Assembler::evpmadd52huq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5155 evpmadd52huq(dst, k0, src1, src2, false, vector_len);
5156 }
5157
5158 void Assembler::evpmadd52huq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5159 assert(VM_Version::supports_avx512ifma(), "");
5160 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5161 attributes.set_is_evex_instruction();
5162 attributes.set_embedded_opmask_register_specifier(mask);
5163 if (merge) {
5164 attributes.reset_is_clear_context();
5165 }
5166
5167 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5168 emit_int16((unsigned char)0xB5, (0xC0 | encode));
5169 }
5170
5171 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5172 assert(VM_Version::supports_evex(), "");
5173 assert(VM_Version::supports_avx512_vnni(), "must support vnni");
5174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5175 attributes.set_is_evex_instruction();
5176 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5177 emit_int16(0x52, (0xC0 | encode));
5178 }
5179
5180 // generic
5181 void Assembler::pop(Register dst) {
5182 int encode = prefix_and_encode(dst->encoding());
5183 emit_int8(0x58 | encode);
5184 }
5185
5186 void Assembler::popcntl(Register dst, Address src) {
5187 assert(VM_Version::supports_popcnt(), "must support");
5188 InstructionMark im(this);
5189 emit_int8((unsigned char)0xF3);
5190 prefix(src, dst);
5191 emit_int16(0x0F, (unsigned char)0xB8);
5192 emit_operand(dst, src, 0);
5193 }
5194
5195 void Assembler::popcntl(Register dst, Register src) {
5196 assert(VM_Version::supports_popcnt(), "must support");
5197 emit_int8((unsigned char)0xF3);
5198 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5199 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
5200 }
5201
5202 void Assembler::evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5203 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5204 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5205 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5206 attributes.set_embedded_opmask_register_specifier(mask);
5207 attributes.set_is_evex_instruction();
5208 if (merge) {
5209 attributes.reset_is_clear_context();
5210 }
5211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5212 emit_int16(0x54, (0xC0 | encode));
5213 }
5214
5215 void Assembler::evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5216 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5217 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5218 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_is_evex_instruction();
5220 attributes.set_embedded_opmask_register_specifier(mask);
5221 if (merge) {
5222 attributes.reset_is_clear_context();
5223 }
5224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5225 emit_int16(0x54, (0xC0 | encode));
5226 }
5227
5228 void Assembler::evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5229 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5230 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5231 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5232 attributes.set_is_evex_instruction();
5233 attributes.set_embedded_opmask_register_specifier(mask);
5234 if (merge) {
5235 attributes.reset_is_clear_context();
5236 }
5237 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5238 emit_int16(0x55, (0xC0 | encode));
5239 }
5240
5241 void Assembler::evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5242 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5243 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5244 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5245 attributes.set_is_evex_instruction();
5246 attributes.set_embedded_opmask_register_specifier(mask);
5247 if (merge) {
5248 attributes.reset_is_clear_context();
5249 }
5250 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5251 emit_int16(0x55, (0xC0 | encode));
5252 }
5253
5254 void Assembler::popf() {
5255 emit_int8((unsigned char)0x9D);
5256 }
5257
5258 #ifndef _LP64 // no 32bit push/pop on amd64
5259 void Assembler::popl(Address dst) {
5260 // NOTE: this will adjust stack by 8byte on 64bits
5261 InstructionMark im(this);
5262 prefix(dst);
5263 emit_int8((unsigned char)0x8F);
5264 emit_operand(rax, dst, 0);
5265 }
5266 #endif
5267
5268 void Assembler::prefetchnta(Address src) {
5269 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5270 InstructionMark im(this);
5271 prefix(src);
5272 emit_int16(0x0F, 0x18);
5273 emit_operand(rax, src, 0); // 0, src
5274 }
5275
5276 void Assembler::prefetchr(Address src) {
5277 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5278 InstructionMark im(this);
5279 prefix(src);
5280 emit_int16(0x0F, 0x0D);
5281 emit_operand(rax, src, 0); // 0, src
5282 }
5283
5284 void Assembler::prefetcht0(Address src) {
5285 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5286 InstructionMark im(this);
5287 prefix(src);
5288 emit_int16(0x0F, 0x18);
5289 emit_operand(rcx, src, 0); // 1, src
5290 }
5291
5292 void Assembler::prefetcht1(Address src) {
5293 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5294 InstructionMark im(this);
5295 prefix(src);
5296 emit_int16(0x0F, 0x18);
5297 emit_operand(rdx, src, 0); // 2, src
5298 }
5299
5300 void Assembler::prefetcht2(Address src) {
5301 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5302 InstructionMark im(this);
5303 prefix(src);
5304 emit_int16(0x0F, 0x18);
5305 emit_operand(rbx, src, 0); // 3, src
5306 }
5307
5308 void Assembler::prefetchw(Address src) {
5309 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5310 InstructionMark im(this);
5311 prefix(src);
5312 emit_int16(0x0F, 0x0D);
5313 emit_operand(rcx, src, 0); // 1, src
5314 }
5315
5316 void Assembler::prefix(Prefix p) {
5317 emit_int8(p);
5318 }
5319
5320 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
5321 assert(VM_Version::supports_ssse3(), "");
5322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5324 emit_int16(0x00, (0xC0 | encode));
5325 }
5326
5327 void Assembler::evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
5328 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
5329 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5330 attributes.set_is_evex_instruction();
5331 attributes.set_embedded_opmask_register_specifier(mask);
5332 if (merge) {
5333 attributes.reset_is_clear_context();
5334 }
5335 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5336 emit_int16(0x00, (0xC0 | encode));
5337 }
5338
5339 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5340 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5341 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5342 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5343 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5344 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5345 emit_int16(0x00, (0xC0 | encode));
5346 }
5347
5348 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5349 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5350 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5351 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5352 InstructionMark im(this);
5353 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5354 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5355 simd_prefix(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5356 emit_int8(0x00);
5357 emit_operand(dst, src, 0);
5358 }
5359
5360 void Assembler::pshufb(XMMRegister dst, Address src) {
5361 assert(VM_Version::supports_ssse3(), "");
5362 InstructionMark im(this);
5363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5365 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5366 emit_int8(0x00);
5367 emit_operand(dst, src, 0);
5368 }
5369
5370 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
5371 assert(isByte(mode), "invalid value");
5372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5373 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
5374 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5375 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5376 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5377 }
5378
5379 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5380 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5381 (vector_len == AVX_256bit? VM_Version::supports_avx2() :
5382 (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
5383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5384 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5385 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5386 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5387 }
5388
5389 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
5390 assert(isByte(mode), "invalid value");
5391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5392 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5393 InstructionMark im(this);
5394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5395 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5396 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5397 emit_int8(0x70);
5398 emit_operand(dst, src, 1);
5399 emit_int8(mode & 0xFF);
5400 }
5401
5402 void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) {
5403 assert(isByte(mode), "invalid value");
5404 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5406 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5407 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5408 }
5409
5410 void Assembler::vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5411 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5412 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5413 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5415 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5416 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5417 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5418 }
5419
5420 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5421 assert(isByte(mode), "invalid value");
5422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5424 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5425 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5426 }
5427
5428 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
5429 assert(isByte(mode), "invalid value");
5430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5431 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5432 InstructionMark im(this);
5433 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5434 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5435 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5436 emit_int8(0x70);
5437 emit_operand(dst, src, 1);
5438 emit_int8(mode & 0xFF);
5439 }
5440
5441 void Assembler::vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5442 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5443 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5444 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5446 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5447 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5448 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5449 }
5450
5451 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5452 assert(VM_Version::supports_evex(), "requires EVEX support");
5453 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
5454 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5455 attributes.set_is_evex_instruction();
5456 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5457 emit_int24(0x43, (0xC0 | encode), imm8 & 0xFF);
5458 }
5459
5460 void Assembler::shufpd(XMMRegister dst, XMMRegister src, int imm8) {
5461 assert(isByte(imm8), "invalid value");
5462 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5463 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5464 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5465 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5466 }
5467
5468 void Assembler::vshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5469 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5470 attributes.set_rex_vex_w_reverted();
5471 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5472 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5473 }
5474
5475 void Assembler::shufps(XMMRegister dst, XMMRegister src, int imm8) {
5476 assert(isByte(imm8), "invalid value");
5477 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5479 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5480 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5481 }
5482
5483 void Assembler::vshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5484 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5485 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5486 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5487 }
5488
5489 void Assembler::psrldq(XMMRegister dst, int shift) {
5490 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5492 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5493 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5494 emit_int24(0x73, (0xC0 | encode), shift);
5495 }
5496
5497 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5498 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5499 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5500 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5501 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5502 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5503 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5504 }
5505
5506 void Assembler::pslldq(XMMRegister dst, int shift) {
5507 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5508 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5509 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5510 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
5511 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5512 emit_int24(0x73, (0xC0 | encode), shift);
5513 }
5514
5515 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5516 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5517 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5518 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5519 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5520 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5521 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5522 }
5523
5524 void Assembler::ptest(XMMRegister dst, Address src) {
5525 assert(VM_Version::supports_sse4_1(), "");
5526 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5527 InstructionMark im(this);
5528 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5529 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5530 emit_int8(0x17);
5531 emit_operand(dst, src, 0);
5532 }
5533
5534 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
5535 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
5536 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5537 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5538 emit_int8(0x17);
5539 emit_int8((0xC0 | encode));
5540 }
5541
5542 void Assembler::vptest(XMMRegister dst, Address src) {
5543 assert(VM_Version::supports_avx(), "");
5544 InstructionMark im(this);
5545 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5546 assert(dst != xnoreg, "sanity");
5547 // swap src<->dst for encoding
5548 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5549 emit_int8(0x17);
5550 emit_operand(dst, src, 0);
5551 }
5552
5553 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
5554 assert(VM_Version::supports_avx(), "");
5555 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5556 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5557 emit_int16(0x17, (0xC0 | encode));
5558 }
5559
5560 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
5561 assert(VM_Version::supports_avx(), "");
5562 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5563 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5564 emit_int16(0x17, (0xC0 | encode));
5565 }
5566
5567 void Assembler::vtestps(XMMRegister dst, XMMRegister src, int vector_len) {
5568 assert(VM_Version::supports_avx(), "");
5569 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5570 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5571 emit_int16(0x0E, (0xC0 | encode));
5572 }
5573
5574 void Assembler::evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5575 assert(vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : VM_Version::supports_avx512vlbw(), "");
5576 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5578 attributes.set_is_evex_instruction();
5579 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5580 emit_int16(0x26, (0xC0 | encode));
5581 }
5582
5583 void Assembler::evptestmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5584 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5585 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5587 attributes.set_is_evex_instruction();
5588 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5589 emit_int16(0x27, (0xC0 | encode));
5590 }
5591
5592 void Assembler::evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5593 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5594 // Encoding: EVEX.NDS.XXX.F3.0F38.W0 DB /r
5595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5596 attributes.set_is_evex_instruction();
5597 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5598 emit_int16(0x27, (0xC0 | encode));
5599 }
5600
5601 void Assembler::punpcklbw(XMMRegister dst, Address src) {
5602 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5603 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5604 InstructionMark im(this);
5605 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5606 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5607 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5608 emit_int8(0x60);
5609 emit_operand(dst, src, 0);
5610 }
5611
5612 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
5613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5615 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int16(0x60, (0xC0 | encode));
5617 }
5618
5619 void Assembler::punpckldq(XMMRegister dst, Address src) {
5620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5621 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5622 InstructionMark im(this);
5623 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5624 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5625 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5626 emit_int8(0x62);
5627 emit_operand(dst, src, 0);
5628 }
5629
5630 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
5631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5632 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5633 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int16(0x62, (0xC0 | encode));
5635 }
5636
5637 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
5638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5639 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5640 attributes.set_rex_vex_w_reverted();
5641 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5642 emit_int16(0x6C, (0xC0 | encode));
5643 }
5644
5645 void Assembler::evpunpcklqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5646 evpunpcklqdq(dst, k0, src1, src2, false, vector_len);
5647 }
5648
5649 void Assembler::evpunpcklqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5650 assert(VM_Version::supports_evex(), "requires AVX512F");
5651 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5652 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5653 attributes.set_is_evex_instruction();
5654 attributes.set_embedded_opmask_register_specifier(mask);
5655 if (merge) {
5656 attributes.reset_is_clear_context();
5657 }
5658
5659 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5660 emit_int16(0x6C, (0xC0 | encode));
5661 }
5662
5663 void Assembler::evpunpckhqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5664 evpunpckhqdq(dst, k0, src1, src2, false, vector_len);
5665 }
5666
5667 void Assembler::evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5668 assert(VM_Version::supports_evex(), "requires AVX512F");
5669 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5670 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5671 attributes.set_is_evex_instruction();
5672 attributes.set_embedded_opmask_register_specifier(mask);
5673 if (merge) {
5674 attributes.reset_is_clear_context();
5675 }
5676
5677 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5678 emit_int16(0x6D, (0xC0 | encode));
5679 }
5680
5681 void Assembler::push(int32_t imm32) {
5682 // in 64bits we push 64bits onto the stack but only
5683 // take a 32bit immediate
5684 emit_int8(0x68);
5685 emit_int32(imm32);
5686 }
5687
5688 void Assembler::push(Register src) {
5689 int encode = prefix_and_encode(src->encoding());
5690 emit_int8(0x50 | encode);
5691 }
5692
5693 void Assembler::pushf() {
5694 emit_int8((unsigned char)0x9C);
5695 }
5696
5697 #ifndef _LP64 // no 32bit push/pop on amd64
5698 void Assembler::pushl(Address src) {
5699 // Note this will push 64bit on 64bit
5700 InstructionMark im(this);
5701 prefix(src);
5702 emit_int8((unsigned char)0xFF);
5703 emit_operand(rsi, src, 0);
5704 }
5705 #endif
5706
5707 void Assembler::rcll(Register dst, int imm8) {
5708 assert(isShiftCount(imm8), "illegal shift count");
5709 int encode = prefix_and_encode(dst->encoding());
5710 if (imm8 == 1) {
5711 emit_int16((unsigned char)0xD1, (0xD0 | encode));
5712 } else {
5713 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
5714 }
5715 }
5716
5717 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
5718 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5721 emit_int16(0x53, (0xC0 | encode));
5722 }
5723
5724 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
5725 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5727 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5728 emit_int16(0x53, (0xC0 | encode));
5729 }
5730
5731 void Assembler::rdtsc() {
5732 emit_int16(0x0F, 0x31);
5733 }
5734
5735 // copies data from [esi] to [edi] using rcx pointer sized words
5736 // generic
5737 void Assembler::rep_mov() {
5738 // REP
5739 // MOVSQ
5740 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
5741 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);)
5742 }
5743
5744 // sets rcx bytes with rax, value at [edi]
5745 void Assembler::rep_stosb() {
5746 // REP
5747 // STOSB
5748 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
5749 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);)
5750 }
5751
5752 // sets rcx pointer sized words with rax, value at [edi]
5753 // generic
5754 void Assembler::rep_stos() {
5755 // REP
5756 // LP64:STOSQ, LP32:STOSD
5757 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
5758 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
5759 }
5760
5761 // scans rcx pointer sized words at [edi] for occurrence of rax,
5762 // generic
5763 void Assembler::repne_scan() { // repne_scan
5764 // SCASQ
5765 LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
5766 NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);)
5767 }
5768
5769 #ifdef _LP64
5770 // scans rcx 4 byte words at [edi] for occurrence of rax,
5771 // generic
5772 void Assembler::repne_scanl() { // repne_scan
5773 // SCASL
5774 emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
5775 }
5776 #endif
5777
5778 void Assembler::ret(int imm16) {
5779 if (imm16 == 0) {
5780 emit_int8((unsigned char)0xC3);
5781 } else {
5782 emit_int8((unsigned char)0xC2);
5783 emit_int16(imm16);
5784 }
5785 }
5786
5787 void Assembler::roll(Register dst, int imm8) {
5788 assert(isShiftCount(imm8), "illegal shift count");
5789 int encode = prefix_and_encode(dst->encoding());
5790 if (imm8 == 1) {
5791 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5792 } else {
5793 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5794 }
5795 }
5796
5797 void Assembler::roll(Register dst) {
5798 int encode = prefix_and_encode(dst->encoding());
5799 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5800 }
5801
5802 void Assembler::rorl(Register dst, int imm8) {
5803 assert(isShiftCount(imm8), "illegal shift count");
5804 int encode = prefix_and_encode(dst->encoding());
5805 if (imm8 == 1) {
5806 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5807 } else {
5808 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5809 }
5810 }
5811
5812 void Assembler::rorl(Register dst) {
5813 int encode = prefix_and_encode(dst->encoding());
5814 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5815 }
5816
5817 #ifdef _LP64
5818 void Assembler::rorq(Register dst) {
5819 int encode = prefixq_and_encode(dst->encoding());
5820 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5821 }
5822
5823 void Assembler::rorq(Register dst, int imm8) {
5824 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5825 int encode = prefixq_and_encode(dst->encoding());
5826 if (imm8 == 1) {
5827 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5828 } else {
5829 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5830 }
5831 }
5832
5833 void Assembler::rolq(Register dst) {
5834 int encode = prefixq_and_encode(dst->encoding());
5835 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5836 }
5837
5838 void Assembler::rolq(Register dst, int imm8) {
5839 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5840 int encode = prefixq_and_encode(dst->encoding());
5841 if (imm8 == 1) {
5842 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5843 } else {
5844 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5845 }
5846 }
5847 #endif
5848
5849 void Assembler::sahf() {
5850 #ifdef _LP64
5851 // Not supported in 64bit mode
5852 ShouldNotReachHere();
5853 #endif
5854 emit_int8((unsigned char)0x9E);
5855 }
5856
5857 void Assembler::sall(Address dst, int imm8) {
5858 InstructionMark im(this);
5859 assert(isShiftCount(imm8), "illegal shift count");
5860 prefix(dst);
5861 if (imm8 == 1) {
5862 emit_int8((unsigned char)0xD1);
5863 emit_operand(as_Register(4), dst, 0);
5864 }
5865 else {
5866 emit_int8((unsigned char)0xC1);
5867 emit_operand(as_Register(4), dst, 1);
5868 emit_int8(imm8);
5869 }
5870 }
5871
5872 void Assembler::sall(Address dst) {
5873 InstructionMark im(this);
5874 prefix(dst);
5875 emit_int8((unsigned char)0xD3);
5876 emit_operand(as_Register(4), dst, 0);
5877 }
5878
5879 void Assembler::sall(Register dst, int imm8) {
5880 assert(isShiftCount(imm8), "illegal shift count");
5881 int encode = prefix_and_encode(dst->encoding());
5882 if (imm8 == 1) {
5883 emit_int16((unsigned char)0xD1, (0xE0 | encode));
5884 } else {
5885 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
5886 }
5887 }
5888
5889 void Assembler::sall(Register dst) {
5890 int encode = prefix_and_encode(dst->encoding());
5891 emit_int16((unsigned char)0xD3, (0xE0 | encode));
5892 }
5893
5894 void Assembler::sarl(Address dst, int imm8) {
5895 assert(isShiftCount(imm8), "illegal shift count");
5896 InstructionMark im(this);
5897 prefix(dst);
5898 if (imm8 == 1) {
5899 emit_int8((unsigned char)0xD1);
5900 emit_operand(as_Register(7), dst, 0);
5901 }
5902 else {
5903 emit_int8((unsigned char)0xC1);
5904 emit_operand(as_Register(7), dst, 1);
5905 emit_int8(imm8);
5906 }
5907 }
5908
5909 void Assembler::sarl(Address dst) {
5910 InstructionMark im(this);
5911 prefix(dst);
5912 emit_int8((unsigned char)0xD3);
5913 emit_operand(as_Register(7), dst, 0);
5914 }
5915
5916 void Assembler::sarl(Register dst, int imm8) {
5917 int encode = prefix_and_encode(dst->encoding());
5918 assert(isShiftCount(imm8), "illegal shift count");
5919 if (imm8 == 1) {
5920 emit_int16((unsigned char)0xD1, (0xF8 | encode));
5921 } else {
5922 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
5923 }
5924 }
5925
5926 void Assembler::sarl(Register dst) {
5927 int encode = prefix_and_encode(dst->encoding());
5928 emit_int16((unsigned char)0xD3, (0xF8 | encode));
5929 }
5930
5931 void Assembler::sbbl(Address dst, int32_t imm32) {
5932 InstructionMark im(this);
5933 prefix(dst);
5934 emit_arith_operand(0x81, rbx, dst, imm32);
5935 }
5936
5937 void Assembler::sbbl(Register dst, int32_t imm32) {
5938 prefix(dst);
5939 emit_arith(0x81, 0xD8, dst, imm32);
5940 }
5941
5942
5943 void Assembler::sbbl(Register dst, Address src) {
5944 InstructionMark im(this);
5945 prefix(src, dst);
5946 emit_int8(0x1B);
5947 emit_operand(dst, src, 0);
5948 }
5949
5950 void Assembler::sbbl(Register dst, Register src) {
5951 (void) prefix_and_encode(dst->encoding(), src->encoding());
5952 emit_arith(0x1B, 0xC0, dst, src);
5953 }
5954
5955 void Assembler::setb(Condition cc, Register dst) {
5956 assert(0 <= cc && cc < 16, "illegal cc");
5957 int encode = prefix_and_encode(dst->encoding(), true);
5958 emit_int24(0x0F, (unsigned char)0x90 | cc, (0xC0 | encode));
5959 }
5960
5961 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
5962 assert(VM_Version::supports_ssse3(), "");
5963 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5964 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5965 emit_int24(0x0F, (0xC0 | encode), imm8);
5966 }
5967
5968 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5969 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5970 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5971 0, "");
5972 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5973 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5974 emit_int24(0x0F, (0xC0 | encode), imm8);
5975 }
5976
5977 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5978 assert(VM_Version::supports_evex(), "");
5979 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5980 attributes.set_is_evex_instruction();
5981 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5982 emit_int24(0x3, (0xC0 | encode), imm8);
5983 }
5984
5985 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
5986 assert(VM_Version::supports_sse4_1(), "");
5987 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5988 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5989 emit_int24(0x0E, (0xC0 | encode), imm8);
5990 }
5991
5992 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
5993 assert(VM_Version::supports_sha(), "");
5994 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
5995 emit_int24((unsigned char)0xCC, (0xC0 | encode), (unsigned char)imm8);
5996 }
5997
5998 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
5999 assert(VM_Version::supports_sha(), "");
6000 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6001 emit_int16((unsigned char)0xC8, (0xC0 | encode));
6002 }
6003
6004 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
6005 assert(VM_Version::supports_sha(), "");
6006 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6007 emit_int16((unsigned char)0xC9, (0xC0 | encode));
6008 }
6009
6010 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
6011 assert(VM_Version::supports_sha(), "");
6012 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6013 emit_int16((unsigned char)0xCA, (0xC0 | encode));
6014 }
6015
6016 // xmm0 is implicit additional source to this instruction.
6017 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
6018 assert(VM_Version::supports_sha(), "");
6019 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6020 emit_int16((unsigned char)0xCB, (0xC0 | encode));
6021 }
6022
6023 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
6024 assert(VM_Version::supports_sha(), "");
6025 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6026 emit_int16((unsigned char)0xCC, (0xC0 | encode));
6027 }
6028
6029 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
6030 assert(VM_Version::supports_sha(), "");
6031 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6032 emit_int16((unsigned char)0xCD, (0xC0 | encode));
6033 }
6034
6035
6036 void Assembler::shll(Register dst, int imm8) {
6037 assert(isShiftCount(imm8), "illegal shift count");
6038 int encode = prefix_and_encode(dst->encoding());
6039 if (imm8 == 1 ) {
6040 emit_int16((unsigned char)0xD1, (0xE0 | encode));
6041 } else {
6042 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
6043 }
6044 }
6045
6046 void Assembler::shll(Register dst) {
6047 int encode = prefix_and_encode(dst->encoding());
6048 emit_int16((unsigned char)0xD3, (0xE0 | encode));
6049 }
6050
6051 void Assembler::shrl(Register dst, int imm8) {
6052 assert(isShiftCount(imm8), "illegal shift count");
6053 int encode = prefix_and_encode(dst->encoding());
6054 if (imm8 == 1) {
6055 emit_int16((unsigned char)0xD1, (0xE8 | encode));
6056 }
6057 else {
6058 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
6059 }
6060 }
6061
6062 void Assembler::shrl(Register dst) {
6063 int encode = prefix_and_encode(dst->encoding());
6064 emit_int16((unsigned char)0xD3, (0xE8 | encode));
6065 }
6066
6067 void Assembler::shrl(Address dst) {
6068 InstructionMark im(this);
6069 prefix(dst);
6070 emit_int8((unsigned char)0xD3);
6071 emit_operand(as_Register(5), dst, 0);
6072 }
6073
6074 void Assembler::shrl(Address dst, int imm8) {
6075 InstructionMark im(this);
6076 assert(isShiftCount(imm8), "illegal shift count");
6077 prefix(dst);
6078 if (imm8 == 1) {
6079 emit_int8((unsigned char)0xD1);
6080 emit_operand(as_Register(5), dst, 0);
6081 }
6082 else {
6083 emit_int8((unsigned char)0xC1);
6084 emit_operand(as_Register(5), dst, 1);
6085 emit_int8(imm8);
6086 }
6087 }
6088
6089
6090 void Assembler::shldl(Register dst, Register src) {
6091 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6092 emit_int24(0x0F, (unsigned char)0xA5, (0xC0 | encode));
6093 }
6094
6095 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6096 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6097 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6098 }
6099
6100 void Assembler::shrdl(Register dst, Register src) {
6101 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6102 emit_int24(0x0F, (unsigned char)0xAD, (0xC0 | encode));
6103 }
6104
6105 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
6106 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6107 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6108 }
6109
6110 #ifdef _LP64
6111 void Assembler::shldq(Register dst, Register src, int8_t imm8) {
6112 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6113 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6114 }
6115
6116 void Assembler::shrdq(Register dst, Register src, int8_t imm8) {
6117 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6118 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6119 }
6120 #endif
6121
6122 // copies a single word from [esi] to [edi]
6123 void Assembler::smovl() {
6124 emit_int8((unsigned char)0xA5);
6125 }
6126
6127 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
6128 assert(VM_Version::supports_sse4_1(), "");
6129 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6130 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6131 emit_int24(0x0B, (0xC0 | encode), (unsigned char)rmode);
6132 }
6133
6134 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
6135 assert(VM_Version::supports_sse4_1(), "");
6136 InstructionMark im(this);
6137 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6138 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6139 emit_int8(0x0B);
6140 emit_operand(dst, src, 1);
6141 emit_int8((unsigned char)rmode);
6142 }
6143
6144 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
6145 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6146 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6147 attributes.set_rex_vex_w_reverted();
6148 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6149 emit_int16(0x51, (0xC0 | encode));
6150 }
6151
6152 void Assembler::sqrtsd(XMMRegister dst, Address src) {
6153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6154 InstructionMark im(this);
6155 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6156 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6157 attributes.set_rex_vex_w_reverted();
6158 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6159 emit_int8(0x51);
6160 emit_operand(dst, src, 0);
6161 }
6162
6163 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
6164 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6165 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6166 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6167 emit_int16(0x51, (0xC0 | encode));
6168 }
6169
6170 void Assembler::std() {
6171 emit_int8((unsigned char)0xFD);
6172 }
6173
6174 void Assembler::sqrtss(XMMRegister dst, Address src) {
6175 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6176 InstructionMark im(this);
6177 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6178 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6179 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6180 emit_int8(0x51);
6181 emit_operand(dst, src, 0);
6182 }
6183
6184 void Assembler::stmxcsr( Address dst) {
6185 if (UseAVX > 0 ) {
6186 assert(VM_Version::supports_avx(), "");
6187 InstructionMark im(this);
6188 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6189 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6190 emit_int8((unsigned char)0xAE);
6191 emit_operand(as_Register(3), dst, 0);
6192 } else {
6193 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6194 InstructionMark im(this);
6195 prefix(dst);
6196 emit_int16(0x0F, (unsigned char)0xAE);
6197 emit_operand(as_Register(3), dst, 0);
6198 }
6199 }
6200
6201 void Assembler::subl(Address dst, int32_t imm32) {
6202 InstructionMark im(this);
6203 prefix(dst);
6204 emit_arith_operand(0x81, rbp, dst, imm32);
6205 }
6206
6207 void Assembler::subl(Address dst, Register src) {
6208 InstructionMark im(this);
6209 prefix(dst, src);
6210 emit_int8(0x29);
6211 emit_operand(src, dst, 0);
6212 }
6213
6214 void Assembler::subl(Register dst, int32_t imm32) {
6215 prefix(dst);
6216 emit_arith(0x81, 0xE8, dst, imm32);
6217 }
6218
6219 // Force generation of a 4 byte immediate value even if it fits into 8bit
6220 void Assembler::subl_imm32(Register dst, int32_t imm32) {
6221 prefix(dst);
6222 emit_arith_imm32(0x81, 0xE8, dst, imm32);
6223 }
6224
6225 void Assembler::subl(Register dst, Address src) {
6226 InstructionMark im(this);
6227 prefix(src, dst);
6228 emit_int8(0x2B);
6229 emit_operand(dst, src, 0);
6230 }
6231
6232 void Assembler::subl(Register dst, Register src) {
6233 (void) prefix_and_encode(dst->encoding(), src->encoding());
6234 emit_arith(0x2B, 0xC0, dst, src);
6235 }
6236
6237 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
6238 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6239 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6240 attributes.set_rex_vex_w_reverted();
6241 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6242 emit_int16(0x5C, (0xC0 | encode));
6243 }
6244
6245 void Assembler::subsd(XMMRegister dst, Address src) {
6246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6247 InstructionMark im(this);
6248 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6249 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6250 attributes.set_rex_vex_w_reverted();
6251 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6252 emit_int8(0x5C);
6253 emit_operand(dst, src, 0);
6254 }
6255
6256 void Assembler::subss(XMMRegister dst, XMMRegister src) {
6257 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
6259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6260 emit_int16(0x5C, (0xC0 | encode));
6261 }
6262
6263 void Assembler::subss(XMMRegister dst, Address src) {
6264 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6265 InstructionMark im(this);
6266 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6268 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6269 emit_int8(0x5C);
6270 emit_operand(dst, src, 0);
6271 }
6272
6273 void Assembler::testb(Register dst, int imm8, bool use_ral) {
6274 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
6275 if (dst == rax) {
6276 if (use_ral) {
6277 emit_int8((unsigned char)0xA8);
6278 emit_int8(imm8);
6279 } else {
6280 emit_int8((unsigned char)0xF6);
6281 emit_int8((unsigned char)0xC4);
6282 emit_int8(imm8);
6283 }
6284 } else {
6285 (void) prefix_and_encode(dst->encoding(), true);
6286 emit_arith_b(0xF6, 0xC0, dst, imm8);
6287 }
6288 }
6289
6290 void Assembler::testb(Address dst, int imm8) {
6291 InstructionMark im(this);
6292 prefix(dst);
6293 emit_int8((unsigned char)0xF6);
6294 emit_operand(rax, dst, 1);
6295 emit_int8(imm8);
6296 }
6297
6298 void Assembler::testl(Address dst, int32_t imm32) {
6299 InstructionMark im(this);
6300 prefix(dst);
6301 emit_int8((unsigned char)0xF7);
6302 emit_operand(as_Register(0), dst, 4);
6303 emit_int32(imm32);
6304 }
6305
6306 void Assembler::testl(Register dst, int32_t imm32) {
6307 // not using emit_arith because test
6308 // doesn't support sign-extension of
6309 // 8bit operands
6310 if (dst == rax) {
6311 emit_int8((unsigned char)0xA9);
6312 emit_int32(imm32);
6313 } else {
6314 int encode = dst->encoding();
6315 encode = prefix_and_encode(encode);
6316 emit_int16((unsigned char)0xF7, (0xC0 | encode));
6317 emit_int32(imm32);
6318 }
6319 }
6320
6321 void Assembler::testl(Register dst, Register src) {
6322 (void) prefix_and_encode(dst->encoding(), src->encoding());
6323 emit_arith(0x85, 0xC0, dst, src);
6324 }
6325
6326 void Assembler::testl(Register dst, Address src) {
6327 InstructionMark im(this);
6328 prefix(src, dst);
6329 emit_int8((unsigned char)0x85);
6330 emit_operand(dst, src, 0);
6331 }
6332
6333 void Assembler::tzcntl(Register dst, Register src) {
6334 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6335 emit_int8((unsigned char)0xF3);
6336 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6337 emit_int24(0x0F,
6338 (unsigned char)0xBC,
6339 0xC0 | encode);
6340 }
6341
6342 void Assembler::tzcntl(Register dst, Address src) {
6343 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6344 InstructionMark im(this);
6345 emit_int8((unsigned char)0xF3);
6346 prefix(src, dst);
6347 emit_int16(0x0F, (unsigned char)0xBC);
6348 emit_operand(dst, src, 0);
6349 }
6350
6351 void Assembler::tzcntq(Register dst, Register src) {
6352 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6353 emit_int8((unsigned char)0xF3);
6354 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6355 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
6356 }
6357
6358 void Assembler::tzcntq(Register dst, Address src) {
6359 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6360 InstructionMark im(this);
6361 emit_int8((unsigned char)0xF3);
6362 prefixq(src, dst);
6363 emit_int16(0x0F, (unsigned char)0xBC);
6364 emit_operand(dst, src, 0);
6365 }
6366
6367 void Assembler::ucomisd(XMMRegister dst, Address src) {
6368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6369 InstructionMark im(this);
6370 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6371 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6372 attributes.set_rex_vex_w_reverted();
6373 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6374 emit_int8(0x2E);
6375 emit_operand(dst, src, 0);
6376 }
6377
6378 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
6379 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6380 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6381 attributes.set_rex_vex_w_reverted();
6382 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6383 emit_int16(0x2E, (0xC0 | encode));
6384 }
6385
6386 void Assembler::ucomiss(XMMRegister dst, Address src) {
6387 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6388 InstructionMark im(this);
6389 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6390 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6391 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6392 emit_int8(0x2E);
6393 emit_operand(dst, src, 0);
6394 }
6395
6396 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
6397 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6398 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6399 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6400 emit_int16(0x2E, (0xC0 | encode));
6401 }
6402
6403 void Assembler::xabort(int8_t imm8) {
6404 emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF));
6405 }
6406
6407 void Assembler::xaddb(Address dst, Register src) {
6408 InstructionMark im(this);
6409 prefix(dst, src, true);
6410 emit_int16(0x0F, (unsigned char)0xC0);
6411 emit_operand(src, dst, 0);
6412 }
6413
6414 void Assembler::xaddw(Address dst, Register src) {
6415 InstructionMark im(this);
6416 emit_int8(0x66);
6417 prefix(dst, src);
6418 emit_int16(0x0F, (unsigned char)0xC1);
6419 emit_operand(src, dst, 0);
6420 }
6421
6422 void Assembler::xaddl(Address dst, Register src) {
6423 InstructionMark im(this);
6424 prefix(dst, src);
6425 emit_int16(0x0F, (unsigned char)0xC1);
6426 emit_operand(src, dst, 0);
6427 }
6428
6429 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
6430 InstructionMark im(this);
6431 relocate(rtype);
6432 if (abort.is_bound()) {
6433 address entry = target(abort);
6434 assert(entry != nullptr, "abort entry null");
6435 int offset = checked_cast<int>(entry - pc());
6436 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6437 emit_int32(offset - 6); // 2 opcode + 4 address
6438 } else {
6439 abort.add_patch_at(code(), locator());
6440 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6441 emit_int32(0);
6442 }
6443 }
6444
6445 void Assembler::xchgb(Register dst, Address src) { // xchg
6446 InstructionMark im(this);
6447 prefix(src, dst, true);
6448 emit_int8((unsigned char)0x86);
6449 emit_operand(dst, src, 0);
6450 }
6451
6452 void Assembler::xchgw(Register dst, Address src) { // xchg
6453 InstructionMark im(this);
6454 emit_int8(0x66);
6455 prefix(src, dst);
6456 emit_int8((unsigned char)0x87);
6457 emit_operand(dst, src, 0);
6458 }
6459
6460 void Assembler::xchgl(Register dst, Address src) { // xchg
6461 InstructionMark im(this);
6462 prefix(src, dst);
6463 emit_int8((unsigned char)0x87);
6464 emit_operand(dst, src, 0);
6465 }
6466
6467 void Assembler::xchgl(Register dst, Register src) {
6468 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6469 emit_int16((unsigned char)0x87, (0xC0 | encode));
6470 }
6471
6472 void Assembler::xend() {
6473 emit_int24(0x0F, 0x01, (unsigned char)0xD5);
6474 }
6475
6476 void Assembler::xgetbv() {
6477 emit_int24(0x0F, 0x01, (unsigned char)0xD0);
6478 }
6479
6480 void Assembler::xorl(Address dst, int32_t imm32) {
6481 InstructionMark im(this);
6482 prefix(dst);
6483 emit_arith_operand(0x81, as_Register(6), dst, imm32);
6484 }
6485
6486 void Assembler::xorl(Register dst, int32_t imm32) {
6487 prefix(dst);
6488 emit_arith(0x81, 0xF0, dst, imm32);
6489 }
6490
6491 void Assembler::xorl(Register dst, Address src) {
6492 InstructionMark im(this);
6493 prefix(src, dst);
6494 emit_int8(0x33);
6495 emit_operand(dst, src, 0);
6496 }
6497
6498 void Assembler::xorl(Register dst, Register src) {
6499 (void) prefix_and_encode(dst->encoding(), src->encoding());
6500 emit_arith(0x33, 0xC0, dst, src);
6501 }
6502
6503 void Assembler::xorl(Address dst, Register src) {
6504 InstructionMark im(this);
6505 prefix(dst, src);
6506 emit_int8(0x31);
6507 emit_operand(src, dst, 0);
6508 }
6509
6510 void Assembler::xorb(Register dst, Address src) {
6511 InstructionMark im(this);
6512 prefix(src, dst);
6513 emit_int8(0x32);
6514 emit_operand(dst, src, 0);
6515 }
6516
6517 void Assembler::xorb(Address dst, Register src) {
6518 InstructionMark im(this);
6519 prefix(dst, src, true);
6520 emit_int8(0x30);
6521 emit_operand(src, dst, 0);
6522 }
6523
6524 void Assembler::xorw(Register dst, Register src) {
6525 (void)prefix_and_encode(dst->encoding(), src->encoding());
6526 emit_arith(0x33, 0xC0, dst, src);
6527 }
6528
6529 // AVX 3-operands scalar float-point arithmetic instructions
6530
6531 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
6532 assert(VM_Version::supports_avx(), "");
6533 InstructionMark im(this);
6534 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6535 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6536 attributes.set_rex_vex_w_reverted();
6537 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6538 emit_int8(0x58);
6539 emit_operand(dst, src, 0);
6540 }
6541
6542 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6543 assert(VM_Version::supports_avx(), "");
6544 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6545 attributes.set_rex_vex_w_reverted();
6546 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6547 emit_int16(0x58, (0xC0 | encode));
6548 }
6549
6550 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
6551 assert(VM_Version::supports_avx(), "");
6552 InstructionMark im(this);
6553 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6554 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6555 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6556 emit_int8(0x58);
6557 emit_operand(dst, src, 0);
6558 }
6559
6560 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6561 assert(VM_Version::supports_avx(), "");
6562 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6563 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6564 emit_int16(0x58, (0xC0 | encode));
6565 }
6566
6567 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
6568 assert(VM_Version::supports_avx(), "");
6569 InstructionMark im(this);
6570 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6571 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6572 attributes.set_rex_vex_w_reverted();
6573 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6574 emit_int8(0x5E);
6575 emit_operand(dst, src, 0);
6576 }
6577
6578 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6579 assert(VM_Version::supports_avx(), "");
6580 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6581 attributes.set_rex_vex_w_reverted();
6582 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6583 emit_int16(0x5E, (0xC0 | encode));
6584 }
6585
6586 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
6587 assert(VM_Version::supports_avx(), "");
6588 InstructionMark im(this);
6589 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6590 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6591 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6592 emit_int8(0x5E);
6593 emit_operand(dst, src, 0);
6594 }
6595
6596 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6597 assert(VM_Version::supports_avx(), "");
6598 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6599 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6600 emit_int16(0x5E, (0xC0 | encode));
6601 }
6602
6603 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6604 assert(VM_Version::supports_fma(), "");
6605 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6606 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6607 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6608 }
6609
6610 void Assembler::evfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2, EvexRoundPrefix rmode) { // Need to add rmode for rounding mode support
6611 assert(VM_Version::supports_evex(), "");
6612 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6613 attributes.set_extended_context();
6614 attributes.set_is_evex_instruction();
6615 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6616 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6617 }
6618
6619 void Assembler::vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6620 assert(VM_Version::supports_fma(), "");
6621 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6622 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6623 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6624 }
6625
6626 void Assembler::vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6627 assert(VM_Version::supports_fma(), "");
6628 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6629 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6630 emit_int16((unsigned char)0xBD, (0xC0 | encode));
6631 }
6632
6633 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6634 assert(VM_Version::supports_fma(), "");
6635 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6636 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6637 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6638 }
6639
6640 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
6641 assert(VM_Version::supports_avx(), "");
6642 InstructionMark im(this);
6643 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6644 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6645 attributes.set_rex_vex_w_reverted();
6646 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6647 emit_int8(0x59);
6648 emit_operand(dst, src, 0);
6649 }
6650
6651 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6652 assert(VM_Version::supports_avx(), "");
6653 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6654 attributes.set_rex_vex_w_reverted();
6655 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6656 emit_int16(0x59, (0xC0 | encode));
6657 }
6658
6659 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
6660 assert(VM_Version::supports_avx(), "");
6661 InstructionMark im(this);
6662 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6663 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6664 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6665 emit_int8(0x59);
6666 emit_operand(dst, src, 0);
6667 }
6668
6669 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6670 assert(VM_Version::supports_avx(), "");
6671 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6673 emit_int16(0x59, (0xC0 | encode));
6674 }
6675
6676 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
6677 assert(VM_Version::supports_avx(), "");
6678 InstructionMark im(this);
6679 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6680 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6681 attributes.set_rex_vex_w_reverted();
6682 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6683 emit_int8(0x5C);
6684 emit_operand(dst, src, 0);
6685 }
6686
6687 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6688 assert(VM_Version::supports_avx(), "");
6689 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6690 attributes.set_rex_vex_w_reverted();
6691 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6692 emit_int16(0x5C, (0xC0 | encode));
6693 }
6694
6695 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
6696 assert(VM_Version::supports_avx(), "");
6697 InstructionMark im(this);
6698 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6699 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6700 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6701 emit_int8(0x5C);
6702 emit_operand(dst, src, 0);
6703 }
6704
6705 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6706 assert(VM_Version::supports_avx(), "");
6707 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6708 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6709 emit_int16(0x5C, (0xC0 | encode));
6710 }
6711
6712 //====================VECTOR ARITHMETIC=====================================
6713
6714 // Float-point vector arithmetic
6715
6716 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
6717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6718 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6719 attributes.set_rex_vex_w_reverted();
6720 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6721 emit_int16(0x58, (0xC0 | encode));
6722 }
6723
6724 void Assembler::addpd(XMMRegister dst, Address src) {
6725 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6726 InstructionMark im(this);
6727 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6728 attributes.set_rex_vex_w_reverted();
6729 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6730 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6731 emit_int8(0x58);
6732 emit_operand(dst, src, 0);
6733 }
6734
6735
6736 void Assembler::addps(XMMRegister dst, XMMRegister src) {
6737 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6738 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6739 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6740 emit_int16(0x58, (0xC0 | encode));
6741 }
6742
6743 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6744 assert(VM_Version::supports_avx(), "");
6745 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6746 attributes.set_rex_vex_w_reverted();
6747 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6748 emit_int16(0x58, (0xC0 | encode));
6749 }
6750
6751 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6752 assert(VM_Version::supports_avx(), "");
6753 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6754 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6755 emit_int16(0x58, (0xC0 | encode));
6756 }
6757
6758 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6759 assert(VM_Version::supports_avx(), "");
6760 InstructionMark im(this);
6761 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6762 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6763 attributes.set_rex_vex_w_reverted();
6764 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6765 emit_int8(0x58);
6766 emit_operand(dst, src, 0);
6767 }
6768
6769 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6770 assert(VM_Version::supports_avx(), "");
6771 InstructionMark im(this);
6772 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6773 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6774 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6775 emit_int8(0x58);
6776 emit_operand(dst, src, 0);
6777 }
6778
6779 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
6780 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6781 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6782 attributes.set_rex_vex_w_reverted();
6783 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6784 emit_int16(0x5C, (0xC0 | encode));
6785 }
6786
6787 void Assembler::subps(XMMRegister dst, XMMRegister src) {
6788 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6789 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6790 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6791 emit_int16(0x5C, (0xC0 | encode));
6792 }
6793
6794 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6795 assert(VM_Version::supports_avx(), "");
6796 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6797 attributes.set_rex_vex_w_reverted();
6798 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6799 emit_int16(0x5C, (0xC0 | encode));
6800 }
6801
6802 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6803 assert(VM_Version::supports_avx(), "");
6804 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6805 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6806 emit_int16(0x5C, (0xC0 | encode));
6807 }
6808
6809 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6810 assert(VM_Version::supports_avx(), "");
6811 InstructionMark im(this);
6812 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6813 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6814 attributes.set_rex_vex_w_reverted();
6815 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6816 emit_int8(0x5C);
6817 emit_operand(dst, src, 0);
6818 }
6819
6820 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6821 assert(VM_Version::supports_avx(), "");
6822 InstructionMark im(this);
6823 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6824 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6825 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6826 emit_int8(0x5C);
6827 emit_operand(dst, src, 0);
6828 }
6829
6830 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
6831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6832 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6833 attributes.set_rex_vex_w_reverted();
6834 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6835 emit_int16(0x59, (0xC0 | encode));
6836 }
6837
6838 void Assembler::mulpd(XMMRegister dst, Address src) {
6839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6840 InstructionMark im(this);
6841 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6842 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6843 attributes.set_rex_vex_w_reverted();
6844 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6845 emit_int8(0x59);
6846 emit_operand(dst, src, 0);
6847 }
6848
6849 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
6850 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6851 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6852 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6853 emit_int16(0x59, (0xC0 | encode));
6854 }
6855
6856 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6857 assert(VM_Version::supports_avx(), "");
6858 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6859 attributes.set_rex_vex_w_reverted();
6860 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6861 emit_int16(0x59, (0xC0 | encode));
6862 }
6863
6864 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6865 assert(VM_Version::supports_avx(), "");
6866 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6867 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6868 emit_int16(0x59, (0xC0 | encode));
6869 }
6870
6871 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6872 assert(VM_Version::supports_avx(), "");
6873 InstructionMark im(this);
6874 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6875 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6876 attributes.set_rex_vex_w_reverted();
6877 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6878 emit_int8(0x59);
6879 emit_operand(dst, src, 0);
6880 }
6881
6882 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6883 assert(VM_Version::supports_avx(), "");
6884 InstructionMark im(this);
6885 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6886 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6887 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6888 emit_int8(0x59);
6889 emit_operand(dst, src, 0);
6890 }
6891
6892 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6893 assert(VM_Version::supports_fma(), "");
6894 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6895 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6896 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6897 }
6898
6899 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6900 assert(VM_Version::supports_fma(), "");
6901 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6902 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6903 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6904 }
6905
6906 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6907 assert(VM_Version::supports_fma(), "");
6908 InstructionMark im(this);
6909 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6910 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6911 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6912 emit_int8((unsigned char)0xB8);
6913 emit_operand(dst, src2, 0);
6914 }
6915
6916 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6917 assert(VM_Version::supports_fma(), "");
6918 InstructionMark im(this);
6919 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6920 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6921 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6922 emit_int8((unsigned char)0xB8);
6923 emit_operand(dst, src2, 0);
6924 }
6925
6926 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
6927 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6928 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6929 attributes.set_rex_vex_w_reverted();
6930 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6931 emit_int16(0x5E, (0xC0 | encode));
6932 }
6933
6934 void Assembler::divps(XMMRegister dst, XMMRegister src) {
6935 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6936 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6937 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6938 emit_int16(0x5E, (0xC0 | encode));
6939 }
6940
6941 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6942 assert(VM_Version::supports_avx(), "");
6943 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6944 attributes.set_rex_vex_w_reverted();
6945 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6946 emit_int16(0x5E, (0xC0 | encode));
6947 }
6948
6949 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6950 assert(VM_Version::supports_avx(), "");
6951 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6952 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6953 emit_int16(0x5E, (0xC0 | encode));
6954 }
6955
6956 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6957 assert(VM_Version::supports_avx(), "");
6958 InstructionMark im(this);
6959 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6960 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6961 attributes.set_rex_vex_w_reverted();
6962 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6963 emit_int8(0x5E);
6964 emit_operand(dst, src, 0);
6965 }
6966
6967 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6968 assert(VM_Version::supports_avx(), "");
6969 InstructionMark im(this);
6970 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6971 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6972 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6973 emit_int8(0x5E);
6974 emit_operand(dst, src, 0);
6975 }
6976
6977 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
6978 assert(VM_Version::supports_avx(), "");
6979 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6980 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6981 emit_int24(0x09, (0xC0 | encode), (rmode));
6982 }
6983
6984 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
6985 assert(VM_Version::supports_avx(), "");
6986 InstructionMark im(this);
6987 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6988 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6989 emit_int8(0x09);
6990 emit_operand(dst, src, 1);
6991 emit_int8((rmode));
6992 }
6993
6994 void Assembler::vroundsd(XMMRegister dst, XMMRegister src, XMMRegister src2, int32_t rmode) {
6995 assert(VM_Version::supports_avx(), "");
6996 assert(rmode <= 0x0f, "rmode 0x%x", rmode);
6997 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6998 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6999 emit_int24(0x0B, (0xC0 | encode), (rmode));
7000 }
7001
7002 void Assembler::vrndscalesd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int32_t rmode) {
7003 assert(VM_Version::supports_evex(), "requires EVEX support");
7004 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7005 attributes.set_is_evex_instruction();
7006 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7007 emit_int24(0x0B, (0xC0 | encode), (rmode));
7008 }
7009
7010 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
7011 assert(VM_Version::supports_evex(), "requires EVEX support");
7012 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7013 attributes.set_is_evex_instruction();
7014 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7015 emit_int24(0x09, (0xC0 | encode), (rmode));
7016 }
7017
7018 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
7019 assert(VM_Version::supports_evex(), "requires EVEX support");
7020 assert(dst != xnoreg, "sanity");
7021 InstructionMark im(this);
7022 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7023 attributes.set_is_evex_instruction();
7024 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7025 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7026 emit_int8(0x09);
7027 emit_operand(dst, src, 1);
7028 emit_int8((rmode));
7029 }
7030
7031 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
7032 assert(VM_Version::supports_avx(), "");
7033 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7034 attributes.set_rex_vex_w_reverted();
7035 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7036 emit_int16(0x51, (0xC0 | encode));
7037 }
7038
7039 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
7040 assert(VM_Version::supports_avx(), "");
7041 InstructionMark im(this);
7042 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7043 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7044 attributes.set_rex_vex_w_reverted();
7045 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7046 emit_int8(0x51);
7047 emit_operand(dst, src, 0);
7048 }
7049
7050 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
7051 assert(VM_Version::supports_avx(), "");
7052 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7053 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7054 emit_int16(0x51, (0xC0 | encode));
7055 }
7056
7057 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
7058 assert(VM_Version::supports_avx(), "");
7059 InstructionMark im(this);
7060 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7061 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7062 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7063 emit_int8(0x51);
7064 emit_operand(dst, src, 0);
7065 }
7066
7067 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
7068 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7069 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7070 attributes.set_rex_vex_w_reverted();
7071 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7072 emit_int16(0x54, (0xC0 | encode));
7073 }
7074
7075 void Assembler::andps(XMMRegister dst, XMMRegister src) {
7076 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7078 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7079 emit_int16(0x54, (0xC0 | encode));
7080 }
7081
7082 void Assembler::andps(XMMRegister dst, Address src) {
7083 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7084 InstructionMark im(this);
7085 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7086 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7087 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7088 emit_int8(0x54);
7089 emit_operand(dst, src, 0);
7090 }
7091
7092 void Assembler::andpd(XMMRegister dst, Address src) {
7093 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7094 InstructionMark im(this);
7095 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7096 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7097 attributes.set_rex_vex_w_reverted();
7098 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7099 emit_int8(0x54);
7100 emit_operand(dst, src, 0);
7101 }
7102
7103 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7104 assert(VM_Version::supports_avx(), "");
7105 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7106 attributes.set_rex_vex_w_reverted();
7107 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7108 emit_int16(0x54, (0xC0 | encode));
7109 }
7110
7111 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7112 assert(VM_Version::supports_avx(), "");
7113 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7114 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7115 emit_int16(0x54, (0xC0 | encode));
7116 }
7117
7118 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7119 assert(VM_Version::supports_avx(), "");
7120 InstructionMark im(this);
7121 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7122 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7123 attributes.set_rex_vex_w_reverted();
7124 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7125 emit_int8(0x54);
7126 emit_operand(dst, src, 0);
7127 }
7128
7129 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7130 assert(VM_Version::supports_avx(), "");
7131 InstructionMark im(this);
7132 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7133 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7134 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7135 emit_int8(0x54);
7136 emit_operand(dst, src, 0);
7137 }
7138
7139 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
7140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7141 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7142 attributes.set_rex_vex_w_reverted();
7143 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7144 emit_int8(0x15);
7145 emit_int8((0xC0 | encode));
7146 }
7147
7148 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
7149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7150 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7151 attributes.set_rex_vex_w_reverted();
7152 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7153 emit_int16(0x14, (0xC0 | encode));
7154 }
7155
7156 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
7157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7158 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7159 attributes.set_rex_vex_w_reverted();
7160 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7161 emit_int16(0x57, (0xC0 | encode));
7162 }
7163
7164 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
7165 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7167 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7168 emit_int16(0x57, (0xC0 | encode));
7169 }
7170
7171 void Assembler::xorpd(XMMRegister dst, Address src) {
7172 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7173 InstructionMark im(this);
7174 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7175 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7176 attributes.set_rex_vex_w_reverted();
7177 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7178 emit_int8(0x57);
7179 emit_operand(dst, src, 0);
7180 }
7181
7182 void Assembler::xorps(XMMRegister dst, Address src) {
7183 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7184 InstructionMark im(this);
7185 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7186 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7187 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7188 emit_int8(0x57);
7189 emit_operand(dst, src, 0);
7190 }
7191
7192 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7193 assert(VM_Version::supports_avx(), "");
7194 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7195 attributes.set_rex_vex_w_reverted();
7196 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7197 emit_int16(0x57, (0xC0 | encode));
7198 }
7199
7200 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7201 assert(VM_Version::supports_avx(), "");
7202 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7203 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7204 emit_int16(0x57, (0xC0 | encode));
7205 }
7206
7207 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7208 assert(VM_Version::supports_avx(), "");
7209 InstructionMark im(this);
7210 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7211 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7212 attributes.set_rex_vex_w_reverted();
7213 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7214 emit_int8(0x57);
7215 emit_operand(dst, src, 0);
7216 }
7217
7218 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7219 assert(VM_Version::supports_avx(), "");
7220 InstructionMark im(this);
7221 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7222 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7223 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7224 emit_int8(0x57);
7225 emit_operand(dst, src, 0);
7226 }
7227
7228 // Integer vector arithmetic
7229 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7230 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7231 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7232 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7233 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7234 emit_int16(0x01, (0xC0 | encode));
7235 }
7236
7237 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7238 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7239 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7240 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7242 emit_int16(0x02, (0xC0 | encode));
7243 }
7244
7245 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
7246 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7248 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7249 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7250 }
7251
7252 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
7253 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7254 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7255 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7256 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7257 }
7258
7259 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
7260 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7261 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7262 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7263 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7264 }
7265
7266 void Assembler::paddd(XMMRegister dst, Address src) {
7267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7268 InstructionMark im(this);
7269 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7270 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7271 emit_int8((unsigned char)0xFE);
7272 emit_operand(dst, src, 0);
7273 }
7274
7275 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
7276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7277 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7278 attributes.set_rex_vex_w_reverted();
7279 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7280 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7281 }
7282
7283 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
7284 assert(VM_Version::supports_sse3(), "");
7285 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7286 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7287 emit_int16(0x01, (0xC0 | encode));
7288 }
7289
7290 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
7291 assert(VM_Version::supports_sse3(), "");
7292 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7293 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7294 emit_int16(0x02, (0xC0 | encode));
7295 }
7296
7297 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7298 assert(UseAVX > 0, "requires some form of AVX");
7299 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7300 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7301 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7302 }
7303
7304 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7305 assert(UseAVX > 0, "requires some form of AVX");
7306 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7307 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7308 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7309 }
7310
7311 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7312 assert(UseAVX > 0, "requires some form of AVX");
7313 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7314 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7315 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7316 }
7317
7318 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7319 assert(UseAVX > 0, "requires some form of AVX");
7320 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7321 attributes.set_rex_vex_w_reverted();
7322 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7323 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7324 }
7325
7326 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7327 assert(UseAVX > 0, "requires some form of AVX");
7328 InstructionMark im(this);
7329 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7330 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7331 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7332 emit_int8((unsigned char)0xFC);
7333 emit_operand(dst, src, 0);
7334 }
7335
7336 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7337 assert(UseAVX > 0, "requires some form of AVX");
7338 InstructionMark im(this);
7339 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7340 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7342 emit_int8((unsigned char)0xFD);
7343 emit_operand(dst, src, 0);
7344 }
7345
7346 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7347 assert(UseAVX > 0, "requires some form of AVX");
7348 InstructionMark im(this);
7349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7350 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7351 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7352 emit_int8((unsigned char)0xFE);
7353 emit_operand(dst, src, 0);
7354 }
7355
7356 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7357 assert(UseAVX > 0, "requires some form of AVX");
7358 InstructionMark im(this);
7359 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7360 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7361 attributes.set_rex_vex_w_reverted();
7362 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7363 emit_int8((unsigned char)0xD4);
7364 emit_operand(dst, src, 0);
7365 }
7366
7367 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
7368 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7369 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7370 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7371 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7372 }
7373
7374 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
7375 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7376 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7377 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7378 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7379 }
7380
7381 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
7382 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7383 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7384 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7385 }
7386
7387 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
7388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7389 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7390 attributes.set_rex_vex_w_reverted();
7391 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7392 emit_int8((unsigned char)0xFB);
7393 emit_int8((0xC0 | encode));
7394 }
7395
7396 void Assembler::vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7397 assert(UseAVX > 0, "requires some form of AVX");
7398 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7399 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7400 emit_int16((unsigned char)0xD8, (0xC0 | encode));
7401 }
7402
7403 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7404 assert(UseAVX > 0, "requires some form of AVX");
7405 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7406 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7407 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7408 }
7409
7410 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7411 assert(UseAVX > 0, "requires some form of AVX");
7412 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7413 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7414 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7415 }
7416
7417 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7418 assert(UseAVX > 0, "requires some form of AVX");
7419 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7420 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7421 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7422 }
7423
7424 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7425 assert(UseAVX > 0, "requires some form of AVX");
7426 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7427 attributes.set_rex_vex_w_reverted();
7428 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7429 emit_int16((unsigned char)0xFB, (0xC0 | encode));
7430 }
7431
7432 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7433 assert(UseAVX > 0, "requires some form of AVX");
7434 InstructionMark im(this);
7435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7436 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7437 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7438 emit_int8((unsigned char)0xF8);
7439 emit_operand(dst, src, 0);
7440 }
7441
7442 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7443 assert(UseAVX > 0, "requires some form of AVX");
7444 InstructionMark im(this);
7445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7446 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7447 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7448 emit_int8((unsigned char)0xF9);
7449 emit_operand(dst, src, 0);
7450 }
7451
7452 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7453 assert(UseAVX > 0, "requires some form of AVX");
7454 InstructionMark im(this);
7455 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7456 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7457 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7458 emit_int8((unsigned char)0xFA);
7459 emit_operand(dst, src, 0);
7460 }
7461
7462 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7463 assert(UseAVX > 0, "requires some form of AVX");
7464 InstructionMark im(this);
7465 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7466 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7467 attributes.set_rex_vex_w_reverted();
7468 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7469 emit_int8((unsigned char)0xFB);
7470 emit_operand(dst, src, 0);
7471 }
7472
7473 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
7474 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7475 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7476 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7477 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7478 }
7479
7480 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
7481 assert(VM_Version::supports_sse4_1(), "");
7482 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7483 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7484 emit_int16(0x40, (0xC0 | encode));
7485 }
7486
7487 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
7488 assert(VM_Version::supports_sse2(), "");
7489 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7490 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7491 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7492 }
7493
7494 void Assembler::vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7495 assert((vector_len == AVX_128bit && VM_Version::supports_avx()) ||
7496 (vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
7497 (vector_len == AVX_512bit && VM_Version::supports_avx512bw()), "");
7498 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7499 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7500 emit_int16((unsigned char)0xE4, (0xC0 | encode));
7501 }
7502
7503 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7504 assert(UseAVX > 0, "requires some form of AVX");
7505 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7506 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7507 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7508 }
7509
7510 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7511 assert(UseAVX > 0, "requires some form of AVX");
7512 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7513 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7514 emit_int16(0x40, (0xC0 | encode));
7515 }
7516
7517 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7518 assert(UseAVX > 2, "requires some form of EVEX");
7519 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7520 attributes.set_is_evex_instruction();
7521 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7522 emit_int16(0x40, (0xC0 | encode));
7523 }
7524
7525 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7526 assert(UseAVX > 0, "requires some form of AVX");
7527 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7528 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7529 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7530 }
7531
7532 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7533 assert(UseAVX > 0, "requires some form of AVX");
7534 InstructionMark im(this);
7535 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7536 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7537 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7538 emit_int8((unsigned char)0xD5);
7539 emit_operand(dst, src, 0);
7540 }
7541
7542 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7543 assert(UseAVX > 0, "requires some form of AVX");
7544 InstructionMark im(this);
7545 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7546 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7547 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7548 emit_int8(0x40);
7549 emit_operand(dst, src, 0);
7550 }
7551
7552 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7553 assert(UseAVX > 2, "requires some form of EVEX");
7554 InstructionMark im(this);
7555 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7556 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7557 attributes.set_is_evex_instruction();
7558 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7559 emit_int8(0x40);
7560 emit_operand(dst, src, 0);
7561 }
7562
7563 // Min, max
7564 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
7565 assert(VM_Version::supports_sse4_1(), "");
7566 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7567 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7568 emit_int16(0x38, (0xC0 | encode));
7569 }
7570
7571 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7572 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7573 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7574 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7575 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7576 emit_int16(0x38, (0xC0 | encode));
7577 }
7578
7579 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
7580 assert(VM_Version::supports_sse2(), "");
7581 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7582 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7583 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7584 }
7585
7586 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7587 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7588 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7589 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7590 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7591 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7592 }
7593
7594 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
7595 assert(VM_Version::supports_sse4_1(), "");
7596 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7597 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7598 emit_int16(0x39, (0xC0 | encode));
7599 }
7600
7601 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7602 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7603 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7604 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7605 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7606 emit_int16(0x39, (0xC0 | encode));
7607 }
7608
7609 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7610 assert(UseAVX > 2, "requires AVX512F");
7611 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7612 attributes.set_is_evex_instruction();
7613 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7614 emit_int16(0x39, (0xC0 | encode));
7615 }
7616
7617 void Assembler::minps(XMMRegister dst, XMMRegister src) {
7618 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7619 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7620 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7621 emit_int16(0x5D, (0xC0 | encode));
7622 }
7623 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7624 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7625 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7626 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7627 emit_int16(0x5D, (0xC0 | encode));
7628 }
7629
7630 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
7631 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7632 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7633 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7634 emit_int16(0x5D, (0xC0 | encode));
7635 }
7636 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7637 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7638 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7639 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7640 emit_int16(0x5D, (0xC0 | encode));
7641 }
7642
7643 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
7644 assert(VM_Version::supports_sse4_1(), "");
7645 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7646 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7647 emit_int16(0x3C, (0xC0 | encode));
7648 }
7649
7650 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7651 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7652 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7653 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7654 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7655 emit_int16(0x3C, (0xC0 | encode));
7656 }
7657
7658 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
7659 assert(VM_Version::supports_sse2(), "");
7660 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7661 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7662 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7663 }
7664
7665 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7666 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7667 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7668 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7669 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7670 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7671 }
7672
7673 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
7674 assert(VM_Version::supports_sse4_1(), "");
7675 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7676 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7677 emit_int16(0x3D, (0xC0 | encode));
7678 }
7679
7680 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7681 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7682 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7684 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7685 emit_int16(0x3D, (0xC0 | encode));
7686 }
7687
7688 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7689 assert(UseAVX > 2, "requires AVX512F");
7690 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7691 attributes.set_is_evex_instruction();
7692 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7693 emit_int16(0x3D, (0xC0 | encode));
7694 }
7695
7696 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
7697 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7698 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7699 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7700 emit_int16(0x5F, (0xC0 | encode));
7701 }
7702
7703 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7704 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7705 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7706 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7707 emit_int16(0x5F, (0xC0 | encode));
7708 }
7709
7710 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
7711 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7712 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7713 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7714 emit_int16(0x5F, (0xC0 | encode));
7715 }
7716
7717 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7718 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7719 InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7720 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7721 emit_int16(0x5F, (0xC0 | encode));
7722 }
7723
7724 // Shift packed integers left by specified number of bits.
7725 void Assembler::psllw(XMMRegister dst, int shift) {
7726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7728 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7729 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7730 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7731 }
7732
7733 void Assembler::pslld(XMMRegister dst, int shift) {
7734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7735 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7736 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7737 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7738 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7739 }
7740
7741 void Assembler::psllq(XMMRegister dst, int shift) {
7742 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7743 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7744 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7745 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7746 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7747 }
7748
7749 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
7750 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7752 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7753 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7754 }
7755
7756 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
7757 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7759 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7760 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7761 }
7762
7763 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
7764 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7765 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7766 attributes.set_rex_vex_w_reverted();
7767 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7768 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7769 }
7770
7771 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7772 assert(UseAVX > 0, "requires some form of AVX");
7773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7774 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7775 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7776 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7777 }
7778
7779 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7780 assert(UseAVX > 0, "requires some form of AVX");
7781 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7782 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7783 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7784 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7785 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7786 }
7787
7788 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7789 assert(UseAVX > 0, "requires some form of AVX");
7790 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7791 attributes.set_rex_vex_w_reverted();
7792 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7793 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7794 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7795 }
7796
7797 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7798 assert(UseAVX > 0, "requires some form of AVX");
7799 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7800 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7801 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7802 }
7803
7804 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7805 assert(UseAVX > 0, "requires some form of AVX");
7806 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7807 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7808 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7809 }
7810
7811 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7812 assert(UseAVX > 0, "requires some form of AVX");
7813 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7814 attributes.set_rex_vex_w_reverted();
7815 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7816 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7817 }
7818
7819 // Shift packed integers logically right by specified number of bits.
7820 void Assembler::psrlw(XMMRegister dst, int shift) {
7821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7823 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7824 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7825 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7826 }
7827
7828 void Assembler::psrld(XMMRegister dst, int shift) {
7829 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7830 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7831 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7832 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7833 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7834 }
7835
7836 void Assembler::psrlq(XMMRegister dst, int shift) {
7837 // Do not confuse it with psrldq SSE2 instruction which
7838 // shifts 128 bit value in xmm register by number of bytes.
7839 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7840 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7841 attributes.set_rex_vex_w_reverted();
7842 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7843 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7844 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7845 }
7846
7847 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
7848 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7849 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7850 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7851 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7852 }
7853
7854 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
7855 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7856 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7857 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7858 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7859 }
7860
7861 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
7862 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7863 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7864 attributes.set_rex_vex_w_reverted();
7865 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7866 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7867 }
7868
7869 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7870 assert(UseAVX > 0, "requires some form of AVX");
7871 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7872 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7873 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7874 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7875 }
7876
7877 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7878 assert(UseAVX > 0, "requires some form of AVX");
7879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7880 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7881 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7882 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7883 }
7884
7885 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7886 assert(UseAVX > 0, "requires some form of AVX");
7887 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7888 attributes.set_rex_vex_w_reverted();
7889 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7890 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7891 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7892 }
7893
7894 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7895 assert(UseAVX > 0, "requires some form of AVX");
7896 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7897 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7898 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7899 }
7900
7901 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7902 assert(UseAVX > 0, "requires some form of AVX");
7903 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7904 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7905 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7906 }
7907
7908 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7909 assert(UseAVX > 0, "requires some form of AVX");
7910 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7911 attributes.set_rex_vex_w_reverted();
7912 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7913 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7914 }
7915
7916 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7917 assert(VM_Version::supports_avx512bw(), "");
7918 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7919 attributes.set_is_evex_instruction();
7920 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7921 emit_int16(0x10, (0xC0 | encode));
7922 }
7923
7924 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7925 assert(VM_Version::supports_avx512bw(), "");
7926 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7927 attributes.set_is_evex_instruction();
7928 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7929 emit_int16(0x12, (0xC0 | encode));
7930 }
7931
7932 // Shift packed integers arithmetically right by specified number of bits.
7933 void Assembler::psraw(XMMRegister dst, int shift) {
7934 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7935 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7936 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7937 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7938 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7939 }
7940
7941 void Assembler::psrad(XMMRegister dst, int shift) {
7942 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7943 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7944 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
7945 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7946 emit_int8(0x72);
7947 emit_int8((0xC0 | encode));
7948 emit_int8(shift & 0xFF);
7949 }
7950
7951 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
7952 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7954 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7955 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7956 }
7957
7958 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
7959 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7961 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7962 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7963 }
7964
7965 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7966 assert(UseAVX > 0, "requires some form of AVX");
7967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7968 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7969 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7970 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7971 }
7972
7973 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7974 assert(UseAVX > 0, "requires some form of AVX");
7975 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7976 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7977 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7978 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7979 }
7980
7981 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7982 assert(UseAVX > 0, "requires some form of AVX");
7983 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7984 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7985 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7986 }
7987
7988 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7989 assert(UseAVX > 0, "requires some form of AVX");
7990 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7991 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7992 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7993 }
7994
7995 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7996 assert(UseAVX > 2, "requires AVX512");
7997 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
7998 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7999 attributes.set_is_evex_instruction();
8000 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8001 emit_int24((unsigned char)0x72, (0xC0 | encode), shift & 0xFF);
8002 }
8003
8004 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8005 assert(UseAVX > 2, "requires AVX512");
8006 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
8007 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8008 attributes.set_is_evex_instruction();
8009 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8010 emit_int16((unsigned char)0xE2, (0xC0 | encode));
8011 }
8012
8013 // logical operations packed integers
8014 void Assembler::pand(XMMRegister dst, XMMRegister src) {
8015 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8016 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8017 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8018 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8019 }
8020
8021 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8022 assert(UseAVX > 0, "requires some form of AVX");
8023 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8024 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8025 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8026 }
8027
8028 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8029 assert(UseAVX > 0, "requires some form of AVX");
8030 InstructionMark im(this);
8031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8032 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8033 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8034 emit_int8((unsigned char)0xDB);
8035 emit_operand(dst, src, 0);
8036 }
8037
8038 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8039 evpandq(dst, k0, nds, src, false, vector_len);
8040 }
8041
8042 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8043 evpandq(dst, k0, nds, src, false, vector_len);
8044 }
8045
8046 //Variable Shift packed integers logically left.
8047 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8048 assert(UseAVX > 1, "requires AVX2");
8049 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8050 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8051 emit_int16(0x47, (0xC0 | encode));
8052 }
8053
8054 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8055 assert(UseAVX > 1, "requires AVX2");
8056 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8057 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8058 emit_int16(0x47, (0xC0 | encode));
8059 }
8060
8061 //Variable Shift packed integers logically right.
8062 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8063 assert(UseAVX > 1, "requires AVX2");
8064 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8065 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8066 emit_int16(0x45, (0xC0 | encode));
8067 }
8068
8069 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8070 assert(UseAVX > 1, "requires AVX2");
8071 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8072 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8073 emit_int16(0x45, (0xC0 | encode));
8074 }
8075
8076 //Variable right Shift arithmetic packed integers .
8077 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8078 assert(UseAVX > 1, "requires AVX2");
8079 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8080 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8081 emit_int16(0x46, (0xC0 | encode));
8082 }
8083
8084 void Assembler::evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8085 assert(VM_Version::supports_avx512bw(), "");
8086 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8087 attributes.set_is_evex_instruction();
8088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8089 emit_int16(0x11, (0xC0 | encode));
8090 }
8091
8092 void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8093 assert(UseAVX > 2, "requires AVX512");
8094 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8095 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8096 attributes.set_is_evex_instruction();
8097 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8098 emit_int16(0x46, (0xC0 | encode));
8099 }
8100
8101 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8102 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8103 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8104 attributes.set_is_evex_instruction();
8105 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8106 emit_int16(0x71, (0xC0 | encode));
8107 }
8108
8109 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8110 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8111 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8112 attributes.set_is_evex_instruction();
8113 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8114 emit_int16(0x73, (0xC0 | encode));
8115 }
8116
8117 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
8118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8119 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8120 attributes.set_rex_vex_w_reverted();
8121 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8122 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8123 }
8124
8125 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8126 assert(UseAVX > 0, "requires some form of AVX");
8127 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8128 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8129 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8130 }
8131
8132 void Assembler::por(XMMRegister dst, XMMRegister src) {
8133 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8134 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8135 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8136 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8137 }
8138
8139 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8140 assert(UseAVX > 0, "requires some form of AVX");
8141 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8142 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8143 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8144 }
8145
8146 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8147 assert(UseAVX > 0, "requires some form of AVX");
8148 InstructionMark im(this);
8149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8150 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8151 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8152 emit_int8((unsigned char)0xEB);
8153 emit_operand(dst, src, 0);
8154 }
8155
8156 void Assembler::evporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8157 evporq(dst, k0, nds, src, false, vector_len);
8158 }
8159
8160 void Assembler::evporq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8161 evporq(dst, k0, nds, src, false, vector_len);
8162 }
8163
8164 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8165 assert(VM_Version::supports_evex(), "");
8166 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8167 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8168 attributes.set_is_evex_instruction();
8169 attributes.set_embedded_opmask_register_specifier(mask);
8170 if (merge) {
8171 attributes.reset_is_clear_context();
8172 }
8173 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8174 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8175 }
8176
8177 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8178 assert(VM_Version::supports_evex(), "");
8179 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8180 InstructionMark im(this);
8181 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8182 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8183 attributes.set_is_evex_instruction();
8184 attributes.set_embedded_opmask_register_specifier(mask);
8185 if (merge) {
8186 attributes.reset_is_clear_context();
8187 }
8188 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8189 emit_int8((unsigned char)0xEB);
8190 emit_operand(dst, src, 0);
8191 }
8192
8193 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
8194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8195 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8196 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8197 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8198 }
8199
8200 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8201 assert(UseAVX > 0, "requires some form of AVX");
8202 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8203 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8204 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8205 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8206 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8207 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8208 }
8209
8210 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8211 assert(UseAVX > 0, "requires some form of AVX");
8212 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8213 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8214 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8215 InstructionMark im(this);
8216 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8217 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8218 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8219 emit_int8((unsigned char)0xEF);
8220 emit_operand(dst, src, 0);
8221 }
8222
8223 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8224 assert(UseAVX > 2, "requires some form of EVEX");
8225 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8226 attributes.set_rex_vex_w_reverted();
8227 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8228 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8229 }
8230
8231 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8232 // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
8233 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8235 attributes.set_is_evex_instruction();
8236 attributes.set_embedded_opmask_register_specifier(mask);
8237 if (merge) {
8238 attributes.reset_is_clear_context();
8239 }
8240 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8241 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8242 }
8243
8244 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8245 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8246 InstructionMark im(this);
8247 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8248 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8249 attributes.set_is_evex_instruction();
8250 attributes.set_embedded_opmask_register_specifier(mask);
8251 if (merge) {
8252 attributes.reset_is_clear_context();
8253 }
8254 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8255 emit_int8((unsigned char)0xEF);
8256 emit_operand(dst, src, 0);
8257 }
8258
8259 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8260 // Encoding: EVEX.NDS.XXX.66.0F.W1 EF /r
8261 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8262 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8263 attributes.set_is_evex_instruction();
8264 attributes.set_embedded_opmask_register_specifier(mask);
8265 if (merge) {
8266 attributes.reset_is_clear_context();
8267 }
8268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8269 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8270 }
8271
8272 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8273 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8274 InstructionMark im(this);
8275 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8276 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8277 attributes.set_is_evex_instruction();
8278 attributes.set_embedded_opmask_register_specifier(mask);
8279 if (merge) {
8280 attributes.reset_is_clear_context();
8281 }
8282 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8283 emit_int8((unsigned char)0xEF);
8284 emit_operand(dst, src, 0);
8285 }
8286
8287 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8288 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8289 InstructionMark im(this);
8290 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8291 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8292 attributes.set_is_evex_instruction();
8293 attributes.set_embedded_opmask_register_specifier(mask);
8294 if (merge) {
8295 attributes.reset_is_clear_context();
8296 }
8297 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8298 emit_int8((unsigned char)0xDB);
8299 emit_operand(dst, src, 0);
8300 }
8301
8302 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8303 assert(VM_Version::supports_evex(), "requires AVX512F");
8304 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8305 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8306 attributes.set_is_evex_instruction();
8307 attributes.set_embedded_opmask_register_specifier(mask);
8308 if (merge) {
8309 attributes.reset_is_clear_context();
8310 }
8311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8312 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8313 }
8314
8315 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8316 assert(VM_Version::supports_evex(), "requires AVX512F");
8317 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8318 InstructionMark im(this);
8319 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8320 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8321 attributes.set_is_evex_instruction();
8322 attributes.set_embedded_opmask_register_specifier(mask);
8323 if (merge) {
8324 attributes.reset_is_clear_context();
8325 }
8326 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8327 emit_int8((unsigned char)0xDB);
8328 emit_operand(dst, src, 0);
8329 }
8330
8331 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8332 assert(VM_Version::supports_evex(), "requires AVX512F");
8333 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8334 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8335 attributes.set_is_evex_instruction();
8336 attributes.set_embedded_opmask_register_specifier(mask);
8337 if (merge) {
8338 attributes.reset_is_clear_context();
8339 }
8340 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8341 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8342 }
8343
8344 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8345 assert(VM_Version::supports_evex(), "requires AVX512F");
8346 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8347 InstructionMark im(this);
8348 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8349 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8350 attributes.set_is_evex_instruction();
8351 attributes.set_embedded_opmask_register_specifier(mask);
8352 if (merge) {
8353 attributes.reset_is_clear_context();
8354 }
8355 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8356 emit_int8((unsigned char)0xEB);
8357 emit_operand(dst, src, 0);
8358 }
8359
8360 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8361 assert(VM_Version::supports_evex(), "requires EVEX support");
8362 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8363 attributes.set_is_evex_instruction();
8364 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8365 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8366 }
8367
8368 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8369 assert(VM_Version::supports_evex(), "requires EVEX support");
8370 assert(dst != xnoreg, "sanity");
8371 InstructionMark im(this);
8372 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8373 attributes.set_is_evex_instruction();
8374 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8375 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8376 emit_int8((unsigned char)0xEF);
8377 emit_operand(dst, src, 0);
8378 }
8379
8380 void Assembler::evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8381 assert(VM_Version::supports_evex(), "requires EVEX support");
8382 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8383 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8384 attributes.set_is_evex_instruction();
8385 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8386 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8387 }
8388
8389 void Assembler::evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8390 assert(VM_Version::supports_evex(), "requires EVEX support");
8391 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8392 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8393 attributes.set_is_evex_instruction();
8394 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8395 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8396 }
8397
8398 void Assembler::evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8399 assert(VM_Version::supports_evex(), "requires EVEX support");
8400 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8401 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8402 attributes.set_is_evex_instruction();
8403 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8404 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8405 }
8406
8407 void Assembler::evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8408 assert(VM_Version::supports_evex(), "requires EVEX support");
8409 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8410 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8411 attributes.set_is_evex_instruction();
8412 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8413 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8414 }
8415
8416 void Assembler::evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8417 assert(VM_Version::supports_evex(), "requires EVEX support");
8418 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8419 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8420 attributes.set_is_evex_instruction();
8421 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8422 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8423 }
8424
8425 void Assembler::evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8426 assert(VM_Version::supports_evex(), "requires EVEX support");
8427 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8428 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8429 attributes.set_is_evex_instruction();
8430 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8431 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8432 }
8433
8434 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8435 assert(VM_Version::supports_evex(), "requires EVEX support");
8436 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8437 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8438 attributes.set_is_evex_instruction();
8439 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8440 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8441 }
8442
8443 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8444 assert(VM_Version::supports_evex(), "requires EVEX support");
8445 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8446 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8447 attributes.set_is_evex_instruction();
8448 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8449 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8450 }
8451
8452 void Assembler::evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8453 assert(VM_Version::supports_avx512cd(), "");
8454 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8455 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8456 attributes.set_is_evex_instruction();
8457 attributes.set_embedded_opmask_register_specifier(mask);
8458 if (merge) {
8459 attributes.reset_is_clear_context();
8460 }
8461 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8462 emit_int16(0x44, (0xC0 | encode));
8463 }
8464
8465 void Assembler::evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8466 assert(VM_Version::supports_avx512cd(), "");
8467 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8468 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8469 attributes.set_is_evex_instruction();
8470 attributes.set_embedded_opmask_register_specifier(mask);
8471 if (merge) {
8472 attributes.reset_is_clear_context();
8473 }
8474 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8475 emit_int16(0x44, (0xC0 | encode));
8476 }
8477
8478 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8479 assert(VM_Version::supports_evex(), "requires EVEX support");
8480 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8482 attributes.set_is_evex_instruction();
8483 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8484 emit_int8(0x25);
8485 emit_int8((unsigned char)(0xC0 | encode));
8486 emit_int8(imm8);
8487 }
8488
8489 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8490 assert(VM_Version::supports_evex(), "requires EVEX support");
8491 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8492 assert(dst != xnoreg, "sanity");
8493 InstructionMark im(this);
8494 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8495 attributes.set_is_evex_instruction();
8496 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8497 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8498 emit_int8(0x25);
8499 emit_operand(dst, src3, 1);
8500 emit_int8(imm8);
8501 }
8502
8503 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8504 assert(VM_Version::supports_evex(), "requires AVX512F");
8505 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8506 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8507 attributes.set_is_evex_instruction();
8508 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8509 emit_int8(0x25);
8510 emit_int8((unsigned char)(0xC0 | encode));
8511 emit_int8(imm8);
8512 }
8513
8514 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8515 assert(VM_Version::supports_evex(), "requires EVEX support");
8516 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8517 assert(dst != xnoreg, "sanity");
8518 InstructionMark im(this);
8519 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8520 attributes.set_is_evex_instruction();
8521 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8522 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8523 emit_int8(0x25);
8524 emit_operand(dst, src3, 1);
8525 emit_int8(imm8);
8526 }
8527
8528 void Assembler::evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8529 assert(VM_Version::supports_evex(), "");
8530 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8532 attributes.set_is_evex_instruction();
8533 attributes.set_embedded_opmask_register_specifier(mask);
8534 if (merge) {
8535 attributes.reset_is_clear_context();
8536 }
8537 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8538 emit_int16((unsigned char)0x88, (0xC0 | encode));
8539 }
8540
8541 void Assembler::evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8542 assert(VM_Version::supports_evex(), "");
8543 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8544 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8545 attributes.set_is_evex_instruction();
8546 attributes.set_embedded_opmask_register_specifier(mask);
8547 if (merge) {
8548 attributes.reset_is_clear_context();
8549 }
8550 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8551 emit_int16((unsigned char)0x88, (0xC0 | encode));
8552 }
8553
8554 void Assembler::evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8555 assert(VM_Version::supports_avx512_vbmi2(), "");
8556 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8558 attributes.set_is_evex_instruction();
8559 attributes.set_embedded_opmask_register_specifier(mask);
8560 if (merge) {
8561 attributes.reset_is_clear_context();
8562 }
8563 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8564 emit_int16(0x62, (0xC0 | encode));
8565 }
8566
8567 void Assembler::evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8568 assert(VM_Version::supports_avx512_vbmi2(), "");
8569 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8570 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8571 attributes.set_is_evex_instruction();
8572 attributes.set_embedded_opmask_register_specifier(mask);
8573 if (merge) {
8574 attributes.reset_is_clear_context();
8575 }
8576 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8577 emit_int16(0x62, (0xC0 | encode));
8578 }
8579
8580 void Assembler::evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8581 assert(VM_Version::supports_evex(), "");
8582 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8583 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8584 attributes.set_is_evex_instruction();
8585 attributes.set_embedded_opmask_register_specifier(mask);
8586 if (merge) {
8587 attributes.reset_is_clear_context();
8588 }
8589 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8590 emit_int16((unsigned char)0x89, (0xC0 | encode));
8591 }
8592
8593 void Assembler::evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8594 assert(VM_Version::supports_evex(), "");
8595 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8596 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8597 attributes.set_is_evex_instruction();
8598 attributes.set_embedded_opmask_register_specifier(mask);
8599 if (merge) {
8600 attributes.reset_is_clear_context();
8601 }
8602 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8603 emit_int16((unsigned char)0x89, (0xC0 | encode));
8604 }
8605
8606 // vinserti forms
8607
8608 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8609 assert(VM_Version::supports_avx2(), "");
8610 assert(imm8 <= 0x01, "imm8: %u", imm8);
8611 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8612 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8613 // last byte:
8614 // 0x00 - insert into lower 128 bits
8615 // 0x01 - insert into upper 128 bits
8616 emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
8617 }
8618
8619 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8620 assert(VM_Version::supports_avx2(), "");
8621 assert(dst != xnoreg, "sanity");
8622 assert(imm8 <= 0x01, "imm8: %u", imm8);
8623 InstructionMark im(this);
8624 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8625 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8626 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8627 emit_int8(0x38);
8628 emit_operand(dst, src, 1);
8629 // 0x00 - insert into lower 128 bits
8630 // 0x01 - insert into upper 128 bits
8631 emit_int8(imm8 & 0x01);
8632 }
8633
8634 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8635 assert(VM_Version::supports_evex(), "");
8636 assert(imm8 <= 0x03, "imm8: %u", imm8);
8637 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8638 attributes.set_is_evex_instruction();
8639 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8640 // imm8:
8641 // 0x00 - insert into q0 128 bits (0..127)
8642 // 0x01 - insert into q1 128 bits (128..255)
8643 // 0x02 - insert into q2 128 bits (256..383)
8644 // 0x03 - insert into q3 128 bits (384..511)
8645 emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
8646 }
8647
8648 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8649 assert(VM_Version::supports_evex(), "");
8650 assert(dst != xnoreg, "sanity");
8651 assert(imm8 <= 0x03, "imm8: %u", imm8);
8652 InstructionMark im(this);
8653 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8654 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8655 attributes.set_is_evex_instruction();
8656 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8657 emit_int8(0x18);
8658 emit_operand(dst, src, 1);
8659 // 0x00 - insert into q0 128 bits (0..127)
8660 // 0x01 - insert into q1 128 bits (128..255)
8661 // 0x02 - insert into q2 128 bits (256..383)
8662 // 0x03 - insert into q3 128 bits (384..511)
8663 emit_int8(imm8 & 0x03);
8664 }
8665
8666 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8667 assert(VM_Version::supports_evex(), "");
8668 assert(imm8 <= 0x01, "imm8: %u", imm8);
8669 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8670 attributes.set_is_evex_instruction();
8671 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8672 //imm8:
8673 // 0x00 - insert into lower 256 bits
8674 // 0x01 - insert into upper 256 bits
8675 emit_int24(0x3A, (0xC0 | encode), imm8 & 0x01);
8676 }
8677
8678
8679 // vinsertf forms
8680
8681 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8682 assert(VM_Version::supports_avx(), "");
8683 assert(imm8 <= 0x01, "imm8: %u", imm8);
8684 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8685 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8686 // imm8:
8687 // 0x00 - insert into lower 128 bits
8688 // 0x01 - insert into upper 128 bits
8689 emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
8690 }
8691
8692 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8693 assert(VM_Version::supports_avx(), "");
8694 assert(dst != xnoreg, "sanity");
8695 assert(imm8 <= 0x01, "imm8: %u", imm8);
8696 InstructionMark im(this);
8697 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8698 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8699 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8700 emit_int8(0x18);
8701 emit_operand(dst, src, 1);
8702 // 0x00 - insert into lower 128 bits
8703 // 0x01 - insert into upper 128 bits
8704 emit_int8(imm8 & 0x01);
8705 }
8706
8707 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8708 assert(VM_Version::supports_evex(), "");
8709 assert(imm8 <= 0x03, "imm8: %u", imm8);
8710 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8711 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8712 // imm8:
8713 // 0x00 - insert into q0 128 bits (0..127)
8714 // 0x01 - insert into q1 128 bits (128..255)
8715 // 0x02 - insert into q0 128 bits (256..383)
8716 // 0x03 - insert into q1 128 bits (384..512)
8717 emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
8718 }
8719
8720 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8721 assert(VM_Version::supports_evex(), "");
8722 assert(dst != xnoreg, "sanity");
8723 assert(imm8 <= 0x03, "imm8: %u", imm8);
8724 InstructionMark im(this);
8725 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8726 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8727 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8728 emit_int8(0x18);
8729 emit_operand(dst, src, 1);
8730 // 0x00 - insert into q0 128 bits (0..127)
8731 // 0x01 - insert into q1 128 bits (128..255)
8732 // 0x02 - insert into q0 128 bits (256..383)
8733 // 0x03 - insert into q1 128 bits (384..512)
8734 emit_int8(imm8 & 0x03);
8735 }
8736
8737 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8738 assert(VM_Version::supports_evex(), "");
8739 assert(imm8 <= 0x01, "imm8: %u", imm8);
8740 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8741 attributes.set_is_evex_instruction();
8742 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8743 // imm8:
8744 // 0x00 - insert into lower 256 bits
8745 // 0x01 - insert into upper 256 bits
8746 emit_int24(0x1A, (0xC0 | encode), imm8 & 0x01);
8747 }
8748
8749 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8750 assert(VM_Version::supports_evex(), "");
8751 assert(dst != xnoreg, "sanity");
8752 assert(imm8 <= 0x01, "imm8: %u", imm8);
8753 InstructionMark im(this);
8754 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8755 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8756 attributes.set_is_evex_instruction();
8757 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8758 emit_int8(0x1A);
8759 emit_operand(dst, src, 1);
8760 // 0x00 - insert into lower 256 bits
8761 // 0x01 - insert into upper 256 bits
8762 emit_int8(imm8 & 0x01);
8763 }
8764
8765
8766 // vextracti forms
8767
8768 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8769 assert(VM_Version::supports_avx2(), "");
8770 assert(imm8 <= 0x01, "imm8: %u", imm8);
8771 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8772 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8773 // imm8:
8774 // 0x00 - extract from lower 128 bits
8775 // 0x01 - extract from upper 128 bits
8776 emit_int24(0x39, (0xC0 | encode), imm8 & 0x01);
8777 }
8778
8779 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
8780 assert(VM_Version::supports_avx2(), "");
8781 assert(src != xnoreg, "sanity");
8782 assert(imm8 <= 0x01, "imm8: %u", imm8);
8783 InstructionMark im(this);
8784 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8785 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8786 attributes.reset_is_clear_context();
8787 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8788 emit_int8(0x39);
8789 emit_operand(src, dst, 1);
8790 // 0x00 - extract from lower 128 bits
8791 // 0x01 - extract from upper 128 bits
8792 emit_int8(imm8 & 0x01);
8793 }
8794
8795 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8796 assert(VM_Version::supports_evex(), "");
8797 assert(imm8 <= 0x03, "imm8: %u", imm8);
8798 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8799 attributes.set_is_evex_instruction();
8800 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8801 // imm8:
8802 // 0x00 - extract from bits 127:0
8803 // 0x01 - extract from bits 255:128
8804 // 0x02 - extract from bits 383:256
8805 // 0x03 - extract from bits 511:384
8806 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8807 }
8808
8809 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
8810 assert(VM_Version::supports_evex(), "");
8811 assert(src != xnoreg, "sanity");
8812 assert(imm8 <= 0x03, "imm8: %u", imm8);
8813 InstructionMark im(this);
8814 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8815 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8816 attributes.reset_is_clear_context();
8817 attributes.set_is_evex_instruction();
8818 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8819 emit_int8(0x39);
8820 emit_operand(src, dst, 1);
8821 // 0x00 - extract from bits 127:0
8822 // 0x01 - extract from bits 255:128
8823 // 0x02 - extract from bits 383:256
8824 // 0x03 - extract from bits 511:384
8825 emit_int8(imm8 & 0x03);
8826 }
8827
8828 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8829 assert(VM_Version::supports_avx512dq(), "");
8830 assert(imm8 <= 0x03, "imm8: %u", imm8);
8831 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8832 attributes.set_is_evex_instruction();
8833 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8834 // imm8:
8835 // 0x00 - extract from bits 127:0
8836 // 0x01 - extract from bits 255:128
8837 // 0x02 - extract from bits 383:256
8838 // 0x03 - extract from bits 511:384
8839 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8840 }
8841
8842 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8843 assert(VM_Version::supports_evex(), "");
8844 assert(imm8 <= 0x01, "imm8: %u", imm8);
8845 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8846 attributes.set_is_evex_instruction();
8847 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8848 // imm8:
8849 // 0x00 - extract from lower 256 bits
8850 // 0x01 - extract from upper 256 bits
8851 emit_int24(0x3B, (0xC0 | encode), imm8 & 0x01);
8852 }
8853
8854 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
8855 assert(VM_Version::supports_evex(), "");
8856 assert(src != xnoreg, "sanity");
8857 assert(imm8 <= 0x01, "imm8: %u", imm8);
8858 InstructionMark im(this);
8859 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8860 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8861 attributes.reset_is_clear_context();
8862 attributes.set_is_evex_instruction();
8863 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8864 emit_int8(0x38);
8865 emit_operand(src, dst, 1);
8866 // 0x00 - extract from lower 256 bits
8867 // 0x01 - extract from upper 256 bits
8868 emit_int8(imm8 & 0x01);
8869 }
8870 // vextractf forms
8871
8872 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8873 assert(VM_Version::supports_avx(), "");
8874 assert(imm8 <= 0x01, "imm8: %u", imm8);
8875 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8876 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8877 // imm8:
8878 // 0x00 - extract from lower 128 bits
8879 // 0x01 - extract from upper 128 bits
8880 emit_int24(0x19, (0xC0 | encode), imm8 & 0x01);
8881 }
8882
8883 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
8884 assert(VM_Version::supports_avx(), "");
8885 assert(src != xnoreg, "sanity");
8886 assert(imm8 <= 0x01, "imm8: %u", imm8);
8887 InstructionMark im(this);
8888 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8889 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8890 attributes.reset_is_clear_context();
8891 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8892 emit_int8(0x19);
8893 emit_operand(src, dst, 1);
8894 // 0x00 - extract from lower 128 bits
8895 // 0x01 - extract from upper 128 bits
8896 emit_int8(imm8 & 0x01);
8897 }
8898
8899 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8900 assert(VM_Version::supports_evex(), "");
8901 assert(imm8 <= 0x03, "imm8: %u", imm8);
8902 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8903 attributes.set_is_evex_instruction();
8904 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8905 // imm8:
8906 // 0x00 - extract from bits 127:0
8907 // 0x01 - extract from bits 255:128
8908 // 0x02 - extract from bits 383:256
8909 // 0x03 - extract from bits 511:384
8910 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8911 }
8912
8913 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
8914 assert(VM_Version::supports_evex(), "");
8915 assert(src != xnoreg, "sanity");
8916 assert(imm8 <= 0x03, "imm8: %u", imm8);
8917 InstructionMark im(this);
8918 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8919 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8920 attributes.reset_is_clear_context();
8921 attributes.set_is_evex_instruction();
8922 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8923 emit_int8(0x19);
8924 emit_operand(src, dst, 1);
8925 // 0x00 - extract from bits 127:0
8926 // 0x01 - extract from bits 255:128
8927 // 0x02 - extract from bits 383:256
8928 // 0x03 - extract from bits 511:384
8929 emit_int8(imm8 & 0x03);
8930 }
8931
8932 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8933 assert(VM_Version::supports_avx512dq(), "");
8934 assert(imm8 <= 0x03, "imm8: %u", imm8);
8935 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8936 attributes.set_is_evex_instruction();
8937 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8938 // imm8:
8939 // 0x00 - extract from bits 127:0
8940 // 0x01 - extract from bits 255:128
8941 // 0x02 - extract from bits 383:256
8942 // 0x03 - extract from bits 511:384
8943 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8944 }
8945
8946 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8947 assert(VM_Version::supports_evex(), "");
8948 assert(imm8 <= 0x01, "imm8: %u", imm8);
8949 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8950 attributes.set_is_evex_instruction();
8951 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8952 // imm8:
8953 // 0x00 - extract from lower 256 bits
8954 // 0x01 - extract from upper 256 bits
8955 emit_int24(0x1B, (0xC0 | encode), imm8 & 0x01);
8956 }
8957
8958 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
8959 assert(VM_Version::supports_evex(), "");
8960 assert(src != xnoreg, "sanity");
8961 assert(imm8 <= 0x01, "imm8: %u", imm8);
8962 InstructionMark im(this);
8963 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8964 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
8965 attributes.reset_is_clear_context();
8966 attributes.set_is_evex_instruction();
8967 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8968 emit_int8(0x1B);
8969 emit_operand(src, dst, 1);
8970 // 0x00 - extract from lower 256 bits
8971 // 0x01 - extract from upper 256 bits
8972 emit_int8(imm8 & 0x01);
8973 }
8974
8975 void Assembler::extractps(Register dst, XMMRegister src, uint8_t imm8) {
8976 assert(VM_Version::supports_sse4_1(), "");
8977 assert(imm8 <= 0x03, "imm8: %u", imm8);
8978 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8979 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8980 // imm8:
8981 // 0x00 - extract from bits 31:0
8982 // 0x01 - extract from bits 63:32
8983 // 0x02 - extract from bits 95:64
8984 // 0x03 - extract from bits 127:96
8985 emit_int24(0x17, (0xC0 | encode), imm8 & 0x03);
8986 }
8987
8988 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
8989 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
8990 assert(VM_Version::supports_avx2(), "");
8991 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8992 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8993 emit_int16(0x78, (0xC0 | encode));
8994 }
8995
8996 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
8997 assert(VM_Version::supports_avx2(), "");
8998 assert(dst != xnoreg, "sanity");
8999 InstructionMark im(this);
9000 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9001 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
9002 // swap src<->dst for encoding
9003 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9004 emit_int8(0x78);
9005 emit_operand(dst, src, 0);
9006 }
9007
9008 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
9009 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
9010 assert(VM_Version::supports_avx2(), "");
9011 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9012 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9013 emit_int16(0x79, (0xC0 | encode));
9014 }
9015
9016 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
9017 assert(VM_Version::supports_avx2(), "");
9018 assert(dst != xnoreg, "sanity");
9019 InstructionMark im(this);
9020 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9021 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
9022 // swap src<->dst for encoding
9023 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9024 emit_int8(0x79);
9025 emit_operand(dst, src, 0);
9026 }
9027
9028 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9029 assert(UseAVX > 0, "requires some form of AVX");
9030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9031 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9032 emit_int16((unsigned char)0xF6, (0xC0 | encode));
9033 }
9034
9035 void Assembler::vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9036 assert(UseAVX > 0, "requires some form of AVX");
9037 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9039 emit_int16(0x69, (0xC0 | encode));
9040 }
9041
9042 void Assembler::vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9043 assert(UseAVX > 0, "requires some form of AVX");
9044 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9045 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9046 emit_int16(0x61, (0xC0 | encode));
9047 }
9048
9049 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9050 assert(UseAVX > 0, "requires some form of AVX");
9051 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9052 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9053 emit_int16(0x6A, (0xC0 | encode));
9054 }
9055
9056 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9057 assert(UseAVX > 0, "requires some form of AVX");
9058 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9059 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9060 emit_int16(0x62, (0xC0 | encode));
9061 }
9062
9063 // xmm/mem sourced byte/word/dword/qword replicate
9064 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9065 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9066 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9067 attributes.set_is_evex_instruction();
9068 attributes.set_embedded_opmask_register_specifier(mask);
9069 if (merge) {
9070 attributes.reset_is_clear_context();
9071 }
9072 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9073 emit_int16((unsigned char)0xFC, (0xC0 | encode));
9074 }
9075
9076 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9077 InstructionMark im(this);
9078 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9079 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9080 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9081 attributes.set_is_evex_instruction();
9082 attributes.set_embedded_opmask_register_specifier(mask);
9083 if (merge) {
9084 attributes.reset_is_clear_context();
9085 }
9086 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9087 emit_int8((unsigned char)0xFC);
9088 emit_operand(dst, src, 0);
9089 }
9090
9091 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9092 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9093 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9094 attributes.set_is_evex_instruction();
9095 attributes.set_embedded_opmask_register_specifier(mask);
9096 if (merge) {
9097 attributes.reset_is_clear_context();
9098 }
9099 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9100 emit_int16((unsigned char)0xFD, (0xC0 | encode));
9101 }
9102
9103 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9104 InstructionMark im(this);
9105 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9106 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9107 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9108 attributes.set_is_evex_instruction();
9109 attributes.set_embedded_opmask_register_specifier(mask);
9110 if (merge) {
9111 attributes.reset_is_clear_context();
9112 }
9113 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9114 emit_int8((unsigned char)0xFD);
9115 emit_operand(dst, src, 0);
9116 }
9117
9118 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9119 assert(VM_Version::supports_evex(), "");
9120 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9121 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9122 attributes.set_is_evex_instruction();
9123 attributes.set_embedded_opmask_register_specifier(mask);
9124 if (merge) {
9125 attributes.reset_is_clear_context();
9126 }
9127 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9128 emit_int16((unsigned char)0xFE, (0xC0 | encode));
9129 }
9130
9131 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9132 InstructionMark im(this);
9133 assert(VM_Version::supports_evex(), "");
9134 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9135 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9136 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9137 attributes.set_is_evex_instruction();
9138 attributes.set_embedded_opmask_register_specifier(mask);
9139 if (merge) {
9140 attributes.reset_is_clear_context();
9141 }
9142 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9143 emit_int8((unsigned char)0xFE);
9144 emit_operand(dst, src, 0);
9145 }
9146
9147 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9148 assert(VM_Version::supports_evex(), "");
9149 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9150 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9151 attributes.set_is_evex_instruction();
9152 attributes.set_embedded_opmask_register_specifier(mask);
9153 if (merge) {
9154 attributes.reset_is_clear_context();
9155 }
9156 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9157 emit_int16((unsigned char)0xD4, (0xC0 | encode));
9158 }
9159
9160 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9161 InstructionMark im(this);
9162 assert(VM_Version::supports_evex(), "");
9163 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9164 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9165 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9166 attributes.set_is_evex_instruction();
9167 attributes.set_embedded_opmask_register_specifier(mask);
9168 if (merge) {
9169 attributes.reset_is_clear_context();
9170 }
9171 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9172 emit_int8((unsigned char)0xD4);
9173 emit_operand(dst, src, 0);
9174 }
9175
9176 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9177 assert(VM_Version::supports_evex(), "");
9178 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9180 attributes.set_is_evex_instruction();
9181 attributes.set_embedded_opmask_register_specifier(mask);
9182 if (merge) {
9183 attributes.reset_is_clear_context();
9184 }
9185 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9186 emit_int16(0x58, (0xC0 | encode));
9187 }
9188
9189 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9190 InstructionMark im(this);
9191 assert(VM_Version::supports_evex(), "");
9192 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9193 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9194 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9195 attributes.set_is_evex_instruction();
9196 attributes.set_embedded_opmask_register_specifier(mask);
9197 if (merge) {
9198 attributes.reset_is_clear_context();
9199 }
9200 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9201 emit_int8(0x58);
9202 emit_operand(dst, src, 0);
9203 }
9204
9205 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9206 assert(VM_Version::supports_evex(), "");
9207 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9208 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9209 attributes.set_is_evex_instruction();
9210 attributes.set_embedded_opmask_register_specifier(mask);
9211 if (merge) {
9212 attributes.reset_is_clear_context();
9213 }
9214 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9215 emit_int16(0x58, (0xC0 | encode));
9216 }
9217
9218 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9219 InstructionMark im(this);
9220 assert(VM_Version::supports_evex(), "");
9221 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9222 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9223 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9224 attributes.set_is_evex_instruction();
9225 attributes.set_embedded_opmask_register_specifier(mask);
9226 if (merge) {
9227 attributes.reset_is_clear_context();
9228 }
9229 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9230 emit_int8(0x58);
9231 emit_operand(dst, src, 0);
9232 }
9233
9234 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9235 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9236 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9237 attributes.set_is_evex_instruction();
9238 attributes.set_embedded_opmask_register_specifier(mask);
9239 if (merge) {
9240 attributes.reset_is_clear_context();
9241 }
9242 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9243 emit_int16((unsigned char)0xF8, (0xC0 | encode));
9244 }
9245
9246 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9247 InstructionMark im(this);
9248 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9249 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9250 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9251 attributes.set_is_evex_instruction();
9252 attributes.set_embedded_opmask_register_specifier(mask);
9253 if (merge) {
9254 attributes.reset_is_clear_context();
9255 }
9256 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9257 emit_int8((unsigned char)0xF8);
9258 emit_operand(dst, src, 0);
9259 }
9260
9261 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9262 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9263 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9264 attributes.set_is_evex_instruction();
9265 attributes.set_embedded_opmask_register_specifier(mask);
9266 if (merge) {
9267 attributes.reset_is_clear_context();
9268 }
9269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9270 emit_int16((unsigned char)0xF9, (0xC0 | encode));
9271 }
9272
9273 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9274 InstructionMark im(this);
9275 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9276 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9277 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9278 attributes.set_is_evex_instruction();
9279 attributes.set_embedded_opmask_register_specifier(mask);
9280 if (merge) {
9281 attributes.reset_is_clear_context();
9282 }
9283 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9284 emit_int8((unsigned char)0xF9);
9285 emit_operand(dst, src, 0);
9286 }
9287
9288 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9289 assert(VM_Version::supports_evex(), "");
9290 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9291 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9292 attributes.set_is_evex_instruction();
9293 attributes.set_embedded_opmask_register_specifier(mask);
9294 if (merge) {
9295 attributes.reset_is_clear_context();
9296 }
9297 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9298 emit_int16((unsigned char)0xFA, (0xC0 | encode));
9299 }
9300
9301 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9302 InstructionMark im(this);
9303 assert(VM_Version::supports_evex(), "");
9304 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9305 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9306 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9307 attributes.set_is_evex_instruction();
9308 attributes.set_embedded_opmask_register_specifier(mask);
9309 if (merge) {
9310 attributes.reset_is_clear_context();
9311 }
9312 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9313 emit_int8((unsigned char)0xFA);
9314 emit_operand(dst, src, 0);
9315 }
9316
9317 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9318 assert(VM_Version::supports_evex(), "");
9319 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9320 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9321 attributes.set_is_evex_instruction();
9322 attributes.set_embedded_opmask_register_specifier(mask);
9323 if (merge) {
9324 attributes.reset_is_clear_context();
9325 }
9326 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9327 emit_int16((unsigned char)0xFB, (0xC0 | encode));
9328 }
9329
9330 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9331 InstructionMark im(this);
9332 assert(VM_Version::supports_evex(), "");
9333 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9334 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9335 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9336 attributes.set_is_evex_instruction();
9337 attributes.set_embedded_opmask_register_specifier(mask);
9338 if (merge) {
9339 attributes.reset_is_clear_context();
9340 }
9341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9342 emit_int8((unsigned char)0xFB);
9343 emit_operand(dst, src, 0);
9344 }
9345
9346 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9347 assert(VM_Version::supports_evex(), "");
9348 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9350 attributes.set_is_evex_instruction();
9351 attributes.set_embedded_opmask_register_specifier(mask);
9352 if (merge) {
9353 attributes.reset_is_clear_context();
9354 }
9355 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9356 emit_int16(0x5C, (0xC0 | encode));
9357 }
9358
9359 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9360 InstructionMark im(this);
9361 assert(VM_Version::supports_evex(), "");
9362 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9363 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9364 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9365 attributes.set_is_evex_instruction();
9366 attributes.set_embedded_opmask_register_specifier(mask);
9367 if (merge) {
9368 attributes.reset_is_clear_context();
9369 }
9370 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9371 emit_int8(0x5C);
9372 emit_operand(dst, src, 0);
9373 }
9374
9375 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9376 assert(VM_Version::supports_evex(), "");
9377 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9378 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9379 attributes.set_is_evex_instruction();
9380 attributes.set_embedded_opmask_register_specifier(mask);
9381 if (merge) {
9382 attributes.reset_is_clear_context();
9383 }
9384 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9385 emit_int16(0x5C, (0xC0 | encode));
9386 }
9387
9388 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9389 InstructionMark im(this);
9390 assert(VM_Version::supports_evex(), "");
9391 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9392 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9393 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9394 attributes.set_is_evex_instruction();
9395 attributes.set_embedded_opmask_register_specifier(mask);
9396 if (merge) {
9397 attributes.reset_is_clear_context();
9398 }
9399 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9400 emit_int8(0x5C);
9401 emit_operand(dst, src, 0);
9402 }
9403
9404 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9405 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9406 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9407 attributes.set_is_evex_instruction();
9408 attributes.set_embedded_opmask_register_specifier(mask);
9409 if (merge) {
9410 attributes.reset_is_clear_context();
9411 }
9412 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9413 emit_int16((unsigned char)0xD5, (0xC0 | encode));
9414 }
9415
9416 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9417 InstructionMark im(this);
9418 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9419 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9420 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9421 attributes.set_is_evex_instruction();
9422 attributes.set_embedded_opmask_register_specifier(mask);
9423 if (merge) {
9424 attributes.reset_is_clear_context();
9425 }
9426 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9427 emit_int8((unsigned char)0xD5);
9428 emit_operand(dst, src, 0);
9429 }
9430
9431 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9432 assert(VM_Version::supports_evex(), "");
9433 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9434 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9435 attributes.set_is_evex_instruction();
9436 attributes.set_embedded_opmask_register_specifier(mask);
9437 if (merge) {
9438 attributes.reset_is_clear_context();
9439 }
9440 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9441 emit_int16(0x40, (0xC0 | encode));
9442 }
9443
9444 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9445 InstructionMark im(this);
9446 assert(VM_Version::supports_evex(), "");
9447 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9448 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9449 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9450 attributes.set_is_evex_instruction();
9451 attributes.set_embedded_opmask_register_specifier(mask);
9452 if (merge) {
9453 attributes.reset_is_clear_context();
9454 }
9455 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9456 emit_int8(0x40);
9457 emit_operand(dst, src, 0);
9458 }
9459
9460 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9461 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9462 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9463 attributes.set_is_evex_instruction();
9464 attributes.set_embedded_opmask_register_specifier(mask);
9465 if (merge) {
9466 attributes.reset_is_clear_context();
9467 }
9468 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9469 emit_int16(0x40, (0xC0 | encode));
9470 }
9471
9472 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9473 InstructionMark im(this);
9474 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9475 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9476 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9477 attributes.set_is_evex_instruction();
9478 attributes.set_embedded_opmask_register_specifier(mask);
9479 if (merge) {
9480 attributes.reset_is_clear_context();
9481 }
9482 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9483 emit_int8(0x40);
9484 emit_operand(dst, src, 0);
9485 }
9486
9487 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9488 assert(VM_Version::supports_evex(), "");
9489 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9490 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9491 attributes.set_is_evex_instruction();
9492 attributes.set_embedded_opmask_register_specifier(mask);
9493 if (merge) {
9494 attributes.reset_is_clear_context();
9495 }
9496 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9497 emit_int16(0x59, (0xC0 | encode));
9498 }
9499
9500 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9501 InstructionMark im(this);
9502 assert(VM_Version::supports_evex(), "");
9503 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9504 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9505 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9506 attributes.set_is_evex_instruction();
9507 attributes.set_embedded_opmask_register_specifier(mask);
9508 if (merge) {
9509 attributes.reset_is_clear_context();
9510 }
9511 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9512 emit_int8(0x59);
9513 emit_operand(dst, src, 0);
9514 }
9515
9516 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9517 assert(VM_Version::supports_evex(), "");
9518 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9519 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9520 attributes.set_is_evex_instruction();
9521 attributes.set_embedded_opmask_register_specifier(mask);
9522 if (merge) {
9523 attributes.reset_is_clear_context();
9524 }
9525 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9526 emit_int16(0x59, (0xC0 | encode));
9527 }
9528
9529 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9530 InstructionMark im(this);
9531 assert(VM_Version::supports_evex(), "");
9532 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9533 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9534 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9535 attributes.set_is_evex_instruction();
9536 attributes.set_embedded_opmask_register_specifier(mask);
9537 if (merge) {
9538 attributes.reset_is_clear_context();
9539 }
9540 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9541 emit_int8(0x59);
9542 emit_operand(dst, src, 0);
9543 }
9544
9545 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9546 assert(VM_Version::supports_evex(), "");
9547 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9548 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9549 attributes.set_is_evex_instruction();
9550 attributes.set_embedded_opmask_register_specifier(mask);
9551 if (merge) {
9552 attributes.reset_is_clear_context();
9553 }
9554 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9555 emit_int16(0x51, (0xC0 | encode));
9556 }
9557
9558 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9559 InstructionMark im(this);
9560 assert(VM_Version::supports_evex(), "");
9561 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9562 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9563 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9564 attributes.set_is_evex_instruction();
9565 attributes.set_embedded_opmask_register_specifier(mask);
9566 if (merge) {
9567 attributes.reset_is_clear_context();
9568 }
9569 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9570 emit_int8(0x51);
9571 emit_operand(dst, src, 0);
9572 }
9573
9574 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9575 assert(VM_Version::supports_evex(), "");
9576 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9577 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9578 attributes.set_is_evex_instruction();
9579 attributes.set_embedded_opmask_register_specifier(mask);
9580 if (merge) {
9581 attributes.reset_is_clear_context();
9582 }
9583 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9584 emit_int16(0x51, (0xC0 | encode));
9585 }
9586
9587 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9588 InstructionMark im(this);
9589 assert(VM_Version::supports_evex(), "");
9590 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9591 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9592 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9593 attributes.set_is_evex_instruction();
9594 attributes.set_embedded_opmask_register_specifier(mask);
9595 if (merge) {
9596 attributes.reset_is_clear_context();
9597 }
9598 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9599 emit_int8(0x51);
9600 emit_operand(dst, src, 0);
9601 }
9602
9603
9604 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9605 assert(VM_Version::supports_evex(), "");
9606 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9607 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9608 attributes.set_is_evex_instruction();
9609 attributes.set_embedded_opmask_register_specifier(mask);
9610 if (merge) {
9611 attributes.reset_is_clear_context();
9612 }
9613 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9614 emit_int16(0x5E, (0xC0 | encode));
9615 }
9616
9617 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9618 InstructionMark im(this);
9619 assert(VM_Version::supports_evex(), "");
9620 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9621 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9622 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9623 attributes.set_is_evex_instruction();
9624 attributes.set_embedded_opmask_register_specifier(mask);
9625 if (merge) {
9626 attributes.reset_is_clear_context();
9627 }
9628 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9629 emit_int8(0x5E);
9630 emit_operand(dst, src, 0);
9631 }
9632
9633 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9634 assert(VM_Version::supports_evex(), "");
9635 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9636 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9637 attributes.set_is_evex_instruction();
9638 attributes.set_embedded_opmask_register_specifier(mask);
9639 if (merge) {
9640 attributes.reset_is_clear_context();
9641 }
9642 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9643 emit_int16(0x5E, (0xC0 | encode));
9644 }
9645
9646 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9647 InstructionMark im(this);
9648 assert(VM_Version::supports_evex(), "");
9649 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9650 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9651 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9652 attributes.set_is_evex_instruction();
9653 attributes.set_embedded_opmask_register_specifier(mask);
9654 if (merge) {
9655 attributes.reset_is_clear_context();
9656 }
9657 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9658 emit_int8(0x5E);
9659 emit_operand(dst, src, 0);
9660 }
9661
9662 void Assembler::evdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src, EvexRoundPrefix rmode) {
9663 assert(VM_Version::supports_evex(), "");
9664 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9665 attributes.set_extended_context();
9666 attributes.set_is_evex_instruction();
9667 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9668 emit_int16(0x5E, (0xC0 | encode));
9669 }
9670
9671 void Assembler::evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9672 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9673 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9674 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9675 attributes.set_is_evex_instruction();
9676 attributes.set_embedded_opmask_register_specifier(mask);
9677 if (merge) {
9678 attributes.reset_is_clear_context();
9679 }
9680 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9681 emit_int16(0x1C, (0xC0 | encode));
9682 }
9683
9684
9685 void Assembler::evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9686 InstructionMark im(this);
9687 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9688 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9689 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9690 attributes.set_is_evex_instruction();
9691 attributes.set_embedded_opmask_register_specifier(mask);
9692 if (merge) {
9693 attributes.reset_is_clear_context();
9694 }
9695 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9696 emit_int8(0x1C);
9697 emit_operand(dst, src, 0);
9698 }
9699
9700 void Assembler::evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9701 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9702 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9703 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9704 attributes.set_is_evex_instruction();
9705 attributes.set_embedded_opmask_register_specifier(mask);
9706 if (merge) {
9707 attributes.reset_is_clear_context();
9708 }
9709 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9710 emit_int16(0x1D, (0xC0 | encode));
9711 }
9712
9713
9714 void Assembler::evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9715 InstructionMark im(this);
9716 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9717 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9718 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9719 attributes.set_is_evex_instruction();
9720 attributes.set_embedded_opmask_register_specifier(mask);
9721 if (merge) {
9722 attributes.reset_is_clear_context();
9723 }
9724 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9725 emit_int8(0x1D);
9726 emit_operand(dst, src, 0);
9727 }
9728
9729 void Assembler::evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9730 assert(VM_Version::supports_evex(), "");
9731 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9732 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9733 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9734 attributes.set_is_evex_instruction();
9735 attributes.set_embedded_opmask_register_specifier(mask);
9736 if (merge) {
9737 attributes.reset_is_clear_context();
9738 }
9739 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9740 emit_int16(0x1E, (0xC0 | encode));
9741 }
9742
9743
9744 void Assembler::evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9745 InstructionMark im(this);
9746 assert(VM_Version::supports_evex(), "");
9747 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9748 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9749 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9750 attributes.set_is_evex_instruction();
9751 attributes.set_embedded_opmask_register_specifier(mask);
9752 if (merge) {
9753 attributes.reset_is_clear_context();
9754 }
9755 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9756 emit_int8(0x1E);
9757 emit_operand(dst, src, 0);
9758 }
9759
9760 void Assembler::evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9761 assert(VM_Version::supports_evex(), "");
9762 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9763 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9764 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9765 attributes.set_is_evex_instruction();
9766 attributes.set_embedded_opmask_register_specifier(mask);
9767 if (merge) {
9768 attributes.reset_is_clear_context();
9769 }
9770 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9771 emit_int16(0x1F, (0xC0 | encode));
9772 }
9773
9774
9775 void Assembler::evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9776 InstructionMark im(this);
9777 assert(VM_Version::supports_evex(), "");
9778 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9779 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9780 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9781 attributes.set_is_evex_instruction();
9782 attributes.set_embedded_opmask_register_specifier(mask);
9783 if (merge) {
9784 attributes.reset_is_clear_context();
9785 }
9786 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9787 emit_int8(0x1F);
9788 emit_operand(dst, src, 0);
9789 }
9790
9791 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9792 assert(VM_Version::supports_evex(), "");
9793 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9794 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9795 attributes.set_is_evex_instruction();
9796 attributes.set_embedded_opmask_register_specifier(mask);
9797 if (merge) {
9798 attributes.reset_is_clear_context();
9799 }
9800 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9801 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9802 }
9803
9804 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9805 InstructionMark im(this);
9806 assert(VM_Version::supports_evex(), "");
9807 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9808 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9809 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9810 attributes.set_is_evex_instruction();
9811 attributes.set_embedded_opmask_register_specifier(mask);
9812 if (merge) {
9813 attributes.reset_is_clear_context();
9814 }
9815 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9816 emit_int8((unsigned char)0xA8);
9817 emit_operand(dst, src, 0);
9818 }
9819
9820 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9821 assert(VM_Version::supports_evex(), "");
9822 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9823 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9824 attributes.set_is_evex_instruction();
9825 attributes.set_embedded_opmask_register_specifier(mask);
9826 if (merge) {
9827 attributes.reset_is_clear_context();
9828 }
9829 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9830 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9831 }
9832
9833 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9834 InstructionMark im(this);
9835 assert(VM_Version::supports_evex(), "");
9836 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9837 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9838 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9839 attributes.set_is_evex_instruction();
9840 attributes.set_embedded_opmask_register_specifier(mask);
9841 if (merge) {
9842 attributes.reset_is_clear_context();
9843 }
9844 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9845 emit_int8((unsigned char)0xA8);
9846 emit_operand(dst, src, 0);
9847 }
9848
9849 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9850 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9851 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9852 attributes.set_is_evex_instruction();
9853 attributes.set_embedded_opmask_register_specifier(mask);
9854 if (merge) {
9855 attributes.reset_is_clear_context();
9856 }
9857 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9858 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9859 }
9860
9861 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9862 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9863 InstructionMark im(this);
9864 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9865 attributes.set_is_evex_instruction();
9866 attributes.set_embedded_opmask_register_specifier(mask);
9867 if (merge) {
9868 attributes.reset_is_clear_context();
9869 }
9870 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9871 emit_int8((unsigned char)0x8D);
9872 emit_operand(dst, src, 0);
9873 }
9874
9875 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9876 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9877 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9878 attributes.set_is_evex_instruction();
9879 attributes.set_embedded_opmask_register_specifier(mask);
9880 if (merge) {
9881 attributes.reset_is_clear_context();
9882 }
9883 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9884 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9885 }
9886
9887 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9888 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9889 InstructionMark im(this);
9890 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9891 attributes.set_is_evex_instruction();
9892 attributes.set_embedded_opmask_register_specifier(mask);
9893 if (merge) {
9894 attributes.reset_is_clear_context();
9895 }
9896 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9897 emit_int8((unsigned char)0x8D);
9898 emit_operand(dst, src, 0);
9899 }
9900
9901 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9902 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9903 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9904 attributes.set_is_evex_instruction();
9905 attributes.set_embedded_opmask_register_specifier(mask);
9906 if (merge) {
9907 attributes.reset_is_clear_context();
9908 }
9909 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9910 emit_int16(0x36, (0xC0 | encode));
9911 }
9912
9913 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9914 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9915 InstructionMark im(this);
9916 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9917 attributes.set_is_evex_instruction();
9918 attributes.set_embedded_opmask_register_specifier(mask);
9919 if (merge) {
9920 attributes.reset_is_clear_context();
9921 }
9922 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9923 emit_int8(0x36);
9924 emit_operand(dst, src, 0);
9925 }
9926
9927 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9928 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9929 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9930 attributes.set_is_evex_instruction();
9931 attributes.set_embedded_opmask_register_specifier(mask);
9932 if (merge) {
9933 attributes.reset_is_clear_context();
9934 }
9935 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9936 emit_int16(0x36, (0xC0 | encode));
9937 }
9938
9939 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9940 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9941 InstructionMark im(this);
9942 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9943 attributes.set_is_evex_instruction();
9944 attributes.set_embedded_opmask_register_specifier(mask);
9945 if (merge) {
9946 attributes.reset_is_clear_context();
9947 }
9948 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9949 emit_int8(0x36);
9950 emit_operand(dst, src, 0);
9951 }
9952
9953 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9954 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9956 attributes.set_is_evex_instruction();
9957 attributes.set_embedded_opmask_register_specifier(mask);
9958 if (merge) {
9959 attributes.reset_is_clear_context();
9960 }
9961 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9962 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
9963 }
9964
9965 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9966 assert(VM_Version::supports_evex(), "");
9967 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9968 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9969 attributes.set_is_evex_instruction();
9970 attributes.set_embedded_opmask_register_specifier(mask);
9971 if (merge) {
9972 attributes.reset_is_clear_context();
9973 }
9974 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9975 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
9976 }
9977
9978 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9979 assert(VM_Version::supports_evex(), "");
9980 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9981 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9982 attributes.set_is_evex_instruction();
9983 attributes.set_embedded_opmask_register_specifier(mask);
9984 if (merge) {
9985 attributes.reset_is_clear_context();
9986 }
9987 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9988 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
9989 }
9990
9991 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9992 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9993 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9994 attributes.set_is_evex_instruction();
9995 attributes.set_embedded_opmask_register_specifier(mask);
9996 if (merge) {
9997 attributes.reset_is_clear_context();
9998 }
9999 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10000 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
10001 }
10002
10003 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10004 assert(VM_Version::supports_evex(), "");
10005 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10006 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10007 attributes.set_is_evex_instruction();
10008 attributes.set_embedded_opmask_register_specifier(mask);
10009 if (merge) {
10010 attributes.reset_is_clear_context();
10011 }
10012 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10013 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10014 }
10015
10016 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10017 assert(VM_Version::supports_evex(), "");
10018 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10019 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10020 attributes.set_is_evex_instruction();
10021 attributes.set_embedded_opmask_register_specifier(mask);
10022 if (merge) {
10023 attributes.reset_is_clear_context();
10024 }
10025 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10026 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
10027 }
10028
10029 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10030 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10032 attributes.set_is_evex_instruction();
10033 attributes.set_embedded_opmask_register_specifier(mask);
10034 if (merge) {
10035 attributes.reset_is_clear_context();
10036 }
10037 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10038 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
10039 }
10040
10041 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10042 assert(VM_Version::supports_evex(), "");
10043 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10044 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10045 attributes.set_is_evex_instruction();
10046 attributes.set_embedded_opmask_register_specifier(mask);
10047 if (merge) {
10048 attributes.reset_is_clear_context();
10049 }
10050 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10051 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10052 }
10053
10054 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10055 assert(VM_Version::supports_evex(), "");
10056 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10057 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10058 attributes.set_is_evex_instruction();
10059 attributes.set_embedded_opmask_register_specifier(mask);
10060 if (merge) {
10061 attributes.reset_is_clear_context();
10062 }
10063 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10064 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10065 }
10066
10067 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10068 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10069 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10070 attributes.set_is_evex_instruction();
10071 attributes.set_embedded_opmask_register_specifier(mask);
10072 if (merge) {
10073 attributes.reset_is_clear_context();
10074 }
10075 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10076 emit_int16((unsigned char)0xF1, (0xC0 | encode));
10077 }
10078
10079 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10080 assert(VM_Version::supports_evex(), "");
10081 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10082 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10083 attributes.set_is_evex_instruction();
10084 attributes.set_embedded_opmask_register_specifier(mask);
10085 if (merge) {
10086 attributes.reset_is_clear_context();
10087 }
10088 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10089 emit_int16((unsigned char)0xF2, (0xC0 | encode));
10090 }
10091
10092 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10093 assert(VM_Version::supports_evex(), "");
10094 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10095 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10096 attributes.set_is_evex_instruction();
10097 attributes.set_embedded_opmask_register_specifier(mask);
10098 if (merge) {
10099 attributes.reset_is_clear_context();
10100 }
10101 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10102 emit_int16((unsigned char)0xF3, (0xC0 | encode));
10103 }
10104
10105 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10106 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10107 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10108 attributes.set_is_evex_instruction();
10109 attributes.set_embedded_opmask_register_specifier(mask);
10110 if (merge) {
10111 attributes.reset_is_clear_context();
10112 }
10113 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10114 emit_int16((unsigned char)0xD1, (0xC0 | encode));
10115 }
10116
10117 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10118 assert(VM_Version::supports_evex(), "");
10119 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10120 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10121 attributes.set_is_evex_instruction();
10122 attributes.set_embedded_opmask_register_specifier(mask);
10123 if (merge) {
10124 attributes.reset_is_clear_context();
10125 }
10126 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10127 emit_int16((unsigned char)0xD2, (0xC0 | encode));
10128 }
10129
10130 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10131 assert(VM_Version::supports_evex(), "");
10132 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10133 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10134 attributes.set_is_evex_instruction();
10135 attributes.set_embedded_opmask_register_specifier(mask);
10136 if (merge) {
10137 attributes.reset_is_clear_context();
10138 }
10139 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10140 emit_int16((unsigned char)0xD3, (0xC0 | encode));
10141 }
10142
10143 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10144 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10145 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10146 attributes.set_is_evex_instruction();
10147 attributes.set_embedded_opmask_register_specifier(mask);
10148 if (merge) {
10149 attributes.reset_is_clear_context();
10150 }
10151 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10152 emit_int16((unsigned char)0xE1, (0xC0 | encode));
10153 }
10154
10155 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10156 assert(VM_Version::supports_evex(), "");
10157 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10158 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10159 attributes.set_is_evex_instruction();
10160 attributes.set_embedded_opmask_register_specifier(mask);
10161 if (merge) {
10162 attributes.reset_is_clear_context();
10163 }
10164 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10165 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10166 }
10167
10168 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10169 assert(VM_Version::supports_evex(), "");
10170 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10171 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10172 attributes.set_is_evex_instruction();
10173 attributes.set_embedded_opmask_register_specifier(mask);
10174 if (merge) {
10175 attributes.reset_is_clear_context();
10176 }
10177 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10178 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10179 }
10180
10181 void Assembler::evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10182 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10183 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10184 attributes.set_is_evex_instruction();
10185 attributes.set_embedded_opmask_register_specifier(mask);
10186 if (merge) {
10187 attributes.reset_is_clear_context();
10188 }
10189 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10190 emit_int16(0x12, (0xC0 | encode));
10191 }
10192
10193 void Assembler::evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10194 assert(VM_Version::supports_evex(), "");
10195 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10196 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10197 attributes.set_is_evex_instruction();
10198 attributes.set_embedded_opmask_register_specifier(mask);
10199 if (merge) {
10200 attributes.reset_is_clear_context();
10201 }
10202 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10203 emit_int16(0x47, (0xC0 | encode));
10204 }
10205
10206 void Assembler::evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10207 assert(VM_Version::supports_evex(), "");
10208 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10209 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10210 attributes.set_is_evex_instruction();
10211 attributes.set_embedded_opmask_register_specifier(mask);
10212 if (merge) {
10213 attributes.reset_is_clear_context();
10214 }
10215 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10216 emit_int16(0x47, (0xC0 | encode));
10217 }
10218
10219 void Assembler::evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10220 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10221 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10222 attributes.set_is_evex_instruction();
10223 attributes.set_embedded_opmask_register_specifier(mask);
10224 if (merge) {
10225 attributes.reset_is_clear_context();
10226 }
10227 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10228 emit_int16(0x10, (0xC0 | encode));
10229 }
10230
10231 void Assembler::evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10232 assert(VM_Version::supports_evex(), "");
10233 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10235 attributes.set_is_evex_instruction();
10236 attributes.set_embedded_opmask_register_specifier(mask);
10237 if (merge) {
10238 attributes.reset_is_clear_context();
10239 }
10240 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10241 emit_int16(0x45, (0xC0 | encode));
10242 }
10243
10244 void Assembler::evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10245 assert(VM_Version::supports_evex(), "");
10246 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10247 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10248 attributes.set_is_evex_instruction();
10249 attributes.set_embedded_opmask_register_specifier(mask);
10250 if (merge) {
10251 attributes.reset_is_clear_context();
10252 }
10253 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10254 emit_int16(0x45, (0xC0 | encode));
10255 }
10256
10257 void Assembler::evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10258 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10259 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10260 attributes.set_is_evex_instruction();
10261 attributes.set_embedded_opmask_register_specifier(mask);
10262 if (merge) {
10263 attributes.reset_is_clear_context();
10264 }
10265 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10266 emit_int16(0x11, (0xC0 | encode));
10267 }
10268
10269 void Assembler::evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10270 assert(VM_Version::supports_evex(), "");
10271 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10272 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10273 attributes.set_is_evex_instruction();
10274 attributes.set_embedded_opmask_register_specifier(mask);
10275 if (merge) {
10276 attributes.reset_is_clear_context();
10277 }
10278 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10279 emit_int16(0x46, (0xC0 | encode));
10280 }
10281
10282 void Assembler::evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10283 assert(VM_Version::supports_evex(), "");
10284 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10285 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10286 attributes.set_is_evex_instruction();
10287 attributes.set_embedded_opmask_register_specifier(mask);
10288 if (merge) {
10289 attributes.reset_is_clear_context();
10290 }
10291 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10292 emit_int16(0x46, (0xC0 | encode));
10293 }
10294
10295 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10296 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10297 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10298 attributes.set_is_evex_instruction();
10299 attributes.set_embedded_opmask_register_specifier(mask);
10300 if (merge) {
10301 attributes.reset_is_clear_context();
10302 }
10303 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10304 emit_int16(0x38, (0xC0 | encode));
10305 }
10306
10307 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10308 assert(VM_Version::supports_avx512bw(), "");
10309 InstructionMark im(this);
10310 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10311 attributes.set_is_evex_instruction();
10312 attributes.set_embedded_opmask_register_specifier(mask);
10313 if (merge) {
10314 attributes.reset_is_clear_context();
10315 }
10316 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10317 emit_int8(0x38);
10318 emit_operand(dst, src, 0);
10319 }
10320
10321 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10322 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10324 attributes.set_is_evex_instruction();
10325 attributes.set_embedded_opmask_register_specifier(mask);
10326 if (merge) {
10327 attributes.reset_is_clear_context();
10328 }
10329 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10330 emit_int16((unsigned char)0xEA, (0xC0 | encode));
10331 }
10332
10333 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10334 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10335 InstructionMark im(this);
10336 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10337 attributes.set_is_evex_instruction();
10338 attributes.set_embedded_opmask_register_specifier(mask);
10339 if (merge) {
10340 attributes.reset_is_clear_context();
10341 }
10342 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10343 emit_int8((unsigned char)0xEA);
10344 emit_operand(dst, src, 0);
10345 }
10346
10347 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10348 assert(VM_Version::supports_evex(), "");
10349 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10350 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10351 attributes.set_is_evex_instruction();
10352 attributes.set_embedded_opmask_register_specifier(mask);
10353 if (merge) {
10354 attributes.reset_is_clear_context();
10355 }
10356 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10357 emit_int16(0x39, (0xC0 | encode));
10358 }
10359
10360 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10361 assert(VM_Version::supports_evex(), "");
10362 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10363 InstructionMark im(this);
10364 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10365 attributes.set_is_evex_instruction();
10366 attributes.set_embedded_opmask_register_specifier(mask);
10367 if (merge) {
10368 attributes.reset_is_clear_context();
10369 }
10370 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10371 emit_int8(0x39);
10372 emit_operand(dst, src, 0);
10373 }
10374
10375 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10376 assert(VM_Version::supports_evex(), "");
10377 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10378 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10379 attributes.set_is_evex_instruction();
10380 attributes.set_embedded_opmask_register_specifier(mask);
10381 if (merge) {
10382 attributes.reset_is_clear_context();
10383 }
10384 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10385 emit_int16(0x39, (0xC0 | encode));
10386 }
10387
10388 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10389 assert(VM_Version::supports_evex(), "");
10390 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10391 InstructionMark im(this);
10392 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10393 attributes.set_is_evex_instruction();
10394 attributes.set_embedded_opmask_register_specifier(mask);
10395 if (merge) {
10396 attributes.reset_is_clear_context();
10397 }
10398 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10399 emit_int8(0x39);
10400 emit_operand(dst, src, 0);
10401 }
10402
10403
10404 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10405 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10406 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10407 attributes.set_is_evex_instruction();
10408 attributes.set_embedded_opmask_register_specifier(mask);
10409 if (merge) {
10410 attributes.reset_is_clear_context();
10411 }
10412 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10413 emit_int16(0x3C, (0xC0 | encode));
10414 }
10415
10416 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10417 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10418 InstructionMark im(this);
10419 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10420 attributes.set_is_evex_instruction();
10421 attributes.set_embedded_opmask_register_specifier(mask);
10422 if (merge) {
10423 attributes.reset_is_clear_context();
10424 }
10425 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10426 emit_int8(0x3C);
10427 emit_operand(dst, src, 0);
10428 }
10429
10430 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10431 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10432 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10433 attributes.set_is_evex_instruction();
10434 attributes.set_embedded_opmask_register_specifier(mask);
10435 if (merge) {
10436 attributes.reset_is_clear_context();
10437 }
10438 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10439 emit_int16((unsigned char)0xEE, (0xC0 | encode));
10440 }
10441
10442 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10443 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10444 InstructionMark im(this);
10445 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10446 attributes.set_is_evex_instruction();
10447 attributes.set_embedded_opmask_register_specifier(mask);
10448 if (merge) {
10449 attributes.reset_is_clear_context();
10450 }
10451 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10452 emit_int8((unsigned char)0xEE);
10453 emit_operand(dst, src, 0);
10454 }
10455
10456 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10457 assert(VM_Version::supports_evex(), "");
10458 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10459 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10460 attributes.set_is_evex_instruction();
10461 attributes.set_embedded_opmask_register_specifier(mask);
10462 if (merge) {
10463 attributes.reset_is_clear_context();
10464 }
10465 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10466 emit_int16(0x3D, (0xC0 | encode));
10467 }
10468
10469 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10470 assert(VM_Version::supports_evex(), "");
10471 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10472 InstructionMark im(this);
10473 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10474 attributes.set_is_evex_instruction();
10475 attributes.set_embedded_opmask_register_specifier(mask);
10476 if (merge) {
10477 attributes.reset_is_clear_context();
10478 }
10479 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10480 emit_int8(0x3D);
10481 emit_operand(dst, src, 0);
10482 }
10483
10484 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10485 assert(VM_Version::supports_evex(), "");
10486 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10487 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10488 attributes.set_is_evex_instruction();
10489 attributes.set_embedded_opmask_register_specifier(mask);
10490 if (merge) {
10491 attributes.reset_is_clear_context();
10492 }
10493 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10494 emit_int16(0x3D, (0xC0 | encode));
10495 }
10496
10497 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10498 assert(VM_Version::supports_evex(), "");
10499 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10500 InstructionMark im(this);
10501 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10502 attributes.set_is_evex_instruction();
10503 attributes.set_embedded_opmask_register_specifier(mask);
10504 if (merge) {
10505 attributes.reset_is_clear_context();
10506 }
10507 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10508 emit_int8(0x3D);
10509 emit_operand(dst, src, 0);
10510 }
10511
10512 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10513 assert(VM_Version::supports_evex(), "requires EVEX support");
10514 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10515 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10516 attributes.set_is_evex_instruction();
10517 attributes.set_embedded_opmask_register_specifier(mask);
10518 if (merge) {
10519 attributes.reset_is_clear_context();
10520 }
10521 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10522 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10523 }
10524
10525 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10526 assert(VM_Version::supports_evex(), "requires EVEX support");
10527 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10528 assert(dst != xnoreg, "sanity");
10529 InstructionMark im(this);
10530 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10531 attributes.set_is_evex_instruction();
10532 attributes.set_embedded_opmask_register_specifier(mask);
10533 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10534 if (merge) {
10535 attributes.reset_is_clear_context();
10536 }
10537 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10538 emit_int8(0x25);
10539 emit_operand(dst, src3, 1);
10540 emit_int8(imm8);
10541 }
10542
10543 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10544 assert(VM_Version::supports_evex(), "requires EVEX support");
10545 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10546 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10547 attributes.set_is_evex_instruction();
10548 attributes.set_embedded_opmask_register_specifier(mask);
10549 if (merge) {
10550 attributes.reset_is_clear_context();
10551 }
10552 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10553 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10554 }
10555
10556 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10557 assert(VM_Version::supports_evex(), "requires EVEX support");
10558 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10559 assert(dst != xnoreg, "sanity");
10560 InstructionMark im(this);
10561 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10562 attributes.set_is_evex_instruction();
10563 attributes.set_embedded_opmask_register_specifier(mask);
10564 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10565 if (merge) {
10566 attributes.reset_is_clear_context();
10567 }
10568 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10569 emit_int8(0x25);
10570 emit_operand(dst, src3, 1);
10571 emit_int8(imm8);
10572 }
10573
10574 void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
10575 assert(VM_Version::supports_gfni(), "");
10576 assert(VM_Version::supports_sse(), "");
10577 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
10578 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10579 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10580 }
10581
10582 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
10583 assert(VM_Version::supports_gfni(), "requires GFNI support");
10584 assert(VM_Version::supports_sse(), "");
10585 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10586 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10587 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10588 }
10589
10590 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10591 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
10592 assert(UseAVX >= 2, "");
10593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10594 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10595 emit_int16(0x58, (0xC0 | encode));
10596 }
10597
10598 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
10599 assert(VM_Version::supports_avx2(), "");
10600 assert(dst != xnoreg, "sanity");
10601 InstructionMark im(this);
10602 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10604 // swap src<->dst for encoding
10605 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10606 emit_int8(0x58);
10607 emit_operand(dst, src, 0);
10608 }
10609
10610 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10611 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
10612 assert(VM_Version::supports_avx2(), "");
10613 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10614 attributes.set_rex_vex_w_reverted();
10615 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10616 emit_int16(0x59, (0xC0 | encode));
10617 }
10618
10619 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
10620 assert(VM_Version::supports_avx2(), "");
10621 assert(dst != xnoreg, "sanity");
10622 InstructionMark im(this);
10623 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10624 attributes.set_rex_vex_w_reverted();
10625 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10626 // swap src<->dst for encoding
10627 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10628 emit_int8(0x59);
10629 emit_operand(dst, src, 0);
10630 }
10631
10632 void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) {
10633 assert(vector_len != Assembler::AVX_128bit, "");
10634 assert(VM_Version::supports_evex(), "");
10635 assert(dst != xnoreg, "sanity");
10636 InstructionMark im(this);
10637 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10638 attributes.set_rex_vex_w_reverted();
10639 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10640 // swap src<->dst for encoding
10641 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10642 emit_int8(0x5A);
10643 emit_operand(dst, src, 0);
10644 }
10645
10646 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
10647 assert(vector_len != Assembler::AVX_128bit, "");
10648 assert(VM_Version::supports_avx512dq(), "");
10649 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10650 attributes.set_rex_vex_w_reverted();
10651 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10652 emit_int16(0x5A, (0xC0 | encode));
10653 }
10654
10655 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
10656 assert(vector_len != Assembler::AVX_128bit, "");
10657 assert(VM_Version::supports_avx512dq(), "");
10658 assert(dst != xnoreg, "sanity");
10659 InstructionMark im(this);
10660 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10661 attributes.set_rex_vex_w_reverted();
10662 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
10663 // swap src<->dst for encoding
10664 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10665 emit_int8(0x5A);
10666 emit_operand(dst, src, 0);
10667 }
10668
10669 // scalar single/double precision replicate
10670
10671 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
10672 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
10673 assert(VM_Version::supports_avx2(), "");
10674 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10675 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10676 emit_int16(0x18, (0xC0 | encode));
10677 }
10678
10679 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
10680 assert(VM_Version::supports_avx(), "");
10681 assert(dst != xnoreg, "sanity");
10682 InstructionMark im(this);
10683 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10684 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10685 // swap src<->dst for encoding
10686 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10687 emit_int8(0x18);
10688 emit_operand(dst, src, 0);
10689 }
10690
10691 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
10692 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
10693 assert(VM_Version::supports_avx2(), "");
10694 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10695 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10696 attributes.set_rex_vex_w_reverted();
10697 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10698 emit_int16(0x19, (0xC0 | encode));
10699 }
10700
10701 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
10702 assert(VM_Version::supports_avx(), "");
10703 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10704 assert(dst != xnoreg, "sanity");
10705 InstructionMark im(this);
10706 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10707 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10708 attributes.set_rex_vex_w_reverted();
10709 // swap src<->dst for encoding
10710 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10711 emit_int8(0x19);
10712 emit_operand(dst, src, 0);
10713 }
10714
10715 void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
10716 assert(VM_Version::supports_avx(), "");
10717 assert(vector_len == AVX_256bit, "");
10718 assert(dst != xnoreg, "sanity");
10719 InstructionMark im(this);
10720 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10721 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10722 // swap src<->dst for encoding
10723 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10724 emit_int8(0x1A);
10725 emit_operand(dst, src, 0);
10726 }
10727
10728 // gpr source broadcast forms
10729
10730 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10731 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
10732 assert(VM_Version::supports_avx512bw(), "");
10733 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10734 attributes.set_is_evex_instruction();
10735 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10736 emit_int16(0x7A, (0xC0 | encode));
10737 }
10738
10739 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10740 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
10741 assert(VM_Version::supports_avx512bw(), "");
10742 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10743 attributes.set_is_evex_instruction();
10744 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10745 emit_int16(0x7B, (0xC0 | encode));
10746 }
10747
10748 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10749 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
10750 assert(VM_Version::supports_evex(), "");
10751 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10752 attributes.set_is_evex_instruction();
10753 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10754 emit_int16(0x7C, (0xC0 | encode));
10755 }
10756
10757 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10758 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
10759 assert(VM_Version::supports_evex(), "");
10760 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10761 attributes.set_is_evex_instruction();
10762 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10763 emit_int16(0x7C, (0xC0 | encode));
10764 }
10765
10766 void Assembler::vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10767 assert(VM_Version::supports_avx2(), "");
10768 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10769 assert(dst != xnoreg, "sanity");
10770 assert(src.isxmmindex(),"expected to be xmm index");
10771 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10772 InstructionMark im(this);
10773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10774 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10775 emit_int8((unsigned char)0x90);
10776 emit_operand(dst, src, 0);
10777 }
10778
10779 void Assembler::vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10780 assert(VM_Version::supports_avx2(), "");
10781 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10782 assert(dst != xnoreg, "sanity");
10783 assert(src.isxmmindex(),"expected to be xmm index");
10784 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10785 InstructionMark im(this);
10786 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10787 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10788 emit_int8((unsigned char)0x90);
10789 emit_operand(dst, src, 0);
10790 }
10791
10792 void Assembler::vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10793 assert(VM_Version::supports_avx2(), "");
10794 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10795 assert(dst != xnoreg, "sanity");
10796 assert(src.isxmmindex(),"expected to be xmm index");
10797 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10798 InstructionMark im(this);
10799 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10800 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10801 emit_int8((unsigned char)0x92);
10802 emit_operand(dst, src, 0);
10803 }
10804
10805 void Assembler::vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10806 assert(VM_Version::supports_avx2(), "");
10807 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10808 assert(dst != xnoreg, "sanity");
10809 assert(src.isxmmindex(),"expected to be xmm index");
10810 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10811 InstructionMark im(this);
10812 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
10813 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10814 emit_int8((unsigned char)0x92);
10815 emit_operand(dst, src, 0);
10816 }
10817 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10818 assert(VM_Version::supports_evex(), "");
10819 assert(dst != xnoreg, "sanity");
10820 assert(src.isxmmindex(),"expected to be xmm index");
10821 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10822 assert(mask != k0, "instruction will #UD if mask is in k0");
10823 InstructionMark im(this);
10824 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10825 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10826 attributes.reset_is_clear_context();
10827 attributes.set_embedded_opmask_register_specifier(mask);
10828 attributes.set_is_evex_instruction();
10829 // swap src<->dst for encoding
10830 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10831 emit_int8((unsigned char)0x90);
10832 emit_operand(dst, src, 0);
10833 }
10834
10835 void Assembler::evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10836 assert(VM_Version::supports_evex(), "");
10837 assert(dst != xnoreg, "sanity");
10838 assert(src.isxmmindex(),"expected to be xmm index");
10839 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10840 assert(mask != k0, "instruction will #UD if mask is in k0");
10841 InstructionMark im(this);
10842 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10843 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10844 attributes.reset_is_clear_context();
10845 attributes.set_embedded_opmask_register_specifier(mask);
10846 attributes.set_is_evex_instruction();
10847 // swap src<->dst for encoding
10848 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10849 emit_int8((unsigned char)0x90);
10850 emit_operand(dst, src, 0);
10851 }
10852
10853 void Assembler::evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10854 assert(VM_Version::supports_evex(), "");
10855 assert(dst != xnoreg, "sanity");
10856 assert(src.isxmmindex(),"expected to be xmm index");
10857 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10858 assert(mask != k0, "instruction will #UD if mask is in k0");
10859 InstructionMark im(this);
10860 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10861 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10862 attributes.reset_is_clear_context();
10863 attributes.set_embedded_opmask_register_specifier(mask);
10864 attributes.set_is_evex_instruction();
10865 // swap src<->dst for encoding
10866 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10867 emit_int8((unsigned char)0x92);
10868 emit_operand(dst, src, 0);
10869 }
10870
10871 void Assembler::evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10872 assert(VM_Version::supports_evex(), "");
10873 assert(dst != xnoreg, "sanity");
10874 assert(src.isxmmindex(),"expected to be xmm index");
10875 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10876 assert(mask != k0, "instruction will #UD if mask is in k0");
10877 InstructionMark im(this);
10878 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10879 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10880 attributes.reset_is_clear_context();
10881 attributes.set_embedded_opmask_register_specifier(mask);
10882 attributes.set_is_evex_instruction();
10883 // swap src<->dst for encoding
10884 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10885 emit_int8((unsigned char)0x92);
10886 emit_operand(dst, src, 0);
10887 }
10888
10889 void Assembler::evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10890 assert(VM_Version::supports_evex(), "");
10891 assert(mask != k0, "instruction will #UD if mask is in k0");
10892 InstructionMark im(this);
10893 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10894 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10895 attributes.reset_is_clear_context();
10896 attributes.set_embedded_opmask_register_specifier(mask);
10897 attributes.set_is_evex_instruction();
10898 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10899 emit_int8((unsigned char)0xA0);
10900 emit_operand(src, dst, 0);
10901 }
10902
10903 void Assembler::evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10904 assert(VM_Version::supports_evex(), "");
10905 assert(mask != k0, "instruction will #UD if mask is in k0");
10906 InstructionMark im(this);
10907 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10908 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10909 attributes.reset_is_clear_context();
10910 attributes.set_embedded_opmask_register_specifier(mask);
10911 attributes.set_is_evex_instruction();
10912 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10913 emit_int8((unsigned char)0xA0);
10914 emit_operand(src, dst, 0);
10915 }
10916
10917 void Assembler::evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10918 assert(VM_Version::supports_evex(), "");
10919 assert(mask != k0, "instruction will #UD if mask is in k0");
10920 InstructionMark im(this);
10921 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10922 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10923 attributes.reset_is_clear_context();
10924 attributes.set_embedded_opmask_register_specifier(mask);
10925 attributes.set_is_evex_instruction();
10926 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10927 emit_int8((unsigned char)0xA2);
10928 emit_operand(src, dst, 0);
10929 }
10930
10931 void Assembler::evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10932 assert(VM_Version::supports_evex(), "");
10933 assert(mask != k0, "instruction will #UD if mask is in k0");
10934 InstructionMark im(this);
10935 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10936 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10937 attributes.reset_is_clear_context();
10938 attributes.set_embedded_opmask_register_specifier(mask);
10939 attributes.set_is_evex_instruction();
10940 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10941 emit_int8((unsigned char)0xA2);
10942 emit_operand(src, dst, 0);
10943 }
10944 // Carry-Less Multiplication Quadword
10945 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
10946 assert(VM_Version::supports_clmul(), "");
10947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10948 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10949 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10950 }
10951
10952 // Carry-Less Multiplication Quadword
10953 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
10954 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
10955 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10956 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10957 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10958 }
10959
10960 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
10961 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
10962 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10963 attributes.set_is_evex_instruction();
10964 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10965 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10966 }
10967
10968 void Assembler::vzeroupper_uncached() {
10969 if (VM_Version::supports_vzeroupper()) {
10970 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10971 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
10972 emit_int8(0x77);
10973 }
10974 }
10975
10976 void Assembler::vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8) {
10977 // Encoding: EVEX.LIG.66.0F3A.W0 67 /r ib
10978 assert(VM_Version::supports_evex(), "");
10979 assert(VM_Version::supports_avx512dq(), "");
10980 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10981 attributes.set_is_evex_instruction();
10982 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10983 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10984 }
10985
10986 void Assembler::vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8) {
10987 // Encoding: EVEX.LIG.66.0F3A.W1 67 /r ib
10988 assert(VM_Version::supports_evex(), "");
10989 assert(VM_Version::supports_avx512dq(), "");
10990 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10991 attributes.set_is_evex_instruction();
10992 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10993 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10994 }
10995
10996 void Assembler::fld_x(Address adr) {
10997 InstructionMark im(this);
10998 emit_int8((unsigned char)0xDB);
10999 emit_operand32(rbp, adr, 0);
11000 }
11001
11002 void Assembler::fstp_x(Address adr) {
11003 InstructionMark im(this);
11004 emit_int8((unsigned char)0xDB);
11005 emit_operand32(rdi, adr, 0);
11006 }
11007
11008 void Assembler::emit_operand32(Register reg, Address adr, int post_addr_length) {
11009 assert(reg->encoding() < 8, "no extended registers");
11010 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
11011 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
11012 }
11013
11014 void Assembler::fld_d(Address adr) {
11015 InstructionMark im(this);
11016 emit_int8((unsigned char)0xDD);
11017 emit_operand32(rax, adr, 0);
11018 }
11019
11020 void Assembler::fprem() {
11021 emit_int16((unsigned char)0xD9, (unsigned char)0xF8);
11022 }
11023
11024 void Assembler::fnstsw_ax() {
11025 emit_int16((unsigned char)0xDF, (unsigned char)0xE0);
11026 }
11027
11028 void Assembler::fstp_d(Address adr) {
11029 InstructionMark im(this);
11030 emit_int8((unsigned char)0xDD);
11031 emit_operand32(rbx, adr, 0);
11032 }
11033
11034 void Assembler::fstp_d(int index) {
11035 emit_farith(0xDD, 0xD8, index);
11036 }
11037
11038 void Assembler::emit_farith(int b1, int b2, int i) {
11039 assert(isByte(b1) && isByte(b2), "wrong opcode");
11040 assert(0 <= i && i < 8, "illegal stack offset");
11041 emit_int16(b1, b2 + i);
11042 }
11043
11044 #ifndef _LP64
11045 // 32bit only pieces of the assembler
11046
11047 void Assembler::emms() {
11048 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
11049 emit_int16(0x0F, 0x77);
11050 }
11051
11052 void Assembler::vzeroupper() {
11053 vzeroupper_uncached();
11054 }
11055
11056 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
11057 // NO PREFIX AS NEVER 64BIT
11058 InstructionMark im(this);
11059 emit_int16((unsigned char)0x81, (0xF8 | src1->encoding()));
11060 emit_data(imm32, rspec, 0);
11061 }
11062
11063 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
11064 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
11065 InstructionMark im(this);
11066 emit_int8((unsigned char)0x81);
11067 emit_operand(rdi, src1, 4);
11068 emit_data(imm32, rspec, 0);
11069 }
11070
11071 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
11072 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
11073 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
11074 void Assembler::cmpxchg8(Address adr) {
11075 InstructionMark im(this);
11076 emit_int16(0x0F, (unsigned char)0xC7);
11077 emit_operand(rcx, adr, 0);
11078 }
11079
11080 void Assembler::decl(Register dst) {
11081 // Don't use it directly. Use MacroAssembler::decrementl() instead.
11082 emit_int8(0x48 | dst->encoding());
11083 }
11084
11085 // 64bit doesn't use the x87
11086
11087 void Assembler::fabs() {
11088 emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
11089 }
11090
11091 void Assembler::fadd(int i) {
11092 emit_farith(0xD8, 0xC0, i);
11093 }
11094
11095 void Assembler::fadd_d(Address src) {
11096 InstructionMark im(this);
11097 emit_int8((unsigned char)0xDC);
11098 emit_operand32(rax, src, 0);
11099 }
11100
11101 void Assembler::fadd_s(Address src) {
11102 InstructionMark im(this);
11103 emit_int8((unsigned char)0xD8);
11104 emit_operand32(rax, src, 0);
11105 }
11106
11107 void Assembler::fadda(int i) {
11108 emit_farith(0xDC, 0xC0, i);
11109 }
11110
11111 void Assembler::faddp(int i) {
11112 emit_farith(0xDE, 0xC0, i);
11113 }
11114
11115 void Assembler::fchs() {
11116 emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
11117 }
11118
11119 void Assembler::fcom(int i) {
11120 emit_farith(0xD8, 0xD0, i);
11121 }
11122
11123 void Assembler::fcomp(int i) {
11124 emit_farith(0xD8, 0xD8, i);
11125 }
11126
11127 void Assembler::fcomp_d(Address src) {
11128 InstructionMark im(this);
11129 emit_int8((unsigned char)0xDC);
11130 emit_operand32(rbx, src, 0);
11131 }
11132
11133 void Assembler::fcomp_s(Address src) {
11134 InstructionMark im(this);
11135 emit_int8((unsigned char)0xD8);
11136 emit_operand32(rbx, src, 0);
11137 }
11138
11139 void Assembler::fcompp() {
11140 emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
11141 }
11142
11143 void Assembler::fcos() {
11144 emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
11145 }
11146
11147 void Assembler::fdecstp() {
11148 emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
11149 }
11150
11151 void Assembler::fdiv(int i) {
11152 emit_farith(0xD8, 0xF0, i);
11153 }
11154
11155 void Assembler::fdiv_d(Address src) {
11156 InstructionMark im(this);
11157 emit_int8((unsigned char)0xDC);
11158 emit_operand32(rsi, src, 0);
11159 }
11160
11161 void Assembler::fdiv_s(Address src) {
11162 InstructionMark im(this);
11163 emit_int8((unsigned char)0xD8);
11164 emit_operand32(rsi, src, 0);
11165 }
11166
11167 void Assembler::fdiva(int i) {
11168 emit_farith(0xDC, 0xF8, i);
11169 }
11170
11171 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
11172 // is erroneous for some of the floating-point instructions below.
11173
11174 void Assembler::fdivp(int i) {
11175 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
11176 }
11177
11178 void Assembler::fdivr(int i) {
11179 emit_farith(0xD8, 0xF8, i);
11180 }
11181
11182 void Assembler::fdivr_d(Address src) {
11183 InstructionMark im(this);
11184 emit_int8((unsigned char)0xDC);
11185 emit_operand32(rdi, src, 0);
11186 }
11187
11188 void Assembler::fdivr_s(Address src) {
11189 InstructionMark im(this);
11190 emit_int8((unsigned char)0xD8);
11191 emit_operand32(rdi, src, 0);
11192 }
11193
11194 void Assembler::fdivra(int i) {
11195 emit_farith(0xDC, 0xF0, i);
11196 }
11197
11198 void Assembler::fdivrp(int i) {
11199 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
11200 }
11201
11202 void Assembler::ffree(int i) {
11203 emit_farith(0xDD, 0xC0, i);
11204 }
11205
11206 void Assembler::fild_d(Address adr) {
11207 InstructionMark im(this);
11208 emit_int8((unsigned char)0xDF);
11209 emit_operand32(rbp, adr, 0);
11210 }
11211
11212 void Assembler::fild_s(Address adr) {
11213 InstructionMark im(this);
11214 emit_int8((unsigned char)0xDB);
11215 emit_operand32(rax, adr, 0);
11216 }
11217
11218 void Assembler::fincstp() {
11219 emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
11220 }
11221
11222 void Assembler::finit() {
11223 emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
11224 }
11225
11226 void Assembler::fist_s(Address adr) {
11227 InstructionMark im(this);
11228 emit_int8((unsigned char)0xDB);
11229 emit_operand32(rdx, adr, 0);
11230 }
11231
11232 void Assembler::fistp_d(Address adr) {
11233 InstructionMark im(this);
11234 emit_int8((unsigned char)0xDF);
11235 emit_operand32(rdi, adr, 0);
11236 }
11237
11238 void Assembler::fistp_s(Address adr) {
11239 InstructionMark im(this);
11240 emit_int8((unsigned char)0xDB);
11241 emit_operand32(rbx, adr, 0);
11242 }
11243
11244 void Assembler::fld1() {
11245 emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
11246 }
11247
11248 void Assembler::fld_s(Address adr) {
11249 InstructionMark im(this);
11250 emit_int8((unsigned char)0xD9);
11251 emit_operand32(rax, adr, 0);
11252 }
11253
11254
11255 void Assembler::fld_s(int index) {
11256 emit_farith(0xD9, 0xC0, index);
11257 }
11258
11259 void Assembler::fldcw(Address src) {
11260 InstructionMark im(this);
11261 emit_int8((unsigned char)0xD9);
11262 emit_operand32(rbp, src, 0);
11263 }
11264
11265 void Assembler::fldenv(Address src) {
11266 InstructionMark im(this);
11267 emit_int8((unsigned char)0xD9);
11268 emit_operand32(rsp, src, 0);
11269 }
11270
11271 void Assembler::fldlg2() {
11272 emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
11273 }
11274
11275 void Assembler::fldln2() {
11276 emit_int16((unsigned char)0xD9, (unsigned char)0xED);
11277 }
11278
11279 void Assembler::fldz() {
11280 emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
11281 }
11282
11283 void Assembler::flog() {
11284 fldln2();
11285 fxch();
11286 fyl2x();
11287 }
11288
11289 void Assembler::flog10() {
11290 fldlg2();
11291 fxch();
11292 fyl2x();
11293 }
11294
11295 void Assembler::fmul(int i) {
11296 emit_farith(0xD8, 0xC8, i);
11297 }
11298
11299 void Assembler::fmul_d(Address src) {
11300 InstructionMark im(this);
11301 emit_int8((unsigned char)0xDC);
11302 emit_operand32(rcx, src, 0);
11303 }
11304
11305 void Assembler::fmul_s(Address src) {
11306 InstructionMark im(this);
11307 emit_int8((unsigned char)0xD8);
11308 emit_operand32(rcx, src, 0);
11309 }
11310
11311 void Assembler::fmula(int i) {
11312 emit_farith(0xDC, 0xC8, i);
11313 }
11314
11315 void Assembler::fmulp(int i) {
11316 emit_farith(0xDE, 0xC8, i);
11317 }
11318
11319 void Assembler::fnsave(Address dst) {
11320 InstructionMark im(this);
11321 emit_int8((unsigned char)0xDD);
11322 emit_operand32(rsi, dst, 0);
11323 }
11324
11325 void Assembler::fnstcw(Address src) {
11326 InstructionMark im(this);
11327 emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
11328 emit_operand32(rdi, src, 0);
11329 }
11330
11331 void Assembler::fprem1() {
11332 emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
11333 }
11334
11335 void Assembler::frstor(Address src) {
11336 InstructionMark im(this);
11337 emit_int8((unsigned char)0xDD);
11338 emit_operand32(rsp, src, 0);
11339 }
11340
11341 void Assembler::fsin() {
11342 emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
11343 }
11344
11345 void Assembler::fsqrt() {
11346 emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
11347 }
11348
11349 void Assembler::fst_d(Address adr) {
11350 InstructionMark im(this);
11351 emit_int8((unsigned char)0xDD);
11352 emit_operand32(rdx, adr, 0);
11353 }
11354
11355 void Assembler::fst_s(Address adr) {
11356 InstructionMark im(this);
11357 emit_int8((unsigned char)0xD9);
11358 emit_operand32(rdx, adr, 0);
11359 }
11360
11361 void Assembler::fstp_s(Address adr) {
11362 InstructionMark im(this);
11363 emit_int8((unsigned char)0xD9);
11364 emit_operand32(rbx, adr, 0);
11365 }
11366
11367 void Assembler::fsub(int i) {
11368 emit_farith(0xD8, 0xE0, i);
11369 }
11370
11371 void Assembler::fsub_d(Address src) {
11372 InstructionMark im(this);
11373 emit_int8((unsigned char)0xDC);
11374 emit_operand32(rsp, src, 0);
11375 }
11376
11377 void Assembler::fsub_s(Address src) {
11378 InstructionMark im(this);
11379 emit_int8((unsigned char)0xD8);
11380 emit_operand32(rsp, src, 0);
11381 }
11382
11383 void Assembler::fsuba(int i) {
11384 emit_farith(0xDC, 0xE8, i);
11385 }
11386
11387 void Assembler::fsubp(int i) {
11388 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
11389 }
11390
11391 void Assembler::fsubr(int i) {
11392 emit_farith(0xD8, 0xE8, i);
11393 }
11394
11395 void Assembler::fsubr_d(Address src) {
11396 InstructionMark im(this);
11397 emit_int8((unsigned char)0xDC);
11398 emit_operand32(rbp, src, 0);
11399 }
11400
11401 void Assembler::fsubr_s(Address src) {
11402 InstructionMark im(this);
11403 emit_int8((unsigned char)0xD8);
11404 emit_operand32(rbp, src, 0);
11405 }
11406
11407 void Assembler::fsubra(int i) {
11408 emit_farith(0xDC, 0xE0, i);
11409 }
11410
11411 void Assembler::fsubrp(int i) {
11412 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
11413 }
11414
11415 void Assembler::ftan() {
11416 emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
11417 }
11418
11419 void Assembler::ftst() {
11420 emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
11421 }
11422
11423 void Assembler::fucomi(int i) {
11424 // make sure the instruction is supported (introduced for P6, together with cmov)
11425 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11426 emit_farith(0xDB, 0xE8, i);
11427 }
11428
11429 void Assembler::fucomip(int i) {
11430 // make sure the instruction is supported (introduced for P6, together with cmov)
11431 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11432 emit_farith(0xDF, 0xE8, i);
11433 }
11434
11435 void Assembler::fwait() {
11436 emit_int8((unsigned char)0x9B);
11437 }
11438
11439 void Assembler::fxch(int i) {
11440 emit_farith(0xD9, 0xC8, i);
11441 }
11442
11443 void Assembler::fyl2x() {
11444 emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
11445 }
11446
11447 void Assembler::frndint() {
11448 emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
11449 }
11450
11451 void Assembler::f2xm1() {
11452 emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
11453 }
11454
11455 void Assembler::fldl2e() {
11456 emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
11457 }
11458 #endif // !_LP64
11459
11460 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
11461 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
11462 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
11463 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
11464
11465 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
11466 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11467 if (pre > 0) {
11468 emit_int8(simd_pre[pre]);
11469 }
11470 if (rex_w) {
11471 prefixq(adr, xreg);
11472 } else {
11473 prefix(adr, xreg);
11474 }
11475 if (opc > 0) {
11476 emit_int8(0x0F);
11477 int opc2 = simd_opc[opc];
11478 if (opc2 > 0) {
11479 emit_int8(opc2);
11480 }
11481 }
11482 }
11483
11484 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11485 if (pre > 0) {
11486 emit_int8(simd_pre[pre]);
11487 }
11488 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
11489 if (opc > 0) {
11490 emit_int8(0x0F);
11491 int opc2 = simd_opc[opc];
11492 if (opc2 > 0) {
11493 emit_int8(opc2);
11494 }
11495 }
11496 return encode;
11497 }
11498
11499
11500 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
11501 int vector_len = _attributes->get_vector_len();
11502 bool vex_w = _attributes->is_rex_vex_w();
11503 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
11504 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
11505 byte1 = (~byte1) & 0xE0;
11506 byte1 |= opc;
11507
11508 int byte2 = ((~nds_enc) & 0xf) << 3;
11509 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
11510
11511 emit_int24((unsigned char)VEX_3bytes, byte1, byte2);
11512 } else {
11513 int byte1 = vex_r ? VEX_R : 0;
11514 byte1 = (~byte1) & 0x80;
11515 byte1 |= ((~nds_enc) & 0xf) << 3;
11516 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
11517 emit_int16((unsigned char)VEX_2bytes, byte1);
11518 }
11519 }
11520
11521 // This is a 4 byte encoding
11522 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
11523 // EVEX 0x62 prefix
11524 // byte1 = EVEX_4bytes;
11525
11526 bool vex_w = _attributes->is_rex_vex_w();
11527 int evex_encoding = (vex_w ? VEX_W : 0);
11528 // EVEX.b is not currently used for broadcast of single element or data rounding modes
11529 _attributes->set_evex_encoding(evex_encoding);
11530
11531 // P0: byte 2, initialized to RXBR`00mm
11532 // instead of not'd
11533 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
11534 byte2 = (~byte2) & 0xF0;
11535 // confine opc opcode extensions in mm bits to lower two bits
11536 // of form {0F, 0F_38, 0F_3A}
11537 byte2 |= opc;
11538
11539 // P1: byte 3 as Wvvvv1pp
11540 int byte3 = ((~nds_enc) & 0xf) << 3;
11541 // p[10] is always 1
11542 byte3 |= EVEX_F;
11543 byte3 |= (vex_w & 1) << 7;
11544 // confine pre opcode extensions in pp bits to lower two bits
11545 // of form {66, F3, F2}
11546 byte3 |= pre;
11547
11548 // P2: byte 4 as zL'Lbv'aaa
11549 // kregs are implemented in the low 3 bits as aaa
11550 int byte4 = (_attributes->is_no_reg_mask()) ?
11551 0 :
11552 _attributes->get_embedded_opmask_register_specifier();
11553 // EVEX.v` for extending EVEX.vvvv or VIDX
11554 byte4 |= (evex_v ? 0: EVEX_V);
11555 // third EXEC.b for broadcast actions
11556 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
11557 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
11558 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
11559 // last is EVEX.z for zero/merge actions
11560 if (_attributes->is_no_reg_mask() == false &&
11561 _attributes->get_embedded_opmask_register_specifier() != 0) {
11562 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
11563 }
11564
11565 emit_int32(EVEX_4bytes, byte2, byte3, byte4);
11566 }
11567
11568 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11569 bool vex_r = (xreg_enc & 8) == 8;
11570 bool vex_b = adr.base_needs_rex();
11571 bool vex_x;
11572 if (adr.isxmmindex()) {
11573 vex_x = adr.xmmindex_needs_rex();
11574 } else {
11575 vex_x = adr.index_needs_rex();
11576 }
11577 set_attributes(attributes);
11578
11579 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11580 // is allowed in legacy mode and has resources which will fit in it.
11581 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11582 if (!attributes->is_legacy_mode()) {
11583 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11584 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
11585 attributes->set_is_legacy_mode();
11586 }
11587 }
11588 }
11589
11590 if (UseAVX > 2) {
11591 assert(((!attributes->uses_vl()) ||
11592 (attributes->get_vector_len() == AVX_512bit) ||
11593 (!_legacy_mode_vl) ||
11594 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11595 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11596 }
11597
11598 clear_managed();
11599 if (UseAVX > 2 && !attributes->is_legacy_mode())
11600 {
11601 bool evex_r = (xreg_enc >= 16);
11602 bool evex_v;
11603 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
11604 if (adr.isxmmindex()) {
11605 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
11606 } else {
11607 evex_v = (nds_enc >= 16);
11608 }
11609 attributes->set_is_evex_instruction();
11610 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11611 } else {
11612 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11613 attributes->set_rex_vex_w(false);
11614 }
11615 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11616 }
11617 }
11618
11619 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11620 bool vex_r = (dst_enc & 8) == 8;
11621 bool vex_b = (src_enc & 8) == 8;
11622 bool vex_x = false;
11623 set_attributes(attributes);
11624
11625 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11626 // is allowed in legacy mode and has resources which will fit in it.
11627 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11628 if (!attributes->is_legacy_mode()) {
11629 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11630 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
11631 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
11632 attributes->set_is_legacy_mode();
11633 }
11634 }
11635 }
11636
11637 if (UseAVX > 2) {
11638 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
11639 // Instruction with uses_vl true are vector instructions
11640 // All the vector instructions with AVX_512bit length can have legacy_mode as false
11641 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
11642 // Rest all should have legacy_mode set as true
11643 assert(((!attributes->uses_vl()) ||
11644 (attributes->get_vector_len() == AVX_512bit) ||
11645 (!_legacy_mode_vl) ||
11646 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11647 // Instruction with legacy_mode true should have dst, nds and src < 15
11648 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11649 }
11650
11651 clear_managed();
11652 if (UseAVX > 2 && !attributes->is_legacy_mode())
11653 {
11654 bool evex_r = (dst_enc >= 16);
11655 bool evex_v = (nds_enc >= 16);
11656 // can use vex_x as bank extender on rm encoding
11657 vex_x = (src_enc >= 16);
11658 attributes->set_is_evex_instruction();
11659 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11660 } else {
11661 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11662 attributes->set_rex_vex_w(false);
11663 }
11664 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11665 }
11666
11667 // return modrm byte components for operands
11668 return (((dst_enc & 7) << 3) | (src_enc & 7));
11669 }
11670
11671
11672 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
11673 VexOpcode opc, InstructionAttr *attributes) {
11674 if (UseAVX > 0) {
11675 int xreg_enc = xreg->encoding();
11676 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11677 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
11678 } else {
11679 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
11680 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
11681 }
11682 }
11683
11684 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
11685 VexOpcode opc, InstructionAttr *attributes) {
11686 int dst_enc = dst->encoding();
11687 int src_enc = src->encoding();
11688 if (UseAVX > 0) {
11689 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11690 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
11691 } else {
11692 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
11693 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
11694 }
11695 }
11696
11697 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11698 assert(VM_Version::supports_avx(), "");
11699 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11700 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11701 emit_int16(0x5F, (0xC0 | encode));
11702 }
11703
11704 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11705 assert(VM_Version::supports_avx(), "");
11706 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11707 attributes.set_rex_vex_w_reverted();
11708 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11709 emit_int16(0x5F, (0xC0 | encode));
11710 }
11711
11712 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11713 assert(VM_Version::supports_avx(), "");
11714 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11715 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11716 emit_int16(0x5D, (0xC0 | encode));
11717 }
11718
11719 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11720 assert(VM_Version::supports_avx(), "");
11721 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11722 attributes.set_rex_vex_w_reverted();
11723 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11724 emit_int16(0x5D, (0xC0 | encode));
11725 }
11726
11727 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
11728 assert(VM_Version::supports_avx(), "");
11729 assert(vector_len <= AVX_256bit, "");
11730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11731 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11732 emit_int24((unsigned char)0xC2, (0xC0 | encode), (0xF & cop));
11733 }
11734
11735 void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11736 assert(VM_Version::supports_avx(), "");
11737 assert(vector_len <= AVX_256bit, "");
11738 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11739 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11740 int src2_enc = src2->encoding();
11741 emit_int24(0x4C, (0xC0 | encode), (0xF0 & src2_enc << 4));
11742 }
11743
11744 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11745 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11746 assert(vector_len <= AVX_256bit, "");
11747 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11748 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11749 int src2_enc = src2->encoding();
11750 emit_int24(0x4B, (0xC0 | encode), (0xF0 & src2_enc << 4));
11751 }
11752
11753 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11754 assert(VM_Version::supports_avx2(), "");
11755 assert(vector_len <= AVX_256bit, "");
11756 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11757 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11758 emit_int24(0x02, (0xC0 | encode), (unsigned char)imm8);
11759 }
11760
11761 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
11762 assert(VM_Version::supports_avx(), "");
11763 assert(vector_len <= AVX_256bit, "");
11764 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11765 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11766 emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison);
11767 }
11768
11769 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11770 ComparisonPredicateFP comparison, int vector_len) {
11771 assert(VM_Version::supports_evex(), "");
11772 // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
11773 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11774 attributes.set_is_evex_instruction();
11775 attributes.set_embedded_opmask_register_specifier(mask);
11776 attributes.reset_is_clear_context();
11777 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11778 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11779 }
11780
11781 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11782 ComparisonPredicateFP comparison, int vector_len) {
11783 assert(VM_Version::supports_evex(), "");
11784 // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
11785 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11786 attributes.set_is_evex_instruction();
11787 attributes.set_embedded_opmask_register_specifier(mask);
11788 attributes.reset_is_clear_context();
11789 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11790 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11791 }
11792
11793 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
11794 assert(VM_Version::supports_sse4_1(), "");
11795 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11796 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11797 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11798 emit_int16(0x14, (0xC0 | encode));
11799 }
11800
11801 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
11802 assert(VM_Version::supports_sse4_1(), "");
11803 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11805 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11806 emit_int16(0x15, (0xC0 | encode));
11807 }
11808
11809 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
11810 assert(VM_Version::supports_sse4_1(), "");
11811 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11812 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11813 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11814 emit_int16(0x10, (0xC0 | encode));
11815 }
11816
11817 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11818 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11819 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11820 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11821 int src2_enc = src2->encoding();
11822 emit_int24(0x4A, (0xC0 | encode), (0xF0 & src2_enc << 4));
11823 }
11824
11825 void Assembler::vblendps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11826 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11827 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11828 emit_int24(0x0C, (0xC0 | encode), imm8);
11829 }
11830
11831 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11832 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11833 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11834 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11835 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11836 emit_int16(0x64, (0xC0 | encode));
11837 }
11838
11839 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11840 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11841 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11842 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11843 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11844 emit_int16(0x65, (0xC0 | encode));
11845 }
11846
11847 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11848 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11849 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11850 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11851 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11852 emit_int16(0x66, (0xC0 | encode));
11853 }
11854
11855 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11856 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11857 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11858 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11859 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11860 emit_int16(0x37, (0xC0 | encode));
11861 }
11862
11863 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11864 int comparison, bool is_signed, int vector_len) {
11865 assert(VM_Version::supports_evex(), "");
11866 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11867 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11869 attributes.set_is_evex_instruction();
11870 attributes.set_embedded_opmask_register_specifier(mask);
11871 attributes.reset_is_clear_context();
11872 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11873 int opcode = is_signed ? 0x1F : 0x1E;
11874 emit_int24(opcode, (0xC0 | encode), comparison);
11875 }
11876
11877 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11878 int comparison, bool is_signed, int vector_len) {
11879 assert(VM_Version::supports_evex(), "");
11880 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11881 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11882 InstructionMark im(this);
11883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11884 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11885 attributes.set_is_evex_instruction();
11886 attributes.set_embedded_opmask_register_specifier(mask);
11887 attributes.reset_is_clear_context();
11888 int dst_enc = kdst->encoding();
11889 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11890 int opcode = is_signed ? 0x1F : 0x1E;
11891 emit_int8((unsigned char)opcode);
11892 emit_operand(as_Register(dst_enc), src, 1);
11893 emit_int8((unsigned char)comparison);
11894 }
11895
11896 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11897 int comparison, bool is_signed, int vector_len) {
11898 assert(VM_Version::supports_evex(), "");
11899 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11900 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11901 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11902 attributes.set_is_evex_instruction();
11903 attributes.set_embedded_opmask_register_specifier(mask);
11904 attributes.reset_is_clear_context();
11905 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11906 int opcode = is_signed ? 0x1F : 0x1E;
11907 emit_int24(opcode, (0xC0 | encode), comparison);
11908 }
11909
11910 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11911 int comparison, bool is_signed, int vector_len) {
11912 assert(VM_Version::supports_evex(), "");
11913 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11914 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11915 InstructionMark im(this);
11916 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11917 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11918 attributes.set_is_evex_instruction();
11919 attributes.set_embedded_opmask_register_specifier(mask);
11920 attributes.reset_is_clear_context();
11921 int dst_enc = kdst->encoding();
11922 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11923 int opcode = is_signed ? 0x1F : 0x1E;
11924 emit_int8((unsigned char)opcode);
11925 emit_operand(as_Register(dst_enc), src, 1);
11926 emit_int8((unsigned char)comparison);
11927 }
11928
11929 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11930 int comparison, bool is_signed, int vector_len) {
11931 assert(VM_Version::supports_evex(), "");
11932 assert(VM_Version::supports_avx512bw(), "");
11933 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11934 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11935 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11936 attributes.set_is_evex_instruction();
11937 attributes.set_embedded_opmask_register_specifier(mask);
11938 attributes.reset_is_clear_context();
11939 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11940 int opcode = is_signed ? 0x3F : 0x3E;
11941 emit_int24(opcode, (0xC0 | encode), comparison);
11942 }
11943
11944 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11945 int comparison, bool is_signed, int vector_len) {
11946 assert(VM_Version::supports_evex(), "");
11947 assert(VM_Version::supports_avx512bw(), "");
11948 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11949 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11950 InstructionMark im(this);
11951 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11952 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11953 attributes.set_is_evex_instruction();
11954 attributes.set_embedded_opmask_register_specifier(mask);
11955 attributes.reset_is_clear_context();
11956 int dst_enc = kdst->encoding();
11957 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11958 int opcode = is_signed ? 0x3F : 0x3E;
11959 emit_int8((unsigned char)opcode);
11960 emit_operand(as_Register(dst_enc), src, 1);
11961 emit_int8((unsigned char)comparison);
11962 }
11963
11964 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11965 int comparison, bool is_signed, int vector_len) {
11966 assert(VM_Version::supports_evex(), "");
11967 assert(VM_Version::supports_avx512bw(), "");
11968 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11969 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11970 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11971 attributes.set_is_evex_instruction();
11972 attributes.set_embedded_opmask_register_specifier(mask);
11973 attributes.reset_is_clear_context();
11974 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11975 int opcode = is_signed ? 0x3F : 0x3E;
11976 emit_int24(opcode, (0xC0 | encode), comparison);
11977 }
11978
11979 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11980 int comparison, bool is_signed, int vector_len) {
11981 assert(VM_Version::supports_evex(), "");
11982 assert(VM_Version::supports_avx512bw(), "");
11983 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11984 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11985 InstructionMark im(this);
11986 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11987 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11988 attributes.set_is_evex_instruction();
11989 attributes.set_embedded_opmask_register_specifier(mask);
11990 attributes.reset_is_clear_context();
11991 int dst_enc = kdst->encoding();
11992 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11993 int opcode = is_signed ? 0x3F : 0x3E;
11994 emit_int8((unsigned char)opcode);
11995 emit_operand(as_Register(dst_enc), src, 1);
11996 emit_int8((unsigned char)comparison);
11997 }
11998
11999 void Assembler::evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12000 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12001 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12002 attributes.set_is_evex_instruction();
12003 attributes.set_embedded_opmask_register_specifier(mask);
12004 if (merge) {
12005 attributes.reset_is_clear_context();
12006 }
12007 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12008 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12009 }
12010
12011 void Assembler::evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12012 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12013 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12014 attributes.set_is_evex_instruction();
12015 attributes.set_embedded_opmask_register_specifier(mask);
12016 if (merge) {
12017 attributes.reset_is_clear_context();
12018 }
12019 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12020 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12021 }
12022
12023 void Assembler::evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12024 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12025 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12026 attributes.set_is_evex_instruction();
12027 attributes.set_embedded_opmask_register_specifier(mask);
12028 if (merge) {
12029 attributes.reset_is_clear_context();
12030 }
12031 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12032 emit_int16(0x14, (0xC0 | encode));
12033 }
12034
12035 void Assembler::evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12036 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12037 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12038 attributes.set_is_evex_instruction();
12039 attributes.set_embedded_opmask_register_specifier(mask);
12040 if (merge) {
12041 attributes.reset_is_clear_context();
12042 }
12043 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12044 emit_int16(0x14, (0xC0 | encode));
12045 }
12046
12047 void Assembler::evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12048 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12049 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12050 attributes.set_is_evex_instruction();
12051 attributes.set_embedded_opmask_register_specifier(mask);
12052 if (merge) {
12053 attributes.reset_is_clear_context();
12054 }
12055 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12056 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12057 }
12058
12059 void Assembler::evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12060 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12061 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12062 attributes.set_is_evex_instruction();
12063 attributes.set_embedded_opmask_register_specifier(mask);
12064 if (merge) {
12065 attributes.reset_is_clear_context();
12066 }
12067 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12068 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12069 }
12070
12071 void Assembler::evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12072 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12073 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12074 attributes.set_is_evex_instruction();
12075 attributes.set_embedded_opmask_register_specifier(mask);
12076 if (merge) {
12077 attributes.reset_is_clear_context();
12078 }
12079 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12080 emit_int16(0x15, (0xC0 | encode));
12081 }
12082
12083 void Assembler::evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12084 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12085 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12086 attributes.set_is_evex_instruction();
12087 attributes.set_embedded_opmask_register_specifier(mask);
12088 if (merge) {
12089 attributes.reset_is_clear_context();
12090 }
12091 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12092 emit_int16(0x15, (0xC0 | encode));
12093 }
12094
12095 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
12096 assert(VM_Version::supports_avx(), "");
12097 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12098 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
12099 int mask_enc = mask->encoding();
12100 emit_int24(0x4C, (0xC0 | encode), 0xF0 & mask_enc << 4);
12101 }
12102
12103 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12104 assert(VM_Version::supports_evex(), "");
12105 // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
12106 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12107 attributes.set_is_evex_instruction();
12108 attributes.set_embedded_opmask_register_specifier(mask);
12109 if (merge) {
12110 attributes.reset_is_clear_context();
12111 }
12112 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12113 emit_int16(0x65, (0xC0 | encode));
12114 }
12115
12116 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12117 assert(VM_Version::supports_evex(), "");
12118 // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
12119 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12120 attributes.set_is_evex_instruction();
12121 attributes.set_embedded_opmask_register_specifier(mask);
12122 if (merge) {
12123 attributes.reset_is_clear_context();
12124 }
12125 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12126 emit_int16(0x65, (0xC0 | encode));
12127 }
12128
12129 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12130 assert(VM_Version::supports_evex(), "");
12131 assert(VM_Version::supports_avx512bw(), "");
12132 // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
12133 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12134 attributes.set_is_evex_instruction();
12135 attributes.set_embedded_opmask_register_specifier(mask);
12136 if (merge) {
12137 attributes.reset_is_clear_context();
12138 }
12139 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12140 emit_int16(0x66, (0xC0 | encode));
12141 }
12142
12143 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12144 assert(VM_Version::supports_evex(), "");
12145 assert(VM_Version::supports_avx512bw(), "");
12146 // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
12147 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12148 attributes.set_is_evex_instruction();
12149 attributes.set_embedded_opmask_register_specifier(mask);
12150 if (merge) {
12151 attributes.reset_is_clear_context();
12152 }
12153 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12154 emit_int16(0x66, (0xC0 | encode));
12155 }
12156
12157 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12158 assert(VM_Version::supports_evex(), "");
12159 //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
12160 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12161 attributes.set_is_evex_instruction();
12162 attributes.set_embedded_opmask_register_specifier(mask);
12163 if (merge) {
12164 attributes.reset_is_clear_context();
12165 }
12166 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12167 emit_int16(0x64, (0xC0 | encode));
12168 }
12169
12170 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12171 assert(VM_Version::supports_evex(), "");
12172 //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
12173 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12174 attributes.set_is_evex_instruction();
12175 attributes.set_embedded_opmask_register_specifier(mask);
12176 if (merge) {
12177 attributes.reset_is_clear_context();
12178 }
12179 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12180 emit_int16(0x64, (0xC0 | encode));
12181 }
12182
12183 void Assembler::bzhiq(Register dst, Register src1, Register src2) {
12184 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12185 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12186 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12187 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12188 }
12189
12190 void Assembler::pextl(Register dst, Register src1, Register src2) {
12191 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12192 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12193 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12194 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12195 }
12196
12197 void Assembler::pdepl(Register dst, Register src1, Register src2) {
12198 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12199 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12200 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12201 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12202 }
12203
12204 void Assembler::pextq(Register dst, Register src1, Register src2) {
12205 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12206 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12207 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12208 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12209 }
12210
12211 void Assembler::pdepq(Register dst, Register src1, Register src2) {
12212 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12213 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12214 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12215 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12216 }
12217
12218 void Assembler::pextl(Register dst, Register src1, Address src2) {
12219 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12220 InstructionMark im(this);
12221 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12222 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12223 emit_int8((unsigned char)0xF5);
12224 emit_operand(dst, src2, 0);
12225 }
12226
12227 void Assembler::pdepl(Register dst, Register src1, Address src2) {
12228 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12229 InstructionMark im(this);
12230 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12231 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12232 emit_int8((unsigned char)0xF5);
12233 emit_operand(dst, src2, 0);
12234 }
12235
12236 void Assembler::pextq(Register dst, Register src1, Address src2) {
12237 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12238 InstructionMark im(this);
12239 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12240 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12241 emit_int8((unsigned char)0xF5);
12242 emit_operand(dst, src2, 0);
12243 }
12244
12245 void Assembler::pdepq(Register dst, Register src1, Address src2) {
12246 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12247 InstructionMark im(this);
12248 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12249 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12250 emit_int8((unsigned char)0xF5);
12251 emit_operand(dst, src2, 0);
12252 }
12253
12254 void Assembler::sarxl(Register dst, Register src1, Register src2) {
12255 assert(VM_Version::supports_bmi2(), "");
12256 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12257 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12258 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12259 }
12260
12261 void Assembler::sarxl(Register dst, Address src1, Register src2) {
12262 assert(VM_Version::supports_bmi2(), "");
12263 InstructionMark im(this);
12264 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12265 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12266 emit_int8((unsigned char)0xF7);
12267 emit_operand(dst, src1, 0);
12268 }
12269
12270 void Assembler::sarxq(Register dst, Register src1, Register src2) {
12271 assert(VM_Version::supports_bmi2(), "");
12272 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12273 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12274 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12275 }
12276
12277 void Assembler::sarxq(Register dst, Address src1, Register src2) {
12278 assert(VM_Version::supports_bmi2(), "");
12279 InstructionMark im(this);
12280 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12281 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12282 emit_int8((unsigned char)0xF7);
12283 emit_operand(dst, src1, 0);
12284 }
12285
12286 void Assembler::shlxl(Register dst, Register src1, Register src2) {
12287 assert(VM_Version::supports_bmi2(), "");
12288 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12289 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12290 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12291 }
12292
12293 void Assembler::shlxl(Register dst, Address src1, Register src2) {
12294 assert(VM_Version::supports_bmi2(), "");
12295 InstructionMark im(this);
12296 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12297 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12298 emit_int8((unsigned char)0xF7);
12299 emit_operand(dst, src1, 0);
12300 }
12301
12302 void Assembler::shlxq(Register dst, Register src1, Register src2) {
12303 assert(VM_Version::supports_bmi2(), "");
12304 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12305 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12306 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12307 }
12308
12309 void Assembler::shlxq(Register dst, Address src1, Register src2) {
12310 assert(VM_Version::supports_bmi2(), "");
12311 InstructionMark im(this);
12312 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12313 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12314 emit_int8((unsigned char)0xF7);
12315 emit_operand(dst, src1, 0);
12316 }
12317
12318 void Assembler::shrxl(Register dst, Register src1, Register src2) {
12319 assert(VM_Version::supports_bmi2(), "");
12320 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12321 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12322 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12323 }
12324
12325 void Assembler::shrxl(Register dst, Address src1, Register src2) {
12326 assert(VM_Version::supports_bmi2(), "");
12327 InstructionMark im(this);
12328 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12329 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12330 emit_int8((unsigned char)0xF7);
12331 emit_operand(dst, src1, 0);
12332 }
12333
12334 void Assembler::shrxq(Register dst, Register src1, Register src2) {
12335 assert(VM_Version::supports_bmi2(), "");
12336 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12337 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12338 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12339 }
12340
12341 void Assembler::shrxq(Register dst, Address src1, Register src2) {
12342 assert(VM_Version::supports_bmi2(), "");
12343 InstructionMark im(this);
12344 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12345 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12346 emit_int8((unsigned char)0xF7);
12347 emit_operand(dst, src1, 0);
12348 }
12349
12350 void Assembler::evpmovq2m(KRegister dst, XMMRegister src, int vector_len) {
12351 assert(VM_Version::supports_avx512vldq(), "");
12352 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12353 attributes.set_is_evex_instruction();
12354 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12355 emit_int16(0x39, (0xC0 | encode));
12356 }
12357
12358 void Assembler::evpmovd2m(KRegister dst, XMMRegister src, int vector_len) {
12359 assert(VM_Version::supports_avx512vldq(), "");
12360 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12361 attributes.set_is_evex_instruction();
12362 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12363 emit_int16(0x39, (0xC0 | encode));
12364 }
12365
12366 void Assembler::evpmovw2m(KRegister dst, XMMRegister src, int vector_len) {
12367 assert(VM_Version::supports_avx512vlbw(), "");
12368 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12369 attributes.set_is_evex_instruction();
12370 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12371 emit_int16(0x29, (0xC0 | encode));
12372 }
12373
12374 void Assembler::evpmovb2m(KRegister dst, XMMRegister src, int vector_len) {
12375 assert(VM_Version::supports_avx512vlbw(), "");
12376 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12377 attributes.set_is_evex_instruction();
12378 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12379 emit_int16(0x29, (0xC0 | encode));
12380 }
12381
12382 void Assembler::evpmovm2q(XMMRegister dst, KRegister src, int vector_len) {
12383 assert(VM_Version::supports_avx512vldq(), "");
12384 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12385 attributes.set_is_evex_instruction();
12386 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12387 emit_int16(0x38, (0xC0 | encode));
12388 }
12389
12390 void Assembler::evpmovm2d(XMMRegister dst, KRegister src, int vector_len) {
12391 assert(VM_Version::supports_avx512vldq(), "");
12392 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12393 attributes.set_is_evex_instruction();
12394 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12395 emit_int16(0x38, (0xC0 | encode));
12396 }
12397
12398 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
12399 assert(VM_Version::supports_avx512vlbw(), "");
12400 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12401 attributes.set_is_evex_instruction();
12402 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12403 emit_int16(0x28, (0xC0 | encode));
12404 }
12405
12406 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
12407 assert(VM_Version::supports_avx512vlbw(), "");
12408 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12409 attributes.set_is_evex_instruction();
12410 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12411 emit_int16(0x28, (0xC0 | encode));
12412 }
12413
12414 void Assembler::evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12415 assert(VM_Version::supports_avx512_vbmi2(), "");
12416 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12417 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12418 attributes.set_embedded_opmask_register_specifier(mask);
12419 attributes.set_is_evex_instruction();
12420 if (merge) {
12421 attributes.reset_is_clear_context();
12422 }
12423 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12424 emit_int16((unsigned char)0x63, (0xC0 | encode));
12425 }
12426
12427 void Assembler::evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12428 assert(VM_Version::supports_avx512_vbmi2(), "");
12429 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12430 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12431 attributes.set_embedded_opmask_register_specifier(mask);
12432 attributes.set_is_evex_instruction();
12433 if (merge) {
12434 attributes.reset_is_clear_context();
12435 }
12436 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12437 emit_int16((unsigned char)0x63, (0xC0 | encode));
12438 }
12439
12440 void Assembler::evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12441 assert(VM_Version::supports_evex(), "");
12442 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12443 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12444 attributes.set_embedded_opmask_register_specifier(mask);
12445 attributes.set_is_evex_instruction();
12446 if (merge) {
12447 attributes.reset_is_clear_context();
12448 }
12449 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12450 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12451 }
12452
12453 void Assembler::evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12454 assert(VM_Version::supports_evex(), "");
12455 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12456 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12457 attributes.set_embedded_opmask_register_specifier(mask);
12458 attributes.set_is_evex_instruction();
12459 if (merge) {
12460 attributes.reset_is_clear_context();
12461 }
12462 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12463 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12464 }
12465
12466 void Assembler::evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12467 assert(VM_Version::supports_evex(), "");
12468 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12469 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12470 attributes.set_embedded_opmask_register_specifier(mask);
12471 attributes.set_is_evex_instruction();
12472 if (merge) {
12473 attributes.reset_is_clear_context();
12474 }
12475 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12476 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12477 }
12478
12479 void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12480 assert(VM_Version::supports_evex(), "");
12481 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12482 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12483 attributes.set_embedded_opmask_register_specifier(mask);
12484 attributes.set_is_evex_instruction();
12485 if (merge) {
12486 attributes.reset_is_clear_context();
12487 }
12488 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12489 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12490 }
12491
12492 #ifndef _LP64
12493
12494 void Assembler::incl(Register dst) {
12495 // Don't use it directly. Use MacroAssembler::incrementl() instead.
12496 emit_int8(0x40 | dst->encoding());
12497 }
12498
12499 void Assembler::lea(Register dst, Address src) {
12500 leal(dst, src);
12501 }
12502
12503 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
12504 InstructionMark im(this);
12505 emit_int8((unsigned char)0xC7);
12506 emit_operand(rax, dst, 4);
12507 emit_data((int)imm32, rspec, 0);
12508 }
12509
12510 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
12511 InstructionMark im(this);
12512 int encode = prefix_and_encode(dst->encoding());
12513 emit_int8((0xB8 | encode));
12514 emit_data((int)imm32, rspec, 0);
12515 }
12516
12517 void Assembler::popa() { // 32bit
12518 emit_int8(0x61);
12519 }
12520
12521 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
12522 InstructionMark im(this);
12523 emit_int8(0x68);
12524 emit_data(imm32, rspec, 0);
12525 }
12526
12527 void Assembler::pusha() { // 32bit
12528 emit_int8(0x60);
12529 }
12530
12531 #else // LP64
12532
12533 // 64bit only pieces of the assembler
12534
12535 // This should only be used by 64bit instructions that can use rip-relative
12536 // it cannot be used by instructions that want an immediate value.
12537
12538 // Determine whether an address is always reachable in rip-relative addressing mode
12539 // when accessed from the code cache.
12540 static bool is_always_reachable(address target, relocInfo::relocType reloc_type) {
12541 switch (reloc_type) {
12542 // This should be rip-relative and easily reachable.
12543 case relocInfo::internal_word_type: {
12544 return true;
12545 }
12546 // This should be rip-relative within the code cache and easily
12547 // reachable until we get huge code caches. (At which point
12548 // IC code is going to have issues).
12549 case relocInfo::virtual_call_type:
12550 case relocInfo::opt_virtual_call_type:
12551 case relocInfo::static_call_type:
12552 case relocInfo::static_stub_type: {
12553 return true;
12554 }
12555 case relocInfo::runtime_call_type:
12556 case relocInfo::external_word_type:
12557 case relocInfo::poll_return_type: // these are really external_word but need special
12558 case relocInfo::poll_type: { // relocs to identify them
12559 return CodeCache::contains(target);
12560 }
12561 default: {
12562 return false;
12563 }
12564 }
12565 }
12566
12567 // Determine whether an address is reachable in rip-relative addressing mode from the code cache.
12568 static bool is_reachable(address target, relocInfo::relocType reloc_type) {
12569 if (is_always_reachable(target, reloc_type)) {
12570 return true;
12571 }
12572 switch (reloc_type) {
12573 // None will force a 64bit literal to the code stream. Likely a placeholder
12574 // for something that will be patched later and we need to certain it will
12575 // always be reachable.
12576 case relocInfo::none: {
12577 return false;
12578 }
12579 case relocInfo::runtime_call_type:
12580 case relocInfo::external_word_type:
12581 case relocInfo::poll_return_type: // these are really external_word but need special
12582 case relocInfo::poll_type: { // relocs to identify them
12583 assert(!CodeCache::contains(target), "always reachable");
12584 if (ForceUnreachable) {
12585 return false; // stress the correction code
12586 }
12587 // For external_word_type/runtime_call_type if it is reachable from where we
12588 // are now (possibly a temp buffer) and where we might end up
12589 // anywhere in the code cache then we are always reachable.
12590 // This would have to change if we ever save/restore shared code to be more pessimistic.
12591 // Code buffer has to be allocated in the code cache, so check against
12592 // code cache boundaries cover that case.
12593 //
12594 // In rip-relative addressing mode, an effective address is formed by adding displacement
12595 // to the 64-bit RIP of the next instruction which is not known yet. Considering target address
12596 // is guaranteed to be outside of the code cache, checking against code cache boundaries is enough
12597 // to account for that.
12598 return Assembler::is_simm32(target - CodeCache::low_bound()) &&
12599 Assembler::is_simm32(target - CodeCache::high_bound());
12600 }
12601 default: {
12602 return false;
12603 }
12604 }
12605 }
12606
12607 bool Assembler::reachable(AddressLiteral adr) {
12608 assert(CodeCache::contains(pc()), "required");
12609 if (adr.is_lval()) {
12610 return false;
12611 }
12612 return is_reachable(adr.target(), adr.reloc());
12613 }
12614
12615 bool Assembler::always_reachable(AddressLiteral adr) {
12616 assert(CodeCache::contains(pc()), "required");
12617 if (adr.is_lval()) {
12618 return false;
12619 }
12620 return is_always_reachable(adr.target(), adr.reloc());
12621 }
12622
12623 void Assembler::emit_data64(jlong data,
12624 relocInfo::relocType rtype,
12625 int format) {
12626 if (rtype == relocInfo::none) {
12627 emit_int64(data);
12628 } else {
12629 emit_data64(data, Relocation::spec_simple(rtype), format);
12630 }
12631 }
12632
12633 void Assembler::emit_data64(jlong data,
12634 RelocationHolder const& rspec,
12635 int format) {
12636 assert(imm_operand == 0, "default format must be immediate in this file");
12637 assert(imm_operand == format, "must be immediate");
12638 assert(inst_mark() != nullptr, "must be inside InstructionMark");
12639 // Do not use AbstractAssembler::relocate, which is not intended for
12640 // embedded words. Instead, relocate to the enclosing instruction.
12641 code_section()->relocate(inst_mark(), rspec, format);
12642 #ifdef ASSERT
12643 check_relocation(rspec, format);
12644 #endif
12645 emit_int64(data);
12646 }
12647
12648 void Assembler::prefix(Register reg) {
12649 if (reg->encoding() >= 8) {
12650 prefix(REX_B);
12651 }
12652 }
12653
12654 void Assembler::prefix(Register dst, Register src, Prefix p) {
12655 if (src->encoding() >= 8) {
12656 p = (Prefix)(p | REX_B);
12657 }
12658 if (dst->encoding() >= 8) {
12659 p = (Prefix)(p | REX_R);
12660 }
12661 if (p != Prefix_EMPTY) {
12662 // do not generate an empty prefix
12663 prefix(p);
12664 }
12665 }
12666
12667 void Assembler::prefix(Register dst, Address adr, Prefix p) {
12668 if (adr.base_needs_rex()) {
12669 if (adr.index_needs_rex()) {
12670 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12671 } else {
12672 p = (Prefix)(p | REX_B);
12673 }
12674 } else {
12675 if (adr.index_needs_rex()) {
12676 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12677 }
12678 }
12679 if (dst->encoding() >= 8) {
12680 p = (Prefix)(p | REX_R);
12681 }
12682 if (p != Prefix_EMPTY) {
12683 // do not generate an empty prefix
12684 prefix(p);
12685 }
12686 }
12687
12688 void Assembler::prefix(Address adr) {
12689 if (adr.base_needs_rex()) {
12690 if (adr.index_needs_rex()) {
12691 prefix(REX_XB);
12692 } else {
12693 prefix(REX_B);
12694 }
12695 } else {
12696 if (adr.index_needs_rex()) {
12697 prefix(REX_X);
12698 }
12699 }
12700 }
12701
12702 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
12703 if (reg->encoding() < 8) {
12704 if (adr.base_needs_rex()) {
12705 if (adr.index_needs_rex()) {
12706 prefix(REX_XB);
12707 } else {
12708 prefix(REX_B);
12709 }
12710 } else {
12711 if (adr.index_needs_rex()) {
12712 prefix(REX_X);
12713 } else if (byteinst && reg->encoding() >= 4) {
12714 prefix(REX);
12715 }
12716 }
12717 } else {
12718 if (adr.base_needs_rex()) {
12719 if (adr.index_needs_rex()) {
12720 prefix(REX_RXB);
12721 } else {
12722 prefix(REX_RB);
12723 }
12724 } else {
12725 if (adr.index_needs_rex()) {
12726 prefix(REX_RX);
12727 } else {
12728 prefix(REX_R);
12729 }
12730 }
12731 }
12732 }
12733
12734 void Assembler::prefix(Address adr, XMMRegister reg) {
12735 if (reg->encoding() < 8) {
12736 if (adr.base_needs_rex()) {
12737 if (adr.index_needs_rex()) {
12738 prefix(REX_XB);
12739 } else {
12740 prefix(REX_B);
12741 }
12742 } else {
12743 if (adr.index_needs_rex()) {
12744 prefix(REX_X);
12745 }
12746 }
12747 } else {
12748 if (adr.base_needs_rex()) {
12749 if (adr.index_needs_rex()) {
12750 prefix(REX_RXB);
12751 } else {
12752 prefix(REX_RB);
12753 }
12754 } else {
12755 if (adr.index_needs_rex()) {
12756 prefix(REX_RX);
12757 } else {
12758 prefix(REX_R);
12759 }
12760 }
12761 }
12762 }
12763
12764 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
12765 if (reg_enc >= 8) {
12766 prefix(REX_B);
12767 reg_enc -= 8;
12768 } else if (byteinst && reg_enc >= 4) {
12769 prefix(REX);
12770 }
12771 return reg_enc;
12772 }
12773
12774 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
12775 if (dst_enc < 8) {
12776 if (src_enc >= 8) {
12777 prefix(REX_B);
12778 src_enc -= 8;
12779 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
12780 prefix(REX);
12781 }
12782 } else {
12783 if (src_enc < 8) {
12784 prefix(REX_R);
12785 } else {
12786 prefix(REX_RB);
12787 src_enc -= 8;
12788 }
12789 dst_enc -= 8;
12790 }
12791 return dst_enc << 3 | src_enc;
12792 }
12793
12794 int8_t Assembler::get_prefixq(Address adr) {
12795 int8_t prfx = get_prefixq(adr, rax);
12796 assert(REX_W <= prfx && prfx <= REX_WXB, "must be");
12797 return prfx;
12798 }
12799
12800 int8_t Assembler::get_prefixq(Address adr, Register src) {
12801 int8_t prfx = (int8_t)(REX_W +
12802 ((int)adr.base_needs_rex()) +
12803 ((int)adr.index_needs_rex() << 1) +
12804 ((int)(src->encoding() >= 8) << 2));
12805 #ifdef ASSERT
12806 if (src->encoding() < 8) {
12807 if (adr.base_needs_rex()) {
12808 if (adr.index_needs_rex()) {
12809 assert(prfx == REX_WXB, "must be");
12810 } else {
12811 assert(prfx == REX_WB, "must be");
12812 }
12813 } else {
12814 if (adr.index_needs_rex()) {
12815 assert(prfx == REX_WX, "must be");
12816 } else {
12817 assert(prfx == REX_W, "must be");
12818 }
12819 }
12820 } else {
12821 if (adr.base_needs_rex()) {
12822 if (adr.index_needs_rex()) {
12823 assert(prfx == REX_WRXB, "must be");
12824 } else {
12825 assert(prfx == REX_WRB, "must be");
12826 }
12827 } else {
12828 if (adr.index_needs_rex()) {
12829 assert(prfx == REX_WRX, "must be");
12830 } else {
12831 assert(prfx == REX_WR, "must be");
12832 }
12833 }
12834 }
12835 #endif
12836 return prfx;
12837 }
12838
12839 void Assembler::prefixq(Address adr) {
12840 emit_int8(get_prefixq(adr));
12841 }
12842
12843 void Assembler::prefixq(Address adr, Register src) {
12844 emit_int8(get_prefixq(adr, src));
12845 }
12846
12847 void Assembler::prefixq(Address adr, XMMRegister src) {
12848 if (src->encoding() < 8) {
12849 if (adr.base_needs_rex()) {
12850 if (adr.index_needs_rex()) {
12851 prefix(REX_WXB);
12852 } else {
12853 prefix(REX_WB);
12854 }
12855 } else {
12856 if (adr.index_needs_rex()) {
12857 prefix(REX_WX);
12858 } else {
12859 prefix(REX_W);
12860 }
12861 }
12862 } else {
12863 if (adr.base_needs_rex()) {
12864 if (adr.index_needs_rex()) {
12865 prefix(REX_WRXB);
12866 } else {
12867 prefix(REX_WRB);
12868 }
12869 } else {
12870 if (adr.index_needs_rex()) {
12871 prefix(REX_WRX);
12872 } else {
12873 prefix(REX_WR);
12874 }
12875 }
12876 }
12877 }
12878
12879 int Assembler::prefixq_and_encode(int reg_enc) {
12880 if (reg_enc < 8) {
12881 prefix(REX_W);
12882 } else {
12883 prefix(REX_WB);
12884 reg_enc -= 8;
12885 }
12886 return reg_enc;
12887 }
12888
12889 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
12890 if (dst_enc < 8) {
12891 if (src_enc < 8) {
12892 prefix(REX_W);
12893 } else {
12894 prefix(REX_WB);
12895 src_enc -= 8;
12896 }
12897 } else {
12898 if (src_enc < 8) {
12899 prefix(REX_WR);
12900 } else {
12901 prefix(REX_WRB);
12902 src_enc -= 8;
12903 }
12904 dst_enc -= 8;
12905 }
12906 return dst_enc << 3 | src_enc;
12907 }
12908
12909 void Assembler::adcq(Register dst, int32_t imm32) {
12910 (void) prefixq_and_encode(dst->encoding());
12911 emit_arith(0x81, 0xD0, dst, imm32);
12912 }
12913
12914 void Assembler::adcq(Register dst, Address src) {
12915 InstructionMark im(this);
12916 emit_int16(get_prefixq(src, dst), 0x13);
12917 emit_operand(dst, src, 0);
12918 }
12919
12920 void Assembler::adcq(Register dst, Register src) {
12921 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12922 emit_arith(0x13, 0xC0, dst, src);
12923 }
12924
12925 void Assembler::addq(Address dst, int32_t imm32) {
12926 InstructionMark im(this);
12927 prefixq(dst);
12928 emit_arith_operand(0x81, rax, dst, imm32);
12929 }
12930
12931 void Assembler::addq(Address dst, Register src) {
12932 InstructionMark im(this);
12933 emit_int16(get_prefixq(dst, src), 0x01);
12934 emit_operand(src, dst, 0);
12935 }
12936
12937 void Assembler::addq(Register dst, int32_t imm32) {
12938 (void) prefixq_and_encode(dst->encoding());
12939 emit_arith(0x81, 0xC0, dst, imm32);
12940 }
12941
12942 void Assembler::addq(Register dst, Address src) {
12943 InstructionMark im(this);
12944 emit_int16(get_prefixq(src, dst), 0x03);
12945 emit_operand(dst, src, 0);
12946 }
12947
12948 void Assembler::addq(Register dst, Register src) {
12949 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12950 emit_arith(0x03, 0xC0, dst, src);
12951 }
12952
12953 void Assembler::adcxq(Register dst, Register src) {
12954 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12955 emit_int8(0x66);
12956 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12957 emit_int32(0x0F,
12958 0x38,
12959 (unsigned char)0xF6,
12960 (0xC0 | encode));
12961 }
12962
12963 void Assembler::adoxq(Register dst, Register src) {
12964 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12965 emit_int8((unsigned char)0xF3);
12966 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12967 emit_int32(0x0F,
12968 0x38,
12969 (unsigned char)0xF6,
12970 (0xC0 | encode));
12971 }
12972
12973 void Assembler::andq(Address dst, int32_t imm32) {
12974 InstructionMark im(this);
12975 prefixq(dst);
12976 emit_arith_operand(0x81, as_Register(4), dst, imm32);
12977 }
12978
12979 void Assembler::andq(Register dst, int32_t imm32) {
12980 (void) prefixq_and_encode(dst->encoding());
12981 emit_arith(0x81, 0xE0, dst, imm32);
12982 }
12983
12984 void Assembler::andq(Register dst, Address src) {
12985 InstructionMark im(this);
12986 emit_int16(get_prefixq(src, dst), 0x23);
12987 emit_operand(dst, src, 0);
12988 }
12989
12990 void Assembler::andq(Register dst, Register src) {
12991 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12992 emit_arith(0x23, 0xC0, dst, src);
12993 }
12994
12995 void Assembler::andq(Address dst, Register src) {
12996 InstructionMark im(this);
12997 emit_int16(get_prefixq(dst, src), 0x21);
12998 emit_operand(src, dst, 0);
12999 }
13000
13001 void Assembler::andnq(Register dst, Register src1, Register src2) {
13002 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13003 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13004 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13005 emit_int16((unsigned char)0xF2, (0xC0 | encode));
13006 }
13007
13008 void Assembler::andnq(Register dst, Register src1, Address src2) {
13009 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13010 InstructionMark im(this);
13011 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13012 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13013 emit_int8((unsigned char)0xF2);
13014 emit_operand(dst, src2, 0);
13015 }
13016
13017 void Assembler::bsfq(Register dst, Register src) {
13018 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13019 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
13020 }
13021
13022 void Assembler::bsrq(Register dst, Register src) {
13023 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13024 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
13025 }
13026
13027 void Assembler::bswapq(Register reg) {
13028 int encode = prefixq_and_encode(reg->encoding());
13029 emit_int16(0x0F, (0xC8 | encode));
13030 }
13031
13032 void Assembler::blsiq(Register dst, Register src) {
13033 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13034 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13035 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13036 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13037 }
13038
13039 void Assembler::blsiq(Register dst, Address src) {
13040 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13041 InstructionMark im(this);
13042 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13043 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13044 emit_int8((unsigned char)0xF3);
13045 emit_operand(rbx, src, 0);
13046 }
13047
13048 void Assembler::blsmskq(Register dst, Register src) {
13049 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13050 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13051 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13052 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13053 }
13054
13055 void Assembler::blsmskq(Register dst, Address src) {
13056 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13057 InstructionMark im(this);
13058 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13059 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13060 emit_int8((unsigned char)0xF3);
13061 emit_operand(rdx, src, 0);
13062 }
13063
13064 void Assembler::blsrq(Register dst, Register src) {
13065 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13066 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13067 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13068 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13069 }
13070
13071 void Assembler::blsrq(Register dst, Address src) {
13072 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13073 InstructionMark im(this);
13074 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13075 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13076 emit_int8((unsigned char)0xF3);
13077 emit_operand(rcx, src, 0);
13078 }
13079
13080 void Assembler::cdqq() {
13081 emit_int16(REX_W, (unsigned char)0x99);
13082 }
13083
13084 void Assembler::clflush(Address adr) {
13085 assert(VM_Version::supports_clflush(), "should do");
13086 prefix(adr);
13087 emit_int16(0x0F, (unsigned char)0xAE);
13088 emit_operand(rdi, adr, 0);
13089 }
13090
13091 void Assembler::clflushopt(Address adr) {
13092 assert(VM_Version::supports_clflushopt(), "should do!");
13093 // adr should be base reg only with no index or offset
13094 assert(adr.index() == noreg, "index should be noreg");
13095 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13096 assert(adr.disp() == 0, "displacement should be 0");
13097 // instruction prefix is 0x66
13098 emit_int8(0x66);
13099 prefix(adr);
13100 // opcode family is 0x0F 0xAE
13101 emit_int16(0x0F, (unsigned char)0xAE);
13102 // extended opcode byte is 7 == rdi
13103 emit_operand(rdi, adr, 0);
13104 }
13105
13106 void Assembler::clwb(Address adr) {
13107 assert(VM_Version::supports_clwb(), "should do!");
13108 // adr should be base reg only with no index or offset
13109 assert(adr.index() == noreg, "index should be noreg");
13110 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13111 assert(adr.disp() == 0, "displacement should be 0");
13112 // instruction prefix is 0x66
13113 emit_int8(0x66);
13114 prefix(adr);
13115 // opcode family is 0x0f 0xAE
13116 emit_int16(0x0F, (unsigned char)0xAE);
13117 // extended opcode byte is 6 == rsi
13118 emit_operand(rsi, adr, 0);
13119 }
13120
13121 void Assembler::cmovq(Condition cc, Register dst, Register src) {
13122 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13123 emit_int24(0x0F, (0x40 | cc), (0xC0 | encode));
13124 }
13125
13126 void Assembler::cmovq(Condition cc, Register dst, Address src) {
13127 InstructionMark im(this);
13128 emit_int24(get_prefixq(src, dst), 0x0F, (0x40 | cc));
13129 emit_operand(dst, src, 0);
13130 }
13131
13132 void Assembler::cmpq(Address dst, int32_t imm32) {
13133 InstructionMark im(this);
13134 prefixq(dst);
13135 emit_arith_operand(0x81, as_Register(7), dst, imm32);
13136 }
13137
13138 void Assembler::cmpq(Register dst, int32_t imm32) {
13139 (void) prefixq_and_encode(dst->encoding());
13140 emit_arith(0x81, 0xF8, dst, imm32);
13141 }
13142
13143 void Assembler::cmpq(Address dst, Register src) {
13144 InstructionMark im(this);
13145 emit_int16(get_prefixq(dst, src), 0x39);
13146 emit_operand(src, dst, 0);
13147 }
13148
13149 void Assembler::cmpq(Register dst, Register src) {
13150 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13151 emit_arith(0x3B, 0xC0, dst, src);
13152 }
13153
13154 void Assembler::cmpq(Register dst, Address src) {
13155 InstructionMark im(this);
13156 emit_int16(get_prefixq(src, dst), 0x3B);
13157 emit_operand(dst, src, 0);
13158 }
13159
13160 void Assembler::cmpxchgq(Register reg, Address adr) {
13161 InstructionMark im(this);
13162 emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1);
13163 emit_operand(reg, adr, 0);
13164 }
13165
13166 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
13167 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13168 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13169 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13170 emit_int16(0x2A, (0xC0 | encode));
13171 }
13172
13173 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
13174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13175 InstructionMark im(this);
13176 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13177 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13178 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13179 emit_int8(0x2A);
13180 emit_operand(dst, src, 0);
13181 }
13182
13183 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
13184 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13185 InstructionMark im(this);
13186 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13187 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13188 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13189 emit_int8(0x2A);
13190 emit_operand(dst, src, 0);
13191 }
13192
13193 void Assembler::cvttsd2siq(Register dst, Address src) {
13194 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13195 // F2 REX.W 0F 2C /r
13196 // CVTTSD2SI r64, xmm1/m64
13197 InstructionMark im(this);
13198 emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C);
13199 emit_operand(dst, src, 0);
13200 }
13201
13202 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
13203 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13204 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13205 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13206 emit_int16(0x2C, (0xC0 | encode));
13207 }
13208
13209 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
13210 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13211 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13212 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13213 emit_int16(0x2D, (0xC0 | encode));
13214 }
13215
13216 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
13217 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13218 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13219 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13220 emit_int16(0x2C, (0xC0 | encode));
13221 }
13222
13223 void Assembler::decl(Register dst) {
13224 // Don't use it directly. Use MacroAssembler::decrementl() instead.
13225 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
13226 int encode = prefix_and_encode(dst->encoding());
13227 emit_int16((unsigned char)0xFF, (0xC8 | encode));
13228 }
13229
13230 void Assembler::decq(Register dst) {
13231 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13232 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13233 int encode = prefixq_and_encode(dst->encoding());
13234 emit_int16((unsigned char)0xFF, 0xC8 | encode);
13235 }
13236
13237 void Assembler::decq(Address dst) {
13238 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13239 InstructionMark im(this);
13240 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13241 emit_operand(rcx, dst, 0);
13242 }
13243
13244 void Assembler::fxrstor(Address src) {
13245 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13246 emit_operand(as_Register(1), src, 0);
13247 }
13248
13249 void Assembler::xrstor(Address src) {
13250 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13251 emit_operand(as_Register(5), src, 0);
13252 }
13253
13254 void Assembler::fxsave(Address dst) {
13255 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13256 emit_operand(as_Register(0), dst, 0);
13257 }
13258
13259 void Assembler::xsave(Address dst) {
13260 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13261 emit_operand(as_Register(4), dst, 0);
13262 }
13263
13264 void Assembler::idivq(Register src) {
13265 int encode = prefixq_and_encode(src->encoding());
13266 emit_int16((unsigned char)0xF7, (0xF8 | encode));
13267 }
13268
13269 void Assembler::divq(Register src) {
13270 int encode = prefixq_and_encode(src->encoding());
13271 emit_int16((unsigned char)0xF7, (0xF0 | encode));
13272 }
13273
13274 void Assembler::imulq(Register dst, Register src) {
13275 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13276 emit_int24(0x0F, (unsigned char)0xAF, (0xC0 | encode));
13277 }
13278
13279 void Assembler::imulq(Register src) {
13280 int encode = prefixq_and_encode(src->encoding());
13281 emit_int16((unsigned char)0xF7, (0xE8 | encode));
13282 }
13283
13284 void Assembler::imulq(Register dst, Address src, int32_t value) {
13285 InstructionMark im(this);
13286 prefixq(src, dst);
13287 if (is8bit(value)) {
13288 emit_int8((unsigned char)0x6B);
13289 emit_operand(dst, src, 1);
13290 emit_int8(value);
13291 } else {
13292 emit_int8((unsigned char)0x69);
13293 emit_operand(dst, src, 4);
13294 emit_int32(value);
13295 }
13296 }
13297
13298 void Assembler::imulq(Register dst, Register src, int value) {
13299 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13300 if (is8bit(value)) {
13301 emit_int24(0x6B, (0xC0 | encode), (value & 0xFF));
13302 } else {
13303 emit_int16(0x69, (0xC0 | encode));
13304 emit_int32(value);
13305 }
13306 }
13307
13308 void Assembler::imulq(Register dst, Address src) {
13309 InstructionMark im(this);
13310 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF);
13311 emit_operand(dst, src, 0);
13312 }
13313
13314 void Assembler::incl(Register dst) {
13315 // Don't use it directly. Use MacroAssembler::incrementl() instead.
13316 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13317 int encode = prefix_and_encode(dst->encoding());
13318 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13319 }
13320
13321 void Assembler::incq(Register dst) {
13322 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13323 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13324 int encode = prefixq_and_encode(dst->encoding());
13325 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13326 }
13327
13328 void Assembler::incq(Address dst) {
13329 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13330 InstructionMark im(this);
13331 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13332 emit_operand(rax, dst, 0);
13333 }
13334
13335 void Assembler::lea(Register dst, Address src) {
13336 leaq(dst, src);
13337 }
13338
13339 void Assembler::leaq(Register dst, Address src) {
13340 InstructionMark im(this);
13341 emit_int16(get_prefixq(src, dst), (unsigned char)0x8D);
13342 emit_operand(dst, src, 0);
13343 }
13344
13345 void Assembler::mov64(Register dst, int64_t imm64) {
13346 InstructionMark im(this);
13347 int encode = prefixq_and_encode(dst->encoding());
13348 emit_int8(0xB8 | encode);
13349 emit_int64(imm64);
13350 }
13351
13352 void Assembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
13353 InstructionMark im(this);
13354 int encode = prefixq_and_encode(dst->encoding());
13355 emit_int8(0xB8 | encode);
13356 emit_data64(imm64, rtype, format);
13357 }
13358
13359 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
13360 InstructionMark im(this);
13361 int encode = prefixq_and_encode(dst->encoding());
13362 emit_int8(0xB8 | encode);
13363 emit_data64(imm64, rspec);
13364 }
13365
13366 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
13367 InstructionMark im(this);
13368 int encode = prefix_and_encode(dst->encoding());
13369 emit_int8(0xB8 | encode);
13370 emit_data((int)imm32, rspec, narrow_oop_operand);
13371 }
13372
13373 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
13374 InstructionMark im(this);
13375 prefix(dst);
13376 emit_int8((unsigned char)0xC7);
13377 emit_operand(rax, dst, 4);
13378 emit_data((int)imm32, rspec, narrow_oop_operand);
13379 }
13380
13381 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
13382 InstructionMark im(this);
13383 int encode = prefix_and_encode(src1->encoding());
13384 emit_int16((unsigned char)0x81, (0xF8 | encode));
13385 emit_data((int)imm32, rspec, narrow_oop_operand);
13386 }
13387
13388 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
13389 InstructionMark im(this);
13390 prefix(src1);
13391 emit_int8((unsigned char)0x81);
13392 emit_operand(rax, src1, 4);
13393 emit_data((int)imm32, rspec, narrow_oop_operand);
13394 }
13395
13396 void Assembler::lzcntq(Register dst, Register src) {
13397 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13398 emit_int8((unsigned char)0xF3);
13399 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13400 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
13401 }
13402
13403 void Assembler::lzcntq(Register dst, Address src) {
13404 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13405 InstructionMark im(this);
13406 emit_int8((unsigned char)0xF3);
13407 prefixq(src, dst);
13408 emit_int16(0x0F, (unsigned char)0xBD);
13409 emit_operand(dst, src, 0);
13410 }
13411
13412 void Assembler::movdq(XMMRegister dst, Register src) {
13413 // table D-1 says MMX/SSE2
13414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13415 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13416 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13417 emit_int16(0x6E, (0xC0 | encode));
13418 }
13419
13420 void Assembler::movdq(Register dst, XMMRegister src) {
13421 // table D-1 says MMX/SSE2
13422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13423 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13424 // swap src/dst to get correct prefix
13425 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13426 emit_int16(0x7E,
13427 (0xC0 | encode));
13428 }
13429
13430 void Assembler::movq(Register dst, Register src) {
13431 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13432 emit_int16((unsigned char)0x8B,
13433 (0xC0 | encode));
13434 }
13435
13436 void Assembler::movq(Register dst, Address src) {
13437 InstructionMark im(this);
13438 emit_int16(get_prefixq(src, dst), (unsigned char)0x8B);
13439 emit_operand(dst, src, 0);
13440 }
13441
13442 void Assembler::movq(Address dst, Register src) {
13443 InstructionMark im(this);
13444 emit_int16(get_prefixq(dst, src), (unsigned char)0x89);
13445 emit_operand(src, dst, 0);
13446 }
13447
13448 void Assembler::movq(Address dst, int32_t imm32) {
13449 InstructionMark im(this);
13450 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13451 emit_operand(as_Register(0), dst, 4);
13452 emit_int32(imm32);
13453 }
13454
13455 void Assembler::movq(Register dst, int32_t imm32) {
13456 int encode = prefixq_and_encode(dst->encoding());
13457 emit_int16((unsigned char)0xC7, (0xC0 | encode));
13458 emit_int32(imm32);
13459 }
13460
13461 void Assembler::movsbq(Register dst, Address src) {
13462 InstructionMark im(this);
13463 emit_int24(get_prefixq(src, dst),
13464 0x0F,
13465 (unsigned char)0xBE);
13466 emit_operand(dst, src, 0);
13467 }
13468
13469 void Assembler::movsbq(Register dst, Register src) {
13470 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13471 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
13472 }
13473
13474 void Assembler::movslq(Address dst, int32_t imm32) {
13475 assert(is_simm32(imm32), "lost bits");
13476 InstructionMark im(this);
13477 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13478 emit_operand(rax, dst, 4);
13479 emit_int32(imm32);
13480 }
13481
13482 void Assembler::movslq(Register dst, Address src) {
13483 InstructionMark im(this);
13484 emit_int16(get_prefixq(src, dst), 0x63);
13485 emit_operand(dst, src, 0);
13486 }
13487
13488 void Assembler::movslq(Register dst, Register src) {
13489 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13490 emit_int16(0x63, (0xC0 | encode));
13491 }
13492
13493 void Assembler::movswq(Register dst, Address src) {
13494 InstructionMark im(this);
13495 emit_int24(get_prefixq(src, dst),
13496 0x0F,
13497 (unsigned char)0xBF);
13498 emit_operand(dst, src, 0);
13499 }
13500
13501 void Assembler::movswq(Register dst, Register src) {
13502 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13503 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
13504 }
13505
13506 void Assembler::movzbq(Register dst, Address src) {
13507 InstructionMark im(this);
13508 emit_int24(get_prefixq(src, dst),
13509 0x0F,
13510 (unsigned char)0xB6);
13511 emit_operand(dst, src, 0);
13512 }
13513
13514 void Assembler::movzbq(Register dst, Register src) {
13515 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13516 emit_int24(0x0F, (unsigned char)0xB6, (0xC0 | encode));
13517 }
13518
13519 void Assembler::movzwq(Register dst, Address src) {
13520 InstructionMark im(this);
13521 emit_int24(get_prefixq(src, dst),
13522 0x0F,
13523 (unsigned char)0xB7);
13524 emit_operand(dst, src, 0);
13525 }
13526
13527 void Assembler::movzwq(Register dst, Register src) {
13528 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13529 emit_int24(0x0F, (unsigned char)0xB7, (0xC0 | encode));
13530 }
13531
13532 void Assembler::mulq(Address src) {
13533 InstructionMark im(this);
13534 emit_int16(get_prefixq(src), (unsigned char)0xF7);
13535 emit_operand(rsp, src, 0);
13536 }
13537
13538 void Assembler::mulq(Register src) {
13539 int encode = prefixq_and_encode(src->encoding());
13540 emit_int16((unsigned char)0xF7, (0xE0 | encode));
13541 }
13542
13543 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
13544 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13545 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13546 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
13547 emit_int16((unsigned char)0xF6, (0xC0 | encode));
13548 }
13549
13550 void Assembler::negq(Register dst) {
13551 int encode = prefixq_and_encode(dst->encoding());
13552 emit_int16((unsigned char)0xF7, (0xD8 | encode));
13553 }
13554
13555 void Assembler::negq(Address dst) {
13556 InstructionMark im(this);
13557 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
13558 emit_operand(as_Register(3), dst, 0);
13559 }
13560
13561 void Assembler::notq(Register dst) {
13562 int encode = prefixq_and_encode(dst->encoding());
13563 emit_int16((unsigned char)0xF7, (0xD0 | encode));
13564 }
13565
13566 void Assembler::btsq(Address dst, int imm8) {
13567 assert(isByte(imm8), "not a byte");
13568 InstructionMark im(this);
13569 emit_int24(get_prefixq(dst),
13570 0x0F,
13571 (unsigned char)0xBA);
13572 emit_operand(rbp /* 5 */, dst, 1);
13573 emit_int8(imm8);
13574 }
13575
13576 void Assembler::btrq(Address dst, int imm8) {
13577 assert(isByte(imm8), "not a byte");
13578 InstructionMark im(this);
13579 emit_int24(get_prefixq(dst),
13580 0x0F,
13581 (unsigned char)0xBA);
13582 emit_operand(rsi /* 6 */, dst, 1);
13583 emit_int8(imm8);
13584 }
13585
13586 void Assembler::orq(Address dst, int32_t imm32) {
13587 InstructionMark im(this);
13588 prefixq(dst);
13589 emit_arith_operand(0x81, as_Register(1), dst, imm32);
13590 }
13591
13592 void Assembler::orq(Address dst, Register src) {
13593 InstructionMark im(this);
13594 emit_int16(get_prefixq(dst, src), (unsigned char)0x09);
13595 emit_operand(src, dst, 0);
13596 }
13597
13598 void Assembler::orq(Register dst, int32_t imm32) {
13599 (void) prefixq_and_encode(dst->encoding());
13600 emit_arith(0x81, 0xC8, dst, imm32);
13601 }
13602
13603 void Assembler::orq_imm32(Register dst, int32_t imm32) {
13604 (void) prefixq_and_encode(dst->encoding());
13605 emit_arith_imm32(0x81, 0xC8, dst, imm32);
13606 }
13607
13608 void Assembler::orq(Register dst, Address src) {
13609 InstructionMark im(this);
13610 emit_int16(get_prefixq(src, dst), 0x0B);
13611 emit_operand(dst, src, 0);
13612 }
13613
13614 void Assembler::orq(Register dst, Register src) {
13615 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13616 emit_arith(0x0B, 0xC0, dst, src);
13617 }
13618
13619 void Assembler::popcntq(Register dst, Address src) {
13620 assert(VM_Version::supports_popcnt(), "must support");
13621 InstructionMark im(this);
13622 emit_int32((unsigned char)0xF3,
13623 get_prefixq(src, dst),
13624 0x0F,
13625 (unsigned char)0xB8);
13626 emit_operand(dst, src, 0);
13627 }
13628
13629 void Assembler::popcntq(Register dst, Register src) {
13630 assert(VM_Version::supports_popcnt(), "must support");
13631 emit_int8((unsigned char)0xF3);
13632 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13633 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
13634 }
13635
13636 void Assembler::popq(Address dst) {
13637 InstructionMark im(this);
13638 emit_int16(get_prefixq(dst), (unsigned char)0x8F);
13639 emit_operand(rax, dst, 0);
13640 }
13641
13642 void Assembler::popq(Register dst) {
13643 emit_int8((unsigned char)0x58 | dst->encoding());
13644 }
13645
13646 // Precomputable: popa, pusha, vzeroupper
13647
13648 // The result of these routines are invariant from one invocation to another
13649 // invocation for the duration of a run. Caching the result on bootstrap
13650 // and copying it out on subsequent invocations can thus be beneficial
13651 static bool precomputed = false;
13652
13653 static u_char* popa_code = nullptr;
13654 static int popa_len = 0;
13655
13656 static u_char* pusha_code = nullptr;
13657 static int pusha_len = 0;
13658
13659 static u_char* vzup_code = nullptr;
13660 static int vzup_len = 0;
13661
13662 void Assembler::precompute_instructions() {
13663 assert(!Universe::is_fully_initialized(), "must still be single threaded");
13664 guarantee(!precomputed, "only once");
13665 precomputed = true;
13666 ResourceMark rm;
13667
13668 // Make a temporary buffer big enough for the routines we're capturing
13669 int size = 256;
13670 char* tmp_code = NEW_RESOURCE_ARRAY(char, size);
13671 CodeBuffer buffer((address)tmp_code, size);
13672 MacroAssembler masm(&buffer);
13673
13674 address begin_popa = masm.code_section()->end();
13675 masm.popa_uncached();
13676 address end_popa = masm.code_section()->end();
13677 masm.pusha_uncached();
13678 address end_pusha = masm.code_section()->end();
13679 masm.vzeroupper_uncached();
13680 address end_vzup = masm.code_section()->end();
13681
13682 // Save the instructions to permanent buffers.
13683 popa_len = (int)(end_popa - begin_popa);
13684 popa_code = NEW_C_HEAP_ARRAY(u_char, popa_len, mtInternal);
13685 memcpy(popa_code, begin_popa, popa_len);
13686
13687 pusha_len = (int)(end_pusha - end_popa);
13688 pusha_code = NEW_C_HEAP_ARRAY(u_char, pusha_len, mtInternal);
13689 memcpy(pusha_code, end_popa, pusha_len);
13690
13691 vzup_len = (int)(end_vzup - end_pusha);
13692 if (vzup_len > 0) {
13693 vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
13694 memcpy(vzup_code, end_pusha, vzup_len);
13695 } else {
13696 vzup_code = pusha_code; // dummy
13697 }
13698
13699 assert(masm.code()->total_oop_size() == 0 &&
13700 masm.code()->total_metadata_size() == 0 &&
13701 masm.code()->total_relocation_size() == 0,
13702 "pre-computed code can't reference oops, metadata or contain relocations");
13703 }
13704
13705 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
13706 assert(src != nullptr, "code to copy must have been pre-computed");
13707 assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
13708 address end = code_section->end();
13709 memcpy(end, src, src_len);
13710 code_section->set_end(end + src_len);
13711 }
13712
13713 void Assembler::popa() { // 64bit
13714 emit_copy(code_section(), popa_code, popa_len);
13715 }
13716
13717 void Assembler::popa_uncached() { // 64bit
13718 movq(r15, Address(rsp, 0));
13719 movq(r14, Address(rsp, wordSize));
13720 movq(r13, Address(rsp, 2 * wordSize));
13721 movq(r12, Address(rsp, 3 * wordSize));
13722 movq(r11, Address(rsp, 4 * wordSize));
13723 movq(r10, Address(rsp, 5 * wordSize));
13724 movq(r9, Address(rsp, 6 * wordSize));
13725 movq(r8, Address(rsp, 7 * wordSize));
13726 movq(rdi, Address(rsp, 8 * wordSize));
13727 movq(rsi, Address(rsp, 9 * wordSize));
13728 movq(rbp, Address(rsp, 10 * wordSize));
13729 // Skip rsp as it is restored automatically to the value
13730 // before the corresponding pusha when popa is done.
13731 movq(rbx, Address(rsp, 12 * wordSize));
13732 movq(rdx, Address(rsp, 13 * wordSize));
13733 movq(rcx, Address(rsp, 14 * wordSize));
13734 movq(rax, Address(rsp, 15 * wordSize));
13735
13736 addq(rsp, 16 * wordSize);
13737 }
13738
13739 // Does not actually store the value of rsp on the stack.
13740 // The slot for rsp just contains an arbitrary value.
13741 void Assembler::pusha() { // 64bit
13742 emit_copy(code_section(), pusha_code, pusha_len);
13743 }
13744
13745 // Does not actually store the value of rsp on the stack.
13746 // The slot for rsp just contains an arbitrary value.
13747 void Assembler::pusha_uncached() { // 64bit
13748 subq(rsp, 16 * wordSize);
13749
13750 movq(Address(rsp, 15 * wordSize), rax);
13751 movq(Address(rsp, 14 * wordSize), rcx);
13752 movq(Address(rsp, 13 * wordSize), rdx);
13753 movq(Address(rsp, 12 * wordSize), rbx);
13754 // Skip rsp as the value is normally not used. There are a few places where
13755 // the original value of rsp needs to be known but that can be computed
13756 // from the value of rsp immediately after pusha (rsp + 16 * wordSize).
13757 movq(Address(rsp, 10 * wordSize), rbp);
13758 movq(Address(rsp, 9 * wordSize), rsi);
13759 movq(Address(rsp, 8 * wordSize), rdi);
13760 movq(Address(rsp, 7 * wordSize), r8);
13761 movq(Address(rsp, 6 * wordSize), r9);
13762 movq(Address(rsp, 5 * wordSize), r10);
13763 movq(Address(rsp, 4 * wordSize), r11);
13764 movq(Address(rsp, 3 * wordSize), r12);
13765 movq(Address(rsp, 2 * wordSize), r13);
13766 movq(Address(rsp, wordSize), r14);
13767 movq(Address(rsp, 0), r15);
13768 }
13769
13770 void Assembler::vzeroupper() {
13771 emit_copy(code_section(), vzup_code, vzup_len);
13772 }
13773
13774 void Assembler::vzeroall() {
13775 assert(VM_Version::supports_avx(), "requires AVX");
13776 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13777 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
13778 emit_int8(0x77);
13779 }
13780
13781 void Assembler::pushq(Address src) {
13782 InstructionMark im(this);
13783 emit_int16(get_prefixq(src), (unsigned char)0xFF);
13784 emit_operand(rsi, src, 0);
13785 }
13786
13787 void Assembler::rclq(Register dst, int imm8) {
13788 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13789 int encode = prefixq_and_encode(dst->encoding());
13790 if (imm8 == 1) {
13791 emit_int16((unsigned char)0xD1, (0xD0 | encode));
13792 } else {
13793 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
13794 }
13795 }
13796
13797 void Assembler::rcrq(Register dst, int imm8) {
13798 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13799 int encode = prefixq_and_encode(dst->encoding());
13800 if (imm8 == 1) {
13801 emit_int16((unsigned char)0xD1, (0xD8 | encode));
13802 } else {
13803 emit_int24((unsigned char)0xC1, (0xD8 | encode), imm8);
13804 }
13805 }
13806
13807 void Assembler::rorxl(Register dst, Register src, int imm8) {
13808 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13809 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13810 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13811 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13812 }
13813
13814 void Assembler::rorxl(Register dst, Address src, int imm8) {
13815 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13816 InstructionMark im(this);
13817 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13818 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13819 emit_int8((unsigned char)0xF0);
13820 emit_operand(dst, src, 1);
13821 emit_int8(imm8);
13822 }
13823
13824 void Assembler::rorxq(Register dst, Register src, int imm8) {
13825 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13826 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13827 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13828 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13829 }
13830
13831 void Assembler::rorxq(Register dst, Address src, int imm8) {
13832 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13833 InstructionMark im(this);
13834 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13835 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13836 emit_int8((unsigned char)0xF0);
13837 emit_operand(dst, src, 1);
13838 emit_int8(imm8);
13839 }
13840
13841 #ifdef _LP64
13842 void Assembler::salq(Address dst, int imm8) {
13843 InstructionMark im(this);
13844 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13845 if (imm8 == 1) {
13846 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13847 emit_operand(as_Register(4), dst, 0);
13848 }
13849 else {
13850 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13851 emit_operand(as_Register(4), dst, 1);
13852 emit_int8(imm8);
13853 }
13854 }
13855
13856 void Assembler::salq(Address dst) {
13857 InstructionMark im(this);
13858 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13859 emit_operand(as_Register(4), dst, 0);
13860 }
13861
13862 void Assembler::salq(Register dst, int imm8) {
13863 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13864 int encode = prefixq_and_encode(dst->encoding());
13865 if (imm8 == 1) {
13866 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13867 } else {
13868 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13869 }
13870 }
13871
13872 void Assembler::salq(Register dst) {
13873 int encode = prefixq_and_encode(dst->encoding());
13874 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13875 }
13876
13877 void Assembler::sarq(Address dst, int imm8) {
13878 InstructionMark im(this);
13879 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13880 if (imm8 == 1) {
13881 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13882 emit_operand(as_Register(7), dst, 0);
13883 }
13884 else {
13885 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13886 emit_operand(as_Register(7), dst, 1);
13887 emit_int8(imm8);
13888 }
13889 }
13890
13891 void Assembler::sarq(Address dst) {
13892 InstructionMark im(this);
13893 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13894 emit_operand(as_Register(7), dst, 0);
13895 }
13896
13897 void Assembler::sarq(Register dst, int imm8) {
13898 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13899 int encode = prefixq_and_encode(dst->encoding());
13900 if (imm8 == 1) {
13901 emit_int16((unsigned char)0xD1, (0xF8 | encode));
13902 } else {
13903 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
13904 }
13905 }
13906
13907 void Assembler::sarq(Register dst) {
13908 int encode = prefixq_and_encode(dst->encoding());
13909 emit_int16((unsigned char)0xD3, (0xF8 | encode));
13910 }
13911 #endif
13912
13913 void Assembler::sbbq(Address dst, int32_t imm32) {
13914 InstructionMark im(this);
13915 prefixq(dst);
13916 emit_arith_operand(0x81, rbx, dst, imm32);
13917 }
13918
13919 void Assembler::sbbq(Register dst, int32_t imm32) {
13920 (void) prefixq_and_encode(dst->encoding());
13921 emit_arith(0x81, 0xD8, dst, imm32);
13922 }
13923
13924 void Assembler::sbbq(Register dst, Address src) {
13925 InstructionMark im(this);
13926 emit_int16(get_prefixq(src, dst), 0x1B);
13927 emit_operand(dst, src, 0);
13928 }
13929
13930 void Assembler::sbbq(Register dst, Register src) {
13931 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13932 emit_arith(0x1B, 0xC0, dst, src);
13933 }
13934
13935 void Assembler::shlq(Register dst, int imm8) {
13936 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13937 int encode = prefixq_and_encode(dst->encoding());
13938 if (imm8 == 1) {
13939 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13940 } else {
13941 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13942 }
13943 }
13944
13945 void Assembler::shlq(Register dst) {
13946 int encode = prefixq_and_encode(dst->encoding());
13947 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13948 }
13949
13950 void Assembler::shrq(Register dst, int imm8) {
13951 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13952 int encode = prefixq_and_encode(dst->encoding());
13953 if (imm8 == 1) {
13954 emit_int16((unsigned char)0xD1, (0xE8 | encode));
13955 }
13956 else {
13957 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
13958 }
13959 }
13960
13961 void Assembler::shrq(Register dst) {
13962 int encode = prefixq_and_encode(dst->encoding());
13963 emit_int16((unsigned char)0xD3, 0xE8 | encode);
13964 }
13965
13966 void Assembler::shrq(Address dst) {
13967 InstructionMark im(this);
13968 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13969 emit_operand(as_Register(5), dst, 0);
13970 }
13971
13972 void Assembler::shrq(Address dst, int imm8) {
13973 InstructionMark im(this);
13974 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13975 if (imm8 == 1) {
13976 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13977 emit_operand(as_Register(5), dst, 0);
13978 }
13979 else {
13980 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13981 emit_operand(as_Register(5), dst, 1);
13982 emit_int8(imm8);
13983 }
13984 }
13985
13986 void Assembler::subq(Address dst, int32_t imm32) {
13987 InstructionMark im(this);
13988 prefixq(dst);
13989 emit_arith_operand(0x81, rbp, dst, imm32);
13990 }
13991
13992 void Assembler::subq(Address dst, Register src) {
13993 InstructionMark im(this);
13994 emit_int16(get_prefixq(dst, src), 0x29);
13995 emit_operand(src, dst, 0);
13996 }
13997
13998 void Assembler::subq(Register dst, int32_t imm32) {
13999 (void) prefixq_and_encode(dst->encoding());
14000 emit_arith(0x81, 0xE8, dst, imm32);
14001 }
14002
14003 // Force generation of a 4 byte immediate value even if it fits into 8bit
14004 void Assembler::subq_imm32(Register dst, int32_t imm32) {
14005 (void) prefixq_and_encode(dst->encoding());
14006 emit_arith_imm32(0x81, 0xE8, dst, imm32);
14007 }
14008
14009 void Assembler::subq(Register dst, Address src) {
14010 InstructionMark im(this);
14011 emit_int16(get_prefixq(src, dst), 0x2B);
14012 emit_operand(dst, src, 0);
14013 }
14014
14015 void Assembler::subq(Register dst, Register src) {
14016 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14017 emit_arith(0x2B, 0xC0, dst, src);
14018 }
14019
14020 void Assembler::testq(Address dst, int32_t imm32) {
14021 InstructionMark im(this);
14022 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
14023 emit_operand(as_Register(0), dst, 4);
14024 emit_int32(imm32);
14025 }
14026
14027 void Assembler::testq(Register dst, int32_t imm32) {
14028 // not using emit_arith because test
14029 // doesn't support sign-extension of
14030 // 8bit operands
14031 if (dst == rax) {
14032 prefix(REX_W);
14033 emit_int8((unsigned char)0xA9);
14034 emit_int32(imm32);
14035 } else {
14036 int encode = dst->encoding();
14037 encode = prefixq_and_encode(encode);
14038 emit_int16((unsigned char)0xF7, (0xC0 | encode));
14039 emit_int32(imm32);
14040 }
14041 }
14042
14043 void Assembler::testq(Register dst, Register src) {
14044 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14045 emit_arith(0x85, 0xC0, dst, src);
14046 }
14047
14048 void Assembler::testq(Register dst, Address src) {
14049 InstructionMark im(this);
14050 emit_int16(get_prefixq(src, dst), (unsigned char)0x85);
14051 emit_operand(dst, src, 0);
14052 }
14053
14054 void Assembler::xaddq(Address dst, Register src) {
14055 InstructionMark im(this);
14056 emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1);
14057 emit_operand(src, dst, 0);
14058 }
14059
14060 void Assembler::xchgq(Register dst, Address src) {
14061 InstructionMark im(this);
14062 emit_int16(get_prefixq(src, dst), (unsigned char)0x87);
14063 emit_operand(dst, src, 0);
14064 }
14065
14066 void Assembler::xchgq(Register dst, Register src) {
14067 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
14068 emit_int16((unsigned char)0x87, (0xc0 | encode));
14069 }
14070
14071 void Assembler::xorq(Register dst, Register src) {
14072 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14073 emit_arith(0x33, 0xC0, dst, src);
14074 }
14075
14076 void Assembler::xorq(Register dst, Address src) {
14077 InstructionMark im(this);
14078 emit_int16(get_prefixq(src, dst), 0x33);
14079 emit_operand(dst, src, 0);
14080 }
14081
14082 void Assembler::xorq(Register dst, int32_t imm32) {
14083 (void) prefixq_and_encode(dst->encoding());
14084 emit_arith(0x81, 0xF0, dst, imm32);
14085 }
14086
14087 void Assembler::xorq(Address dst, int32_t imm32) {
14088 InstructionMark im(this);
14089 prefixq(dst);
14090 emit_arith_operand(0x81, as_Register(6), dst, imm32);
14091 }
14092
14093 void Assembler::xorq(Address dst, Register src) {
14094 InstructionMark im(this);
14095 emit_int16(get_prefixq(dst, src), 0x31);
14096 emit_operand(src, dst, 0);
14097 }
14098
14099 #endif // !LP64
14100
14101 void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) {
14102 if (VM_Version::supports_evex()) {
14103 _tuple_type = tuple_type;
14104 _input_size_in_bits = input_size_in_bits;
14105 }
14106 }