1 /*
    2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
    3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    4  *
    5  * This code is free software; you can redistribute it and/or modify it
    6  * under the terms of the GNU General Public License version 2 only, as
    7  * published by the Free Software Foundation.
    8  *
    9  * This code is distributed in the hope that it will be useful, but WITHOUT
   10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   12  * version 2 for more details (a copy is included in the LICENSE file that
   13  * accompanied this code).
   14  *
   15  * You should have received a copy of the GNU General Public License version
   16  * 2 along with this work; if not, write to the Free Software Foundation,
   17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   18  *
   19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   20  * or visit www.oracle.com if you need additional information or have any
   21  * questions.
   22  *
   23  */
   24 
   25 #include "precompiled.hpp"
   26 #include "asm/assembler.hpp"
   27 #include "asm/assembler.inline.hpp"
   28 #include "gc/shared/cardTableBarrierSet.hpp"
   29 #include "gc/shared/collectedHeap.inline.hpp"
   30 #include "interpreter/interpreter.hpp"
   31 #include "memory/resourceArea.hpp"
   32 #include "prims/methodHandles.hpp"
   33 #include "runtime/objectMonitor.hpp"
   34 #include "runtime/os.hpp"
   35 #include "runtime/sharedRuntime.hpp"
   36 #include "runtime/stubRoutines.hpp"
   37 #include "runtime/vm_version.hpp"
   38 #include "utilities/macros.hpp"
   39 
   40 #ifdef PRODUCT
   41 #define BLOCK_COMMENT(str) /* nothing */
   42 #define STOP(error) stop(error)
   43 #else
   44 #define BLOCK_COMMENT(str) block_comment(str)
   45 #define STOP(error) block_comment(error); stop(error)
   46 #endif
   47 
   48 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
   49 // Implementation of AddressLiteral
   50 
   51 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
   52 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
   53   // -----------------Table 4.5 -------------------- //
   54   16, 32, 64,  // EVEX_FV(0)
   55   4,  4,  4,   // EVEX_FV(1) - with Evex.b
   56   16, 32, 64,  // EVEX_FV(2) - with Evex.w
   57   8,  8,  8,   // EVEX_FV(3) - with Evex.w and Evex.b
   58   8,  16, 32,  // EVEX_HV(0)
   59   4,  4,  4,   // EVEX_HV(1) - with Evex.b
   60   // -----------------Table 4.6 -------------------- //
   61   16, 32, 64,  // EVEX_FVM(0)
   62   1,  1,  1,   // EVEX_T1S(0)
   63   2,  2,  2,   // EVEX_T1S(1)
   64   4,  4,  4,   // EVEX_T1S(2)
   65   8,  8,  8,   // EVEX_T1S(3)
   66   4,  4,  4,   // EVEX_T1F(0)
   67   8,  8,  8,   // EVEX_T1F(1)
   68   8,  8,  8,   // EVEX_T2(0)
   69   0,  16, 16,  // EVEX_T2(1)
   70   0,  16, 16,  // EVEX_T4(0)
   71   0,  0,  32,  // EVEX_T4(1)
   72   0,  0,  32,  // EVEX_T8(0)
   73   8,  16, 32,  // EVEX_HVM(0)
   74   4,  8,  16,  // EVEX_QVM(0)
   75   2,  4,  8,   // EVEX_OVM(0)
   76   16, 16, 16,  // EVEX_M128(0)
   77   8,  32, 64,  // EVEX_DUP(0)
   78   0,  0,  0    // EVEX_NTUP
   79 };
   80 
   81 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
   82   _is_lval = false;
   83   _target = target;
   84   switch (rtype) {
   85   case relocInfo::oop_type:
   86   case relocInfo::metadata_type:
   87     // Oops are a special case. Normally they would be their own section
   88     // but in cases like icBuffer they are literals in the code stream that
   89     // we don't have a section for. We use none so that we get a literal address
   90     // which is always patchable.
   91     break;
   92   case relocInfo::external_word_type:
   93     _rspec = external_word_Relocation::spec(target);
   94     break;
   95   case relocInfo::internal_word_type:
   96     _rspec = internal_word_Relocation::spec(target);
   97     break;
   98   case relocInfo::opt_virtual_call_type:
   99     _rspec = opt_virtual_call_Relocation::spec();
  100     break;
  101   case relocInfo::static_call_type:
  102     _rspec = static_call_Relocation::spec();
  103     break;
  104   case relocInfo::runtime_call_type:
  105     _rspec = runtime_call_Relocation::spec();
  106     break;
  107   case relocInfo::poll_type:
  108   case relocInfo::poll_return_type:
  109     _rspec = Relocation::spec_simple(rtype);
  110     break;
  111   case relocInfo::none:
  112     break;
  113   default:
  114     ShouldNotReachHere();
  115     break;
  116   }
  117 }
  118 
  119 // Implementation of Address
  120 
  121 #ifdef _LP64
  122 
  123 Address Address::make_array(ArrayAddress adr) {
  124   // Not implementable on 64bit machines
  125   // Should have been handled higher up the call chain.
  126   ShouldNotReachHere();
  127   return Address();
  128 }
  129 
  130 // exceedingly dangerous constructor
  131 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
  132   _base  = noreg;
  133   _index = noreg;
  134   _scale = no_scale;
  135   _disp  = disp;
  136   _xmmindex = xnoreg;
  137   _isxmmindex = false;
  138   switch (rtype) {
  139     case relocInfo::external_word_type:
  140       _rspec = external_word_Relocation::spec(loc);
  141       break;
  142     case relocInfo::internal_word_type:
  143       _rspec = internal_word_Relocation::spec(loc);
  144       break;
  145     case relocInfo::runtime_call_type:
  146       // HMM
  147       _rspec = runtime_call_Relocation::spec();
  148       break;
  149     case relocInfo::poll_type:
  150     case relocInfo::poll_return_type:
  151       _rspec = Relocation::spec_simple(rtype);
  152       break;
  153     case relocInfo::none:
  154       break;
  155     default:
  156       ShouldNotReachHere();
  157   }
  158 }
  159 #else // LP64
  160 
  161 Address Address::make_array(ArrayAddress adr) {
  162   AddressLiteral base = adr.base();
  163   Address index = adr.index();
  164   assert(index._disp == 0, "must not have disp"); // maybe it can?
  165   Address array(index._base, index._index, index._scale, (intptr_t) base.target());
  166   array._rspec = base._rspec;
  167   return array;
  168 }
  169 
  170 // exceedingly dangerous constructor
  171 Address::Address(address loc, RelocationHolder spec) {
  172   _base  = noreg;
  173   _index = noreg;
  174   _scale = no_scale;
  175   _disp  = (intptr_t) loc;
  176   _rspec = spec;
  177   _xmmindex = xnoreg;
  178   _isxmmindex = false;
  179 }
  180 
  181 #endif // _LP64
  182 
  183 
  184 
  185 // Convert the raw encoding form into the form expected by the constructor for
  186 // Address.  An index of 4 (rsp) corresponds to having no index, so convert
  187 // that to noreg for the Address constructor.
  188 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
  189   RelocationHolder rspec = RelocationHolder::none;
  190   if (disp_reloc != relocInfo::none) {
  191     rspec = Relocation::spec_simple(disp_reloc);
  192   }
  193   bool valid_index = index != rsp->encoding();
  194   if (valid_index) {
  195     Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
  196     madr._rspec = rspec;
  197     return madr;
  198   } else {
  199     Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
  200     madr._rspec = rspec;
  201     return madr;
  202   }
  203 }
  204 
  205 // Implementation of Assembler
  206 
  207 int AbstractAssembler::code_fill_byte() {
  208   return (u_char)'\xF4'; // hlt
  209 }
  210 
  211 void Assembler::init_attributes(void) {
  212   _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
  213   _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
  214   _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
  215   _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
  216   NOT_LP64(_is_managed = false;)
  217   _attributes = NULL;
  218 }
  219 
  220 
  221 void Assembler::membar(Membar_mask_bits order_constraint) {
  222   // We only have to handle StoreLoad
  223   if (order_constraint & StoreLoad) {
  224     // All usable chips support "locked" instructions which suffice
  225     // as barriers, and are much faster than the alternative of
  226     // using cpuid instruction. We use here a locked add [esp-C],0.
  227     // This is conveniently otherwise a no-op except for blowing
  228     // flags, and introducing a false dependency on target memory
  229     // location. We can't do anything with flags, but we can avoid
  230     // memory dependencies in the current method by locked-adding
  231     // somewhere else on the stack. Doing [esp+C] will collide with
  232     // something on stack in current method, hence we go for [esp-C].
  233     // It is convenient since it is almost always in data cache, for
  234     // any small C.  We need to step back from SP to avoid data
  235     // dependencies with other things on below SP (callee-saves, for
  236     // example). Without a clear way to figure out the minimal safe
  237     // distance from SP, it makes sense to step back the complete
  238     // cache line, as this will also avoid possible second-order effects
  239     // with locked ops against the cache line. Our choice of offset
  240     // is bounded by x86 operand encoding, which should stay within
  241     // [-128; +127] to have the 8-byte displacement encoding.
  242     //
  243     // Any change to this code may need to revisit other places in
  244     // the code where this idiom is used, in particular the
  245     // orderAccess code.
  246 
  247     int offset = -VM_Version::L1_line_size();
  248     if (offset < -128) {
  249       offset = -128;
  250     }
  251 
  252     lock();
  253     addl(Address(rsp, offset), 0);// Assert the lock# signal here
  254   }
  255 }
  256 
  257 // make this go away someday
  258 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
  259   if (rtype == relocInfo::none)
  260     emit_int32(data);
  261   else
  262     emit_data(data, Relocation::spec_simple(rtype), format);
  263 }
  264 
  265 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
  266   assert(imm_operand == 0, "default format must be immediate in this file");
  267   assert(inst_mark() != NULL, "must be inside InstructionMark");
  268   if (rspec.type() !=  relocInfo::none) {
  269     #ifdef ASSERT
  270       check_relocation(rspec, format);
  271     #endif
  272     // Do not use AbstractAssembler::relocate, which is not intended for
  273     // embedded words.  Instead, relocate to the enclosing instruction.
  274 
  275     // hack. call32 is too wide for mask so use disp32
  276     if (format == call32_operand)
  277       code_section()->relocate(inst_mark(), rspec, disp32_operand);
  278     else
  279       code_section()->relocate(inst_mark(), rspec, format);
  280   }
  281   emit_int32(data);
  282 }
  283 
  284 static int encode(Register r) {
  285   int enc = r->encoding();
  286   if (enc >= 8) {
  287     enc -= 8;
  288   }
  289   return enc;
  290 }
  291 
  292 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
  293   assert(dst->has_byte_register(), "must have byte register");
  294   assert(isByte(op1) && isByte(op2), "wrong opcode");
  295   assert(isByte(imm8), "not a byte");
  296   assert((op1 & 0x01) == 0, "should be 8bit operation");
  297   emit_int24(op1, (op2 | encode(dst)), imm8);
  298 }
  299 
  300 
  301 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
  302   assert(isByte(op1) && isByte(op2), "wrong opcode");
  303   assert(op1 == 0x81, "Unexpected opcode");
  304   if (is8bit(imm32)) {
  305     emit_int24(op1 | 0x02,        // set sign bit
  306                op2 | encode(dst),
  307                imm32 & 0xFF);
  308   } else if (dst == rax) {
  309     switch (op2) {
  310       case 0xD0: emit_int8(0x15); break; // adc
  311       case 0xC0: emit_int8(0x05); break; // add
  312       case 0xE0: emit_int8(0x25); break; // and
  313       case 0xF8: emit_int8(0x3D); break; // cmp
  314       case 0xC8: emit_int8(0x0D); break; // or
  315       case 0xD8: emit_int8(0x1D); break; // sbb
  316       case 0xE8: emit_int8(0x2D); break; // sub
  317       case 0xF0: emit_int8(0x35); break; // xor
  318       default: ShouldNotReachHere();
  319     }
  320     emit_int32(imm32);
  321   } else {
  322     emit_int16(op1, (op2 | encode(dst)));
  323     emit_int32(imm32);
  324   }
  325 }
  326 
  327 // Force generation of a 4 byte immediate value even if it fits into 8bit
  328 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
  329   assert(isByte(op1) && isByte(op2), "wrong opcode");
  330   assert((op1 & 0x01) == 1, "should be 32bit operation");
  331   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
  332   emit_int16(op1, (op2 | encode(dst)));
  333   emit_int32(imm32);
  334 }
  335 
  336 // immediate-to-memory forms
  337 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
  338   assert((op1 & 0x01) == 1, "should be 32bit operation");
  339   assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
  340   if (is8bit(imm32)) {
  341     emit_int8(op1 | 0x02); // set sign bit
  342     emit_operand(rm, adr, 1);
  343     emit_int8(imm32 & 0xFF);
  344   } else {
  345     emit_int8(op1);
  346     emit_operand(rm, adr, 4);
  347     emit_int32(imm32);
  348   }
  349 }
  350 
  351 
  352 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
  353   assert(isByte(op1) && isByte(op2), "wrong opcode");
  354   emit_int16(op1, (op2 | encode(dst) << 3 | encode(src)));
  355 }
  356 
  357 
  358 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
  359                                            int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
  360   int mod_idx = 0;
  361   // We will test if the displacement fits the compressed format and if so
  362   // apply the compression to the displacement iff the result is8bit.
  363   if (VM_Version::supports_evex() && is_evex_inst) {
  364     switch (cur_tuple_type) {
  365     case EVEX_FV:
  366       if ((cur_encoding & VEX_W) == VEX_W) {
  367         mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
  368       } else {
  369         mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
  370       }
  371       break;
  372 
  373     case EVEX_HV:
  374       mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
  375       break;
  376 
  377     case EVEX_FVM:
  378       break;
  379 
  380     case EVEX_T1S:
  381       switch (in_size_in_bits) {
  382       case EVEX_8bit:
  383         break;
  384 
  385       case EVEX_16bit:
  386         mod_idx = 1;
  387         break;
  388 
  389       case EVEX_32bit:
  390         mod_idx = 2;
  391         break;
  392 
  393       case EVEX_64bit:
  394         mod_idx = 3;
  395         break;
  396       }
  397       break;
  398 
  399     case EVEX_T1F:
  400     case EVEX_T2:
  401     case EVEX_T4:
  402       mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
  403       break;
  404 
  405     case EVEX_T8:
  406       break;
  407 
  408     case EVEX_HVM:
  409       break;
  410 
  411     case EVEX_QVM:
  412       break;
  413 
  414     case EVEX_OVM:
  415       break;
  416 
  417     case EVEX_M128:
  418       break;
  419 
  420     case EVEX_DUP:
  421       break;
  422 
  423     default:
  424       assert(0, "no valid evex tuple_table entry");
  425       break;
  426     }
  427 
  428     if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
  429       int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
  430       if ((disp % disp_factor) == 0) {
  431         int new_disp = disp / disp_factor;
  432         if ((-0x80 <= new_disp && new_disp < 0x80)) {
  433           disp = new_disp;
  434         }
  435       } else {
  436         return false;
  437       }
  438     }
  439   }
  440   return (-0x80 <= disp && disp < 0x80);
  441 }
  442 
  443 
  444 bool Assembler::emit_compressed_disp_byte(int &disp) {
  445   int mod_idx = 0;
  446   // We will test if the displacement fits the compressed format and if so
  447   // apply the compression to the displacement iff the result is8bit.
  448   if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
  449     int evex_encoding = _attributes->get_evex_encoding();
  450     int tuple_type = _attributes->get_tuple_type();
  451     switch (tuple_type) {
  452     case EVEX_FV:
  453       if ((evex_encoding & VEX_W) == VEX_W) {
  454         mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
  455       } else {
  456         mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
  457       }
  458       break;
  459 
  460     case EVEX_HV:
  461       mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
  462       break;
  463 
  464     case EVEX_FVM:
  465       break;
  466 
  467     case EVEX_T1S:
  468       switch (_attributes->get_input_size()) {
  469       case EVEX_8bit:
  470         break;
  471 
  472       case EVEX_16bit:
  473         mod_idx = 1;
  474         break;
  475 
  476       case EVEX_32bit:
  477         mod_idx = 2;
  478         break;
  479 
  480       case EVEX_64bit:
  481         mod_idx = 3;
  482         break;
  483       }
  484       break;
  485 
  486     case EVEX_T1F:
  487     case EVEX_T2:
  488     case EVEX_T4:
  489       mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
  490       break;
  491 
  492     case EVEX_T8:
  493       break;
  494 
  495     case EVEX_HVM:
  496       break;
  497 
  498     case EVEX_QVM:
  499       break;
  500 
  501     case EVEX_OVM:
  502       break;
  503 
  504     case EVEX_M128:
  505       break;
  506 
  507     case EVEX_DUP:
  508       break;
  509 
  510     default:
  511       assert(0, "no valid evex tuple_table entry");
  512       break;
  513     }
  514 
  515     int vector_len = _attributes->get_vector_len();
  516     if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
  517       int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
  518       if ((disp % disp_factor) == 0) {
  519         int new_disp = disp / disp_factor;
  520         if (is8bit(new_disp)) {
  521           disp = new_disp;
  522         }
  523       } else {
  524         return false;
  525       }
  526     }
  527   }
  528   return is8bit(disp);
  529 }
  530 
  531 static bool is_valid_encoding(int reg_enc) {
  532   return reg_enc >= 0;
  533 }
  534 
  535 static int raw_encode(Register reg) {
  536   assert(reg == noreg || reg->is_valid(), "sanity");
  537   int reg_enc = (intptr_t)reg;
  538   assert(reg_enc == -1 || is_valid_encoding(reg_enc), "sanity");
  539   return reg_enc;
  540 }
  541 
  542 static int raw_encode(XMMRegister xmmreg) {
  543   assert(xmmreg == xnoreg || xmmreg->is_valid(), "sanity");
  544   int xmmreg_enc = (intptr_t)xmmreg;
  545   assert(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc), "sanity");
  546   return xmmreg_enc;
  547 }
  548 
  549 static int modrm_encoding(int mod, int dst_enc, int src_enc) {
  550   return (mod & 3) << 6 | (dst_enc & 7) << 3 | (src_enc & 7);
  551 }
  552 
  553 static int sib_encoding(Address::ScaleFactor scale, int index_enc, int base_enc) {
  554   return (scale & 3) << 6 | (index_enc & 7) << 3 | (base_enc & 7);
  555 }
  556 
  557 inline void Assembler::emit_modrm(int mod, int dst_enc, int src_enc) {
  558   assert((mod & 3) != 0b11, "forbidden");
  559   int modrm = modrm_encoding(mod, dst_enc, src_enc);
  560   emit_int8(modrm);
  561 }
  562 
  563 inline void Assembler::emit_modrm_disp8(int mod, int dst_enc, int src_enc,
  564                                         int disp) {
  565   int modrm = modrm_encoding(mod, dst_enc, src_enc);
  566   emit_int16(modrm, disp & 0xFF);
  567 }
  568 
  569 inline void Assembler::emit_modrm_sib(int mod, int dst_enc, int src_enc,
  570                                       Address::ScaleFactor scale, int index_enc, int base_enc) {
  571   int modrm = modrm_encoding(mod, dst_enc, src_enc);
  572   int sib = sib_encoding(scale, index_enc, base_enc);
  573   emit_int16(modrm, sib);
  574 }
  575 
  576 inline void Assembler::emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
  577                                             Address::ScaleFactor scale, int index_enc, int base_enc,
  578                                             int disp) {
  579   int modrm = modrm_encoding(mod, dst_enc, src_enc);
  580   int sib = sib_encoding(scale, index_enc, base_enc);
  581   emit_int24(modrm, sib, disp & 0xFF);
  582 }
  583 
  584 void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc,
  585                                     Address::ScaleFactor scale, int disp,
  586                                     RelocationHolder const& rspec,
  587                                     int rip_relative_correction) {
  588   bool no_relocation = (rspec.type() == relocInfo::none);
  589 
  590   if (is_valid_encoding(base_enc)) {
  591     if (is_valid_encoding(index_enc)) {
  592       assert(scale != Address::no_scale, "inconsistent address");
  593       // [base + index*scale + disp]
  594       if (disp == 0 && no_relocation &&
  595           base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
  596         // [base + index*scale]
  597         // [00 reg 100][ss index base]
  598         emit_modrm_sib(0b00, reg_enc, 0b100,
  599                        scale, index_enc, base_enc);
  600       } else if (emit_compressed_disp_byte(disp) && no_relocation) {
  601         // [base + index*scale + imm8]
  602         // [01 reg 100][ss index base] imm8
  603         emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
  604                              scale, index_enc, base_enc,
  605                              disp);
  606       } else {
  607         // [base + index*scale + disp32]
  608         // [10 reg 100][ss index base] disp32
  609         emit_modrm_sib(0b10, reg_enc, 0b100,
  610                        scale, index_enc, base_enc);
  611         emit_data(disp, rspec, disp32_operand);
  612       }
  613     } else if (base_enc == rsp->encoding() LP64_ONLY(|| base_enc == r12->encoding())) {
  614       // [rsp + disp]
  615       if (disp == 0 && no_relocation) {
  616         // [rsp]
  617         // [00 reg 100][00 100 100]
  618         emit_modrm_sib(0b00, reg_enc, 0b100,
  619                        Address::times_1, 0b100, 0b100);
  620       } else if (emit_compressed_disp_byte(disp) && no_relocation) {
  621         // [rsp + imm8]
  622         // [01 reg 100][00 100 100] disp8
  623         emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
  624                              Address::times_1, 0b100, 0b100,
  625                              disp);
  626       } else {
  627         // [rsp + imm32]
  628         // [10 reg 100][00 100 100] disp32
  629         emit_modrm_sib(0b10, reg_enc, 0b100,
  630                        Address::times_1, 0b100, 0b100);
  631         emit_data(disp, rspec, disp32_operand);
  632       }
  633     } else {
  634       // [base + disp]
  635       assert(base_enc != rsp->encoding() LP64_ONLY(&& base_enc != r12->encoding()), "illegal addressing mode");
  636       if (disp == 0 && no_relocation &&
  637           base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
  638         // [base]
  639         // [00 reg base]
  640         emit_modrm(0, reg_enc, base_enc);
  641       } else if (emit_compressed_disp_byte(disp) && no_relocation) {
  642         // [base + disp8]
  643         // [01 reg base] disp8
  644         emit_modrm_disp8(0b01, reg_enc, base_enc,
  645                          disp);
  646       } else {
  647         // [base + disp32]
  648         // [10 reg base] disp32
  649         emit_modrm(0b10, reg_enc, base_enc);
  650         emit_data(disp, rspec, disp32_operand);
  651       }
  652     }
  653   } else {
  654     if (is_valid_encoding(index_enc)) {
  655       assert(scale != Address::no_scale, "inconsistent address");
  656       // base == noreg
  657       // [index*scale + disp]
  658       // [00 reg 100][ss index 101] disp32
  659       emit_modrm_sib(0b00, reg_enc, 0b100,
  660                      scale, index_enc, 0b101 /* no base */);
  661       emit_data(disp, rspec, disp32_operand);
  662     } else if (!no_relocation) {
  663       // base == noreg, index == noreg
  664       // [disp] (64bit) RIP-RELATIVE (32bit) abs
  665       // [00 reg 101] disp32
  666 
  667       emit_modrm(0b00, reg_enc, 0b101 /* no base */);
  668       // Note that the RIP-rel. correction applies to the generated
  669       // disp field, but _not_ to the target address in the rspec.
  670 
  671       // disp was created by converting the target address minus the pc
  672       // at the start of the instruction. That needs more correction here.
  673       // intptr_t disp = target - next_ip;
  674       assert(inst_mark() != NULL, "must be inside InstructionMark");
  675       address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
  676       int64_t adjusted = disp;
  677       // Do rip-rel adjustment for 64bit
  678       LP64_ONLY(adjusted -=  (next_ip - inst_mark()));
  679       assert(is_simm32(adjusted),
  680              "must be 32bit offset (RIP relative address)");
  681       emit_data((int32_t) adjusted, rspec, disp32_operand);
  682 
  683     } else {
  684       // base == noreg, index == noreg, no_relocation == true
  685       // 32bit never did this, did everything as the rip-rel/disp code above
  686       // [disp] ABSOLUTE
  687       // [00 reg 100][00 100 101] disp32
  688       emit_modrm_sib(0b00, reg_enc, 0b100 /* no base */,
  689                      Address::times_1, 0b100, 0b101);
  690       emit_data(disp, rspec, disp32_operand);
  691     }
  692   }
  693 }
  694 
  695 void Assembler::emit_operand(Register reg, Register base, Register index,
  696                              Address::ScaleFactor scale, int disp,
  697                              RelocationHolder const& rspec,
  698                              int rip_relative_correction) {
  699   assert(!index->is_valid() || index != rsp, "illegal addressing mode");
  700   emit_operand_helper(raw_encode(reg), raw_encode(base), raw_encode(index),
  701                       scale, disp, rspec, rip_relative_correction);
  702 
  703 }
  704 void Assembler::emit_operand(XMMRegister xmmreg, Register base, Register index,
  705                              Address::ScaleFactor scale, int disp,
  706                              RelocationHolder const& rspec) {
  707   assert(!index->is_valid() || index != rsp, "illegal addressing mode");
  708   assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
  709   emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(index),
  710                       scale, disp, rspec);
  711 }
  712 
  713 void Assembler::emit_operand(XMMRegister xmmreg, Register base, XMMRegister xmmindex,
  714                              Address::ScaleFactor scale, int disp,
  715                              RelocationHolder const& rspec) {
  716   assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
  717   assert(xmmindex->encoding() < 16 || UseAVX > 2, "not supported");
  718   emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(xmmindex),
  719                       scale, disp, rspec, /* rip_relative_correction */ 0);
  720 }
  721 
  722 // Secret local extension to Assembler::WhichOperand:
  723 #define end_pc_operand (_WhichOperand_limit)
  724 
  725 address Assembler::locate_operand(address inst, WhichOperand which) {
  726   // Decode the given instruction, and return the address of
  727   // an embedded 32-bit operand word.
  728 
  729   // If "which" is disp32_operand, selects the displacement portion
  730   // of an effective address specifier.
  731   // If "which" is imm64_operand, selects the trailing immediate constant.
  732   // If "which" is call32_operand, selects the displacement of a call or jump.
  733   // Caller is responsible for ensuring that there is such an operand,
  734   // and that it is 32/64 bits wide.
  735 
  736   // If "which" is end_pc_operand, find the end of the instruction.
  737 
  738   address ip = inst;
  739   bool is_64bit = false;
  740 
  741   debug_only(bool has_disp32 = false);
  742   int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
  743 
  744   again_after_prefix:
  745   switch (0xFF & *ip++) {
  746 
  747   // These convenience macros generate groups of "case" labels for the switch.
  748 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
  749 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
  750              case (x)+4: case (x)+5: case (x)+6: case (x)+7
  751 #define REP16(x) REP8((x)+0): \
  752               case REP8((x)+8)
  753 
  754   case CS_segment:
  755   case SS_segment:
  756   case DS_segment:
  757   case ES_segment:
  758   case FS_segment:
  759   case GS_segment:
  760     // Seems dubious
  761     LP64_ONLY(assert(false, "shouldn't have that prefix"));
  762     assert(ip == inst+1, "only one prefix allowed");
  763     goto again_after_prefix;
  764 
  765   case 0x67:
  766   case REX:
  767   case REX_B:
  768   case REX_X:
  769   case REX_XB:
  770   case REX_R:
  771   case REX_RB:
  772   case REX_RX:
  773   case REX_RXB:
  774     NOT_LP64(assert(false, "64bit prefixes"));
  775     goto again_after_prefix;
  776 
  777   case REX_W:
  778   case REX_WB:
  779   case REX_WX:
  780   case REX_WXB:
  781   case REX_WR:
  782   case REX_WRB:
  783   case REX_WRX:
  784   case REX_WRXB:
  785     NOT_LP64(assert(false, "64bit prefixes"));
  786     is_64bit = true;
  787     goto again_after_prefix;
  788 
  789   case 0xFF: // pushq a; decl a; incl a; call a; jmp a
  790   case 0x88: // movb a, r
  791   case 0x89: // movl a, r
  792   case 0x8A: // movb r, a
  793   case 0x8B: // movl r, a
  794   case 0x8F: // popl a
  795     debug_only(has_disp32 = true);
  796     break;
  797 
  798   case 0x68: // pushq #32
  799     if (which == end_pc_operand) {
  800       return ip + 4;
  801     }
  802     assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
  803     return ip;                  // not produced by emit_operand
  804 
  805   case 0x66: // movw ... (size prefix)
  806     again_after_size_prefix2:
  807     switch (0xFF & *ip++) {
  808     case REX:
  809     case REX_B:
  810     case REX_X:
  811     case REX_XB:
  812     case REX_R:
  813     case REX_RB:
  814     case REX_RX:
  815     case REX_RXB:
  816     case REX_W:
  817     case REX_WB:
  818     case REX_WX:
  819     case REX_WXB:
  820     case REX_WR:
  821     case REX_WRB:
  822     case REX_WRX:
  823     case REX_WRXB:
  824       NOT_LP64(assert(false, "64bit prefix found"));
  825       goto again_after_size_prefix2;
  826     case 0x8B: // movw r, a
  827     case 0x89: // movw a, r
  828       debug_only(has_disp32 = true);
  829       break;
  830     case 0xC7: // movw a, #16
  831       debug_only(has_disp32 = true);
  832       tail_size = 2;  // the imm16
  833       break;
  834     case 0x0F: // several SSE/SSE2 variants
  835       ip--;    // reparse the 0x0F
  836       goto again_after_prefix;
  837     default:
  838       ShouldNotReachHere();
  839     }
  840     break;
  841 
  842   case REP8(0xB8): // movl/q r, #32/#64(oop?)
  843     if (which == end_pc_operand)  return ip + (is_64bit ? 8 : 4);
  844     // these asserts are somewhat nonsensical
  845 #ifndef _LP64
  846     assert(which == imm_operand || which == disp32_operand,
  847            "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
  848 #else
  849     assert((which == call32_operand || which == imm_operand) && is_64bit ||
  850            which == narrow_oop_operand && !is_64bit,
  851            "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
  852 #endif // _LP64
  853     return ip;
  854 
  855   case 0x69: // imul r, a, #32
  856   case 0xC7: // movl a, #32(oop?)
  857     tail_size = 4;
  858     debug_only(has_disp32 = true); // has both kinds of operands!
  859     break;
  860 
  861   case 0x0F: // movx..., etc.
  862     switch (0xFF & *ip++) {
  863     case 0x3A: // pcmpestri
  864       tail_size = 1;
  865     case 0x38: // ptest, pmovzxbw
  866       ip++; // skip opcode
  867       debug_only(has_disp32 = true); // has both kinds of operands!
  868       break;
  869 
  870     case 0x70: // pshufd r, r/a, #8
  871       debug_only(has_disp32 = true); // has both kinds of operands!
  872     case 0x73: // psrldq r, #8
  873       tail_size = 1;
  874       break;
  875 
  876     case 0x12: // movlps
  877     case 0x28: // movaps
  878     case 0x2E: // ucomiss
  879     case 0x2F: // comiss
  880     case 0x54: // andps
  881     case 0x55: // andnps
  882     case 0x56: // orps
  883     case 0x57: // xorps
  884     case 0x58: // addpd
  885     case 0x59: // mulpd
  886     case 0x6E: // movd
  887     case 0x7E: // movd
  888     case 0x6F: // movdq
  889     case 0x7F: // movdq
  890     case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
  891     case 0xFE: // paddd
  892       debug_only(has_disp32 = true);
  893       break;
  894 
  895     case 0xAD: // shrd r, a, %cl
  896     case 0xAF: // imul r, a
  897     case 0xBE: // movsbl r, a (movsxb)
  898     case 0xBF: // movswl r, a (movsxw)
  899     case 0xB6: // movzbl r, a (movzxb)
  900     case 0xB7: // movzwl r, a (movzxw)
  901     case REP16(0x40): // cmovl cc, r, a
  902     case 0xB0: // cmpxchgb
  903     case 0xB1: // cmpxchg
  904     case 0xC1: // xaddl
  905     case 0xC7: // cmpxchg8
  906     case REP16(0x90): // setcc a
  907       debug_only(has_disp32 = true);
  908       // fall out of the switch to decode the address
  909       break;
  910 
  911     case 0xC4: // pinsrw r, a, #8
  912       debug_only(has_disp32 = true);
  913     case 0xC5: // pextrw r, r, #8
  914       tail_size = 1;  // the imm8
  915       break;
  916 
  917     case 0xAC: // shrd r, a, #8
  918       debug_only(has_disp32 = true);
  919       tail_size = 1;  // the imm8
  920       break;
  921 
  922     case REP16(0x80): // jcc rdisp32
  923       if (which == end_pc_operand)  return ip + 4;
  924       assert(which == call32_operand, "jcc has no disp32 or imm");
  925       return ip;
  926     default:
  927       ShouldNotReachHere();
  928     }
  929     break;
  930 
  931   case 0x81: // addl a, #32; addl r, #32
  932     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
  933     // on 32bit in the case of cmpl, the imm might be an oop
  934     tail_size = 4;
  935     debug_only(has_disp32 = true); // has both kinds of operands!
  936     break;
  937 
  938   case 0x83: // addl a, #8; addl r, #8
  939     // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
  940     debug_only(has_disp32 = true); // has both kinds of operands!
  941     tail_size = 1;
  942     break;
  943 
  944   case 0x15: // adc rax, #32
  945   case 0x05: // add rax, #32
  946   case 0x25: // and rax, #32
  947   case 0x3D: // cmp rax, #32
  948   case 0x0D: // or  rax, #32
  949   case 0x1D: // sbb rax, #32
  950   case 0x2D: // sub rax, #32
  951   case 0x35: // xor rax, #32
  952     return which == end_pc_operand ? ip + 4 : ip;
  953 
  954   case 0x9B:
  955     switch (0xFF & *ip++) {
  956     case 0xD9: // fnstcw a
  957       debug_only(has_disp32 = true);
  958       break;
  959     default:
  960       ShouldNotReachHere();
  961     }
  962     break;
  963 
  964   case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
  965   case REP4(0x10): // adc...
  966   case REP4(0x20): // and...
  967   case REP4(0x30): // xor...
  968   case REP4(0x08): // or...
  969   case REP4(0x18): // sbb...
  970   case REP4(0x28): // sub...
  971   case 0xF7: // mull a
  972   case 0x8D: // lea r, a
  973   case 0x87: // xchg r, a
  974   case REP4(0x38): // cmp...
  975   case 0x85: // test r, a
  976     debug_only(has_disp32 = true); // has both kinds of operands!
  977     break;
  978 
  979   case 0xA8: // testb rax, #8
  980     return which == end_pc_operand ? ip + 1 : ip;
  981   case 0xA9: // testl/testq rax, #32
  982     return which == end_pc_operand ? ip + 4 : ip;
  983 
  984   case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
  985   case 0xC6: // movb a, #8
  986   case 0x80: // cmpb a, #8
  987   case 0x6B: // imul r, a, #8
  988     debug_only(has_disp32 = true); // has both kinds of operands!
  989     tail_size = 1; // the imm8
  990     break;
  991 
  992   case 0xC4: // VEX_3bytes
  993   case 0xC5: // VEX_2bytes
  994     assert((UseAVX > 0), "shouldn't have VEX prefix");
  995     assert(ip == inst+1, "no prefixes allowed");
  996     // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
  997     // but they have prefix 0x0F and processed when 0x0F processed above.
  998     //
  999     // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
 1000     // instructions (these instructions are not supported in 64-bit mode).
 1001     // To distinguish them bits [7:6] are set in the VEX second byte since
 1002     // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
 1003     // those VEX bits REX and vvvv bits are inverted.
 1004     //
 1005     // Fortunately C2 doesn't generate these instructions so we don't need
 1006     // to check for them in product version.
 1007 
 1008     // Check second byte
 1009     NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
 1010 
 1011     int vex_opcode;
 1012     // First byte
 1013     if ((0xFF & *inst) == VEX_3bytes) {
 1014       vex_opcode = VEX_OPCODE_MASK & *ip;
 1015       ip++; // third byte
 1016       is_64bit = ((VEX_W & *ip) == VEX_W);
 1017     } else {
 1018       vex_opcode = VEX_OPCODE_0F;
 1019     }
 1020     ip++; // opcode
 1021     // To find the end of instruction (which == end_pc_operand).
 1022     switch (vex_opcode) {
 1023       case VEX_OPCODE_0F:
 1024         switch (0xFF & *ip) {
 1025         case 0x70: // pshufd r, r/a, #8
 1026         case 0x71: // ps[rl|ra|ll]w r, #8
 1027         case 0x72: // ps[rl|ra|ll]d r, #8
 1028         case 0x73: // ps[rl|ra|ll]q r, #8
 1029         case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
 1030         case 0xC4: // pinsrw r, r, r/a, #8
 1031         case 0xC5: // pextrw r/a, r, #8
 1032         case 0xC6: // shufp[s|d] r, r, r/a, #8
 1033           tail_size = 1;  // the imm8
 1034           break;
 1035         }
 1036         break;
 1037       case VEX_OPCODE_0F_3A:
 1038         tail_size = 1;
 1039         break;
 1040     }
 1041     ip++; // skip opcode
 1042     debug_only(has_disp32 = true); // has both kinds of operands!
 1043     break;
 1044 
 1045   case 0x62: // EVEX_4bytes
 1046     assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
 1047     assert(ip == inst+1, "no prefixes allowed");
 1048     // no EVEX collisions, all instructions that have 0x62 opcodes
 1049     // have EVEX versions and are subopcodes of 0x66
 1050     ip++; // skip P0 and examine W in P1
 1051     is_64bit = ((VEX_W & *ip) == VEX_W);
 1052     ip++; // move to P2
 1053     ip++; // skip P2, move to opcode
 1054     // To find the end of instruction (which == end_pc_operand).
 1055     switch (0xFF & *ip) {
 1056     case 0x22: // pinsrd r, r/a, #8
 1057     case 0x61: // pcmpestri r, r/a, #8
 1058     case 0x70: // pshufd r, r/a, #8
 1059     case 0x73: // psrldq r, #8
 1060     case 0x1f: // evpcmpd/evpcmpq
 1061     case 0x3f: // evpcmpb/evpcmpw
 1062       tail_size = 1;  // the imm8
 1063       break;
 1064     default:
 1065       break;
 1066     }
 1067     ip++; // skip opcode
 1068     debug_only(has_disp32 = true); // has both kinds of operands!
 1069     break;
 1070 
 1071   case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
 1072   case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
 1073   case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
 1074   case 0xDD: // fld_d a; fst_d a; fstp_d a
 1075   case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
 1076   case 0xDF: // fild_d a; fistp_d a
 1077   case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
 1078   case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
 1079   case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
 1080     debug_only(has_disp32 = true);
 1081     break;
 1082 
 1083   case 0xE8: // call rdisp32
 1084   case 0xE9: // jmp  rdisp32
 1085     if (which == end_pc_operand)  return ip + 4;
 1086     assert(which == call32_operand, "call has no disp32 or imm");
 1087     return ip;
 1088 
 1089   case 0xF0:                    // Lock
 1090     goto again_after_prefix;
 1091 
 1092   case 0xF3:                    // For SSE
 1093   case 0xF2:                    // For SSE2
 1094     switch (0xFF & *ip++) {
 1095     case REX:
 1096     case REX_B:
 1097     case REX_X:
 1098     case REX_XB:
 1099     case REX_R:
 1100     case REX_RB:
 1101     case REX_RX:
 1102     case REX_RXB:
 1103     case REX_W:
 1104     case REX_WB:
 1105     case REX_WX:
 1106     case REX_WXB:
 1107     case REX_WR:
 1108     case REX_WRB:
 1109     case REX_WRX:
 1110     case REX_WRXB:
 1111       NOT_LP64(assert(false, "found 64bit prefix"));
 1112       ip++;
 1113     default:
 1114       ip++;
 1115     }
 1116     debug_only(has_disp32 = true); // has both kinds of operands!
 1117     break;
 1118 
 1119   default:
 1120     ShouldNotReachHere();
 1121 
 1122 #undef REP8
 1123 #undef REP16
 1124   }
 1125 
 1126   assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
 1127 #ifdef _LP64
 1128   assert(which != imm_operand, "instruction is not a movq reg, imm64");
 1129 #else
 1130   // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
 1131   assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
 1132 #endif // LP64
 1133   assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
 1134 
 1135   // parse the output of emit_operand
 1136   int op2 = 0xFF & *ip++;
 1137   int base = op2 & 0x07;
 1138   int op3 = -1;
 1139   const int b100 = 4;
 1140   const int b101 = 5;
 1141   if (base == b100 && (op2 >> 6) != 3) {
 1142     op3 = 0xFF & *ip++;
 1143     base = op3 & 0x07;   // refetch the base
 1144   }
 1145   // now ip points at the disp (if any)
 1146 
 1147   switch (op2 >> 6) {
 1148   case 0:
 1149     // [00 reg  100][ss index base]
 1150     // [00 reg  100][00   100  esp]
 1151     // [00 reg base]
 1152     // [00 reg  100][ss index  101][disp32]
 1153     // [00 reg  101]               [disp32]
 1154 
 1155     if (base == b101) {
 1156       if (which == disp32_operand)
 1157         return ip;              // caller wants the disp32
 1158       ip += 4;                  // skip the disp32
 1159     }
 1160     break;
 1161 
 1162   case 1:
 1163     // [01 reg  100][ss index base][disp8]
 1164     // [01 reg  100][00   100  esp][disp8]
 1165     // [01 reg base]               [disp8]
 1166     ip += 1;                    // skip the disp8
 1167     break;
 1168 
 1169   case 2:
 1170     // [10 reg  100][ss index base][disp32]
 1171     // [10 reg  100][00   100  esp][disp32]
 1172     // [10 reg base]               [disp32]
 1173     if (which == disp32_operand)
 1174       return ip;                // caller wants the disp32
 1175     ip += 4;                    // skip the disp32
 1176     break;
 1177 
 1178   case 3:
 1179     // [11 reg base]  (not a memory addressing mode)
 1180     break;
 1181   }
 1182 
 1183   if (which == end_pc_operand) {
 1184     return ip + tail_size;
 1185   }
 1186 
 1187 #ifdef _LP64
 1188   assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
 1189 #else
 1190   assert(which == imm_operand, "instruction has only an imm field");
 1191 #endif // LP64
 1192   return ip;
 1193 }
 1194 
 1195 address Assembler::locate_next_instruction(address inst) {
 1196   // Secretly share code with locate_operand:
 1197   return locate_operand(inst, end_pc_operand);
 1198 }
 1199 
 1200 
 1201 #ifdef ASSERT
 1202 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
 1203   address inst = inst_mark();
 1204   assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
 1205   address opnd;
 1206 
 1207   Relocation* r = rspec.reloc();
 1208   if (r->type() == relocInfo::none) {
 1209     return;
 1210   } else if (r->is_call() || format == call32_operand) {
 1211     // assert(format == imm32_operand, "cannot specify a nonzero format");
 1212     opnd = locate_operand(inst, call32_operand);
 1213   } else if (r->is_data()) {
 1214     assert(format == imm_operand || format == disp32_operand
 1215            LP64_ONLY(|| format == narrow_oop_operand), "format ok");
 1216     opnd = locate_operand(inst, (WhichOperand)format);
 1217   } else {
 1218     assert(format == imm_operand, "cannot specify a format");
 1219     return;
 1220   }
 1221   assert(opnd == pc(), "must put operand where relocs can find it");
 1222 }
 1223 #endif // ASSERT
 1224 
 1225 void Assembler::emit_operand(Register reg, Address adr,
 1226                              int rip_relative_correction) {
 1227   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
 1228                adr._rspec,
 1229                rip_relative_correction);
 1230 }
 1231 
 1232 void Assembler::emit_operand(XMMRegister reg, Address adr) {
 1233     if (adr.isxmmindex()) {
 1234        emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec);
 1235     } else {
 1236        emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
 1237        adr._rspec);
 1238     }
 1239 }
 1240 
 1241 // Now the Assembler instructions (identical for 32/64 bits)
 1242 
 1243 void Assembler::adcl(Address dst, int32_t imm32) {
 1244   InstructionMark im(this);
 1245   prefix(dst);
 1246   emit_arith_operand(0x81, rdx, dst, imm32);
 1247 }
 1248 
 1249 void Assembler::adcl(Address dst, Register src) {
 1250   InstructionMark im(this);
 1251   prefix(dst, src);
 1252   emit_int8(0x11);
 1253   emit_operand(src, dst);
 1254 }
 1255 
 1256 void Assembler::adcl(Register dst, int32_t imm32) {
 1257   prefix(dst);
 1258   emit_arith(0x81, 0xD0, dst, imm32);
 1259 }
 1260 
 1261 void Assembler::adcl(Register dst, Address src) {
 1262   InstructionMark im(this);
 1263   prefix(src, dst);
 1264   emit_int8(0x13);
 1265   emit_operand(dst, src);
 1266 }
 1267 
 1268 void Assembler::adcl(Register dst, Register src) {
 1269   (void) prefix_and_encode(dst->encoding(), src->encoding());
 1270   emit_arith(0x13, 0xC0, dst, src);
 1271 }
 1272 
 1273 void Assembler::addl(Address dst, int32_t imm32) {
 1274   InstructionMark im(this);
 1275   prefix(dst);
 1276   emit_arith_operand(0x81, rax, dst, imm32);
 1277 }
 1278 
 1279 void Assembler::addb(Address dst, int imm8) {
 1280   InstructionMark im(this);
 1281   prefix(dst);
 1282   emit_int8((unsigned char)0x80);
 1283   emit_operand(rax, dst, 1);
 1284   emit_int8(imm8);
 1285 }
 1286 
 1287 void Assembler::addw(Register dst, Register src) {
 1288   (void)prefix_and_encode(dst->encoding(), src->encoding());
 1289   emit_arith(0x03, 0xC0, dst, src);
 1290 }
 1291 
 1292 void Assembler::addw(Address dst, int imm16) {
 1293   InstructionMark im(this);
 1294   emit_int8(0x66);
 1295   prefix(dst);
 1296   emit_int8((unsigned char)0x81);
 1297   emit_operand(rax, dst, 2);
 1298   emit_int16(imm16);
 1299 }
 1300 
 1301 void Assembler::addl(Address dst, Register src) {
 1302   InstructionMark im(this);
 1303   prefix(dst, src);
 1304   emit_int8(0x01);
 1305   emit_operand(src, dst);
 1306 }
 1307 
 1308 void Assembler::addl(Register dst, int32_t imm32) {
 1309   prefix(dst);
 1310   emit_arith(0x81, 0xC0, dst, imm32);
 1311 }
 1312 
 1313 void Assembler::addl(Register dst, Address src) {
 1314   InstructionMark im(this);
 1315   prefix(src, dst);
 1316   emit_int8(0x03);
 1317   emit_operand(dst, src);
 1318 }
 1319 
 1320 void Assembler::addl(Register dst, Register src) {
 1321   (void) prefix_and_encode(dst->encoding(), src->encoding());
 1322   emit_arith(0x03, 0xC0, dst, src);
 1323 }
 1324 
 1325 void Assembler::addr_nop_4() {
 1326   assert(UseAddressNop, "no CPU support");
 1327   // 4 bytes: NOP DWORD PTR [EAX+0]
 1328   emit_int32(0x0F,
 1329              0x1F,
 1330              0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
 1331              0);   // 8-bits offset (1 byte)
 1332 }
 1333 
 1334 void Assembler::addr_nop_5() {
 1335   assert(UseAddressNop, "no CPU support");
 1336   // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
 1337   emit_int32(0x0F,
 1338              0x1F,
 1339              0x44,  // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
 1340              0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 1341   emit_int8(0);     // 8-bits offset (1 byte)
 1342 }
 1343 
 1344 void Assembler::addr_nop_7() {
 1345   assert(UseAddressNop, "no CPU support");
 1346   // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
 1347   emit_int24(0x0F,
 1348              0x1F,
 1349              (unsigned char)0x80);
 1350                    // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
 1351   emit_int32(0);   // 32-bits offset (4 bytes)
 1352 }
 1353 
 1354 void Assembler::addr_nop_8() {
 1355   assert(UseAddressNop, "no CPU support");
 1356   // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
 1357   emit_int32(0x0F,
 1358              0x1F,
 1359              (unsigned char)0x84,
 1360                     // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
 1361              0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
 1362   emit_int32(0);    // 32-bits offset (4 bytes)
 1363 }
 1364 
 1365 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
 1366   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1367   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1368   attributes.set_rex_vex_w_reverted();
 1369   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1370   emit_int16(0x58, (0xC0 | encode));
 1371 }
 1372 
 1373 void Assembler::addsd(XMMRegister dst, Address src) {
 1374   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1375   InstructionMark im(this);
 1376   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1377   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 1378   attributes.set_rex_vex_w_reverted();
 1379   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1380   emit_int8(0x58);
 1381   emit_operand(dst, src);
 1382 }
 1383 
 1384 void Assembler::addss(XMMRegister dst, XMMRegister src) {
 1385   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1386   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1387   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1388   emit_int16(0x58, (0xC0 | encode));
 1389 }
 1390 
 1391 void Assembler::addss(XMMRegister dst, Address src) {
 1392   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1393   InstructionMark im(this);
 1394   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1395   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 1396   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1397   emit_int8(0x58);
 1398   emit_operand(dst, src);
 1399 }
 1400 
 1401 void Assembler::aesdec(XMMRegister dst, Address src) {
 1402   assert(VM_Version::supports_aes(), "");
 1403   InstructionMark im(this);
 1404   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1405   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1406   emit_int8((unsigned char)0xDE);
 1407   emit_operand(dst, src);
 1408 }
 1409 
 1410 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
 1411   assert(VM_Version::supports_aes(), "");
 1412   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1413   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1414   emit_int16((unsigned char)0xDE, (0xC0 | encode));
 1415 }
 1416 
 1417 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 1418   assert(VM_Version::supports_avx512_vaes(), "");
 1419   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1420   attributes.set_is_evex_instruction();
 1421   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1422   emit_int16((unsigned char)0xDE, (0xC0 | encode));
 1423 }
 1424 
 1425 
 1426 void Assembler::aesdeclast(XMMRegister dst, Address src) {
 1427   assert(VM_Version::supports_aes(), "");
 1428   InstructionMark im(this);
 1429   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1430   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1431   emit_int8((unsigned char)0xDF);
 1432   emit_operand(dst, src);
 1433 }
 1434 
 1435 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
 1436   assert(VM_Version::supports_aes(), "");
 1437   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1438   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1439   emit_int16((unsigned char)0xDF, (0xC0 | encode));
 1440 }
 1441 
 1442 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 1443   assert(VM_Version::supports_avx512_vaes(), "");
 1444   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1445   attributes.set_is_evex_instruction();
 1446   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1447   emit_int16((unsigned char)0xDF, (0xC0 | encode));
 1448 }
 1449 
 1450 void Assembler::aesenc(XMMRegister dst, Address src) {
 1451   assert(VM_Version::supports_aes(), "");
 1452   InstructionMark im(this);
 1453   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1454   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1455   emit_int8((unsigned char)0xDC);
 1456   emit_operand(dst, src);
 1457 }
 1458 
 1459 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
 1460   assert(VM_Version::supports_aes(), "");
 1461   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1462   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1463   emit_int16((unsigned char)0xDC, 0xC0 | encode);
 1464 }
 1465 
 1466 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 1467   assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
 1468   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1469   attributes.set_is_evex_instruction();
 1470   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1471   emit_int16((unsigned char)0xDC, (0xC0 | encode));
 1472 }
 1473 
 1474 void Assembler::aesenclast(XMMRegister dst, Address src) {
 1475   assert(VM_Version::supports_aes(), "");
 1476   InstructionMark im(this);
 1477   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1478   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1479   emit_int8((unsigned char)0xDD);
 1480   emit_operand(dst, src);
 1481 }
 1482 
 1483 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
 1484   assert(VM_Version::supports_aes(), "");
 1485   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1486   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1487   emit_int16((unsigned char)0xDD, (0xC0 | encode));
 1488 }
 1489 
 1490 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 1491   assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
 1492   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1493   attributes.set_is_evex_instruction();
 1494   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 1495   emit_int16((unsigned char)0xDD, (0xC0 | encode));
 1496 }
 1497 
 1498 void Assembler::andb(Address dst, Register src) {
 1499   InstructionMark im(this);
 1500   prefix(dst, src, true);
 1501   emit_int8(0x20);
 1502   emit_operand(src, dst);
 1503 }
 1504 
 1505 void Assembler::andw(Register dst, Register src) {
 1506   (void)prefix_and_encode(dst->encoding(), src->encoding());
 1507   emit_arith(0x23, 0xC0, dst, src);
 1508 }
 1509 
 1510 void Assembler::andl(Address dst, int32_t imm32) {
 1511   InstructionMark im(this);
 1512   prefix(dst);
 1513   emit_arith_operand(0x81, as_Register(4), dst, imm32);
 1514 }
 1515 
 1516 void Assembler::andl(Register dst, int32_t imm32) {
 1517   prefix(dst);
 1518   emit_arith(0x81, 0xE0, dst, imm32);
 1519 }
 1520 
 1521 void Assembler::andl(Address dst, Register src) {
 1522   InstructionMark im(this);
 1523   prefix(dst, src);
 1524   emit_int8(0x21);
 1525   emit_operand(src, dst);
 1526 }
 1527 
 1528 void Assembler::andl(Register dst, Address src) {
 1529   InstructionMark im(this);
 1530   prefix(src, dst);
 1531   emit_int8(0x23);
 1532   emit_operand(dst, src);
 1533 }
 1534 
 1535 void Assembler::andl(Register dst, Register src) {
 1536   (void) prefix_and_encode(dst->encoding(), src->encoding());
 1537   emit_arith(0x23, 0xC0, dst, src);
 1538 }
 1539 
 1540 void Assembler::andnl(Register dst, Register src1, Register src2) {
 1541   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1542   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1543   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1544   emit_int16((unsigned char)0xF2, (0xC0 | encode));
 1545 }
 1546 
 1547 void Assembler::andnl(Register dst, Register src1, Address src2) {
 1548   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1549   InstructionMark im(this);
 1550   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1551   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1552   emit_int8((unsigned char)0xF2);
 1553   emit_operand(dst, src2);
 1554 }
 1555 
 1556 void Assembler::bsfl(Register dst, Register src) {
 1557   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 1558   emit_int24(0x0F,
 1559              (unsigned char)0xBC,
 1560              0xC0 | encode);
 1561 }
 1562 
 1563 void Assembler::bsrl(Register dst, Register src) {
 1564   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 1565   emit_int24(0x0F,
 1566              (unsigned char)0xBD,
 1567              0xC0 | encode);
 1568 }
 1569 
 1570 void Assembler::bswapl(Register reg) { // bswap
 1571   int encode = prefix_and_encode(reg->encoding());
 1572   emit_int16(0x0F, (0xC8 | encode));
 1573 }
 1574 
 1575 void Assembler::blsil(Register dst, Register src) {
 1576   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1577   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1578   int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1579   emit_int16((unsigned char)0xF3, (0xC0 | encode));
 1580 }
 1581 
 1582 void Assembler::blsil(Register dst, Address src) {
 1583   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1584   InstructionMark im(this);
 1585   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1586   vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1587   emit_int8((unsigned char)0xF3);
 1588   emit_operand(rbx, src);
 1589 }
 1590 
 1591 void Assembler::blsmskl(Register dst, Register src) {
 1592   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1593   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1594   int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1595   emit_int16((unsigned char)0xF3,
 1596              0xC0 | encode);
 1597 }
 1598 
 1599 void Assembler::blsmskl(Register dst, Address src) {
 1600   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1601   InstructionMark im(this);
 1602   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1603   vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1604   emit_int8((unsigned char)0xF3);
 1605   emit_operand(rdx, src);
 1606 }
 1607 
 1608 void Assembler::blsrl(Register dst, Register src) {
 1609   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1610   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1611   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1612   emit_int16((unsigned char)0xF3, (0xC0 | encode));
 1613 }
 1614 
 1615 void Assembler::blsrl(Register dst, Address src) {
 1616   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
 1617   InstructionMark im(this);
 1618   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 1619   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
 1620   emit_int8((unsigned char)0xF3);
 1621   emit_operand(rcx, src);
 1622 }
 1623 
 1624 void Assembler::call(Label& L, relocInfo::relocType rtype) {
 1625   // suspect disp32 is always good
 1626   int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
 1627 
 1628   if (L.is_bound()) {
 1629     const int long_size = 5;
 1630     int offs = (int)( target(L) - pc() );
 1631     assert(offs <= 0, "assembler error");
 1632     InstructionMark im(this);
 1633     // 1110 1000 #32-bit disp
 1634     emit_int8((unsigned char)0xE8);
 1635     emit_data(offs - long_size, rtype, operand);
 1636   } else {
 1637     InstructionMark im(this);
 1638     // 1110 1000 #32-bit disp
 1639     L.add_patch_at(code(), locator());
 1640 
 1641     emit_int8((unsigned char)0xE8);
 1642     emit_data(int(0), rtype, operand);
 1643   }
 1644 }
 1645 
 1646 void Assembler::call(Register dst) {
 1647   int encode = prefix_and_encode(dst->encoding());
 1648   emit_int16((unsigned char)0xFF, (0xD0 | encode));
 1649 }
 1650 
 1651 
 1652 void Assembler::call(Address adr) {
 1653   InstructionMark im(this);
 1654   prefix(adr);
 1655   emit_int8((unsigned char)0xFF);
 1656   emit_operand(rdx, adr);
 1657 }
 1658 
 1659 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
 1660   InstructionMark im(this);
 1661   emit_int8((unsigned char)0xE8);
 1662   intptr_t disp = entry - (pc() + sizeof(int32_t));
 1663   // Entry is NULL in case of a scratch emit.
 1664   assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
 1665   // Technically, should use call32_operand, but this format is
 1666   // implied by the fact that we're emitting a call instruction.
 1667 
 1668   int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
 1669   emit_data((int) disp, rspec, operand);
 1670 }
 1671 
 1672 void Assembler::cdql() {
 1673   emit_int8((unsigned char)0x99);
 1674 }
 1675 
 1676 void Assembler::cld() {
 1677   emit_int8((unsigned char)0xFC);
 1678 }
 1679 
 1680 void Assembler::cmovl(Condition cc, Register dst, Register src) {
 1681   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
 1682   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 1683   emit_int24(0x0F,
 1684              0x40 | cc,
 1685              0xC0 | encode);
 1686 }
 1687 
 1688 
 1689 void Assembler::cmovl(Condition cc, Register dst, Address src) {
 1690   InstructionMark im(this);
 1691   NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
 1692   prefix(src, dst);
 1693   emit_int16(0x0F, (0x40 | cc));
 1694   emit_operand(dst, src);
 1695 }
 1696 
 1697 void Assembler::cmpb(Address dst, int imm8) {
 1698   InstructionMark im(this);
 1699   prefix(dst);
 1700   emit_int8((unsigned char)0x80);
 1701   emit_operand(rdi, dst, 1);
 1702   emit_int8(imm8);
 1703 }
 1704 
 1705 void Assembler::cmpl(Address dst, int32_t imm32) {
 1706   InstructionMark im(this);
 1707   prefix(dst);
 1708   emit_int8((unsigned char)0x81);
 1709   emit_operand(rdi, dst, 4);
 1710   emit_int32(imm32);
 1711 }
 1712 
 1713 void Assembler::cmpl(Register dst, int32_t imm32) {
 1714   prefix(dst);
 1715   emit_arith(0x81, 0xF8, dst, imm32);
 1716 }
 1717 
 1718 void Assembler::cmpl(Register dst, Register src) {
 1719   (void) prefix_and_encode(dst->encoding(), src->encoding());
 1720   emit_arith(0x3B, 0xC0, dst, src);
 1721 }
 1722 
 1723 void Assembler::cmpl(Register dst, Address  src) {
 1724   InstructionMark im(this);
 1725   prefix(src, dst);
 1726   emit_int8(0x3B);
 1727   emit_operand(dst, src);
 1728 }
 1729 
 1730 void Assembler::cmpw(Address dst, int imm16) {
 1731   InstructionMark im(this);
 1732   assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
 1733   emit_int16(0x66, (unsigned char)0x81);
 1734   emit_operand(rdi, dst, 2);
 1735   emit_int16(imm16);
 1736 }
 1737 
 1738 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
 1739 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
 1740 // The ZF is set if the compared values were equal, and cleared otherwise.
 1741 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
 1742   InstructionMark im(this);
 1743   prefix(adr, reg);
 1744   emit_int16(0x0F, (unsigned char)0xB1);
 1745   emit_operand(reg, adr);
 1746 }
 1747 
 1748 void Assembler::cmpxchgw(Register reg, Address adr) { // cmpxchg
 1749   InstructionMark im(this);
 1750   size_prefix();
 1751   prefix(adr, reg);
 1752   emit_int16(0x0F, (unsigned char)0xB1);
 1753   emit_operand(reg, adr);
 1754 }
 1755 
 1756 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
 1757 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
 1758 // The ZF is set if the compared values were equal, and cleared otherwise.
 1759 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
 1760   InstructionMark im(this);
 1761   prefix(adr, reg, true);
 1762   emit_int16(0x0F, (unsigned char)0xB0);
 1763   emit_operand(reg, adr);
 1764 }
 1765 
 1766 void Assembler::comisd(XMMRegister dst, Address src) {
 1767   // NOTE: dbx seems to decode this as comiss even though the
 1768   // 0x66 is there. Strangely ucomisd comes out correct
 1769   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1770   InstructionMark im(this);
 1771   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
 1772   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 1773   attributes.set_rex_vex_w_reverted();
 1774   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 1775   emit_int8(0x2F);
 1776   emit_operand(dst, src);
 1777 }
 1778 
 1779 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
 1780   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1781   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1782   attributes.set_rex_vex_w_reverted();
 1783   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 1784   emit_int16(0x2F, (0xC0 | encode));
 1785 }
 1786 
 1787 void Assembler::comiss(XMMRegister dst, Address src) {
 1788   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1789   InstructionMark im(this);
 1790   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1791   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 1792   simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 1793   emit_int8(0x2F);
 1794   emit_operand(dst, src);
 1795 }
 1796 
 1797 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
 1798   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1799   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1800   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 1801   emit_int16(0x2F, (0xC0 | encode));
 1802 }
 1803 
 1804 void Assembler::cpuid() {
 1805   emit_int16(0x0F, (unsigned char)0xA2);
 1806 }
 1807 
 1808 // Opcode / Instruction                      Op /  En  64 - Bit Mode     Compat / Leg Mode Description                  Implemented
 1809 // F2 0F 38 F0 / r       CRC32 r32, r / m8   RM        Valid             Valid             Accumulate CRC32 on r / m8.  v
 1810 // F2 REX 0F 38 F0 / r   CRC32 r32, r / m8*  RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
 1811 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8   RM        Valid             N.E.              Accumulate CRC32 on r / m8.  -
 1812 //
 1813 // F2 0F 38 F1 / r       CRC32 r32, r / m16  RM        Valid             Valid             Accumulate CRC32 on r / m16. v
 1814 //
 1815 // F2 0F 38 F1 / r       CRC32 r32, r / m32  RM        Valid             Valid             Accumulate CRC32 on r / m32. v
 1816 //
 1817 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64  RM        Valid             N.E.              Accumulate CRC32 on r / m64. v
 1818 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
 1819   assert(VM_Version::supports_sse4_2(), "");
 1820   int8_t w = 0x01;
 1821   Prefix p = Prefix_EMPTY;
 1822 
 1823   emit_int8((unsigned char)0xF2);
 1824   switch (sizeInBytes) {
 1825   case 1:
 1826     w = 0;
 1827     break;
 1828   case 2:
 1829   case 4:
 1830     break;
 1831   LP64_ONLY(case 8:)
 1832     // This instruction is not valid in 32 bits
 1833     // Note:
 1834     // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
 1835     //
 1836     // Page B - 72   Vol. 2C says
 1837     // qwreg2 to qwreg            1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
 1838     // mem64 to qwreg             1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
 1839     //                                                                            F0!!!
 1840     // while 3 - 208 Vol. 2A
 1841     // F2 REX.W 0F 38 F1 / r       CRC32 r64, r / m64             RM         Valid      N.E.Accumulate CRC32 on r / m64.
 1842     //
 1843     // the 0 on a last bit is reserved for a different flavor of this instruction :
 1844     // F2 REX.W 0F 38 F0 / r       CRC32 r64, r / m8              RM         Valid      N.E.Accumulate CRC32 on r / m8.
 1845     p = REX_W;
 1846     break;
 1847   default:
 1848     assert(0, "Unsupported value for a sizeInBytes argument");
 1849     break;
 1850   }
 1851   LP64_ONLY(prefix(crc, v, p);)
 1852   emit_int32(0x0F,
 1853              0x38,
 1854              0xF0 | w,
 1855              0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
 1856 }
 1857 
 1858 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
 1859   assert(VM_Version::supports_sse4_2(), "");
 1860   InstructionMark im(this);
 1861   int8_t w = 0x01;
 1862   Prefix p = Prefix_EMPTY;
 1863 
 1864   emit_int8((int8_t)0xF2);
 1865   switch (sizeInBytes) {
 1866   case 1:
 1867     w = 0;
 1868     break;
 1869   case 2:
 1870   case 4:
 1871     break;
 1872   LP64_ONLY(case 8:)
 1873     // This instruction is not valid in 32 bits
 1874     p = REX_W;
 1875     break;
 1876   default:
 1877     assert(0, "Unsupported value for a sizeInBytes argument");
 1878     break;
 1879   }
 1880   LP64_ONLY(prefix(crc, adr, p);)
 1881   emit_int24(0x0F, 0x38, (0xF0 | w));
 1882   emit_operand(crc, adr);
 1883 }
 1884 
 1885 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
 1886   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1887   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1888   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1889   emit_int16((unsigned char)0xE6, (0xC0 | encode));
 1890 }
 1891 
 1892 void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
 1893   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 1894   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1895   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1896   emit_int16((unsigned char)0xE6, (0xC0 | encode));
 1897 }
 1898 
 1899 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
 1900   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1901   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1902   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 1903   emit_int16(0x5B, (0xC0 | encode));
 1904 }
 1905 
 1906 void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
 1907   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 1908   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 1909   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 1910   emit_int16(0x5B, (0xC0 | encode));
 1911 }
 1912 
 1913 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
 1914   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1915   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1916   attributes.set_rex_vex_w_reverted();
 1917   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1918   emit_int16(0x5A, (0xC0 | encode));
 1919 }
 1920 
 1921 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
 1922   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1923   InstructionMark im(this);
 1924   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1925   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 1926   attributes.set_rex_vex_w_reverted();
 1927   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1928   emit_int8(0x5A);
 1929   emit_operand(dst, src);
 1930 }
 1931 
 1932 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
 1933   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1934   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1935   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1936   emit_int16(0x2A, (0xC0 | encode));
 1937 }
 1938 
 1939 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
 1940   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1941   InstructionMark im(this);
 1942   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1943   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 1944   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1945   emit_int8(0x2A);
 1946   emit_operand(dst, src);
 1947 }
 1948 
 1949 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
 1950   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1951   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1952   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1953   emit_int16(0x2A, (0xC0 | encode));
 1954 }
 1955 
 1956 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
 1957   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1958   InstructionMark im(this);
 1959   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1960   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 1961   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1962   emit_int8(0x2A);
 1963   emit_operand(dst, src);
 1964 }
 1965 
 1966 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
 1967   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 1968   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1969   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1970   emit_int16(0x2A, (0xC0 | encode));
 1971 }
 1972 
 1973 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
 1974   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1975   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1976   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1977   emit_int16(0x5A, (0xC0 | encode));
 1978 }
 1979 
 1980 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
 1981   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1982   InstructionMark im(this);
 1983   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1984   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 1985   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 1986   emit_int8(0x5A);
 1987   emit_operand(dst, src);
 1988 }
 1989 
 1990 
 1991 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
 1992   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 1993   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 1994   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 1995   emit_int16(0x2C, (0xC0 | encode));
 1996 }
 1997 
 1998 void Assembler::cvtss2sil(Register dst, XMMRegister src) {
 1999   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2000   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2001   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2002   emit_int16(0x2D, (0xC0 | encode));
 2003 }
 2004 
 2005 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
 2006   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2007   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2008   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2009   emit_int16(0x2C, (0xC0 | encode));
 2010 }
 2011 
 2012 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
 2013   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2014   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
 2015   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2016   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2017   emit_int16((unsigned char)0xE6, (0xC0 | encode));
 2018 }
 2019 
 2020 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
 2021   assert(VM_Version::supports_ssse3(), "");
 2022   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 2023   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2024   emit_int16(0x1C, (0xC0 | encode));
 2025 }
 2026 
 2027 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
 2028   assert(VM_Version::supports_ssse3(), "");
 2029   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 2030   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2031   emit_int16(0x1D, (0xC0 | encode));
 2032 }
 2033 
 2034 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
 2035   assert(VM_Version::supports_ssse3(), "");
 2036   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2037   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2038   emit_int16(0x1E, (0xC0 | encode));
 2039 }
 2040 
 2041 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
 2042   assert(vector_len == AVX_128bit ? VM_Version::supports_avx()      :
 2043          vector_len == AVX_256bit ? VM_Version::supports_avx2()     :
 2044          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
 2045   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 2046   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2047   emit_int16(0x1C, (0xC0 | encode));
 2048 }
 2049 
 2050 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
 2051   assert(vector_len == AVX_128bit ? VM_Version::supports_avx()      :
 2052          vector_len == AVX_256bit ? VM_Version::supports_avx2()     :
 2053          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "");
 2054   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 2055   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2056   emit_int16(0x1D, (0xC0 | encode));
 2057 }
 2058 
 2059 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
 2060   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 2061   vector_len == AVX_256bit? VM_Version::supports_avx2() :
 2062   vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
 2063   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2064   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2065   emit_int16(0x1E, (0xC0 | encode));
 2066 }
 2067 
 2068 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
 2069   assert(UseAVX > 2, "");
 2070   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2071   attributes.set_is_evex_instruction();
 2072   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 2073   emit_int16(0x1F, (0xC0 | encode));
 2074 }
 2075 
 2076 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
 2077   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 2078   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2079   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2080   emit_int16(0x5A, (0xC0 | encode));
 2081 }
 2082 
 2083 void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
 2084   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 2085   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2086   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2087   attributes.set_rex_vex_w_reverted();
 2088   emit_int16(0x5A, (0xC0 | encode));
 2089 }
 2090 
 2091 void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
 2092   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 2093   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2094   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2095   emit_int16(0x5B, (0xC0 | encode));
 2096 }
 2097 
 2098 void Assembler::vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
 2099   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 2100   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2101   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2102   emit_int16(0x5B, (0xC0 | encode));
 2103 }
 2104 
 2105 void Assembler::evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len) {
 2106   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
 2107   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2108   attributes.set_is_evex_instruction();
 2109   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2110   emit_int16(0x7A, (0xC0 | encode));
 2111 }
 2112 
 2113 void Assembler::evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
 2114   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
 2115   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2116   attributes.set_is_evex_instruction();
 2117   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2118   emit_int16(0x7B, (0xC0 | encode));
 2119 }
 2120 
 2121 void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
 2122   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
 2123   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2124   attributes.set_is_evex_instruction();
 2125   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2126   emit_int16(0x5B, (0xC0 | encode));
 2127 }
 2128 
 2129 void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
 2130   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
 2131   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2132   attributes.set_is_evex_instruction();
 2133   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2134   emit_int16(0x7A, (0xC0 | encode));
 2135 }
 2136 
 2137 void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
 2138   assert(UseAVX > 2 && VM_Version::supports_avx512dq(), "");
 2139   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2140   attributes.set_is_evex_instruction();
 2141   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2142   emit_int16((unsigned char)0xE6, (0xC0 | encode));
 2143 }
 2144 
 2145 void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
 2146   assert(UseAVX > 2  && VM_Version::supports_avx512bw(), "");
 2147   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2148   attributes.set_is_evex_instruction();
 2149   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2150   emit_int16(0x30, (0xC0 | encode));
 2151 }
 2152 
 2153 void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
 2154   assert(UseAVX > 2, "");
 2155   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2156   attributes.set_is_evex_instruction();
 2157   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2158   emit_int16(0x33, (0xC0 | encode));
 2159 }
 2160 
 2161 void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
 2162   assert(UseAVX > 2, "");
 2163   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2164   attributes.set_is_evex_instruction();
 2165   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2166   emit_int16(0x31, (0xC0 | encode));
 2167 }
 2168 
 2169 void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
 2170   assert(UseAVX > 2, "");
 2171   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2172   attributes.set_is_evex_instruction();
 2173   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2174   emit_int16(0x35, (0xC0 | encode));
 2175 }
 2176 
 2177 void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
 2178   assert(UseAVX > 2, "");
 2179   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2180   attributes.set_is_evex_instruction();
 2181   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2182   emit_int16(0x32, (0xC0 | encode));
 2183 }
 2184 
 2185 void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
 2186   assert(UseAVX > 2, "");
 2187   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2188   attributes.set_is_evex_instruction();
 2189   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2190   emit_int16(0x34, (0xC0 | encode));
 2191 }
 2192 
 2193 void Assembler::evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len) {
 2194   assert(UseAVX > 2, "");
 2195   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2196   attributes.set_is_evex_instruction();
 2197   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 2198   emit_int16(0x25, (0xC0 | encode));
 2199 }
 2200 
 2201 void Assembler::decl(Address dst) {
 2202   // Don't use it directly. Use MacroAssembler::decrement() instead.
 2203   InstructionMark im(this);
 2204   prefix(dst);
 2205   emit_int8((unsigned char)0xFF);
 2206   emit_operand(rcx, dst);
 2207 }
 2208 
 2209 void Assembler::divsd(XMMRegister dst, Address src) {
 2210   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2211   InstructionMark im(this);
 2212   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2213   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 2214   attributes.set_rex_vex_w_reverted();
 2215   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2216   emit_int8(0x5E);
 2217   emit_operand(dst, src);
 2218 }
 2219 
 2220 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
 2221   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2222   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2223   attributes.set_rex_vex_w_reverted();
 2224   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2225   emit_int16(0x5E, (0xC0 | encode));
 2226 }
 2227 
 2228 void Assembler::divss(XMMRegister dst, Address src) {
 2229   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2230   InstructionMark im(this);
 2231   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2232   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 2233   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2234   emit_int8(0x5E);
 2235   emit_operand(dst, src);
 2236 }
 2237 
 2238 void Assembler::divss(XMMRegister dst, XMMRegister src) {
 2239   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2240   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2241   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2242   emit_int16(0x5E, (0xC0 | encode));
 2243 }
 2244 
 2245 void Assembler::hlt() {
 2246   emit_int8((unsigned char)0xF4);
 2247 }
 2248 
 2249 void Assembler::idivl(Register src) {
 2250   int encode = prefix_and_encode(src->encoding());
 2251   emit_int16((unsigned char)0xF7, (0xF8 | encode));
 2252 }
 2253 
 2254 void Assembler::divl(Register src) { // Unsigned
 2255   int encode = prefix_and_encode(src->encoding());
 2256   emit_int16((unsigned char)0xF7, (0xF0 | encode));
 2257 }
 2258 
 2259 void Assembler::imull(Register src) {
 2260   int encode = prefix_and_encode(src->encoding());
 2261   emit_int16((unsigned char)0xF7, (0xE8 | encode));
 2262 }
 2263 
 2264 void Assembler::imull(Register dst, Register src) {
 2265   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 2266   emit_int24(0x0F,
 2267              (unsigned char)0xAF,
 2268              (0xC0 | encode));
 2269 }
 2270 
 2271 void Assembler::imull(Register dst, Address src, int32_t value) {
 2272   InstructionMark im(this);
 2273   prefix(src, dst);
 2274   if (is8bit(value)) {
 2275     emit_int8((unsigned char)0x6B);
 2276     emit_operand(dst, src);
 2277     emit_int8(value);
 2278   } else {
 2279     emit_int8((unsigned char)0x69);
 2280     emit_operand(dst, src);
 2281     emit_int32(value);
 2282   }
 2283 }
 2284 
 2285 void Assembler::imull(Register dst, Register src, int value) {
 2286   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 2287   if (is8bit(value)) {
 2288     emit_int24(0x6B, (0xC0 | encode), value & 0xFF);
 2289   } else {
 2290     emit_int16(0x69, (0xC0 | encode));
 2291     emit_int32(value);
 2292   }
 2293 }
 2294 
 2295 void Assembler::imull(Register dst, Address src) {
 2296   InstructionMark im(this);
 2297   prefix(src, dst);
 2298   emit_int16(0x0F, (unsigned char)0xAF);
 2299   emit_operand(dst, src);
 2300 }
 2301 
 2302 
 2303 void Assembler::incl(Address dst) {
 2304   // Don't use it directly. Use MacroAssembler::increment() instead.
 2305   InstructionMark im(this);
 2306   prefix(dst);
 2307   emit_int8((unsigned char)0xFF);
 2308   emit_operand(rax, dst);
 2309 }
 2310 
 2311 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
 2312   InstructionMark im(this);
 2313   assert((0 <= cc) && (cc < 16), "illegal cc");
 2314   if (L.is_bound()) {
 2315     address dst = target(L);
 2316     assert(dst != NULL, "jcc most probably wrong");
 2317 
 2318     const int short_size = 2;
 2319     const int long_size = 6;
 2320     intptr_t offs = (intptr_t)dst - (intptr_t)pc();
 2321     if (maybe_short && is8bit(offs - short_size)) {
 2322       // 0111 tttn #8-bit disp
 2323       emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
 2324     } else {
 2325       // 0000 1111 1000 tttn #32-bit disp
 2326       assert(is_simm32(offs - long_size),
 2327              "must be 32bit offset (call4)");
 2328       emit_int16(0x0F, (0x80 | cc));
 2329       emit_int32(offs - long_size);
 2330     }
 2331   } else {
 2332     // Note: could eliminate cond. jumps to this jump if condition
 2333     //       is the same however, seems to be rather unlikely case.
 2334     // Note: use jccb() if label to be bound is very close to get
 2335     //       an 8-bit displacement
 2336     L.add_patch_at(code(), locator());
 2337     emit_int16(0x0F, (0x80 | cc));
 2338     emit_int32(0);
 2339   }
 2340 }
 2341 
 2342 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
 2343   if (L.is_bound()) {
 2344     const int short_size = 2;
 2345     address entry = target(L);
 2346 #ifdef ASSERT
 2347     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
 2348     intptr_t delta = short_branch_delta();
 2349     if (delta != 0) {
 2350       dist += (dist < 0 ? (-delta) :delta);
 2351     }
 2352     assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
 2353 #endif
 2354     intptr_t offs = (intptr_t)entry - (intptr_t)pc();
 2355     // 0111 tttn #8-bit disp
 2356     emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
 2357   } else {
 2358     InstructionMark im(this);
 2359     L.add_patch_at(code(), locator(), file, line);
 2360     emit_int16(0x70 | cc, 0);
 2361   }
 2362 }
 2363 
 2364 void Assembler::jmp(Address adr) {
 2365   InstructionMark im(this);
 2366   prefix(adr);
 2367   emit_int8((unsigned char)0xFF);
 2368   emit_operand(rsp, adr);
 2369 }
 2370 
 2371 void Assembler::jmp(Label& L, bool maybe_short) {
 2372   if (L.is_bound()) {
 2373     address entry = target(L);
 2374     assert(entry != NULL, "jmp most probably wrong");
 2375     InstructionMark im(this);
 2376     const int short_size = 2;
 2377     const int long_size = 5;
 2378     intptr_t offs = entry - pc();
 2379     if (maybe_short && is8bit(offs - short_size)) {
 2380       emit_int16((unsigned char)0xEB, ((offs - short_size) & 0xFF));
 2381     } else {
 2382       emit_int8((unsigned char)0xE9);
 2383       emit_int32(offs - long_size);
 2384     }
 2385   } else {
 2386     // By default, forward jumps are always 32-bit displacements, since
 2387     // we can't yet know where the label will be bound.  If you're sure that
 2388     // the forward jump will not run beyond 256 bytes, use jmpb to
 2389     // force an 8-bit displacement.
 2390     InstructionMark im(this);
 2391     L.add_patch_at(code(), locator());
 2392     emit_int8((unsigned char)0xE9);
 2393     emit_int32(0);
 2394   }
 2395 }
 2396 
 2397 void Assembler::jmp(Register entry) {
 2398   int encode = prefix_and_encode(entry->encoding());
 2399   emit_int16((unsigned char)0xFF, (0xE0 | encode));
 2400 }
 2401 
 2402 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
 2403   InstructionMark im(this);
 2404   emit_int8((unsigned char)0xE9);
 2405   assert(dest != NULL, "must have a target");
 2406   intptr_t disp = dest - (pc() + sizeof(int32_t));
 2407   assert(is_simm32(disp), "must be 32bit offset (jmp)");
 2408   emit_data(disp, rspec.reloc(), call32_operand);
 2409 }
 2410 
 2411 void Assembler::jmpb_0(Label& L, const char* file, int line) {
 2412   if (L.is_bound()) {
 2413     const int short_size = 2;
 2414     address entry = target(L);
 2415     assert(entry != NULL, "jmp most probably wrong");
 2416 #ifdef ASSERT
 2417     intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
 2418     intptr_t delta = short_branch_delta();
 2419     if (delta != 0) {
 2420       dist += (dist < 0 ? (-delta) :delta);
 2421     }
 2422     assert(is8bit(dist), "Dispacement too large for a short jmp at %s:%d", file, line);
 2423 #endif
 2424     intptr_t offs = entry - pc();
 2425     emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
 2426   } else {
 2427     InstructionMark im(this);
 2428     L.add_patch_at(code(), locator(), file, line);
 2429     emit_int16((unsigned char)0xEB, 0);
 2430   }
 2431 }
 2432 
 2433 void Assembler::ldmxcsr( Address src) {
 2434   if (UseAVX > 0 ) {
 2435     InstructionMark im(this);
 2436     InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2437     vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2438     emit_int8((unsigned char)0xAE);
 2439     emit_operand(as_Register(2), src);
 2440   } else {
 2441     NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2442     InstructionMark im(this);
 2443     prefix(src);
 2444     emit_int16(0x0F, (unsigned char)0xAE);
 2445     emit_operand(as_Register(2), src);
 2446   }
 2447 }
 2448 
 2449 void Assembler::leal(Register dst, Address src) {
 2450   InstructionMark im(this);
 2451   prefix(src, dst);
 2452   emit_int8((unsigned char)0x8D);
 2453   emit_operand(dst, src);
 2454 }
 2455 
 2456 void Assembler::lfence() {
 2457   emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
 2458 }
 2459 
 2460 void Assembler::lock() {
 2461   emit_int8((unsigned char)0xF0);
 2462 }
 2463 
 2464 void Assembler::size_prefix() {
 2465   emit_int8(0x66);
 2466 }
 2467 
 2468 void Assembler::lzcntl(Register dst, Register src) {
 2469   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
 2470   emit_int8((unsigned char)0xF3);
 2471   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 2472   emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
 2473 }
 2474 
 2475 void Assembler::lzcntl(Register dst, Address src) {
 2476   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
 2477   InstructionMark im(this);
 2478   emit_int8((unsigned char)0xF3);
 2479   prefix(src, dst);
 2480   emit_int16(0x0F, (unsigned char)0xBD);
 2481   emit_operand(dst, src);
 2482 }
 2483 
 2484 // Emit mfence instruction
 2485 void Assembler::mfence() {
 2486   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
 2487   emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
 2488 }
 2489 
 2490 // Emit sfence instruction
 2491 void Assembler::sfence() {
 2492   NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
 2493   emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
 2494 }
 2495 
 2496 void Assembler::mov(Register dst, Register src) {
 2497   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
 2498 }
 2499 
 2500 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
 2501   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2502   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
 2503   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2504   attributes.set_rex_vex_w_reverted();
 2505   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2506   emit_int16(0x28, (0xC0 | encode));
 2507 }
 2508 
 2509 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
 2510   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2511   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
 2512   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2513   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2514   emit_int16(0x28, (0xC0 | encode));
 2515 }
 2516 
 2517 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
 2518   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 2519   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2520   int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2521   emit_int16(0x16, (0xC0 | encode));
 2522 }
 2523 
 2524 void Assembler::movb(Register dst, Address src) {
 2525   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
 2526   InstructionMark im(this);
 2527   prefix(src, dst, true);
 2528   emit_int8((unsigned char)0x8A);
 2529   emit_operand(dst, src);
 2530 }
 2531 
 2532 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
 2533   NOT_LP64(assert(VM_Version::supports_sse3(), ""));
 2534   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
 2535   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2536   attributes.set_rex_vex_w_reverted();
 2537   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2538   emit_int16(0x12, 0xC0 | encode);
 2539 }
 2540 
 2541 void Assembler::vmovddup(XMMRegister dst, Address src, int vector_len) {
 2542   assert(VM_Version::supports_avx(), "");
 2543   InstructionMark im(this);
 2544   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2545   attributes.set_rex_vex_w_reverted();
 2546   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2547   emit_int8(0x12);
 2548   emit_operand(dst, src);
 2549 }
 2550 
 2551 void Assembler::kmovbl(KRegister dst, KRegister src) {
 2552   assert(VM_Version::supports_avx512dq(), "");
 2553   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2554   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2555   emit_int16((unsigned char)0x90, (0xC0 | encode));
 2556 }
 2557 
 2558 void Assembler::kmovbl(KRegister dst, Register src) {
 2559   assert(VM_Version::supports_avx512dq(), "");
 2560   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2561   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2562   emit_int16((unsigned char)0x92, (0xC0 | encode));
 2563 }
 2564 
 2565 void Assembler::kmovbl(Register dst, KRegister src) {
 2566   assert(VM_Version::supports_avx512dq(), "");
 2567   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2568   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2569   emit_int16((unsigned char)0x93, (0xC0 | encode));
 2570 }
 2571 
 2572 void Assembler::kmovwl(KRegister dst, Register src) {
 2573   assert(VM_Version::supports_evex(), "");
 2574   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2575   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2576   emit_int16((unsigned char)0x92, (0xC0 | encode));
 2577 }
 2578 
 2579 void Assembler::kmovwl(Register dst, KRegister src) {
 2580   assert(VM_Version::supports_evex(), "");
 2581   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2582   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2583   emit_int16((unsigned char)0x93, (0xC0 | encode));
 2584 }
 2585 
 2586 void Assembler::kmovwl(KRegister dst, Address src) {
 2587   assert(VM_Version::supports_evex(), "");
 2588   InstructionMark im(this);
 2589   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2590   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2591   emit_int8((unsigned char)0x90);
 2592   emit_operand((Register)dst, src);
 2593 }
 2594 
 2595 void Assembler::kmovwl(Address dst, KRegister src) {
 2596   assert(VM_Version::supports_evex(), "");
 2597   InstructionMark im(this);
 2598   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2599   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2600   emit_int8((unsigned char)0x91);
 2601   emit_operand((Register)src, dst);
 2602 }
 2603 
 2604 void Assembler::kmovwl(KRegister dst, KRegister src) {
 2605   assert(VM_Version::supports_evex(), "");
 2606   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2607   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2608   emit_int16((unsigned char)0x90, (0xC0 | encode));
 2609 }
 2610 
 2611 void Assembler::kmovdl(KRegister dst, Register src) {
 2612   assert(VM_Version::supports_avx512bw(), "");
 2613   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2614   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2615   emit_int16((unsigned char)0x92, (0xC0 | encode));
 2616 }
 2617 
 2618 void Assembler::kmovdl(Register dst, KRegister src) {
 2619   assert(VM_Version::supports_avx512bw(), "");
 2620   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2621   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2622   emit_int16((unsigned char)0x93, (0xC0 | encode));
 2623 }
 2624 
 2625 void Assembler::kmovql(KRegister dst, KRegister src) {
 2626   assert(VM_Version::supports_avx512bw(), "");
 2627   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2628   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2629   emit_int16((unsigned char)0x90, (0xC0 | encode));
 2630 }
 2631 
 2632 void Assembler::kmovql(KRegister dst, Address src) {
 2633   assert(VM_Version::supports_avx512bw(), "");
 2634   InstructionMark im(this);
 2635   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2636   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2637   emit_int8((unsigned char)0x90);
 2638   emit_operand((Register)dst, src);
 2639 }
 2640 
 2641 void Assembler::kmovql(Address dst, KRegister src) {
 2642   assert(VM_Version::supports_avx512bw(), "");
 2643   InstructionMark im(this);
 2644   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2645   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2646   emit_int8((unsigned char)0x91);
 2647   emit_operand((Register)src, dst);
 2648 }
 2649 
 2650 void Assembler::kmovql(KRegister dst, Register src) {
 2651   assert(VM_Version::supports_avx512bw(), "");
 2652   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2653   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2654   emit_int16((unsigned char)0x92, (0xC0 | encode));
 2655 }
 2656 
 2657 void Assembler::kmovql(Register dst, KRegister src) {
 2658   assert(VM_Version::supports_avx512bw(), "");
 2659   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2660   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 2661   emit_int16((unsigned char)0x93, (0xC0 | encode));
 2662 }
 2663 
 2664 void Assembler::knotwl(KRegister dst, KRegister src) {
 2665   assert(VM_Version::supports_evex(), "");
 2666   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2667   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2668   emit_int16(0x44, (0xC0 | encode));
 2669 }
 2670 
 2671 void Assembler::knotbl(KRegister dst, KRegister src) {
 2672   assert(VM_Version::supports_evex(), "");
 2673   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2674   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2675   emit_int16(0x44, (0xC0 | encode));
 2676 }
 2677 
 2678 void Assembler::korbl(KRegister dst, KRegister src1, KRegister src2) {
 2679   assert(VM_Version::supports_avx512dq(), "");
 2680   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2681   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2682   emit_int16(0x45, (0xC0 | encode));
 2683 }
 2684 
 2685 void Assembler::korwl(KRegister dst, KRegister src1, KRegister src2) {
 2686   assert(VM_Version::supports_evex(), "");
 2687   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2688   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2689   emit_int16(0x45, (0xC0 | encode));
 2690 }
 2691 
 2692 void Assembler::kordl(KRegister dst, KRegister src1, KRegister src2) {
 2693   assert(VM_Version::supports_avx512bw(), "");
 2694   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2695   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2696   emit_int16(0x45, (0xC0 | encode));
 2697 }
 2698 
 2699 void Assembler::korql(KRegister dst, KRegister src1, KRegister src2) {
 2700   assert(VM_Version::supports_avx512bw(), "");
 2701   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2702   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2703   emit_int16(0x45, (0xC0 | encode));
 2704 }
 2705 
 2706 void Assembler::kxorbl(KRegister dst, KRegister src1, KRegister src2) {
 2707   assert(VM_Version::supports_avx512dq(), "");
 2708   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2709   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2710   emit_int16(0x47, (0xC0 | encode));
 2711 }
 2712 
 2713 void Assembler::kxorwl(KRegister dst, KRegister src1, KRegister src2) {
 2714   assert(VM_Version::supports_evex(), "");
 2715   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2716   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2717   emit_int16(0x47, (0xC0 | encode));
 2718 }
 2719 
 2720 void Assembler::kxordl(KRegister dst, KRegister src1, KRegister src2) {
 2721   assert(VM_Version::supports_avx512bw(), "");
 2722   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2723   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2724   emit_int16(0x47, (0xC0 | encode));
 2725 }
 2726 
 2727 void Assembler::kxorql(KRegister dst, KRegister src1, KRegister src2) {
 2728   assert(VM_Version::supports_avx512bw(), "");
 2729   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2730   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2731   emit_int16(0x47, (0xC0 | encode));
 2732 }
 2733 
 2734 void Assembler::kandbl(KRegister dst, KRegister src1, KRegister src2) {
 2735   assert(VM_Version::supports_avx512dq(), "");
 2736   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2737   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2738   emit_int16(0x41, (0xC0 | encode));
 2739 }
 2740 
 2741 void Assembler::kandwl(KRegister dst, KRegister src1, KRegister src2) {
 2742   assert(VM_Version::supports_evex(), "");
 2743   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2744   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2745   emit_int16(0x41, (0xC0 | encode));
 2746 }
 2747 
 2748 void Assembler::kanddl(KRegister dst, KRegister src1, KRegister src2) {
 2749   assert(VM_Version::supports_avx512bw(), "");
 2750   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2751   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2752   emit_int16(0x41, (0xC0 | encode));
 2753 }
 2754 
 2755 void Assembler::kandql(KRegister dst, KRegister src1, KRegister src2) {
 2756   assert(VM_Version::supports_avx512bw(), "");
 2757   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2758   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2759   emit_int16(0x41, (0xC0 | encode));
 2760 }
 2761 
 2762 void Assembler::knotdl(KRegister dst, KRegister src) {
 2763   assert(VM_Version::supports_avx512bw(), "");
 2764   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2765   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2766   emit_int16(0x44, (0xC0 | encode));
 2767 }
 2768 
 2769 void Assembler::knotql(KRegister dst, KRegister src) {
 2770   assert(VM_Version::supports_avx512bw(), "");
 2771   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2772   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2773   emit_int16(0x44, (0xC0 | encode));
 2774 }
 2775 
 2776 // This instruction produces ZF or CF flags
 2777 void Assembler::kortestbl(KRegister src1, KRegister src2) {
 2778   assert(VM_Version::supports_avx512dq(), "");
 2779   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2780   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2781   emit_int16((unsigned char)0x98, (0xC0 | encode));
 2782 }
 2783 
 2784 // This instruction produces ZF or CF flags
 2785 void Assembler::kortestwl(KRegister src1, KRegister src2) {
 2786   assert(VM_Version::supports_evex(), "");
 2787   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2788   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2789   emit_int16((unsigned char)0x98, (0xC0 | encode));
 2790 }
 2791 
 2792 // This instruction produces ZF or CF flags
 2793 void Assembler::kortestdl(KRegister src1, KRegister src2) {
 2794   assert(VM_Version::supports_avx512bw(), "");
 2795   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2796   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2797   emit_int16((unsigned char)0x98, (0xC0 | encode));
 2798 }
 2799 
 2800 // This instruction produces ZF or CF flags
 2801 void Assembler::kortestql(KRegister src1, KRegister src2) {
 2802   assert(VM_Version::supports_avx512bw(), "");
 2803   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2804   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2805   emit_int16((unsigned char)0x98, (0xC0 | encode));
 2806 }
 2807 
 2808 // This instruction produces ZF or CF flags
 2809 void Assembler::ktestql(KRegister src1, KRegister src2) {
 2810   assert(VM_Version::supports_avx512bw(), "");
 2811   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2812   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2813   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2814 }
 2815 
 2816 void Assembler::ktestdl(KRegister src1, KRegister src2) {
 2817   assert(VM_Version::supports_avx512bw(), "");
 2818   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2819   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2820   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2821 }
 2822 
 2823 void Assembler::ktestwl(KRegister src1, KRegister src2) {
 2824   assert(VM_Version::supports_avx512dq(), "");
 2825   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2826   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2827   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2828 }
 2829 
 2830 void Assembler::ktestbl(KRegister src1, KRegister src2) {
 2831   assert(VM_Version::supports_avx512dq(), "");
 2832   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2833   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2834   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2835 }
 2836 
 2837 void Assembler::ktestq(KRegister src1, KRegister src2) {
 2838   assert(VM_Version::supports_avx512bw(), "");
 2839   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2840   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2841   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2842 }
 2843 
 2844 void Assembler::ktestd(KRegister src1, KRegister src2) {
 2845   assert(VM_Version::supports_avx512bw(), "");
 2846   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2847   int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2848   emit_int16((unsigned char)0x99, (0xC0 | encode));
 2849 }
 2850 
 2851 void Assembler::kxnorbl(KRegister dst, KRegister src1, KRegister src2) {
 2852   assert(VM_Version::supports_avx512dq(), "");
 2853   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2854   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2855   emit_int16(0x46, (0xC0 | encode));
 2856 }
 2857 
 2858 void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) {
 2859   assert(VM_Version::supports_avx512dq(), "");
 2860   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2861   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2862   emit_int16(0x32, (0xC0 | encode));
 2863   emit_int8(imm8);
 2864 }
 2865 
 2866 void Assembler::kshiftlql(KRegister dst, KRegister src, int imm8) {
 2867   assert(VM_Version::supports_avx512bw(), "");
 2868   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2869   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2870   emit_int16(0x33, (0xC0 | encode));
 2871   emit_int8(imm8);
 2872 }
 2873 
 2874 
 2875 void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) {
 2876   assert(VM_Version::supports_avx512dq(), "");
 2877   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2878   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2879   emit_int16(0x30, (0xC0 | encode));
 2880 }
 2881 
 2882 void Assembler::kshiftrwl(KRegister dst, KRegister src, int imm8) {
 2883   assert(VM_Version::supports_evex(), "");
 2884   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2885   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2886   emit_int16(0x30, (0xC0 | encode));
 2887   emit_int8(imm8);
 2888 }
 2889 
 2890 void Assembler::kshiftrdl(KRegister dst, KRegister src, int imm8) {
 2891   assert(VM_Version::supports_avx512bw(), "");
 2892   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2893   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2894   emit_int16(0x31, (0xC0 | encode));
 2895   emit_int8(imm8);
 2896 }
 2897 
 2898 void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) {
 2899   assert(VM_Version::supports_avx512bw(), "");
 2900   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2901   int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 2902   emit_int16(0x31, (0xC0 | encode));
 2903   emit_int8(imm8);
 2904 }
 2905 
 2906 void Assembler::kunpckdql(KRegister dst, KRegister src1, KRegister src2) {
 2907   assert(VM_Version::supports_avx512bw(), "");
 2908   InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 2909   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 2910   emit_int16(0x4B, (0xC0 | encode));
 2911 }
 2912 
 2913 void Assembler::movb(Address dst, int imm8) {
 2914   InstructionMark im(this);
 2915    prefix(dst);
 2916   emit_int8((unsigned char)0xC6);
 2917   emit_operand(rax, dst, 1);
 2918   emit_int8(imm8);
 2919 }
 2920 
 2921 
 2922 void Assembler::movb(Address dst, Register src) {
 2923   assert(src->has_byte_register(), "must have byte register");
 2924   InstructionMark im(this);
 2925   prefix(dst, src, true);
 2926   emit_int8((unsigned char)0x88);
 2927   emit_operand(src, dst);
 2928 }
 2929 
 2930 void Assembler::movdl(XMMRegister dst, Register src) {
 2931   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2932   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2933   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2934   emit_int16(0x6E, (0xC0 | encode));
 2935 }
 2936 
 2937 void Assembler::movdl(Register dst, XMMRegister src) {
 2938   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2939   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2940   // swap src/dst to get correct prefix
 2941   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2942   emit_int16(0x7E, (0xC0 | encode));
 2943 }
 2944 
 2945 void Assembler::movdl(XMMRegister dst, Address src) {
 2946   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2947   InstructionMark im(this);
 2948   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2949   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 2950   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2951   emit_int8(0x6E);
 2952   emit_operand(dst, src);
 2953 }
 2954 
 2955 void Assembler::movdl(Address dst, XMMRegister src) {
 2956   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2957   InstructionMark im(this);
 2958   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 2959   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 2960   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2961   emit_int8(0x7E);
 2962   emit_operand(src, dst);
 2963 }
 2964 
 2965 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
 2966   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2967   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2968   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2969   emit_int16(0x6F, (0xC0 | encode));
 2970 }
 2971 
 2972 void Assembler::movdqa(XMMRegister dst, Address src) {
 2973   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2974   InstructionMark im(this);
 2975   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2976   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 2977   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 2978   emit_int8(0x6F);
 2979   emit_operand(dst, src);
 2980 }
 2981 
 2982 void Assembler::movdqu(XMMRegister dst, Address src) {
 2983   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2984   InstructionMark im(this);
 2985   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2986   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 2987   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2988   emit_int8(0x6F);
 2989   emit_operand(dst, src);
 2990 }
 2991 
 2992 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
 2993   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 2994   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 2995   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 2996   emit_int16(0x6F, (0xC0 | encode));
 2997 }
 2998 
 2999 void Assembler::movdqu(Address dst, XMMRegister src) {
 3000   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3001   InstructionMark im(this);
 3002   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 3003   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3004   attributes.reset_is_clear_context();
 3005   simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3006   emit_int8(0x7F);
 3007   emit_operand(src, dst);
 3008 }
 3009 
 3010 // Move Unaligned 256bit Vector
 3011 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
 3012   assert(UseAVX > 0, "");
 3013   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 3014   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3015   emit_int16(0x6F, (0xC0 | encode));
 3016 }
 3017 
 3018 void Assembler::vmovdqu(XMMRegister dst, Address src) {
 3019   assert(UseAVX > 0, "");
 3020   InstructionMark im(this);
 3021   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 3022   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3023   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3024   emit_int8(0x6F);
 3025   emit_operand(dst, src);
 3026 }
 3027 
 3028 void Assembler::vmovdqu(Address dst, XMMRegister src) {
 3029   assert(UseAVX > 0, "");
 3030   InstructionMark im(this);
 3031   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 3032   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3033   attributes.reset_is_clear_context();
 3034   // swap src<->dst for encoding
 3035   assert(src != xnoreg, "sanity");
 3036   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3037   emit_int8(0x7F);
 3038   emit_operand(src, dst);
 3039 }
 3040 
 3041 void Assembler::vpmaskmovd(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
 3042   assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
 3043   InstructionMark im(this);
 3044   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
 3045   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3046   emit_int8((unsigned char)0x8C);
 3047   emit_operand(dst, src);
 3048 }
 3049 
 3050 void Assembler::vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
 3051   assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
 3052   InstructionMark im(this);
 3053   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
 3054   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3055   emit_int8((unsigned char)0x8C);
 3056   emit_operand(dst, src);
 3057 }
 3058 
 3059 void Assembler::vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
 3060   assert(UseAVX > 0, "requires some form of AVX");
 3061   InstructionMark im(this);
 3062   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 3063   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3064   emit_int8(0x2C);
 3065   emit_operand(dst, src);
 3066 }
 3067 
 3068 void Assembler::vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
 3069   assert(UseAVX > 0, "requires some form of AVX");
 3070   InstructionMark im(this);
 3071   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 3072   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3073   emit_int8(0x2D);
 3074   emit_operand(dst, src);
 3075 }
 3076 
 3077 void Assembler::vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
 3078   assert(UseAVX > 0, "");
 3079   InstructionMark im(this);
 3080   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 3081   vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3082   emit_int8(0x2E);
 3083   emit_operand(src, dst);
 3084 }
 3085 
 3086 void Assembler::vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
 3087   assert(UseAVX > 0, "");
 3088   InstructionMark im(this);
 3089   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 3090   vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 3091   emit_int8(0x2F);
 3092   emit_operand(src, dst);
 3093 }
 3094 
 3095 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
 3096 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3097   assert(VM_Version::supports_avx512vlbw(), "");
 3098   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 3099   attributes.set_embedded_opmask_register_specifier(mask);
 3100   attributes.set_is_evex_instruction();
 3101   if (merge) {
 3102     attributes.reset_is_clear_context();
 3103   }
 3104   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3105   emit_int16(0x6F, (0xC0 | encode));
 3106 }
 3107 
 3108 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
 3109   // Unmasked instruction
 3110   evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
 3111 }
 3112 
 3113 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 3114   assert(VM_Version::supports_avx512vlbw(), "");
 3115   InstructionMark im(this);
 3116   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 3117   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3118   attributes.set_embedded_opmask_register_specifier(mask);
 3119   attributes.set_is_evex_instruction();
 3120   if (merge) {
 3121     attributes.reset_is_clear_context();
 3122   }
 3123   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3124   emit_int8(0x6F);
 3125   emit_operand(dst, src);
 3126 }
 3127 
 3128 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
 3129   // Unmasked instruction
 3130   evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
 3131 }
 3132 
 3133 void Assembler::evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3134   assert(VM_Version::supports_avx512vlbw(), "");
 3135   assert(src != xnoreg, "sanity");
 3136   InstructionMark im(this);
 3137   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 3138   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3139   attributes.set_embedded_opmask_register_specifier(mask);
 3140   attributes.set_is_evex_instruction();
 3141   if (merge) {
 3142     attributes.reset_is_clear_context();
 3143   }
 3144   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3145   emit_int8(0x7F);
 3146   emit_operand(src, dst);
 3147 }
 3148 
 3149 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
 3150   // Unmasked instruction
 3151   evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
 3152 }
 3153 
 3154 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 3155   assert(VM_Version::supports_avx512vlbw(), "");
 3156   InstructionMark im(this);
 3157   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 3158   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3159   attributes.set_embedded_opmask_register_specifier(mask);
 3160   attributes.set_is_evex_instruction();
 3161   if (merge) {
 3162     attributes.reset_is_clear_context();
 3163   }
 3164   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3165   emit_int8(0x6F);
 3166   emit_operand(dst, src);
 3167 }
 3168 
 3169 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
 3170   // Unmasked instruction
 3171   evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
 3172 }
 3173 
 3174 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3175   assert(VM_Version::supports_avx512vlbw(), "");
 3176   assert(src != xnoreg, "sanity");
 3177   InstructionMark im(this);
 3178   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 3179   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3180   attributes.set_embedded_opmask_register_specifier(mask);
 3181   attributes.set_is_evex_instruction();
 3182   if (merge) {
 3183     attributes.reset_is_clear_context();
 3184   }
 3185   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3186   emit_int8(0x7F);
 3187   emit_operand(src, dst);
 3188 }
 3189 
 3190 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
 3191   // Unmasked instruction
 3192   evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
 3193 }
 3194 
 3195 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3196   assert(VM_Version::supports_evex(), "");
 3197   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 3198   attributes.set_embedded_opmask_register_specifier(mask);
 3199   attributes.set_is_evex_instruction();
 3200   if (merge) {
 3201     attributes.reset_is_clear_context();
 3202   }
 3203   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3204   emit_int16(0x6F, (0xC0 | encode));
 3205 }
 3206 
 3207 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
 3208   // Unmasked instruction
 3209   evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
 3210 }
 3211 
 3212 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 3213   assert(VM_Version::supports_evex(), "");
 3214   InstructionMark im(this);
 3215   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
 3216   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3217   attributes.set_embedded_opmask_register_specifier(mask);
 3218   attributes.set_is_evex_instruction();
 3219   if (merge) {
 3220     attributes.reset_is_clear_context();
 3221   }
 3222   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3223   emit_int8(0x6F);
 3224   emit_operand(dst, src);
 3225 }
 3226 
 3227 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
 3228   // Unmasked isntruction
 3229   evmovdqul(dst, k0, src, /*merge*/ true, vector_len);
 3230 }
 3231 
 3232 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3233   assert(VM_Version::supports_evex(), "");
 3234   assert(src != xnoreg, "sanity");
 3235   InstructionMark im(this);
 3236   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 3237   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3238   attributes.set_embedded_opmask_register_specifier(mask);
 3239   attributes.set_is_evex_instruction();
 3240   if (merge) {
 3241     attributes.reset_is_clear_context();
 3242   }
 3243   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3244   emit_int8(0x7F);
 3245   emit_operand(src, dst);
 3246 }
 3247 
 3248 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
 3249   // Unmasked instruction
 3250   if (dst->encoding() == src->encoding()) return;
 3251   evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
 3252 }
 3253 
 3254 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3255   assert(VM_Version::supports_evex(), "");
 3256   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 3257   attributes.set_embedded_opmask_register_specifier(mask);
 3258   attributes.set_is_evex_instruction();
 3259   if (merge) {
 3260     attributes.reset_is_clear_context();
 3261   }
 3262   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3263   emit_int16(0x6F, (0xC0 | encode));
 3264 }
 3265 
 3266 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
 3267   // Unmasked instruction
 3268   evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
 3269 }
 3270 
 3271 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 3272   assert(VM_Version::supports_evex(), "");
 3273   InstructionMark im(this);
 3274   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 3275   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3276   attributes.set_embedded_opmask_register_specifier(mask);
 3277   attributes.set_is_evex_instruction();
 3278   if (merge) {
 3279     attributes.reset_is_clear_context();
 3280   }
 3281   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3282   emit_int8(0x6F);
 3283   emit_operand(dst, src);
 3284 }
 3285 
 3286 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
 3287   // Unmasked instruction
 3288   evmovdquq(dst, k0, src, /*merge*/ true, vector_len);
 3289 }
 3290 
 3291 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 3292   assert(VM_Version::supports_evex(), "");
 3293   assert(src != xnoreg, "sanity");
 3294   InstructionMark im(this);
 3295   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 3296   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 3297   attributes.set_embedded_opmask_register_specifier(mask);
 3298   if (merge) {
 3299     attributes.reset_is_clear_context();
 3300   }
 3301   attributes.set_is_evex_instruction();
 3302   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3303   emit_int8(0x7F);
 3304   emit_operand(src, dst);
 3305 }
 3306 
 3307 // Uses zero extension on 64bit
 3308 
 3309 void Assembler::movl(Register dst, int32_t imm32) {
 3310   int encode = prefix_and_encode(dst->encoding());
 3311   emit_int8(0xB8 | encode);
 3312   emit_int32(imm32);
 3313 }
 3314 
 3315 void Assembler::movl(Register dst, Register src) {
 3316   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 3317   emit_int16((unsigned char)0x8B, (0xC0 | encode));
 3318 }
 3319 
 3320 void Assembler::movl(Register dst, Address src) {
 3321   InstructionMark im(this);
 3322   prefix(src, dst);
 3323   emit_int8((unsigned char)0x8B);
 3324   emit_operand(dst, src);
 3325 }
 3326 
 3327 void Assembler::movl(Address dst, int32_t imm32) {
 3328   InstructionMark im(this);
 3329   prefix(dst);
 3330   emit_int8((unsigned char)0xC7);
 3331   emit_operand(rax, dst, 4);
 3332   emit_int32(imm32);
 3333 }
 3334 
 3335 void Assembler::movl(Address dst, Register src) {
 3336   InstructionMark im(this);
 3337   prefix(dst, src);
 3338   emit_int8((unsigned char)0x89);
 3339   emit_operand(src, dst);
 3340 }
 3341 
 3342 // New cpus require to use movsd and movss to avoid partial register stall
 3343 // when loading from memory. But for old Opteron use movlpd instead of movsd.
 3344 // The selection is done in MacroAssembler::movdbl() and movflt().
 3345 void Assembler::movlpd(XMMRegister dst, Address src) {
 3346   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3347   InstructionMark im(this);
 3348   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 3349   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3350   attributes.set_rex_vex_w_reverted();
 3351   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3352   emit_int8(0x12);
 3353   emit_operand(dst, src);
 3354 }
 3355 
 3356 void Assembler::movq(XMMRegister dst, Address src) {
 3357   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3358   InstructionMark im(this);
 3359   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3360   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3361   attributes.set_rex_vex_w_reverted();
 3362   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3363   emit_int8(0x7E);
 3364   emit_operand(dst, src);
 3365 }
 3366 
 3367 void Assembler::movq(Address dst, XMMRegister src) {
 3368   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3369   InstructionMark im(this);
 3370   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3371   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3372   attributes.set_rex_vex_w_reverted();
 3373   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3374   emit_int8((unsigned char)0xD6);
 3375   emit_operand(src, dst);
 3376 }
 3377 
 3378 void Assembler::movq(XMMRegister dst, XMMRegister src) {
 3379   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3380   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3381   attributes.set_rex_vex_w_reverted();
 3382   int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3383   emit_int16((unsigned char)0xD6, (0xC0 | encode));
 3384 }
 3385 
 3386 void Assembler::movq(Register dst, XMMRegister src) {
 3387   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3388   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3389   // swap src/dst to get correct prefix
 3390   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3391   emit_int16(0x7E, (0xC0 | encode));
 3392 }
 3393 
 3394 void Assembler::movq(XMMRegister dst, Register src) {
 3395   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3396   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3397   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3398   emit_int16(0x6E, (0xC0 | encode));
 3399 }
 3400 
 3401 void Assembler::movsbl(Register dst, Address src) { // movsxb
 3402   InstructionMark im(this);
 3403   prefix(src, dst);
 3404   emit_int16(0x0F, (unsigned char)0xBE);
 3405   emit_operand(dst, src);
 3406 }
 3407 
 3408 void Assembler::movsbl(Register dst, Register src) { // movsxb
 3409   NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
 3410   int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
 3411   emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
 3412 }
 3413 
 3414 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
 3415   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3416   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3417   attributes.set_rex_vex_w_reverted();
 3418   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3419   emit_int16(0x10, (0xC0 | encode));
 3420 }
 3421 
 3422 void Assembler::movsd(XMMRegister dst, Address src) {
 3423   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3424   InstructionMark im(this);
 3425   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3426   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3427   attributes.set_rex_vex_w_reverted();
 3428   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3429   emit_int8(0x10);
 3430   emit_operand(dst, src);
 3431 }
 3432 
 3433 void Assembler::movsd(Address dst, XMMRegister src) {
 3434   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3435   InstructionMark im(this);
 3436   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3437   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3438   attributes.reset_is_clear_context();
 3439   attributes.set_rex_vex_w_reverted();
 3440   simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3441   emit_int8(0x11);
 3442   emit_operand(src, dst);
 3443 }
 3444 
 3445 void Assembler::movss(XMMRegister dst, XMMRegister src) {
 3446   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 3447   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3448   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3449   emit_int16(0x10, (0xC0 | encode));
 3450 }
 3451 
 3452 void Assembler::movss(XMMRegister dst, Address src) {
 3453   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 3454   InstructionMark im(this);
 3455   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3456   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 3457   simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3458   emit_int8(0x10);
 3459   emit_operand(dst, src);
 3460 }
 3461 
 3462 void Assembler::movss(Address dst, XMMRegister src) {
 3463   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 3464   InstructionMark im(this);
 3465   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3466   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 3467   attributes.reset_is_clear_context();
 3468   simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3469   emit_int8(0x11);
 3470   emit_operand(src, dst);
 3471 }
 3472 
 3473 void Assembler::movswl(Register dst, Address src) { // movsxw
 3474   InstructionMark im(this);
 3475   prefix(src, dst);
 3476   emit_int16(0x0F, (unsigned char)0xBF);
 3477   emit_operand(dst, src);
 3478 }
 3479 
 3480 void Assembler::movswl(Register dst, Register src) { // movsxw
 3481   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 3482   emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
 3483 }
 3484 
 3485 void Assembler::movw(Address dst, int imm16) {
 3486   InstructionMark im(this);
 3487 
 3488   emit_int8(0x66); // switch to 16-bit mode
 3489   prefix(dst);
 3490   emit_int8((unsigned char)0xC7);
 3491   emit_operand(rax, dst, 2);
 3492   emit_int16(imm16);
 3493 }
 3494 
 3495 void Assembler::movw(Register dst, Address src) {
 3496   InstructionMark im(this);
 3497   emit_int8(0x66);
 3498   prefix(src, dst);
 3499   emit_int8((unsigned char)0x8B);
 3500   emit_operand(dst, src);
 3501 }
 3502 
 3503 void Assembler::movw(Address dst, Register src) {
 3504   InstructionMark im(this);
 3505   emit_int8(0x66);
 3506   prefix(dst, src);
 3507   emit_int8((unsigned char)0x89);
 3508   emit_operand(src, dst);
 3509 }
 3510 
 3511 void Assembler::movzbl(Register dst, Address src) { // movzxb
 3512   InstructionMark im(this);
 3513   prefix(src, dst);
 3514   emit_int16(0x0F, (unsigned char)0xB6);
 3515   emit_operand(dst, src);
 3516 }
 3517 
 3518 void Assembler::movzbl(Register dst, Register src) { // movzxb
 3519   NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
 3520   int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
 3521   emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
 3522 }
 3523 
 3524 void Assembler::movzwl(Register dst, Address src) { // movzxw
 3525   InstructionMark im(this);
 3526   prefix(src, dst);
 3527   emit_int16(0x0F, (unsigned char)0xB7);
 3528   emit_operand(dst, src);
 3529 }
 3530 
 3531 void Assembler::movzwl(Register dst, Register src) { // movzxw
 3532   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 3533   emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode);
 3534 }
 3535 
 3536 void Assembler::mull(Address src) {
 3537   InstructionMark im(this);
 3538   prefix(src);
 3539   emit_int8((unsigned char)0xF7);
 3540   emit_operand(rsp, src);
 3541 }
 3542 
 3543 void Assembler::mull(Register src) {
 3544   int encode = prefix_and_encode(src->encoding());
 3545   emit_int16((unsigned char)0xF7, (0xE0 | encode));
 3546 }
 3547 
 3548 void Assembler::mulsd(XMMRegister dst, Address src) {
 3549   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3550   InstructionMark im(this);
 3551   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3552   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 3553   attributes.set_rex_vex_w_reverted();
 3554   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3555   emit_int8(0x59);
 3556   emit_operand(dst, src);
 3557 }
 3558 
 3559 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
 3560   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3561   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3562   attributes.set_rex_vex_w_reverted();
 3563   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 3564   emit_int16(0x59, (0xC0 | encode));
 3565 }
 3566 
 3567 void Assembler::mulss(XMMRegister dst, Address src) {
 3568   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 3569   InstructionMark im(this);
 3570   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3571   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 3572   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3573   emit_int8(0x59);
 3574   emit_operand(dst, src);
 3575 }
 3576 
 3577 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
 3578   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 3579   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 3580   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 3581   emit_int16(0x59, (0xC0 | encode));
 3582 }
 3583 
 3584 void Assembler::negl(Register dst) {
 3585   int encode = prefix_and_encode(dst->encoding());
 3586   emit_int16((unsigned char)0xF7, (0xD8 | encode));
 3587 }
 3588 
 3589 void Assembler::negl(Address dst) {
 3590   InstructionMark im(this);
 3591   prefix(dst);
 3592   emit_int8((unsigned char)0xF7);
 3593   emit_operand(as_Register(3), dst);
 3594 }
 3595 
 3596 void Assembler::nop(int i) {
 3597 #ifdef ASSERT
 3598   assert(i > 0, " ");
 3599   // The fancy nops aren't currently recognized by debuggers making it a
 3600   // pain to disassemble code while debugging. If asserts are on clearly
 3601   // speed is not an issue so simply use the single byte traditional nop
 3602   // to do alignment.
 3603 
 3604   for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
 3605   return;
 3606 
 3607 #endif // ASSERT
 3608 
 3609   if (UseAddressNop && VM_Version::is_intel()) {
 3610     //
 3611     // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
 3612     //  1: 0x90
 3613     //  2: 0x66 0x90
 3614     //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
 3615     //  4: 0x0F 0x1F 0x40 0x00
 3616     //  5: 0x0F 0x1F 0x44 0x00 0x00
 3617     //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
 3618     //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
 3619     //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3620     //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3621     // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3622     // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3623 
 3624     // The rest coding is Intel specific - don't use consecutive address nops
 3625 
 3626     // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3627     // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3628     // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3629     // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3630 
 3631     while(i >= 15) {
 3632       // For Intel don't generate consecutive address nops (mix with regular nops)
 3633       i -= 15;
 3634       emit_int24(0x66, 0x66, 0x66);
 3635       addr_nop_8();
 3636       emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
 3637     }
 3638     switch (i) {
 3639       case 14:
 3640         emit_int8(0x66); // size prefix
 3641       case 13:
 3642         emit_int8(0x66); // size prefix
 3643       case 12:
 3644         addr_nop_8();
 3645         emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
 3646         break;
 3647       case 11:
 3648         emit_int8(0x66); // size prefix
 3649       case 10:
 3650         emit_int8(0x66); // size prefix
 3651       case 9:
 3652         emit_int8(0x66); // size prefix
 3653       case 8:
 3654         addr_nop_8();
 3655         break;
 3656       case 7:
 3657         addr_nop_7();
 3658         break;
 3659       case 6:
 3660         emit_int8(0x66); // size prefix
 3661       case 5:
 3662         addr_nop_5();
 3663         break;
 3664       case 4:
 3665         addr_nop_4();
 3666         break;
 3667       case 3:
 3668         // Don't use "0x0F 0x1F 0x00" - need patching safe padding
 3669         emit_int8(0x66); // size prefix
 3670       case 2:
 3671         emit_int8(0x66); // size prefix
 3672       case 1:
 3673         emit_int8((unsigned char)0x90);
 3674                          // nop
 3675         break;
 3676       default:
 3677         assert(i == 0, " ");
 3678     }
 3679     return;
 3680   }
 3681   if (UseAddressNop && VM_Version::is_amd_family()) {
 3682     //
 3683     // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
 3684     //  1: 0x90
 3685     //  2: 0x66 0x90
 3686     //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
 3687     //  4: 0x0F 0x1F 0x40 0x00
 3688     //  5: 0x0F 0x1F 0x44 0x00 0x00
 3689     //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
 3690     //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
 3691     //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3692     //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3693     // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3694     // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3695 
 3696     // The rest coding is AMD specific - use consecutive address nops
 3697 
 3698     // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
 3699     // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
 3700     // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
 3701     // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
 3702     // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3703     //     Size prefixes (0x66) are added for larger sizes
 3704 
 3705     while(i >= 22) {
 3706       i -= 11;
 3707       emit_int24(0x66, 0x66, 0x66);
 3708       addr_nop_8();
 3709     }
 3710     // Generate first nop for size between 21-12
 3711     switch (i) {
 3712       case 21:
 3713         i -= 1;
 3714         emit_int8(0x66); // size prefix
 3715       case 20:
 3716       case 19:
 3717         i -= 1;
 3718         emit_int8(0x66); // size prefix
 3719       case 18:
 3720       case 17:
 3721         i -= 1;
 3722         emit_int8(0x66); // size prefix
 3723       case 16:
 3724       case 15:
 3725         i -= 8;
 3726         addr_nop_8();
 3727         break;
 3728       case 14:
 3729       case 13:
 3730         i -= 7;
 3731         addr_nop_7();
 3732         break;
 3733       case 12:
 3734         i -= 6;
 3735         emit_int8(0x66); // size prefix
 3736         addr_nop_5();
 3737         break;
 3738       default:
 3739         assert(i < 12, " ");
 3740     }
 3741 
 3742     // Generate second nop for size between 11-1
 3743     switch (i) {
 3744       case 11:
 3745         emit_int8(0x66); // size prefix
 3746       case 10:
 3747         emit_int8(0x66); // size prefix
 3748       case 9:
 3749         emit_int8(0x66); // size prefix
 3750       case 8:
 3751         addr_nop_8();
 3752         break;
 3753       case 7:
 3754         addr_nop_7();
 3755         break;
 3756       case 6:
 3757         emit_int8(0x66); // size prefix
 3758       case 5:
 3759         addr_nop_5();
 3760         break;
 3761       case 4:
 3762         addr_nop_4();
 3763         break;
 3764       case 3:
 3765         // Don't use "0x0F 0x1F 0x00" - need patching safe padding
 3766         emit_int8(0x66); // size prefix
 3767       case 2:
 3768         emit_int8(0x66); // size prefix
 3769       case 1:
 3770         emit_int8((unsigned char)0x90);
 3771                          // nop
 3772         break;
 3773       default:
 3774         assert(i == 0, " ");
 3775     }
 3776     return;
 3777   }
 3778 
 3779   if (UseAddressNop && VM_Version::is_zx()) {
 3780     //
 3781     // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
 3782     //  1: 0x90
 3783     //  2: 0x66 0x90
 3784     //  3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
 3785     //  4: 0x0F 0x1F 0x40 0x00
 3786     //  5: 0x0F 0x1F 0x44 0x00 0x00
 3787     //  6: 0x66 0x0F 0x1F 0x44 0x00 0x00
 3788     //  7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
 3789     //  8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3790     //  9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3791     // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3792     // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
 3793 
 3794     // The rest coding is ZX specific - don't use consecutive address nops
 3795 
 3796     // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3797     // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3798     // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3799     // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
 3800 
 3801     while (i >= 15) {
 3802       // For ZX don't generate consecutive address nops (mix with regular nops)
 3803       i -= 15;
 3804       emit_int24(0x66, 0x66, 0x66);
 3805       addr_nop_8();
 3806       emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
 3807     }
 3808     switch (i) {
 3809       case 14:
 3810         emit_int8(0x66); // size prefix
 3811       case 13:
 3812         emit_int8(0x66); // size prefix
 3813       case 12:
 3814         addr_nop_8();
 3815         emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
 3816         break;
 3817       case 11:
 3818         emit_int8(0x66); // size prefix
 3819       case 10:
 3820         emit_int8(0x66); // size prefix
 3821       case 9:
 3822         emit_int8(0x66); // size prefix
 3823       case 8:
 3824         addr_nop_8();
 3825         break;
 3826       case 7:
 3827         addr_nop_7();
 3828         break;
 3829       case 6:
 3830         emit_int8(0x66); // size prefix
 3831       case 5:
 3832         addr_nop_5();
 3833         break;
 3834       case 4:
 3835         addr_nop_4();
 3836         break;
 3837       case 3:
 3838         // Don't use "0x0F 0x1F 0x00" - need patching safe padding
 3839         emit_int8(0x66); // size prefix
 3840       case 2:
 3841         emit_int8(0x66); // size prefix
 3842       case 1:
 3843         emit_int8((unsigned char)0x90);
 3844                          // nop
 3845         break;
 3846       default:
 3847         assert(i == 0, " ");
 3848     }
 3849     return;
 3850   }
 3851 
 3852   // Using nops with size prefixes "0x66 0x90".
 3853   // From AMD Optimization Guide:
 3854   //  1: 0x90
 3855   //  2: 0x66 0x90
 3856   //  3: 0x66 0x66 0x90
 3857   //  4: 0x66 0x66 0x66 0x90
 3858   //  5: 0x66 0x66 0x90 0x66 0x90
 3859   //  6: 0x66 0x66 0x90 0x66 0x66 0x90
 3860   //  7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
 3861   //  8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
 3862   //  9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
 3863   // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
 3864   //
 3865   while (i > 12) {
 3866     i -= 4;
 3867     emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
 3868   }
 3869   // 1 - 12 nops
 3870   if (i > 8) {
 3871     if (i > 9) {
 3872       i -= 1;
 3873       emit_int8(0x66);
 3874     }
 3875     i -= 3;
 3876     emit_int24(0x66, 0x66, (unsigned char)0x90);
 3877   }
 3878   // 1 - 8 nops
 3879   if (i > 4) {
 3880     if (i > 6) {
 3881       i -= 1;
 3882       emit_int8(0x66);
 3883     }
 3884     i -= 3;
 3885     emit_int24(0x66, 0x66, (unsigned char)0x90);
 3886   }
 3887   switch (i) {
 3888     case 4:
 3889       emit_int8(0x66);
 3890     case 3:
 3891       emit_int8(0x66);
 3892     case 2:
 3893       emit_int8(0x66);
 3894     case 1:
 3895       emit_int8((unsigned char)0x90);
 3896       break;
 3897     default:
 3898       assert(i == 0, " ");
 3899   }
 3900 }
 3901 
 3902 void Assembler::notl(Register dst) {
 3903   int encode = prefix_and_encode(dst->encoding());
 3904   emit_int16((unsigned char)0xF7, (0xD0 | encode));
 3905 }
 3906 
 3907 void Assembler::orw(Register dst, Register src) {
 3908   (void)prefix_and_encode(dst->encoding(), src->encoding());
 3909   emit_arith(0x0B, 0xC0, dst, src);
 3910 }
 3911 
 3912 void Assembler::orl(Address dst, int32_t imm32) {
 3913   InstructionMark im(this);
 3914   prefix(dst);
 3915   emit_arith_operand(0x81, rcx, dst, imm32);
 3916 }
 3917 
 3918 void Assembler::orl(Register dst, int32_t imm32) {
 3919   prefix(dst);
 3920   emit_arith(0x81, 0xC8, dst, imm32);
 3921 }
 3922 
 3923 void Assembler::orl(Register dst, Address src) {
 3924   InstructionMark im(this);
 3925   prefix(src, dst);
 3926   emit_int8(0x0B);
 3927   emit_operand(dst, src);
 3928 }
 3929 
 3930 void Assembler::orl(Register dst, Register src) {
 3931   (void) prefix_and_encode(dst->encoding(), src->encoding());
 3932   emit_arith(0x0B, 0xC0, dst, src);
 3933 }
 3934 
 3935 void Assembler::orl(Address dst, Register src) {
 3936   InstructionMark im(this);
 3937   prefix(dst, src);
 3938   emit_int8(0x09);
 3939   emit_operand(src, dst);
 3940 }
 3941 
 3942 void Assembler::orb(Address dst, int imm8) {
 3943   InstructionMark im(this);
 3944   prefix(dst);
 3945   emit_int8((unsigned char)0x80);
 3946   emit_operand(rcx, dst, 1);
 3947   emit_int8(imm8);
 3948 }
 3949 
 3950 void Assembler::orb(Address dst, Register src) {
 3951   InstructionMark im(this);
 3952   prefix(dst, src, true);
 3953   emit_int8(0x08);
 3954   emit_operand(src, dst);
 3955 }
 3956 
 3957 void Assembler::packsswb(XMMRegister dst, XMMRegister src) {
 3958   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3959   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3960   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3961   emit_int16(0x63, (0xC0 | encode));
 3962 }
 3963 
 3964 void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3965   assert(UseAVX > 0, "some form of AVX must be enabled");
 3966   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3967   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3968   emit_int16(0x63, (0xC0 | encode));
 3969 }
 3970 
 3971 void Assembler::packssdw(XMMRegister dst, XMMRegister src) {
 3972   assert(VM_Version::supports_sse2(), "");
 3973   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3974   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3975   emit_int16(0x6B, (0xC0 | encode));
 3976 }
 3977 
 3978 void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 3979   assert(UseAVX > 0, "some form of AVX must be enabled");
 3980   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3981   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3982   emit_int16(0x6B, (0xC0 | encode));
 3983 }
 3984 
 3985 void Assembler::packuswb(XMMRegister dst, Address src) {
 3986   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3987   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 3988   InstructionMark im(this);
 3989   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3990   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 3991   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 3992   emit_int8(0x67);
 3993   emit_operand(dst, src);
 3994 }
 3995 
 3996 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
 3997   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 3998   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 3999   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4000   emit_int16(0x67, (0xC0 | encode));
 4001 }
 4002 
 4003 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4004   assert(UseAVX > 0, "some form of AVX must be enabled");
 4005   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4006   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4007   emit_int16(0x67, (0xC0 | encode));
 4008 }
 4009 
 4010 void Assembler::packusdw(XMMRegister dst, XMMRegister src) {
 4011   assert(VM_Version::supports_sse4_1(), "");
 4012   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4013   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4014   emit_int16(0x2B, (0xC0 | encode));
 4015 }
 4016 
 4017 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4018   assert(UseAVX > 0, "some form of AVX must be enabled");
 4019   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4020   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4021   emit_int16(0x2B, (0xC0 | encode));
 4022 }
 4023 
 4024 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
 4025   assert(VM_Version::supports_avx2(), "");
 4026   assert(vector_len != AVX_128bit, "");
 4027   // VEX.256.66.0F3A.W1 00 /r ib
 4028   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4029   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4030   emit_int24(0x00, (0xC0 | encode), imm8);
 4031 }
 4032 
 4033 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4034   assert(vector_len == AVX_256bit ? VM_Version::supports_avx512vl() :
 4035          vector_len == AVX_512bit ? VM_Version::supports_evex()     : false, "not supported");
 4036   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4037   attributes.set_is_evex_instruction();
 4038   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4039   emit_int16(0x36, (0xC0 | encode));
 4040 }
 4041 
 4042 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4043   assert(VM_Version::supports_avx512_vbmi(), "");
 4044   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4045   attributes.set_is_evex_instruction();
 4046   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4047   emit_int16((unsigned char)0x8D, (0xC0 | encode));
 4048 }
 4049 
 4050 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 4051   assert(VM_Version::supports_avx512_vbmi(), "");
 4052   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4053   attributes.set_is_evex_instruction();
 4054   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4055   emit_int8((unsigned char)0x8D);
 4056   emit_operand(dst, src);
 4057 }
 4058 
 4059 void Assembler::vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4060   assert(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() :
 4061          vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() :
 4062          vector_len == AVX_512bit ? VM_Version::supports_avx512bw()   : false, "not supported");
 4063   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4064   attributes.set_is_evex_instruction();
 4065   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4066   emit_int16((unsigned char)0x8D, (0xC0 | encode));
 4067 }
 4068 
 4069 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4070   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
 4071   // VEX.NDS.256.66.0F38.W0 36 /r
 4072   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4073   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4074   emit_int16(0x36, (0xC0 | encode));
 4075 }
 4076 
 4077 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 4078   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
 4079   // VEX.NDS.256.66.0F38.W0 36 /r
 4080   InstructionMark im(this);
 4081   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4082   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4083   emit_int8(0x36);
 4084   emit_operand(dst, src);
 4085 }
 4086 
 4087 void Assembler::vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8) {
 4088   assert(VM_Version::supports_avx2(), "");
 4089   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4090   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4091   emit_int24(0x46, (0xC0 | encode), imm8);
 4092 }
 4093 
 4094 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
 4095   assert(VM_Version::supports_avx(), "");
 4096   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4097   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4098   emit_int24(0x06, (0xC0 | encode), imm8);
 4099 }
 4100 
 4101 void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
 4102   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 4103   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 4104   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4105   emit_int24(0x04, (0xC0 | encode), imm8);
 4106 }
 4107 
 4108 void Assembler::vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
 4109   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
 4110   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(),/* legacy_mode */ false,/* no_mask_reg */ true, /* uses_vl */ false);
 4111   attributes.set_rex_vex_w_reverted();
 4112   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4113   emit_int24(0x05, (0xC0 | encode), imm8);
 4114 }
 4115 
 4116 void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
 4117   assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
 4118   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ false);
 4119   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4120   emit_int24(0x01, (0xC0 | encode), imm8);
 4121 }
 4122 
 4123 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4124   assert(VM_Version::supports_evex(), "");
 4125   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4126   attributes.set_is_evex_instruction();
 4127   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4128   emit_int16(0x76, (0xC0 | encode));
 4129 }
 4130 
 4131 void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4132   assert(VM_Version::supports_avx512_vbmi(), "");
 4133   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4134   attributes.set_is_evex_instruction();
 4135   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4136   emit_int16(0x7D, (0xC0 | encode));
 4137 }
 4138 
 4139 void Assembler::evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) {
 4140   assert(VM_Version::supports_avx512_vbmi(), "");
 4141   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4142   attributes.set_is_evex_instruction();
 4143   int encode = vex_prefix_and_encode(dst->encoding(), ctl->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4144   emit_int16((unsigned char)0x83, (unsigned char)(0xC0 | encode));
 4145 }
 4146 
 4147 void Assembler::pause() {
 4148   emit_int16((unsigned char)0xF3, (unsigned char)0x90);
 4149 }
 4150 
 4151 void Assembler::ud2() {
 4152   emit_int16(0x0F, 0x0B);
 4153 }
 4154 
 4155 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
 4156   assert(VM_Version::supports_sse4_2(), "");
 4157   InstructionMark im(this);
 4158   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4159   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4160   emit_int8(0x61);
 4161   emit_operand(dst, src);
 4162   emit_int8(imm8);
 4163 }
 4164 
 4165 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
 4166   assert(VM_Version::supports_sse4_2(), "");
 4167   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4168   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4169   emit_int24(0x61, (0xC0 | encode), imm8);
 4170 }
 4171 
 4172 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4173 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
 4174   assert(VM_Version::supports_sse2(), "");
 4175   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4176   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4177   emit_int16(0x74, (0xC0 | encode));
 4178 }
 4179 
 4180 void Assembler::vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
 4181   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
 4182   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
 4183   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4184   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4185   emit_int16(cond_encoding, (0xC0 | encode));
 4186 }
 4187 
 4188 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4189 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4190   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
 4191   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
 4192   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4193   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4194   emit_int16(0x74, (0xC0 | encode));
 4195 }
 4196 
 4197 // In this context, kdst is written the mask used to process the equal components
 4198 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
 4199   assert(VM_Version::supports_avx512bw(), "");
 4200   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4201   attributes.set_is_evex_instruction();
 4202   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4203   emit_int16(0x74, (0xC0 | encode));
 4204 }
 4205 
 4206 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
 4207   assert(VM_Version::supports_avx512vlbw(), "");
 4208   InstructionMark im(this);
 4209   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4210   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4211   attributes.set_is_evex_instruction();
 4212   int dst_enc = kdst->encoding();
 4213   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4214   emit_int8(0x64);
 4215   emit_operand(as_Register(dst_enc), src);
 4216 }
 4217 
 4218 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
 4219   assert(VM_Version::supports_avx512vlbw(), "");
 4220   InstructionMark im(this);
 4221   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4222   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4223   attributes.reset_is_clear_context();
 4224   attributes.set_embedded_opmask_register_specifier(mask);
 4225   attributes.set_is_evex_instruction();
 4226   int dst_enc = kdst->encoding();
 4227   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4228   emit_int8(0x64);
 4229   emit_operand(as_Register(dst_enc), src);
 4230 }
 4231 
 4232 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
 4233   assert(VM_Version::supports_avx512vlbw(), "");
 4234   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4235   attributes.set_is_evex_instruction();
 4236   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4237   emit_int24(0x3E, (0xC0 | encode), vcc);
 4238 }
 4239 
 4240 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
 4241   assert(VM_Version::supports_avx512vlbw(), "");
 4242   InstructionMark im(this);
 4243   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4244   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4245   attributes.set_is_evex_instruction();
 4246   int dst_enc = kdst->encoding();
 4247   vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4248   emit_int8(0x3E);
 4249   emit_operand(as_Register(dst_enc), src);
 4250   emit_int8(vcc);
 4251 }
 4252 
 4253 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
 4254   assert(VM_Version::supports_avx512bw(), "");
 4255   InstructionMark im(this);
 4256   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4257   attributes.set_is_evex_instruction();
 4258   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4259   int dst_enc = kdst->encoding();
 4260   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4261   emit_int8(0x74);
 4262   emit_operand(as_Register(dst_enc), src);
 4263 }
 4264 
 4265 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
 4266   assert(VM_Version::supports_avx512vlbw(), "");
 4267   InstructionMark im(this);
 4268   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4269   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4270   attributes.reset_is_clear_context();
 4271   attributes.set_embedded_opmask_register_specifier(mask);
 4272   attributes.set_is_evex_instruction();
 4273   vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4274   emit_int8(0x74);
 4275   emit_operand(as_Register(kdst->encoding()), src);
 4276 }
 4277 
 4278 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4279 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
 4280   assert(VM_Version::supports_sse2(), "");
 4281   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4282   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4283   emit_int16(0x75, (0xC0 | encode));
 4284 }
 4285 
 4286 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4287 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4288   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
 4289   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
 4290   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4291   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4292   emit_int16(0x75, (0xC0 | encode));
 4293 }
 4294 
 4295 // In this context, kdst is written the mask used to process the equal components
 4296 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
 4297   assert(VM_Version::supports_avx512bw(), "");
 4298   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4299   attributes.set_is_evex_instruction();
 4300   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4301   emit_int16(0x75, (0xC0 | encode));
 4302 }
 4303 
 4304 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
 4305   assert(VM_Version::supports_avx512bw(), "");
 4306   InstructionMark im(this);
 4307   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4308   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 4309   attributes.set_is_evex_instruction();
 4310   int dst_enc = kdst->encoding();
 4311   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4312   emit_int8(0x75);
 4313   emit_operand(as_Register(dst_enc), src);
 4314 }
 4315 
 4316 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4317 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
 4318   assert(VM_Version::supports_sse2(), "");
 4319   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4320   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4321   emit_int16(0x76, (0xC0 | encode));
 4322 }
 4323 
 4324 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4325 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4326   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
 4327   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
 4328   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4329   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4330   emit_int16(0x76, (0xC0 | encode));
 4331 }
 4332 
 4333 // In this context, kdst is written the mask used to process the equal components
 4334 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
 4335   assert(VM_Version::supports_evex(), "");
 4336   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4337   attributes.set_is_evex_instruction();
 4338   attributes.reset_is_clear_context();
 4339   attributes.set_embedded_opmask_register_specifier(mask);
 4340   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4341   emit_int16(0x76, (0xC0 | encode));
 4342 }
 4343 
 4344 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
 4345   assert(VM_Version::supports_evex(), "");
 4346   InstructionMark im(this);
 4347   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4348   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 4349   attributes.set_is_evex_instruction();
 4350   attributes.reset_is_clear_context();
 4351   attributes.set_embedded_opmask_register_specifier(mask);
 4352   int dst_enc = kdst->encoding();
 4353   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4354   emit_int8(0x76);
 4355   emit_operand(as_Register(dst_enc), src);
 4356 }
 4357 
 4358 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4359 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
 4360   assert(VM_Version::supports_sse4_1(), "");
 4361   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4362   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4363   emit_int16(0x29, (0xC0 | encode));
 4364 }
 4365 
 4366 void Assembler::evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
 4367   assert(VM_Version::supports_evex(), "");
 4368   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4369   attributes.set_is_evex_instruction();
 4370   attributes.reset_is_clear_context();
 4371   attributes.set_embedded_opmask_register_specifier(mask);
 4372   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4373   emit_int16(0x29, (0xC0 | encode));
 4374 }
 4375 
 4376 void Assembler::vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
 4377   assert(VM_Version::supports_avx(), "");
 4378   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4379   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4380   emit_int16(cond_encoding, (0xC0 | encode));
 4381 }
 4382 
 4383 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
 4384 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4385   assert(VM_Version::supports_avx(), "");
 4386   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4387   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4388   emit_int16(0x29, (0xC0 | encode));
 4389 }
 4390 
 4391 // In this context, kdst is written the mask used to process the equal components
 4392 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
 4393   assert(VM_Version::supports_evex(), "");
 4394   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4395   attributes.reset_is_clear_context();
 4396   attributes.set_is_evex_instruction();
 4397   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4398   emit_int16(0x29, (0xC0 | encode));
 4399 }
 4400 
 4401 // In this context, kdst is written the mask used to process the equal components
 4402 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
 4403   assert(VM_Version::supports_evex(), "");
 4404   InstructionMark im(this);
 4405   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4406   attributes.reset_is_clear_context();
 4407   attributes.set_is_evex_instruction();
 4408   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 4409   int dst_enc = kdst->encoding();
 4410   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4411   emit_int8(0x29);
 4412   emit_operand(as_Register(dst_enc), src);
 4413 }
 4414 
 4415 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
 4416   assert(VM_Version::supports_sse4_1(), "");
 4417   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4418   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4419   emit_int16(0x37, (0xC0 | encode));
 4420 }
 4421 
 4422 void Assembler::pmovmskb(Register dst, XMMRegister src) {
 4423   assert(VM_Version::supports_sse2(), "");
 4424   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4425   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4426   emit_int16((unsigned char)0xD7, (0xC0 | encode));
 4427 }
 4428 
 4429 void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
 4430   assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||
 4431          (VM_Version::supports_avx2() && vec_enc  == AVX_256bit), "");
 4432   InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4433   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4434   emit_int16((unsigned char)0xD7, (0xC0 | encode));
 4435 }
 4436 
 4437 void Assembler::vmovmskps(Register dst, XMMRegister src, int vec_enc) {
 4438   assert(VM_Version::supports_avx(), "");
 4439   InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4440   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 4441   emit_int16(0x50, (0xC0 | encode));
 4442 }
 4443 
 4444 void Assembler::vmovmskpd(Register dst, XMMRegister src, int vec_enc) {
 4445   assert(VM_Version::supports_avx(), "");
 4446   InstructionAttr attributes(vec_enc, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 4447   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4448   emit_int16(0x50, (0xC0 | encode));
 4449 }
 4450 
 4451 
 4452 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
 4453   assert(VM_Version::supports_sse4_1(), "");
 4454   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4455   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4456   emit_int24(0x16, (0xC0 | encode), imm8);
 4457 }
 4458 
 4459 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
 4460   assert(VM_Version::supports_sse4_1(), "");
 4461   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4462   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 4463   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4464   emit_int8(0x16);
 4465   emit_operand(src, dst);
 4466   emit_int8(imm8);
 4467 }
 4468 
 4469 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
 4470   assert(VM_Version::supports_sse4_1(), "");
 4471   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4472   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4473   emit_int24(0x16, (0xC0 | encode), imm8);
 4474 }
 4475 
 4476 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
 4477   assert(VM_Version::supports_sse4_1(), "");
 4478   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4479   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 4480   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4481   emit_int8(0x16);
 4482   emit_operand(src, dst);
 4483   emit_int8(imm8);
 4484 }
 4485 
 4486 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
 4487   assert(VM_Version::supports_sse2(), "");
 4488   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4489   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4490   emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
 4491 }
 4492 
 4493 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
 4494   assert(VM_Version::supports_sse4_1(), "");
 4495   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4496   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 4497   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4498   emit_int8(0x15);
 4499   emit_operand(src, dst);
 4500   emit_int8(imm8);
 4501 }
 4502 
 4503 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
 4504   assert(VM_Version::supports_sse4_1(), "");
 4505   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4506   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4507   emit_int24(0x14, (0xC0 | encode), imm8);
 4508 }
 4509 
 4510 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
 4511   assert(VM_Version::supports_sse4_1(), "");
 4512   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4513   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
 4514   simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4515   emit_int8(0x14);
 4516   emit_operand(src, dst);
 4517   emit_int8(imm8);
 4518 }
 4519 
 4520 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
 4521   assert(VM_Version::supports_sse4_1(), "");
 4522   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4523   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4524   emit_int24(0x22, (0xC0 | encode), imm8);
 4525 }
 4526 
 4527 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
 4528   assert(VM_Version::supports_sse4_1(), "");
 4529   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4530   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 4531   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4532   emit_int8(0x22);
 4533   emit_operand(dst,src);
 4534   emit_int8(imm8);
 4535 }
 4536 
 4537 void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
 4538   assert(VM_Version::supports_avx(), "");
 4539   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4540   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4541   emit_int24(0x22, (0xC0 | encode), imm8);
 4542 }
 4543 
 4544 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
 4545   assert(VM_Version::supports_sse4_1(), "");
 4546   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4547   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4548   emit_int24(0x22, (0xC0 | encode), imm8);
 4549 }
 4550 
 4551 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
 4552   assert(VM_Version::supports_sse4_1(), "");
 4553   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4554   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 4555   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4556   emit_int8(0x22);
 4557   emit_operand(dst, src);
 4558   emit_int8(imm8);
 4559 }
 4560 
 4561 void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
 4562   assert(VM_Version::supports_avx(), "");
 4563   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
 4564   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4565   emit_int24(0x22, (0xC0 | encode), imm8);
 4566 }
 4567 
 4568 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
 4569   assert(VM_Version::supports_sse2(), "");
 4570   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4571   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4572   emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
 4573 }
 4574 
 4575 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
 4576   assert(VM_Version::supports_sse2(), "");
 4577   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4578   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 4579   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4580   emit_int8((unsigned char)0xC4);
 4581   emit_operand(dst, src);
 4582   emit_int8(imm8);
 4583 }
 4584 
 4585 void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
 4586   assert(VM_Version::supports_avx(), "");
 4587   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4588   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4589   emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
 4590 }
 4591 
 4592 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
 4593   assert(VM_Version::supports_sse4_1(), "");
 4594   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4595   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
 4596   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4597   emit_int8(0x20);
 4598   emit_operand(dst, src);
 4599   emit_int8(imm8);
 4600 }
 4601 
 4602 void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) {
 4603   assert(VM_Version::supports_sse4_1(), "");
 4604   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4605   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4606   emit_int24(0x20, (0xC0 | encode), imm8);
 4607 }
 4608 
 4609 void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
 4610   assert(VM_Version::supports_avx(), "");
 4611   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
 4612   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4613   emit_int24(0x20, (0xC0 | encode), imm8);
 4614 }
 4615 
 4616 void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) {
 4617   assert(VM_Version::supports_sse4_1(), "");
 4618   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 4619   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4620   emit_int24(0x21, (0xC0 | encode), imm8);
 4621 }
 4622 
 4623 void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
 4624   assert(VM_Version::supports_avx(), "");
 4625   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 4626   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 4627   emit_int24(0x21, (0xC0 | encode), imm8);
 4628 }
 4629 
 4630 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
 4631   assert(VM_Version::supports_sse4_1(), "");
 4632   InstructionMark im(this);
 4633   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4634   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
 4635   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4636   emit_int8(0x30);
 4637   emit_operand(dst, src);
 4638 }
 4639 
 4640 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
 4641   assert(VM_Version::supports_sse4_1(), "");
 4642   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4643   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4644   emit_int16(0x30, (0xC0 | encode));
 4645 }
 4646 
 4647 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
 4648   assert(VM_Version::supports_sse4_1(), "");
 4649   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4650   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4651   emit_int16(0x20, (0xC0 | encode));
 4652 }
 4653 
 4654 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
 4655   assert(VM_Version::supports_sse4_1(), "");
 4656   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4657   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4658   emit_int16(0x35, (0xC0 | encode));
 4659 }
 4660 
 4661 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
 4662   assert(VM_Version::supports_sse4_1(), "");
 4663   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4664   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4665   emit_int16(0x21, (0xC0 | encode));
 4666 }
 4667 
 4668 void Assembler::pmovzxbd(XMMRegister dst, XMMRegister src) {
 4669   assert(VM_Version::supports_sse4_1(), "");
 4670   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4671   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4672   emit_int16(0x31, (0xC0 | encode));
 4673 }
 4674 
 4675 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
 4676   assert(VM_Version::supports_sse4_1(), "");
 4677   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4678   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4679   emit_int16(0x22, (0xC0 | encode));
 4680 }
 4681 
 4682 void Assembler::pmovsxwd(XMMRegister dst, XMMRegister src) {
 4683   assert(VM_Version::supports_sse4_1(), "");
 4684   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4685   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4686   emit_int16(0x23, (0xC0 | encode));
 4687 }
 4688 
 4689 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
 4690   assert(VM_Version::supports_avx(), "");
 4691   InstructionMark im(this);
 4692   assert(dst != xnoreg, "sanity");
 4693   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4694   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
 4695   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4696   emit_int8(0x30);
 4697   emit_operand(dst, src);
 4698 }
 4699 
 4700 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
 4701   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 4702   vector_len == AVX_256bit? VM_Version::supports_avx2() :
 4703   vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
 4704   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4705   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4706   emit_int16(0x30, (unsigned char) (0xC0 | encode));
 4707 }
 4708 
 4709 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
 4710   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 4711   vector_len == AVX_256bit? VM_Version::supports_avx2() :
 4712   vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
 4713   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4714   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4715   emit_int16(0x20, (0xC0 | encode));
 4716 }
 4717 
 4718 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
 4719   assert(VM_Version::supports_avx512vlbw(), "");
 4720   assert(dst != xnoreg, "sanity");
 4721   InstructionMark im(this);
 4722   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
 4723   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
 4724   attributes.set_embedded_opmask_register_specifier(mask);
 4725   attributes.set_is_evex_instruction();
 4726   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4727   emit_int8(0x30);
 4728   emit_operand(dst, src);
 4729 }
 4730 
 4731 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 4732   assert(VM_Version::supports_evex(), "");
 4733   // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
 4734   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4735   attributes.set_is_evex_instruction();
 4736   attributes.set_embedded_opmask_register_specifier(mask);
 4737   if (merge) {
 4738     attributes.reset_is_clear_context();
 4739   }
 4740   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4741   emit_int16((unsigned char)0xDB, (0xC0 | encode));
 4742 }
 4743 
 4744 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
 4745   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
 4746   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4747   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4748   emit_int16(0x35, (0xC0 | encode));
 4749 }
 4750 
 4751 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
 4752   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
 4753   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4754   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4755   emit_int16(0x31, (0xC0 | encode));
 4756 }
 4757 
 4758 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
 4759   assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
 4760   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4761   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4762   emit_int16(0x32, (0xC0 | encode));
 4763 }
 4764 
 4765 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
 4766   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4767          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4768              VM_Version::supports_evex(), "");
 4769   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4770   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4771   emit_int16(0x21, (0xC0 | encode));
 4772 }
 4773 
 4774 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
 4775   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4776          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4777              VM_Version::supports_evex(), "");
 4778   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4779   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4780   emit_int16(0x22, (0xC0 | encode));
 4781 }
 4782 
 4783 void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
 4784   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4785          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4786              VM_Version::supports_evex(), "");
 4787   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4788   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4789   emit_int16(0x23, (0xC0 | encode));
 4790 }
 4791 
 4792 void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
 4793   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4794          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4795              VM_Version::supports_evex(), "");
 4796   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4797   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4798   emit_int16(0x24, (0xC0 | encode));
 4799 }
 4800 
 4801 void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
 4802   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4803          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4804              VM_Version::supports_evex(), "");
 4805   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4806   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4807   emit_int16(0x25, (0xC0 | encode));
 4808 }
 4809 
 4810 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
 4811   assert(VM_Version::supports_avx512vlbw(), "");
 4812   assert(src != xnoreg, "sanity");
 4813   InstructionMark im(this);
 4814   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4815   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
 4816   attributes.set_is_evex_instruction();
 4817   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 4818   emit_int8(0x30);
 4819   emit_operand(src, dst);
 4820 }
 4821 
 4822 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
 4823   assert(VM_Version::supports_avx512vlbw(), "");
 4824   assert(src != xnoreg, "sanity");
 4825   InstructionMark im(this);
 4826   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4827   attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
 4828   attributes.reset_is_clear_context();
 4829   attributes.set_embedded_opmask_register_specifier(mask);
 4830   attributes.set_is_evex_instruction();
 4831   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 4832   emit_int8(0x30);
 4833   emit_operand(src, dst);
 4834 }
 4835 
 4836 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
 4837   assert(VM_Version::supports_evex(), "");
 4838   assert(src != xnoreg, "sanity");
 4839   InstructionMark im(this);
 4840   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4841   attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
 4842   attributes.set_is_evex_instruction();
 4843   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
 4844   emit_int8(0x31);
 4845   emit_operand(src, dst);
 4846 }
 4847 
 4848 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
 4849   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 4850   vector_len == AVX_256bit? VM_Version::supports_avx2() :
 4851   vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
 4852   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4853   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4854   emit_int16(0x33, (0xC0 | encode));
 4855 }
 4856 
 4857 void Assembler::vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len) {
 4858   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 4859   vector_len == AVX_256bit? VM_Version::supports_avx2() :
 4860   vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
 4861   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4862   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4863   emit_int16(0x34, (0xC0 | encode));
 4864 }
 4865 
 4866 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
 4867   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 4868   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4869   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4870   emit_int16((unsigned char)0xF5, (0xC0 | encode));
 4871 }
 4872 
 4873 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4874   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 4875     (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 4876     (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
 4877   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4878   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 4879   emit_int16((unsigned char)0xF5, (0xC0 | encode));
 4880 }
 4881 
 4882 void Assembler::vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
 4883 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 4884        vector_len == AVX_256bit? VM_Version::supports_avx2() :
 4885        vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
 4886   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 4887   int encode = simd_prefix_and_encode(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4888   emit_int16(0x04, (0xC0 | encode));
 4889 }
 4890 
 4891 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 4892   assert(VM_Version::supports_evex(), "");
 4893   assert(VM_Version::supports_avx512_vnni(), "must support vnni");
 4894   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 4895   attributes.set_is_evex_instruction();
 4896   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4897   emit_int16(0x52, (0xC0 | encode));
 4898 }
 4899 
 4900 // generic
 4901 void Assembler::pop(Register dst) {
 4902   int encode = prefix_and_encode(dst->encoding());
 4903   emit_int8(0x58 | encode);
 4904 }
 4905 
 4906 void Assembler::popcntl(Register dst, Address src) {
 4907   assert(VM_Version::supports_popcnt(), "must support");
 4908   InstructionMark im(this);
 4909   emit_int8((unsigned char)0xF3);
 4910   prefix(src, dst);
 4911   emit_int16(0x0F, (unsigned char)0xB8);
 4912   emit_operand(dst, src);
 4913 }
 4914 
 4915 void Assembler::popcntl(Register dst, Register src) {
 4916   assert(VM_Version::supports_popcnt(), "must support");
 4917   emit_int8((unsigned char)0xF3);
 4918   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 4919   emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
 4920 }
 4921 
 4922 void Assembler::evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4923   assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
 4924   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4925   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4926   attributes.set_embedded_opmask_register_specifier(mask);
 4927   attributes.set_is_evex_instruction();
 4928   if (merge) {
 4929     attributes.reset_is_clear_context();
 4930   }
 4931   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4932   emit_int16(0x54, (0xC0 | encode));
 4933 }
 4934 
 4935 void Assembler::evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4936   assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
 4937   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4938   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4939   attributes.set_is_evex_instruction();
 4940   attributes.set_embedded_opmask_register_specifier(mask);
 4941   if (merge) {
 4942     attributes.reset_is_clear_context();
 4943   }
 4944   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4945   emit_int16(0x54, (0xC0 | encode));
 4946 }
 4947 
 4948 void Assembler::evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4949   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4950   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4951   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4952   attributes.set_is_evex_instruction();
 4953   attributes.set_embedded_opmask_register_specifier(mask);
 4954   if (merge) {
 4955     attributes.reset_is_clear_context();
 4956   }
 4957   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4958   emit_int16(0x55, (0xC0 | encode));
 4959 }
 4960 
 4961 void Assembler::evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4962   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4963   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4964   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4965   attributes.set_is_evex_instruction();
 4966   attributes.set_embedded_opmask_register_specifier(mask);
 4967   if (merge) {
 4968     attributes.reset_is_clear_context();
 4969   }
 4970   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4971   emit_int16(0x55, (0xC0 | encode));
 4972 }
 4973 
 4974 void Assembler::popf() {
 4975   emit_int8((unsigned char)0x9D);
 4976 }
 4977 
 4978 #ifndef _LP64 // no 32bit push/pop on amd64
 4979 void Assembler::popl(Address dst) {
 4980   // NOTE: this will adjust stack by 8byte on 64bits
 4981   InstructionMark im(this);
 4982   prefix(dst);
 4983   emit_int8((unsigned char)0x8F);
 4984   emit_operand(rax, dst);
 4985 }
 4986 #endif
 4987 
 4988 void Assembler::prefetchnta(Address src) {
 4989   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
 4990   InstructionMark im(this);
 4991   prefix(src);
 4992   emit_int16(0x0F, 0x18);
 4993   emit_operand(rax, src); // 0, src
 4994 }
 4995 
 4996 void Assembler::prefetchr(Address src) {
 4997   assert(VM_Version::supports_3dnow_prefetch(), "must support");
 4998   InstructionMark im(this);
 4999   prefix(src);
 5000   emit_int16(0x0F, 0x0D);
 5001   emit_operand(rax, src); // 0, src
 5002 }
 5003 
 5004 void Assembler::prefetcht0(Address src) {
 5005   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
 5006   InstructionMark im(this);
 5007   prefix(src);
 5008   emit_int16(0x0F, 0x18);
 5009   emit_operand(rcx, src); // 1, src
 5010 }
 5011 
 5012 void Assembler::prefetcht1(Address src) {
 5013   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
 5014   InstructionMark im(this);
 5015   prefix(src);
 5016   emit_int16(0x0F, 0x18);
 5017   emit_operand(rdx, src); // 2, src
 5018 }
 5019 
 5020 void Assembler::prefetcht2(Address src) {
 5021   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
 5022   InstructionMark im(this);
 5023   prefix(src);
 5024   emit_int16(0x0F, 0x18);
 5025   emit_operand(rbx, src); // 3, src
 5026 }
 5027 
 5028 void Assembler::prefetchw(Address src) {
 5029   assert(VM_Version::supports_3dnow_prefetch(), "must support");
 5030   InstructionMark im(this);
 5031   prefix(src);
 5032   emit_int16(0x0F, 0x0D);
 5033   emit_operand(rcx, src); // 1, src
 5034 }
 5035 
 5036 void Assembler::prefix(Prefix p) {
 5037   emit_int8(p);
 5038 }
 5039 
 5040 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
 5041   assert(VM_Version::supports_ssse3(), "");
 5042   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5043   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5044   emit_int16(0x00, (0xC0 | encode));
 5045 }
 5046 
 5047 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 5048   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 5049          vector_len == AVX_256bit? VM_Version::supports_avx2() :
 5050          vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
 5051   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5052   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5053   emit_int16(0x00, (0xC0 | encode));
 5054 }
 5055 
 5056 void Assembler::pshufb(XMMRegister dst, Address src) {
 5057   assert(VM_Version::supports_ssse3(), "");
 5058   InstructionMark im(this);
 5059   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5060   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 5061   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5062   emit_int8(0x00);
 5063   emit_operand(dst, src);
 5064 }
 5065 
 5066 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
 5067   assert(isByte(mode), "invalid value");
 5068   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5069   int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
 5070   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5071   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5072   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
 5073 }
 5074 
 5075 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
 5076   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 5077          (vector_len == AVX_256bit? VM_Version::supports_avx2() :
 5078          (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
 5079   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5080   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5081   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5082   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
 5083 }
 5084 
 5085 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
 5086   assert(isByte(mode), "invalid value");
 5087   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5088   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 5089   InstructionMark im(this);
 5090   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5091   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 5092   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5093   emit_int8(0x70);
 5094   emit_operand(dst, src);
 5095   emit_int8(mode & 0xFF);
 5096 }
 5097 
 5098 void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) {
 5099   assert(isByte(mode), "invalid value");
 5100   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5101   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5102   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5103   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
 5104 }
 5105 
 5106 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
 5107   assert(isByte(mode), "invalid value");
 5108   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5109   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5110   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5111   emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
 5112 }
 5113 
 5114 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
 5115   assert(isByte(mode), "invalid value");
 5116   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5117   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 5118   InstructionMark im(this);
 5119   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5120   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 5121   simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5122   emit_int8(0x70);
 5123   emit_operand(dst, src);
 5124   emit_int8(mode & 0xFF);
 5125 }
 5126 
 5127 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
 5128   assert(VM_Version::supports_evex(), "requires EVEX support");
 5129   assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
 5130   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5131   attributes.set_is_evex_instruction();
 5132   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5133   emit_int24(0x43, (0xC0 | encode), imm8 & 0xFF);
 5134 }
 5135 
 5136 void Assembler::pshufpd(XMMRegister dst, XMMRegister src, int imm8) {
 5137   assert(isByte(imm8), "invalid value");
 5138   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5139   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5140   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5141   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
 5142 }
 5143 
 5144 void Assembler::vpshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
 5145   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5146   attributes.set_rex_vex_w_reverted();
 5147   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5148   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
 5149 }
 5150 
 5151 void Assembler::pshufps(XMMRegister dst, XMMRegister src, int imm8) {
 5152   assert(isByte(imm8), "invalid value");
 5153   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5154   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5155   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 5156   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
 5157 }
 5158 
 5159 void Assembler::vpshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
 5160   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5161   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 5162   emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
 5163 }
 5164 
 5165 void Assembler::psrldq(XMMRegister dst, int shift) {
 5166   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
 5167   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5168   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5169   int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5170   emit_int24(0x73, (0xC0 | encode), shift);
 5171 }
 5172 
 5173 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 5174   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 5175          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 5176          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
 5177   InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5178   int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5179   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 5180 }
 5181 
 5182 void Assembler::pslldq(XMMRegister dst, int shift) {
 5183   // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
 5184   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5185   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5186   // XMM7 is for /7 encoding: 66 0F 73 /7 ib
 5187   int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5188   emit_int24(0x73, (0xC0 | encode), shift);
 5189 }
 5190 
 5191 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 5192   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 5193          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 5194          vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
 5195   InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5196   int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5197   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 5198 }
 5199 
 5200 void Assembler::ptest(XMMRegister dst, Address src) {
 5201   assert(VM_Version::supports_sse4_1(), "");
 5202   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 5203   InstructionMark im(this);
 5204   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5205   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5206   emit_int8(0x17);
 5207   emit_operand(dst, src);
 5208 }
 5209 
 5210 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
 5211   assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
 5212   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5213   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5214   emit_int8(0x17);
 5215   emit_int8((0xC0 | encode));
 5216 }
 5217 
 5218 void Assembler::vptest(XMMRegister dst, Address src) {
 5219   assert(VM_Version::supports_avx(), "");
 5220   InstructionMark im(this);
 5221   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5222   assert(dst != xnoreg, "sanity");
 5223   // swap src<->dst for encoding
 5224   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5225   emit_int8(0x17);
 5226   emit_operand(dst, src);
 5227 }
 5228 
 5229 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
 5230   assert(VM_Version::supports_avx(), "");
 5231   InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5232   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5233   emit_int16(0x17, (0xC0 | encode));
 5234 }
 5235 
 5236 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
 5237   assert(VM_Version::supports_avx(), "");
 5238   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5239   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5240   emit_int16(0x17, (0xC0 | encode));
 5241 }
 5242 
 5243 void Assembler::evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 5244   assert(VM_Version::supports_avx512vlbw(), "");
 5245   // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
 5246   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5247   attributes.set_is_evex_instruction();
 5248   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 5249   emit_int16((unsigned char)0x26, (0xC0 | encode));
 5250 }
 5251 
 5252 void Assembler::punpcklbw(XMMRegister dst, Address src) {
 5253   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5254   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 5255   InstructionMark im(this);
 5256   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
 5257   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 5258   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5259   emit_int8(0x60);
 5260   emit_operand(dst, src);
 5261 }
 5262 
 5263 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
 5264   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5265   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
 5266   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5267   emit_int16(0x60, (0xC0 | encode));
 5268 }
 5269 
 5270 void Assembler::punpckldq(XMMRegister dst, Address src) {
 5271   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5272   assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
 5273   InstructionMark im(this);
 5274   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5275   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 5276   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5277   emit_int8(0x62);
 5278   emit_operand(dst, src);
 5279 }
 5280 
 5281 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
 5282   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5283   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5284   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5285   emit_int16(0x62, (0xC0 | encode));
 5286 }
 5287 
 5288 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
 5289   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5290   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5291   attributes.set_rex_vex_w_reverted();
 5292   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5293   emit_int16(0x6C, (0xC0 | encode));
 5294 }
 5295 
 5296 void Assembler::push(int32_t imm32) {
 5297   // in 64bits we push 64bits onto the stack but only
 5298   // take a 32bit immediate
 5299   emit_int8(0x68);
 5300   emit_int32(imm32);
 5301 }
 5302 
 5303 void Assembler::push(Register src) {
 5304   int encode = prefix_and_encode(src->encoding());
 5305   emit_int8(0x50 | encode);
 5306 }
 5307 
 5308 void Assembler::pushf() {
 5309   emit_int8((unsigned char)0x9C);
 5310 }
 5311 
 5312 #ifndef _LP64 // no 32bit push/pop on amd64
 5313 void Assembler::pushl(Address src) {
 5314   // Note this will push 64bit on 64bit
 5315   InstructionMark im(this);
 5316   prefix(src);
 5317   emit_int8((unsigned char)0xFF);
 5318   emit_operand(rsi, src);
 5319 }
 5320 #endif
 5321 
 5322 void Assembler::rcll(Register dst, int imm8) {
 5323   assert(isShiftCount(imm8), "illegal shift count");
 5324   int encode = prefix_and_encode(dst->encoding());
 5325   if (imm8 == 1) {
 5326     emit_int16((unsigned char)0xD1, (0xD0 | encode));
 5327   } else {
 5328     emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
 5329   }
 5330 }
 5331 
 5332 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
 5333   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5334   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5335   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 5336   emit_int16(0x53, (0xC0 | encode));
 5337 }
 5338 
 5339 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
 5340   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5341   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5342   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5343   emit_int16(0x53, (0xC0 | encode));
 5344 }
 5345 
 5346 void Assembler::rdtsc() {
 5347   emit_int16(0x0F, 0x31);
 5348 }
 5349 
 5350 // copies data from [esi] to [edi] using rcx pointer sized words
 5351 // generic
 5352 void Assembler::rep_mov() {
 5353   // REP
 5354   // MOVSQ
 5355   LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
 5356   NOT_LP64( emit_int16((unsigned char)0xF3,        (unsigned char)0xA5);)
 5357 }
 5358 
 5359 // sets rcx bytes with rax, value at [edi]
 5360 void Assembler::rep_stosb() {
 5361   // REP
 5362   // STOSB
 5363   LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
 5364   NOT_LP64( emit_int16((unsigned char)0xF3,        (unsigned char)0xAA);)
 5365 }
 5366 
 5367 // sets rcx pointer sized words with rax, value at [edi]
 5368 // generic
 5369 void Assembler::rep_stos() {
 5370   // REP
 5371   // LP64:STOSQ, LP32:STOSD
 5372   LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
 5373   NOT_LP64( emit_int16((unsigned char)0xF3,        (unsigned char)0xAB);)
 5374 }
 5375 
 5376 // scans rcx pointer sized words at [edi] for occurrence of rax,
 5377 // generic
 5378 void Assembler::repne_scan() { // repne_scan
 5379   // SCASQ
 5380   LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
 5381   NOT_LP64( emit_int16((unsigned char)0xF2,        (unsigned char)0xAF);)
 5382 }
 5383 
 5384 #ifdef _LP64
 5385 // scans rcx 4 byte words at [edi] for occurrence of rax,
 5386 // generic
 5387 void Assembler::repne_scanl() { // repne_scan
 5388   // SCASL
 5389   emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
 5390 }
 5391 #endif
 5392 
 5393 void Assembler::ret(int imm16) {
 5394   if (imm16 == 0) {
 5395     emit_int8((unsigned char)0xC3);
 5396   } else {
 5397     emit_int8((unsigned char)0xC2);
 5398     emit_int16(imm16);
 5399   }
 5400 }
 5401 
 5402 void Assembler::roll(Register dst, int imm8) {
 5403   assert(isShiftCount(imm8), "illegal shift count");
 5404   int encode = prefix_and_encode(dst->encoding());
 5405   if (imm8 == 1) {
 5406     emit_int16((unsigned char)0xD1, (0xC0 | encode));
 5407   } else {
 5408     emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
 5409   }
 5410 }
 5411 
 5412 void Assembler::roll(Register dst) {
 5413   int encode = prefix_and_encode(dst->encoding());
 5414   emit_int16((unsigned char)0xD3, (0xC0 | encode));
 5415 }
 5416 
 5417 void Assembler::rorl(Register dst, int imm8) {
 5418   assert(isShiftCount(imm8), "illegal shift count");
 5419   int encode = prefix_and_encode(dst->encoding());
 5420   if (imm8 == 1) {
 5421     emit_int16((unsigned char)0xD1, (0xC8 | encode));
 5422   } else {
 5423     emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
 5424   }
 5425 }
 5426 
 5427 void Assembler::rorl(Register dst) {
 5428   int encode = prefix_and_encode(dst->encoding());
 5429   emit_int16((unsigned char)0xD3, (0xC8 | encode));
 5430 }
 5431 
 5432 #ifdef _LP64
 5433 void Assembler::rorq(Register dst) {
 5434   int encode = prefixq_and_encode(dst->encoding());
 5435   emit_int16((unsigned char)0xD3, (0xC8 | encode));
 5436 }
 5437 
 5438 void Assembler::rorq(Register dst, int imm8) {
 5439   assert(isShiftCount(imm8 >> 1), "illegal shift count");
 5440   int encode = prefixq_and_encode(dst->encoding());
 5441   if (imm8 == 1) {
 5442     emit_int16((unsigned char)0xD1, (0xC8 | encode));
 5443   } else {
 5444     emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
 5445   }
 5446 }
 5447 
 5448 void Assembler::rolq(Register dst) {
 5449   int encode = prefixq_and_encode(dst->encoding());
 5450   emit_int16((unsigned char)0xD3, (0xC0 | encode));
 5451 }
 5452 
 5453 void Assembler::rolq(Register dst, int imm8) {
 5454   assert(isShiftCount(imm8 >> 1), "illegal shift count");
 5455   int encode = prefixq_and_encode(dst->encoding());
 5456   if (imm8 == 1) {
 5457     emit_int16((unsigned char)0xD1, (0xC0 | encode));
 5458   } else {
 5459     emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
 5460   }
 5461 }
 5462 #endif
 5463 
 5464 void Assembler::sahf() {
 5465 #ifdef _LP64
 5466   // Not supported in 64bit mode
 5467   ShouldNotReachHere();
 5468 #endif
 5469   emit_int8((unsigned char)0x9E);
 5470 }
 5471 
 5472 void Assembler::sall(Address dst, int imm8) {
 5473   InstructionMark im(this);
 5474   assert(isShiftCount(imm8), "illegal shift count");
 5475   prefix(dst);
 5476   if (imm8 == 1) {
 5477     emit_int8((unsigned char)0xD1);
 5478     emit_operand(as_Register(4), dst);
 5479   }
 5480   else {
 5481     emit_int8((unsigned char)0xC1);
 5482     emit_operand(as_Register(4), dst);
 5483     emit_int8(imm8);
 5484   }
 5485 }
 5486 
 5487 void Assembler::sall(Address dst) {
 5488   InstructionMark im(this);
 5489   prefix(dst);
 5490   emit_int8((unsigned char)0xD3);
 5491   emit_operand(as_Register(4), dst);
 5492 }
 5493 
 5494 void Assembler::sall(Register dst, int imm8) {
 5495   assert(isShiftCount(imm8), "illegal shift count");
 5496   int encode = prefix_and_encode(dst->encoding());
 5497   if (imm8 == 1) {
 5498     emit_int16((unsigned char)0xD1, (0xE0 | encode));
 5499   } else {
 5500     emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
 5501   }
 5502 }
 5503 
 5504 void Assembler::sall(Register dst) {
 5505   int encode = prefix_and_encode(dst->encoding());
 5506   emit_int16((unsigned char)0xD3, (0xE0 | encode));
 5507 }
 5508 
 5509 void Assembler::sarl(Address dst, int imm8) {
 5510   assert(isShiftCount(imm8), "illegal shift count");
 5511   InstructionMark im(this);
 5512   prefix(dst);
 5513   if (imm8 == 1) {
 5514     emit_int8((unsigned char)0xD1);
 5515     emit_operand(as_Register(7), dst);
 5516   }
 5517   else {
 5518     emit_int8((unsigned char)0xC1);
 5519     emit_operand(as_Register(7), dst);
 5520     emit_int8(imm8);
 5521   }
 5522 }
 5523 
 5524 void Assembler::sarl(Address dst) {
 5525   InstructionMark im(this);
 5526   prefix(dst);
 5527   emit_int8((unsigned char)0xD3);
 5528   emit_operand(as_Register(7), dst);
 5529 }
 5530 
 5531 void Assembler::sarl(Register dst, int imm8) {
 5532   int encode = prefix_and_encode(dst->encoding());
 5533   assert(isShiftCount(imm8), "illegal shift count");
 5534   if (imm8 == 1) {
 5535     emit_int16((unsigned char)0xD1, (0xF8 | encode));
 5536   } else {
 5537     emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
 5538   }
 5539 }
 5540 
 5541 void Assembler::sarl(Register dst) {
 5542   int encode = prefix_and_encode(dst->encoding());
 5543   emit_int16((unsigned char)0xD3, (0xF8 | encode));
 5544 }
 5545 
 5546 void Assembler::sbbl(Address dst, int32_t imm32) {
 5547   InstructionMark im(this);
 5548   prefix(dst);
 5549   emit_arith_operand(0x81, rbx, dst, imm32);
 5550 }
 5551 
 5552 void Assembler::sbbl(Register dst, int32_t imm32) {
 5553   prefix(dst);
 5554   emit_arith(0x81, 0xD8, dst, imm32);
 5555 }
 5556 
 5557 
 5558 void Assembler::sbbl(Register dst, Address src) {
 5559   InstructionMark im(this);
 5560   prefix(src, dst);
 5561   emit_int8(0x1B);
 5562   emit_operand(dst, src);
 5563 }
 5564 
 5565 void Assembler::sbbl(Register dst, Register src) {
 5566   (void) prefix_and_encode(dst->encoding(), src->encoding());
 5567   emit_arith(0x1B, 0xC0, dst, src);
 5568 }
 5569 
 5570 void Assembler::setb(Condition cc, Register dst) {
 5571   assert(0 <= cc && cc < 16, "illegal cc");
 5572   int encode = prefix_and_encode(dst->encoding(), true);
 5573   emit_int24(0x0F, (unsigned char)0x90 | cc, (0xC0 | encode));
 5574 }
 5575 
 5576 void Assembler::sete(Register dst) {
 5577   int encode = prefix_and_encode(dst->encoding(), true);
 5578   emit_int24(0x0F, (unsigned char)0x94, (0xC0 | encode));
 5579 }
 5580 
 5581 void Assembler::setl(Register dst) {
 5582   int encode = prefix_and_encode(dst->encoding(), true);
 5583   emit_int24(0x0F, (unsigned char)0x9C, (0xC0 | encode));
 5584 }
 5585 
 5586 void Assembler::setne(Register dst) {
 5587   int encode = prefix_and_encode(dst->encoding(), true);
 5588   emit_int24(0x0F, (unsigned char)0x95, (0xC0 | encode));
 5589 }
 5590 
 5591 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
 5592   assert(VM_Version::supports_ssse3(), "");
 5593   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5594   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5595   emit_int24(0x0F, (0xC0 | encode), imm8);
 5596 }
 5597 
 5598 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
 5599   assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
 5600          vector_len == AVX_256bit? VM_Version::supports_avx2() :
 5601          0, "");
 5602   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 5603   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5604   emit_int24(0x0F, (0xC0 | encode), imm8);
 5605 }
 5606 
 5607 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 5608   assert(VM_Version::supports_evex(), "");
 5609   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 5610   attributes.set_is_evex_instruction();
 5611   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5612   emit_int24(0x3, (0xC0 | encode), imm8);
 5613 }
 5614 
 5615 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
 5616   assert(VM_Version::supports_sse4_1(), "");
 5617   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5618   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5619   emit_int24(0x0E, (0xC0 | encode), imm8);
 5620 }
 5621 
 5622 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
 5623   assert(VM_Version::supports_sha(), "");
 5624   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
 5625   emit_int24((unsigned char)0xCC, (0xC0 | encode), (unsigned char)imm8);
 5626 }
 5627 
 5628 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
 5629   assert(VM_Version::supports_sha(), "");
 5630   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5631   emit_int16((unsigned char)0xC8, (0xC0 | encode));
 5632 }
 5633 
 5634 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
 5635   assert(VM_Version::supports_sha(), "");
 5636   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5637   emit_int16((unsigned char)0xC9, (0xC0 | encode));
 5638 }
 5639 
 5640 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
 5641   assert(VM_Version::supports_sha(), "");
 5642   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5643   emit_int16((unsigned char)0xCA, (0xC0 | encode));
 5644 }
 5645 
 5646 // xmm0 is implicit additional source to this instruction.
 5647 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
 5648   assert(VM_Version::supports_sha(), "");
 5649   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5650   emit_int16((unsigned char)0xCB, (0xC0 | encode));
 5651 }
 5652 
 5653 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
 5654   assert(VM_Version::supports_sha(), "");
 5655   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5656   emit_int16((unsigned char)0xCC, (0xC0 | encode));
 5657 }
 5658 
 5659 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
 5660   assert(VM_Version::supports_sha(), "");
 5661   int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
 5662   emit_int16((unsigned char)0xCD, (0xC0 | encode));
 5663 }
 5664 
 5665 
 5666 void Assembler::shll(Register dst, int imm8) {
 5667   assert(isShiftCount(imm8), "illegal shift count");
 5668   int encode = prefix_and_encode(dst->encoding());
 5669   if (imm8 == 1 ) {
 5670     emit_int16((unsigned char)0xD1, (0xE0 | encode));
 5671   } else {
 5672     emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
 5673   }
 5674 }
 5675 
 5676 void Assembler::shll(Register dst) {
 5677   int encode = prefix_and_encode(dst->encoding());
 5678   emit_int16((unsigned char)0xD3, (0xE0 | encode));
 5679 }
 5680 
 5681 void Assembler::shrl(Register dst, int imm8) {
 5682   assert(isShiftCount(imm8), "illegal shift count");
 5683   int encode = prefix_and_encode(dst->encoding());
 5684   if (imm8 == 1) {
 5685     emit_int16((unsigned char)0xD1, (0xE8 | encode));
 5686   }
 5687   else {
 5688     emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
 5689   }
 5690 }
 5691 
 5692 void Assembler::shrl(Register dst) {
 5693   int encode = prefix_and_encode(dst->encoding());
 5694   emit_int16((unsigned char)0xD3, (0xE8 | encode));
 5695 }
 5696 
 5697 void Assembler::shrl(Address dst) {
 5698   InstructionMark im(this);
 5699   prefix(dst);
 5700   emit_int8((unsigned char)0xD3);
 5701   emit_operand(as_Register(5), dst);
 5702 }
 5703 
 5704 void Assembler::shrl(Address dst, int imm8) {
 5705   InstructionMark im(this);
 5706   assert(isShiftCount(imm8), "illegal shift count");
 5707   prefix(dst);
 5708   if (imm8 == 1) {
 5709     emit_int8((unsigned char)0xD1);
 5710     emit_operand(as_Register(5), dst);
 5711   }
 5712   else {
 5713     emit_int8((unsigned char)0xC1);
 5714     emit_operand(as_Register(5), dst);
 5715     emit_int8(imm8);
 5716   }
 5717 }
 5718 
 5719 
 5720 void Assembler::shldl(Register dst, Register src) {
 5721   int encode = prefix_and_encode(src->encoding(), dst->encoding());
 5722   emit_int24(0x0F, (unsigned char)0xA5, (0xC0 | encode));
 5723 }
 5724 
 5725 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
 5726   int encode = prefix_and_encode(src->encoding(), dst->encoding());
 5727   emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
 5728 }
 5729 
 5730 void Assembler::shrdl(Register dst, Register src) {
 5731   int encode = prefix_and_encode(src->encoding(), dst->encoding());
 5732   emit_int24(0x0F, (unsigned char)0xAD, (0xC0 | encode));
 5733 }
 5734 
 5735 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
 5736   int encode = prefix_and_encode(src->encoding(), dst->encoding());
 5737   emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
 5738 }
 5739 
 5740 // copies a single word from [esi] to [edi]
 5741 void Assembler::smovl() {
 5742   emit_int8((unsigned char)0xA5);
 5743 }
 5744 
 5745 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
 5746   assert(VM_Version::supports_sse4_1(), "");
 5747   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5748   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5749   emit_int24(0x0B, (0xC0 | encode), (unsigned char)rmode);
 5750 }
 5751 
 5752 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
 5753   assert(VM_Version::supports_sse4_1(), "");
 5754   InstructionMark im(this);
 5755   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5756   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 5757   emit_int8(0x0B);
 5758   emit_operand(dst, src);
 5759   emit_int8((unsigned char)rmode);
 5760 }
 5761 
 5762 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
 5763   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5764   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5765   attributes.set_rex_vex_w_reverted();
 5766   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5767   emit_int16(0x51, (0xC0 | encode));
 5768 }
 5769 
 5770 void Assembler::sqrtsd(XMMRegister dst, Address src) {
 5771   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5772   InstructionMark im(this);
 5773   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5774   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 5775   attributes.set_rex_vex_w_reverted();
 5776   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5777   emit_int8(0x51);
 5778   emit_operand(dst, src);
 5779 }
 5780 
 5781 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
 5782   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5783   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5784   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5785   emit_int16(0x51, (0xC0 | encode));
 5786 }
 5787 
 5788 void Assembler::std() {
 5789   emit_int8((unsigned char)0xFD);
 5790 }
 5791 
 5792 void Assembler::sqrtss(XMMRegister dst, Address src) {
 5793   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5794   InstructionMark im(this);
 5795   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5796   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 5797   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5798   emit_int8(0x51);
 5799   emit_operand(dst, src);
 5800 }
 5801 
 5802 void Assembler::stmxcsr( Address dst) {
 5803   if (UseAVX > 0 ) {
 5804     assert(VM_Version::supports_avx(), "");
 5805     InstructionMark im(this);
 5806     InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 5807     vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 5808     emit_int8((unsigned char)0xAE);
 5809     emit_operand(as_Register(3), dst);
 5810   } else {
 5811     NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5812     InstructionMark im(this);
 5813     prefix(dst);
 5814     emit_int16(0x0F, (unsigned char)0xAE);
 5815     emit_operand(as_Register(3), dst);
 5816   }
 5817 }
 5818 
 5819 void Assembler::subl(Address dst, int32_t imm32) {
 5820   InstructionMark im(this);
 5821   prefix(dst);
 5822   emit_arith_operand(0x81, rbp, dst, imm32);
 5823 }
 5824 
 5825 void Assembler::subl(Address dst, Register src) {
 5826   InstructionMark im(this);
 5827   prefix(dst, src);
 5828   emit_int8(0x29);
 5829   emit_operand(src, dst);
 5830 }
 5831 
 5832 void Assembler::subl(Register dst, int32_t imm32) {
 5833   prefix(dst);
 5834   emit_arith(0x81, 0xE8, dst, imm32);
 5835 }
 5836 
 5837 // Force generation of a 4 byte immediate value even if it fits into 8bit
 5838 void Assembler::subl_imm32(Register dst, int32_t imm32) {
 5839   prefix(dst);
 5840   emit_arith_imm32(0x81, 0xE8, dst, imm32);
 5841 }
 5842 
 5843 void Assembler::subl(Register dst, Address src) {
 5844   InstructionMark im(this);
 5845   prefix(src, dst);
 5846   emit_int8(0x2B);
 5847   emit_operand(dst, src);
 5848 }
 5849 
 5850 void Assembler::subl(Register dst, Register src) {
 5851   (void) prefix_and_encode(dst->encoding(), src->encoding());
 5852   emit_arith(0x2B, 0xC0, dst, src);
 5853 }
 5854 
 5855 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
 5856   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5857   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5858   attributes.set_rex_vex_w_reverted();
 5859   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5860   emit_int16(0x5C, (0xC0 | encode));
 5861 }
 5862 
 5863 void Assembler::subsd(XMMRegister dst, Address src) {
 5864   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5865   InstructionMark im(this);
 5866   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5867   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 5868   attributes.set_rex_vex_w_reverted();
 5869   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 5870   emit_int8(0x5C);
 5871   emit_operand(dst, src);
 5872 }
 5873 
 5874 void Assembler::subss(XMMRegister dst, XMMRegister src) {
 5875   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5876   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
 5877   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5878   emit_int16(0x5C, (0xC0 | encode));
 5879 }
 5880 
 5881 void Assembler::subss(XMMRegister dst, Address src) {
 5882   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 5883   InstructionMark im(this);
 5884   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5885   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 5886   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 5887   emit_int8(0x5C);
 5888   emit_operand(dst, src);
 5889 }
 5890 
 5891 void Assembler::testb(Register dst, int imm8) {
 5892   NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
 5893   if (dst == rax) {
 5894     emit_int8((unsigned char)0xA8);
 5895     emit_int8(imm8);
 5896   } else {
 5897     (void) prefix_and_encode(dst->encoding(), true);
 5898     emit_arith_b(0xF6, 0xC0, dst, imm8);
 5899   }
 5900 }
 5901 
 5902 void Assembler::testb(Address dst, int imm8) {
 5903   InstructionMark im(this);
 5904   prefix(dst);
 5905   emit_int8((unsigned char)0xF6);
 5906   emit_operand(rax, dst, 1);
 5907   emit_int8(imm8);
 5908 }
 5909 
 5910 void Assembler::testl(Address dst, int32_t imm32) {
 5911   if (imm32 >= 0 && is8bit(imm32)) {
 5912     testb(dst, imm32);
 5913     return;
 5914   }
 5915   InstructionMark im(this);
 5916   emit_int8((unsigned char)0xF7);
 5917   emit_operand(as_Register(0), dst);
 5918   emit_int32(imm32);
 5919 }
 5920 
 5921 void Assembler::testl(Register dst, int32_t imm32) {
 5922   if (imm32 >= 0 && is8bit(imm32) && dst->has_byte_register()) {
 5923     testb(dst, imm32);
 5924     return;
 5925   }
 5926   // not using emit_arith because test
 5927   // doesn't support sign-extension of
 5928   // 8bit operands
 5929   if (dst == rax) {
 5930     emit_int8((unsigned char)0xA9);
 5931     emit_int32(imm32);
 5932   } else {
 5933     int encode = dst->encoding();
 5934     encode = prefix_and_encode(encode);
 5935     emit_int16((unsigned char)0xF7, (0xC0 | encode));
 5936     emit_int32(imm32);
 5937   }
 5938 }
 5939 
 5940 void Assembler::testl(Register dst, Register src) {
 5941   (void) prefix_and_encode(dst->encoding(), src->encoding());
 5942   emit_arith(0x85, 0xC0, dst, src);
 5943 }
 5944 
 5945 void Assembler::testl(Register dst, Address src) {
 5946   InstructionMark im(this);
 5947   prefix(src, dst);
 5948   emit_int8((unsigned char)0x85);
 5949   emit_operand(dst, src);
 5950 }
 5951 
 5952 void Assembler::tzcntl(Register dst, Register src) {
 5953   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
 5954   emit_int8((unsigned char)0xF3);
 5955   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 5956   emit_int24(0x0F,
 5957              (unsigned char)0xBC,
 5958              0xC0 | encode);
 5959 }
 5960 
 5961 void Assembler::tzcntl(Register dst, Address src) {
 5962   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
 5963   InstructionMark im(this);
 5964   emit_int8((unsigned char)0xF3);
 5965   prefix(src, dst);
 5966   emit_int16(0x0F, (unsigned char)0xBC);
 5967   emit_operand(dst, src);
 5968 }
 5969 
 5970 void Assembler::tzcntq(Register dst, Register src) {
 5971   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
 5972   emit_int8((unsigned char)0xF3);
 5973   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
 5974   emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
 5975 }
 5976 
 5977 void Assembler::tzcntq(Register dst, Address src) {
 5978   assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
 5979   InstructionMark im(this);
 5980   emit_int8((unsigned char)0xF3);
 5981   prefixq(src, dst);
 5982   emit_int16(0x0F, (unsigned char)0xBC);
 5983   emit_operand(dst, src);
 5984 }
 5985 
 5986 void Assembler::ucomisd(XMMRegister dst, Address src) {
 5987   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5988   InstructionMark im(this);
 5989   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 5990   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 5991   attributes.set_rex_vex_w_reverted();
 5992   simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 5993   emit_int8(0x2E);
 5994   emit_operand(dst, src);
 5995 }
 5996 
 5997 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
 5998   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 5999   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6000   attributes.set_rex_vex_w_reverted();
 6001   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6002   emit_int16(0x2E, (0xC0 | encode));
 6003 }
 6004 
 6005 void Assembler::ucomiss(XMMRegister dst, Address src) {
 6006   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6007   InstructionMark im(this);
 6008   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6009   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 6010   simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6011   emit_int8(0x2E);
 6012   emit_operand(dst, src);
 6013 }
 6014 
 6015 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
 6016   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6017   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6018   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6019   emit_int16(0x2E, (0xC0 | encode));
 6020 }
 6021 
 6022 void Assembler::xabort(int8_t imm8) {
 6023   emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF));
 6024 }
 6025 
 6026 void Assembler::xaddb(Address dst, Register src) {
 6027   InstructionMark im(this);
 6028   prefix(dst, src, true);
 6029   emit_int16(0x0F, (unsigned char)0xC0);
 6030   emit_operand(src, dst);
 6031 }
 6032 
 6033 void Assembler::xaddw(Address dst, Register src) {
 6034   InstructionMark im(this);
 6035   emit_int8(0x66);
 6036   prefix(dst, src);
 6037   emit_int16(0x0F, (unsigned char)0xC1);
 6038   emit_operand(src, dst);
 6039 }
 6040 
 6041 void Assembler::xaddl(Address dst, Register src) {
 6042   InstructionMark im(this);
 6043   prefix(dst, src);
 6044   emit_int16(0x0F, (unsigned char)0xC1);
 6045   emit_operand(src, dst);
 6046 }
 6047 
 6048 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
 6049   InstructionMark im(this);
 6050   relocate(rtype);
 6051   if (abort.is_bound()) {
 6052     address entry = target(abort);
 6053     assert(entry != NULL, "abort entry NULL");
 6054     intptr_t offset = entry - pc();
 6055     emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
 6056     emit_int32(offset - 6); // 2 opcode + 4 address
 6057   } else {
 6058     abort.add_patch_at(code(), locator());
 6059     emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
 6060     emit_int32(0);
 6061   }
 6062 }
 6063 
 6064 void Assembler::xchgb(Register dst, Address src) { // xchg
 6065   InstructionMark im(this);
 6066   prefix(src, dst, true);
 6067   emit_int8((unsigned char)0x86);
 6068   emit_operand(dst, src);
 6069 }
 6070 
 6071 void Assembler::xchgw(Register dst, Address src) { // xchg
 6072   InstructionMark im(this);
 6073   emit_int8(0x66);
 6074   prefix(src, dst);
 6075   emit_int8((unsigned char)0x87);
 6076   emit_operand(dst, src);
 6077 }
 6078 
 6079 void Assembler::xchgl(Register dst, Address src) { // xchg
 6080   InstructionMark im(this);
 6081   prefix(src, dst);
 6082   emit_int8((unsigned char)0x87);
 6083   emit_operand(dst, src);
 6084 }
 6085 
 6086 void Assembler::xchgl(Register dst, Register src) {
 6087   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 6088   emit_int16((unsigned char)0x87, (0xC0 | encode));
 6089 }
 6090 
 6091 void Assembler::xend() {
 6092   emit_int24(0x0F, 0x01, (unsigned char)0xD5);
 6093 }
 6094 
 6095 void Assembler::xgetbv() {
 6096   emit_int24(0x0F, 0x01, (unsigned char)0xD0);
 6097 }
 6098 
 6099 void Assembler::xorl(Address dst, int32_t imm32) {
 6100   InstructionMark im(this);
 6101   prefix(dst);
 6102   emit_arith_operand(0x81, as_Register(6), dst, imm32);
 6103 }
 6104 
 6105 void Assembler::xorl(Register dst, int32_t imm32) {
 6106   prefix(dst);
 6107   emit_arith(0x81, 0xF0, dst, imm32);
 6108 }
 6109 
 6110 void Assembler::xorl(Register dst, Address src) {
 6111   InstructionMark im(this);
 6112   prefix(src, dst);
 6113   emit_int8(0x33);
 6114   emit_operand(dst, src);
 6115 }
 6116 
 6117 void Assembler::xorl(Register dst, Register src) {
 6118   (void) prefix_and_encode(dst->encoding(), src->encoding());
 6119   emit_arith(0x33, 0xC0, dst, src);
 6120 }
 6121 
 6122 void Assembler::xorl(Address dst, Register src) {
 6123   InstructionMark im(this);
 6124   prefix(dst, src);
 6125   emit_int8(0x31);
 6126   emit_operand(src, dst);
 6127 }
 6128 
 6129 void Assembler::xorb(Register dst, Address src) {
 6130   InstructionMark im(this);
 6131   prefix(src, dst);
 6132   emit_int8(0x32);
 6133   emit_operand(dst, src);
 6134 }
 6135 
 6136 void Assembler::xorb(Address dst, Register src) {
 6137   InstructionMark im(this);
 6138   prefix(dst, src, true);
 6139   emit_int8(0x30);
 6140   emit_operand(src, dst);
 6141 }
 6142 
 6143 void Assembler::xorw(Register dst, Register src) {
 6144   (void)prefix_and_encode(dst->encoding(), src->encoding());
 6145   emit_arith(0x33, 0xC0, dst, src);
 6146 }
 6147 
 6148 // AVX 3-operands scalar float-point arithmetic instructions
 6149 
 6150 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
 6151   assert(VM_Version::supports_avx(), "");
 6152   InstructionMark im(this);
 6153   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6154   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 6155   attributes.set_rex_vex_w_reverted();
 6156   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6157   emit_int8(0x58);
 6158   emit_operand(dst, src);
 6159 }
 6160 
 6161 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6162   assert(VM_Version::supports_avx(), "");
 6163   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6164   attributes.set_rex_vex_w_reverted();
 6165   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6166   emit_int16(0x58, (0xC0 | encode));
 6167 }
 6168 
 6169 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
 6170   assert(VM_Version::supports_avx(), "");
 6171   InstructionMark im(this);
 6172   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6173   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 6174   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6175   emit_int8(0x58);
 6176   emit_operand(dst, src);
 6177 }
 6178 
 6179 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6180   assert(VM_Version::supports_avx(), "");
 6181   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6182   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6183   emit_int16(0x58, (0xC0 | encode));
 6184 }
 6185 
 6186 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
 6187   assert(VM_Version::supports_avx(), "");
 6188   InstructionMark im(this);
 6189   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6190   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 6191   attributes.set_rex_vex_w_reverted();
 6192   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6193   emit_int8(0x5E);
 6194   emit_operand(dst, src);
 6195 }
 6196 
 6197 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6198   assert(VM_Version::supports_avx(), "");
 6199   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6200   attributes.set_rex_vex_w_reverted();
 6201   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6202   emit_int16(0x5E, (0xC0 | encode));
 6203 }
 6204 
 6205 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
 6206   assert(VM_Version::supports_avx(), "");
 6207   InstructionMark im(this);
 6208   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6209   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 6210   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6211   emit_int8(0x5E);
 6212   emit_operand(dst, src);
 6213 }
 6214 
 6215 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6216   assert(VM_Version::supports_avx(), "");
 6217   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6218   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6219   emit_int16(0x5E, (0xC0 | encode));
 6220 }
 6221 
 6222 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
 6223   assert(VM_Version::supports_fma(), "");
 6224   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6225   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6226   emit_int16((unsigned char)0xB9, (0xC0 | encode));
 6227 }
 6228 
 6229 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
 6230   assert(VM_Version::supports_fma(), "");
 6231   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6232   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6233   emit_int16((unsigned char)0xB9, (0xC0 | encode));
 6234 }
 6235 
 6236 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
 6237   assert(VM_Version::supports_avx(), "");
 6238   InstructionMark im(this);
 6239   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6240   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 6241   attributes.set_rex_vex_w_reverted();
 6242   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6243   emit_int8(0x59);
 6244   emit_operand(dst, src);
 6245 }
 6246 
 6247 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6248   assert(VM_Version::supports_avx(), "");
 6249   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6250   attributes.set_rex_vex_w_reverted();
 6251   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6252   emit_int16(0x59, (0xC0 | encode));
 6253 }
 6254 
 6255 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
 6256   assert(VM_Version::supports_avx(), "");
 6257   InstructionMark im(this);
 6258   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6259   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 6260   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6261   emit_int8(0x59);
 6262   emit_operand(dst, src);
 6263 }
 6264 
 6265 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6266   assert(VM_Version::supports_avx(), "");
 6267   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6268   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6269   emit_int16(0x59, (0xC0 | encode));
 6270 }
 6271 
 6272 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
 6273   assert(VM_Version::supports_avx(), "");
 6274   InstructionMark im(this);
 6275   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6276   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
 6277   attributes.set_rex_vex_w_reverted();
 6278   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6279   emit_int8(0x5C);
 6280   emit_operand(dst, src);
 6281 }
 6282 
 6283 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6284   assert(VM_Version::supports_avx(), "");
 6285   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6286   attributes.set_rex_vex_w_reverted();
 6287   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
 6288   emit_int16(0x5C, (0xC0 | encode));
 6289 }
 6290 
 6291 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
 6292   assert(VM_Version::supports_avx(), "");
 6293   InstructionMark im(this);
 6294   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6295   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 6296   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6297   emit_int8(0x5C);
 6298   emit_operand(dst, src);
 6299 }
 6300 
 6301 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
 6302   assert(VM_Version::supports_avx(), "");
 6303   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
 6304   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
 6305   emit_int16(0x5C, (0xC0 | encode));
 6306 }
 6307 
 6308 //====================VECTOR ARITHMETIC=====================================
 6309 
 6310 // Float-point vector arithmetic
 6311 
 6312 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
 6313   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6314   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6315   attributes.set_rex_vex_w_reverted();
 6316   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6317   emit_int16(0x58, (0xC0 | encode));
 6318 }
 6319 
 6320 void Assembler::addpd(XMMRegister dst, Address src) {
 6321   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6322   InstructionMark im(this);
 6323   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6324   attributes.set_rex_vex_w_reverted();
 6325   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6326   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6327   emit_int8(0x58);
 6328   emit_operand(dst, src);
 6329 }
 6330 
 6331 
 6332 void Assembler::addps(XMMRegister dst, XMMRegister src) {
 6333   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6334   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6335   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6336   emit_int16(0x58, (0xC0 | encode));
 6337 }
 6338 
 6339 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6340   assert(VM_Version::supports_avx(), "");
 6341   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6342   attributes.set_rex_vex_w_reverted();
 6343   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6344   emit_int16(0x58, (0xC0 | encode));
 6345 }
 6346 
 6347 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6348   assert(VM_Version::supports_avx(), "");
 6349   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6350   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6351   emit_int16(0x58, (0xC0 | encode));
 6352 }
 6353 
 6354 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6355   assert(VM_Version::supports_avx(), "");
 6356   InstructionMark im(this);
 6357   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6358   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6359   attributes.set_rex_vex_w_reverted();
 6360   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6361   emit_int8(0x58);
 6362   emit_operand(dst, src);
 6363 }
 6364 
 6365 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6366   assert(VM_Version::supports_avx(), "");
 6367   InstructionMark im(this);
 6368   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6369   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6370   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6371   emit_int8(0x58);
 6372   emit_operand(dst, src);
 6373 }
 6374 
 6375 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
 6376   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6377   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6378   attributes.set_rex_vex_w_reverted();
 6379   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6380   emit_int16(0x5C, (0xC0 | encode));
 6381 }
 6382 
 6383 void Assembler::subps(XMMRegister dst, XMMRegister src) {
 6384   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6385   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6386   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6387   emit_int16(0x5C, (0xC0 | encode));
 6388 }
 6389 
 6390 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6391   assert(VM_Version::supports_avx(), "");
 6392   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6393   attributes.set_rex_vex_w_reverted();
 6394   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6395   emit_int16(0x5C, (0xC0 | encode));
 6396 }
 6397 
 6398 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6399   assert(VM_Version::supports_avx(), "");
 6400   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6401   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6402   emit_int16(0x5C, (0xC0 | encode));
 6403 }
 6404 
 6405 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6406   assert(VM_Version::supports_avx(), "");
 6407   InstructionMark im(this);
 6408   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6409   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6410   attributes.set_rex_vex_w_reverted();
 6411   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6412   emit_int8(0x5C);
 6413   emit_operand(dst, src);
 6414 }
 6415 
 6416 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6417   assert(VM_Version::supports_avx(), "");
 6418   InstructionMark im(this);
 6419   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6420   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6421   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6422   emit_int8(0x5C);
 6423   emit_operand(dst, src);
 6424 }
 6425 
 6426 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
 6427   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6428   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6429   attributes.set_rex_vex_w_reverted();
 6430   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6431   emit_int16(0x59, (0xC0 | encode));
 6432 }
 6433 
 6434 void Assembler::mulpd(XMMRegister dst, Address src) {
 6435   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6436   InstructionMark im(this);
 6437   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6438   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6439   attributes.set_rex_vex_w_reverted();
 6440   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6441   emit_int8(0x59);
 6442   emit_operand(dst, src);
 6443 }
 6444 
 6445 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
 6446   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6447   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6448   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6449   emit_int16(0x59, (0xC0 | encode));
 6450 }
 6451 
 6452 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6453   assert(VM_Version::supports_avx(), "");
 6454   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6455   attributes.set_rex_vex_w_reverted();
 6456   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6457   emit_int16(0x59, (0xC0 | encode));
 6458 }
 6459 
 6460 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6461   assert(VM_Version::supports_avx(), "");
 6462   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6463   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6464   emit_int16(0x59, (0xC0 | encode));
 6465 }
 6466 
 6467 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6468   assert(VM_Version::supports_avx(), "");
 6469   InstructionMark im(this);
 6470   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6471   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6472   attributes.set_rex_vex_w_reverted();
 6473   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6474   emit_int8(0x59);
 6475   emit_operand(dst, src);
 6476 }
 6477 
 6478 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6479   assert(VM_Version::supports_avx(), "");
 6480   InstructionMark im(this);
 6481   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6482   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6483   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6484   emit_int8(0x59);
 6485   emit_operand(dst, src);
 6486 }
 6487 
 6488 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
 6489   assert(VM_Version::supports_fma(), "");
 6490   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6491   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6492   emit_int16((unsigned char)0xB8, (0xC0 | encode));
 6493 }
 6494 
 6495 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
 6496   assert(VM_Version::supports_fma(), "");
 6497   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6498   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6499   emit_int16((unsigned char)0xB8, (0xC0 | encode));
 6500 }
 6501 
 6502 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
 6503   assert(VM_Version::supports_fma(), "");
 6504   InstructionMark im(this);
 6505   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6506   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6507   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6508   emit_int8((unsigned char)0xB8);
 6509   emit_operand(dst, src2);
 6510 }
 6511 
 6512 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
 6513   assert(VM_Version::supports_fma(), "");
 6514   InstructionMark im(this);
 6515   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6516   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6517   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6518   emit_int8((unsigned char)0xB8);
 6519   emit_operand(dst, src2);
 6520 }
 6521 
 6522 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
 6523   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6524   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6525   attributes.set_rex_vex_w_reverted();
 6526   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6527   emit_int16(0x5E, (0xC0 | encode));
 6528 }
 6529 
 6530 void Assembler::divps(XMMRegister dst, XMMRegister src) {
 6531   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6532   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6533   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6534   emit_int16(0x5E, (0xC0 | encode));
 6535 }
 6536 
 6537 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6538   assert(VM_Version::supports_avx(), "");
 6539   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6540   attributes.set_rex_vex_w_reverted();
 6541   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6542   emit_int16(0x5E, (0xC0 | encode));
 6543 }
 6544 
 6545 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6546   assert(VM_Version::supports_avx(), "");
 6547   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6548   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6549   emit_int16(0x5E, (0xC0 | encode));
 6550 }
 6551 
 6552 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6553   assert(VM_Version::supports_avx(), "");
 6554   InstructionMark im(this);
 6555   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6556   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6557   attributes.set_rex_vex_w_reverted();
 6558   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6559   emit_int8(0x5E);
 6560   emit_operand(dst, src);
 6561 }
 6562 
 6563 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6564   assert(VM_Version::supports_avx(), "");
 6565   InstructionMark im(this);
 6566   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6567   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6568   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6569   emit_int8(0x5E);
 6570   emit_operand(dst, src);
 6571 }
 6572 
 6573 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
 6574   assert(VM_Version::supports_avx(), "");
 6575   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 6576   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 6577   emit_int24(0x09, (0xC0 | encode), (rmode));
 6578 }
 6579 
 6580 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode,  int vector_len) {
 6581   assert(VM_Version::supports_avx(), "");
 6582   InstructionMark im(this);
 6583   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
 6584   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 6585   emit_int8(0x09);
 6586   emit_operand(dst, src);
 6587   emit_int8((rmode));
 6588 }
 6589 
 6590 void Assembler::vrndscalepd(XMMRegister dst,  XMMRegister src,  int32_t rmode, int vector_len) {
 6591   assert(VM_Version::supports_evex(), "requires EVEX support");
 6592   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6593   attributes.set_is_evex_instruction();
 6594   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 6595   emit_int24(0x09, (0xC0 | encode), (rmode));
 6596 }
 6597 
 6598 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
 6599   assert(VM_Version::supports_evex(), "requires EVEX support");
 6600   assert(dst != xnoreg, "sanity");
 6601   InstructionMark im(this);
 6602   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6603   attributes.set_is_evex_instruction();
 6604   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6605   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 6606   emit_int8(0x09);
 6607   emit_operand(dst, src);
 6608   emit_int8((rmode));
 6609 }
 6610 
 6611 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
 6612   assert(VM_Version::supports_avx(), "");
 6613   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6614   attributes.set_rex_vex_w_reverted();
 6615   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6616   emit_int16(0x51, (0xC0 | encode));
 6617 }
 6618 
 6619 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
 6620   assert(VM_Version::supports_avx(), "");
 6621   InstructionMark im(this);
 6622   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6623   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6624   attributes.set_rex_vex_w_reverted();
 6625   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6626   emit_int8(0x51);
 6627   emit_operand(dst, src);
 6628 }
 6629 
 6630 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
 6631   assert(VM_Version::supports_avx(), "");
 6632   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6633   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6634   emit_int16(0x51, (0xC0 | encode));
 6635 }
 6636 
 6637 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
 6638   assert(VM_Version::supports_avx(), "");
 6639   InstructionMark im(this);
 6640   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6641   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6642   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6643   emit_int8(0x51);
 6644   emit_operand(dst, src);
 6645 }
 6646 
 6647 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
 6648   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6649   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6650   attributes.set_rex_vex_w_reverted();
 6651   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6652   emit_int16(0x54, (0xC0 | encode));
 6653 }
 6654 
 6655 void Assembler::andps(XMMRegister dst, XMMRegister src) {
 6656   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6657   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6658   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6659   emit_int16(0x54, (0xC0 | encode));
 6660 }
 6661 
 6662 void Assembler::andps(XMMRegister dst, Address src) {
 6663   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6664   InstructionMark im(this);
 6665   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6666   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6667   simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6668   emit_int8(0x54);
 6669   emit_operand(dst, src);
 6670 }
 6671 
 6672 void Assembler::andpd(XMMRegister dst, Address src) {
 6673   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6674   InstructionMark im(this);
 6675   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6676   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6677   attributes.set_rex_vex_w_reverted();
 6678   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6679   emit_int8(0x54);
 6680   emit_operand(dst, src);
 6681 }
 6682 
 6683 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6684   assert(VM_Version::supports_avx(), "");
 6685   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6686   attributes.set_rex_vex_w_reverted();
 6687   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6688   emit_int16(0x54, (0xC0 | encode));
 6689 }
 6690 
 6691 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6692   assert(VM_Version::supports_avx(), "");
 6693   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6694   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6695   emit_int16(0x54, (0xC0 | encode));
 6696 }
 6697 
 6698 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6699   assert(VM_Version::supports_avx(), "");
 6700   InstructionMark im(this);
 6701   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6702   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6703   attributes.set_rex_vex_w_reverted();
 6704   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6705   emit_int8(0x54);
 6706   emit_operand(dst, src);
 6707 }
 6708 
 6709 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6710   assert(VM_Version::supports_avx(), "");
 6711   InstructionMark im(this);
 6712   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6713   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6714   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6715   emit_int8(0x54);
 6716   emit_operand(dst, src);
 6717 }
 6718 
 6719 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
 6720   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6721   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6722   attributes.set_rex_vex_w_reverted();
 6723   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6724   emit_int8(0x15);
 6725   emit_int8((0xC0 | encode));
 6726 }
 6727 
 6728 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
 6729   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6730   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6731   attributes.set_rex_vex_w_reverted();
 6732   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6733   emit_int16(0x14, (0xC0 | encode));
 6734 }
 6735 
 6736 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
 6737   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6738   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6739   attributes.set_rex_vex_w_reverted();
 6740   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6741   emit_int16(0x57, (0xC0 | encode));
 6742 }
 6743 
 6744 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
 6745   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6746   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6747   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6748   emit_int16(0x57, (0xC0 | encode));
 6749 }
 6750 
 6751 void Assembler::xorpd(XMMRegister dst, Address src) {
 6752   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6753   InstructionMark im(this);
 6754   InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6755   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6756   attributes.set_rex_vex_w_reverted();
 6757   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6758   emit_int8(0x57);
 6759   emit_operand(dst, src);
 6760 }
 6761 
 6762 void Assembler::xorps(XMMRegister dst, Address src) {
 6763   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 6764   InstructionMark im(this);
 6765   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6766   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6767   simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6768   emit_int8(0x57);
 6769   emit_operand(dst, src);
 6770 }
 6771 
 6772 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6773   assert(VM_Version::supports_avx(), "");
 6774   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6775   attributes.set_rex_vex_w_reverted();
 6776   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6777   emit_int16(0x57, (0xC0 | encode));
 6778 }
 6779 
 6780 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6781   assert(VM_Version::supports_avx(), "");
 6782   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6783   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6784   emit_int16(0x57, (0xC0 | encode));
 6785 }
 6786 
 6787 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6788   assert(VM_Version::supports_avx(), "");
 6789   InstructionMark im(this);
 6790   InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6791   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6792   attributes.set_rex_vex_w_reverted();
 6793   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6794   emit_int8(0x57);
 6795   emit_operand(dst, src);
 6796 }
 6797 
 6798 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6799   assert(VM_Version::supports_avx(), "");
 6800   InstructionMark im(this);
 6801   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 6802   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6803   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 6804   emit_int8(0x57);
 6805   emit_operand(dst, src);
 6806 }
 6807 
 6808 // Integer vector arithmetic
 6809 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6810   assert(VM_Version::supports_avx() && (vector_len == 0) ||
 6811          VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
 6812   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 6813   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6814   emit_int16(0x01, (0xC0 | encode));
 6815 }
 6816 
 6817 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6818   assert(VM_Version::supports_avx() && (vector_len == 0) ||
 6819          VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
 6820   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 6821   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6822   emit_int16(0x02, (0xC0 | encode));
 6823 }
 6824 
 6825 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
 6826   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6827   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6828   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6829   emit_int16((unsigned char)0xFC, (0xC0 | encode));
 6830 }
 6831 
 6832 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
 6833   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6834   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6835   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6836   emit_int16((unsigned char)0xFD, (0xC0 | encode));
 6837 }
 6838 
 6839 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
 6840   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6841   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6842   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6843   emit_int16((unsigned char)0xFE, (0xC0 | encode));
 6844 }
 6845 
 6846 void Assembler::paddd(XMMRegister dst, Address src) {
 6847   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6848   InstructionMark im(this);
 6849   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6850   simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6851   emit_int8((unsigned char)0xFE);
 6852   emit_operand(dst, src);
 6853 }
 6854 
 6855 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
 6856   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6857   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6858   attributes.set_rex_vex_w_reverted();
 6859   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6860   emit_int16((unsigned char)0xD4, (0xC0 | encode));
 6861 }
 6862 
 6863 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
 6864   assert(VM_Version::supports_sse3(), "");
 6865   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 6866   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6867   emit_int16(0x01, (0xC0 | encode));
 6868 }
 6869 
 6870 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
 6871   assert(VM_Version::supports_sse3(), "");
 6872   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
 6873   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 6874   emit_int16(0x02, (0xC0 | encode));
 6875 }
 6876 
 6877 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6878   assert(UseAVX > 0, "requires some form of AVX");
 6879   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6880   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6881   emit_int16((unsigned char)0xFC, (0xC0 | encode));
 6882 }
 6883 
 6884 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6885   assert(UseAVX > 0, "requires some form of AVX");
 6886   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6887   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6888   emit_int16((unsigned char)0xFD, (0xC0 | encode));
 6889 }
 6890 
 6891 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6892   assert(UseAVX > 0, "requires some form of AVX");
 6893   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6894   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6895   emit_int16((unsigned char)0xFE, (0xC0 | encode));
 6896 }
 6897 
 6898 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6899   assert(UseAVX > 0, "requires some form of AVX");
 6900   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6901   attributes.set_rex_vex_w_reverted();
 6902   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6903   emit_int16((unsigned char)0xD4, (0xC0 | encode));
 6904 }
 6905 
 6906 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6907   assert(UseAVX > 0, "requires some form of AVX");
 6908   InstructionMark im(this);
 6909   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6910   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 6911   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6912   emit_int8((unsigned char)0xFC);
 6913   emit_operand(dst, src);
 6914 }
 6915 
 6916 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6917   assert(UseAVX > 0, "requires some form of AVX");
 6918   InstructionMark im(this);
 6919   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6920   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 6921   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6922   emit_int8((unsigned char)0xFD);
 6923   emit_operand(dst, src);
 6924 }
 6925 
 6926 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6927   assert(UseAVX > 0, "requires some form of AVX");
 6928   InstructionMark im(this);
 6929   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6930   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 6931   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6932   emit_int8((unsigned char)0xFE);
 6933   emit_operand(dst, src);
 6934 }
 6935 
 6936 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 6937   assert(UseAVX > 0, "requires some form of AVX");
 6938   InstructionMark im(this);
 6939   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6940   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 6941   attributes.set_rex_vex_w_reverted();
 6942   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6943   emit_int8((unsigned char)0xD4);
 6944   emit_operand(dst, src);
 6945 }
 6946 
 6947 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
 6948   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6949   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6950   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6951   emit_int16((unsigned char)0xF8, (0xC0 | encode));
 6952 }
 6953 
 6954 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
 6955   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6956   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6957   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6958   emit_int16((unsigned char)0xF9, (0xC0 | encode));
 6959 }
 6960 
 6961 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
 6962   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6963   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6964   emit_int16((unsigned char)0xFA, (0xC0 | encode));
 6965 }
 6966 
 6967 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
 6968   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 6969   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 6970   attributes.set_rex_vex_w_reverted();
 6971   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6972   emit_int8((unsigned char)0xFB);
 6973   emit_int8((0xC0 | encode));
 6974 }
 6975 
 6976 void Assembler::vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6977   assert(UseAVX > 0, "requires some form of AVX");
 6978   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6979   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6980   emit_int16((unsigned char)0xD8, (0xC0 | encode));
 6981 }
 6982 
 6983 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6984   assert(UseAVX > 0, "requires some form of AVX");
 6985   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6986   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6987   emit_int16((unsigned char)0xF8, (0xC0 | encode));
 6988 }
 6989 
 6990 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6991   assert(UseAVX > 0, "requires some form of AVX");
 6992   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 6993   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 6994   emit_int16((unsigned char)0xF9, (0xC0 | encode));
 6995 }
 6996 
 6997 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 6998   assert(UseAVX > 0, "requires some form of AVX");
 6999   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7000   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7001   emit_int16((unsigned char)0xFA, (0xC0 | encode));
 7002 }
 7003 
 7004 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7005   assert(UseAVX > 0, "requires some form of AVX");
 7006   InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7007   attributes.set_rex_vex_w_reverted();
 7008   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7009   emit_int16((unsigned char)0xFB, (0xC0 | encode));
 7010 }
 7011 
 7012 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7013   assert(UseAVX > 0, "requires some form of AVX");
 7014   InstructionMark im(this);
 7015   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7016   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 7017   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7018   emit_int8((unsigned char)0xF8);
 7019   emit_operand(dst, src);
 7020 }
 7021 
 7022 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7023   assert(UseAVX > 0, "requires some form of AVX");
 7024   InstructionMark im(this);
 7025   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7026   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 7027   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7028   emit_int8((unsigned char)0xF9);
 7029   emit_operand(dst, src);
 7030 }
 7031 
 7032 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7033   assert(UseAVX > 0, "requires some form of AVX");
 7034   InstructionMark im(this);
 7035   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7036   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 7037   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7038   emit_int8((unsigned char)0xFA);
 7039   emit_operand(dst, src);
 7040 }
 7041 
 7042 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7043   assert(UseAVX > 0, "requires some form of AVX");
 7044   InstructionMark im(this);
 7045   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7046   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 7047   attributes.set_rex_vex_w_reverted();
 7048   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7049   emit_int8((unsigned char)0xFB);
 7050   emit_operand(dst, src);
 7051 }
 7052 
 7053 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
 7054   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7055   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7056   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7057   emit_int16((unsigned char)0xD5, (0xC0 | encode));
 7058 }
 7059 
 7060 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
 7061   assert(VM_Version::supports_sse4_1(), "");
 7062   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7063   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7064   emit_int16(0x40, (0xC0 | encode));
 7065 }
 7066 
 7067 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
 7068   assert(VM_Version::supports_sse2(), "");
 7069   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7070   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7071   emit_int16((unsigned char)0xF4, (0xC0 | encode));
 7072 }
 7073 
 7074 void Assembler::vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7075   assert((vector_len == AVX_128bit && VM_Version::supports_avx()) ||
 7076          (vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
 7077          (vector_len == AVX_512bit && VM_Version::supports_avx512bw()), "");
 7078   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7079   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7080   emit_int16((unsigned char)0xE4, (0xC0 | encode));
 7081 }
 7082 
 7083 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7084   assert(UseAVX > 0, "requires some form of AVX");
 7085   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7086   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7087   emit_int16((unsigned char)0xD5, (0xC0 | encode));
 7088 }
 7089 
 7090 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7091   assert(UseAVX > 0, "requires some form of AVX");
 7092   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7093   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7094   emit_int16(0x40, (0xC0 | encode));
 7095 }
 7096 
 7097 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7098   assert(UseAVX > 2, "requires some form of EVEX");
 7099   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 7100   attributes.set_is_evex_instruction();
 7101   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7102   emit_int16(0x40, (0xC0 | encode));
 7103 }
 7104 
 7105 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7106   assert(UseAVX > 0, "requires some form of AVX");
 7107   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7108   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7109   emit_int16((unsigned char)0xF4, (0xC0 | encode));
 7110 }
 7111 
 7112 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7113   assert(UseAVX > 0, "requires some form of AVX");
 7114   InstructionMark im(this);
 7115   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7116   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
 7117   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7118   emit_int8((unsigned char)0xD5);
 7119   emit_operand(dst, src);
 7120 }
 7121 
 7122 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7123   assert(UseAVX > 0, "requires some form of AVX");
 7124   InstructionMark im(this);
 7125   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7126   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 7127   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7128   emit_int8(0x40);
 7129   emit_operand(dst, src);
 7130 }
 7131 
 7132 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7133   assert(UseAVX > 2, "requires some form of EVEX");
 7134   InstructionMark im(this);
 7135   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
 7136   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 7137   attributes.set_is_evex_instruction();
 7138   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7139   emit_int8(0x40);
 7140   emit_operand(dst, src);
 7141 }
 7142 
 7143 // Min, max
 7144 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
 7145   assert(VM_Version::supports_sse4_1(), "");
 7146   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7147   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7148   emit_int16(0x38, (0xC0 | encode));
 7149 }
 7150 
 7151 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7152   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7153         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
 7154   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7155   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7156   emit_int16(0x38, (0xC0 | encode));
 7157 }
 7158 
 7159 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
 7160   assert(VM_Version::supports_sse2(), "");
 7161   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7162   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7163   emit_int16((unsigned char)0xEA, (0xC0 | encode));
 7164 }
 7165 
 7166 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7167   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7168         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
 7169   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7170   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7171   emit_int16((unsigned char)0xEA, (0xC0 | encode));
 7172 }
 7173 
 7174 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
 7175   assert(VM_Version::supports_sse4_1(), "");
 7176   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7177   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7178   emit_int16(0x39, (0xC0 | encode));
 7179 }
 7180 
 7181 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7182   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7183         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
 7184   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7185   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7186   emit_int16(0x39, (0xC0 | encode));
 7187 }
 7188 
 7189 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7190   assert(UseAVX > 2, "requires AVX512F");
 7191   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7192   attributes.set_is_evex_instruction();
 7193   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7194   emit_int16(0x39, (0xC0 | encode));
 7195 }
 7196 
 7197 void Assembler::minps(XMMRegister dst, XMMRegister src) {
 7198   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 7199   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7200   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 7201   emit_int16(0x5D, (0xC0 | encode));
 7202 }
 7203 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7204   assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
 7205   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7206   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 7207   emit_int16(0x5D, (0xC0 | encode));
 7208 }
 7209 
 7210 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
 7211   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 7212   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7213   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7214   emit_int16(0x5D, (0xC0 | encode));
 7215 }
 7216 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7217   assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
 7218   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7219   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7220   emit_int16(0x5D, (0xC0 | encode));
 7221 }
 7222 
 7223 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
 7224   assert(VM_Version::supports_sse4_1(), "");
 7225   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7226   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7227   emit_int16(0x3C, (0xC0 | encode));
 7228 }
 7229 
 7230 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7231   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7232         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
 7233   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7234   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7235   emit_int16(0x3C, (0xC0 | encode));
 7236 }
 7237 
 7238 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
 7239   assert(VM_Version::supports_sse2(), "");
 7240   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7241   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7242   emit_int16((unsigned char)0xEE, (0xC0 | encode));
 7243 }
 7244 
 7245 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7246   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7247         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
 7248   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7249   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7250   emit_int16((unsigned char)0xEE, (0xC0 | encode));
 7251 }
 7252 
 7253 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
 7254   assert(VM_Version::supports_sse4_1(), "");
 7255   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7256   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7257   emit_int16(0x3D, (0xC0 | encode));
 7258 }
 7259 
 7260 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7261   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7262         (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
 7263   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7264   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7265   emit_int16(0x3D, (0xC0 | encode));
 7266 }
 7267 
 7268 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7269   assert(UseAVX > 2, "requires AVX512F");
 7270   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7271   attributes.set_is_evex_instruction();
 7272   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7273   emit_int16(0x3D, (0xC0 | encode));
 7274 }
 7275 
 7276 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
 7277   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 7278   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7279   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 7280   emit_int16(0x5F, (0xC0 | encode));
 7281 }
 7282 
 7283 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7284   assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
 7285   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7286   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 7287   emit_int16(0x5F, (0xC0 | encode));
 7288 }
 7289 
 7290 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
 7291   NOT_LP64(assert(VM_Version::supports_sse(), ""));
 7292   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7293   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7294   emit_int16(0x5F, (0xC0 | encode));
 7295 }
 7296 
 7297 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7298   assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
 7299   InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7300   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7301   emit_int16(0x5F, (0xC0 | encode));
 7302 }
 7303 
 7304 // Shift packed integers left by specified number of bits.
 7305 void Assembler::psllw(XMMRegister dst, int shift) {
 7306   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7307   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7308   // XMM6 is for /6 encoding: 66 0F 71 /6 ib
 7309   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7310   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7311 }
 7312 
 7313 void Assembler::pslld(XMMRegister dst, int shift) {
 7314   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7315   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7316   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
 7317   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7318   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7319 }
 7320 
 7321 void Assembler::psllq(XMMRegister dst, int shift) {
 7322   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7323   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7324   // XMM6 is for /6 encoding: 66 0F 73 /6 ib
 7325   int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7326   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 7327 }
 7328 
 7329 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
 7330   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7331   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7332   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7333   emit_int16((unsigned char)0xF1, (0xC0 | encode));
 7334 }
 7335 
 7336 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
 7337   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7338   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7339   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7340   emit_int16((unsigned char)0xF2, (0xC0 | encode));
 7341 }
 7342 
 7343 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
 7344   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7345   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7346   attributes.set_rex_vex_w_reverted();
 7347   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7348   emit_int16((unsigned char)0xF3, (0xC0 | encode));
 7349 }
 7350 
 7351 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7352   assert(UseAVX > 0, "requires some form of AVX");
 7353   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7354   // XMM6 is for /6 encoding: 66 0F 71 /6 ib
 7355   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7356   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7357 }
 7358 
 7359 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7360   assert(UseAVX > 0, "requires some form of AVX");
 7361   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7362   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7363   // XMM6 is for /6 encoding: 66 0F 72 /6 ib
 7364   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7365   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7366 }
 7367 
 7368 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7369   assert(UseAVX > 0, "requires some form of AVX");
 7370   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7371   attributes.set_rex_vex_w_reverted();
 7372   // XMM6 is for /6 encoding: 66 0F 73 /6 ib
 7373   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7374   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 7375 }
 7376 
 7377 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7378   assert(UseAVX > 0, "requires some form of AVX");
 7379   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7380   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7381   emit_int16((unsigned char)0xF1, (0xC0 | encode));
 7382 }
 7383 
 7384 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7385   assert(UseAVX > 0, "requires some form of AVX");
 7386   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7387   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7388   emit_int16((unsigned char)0xF2, (0xC0 | encode));
 7389 }
 7390 
 7391 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7392   assert(UseAVX > 0, "requires some form of AVX");
 7393   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7394   attributes.set_rex_vex_w_reverted();
 7395   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7396   emit_int16((unsigned char)0xF3, (0xC0 | encode));
 7397 }
 7398 
 7399 // Shift packed integers logically right by specified number of bits.
 7400 void Assembler::psrlw(XMMRegister dst, int shift) {
 7401   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7402   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7403   // XMM2 is for /2 encoding: 66 0F 71 /2 ib
 7404   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7405   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7406 }
 7407 
 7408 void Assembler::psrld(XMMRegister dst, int shift) {
 7409   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7410   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7411   // XMM2 is for /2 encoding: 66 0F 72 /2 ib
 7412   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7413   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7414 }
 7415 
 7416 void Assembler::psrlq(XMMRegister dst, int shift) {
 7417   // Do not confuse it with psrldq SSE2 instruction which
 7418   // shifts 128 bit value in xmm register by number of bytes.
 7419   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7420   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7421   attributes.set_rex_vex_w_reverted();
 7422   // XMM2 is for /2 encoding: 66 0F 73 /2 ib
 7423   int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7424   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 7425 }
 7426 
 7427 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
 7428   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7429   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7430   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7431   emit_int16((unsigned char)0xD1, (0xC0 | encode));
 7432 }
 7433 
 7434 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
 7435   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7436   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7437   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7438   emit_int16((unsigned char)0xD2, (0xC0 | encode));
 7439 }
 7440 
 7441 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
 7442   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7443   InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7444   attributes.set_rex_vex_w_reverted();
 7445   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7446   emit_int16((unsigned char)0xD3, (0xC0 | encode));
 7447 }
 7448 
 7449 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7450   assert(UseAVX > 0, "requires some form of AVX");
 7451   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7452   // XMM2 is for /2 encoding: 66 0F 71 /2 ib
 7453   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7454   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7455 }
 7456 
 7457 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7458   assert(UseAVX > 0, "requires some form of AVX");
 7459   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7460   // XMM2 is for /2 encoding: 66 0F 72 /2 ib
 7461   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7462   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7463 }
 7464 
 7465 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7466   assert(UseAVX > 0, "requires some form of AVX");
 7467   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7468   attributes.set_rex_vex_w_reverted();
 7469   // XMM2 is for /2 encoding: 66 0F 73 /2 ib
 7470   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7471   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 7472 }
 7473 
 7474 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7475   assert(UseAVX > 0, "requires some form of AVX");
 7476   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7477   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7478   emit_int16((unsigned char)0xD1, (0xC0 | encode));
 7479 }
 7480 
 7481 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7482   assert(UseAVX > 0, "requires some form of AVX");
 7483   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7484   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7485   emit_int16((unsigned char)0xD2, (0xC0 | encode));
 7486 }
 7487 
 7488 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7489   assert(UseAVX > 0, "requires some form of AVX");
 7490   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7491   attributes.set_rex_vex_w_reverted();
 7492   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7493   emit_int16((unsigned char)0xD3, (0xC0 | encode));
 7494 }
 7495 
 7496 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7497   assert(VM_Version::supports_avx512bw(), "");
 7498   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7499   attributes.set_is_evex_instruction();
 7500   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7501   emit_int16(0x10, (0xC0 | encode));
 7502 }
 7503 
 7504 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7505   assert(VM_Version::supports_avx512bw(), "");
 7506   InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7507   attributes.set_is_evex_instruction();
 7508   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7509   emit_int16(0x12, (0xC0 | encode));
 7510 }
 7511 
 7512 // Shift packed integers arithmetically right by specified number of bits.
 7513 void Assembler::psraw(XMMRegister dst, int shift) {
 7514   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7515   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7516   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
 7517   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7518   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7519 }
 7520 
 7521 void Assembler::psrad(XMMRegister dst, int shift) {
 7522   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7523   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7524   // XMM4 is for /4 encoding: 66 0F 72 /4 ib
 7525   int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7526   emit_int8(0x72);
 7527   emit_int8((0xC0 | encode));
 7528   emit_int8(shift & 0xFF);
 7529 }
 7530 
 7531 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
 7532   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7533   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7534   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7535   emit_int16((unsigned char)0xE1, (0xC0 | encode));
 7536 }
 7537 
 7538 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
 7539   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7540   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7541   int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7542   emit_int16((unsigned char)0xE2, (0xC0 | encode));
 7543 }
 7544 
 7545 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7546   assert(UseAVX > 0, "requires some form of AVX");
 7547   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7548   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
 7549   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7550   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 7551 }
 7552 
 7553 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7554   assert(UseAVX > 0, "requires some form of AVX");
 7555   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7556   // XMM4 is for /4 encoding: 66 0F 71 /4 ib
 7557   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7558   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7559 }
 7560 
 7561 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7562   assert(UseAVX > 0, "requires some form of AVX");
 7563   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 7564   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7565   emit_int16((unsigned char)0xE1, (0xC0 | encode));
 7566 }
 7567 
 7568 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7569   assert(UseAVX > 0, "requires some form of AVX");
 7570   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7571   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7572   emit_int16((unsigned char)0xE2, (0xC0 | encode));
 7573 }
 7574 
 7575 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7576   assert(UseAVX > 2, "requires AVX512");
 7577   assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
 7578   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7579   attributes.set_is_evex_instruction();
 7580   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7581   emit_int24((unsigned char)0x72, (0xC0 | encode), shift & 0xFF);
 7582 }
 7583 
 7584 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7585   assert(UseAVX > 2, "requires AVX512");
 7586   assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
 7587   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7588   attributes.set_is_evex_instruction();
 7589   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7590   emit_int16((unsigned char)0xE2, (0xC0 | encode));
 7591 }
 7592 
 7593 // logical operations packed integers
 7594 void Assembler::pand(XMMRegister dst, XMMRegister src) {
 7595   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7596   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7597   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7598   emit_int16((unsigned char)0xDB, (0xC0 | encode));
 7599 }
 7600 
 7601 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7602   assert(UseAVX > 0, "requires some form of AVX");
 7603   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7604   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7605   emit_int16((unsigned char)0xDB, (0xC0 | encode));
 7606 }
 7607 
 7608 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7609   assert(UseAVX > 0, "requires some form of AVX");
 7610   InstructionMark im(this);
 7611   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7612   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 7613   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7614   emit_int8((unsigned char)0xDB);
 7615   emit_operand(dst, src);
 7616 }
 7617 
 7618 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7619   assert(VM_Version::supports_evex(), "");
 7620   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7621   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7622   emit_int16((unsigned char)0xDB, (0xC0 | encode));
 7623 }
 7624 
 7625 //Variable Shift packed integers logically left.
 7626 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7627   assert(UseAVX > 1, "requires AVX2");
 7628   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7629   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7630   emit_int16(0x47, (0xC0 | encode));
 7631 }
 7632 
 7633 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7634   assert(UseAVX > 1, "requires AVX2");
 7635   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7636   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7637   emit_int16(0x47, (0xC0 | encode));
 7638 }
 7639 
 7640 //Variable Shift packed integers logically right.
 7641 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7642   assert(UseAVX > 1, "requires AVX2");
 7643   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7644   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7645   emit_int16(0x45, (0xC0 | encode));
 7646 }
 7647 
 7648 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7649   assert(UseAVX > 1, "requires AVX2");
 7650   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7651   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7652   emit_int16(0x45, (0xC0 | encode));
 7653 }
 7654 
 7655 //Variable right Shift arithmetic packed integers .
 7656 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7657   assert(UseAVX > 1, "requires AVX2");
 7658   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7659   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7660   emit_int16(0x46, (0xC0 | encode));
 7661 }
 7662 
 7663 void Assembler::evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7664   assert(VM_Version::supports_avx512bw(), "");
 7665   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7666   attributes.set_is_evex_instruction();
 7667   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7668   emit_int16(0x11, (0xC0 | encode));
 7669 }
 7670 
 7671 void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7672   assert(UseAVX > 2, "requires AVX512");
 7673   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
 7674   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7675   attributes.set_is_evex_instruction();
 7676   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7677   emit_int16(0x46, (0xC0 | encode));
 7678 }
 7679 
 7680 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7681   assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
 7682   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7683   attributes.set_is_evex_instruction();
 7684   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7685   emit_int16(0x71, (0xC0 | encode));
 7686 }
 7687 
 7688 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7689   assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
 7690   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7691   attributes.set_is_evex_instruction();
 7692   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7693   emit_int16(0x73, (0xC0 | encode));
 7694 }
 7695 
 7696 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
 7697   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7698   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7699   attributes.set_rex_vex_w_reverted();
 7700   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7701   emit_int16((unsigned char)0xDF, (0xC0 | encode));
 7702 }
 7703 
 7704 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7705   assert(UseAVX > 0, "requires some form of AVX");
 7706   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7707   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7708   emit_int16((unsigned char)0xDF, (0xC0 | encode));
 7709 }
 7710 
 7711 void Assembler::por(XMMRegister dst, XMMRegister src) {
 7712   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7713   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7714   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7715   emit_int16((unsigned char)0xEB, (0xC0 | encode));
 7716 }
 7717 
 7718 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7719   assert(UseAVX > 0, "requires some form of AVX");
 7720   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7721   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7722   emit_int16((unsigned char)0xEB, (0xC0 | encode));
 7723 }
 7724 
 7725 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7726   assert(UseAVX > 0, "requires some form of AVX");
 7727   InstructionMark im(this);
 7728   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7729   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 7730   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7731   emit_int8((unsigned char)0xEB);
 7732   emit_operand(dst, src);
 7733 }
 7734 
 7735 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7736   assert(VM_Version::supports_evex(), "");
 7737   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7738   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7739   emit_int16((unsigned char)0xEB, (0xC0 | encode));
 7740 }
 7741 
 7742 
 7743 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 7744   assert(VM_Version::supports_evex(), "");
 7745   // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
 7746   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7747   attributes.set_is_evex_instruction();
 7748   attributes.set_embedded_opmask_register_specifier(mask);
 7749   if (merge) {
 7750     attributes.reset_is_clear_context();
 7751   }
 7752   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7753   emit_int16((unsigned char)0xEB, (0xC0 | encode));
 7754 }
 7755 
 7756 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7757   assert(VM_Version::supports_evex(), "");
 7758   // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
 7759   InstructionMark im(this);
 7760   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7761   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
 7762   attributes.set_is_evex_instruction();
 7763   attributes.set_embedded_opmask_register_specifier(mask);
 7764   if (merge) {
 7765     attributes.reset_is_clear_context();
 7766   }
 7767   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7768   emit_int8((unsigned char)0xEB);
 7769   emit_operand(dst, src);
 7770 }
 7771 
 7772 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
 7773   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
 7774   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7775   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7776   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7777 }
 7778 
 7779 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7780   assert(UseAVX > 0, "requires some form of AVX");
 7781   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7782          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 7783          vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
 7784   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7785   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7786   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7787 }
 7788 
 7789 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7790   assert(UseAVX > 0, "requires some form of AVX");
 7791   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
 7792          vector_len == AVX_256bit ? VM_Version::supports_avx2() :
 7793          vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
 7794   InstructionMark im(this);
 7795   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7796   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
 7797   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7798   emit_int8((unsigned char)0xEF);
 7799   emit_operand(dst, src);
 7800 }
 7801 
 7802 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7803   assert(UseAVX > 2, "requires some form of EVEX");
 7804   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7805   attributes.set_rex_vex_w_reverted();
 7806   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7807   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7808 }
 7809 
 7810 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 7811   // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
 7812   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7813   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7814   attributes.set_is_evex_instruction();
 7815   attributes.set_embedded_opmask_register_specifier(mask);
 7816   if (merge) {
 7817     attributes.reset_is_clear_context();
 7818   }
 7819   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7820   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7821 }
 7822 
 7823 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7824   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7825   InstructionMark im(this);
 7826   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7827   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 7828   attributes.set_is_evex_instruction();
 7829   attributes.set_embedded_opmask_register_specifier(mask);
 7830   if (merge) {
 7831     attributes.reset_is_clear_context();
 7832   }
 7833   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7834   emit_int8((unsigned char)0xEF);
 7835   emit_operand(dst, src);
 7836 }
 7837 
 7838 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 7839   // Encoding: EVEX.NDS.XXX.66.0F.W1 EF /r
 7840   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7841   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7842   attributes.set_is_evex_instruction();
 7843   attributes.set_embedded_opmask_register_specifier(mask);
 7844   if (merge) {
 7845     attributes.reset_is_clear_context();
 7846   }
 7847   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7848   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7849 }
 7850 
 7851 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7852   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7853   InstructionMark im(this);
 7854   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7855   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 7856   attributes.set_is_evex_instruction();
 7857   attributes.set_embedded_opmask_register_specifier(mask);
 7858   if (merge) {
 7859     attributes.reset_is_clear_context();
 7860   }
 7861   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7862   emit_int8((unsigned char)0xEF);
 7863   emit_operand(dst, src);
 7864 }
 7865 
 7866 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7867   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7868   InstructionMark im(this);
 7869   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7870   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 7871   attributes.set_is_evex_instruction();
 7872   attributes.set_embedded_opmask_register_specifier(mask);
 7873   if (merge) {
 7874     attributes.reset_is_clear_context();
 7875   }
 7876   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7877   emit_int8((unsigned char)0xDB);
 7878   emit_operand(dst, src);
 7879 }
 7880 
 7881 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 7882   assert(VM_Version::supports_evex(), "");
 7883   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7884   attributes.set_is_evex_instruction();
 7885   attributes.set_embedded_opmask_register_specifier(mask);
 7886   if (merge) {
 7887     attributes.reset_is_clear_context();
 7888   }
 7889   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7890   emit_int16((unsigned char)0xDB, (0xC0 | encode));
 7891 }
 7892 
 7893 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7894   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7895   InstructionMark im(this);
 7896   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7897   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 7898   attributes.set_is_evex_instruction();
 7899   attributes.set_embedded_opmask_register_specifier(mask);
 7900   if (merge) {
 7901     attributes.reset_is_clear_context();
 7902   }
 7903   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7904   emit_int8((unsigned char)0xDB);
 7905   emit_operand(dst, src);
 7906 }
 7907 
 7908 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 7909   assert(VM_Version::supports_evex(), "");
 7910   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 7911   attributes.set_is_evex_instruction();
 7912   attributes.set_embedded_opmask_register_specifier(mask);
 7913   if (merge) {
 7914     attributes.reset_is_clear_context();
 7915   }
 7916   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7917   emit_int16((unsigned char)0xEB, (0xC0 | encode));
 7918 }
 7919 
 7920 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 7921   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 7922   InstructionMark im(this);
 7923   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7924   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 7925   attributes.set_is_evex_instruction();
 7926   attributes.set_embedded_opmask_register_specifier(mask);
 7927   if (merge) {
 7928     attributes.reset_is_clear_context();
 7929   }
 7930   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7931   emit_int8((unsigned char)0xEB);
 7932   emit_operand(dst, src);
 7933 }
 7934 
 7935 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 7936   assert(VM_Version::supports_evex(), "requires EVEX support");
 7937   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7938   attributes.set_is_evex_instruction();
 7939   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7940   emit_int16((unsigned char)0xEF, (0xC0 | encode));
 7941 }
 7942 
 7943 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
 7944   assert(VM_Version::supports_evex(), "requires EVEX support");
 7945   assert(dst != xnoreg, "sanity");
 7946   InstructionMark im(this);
 7947   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7948   attributes.set_is_evex_instruction();
 7949   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 7950   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7951   emit_int8((unsigned char)0xEF);
 7952   emit_operand(dst, src);
 7953 }
 7954 
 7955 void Assembler::evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7956   assert(VM_Version::supports_evex(), "requires EVEX support");
 7957   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7958   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7959   attributes.set_is_evex_instruction();
 7960   int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7961   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7962 }
 7963 
 7964 void Assembler::evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7965   assert(VM_Version::supports_evex(), "requires EVEX support");
 7966   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7967   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7968   attributes.set_is_evex_instruction();
 7969   int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7970   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7971 }
 7972 
 7973 // Register is a class, but it would be assigned numerical value.
 7974 // "0" is assigned for xmm0. Thus we need to ignore -Wnonnull.
 7975 PRAGMA_DIAG_PUSH
 7976 PRAGMA_NONNULL_IGNORED
 7977 void Assembler::evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7978   assert(VM_Version::supports_evex(), "requires EVEX support");
 7979   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7980   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7981   attributes.set_is_evex_instruction();
 7982   int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7983   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7984 }
 7985 
 7986 void Assembler::evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
 7987   assert(VM_Version::supports_evex(), "requires EVEX support");
 7988   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7989   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7990   attributes.set_is_evex_instruction();
 7991   int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 7992   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 7993 }
 7994 PRAGMA_DIAG_POP
 7995 
 7996 void Assembler::evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7997   assert(VM_Version::supports_evex(), "requires EVEX support");
 7998   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7999   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8000   attributes.set_is_evex_instruction();
 8001   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8002   emit_int16(0x15, (unsigned char)(0xC0 | encode));
 8003 }
 8004 
 8005 void Assembler::evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 8006   assert(VM_Version::supports_evex(), "requires EVEX support");
 8007   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8008   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8009   attributes.set_is_evex_instruction();
 8010   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8011   emit_int16(0x15, (unsigned char)(0xC0 | encode));
 8012 }
 8013 
 8014 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 8015   assert(VM_Version::supports_evex(), "requires EVEX support");
 8016   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8017   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8018   attributes.set_is_evex_instruction();
 8019   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8020   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 8021 }
 8022 
 8023 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 8024   assert(VM_Version::supports_evex(), "requires EVEX support");
 8025   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8026   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8027   attributes.set_is_evex_instruction();
 8028   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8029   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 8030 }
 8031 
 8032 void Assembler::evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8033   assert(VM_Version::supports_avx512cd(), "");
 8034   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8035   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8036   attributes.set_is_evex_instruction();
 8037   attributes.set_embedded_opmask_register_specifier(mask);
 8038   if (merge) {
 8039     attributes.reset_is_clear_context();
 8040   }
 8041   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8042   emit_int16(0x44, (0xC0 | encode));
 8043 }
 8044 
 8045 void Assembler::evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8046   assert(VM_Version::supports_avx512cd(), "");
 8047   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8048   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8049   attributes.set_is_evex_instruction();
 8050   attributes.set_embedded_opmask_register_specifier(mask);
 8051   if (merge) {
 8052     attributes.reset_is_clear_context();
 8053   }
 8054   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8055   emit_int16(0x44, (0xC0 | encode));
 8056 }
 8057 
 8058 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 8059   assert(VM_Version::supports_evex(), "requires EVEX support");
 8060   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8061   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8062   attributes.set_is_evex_instruction();
 8063   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8064   emit_int8(0x25);
 8065   emit_int8((unsigned char)(0xC0 | encode));
 8066   emit_int8(imm8);
 8067 }
 8068 
 8069 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
 8070   assert(VM_Version::supports_evex(), "requires EVEX support");
 8071   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8072   assert(dst != xnoreg, "sanity");
 8073   InstructionMark im(this);
 8074   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8075   attributes.set_is_evex_instruction();
 8076   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 8077   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8078   emit_int8(0x25);
 8079   emit_operand(dst, src3);
 8080   emit_int8(imm8);
 8081 }
 8082 
 8083 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 8084   assert(VM_Version::supports_evex(), "requires EVEX support");
 8085   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8086   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8087   attributes.set_is_evex_instruction();
 8088   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8089   emit_int8(0x25);
 8090   emit_int8((unsigned char)(0xC0 | encode));
 8091   emit_int8(imm8);
 8092 }
 8093 
 8094 void Assembler::evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8095   assert(VM_Version::supports_evex(), "");
 8096   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8097   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8098   attributes.set_is_evex_instruction();
 8099   attributes.set_embedded_opmask_register_specifier(mask);
 8100   if (merge) {
 8101     attributes.reset_is_clear_context();
 8102   }
 8103   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8104   emit_int16((unsigned char)0x88, (0xC0 | encode));
 8105 }
 8106 
 8107 void Assembler::evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8108   assert(VM_Version::supports_evex(), "");
 8109   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8110   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8111   attributes.set_is_evex_instruction();
 8112   attributes.set_embedded_opmask_register_specifier(mask);
 8113   if (merge) {
 8114     attributes.reset_is_clear_context();
 8115   }
 8116   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8117   emit_int16((unsigned char)0x88, (0xC0 | encode));
 8118 }
 8119 
 8120 void Assembler::evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8121   assert(VM_Version::supports_avx512_vbmi2(), "");
 8122   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8123   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8124   attributes.set_is_evex_instruction();
 8125   attributes.set_embedded_opmask_register_specifier(mask);
 8126   if (merge) {
 8127     attributes.reset_is_clear_context();
 8128   }
 8129   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8130   emit_int16(0x62, (0xC0 | encode));
 8131 }
 8132 
 8133 void Assembler::evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8134   assert(VM_Version::supports_avx512_vbmi2(), "");
 8135   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8136   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8137   attributes.set_is_evex_instruction();
 8138   attributes.set_embedded_opmask_register_specifier(mask);
 8139   if (merge) {
 8140     attributes.reset_is_clear_context();
 8141   }
 8142   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8143   emit_int16(0x62, (0xC0 | encode));
 8144 }
 8145 
 8146 void Assembler::evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8147   assert(VM_Version::supports_evex(), "");
 8148   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8149   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8150   attributes.set_is_evex_instruction();
 8151   attributes.set_embedded_opmask_register_specifier(mask);
 8152   if (merge) {
 8153     attributes.reset_is_clear_context();
 8154   }
 8155   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8156   emit_int16((unsigned char)0x89, (0xC0 | encode));
 8157 }
 8158 
 8159 void Assembler::evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8160   assert(VM_Version::supports_evex(), "");
 8161   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8162   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8163   attributes.set_is_evex_instruction();
 8164   attributes.set_embedded_opmask_register_specifier(mask);
 8165   if (merge) {
 8166     attributes.reset_is_clear_context();
 8167   }
 8168   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8169   emit_int16((unsigned char)0x89, (0xC0 | encode));
 8170 }
 8171 
 8172 // vinserti forms
 8173 
 8174 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8175   assert(VM_Version::supports_avx2(), "");
 8176   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8177   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8178   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8179   // last byte:
 8180   // 0x00 - insert into lower 128 bits
 8181   // 0x01 - insert into upper 128 bits
 8182   emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
 8183 }
 8184 
 8185 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8186   assert(VM_Version::supports_avx2(), "");
 8187   assert(dst != xnoreg, "sanity");
 8188   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8189   InstructionMark im(this);
 8190   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8191   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8192   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8193   emit_int8(0x38);
 8194   emit_operand(dst, src);
 8195   // 0x00 - insert into lower 128 bits
 8196   // 0x01 - insert into upper 128 bits
 8197   emit_int8(imm8 & 0x01);
 8198 }
 8199 
 8200 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8201   assert(VM_Version::supports_evex(), "");
 8202   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8203   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8204   attributes.set_is_evex_instruction();
 8205   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8206   // imm8:
 8207   // 0x00 - insert into q0 128 bits (0..127)
 8208   // 0x01 - insert into q1 128 bits (128..255)
 8209   // 0x02 - insert into q2 128 bits (256..383)
 8210   // 0x03 - insert into q3 128 bits (384..511)
 8211   emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
 8212 }
 8213 
 8214 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8215   assert(VM_Version::supports_evex(), "");
 8216   assert(dst != xnoreg, "sanity");
 8217   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8218   InstructionMark im(this);
 8219   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8220   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8221   attributes.set_is_evex_instruction();
 8222   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8223   emit_int8(0x18);
 8224   emit_operand(dst, src);
 8225   // 0x00 - insert into q0 128 bits (0..127)
 8226   // 0x01 - insert into q1 128 bits (128..255)
 8227   // 0x02 - insert into q2 128 bits (256..383)
 8228   // 0x03 - insert into q3 128 bits (384..511)
 8229   emit_int8(imm8 & 0x03);
 8230 }
 8231 
 8232 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8233   assert(VM_Version::supports_evex(), "");
 8234   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8235   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8236   attributes.set_is_evex_instruction();
 8237   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8238   //imm8:
 8239   // 0x00 - insert into lower 256 bits
 8240   // 0x01 - insert into upper 256 bits
 8241   emit_int24(0x3A, (0xC0 | encode), imm8 & 0x01);
 8242 }
 8243 
 8244 
 8245 // vinsertf forms
 8246 
 8247 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8248   assert(VM_Version::supports_avx(), "");
 8249   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8250   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8251   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8252   // imm8:
 8253   // 0x00 - insert into lower 128 bits
 8254   // 0x01 - insert into upper 128 bits
 8255   emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
 8256 }
 8257 
 8258 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8259   assert(VM_Version::supports_avx(), "");
 8260   assert(dst != xnoreg, "sanity");
 8261   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8262   InstructionMark im(this);
 8263   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8264   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8265   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8266   emit_int8(0x18);
 8267   emit_operand(dst, src);
 8268   // 0x00 - insert into lower 128 bits
 8269   // 0x01 - insert into upper 128 bits
 8270   emit_int8(imm8 & 0x01);
 8271 }
 8272 
 8273 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8274   assert(VM_Version::supports_evex(), "");
 8275   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8276   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8277   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8278   // imm8:
 8279   // 0x00 - insert into q0 128 bits (0..127)
 8280   // 0x01 - insert into q1 128 bits (128..255)
 8281   // 0x02 - insert into q0 128 bits (256..383)
 8282   // 0x03 - insert into q1 128 bits (384..512)
 8283   emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
 8284 }
 8285 
 8286 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8287   assert(VM_Version::supports_evex(), "");
 8288   assert(dst != xnoreg, "sanity");
 8289   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8290   InstructionMark im(this);
 8291   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8292   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8293   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8294   emit_int8(0x18);
 8295   emit_operand(dst, src);
 8296   // 0x00 - insert into q0 128 bits (0..127)
 8297   // 0x01 - insert into q1 128 bits (128..255)
 8298   // 0x02 - insert into q0 128 bits (256..383)
 8299   // 0x03 - insert into q1 128 bits (384..512)
 8300   emit_int8(imm8 & 0x03);
 8301 }
 8302 
 8303 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8304   assert(VM_Version::supports_evex(), "");
 8305   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8306   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8307   attributes.set_is_evex_instruction();
 8308   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8309   // imm8:
 8310   // 0x00 - insert into lower 256 bits
 8311   // 0x01 - insert into upper 256 bits
 8312   emit_int24(0x1A, (0xC0 | encode), imm8 & 0x01);
 8313 }
 8314 
 8315 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8316   assert(VM_Version::supports_evex(), "");
 8317   assert(dst != xnoreg, "sanity");
 8318   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8319   InstructionMark im(this);
 8320   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8321   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
 8322   attributes.set_is_evex_instruction();
 8323   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8324   emit_int8(0x1A);
 8325   emit_operand(dst, src);
 8326   // 0x00 - insert into lower 256 bits
 8327   // 0x01 - insert into upper 256 bits
 8328   emit_int8(imm8 & 0x01);
 8329 }
 8330 
 8331 
 8332 // vextracti forms
 8333 
 8334 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8335   assert(VM_Version::supports_avx2(), "");
 8336   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8337   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8338   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8339   // imm8:
 8340   // 0x00 - extract from lower 128 bits
 8341   // 0x01 - extract from upper 128 bits
 8342   emit_int24(0x39, (0xC0 | encode), imm8 & 0x01);
 8343 }
 8344 
 8345 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
 8346   assert(VM_Version::supports_avx2(), "");
 8347   assert(src != xnoreg, "sanity");
 8348   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8349   InstructionMark im(this);
 8350   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8351   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8352   attributes.reset_is_clear_context();
 8353   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8354   emit_int8(0x39);
 8355   emit_operand(src, dst);
 8356   // 0x00 - extract from lower 128 bits
 8357   // 0x01 - extract from upper 128 bits
 8358   emit_int8(imm8 & 0x01);
 8359 }
 8360 
 8361 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8362   assert(VM_Version::supports_evex(), "");
 8363   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8364   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8365   attributes.set_is_evex_instruction();
 8366   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8367   // imm8:
 8368   // 0x00 - extract from bits 127:0
 8369   // 0x01 - extract from bits 255:128
 8370   // 0x02 - extract from bits 383:256
 8371   // 0x03 - extract from bits 511:384
 8372   emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
 8373 }
 8374 
 8375 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
 8376   assert(VM_Version::supports_evex(), "");
 8377   assert(src != xnoreg, "sanity");
 8378   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8379   InstructionMark im(this);
 8380   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8381   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8382   attributes.reset_is_clear_context();
 8383   attributes.set_is_evex_instruction();
 8384   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8385   emit_int8(0x39);
 8386   emit_operand(src, dst);
 8387   // 0x00 - extract from bits 127:0
 8388   // 0x01 - extract from bits 255:128
 8389   // 0x02 - extract from bits 383:256
 8390   // 0x03 - extract from bits 511:384
 8391   emit_int8(imm8 & 0x03);
 8392 }
 8393 
 8394 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8395   assert(VM_Version::supports_avx512dq(), "");
 8396   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8397   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8398   attributes.set_is_evex_instruction();
 8399   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8400   // imm8:
 8401   // 0x00 - extract from bits 127:0
 8402   // 0x01 - extract from bits 255:128
 8403   // 0x02 - extract from bits 383:256
 8404   // 0x03 - extract from bits 511:384
 8405   emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
 8406 }
 8407 
 8408 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8409   assert(VM_Version::supports_evex(), "");
 8410   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8411   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8412   attributes.set_is_evex_instruction();
 8413   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8414   // imm8:
 8415   // 0x00 - extract from lower 256 bits
 8416   // 0x01 - extract from upper 256 bits
 8417   emit_int24(0x3B, (0xC0 | encode), imm8 & 0x01);
 8418 }
 8419 
 8420 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
 8421   assert(VM_Version::supports_evex(), "");
 8422   assert(src != xnoreg, "sanity");
 8423   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8424   InstructionMark im(this);
 8425   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8426   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
 8427   attributes.reset_is_clear_context();
 8428   attributes.set_is_evex_instruction();
 8429   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8430   emit_int8(0x38);
 8431   emit_operand(src, dst);
 8432   // 0x00 - extract from lower 256 bits
 8433   // 0x01 - extract from upper 256 bits
 8434   emit_int8(imm8 & 0x01);
 8435 }
 8436 // vextractf forms
 8437 
 8438 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8439   assert(VM_Version::supports_avx(), "");
 8440   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8441   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8442   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8443   // imm8:
 8444   // 0x00 - extract from lower 128 bits
 8445   // 0x01 - extract from upper 128 bits
 8446   emit_int24(0x19, (0xC0 | encode), imm8 & 0x01);
 8447 }
 8448 
 8449 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
 8450   assert(VM_Version::supports_avx(), "");
 8451   assert(src != xnoreg, "sanity");
 8452   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8453   InstructionMark im(this);
 8454   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8455   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8456   attributes.reset_is_clear_context();
 8457   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8458   emit_int8(0x19);
 8459   emit_operand(src, dst);
 8460   // 0x00 - extract from lower 128 bits
 8461   // 0x01 - extract from upper 128 bits
 8462   emit_int8(imm8 & 0x01);
 8463 }
 8464 
 8465 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8466   assert(VM_Version::supports_evex(), "");
 8467   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8468   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8469   attributes.set_is_evex_instruction();
 8470   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8471   // imm8:
 8472   // 0x00 - extract from bits 127:0
 8473   // 0x01 - extract from bits 255:128
 8474   // 0x02 - extract from bits 383:256
 8475   // 0x03 - extract from bits 511:384
 8476   emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
 8477 }
 8478 
 8479 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
 8480   assert(VM_Version::supports_evex(), "");
 8481   assert(src != xnoreg, "sanity");
 8482   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8483   InstructionMark im(this);
 8484   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8485   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8486   attributes.reset_is_clear_context();
 8487   attributes.set_is_evex_instruction();
 8488   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8489   emit_int8(0x19);
 8490   emit_operand(src, dst);
 8491   // 0x00 - extract from bits 127:0
 8492   // 0x01 - extract from bits 255:128
 8493   // 0x02 - extract from bits 383:256
 8494   // 0x03 - extract from bits 511:384
 8495   emit_int8(imm8 & 0x03);
 8496 }
 8497 
 8498 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8499   assert(VM_Version::supports_avx512dq(), "");
 8500   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8501   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8502   attributes.set_is_evex_instruction();
 8503   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8504   // imm8:
 8505   // 0x00 - extract from bits 127:0
 8506   // 0x01 - extract from bits 255:128
 8507   // 0x02 - extract from bits 383:256
 8508   // 0x03 - extract from bits 511:384
 8509   emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
 8510 }
 8511 
 8512 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
 8513   assert(VM_Version::supports_evex(), "");
 8514   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8515   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8516   attributes.set_is_evex_instruction();
 8517   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8518   // imm8:
 8519   // 0x00 - extract from lower 256 bits
 8520   // 0x01 - extract from upper 256 bits
 8521   emit_int24(0x1B, (0xC0 | encode), imm8 & 0x01);
 8522 }
 8523 
 8524 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
 8525   assert(VM_Version::supports_evex(), "");
 8526   assert(src != xnoreg, "sanity");
 8527   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8528   InstructionMark im(this);
 8529   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8530   attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */  EVEX_64bit);
 8531   attributes.reset_is_clear_context();
 8532   attributes.set_is_evex_instruction();
 8533   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8534   emit_int8(0x1B);
 8535   emit_operand(src, dst);
 8536   // 0x00 - extract from lower 256 bits
 8537   // 0x01 - extract from upper 256 bits
 8538   emit_int8(imm8 & 0x01);
 8539 }
 8540 
 8541 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
 8542 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
 8543   assert(VM_Version::supports_avx2(), "");
 8544   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8545   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8546   emit_int16(0x78, (0xC0 | encode));
 8547 }
 8548 
 8549 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
 8550   assert(VM_Version::supports_avx2(), "");
 8551   assert(dst != xnoreg, "sanity");
 8552   InstructionMark im(this);
 8553   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8554   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
 8555   // swap src<->dst for encoding
 8556   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8557   emit_int8(0x78);
 8558   emit_operand(dst, src);
 8559 }
 8560 
 8561 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
 8562 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
 8563   assert(VM_Version::supports_avx2(), "");
 8564   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8565   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8566   emit_int16(0x79, (0xC0 | encode));
 8567 }
 8568 
 8569 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
 8570   assert(VM_Version::supports_avx2(), "");
 8571   assert(dst != xnoreg, "sanity");
 8572   InstructionMark im(this);
 8573   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8574   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 8575   // swap src<->dst for encoding
 8576   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8577   emit_int8(0x79);
 8578   emit_operand(dst, src);
 8579 }
 8580 
 8581 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8582   assert(UseAVX > 0, "requires some form of AVX");
 8583   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8584   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8585   emit_int16((unsigned char)0xF6, (0xC0 | encode));
 8586 }
 8587 
 8588 void Assembler::vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8589   assert(UseAVX > 0, "requires some form of AVX");
 8590   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8591   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8592   emit_int16(0x69, (0xC0 | encode));
 8593 }
 8594 
 8595 void Assembler::vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8596   assert(UseAVX > 0, "requires some form of AVX");
 8597   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8598   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8599   emit_int16(0x61, (0xC0 | encode));
 8600 }
 8601 
 8602 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8603   assert(UseAVX > 0, "requires some form of AVX");
 8604   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8605   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8606   emit_int16(0x6A, (0xC0 | encode));
 8607 }
 8608 
 8609 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8610   assert(UseAVX > 0, "requires some form of AVX");
 8611   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8612   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8613   emit_int16(0x62, (0xC0 | encode));
 8614 }
 8615 
 8616 // xmm/mem sourced byte/word/dword/qword replicate
 8617 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8618   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8619   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8620   attributes.set_is_evex_instruction();
 8621   attributes.set_embedded_opmask_register_specifier(mask);
 8622   if (merge) {
 8623     attributes.reset_is_clear_context();
 8624   }
 8625   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8626   emit_int16((unsigned char)0xFC, (0xC0 | encode));
 8627 }
 8628 
 8629 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8630   InstructionMark im(this);
 8631   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8632   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8633   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8634   attributes.set_is_evex_instruction();
 8635   attributes.set_embedded_opmask_register_specifier(mask);
 8636   if (merge) {
 8637     attributes.reset_is_clear_context();
 8638   }
 8639   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8640   emit_int8((unsigned char)0xFC);
 8641   emit_operand(dst, src);
 8642 }
 8643 
 8644 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8645   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8646   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8647   attributes.set_is_evex_instruction();
 8648   attributes.set_embedded_opmask_register_specifier(mask);
 8649   if (merge) {
 8650     attributes.reset_is_clear_context();
 8651   }
 8652   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8653   emit_int16((unsigned char)0xFD, (0xC0 | encode));
 8654 }
 8655 
 8656 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8657   InstructionMark im(this);
 8658   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8659   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8660   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8661   attributes.set_is_evex_instruction();
 8662   attributes.set_embedded_opmask_register_specifier(mask);
 8663   if (merge) {
 8664     attributes.reset_is_clear_context();
 8665   }
 8666   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8667   emit_int8((unsigned char)0xFD);
 8668   emit_operand(dst, src);
 8669 }
 8670 
 8671 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8672   assert(VM_Version::supports_evex(), "");
 8673   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8674   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8675   attributes.set_is_evex_instruction();
 8676   attributes.set_embedded_opmask_register_specifier(mask);
 8677   if (merge) {
 8678     attributes.reset_is_clear_context();
 8679   }
 8680   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8681   emit_int16((unsigned char)0xFE, (0xC0 | encode));
 8682 }
 8683 
 8684 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8685   InstructionMark im(this);
 8686   assert(VM_Version::supports_evex(), "");
 8687   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8688   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8689   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8690   attributes.set_is_evex_instruction();
 8691   attributes.set_embedded_opmask_register_specifier(mask);
 8692   if (merge) {
 8693     attributes.reset_is_clear_context();
 8694   }
 8695   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8696   emit_int8((unsigned char)0xFE);
 8697   emit_operand(dst, src);
 8698 }
 8699 
 8700 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8701   assert(VM_Version::supports_evex(), "");
 8702   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8703   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8704   attributes.set_is_evex_instruction();
 8705   attributes.set_embedded_opmask_register_specifier(mask);
 8706   if (merge) {
 8707     attributes.reset_is_clear_context();
 8708   }
 8709   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8710   emit_int16((unsigned char)0xD4, (0xC0 | encode));
 8711 }
 8712 
 8713 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8714   InstructionMark im(this);
 8715   assert(VM_Version::supports_evex(), "");
 8716   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8717   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8718   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8719   attributes.set_is_evex_instruction();
 8720   attributes.set_embedded_opmask_register_specifier(mask);
 8721   if (merge) {
 8722     attributes.reset_is_clear_context();
 8723   }
 8724   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8725   emit_int8((unsigned char)0xD4);
 8726   emit_operand(dst, src);
 8727 }
 8728 
 8729 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8730   assert(VM_Version::supports_evex(), "");
 8731   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8732   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8733   attributes.set_is_evex_instruction();
 8734   attributes.set_embedded_opmask_register_specifier(mask);
 8735   if (merge) {
 8736     attributes.reset_is_clear_context();
 8737   }
 8738   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 8739   emit_int16(0x58, (0xC0 | encode));
 8740 }
 8741 
 8742 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8743   InstructionMark im(this);
 8744   assert(VM_Version::supports_evex(), "");
 8745   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8746   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8747   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8748   attributes.set_is_evex_instruction();
 8749   attributes.set_embedded_opmask_register_specifier(mask);
 8750   if (merge) {
 8751     attributes.reset_is_clear_context();
 8752   }
 8753   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 8754   emit_int8(0x58);
 8755   emit_operand(dst, src);
 8756 }
 8757 
 8758 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8759   assert(VM_Version::supports_evex(), "");
 8760   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8761   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8762   attributes.set_is_evex_instruction();
 8763   attributes.set_embedded_opmask_register_specifier(mask);
 8764   if (merge) {
 8765     attributes.reset_is_clear_context();
 8766   }
 8767   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8768   emit_int16(0x58, (0xC0 | encode));
 8769 }
 8770 
 8771 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8772   InstructionMark im(this);
 8773   assert(VM_Version::supports_evex(), "");
 8774   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8775   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8776   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8777   attributes.set_is_evex_instruction();
 8778   attributes.set_embedded_opmask_register_specifier(mask);
 8779   if (merge) {
 8780     attributes.reset_is_clear_context();
 8781   }
 8782   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8783   emit_int8(0x58);
 8784   emit_operand(dst, src);
 8785 }
 8786 
 8787 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8788   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8789   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8790   attributes.set_is_evex_instruction();
 8791   attributes.set_embedded_opmask_register_specifier(mask);
 8792   if (merge) {
 8793     attributes.reset_is_clear_context();
 8794   }
 8795   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8796   emit_int16((unsigned char)0xF8, (0xC0 | encode));
 8797 }
 8798 
 8799 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8800   InstructionMark im(this);
 8801   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8802   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8803   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8804   attributes.set_is_evex_instruction();
 8805   attributes.set_embedded_opmask_register_specifier(mask);
 8806   if (merge) {
 8807     attributes.reset_is_clear_context();
 8808   }
 8809   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8810   emit_int8((unsigned char)0xF8);
 8811   emit_operand(dst, src);
 8812 }
 8813 
 8814 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8815   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8816   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8817   attributes.set_is_evex_instruction();
 8818   attributes.set_embedded_opmask_register_specifier(mask);
 8819   if (merge) {
 8820     attributes.reset_is_clear_context();
 8821   }
 8822   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8823   emit_int16((unsigned char)0xF9, (0xC0 | encode));
 8824 }
 8825 
 8826 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8827   InstructionMark im(this);
 8828   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8829   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8830   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8831   attributes.set_is_evex_instruction();
 8832   attributes.set_embedded_opmask_register_specifier(mask);
 8833   if (merge) {
 8834     attributes.reset_is_clear_context();
 8835   }
 8836   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8837   emit_int8((unsigned char)0xF9);
 8838   emit_operand(dst, src);
 8839 }
 8840 
 8841 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8842   assert(VM_Version::supports_evex(), "");
 8843   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8844   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8845   attributes.set_is_evex_instruction();
 8846   attributes.set_embedded_opmask_register_specifier(mask);
 8847   if (merge) {
 8848     attributes.reset_is_clear_context();
 8849   }
 8850   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8851   emit_int16((unsigned char)0xFA, (0xC0 | encode));
 8852 }
 8853 
 8854 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8855   InstructionMark im(this);
 8856   assert(VM_Version::supports_evex(), "");
 8857   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8858   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8859   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8860   attributes.set_is_evex_instruction();
 8861   attributes.set_embedded_opmask_register_specifier(mask);
 8862   if (merge) {
 8863     attributes.reset_is_clear_context();
 8864   }
 8865   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8866   emit_int8((unsigned char)0xFA);
 8867   emit_operand(dst, src);
 8868 }
 8869 
 8870 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8871   assert(VM_Version::supports_evex(), "");
 8872   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8873   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8874   attributes.set_is_evex_instruction();
 8875   attributes.set_embedded_opmask_register_specifier(mask);
 8876   if (merge) {
 8877     attributes.reset_is_clear_context();
 8878   }
 8879   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8880   emit_int16((unsigned char)0xFB, (0xC0 | encode));
 8881 }
 8882 
 8883 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8884   InstructionMark im(this);
 8885   assert(VM_Version::supports_evex(), "");
 8886   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8887   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8888   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8889   attributes.set_is_evex_instruction();
 8890   attributes.set_embedded_opmask_register_specifier(mask);
 8891   if (merge) {
 8892     attributes.reset_is_clear_context();
 8893   }
 8894   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8895   emit_int8((unsigned char)0xFB);
 8896   emit_operand(dst, src);
 8897 }
 8898 
 8899 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8900   assert(VM_Version::supports_evex(), "");
 8901   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8902   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8903   attributes.set_is_evex_instruction();
 8904   attributes.set_embedded_opmask_register_specifier(mask);
 8905   if (merge) {
 8906     attributes.reset_is_clear_context();
 8907   }
 8908   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 8909   emit_int16(0x5C, (0xC0 | encode));
 8910 }
 8911 
 8912 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8913   InstructionMark im(this);
 8914   assert(VM_Version::supports_evex(), "");
 8915   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8916   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8917   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8918   attributes.set_is_evex_instruction();
 8919   attributes.set_embedded_opmask_register_specifier(mask);
 8920   if (merge) {
 8921     attributes.reset_is_clear_context();
 8922   }
 8923   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 8924   emit_int8(0x5C);
 8925   emit_operand(dst, src);
 8926 }
 8927 
 8928 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8929   assert(VM_Version::supports_evex(), "");
 8930   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8931   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8932   attributes.set_is_evex_instruction();
 8933   attributes.set_embedded_opmask_register_specifier(mask);
 8934   if (merge) {
 8935     attributes.reset_is_clear_context();
 8936   }
 8937   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8938   emit_int16(0x5C, (0xC0 | encode));
 8939 }
 8940 
 8941 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8942   InstructionMark im(this);
 8943   assert(VM_Version::supports_evex(), "");
 8944   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8945   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8946   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8947   attributes.set_is_evex_instruction();
 8948   attributes.set_embedded_opmask_register_specifier(mask);
 8949   if (merge) {
 8950     attributes.reset_is_clear_context();
 8951   }
 8952   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8953   emit_int8(0x5C);
 8954   emit_operand(dst, src);
 8955 }
 8956 
 8957 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8958   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8959   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8960   attributes.set_is_evex_instruction();
 8961   attributes.set_embedded_opmask_register_specifier(mask);
 8962   if (merge) {
 8963     attributes.reset_is_clear_context();
 8964   }
 8965   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8966   emit_int16((unsigned char)0xD5, (0xC0 | encode));
 8967 }
 8968 
 8969 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8970   InstructionMark im(this);
 8971   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8972   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8973   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 8974   attributes.set_is_evex_instruction();
 8975   attributes.set_embedded_opmask_register_specifier(mask);
 8976   if (merge) {
 8977     attributes.reset_is_clear_context();
 8978   }
 8979   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8980   emit_int8((unsigned char)0xD5);
 8981   emit_operand(dst, src);
 8982 }
 8983 
 8984 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8985   assert(VM_Version::supports_evex(), "");
 8986   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8987   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8988   attributes.set_is_evex_instruction();
 8989   attributes.set_embedded_opmask_register_specifier(mask);
 8990   if (merge) {
 8991     attributes.reset_is_clear_context();
 8992   }
 8993   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8994   emit_int16(0x40, (0xC0 | encode));
 8995 }
 8996 
 8997 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 8998   InstructionMark im(this);
 8999   assert(VM_Version::supports_evex(), "");
 9000   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9001   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9002   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9003   attributes.set_is_evex_instruction();
 9004   attributes.set_embedded_opmask_register_specifier(mask);
 9005   if (merge) {
 9006     attributes.reset_is_clear_context();
 9007   }
 9008   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9009   emit_int8(0x40);
 9010   emit_operand(dst, src);
 9011 }
 9012 
 9013 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9014   assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9015   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9016   attributes.set_is_evex_instruction();
 9017   attributes.set_embedded_opmask_register_specifier(mask);
 9018   if (merge) {
 9019     attributes.reset_is_clear_context();
 9020   }
 9021   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9022   emit_int16(0x40, (0xC0 | encode));
 9023 }
 9024 
 9025 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9026   InstructionMark im(this);
 9027   assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9028   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9029   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9030   attributes.set_is_evex_instruction();
 9031   attributes.set_embedded_opmask_register_specifier(mask);
 9032   if (merge) {
 9033     attributes.reset_is_clear_context();
 9034   }
 9035   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9036   emit_int8(0x40);
 9037   emit_operand(dst, src);
 9038 }
 9039 
 9040 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9041   assert(VM_Version::supports_evex(), "");
 9042   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9043   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9044   attributes.set_is_evex_instruction();
 9045   attributes.set_embedded_opmask_register_specifier(mask);
 9046   if (merge) {
 9047     attributes.reset_is_clear_context();
 9048   }
 9049   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9050   emit_int16(0x59, (0xC0 | encode));
 9051 }
 9052 
 9053 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9054   InstructionMark im(this);
 9055   assert(VM_Version::supports_evex(), "");
 9056   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9057   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9058   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9059   attributes.set_is_evex_instruction();
 9060   attributes.set_embedded_opmask_register_specifier(mask);
 9061   if (merge) {
 9062     attributes.reset_is_clear_context();
 9063   }
 9064   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9065   emit_int8(0x59);
 9066   emit_operand(dst, src);
 9067 }
 9068 
 9069 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9070   assert(VM_Version::supports_evex(), "");
 9071   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9072   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9073   attributes.set_is_evex_instruction();
 9074   attributes.set_embedded_opmask_register_specifier(mask);
 9075   if (merge) {
 9076     attributes.reset_is_clear_context();
 9077   }
 9078   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9079   emit_int16(0x59, (0xC0 | encode));
 9080 }
 9081 
 9082 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9083   InstructionMark im(this);
 9084   assert(VM_Version::supports_evex(), "");
 9085   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9086   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9087   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9088   attributes.set_is_evex_instruction();
 9089   attributes.set_embedded_opmask_register_specifier(mask);
 9090   if (merge) {
 9091     attributes.reset_is_clear_context();
 9092   }
 9093   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9094   emit_int8(0x59);
 9095   emit_operand(dst, src);
 9096 }
 9097 
 9098 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9099   assert(VM_Version::supports_evex(), "");
 9100   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9101   InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9102   attributes.set_is_evex_instruction();
 9103   attributes.set_embedded_opmask_register_specifier(mask);
 9104   if (merge) {
 9105     attributes.reset_is_clear_context();
 9106   }
 9107   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9108   emit_int16(0x51, (0xC0 | encode));
 9109 }
 9110 
 9111 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9112   InstructionMark im(this);
 9113   assert(VM_Version::supports_evex(), "");
 9114   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9115   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9116   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9117   attributes.set_is_evex_instruction();
 9118   attributes.set_embedded_opmask_register_specifier(mask);
 9119   if (merge) {
 9120     attributes.reset_is_clear_context();
 9121   }
 9122   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9123   emit_int8(0x51);
 9124   emit_operand(dst, src);
 9125 }
 9126 
 9127 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9128   assert(VM_Version::supports_evex(), "");
 9129   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9130   InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9131   attributes.set_is_evex_instruction();
 9132   attributes.set_embedded_opmask_register_specifier(mask);
 9133   if (merge) {
 9134     attributes.reset_is_clear_context();
 9135   }
 9136   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9137   emit_int16(0x51, (0xC0 | encode));
 9138 }
 9139 
 9140 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9141   InstructionMark im(this);
 9142   assert(VM_Version::supports_evex(), "");
 9143   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9144   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9145   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9146   attributes.set_is_evex_instruction();
 9147   attributes.set_embedded_opmask_register_specifier(mask);
 9148   if (merge) {
 9149     attributes.reset_is_clear_context();
 9150   }
 9151   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9152   emit_int8(0x51);
 9153   emit_operand(dst, src);
 9154 }
 9155 
 9156 
 9157 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9158   assert(VM_Version::supports_evex(), "");
 9159   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9160   InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9161   attributes.set_is_evex_instruction();
 9162   attributes.set_embedded_opmask_register_specifier(mask);
 9163   if (merge) {
 9164     attributes.reset_is_clear_context();
 9165   }
 9166   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9167   emit_int16(0x5E, (0xC0 | encode));
 9168 }
 9169 
 9170 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9171   InstructionMark im(this);
 9172   assert(VM_Version::supports_evex(), "");
 9173   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9174   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9175   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9176   attributes.set_is_evex_instruction();
 9177   attributes.set_embedded_opmask_register_specifier(mask);
 9178   if (merge) {
 9179     attributes.reset_is_clear_context();
 9180   }
 9181   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
 9182   emit_int8(0x5E);
 9183   emit_operand(dst, src);
 9184 }
 9185 
 9186 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9187   assert(VM_Version::supports_evex(), "");
 9188   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9189   InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9190   attributes.set_is_evex_instruction();
 9191   attributes.set_embedded_opmask_register_specifier(mask);
 9192   if (merge) {
 9193     attributes.reset_is_clear_context();
 9194   }
 9195   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9196   emit_int16(0x5E, (0xC0 | encode));
 9197 }
 9198 
 9199 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9200   InstructionMark im(this);
 9201   assert(VM_Version::supports_evex(), "");
 9202   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9203   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9204   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9205   attributes.set_is_evex_instruction();
 9206   attributes.set_embedded_opmask_register_specifier(mask);
 9207   if (merge) {
 9208     attributes.reset_is_clear_context();
 9209   }
 9210   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9211   emit_int8(0x5E);
 9212   emit_operand(dst, src);
 9213 }
 9214 
 9215 void Assembler::evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 9216   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9217   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9218   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9219   attributes.set_is_evex_instruction();
 9220   attributes.set_embedded_opmask_register_specifier(mask);
 9221   if (merge) {
 9222     attributes.reset_is_clear_context();
 9223   }
 9224   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9225   emit_int16(0x1C, (0xC0 | encode));
 9226 }
 9227 
 9228 
 9229 void Assembler::evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 9230   InstructionMark im(this);
 9231   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9232   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9233   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9234   attributes.set_is_evex_instruction();
 9235   attributes.set_embedded_opmask_register_specifier(mask);
 9236   if (merge) {
 9237     attributes.reset_is_clear_context();
 9238   }
 9239   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9240   emit_int8(0x1C);
 9241   emit_operand(dst, src);
 9242 }
 9243 
 9244 void Assembler::evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 9245   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9246   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9247   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9248   attributes.set_is_evex_instruction();
 9249   attributes.set_embedded_opmask_register_specifier(mask);
 9250   if (merge) {
 9251     attributes.reset_is_clear_context();
 9252   }
 9253   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9254   emit_int16(0x1D, (0xC0 | encode));
 9255 }
 9256 
 9257 
 9258 void Assembler::evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 9259   InstructionMark im(this);
 9260   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9261   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9262   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9263   attributes.set_is_evex_instruction();
 9264   attributes.set_embedded_opmask_register_specifier(mask);
 9265   if (merge) {
 9266     attributes.reset_is_clear_context();
 9267   }
 9268   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9269   emit_int8(0x1D);
 9270   emit_operand(dst, src);
 9271 }
 9272 
 9273 void Assembler::evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 9274   assert(VM_Version::supports_evex(), "");
 9275   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9276   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9277   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9278   attributes.set_is_evex_instruction();
 9279   attributes.set_embedded_opmask_register_specifier(mask);
 9280   if (merge) {
 9281     attributes.reset_is_clear_context();
 9282   }
 9283   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9284   emit_int16(0x1E, (0xC0 | encode));
 9285 }
 9286 
 9287 
 9288 void Assembler::evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 9289   InstructionMark im(this);
 9290   assert(VM_Version::supports_evex(), "");
 9291   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9292   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9293   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9294   attributes.set_is_evex_instruction();
 9295   attributes.set_embedded_opmask_register_specifier(mask);
 9296   if (merge) {
 9297     attributes.reset_is_clear_context();
 9298   }
 9299   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9300   emit_int8(0x1E);
 9301   emit_operand(dst, src);
 9302 }
 9303 
 9304 void Assembler::evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 9305   assert(VM_Version::supports_evex(), "");
 9306   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9307   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9308   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9309   attributes.set_is_evex_instruction();
 9310   attributes.set_embedded_opmask_register_specifier(mask);
 9311   if (merge) {
 9312     attributes.reset_is_clear_context();
 9313   }
 9314   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9315   emit_int16(0x1F, (0xC0 | encode));
 9316 }
 9317 
 9318 
 9319 void Assembler::evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
 9320   InstructionMark im(this);
 9321   assert(VM_Version::supports_evex(), "");
 9322   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9323   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9324   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9325   attributes.set_is_evex_instruction();
 9326   attributes.set_embedded_opmask_register_specifier(mask);
 9327   if (merge) {
 9328     attributes.reset_is_clear_context();
 9329   }
 9330   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9331   emit_int8(0x1F);
 9332   emit_operand(dst, src);
 9333 }
 9334 
 9335 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9336   assert(VM_Version::supports_evex(), "");
 9337   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9338   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9339   attributes.set_is_evex_instruction();
 9340   attributes.set_embedded_opmask_register_specifier(mask);
 9341   if (merge) {
 9342     attributes.reset_is_clear_context();
 9343   }
 9344   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9345   emit_int16((unsigned char)0xA8, (0xC0 | encode));
 9346 }
 9347 
 9348 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9349   InstructionMark im(this);
 9350   assert(VM_Version::supports_evex(), "");
 9351   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9352   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9353   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9354   attributes.set_is_evex_instruction();
 9355   attributes.set_embedded_opmask_register_specifier(mask);
 9356   if (merge) {
 9357     attributes.reset_is_clear_context();
 9358   }
 9359   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9360   emit_int8((unsigned char)0xA8);
 9361   emit_operand(dst, src);
 9362 }
 9363 
 9364 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9365   assert(VM_Version::supports_evex(), "");
 9366   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9367   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9368   attributes.set_is_evex_instruction();
 9369   attributes.set_embedded_opmask_register_specifier(mask);
 9370   if (merge) {
 9371     attributes.reset_is_clear_context();
 9372   }
 9373   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9374   emit_int16((unsigned char)0xA8, (0xC0 | encode));
 9375 }
 9376 
 9377 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9378   InstructionMark im(this);
 9379   assert(VM_Version::supports_evex(), "");
 9380   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9381   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 9382   attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
 9383   attributes.set_is_evex_instruction();
 9384   attributes.set_embedded_opmask_register_specifier(mask);
 9385   if (merge) {
 9386     attributes.reset_is_clear_context();
 9387   }
 9388   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9389   emit_int8((unsigned char)0xA8);
 9390   emit_operand(dst, src);
 9391 }
 9392 
 9393 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9394   assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9395   InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9396   attributes.set_is_evex_instruction();
 9397   attributes.set_embedded_opmask_register_specifier(mask);
 9398   if (merge) {
 9399     attributes.reset_is_clear_context();
 9400   }
 9401   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9402   emit_int16((unsigned char)0x8D, (0xC0 | encode));
 9403 }
 9404 
 9405 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9406   assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9407   InstructionMark im(this);
 9408   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9409   attributes.set_is_evex_instruction();
 9410   attributes.set_embedded_opmask_register_specifier(mask);
 9411   if (merge) {
 9412     attributes.reset_is_clear_context();
 9413   }
 9414   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9415   emit_int8((unsigned char)0x8D);
 9416   emit_operand(dst, src);
 9417 }
 9418 
 9419 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9420   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9421   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9422   attributes.set_is_evex_instruction();
 9423   attributes.set_embedded_opmask_register_specifier(mask);
 9424   if (merge) {
 9425     attributes.reset_is_clear_context();
 9426   }
 9427   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9428   emit_int16((unsigned char)0x8D, (0xC0 | encode));
 9429 }
 9430 
 9431 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9432   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9433   InstructionMark im(this);
 9434   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9435   attributes.set_is_evex_instruction();
 9436   attributes.set_embedded_opmask_register_specifier(mask);
 9437   if (merge) {
 9438     attributes.reset_is_clear_context();
 9439   }
 9440   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9441   emit_int8((unsigned char)0x8D);
 9442   emit_operand(dst, src);
 9443 }
 9444 
 9445 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9446   assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
 9447   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9448   attributes.set_is_evex_instruction();
 9449   attributes.set_embedded_opmask_register_specifier(mask);
 9450   if (merge) {
 9451     attributes.reset_is_clear_context();
 9452   }
 9453   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9454   emit_int16(0x36, (0xC0 | encode));
 9455 }
 9456 
 9457 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9458   assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
 9459   InstructionMark im(this);
 9460   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9461   attributes.set_is_evex_instruction();
 9462   attributes.set_embedded_opmask_register_specifier(mask);
 9463   if (merge) {
 9464     attributes.reset_is_clear_context();
 9465   }
 9466   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9467   emit_int8(0x36);
 9468   emit_operand(dst, src);
 9469 }
 9470 
 9471 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9472   assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
 9473   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9474   attributes.set_is_evex_instruction();
 9475   attributes.set_embedded_opmask_register_specifier(mask);
 9476   if (merge) {
 9477     attributes.reset_is_clear_context();
 9478   }
 9479   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9480   emit_int16(0x36, (0xC0 | encode));
 9481 }
 9482 
 9483 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9484   assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
 9485   InstructionMark im(this);
 9486   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9487   attributes.set_is_evex_instruction();
 9488   attributes.set_embedded_opmask_register_specifier(mask);
 9489   if (merge) {
 9490     attributes.reset_is_clear_context();
 9491   }
 9492   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9493   emit_int8(0x36);
 9494   emit_operand(dst, src);
 9495 }
 9496 
 9497 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9498   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9499   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9500   attributes.set_is_evex_instruction();
 9501   attributes.set_embedded_opmask_register_specifier(mask);
 9502   if (merge) {
 9503     attributes.reset_is_clear_context();
 9504   }
 9505   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9506   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 9507 }
 9508 
 9509 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9510   assert(VM_Version::supports_evex(), "");
 9511   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9512   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9513   attributes.set_is_evex_instruction();
 9514   attributes.set_embedded_opmask_register_specifier(mask);
 9515   if (merge) {
 9516     attributes.reset_is_clear_context();
 9517   }
 9518   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9519   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 9520 }
 9521 
 9522 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9523   assert(VM_Version::supports_evex(), "");
 9524   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9525   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9526   attributes.set_is_evex_instruction();
 9527   attributes.set_embedded_opmask_register_specifier(mask);
 9528   if (merge) {
 9529     attributes.reset_is_clear_context();
 9530   }
 9531   int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9532   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 9533 }
 9534 
 9535 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9536   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9537   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9538   attributes.set_is_evex_instruction();
 9539   attributes.set_embedded_opmask_register_specifier(mask);
 9540   if (merge) {
 9541     attributes.reset_is_clear_context();
 9542   }
 9543   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9544   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 9545 }
 9546 
 9547 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9548   assert(VM_Version::supports_evex(), "");
 9549   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9550   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9551   attributes.set_is_evex_instruction();
 9552   attributes.set_embedded_opmask_register_specifier(mask);
 9553   if (merge) {
 9554     attributes.reset_is_clear_context();
 9555   }
 9556   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9557   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 9558 }
 9559 
 9560 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9561   assert(VM_Version::supports_evex(), "");
 9562   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9563   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9564   attributes.set_is_evex_instruction();
 9565   attributes.set_embedded_opmask_register_specifier(mask);
 9566   if (merge) {
 9567     attributes.reset_is_clear_context();
 9568   }
 9569   int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9570   emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
 9571 }
 9572 
 9573 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9574   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9575   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9576   attributes.set_is_evex_instruction();
 9577   attributes.set_embedded_opmask_register_specifier(mask);
 9578   if (merge) {
 9579     attributes.reset_is_clear_context();
 9580   }
 9581   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9582   emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
 9583 }
 9584 
 9585 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9586   assert(VM_Version::supports_evex(), "");
 9587   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9588   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9589   attributes.set_is_evex_instruction();
 9590   attributes.set_embedded_opmask_register_specifier(mask);
 9591   if (merge) {
 9592     attributes.reset_is_clear_context();
 9593   }
 9594   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9595   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 9596 }
 9597 
 9598 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
 9599   assert(VM_Version::supports_evex(), "");
 9600   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9601   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9602   attributes.set_is_evex_instruction();
 9603   attributes.set_embedded_opmask_register_specifier(mask);
 9604   if (merge) {
 9605     attributes.reset_is_clear_context();
 9606   }
 9607   int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9608   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
 9609 }
 9610 
 9611 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9612   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9613   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9614   attributes.set_is_evex_instruction();
 9615   attributes.set_embedded_opmask_register_specifier(mask);
 9616   if (merge) {
 9617     attributes.reset_is_clear_context();
 9618   }
 9619   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9620   emit_int16((unsigned char)0xF1, (0xC0 | encode));
 9621 }
 9622 
 9623 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9624   assert(VM_Version::supports_evex(), "");
 9625   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9626   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9627   attributes.set_is_evex_instruction();
 9628   attributes.set_embedded_opmask_register_specifier(mask);
 9629   if (merge) {
 9630     attributes.reset_is_clear_context();
 9631   }
 9632   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9633   emit_int16((unsigned char)0xF2, (0xC0 | encode));
 9634 }
 9635 
 9636 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9637   assert(VM_Version::supports_evex(), "");
 9638   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9639   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9640   attributes.set_is_evex_instruction();
 9641   attributes.set_embedded_opmask_register_specifier(mask);
 9642   if (merge) {
 9643     attributes.reset_is_clear_context();
 9644   }
 9645   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9646   emit_int16((unsigned char)0xF3, (0xC0 | encode));
 9647 }
 9648 
 9649 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9650   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9651   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9652   attributes.set_is_evex_instruction();
 9653   attributes.set_embedded_opmask_register_specifier(mask);
 9654   if (merge) {
 9655     attributes.reset_is_clear_context();
 9656   }
 9657   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9658   emit_int16((unsigned char)0xD1, (0xC0 | encode));
 9659 }
 9660 
 9661 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9662   assert(VM_Version::supports_evex(), "");
 9663   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9664   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9665   attributes.set_is_evex_instruction();
 9666   attributes.set_embedded_opmask_register_specifier(mask);
 9667   if (merge) {
 9668     attributes.reset_is_clear_context();
 9669   }
 9670   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9671   emit_int16((unsigned char)0xD2, (0xC0 | encode));
 9672 }
 9673 
 9674 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9675   assert(VM_Version::supports_evex(), "");
 9676   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9677   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9678   attributes.set_is_evex_instruction();
 9679   attributes.set_embedded_opmask_register_specifier(mask);
 9680   if (merge) {
 9681     attributes.reset_is_clear_context();
 9682   }
 9683   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9684   emit_int16((unsigned char)0xD3, (0xC0 | encode));
 9685 }
 9686 
 9687 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9688   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9689   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9690   attributes.set_is_evex_instruction();
 9691   attributes.set_embedded_opmask_register_specifier(mask);
 9692   if (merge) {
 9693     attributes.reset_is_clear_context();
 9694   }
 9695   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9696   emit_int16((unsigned char)0xE1, (0xC0 | encode));
 9697 }
 9698 
 9699 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9700   assert(VM_Version::supports_evex(), "");
 9701   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9702   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9703   attributes.set_is_evex_instruction();
 9704   attributes.set_embedded_opmask_register_specifier(mask);
 9705   if (merge) {
 9706     attributes.reset_is_clear_context();
 9707   }
 9708   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9709   emit_int16((unsigned char)0xE2, (0xC0 | encode));
 9710 }
 9711 
 9712 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9713   assert(VM_Version::supports_evex(), "");
 9714   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9715   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9716   attributes.set_is_evex_instruction();
 9717   attributes.set_embedded_opmask_register_specifier(mask);
 9718   if (merge) {
 9719     attributes.reset_is_clear_context();
 9720   }
 9721   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9722   emit_int16((unsigned char)0xE2, (0xC0 | encode));
 9723 }
 9724 
 9725 void Assembler::evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9726   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9727   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9728   attributes.set_is_evex_instruction();
 9729   attributes.set_embedded_opmask_register_specifier(mask);
 9730   if (merge) {
 9731     attributes.reset_is_clear_context();
 9732   }
 9733   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9734   emit_int16(0x12, (0xC0 | encode));
 9735 }
 9736 
 9737 void Assembler::evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9738   assert(VM_Version::supports_evex(), "");
 9739   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9740   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9741   attributes.set_is_evex_instruction();
 9742   attributes.set_embedded_opmask_register_specifier(mask);
 9743   if (merge) {
 9744     attributes.reset_is_clear_context();
 9745   }
 9746   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9747   emit_int16(0x47, (0xC0 | encode));
 9748 }
 9749 
 9750 void Assembler::evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9751   assert(VM_Version::supports_evex(), "");
 9752   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9753   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9754   attributes.set_is_evex_instruction();
 9755   attributes.set_embedded_opmask_register_specifier(mask);
 9756   if (merge) {
 9757     attributes.reset_is_clear_context();
 9758   }
 9759   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9760   emit_int16(0x47, (0xC0 | encode));
 9761 }
 9762 
 9763 void Assembler::evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9764   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9765   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9766   attributes.set_is_evex_instruction();
 9767   attributes.set_embedded_opmask_register_specifier(mask);
 9768   if (merge) {
 9769     attributes.reset_is_clear_context();
 9770   }
 9771   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9772   emit_int16(0x10, (0xC0 | encode));
 9773 }
 9774 
 9775 void Assembler::evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9776   assert(VM_Version::supports_evex(), "");
 9777   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9778   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9779   attributes.set_is_evex_instruction();
 9780   attributes.set_embedded_opmask_register_specifier(mask);
 9781   if (merge) {
 9782     attributes.reset_is_clear_context();
 9783   }
 9784   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9785   emit_int16(0x45, (0xC0 | encode));
 9786 }
 9787 
 9788 void Assembler::evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9789   assert(VM_Version::supports_evex(), "");
 9790   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9791   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9792   attributes.set_is_evex_instruction();
 9793   attributes.set_embedded_opmask_register_specifier(mask);
 9794   if (merge) {
 9795     attributes.reset_is_clear_context();
 9796   }
 9797   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9798   emit_int16(0x45, (0xC0 | encode));
 9799 }
 9800 
 9801 void Assembler::evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9802   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9803   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9804   attributes.set_is_evex_instruction();
 9805   attributes.set_embedded_opmask_register_specifier(mask);
 9806   if (merge) {
 9807     attributes.reset_is_clear_context();
 9808   }
 9809   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9810   emit_int16(0x11, (0xC0 | encode));
 9811 }
 9812 
 9813 void Assembler::evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9814   assert(VM_Version::supports_evex(), "");
 9815   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9816   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9817   attributes.set_is_evex_instruction();
 9818   attributes.set_embedded_opmask_register_specifier(mask);
 9819   if (merge) {
 9820     attributes.reset_is_clear_context();
 9821   }
 9822   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9823   emit_int16(0x46, (0xC0 | encode));
 9824 }
 9825 
 9826 void Assembler::evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9827   assert(VM_Version::supports_evex(), "");
 9828   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9829   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9830   attributes.set_is_evex_instruction();
 9831   attributes.set_embedded_opmask_register_specifier(mask);
 9832   if (merge) {
 9833     attributes.reset_is_clear_context();
 9834   }
 9835   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9836   emit_int16(0x46, (0xC0 | encode));
 9837 }
 9838 
 9839 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9840   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9841   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9842   attributes.set_is_evex_instruction();
 9843   attributes.set_embedded_opmask_register_specifier(mask);
 9844   if (merge) {
 9845     attributes.reset_is_clear_context();
 9846   }
 9847   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9848   emit_int16(0x38, (0xC0 | encode));
 9849 }
 9850 
 9851 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9852   assert(VM_Version::supports_avx512bw(), "");
 9853   InstructionMark im(this);
 9854   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9855   attributes.set_is_evex_instruction();
 9856   attributes.set_embedded_opmask_register_specifier(mask);
 9857   if (merge) {
 9858     attributes.reset_is_clear_context();
 9859   }
 9860   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9861   emit_int8(0x38);
 9862   emit_operand(dst, src);
 9863 }
 9864 
 9865 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9866   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9867   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9868   attributes.set_is_evex_instruction();
 9869   attributes.set_embedded_opmask_register_specifier(mask);
 9870   if (merge) {
 9871     attributes.reset_is_clear_context();
 9872   }
 9873   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9874   emit_int16((unsigned char)0xEA, (0xC0 | encode));
 9875 }
 9876 
 9877 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9878   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9879   InstructionMark im(this);
 9880   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9881   attributes.set_is_evex_instruction();
 9882   attributes.set_embedded_opmask_register_specifier(mask);
 9883   if (merge) {
 9884     attributes.reset_is_clear_context();
 9885   }
 9886   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9887   emit_int8((unsigned char)0xEA);
 9888   emit_operand(dst, src);
 9889 }
 9890 
 9891 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9892   assert(VM_Version::supports_evex(), "");
 9893   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9894   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9895   attributes.set_is_evex_instruction();
 9896   attributes.set_embedded_opmask_register_specifier(mask);
 9897   if (merge) {
 9898     attributes.reset_is_clear_context();
 9899   }
 9900   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9901   emit_int16(0x39, (0xC0 | encode));
 9902 }
 9903 
 9904 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9905   assert(VM_Version::supports_evex(), "");
 9906   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9907   InstructionMark im(this);
 9908   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9909   attributes.set_is_evex_instruction();
 9910   attributes.set_embedded_opmask_register_specifier(mask);
 9911   if (merge) {
 9912     attributes.reset_is_clear_context();
 9913   }
 9914   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9915   emit_int8(0x39);
 9916   emit_operand(dst, src);
 9917 }
 9918 
 9919 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9920   assert(VM_Version::supports_evex(), "");
 9921   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9922   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9923   attributes.set_is_evex_instruction();
 9924   attributes.set_embedded_opmask_register_specifier(mask);
 9925   if (merge) {
 9926     attributes.reset_is_clear_context();
 9927   }
 9928   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9929   emit_int16(0x39, (0xC0 | encode));
 9930 }
 9931 
 9932 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9933   assert(VM_Version::supports_evex(), "");
 9934   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 9935   InstructionMark im(this);
 9936   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9937   attributes.set_is_evex_instruction();
 9938   attributes.set_embedded_opmask_register_specifier(mask);
 9939   if (merge) {
 9940     attributes.reset_is_clear_context();
 9941   }
 9942   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9943   emit_int8(0x39);
 9944   emit_operand(dst, src);
 9945 }
 9946 
 9947 
 9948 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9949   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9950   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9951   attributes.set_is_evex_instruction();
 9952   attributes.set_embedded_opmask_register_specifier(mask);
 9953   if (merge) {
 9954     attributes.reset_is_clear_context();
 9955   }
 9956   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9957   emit_int16(0x3C, (0xC0 | encode));
 9958 }
 9959 
 9960 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9961   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9962   InstructionMark im(this);
 9963   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9964   attributes.set_is_evex_instruction();
 9965   attributes.set_embedded_opmask_register_specifier(mask);
 9966   if (merge) {
 9967     attributes.reset_is_clear_context();
 9968   }
 9969   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9970   emit_int8(0x3C);
 9971   emit_operand(dst, src);
 9972 }
 9973 
 9974 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 9975   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9976   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9977   attributes.set_is_evex_instruction();
 9978   attributes.set_embedded_opmask_register_specifier(mask);
 9979   if (merge) {
 9980     attributes.reset_is_clear_context();
 9981   }
 9982   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9983   emit_int16((unsigned char)0xEE, (0xC0 | encode));
 9984 }
 9985 
 9986 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
 9987   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 9988   InstructionMark im(this);
 9989   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9990   attributes.set_is_evex_instruction();
 9991   attributes.set_embedded_opmask_register_specifier(mask);
 9992   if (merge) {
 9993     attributes.reset_is_clear_context();
 9994   }
 9995   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 9996   emit_int8((unsigned char)0xEE);
 9997   emit_operand(dst, src);
 9998 }
 9999 
10000 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10001   assert(VM_Version::supports_evex(), "");
10002   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10003   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10004   attributes.set_is_evex_instruction();
10005   attributes.set_embedded_opmask_register_specifier(mask);
10006   if (merge) {
10007     attributes.reset_is_clear_context();
10008   }
10009   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10010   emit_int16(0x3D, (0xC0 | encode));
10011 }
10012 
10013 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10014   assert(VM_Version::supports_evex(), "");
10015   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10016   InstructionMark im(this);
10017   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10018   attributes.set_is_evex_instruction();
10019   attributes.set_embedded_opmask_register_specifier(mask);
10020   if (merge) {
10021     attributes.reset_is_clear_context();
10022   }
10023   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10024   emit_int8(0x3D);
10025   emit_operand(dst, src);
10026 }
10027 
10028 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10029   assert(VM_Version::supports_evex(), "");
10030   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10031   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10032   attributes.set_is_evex_instruction();
10033   attributes.set_embedded_opmask_register_specifier(mask);
10034   if (merge) {
10035     attributes.reset_is_clear_context();
10036   }
10037   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10038   emit_int16(0x3D, (0xC0 | encode));
10039 }
10040 
10041 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10042   assert(VM_Version::supports_evex(), "");
10043   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10044   InstructionMark im(this);
10045   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10046   attributes.set_is_evex_instruction();
10047   attributes.set_embedded_opmask_register_specifier(mask);
10048   if (merge) {
10049     attributes.reset_is_clear_context();
10050   }
10051   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10052   emit_int8(0x3D);
10053   emit_operand(dst, src);
10054 }
10055 
10056 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10057   assert(VM_Version::supports_evex(), "requires EVEX support");
10058   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10059   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10060   attributes.set_is_evex_instruction();
10061   attributes.set_embedded_opmask_register_specifier(mask);
10062   if (merge) {
10063     attributes.reset_is_clear_context();
10064   }
10065   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10066   emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10067 }
10068 
10069 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10070   assert(VM_Version::supports_evex(), "requires EVEX support");
10071   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10072   assert(dst != xnoreg, "sanity");
10073   InstructionMark im(this);
10074   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10075   attributes.set_is_evex_instruction();
10076   attributes.set_embedded_opmask_register_specifier(mask);
10077   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10078   if (merge) {
10079     attributes.reset_is_clear_context();
10080   }
10081   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10082   emit_int8(0x25);
10083   emit_operand(dst, src3);
10084   emit_int8(imm8);
10085 }
10086 
10087 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10088   assert(VM_Version::supports_evex(), "requires EVEX support");
10089   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10090   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10091   attributes.set_is_evex_instruction();
10092   attributes.set_embedded_opmask_register_specifier(mask);
10093   if (merge) {
10094     attributes.reset_is_clear_context();
10095   }
10096   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10097   emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10098 }
10099 
10100 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10101   assert(VM_Version::supports_evex(), "requires EVEX support");
10102   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10103   assert(dst != xnoreg, "sanity");
10104   InstructionMark im(this);
10105   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10106   attributes.set_is_evex_instruction();
10107   attributes.set_embedded_opmask_register_specifier(mask);
10108   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10109   if (merge) {
10110     attributes.reset_is_clear_context();
10111   }
10112   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10113   emit_int8(0x25);
10114   emit_operand(dst, src3);
10115   emit_int8(imm8);
10116 }
10117 
10118 void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
10119   assert(VM_Version::supports_gfni(), "");
10120   assert(VM_Version::supports_sse(), "");
10121   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
10122   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10123   emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10124 }
10125 
10126 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
10127   assert(VM_Version::supports_gfni(), "requires GFNI support");
10128   assert(VM_Version::supports_sse(), "");
10129   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10130   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10131   emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10132 }
10133 
10134 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10135 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
10136   assert(UseAVX >= 2, "");
10137   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10138   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10139   emit_int16(0x58, (0xC0 | encode));
10140 }
10141 
10142 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
10143   assert(VM_Version::supports_avx2(), "");
10144   assert(dst != xnoreg, "sanity");
10145   InstructionMark im(this);
10146   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10147   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10148   // swap src<->dst for encoding
10149   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10150   emit_int8(0x58);
10151   emit_operand(dst, src);
10152 }
10153 
10154 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10155 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
10156   assert(VM_Version::supports_avx2(), "");
10157   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10158   attributes.set_rex_vex_w_reverted();
10159   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10160   emit_int16(0x59, (0xC0 | encode));
10161 }
10162 
10163 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
10164   assert(VM_Version::supports_avx2(), "");
10165   assert(dst != xnoreg, "sanity");
10166   InstructionMark im(this);
10167   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10168   attributes.set_rex_vex_w_reverted();
10169   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10170   // swap src<->dst for encoding
10171   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10172   emit_int8(0x59);
10173   emit_operand(dst, src);
10174 }
10175 
10176 void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) {
10177   assert(vector_len != Assembler::AVX_128bit, "");
10178   assert(VM_Version::supports_evex(), "");
10179   assert(dst != xnoreg, "sanity");
10180   InstructionMark im(this);
10181   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10182   attributes.set_rex_vex_w_reverted();
10183   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10184   // swap src<->dst for encoding
10185   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10186   emit_int8(0x5A);
10187   emit_operand(dst, src);
10188 }
10189 
10190 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
10191   assert(vector_len != Assembler::AVX_128bit, "");
10192   assert(VM_Version::supports_avx512dq(), "");
10193   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10194   attributes.set_rex_vex_w_reverted();
10195   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10196   emit_int16(0x5A, (0xC0 | encode));
10197 }
10198 
10199 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
10200   assert(vector_len != Assembler::AVX_128bit, "");
10201   assert(VM_Version::supports_avx512dq(), "");
10202   assert(dst != xnoreg, "sanity");
10203   InstructionMark im(this);
10204   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10205   attributes.set_rex_vex_w_reverted();
10206   attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
10207   // swap src<->dst for encoding
10208   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10209   emit_int8(0x5A);
10210   emit_operand(dst, src);
10211 }
10212 
10213 // scalar single/double precision replicate
10214 
10215 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
10216 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
10217   assert(VM_Version::supports_avx2(), "");
10218   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10219   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10220   emit_int16(0x18, (0xC0 | encode));
10221 }
10222 
10223 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
10224   assert(VM_Version::supports_avx(), "");
10225   assert(dst != xnoreg, "sanity");
10226   InstructionMark im(this);
10227   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10228   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10229   // swap src<->dst for encoding
10230   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10231   emit_int8(0x18);
10232   emit_operand(dst, src);
10233 }
10234 
10235 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
10236 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
10237   assert(VM_Version::supports_avx2(), "");
10238   assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10239   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10240   attributes.set_rex_vex_w_reverted();
10241   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10242   emit_int16(0x19, (0xC0 | encode));
10243 }
10244 
10245 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
10246   assert(VM_Version::supports_avx(), "");
10247   assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10248   assert(dst != xnoreg, "sanity");
10249   InstructionMark im(this);
10250   InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10251   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10252   attributes.set_rex_vex_w_reverted();
10253   // swap src<->dst for encoding
10254   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10255   emit_int8(0x19);
10256   emit_operand(dst, src);
10257 }
10258 
10259 void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
10260   assert(VM_Version::supports_avx(), "");
10261   assert(vector_len == AVX_256bit, "");
10262   assert(dst != xnoreg, "sanity");
10263   InstructionMark im(this);
10264   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10265   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10266   // swap src<->dst for encoding
10267   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10268   emit_int8(0x1A);
10269   emit_operand(dst, src);
10270 }
10271 
10272 // gpr source broadcast forms
10273 
10274 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10275 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
10276   assert(VM_Version::supports_avx512bw(), "");
10277   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10278   attributes.set_is_evex_instruction();
10279   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10280   emit_int16(0x7A, (0xC0 | encode));
10281 }
10282 
10283 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10284 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
10285   assert(VM_Version::supports_avx512bw(), "");
10286   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10287   attributes.set_is_evex_instruction();
10288   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10289   emit_int16(0x7B, (0xC0 | encode));
10290 }
10291 
10292 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10293 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
10294   assert(VM_Version::supports_evex(), "");
10295   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10296   attributes.set_is_evex_instruction();
10297   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10298   emit_int16(0x7C, (0xC0 | encode));
10299 }
10300 
10301 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10302 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
10303   assert(VM_Version::supports_evex(), "");
10304   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10305   attributes.set_is_evex_instruction();
10306   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10307   emit_int16(0x7C, (0xC0 | encode));
10308 }
10309 
10310 void Assembler::vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10311   assert(VM_Version::supports_avx2(), "");
10312   assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10313   assert(dst != xnoreg, "sanity");
10314   assert(src.isxmmindex(),"expected to be xmm index");
10315   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10316   InstructionMark im(this);
10317   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10318   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10319   emit_int8((unsigned char)0x90);
10320   emit_operand(dst, src);
10321 }
10322 
10323 void Assembler::vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10324   assert(VM_Version::supports_avx2(), "");
10325   assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10326   assert(dst != xnoreg, "sanity");
10327   assert(src.isxmmindex(),"expected to be xmm index");
10328   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10329   InstructionMark im(this);
10330   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10331   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10332   emit_int8((unsigned char)0x90);
10333   emit_operand(dst, src);
10334 }
10335 
10336 void Assembler::vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10337   assert(VM_Version::supports_avx2(), "");
10338   assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10339   assert(dst != xnoreg, "sanity");
10340   assert(src.isxmmindex(),"expected to be xmm index");
10341   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10342   InstructionMark im(this);
10343   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10344   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10345   emit_int8((unsigned char)0x92);
10346   emit_operand(dst, src);
10347 }
10348 
10349 void Assembler::vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10350   assert(VM_Version::supports_avx2(), "");
10351   assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10352   assert(dst != xnoreg, "sanity");
10353   assert(src.isxmmindex(),"expected to be xmm index");
10354   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10355   InstructionMark im(this);
10356   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
10357   vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10358   emit_int8((unsigned char)0x92);
10359   emit_operand(dst, src);
10360 }
10361 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10362   assert(VM_Version::supports_evex(), "");
10363   assert(dst != xnoreg, "sanity");
10364   assert(src.isxmmindex(),"expected to be xmm index");
10365   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10366   assert(mask != k0, "instruction will #UD if mask is in k0");
10367   InstructionMark im(this);
10368   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10369   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10370   attributes.reset_is_clear_context();
10371   attributes.set_embedded_opmask_register_specifier(mask);
10372   attributes.set_is_evex_instruction();
10373   // swap src<->dst for encoding
10374   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10375   emit_int8((unsigned char)0x90);
10376   emit_operand(dst, src);
10377 }
10378 
10379 void Assembler::evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10380   assert(VM_Version::supports_evex(), "");
10381   assert(dst != xnoreg, "sanity");
10382   assert(src.isxmmindex(),"expected to be xmm index");
10383   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10384   assert(mask != k0, "instruction will #UD if mask is in k0");
10385   InstructionMark im(this);
10386   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10387   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10388   attributes.reset_is_clear_context();
10389   attributes.set_embedded_opmask_register_specifier(mask);
10390   attributes.set_is_evex_instruction();
10391   // swap src<->dst for encoding
10392   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10393   emit_int8((unsigned char)0x90);
10394   emit_operand(dst, src);
10395 }
10396 
10397 void Assembler::evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10398   assert(VM_Version::supports_evex(), "");
10399   assert(dst != xnoreg, "sanity");
10400   assert(src.isxmmindex(),"expected to be xmm index");
10401   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10402   assert(mask != k0, "instruction will #UD if mask is in k0");
10403   InstructionMark im(this);
10404   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10405   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10406   attributes.reset_is_clear_context();
10407   attributes.set_embedded_opmask_register_specifier(mask);
10408   attributes.set_is_evex_instruction();
10409   // swap src<->dst for encoding
10410   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10411   emit_int8((unsigned char)0x92);
10412   emit_operand(dst, src);
10413 }
10414 
10415 void Assembler::evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10416   assert(VM_Version::supports_evex(), "");
10417   assert(dst != xnoreg, "sanity");
10418   assert(src.isxmmindex(),"expected to be xmm index");
10419   assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10420   assert(mask != k0, "instruction will #UD if mask is in k0");
10421   InstructionMark im(this);
10422   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10423   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10424   attributes.reset_is_clear_context();
10425   attributes.set_embedded_opmask_register_specifier(mask);
10426   attributes.set_is_evex_instruction();
10427   // swap src<->dst for encoding
10428   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10429   emit_int8((unsigned char)0x92);
10430   emit_operand(dst, src);
10431 }
10432 
10433 void Assembler::evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10434   assert(VM_Version::supports_evex(), "");
10435   assert(mask != k0, "instruction will #UD if mask is in k0");
10436   InstructionMark im(this);
10437   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10438   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10439   attributes.reset_is_clear_context();
10440   attributes.set_embedded_opmask_register_specifier(mask);
10441   attributes.set_is_evex_instruction();
10442   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10443   emit_int8((unsigned char)0xA0);
10444   emit_operand(src, dst);
10445 }
10446 
10447 void Assembler::evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10448   assert(VM_Version::supports_evex(), "");
10449   assert(mask != k0, "instruction will #UD if mask is in k0");
10450   InstructionMark im(this);
10451   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10452   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10453   attributes.reset_is_clear_context();
10454   attributes.set_embedded_opmask_register_specifier(mask);
10455   attributes.set_is_evex_instruction();
10456   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10457   emit_int8((unsigned char)0xA0);
10458   emit_operand(src, dst);
10459 }
10460 
10461 void Assembler::evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10462   assert(VM_Version::supports_evex(), "");
10463   assert(mask != k0, "instruction will #UD if mask is in k0");
10464   InstructionMark im(this);
10465   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10466   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10467   attributes.reset_is_clear_context();
10468   attributes.set_embedded_opmask_register_specifier(mask);
10469   attributes.set_is_evex_instruction();
10470   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10471   emit_int8((unsigned char)0xA2);
10472   emit_operand(src, dst);
10473 }
10474 
10475 void Assembler::evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10476   assert(VM_Version::supports_evex(), "");
10477   assert(mask != k0, "instruction will #UD if mask is in k0");
10478   InstructionMark im(this);
10479   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10480   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10481   attributes.reset_is_clear_context();
10482   attributes.set_embedded_opmask_register_specifier(mask);
10483   attributes.set_is_evex_instruction();
10484   vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10485   emit_int8((unsigned char)0xA2);
10486   emit_operand(src, dst);
10487 }
10488 // Carry-Less Multiplication Quadword
10489 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
10490   assert(VM_Version::supports_clmul(), "");
10491   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10492   int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10493   emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10494 }
10495 
10496 // Carry-Less Multiplication Quadword
10497 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
10498   assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
10499   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10500   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10501   emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10502 }
10503 
10504 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
10505   assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
10506   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10507   attributes.set_is_evex_instruction();
10508   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10509   emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10510 }
10511 
10512 void Assembler::vzeroupper_uncached() {
10513   if (VM_Version::supports_vzeroupper()) {
10514     InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10515     (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
10516     emit_int8(0x77);
10517   }
10518 }
10519 
10520 void Assembler::vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8) {
10521   // Encoding: EVEX.LIG.66.0F3A.W0 67 /r ib
10522   assert(VM_Version::supports_evex(), "");
10523   assert(VM_Version::supports_avx512dq(), "");
10524   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10525   attributes.set_is_evex_instruction();
10526   int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10527   emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10528 }
10529 
10530 void Assembler::vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8) {
10531   // Encoding: EVEX.LIG.66.0F3A.W1 67 /r ib
10532   assert(VM_Version::supports_evex(), "");
10533   assert(VM_Version::supports_avx512dq(), "");
10534   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10535   attributes.set_is_evex_instruction();
10536   int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10537   emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10538 }
10539 
10540 void Assembler::fld_x(Address adr) {
10541   InstructionMark im(this);
10542   emit_int8((unsigned char)0xDB);
10543   emit_operand32(rbp, adr);
10544 }
10545 
10546 void Assembler::fstp_x(Address adr) {
10547   InstructionMark im(this);
10548   emit_int8((unsigned char)0xDB);
10549   emit_operand32(rdi, adr);
10550 }
10551 
10552 void Assembler::emit_operand32(Register reg, Address adr) {
10553   assert(reg->encoding() < 8, "no extended registers");
10554   assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
10555   emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
10556                adr._rspec);
10557 }
10558 
10559 #ifndef _LP64
10560 // 32bit only pieces of the assembler
10561 
10562 void Assembler::emms() {
10563   NOT_LP64(assert(VM_Version::supports_mmx(), ""));
10564   emit_int16(0x0F, 0x77);
10565 }
10566 
10567 void Assembler::vzeroupper() {
10568   vzeroupper_uncached();
10569 }
10570 
10571 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
10572   // NO PREFIX AS NEVER 64BIT
10573   InstructionMark im(this);
10574   emit_int16((unsigned char)0x81, (0xF8 | src1->encoding()));
10575   emit_data(imm32, rspec, 0);
10576 }
10577 
10578 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
10579   // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
10580   InstructionMark im(this);
10581   emit_int8((unsigned char)0x81);
10582   emit_operand(rdi, src1);
10583   emit_data(imm32, rspec, 0);
10584 }
10585 
10586 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
10587 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
10588 // into rdx:rax.  The ZF is set if the compared values were equal, and cleared otherwise.
10589 void Assembler::cmpxchg8(Address adr) {
10590   InstructionMark im(this);
10591   emit_int16(0x0F, (unsigned char)0xC7);
10592   emit_operand(rcx, adr);
10593 }
10594 
10595 void Assembler::decl(Register dst) {
10596   // Don't use it directly. Use MacroAssembler::decrementl() instead.
10597  emit_int8(0x48 | dst->encoding());
10598 }
10599 
10600 // 64bit doesn't use the x87
10601 
10602 void Assembler::emit_farith(int b1, int b2, int i) {
10603   assert(isByte(b1) && isByte(b2), "wrong opcode");
10604   assert(0 <= i &&  i < 8, "illegal stack offset");
10605   emit_int16(b1, b2 + i);
10606 }
10607 
10608 void Assembler::fabs() {
10609   emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
10610 }
10611 
10612 void Assembler::fadd(int i) {
10613   emit_farith(0xD8, 0xC0, i);
10614 }
10615 
10616 void Assembler::fadd_d(Address src) {
10617   InstructionMark im(this);
10618   emit_int8((unsigned char)0xDC);
10619   emit_operand32(rax, src);
10620 }
10621 
10622 void Assembler::fadd_s(Address src) {
10623   InstructionMark im(this);
10624   emit_int8((unsigned char)0xD8);
10625   emit_operand32(rax, src);
10626 }
10627 
10628 void Assembler::fadda(int i) {
10629   emit_farith(0xDC, 0xC0, i);
10630 }
10631 
10632 void Assembler::faddp(int i) {
10633   emit_farith(0xDE, 0xC0, i);
10634 }
10635 
10636 void Assembler::fchs() {
10637   emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
10638 }
10639 
10640 void Assembler::fcom(int i) {
10641   emit_farith(0xD8, 0xD0, i);
10642 }
10643 
10644 void Assembler::fcomp(int i) {
10645   emit_farith(0xD8, 0xD8, i);
10646 }
10647 
10648 void Assembler::fcomp_d(Address src) {
10649   InstructionMark im(this);
10650   emit_int8((unsigned char)0xDC);
10651   emit_operand32(rbx, src);
10652 }
10653 
10654 void Assembler::fcomp_s(Address src) {
10655   InstructionMark im(this);
10656   emit_int8((unsigned char)0xD8);
10657   emit_operand32(rbx, src);
10658 }
10659 
10660 void Assembler::fcompp() {
10661   emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
10662 }
10663 
10664 void Assembler::fcos() {
10665   emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
10666 }
10667 
10668 void Assembler::fdecstp() {
10669   emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
10670 }
10671 
10672 void Assembler::fdiv(int i) {
10673   emit_farith(0xD8, 0xF0, i);
10674 }
10675 
10676 void Assembler::fdiv_d(Address src) {
10677   InstructionMark im(this);
10678   emit_int8((unsigned char)0xDC);
10679   emit_operand32(rsi, src);
10680 }
10681 
10682 void Assembler::fdiv_s(Address src) {
10683   InstructionMark im(this);
10684   emit_int8((unsigned char)0xD8);
10685   emit_operand32(rsi, src);
10686 }
10687 
10688 void Assembler::fdiva(int i) {
10689   emit_farith(0xDC, 0xF8, i);
10690 }
10691 
10692 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
10693 //       is erroneous for some of the floating-point instructions below.
10694 
10695 void Assembler::fdivp(int i) {
10696   emit_farith(0xDE, 0xF8, i);                    // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
10697 }
10698 
10699 void Assembler::fdivr(int i) {
10700   emit_farith(0xD8, 0xF8, i);
10701 }
10702 
10703 void Assembler::fdivr_d(Address src) {
10704   InstructionMark im(this);
10705   emit_int8((unsigned char)0xDC);
10706   emit_operand32(rdi, src);
10707 }
10708 
10709 void Assembler::fdivr_s(Address src) {
10710   InstructionMark im(this);
10711   emit_int8((unsigned char)0xD8);
10712   emit_operand32(rdi, src);
10713 }
10714 
10715 void Assembler::fdivra(int i) {
10716   emit_farith(0xDC, 0xF0, i);
10717 }
10718 
10719 void Assembler::fdivrp(int i) {
10720   emit_farith(0xDE, 0xF0, i);                    // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
10721 }
10722 
10723 void Assembler::ffree(int i) {
10724   emit_farith(0xDD, 0xC0, i);
10725 }
10726 
10727 void Assembler::fild_d(Address adr) {
10728   InstructionMark im(this);
10729   emit_int8((unsigned char)0xDF);
10730   emit_operand32(rbp, adr);
10731 }
10732 
10733 void Assembler::fild_s(Address adr) {
10734   InstructionMark im(this);
10735   emit_int8((unsigned char)0xDB);
10736   emit_operand32(rax, adr);
10737 }
10738 
10739 void Assembler::fincstp() {
10740   emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
10741 }
10742 
10743 void Assembler::finit() {
10744   emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
10745 }
10746 
10747 void Assembler::fist_s(Address adr) {
10748   InstructionMark im(this);
10749   emit_int8((unsigned char)0xDB);
10750   emit_operand32(rdx, adr);
10751 }
10752 
10753 void Assembler::fistp_d(Address adr) {
10754   InstructionMark im(this);
10755   emit_int8((unsigned char)0xDF);
10756   emit_operand32(rdi, adr);
10757 }
10758 
10759 void Assembler::fistp_s(Address adr) {
10760   InstructionMark im(this);
10761   emit_int8((unsigned char)0xDB);
10762   emit_operand32(rbx, adr);
10763 }
10764 
10765 void Assembler::fld1() {
10766   emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
10767 }
10768 
10769 void Assembler::fld_d(Address adr) {
10770   InstructionMark im(this);
10771   emit_int8((unsigned char)0xDD);
10772   emit_operand32(rax, adr);
10773 }
10774 
10775 void Assembler::fld_s(Address adr) {
10776   InstructionMark im(this);
10777   emit_int8((unsigned char)0xD9);
10778   emit_operand32(rax, adr);
10779 }
10780 
10781 
10782 void Assembler::fld_s(int index) {
10783   emit_farith(0xD9, 0xC0, index);
10784 }
10785 
10786 void Assembler::fldcw(Address src) {
10787   InstructionMark im(this);
10788   emit_int8((unsigned char)0xD9);
10789   emit_operand32(rbp, src);
10790 }
10791 
10792 void Assembler::fldenv(Address src) {
10793   InstructionMark im(this);
10794   emit_int8((unsigned char)0xD9);
10795   emit_operand32(rsp, src);
10796 }
10797 
10798 void Assembler::fldlg2() {
10799   emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
10800 }
10801 
10802 void Assembler::fldln2() {
10803   emit_int16((unsigned char)0xD9, (unsigned char)0xED);
10804 }
10805 
10806 void Assembler::fldz() {
10807   emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
10808 }
10809 
10810 void Assembler::flog() {
10811   fldln2();
10812   fxch();
10813   fyl2x();
10814 }
10815 
10816 void Assembler::flog10() {
10817   fldlg2();
10818   fxch();
10819   fyl2x();
10820 }
10821 
10822 void Assembler::fmul(int i) {
10823   emit_farith(0xD8, 0xC8, i);
10824 }
10825 
10826 void Assembler::fmul_d(Address src) {
10827   InstructionMark im(this);
10828   emit_int8((unsigned char)0xDC);
10829   emit_operand32(rcx, src);
10830 }
10831 
10832 void Assembler::fmul_s(Address src) {
10833   InstructionMark im(this);
10834   emit_int8((unsigned char)0xD8);
10835   emit_operand32(rcx, src);
10836 }
10837 
10838 void Assembler::fmula(int i) {
10839   emit_farith(0xDC, 0xC8, i);
10840 }
10841 
10842 void Assembler::fmulp(int i) {
10843   emit_farith(0xDE, 0xC8, i);
10844 }
10845 
10846 void Assembler::fnsave(Address dst) {
10847   InstructionMark im(this);
10848   emit_int8((unsigned char)0xDD);
10849   emit_operand32(rsi, dst);
10850 }
10851 
10852 void Assembler::fnstcw(Address src) {
10853   InstructionMark im(this);
10854   emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
10855   emit_operand32(rdi, src);
10856 }
10857 
10858 void Assembler::fnstsw_ax() {
10859   emit_int16((unsigned char)0xDF, (unsigned char)0xE0);
10860 }
10861 
10862 void Assembler::fprem() {
10863   emit_int16((unsigned char)0xD9, (unsigned char)0xF8);
10864 }
10865 
10866 void Assembler::fprem1() {
10867   emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
10868 }
10869 
10870 void Assembler::frstor(Address src) {
10871   InstructionMark im(this);
10872   emit_int8((unsigned char)0xDD);
10873   emit_operand32(rsp, src);
10874 }
10875 
10876 void Assembler::fsin() {
10877   emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
10878 }
10879 
10880 void Assembler::fsqrt() {
10881   emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
10882 }
10883 
10884 void Assembler::fst_d(Address adr) {
10885   InstructionMark im(this);
10886   emit_int8((unsigned char)0xDD);
10887   emit_operand32(rdx, adr);
10888 }
10889 
10890 void Assembler::fst_s(Address adr) {
10891   InstructionMark im(this);
10892   emit_int8((unsigned char)0xD9);
10893   emit_operand32(rdx, adr);
10894 }
10895 
10896 void Assembler::fstp_d(Address adr) {
10897   InstructionMark im(this);
10898   emit_int8((unsigned char)0xDD);
10899   emit_operand32(rbx, adr);
10900 }
10901 
10902 void Assembler::fstp_d(int index) {
10903   emit_farith(0xDD, 0xD8, index);
10904 }
10905 
10906 void Assembler::fstp_s(Address adr) {
10907   InstructionMark im(this);
10908   emit_int8((unsigned char)0xD9);
10909   emit_operand32(rbx, adr);
10910 }
10911 
10912 void Assembler::fsub(int i) {
10913   emit_farith(0xD8, 0xE0, i);
10914 }
10915 
10916 void Assembler::fsub_d(Address src) {
10917   InstructionMark im(this);
10918   emit_int8((unsigned char)0xDC);
10919   emit_operand32(rsp, src);
10920 }
10921 
10922 void Assembler::fsub_s(Address src) {
10923   InstructionMark im(this);
10924   emit_int8((unsigned char)0xD8);
10925   emit_operand32(rsp, src);
10926 }
10927 
10928 void Assembler::fsuba(int i) {
10929   emit_farith(0xDC, 0xE8, i);
10930 }
10931 
10932 void Assembler::fsubp(int i) {
10933   emit_farith(0xDE, 0xE8, i);                    // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
10934 }
10935 
10936 void Assembler::fsubr(int i) {
10937   emit_farith(0xD8, 0xE8, i);
10938 }
10939 
10940 void Assembler::fsubr_d(Address src) {
10941   InstructionMark im(this);
10942   emit_int8((unsigned char)0xDC);
10943   emit_operand32(rbp, src);
10944 }
10945 
10946 void Assembler::fsubr_s(Address src) {
10947   InstructionMark im(this);
10948   emit_int8((unsigned char)0xD8);
10949   emit_operand32(rbp, src);
10950 }
10951 
10952 void Assembler::fsubra(int i) {
10953   emit_farith(0xDC, 0xE0, i);
10954 }
10955 
10956 void Assembler::fsubrp(int i) {
10957   emit_farith(0xDE, 0xE0, i);                    // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
10958 }
10959 
10960 void Assembler::ftan() {
10961   emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
10962 }
10963 
10964 void Assembler::ftst() {
10965   emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
10966 }
10967 
10968 void Assembler::fucomi(int i) {
10969   // make sure the instruction is supported (introduced for P6, together with cmov)
10970   guarantee(VM_Version::supports_cmov(), "illegal instruction");
10971   emit_farith(0xDB, 0xE8, i);
10972 }
10973 
10974 void Assembler::fucomip(int i) {
10975   // make sure the instruction is supported (introduced for P6, together with cmov)
10976   guarantee(VM_Version::supports_cmov(), "illegal instruction");
10977   emit_farith(0xDF, 0xE8, i);
10978 }
10979 
10980 void Assembler::fwait() {
10981   emit_int8((unsigned char)0x9B);
10982 }
10983 
10984 void Assembler::fxch(int i) {
10985   emit_farith(0xD9, 0xC8, i);
10986 }
10987 
10988 void Assembler::fyl2x() {
10989   emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
10990 }
10991 
10992 void Assembler::frndint() {
10993   emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
10994 }
10995 
10996 void Assembler::f2xm1() {
10997   emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
10998 }
10999 
11000 void Assembler::fldl2e() {
11001   emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
11002 }
11003 #endif // !_LP64
11004 
11005 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
11006 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
11007 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
11008 static int simd_opc[4] = { 0,    0, 0x38, 0x3A };
11009 
11010 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
11011 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11012   if (pre > 0) {
11013     emit_int8(simd_pre[pre]);
11014   }
11015   if (rex_w) {
11016     prefixq(adr, xreg);
11017   } else {
11018     prefix(adr, xreg);
11019   }
11020   if (opc > 0) {
11021     emit_int8(0x0F);
11022     int opc2 = simd_opc[opc];
11023     if (opc2 > 0) {
11024       emit_int8(opc2);
11025     }
11026   }
11027 }
11028 
11029 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11030   if (pre > 0) {
11031     emit_int8(simd_pre[pre]);
11032   }
11033   int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
11034   if (opc > 0) {
11035     emit_int8(0x0F);
11036     int opc2 = simd_opc[opc];
11037     if (opc2 > 0) {
11038       emit_int8(opc2);
11039     }
11040   }
11041   return encode;
11042 }
11043 
11044 
11045 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
11046   int vector_len = _attributes->get_vector_len();
11047   bool vex_w = _attributes->is_rex_vex_w();
11048   if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
11049     int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
11050     byte1 = (~byte1) & 0xE0;
11051     byte1 |= opc;
11052 
11053     int byte2 = ((~nds_enc) & 0xf) << 3;
11054     byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
11055 
11056     emit_int24((unsigned char)VEX_3bytes, byte1, byte2);
11057   } else {
11058     int byte1 = vex_r ? VEX_R : 0;
11059     byte1 = (~byte1) & 0x80;
11060     byte1 |= ((~nds_enc) & 0xf) << 3;
11061     byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
11062     emit_int16((unsigned char)VEX_2bytes, byte1);
11063   }
11064 }
11065 
11066 // This is a 4 byte encoding
11067 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
11068   // EVEX 0x62 prefix
11069   // byte1 = EVEX_4bytes;
11070 
11071   bool vex_w = _attributes->is_rex_vex_w();
11072   int evex_encoding = (vex_w ? VEX_W : 0);
11073   // EVEX.b is not currently used for broadcast of single element or data rounding modes
11074   _attributes->set_evex_encoding(evex_encoding);
11075 
11076   // P0: byte 2, initialized to RXBR`00mm
11077   // instead of not'd
11078   int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
11079   byte2 = (~byte2) & 0xF0;
11080   // confine opc opcode extensions in mm bits to lower two bits
11081   // of form {0F, 0F_38, 0F_3A}
11082   byte2 |= opc;
11083 
11084   // P1: byte 3 as Wvvvv1pp
11085   int byte3 = ((~nds_enc) & 0xf) << 3;
11086   // p[10] is always 1
11087   byte3 |= EVEX_F;
11088   byte3 |= (vex_w & 1) << 7;
11089   // confine pre opcode extensions in pp bits to lower two bits
11090   // of form {66, F3, F2}
11091   byte3 |= pre;
11092 
11093   // P2: byte 4 as zL'Lbv'aaa
11094   // kregs are implemented in the low 3 bits as aaa
11095   int byte4 = (_attributes->is_no_reg_mask()) ?
11096               0 :
11097               _attributes->get_embedded_opmask_register_specifier();
11098   // EVEX.v` for extending EVEX.vvvv or VIDX
11099   byte4 |= (evex_v ? 0: EVEX_V);
11100   // third EXEC.b for broadcast actions
11101   byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
11102   // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
11103   byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
11104   // last is EVEX.z for zero/merge actions
11105   if (_attributes->is_no_reg_mask() == false &&
11106       _attributes->get_embedded_opmask_register_specifier() != 0) {
11107     byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
11108   }
11109 
11110   emit_int32(EVEX_4bytes, byte2, byte3, byte4);
11111 }
11112 
11113 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11114   bool vex_r = (xreg_enc & 8) == 8;
11115   bool vex_b = adr.base_needs_rex();
11116   bool vex_x;
11117   if (adr.isxmmindex()) {
11118     vex_x = adr.xmmindex_needs_rex();
11119   } else {
11120     vex_x = adr.index_needs_rex();
11121   }
11122   set_attributes(attributes);
11123   attributes->set_current_assembler(this);
11124 
11125   // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11126   // is allowed in legacy mode and has resources which will fit in it.
11127   // Pure EVEX instructions will have is_evex_instruction set in their definition.
11128   if (!attributes->is_legacy_mode()) {
11129     if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11130       if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
11131           attributes->set_is_legacy_mode();
11132       }
11133     }
11134   }
11135 
11136   if (UseAVX > 2) {
11137     assert(((!attributes->uses_vl()) ||
11138             (attributes->get_vector_len() == AVX_512bit) ||
11139             (!_legacy_mode_vl) ||
11140             (attributes->is_legacy_mode())),"XMM register should be 0-15");
11141     assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11142   }
11143 
11144   clear_managed();
11145   if (UseAVX > 2 && !attributes->is_legacy_mode())
11146   {
11147     bool evex_r = (xreg_enc >= 16);
11148     bool evex_v;
11149     // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
11150     if (adr.isxmmindex())  {
11151       evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
11152     } else {
11153       evex_v = (nds_enc >= 16);
11154     }
11155     attributes->set_is_evex_instruction();
11156     evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11157   } else {
11158     if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11159       attributes->set_rex_vex_w(false);
11160     }
11161     vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11162   }
11163 }
11164 
11165 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11166   bool vex_r = (dst_enc & 8) == 8;
11167   bool vex_b = (src_enc & 8) == 8;
11168   bool vex_x = false;
11169   set_attributes(attributes);
11170   attributes->set_current_assembler(this);
11171 
11172   // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11173   // is allowed in legacy mode and has resources which will fit in it.
11174   // Pure EVEX instructions will have is_evex_instruction set in their definition.
11175   if (!attributes->is_legacy_mode()) {
11176     if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11177       if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
11178           (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
11179           attributes->set_is_legacy_mode();
11180       }
11181     }
11182   }
11183 
11184   if (UseAVX > 2) {
11185     // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
11186     // Instruction with uses_vl true are vector instructions
11187     // All the vector instructions with AVX_512bit length can have legacy_mode as false
11188     // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
11189     // Rest all should have legacy_mode set as true
11190     assert(((!attributes->uses_vl()) ||
11191             (attributes->get_vector_len() == AVX_512bit) ||
11192             (!_legacy_mode_vl) ||
11193             (attributes->is_legacy_mode())),"XMM register should be 0-15");
11194     // Instruction with legacy_mode true should have dst, nds and src < 15
11195     assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11196   }
11197 
11198   clear_managed();
11199   if (UseAVX > 2 && !attributes->is_legacy_mode())
11200   {
11201     bool evex_r = (dst_enc >= 16);
11202     bool evex_v = (nds_enc >= 16);
11203     // can use vex_x as bank extender on rm encoding
11204     vex_x = (src_enc >= 16);
11205     attributes->set_is_evex_instruction();
11206     evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11207   } else {
11208     if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11209       attributes->set_rex_vex_w(false);
11210     }
11211     vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11212   }
11213 
11214   // return modrm byte components for operands
11215   return (((dst_enc & 7) << 3) | (src_enc & 7));
11216 }
11217 
11218 
11219 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
11220                             VexOpcode opc, InstructionAttr *attributes) {
11221   if (UseAVX > 0) {
11222     int xreg_enc = xreg->encoding();
11223     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11224     vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
11225   } else {
11226     assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
11227     rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
11228   }
11229 }
11230 
11231 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
11232                                       VexOpcode opc, InstructionAttr *attributes) {
11233   int dst_enc = dst->encoding();
11234   int src_enc = src->encoding();
11235   if (UseAVX > 0) {
11236     int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11237     return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
11238   } else {
11239     assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
11240     return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
11241   }
11242 }
11243 
11244 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11245   assert(VM_Version::supports_avx(), "");
11246   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11247   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11248   emit_int16(0x5F, (0xC0 | encode));
11249 }
11250 
11251 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11252   assert(VM_Version::supports_avx(), "");
11253   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11254   attributes.set_rex_vex_w_reverted();
11255   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11256   emit_int16(0x5F, (0xC0 | encode));
11257 }
11258 
11259 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11260   assert(VM_Version::supports_avx(), "");
11261   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11262   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11263   emit_int16(0x5D, (0xC0 | encode));
11264 }
11265 
11266 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11267   assert(VM_Version::supports_avx(), "");
11268   InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11269   attributes.set_rex_vex_w_reverted();
11270   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11271   emit_int16(0x5D, (0xC0 | encode));
11272 }
11273 
11274 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
11275   assert(VM_Version::supports_avx(), "");
11276   assert(vector_len <= AVX_256bit, "");
11277   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11278   int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11279   emit_int24((unsigned char)0xC2, (0xC0 | encode), (0xF & cop));
11280 }
11281 
11282 void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11283   assert(VM_Version::supports_avx(), "");
11284   assert(vector_len <= AVX_256bit, "");
11285   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11286   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11287   int src2_enc = src2->encoding();
11288   emit_int24(0x4C, (0xC0 | encode), (0xF0 & src2_enc << 4));
11289 }
11290 
11291 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11292   assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11293   assert(vector_len <= AVX_256bit, "");
11294   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11295   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11296   int src2_enc = src2->encoding();
11297   emit_int24(0x4B, (0xC0 | encode), (0xF0 & src2_enc << 4));
11298 }
11299 
11300 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11301   assert(VM_Version::supports_avx2(), "");
11302   assert(vector_len <= AVX_256bit, "");
11303   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11304   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11305   emit_int24(0x02, (0xC0 | encode), (unsigned char)imm8);
11306 }
11307 
11308 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
11309   assert(VM_Version::supports_avx(), "");
11310   assert(vector_len <= AVX_256bit, "");
11311   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11312   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11313   emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison);
11314 }
11315 
11316 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11317                         ComparisonPredicateFP comparison, int vector_len) {
11318   assert(VM_Version::supports_evex(), "");
11319   // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
11320   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11321   attributes.set_is_evex_instruction();
11322   attributes.set_embedded_opmask_register_specifier(mask);
11323   attributes.reset_is_clear_context();
11324   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11325   emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11326 }
11327 
11328 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11329                         ComparisonPredicateFP comparison, int vector_len) {
11330   assert(VM_Version::supports_evex(), "");
11331   // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
11332   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11333   attributes.set_is_evex_instruction();
11334   attributes.set_embedded_opmask_register_specifier(mask);
11335   attributes.reset_is_clear_context();
11336   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11337   emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11338 }
11339 
11340 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
11341   assert(VM_Version::supports_sse4_1(), "");
11342   assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11343   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11344   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11345   emit_int16(0x14, (0xC0 | encode));
11346 }
11347 
11348 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
11349   assert(VM_Version::supports_sse4_1(), "");
11350   assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11351   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11352   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11353   emit_int16(0x15, (0xC0 | encode));
11354 }
11355 
11356 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
11357   assert(VM_Version::supports_sse4_1(), "");
11358   assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11359   InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11360   int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11361   emit_int16(0x10, (0xC0 | encode));
11362 }
11363 
11364 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11365   assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11366   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11367   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11368   int src2_enc = src2->encoding();
11369   emit_int24(0x4A, (0xC0 | encode), (0xF0 & src2_enc << 4));
11370 }
11371 
11372 void Assembler::vblendps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11373   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11374   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11375   emit_int24(0x0C, (0xC0 | encode), imm8);
11376 }
11377 
11378 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11379   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11380   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11381   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11382   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11383   emit_int16(0x64, (0xC0 | encode));
11384 }
11385 
11386 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11387   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11388   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11389   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11390   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11391   emit_int16(0x65, (0xC0 | encode));
11392 }
11393 
11394 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11395   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11396   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11397   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11398   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11399   emit_int16(0x66, (0xC0 | encode));
11400 }
11401 
11402 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11403   assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11404   assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11405   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11406   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11407   emit_int16(0x37, (0xC0 | encode));
11408 }
11409 
11410 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11411                         int comparison, bool is_signed, int vector_len) {
11412   assert(VM_Version::supports_evex(), "");
11413   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11414   // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11415   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11416   attributes.set_is_evex_instruction();
11417   attributes.set_embedded_opmask_register_specifier(mask);
11418   attributes.reset_is_clear_context();
11419   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11420   int opcode = is_signed ? 0x1F : 0x1E;
11421   emit_int24(opcode, (0xC0 | encode), comparison);
11422 }
11423 
11424 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11425                         int comparison, bool is_signed, int vector_len) {
11426   assert(VM_Version::supports_evex(), "");
11427   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11428   // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11429   InstructionMark im(this);
11430   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11431   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11432   attributes.set_is_evex_instruction();
11433   attributes.set_embedded_opmask_register_specifier(mask);
11434   attributes.reset_is_clear_context();
11435   int dst_enc = kdst->encoding();
11436   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11437   int opcode = is_signed ? 0x1F : 0x1E;
11438   emit_int8((unsigned char)opcode);
11439   emit_operand(as_Register(dst_enc), src);
11440   emit_int8((unsigned char)comparison);
11441 }
11442 
11443 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11444                         int comparison, bool is_signed, int vector_len) {
11445   assert(VM_Version::supports_evex(), "");
11446   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11447   // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11448   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11449   attributes.set_is_evex_instruction();
11450   attributes.set_embedded_opmask_register_specifier(mask);
11451   attributes.reset_is_clear_context();
11452   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11453   int opcode = is_signed ? 0x1F : 0x1E;
11454   emit_int24(opcode, (0xC0 | encode), comparison);
11455 }
11456 
11457 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11458                         int comparison, bool is_signed, int vector_len) {
11459   assert(VM_Version::supports_evex(), "");
11460   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11461   // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11462   InstructionMark im(this);
11463   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11464   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11465   attributes.set_is_evex_instruction();
11466   attributes.set_embedded_opmask_register_specifier(mask);
11467   attributes.reset_is_clear_context();
11468   int dst_enc = kdst->encoding();
11469   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11470   int opcode = is_signed ? 0x1F : 0x1E;
11471   emit_int8((unsigned char)opcode);
11472   emit_operand(as_Register(dst_enc), src);
11473   emit_int8((unsigned char)comparison);
11474 }
11475 
11476 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11477                         int comparison, bool is_signed, int vector_len) {
11478   assert(VM_Version::supports_evex(), "");
11479   assert(VM_Version::supports_avx512bw(), "");
11480   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11481   // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11482   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11483   attributes.set_is_evex_instruction();
11484   attributes.set_embedded_opmask_register_specifier(mask);
11485   attributes.reset_is_clear_context();
11486   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11487   int opcode = is_signed ? 0x3F : 0x3E;
11488   emit_int24(opcode, (0xC0 | encode), comparison);
11489 }
11490 
11491 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11492                         int comparison, bool is_signed, int vector_len) {
11493   assert(VM_Version::supports_evex(), "");
11494   assert(VM_Version::supports_avx512bw(), "");
11495   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11496   // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11497   InstructionMark im(this);
11498   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11499   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11500   attributes.set_is_evex_instruction();
11501   attributes.set_embedded_opmask_register_specifier(mask);
11502   attributes.reset_is_clear_context();
11503   int dst_enc = kdst->encoding();
11504   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11505   int opcode = is_signed ? 0x3F : 0x3E;
11506   emit_int8((unsigned char)opcode);
11507   emit_operand(as_Register(dst_enc), src);
11508   emit_int8((unsigned char)comparison);
11509 }
11510 
11511 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11512                         int comparison, bool is_signed, int vector_len) {
11513   assert(VM_Version::supports_evex(), "");
11514   assert(VM_Version::supports_avx512bw(), "");
11515   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11516   // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11517   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11518   attributes.set_is_evex_instruction();
11519   attributes.set_embedded_opmask_register_specifier(mask);
11520   attributes.reset_is_clear_context();
11521   int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11522   int opcode = is_signed ? 0x3F : 0x3E;
11523   emit_int24(opcode, (0xC0 | encode), comparison);
11524 }
11525 
11526 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11527                         int comparison, bool is_signed, int vector_len) {
11528   assert(VM_Version::supports_evex(), "");
11529   assert(VM_Version::supports_avx512bw(), "");
11530   assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11531   // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11532   InstructionMark im(this);
11533   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11534   attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11535   attributes.set_is_evex_instruction();
11536   attributes.set_embedded_opmask_register_specifier(mask);
11537   attributes.reset_is_clear_context();
11538   int dst_enc = kdst->encoding();
11539   vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11540   int opcode = is_signed ? 0x3F : 0x3E;
11541   emit_int8((unsigned char)opcode);
11542   emit_operand(as_Register(dst_enc), src);
11543   emit_int8((unsigned char)comparison);
11544 }
11545 
11546 // Register is a class, but it would be assigned numerical value.
11547 // "0" is assigned for xmm0. Thus we need to ignore -Wnonnull.
11548 PRAGMA_DIAG_PUSH
11549 PRAGMA_NONNULL_IGNORED
11550 void Assembler::evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11551   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11552   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11553   attributes.set_is_evex_instruction();
11554   attributes.set_embedded_opmask_register_specifier(mask);
11555   if (merge) {
11556     attributes.reset_is_clear_context();
11557   }
11558   int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11559   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11560 }
11561 
11562 void Assembler::evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11563   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11564   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11565   attributes.set_is_evex_instruction();
11566   attributes.set_embedded_opmask_register_specifier(mask);
11567   if (merge) {
11568     attributes.reset_is_clear_context();
11569   }
11570   int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11571   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11572 }
11573 PRAGMA_DIAG_POP
11574 
11575 void Assembler::evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11576   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11577   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11578   attributes.set_is_evex_instruction();
11579   attributes.set_embedded_opmask_register_specifier(mask);
11580   if (merge) {
11581     attributes.reset_is_clear_context();
11582   }
11583   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11584   emit_int16(0x14, (0xC0 | encode));
11585 }
11586 
11587 void Assembler::evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11588   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11589   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11590   attributes.set_is_evex_instruction();
11591   attributes.set_embedded_opmask_register_specifier(mask);
11592   if (merge) {
11593     attributes.reset_is_clear_context();
11594   }
11595   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11596   emit_int16(0x14, (0xC0 | encode));
11597 }
11598 
11599 void Assembler::evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11600   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11601   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11602   attributes.set_is_evex_instruction();
11603   attributes.set_embedded_opmask_register_specifier(mask);
11604   if (merge) {
11605     attributes.reset_is_clear_context();
11606   }
11607   int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11608   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11609 }
11610 
11611 void Assembler::evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11612   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11613   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11614   attributes.set_is_evex_instruction();
11615   attributes.set_embedded_opmask_register_specifier(mask);
11616   if (merge) {
11617     attributes.reset_is_clear_context();
11618   }
11619   int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11620   emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11621 }
11622 
11623 void Assembler::evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11624   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11625   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11626   attributes.set_is_evex_instruction();
11627   attributes.set_embedded_opmask_register_specifier(mask);
11628   if (merge) {
11629     attributes.reset_is_clear_context();
11630   }
11631   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11632   emit_int16(0x15, (0xC0 | encode));
11633 }
11634 
11635 void Assembler::evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11636   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11637   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11638   attributes.set_is_evex_instruction();
11639   attributes.set_embedded_opmask_register_specifier(mask);
11640   if (merge) {
11641     attributes.reset_is_clear_context();
11642   }
11643   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11644   emit_int16(0x15, (0xC0 | encode));
11645 }
11646 
11647 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
11648   assert(VM_Version::supports_avx(), "");
11649   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11650   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11651   int mask_enc = mask->encoding();
11652   emit_int24(0x4C, (0xC0 | encode), 0xF0 & mask_enc << 4);
11653 }
11654 
11655 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11656   assert(VM_Version::supports_evex(), "");
11657   // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
11658   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11659   attributes.set_is_evex_instruction();
11660   attributes.set_embedded_opmask_register_specifier(mask);
11661   if (merge) {
11662     attributes.reset_is_clear_context();
11663   }
11664   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11665   emit_int16(0x65, (0xC0 | encode));
11666 }
11667 
11668 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11669   assert(VM_Version::supports_evex(), "");
11670   // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
11671   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11672   attributes.set_is_evex_instruction();
11673   attributes.set_embedded_opmask_register_specifier(mask);
11674   if (merge) {
11675     attributes.reset_is_clear_context();
11676   }
11677   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11678   emit_int16(0x65, (0xC0 | encode));
11679 }
11680 
11681 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11682   assert(VM_Version::supports_evex(), "");
11683   assert(VM_Version::supports_avx512bw(), "");
11684   // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
11685   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11686   attributes.set_is_evex_instruction();
11687   attributes.set_embedded_opmask_register_specifier(mask);
11688   if (merge) {
11689     attributes.reset_is_clear_context();
11690   }
11691   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11692   emit_int16(0x66, (0xC0 | encode));
11693 }
11694 
11695 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11696   assert(VM_Version::supports_evex(), "");
11697   assert(VM_Version::supports_avx512bw(), "");
11698   // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
11699   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11700   attributes.set_is_evex_instruction();
11701   attributes.set_embedded_opmask_register_specifier(mask);
11702   if (merge) {
11703     attributes.reset_is_clear_context();
11704   }
11705   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11706   emit_int16(0x66, (0xC0 | encode));
11707 }
11708 
11709 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11710   assert(VM_Version::supports_evex(), "");
11711   //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
11712   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11713   attributes.set_is_evex_instruction();
11714   attributes.set_embedded_opmask_register_specifier(mask);
11715   if (merge) {
11716     attributes.reset_is_clear_context();
11717   }
11718   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11719   emit_int16(0x64, (0xC0 | encode));
11720 }
11721 
11722 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11723   assert(VM_Version::supports_evex(), "");
11724   //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
11725   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11726   attributes.set_is_evex_instruction();
11727   attributes.set_embedded_opmask_register_specifier(mask);
11728   if (merge) {
11729     attributes.reset_is_clear_context();
11730   }
11731   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11732   emit_int16(0x64, (0xC0 | encode));
11733 }
11734 
11735 void Assembler::bzhiq(Register dst, Register src1, Register src2) {
11736   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11737   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11738   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
11739   emit_int16((unsigned char)0xF5, (0xC0 | encode));
11740 }
11741 
11742 void Assembler::pextl(Register dst, Register src1, Register src2) {
11743   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11744   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11745   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11746   emit_int16((unsigned char)0xF5, (0xC0 | encode));
11747 }
11748 
11749 void Assembler::pdepl(Register dst, Register src1, Register src2) {
11750   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11751   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11752   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11753   emit_int16((unsigned char)0xF5, (0xC0 | encode));
11754 }
11755 
11756 void Assembler::pextq(Register dst, Register src1, Register src2) {
11757   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11758   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11759   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11760   emit_int16((unsigned char)0xF5, (0xC0 | encode));
11761 }
11762 
11763 void Assembler::pdepq(Register dst, Register src1, Register src2) {
11764   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11765   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11766   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11767   emit_int16((unsigned char)0xF5, (0xC0 | encode));
11768 }
11769 
11770 void Assembler::pextl(Register dst, Register src1, Address src2) {
11771   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11772   InstructionMark im(this);
11773   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11774   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11775   emit_int8((unsigned char)0xF5);
11776   emit_operand(dst, src2);
11777 }
11778 
11779 void Assembler::pdepl(Register dst, Register src1, Address src2) {
11780   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11781   InstructionMark im(this);
11782   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11783   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11784   emit_int8((unsigned char)0xF5);
11785   emit_operand(dst, src2);
11786 }
11787 
11788 void Assembler::pextq(Register dst, Register src1, Address src2) {
11789   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11790   InstructionMark im(this);
11791   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11792   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11793   emit_int8((unsigned char)0xF5);
11794   emit_operand(dst, src2);
11795 }
11796 
11797 void Assembler::pdepq(Register dst, Register src1, Address src2) {
11798   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
11799   InstructionMark im(this);
11800   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11801   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11802   emit_int8((unsigned char)0xF5);
11803   emit_operand(dst, src2);
11804 }
11805 
11806 void Assembler::sarxl(Register dst, Register src1, Register src2) {
11807   assert(VM_Version::supports_bmi2(), "");
11808   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11809   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11810   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11811 }
11812 
11813 void Assembler::sarxl(Register dst, Address src1, Register src2) {
11814   assert(VM_Version::supports_bmi2(), "");
11815   InstructionMark im(this);
11816   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11817   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11818   emit_int8((unsigned char)0xF7);
11819   emit_operand(dst, src1);
11820 }
11821 
11822 void Assembler::sarxq(Register dst, Register src1, Register src2) {
11823   assert(VM_Version::supports_bmi2(), "");
11824   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11825   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11826   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11827 }
11828 
11829 void Assembler::sarxq(Register dst, Address src1, Register src2) {
11830   assert(VM_Version::supports_bmi2(), "");
11831   InstructionMark im(this);
11832   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11833   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11834   emit_int8((unsigned char)0xF7);
11835   emit_operand(dst, src1);
11836 }
11837 
11838 void Assembler::shlxl(Register dst, Register src1, Register src2) {
11839   assert(VM_Version::supports_bmi2(), "");
11840   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11841   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11842   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11843 }
11844 
11845 void Assembler::shlxl(Register dst, Address src1, Register src2) {
11846   assert(VM_Version::supports_bmi2(), "");
11847   InstructionMark im(this);
11848   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11849   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11850   emit_int8((unsigned char)0xF7);
11851   emit_operand(dst, src1);
11852 }
11853 
11854 void Assembler::shlxq(Register dst, Register src1, Register src2) {
11855   assert(VM_Version::supports_bmi2(), "");
11856   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11857   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11858   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11859 }
11860 
11861 void Assembler::shlxq(Register dst, Address src1, Register src2) {
11862   assert(VM_Version::supports_bmi2(), "");
11863   InstructionMark im(this);
11864   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11865   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11866   emit_int8((unsigned char)0xF7);
11867   emit_operand(dst, src1);
11868 }
11869 
11870 void Assembler::shrxl(Register dst, Register src1, Register src2) {
11871   assert(VM_Version::supports_bmi2(), "");
11872   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11873   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11874   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11875 }
11876 
11877 void Assembler::shrxl(Register dst, Address src1, Register src2) {
11878   assert(VM_Version::supports_bmi2(), "");
11879   InstructionMark im(this);
11880   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11881   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11882   emit_int8((unsigned char)0xF7);
11883   emit_operand(dst, src1);
11884 }
11885 
11886 void Assembler::shrxq(Register dst, Register src1, Register src2) {
11887   assert(VM_Version::supports_bmi2(), "");
11888   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11889   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11890   emit_int16((unsigned char)0xF7, (0xC0 | encode));
11891 }
11892 
11893 void Assembler::shrxq(Register dst, Address src1, Register src2) {
11894   assert(VM_Version::supports_bmi2(), "");
11895   InstructionMark im(this);
11896   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11897   vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
11898   emit_int8((unsigned char)0xF7);
11899   emit_operand(dst, src1);
11900 }
11901 
11902 void Assembler::evpmovq2m(KRegister dst, XMMRegister src, int vector_len) {
11903   assert(VM_Version::supports_avx512vldq(), "");
11904   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11905   attributes.set_is_evex_instruction();
11906   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11907   emit_int16(0x39, (0xC0 | encode));
11908 }
11909 
11910 void Assembler::evpmovd2m(KRegister dst, XMMRegister src, int vector_len) {
11911   assert(VM_Version::supports_avx512vldq(), "");
11912   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11913   attributes.set_is_evex_instruction();
11914   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11915   emit_int16(0x39, (0xC0 | encode));
11916 }
11917 
11918 void Assembler::evpmovw2m(KRegister dst, XMMRegister src, int vector_len) {
11919   assert(VM_Version::supports_avx512vlbw(), "");
11920   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11921   attributes.set_is_evex_instruction();
11922   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11923   emit_int16(0x29, (0xC0 | encode));
11924 }
11925 
11926 void Assembler::evpmovb2m(KRegister dst, XMMRegister src, int vector_len) {
11927   assert(VM_Version::supports_avx512vlbw(), "");
11928   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11929   attributes.set_is_evex_instruction();
11930   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11931   emit_int16(0x29, (0xC0 | encode));
11932 }
11933 
11934 void Assembler::evpmovm2q(XMMRegister dst, KRegister src, int vector_len) {
11935   assert(VM_Version::supports_avx512vldq(), "");
11936   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11937   attributes.set_is_evex_instruction();
11938   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11939   emit_int16(0x38, (0xC0 | encode));
11940 }
11941 
11942 void Assembler::evpmovm2d(XMMRegister dst, KRegister src, int vector_len) {
11943   assert(VM_Version::supports_avx512vldq(), "");
11944   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11945   attributes.set_is_evex_instruction();
11946   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11947   emit_int16(0x38, (0xC0 | encode));
11948 }
11949 
11950 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
11951   assert(VM_Version::supports_avx512vlbw(), "");
11952   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11953   attributes.set_is_evex_instruction();
11954   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11955   emit_int16(0x28, (0xC0 | encode));
11956 }
11957 
11958 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
11959   assert(VM_Version::supports_avx512vlbw(), "");
11960   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11961   attributes.set_is_evex_instruction();
11962   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11963   emit_int16(0x28, (0xC0 | encode));
11964 }
11965 
11966 void Assembler::evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11967   assert(VM_Version::supports_avx512_vbmi2(), "");
11968   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11969   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11970   attributes.set_embedded_opmask_register_specifier(mask);
11971   attributes.set_is_evex_instruction();
11972   if (merge) {
11973     attributes.reset_is_clear_context();
11974   }
11975   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11976   emit_int16((unsigned char)0x63, (0xC0 | encode));
11977 }
11978 
11979 void Assembler::evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11980   assert(VM_Version::supports_avx512_vbmi2(), "");
11981   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11982   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11983   attributes.set_embedded_opmask_register_specifier(mask);
11984   attributes.set_is_evex_instruction();
11985   if (merge) {
11986     attributes.reset_is_clear_context();
11987   }
11988   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11989   emit_int16((unsigned char)0x63, (0xC0 | encode));
11990 }
11991 
11992 void Assembler::evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11993   assert(VM_Version::supports_evex(), "");
11994   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11995   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11996   attributes.set_embedded_opmask_register_specifier(mask);
11997   attributes.set_is_evex_instruction();
11998   if (merge) {
11999     attributes.reset_is_clear_context();
12000   }
12001   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12002   emit_int16((unsigned char)0x8B, (0xC0 | encode));
12003 }
12004 
12005 void Assembler::evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12006   assert(VM_Version::supports_evex(), "");
12007   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12008   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12009   attributes.set_embedded_opmask_register_specifier(mask);
12010   attributes.set_is_evex_instruction();
12011   if (merge) {
12012     attributes.reset_is_clear_context();
12013   }
12014   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12015   emit_int16((unsigned char)0x8B, (0xC0 | encode));
12016 }
12017 
12018 void Assembler::evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12019   assert(VM_Version::supports_evex(), "");
12020   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12021   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12022   attributes.set_embedded_opmask_register_specifier(mask);
12023   attributes.set_is_evex_instruction();
12024   if (merge) {
12025     attributes.reset_is_clear_context();
12026   }
12027   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12028   emit_int16((unsigned char)0x8A, (0xC0 | encode));
12029 }
12030 
12031 void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12032   assert(VM_Version::supports_evex(), "");
12033   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12034   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12035   attributes.set_embedded_opmask_register_specifier(mask);
12036   attributes.set_is_evex_instruction();
12037   if (merge) {
12038     attributes.reset_is_clear_context();
12039   }
12040   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12041   emit_int16((unsigned char)0x8A, (0xC0 | encode));
12042 }
12043 
12044 #ifndef _LP64
12045 
12046 void Assembler::incl(Register dst) {
12047   // Don't use it directly. Use MacroAssembler::incrementl() instead.
12048   emit_int8(0x40 | dst->encoding());
12049 }
12050 
12051 void Assembler::lea(Register dst, Address src) {
12052   leal(dst, src);
12053 }
12054 
12055 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
12056   InstructionMark im(this);
12057   emit_int8((unsigned char)0xC7);
12058   emit_operand(rax, dst);
12059   emit_data((int)imm32, rspec, 0);
12060 }
12061 
12062 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
12063   InstructionMark im(this);
12064   int encode = prefix_and_encode(dst->encoding());
12065   emit_int8((0xB8 | encode));
12066   emit_data((int)imm32, rspec, 0);
12067 }
12068 
12069 void Assembler::popa() { // 32bit
12070   emit_int8(0x61);
12071 }
12072 
12073 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
12074   InstructionMark im(this);
12075   emit_int8(0x68);
12076   emit_data(imm32, rspec, 0);
12077 }
12078 
12079 void Assembler::pusha() { // 32bit
12080   emit_int8(0x60);
12081 }
12082 
12083 void Assembler::set_byte_if_not_zero(Register dst) {
12084   emit_int24(0x0F, (unsigned char)0x95, (0xC0 | dst->encoding()));
12085 }
12086 
12087 #else // LP64
12088 
12089 void Assembler::set_byte_if_not_zero(Register dst) {
12090   int enc = prefix_and_encode(dst->encoding(), true);
12091   emit_int24(0x0F, (unsigned char)0x95, (0xC0 | enc));
12092 }
12093 
12094 // 64bit only pieces of the assembler
12095 // This should only be used by 64bit instructions that can use rip-relative
12096 // it cannot be used by instructions that want an immediate value.
12097 
12098 bool Assembler::reachable(AddressLiteral adr) {
12099   int64_t disp;
12100   relocInfo::relocType relocType = adr.reloc();
12101 
12102   // None will force a 64bit literal to the code stream. Likely a placeholder
12103   // for something that will be patched later and we need to certain it will
12104   // always be reachable.
12105   if (relocType == relocInfo::none) {
12106     return false;
12107   }
12108   if (relocType == relocInfo::internal_word_type) {
12109     // This should be rip relative and easily reachable.
12110     return true;
12111   }
12112   if (relocType == relocInfo::virtual_call_type ||
12113       relocType == relocInfo::opt_virtual_call_type ||
12114       relocType == relocInfo::static_call_type ||
12115       relocType == relocInfo::static_stub_type ) {
12116     // This should be rip relative within the code cache and easily
12117     // reachable until we get huge code caches. (At which point
12118     // ic code is going to have issues).
12119     return true;
12120   }
12121   if (relocType != relocInfo::external_word_type &&
12122       relocType != relocInfo::poll_return_type &&  // these are really external_word but need special
12123       relocType != relocInfo::poll_type &&         // relocs to identify them
12124       relocType != relocInfo::runtime_call_type ) {
12125     return false;
12126   }
12127 
12128   // Stress the correction code
12129   if (ForceUnreachable) {
12130     // Must be runtimecall reloc, see if it is in the codecache
12131     // Flipping stuff in the codecache to be unreachable causes issues
12132     // with things like inline caches where the additional instructions
12133     // are not handled.
12134     if (CodeCache::find_blob(adr._target) == NULL) {
12135       return false;
12136     }
12137   }
12138   // For external_word_type/runtime_call_type if it is reachable from where we
12139   // are now (possibly a temp buffer) and where we might end up
12140   // anywhere in the codeCache then we are always reachable.
12141   // This would have to change if we ever save/restore shared code
12142   // to be more pessimistic.
12143   disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
12144   if (!is_simm32(disp)) return false;
12145   disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
12146   if (!is_simm32(disp)) return false;
12147 
12148   disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
12149 
12150   // Because rip relative is a disp + address_of_next_instruction and we
12151   // don't know the value of address_of_next_instruction we apply a fudge factor
12152   // to make sure we will be ok no matter the size of the instruction we get placed into.
12153   // We don't have to fudge the checks above here because they are already worst case.
12154 
12155   // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
12156   // + 4 because better safe than sorry.
12157   const int fudge = 12 + 4;
12158   if (disp < 0) {
12159     disp -= fudge;
12160   } else {
12161     disp += fudge;
12162   }
12163   return is_simm32(disp);
12164 }
12165 
12166 void Assembler::emit_data64(jlong data,
12167                             relocInfo::relocType rtype,
12168                             int format) {
12169   if (rtype == relocInfo::none) {
12170     emit_int64(data);
12171   } else {
12172     emit_data64(data, Relocation::spec_simple(rtype), format);
12173   }
12174 }
12175 
12176 void Assembler::emit_data64(jlong data,
12177                             RelocationHolder const& rspec,
12178                             int format) {
12179   assert(imm_operand == 0, "default format must be immediate in this file");
12180   assert(imm_operand == format, "must be immediate");
12181   assert(inst_mark() != NULL, "must be inside InstructionMark");
12182   // Do not use AbstractAssembler::relocate, which is not intended for
12183   // embedded words.  Instead, relocate to the enclosing instruction.
12184   code_section()->relocate(inst_mark(), rspec, format);
12185 #ifdef ASSERT
12186   check_relocation(rspec, format);
12187 #endif
12188   emit_int64(data);
12189 }
12190 
12191 void Assembler::prefix(Register reg) {
12192   if (reg->encoding() >= 8) {
12193     prefix(REX_B);
12194   }
12195 }
12196 
12197 void Assembler::prefix(Register dst, Register src, Prefix p) {
12198   if (src->encoding() >= 8) {
12199     p = (Prefix)(p | REX_B);
12200   }
12201   if (dst->encoding() >= 8) {
12202     p = (Prefix)(p | REX_R);
12203   }
12204   if (p != Prefix_EMPTY) {
12205     // do not generate an empty prefix
12206     prefix(p);
12207   }
12208 }
12209 
12210 void Assembler::prefix(Register dst, Address adr, Prefix p) {
12211   if (adr.base_needs_rex()) {
12212     if (adr.index_needs_rex()) {
12213       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12214     } else {
12215       prefix(REX_B);
12216     }
12217   } else {
12218     if (adr.index_needs_rex()) {
12219       assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12220     }
12221   }
12222   if (dst->encoding() >= 8) {
12223     p = (Prefix)(p | REX_R);
12224   }
12225   if (p != Prefix_EMPTY) {
12226     // do not generate an empty prefix
12227     prefix(p);
12228   }
12229 }
12230 
12231 void Assembler::prefix(Address adr) {
12232   if (adr.base_needs_rex()) {
12233     if (adr.index_needs_rex()) {
12234       prefix(REX_XB);
12235     } else {
12236       prefix(REX_B);
12237     }
12238   } else {
12239     if (adr.index_needs_rex()) {
12240       prefix(REX_X);
12241     }
12242   }
12243 }
12244 
12245 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
12246   if (reg->encoding() < 8) {
12247     if (adr.base_needs_rex()) {
12248       if (adr.index_needs_rex()) {
12249         prefix(REX_XB);
12250       } else {
12251         prefix(REX_B);
12252       }
12253     } else {
12254       if (adr.index_needs_rex()) {
12255         prefix(REX_X);
12256       } else if (byteinst && reg->encoding() >= 4) {
12257         prefix(REX);
12258       }
12259     }
12260   } else {
12261     if (adr.base_needs_rex()) {
12262       if (adr.index_needs_rex()) {
12263         prefix(REX_RXB);
12264       } else {
12265         prefix(REX_RB);
12266       }
12267     } else {
12268       if (adr.index_needs_rex()) {
12269         prefix(REX_RX);
12270       } else {
12271         prefix(REX_R);
12272       }
12273     }
12274   }
12275 }
12276 
12277 void Assembler::prefix(Address adr, XMMRegister reg) {
12278   if (reg->encoding() < 8) {
12279     if (adr.base_needs_rex()) {
12280       if (adr.index_needs_rex()) {
12281         prefix(REX_XB);
12282       } else {
12283         prefix(REX_B);
12284       }
12285     } else {
12286       if (adr.index_needs_rex()) {
12287         prefix(REX_X);
12288       }
12289     }
12290   } else {
12291     if (adr.base_needs_rex()) {
12292       if (adr.index_needs_rex()) {
12293         prefix(REX_RXB);
12294       } else {
12295         prefix(REX_RB);
12296       }
12297     } else {
12298       if (adr.index_needs_rex()) {
12299         prefix(REX_RX);
12300       } else {
12301         prefix(REX_R);
12302       }
12303     }
12304   }
12305 }
12306 
12307 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
12308   if (reg_enc >= 8) {
12309     prefix(REX_B);
12310     reg_enc -= 8;
12311   } else if (byteinst && reg_enc >= 4) {
12312     prefix(REX);
12313   }
12314   return reg_enc;
12315 }
12316 
12317 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
12318   if (dst_enc < 8) {
12319     if (src_enc >= 8) {
12320       prefix(REX_B);
12321       src_enc -= 8;
12322     } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
12323       prefix(REX);
12324     }
12325   } else {
12326     if (src_enc < 8) {
12327       prefix(REX_R);
12328     } else {
12329       prefix(REX_RB);
12330       src_enc -= 8;
12331     }
12332     dst_enc -= 8;
12333   }
12334   return dst_enc << 3 | src_enc;
12335 }
12336 
12337 int8_t Assembler::get_prefixq(Address adr) {
12338   int8_t prfx = get_prefixq(adr, rax);
12339   assert(REX_W <= prfx && prfx <= REX_WXB, "must be");
12340   return prfx;
12341 }
12342 
12343 int8_t Assembler::get_prefixq(Address adr, Register src) {
12344   int8_t prfx = (int8_t)(REX_W +
12345                          ((int)adr.base_needs_rex()) +
12346                          ((int)adr.index_needs_rex() << 1) +
12347                          ((int)(src->encoding() >= 8) << 2));
12348 #ifdef ASSERT
12349   if (src->encoding() < 8) {
12350     if (adr.base_needs_rex()) {
12351       if (adr.index_needs_rex()) {
12352         assert(prfx == REX_WXB, "must be");
12353       } else {
12354         assert(prfx == REX_WB, "must be");
12355       }
12356     } else {
12357       if (adr.index_needs_rex()) {
12358         assert(prfx == REX_WX, "must be");
12359       } else {
12360         assert(prfx == REX_W, "must be");
12361       }
12362     }
12363   } else {
12364     if (adr.base_needs_rex()) {
12365       if (adr.index_needs_rex()) {
12366         assert(prfx == REX_WRXB, "must be");
12367       } else {
12368         assert(prfx == REX_WRB, "must be");
12369       }
12370     } else {
12371       if (adr.index_needs_rex()) {
12372         assert(prfx == REX_WRX, "must be");
12373       } else {
12374         assert(prfx == REX_WR, "must be");
12375       }
12376     }
12377   }
12378 #endif
12379   return prfx;
12380 }
12381 
12382 void Assembler::prefixq(Address adr) {
12383   emit_int8(get_prefixq(adr));
12384 }
12385 
12386 void Assembler::prefixq(Address adr, Register src) {
12387   emit_int8(get_prefixq(adr, src));
12388 }
12389 
12390 void Assembler::prefixq(Address adr, XMMRegister src) {
12391   if (src->encoding() < 8) {
12392     if (adr.base_needs_rex()) {
12393       if (adr.index_needs_rex()) {
12394         prefix(REX_WXB);
12395       } else {
12396         prefix(REX_WB);
12397       }
12398     } else {
12399       if (adr.index_needs_rex()) {
12400         prefix(REX_WX);
12401       } else {
12402         prefix(REX_W);
12403       }
12404     }
12405   } else {
12406     if (adr.base_needs_rex()) {
12407       if (adr.index_needs_rex()) {
12408         prefix(REX_WRXB);
12409       } else {
12410         prefix(REX_WRB);
12411       }
12412     } else {
12413       if (adr.index_needs_rex()) {
12414         prefix(REX_WRX);
12415       } else {
12416         prefix(REX_WR);
12417       }
12418     }
12419   }
12420 }
12421 
12422 int Assembler::prefixq_and_encode(int reg_enc) {
12423   if (reg_enc < 8) {
12424     prefix(REX_W);
12425   } else {
12426     prefix(REX_WB);
12427     reg_enc -= 8;
12428   }
12429   return reg_enc;
12430 }
12431 
12432 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
12433   if (dst_enc < 8) {
12434     if (src_enc < 8) {
12435       prefix(REX_W);
12436     } else {
12437       prefix(REX_WB);
12438       src_enc -= 8;
12439     }
12440   } else {
12441     if (src_enc < 8) {
12442       prefix(REX_WR);
12443     } else {
12444       prefix(REX_WRB);
12445       src_enc -= 8;
12446     }
12447     dst_enc -= 8;
12448   }
12449   return dst_enc << 3 | src_enc;
12450 }
12451 
12452 void Assembler::adcq(Register dst, int32_t imm32) {
12453   (void) prefixq_and_encode(dst->encoding());
12454   emit_arith(0x81, 0xD0, dst, imm32);
12455 }
12456 
12457 void Assembler::adcq(Register dst, Address src) {
12458   InstructionMark im(this);
12459   emit_int16(get_prefixq(src, dst), 0x13);
12460   emit_operand(dst, src);
12461 }
12462 
12463 void Assembler::adcq(Register dst, Register src) {
12464   (void) prefixq_and_encode(dst->encoding(), src->encoding());
12465   emit_arith(0x13, 0xC0, dst, src);
12466 }
12467 
12468 void Assembler::addq(Address dst, int32_t imm32) {
12469   InstructionMark im(this);
12470   prefixq(dst);
12471   emit_arith_operand(0x81, rax, dst, imm32);
12472 }
12473 
12474 void Assembler::addq(Address dst, Register src) {
12475   InstructionMark im(this);
12476   emit_int16(get_prefixq(dst, src), 0x01);
12477   emit_operand(src, dst);
12478 }
12479 
12480 void Assembler::addq(Register dst, int32_t imm32) {
12481   (void) prefixq_and_encode(dst->encoding());
12482   emit_arith(0x81, 0xC0, dst, imm32);
12483 }
12484 
12485 void Assembler::addq(Register dst, Address src) {
12486   InstructionMark im(this);
12487   emit_int16(get_prefixq(src, dst), 0x03);
12488   emit_operand(dst, src);
12489 }
12490 
12491 void Assembler::addq(Register dst, Register src) {
12492   (void) prefixq_and_encode(dst->encoding(), src->encoding());
12493   emit_arith(0x03, 0xC0, dst, src);
12494 }
12495 
12496 void Assembler::adcxq(Register dst, Register src) {
12497   //assert(VM_Version::supports_adx(), "adx instructions not supported");
12498   emit_int8(0x66);
12499   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12500   emit_int32(0x0F,
12501              0x38,
12502              (unsigned char)0xF6,
12503              (0xC0 | encode));
12504 }
12505 
12506 void Assembler::adoxq(Register dst, Register src) {
12507   //assert(VM_Version::supports_adx(), "adx instructions not supported");
12508   emit_int8((unsigned char)0xF3);
12509   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12510   emit_int32(0x0F,
12511              0x38,
12512              (unsigned char)0xF6,
12513              (0xC0 | encode));
12514 }
12515 
12516 void Assembler::andq(Address dst, int32_t imm32) {
12517   InstructionMark im(this);
12518   prefixq(dst);
12519   emit_arith_operand(0x81, as_Register(4), dst, imm32);
12520 }
12521 
12522 void Assembler::andq(Register dst, int32_t imm32) {
12523   (void) prefixq_and_encode(dst->encoding());
12524   emit_arith(0x81, 0xE0, dst, imm32);
12525 }
12526 
12527 void Assembler::andq(Register dst, Address src) {
12528   InstructionMark im(this);
12529   emit_int16(get_prefixq(src, dst), 0x23);
12530   emit_operand(dst, src);
12531 }
12532 
12533 void Assembler::andq(Register dst, Register src) {
12534   (void) prefixq_and_encode(dst->encoding(), src->encoding());
12535   emit_arith(0x23, 0xC0, dst, src);
12536 }
12537 
12538 void Assembler::andq(Address dst, Register src) {
12539   InstructionMark im(this);
12540   emit_int16(get_prefixq(dst, src), 0x21);
12541   emit_operand(src, dst);
12542 }
12543 
12544 void Assembler::andnq(Register dst, Register src1, Register src2) {
12545   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12546   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12547   int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12548   emit_int16((unsigned char)0xF2, (0xC0 | encode));
12549 }
12550 
12551 void Assembler::andnq(Register dst, Register src1, Address src2) {
12552   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12553   InstructionMark im(this);
12554   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12555   vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12556   emit_int8((unsigned char)0xF2);
12557   emit_operand(dst, src2);
12558 }
12559 
12560 void Assembler::bsfq(Register dst, Register src) {
12561   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12562   emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
12563 }
12564 
12565 void Assembler::bsrq(Register dst, Register src) {
12566   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12567   emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
12568 }
12569 
12570 void Assembler::bswapq(Register reg) {
12571   int encode = prefixq_and_encode(reg->encoding());
12572   emit_int16(0x0F, (0xC8 | encode));
12573 }
12574 
12575 void Assembler::blsiq(Register dst, Register src) {
12576   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12577   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12578   int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12579   emit_int16((unsigned char)0xF3, (0xC0 | encode));
12580 }
12581 
12582 void Assembler::blsiq(Register dst, Address src) {
12583   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12584   InstructionMark im(this);
12585   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12586   vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12587   emit_int8((unsigned char)0xF3);
12588   emit_operand(rbx, src);
12589 }
12590 
12591 void Assembler::blsmskq(Register dst, Register src) {
12592   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12593   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12594   int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12595   emit_int16((unsigned char)0xF3, (0xC0 | encode));
12596 }
12597 
12598 void Assembler::blsmskq(Register dst, Address src) {
12599   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12600   InstructionMark im(this);
12601   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12602   vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12603   emit_int8((unsigned char)0xF3);
12604   emit_operand(rdx, src);
12605 }
12606 
12607 void Assembler::blsrq(Register dst, Register src) {
12608   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12609   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12610   int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12611   emit_int16((unsigned char)0xF3, (0xC0 | encode));
12612 }
12613 
12614 void Assembler::blsrq(Register dst, Address src) {
12615   assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12616   InstructionMark im(this);
12617   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12618   vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12619   emit_int8((unsigned char)0xF3);
12620   emit_operand(rcx, src);
12621 }
12622 
12623 void Assembler::cdqq() {
12624   emit_int16(REX_W, (unsigned char)0x99);
12625 }
12626 
12627 void Assembler::clflush(Address adr) {
12628   assert(VM_Version::supports_clflush(), "should do");
12629   prefix(adr);
12630   emit_int16(0x0F, (unsigned char)0xAE);
12631   emit_operand(rdi, adr);
12632 }
12633 
12634 void Assembler::clflushopt(Address adr) {
12635   assert(VM_Version::supports_clflushopt(), "should do!");
12636   // adr should be base reg only with no index or offset
12637   assert(adr.index() == noreg, "index should be noreg");
12638   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
12639   assert(adr.disp() == 0, "displacement should be 0");
12640   // instruction prefix is 0x66
12641   emit_int8(0x66);
12642   prefix(adr);
12643   // opcode family is 0x0F 0xAE
12644   emit_int16(0x0F, (unsigned char)0xAE);
12645   // extended opcode byte is 7 == rdi
12646   emit_operand(rdi, adr);
12647 }
12648 
12649 void Assembler::clwb(Address adr) {
12650   assert(VM_Version::supports_clwb(), "should do!");
12651   // adr should be base reg only with no index or offset
12652   assert(adr.index() == noreg, "index should be noreg");
12653   assert(adr.scale() == Address::no_scale, "scale should be no_scale");
12654   assert(adr.disp() == 0, "displacement should be 0");
12655   // instruction prefix is 0x66
12656   emit_int8(0x66);
12657   prefix(adr);
12658   // opcode family is 0x0f 0xAE
12659   emit_int16(0x0F, (unsigned char)0xAE);
12660   // extended opcode byte is 6 == rsi
12661   emit_operand(rsi, adr);
12662 }
12663 
12664 void Assembler::cmovq(Condition cc, Register dst, Register src) {
12665   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12666   emit_int24(0x0F, (0x40 | cc), (0xC0 | encode));
12667 }
12668 
12669 void Assembler::cmovq(Condition cc, Register dst, Address src) {
12670   InstructionMark im(this);
12671   emit_int24(get_prefixq(src, dst), 0x0F, (0x40 | cc));
12672   emit_operand(dst, src);
12673 }
12674 
12675 void Assembler::cmpq(Address dst, int32_t imm32) {
12676   InstructionMark im(this);
12677   emit_int16(get_prefixq(dst), (unsigned char)0x81);
12678   emit_operand(rdi, dst, 4);
12679   emit_int32(imm32);
12680 }
12681 
12682 void Assembler::cmpq(Register dst, int32_t imm32) {
12683   (void) prefixq_and_encode(dst->encoding());
12684   emit_arith(0x81, 0xF8, dst, imm32);
12685 }
12686 
12687 void Assembler::cmpq(Address dst, Register src) {
12688   InstructionMark im(this);
12689   emit_int16(get_prefixq(dst, src), 0x39);
12690   emit_operand(src, dst);
12691 }
12692 
12693 void Assembler::cmpq(Register dst, Register src) {
12694   (void) prefixq_and_encode(dst->encoding(), src->encoding());
12695   emit_arith(0x3B, 0xC0, dst, src);
12696 }
12697 
12698 void Assembler::cmpq(Register dst, Address src) {
12699   InstructionMark im(this);
12700   emit_int16(get_prefixq(src, dst), 0x3B);
12701   emit_operand(dst, src);
12702 }
12703 
12704 void Assembler::cmpxchgq(Register reg, Address adr) {
12705   InstructionMark im(this);
12706   emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1);
12707   emit_operand(reg, adr);
12708 }
12709 
12710 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
12711   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12712   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12713   int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
12714   emit_int16(0x2A, (0xC0 | encode));
12715 }
12716 
12717 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
12718   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12719   InstructionMark im(this);
12720   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12721   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
12722   simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
12723   emit_int8(0x2A);
12724   emit_operand(dst, src);
12725 }
12726 
12727 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
12728   NOT_LP64(assert(VM_Version::supports_sse(), ""));
12729   InstructionMark im(this);
12730   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12731   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
12732   simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
12733   emit_int8(0x2A);
12734   emit_operand(dst, src);
12735 }
12736 
12737 void Assembler::cvttsd2siq(Register dst, Address src) {
12738   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12739   // F2 REX.W 0F 2C /r
12740   // CVTTSD2SI r64, xmm1/m64
12741   InstructionMark im(this);
12742   emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C);
12743   emit_operand(dst, src);
12744 }
12745 
12746 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
12747   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12748   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12749   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
12750   emit_int16(0x2C, (0xC0 | encode));
12751 }
12752 
12753 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
12754   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12755   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12756   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
12757   emit_int16(0x2D, (0xC0 | encode));
12758 }
12759 
12760 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
12761   NOT_LP64(assert(VM_Version::supports_sse(), ""));
12762   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12763   int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
12764   emit_int16(0x2C, (0xC0 | encode));
12765 }
12766 
12767 void Assembler::decl(Register dst) {
12768   // Don't use it directly. Use MacroAssembler::decrementl() instead.
12769   // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
12770   int encode = prefix_and_encode(dst->encoding());
12771   emit_int16((unsigned char)0xFF, (0xC8 | encode));
12772 }
12773 
12774 void Assembler::decq(Register dst) {
12775   // Don't use it directly. Use MacroAssembler::decrementq() instead.
12776   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
12777   int encode = prefixq_and_encode(dst->encoding());
12778   emit_int16((unsigned char)0xFF, 0xC8 | encode);
12779 }
12780 
12781 void Assembler::decq(Address dst) {
12782   // Don't use it directly. Use MacroAssembler::decrementq() instead.
12783   InstructionMark im(this);
12784   emit_int16(get_prefixq(dst), (unsigned char)0xFF);
12785   emit_operand(rcx, dst);
12786 }
12787 
12788 void Assembler::fxrstor(Address src) {
12789   emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
12790   emit_operand(as_Register(1), src);
12791 }
12792 
12793 void Assembler::xrstor(Address src) {
12794   emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
12795   emit_operand(as_Register(5), src);
12796 }
12797 
12798 void Assembler::fxsave(Address dst) {
12799   emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
12800   emit_operand(as_Register(0), dst);
12801 }
12802 
12803 void Assembler::xsave(Address dst) {
12804   emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
12805   emit_operand(as_Register(4), dst);
12806 }
12807 
12808 void Assembler::idivq(Register src) {
12809   int encode = prefixq_and_encode(src->encoding());
12810   emit_int16((unsigned char)0xF7, (0xF8 | encode));
12811 }
12812 
12813 void Assembler::divq(Register src) {
12814   int encode = prefixq_and_encode(src->encoding());
12815   emit_int16((unsigned char)0xF7, (0xF0 | encode));
12816 }
12817 
12818 void Assembler::imulq(Register dst, Register src) {
12819   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12820   emit_int24(0x0F, (unsigned char)0xAF, (0xC0 | encode));
12821 }
12822 
12823 void Assembler::imulq(Register src) {
12824   int encode = prefixq_and_encode(src->encoding());
12825   emit_int16((unsigned char)0xF7, (0xE8 | encode));
12826 }
12827 
12828 void Assembler::imulq(Register dst, Address src, int32_t value) {
12829   InstructionMark im(this);
12830   prefixq(src, dst);
12831   if (is8bit(value)) {
12832     emit_int8((unsigned char)0x6B);
12833     emit_operand(dst, src);
12834     emit_int8(value);
12835   } else {
12836     emit_int8((unsigned char)0x69);
12837     emit_operand(dst, src);
12838     emit_int32(value);
12839   }
12840 }
12841 
12842 void Assembler::imulq(Register dst, Register src, int value) {
12843   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12844   if (is8bit(value)) {
12845     emit_int24(0x6B, (0xC0 | encode), (value & 0xFF));
12846   } else {
12847     emit_int16(0x69, (0xC0 | encode));
12848     emit_int32(value);
12849   }
12850 }
12851 
12852 void Assembler::imulq(Register dst, Address src) {
12853   InstructionMark im(this);
12854   emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF);
12855   emit_operand(dst, src);
12856 }
12857 
12858 void Assembler::incl(Register dst) {
12859   // Don't use it directly. Use MacroAssembler::incrementl() instead.
12860   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
12861   int encode = prefix_and_encode(dst->encoding());
12862   emit_int16((unsigned char)0xFF, (0xC0 | encode));
12863 }
12864 
12865 void Assembler::incq(Register dst) {
12866   // Don't use it directly. Use MacroAssembler::incrementq() instead.
12867   // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
12868   int encode = prefixq_and_encode(dst->encoding());
12869   emit_int16((unsigned char)0xFF, (0xC0 | encode));
12870 }
12871 
12872 void Assembler::incq(Address dst) {
12873   // Don't use it directly. Use MacroAssembler::incrementq() instead.
12874   InstructionMark im(this);
12875   emit_int16(get_prefixq(dst), (unsigned char)0xFF);
12876   emit_operand(rax, dst);
12877 }
12878 
12879 void Assembler::lea(Register dst, Address src) {
12880   leaq(dst, src);
12881 }
12882 
12883 void Assembler::leaq(Register dst, Address src) {
12884   InstructionMark im(this);
12885   emit_int16(get_prefixq(src, dst), (unsigned char)0x8D);
12886   emit_operand(dst, src);
12887 }
12888 
12889 void Assembler::mov64(Register dst, int64_t imm64) {
12890   InstructionMark im(this);
12891   int encode = prefixq_and_encode(dst->encoding());
12892   emit_int8(0xB8 | encode);
12893   emit_int64(imm64);
12894 }
12895 
12896 void Assembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
12897   InstructionMark im(this);
12898   int encode = prefixq_and_encode(dst->encoding());
12899   emit_int8(0xB8 | encode);
12900   emit_data64(imm64, rtype, format);
12901 }
12902 
12903 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
12904   InstructionMark im(this);
12905   int encode = prefixq_and_encode(dst->encoding());
12906   emit_int8(0xB8 | encode);
12907   emit_data64(imm64, rspec);
12908 }
12909 
12910 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
12911   InstructionMark im(this);
12912   int encode = prefix_and_encode(dst->encoding());
12913   emit_int8(0xB8 | encode);
12914   emit_data((int)imm32, rspec, narrow_oop_operand);
12915 }
12916 
12917 void Assembler::mov_narrow_oop(Address dst, int32_t imm32,  RelocationHolder const& rspec) {
12918   InstructionMark im(this);
12919   prefix(dst);
12920   emit_int8((unsigned char)0xC7);
12921   emit_operand(rax, dst, 4);
12922   emit_data((int)imm32, rspec, narrow_oop_operand);
12923 }
12924 
12925 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
12926   InstructionMark im(this);
12927   int encode = prefix_and_encode(src1->encoding());
12928   emit_int16((unsigned char)0x81, (0xF8 | encode));
12929   emit_data((int)imm32, rspec, narrow_oop_operand);
12930 }
12931 
12932 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
12933   InstructionMark im(this);
12934   prefix(src1);
12935   emit_int8((unsigned char)0x81);
12936   emit_operand(rax, src1, 4);
12937   emit_data((int)imm32, rspec, narrow_oop_operand);
12938 }
12939 
12940 void Assembler::lzcntq(Register dst, Register src) {
12941   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
12942   emit_int8((unsigned char)0xF3);
12943   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12944   emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
12945 }
12946 
12947 void Assembler::lzcntq(Register dst, Address src) {
12948   assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
12949   InstructionMark im(this);
12950   emit_int8((unsigned char)0xF3);
12951   prefixq(src, dst);
12952   emit_int16(0x0F, (unsigned char)0xBD);
12953   emit_operand(dst, src);
12954 }
12955 
12956 void Assembler::movdq(XMMRegister dst, Register src) {
12957   // table D-1 says MMX/SSE2
12958   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12959   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12960   int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12961   emit_int16(0x6E, (0xC0 | encode));
12962 }
12963 
12964 void Assembler::movdq(Register dst, XMMRegister src) {
12965   // table D-1 says MMX/SSE2
12966   NOT_LP64(assert(VM_Version::supports_sse2(), ""));
12967   InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
12968   // swap src/dst to get correct prefix
12969   int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12970   emit_int16(0x7E,
12971              (0xC0 | encode));
12972 }
12973 
12974 void Assembler::movq(Register dst, Register src) {
12975   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12976   emit_int16((unsigned char)0x8B,
12977              (0xC0 | encode));
12978 }
12979 
12980 void Assembler::movq(Register dst, Address src) {
12981   InstructionMark im(this);
12982   emit_int16(get_prefixq(src, dst), (unsigned char)0x8B);
12983   emit_operand(dst, src);
12984 }
12985 
12986 void Assembler::movq(Address dst, Register src) {
12987   InstructionMark im(this);
12988   emit_int16(get_prefixq(dst, src), (unsigned char)0x89);
12989   emit_operand(src, dst);
12990 }
12991 
12992 void Assembler::movq(Address dst, int32_t imm32) {
12993   InstructionMark im(this);
12994   emit_int16(get_prefixq(dst), (unsigned char)0xC7);
12995   emit_operand(as_Register(0), dst);
12996   emit_int32(imm32);
12997 }
12998 
12999 void Assembler::movq(Register dst, int32_t imm32) {
13000   int encode = prefixq_and_encode(dst->encoding());
13001   emit_int16((unsigned char)0xC7, (0xC0 | encode));
13002   emit_int32(imm32);
13003 }
13004 
13005 void Assembler::movsbq(Register dst, Address src) {
13006   InstructionMark im(this);
13007   emit_int24(get_prefixq(src, dst),
13008              0x0F,
13009              (unsigned char)0xBE);
13010   emit_operand(dst, src);
13011 }
13012 
13013 void Assembler::movsbq(Register dst, Register src) {
13014   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13015   emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
13016 }
13017 
13018 void Assembler::movslq(Register dst, int32_t imm32) {
13019   // dbx shows movslq(rcx, 3) as movq     $0x0000000049000000,(%rbx)
13020   // and movslq(r8, 3); as movl     $0x0000000048000000,(%rbx)
13021   // as a result we shouldn't use until tested at runtime...
13022   ShouldNotReachHere();
13023   InstructionMark im(this);
13024   int encode = prefixq_and_encode(dst->encoding());
13025   emit_int8(0xC7 | encode);
13026   emit_int32(imm32);
13027 }
13028 
13029 void Assembler::movslq(Address dst, int32_t imm32) {
13030   assert(is_simm32(imm32), "lost bits");
13031   InstructionMark im(this);
13032   emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13033   emit_operand(rax, dst, 4);
13034   emit_int32(imm32);
13035 }
13036 
13037 void Assembler::movslq(Register dst, Address src) {
13038   InstructionMark im(this);
13039   emit_int16(get_prefixq(src, dst), 0x63);
13040   emit_operand(dst, src);
13041 }
13042 
13043 void Assembler::movslq(Register dst, Register src) {
13044   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13045   emit_int16(0x63, (0xC0 | encode));
13046 }
13047 
13048 void Assembler::movswq(Register dst, Address src) {
13049   InstructionMark im(this);
13050   emit_int24(get_prefixq(src, dst),
13051              0x0F,
13052              (unsigned char)0xBF);
13053   emit_operand(dst, src);
13054 }
13055 
13056 void Assembler::movswq(Register dst, Register src) {
13057   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13058   emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
13059 }
13060 
13061 void Assembler::movzbq(Register dst, Address src) {
13062   InstructionMark im(this);
13063   emit_int24(get_prefixq(src, dst),
13064              0x0F,
13065              (unsigned char)0xB6);
13066   emit_operand(dst, src);
13067 }
13068 
13069 void Assembler::movzbq(Register dst, Register src) {
13070   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13071   emit_int24(0x0F, (unsigned char)0xB6, (0xC0 | encode));
13072 }
13073 
13074 void Assembler::movzwq(Register dst, Address src) {
13075   InstructionMark im(this);
13076   emit_int24(get_prefixq(src, dst),
13077              0x0F,
13078              (unsigned char)0xB7);
13079   emit_operand(dst, src);
13080 }
13081 
13082 void Assembler::movzwq(Register dst, Register src) {
13083   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13084   emit_int24(0x0F, (unsigned char)0xB7, (0xC0 | encode));
13085 }
13086 
13087 void Assembler::mulq(Address src) {
13088   InstructionMark im(this);
13089   emit_int16(get_prefixq(src), (unsigned char)0xF7);
13090   emit_operand(rsp, src);
13091 }
13092 
13093 void Assembler::mulq(Register src) {
13094   int encode = prefixq_and_encode(src->encoding());
13095   emit_int16((unsigned char)0xF7, (0xE0 | encode));
13096 }
13097 
13098 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
13099   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13100   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13101   int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
13102   emit_int16((unsigned char)0xF6, (0xC0 | encode));
13103 }
13104 
13105 void Assembler::negq(Register dst) {
13106   int encode = prefixq_and_encode(dst->encoding());
13107   emit_int16((unsigned char)0xF7, (0xD8 | encode));
13108 }
13109 
13110 void Assembler::negq(Address dst) {
13111   InstructionMark im(this);
13112   emit_int16(get_prefixq(dst), (unsigned char)0xF7);
13113   emit_operand(as_Register(3), dst);
13114 }
13115 
13116 void Assembler::notq(Register dst) {
13117   int encode = prefixq_and_encode(dst->encoding());
13118   emit_int16((unsigned char)0xF7, (0xD0 | encode));
13119 }
13120 
13121 void Assembler::btsq(Address dst, int imm8) {
13122   assert(isByte(imm8), "not a byte");
13123   InstructionMark im(this);
13124   emit_int24(get_prefixq(dst),
13125              0x0F,
13126              (unsigned char)0xBA);
13127   emit_operand(rbp /* 5 */, dst, 1);
13128   emit_int8(imm8);
13129 }
13130 
13131 void Assembler::btrq(Address dst, int imm8) {
13132   assert(isByte(imm8), "not a byte");
13133   InstructionMark im(this);
13134   emit_int24(get_prefixq(dst),
13135              0x0F,
13136              (unsigned char)0xBA);
13137   emit_operand(rsi /* 6 */, dst, 1);
13138   emit_int8(imm8);
13139 }
13140 
13141 void Assembler::orq(Address dst, int32_t imm32) {
13142   InstructionMark im(this);
13143   prefixq(dst);
13144   emit_arith_operand(0x81, as_Register(1), dst, imm32);
13145 }
13146 
13147 void Assembler::orq(Address dst, Register src) {
13148   InstructionMark im(this);
13149   emit_int16(get_prefixq(dst, src), (unsigned char)0x09);
13150   emit_operand(src, dst);
13151 }
13152 
13153 void Assembler::orq(Register dst, int32_t imm32) {
13154   (void) prefixq_and_encode(dst->encoding());
13155   emit_arith(0x81, 0xC8, dst, imm32);
13156 }
13157 
13158 void Assembler::orq(Register dst, Address src) {
13159   InstructionMark im(this);
13160   emit_int16(get_prefixq(src, dst), 0x0B);
13161   emit_operand(dst, src);
13162 }
13163 
13164 void Assembler::orq(Register dst, Register src) {
13165   (void) prefixq_and_encode(dst->encoding(), src->encoding());
13166   emit_arith(0x0B, 0xC0, dst, src);
13167 }
13168 
13169 void Assembler::popcntq(Register dst, Address src) {
13170   assert(VM_Version::supports_popcnt(), "must support");
13171   InstructionMark im(this);
13172   emit_int32((unsigned char)0xF3,
13173              get_prefixq(src, dst),
13174              0x0F,
13175              (unsigned char)0xB8);
13176   emit_operand(dst, src);
13177 }
13178 
13179 void Assembler::popcntq(Register dst, Register src) {
13180   assert(VM_Version::supports_popcnt(), "must support");
13181   emit_int8((unsigned char)0xF3);
13182   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13183   emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
13184 }
13185 
13186 void Assembler::popq(Address dst) {
13187   InstructionMark im(this);
13188   emit_int16(get_prefixq(dst), (unsigned char)0x8F);
13189   emit_operand(rax, dst);
13190 }
13191 
13192 void Assembler::popq(Register dst) {
13193   emit_int8((unsigned char)0x58 | dst->encoding());
13194 }
13195 
13196 // Precomputable: popa, pusha, vzeroupper
13197 
13198 // The result of these routines are invariant from one invocation to another
13199 // invocation for the duration of a run. Caching the result on bootstrap
13200 // and copying it out on subsequent invocations can thus be beneficial
13201 static bool     precomputed = false;
13202 
13203 static u_char* popa_code  = NULL;
13204 static int     popa_len   = 0;
13205 
13206 static u_char* pusha_code = NULL;
13207 static int     pusha_len  = 0;
13208 
13209 static u_char* vzup_code  = NULL;
13210 static int     vzup_len   = 0;
13211 
13212 void Assembler::precompute_instructions() {
13213   assert(!Universe::is_fully_initialized(), "must still be single threaded");
13214   guarantee(!precomputed, "only once");
13215   precomputed = true;
13216   ResourceMark rm;
13217 
13218   // Make a temporary buffer big enough for the routines we're capturing
13219   int size = 256;
13220   char* tmp_code = NEW_RESOURCE_ARRAY(char, size);
13221   CodeBuffer buffer((address)tmp_code, size);
13222   MacroAssembler masm(&buffer);
13223 
13224   address begin_popa  = masm.code_section()->end();
13225   masm.popa_uncached();
13226   address end_popa    = masm.code_section()->end();
13227   masm.pusha_uncached();
13228   address end_pusha   = masm.code_section()->end();
13229   masm.vzeroupper_uncached();
13230   address end_vzup    = masm.code_section()->end();
13231 
13232   // Save the instructions to permanent buffers.
13233   popa_len = (int)(end_popa - begin_popa);
13234   popa_code = NEW_C_HEAP_ARRAY(u_char, popa_len, mtInternal);
13235   memcpy(popa_code, begin_popa, popa_len);
13236 
13237   pusha_len = (int)(end_pusha - end_popa);
13238   pusha_code = NEW_C_HEAP_ARRAY(u_char, pusha_len, mtInternal);
13239   memcpy(pusha_code, end_popa, pusha_len);
13240 
13241   vzup_len = (int)(end_vzup - end_pusha);
13242   if (vzup_len > 0) {
13243     vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
13244     memcpy(vzup_code, end_pusha, vzup_len);
13245   } else {
13246     vzup_code = pusha_code; // dummy
13247   }
13248 
13249   assert(masm.code()->total_oop_size() == 0 &&
13250          masm.code()->total_metadata_size() == 0 &&
13251          masm.code()->total_relocation_size() == 0,
13252          "pre-computed code can't reference oops, metadata or contain relocations");
13253 }
13254 
13255 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
13256   assert(src != NULL, "code to copy must have been pre-computed");
13257   assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
13258   address end = code_section->end();
13259   memcpy(end, src, src_len);
13260   code_section->set_end(end + src_len);
13261 }
13262 
13263 void Assembler::popa() { // 64bit
13264   emit_copy(code_section(), popa_code, popa_len);
13265 }
13266 
13267 void Assembler::popa_uncached() { // 64bit
13268   movq(r15, Address(rsp, 0));
13269   movq(r14, Address(rsp, wordSize));
13270   movq(r13, Address(rsp, 2 * wordSize));
13271   movq(r12, Address(rsp, 3 * wordSize));
13272   movq(r11, Address(rsp, 4 * wordSize));
13273   movq(r10, Address(rsp, 5 * wordSize));
13274   movq(r9,  Address(rsp, 6 * wordSize));
13275   movq(r8,  Address(rsp, 7 * wordSize));
13276   movq(rdi, Address(rsp, 8 * wordSize));
13277   movq(rsi, Address(rsp, 9 * wordSize));
13278   movq(rbp, Address(rsp, 10 * wordSize));
13279   // Skip rsp as it is restored automatically to the value
13280   // before the corresponding pusha when popa is done.
13281   movq(rbx, Address(rsp, 12 * wordSize));
13282   movq(rdx, Address(rsp, 13 * wordSize));
13283   movq(rcx, Address(rsp, 14 * wordSize));
13284   movq(rax, Address(rsp, 15 * wordSize));
13285 
13286   addq(rsp, 16 * wordSize);
13287 }
13288 
13289 // Does not actually store the value of rsp on the stack.
13290 // The slot for rsp just contains an arbitrary value.
13291 void Assembler::pusha() { // 64bit
13292   emit_copy(code_section(), pusha_code, pusha_len);
13293 }
13294 
13295 // Does not actually store the value of rsp on the stack.
13296 // The slot for rsp just contains an arbitrary value.
13297 void Assembler::pusha_uncached() { // 64bit
13298   subq(rsp, 16 * wordSize);
13299 
13300   movq(Address(rsp, 15 * wordSize), rax);
13301   movq(Address(rsp, 14 * wordSize), rcx);
13302   movq(Address(rsp, 13 * wordSize), rdx);
13303   movq(Address(rsp, 12 * wordSize), rbx);
13304   // Skip rsp as the value is normally not used. There are a few places where
13305   // the original value of rsp needs to be known but that can be computed
13306   // from the value of rsp immediately after pusha (rsp + 16 * wordSize).
13307   movq(Address(rsp, 10 * wordSize), rbp);
13308   movq(Address(rsp, 9 * wordSize), rsi);
13309   movq(Address(rsp, 8 * wordSize), rdi);
13310   movq(Address(rsp, 7 * wordSize), r8);
13311   movq(Address(rsp, 6 * wordSize), r9);
13312   movq(Address(rsp, 5 * wordSize), r10);
13313   movq(Address(rsp, 4 * wordSize), r11);
13314   movq(Address(rsp, 3 * wordSize), r12);
13315   movq(Address(rsp, 2 * wordSize), r13);
13316   movq(Address(rsp, wordSize), r14);
13317   movq(Address(rsp, 0), r15);
13318 }
13319 
13320 void Assembler::vzeroupper() {
13321   emit_copy(code_section(), vzup_code, vzup_len);
13322 }
13323 
13324 void Assembler::pushq(Address src) {
13325   InstructionMark im(this);
13326   emit_int16(get_prefixq(src), (unsigned char)0xFF);
13327   emit_operand(rsi, src);
13328 }
13329 
13330 void Assembler::rclq(Register dst, int imm8) {
13331   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13332   int encode = prefixq_and_encode(dst->encoding());
13333   if (imm8 == 1) {
13334     emit_int16((unsigned char)0xD1, (0xD0 | encode));
13335   } else {
13336     emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
13337   }
13338 }
13339 
13340 void Assembler::rcrq(Register dst, int imm8) {
13341   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13342   int encode = prefixq_and_encode(dst->encoding());
13343   if (imm8 == 1) {
13344     emit_int16((unsigned char)0xD1, (0xD8 | encode));
13345   } else {
13346     emit_int24((unsigned char)0xC1, (0xD8 | encode), imm8);
13347   }
13348 }
13349 
13350 void Assembler::rorxl(Register dst, Register src, int imm8) {
13351   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13352   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13353   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13354   emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13355 }
13356 
13357 void Assembler::rorxl(Register dst, Address src, int imm8) {
13358   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13359   InstructionMark im(this);
13360   InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13361   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13362   emit_int8((unsigned char)0xF0);
13363   emit_operand(dst, src);
13364   emit_int8(imm8);
13365 }
13366 
13367 void Assembler::rorxq(Register dst, Register src, int imm8) {
13368   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13369   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13370   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13371   emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13372 }
13373 
13374 void Assembler::rorxq(Register dst, Address src, int imm8) {
13375   assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13376   InstructionMark im(this);
13377   InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13378   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13379   emit_int8((unsigned char)0xF0);
13380   emit_operand(dst, src);
13381   emit_int8(imm8);
13382 }
13383 
13384 #ifdef _LP64
13385 void Assembler::salq(Address dst, int imm8) {
13386   InstructionMark im(this);
13387   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13388   if (imm8 == 1) {
13389     emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13390     emit_operand(as_Register(4), dst);
13391   }
13392   else {
13393     emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13394     emit_operand(as_Register(4), dst);
13395     emit_int8(imm8);
13396   }
13397 }
13398 
13399 void Assembler::salq(Address dst) {
13400   InstructionMark im(this);
13401   emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13402   emit_operand(as_Register(4), dst);
13403 }
13404 
13405 void Assembler::salq(Register dst, int imm8) {
13406   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13407   int encode = prefixq_and_encode(dst->encoding());
13408   if (imm8 == 1) {
13409     emit_int16((unsigned char)0xD1, (0xE0 | encode));
13410   } else {
13411     emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13412   }
13413 }
13414 
13415 void Assembler::salq(Register dst) {
13416   int encode = prefixq_and_encode(dst->encoding());
13417   emit_int16((unsigned char)0xD3, (0xE0 | encode));
13418 }
13419 
13420 void Assembler::sarq(Address dst, int imm8) {
13421   InstructionMark im(this);
13422   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13423   if (imm8 == 1) {
13424     emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13425     emit_operand(as_Register(7), dst);
13426   }
13427   else {
13428     emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13429     emit_operand(as_Register(7), dst);
13430     emit_int8(imm8);
13431   }
13432 }
13433 
13434 void Assembler::sarq(Address dst) {
13435   InstructionMark im(this);
13436   emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13437   emit_operand(as_Register(7), dst);
13438 }
13439 
13440 void Assembler::sarq(Register dst, int imm8) {
13441   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13442   int encode = prefixq_and_encode(dst->encoding());
13443   if (imm8 == 1) {
13444     emit_int16((unsigned char)0xD1, (0xF8 | encode));
13445   } else {
13446     emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
13447   }
13448 }
13449 
13450 void Assembler::sarq(Register dst) {
13451   int encode = prefixq_and_encode(dst->encoding());
13452   emit_int16((unsigned char)0xD3, (0xF8 | encode));
13453 }
13454 #endif
13455 
13456 void Assembler::sbbq(Address dst, int32_t imm32) {
13457   InstructionMark im(this);
13458   prefixq(dst);
13459   emit_arith_operand(0x81, rbx, dst, imm32);
13460 }
13461 
13462 void Assembler::sbbq(Register dst, int32_t imm32) {
13463   (void) prefixq_and_encode(dst->encoding());
13464   emit_arith(0x81, 0xD8, dst, imm32);
13465 }
13466 
13467 void Assembler::sbbq(Register dst, Address src) {
13468   InstructionMark im(this);
13469   emit_int16(get_prefixq(src, dst), 0x1B);
13470   emit_operand(dst, src);
13471 }
13472 
13473 void Assembler::sbbq(Register dst, Register src) {
13474   (void) prefixq_and_encode(dst->encoding(), src->encoding());
13475   emit_arith(0x1B, 0xC0, dst, src);
13476 }
13477 
13478 void Assembler::shlq(Register dst, int imm8) {
13479   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13480   int encode = prefixq_and_encode(dst->encoding());
13481   if (imm8 == 1) {
13482     emit_int16((unsigned char)0xD1, (0xE0 | encode));
13483   } else {
13484     emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13485   }
13486 }
13487 
13488 void Assembler::shlq(Register dst) {
13489   int encode = prefixq_and_encode(dst->encoding());
13490   emit_int16((unsigned char)0xD3, (0xE0 | encode));
13491 }
13492 
13493 void Assembler::shrq(Register dst, int imm8) {
13494   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13495   int encode = prefixq_and_encode(dst->encoding());
13496   if (imm8 == 1) {
13497     emit_int16((unsigned char)0xD1, (0xE8 | encode));
13498   }
13499   else {
13500     emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
13501   }
13502 }
13503 
13504 void Assembler::shrq(Register dst) {
13505   int encode = prefixq_and_encode(dst->encoding());
13506   emit_int16((unsigned char)0xD3, 0xE8 | encode);
13507 }
13508 
13509 void Assembler::shrq(Address dst) {
13510   InstructionMark im(this);
13511   emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13512   emit_operand(as_Register(5), dst);
13513 }
13514 
13515 void Assembler::shrq(Address dst, int imm8) {
13516   InstructionMark im(this);
13517   assert(isShiftCount(imm8 >> 1), "illegal shift count");
13518   if (imm8 == 1) {
13519     emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13520     emit_operand(as_Register(5), dst);
13521   }
13522   else {
13523     emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13524     emit_operand(as_Register(5), dst);
13525     emit_int8(imm8);
13526   }
13527 }
13528 
13529 void Assembler::subq(Address dst, int32_t imm32) {
13530   InstructionMark im(this);
13531   prefixq(dst);
13532   emit_arith_operand(0x81, rbp, dst, imm32);
13533 }
13534 
13535 void Assembler::subq(Address dst, Register src) {
13536   InstructionMark im(this);
13537   emit_int16(get_prefixq(dst, src), 0x29);
13538   emit_operand(src, dst);
13539 }
13540 
13541 void Assembler::subq(Register dst, int32_t imm32) {
13542   (void) prefixq_and_encode(dst->encoding());
13543   emit_arith(0x81, 0xE8, dst, imm32);
13544 }
13545 
13546 // Force generation of a 4 byte immediate value even if it fits into 8bit
13547 void Assembler::subq_imm32(Register dst, int32_t imm32) {
13548   (void) prefixq_and_encode(dst->encoding());
13549   emit_arith_imm32(0x81, 0xE8, dst, imm32);
13550 }
13551 
13552 void Assembler::subq(Register dst, Address src) {
13553   InstructionMark im(this);
13554   emit_int16(get_prefixq(src, dst), 0x2B);
13555   emit_operand(dst, src);
13556 }
13557 
13558 void Assembler::subq(Register dst, Register src) {
13559   (void) prefixq_and_encode(dst->encoding(), src->encoding());
13560   emit_arith(0x2B, 0xC0, dst, src);
13561 }
13562 
13563 void Assembler::testq(Address dst, int32_t imm32) {
13564   if (imm32 >= 0) {
13565     testl(dst, imm32);
13566     return;
13567   }
13568   InstructionMark im(this);
13569   emit_int16(get_prefixq(dst), (unsigned char)0xF7);
13570   emit_operand(as_Register(0), dst);
13571   emit_int32(imm32);
13572 }
13573 
13574 void Assembler::testq(Register dst, int32_t imm32) {
13575   if (imm32 >= 0) {
13576     testl(dst, imm32);
13577     return;
13578   }
13579   // not using emit_arith because test
13580   // doesn't support sign-extension of
13581   // 8bit operands
13582   if (dst == rax) {
13583     prefix(REX_W);
13584     emit_int8((unsigned char)0xA9);
13585     emit_int32(imm32);
13586   } else {
13587     int encode = dst->encoding();
13588     encode = prefixq_and_encode(encode);
13589     emit_int16((unsigned char)0xF7, (0xC0 | encode));
13590     emit_int32(imm32);
13591   }
13592 }
13593 
13594 void Assembler::testq(Register dst, Register src) {
13595   (void) prefixq_and_encode(dst->encoding(), src->encoding());
13596   emit_arith(0x85, 0xC0, dst, src);
13597 }
13598 
13599 void Assembler::testq(Register dst, Address src) {
13600   InstructionMark im(this);
13601   emit_int16(get_prefixq(src, dst), (unsigned char)0x85);
13602   emit_operand(dst, src);
13603 }
13604 
13605 void Assembler::xaddq(Address dst, Register src) {
13606   InstructionMark im(this);
13607   emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1);
13608   emit_operand(src, dst);
13609 }
13610 
13611 void Assembler::xchgq(Register dst, Address src) {
13612   InstructionMark im(this);
13613   emit_int16(get_prefixq(src, dst), (unsigned char)0x87);
13614   emit_operand(dst, src);
13615 }
13616 
13617 void Assembler::xchgq(Register dst, Register src) {
13618   int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13619   emit_int16((unsigned char)0x87, (0xc0 | encode));
13620 }
13621 
13622 void Assembler::xorq(Register dst, Register src) {
13623   (void) prefixq_and_encode(dst->encoding(), src->encoding());
13624   emit_arith(0x33, 0xC0, dst, src);
13625 }
13626 
13627 void Assembler::xorq(Register dst, Address src) {
13628   InstructionMark im(this);
13629   emit_int16(get_prefixq(src, dst), 0x33);
13630   emit_operand(dst, src);
13631 }
13632 
13633 void Assembler::xorq(Register dst, int32_t imm32) {
13634   (void) prefixq_and_encode(dst->encoding());
13635   emit_arith(0x81, 0xF0, dst, imm32);
13636 }
13637 
13638 void Assembler::xorq(Address dst, int32_t imm32) {
13639   InstructionMark im(this);
13640   prefixq(dst);
13641   emit_arith_operand(0x81, as_Register(6), dst, imm32);
13642 }
13643 
13644 void Assembler::xorq(Address dst, Register src) {
13645   InstructionMark im(this);
13646   emit_int16(get_prefixq(dst, src), 0x31);
13647   emit_operand(src, dst);
13648 }
13649 
13650 #endif // !LP64
13651 
13652 void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) {
13653   if (VM_Version::supports_evex()) {
13654     _tuple_type = tuple_type;
13655     _input_size_in_bits = input_size_in_bits;
13656   }
13657 }