1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "memory/universe.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/objectMonitor.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/sharedRuntime.hpp"
36 #include "runtime/stubRoutines.hpp"
37 #include "runtime/vm_version.hpp"
38 #include "utilities/checkedCast.hpp"
39 #include "utilities/macros.hpp"
40
41 #ifdef PRODUCT
42 #define BLOCK_COMMENT(str) /* nothing */
43 #define STOP(error) stop(error)
44 #else
45 #define BLOCK_COMMENT(str) block_comment(str)
46 #define STOP(error) block_comment(error); stop(error)
47 #endif
48
49 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
50 // Implementation of AddressLiteral
51
52 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
53 static const unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
54 // -----------------Table 4.5 -------------------- //
55 16, 32, 64, // EVEX_FV(0)
56 4, 4, 4, // EVEX_FV(1) - with Evex.b
57 16, 32, 64, // EVEX_FV(2) - with Evex.w
58 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
59 8, 16, 32, // EVEX_HV(0)
60 4, 4, 4, // EVEX_HV(1) - with Evex.b
61 // -----------------Table 4.6 -------------------- //
62 16, 32, 64, // EVEX_FVM(0)
63 1, 1, 1, // EVEX_T1S(0)
64 2, 2, 2, // EVEX_T1S(1)
65 4, 4, 4, // EVEX_T1S(2)
66 8, 8, 8, // EVEX_T1S(3)
67 4, 4, 4, // EVEX_T1F(0)
68 8, 8, 8, // EVEX_T1F(1)
69 8, 8, 8, // EVEX_T2(0)
70 0, 16, 16, // EVEX_T2(1)
71 0, 16, 16, // EVEX_T4(0)
72 0, 0, 32, // EVEX_T4(1)
73 0, 0, 32, // EVEX_T8(0)
74 8, 16, 32, // EVEX_HVM(0)
75 4, 8, 16, // EVEX_QVM(0)
76 2, 4, 8, // EVEX_OVM(0)
77 16, 16, 16, // EVEX_M128(0)
78 8, 32, 64, // EVEX_DUP(0)
79 0, 0, 0 // EVEX_NTUP
80 };
81
82 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
83 _is_lval = false;
84 _target = target;
85 switch (rtype) {
86 case relocInfo::oop_type:
87 case relocInfo::metadata_type:
88 // Oops are a special case. Normally they would be their own section
89 // but in cases like icBuffer they are literals in the code stream that
90 // we don't have a section for. We use none so that we get a literal address
91 // which is always patchable.
92 break;
93 case relocInfo::external_word_type:
94 _rspec = external_word_Relocation::spec(target);
95 break;
96 case relocInfo::internal_word_type:
97 _rspec = internal_word_Relocation::spec(target);
98 break;
99 case relocInfo::opt_virtual_call_type:
100 _rspec = opt_virtual_call_Relocation::spec();
101 break;
102 case relocInfo::static_call_type:
103 _rspec = static_call_Relocation::spec();
104 break;
105 case relocInfo::runtime_call_type:
106 _rspec = runtime_call_Relocation::spec();
107 break;
108 case relocInfo::poll_type:
109 case relocInfo::poll_return_type:
110 _rspec = Relocation::spec_simple(rtype);
111 break;
112 case relocInfo::none:
113 break;
114 default:
115 ShouldNotReachHere();
116 break;
117 }
118 }
119
120 // Implementation of Address
121
122 #ifdef _LP64
123
124 Address Address::make_array(ArrayAddress adr) {
125 // Not implementable on 64bit machines
126 // Should have been handled higher up the call chain.
127 ShouldNotReachHere();
128 return Address();
129 }
130
131 // exceedingly dangerous constructor
132 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
133 _base = noreg;
134 _index = noreg;
135 _scale = no_scale;
136 _disp = disp;
137 _xmmindex = xnoreg;
138 _isxmmindex = false;
139 switch (rtype) {
140 case relocInfo::external_word_type:
141 _rspec = external_word_Relocation::spec(loc);
142 break;
143 case relocInfo::internal_word_type:
144 _rspec = internal_word_Relocation::spec(loc);
145 break;
146 case relocInfo::runtime_call_type:
147 // HMM
148 _rspec = runtime_call_Relocation::spec();
149 break;
150 case relocInfo::poll_type:
151 case relocInfo::poll_return_type:
152 _rspec = Relocation::spec_simple(rtype);
153 break;
154 case relocInfo::none:
155 break;
156 default:
157 ShouldNotReachHere();
158 }
159 }
160 #else // LP64
161
162 Address Address::make_array(ArrayAddress adr) {
163 AddressLiteral base = adr.base();
164 Address index = adr.index();
165 assert(index._disp == 0, "must not have disp"); // maybe it can?
166 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
167 array._rspec = base._rspec;
168 return array;
169 }
170
171 // exceedingly dangerous constructor
172 Address::Address(address loc, RelocationHolder spec) {
173 _base = noreg;
174 _index = noreg;
175 _scale = no_scale;
176 _disp = (intptr_t) loc;
177 _rspec = spec;
178 _xmmindex = xnoreg;
179 _isxmmindex = false;
180 }
181
182 #endif // _LP64
183
184
185
186 // Convert the raw encoding form into the form expected by the constructor for
187 // Address. An index of 4 (rsp) corresponds to having no index, so convert
188 // that to noreg for the Address constructor.
189 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
190 RelocationHolder rspec = RelocationHolder::none;
191 if (disp_reloc != relocInfo::none) {
192 rspec = Relocation::spec_simple(disp_reloc);
193 }
194 bool valid_index = index != rsp->encoding();
195 if (valid_index) {
196 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
197 madr._rspec = rspec;
198 return madr;
199 } else {
200 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
201 madr._rspec = rspec;
202 return madr;
203 }
204 }
205
206 // Implementation of Assembler
207
208 int AbstractAssembler::code_fill_byte() {
209 return (u_char)'\xF4'; // hlt
210 }
211
212 void Assembler::init_attributes(void) {
213 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
214 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
215 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
216 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
217 NOT_LP64(_is_managed = false;)
218 _attributes = nullptr;
219 }
220
221 void Assembler::set_attributes(InstructionAttr* attributes) {
222 // Record the assembler in the attributes, so the attributes destructor can
223 // clear the assembler's attributes, cleaning up the otherwise dangling
224 // pointer. gcc13 has a false positive warning, because it doesn't tie that
225 // cleanup to the assignment of _attributes here.
226 attributes->set_current_assembler(this);
227 PRAGMA_DIAG_PUSH
228 PRAGMA_DANGLING_POINTER_IGNORED
229 _attributes = attributes;
230 PRAGMA_DIAG_POP
231 }
232
233 void Assembler::membar(Membar_mask_bits order_constraint) {
234 // We only have to handle StoreLoad
235 if (order_constraint & StoreLoad) {
236 // All usable chips support "locked" instructions which suffice
237 // as barriers, and are much faster than the alternative of
238 // using cpuid instruction. We use here a locked add [esp-C],0.
239 // This is conveniently otherwise a no-op except for blowing
240 // flags, and introducing a false dependency on target memory
241 // location. We can't do anything with flags, but we can avoid
242 // memory dependencies in the current method by locked-adding
243 // somewhere else on the stack. Doing [esp+C] will collide with
244 // something on stack in current method, hence we go for [esp-C].
245 // It is convenient since it is almost always in data cache, for
246 // any small C. We need to step back from SP to avoid data
247 // dependencies with other things on below SP (callee-saves, for
248 // example). Without a clear way to figure out the minimal safe
249 // distance from SP, it makes sense to step back the complete
250 // cache line, as this will also avoid possible second-order effects
251 // with locked ops against the cache line. Our choice of offset
252 // is bounded by x86 operand encoding, which should stay within
253 // [-128; +127] to have the 8-byte displacement encoding.
254 //
255 // Any change to this code may need to revisit other places in
256 // the code where this idiom is used, in particular the
257 // orderAccess code.
258
259 int offset = -VM_Version::L1_line_size();
260 if (offset < -128) {
261 offset = -128;
262 }
263
264 lock();
265 addl(Address(rsp, offset), 0);// Assert the lock# signal here
266 }
267 }
268
269 // make this go away someday
270 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
271 if (rtype == relocInfo::none)
272 emit_int32(data);
273 else
274 emit_data(data, Relocation::spec_simple(rtype), format);
275 }
276
277 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
278 assert(imm_operand == 0, "default format must be immediate in this file");
279 assert(inst_mark() != nullptr, "must be inside InstructionMark");
280 if (rspec.type() != relocInfo::none) {
281 #ifdef ASSERT
282 check_relocation(rspec, format);
283 #endif
284 // Do not use AbstractAssembler::relocate, which is not intended for
285 // embedded words. Instead, relocate to the enclosing instruction.
286
287 // hack. call32 is too wide for mask so use disp32
288 if (format == call32_operand)
289 code_section()->relocate(inst_mark(), rspec, disp32_operand);
290 else
291 code_section()->relocate(inst_mark(), rspec, format);
292 }
293 emit_int32(data);
294 }
295
296 static int encode(Register r) {
297 int enc = r->encoding();
298 if (enc >= 8) {
299 enc -= 8;
300 }
301 return enc;
302 }
303
304 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
305 assert(dst->has_byte_register(), "must have byte register");
306 assert(isByte(op1) && isByte(op2), "wrong opcode");
307 assert(isByte(imm8), "not a byte");
308 assert((op1 & 0x01) == 0, "should be 8bit operation");
309 emit_int24(op1, (op2 | encode(dst)), imm8);
310 }
311
312
313 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
314 assert(isByte(op1) && isByte(op2), "wrong opcode");
315 assert(op1 == 0x81, "Unexpected opcode");
316 if (is8bit(imm32)) {
317 emit_int24(op1 | 0x02, // set sign bit
318 op2 | encode(dst),
319 imm32 & 0xFF);
320 } else if (dst == rax) {
321 switch (op2) {
322 case 0xD0: emit_int8(0x15); break; // adc
323 case 0xC0: emit_int8(0x05); break; // add
324 case 0xE0: emit_int8(0x25); break; // and
325 case 0xF8: emit_int8(0x3D); break; // cmp
326 case 0xC8: emit_int8(0x0D); break; // or
327 case 0xD8: emit_int8(0x1D); break; // sbb
328 case 0xE8: emit_int8(0x2D); break; // sub
329 case 0xF0: emit_int8(0x35); break; // xor
330 default: ShouldNotReachHere();
331 }
332 emit_int32(imm32);
333 } else {
334 emit_int16(op1, (op2 | encode(dst)));
335 emit_int32(imm32);
336 }
337 }
338
339 // Force generation of a 4 byte immediate value even if it fits into 8bit
340 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
341 assert(isByte(op1) && isByte(op2), "wrong opcode");
342 assert((op1 & 0x01) == 1, "should be 32bit operation");
343 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
344 emit_int16(op1, (op2 | encode(dst)));
345 emit_int32(imm32);
346 }
347
348 // immediate-to-memory forms
349 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
350 assert((op1 & 0x01) == 1, "should be 32bit operation");
351 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
352 if (is8bit(imm32)) {
353 emit_int8(op1 | 0x02); // set sign bit
354 emit_operand(rm, adr, 1);
355 emit_int8(imm32 & 0xFF);
356 } else {
357 emit_int8(op1);
358 emit_operand(rm, adr, 4);
359 emit_int32(imm32);
360 }
361 }
362
363 void Assembler::emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32) {
364 assert(op1 == 0x81, "unexpected opcode");
365 emit_int8(op1);
366 emit_operand(rm, adr, 4);
367 emit_int32(imm32);
368 }
369
370 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
371 assert(isByte(op1) && isByte(op2), "wrong opcode");
372 emit_int16(op1, (op2 | encode(dst) << 3 | encode(src)));
373 }
374
375
376 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
377 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
378 int mod_idx = 0;
379 // We will test if the displacement fits the compressed format and if so
380 // apply the compression to the displacement iff the result is8bit.
381 if (VM_Version::supports_evex() && is_evex_inst) {
382 switch (cur_tuple_type) {
383 case EVEX_FV:
384 if ((cur_encoding & VEX_W) == VEX_W) {
385 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
386 } else {
387 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
388 }
389 break;
390
391 case EVEX_HV:
392 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
393 break;
394
395 case EVEX_FVM:
396 break;
397
398 case EVEX_T1S:
399 switch (in_size_in_bits) {
400 case EVEX_8bit:
401 break;
402
403 case EVEX_16bit:
404 mod_idx = 1;
405 break;
406
407 case EVEX_32bit:
408 mod_idx = 2;
409 break;
410
411 case EVEX_64bit:
412 mod_idx = 3;
413 break;
414 }
415 break;
416
417 case EVEX_T1F:
418 case EVEX_T2:
419 case EVEX_T4:
420 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
421 break;
422
423 case EVEX_T8:
424 break;
425
426 case EVEX_HVM:
427 break;
428
429 case EVEX_QVM:
430 break;
431
432 case EVEX_OVM:
433 break;
434
435 case EVEX_M128:
436 break;
437
438 case EVEX_DUP:
439 break;
440
441 default:
442 assert(0, "no valid evex tuple_table entry");
443 break;
444 }
445
446 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
447 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
448 if ((disp % disp_factor) == 0) {
449 int new_disp = disp / disp_factor;
450 if ((-0x80 <= new_disp && new_disp < 0x80)) {
451 disp = new_disp;
452 }
453 } else {
454 return false;
455 }
456 }
457 }
458 return (-0x80 <= disp && disp < 0x80);
459 }
460
461
462 bool Assembler::emit_compressed_disp_byte(int &disp) {
463 int mod_idx = 0;
464 // We will test if the displacement fits the compressed format and if so
465 // apply the compression to the displacement iff the result is8bit.
466 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
467 int evex_encoding = _attributes->get_evex_encoding();
468 int tuple_type = _attributes->get_tuple_type();
469 switch (tuple_type) {
470 case EVEX_FV:
471 if ((evex_encoding & VEX_W) == VEX_W) {
472 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
473 } else {
474 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
475 }
476 break;
477
478 case EVEX_HV:
479 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
480 break;
481
482 case EVEX_FVM:
483 break;
484
485 case EVEX_T1S:
486 switch (_attributes->get_input_size()) {
487 case EVEX_8bit:
488 break;
489
490 case EVEX_16bit:
491 mod_idx = 1;
492 break;
493
494 case EVEX_32bit:
495 mod_idx = 2;
496 break;
497
498 case EVEX_64bit:
499 mod_idx = 3;
500 break;
501 }
502 break;
503
504 case EVEX_T1F:
505 case EVEX_T2:
506 case EVEX_T4:
507 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
508 break;
509
510 case EVEX_T8:
511 break;
512
513 case EVEX_HVM:
514 break;
515
516 case EVEX_QVM:
517 break;
518
519 case EVEX_OVM:
520 break;
521
522 case EVEX_M128:
523 break;
524
525 case EVEX_DUP:
526 break;
527
528 default:
529 assert(0, "no valid evex tuple_table entry");
530 break;
531 }
532
533 int vector_len = _attributes->get_vector_len();
534 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
535 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
536 if ((disp % disp_factor) == 0) {
537 int new_disp = disp / disp_factor;
538 if (is8bit(new_disp)) {
539 disp = new_disp;
540 }
541 } else {
542 return false;
543 }
544 }
545 }
546 return is8bit(disp);
547 }
548
549 static bool is_valid_encoding(int reg_enc) {
550 return reg_enc >= 0;
551 }
552
553 static int raw_encode(Register reg) {
554 assert(reg == noreg || reg->is_valid(), "sanity");
555 int reg_enc = reg->raw_encoding();
556 assert(reg_enc == -1 || is_valid_encoding(reg_enc), "sanity");
557 return reg_enc;
558 }
559
560 static int raw_encode(XMMRegister xmmreg) {
561 assert(xmmreg == xnoreg || xmmreg->is_valid(), "sanity");
562 int xmmreg_enc = xmmreg->raw_encoding();
563 assert(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc), "sanity");
564 return xmmreg_enc;
565 }
566
567 static int raw_encode(KRegister kreg) {
568 assert(kreg == knoreg || kreg->is_valid(), "sanity");
569 int kreg_enc = kreg->raw_encoding();
570 assert(kreg_enc == -1 || is_valid_encoding(kreg_enc), "sanity");
571 return kreg_enc;
572 }
573
574 static int modrm_encoding(int mod, int dst_enc, int src_enc) {
575 return (mod & 3) << 6 | (dst_enc & 7) << 3 | (src_enc & 7);
576 }
577
578 static int sib_encoding(Address::ScaleFactor scale, int index_enc, int base_enc) {
579 return (scale & 3) << 6 | (index_enc & 7) << 3 | (base_enc & 7);
580 }
581
582 inline void Assembler::emit_modrm(int mod, int dst_enc, int src_enc) {
583 assert((mod & 3) != 0b11, "forbidden");
584 int modrm = modrm_encoding(mod, dst_enc, src_enc);
585 emit_int8(modrm);
586 }
587
588 inline void Assembler::emit_modrm_disp8(int mod, int dst_enc, int src_enc,
589 int disp) {
590 int modrm = modrm_encoding(mod, dst_enc, src_enc);
591 emit_int16(modrm, disp & 0xFF);
592 }
593
594 inline void Assembler::emit_modrm_sib(int mod, int dst_enc, int src_enc,
595 Address::ScaleFactor scale, int index_enc, int base_enc) {
596 int modrm = modrm_encoding(mod, dst_enc, src_enc);
597 int sib = sib_encoding(scale, index_enc, base_enc);
598 emit_int16(modrm, sib);
599 }
600
601 inline void Assembler::emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
602 Address::ScaleFactor scale, int index_enc, int base_enc,
603 int disp) {
604 int modrm = modrm_encoding(mod, dst_enc, src_enc);
605 int sib = sib_encoding(scale, index_enc, base_enc);
606 emit_int24(modrm, sib, disp & 0xFF);
607 }
608
609 void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc,
610 Address::ScaleFactor scale, int disp,
611 RelocationHolder const& rspec,
612 int post_addr_length) {
613 bool no_relocation = (rspec.type() == relocInfo::none);
614
615 if (is_valid_encoding(base_enc)) {
616 if (is_valid_encoding(index_enc)) {
617 assert(scale != Address::no_scale, "inconsistent address");
618 // [base + index*scale + disp]
619 if (disp == 0 && no_relocation &&
620 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
621 // [base + index*scale]
622 // [00 reg 100][ss index base]
623 emit_modrm_sib(0b00, reg_enc, 0b100,
624 scale, index_enc, base_enc);
625 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
626 // [base + index*scale + imm8]
627 // [01 reg 100][ss index base] imm8
628 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
629 scale, index_enc, base_enc,
630 disp);
631 } else {
632 // [base + index*scale + disp32]
633 // [10 reg 100][ss index base] disp32
634 emit_modrm_sib(0b10, reg_enc, 0b100,
635 scale, index_enc, base_enc);
636 emit_data(disp, rspec, disp32_operand);
637 }
638 } else if (base_enc == rsp->encoding() LP64_ONLY(|| base_enc == r12->encoding())) {
639 // [rsp + disp]
640 if (disp == 0 && no_relocation) {
641 // [rsp]
642 // [00 reg 100][00 100 100]
643 emit_modrm_sib(0b00, reg_enc, 0b100,
644 Address::times_1, 0b100, 0b100);
645 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
646 // [rsp + imm8]
647 // [01 reg 100][00 100 100] disp8
648 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
649 Address::times_1, 0b100, 0b100,
650 disp);
651 } else {
652 // [rsp + imm32]
653 // [10 reg 100][00 100 100] disp32
654 emit_modrm_sib(0b10, reg_enc, 0b100,
655 Address::times_1, 0b100, 0b100);
656 emit_data(disp, rspec, disp32_operand);
657 }
658 } else {
659 // [base + disp]
660 assert(base_enc != rsp->encoding() LP64_ONLY(&& base_enc != r12->encoding()), "illegal addressing mode");
661 if (disp == 0 && no_relocation &&
662 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
663 // [base]
664 // [00 reg base]
665 emit_modrm(0, reg_enc, base_enc);
666 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
667 // [base + disp8]
668 // [01 reg base] disp8
669 emit_modrm_disp8(0b01, reg_enc, base_enc,
670 disp);
671 } else {
672 // [base + disp32]
673 // [10 reg base] disp32
674 emit_modrm(0b10, reg_enc, base_enc);
675 emit_data(disp, rspec, disp32_operand);
676 }
677 }
678 } else {
679 if (is_valid_encoding(index_enc)) {
680 assert(scale != Address::no_scale, "inconsistent address");
681 // base == noreg
682 // [index*scale + disp]
683 // [00 reg 100][ss index 101] disp32
684 emit_modrm_sib(0b00, reg_enc, 0b100,
685 scale, index_enc, 0b101 /* no base */);
686 emit_data(disp, rspec, disp32_operand);
687 } else if (!no_relocation) {
688 // base == noreg, index == noreg
689 // [disp] (64bit) RIP-RELATIVE (32bit) abs
690 // [00 reg 101] disp32
691
692 emit_modrm(0b00, reg_enc, 0b101 /* no base */);
693 // Note that the RIP-rel. correction applies to the generated
694 // disp field, but _not_ to the target address in the rspec.
695
696 // disp was created by converting the target address minus the pc
697 // at the start of the instruction. That needs more correction here.
698 // intptr_t disp = target - next_ip;
699 assert(inst_mark() != nullptr, "must be inside InstructionMark");
700 address next_ip = pc() + sizeof(int32_t) + post_addr_length;
701 int64_t adjusted = disp;
702 // Do rip-rel adjustment for 64bit
703 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
704 assert(is_simm32(adjusted),
705 "must be 32bit offset (RIP relative address)");
706 emit_data((int32_t) adjusted, rspec, disp32_operand);
707
708 } else {
709 // base == noreg, index == noreg, no_relocation == true
710 // 32bit never did this, did everything as the rip-rel/disp code above
711 // [disp] ABSOLUTE
712 // [00 reg 100][00 100 101] disp32
713 emit_modrm_sib(0b00, reg_enc, 0b100 /* no base */,
714 Address::times_1, 0b100, 0b101);
715 emit_data(disp, rspec, disp32_operand);
716 }
717 }
718 }
719
720 void Assembler::emit_operand(Register reg, Register base, Register index,
721 Address::ScaleFactor scale, int disp,
722 RelocationHolder const& rspec,
723 int post_addr_length) {
724 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
725 emit_operand_helper(raw_encode(reg), raw_encode(base), raw_encode(index),
726 scale, disp, rspec, post_addr_length);
727
728 }
729 void Assembler::emit_operand(XMMRegister xmmreg, Register base, Register index,
730 Address::ScaleFactor scale, int disp,
731 RelocationHolder const& rspec,
732 int post_addr_length) {
733 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
734 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
735 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(index),
736 scale, disp, rspec, post_addr_length);
737 }
738
739 void Assembler::emit_operand(XMMRegister xmmreg, Register base, XMMRegister xmmindex,
740 Address::ScaleFactor scale, int disp,
741 RelocationHolder const& rspec,
742 int post_addr_length) {
743 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
744 assert(xmmindex->encoding() < 16 || UseAVX > 2, "not supported");
745 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(xmmindex),
746 scale, disp, rspec, post_addr_length);
747 }
748
749 void Assembler::emit_operand(KRegister kreg, Address adr,
750 int post_addr_length) {
751 emit_operand(kreg, adr._base, adr._index, adr._scale, adr._disp,
752 adr._rspec,
753 post_addr_length);
754 }
755
756 void Assembler::emit_operand(KRegister kreg, Register base, Register index,
757 Address::ScaleFactor scale, int disp,
758 RelocationHolder const& rspec,
759 int post_addr_length) {
760 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
761 emit_operand_helper(raw_encode(kreg), raw_encode(base), raw_encode(index),
762 scale, disp, rspec, post_addr_length);
763 }
764
765 // Secret local extension to Assembler::WhichOperand:
766 #define end_pc_operand (_WhichOperand_limit)
767
768 address Assembler::locate_operand(address inst, WhichOperand which) {
769 // Decode the given instruction, and return the address of
770 // an embedded 32-bit operand word.
771
772 // If "which" is disp32_operand, selects the displacement portion
773 // of an effective address specifier.
774 // If "which" is imm64_operand, selects the trailing immediate constant.
775 // If "which" is call32_operand, selects the displacement of a call or jump.
776 // Caller is responsible for ensuring that there is such an operand,
777 // and that it is 32/64 bits wide.
778
779 // If "which" is end_pc_operand, find the end of the instruction.
780
781 address ip = inst;
782 bool is_64bit = false;
783
784 debug_only(bool has_disp32 = false);
785 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
786
787 again_after_prefix:
788 switch (0xFF & *ip++) {
789
790 // These convenience macros generate groups of "case" labels for the switch.
791 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
792 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
793 case (x)+4: case (x)+5: case (x)+6: case (x)+7
794 #define REP16(x) REP8((x)+0): \
795 case REP8((x)+8)
796
797 case CS_segment:
798 case SS_segment:
799 case DS_segment:
800 case ES_segment:
801 case FS_segment:
802 case GS_segment:
803 // Seems dubious
804 LP64_ONLY(assert(false, "shouldn't have that prefix"));
805 assert(ip == inst+1, "only one prefix allowed");
806 goto again_after_prefix;
807
808 case 0x67:
809 case REX:
810 case REX_B:
811 case REX_X:
812 case REX_XB:
813 case REX_R:
814 case REX_RB:
815 case REX_RX:
816 case REX_RXB:
817 NOT_LP64(assert(false, "64bit prefixes"));
818 goto again_after_prefix;
819
820 case REX_W:
821 case REX_WB:
822 case REX_WX:
823 case REX_WXB:
824 case REX_WR:
825 case REX_WRB:
826 case REX_WRX:
827 case REX_WRXB:
828 NOT_LP64(assert(false, "64bit prefixes"));
829 is_64bit = true;
830 goto again_after_prefix;
831
832 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
833 case 0x88: // movb a, r
834 case 0x89: // movl a, r
835 case 0x8A: // movb r, a
836 case 0x8B: // movl r, a
837 case 0x8F: // popl a
838 debug_only(has_disp32 = true);
839 break;
840
841 case 0x68: // pushq #32
842 if (which == end_pc_operand) {
843 return ip + 4;
844 }
845 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
846 return ip; // not produced by emit_operand
847
848 case 0x66: // movw ... (size prefix)
849 again_after_size_prefix2:
850 switch (0xFF & *ip++) {
851 case REX:
852 case REX_B:
853 case REX_X:
854 case REX_XB:
855 case REX_R:
856 case REX_RB:
857 case REX_RX:
858 case REX_RXB:
859 case REX_W:
860 case REX_WB:
861 case REX_WX:
862 case REX_WXB:
863 case REX_WR:
864 case REX_WRB:
865 case REX_WRX:
866 case REX_WRXB:
867 NOT_LP64(assert(false, "64bit prefix found"));
868 goto again_after_size_prefix2;
869 case 0x8B: // movw r, a
870 case 0x89: // movw a, r
871 debug_only(has_disp32 = true);
872 break;
873 case 0xC7: // movw a, #16
874 debug_only(has_disp32 = true);
875 tail_size = 2; // the imm16
876 break;
877 case 0x0F: // several SSE/SSE2 variants
878 ip--; // reparse the 0x0F
879 goto again_after_prefix;
880 default:
881 ShouldNotReachHere();
882 }
883 break;
884
885 case REP8(0xB8): // movl/q r, #32/#64(oop?)
886 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
887 // these asserts are somewhat nonsensical
888 #ifndef _LP64
889 assert(which == imm_operand || which == disp32_operand,
890 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
891 #else
892 assert((which == call32_operand || which == imm_operand) && is_64bit ||
893 which == narrow_oop_operand && !is_64bit,
894 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
895 #endif // _LP64
896 return ip;
897
898 case 0x69: // imul r, a, #32
899 case 0xC7: // movl a, #32(oop?)
900 tail_size = 4;
901 debug_only(has_disp32 = true); // has both kinds of operands!
902 break;
903
904 case 0x0F: // movx..., etc.
905 switch (0xFF & *ip++) {
906 case 0x3A: // pcmpestri
907 tail_size = 1;
908 case 0x38: // ptest, pmovzxbw
909 ip++; // skip opcode
910 debug_only(has_disp32 = true); // has both kinds of operands!
911 break;
912
913 case 0x70: // pshufd r, r/a, #8
914 debug_only(has_disp32 = true); // has both kinds of operands!
915 case 0x73: // psrldq r, #8
916 tail_size = 1;
917 break;
918
919 case 0x10: // movups
920 case 0x11: // movups
921 case 0x12: // movlps
922 case 0x28: // movaps
923 case 0x2E: // ucomiss
924 case 0x2F: // comiss
925 case 0x54: // andps
926 case 0x55: // andnps
927 case 0x56: // orps
928 case 0x57: // xorps
929 case 0x58: // addpd
930 case 0x59: // mulpd
931 case 0x6E: // movd
932 case 0x7E: // movd
933 case 0x6F: // movdq
934 case 0x7F: // movdq
935 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
936 case 0xFE: // paddd
937 debug_only(has_disp32 = true);
938 break;
939
940 case 0xAD: // shrd r, a, %cl
941 case 0xAF: // imul r, a
942 case 0xBE: // movsbl r, a (movsxb)
943 case 0xBF: // movswl r, a (movsxw)
944 case 0xB6: // movzbl r, a (movzxb)
945 case 0xB7: // movzwl r, a (movzxw)
946 case REP16(0x40): // cmovl cc, r, a
947 case 0xB0: // cmpxchgb
948 case 0xB1: // cmpxchg
949 case 0xC1: // xaddl
950 case 0xC7: // cmpxchg8
951 case REP16(0x90): // setcc a
952 debug_only(has_disp32 = true);
953 // fall out of the switch to decode the address
954 break;
955
956 case 0xC4: // pinsrw r, a, #8
957 debug_only(has_disp32 = true);
958 case 0xC5: // pextrw r, r, #8
959 tail_size = 1; // the imm8
960 break;
961
962 case 0xAC: // shrd r, a, #8
963 debug_only(has_disp32 = true);
964 tail_size = 1; // the imm8
965 break;
966
967 case REP16(0x80): // jcc rdisp32
968 if (which == end_pc_operand) return ip + 4;
969 assert(which == call32_operand, "jcc has no disp32 or imm");
970 return ip;
971 default:
972 ShouldNotReachHere();
973 }
974 break;
975
976 case 0x81: // addl a, #32; addl r, #32
977 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
978 // on 32bit in the case of cmpl, the imm might be an oop
979 tail_size = 4;
980 debug_only(has_disp32 = true); // has both kinds of operands!
981 break;
982
983 case 0x83: // addl a, #8; addl r, #8
984 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
985 debug_only(has_disp32 = true); // has both kinds of operands!
986 tail_size = 1;
987 break;
988
989 case 0x15: // adc rax, #32
990 case 0x05: // add rax, #32
991 case 0x25: // and rax, #32
992 case 0x3D: // cmp rax, #32
993 case 0x0D: // or rax, #32
994 case 0x1D: // sbb rax, #32
995 case 0x2D: // sub rax, #32
996 case 0x35: // xor rax, #32
997 return which == end_pc_operand ? ip + 4 : ip;
998
999 case 0x9B:
1000 switch (0xFF & *ip++) {
1001 case 0xD9: // fnstcw a
1002 debug_only(has_disp32 = true);
1003 break;
1004 default:
1005 ShouldNotReachHere();
1006 }
1007 break;
1008
1009 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
1010 case REP4(0x10): // adc...
1011 case REP4(0x20): // and...
1012 case REP4(0x30): // xor...
1013 case REP4(0x08): // or...
1014 case REP4(0x18): // sbb...
1015 case REP4(0x28): // sub...
1016 case 0xF7: // mull a
1017 case 0x8D: // lea r, a
1018 case 0x87: // xchg r, a
1019 case REP4(0x38): // cmp...
1020 case 0x85: // test r, a
1021 debug_only(has_disp32 = true); // has both kinds of operands!
1022 break;
1023
1024 case 0xA8: // testb rax, #8
1025 return which == end_pc_operand ? ip + 1 : ip;
1026 case 0xA9: // testl/testq rax, #32
1027 return which == end_pc_operand ? ip + 4 : ip;
1028
1029 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
1030 case 0xC6: // movb a, #8
1031 case 0x80: // cmpb a, #8
1032 case 0x6B: // imul r, a, #8
1033 debug_only(has_disp32 = true); // has both kinds of operands!
1034 tail_size = 1; // the imm8
1035 break;
1036
1037 case 0xC4: // VEX_3bytes
1038 case 0xC5: // VEX_2bytes
1039 assert((UseAVX > 0), "shouldn't have VEX prefix");
1040 assert(ip == inst+1, "no prefixes allowed");
1041 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
1042 // but they have prefix 0x0F and processed when 0x0F processed above.
1043 //
1044 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
1045 // instructions (these instructions are not supported in 64-bit mode).
1046 // To distinguish them bits [7:6] are set in the VEX second byte since
1047 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
1048 // those VEX bits REX and vvvv bits are inverted.
1049 //
1050 // Fortunately C2 doesn't generate these instructions so we don't need
1051 // to check for them in product version.
1052
1053 // Check second byte
1054 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
1055
1056 int vex_opcode;
1057 // First byte
1058 if ((0xFF & *inst) == VEX_3bytes) {
1059 vex_opcode = VEX_OPCODE_MASK & *ip;
1060 ip++; // third byte
1061 is_64bit = ((VEX_W & *ip) == VEX_W);
1062 } else {
1063 vex_opcode = VEX_OPCODE_0F;
1064 }
1065 ip++; // opcode
1066 // To find the end of instruction (which == end_pc_operand).
1067 switch (vex_opcode) {
1068 case VEX_OPCODE_0F:
1069 switch (0xFF & *ip) {
1070 case 0x70: // pshufd r, r/a, #8
1071 case 0x71: // ps[rl|ra|ll]w r, #8
1072 case 0x72: // ps[rl|ra|ll]d r, #8
1073 case 0x73: // ps[rl|ra|ll]q r, #8
1074 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
1075 case 0xC4: // pinsrw r, r, r/a, #8
1076 case 0xC5: // pextrw r/a, r, #8
1077 case 0xC6: // shufp[s|d] r, r, r/a, #8
1078 tail_size = 1; // the imm8
1079 break;
1080 }
1081 break;
1082 case VEX_OPCODE_0F_3A:
1083 tail_size = 1;
1084 break;
1085 }
1086 ip++; // skip opcode
1087 debug_only(has_disp32 = true); // has both kinds of operands!
1088 break;
1089
1090 case 0x62: // EVEX_4bytes
1091 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
1092 assert(ip == inst+1, "no prefixes allowed");
1093 // no EVEX collisions, all instructions that have 0x62 opcodes
1094 // have EVEX versions and are subopcodes of 0x66
1095 ip++; // skip P0 and examine W in P1
1096 is_64bit = ((VEX_W & *ip) == VEX_W);
1097 ip++; // move to P2
1098 ip++; // skip P2, move to opcode
1099 // To find the end of instruction (which == end_pc_operand).
1100 switch (0xFF & *ip) {
1101 case 0x22: // pinsrd r, r/a, #8
1102 case 0x61: // pcmpestri r, r/a, #8
1103 case 0x70: // pshufd r, r/a, #8
1104 case 0x73: // psrldq r, #8
1105 case 0x1f: // evpcmpd/evpcmpq
1106 case 0x3f: // evpcmpb/evpcmpw
1107 tail_size = 1; // the imm8
1108 break;
1109 default:
1110 break;
1111 }
1112 ip++; // skip opcode
1113 debug_only(has_disp32 = true); // has both kinds of operands!
1114 break;
1115
1116 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
1117 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
1118 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
1119 case 0xDD: // fld_d a; fst_d a; fstp_d a
1120 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
1121 case 0xDF: // fild_d a; fistp_d a
1122 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
1123 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
1124 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
1125 debug_only(has_disp32 = true);
1126 break;
1127
1128 case 0xE8: // call rdisp32
1129 case 0xE9: // jmp rdisp32
1130 if (which == end_pc_operand) return ip + 4;
1131 assert(which == call32_operand, "call has no disp32 or imm");
1132 return ip;
1133
1134 case 0xF0: // Lock
1135 goto again_after_prefix;
1136
1137 case 0xF3: // For SSE
1138 case 0xF2: // For SSE2
1139 switch (0xFF & *ip++) {
1140 case REX:
1141 case REX_B:
1142 case REX_X:
1143 case REX_XB:
1144 case REX_R:
1145 case REX_RB:
1146 case REX_RX:
1147 case REX_RXB:
1148 case REX_W:
1149 case REX_WB:
1150 case REX_WX:
1151 case REX_WXB:
1152 case REX_WR:
1153 case REX_WRB:
1154 case REX_WRX:
1155 case REX_WRXB:
1156 NOT_LP64(assert(false, "found 64bit prefix"));
1157 ip++;
1158 default:
1159 ip++;
1160 }
1161 debug_only(has_disp32 = true); // has both kinds of operands!
1162 break;
1163
1164 default:
1165 ShouldNotReachHere();
1166
1167 #undef REP8
1168 #undef REP16
1169 }
1170
1171 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1172 #ifdef _LP64
1173 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1174 #else
1175 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1176 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1177 #endif // LP64
1178 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1179
1180 // parse the output of emit_operand
1181 int op2 = 0xFF & *ip++;
1182 int base = op2 & 0x07;
1183 int op3 = -1;
1184 const int b100 = 4;
1185 const int b101 = 5;
1186 if (base == b100 && (op2 >> 6) != 3) {
1187 op3 = 0xFF & *ip++;
1188 base = op3 & 0x07; // refetch the base
1189 }
1190 // now ip points at the disp (if any)
1191
1192 switch (op2 >> 6) {
1193 case 0:
1194 // [00 reg 100][ss index base]
1195 // [00 reg 100][00 100 esp]
1196 // [00 reg base]
1197 // [00 reg 100][ss index 101][disp32]
1198 // [00 reg 101] [disp32]
1199
1200 if (base == b101) {
1201 if (which == disp32_operand)
1202 return ip; // caller wants the disp32
1203 ip += 4; // skip the disp32
1204 }
1205 break;
1206
1207 case 1:
1208 // [01 reg 100][ss index base][disp8]
1209 // [01 reg 100][00 100 esp][disp8]
1210 // [01 reg base] [disp8]
1211 ip += 1; // skip the disp8
1212 break;
1213
1214 case 2:
1215 // [10 reg 100][ss index base][disp32]
1216 // [10 reg 100][00 100 esp][disp32]
1217 // [10 reg base] [disp32]
1218 if (which == disp32_operand)
1219 return ip; // caller wants the disp32
1220 ip += 4; // skip the disp32
1221 break;
1222
1223 case 3:
1224 // [11 reg base] (not a memory addressing mode)
1225 break;
1226 }
1227
1228 if (which == end_pc_operand) {
1229 return ip + tail_size;
1230 }
1231
1232 #ifdef _LP64
1233 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1234 #else
1235 assert(which == imm_operand, "instruction has only an imm field");
1236 #endif // LP64
1237 return ip;
1238 }
1239
1240 address Assembler::locate_next_instruction(address inst) {
1241 // Secretly share code with locate_operand:
1242 return locate_operand(inst, end_pc_operand);
1243 }
1244
1245
1246 #ifdef ASSERT
1247 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1248 address inst = inst_mark();
1249 assert(inst != nullptr && inst < pc(), "must point to beginning of instruction");
1250 address opnd;
1251
1252 Relocation* r = rspec.reloc();
1253 if (r->type() == relocInfo::none) {
1254 return;
1255 } else if (r->is_call() || format == call32_operand) {
1256 // assert(format == imm32_operand, "cannot specify a nonzero format");
1257 opnd = locate_operand(inst, call32_operand);
1258 } else if (r->is_data()) {
1259 assert(format == imm_operand || format == disp32_operand
1260 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1261 opnd = locate_operand(inst, (WhichOperand)format);
1262 } else {
1263 assert(format == imm_operand, "cannot specify a format");
1264 return;
1265 }
1266 assert(opnd == pc(), "must put operand where relocs can find it");
1267 }
1268 #endif // ASSERT
1269
1270 void Assembler::emit_operand(Register reg, Address adr, int post_addr_length) {
1271 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1272 }
1273
1274 void Assembler::emit_operand(XMMRegister reg, Address adr, int post_addr_length) {
1275 if (adr.isxmmindex()) {
1276 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec, post_addr_length);
1277 } else {
1278 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1279 }
1280 }
1281
1282 // Now the Assembler instructions (identical for 32/64 bits)
1283
1284 void Assembler::adcl(Address dst, int32_t imm32) {
1285 InstructionMark im(this);
1286 prefix(dst);
1287 emit_arith_operand(0x81, rdx, dst, imm32);
1288 }
1289
1290 void Assembler::adcl(Address dst, Register src) {
1291 InstructionMark im(this);
1292 prefix(dst, src);
1293 emit_int8(0x11);
1294 emit_operand(src, dst, 0);
1295 }
1296
1297 void Assembler::adcl(Register dst, int32_t imm32) {
1298 prefix(dst);
1299 emit_arith(0x81, 0xD0, dst, imm32);
1300 }
1301
1302 void Assembler::adcl(Register dst, Address src) {
1303 InstructionMark im(this);
1304 prefix(src, dst);
1305 emit_int8(0x13);
1306 emit_operand(dst, src, 0);
1307 }
1308
1309 void Assembler::adcl(Register dst, Register src) {
1310 (void) prefix_and_encode(dst->encoding(), src->encoding());
1311 emit_arith(0x13, 0xC0, dst, src);
1312 }
1313
1314 void Assembler::addl(Address dst, int32_t imm32) {
1315 InstructionMark im(this);
1316 prefix(dst);
1317 emit_arith_operand(0x81, rax, dst, imm32);
1318 }
1319
1320 void Assembler::addb(Address dst, int imm8) {
1321 InstructionMark im(this);
1322 prefix(dst);
1323 emit_int8((unsigned char)0x80);
1324 emit_operand(rax, dst, 1);
1325 emit_int8(imm8);
1326 }
1327
1328 void Assembler::addb(Address dst, Register src) {
1329 InstructionMark im(this);
1330 prefix(dst, src);
1331 emit_int8(0x00);
1332 emit_operand(src, dst, 0);
1333 }
1334
1335 void Assembler::addb(Register dst, int imm8) {
1336 (void) prefix_and_encode(dst->encoding(), true);
1337 emit_arith_b(0x80, 0xC0, dst, imm8);
1338 }
1339
1340 void Assembler::addw(Register dst, Register src) {
1341 emit_int8(0x66);
1342 (void)prefix_and_encode(dst->encoding(), src->encoding());
1343 emit_arith(0x03, 0xC0, dst, src);
1344 }
1345
1346 void Assembler::addw(Address dst, int imm16) {
1347 InstructionMark im(this);
1348 emit_int8(0x66);
1349 prefix(dst);
1350 emit_int8((unsigned char)0x81);
1351 emit_operand(rax, dst, 2);
1352 emit_int16(imm16);
1353 }
1354
1355 void Assembler::addw(Address dst, Register src) {
1356 InstructionMark im(this);
1357 emit_int8(0x66);
1358 prefix(dst, src);
1359 emit_int8(0x01);
1360 emit_operand(src, dst, 0);
1361 }
1362
1363 void Assembler::addl(Address dst, Register src) {
1364 InstructionMark im(this);
1365 prefix(dst, src);
1366 emit_int8(0x01);
1367 emit_operand(src, dst, 0);
1368 }
1369
1370 void Assembler::addl(Register dst, int32_t imm32) {
1371 prefix(dst);
1372 emit_arith(0x81, 0xC0, dst, imm32);
1373 }
1374
1375 void Assembler::addl(Register dst, Address src) {
1376 InstructionMark im(this);
1377 prefix(src, dst);
1378 emit_int8(0x03);
1379 emit_operand(dst, src, 0);
1380 }
1381
1382 void Assembler::addl(Register dst, Register src) {
1383 (void) prefix_and_encode(dst->encoding(), src->encoding());
1384 emit_arith(0x03, 0xC0, dst, src);
1385 }
1386
1387 void Assembler::addr_nop_4() {
1388 assert(UseAddressNop, "no CPU support");
1389 // 4 bytes: NOP DWORD PTR [EAX+0]
1390 emit_int32(0x0F,
1391 0x1F,
1392 0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1393 0); // 8-bits offset (1 byte)
1394 }
1395
1396 void Assembler::addr_nop_5() {
1397 assert(UseAddressNop, "no CPU support");
1398 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1399 emit_int32(0x0F,
1400 0x1F,
1401 0x44, // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1402 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1403 emit_int8(0); // 8-bits offset (1 byte)
1404 }
1405
1406 void Assembler::addr_nop_7() {
1407 assert(UseAddressNop, "no CPU support");
1408 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1409 emit_int24(0x0F,
1410 0x1F,
1411 (unsigned char)0x80);
1412 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1413 emit_int32(0); // 32-bits offset (4 bytes)
1414 }
1415
1416 void Assembler::addr_nop_8() {
1417 assert(UseAddressNop, "no CPU support");
1418 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1419 emit_int32(0x0F,
1420 0x1F,
1421 (unsigned char)0x84,
1422 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1423 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1424 emit_int32(0); // 32-bits offset (4 bytes)
1425 }
1426
1427 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1428 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1429 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1430 attributes.set_rex_vex_w_reverted();
1431 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1432 emit_int16(0x58, (0xC0 | encode));
1433 }
1434
1435 void Assembler::addsd(XMMRegister dst, Address src) {
1436 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1437 InstructionMark im(this);
1438 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1439 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1440 attributes.set_rex_vex_w_reverted();
1441 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1442 emit_int8(0x58);
1443 emit_operand(dst, src, 0);
1444 }
1445
1446 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1447 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1449 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1450 emit_int16(0x58, (0xC0 | encode));
1451 }
1452
1453 void Assembler::addss(XMMRegister dst, Address src) {
1454 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1455 InstructionMark im(this);
1456 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1457 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1458 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1459 emit_int8(0x58);
1460 emit_operand(dst, src, 0);
1461 }
1462
1463 void Assembler::aesdec(XMMRegister dst, Address src) {
1464 assert(VM_Version::supports_aes(), "");
1465 InstructionMark im(this);
1466 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1467 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1468 emit_int8((unsigned char)0xDE);
1469 emit_operand(dst, src, 0);
1470 }
1471
1472 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1473 assert(VM_Version::supports_aes(), "");
1474 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1475 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1476 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1477 }
1478
1479 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1480 assert(VM_Version::supports_avx512_vaes(), "");
1481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1482 attributes.set_is_evex_instruction();
1483 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1484 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1485 }
1486
1487
1488 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1489 assert(VM_Version::supports_aes(), "");
1490 InstructionMark im(this);
1491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1492 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1493 emit_int8((unsigned char)0xDF);
1494 emit_operand(dst, src, 0);
1495 }
1496
1497 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1498 assert(VM_Version::supports_aes(), "");
1499 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1500 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1501 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1502 }
1503
1504 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1505 assert(VM_Version::supports_avx512_vaes(), "");
1506 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1507 attributes.set_is_evex_instruction();
1508 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1509 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1510 }
1511
1512 void Assembler::aesenc(XMMRegister dst, Address src) {
1513 assert(VM_Version::supports_aes(), "");
1514 InstructionMark im(this);
1515 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1516 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1517 emit_int8((unsigned char)0xDC);
1518 emit_operand(dst, src, 0);
1519 }
1520
1521 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1522 assert(VM_Version::supports_aes(), "");
1523 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1524 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1525 emit_int16((unsigned char)0xDC, 0xC0 | encode);
1526 }
1527
1528 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1529 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1530 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1531 attributes.set_is_evex_instruction();
1532 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1533 emit_int16((unsigned char)0xDC, (0xC0 | encode));
1534 }
1535
1536 void Assembler::aesenclast(XMMRegister dst, Address src) {
1537 assert(VM_Version::supports_aes(), "");
1538 InstructionMark im(this);
1539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1540 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1541 emit_int8((unsigned char)0xDD);
1542 emit_operand(dst, src, 0);
1543 }
1544
1545 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1546 assert(VM_Version::supports_aes(), "");
1547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1548 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1549 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1550 }
1551
1552 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1553 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1554 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1555 attributes.set_is_evex_instruction();
1556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1557 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1558 }
1559
1560 void Assembler::andb(Address dst, Register src) {
1561 InstructionMark im(this);
1562 prefix(dst, src, true);
1563 emit_int8(0x20);
1564 emit_operand(src, dst, 0);
1565 }
1566
1567 void Assembler::andw(Register dst, Register src) {
1568 (void)prefix_and_encode(dst->encoding(), src->encoding());
1569 emit_arith(0x23, 0xC0, dst, src);
1570 }
1571
1572 void Assembler::andl(Address dst, int32_t imm32) {
1573 InstructionMark im(this);
1574 prefix(dst);
1575 emit_arith_operand(0x81, as_Register(4), dst, imm32);
1576 }
1577
1578 void Assembler::andl(Register dst, int32_t imm32) {
1579 prefix(dst);
1580 emit_arith(0x81, 0xE0, dst, imm32);
1581 }
1582
1583 void Assembler::andl(Address dst, Register src) {
1584 InstructionMark im(this);
1585 prefix(dst, src);
1586 emit_int8(0x21);
1587 emit_operand(src, dst, 0);
1588 }
1589
1590 void Assembler::andl(Register dst, Address src) {
1591 InstructionMark im(this);
1592 prefix(src, dst);
1593 emit_int8(0x23);
1594 emit_operand(dst, src, 0);
1595 }
1596
1597 void Assembler::andl(Register dst, Register src) {
1598 (void) prefix_and_encode(dst->encoding(), src->encoding());
1599 emit_arith(0x23, 0xC0, dst, src);
1600 }
1601
1602 void Assembler::andnl(Register dst, Register src1, Register src2) {
1603 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1604 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1605 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1606 emit_int16((unsigned char)0xF2, (0xC0 | encode));
1607 }
1608
1609 void Assembler::andnl(Register dst, Register src1, Address src2) {
1610 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1611 InstructionMark im(this);
1612 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1613 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1614 emit_int8((unsigned char)0xF2);
1615 emit_operand(dst, src2, 0);
1616 }
1617
1618 void Assembler::bsfl(Register dst, Register src) {
1619 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1620 emit_int24(0x0F,
1621 (unsigned char)0xBC,
1622 0xC0 | encode);
1623 }
1624
1625 void Assembler::bsrl(Register dst, Register src) {
1626 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1627 emit_int24(0x0F,
1628 (unsigned char)0xBD,
1629 0xC0 | encode);
1630 }
1631
1632 void Assembler::bswapl(Register reg) { // bswap
1633 int encode = prefix_and_encode(reg->encoding());
1634 emit_int16(0x0F, (0xC8 | encode));
1635 }
1636
1637 void Assembler::blsil(Register dst, Register src) {
1638 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1639 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1640 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1641 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1642 }
1643
1644 void Assembler::blsil(Register dst, Address src) {
1645 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1646 InstructionMark im(this);
1647 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1648 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1649 emit_int8((unsigned char)0xF3);
1650 emit_operand(rbx, src, 0);
1651 }
1652
1653 void Assembler::blsmskl(Register dst, Register src) {
1654 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1655 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1656 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1657 emit_int16((unsigned char)0xF3,
1658 0xC0 | encode);
1659 }
1660
1661 void Assembler::blsmskl(Register dst, Address src) {
1662 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1663 InstructionMark im(this);
1664 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1665 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1666 emit_int8((unsigned char)0xF3);
1667 emit_operand(rdx, src, 0);
1668 }
1669
1670 void Assembler::blsrl(Register dst, Register src) {
1671 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1672 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1673 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1674 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1675 }
1676
1677 void Assembler::blsrl(Register dst, Address src) {
1678 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1679 InstructionMark im(this);
1680 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1681 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1682 emit_int8((unsigned char)0xF3);
1683 emit_operand(rcx, src, 0);
1684 }
1685
1686 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1687 // suspect disp32 is always good
1688 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1689
1690 if (L.is_bound()) {
1691 const int long_size = 5;
1692 int offs = (int)( target(L) - pc() );
1693 assert(offs <= 0, "assembler error");
1694 InstructionMark im(this);
1695 // 1110 1000 #32-bit disp
1696 emit_int8((unsigned char)0xE8);
1697 emit_data(offs - long_size, rtype, operand);
1698 } else {
1699 InstructionMark im(this);
1700 // 1110 1000 #32-bit disp
1701 L.add_patch_at(code(), locator());
1702
1703 emit_int8((unsigned char)0xE8);
1704 emit_data(int(0), rtype, operand);
1705 }
1706 }
1707
1708 void Assembler::call(Register dst) {
1709 int encode = prefix_and_encode(dst->encoding());
1710 emit_int16((unsigned char)0xFF, (0xD0 | encode));
1711 }
1712
1713
1714 void Assembler::call(Address adr) {
1715 InstructionMark im(this);
1716 prefix(adr);
1717 emit_int8((unsigned char)0xFF);
1718 emit_operand(rdx, adr, 0);
1719 }
1720
1721 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1722 InstructionMark im(this);
1723 emit_int8((unsigned char)0xE8);
1724 intptr_t disp = entry - (pc() + sizeof(int32_t));
1725 // Entry is null in case of a scratch emit.
1726 assert(entry == nullptr || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1727 // Technically, should use call32_operand, but this format is
1728 // implied by the fact that we're emitting a call instruction.
1729
1730 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1731 emit_data((int) disp, rspec, operand);
1732 }
1733
1734 void Assembler::cdql() {
1735 emit_int8((unsigned char)0x99);
1736 }
1737
1738 void Assembler::cld() {
1739 emit_int8((unsigned char)0xFC);
1740 }
1741
1742 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1743 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1744 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1745 emit_int24(0x0F,
1746 0x40 | cc,
1747 0xC0 | encode);
1748 }
1749
1750
1751 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1752 InstructionMark im(this);
1753 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1754 prefix(src, dst);
1755 emit_int16(0x0F, (0x40 | cc));
1756 emit_operand(dst, src, 0);
1757 }
1758
1759 void Assembler::cmpb(Address dst, int imm8) {
1760 InstructionMark im(this);
1761 prefix(dst);
1762 emit_int8((unsigned char)0x80);
1763 emit_operand(rdi, dst, 1);
1764 emit_int8(imm8);
1765 }
1766
1767 void Assembler::cmpl(Address dst, int32_t imm32) {
1768 InstructionMark im(this);
1769 prefix(dst);
1770 emit_arith_operand(0x81, as_Register(7), dst, imm32);
1771 }
1772
1773 void Assembler::cmpl(Register dst, int32_t imm32) {
1774 prefix(dst);
1775 emit_arith(0x81, 0xF8, dst, imm32);
1776 }
1777
1778 void Assembler::cmpl(Register dst, Register src) {
1779 (void) prefix_and_encode(dst->encoding(), src->encoding());
1780 emit_arith(0x3B, 0xC0, dst, src);
1781 }
1782
1783 void Assembler::cmpl(Register dst, Address src) {
1784 InstructionMark im(this);
1785 prefix(src, dst);
1786 emit_int8(0x3B);
1787 emit_operand(dst, src, 0);
1788 }
1789
1790 void Assembler::cmpl_imm32(Address dst, int32_t imm32) {
1791 InstructionMark im(this);
1792 prefix(dst);
1793 emit_arith_operand_imm32(0x81, as_Register(7), dst, imm32);
1794 }
1795
1796 void Assembler::cmpw(Address dst, int imm16) {
1797 InstructionMark im(this);
1798 emit_int8(0x66);
1799 prefix(dst);
1800 emit_int8((unsigned char)0x81);
1801 emit_operand(rdi, dst, 2);
1802 emit_int16(imm16);
1803 }
1804
1805 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1806 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1807 // The ZF is set if the compared values were equal, and cleared otherwise.
1808 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1809 InstructionMark im(this);
1810 prefix(adr, reg);
1811 emit_int16(0x0F, (unsigned char)0xB1);
1812 emit_operand(reg, adr, 0);
1813 }
1814
1815 void Assembler::cmpxchgw(Register reg, Address adr) { // cmpxchg
1816 InstructionMark im(this);
1817 size_prefix();
1818 prefix(adr, reg);
1819 emit_int16(0x0F, (unsigned char)0xB1);
1820 emit_operand(reg, adr, 0);
1821 }
1822
1823 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1824 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1825 // The ZF is set if the compared values were equal, and cleared otherwise.
1826 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1827 InstructionMark im(this);
1828 prefix(adr, reg, true);
1829 emit_int16(0x0F, (unsigned char)0xB0);
1830 emit_operand(reg, adr, 0);
1831 }
1832
1833 void Assembler::comisd(XMMRegister dst, Address src) {
1834 // NOTE: dbx seems to decode this as comiss even though the
1835 // 0x66 is there. Strangely ucomisd comes out correct
1836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1837 InstructionMark im(this);
1838 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1839 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1840 attributes.set_rex_vex_w_reverted();
1841 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1842 emit_int8(0x2F);
1843 emit_operand(dst, src, 0);
1844 }
1845
1846 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1847 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1849 attributes.set_rex_vex_w_reverted();
1850 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1851 emit_int16(0x2F, (0xC0 | encode));
1852 }
1853
1854 void Assembler::comiss(XMMRegister dst, Address src) {
1855 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1856 InstructionMark im(this);
1857 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1858 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1859 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x2F);
1861 emit_operand(dst, src, 0);
1862 }
1863
1864 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1867 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1868 emit_int16(0x2F, (0xC0 | encode));
1869 }
1870
1871 void Assembler::cpuid() {
1872 emit_int16(0x0F, (unsigned char)0xA2);
1873 }
1874
1875 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1876 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1877 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1878 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1879 //
1880 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1881 //
1882 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1883 //
1884 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1885 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1886 assert(VM_Version::supports_sse4_2(), "");
1887 int8_t w = 0x01;
1888 Prefix p = Prefix_EMPTY;
1889
1890 emit_int8((unsigned char)0xF2);
1891 switch (sizeInBytes) {
1892 case 1:
1893 w = 0;
1894 break;
1895 case 2:
1896 case 4:
1897 break;
1898 LP64_ONLY(case 8:)
1899 // This instruction is not valid in 32 bits
1900 // Note:
1901 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1902 //
1903 // Page B - 72 Vol. 2C says
1904 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1905 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1906 // F0!!!
1907 // while 3 - 208 Vol. 2A
1908 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1909 //
1910 // the 0 on a last bit is reserved for a different flavor of this instruction :
1911 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1912 p = REX_W;
1913 break;
1914 default:
1915 assert(0, "Unsupported value for a sizeInBytes argument");
1916 break;
1917 }
1918 LP64_ONLY(prefix(crc, v, p);)
1919 emit_int32(0x0F,
1920 0x38,
1921 0xF0 | w,
1922 0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1923 }
1924
1925 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1926 assert(VM_Version::supports_sse4_2(), "");
1927 InstructionMark im(this);
1928 int8_t w = 0x01;
1929 Prefix p = Prefix_EMPTY;
1930
1931 emit_int8((uint8_t)0xF2);
1932 switch (sizeInBytes) {
1933 case 1:
1934 w = 0;
1935 break;
1936 case 2:
1937 case 4:
1938 break;
1939 LP64_ONLY(case 8:)
1940 // This instruction is not valid in 32 bits
1941 p = REX_W;
1942 break;
1943 default:
1944 assert(0, "Unsupported value for a sizeInBytes argument");
1945 break;
1946 }
1947 LP64_ONLY(prefix(crc, adr, p);)
1948 emit_int24(0x0F, 0x38, (0xF0 | w));
1949 emit_operand(crc, adr, 0);
1950 }
1951
1952 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1953 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1954 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1955 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1956 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1957 }
1958
1959 void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1960 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
1961 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1962 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1963 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1964 }
1965
1966 void Assembler::vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
1967 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1968 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1969 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1970 emit_int24(0x1D, (0xC0 | encode), imm8);
1971 }
1972
1973 void Assembler::evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len) {
1974 assert(VM_Version::supports_evex(), "");
1975 InstructionMark im(this);
1976 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
1977 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_64bit);
1978 attributes.reset_is_clear_context();
1979 attributes.set_embedded_opmask_register_specifier(mask);
1980 attributes.set_is_evex_instruction();
1981 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1982 emit_int8(0x1D);
1983 emit_operand(src, dst, 1);
1984 emit_int8(imm8);
1985 }
1986
1987 void Assembler::vcvtps2ph(Address dst, XMMRegister src, int imm8, int vector_len) {
1988 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1989 InstructionMark im(this);
1990 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1991 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
1992 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1993 emit_int8(0x1D);
1994 emit_operand(src, dst, 1);
1995 emit_int8(imm8);
1996 }
1997
1998 void Assembler::vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1999 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
2000 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ true);
2001 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2002 emit_int16(0x13, (0xC0 | encode));
2003 }
2004
2005 void Assembler::vcvtph2ps(XMMRegister dst, Address src, int vector_len) {
2006 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
2007 InstructionMark im(this);
2008 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
2009 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
2010 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2011 emit_int8(0x13);
2012 emit_operand(dst, src, 0);
2013 }
2014
2015 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
2016 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2017 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2018 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2019 emit_int16(0x5B, (0xC0 | encode));
2020 }
2021
2022 void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2023 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2024 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2025 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2026 emit_int16(0x5B, (0xC0 | encode));
2027 }
2028
2029 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
2030 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2031 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2032 attributes.set_rex_vex_w_reverted();
2033 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2034 emit_int16(0x5A, (0xC0 | encode));
2035 }
2036
2037 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
2038 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2039 InstructionMark im(this);
2040 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2041 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2042 attributes.set_rex_vex_w_reverted();
2043 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2044 emit_int8(0x5A);
2045 emit_operand(dst, src, 0);
2046 }
2047
2048 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
2049 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2050 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2051 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2052 emit_int16(0x2A, (0xC0 | encode));
2053 }
2054
2055 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
2056 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2057 InstructionMark im(this);
2058 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2059 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2060 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2061 emit_int8(0x2A);
2062 emit_operand(dst, src, 0);
2063 }
2064
2065 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
2066 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2067 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2068 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2069 emit_int16(0x2A, (0xC0 | encode));
2070 }
2071
2072 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
2073 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2074 InstructionMark im(this);
2075 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2076 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2077 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2078 emit_int8(0x2A);
2079 emit_operand(dst, src, 0);
2080 }
2081
2082 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
2083 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2084 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2085 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2086 emit_int16(0x2A, (0xC0 | encode));
2087 }
2088
2089 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
2090 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2091 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2092 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2093 emit_int16(0x5A, (0xC0 | encode));
2094 }
2095
2096 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
2097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2098 InstructionMark im(this);
2099 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2100 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2101 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2102 emit_int8(0x5A);
2103 emit_operand(dst, src, 0);
2104 }
2105
2106
2107 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
2108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2109 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2110 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2111 emit_int16(0x2C, (0xC0 | encode));
2112 }
2113
2114 void Assembler::cvtss2sil(Register dst, XMMRegister src) {
2115 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2116 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2117 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2118 emit_int16(0x2D, (0xC0 | encode));
2119 }
2120
2121 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
2122 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2123 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2124 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2125 emit_int16(0x2C, (0xC0 | encode));
2126 }
2127
2128 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
2129 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2130 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2131 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2132 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2133 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2134 }
2135
2136 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
2137 assert(VM_Version::supports_ssse3(), "");
2138 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2139 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2140 emit_int16(0x1C, (0xC0 | encode));
2141 }
2142
2143 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
2144 assert(VM_Version::supports_ssse3(), "");
2145 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2146 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2147 emit_int16(0x1D, (0xC0 | encode));
2148 }
2149
2150 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
2151 assert(VM_Version::supports_ssse3(), "");
2152 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2153 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2154 emit_int16(0x1E, (0xC0 | encode));
2155 }
2156
2157 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
2158 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2159 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2160 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
2161 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2162 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2163 emit_int16(0x1C, (0xC0 | encode));
2164 }
2165
2166 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
2167 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2168 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2169 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "");
2170 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2171 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2172 emit_int16(0x1D, (0xC0 | encode));
2173 }
2174
2175 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
2176 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
2177 vector_len == AVX_256bit? VM_Version::supports_avx2() :
2178 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
2179 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2180 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2181 emit_int16(0x1E, (0xC0 | encode));
2182 }
2183
2184 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
2185 assert(UseAVX > 2, "");
2186 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2187 attributes.set_is_evex_instruction();
2188 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2189 emit_int16(0x1F, (0xC0 | encode));
2190 }
2191
2192 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2193 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2194 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2195 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2196 emit_int16(0x5A, (0xC0 | encode));
2197 }
2198
2199 void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2200 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2201 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2202 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2203 attributes.set_rex_vex_w_reverted();
2204 emit_int16(0x5A, (0xC0 | encode));
2205 }
2206
2207 void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2208 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2209 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2210 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2211 emit_int16(0x5B, (0xC0 | encode));
2212 }
2213
2214 void Assembler::vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2215 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2216 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2217 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2218 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2219 }
2220
2221 void Assembler::vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2222 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2223 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2225 emit_int16(0x5B, (0xC0 | encode));
2226 }
2227
2228 void Assembler::evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2229 assert(VM_Version::supports_avx512dq(), "");
2230 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2231 attributes.set_is_evex_instruction();
2232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2233 emit_int16(0x7A, (0xC0 | encode));
2234 }
2235
2236 void Assembler::evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2237 assert(VM_Version::supports_avx512dq(), "");
2238 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2239 attributes.set_is_evex_instruction();
2240 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2241 emit_int16(0x7B, (0xC0 | encode));
2242 }
2243
2244 void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2245 assert(VM_Version::supports_avx512dq(), "");
2246 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2247 attributes.set_is_evex_instruction();
2248 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2249 emit_int16(0x5B, (0xC0 | encode));
2250 }
2251
2252 void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2253 assert(VM_Version::supports_avx512dq(), "");
2254 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2255 attributes.set_is_evex_instruction();
2256 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2257 emit_int16(0x7A, (0xC0 | encode));
2258 }
2259
2260 void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2261 assert(VM_Version::supports_avx512dq(), "");
2262 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2263 attributes.set_is_evex_instruction();
2264 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2265 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2266 }
2267
2268 void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
2269 assert(VM_Version::supports_avx512bw(), "");
2270 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2271 attributes.set_is_evex_instruction();
2272 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2273 emit_int16(0x30, (0xC0 | encode));
2274 }
2275
2276 void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
2277 assert(UseAVX > 2, "");
2278 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2279 attributes.set_is_evex_instruction();
2280 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2281 emit_int16(0x33, (0xC0 | encode));
2282 }
2283
2284 void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
2285 assert(UseAVX > 2, "");
2286 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2287 attributes.set_is_evex_instruction();
2288 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2289 emit_int16(0x31, (0xC0 | encode));
2290 }
2291
2292 void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
2293 assert(UseAVX > 2, "");
2294 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2295 attributes.set_is_evex_instruction();
2296 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2297 emit_int16(0x35, (0xC0 | encode));
2298 }
2299
2300 void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
2301 assert(UseAVX > 2, "");
2302 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2303 attributes.set_is_evex_instruction();
2304 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2305 emit_int16(0x32, (0xC0 | encode));
2306 }
2307
2308 void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
2309 assert(UseAVX > 2, "");
2310 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2311 attributes.set_is_evex_instruction();
2312 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2313 emit_int16(0x34, (0xC0 | encode));
2314 }
2315
2316 void Assembler::evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len) {
2317 assert(UseAVX > 2, "");
2318 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2319 attributes.set_is_evex_instruction();
2320 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2321 emit_int16(0x25, (0xC0 | encode));
2322 }
2323
2324 void Assembler::decl(Address dst) {
2325 // Don't use it directly. Use MacroAssembler::decrement() instead.
2326 InstructionMark im(this);
2327 prefix(dst);
2328 emit_int8((unsigned char)0xFF);
2329 emit_operand(rcx, dst, 0);
2330 }
2331
2332 void Assembler::divsd(XMMRegister dst, Address src) {
2333 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2334 InstructionMark im(this);
2335 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2336 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2337 attributes.set_rex_vex_w_reverted();
2338 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2339 emit_int8(0x5E);
2340 emit_operand(dst, src, 0);
2341 }
2342
2343 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2344 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2346 attributes.set_rex_vex_w_reverted();
2347 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2348 emit_int16(0x5E, (0xC0 | encode));
2349 }
2350
2351 void Assembler::divss(XMMRegister dst, Address src) {
2352 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2353 InstructionMark im(this);
2354 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2355 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2356 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2357 emit_int8(0x5E);
2358 emit_operand(dst, src, 0);
2359 }
2360
2361 void Assembler::divss(XMMRegister dst, XMMRegister src) {
2362 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2364 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2365 emit_int16(0x5E, (0xC0 | encode));
2366 }
2367
2368 void Assembler::hlt() {
2369 emit_int8((unsigned char)0xF4);
2370 }
2371
2372 void Assembler::idivl(Register src) {
2373 int encode = prefix_and_encode(src->encoding());
2374 emit_int16((unsigned char)0xF7, (0xF8 | encode));
2375 }
2376
2377 void Assembler::divl(Register src) { // Unsigned
2378 int encode = prefix_and_encode(src->encoding());
2379 emit_int16((unsigned char)0xF7, (0xF0 | encode));
2380 }
2381
2382 void Assembler::imull(Register src) {
2383 int encode = prefix_and_encode(src->encoding());
2384 emit_int16((unsigned char)0xF7, (0xE8 | encode));
2385 }
2386
2387 void Assembler::imull(Register dst, Register src) {
2388 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2389 emit_int24(0x0F,
2390 (unsigned char)0xAF,
2391 (0xC0 | encode));
2392 }
2393
2394 void Assembler::imull(Register dst, Address src, int32_t value) {
2395 InstructionMark im(this);
2396 prefix(src, dst);
2397 if (is8bit(value)) {
2398 emit_int8((unsigned char)0x6B);
2399 emit_operand(dst, src, 1);
2400 emit_int8(value);
2401 } else {
2402 emit_int8((unsigned char)0x69);
2403 emit_operand(dst, src, 4);
2404 emit_int32(value);
2405 }
2406 }
2407
2408 void Assembler::imull(Register dst, Register src, int value) {
2409 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2410 if (is8bit(value)) {
2411 emit_int24(0x6B, (0xC0 | encode), value & 0xFF);
2412 } else {
2413 emit_int16(0x69, (0xC0 | encode));
2414 emit_int32(value);
2415 }
2416 }
2417
2418 void Assembler::imull(Register dst, Address src) {
2419 InstructionMark im(this);
2420 prefix(src, dst);
2421 emit_int16(0x0F, (unsigned char)0xAF);
2422 emit_operand(dst, src, 0);
2423 }
2424
2425
2426 void Assembler::incl(Address dst) {
2427 // Don't use it directly. Use MacroAssembler::increment() instead.
2428 InstructionMark im(this);
2429 prefix(dst);
2430 emit_int8((unsigned char)0xFF);
2431 emit_operand(rax, dst, 0);
2432 }
2433
2434 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2435 InstructionMark im(this);
2436 assert((0 <= cc) && (cc < 16), "illegal cc");
2437 if (L.is_bound()) {
2438 address dst = target(L);
2439 assert(dst != nullptr, "jcc most probably wrong");
2440
2441 const int short_size = 2;
2442 const int long_size = 6;
2443 int offs = checked_cast<int>((intptr_t)dst - (intptr_t)pc());
2444 if (maybe_short && is8bit(offs - short_size)) {
2445 // 0111 tttn #8-bit disp
2446 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2447 } else {
2448 // 0000 1111 1000 tttn #32-bit disp
2449 assert(is_simm32(offs - long_size),
2450 "must be 32bit offset (call4)");
2451 emit_int16(0x0F, (0x80 | cc));
2452 emit_int32(offs - long_size);
2453 }
2454 } else {
2455 // Note: could eliminate cond. jumps to this jump if condition
2456 // is the same however, seems to be rather unlikely case.
2457 // Note: use jccb() if label to be bound is very close to get
2458 // an 8-bit displacement
2459 L.add_patch_at(code(), locator());
2460 emit_int16(0x0F, (0x80 | cc));
2461 emit_int32(0);
2462 }
2463 }
2464
2465 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2466 if (L.is_bound()) {
2467 const int short_size = 2;
2468 address entry = target(L);
2469 #ifdef ASSERT
2470 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2471 int delta = short_branch_delta();
2472 if (delta != 0) {
2473 dist += (dist < 0 ? (-delta) :delta);
2474 }
2475 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2476 #endif
2477 int offs = checked_cast<int>((intptr_t)entry - (intptr_t)pc());
2478 // 0111 tttn #8-bit disp
2479 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2480 } else {
2481 InstructionMark im(this);
2482 L.add_patch_at(code(), locator(), file, line);
2483 emit_int16(0x70 | cc, 0);
2484 }
2485 }
2486
2487 void Assembler::jmp(Address adr) {
2488 InstructionMark im(this);
2489 prefix(adr);
2490 emit_int8((unsigned char)0xFF);
2491 emit_operand(rsp, adr, 0);
2492 }
2493
2494 void Assembler::jmp(Label& L, bool maybe_short) {
2495 if (L.is_bound()) {
2496 address entry = target(L);
2497 assert(entry != nullptr, "jmp most probably wrong");
2498 InstructionMark im(this);
2499 const int short_size = 2;
2500 const int long_size = 5;
2501 int offs = checked_cast<int>(entry - pc());
2502 if (maybe_short && is8bit(offs - short_size)) {
2503 emit_int16((unsigned char)0xEB, ((offs - short_size) & 0xFF));
2504 } else {
2505 emit_int8((unsigned char)0xE9);
2506 emit_int32(offs - long_size);
2507 }
2508 } else {
2509 // By default, forward jumps are always 32-bit displacements, since
2510 // we can't yet know where the label will be bound. If you're sure that
2511 // the forward jump will not run beyond 256 bytes, use jmpb to
2512 // force an 8-bit displacement.
2513 InstructionMark im(this);
2514 L.add_patch_at(code(), locator());
2515 emit_int8((unsigned char)0xE9);
2516 emit_int32(0);
2517 }
2518 }
2519
2520 void Assembler::jmp(Register entry) {
2521 int encode = prefix_and_encode(entry->encoding());
2522 emit_int16((unsigned char)0xFF, (0xE0 | encode));
2523 }
2524
2525 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2526 InstructionMark im(this);
2527 emit_int8((unsigned char)0xE9);
2528 assert(dest != nullptr, "must have a target");
2529 intptr_t disp = dest - (pc() + sizeof(int32_t));
2530 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2531 emit_data(checked_cast<int32_t>(disp), rspec, call32_operand);
2532 }
2533
2534 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2535 if (L.is_bound()) {
2536 const int short_size = 2;
2537 address entry = target(L);
2538 assert(entry != nullptr, "jmp most probably wrong");
2539 #ifdef ASSERT
2540 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2541 int delta = short_branch_delta();
2542 if (delta != 0) {
2543 dist += (dist < 0 ? (-delta) :delta);
2544 }
2545 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2546 #endif
2547 intptr_t offs = entry - pc();
2548 emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
2549 } else {
2550 InstructionMark im(this);
2551 L.add_patch_at(code(), locator(), file, line);
2552 emit_int16((unsigned char)0xEB, 0);
2553 }
2554 }
2555
2556 void Assembler::ldmxcsr( Address src) {
2557 if (UseAVX > 0 ) {
2558 InstructionMark im(this);
2559 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2560 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2561 emit_int8((unsigned char)0xAE);
2562 emit_operand(as_Register(2), src, 0);
2563 } else {
2564 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2565 InstructionMark im(this);
2566 prefix(src);
2567 emit_int16(0x0F, (unsigned char)0xAE);
2568 emit_operand(as_Register(2), src, 0);
2569 }
2570 }
2571
2572 void Assembler::leal(Register dst, Address src) {
2573 InstructionMark im(this);
2574 prefix(src, dst);
2575 emit_int8((unsigned char)0x8D);
2576 emit_operand(dst, src, 0);
2577 }
2578
2579 void Assembler::lfence() {
2580 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
2581 }
2582
2583 void Assembler::lock() {
2584 emit_int8((unsigned char)0xF0);
2585 }
2586
2587 void Assembler::size_prefix() {
2588 emit_int8(0x66);
2589 }
2590
2591 void Assembler::lzcntl(Register dst, Register src) {
2592 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2593 emit_int8((unsigned char)0xF3);
2594 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2595 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
2596 }
2597
2598 void Assembler::lzcntl(Register dst, Address src) {
2599 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2600 InstructionMark im(this);
2601 emit_int8((unsigned char)0xF3);
2602 prefix(src, dst);
2603 emit_int16(0x0F, (unsigned char)0xBD);
2604 emit_operand(dst, src, 0);
2605 }
2606
2607 // Emit mfence instruction
2608 void Assembler::mfence() {
2609 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2610 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
2611 }
2612
2613 // Emit sfence instruction
2614 void Assembler::sfence() {
2615 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2616 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
2617 }
2618
2619 void Assembler::mov(Register dst, Register src) {
2620 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2621 }
2622
2623 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2624 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2625 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2626 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2627 attributes.set_rex_vex_w_reverted();
2628 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2629 emit_int16(0x28, (0xC0 | encode));
2630 }
2631
2632 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2633 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2634 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2635 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2636 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2637 emit_int16(0x28, (0xC0 | encode));
2638 }
2639
2640 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2641 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2643 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2644 emit_int16(0x16, (0xC0 | encode));
2645 }
2646
2647 void Assembler::movb(Register dst, Address src) {
2648 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2649 InstructionMark im(this);
2650 prefix(src, dst, true);
2651 emit_int8((unsigned char)0x8A);
2652 emit_operand(dst, src, 0);
2653 }
2654
2655 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2656 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2657 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2658 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2659 attributes.set_rex_vex_w_reverted();
2660 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2661 emit_int16(0x12, 0xC0 | encode);
2662 }
2663
2664 void Assembler::movddup(XMMRegister dst, Address src) {
2665 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2666 InstructionMark im(this);
2667 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2668 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2669 attributes.set_rex_vex_w_reverted();
2670 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2671 emit_int8(0x12);
2672 emit_operand(dst, src, 0);
2673 }
2674
2675 void Assembler::vmovddup(XMMRegister dst, Address src, int vector_len) {
2676 assert(VM_Version::supports_avx(), "");
2677 InstructionMark im(this);
2678 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2679 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2680 attributes.set_rex_vex_w_reverted();
2681 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2682 emit_int8(0x12);
2683 emit_operand(dst, src, 0);
2684 }
2685
2686 void Assembler::kmovbl(KRegister dst, KRegister src) {
2687 assert(VM_Version::supports_avx512dq(), "");
2688 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2689 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2690 emit_int16((unsigned char)0x90, (0xC0 | encode));
2691 }
2692
2693 void Assembler::kmovbl(KRegister dst, Register src) {
2694 assert(VM_Version::supports_avx512dq(), "");
2695 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2696 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2697 emit_int16((unsigned char)0x92, (0xC0 | encode));
2698 }
2699
2700 void Assembler::kmovbl(Register dst, KRegister src) {
2701 assert(VM_Version::supports_avx512dq(), "");
2702 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2703 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2704 emit_int16((unsigned char)0x93, (0xC0 | encode));
2705 }
2706
2707 void Assembler::kmovwl(KRegister dst, Register src) {
2708 assert(VM_Version::supports_evex(), "");
2709 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2710 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2711 emit_int16((unsigned char)0x92, (0xC0 | encode));
2712 }
2713
2714 void Assembler::kmovwl(Register dst, KRegister src) {
2715 assert(VM_Version::supports_evex(), "");
2716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2717 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2718 emit_int16((unsigned char)0x93, (0xC0 | encode));
2719 }
2720
2721 void Assembler::kmovwl(KRegister dst, Address src) {
2722 assert(VM_Version::supports_evex(), "");
2723 InstructionMark im(this);
2724 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2725 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2726 emit_int8((unsigned char)0x90);
2727 emit_operand(dst, src, 0);
2728 }
2729
2730 void Assembler::kmovwl(Address dst, KRegister src) {
2731 assert(VM_Version::supports_evex(), "");
2732 InstructionMark im(this);
2733 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2734 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2735 emit_int8((unsigned char)0x91);
2736 emit_operand(src, dst, 0);
2737 }
2738
2739 void Assembler::kmovwl(KRegister dst, KRegister src) {
2740 assert(VM_Version::supports_evex(), "");
2741 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2742 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2743 emit_int16((unsigned char)0x90, (0xC0 | encode));
2744 }
2745
2746 void Assembler::kmovdl(KRegister dst, Register src) {
2747 assert(VM_Version::supports_avx512bw(), "");
2748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2749 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2750 emit_int16((unsigned char)0x92, (0xC0 | encode));
2751 }
2752
2753 void Assembler::kmovdl(Register dst, KRegister src) {
2754 assert(VM_Version::supports_avx512bw(), "");
2755 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2756 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2757 emit_int16((unsigned char)0x93, (0xC0 | encode));
2758 }
2759
2760 void Assembler::kmovql(KRegister dst, KRegister src) {
2761 assert(VM_Version::supports_avx512bw(), "");
2762 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2763 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2764 emit_int16((unsigned char)0x90, (0xC0 | encode));
2765 }
2766
2767 void Assembler::kmovql(KRegister dst, Address src) {
2768 assert(VM_Version::supports_avx512bw(), "");
2769 InstructionMark im(this);
2770 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2771 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2772 emit_int8((unsigned char)0x90);
2773 emit_operand(dst, src, 0);
2774 }
2775
2776 void Assembler::kmovql(Address dst, KRegister src) {
2777 assert(VM_Version::supports_avx512bw(), "");
2778 InstructionMark im(this);
2779 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2780 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2781 emit_int8((unsigned char)0x91);
2782 emit_operand(src, dst, 0);
2783 }
2784
2785 void Assembler::kmovql(KRegister dst, Register src) {
2786 assert(VM_Version::supports_avx512bw(), "");
2787 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2788 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2789 emit_int16((unsigned char)0x92, (0xC0 | encode));
2790 }
2791
2792 void Assembler::kmovql(Register dst, KRegister src) {
2793 assert(VM_Version::supports_avx512bw(), "");
2794 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2795 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2796 emit_int16((unsigned char)0x93, (0xC0 | encode));
2797 }
2798
2799 void Assembler::knotwl(KRegister dst, KRegister src) {
2800 assert(VM_Version::supports_evex(), "");
2801 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2802 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2803 emit_int16(0x44, (0xC0 | encode));
2804 }
2805
2806 void Assembler::knotbl(KRegister dst, KRegister src) {
2807 assert(VM_Version::supports_evex(), "");
2808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2809 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2810 emit_int16(0x44, (0xC0 | encode));
2811 }
2812
2813 void Assembler::korbl(KRegister dst, KRegister src1, KRegister src2) {
2814 assert(VM_Version::supports_avx512dq(), "");
2815 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2816 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2817 emit_int16(0x45, (0xC0 | encode));
2818 }
2819
2820 void Assembler::korwl(KRegister dst, KRegister src1, KRegister src2) {
2821 assert(VM_Version::supports_evex(), "");
2822 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2823 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2824 emit_int16(0x45, (0xC0 | encode));
2825 }
2826
2827 void Assembler::kordl(KRegister dst, KRegister src1, KRegister src2) {
2828 assert(VM_Version::supports_avx512bw(), "");
2829 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2830 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2831 emit_int16(0x45, (0xC0 | encode));
2832 }
2833
2834 void Assembler::korql(KRegister dst, KRegister src1, KRegister src2) {
2835 assert(VM_Version::supports_avx512bw(), "");
2836 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2837 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2838 emit_int16(0x45, (0xC0 | encode));
2839 }
2840
2841 void Assembler::kxorbl(KRegister dst, KRegister src1, KRegister src2) {
2842 assert(VM_Version::supports_avx512dq(), "");
2843 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2844 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2845 emit_int16(0x47, (0xC0 | encode));
2846 }
2847
2848 void Assembler::kxorwl(KRegister dst, KRegister src1, KRegister src2) {
2849 assert(VM_Version::supports_evex(), "");
2850 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2851 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2852 emit_int16(0x47, (0xC0 | encode));
2853 }
2854
2855 void Assembler::kxordl(KRegister dst, KRegister src1, KRegister src2) {
2856 assert(VM_Version::supports_avx512bw(), "");
2857 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2858 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2859 emit_int16(0x47, (0xC0 | encode));
2860 }
2861
2862 void Assembler::kxorql(KRegister dst, KRegister src1, KRegister src2) {
2863 assert(VM_Version::supports_avx512bw(), "");
2864 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2865 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2866 emit_int16(0x47, (0xC0 | encode));
2867 }
2868
2869 void Assembler::kandbl(KRegister dst, KRegister src1, KRegister src2) {
2870 assert(VM_Version::supports_avx512dq(), "");
2871 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2872 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2873 emit_int16(0x41, (0xC0 | encode));
2874 }
2875
2876 void Assembler::kandwl(KRegister dst, KRegister src1, KRegister src2) {
2877 assert(VM_Version::supports_evex(), "");
2878 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2879 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2880 emit_int16(0x41, (0xC0 | encode));
2881 }
2882
2883 void Assembler::kanddl(KRegister dst, KRegister src1, KRegister src2) {
2884 assert(VM_Version::supports_avx512bw(), "");
2885 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2886 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2887 emit_int16(0x41, (0xC0 | encode));
2888 }
2889
2890 void Assembler::kandql(KRegister dst, KRegister src1, KRegister src2) {
2891 assert(VM_Version::supports_avx512bw(), "");
2892 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2893 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2894 emit_int16(0x41, (0xC0 | encode));
2895 }
2896
2897 void Assembler::knotdl(KRegister dst, KRegister src) {
2898 assert(VM_Version::supports_avx512bw(), "");
2899 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2900 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2901 emit_int16(0x44, (0xC0 | encode));
2902 }
2903
2904 void Assembler::knotql(KRegister dst, KRegister src) {
2905 assert(VM_Version::supports_avx512bw(), "");
2906 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2907 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2908 emit_int16(0x44, (0xC0 | encode));
2909 }
2910
2911 // This instruction produces ZF or CF flags
2912 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2913 assert(VM_Version::supports_avx512dq(), "");
2914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2915 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2916 emit_int16((unsigned char)0x98, (0xC0 | encode));
2917 }
2918
2919 // This instruction produces ZF or CF flags
2920 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2921 assert(VM_Version::supports_evex(), "");
2922 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2923 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2924 emit_int16((unsigned char)0x98, (0xC0 | encode));
2925 }
2926
2927 // This instruction produces ZF or CF flags
2928 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2929 assert(VM_Version::supports_avx512bw(), "");
2930 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2931 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2932 emit_int16((unsigned char)0x98, (0xC0 | encode));
2933 }
2934
2935 // This instruction produces ZF or CF flags
2936 void Assembler::kortestql(KRegister src1, KRegister src2) {
2937 assert(VM_Version::supports_avx512bw(), "");
2938 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2939 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2940 emit_int16((unsigned char)0x98, (0xC0 | encode));
2941 }
2942
2943 // This instruction produces ZF or CF flags
2944 void Assembler::ktestql(KRegister src1, KRegister src2) {
2945 assert(VM_Version::supports_avx512bw(), "");
2946 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2947 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2948 emit_int16((unsigned char)0x99, (0xC0 | encode));
2949 }
2950
2951 void Assembler::ktestdl(KRegister src1, KRegister src2) {
2952 assert(VM_Version::supports_avx512bw(), "");
2953 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2954 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2955 emit_int16((unsigned char)0x99, (0xC0 | encode));
2956 }
2957
2958 void Assembler::ktestwl(KRegister src1, KRegister src2) {
2959 assert(VM_Version::supports_avx512dq(), "");
2960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2961 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2962 emit_int16((unsigned char)0x99, (0xC0 | encode));
2963 }
2964
2965 void Assembler::ktestbl(KRegister src1, KRegister src2) {
2966 assert(VM_Version::supports_avx512dq(), "");
2967 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2968 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2969 emit_int16((unsigned char)0x99, (0xC0 | encode));
2970 }
2971
2972 void Assembler::ktestq(KRegister src1, KRegister src2) {
2973 assert(VM_Version::supports_avx512bw(), "");
2974 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2975 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2976 emit_int16((unsigned char)0x99, (0xC0 | encode));
2977 }
2978
2979 void Assembler::ktestd(KRegister src1, KRegister src2) {
2980 assert(VM_Version::supports_avx512bw(), "");
2981 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2982 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2983 emit_int16((unsigned char)0x99, (0xC0 | encode));
2984 }
2985
2986 void Assembler::kxnorbl(KRegister dst, KRegister src1, KRegister src2) {
2987 assert(VM_Version::supports_avx512dq(), "");
2988 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2989 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2990 emit_int16(0x46, (0xC0 | encode));
2991 }
2992
2993 void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) {
2994 assert(VM_Version::supports_avx512dq(), "");
2995 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2996 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
2997 emit_int16(0x32, (0xC0 | encode));
2998 emit_int8(imm8);
2999 }
3000
3001 void Assembler::kshiftlql(KRegister dst, KRegister src, int imm8) {
3002 assert(VM_Version::supports_avx512bw(), "");
3003 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3004 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3005 emit_int16(0x33, (0xC0 | encode));
3006 emit_int8(imm8);
3007 }
3008
3009
3010 void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) {
3011 assert(VM_Version::supports_avx512dq(), "");
3012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3013 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3014 emit_int16(0x30, (0xC0 | encode));
3015 }
3016
3017 void Assembler::kshiftrwl(KRegister dst, KRegister src, int imm8) {
3018 assert(VM_Version::supports_evex(), "");
3019 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3020 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3021 emit_int16(0x30, (0xC0 | encode));
3022 emit_int8(imm8);
3023 }
3024
3025 void Assembler::kshiftrdl(KRegister dst, KRegister src, int imm8) {
3026 assert(VM_Version::supports_avx512bw(), "");
3027 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3028 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3029 emit_int16(0x31, (0xC0 | encode));
3030 emit_int8(imm8);
3031 }
3032
3033 void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) {
3034 assert(VM_Version::supports_avx512bw(), "");
3035 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3036 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3037 emit_int16(0x31, (0xC0 | encode));
3038 emit_int8(imm8);
3039 }
3040
3041 void Assembler::kunpckdql(KRegister dst, KRegister src1, KRegister src2) {
3042 assert(VM_Version::supports_avx512bw(), "");
3043 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3044 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3045 emit_int16(0x4B, (0xC0 | encode));
3046 }
3047
3048 void Assembler::movb(Address dst, int imm8) {
3049 InstructionMark im(this);
3050 prefix(dst);
3051 emit_int8((unsigned char)0xC6);
3052 emit_operand(rax, dst, 1);
3053 emit_int8(imm8);
3054 }
3055
3056
3057 void Assembler::movb(Address dst, Register src) {
3058 assert(src->has_byte_register(), "must have byte register");
3059 InstructionMark im(this);
3060 prefix(dst, src, true);
3061 emit_int8((unsigned char)0x88);
3062 emit_operand(src, dst, 0);
3063 }
3064
3065 void Assembler::movdl(XMMRegister dst, Register src) {
3066 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3067 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3068 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3069 emit_int16(0x6E, (0xC0 | encode));
3070 }
3071
3072 void Assembler::movdl(Register dst, XMMRegister src) {
3073 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3074 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3075 // swap src/dst to get correct prefix
3076 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3077 emit_int16(0x7E, (0xC0 | encode));
3078 }
3079
3080 void Assembler::movdl(XMMRegister dst, Address src) {
3081 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3082 InstructionMark im(this);
3083 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3084 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3085 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3086 emit_int8(0x6E);
3087 emit_operand(dst, src, 0);
3088 }
3089
3090 void Assembler::movdl(Address dst, XMMRegister src) {
3091 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3092 InstructionMark im(this);
3093 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3094 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3095 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3096 emit_int8(0x7E);
3097 emit_operand(src, dst, 0);
3098 }
3099
3100 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
3101 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3102 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3103 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3104 emit_int16(0x6F, (0xC0 | encode));
3105 }
3106
3107 void Assembler::movdqa(XMMRegister dst, Address src) {
3108 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3109 InstructionMark im(this);
3110 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3111 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3112 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3113 emit_int8(0x6F);
3114 emit_operand(dst, src, 0);
3115 }
3116
3117 void Assembler::movdqu(XMMRegister dst, Address src) {
3118 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3119 InstructionMark im(this);
3120 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3121 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3122 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3123 emit_int8(0x6F);
3124 emit_operand(dst, src, 0);
3125 }
3126
3127 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
3128 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3129 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3130 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3131 emit_int16(0x6F, (0xC0 | encode));
3132 }
3133
3134 void Assembler::movdqu(Address dst, XMMRegister src) {
3135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3136 InstructionMark im(this);
3137 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3138 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3139 attributes.reset_is_clear_context();
3140 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3141 emit_int8(0x7F);
3142 emit_operand(src, dst, 0);
3143 }
3144
3145 // Move Unaligned 256bit Vector
3146 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3147 assert(UseAVX > 0, "");
3148 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3149 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3150 emit_int16(0x6F, (0xC0 | encode));
3151 }
3152
3153 void Assembler::vmovdqu(XMMRegister dst, Address src) {
3154 assert(UseAVX > 0, "");
3155 InstructionMark im(this);
3156 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3157 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3158 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3159 emit_int8(0x6F);
3160 emit_operand(dst, src, 0);
3161 }
3162
3163 void Assembler::vmovdqu(Address dst, XMMRegister src) {
3164 assert(UseAVX > 0, "");
3165 InstructionMark im(this);
3166 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3167 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3168 attributes.reset_is_clear_context();
3169 // swap src<->dst for encoding
3170 assert(src != xnoreg, "sanity");
3171 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3172 emit_int8(0x7F);
3173 emit_operand(src, dst, 0);
3174 }
3175
3176 void Assembler::vpmaskmovd(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3177 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3178 InstructionMark im(this);
3179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3180 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3181 emit_int8((unsigned char)0x8C);
3182 emit_operand(dst, src, 0);
3183 }
3184
3185 void Assembler::vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3186 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3187 InstructionMark im(this);
3188 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3189 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3190 emit_int8((unsigned char)0x8C);
3191 emit_operand(dst, src, 0);
3192 }
3193
3194 void Assembler::vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3195 assert(UseAVX > 0, "requires some form of AVX");
3196 InstructionMark im(this);
3197 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3198 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3199 emit_int8(0x2C);
3200 emit_operand(dst, src, 0);
3201 }
3202
3203 void Assembler::vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3204 assert(UseAVX > 0, "requires some form of AVX");
3205 InstructionMark im(this);
3206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3207 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3208 emit_int8(0x2D);
3209 emit_operand(dst, src, 0);
3210 }
3211
3212 void Assembler::vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3213 assert(UseAVX > 0, "");
3214 InstructionMark im(this);
3215 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3216 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3217 emit_int8(0x2E);
3218 emit_operand(src, dst, 0);
3219 }
3220
3221 void Assembler::vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3222 assert(UseAVX > 0, "");
3223 InstructionMark im(this);
3224 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3225 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3226 emit_int8(0x2F);
3227 emit_operand(src, dst, 0);
3228 }
3229
3230 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
3231 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3232 assert(VM_Version::supports_avx512vlbw(), "");
3233 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3234 attributes.set_embedded_opmask_register_specifier(mask);
3235 attributes.set_is_evex_instruction();
3236 if (merge) {
3237 attributes.reset_is_clear_context();
3238 }
3239 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3240 emit_int16(0x6F, (0xC0 | encode));
3241 }
3242
3243 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
3244 // Unmasked instruction
3245 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3246 }
3247
3248 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3249 assert(VM_Version::supports_avx512vlbw(), "");
3250 InstructionMark im(this);
3251 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3252 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3253 attributes.set_embedded_opmask_register_specifier(mask);
3254 attributes.set_is_evex_instruction();
3255 if (merge) {
3256 attributes.reset_is_clear_context();
3257 }
3258 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3259 emit_int8(0x6F);
3260 emit_operand(dst, src, 0);
3261 }
3262
3263 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
3264 // Unmasked instruction
3265 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3266 }
3267
3268 void Assembler::evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3269 assert(VM_Version::supports_avx512vlbw(), "");
3270 assert(src != xnoreg, "sanity");
3271 InstructionMark im(this);
3272 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3273 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3274 attributes.set_embedded_opmask_register_specifier(mask);
3275 attributes.set_is_evex_instruction();
3276 if (merge) {
3277 attributes.reset_is_clear_context();
3278 }
3279 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3280 emit_int8(0x7F);
3281 emit_operand(src, dst, 0);
3282 }
3283
3284 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
3285 // Unmasked instruction
3286 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3287 }
3288
3289 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3290 assert(VM_Version::supports_avx512vlbw(), "");
3291 InstructionMark im(this);
3292 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3293 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3294 attributes.set_embedded_opmask_register_specifier(mask);
3295 attributes.set_is_evex_instruction();
3296 if (merge) {
3297 attributes.reset_is_clear_context();
3298 }
3299 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3300 emit_int8(0x6F);
3301 emit_operand(dst, src, 0);
3302 }
3303
3304 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
3305 // Unmasked instruction
3306 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3307 }
3308
3309 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3310 assert(VM_Version::supports_avx512vlbw(), "");
3311 assert(src != xnoreg, "sanity");
3312 InstructionMark im(this);
3313 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3314 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3315 attributes.set_embedded_opmask_register_specifier(mask);
3316 attributes.set_is_evex_instruction();
3317 if (merge) {
3318 attributes.reset_is_clear_context();
3319 }
3320 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3321 emit_int8(0x7F);
3322 emit_operand(src, dst, 0);
3323 }
3324
3325 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
3326 // Unmasked instruction
3327 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3328 }
3329
3330 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3331 assert(VM_Version::supports_evex(), "");
3332 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3333 attributes.set_embedded_opmask_register_specifier(mask);
3334 attributes.set_is_evex_instruction();
3335 if (merge) {
3336 attributes.reset_is_clear_context();
3337 }
3338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3339 emit_int16(0x6F, (0xC0 | encode));
3340 }
3341
3342 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
3343 // Unmasked instruction
3344 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3345 }
3346
3347 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3348 assert(VM_Version::supports_evex(), "");
3349 InstructionMark im(this);
3350 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
3351 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3352 attributes.set_embedded_opmask_register_specifier(mask);
3353 attributes.set_is_evex_instruction();
3354 if (merge) {
3355 attributes.reset_is_clear_context();
3356 }
3357 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3358 emit_int8(0x6F);
3359 emit_operand(dst, src, 0);
3360 }
3361
3362 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
3363 // Unmasked isntruction
3364 evmovdqul(dst, k0, src, /*merge*/ true, vector_len);
3365 }
3366
3367 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3368 assert(VM_Version::supports_evex(), "");
3369 assert(src != xnoreg, "sanity");
3370 InstructionMark im(this);
3371 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3372 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3373 attributes.set_embedded_opmask_register_specifier(mask);
3374 attributes.set_is_evex_instruction();
3375 if (merge) {
3376 attributes.reset_is_clear_context();
3377 }
3378 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3379 emit_int8(0x7F);
3380 emit_operand(src, dst, 0);
3381 }
3382
3383 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
3384 // Unmasked instruction
3385 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3386 }
3387
3388 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3389 assert(VM_Version::supports_evex(), "");
3390 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3391 attributes.set_embedded_opmask_register_specifier(mask);
3392 attributes.set_is_evex_instruction();
3393 if (merge) {
3394 attributes.reset_is_clear_context();
3395 }
3396 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3397 emit_int16(0x6F, (0xC0 | encode));
3398 }
3399
3400 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
3401 // Unmasked instruction
3402 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3403 }
3404
3405 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3406 assert(VM_Version::supports_evex(), "");
3407 InstructionMark im(this);
3408 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3409 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3410 attributes.set_embedded_opmask_register_specifier(mask);
3411 attributes.set_is_evex_instruction();
3412 if (merge) {
3413 attributes.reset_is_clear_context();
3414 }
3415 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3416 emit_int8(0x6F);
3417 emit_operand(dst, src, 0);
3418 }
3419
3420 void Assembler::evmovntdquq(Address dst, XMMRegister src, int vector_len) {
3421 // Unmasked instruction
3422 evmovntdquq(dst, k0, src, /*merge*/ true, vector_len);
3423 }
3424
3425 void Assembler::evmovntdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3426 assert(VM_Version::supports_evex(), "");
3427 assert(src != xnoreg, "sanity");
3428 InstructionMark im(this);
3429 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3430 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3431 attributes.set_embedded_opmask_register_specifier(mask);
3432 if (merge) {
3433 attributes.reset_is_clear_context();
3434 }
3435 attributes.set_is_evex_instruction();
3436 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3437 emit_int8(0xE7);
3438 emit_operand(src, dst, 0);
3439 }
3440
3441 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
3442 // Unmasked instruction
3443 evmovdquq(dst, k0, src, /*merge*/ true, vector_len);
3444 }
3445
3446 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3447 assert(VM_Version::supports_evex(), "");
3448 assert(src != xnoreg, "sanity");
3449 InstructionMark im(this);
3450 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3451 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3452 attributes.set_embedded_opmask_register_specifier(mask);
3453 if (merge) {
3454 attributes.reset_is_clear_context();
3455 }
3456 attributes.set_is_evex_instruction();
3457 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3458 emit_int8(0x7F);
3459 emit_operand(src, dst, 0);
3460 }
3461
3462 // Uses zero extension on 64bit
3463
3464 void Assembler::movl(Register dst, int32_t imm32) {
3465 int encode = prefix_and_encode(dst->encoding());
3466 emit_int8(0xB8 | encode);
3467 emit_int32(imm32);
3468 }
3469
3470 void Assembler::movl(Register dst, Register src) {
3471 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3472 emit_int16((unsigned char)0x8B, (0xC0 | encode));
3473 }
3474
3475 void Assembler::movl(Register dst, Address src) {
3476 InstructionMark im(this);
3477 prefix(src, dst);
3478 emit_int8((unsigned char)0x8B);
3479 emit_operand(dst, src, 0);
3480 }
3481
3482 void Assembler::movl(Address dst, int32_t imm32) {
3483 InstructionMark im(this);
3484 prefix(dst);
3485 emit_int8((unsigned char)0xC7);
3486 emit_operand(rax, dst, 4);
3487 emit_int32(imm32);
3488 }
3489
3490 void Assembler::movl(Address dst, Register src) {
3491 InstructionMark im(this);
3492 prefix(dst, src);
3493 emit_int8((unsigned char)0x89);
3494 emit_operand(src, dst, 0);
3495 }
3496
3497 // New cpus require to use movsd and movss to avoid partial register stall
3498 // when loading from memory. But for old Opteron use movlpd instead of movsd.
3499 // The selection is done in MacroAssembler::movdbl() and movflt().
3500 void Assembler::movlpd(XMMRegister dst, Address src) {
3501 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3502 InstructionMark im(this);
3503 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3504 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3505 attributes.set_rex_vex_w_reverted();
3506 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3507 emit_int8(0x12);
3508 emit_operand(dst, src, 0);
3509 }
3510
3511 void Assembler::movq(XMMRegister dst, Address src) {
3512 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3513 InstructionMark im(this);
3514 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3515 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3516 attributes.set_rex_vex_w_reverted();
3517 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3518 emit_int8(0x7E);
3519 emit_operand(dst, src, 0);
3520 }
3521
3522 void Assembler::movq(Address dst, XMMRegister src) {
3523 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3524 InstructionMark im(this);
3525 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3526 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3527 attributes.set_rex_vex_w_reverted();
3528 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3529 emit_int8((unsigned char)0xD6);
3530 emit_operand(src, dst, 0);
3531 }
3532
3533 void Assembler::movq(XMMRegister dst, XMMRegister src) {
3534 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3535 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3536 attributes.set_rex_vex_w_reverted();
3537 int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3538 emit_int16((unsigned char)0xD6, (0xC0 | encode));
3539 }
3540
3541 void Assembler::movq(Register dst, XMMRegister src) {
3542 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3543 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3544 // swap src/dst to get correct prefix
3545 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3546 emit_int16(0x7E, (0xC0 | encode));
3547 }
3548
3549 void Assembler::movq(XMMRegister dst, Register src) {
3550 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3551 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3552 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3553 emit_int16(0x6E, (0xC0 | encode));
3554 }
3555
3556 void Assembler::movsbl(Register dst, Address src) { // movsxb
3557 InstructionMark im(this);
3558 prefix(src, dst);
3559 emit_int16(0x0F, (unsigned char)0xBE);
3560 emit_operand(dst, src, 0);
3561 }
3562
3563 void Assembler::movsbl(Register dst, Register src) { // movsxb
3564 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3565 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3566 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
3567 }
3568
3569 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
3570 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3571 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3572 attributes.set_rex_vex_w_reverted();
3573 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3574 emit_int16(0x10, (0xC0 | encode));
3575 }
3576
3577 void Assembler::movsd(XMMRegister dst, Address src) {
3578 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3579 InstructionMark im(this);
3580 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3581 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3582 attributes.set_rex_vex_w_reverted();
3583 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3584 emit_int8(0x10);
3585 emit_operand(dst, src, 0);
3586 }
3587
3588 void Assembler::movsd(Address dst, XMMRegister src) {
3589 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3590 InstructionMark im(this);
3591 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3592 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3593 attributes.reset_is_clear_context();
3594 attributes.set_rex_vex_w_reverted();
3595 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3596 emit_int8(0x11);
3597 emit_operand(src, dst, 0);
3598 }
3599
3600 void Assembler::vmovsd(XMMRegister dst, XMMRegister src, XMMRegister src2) {
3601 assert(UseAVX > 0, "Requires some form of AVX");
3602 InstructionMark im(this);
3603 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3604 int encode = vex_prefix_and_encode(src2->encoding(), src->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3605 emit_int16(0x11, (0xC0 | encode));
3606 }
3607
3608 void Assembler::movss(XMMRegister dst, XMMRegister src) {
3609 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3610 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3611 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3612 emit_int16(0x10, (0xC0 | encode));
3613 }
3614
3615 void Assembler::movss(XMMRegister dst, Address src) {
3616 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3617 InstructionMark im(this);
3618 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3619 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3620 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3621 emit_int8(0x10);
3622 emit_operand(dst, src, 0);
3623 }
3624
3625 void Assembler::movss(Address dst, XMMRegister src) {
3626 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3627 InstructionMark im(this);
3628 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3629 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3630 attributes.reset_is_clear_context();
3631 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3632 emit_int8(0x11);
3633 emit_operand(src, dst, 0);
3634 }
3635
3636 void Assembler::movswl(Register dst, Address src) { // movsxw
3637 InstructionMark im(this);
3638 prefix(src, dst);
3639 emit_int16(0x0F, (unsigned char)0xBF);
3640 emit_operand(dst, src, 0);
3641 }
3642
3643 void Assembler::movswl(Register dst, Register src) { // movsxw
3644 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3645 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
3646 }
3647
3648 void Assembler::movups(XMMRegister dst, Address src) {
3649 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3650 InstructionMark im(this);
3651 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3652 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3653 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3654 emit_int8(0x10);
3655 emit_operand(dst, src, 0);
3656 }
3657
3658 void Assembler::vmovups(XMMRegister dst, Address src, int vector_len) {
3659 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3660 InstructionMark im(this);
3661 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3662 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3663 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3664 emit_int8(0x10);
3665 emit_operand(dst, src, 0);
3666 }
3667
3668 void Assembler::movups(Address dst, XMMRegister src) {
3669 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3670 InstructionMark im(this);
3671 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3672 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3673 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3674 emit_int8(0x11);
3675 emit_operand(src, dst, 0);
3676 }
3677
3678 void Assembler::vmovups(Address dst, XMMRegister src, int vector_len) {
3679 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3680 InstructionMark im(this);
3681 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3682 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3683 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3684 emit_int8(0x11);
3685 emit_operand(src, dst, 0);
3686 }
3687
3688 void Assembler::movw(Address dst, int imm16) {
3689 InstructionMark im(this);
3690
3691 emit_int8(0x66); // switch to 16-bit mode
3692 prefix(dst);
3693 emit_int8((unsigned char)0xC7);
3694 emit_operand(rax, dst, 2);
3695 emit_int16(imm16);
3696 }
3697
3698 void Assembler::movw(Register dst, Address src) {
3699 InstructionMark im(this);
3700 emit_int8(0x66);
3701 prefix(src, dst);
3702 emit_int8((unsigned char)0x8B);
3703 emit_operand(dst, src, 0);
3704 }
3705
3706 void Assembler::movw(Address dst, Register src) {
3707 InstructionMark im(this);
3708 emit_int8(0x66);
3709 prefix(dst, src);
3710 emit_int8((unsigned char)0x89);
3711 emit_operand(src, dst, 0);
3712 }
3713
3714 void Assembler::movzbl(Register dst, Address src) { // movzxb
3715 InstructionMark im(this);
3716 prefix(src, dst);
3717 emit_int16(0x0F, (unsigned char)0xB6);
3718 emit_operand(dst, src, 0);
3719 }
3720
3721 void Assembler::movzbl(Register dst, Register src) { // movzxb
3722 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3723 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3724 emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
3725 }
3726
3727 void Assembler::movzwl(Register dst, Address src) { // movzxw
3728 InstructionMark im(this);
3729 prefix(src, dst);
3730 emit_int16(0x0F, (unsigned char)0xB7);
3731 emit_operand(dst, src, 0);
3732 }
3733
3734 void Assembler::movzwl(Register dst, Register src) { // movzxw
3735 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3736 emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode);
3737 }
3738
3739 void Assembler::mull(Address src) {
3740 InstructionMark im(this);
3741 prefix(src);
3742 emit_int8((unsigned char)0xF7);
3743 emit_operand(rsp, src, 0);
3744 }
3745
3746 void Assembler::mull(Register src) {
3747 int encode = prefix_and_encode(src->encoding());
3748 emit_int16((unsigned char)0xF7, (0xE0 | encode));
3749 }
3750
3751 void Assembler::mulsd(XMMRegister dst, Address src) {
3752 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3753 InstructionMark im(this);
3754 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3755 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3756 attributes.set_rex_vex_w_reverted();
3757 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3758 emit_int8(0x59);
3759 emit_operand(dst, src, 0);
3760 }
3761
3762 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3763 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3764 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3765 attributes.set_rex_vex_w_reverted();
3766 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3767 emit_int16(0x59, (0xC0 | encode));
3768 }
3769
3770 void Assembler::mulss(XMMRegister dst, Address src) {
3771 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3772 InstructionMark im(this);
3773 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3774 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3775 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3776 emit_int8(0x59);
3777 emit_operand(dst, src, 0);
3778 }
3779
3780 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3781 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3782 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3783 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3784 emit_int16(0x59, (0xC0 | encode));
3785 }
3786
3787 void Assembler::negl(Register dst) {
3788 int encode = prefix_and_encode(dst->encoding());
3789 emit_int16((unsigned char)0xF7, (0xD8 | encode));
3790 }
3791
3792 void Assembler::negl(Address dst) {
3793 InstructionMark im(this);
3794 prefix(dst);
3795 emit_int8((unsigned char)0xF7);
3796 emit_operand(as_Register(3), dst, 0);
3797 }
3798
3799 void Assembler::nop(int i) {
3800 #ifdef ASSERT
3801 assert(i > 0, " ");
3802 // The fancy nops aren't currently recognized by debuggers making it a
3803 // pain to disassemble code while debugging. If asserts are on clearly
3804 // speed is not an issue so simply use the single byte traditional nop
3805 // to do alignment.
3806
3807 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3808 return;
3809
3810 #endif // ASSERT
3811
3812 if (UseAddressNop && VM_Version::is_intel()) {
3813 //
3814 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3815 // 1: 0x90
3816 // 2: 0x66 0x90
3817 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3818 // 4: 0x0F 0x1F 0x40 0x00
3819 // 5: 0x0F 0x1F 0x44 0x00 0x00
3820 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3821 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3822 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3823 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3824 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3825 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3826
3827 // The rest coding is Intel specific - don't use consecutive address nops
3828
3829 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3830 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3831 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3832 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3833
3834 while(i >= 15) {
3835 // For Intel don't generate consecutive address nops (mix with regular nops)
3836 i -= 15;
3837 emit_int24(0x66, 0x66, 0x66);
3838 addr_nop_8();
3839 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3840 }
3841 switch (i) {
3842 case 14:
3843 emit_int8(0x66); // size prefix
3844 case 13:
3845 emit_int8(0x66); // size prefix
3846 case 12:
3847 addr_nop_8();
3848 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3849 break;
3850 case 11:
3851 emit_int8(0x66); // size prefix
3852 case 10:
3853 emit_int8(0x66); // size prefix
3854 case 9:
3855 emit_int8(0x66); // size prefix
3856 case 8:
3857 addr_nop_8();
3858 break;
3859 case 7:
3860 addr_nop_7();
3861 break;
3862 case 6:
3863 emit_int8(0x66); // size prefix
3864 case 5:
3865 addr_nop_5();
3866 break;
3867 case 4:
3868 addr_nop_4();
3869 break;
3870 case 3:
3871 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3872 emit_int8(0x66); // size prefix
3873 case 2:
3874 emit_int8(0x66); // size prefix
3875 case 1:
3876 emit_int8((unsigned char)0x90);
3877 // nop
3878 break;
3879 default:
3880 assert(i == 0, " ");
3881 }
3882 return;
3883 }
3884 if (UseAddressNop && VM_Version::is_amd_family()) {
3885 //
3886 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3887 // 1: 0x90
3888 // 2: 0x66 0x90
3889 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3890 // 4: 0x0F 0x1F 0x40 0x00
3891 // 5: 0x0F 0x1F 0x44 0x00 0x00
3892 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3893 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3894 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3895 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3896 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3897 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3898
3899 // The rest coding is AMD specific - use consecutive address nops
3900
3901 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3902 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3903 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3904 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3905 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3906 // Size prefixes (0x66) are added for larger sizes
3907
3908 while(i >= 22) {
3909 i -= 11;
3910 emit_int24(0x66, 0x66, 0x66);
3911 addr_nop_8();
3912 }
3913 // Generate first nop for size between 21-12
3914 switch (i) {
3915 case 21:
3916 i -= 1;
3917 emit_int8(0x66); // size prefix
3918 case 20:
3919 case 19:
3920 i -= 1;
3921 emit_int8(0x66); // size prefix
3922 case 18:
3923 case 17:
3924 i -= 1;
3925 emit_int8(0x66); // size prefix
3926 case 16:
3927 case 15:
3928 i -= 8;
3929 addr_nop_8();
3930 break;
3931 case 14:
3932 case 13:
3933 i -= 7;
3934 addr_nop_7();
3935 break;
3936 case 12:
3937 i -= 6;
3938 emit_int8(0x66); // size prefix
3939 addr_nop_5();
3940 break;
3941 default:
3942 assert(i < 12, " ");
3943 }
3944
3945 // Generate second nop for size between 11-1
3946 switch (i) {
3947 case 11:
3948 emit_int8(0x66); // size prefix
3949 case 10:
3950 emit_int8(0x66); // size prefix
3951 case 9:
3952 emit_int8(0x66); // size prefix
3953 case 8:
3954 addr_nop_8();
3955 break;
3956 case 7:
3957 addr_nop_7();
3958 break;
3959 case 6:
3960 emit_int8(0x66); // size prefix
3961 case 5:
3962 addr_nop_5();
3963 break;
3964 case 4:
3965 addr_nop_4();
3966 break;
3967 case 3:
3968 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3969 emit_int8(0x66); // size prefix
3970 case 2:
3971 emit_int8(0x66); // size prefix
3972 case 1:
3973 emit_int8((unsigned char)0x90);
3974 // nop
3975 break;
3976 default:
3977 assert(i == 0, " ");
3978 }
3979 return;
3980 }
3981
3982 if (UseAddressNop && VM_Version::is_zx()) {
3983 //
3984 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3985 // 1: 0x90
3986 // 2: 0x66 0x90
3987 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3988 // 4: 0x0F 0x1F 0x40 0x00
3989 // 5: 0x0F 0x1F 0x44 0x00 0x00
3990 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3991 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3992 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3993 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3994 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3995 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3996
3997 // The rest coding is ZX specific - don't use consecutive address nops
3998
3999 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4000 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4001 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4002 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
4003
4004 while (i >= 15) {
4005 // For ZX don't generate consecutive address nops (mix with regular nops)
4006 i -= 15;
4007 emit_int24(0x66, 0x66, 0x66);
4008 addr_nop_8();
4009 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4010 }
4011 switch (i) {
4012 case 14:
4013 emit_int8(0x66); // size prefix
4014 case 13:
4015 emit_int8(0x66); // size prefix
4016 case 12:
4017 addr_nop_8();
4018 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4019 break;
4020 case 11:
4021 emit_int8(0x66); // size prefix
4022 case 10:
4023 emit_int8(0x66); // size prefix
4024 case 9:
4025 emit_int8(0x66); // size prefix
4026 case 8:
4027 addr_nop_8();
4028 break;
4029 case 7:
4030 addr_nop_7();
4031 break;
4032 case 6:
4033 emit_int8(0x66); // size prefix
4034 case 5:
4035 addr_nop_5();
4036 break;
4037 case 4:
4038 addr_nop_4();
4039 break;
4040 case 3:
4041 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
4042 emit_int8(0x66); // size prefix
4043 case 2:
4044 emit_int8(0x66); // size prefix
4045 case 1:
4046 emit_int8((unsigned char)0x90);
4047 // nop
4048 break;
4049 default:
4050 assert(i == 0, " ");
4051 }
4052 return;
4053 }
4054
4055 // Using nops with size prefixes "0x66 0x90".
4056 // From AMD Optimization Guide:
4057 // 1: 0x90
4058 // 2: 0x66 0x90
4059 // 3: 0x66 0x66 0x90
4060 // 4: 0x66 0x66 0x66 0x90
4061 // 5: 0x66 0x66 0x90 0x66 0x90
4062 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
4063 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
4064 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
4065 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4066 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4067 //
4068 while (i > 12) {
4069 i -= 4;
4070 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4071 }
4072 // 1 - 12 nops
4073 if (i > 8) {
4074 if (i > 9) {
4075 i -= 1;
4076 emit_int8(0x66);
4077 }
4078 i -= 3;
4079 emit_int24(0x66, 0x66, (unsigned char)0x90);
4080 }
4081 // 1 - 8 nops
4082 if (i > 4) {
4083 if (i > 6) {
4084 i -= 1;
4085 emit_int8(0x66);
4086 }
4087 i -= 3;
4088 emit_int24(0x66, 0x66, (unsigned char)0x90);
4089 }
4090 switch (i) {
4091 case 4:
4092 emit_int8(0x66);
4093 case 3:
4094 emit_int8(0x66);
4095 case 2:
4096 emit_int8(0x66);
4097 case 1:
4098 emit_int8((unsigned char)0x90);
4099 break;
4100 default:
4101 assert(i == 0, " ");
4102 }
4103 }
4104
4105 void Assembler::notl(Register dst) {
4106 int encode = prefix_and_encode(dst->encoding());
4107 emit_int16((unsigned char)0xF7, (0xD0 | encode));
4108 }
4109
4110 void Assembler::orw(Register dst, Register src) {
4111 (void)prefix_and_encode(dst->encoding(), src->encoding());
4112 emit_arith(0x0B, 0xC0, dst, src);
4113 }
4114
4115 void Assembler::orl(Address dst, int32_t imm32) {
4116 InstructionMark im(this);
4117 prefix(dst);
4118 emit_arith_operand(0x81, rcx, dst, imm32);
4119 }
4120
4121 void Assembler::orl(Register dst, int32_t imm32) {
4122 prefix(dst);
4123 emit_arith(0x81, 0xC8, dst, imm32);
4124 }
4125
4126 void Assembler::orl(Register dst, Address src) {
4127 InstructionMark im(this);
4128 prefix(src, dst);
4129 emit_int8(0x0B);
4130 emit_operand(dst, src, 0);
4131 }
4132
4133 void Assembler::orl(Register dst, Register src) {
4134 (void) prefix_and_encode(dst->encoding(), src->encoding());
4135 emit_arith(0x0B, 0xC0, dst, src);
4136 }
4137
4138 void Assembler::orl(Address dst, Register src) {
4139 InstructionMark im(this);
4140 prefix(dst, src);
4141 emit_int8(0x09);
4142 emit_operand(src, dst, 0);
4143 }
4144
4145 void Assembler::orb(Address dst, int imm8) {
4146 InstructionMark im(this);
4147 prefix(dst);
4148 emit_int8((unsigned char)0x80);
4149 emit_operand(rcx, dst, 1);
4150 emit_int8(imm8);
4151 }
4152
4153 void Assembler::orb(Address dst, Register src) {
4154 InstructionMark im(this);
4155 prefix(dst, src, true);
4156 emit_int8(0x08);
4157 emit_operand(src, dst, 0);
4158 }
4159
4160 void Assembler::packsswb(XMMRegister dst, XMMRegister src) {
4161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4162 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4163 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4164 emit_int16(0x63, (0xC0 | encode));
4165 }
4166
4167 void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4168 assert(UseAVX > 0, "some form of AVX must be enabled");
4169 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4170 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4171 emit_int16(0x63, (0xC0 | encode));
4172 }
4173
4174 void Assembler::packssdw(XMMRegister dst, XMMRegister src) {
4175 assert(VM_Version::supports_sse2(), "");
4176 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4177 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4178 emit_int16(0x6B, (0xC0 | encode));
4179 }
4180
4181 void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4182 assert(UseAVX > 0, "some form of AVX must be enabled");
4183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4184 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4185 emit_int16(0x6B, (0xC0 | encode));
4186 }
4187
4188 void Assembler::packuswb(XMMRegister dst, Address src) {
4189 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4190 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4191 InstructionMark im(this);
4192 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4193 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4194 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4195 emit_int8(0x67);
4196 emit_operand(dst, src, 0);
4197 }
4198
4199 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
4200 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4201 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4202 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4203 emit_int16(0x67, (0xC0 | encode));
4204 }
4205
4206 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4207 assert(UseAVX > 0, "some form of AVX must be enabled");
4208 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4209 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4210 emit_int16(0x67, (0xC0 | encode));
4211 }
4212
4213 void Assembler::packusdw(XMMRegister dst, XMMRegister src) {
4214 assert(VM_Version::supports_sse4_1(), "");
4215 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4216 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4217 emit_int16(0x2B, (0xC0 | encode));
4218 }
4219
4220 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4221 assert(UseAVX > 0, "some form of AVX must be enabled");
4222 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4223 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4224 emit_int16(0x2B, (0xC0 | encode));
4225 }
4226
4227 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4228 assert(VM_Version::supports_avx2(), "");
4229 assert(vector_len != AVX_128bit, "");
4230 // VEX.256.66.0F3A.W1 00 /r ib
4231 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4232 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4233 emit_int24(0x00, (0xC0 | encode), imm8);
4234 }
4235
4236 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4237 assert(vector_len == AVX_256bit ? VM_Version::supports_avx512vl() :
4238 vector_len == AVX_512bit ? VM_Version::supports_evex() : false, "not supported");
4239 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4240 attributes.set_is_evex_instruction();
4241 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4242 emit_int16(0x36, (0xC0 | encode));
4243 }
4244
4245 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4246 assert(VM_Version::supports_avx512_vbmi(), "");
4247 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4248 attributes.set_is_evex_instruction();
4249 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4250 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4251 }
4252
4253 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4254 assert(VM_Version::supports_avx512_vbmi(), "");
4255 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4256 attributes.set_is_evex_instruction();
4257 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4258 emit_int8((unsigned char)0x8D);
4259 emit_operand(dst, src, 0);
4260 }
4261
4262 void Assembler::vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4263 assert(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() :
4264 vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() :
4265 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
4266 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4267 attributes.set_is_evex_instruction();
4268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4269 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4270 }
4271
4272 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4273 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4274 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4275 // VEX.NDS.256.66.0F38.W0 36 /r
4276 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4278 emit_int16(0x36, (0xC0 | encode));
4279 }
4280
4281 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4282 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4283 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4284 // VEX.NDS.256.66.0F38.W0 36 /r
4285 InstructionMark im(this);
4286 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4287 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4288 emit_int8(0x36);
4289 emit_operand(dst, src, 0);
4290 }
4291
4292 void Assembler::vpermps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4293 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4294 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4295 // VEX.NDS.XXX.66.0F38.W0 16 /r
4296 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4297 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4298 emit_int16(0x16, (0xC0 | encode));
4299 }
4300
4301 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4302 assert(VM_Version::supports_avx2(), "");
4303 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4304 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4305 emit_int24(0x46, (0xC0 | encode), imm8);
4306 }
4307
4308 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4309 assert(VM_Version::supports_avx(), "");
4310 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4312 emit_int24(0x06, (0xC0 | encode), imm8);
4313 }
4314
4315 void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4316 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4317 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4318 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4319 emit_int24(0x04, (0xC0 | encode), imm8);
4320 }
4321
4322 void Assembler::vpermilps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4323 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4324 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4325 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4326 emit_int16(0x0C, (0xC0 | encode));
4327 }
4328
4329 void Assembler::vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4330 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4331 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(),/* legacy_mode */ false,/* no_mask_reg */ true, /* uses_vl */ false);
4332 attributes.set_rex_vex_w_reverted();
4333 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4334 emit_int24(0x05, (0xC0 | encode), imm8);
4335 }
4336
4337 void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4338 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
4339 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ false);
4340 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4341 emit_int24(0x01, (0xC0 | encode), imm8);
4342 }
4343
4344 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4345 assert(VM_Version::supports_evex(), "");
4346 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4347 attributes.set_is_evex_instruction();
4348 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4349 emit_int16(0x76, (0xC0 | encode));
4350 }
4351
4352 void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4353 assert(VM_Version::supports_avx512_vbmi(), "");
4354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4355 attributes.set_is_evex_instruction();
4356 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4357 emit_int16(0x7D, (0xC0 | encode));
4358 }
4359
4360 void Assembler::evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) {
4361 assert(VM_Version::supports_avx512_vbmi(), "");
4362 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4363 attributes.set_is_evex_instruction();
4364 int encode = vex_prefix_and_encode(dst->encoding(), ctl->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4365 emit_int16((unsigned char)0x83, (unsigned char)(0xC0 | encode));
4366 }
4367
4368 void Assembler::pause() {
4369 emit_int16((unsigned char)0xF3, (unsigned char)0x90);
4370 }
4371
4372 void Assembler::ud2() {
4373 emit_int16(0x0F, 0x0B);
4374 }
4375
4376 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
4377 assert(VM_Version::supports_sse4_2(), "");
4378 InstructionMark im(this);
4379 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4380 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4381 emit_int8(0x61);
4382 emit_operand(dst, src, 1);
4383 emit_int8(imm8);
4384 }
4385
4386 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
4387 assert(VM_Version::supports_sse4_2(), "");
4388 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4389 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4390 emit_int24(0x61, (0xC0 | encode), imm8);
4391 }
4392
4393 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4394 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
4395 assert(VM_Version::supports_sse2(), "");
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4397 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4398 emit_int16(0x74, (0xC0 | encode));
4399 }
4400
4401 void Assembler::vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4402 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4403 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4404 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4405 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4406 emit_int16(cond_encoding, (0xC0 | encode));
4407 }
4408
4409 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4410 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4411 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4412 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4413 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4414 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4415 emit_int16(0x74, (0xC0 | encode));
4416 }
4417
4418 // In this context, kdst is written the mask used to process the equal components
4419 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4420 assert(VM_Version::supports_avx512bw(), "");
4421 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4422 attributes.set_is_evex_instruction();
4423 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4424 emit_int16(0x74, (0xC0 | encode));
4425 }
4426
4427 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4428 assert(VM_Version::supports_avx512vlbw(), "");
4429 InstructionMark im(this);
4430 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4431 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4432 attributes.set_is_evex_instruction();
4433 int dst_enc = kdst->encoding();
4434 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4435 emit_int8(0x64);
4436 emit_operand(as_Register(dst_enc), src, 0);
4437 }
4438
4439 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4440 assert(VM_Version::supports_avx512vlbw(), "");
4441 InstructionMark im(this);
4442 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4443 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4444 attributes.reset_is_clear_context();
4445 attributes.set_embedded_opmask_register_specifier(mask);
4446 attributes.set_is_evex_instruction();
4447 int dst_enc = kdst->encoding();
4448 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4449 emit_int8(0x64);
4450 emit_operand(as_Register(dst_enc), src, 0);
4451 }
4452
4453 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4454 assert(VM_Version::supports_avx512vlbw(), "");
4455 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4456 attributes.set_is_evex_instruction();
4457 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4458 emit_int24(0x3E, (0xC0 | encode), vcc);
4459 }
4460
4461 void Assembler::evpcmpuq(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4462 assert(VM_Version::supports_avx512vl(), "");
4463 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4464 attributes.set_is_evex_instruction();
4465 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4466 emit_int24(0x1E, (0xC0 | encode), vcc);
4467 }
4468
4469 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
4470 assert(VM_Version::supports_avx512vlbw(), "");
4471 InstructionMark im(this);
4472 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4473 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4474 attributes.set_is_evex_instruction();
4475 int dst_enc = kdst->encoding();
4476 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4477 emit_int8(0x3E);
4478 emit_operand(as_Register(dst_enc), src, 1);
4479 emit_int8(vcc);
4480 }
4481
4482 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4483 assert(VM_Version::supports_avx512bw(), "");
4484 InstructionMark im(this);
4485 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4486 attributes.set_is_evex_instruction();
4487 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4488 int dst_enc = kdst->encoding();
4489 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4490 emit_int8(0x74);
4491 emit_operand(as_Register(dst_enc), src, 0);
4492 }
4493
4494 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4495 assert(VM_Version::supports_avx512vlbw(), "");
4496 InstructionMark im(this);
4497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4498 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4499 attributes.reset_is_clear_context();
4500 attributes.set_embedded_opmask_register_specifier(mask);
4501 attributes.set_is_evex_instruction();
4502 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4503 emit_int8(0x74);
4504 emit_operand(as_Register(kdst->encoding()), src, 0);
4505 }
4506
4507 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4508 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
4509 assert(VM_Version::supports_sse2(), "");
4510 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4511 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4512 emit_int16(0x75, (0xC0 | encode));
4513 }
4514
4515 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4516 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4517 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4518 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4519 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4520 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4521 emit_int16(0x75, (0xC0 | encode));
4522 }
4523
4524 // In this context, kdst is written the mask used to process the equal components
4525 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4526 assert(VM_Version::supports_avx512bw(), "");
4527 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4528 attributes.set_is_evex_instruction();
4529 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4530 emit_int16(0x75, (0xC0 | encode));
4531 }
4532
4533 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4534 assert(VM_Version::supports_avx512bw(), "");
4535 InstructionMark im(this);
4536 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4537 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4538 attributes.set_is_evex_instruction();
4539 int dst_enc = kdst->encoding();
4540 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4541 emit_int8(0x75);
4542 emit_operand(as_Register(dst_enc), src, 0);
4543 }
4544
4545 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4546 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
4547 assert(VM_Version::supports_sse2(), "");
4548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4549 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4550 emit_int16(0x76, (0xC0 | encode));
4551 }
4552
4553 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4554 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4555 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4556 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4558 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4559 emit_int16(0x76, (0xC0 | encode));
4560 }
4561
4562 // In this context, kdst is written the mask used to process the equal components
4563 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4564 assert(VM_Version::supports_evex(), "");
4565 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4566 attributes.set_is_evex_instruction();
4567 attributes.reset_is_clear_context();
4568 attributes.set_embedded_opmask_register_specifier(mask);
4569 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4570 emit_int16(0x76, (0xC0 | encode));
4571 }
4572
4573 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4574 assert(VM_Version::supports_evex(), "");
4575 InstructionMark im(this);
4576 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4577 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4578 attributes.set_is_evex_instruction();
4579 attributes.reset_is_clear_context();
4580 attributes.set_embedded_opmask_register_specifier(mask);
4581 int dst_enc = kdst->encoding();
4582 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4583 emit_int8(0x76);
4584 emit_operand(as_Register(dst_enc), src, 0);
4585 }
4586
4587 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4588 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
4589 assert(VM_Version::supports_sse4_1(), "");
4590 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4591 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4592 emit_int16(0x29, (0xC0 | encode));
4593 }
4594
4595 void Assembler::evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4596 assert(VM_Version::supports_evex(), "");
4597 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4598 attributes.set_is_evex_instruction();
4599 attributes.reset_is_clear_context();
4600 attributes.set_embedded_opmask_register_specifier(mask);
4601 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4602 emit_int16(0x29, (0xC0 | encode));
4603 }
4604
4605 void Assembler::vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4606 assert(VM_Version::supports_avx(), "");
4607 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4608 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4609 emit_int16(cond_encoding, (0xC0 | encode));
4610 }
4611
4612 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4613 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4614 assert(VM_Version::supports_avx(), "");
4615 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4616 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4617 emit_int16(0x29, (0xC0 | encode));
4618 }
4619
4620 // In this context, kdst is written the mask used to process the equal components
4621 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4622 assert(VM_Version::supports_evex(), "");
4623 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4624 attributes.reset_is_clear_context();
4625 attributes.set_is_evex_instruction();
4626 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4627 emit_int16(0x29, (0xC0 | encode));
4628 }
4629
4630 // In this context, kdst is written the mask used to process the equal components
4631 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4632 assert(VM_Version::supports_evex(), "");
4633 InstructionMark im(this);
4634 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4635 attributes.reset_is_clear_context();
4636 attributes.set_is_evex_instruction();
4637 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4638 int dst_enc = kdst->encoding();
4639 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4640 emit_int8(0x29);
4641 emit_operand(as_Register(dst_enc), src, 0);
4642 }
4643
4644 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
4645 assert(VM_Version::supports_sse4_1(), "");
4646 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4647 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4648 emit_int16(0x37, (0xC0 | encode));
4649 }
4650
4651 void Assembler::pmovmskb(Register dst, XMMRegister src) {
4652 assert(VM_Version::supports_sse2(), "");
4653 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4654 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4655 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4656 }
4657
4658 void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
4659 assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||
4660 (VM_Version::supports_avx2() && vec_enc == AVX_256bit), "");
4661 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4662 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4663 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4664 }
4665
4666 void Assembler::vmovmskps(Register dst, XMMRegister src, int vec_enc) {
4667 assert(VM_Version::supports_avx(), "");
4668 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4669 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4670 emit_int16(0x50, (0xC0 | encode));
4671 }
4672
4673 void Assembler::vmovmskpd(Register dst, XMMRegister src, int vec_enc) {
4674 assert(VM_Version::supports_avx(), "");
4675 InstructionAttr attributes(vec_enc, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4676 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4677 emit_int16(0x50, (0xC0 | encode));
4678 }
4679
4680
4681 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
4682 assert(VM_Version::supports_sse4_1(), "");
4683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4684 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4685 emit_int24(0x16, (0xC0 | encode), imm8);
4686 }
4687
4688 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
4689 assert(VM_Version::supports_sse4_1(), "");
4690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4691 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4692 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4693 emit_int8(0x16);
4694 emit_operand(src, dst, 1);
4695 emit_int8(imm8);
4696 }
4697
4698 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
4699 assert(VM_Version::supports_sse4_1(), "");
4700 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4701 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4702 emit_int24(0x16, (0xC0 | encode), imm8);
4703 }
4704
4705 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
4706 assert(VM_Version::supports_sse4_1(), "");
4707 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4708 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4709 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4710 emit_int8(0x16);
4711 emit_operand(src, dst, 1);
4712 emit_int8(imm8);
4713 }
4714
4715 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
4716 assert(VM_Version::supports_sse2(), "");
4717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4718 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4719 emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
4720 }
4721
4722 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
4723 assert(VM_Version::supports_sse4_1(), "");
4724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4725 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4726 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4727 emit_int8(0x15);
4728 emit_operand(src, dst, 1);
4729 emit_int8(imm8);
4730 }
4731
4732 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
4733 assert(VM_Version::supports_sse4_1(), "");
4734 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4735 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4736 emit_int24(0x14, (0xC0 | encode), imm8);
4737 }
4738
4739 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
4740 assert(VM_Version::supports_sse4_1(), "");
4741 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4742 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4743 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4744 emit_int8(0x14);
4745 emit_operand(src, dst, 1);
4746 emit_int8(imm8);
4747 }
4748
4749 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
4750 assert(VM_Version::supports_sse4_1(), "");
4751 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4752 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4753 emit_int24(0x22, (0xC0 | encode), imm8);
4754 }
4755
4756 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
4757 assert(VM_Version::supports_sse4_1(), "");
4758 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4759 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4760 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4761 emit_int8(0x22);
4762 emit_operand(dst, src, 1);
4763 emit_int8(imm8);
4764 }
4765
4766 void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4767 assert(VM_Version::supports_avx(), "");
4768 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4769 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4770 emit_int24(0x22, (0xC0 | encode), imm8);
4771 }
4772
4773 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
4774 assert(VM_Version::supports_sse4_1(), "");
4775 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4776 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4777 emit_int24(0x22, (0xC0 | encode), imm8);
4778 }
4779
4780 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
4781 assert(VM_Version::supports_sse4_1(), "");
4782 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4783 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4784 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4785 emit_int8(0x22);
4786 emit_operand(dst, src, 1);
4787 emit_int8(imm8);
4788 }
4789
4790 void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4791 assert(VM_Version::supports_avx(), "");
4792 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4793 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4794 emit_int24(0x22, (0xC0 | encode), imm8);
4795 }
4796
4797 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
4798 assert(VM_Version::supports_sse2(), "");
4799 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4800 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4801 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4802 }
4803
4804 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
4805 assert(VM_Version::supports_sse2(), "");
4806 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4807 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4808 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4809 emit_int8((unsigned char)0xC4);
4810 emit_operand(dst, src, 1);
4811 emit_int8(imm8);
4812 }
4813
4814 void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4815 assert(VM_Version::supports_avx(), "");
4816 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4818 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4819 }
4820
4821 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
4822 assert(VM_Version::supports_sse4_1(), "");
4823 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4824 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4825 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4826 emit_int8(0x20);
4827 emit_operand(dst, src, 1);
4828 emit_int8(imm8);
4829 }
4830
4831 void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) {
4832 assert(VM_Version::supports_sse4_1(), "");
4833 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4834 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4835 emit_int24(0x20, (0xC0 | encode), imm8);
4836 }
4837
4838 void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4839 assert(VM_Version::supports_avx(), "");
4840 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4841 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4842 emit_int24(0x20, (0xC0 | encode), imm8);
4843 }
4844
4845 void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) {
4846 assert(VM_Version::supports_sse4_1(), "");
4847 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4848 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4849 emit_int24(0x21, (0xC0 | encode), imm8);
4850 }
4851
4852 void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4853 assert(VM_Version::supports_avx(), "");
4854 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4855 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4856 emit_int24(0x21, (0xC0 | encode), imm8);
4857 }
4858
4859 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
4860 assert(VM_Version::supports_sse4_1(), "");
4861 InstructionMark im(this);
4862 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4863 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4864 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4865 emit_int8(0x30);
4866 emit_operand(dst, src, 0);
4867 }
4868
4869 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4870 assert(VM_Version::supports_sse4_1(), "");
4871 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4872 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4873 emit_int16(0x30, (0xC0 | encode));
4874 }
4875
4876 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
4877 assert(VM_Version::supports_sse4_1(), "");
4878 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4879 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4880 emit_int16(0x20, (0xC0 | encode));
4881 }
4882
4883 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
4884 assert(VM_Version::supports_sse4_1(), "");
4885 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4886 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4887 emit_int16(0x35, (0xC0 | encode));
4888 }
4889
4890 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
4891 assert(VM_Version::supports_sse4_1(), "");
4892 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4893 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4894 emit_int16(0x21, (0xC0 | encode));
4895 }
4896
4897 void Assembler::pmovzxbd(XMMRegister dst, XMMRegister src) {
4898 assert(VM_Version::supports_sse4_1(), "");
4899 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4900 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4901 emit_int16(0x31, (0xC0 | encode));
4902 }
4903
4904 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
4905 assert(VM_Version::supports_sse4_1(), "");
4906 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4907 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4908 emit_int16(0x22, (0xC0 | encode));
4909 }
4910
4911 void Assembler::pmovsxwd(XMMRegister dst, XMMRegister src) {
4912 assert(VM_Version::supports_sse4_1(), "");
4913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4914 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4915 emit_int16(0x23, (0xC0 | encode));
4916 }
4917
4918 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4919 assert(VM_Version::supports_avx(), "");
4920 InstructionMark im(this);
4921 assert(dst != xnoreg, "sanity");
4922 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4923 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4924 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4925 emit_int8(0x30);
4926 emit_operand(dst, src, 0);
4927 }
4928
4929 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4930 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4931 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4932 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4933 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4934 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4935 emit_int16(0x30, (unsigned char) (0xC0 | encode));
4936 }
4937
4938 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4939 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4940 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4941 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4942 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4943 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4944 emit_int16(0x20, (0xC0 | encode));
4945 }
4946
4947 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4948 assert(VM_Version::supports_avx512vlbw(), "");
4949 assert(dst != xnoreg, "sanity");
4950 InstructionMark im(this);
4951 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4952 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4953 attributes.set_embedded_opmask_register_specifier(mask);
4954 attributes.set_is_evex_instruction();
4955 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4956 emit_int8(0x30);
4957 emit_operand(dst, src, 0);
4958 }
4959
4960 void Assembler::evpmovzxbd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4961 assert(VM_Version::supports_avx512vl(), "");
4962 assert(dst != xnoreg, "sanity");
4963 InstructionMark im(this);
4964 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4965 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4966 attributes.set_embedded_opmask_register_specifier(mask);
4967 attributes.set_is_evex_instruction();
4968 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4969 emit_int8(0x31);
4970 emit_operand(dst, src, 0);
4971 }
4972
4973 void Assembler::evpmovzxbd(XMMRegister dst, Address src, int vector_len) {
4974 evpmovzxbd(dst, k0, src, vector_len);
4975 }
4976
4977 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
4978 assert(VM_Version::supports_evex(), "");
4979 // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
4980 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4981 attributes.set_is_evex_instruction();
4982 attributes.set_embedded_opmask_register_specifier(mask);
4983 if (merge) {
4984 attributes.reset_is_clear_context();
4985 }
4986 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4987 emit_int16((unsigned char)0xDB, (0xC0 | encode));
4988 }
4989
4990 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4991 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4992 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4993 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4994 emit_int16(0x35, (0xC0 | encode));
4995 }
4996
4997 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4998 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4999 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5000 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5001 emit_int16(0x31, (0xC0 | encode));
5002 }
5003
5004 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
5005 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
5006 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5007 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5008 emit_int16(0x32, (0xC0 | encode));
5009 }
5010
5011 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
5012 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5013 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5014 VM_Version::supports_evex(), "");
5015 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5016 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5017 emit_int16(0x21, (0xC0 | encode));
5018 }
5019
5020 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
5021 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5022 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5023 VM_Version::supports_evex(), "");
5024 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5025 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5026 emit_int16(0x22, (0xC0 | encode));
5027 }
5028
5029 void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5030 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5031 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5032 VM_Version::supports_evex(), "");
5033 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5034 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5035 emit_int16(0x23, (0xC0 | encode));
5036 }
5037
5038 void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5039 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5040 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5041 VM_Version::supports_evex(), "");
5042 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5043 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5044 emit_int16(0x24, (0xC0 | encode));
5045 }
5046
5047 void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
5048 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5049 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5050 VM_Version::supports_evex(), "");
5051 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5052 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5053 emit_int16(0x25, (0xC0 | encode));
5054 }
5055
5056 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
5057 assert(VM_Version::supports_avx512vlbw(), "");
5058 assert(src != xnoreg, "sanity");
5059 InstructionMark im(this);
5060 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5061 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5062 attributes.set_is_evex_instruction();
5063 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5064 emit_int8(0x30);
5065 emit_operand(src, dst, 0);
5066 }
5067
5068 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
5069 assert(VM_Version::supports_avx512vlbw(), "");
5070 assert(src != xnoreg, "sanity");
5071 InstructionMark im(this);
5072 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5073 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5074 attributes.reset_is_clear_context();
5075 attributes.set_embedded_opmask_register_specifier(mask);
5076 attributes.set_is_evex_instruction();
5077 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5078 emit_int8(0x30);
5079 emit_operand(src, dst, 0);
5080 }
5081
5082 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
5083 assert(VM_Version::supports_evex(), "");
5084 assert(src != xnoreg, "sanity");
5085 InstructionMark im(this);
5086 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5087 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
5088 attributes.set_is_evex_instruction();
5089 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5090 emit_int8(0x31);
5091 emit_operand(src, dst, 0);
5092 }
5093
5094 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5095 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5096 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5097 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5098 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5099 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5100 emit_int16(0x33, (0xC0 | encode));
5101 }
5102
5103 void Assembler::vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5104 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5105 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5106 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5107 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5108 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5109 emit_int16(0x34, (0xC0 | encode));
5110 }
5111
5112 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
5113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5114 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5115 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5116 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5117 }
5118
5119 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5120 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5121 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5122 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
5123 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5124 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5125 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5126 }
5127
5128 void Assembler::vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5129 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5130 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5131 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5132 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5133 int encode = simd_prefix_and_encode(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5134 emit_int16(0x04, (0xC0 | encode));
5135 }
5136
5137 void Assembler::evpmadd52luq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5138 evpmadd52luq(dst, k0, src1, src2, false, vector_len);
5139 }
5140
5141 void Assembler::evpmadd52luq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5142 assert(VM_Version::supports_avx512ifma(), "");
5143 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5144 attributes.set_is_evex_instruction();
5145 attributes.set_embedded_opmask_register_specifier(mask);
5146 if (merge) {
5147 attributes.reset_is_clear_context();
5148 }
5149
5150 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5151 emit_int16((unsigned char)0xB4, (0xC0 | encode));
5152 }
5153
5154 void Assembler::evpmadd52huq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5155 evpmadd52huq(dst, k0, src1, src2, false, vector_len);
5156 }
5157
5158 void Assembler::evpmadd52huq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5159 assert(VM_Version::supports_avx512ifma(), "");
5160 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5161 attributes.set_is_evex_instruction();
5162 attributes.set_embedded_opmask_register_specifier(mask);
5163 if (merge) {
5164 attributes.reset_is_clear_context();
5165 }
5166
5167 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5168 emit_int16((unsigned char)0xB5, (0xC0 | encode));
5169 }
5170
5171 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5172 assert(VM_Version::supports_evex(), "");
5173 assert(VM_Version::supports_avx512_vnni(), "must support vnni");
5174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5175 attributes.set_is_evex_instruction();
5176 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5177 emit_int16(0x52, (0xC0 | encode));
5178 }
5179
5180 // generic
5181 void Assembler::pop(Register dst) {
5182 int encode = prefix_and_encode(dst->encoding());
5183 emit_int8(0x58 | encode);
5184 }
5185
5186 void Assembler::popcntl(Register dst, Address src) {
5187 assert(VM_Version::supports_popcnt(), "must support");
5188 InstructionMark im(this);
5189 emit_int8((unsigned char)0xF3);
5190 prefix(src, dst);
5191 emit_int16(0x0F, (unsigned char)0xB8);
5192 emit_operand(dst, src, 0);
5193 }
5194
5195 void Assembler::popcntl(Register dst, Register src) {
5196 assert(VM_Version::supports_popcnt(), "must support");
5197 emit_int8((unsigned char)0xF3);
5198 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5199 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
5200 }
5201
5202 void Assembler::evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5203 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5204 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5205 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5206 attributes.set_embedded_opmask_register_specifier(mask);
5207 attributes.set_is_evex_instruction();
5208 if (merge) {
5209 attributes.reset_is_clear_context();
5210 }
5211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5212 emit_int16(0x54, (0xC0 | encode));
5213 }
5214
5215 void Assembler::evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5216 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5217 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5218 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_is_evex_instruction();
5220 attributes.set_embedded_opmask_register_specifier(mask);
5221 if (merge) {
5222 attributes.reset_is_clear_context();
5223 }
5224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5225 emit_int16(0x54, (0xC0 | encode));
5226 }
5227
5228 void Assembler::evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5229 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5230 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5231 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5232 attributes.set_is_evex_instruction();
5233 attributes.set_embedded_opmask_register_specifier(mask);
5234 if (merge) {
5235 attributes.reset_is_clear_context();
5236 }
5237 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5238 emit_int16(0x55, (0xC0 | encode));
5239 }
5240
5241 void Assembler::evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5242 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5243 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5244 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5245 attributes.set_is_evex_instruction();
5246 attributes.set_embedded_opmask_register_specifier(mask);
5247 if (merge) {
5248 attributes.reset_is_clear_context();
5249 }
5250 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5251 emit_int16(0x55, (0xC0 | encode));
5252 }
5253
5254 void Assembler::popf() {
5255 emit_int8((unsigned char)0x9D);
5256 }
5257
5258 #ifndef _LP64 // no 32bit push/pop on amd64
5259 void Assembler::popl(Address dst) {
5260 // NOTE: this will adjust stack by 8byte on 64bits
5261 InstructionMark im(this);
5262 prefix(dst);
5263 emit_int8((unsigned char)0x8F);
5264 emit_operand(rax, dst, 0);
5265 }
5266 #endif
5267
5268 void Assembler::prefetchnta(Address src) {
5269 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5270 InstructionMark im(this);
5271 prefix(src);
5272 emit_int16(0x0F, 0x18);
5273 emit_operand(rax, src, 0); // 0, src
5274 }
5275
5276 void Assembler::prefetchr(Address src) {
5277 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5278 InstructionMark im(this);
5279 prefix(src);
5280 emit_int16(0x0F, 0x0D);
5281 emit_operand(rax, src, 0); // 0, src
5282 }
5283
5284 void Assembler::prefetcht0(Address src) {
5285 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5286 InstructionMark im(this);
5287 prefix(src);
5288 emit_int16(0x0F, 0x18);
5289 emit_operand(rcx, src, 0); // 1, src
5290 }
5291
5292 void Assembler::prefetcht1(Address src) {
5293 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5294 InstructionMark im(this);
5295 prefix(src);
5296 emit_int16(0x0F, 0x18);
5297 emit_operand(rdx, src, 0); // 2, src
5298 }
5299
5300 void Assembler::prefetcht2(Address src) {
5301 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5302 InstructionMark im(this);
5303 prefix(src);
5304 emit_int16(0x0F, 0x18);
5305 emit_operand(rbx, src, 0); // 3, src
5306 }
5307
5308 void Assembler::prefetchw(Address src) {
5309 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5310 InstructionMark im(this);
5311 prefix(src);
5312 emit_int16(0x0F, 0x0D);
5313 emit_operand(rcx, src, 0); // 1, src
5314 }
5315
5316 void Assembler::prefix(Prefix p) {
5317 emit_int8(p);
5318 }
5319
5320 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
5321 assert(VM_Version::supports_ssse3(), "");
5322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5323 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5324 emit_int16(0x00, (0xC0 | encode));
5325 }
5326
5327 void Assembler::evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
5328 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
5329 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5330 attributes.set_is_evex_instruction();
5331 attributes.set_embedded_opmask_register_specifier(mask);
5332 if (merge) {
5333 attributes.reset_is_clear_context();
5334 }
5335 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5336 emit_int16(0x00, (0xC0 | encode));
5337 }
5338
5339 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5340 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5341 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5342 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5343 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5344 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5345 emit_int16(0x00, (0xC0 | encode));
5346 }
5347
5348 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5349 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5350 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5351 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5352 InstructionMark im(this);
5353 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5354 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5355 simd_prefix(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5356 emit_int8(0x00);
5357 emit_operand(dst, src, 0);
5358 }
5359
5360 void Assembler::pshufb(XMMRegister dst, Address src) {
5361 assert(VM_Version::supports_ssse3(), "");
5362 InstructionMark im(this);
5363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5364 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5365 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5366 emit_int8(0x00);
5367 emit_operand(dst, src, 0);
5368 }
5369
5370 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
5371 assert(isByte(mode), "invalid value");
5372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5373 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
5374 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5375 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5376 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5377 }
5378
5379 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5380 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5381 (vector_len == AVX_256bit? VM_Version::supports_avx2() :
5382 (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
5383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5384 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5385 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5386 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5387 }
5388
5389 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
5390 assert(isByte(mode), "invalid value");
5391 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5392 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5393 InstructionMark im(this);
5394 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5395 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5396 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5397 emit_int8(0x70);
5398 emit_operand(dst, src, 1);
5399 emit_int8(mode & 0xFF);
5400 }
5401
5402 void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) {
5403 assert(isByte(mode), "invalid value");
5404 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5406 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5407 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5408 }
5409
5410 void Assembler::vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5411 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5412 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5413 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5414 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5415 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5416 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5417 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5418 }
5419
5420 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5421 assert(isByte(mode), "invalid value");
5422 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5423 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5424 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5425 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5426 }
5427
5428 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
5429 assert(isByte(mode), "invalid value");
5430 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5431 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5432 InstructionMark im(this);
5433 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5434 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5435 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5436 emit_int8(0x70);
5437 emit_operand(dst, src, 1);
5438 emit_int8(mode & 0xFF);
5439 }
5440
5441 void Assembler::vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5442 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5443 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5444 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5445 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5446 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5447 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5448 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5449 }
5450
5451 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5452 assert(VM_Version::supports_evex(), "requires EVEX support");
5453 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
5454 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5455 attributes.set_is_evex_instruction();
5456 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5457 emit_int24(0x43, (0xC0 | encode), imm8 & 0xFF);
5458 }
5459
5460 void Assembler::shufpd(XMMRegister dst, XMMRegister src, int imm8) {
5461 assert(isByte(imm8), "invalid value");
5462 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5463 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5464 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5465 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5466 }
5467
5468 void Assembler::vshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5469 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5470 attributes.set_rex_vex_w_reverted();
5471 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5472 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5473 }
5474
5475 void Assembler::shufps(XMMRegister dst, XMMRegister src, int imm8) {
5476 assert(isByte(imm8), "invalid value");
5477 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5478 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5479 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5480 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5481 }
5482
5483 void Assembler::vshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5484 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5485 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5486 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5487 }
5488
5489 void Assembler::psrldq(XMMRegister dst, int shift) {
5490 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5491 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5492 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5493 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5494 emit_int24(0x73, (0xC0 | encode), shift);
5495 }
5496
5497 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5498 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5499 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5500 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5501 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5502 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5503 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5504 }
5505
5506 void Assembler::pslldq(XMMRegister dst, int shift) {
5507 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5508 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5509 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5510 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
5511 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5512 emit_int24(0x73, (0xC0 | encode), shift);
5513 }
5514
5515 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5516 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5517 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5518 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5519 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5520 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5521 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5522 }
5523
5524 void Assembler::ptest(XMMRegister dst, Address src) {
5525 assert(VM_Version::supports_sse4_1(), "");
5526 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5527 InstructionMark im(this);
5528 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5529 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5530 emit_int8(0x17);
5531 emit_operand(dst, src, 0);
5532 }
5533
5534 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
5535 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
5536 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5537 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5538 emit_int8(0x17);
5539 emit_int8((0xC0 | encode));
5540 }
5541
5542 void Assembler::vptest(XMMRegister dst, Address src) {
5543 assert(VM_Version::supports_avx(), "");
5544 InstructionMark im(this);
5545 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5546 assert(dst != xnoreg, "sanity");
5547 // swap src<->dst for encoding
5548 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5549 emit_int8(0x17);
5550 emit_operand(dst, src, 0);
5551 }
5552
5553 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
5554 assert(VM_Version::supports_avx(), "");
5555 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5556 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5557 emit_int16(0x17, (0xC0 | encode));
5558 }
5559
5560 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
5561 assert(VM_Version::supports_avx(), "");
5562 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5563 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5564 emit_int16(0x17, (0xC0 | encode));
5565 }
5566
5567 void Assembler::vtestps(XMMRegister dst, XMMRegister src, int vector_len) {
5568 assert(VM_Version::supports_avx(), "");
5569 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5570 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5571 emit_int16(0x0E, (0xC0 | encode));
5572 }
5573
5574 void Assembler::evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5575 assert(vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : VM_Version::supports_avx512vlbw(), "");
5576 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5578 attributes.set_is_evex_instruction();
5579 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5580 emit_int16(0x26, (0xC0 | encode));
5581 }
5582
5583 void Assembler::evptestmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5584 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5585 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5587 attributes.set_is_evex_instruction();
5588 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5589 emit_int16(0x27, (0xC0 | encode));
5590 }
5591
5592 void Assembler::evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5593 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5594 // Encoding: EVEX.NDS.XXX.F3.0F38.W0 DB /r
5595 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5596 attributes.set_is_evex_instruction();
5597 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5598 emit_int16(0x27, (0xC0 | encode));
5599 }
5600
5601 void Assembler::punpcklbw(XMMRegister dst, Address src) {
5602 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5603 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5604 InstructionMark im(this);
5605 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5606 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5607 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5608 emit_int8(0x60);
5609 emit_operand(dst, src, 0);
5610 }
5611
5612 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
5613 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5614 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5615 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5616 emit_int16(0x60, (0xC0 | encode));
5617 }
5618
5619 void Assembler::punpckldq(XMMRegister dst, Address src) {
5620 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5621 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5622 InstructionMark im(this);
5623 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5624 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5625 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5626 emit_int8(0x62);
5627 emit_operand(dst, src, 0);
5628 }
5629
5630 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
5631 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5632 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5633 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5634 emit_int16(0x62, (0xC0 | encode));
5635 }
5636
5637 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
5638 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5639 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5640 attributes.set_rex_vex_w_reverted();
5641 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5642 emit_int16(0x6C, (0xC0 | encode));
5643 }
5644
5645 void Assembler::evpunpcklqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5646 evpunpcklqdq(dst, k0, src1, src2, false, vector_len);
5647 }
5648
5649 void Assembler::evpunpcklqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5650 assert(VM_Version::supports_evex(), "requires AVX512F");
5651 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5652 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5653 attributes.set_is_evex_instruction();
5654 attributes.set_embedded_opmask_register_specifier(mask);
5655 if (merge) {
5656 attributes.reset_is_clear_context();
5657 }
5658
5659 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5660 emit_int16(0x6C, (0xC0 | encode));
5661 }
5662
5663 void Assembler::evpunpckhqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5664 evpunpckhqdq(dst, k0, src1, src2, false, vector_len);
5665 }
5666
5667 void Assembler::evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5668 assert(VM_Version::supports_evex(), "requires AVX512F");
5669 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5670 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5671 attributes.set_is_evex_instruction();
5672 attributes.set_embedded_opmask_register_specifier(mask);
5673 if (merge) {
5674 attributes.reset_is_clear_context();
5675 }
5676
5677 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5678 emit_int16(0x6D, (0xC0 | encode));
5679 }
5680
5681 void Assembler::push(int32_t imm32) {
5682 // in 64bits we push 64bits onto the stack but only
5683 // take a 32bit immediate
5684 emit_int8(0x68);
5685 emit_int32(imm32);
5686 }
5687
5688 void Assembler::push(Register src) {
5689 int encode = prefix_and_encode(src->encoding());
5690 emit_int8(0x50 | encode);
5691 }
5692
5693 void Assembler::pushf() {
5694 emit_int8((unsigned char)0x9C);
5695 }
5696
5697 #ifndef _LP64 // no 32bit push/pop on amd64
5698 void Assembler::pushl(Address src) {
5699 // Note this will push 64bit on 64bit
5700 InstructionMark im(this);
5701 prefix(src);
5702 emit_int8((unsigned char)0xFF);
5703 emit_operand(rsi, src, 0);
5704 }
5705 #endif
5706
5707 void Assembler::rcll(Register dst, int imm8) {
5708 assert(isShiftCount(imm8), "illegal shift count");
5709 int encode = prefix_and_encode(dst->encoding());
5710 if (imm8 == 1) {
5711 emit_int16((unsigned char)0xD1, (0xD0 | encode));
5712 } else {
5713 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
5714 }
5715 }
5716
5717 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
5718 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5719 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5720 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5721 emit_int16(0x53, (0xC0 | encode));
5722 }
5723
5724 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
5725 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5726 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5727 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5728 emit_int16(0x53, (0xC0 | encode));
5729 }
5730
5731 void Assembler::rdtsc() {
5732 emit_int16(0x0F, 0x31);
5733 }
5734
5735 void Assembler::rdtscp() {
5736 emit_int24(0x0F, 0x01, (unsigned char)0xF9);
5737 }
5738
5739 // copies data from [esi] to [edi] using rcx pointer sized words
5740 // generic
5741 void Assembler::rep_mov() {
5742 // REP
5743 // MOVSQ
5744 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
5745 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);)
5746 }
5747
5748 // sets rcx bytes with rax, value at [edi]
5749 void Assembler::rep_stosb() {
5750 // REP
5751 // STOSB
5752 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
5753 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);)
5754 }
5755
5756 // sets rcx pointer sized words with rax, value at [edi]
5757 // generic
5758 void Assembler::rep_stos() {
5759 // REP
5760 // LP64:STOSQ, LP32:STOSD
5761 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
5762 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
5763 }
5764
5765 // scans rcx pointer sized words at [edi] for occurrence of rax,
5766 // generic
5767 void Assembler::repne_scan() { // repne_scan
5768 // SCASQ
5769 LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
5770 NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);)
5771 }
5772
5773 #ifdef _LP64
5774 // scans rcx 4 byte words at [edi] for occurrence of rax,
5775 // generic
5776 void Assembler::repne_scanl() { // repne_scan
5777 // SCASL
5778 emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
5779 }
5780 #endif
5781
5782 void Assembler::ret(int imm16) {
5783 if (imm16 == 0) {
5784 emit_int8((unsigned char)0xC3);
5785 } else {
5786 emit_int8((unsigned char)0xC2);
5787 emit_int16(imm16);
5788 }
5789 }
5790
5791 void Assembler::roll(Register dst, int imm8) {
5792 assert(isShiftCount(imm8), "illegal shift count");
5793 int encode = prefix_and_encode(dst->encoding());
5794 if (imm8 == 1) {
5795 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5796 } else {
5797 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5798 }
5799 }
5800
5801 void Assembler::roll(Register dst) {
5802 int encode = prefix_and_encode(dst->encoding());
5803 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5804 }
5805
5806 void Assembler::rorl(Register dst, int imm8) {
5807 assert(isShiftCount(imm8), "illegal shift count");
5808 int encode = prefix_and_encode(dst->encoding());
5809 if (imm8 == 1) {
5810 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5811 } else {
5812 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5813 }
5814 }
5815
5816 void Assembler::rorl(Register dst) {
5817 int encode = prefix_and_encode(dst->encoding());
5818 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5819 }
5820
5821 #ifdef _LP64
5822 void Assembler::rorq(Register dst) {
5823 int encode = prefixq_and_encode(dst->encoding());
5824 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5825 }
5826
5827 void Assembler::rorq(Register dst, int imm8) {
5828 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5829 int encode = prefixq_and_encode(dst->encoding());
5830 if (imm8 == 1) {
5831 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5832 } else {
5833 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5834 }
5835 }
5836
5837 void Assembler::rolq(Register dst) {
5838 int encode = prefixq_and_encode(dst->encoding());
5839 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5840 }
5841
5842 void Assembler::rolq(Register dst, int imm8) {
5843 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5844 int encode = prefixq_and_encode(dst->encoding());
5845 if (imm8 == 1) {
5846 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5847 } else {
5848 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5849 }
5850 }
5851 #endif
5852
5853 void Assembler::sahf() {
5854 #ifdef _LP64
5855 // Not supported in 64bit mode
5856 ShouldNotReachHere();
5857 #endif
5858 emit_int8((unsigned char)0x9E);
5859 }
5860
5861 void Assembler::sall(Address dst, int imm8) {
5862 InstructionMark im(this);
5863 assert(isShiftCount(imm8), "illegal shift count");
5864 prefix(dst);
5865 if (imm8 == 1) {
5866 emit_int8((unsigned char)0xD1);
5867 emit_operand(as_Register(4), dst, 0);
5868 }
5869 else {
5870 emit_int8((unsigned char)0xC1);
5871 emit_operand(as_Register(4), dst, 1);
5872 emit_int8(imm8);
5873 }
5874 }
5875
5876 void Assembler::sall(Address dst) {
5877 InstructionMark im(this);
5878 prefix(dst);
5879 emit_int8((unsigned char)0xD3);
5880 emit_operand(as_Register(4), dst, 0);
5881 }
5882
5883 void Assembler::sall(Register dst, int imm8) {
5884 assert(isShiftCount(imm8), "illegal shift count");
5885 int encode = prefix_and_encode(dst->encoding());
5886 if (imm8 == 1) {
5887 emit_int16((unsigned char)0xD1, (0xE0 | encode));
5888 } else {
5889 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
5890 }
5891 }
5892
5893 void Assembler::sall(Register dst) {
5894 int encode = prefix_and_encode(dst->encoding());
5895 emit_int16((unsigned char)0xD3, (0xE0 | encode));
5896 }
5897
5898 void Assembler::sarl(Address dst, int imm8) {
5899 assert(isShiftCount(imm8), "illegal shift count");
5900 InstructionMark im(this);
5901 prefix(dst);
5902 if (imm8 == 1) {
5903 emit_int8((unsigned char)0xD1);
5904 emit_operand(as_Register(7), dst, 0);
5905 }
5906 else {
5907 emit_int8((unsigned char)0xC1);
5908 emit_operand(as_Register(7), dst, 1);
5909 emit_int8(imm8);
5910 }
5911 }
5912
5913 void Assembler::sarl(Address dst) {
5914 InstructionMark im(this);
5915 prefix(dst);
5916 emit_int8((unsigned char)0xD3);
5917 emit_operand(as_Register(7), dst, 0);
5918 }
5919
5920 void Assembler::sarl(Register dst, int imm8) {
5921 int encode = prefix_and_encode(dst->encoding());
5922 assert(isShiftCount(imm8), "illegal shift count");
5923 if (imm8 == 1) {
5924 emit_int16((unsigned char)0xD1, (0xF8 | encode));
5925 } else {
5926 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
5927 }
5928 }
5929
5930 void Assembler::sarl(Register dst) {
5931 int encode = prefix_and_encode(dst->encoding());
5932 emit_int16((unsigned char)0xD3, (0xF8 | encode));
5933 }
5934
5935 void Assembler::sbbl(Address dst, int32_t imm32) {
5936 InstructionMark im(this);
5937 prefix(dst);
5938 emit_arith_operand(0x81, rbx, dst, imm32);
5939 }
5940
5941 void Assembler::sbbl(Register dst, int32_t imm32) {
5942 prefix(dst);
5943 emit_arith(0x81, 0xD8, dst, imm32);
5944 }
5945
5946
5947 void Assembler::sbbl(Register dst, Address src) {
5948 InstructionMark im(this);
5949 prefix(src, dst);
5950 emit_int8(0x1B);
5951 emit_operand(dst, src, 0);
5952 }
5953
5954 void Assembler::sbbl(Register dst, Register src) {
5955 (void) prefix_and_encode(dst->encoding(), src->encoding());
5956 emit_arith(0x1B, 0xC0, dst, src);
5957 }
5958
5959 void Assembler::setb(Condition cc, Register dst) {
5960 assert(0 <= cc && cc < 16, "illegal cc");
5961 int encode = prefix_and_encode(dst->encoding(), true);
5962 emit_int24(0x0F, (unsigned char)0x90 | cc, (0xC0 | encode));
5963 }
5964
5965 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
5966 assert(VM_Version::supports_ssse3(), "");
5967 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5968 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5969 emit_int24(0x0F, (0xC0 | encode), imm8);
5970 }
5971
5972 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5973 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5974 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5975 0, "");
5976 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5977 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5978 emit_int24(0x0F, (0xC0 | encode), imm8);
5979 }
5980
5981 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5982 assert(VM_Version::supports_evex(), "");
5983 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5984 attributes.set_is_evex_instruction();
5985 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5986 emit_int24(0x3, (0xC0 | encode), imm8);
5987 }
5988
5989 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
5990 assert(VM_Version::supports_sse4_1(), "");
5991 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5992 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5993 emit_int24(0x0E, (0xC0 | encode), imm8);
5994 }
5995
5996 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
5997 assert(VM_Version::supports_sha(), "");
5998 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
5999 emit_int24((unsigned char)0xCC, (0xC0 | encode), (unsigned char)imm8);
6000 }
6001
6002 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
6003 assert(VM_Version::supports_sha(), "");
6004 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6005 emit_int16((unsigned char)0xC8, (0xC0 | encode));
6006 }
6007
6008 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
6009 assert(VM_Version::supports_sha(), "");
6010 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6011 emit_int16((unsigned char)0xC9, (0xC0 | encode));
6012 }
6013
6014 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
6015 assert(VM_Version::supports_sha(), "");
6016 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6017 emit_int16((unsigned char)0xCA, (0xC0 | encode));
6018 }
6019
6020 // xmm0 is implicit additional source to this instruction.
6021 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
6022 assert(VM_Version::supports_sha(), "");
6023 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6024 emit_int16((unsigned char)0xCB, (0xC0 | encode));
6025 }
6026
6027 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
6028 assert(VM_Version::supports_sha(), "");
6029 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6030 emit_int16((unsigned char)0xCC, (0xC0 | encode));
6031 }
6032
6033 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
6034 assert(VM_Version::supports_sha(), "");
6035 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
6036 emit_int16((unsigned char)0xCD, (0xC0 | encode));
6037 }
6038
6039
6040 void Assembler::shll(Register dst, int imm8) {
6041 assert(isShiftCount(imm8), "illegal shift count");
6042 int encode = prefix_and_encode(dst->encoding());
6043 if (imm8 == 1 ) {
6044 emit_int16((unsigned char)0xD1, (0xE0 | encode));
6045 } else {
6046 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
6047 }
6048 }
6049
6050 void Assembler::shll(Register dst) {
6051 int encode = prefix_and_encode(dst->encoding());
6052 emit_int16((unsigned char)0xD3, (0xE0 | encode));
6053 }
6054
6055 void Assembler::shrl(Register dst, int imm8) {
6056 assert(isShiftCount(imm8), "illegal shift count");
6057 int encode = prefix_and_encode(dst->encoding());
6058 if (imm8 == 1) {
6059 emit_int16((unsigned char)0xD1, (0xE8 | encode));
6060 }
6061 else {
6062 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
6063 }
6064 }
6065
6066 void Assembler::shrl(Register dst) {
6067 int encode = prefix_and_encode(dst->encoding());
6068 emit_int16((unsigned char)0xD3, (0xE8 | encode));
6069 }
6070
6071 void Assembler::shrl(Address dst) {
6072 InstructionMark im(this);
6073 prefix(dst);
6074 emit_int8((unsigned char)0xD3);
6075 emit_operand(as_Register(5), dst, 0);
6076 }
6077
6078 void Assembler::shrl(Address dst, int imm8) {
6079 InstructionMark im(this);
6080 assert(isShiftCount(imm8), "illegal shift count");
6081 prefix(dst);
6082 if (imm8 == 1) {
6083 emit_int8((unsigned char)0xD1);
6084 emit_operand(as_Register(5), dst, 0);
6085 }
6086 else {
6087 emit_int8((unsigned char)0xC1);
6088 emit_operand(as_Register(5), dst, 1);
6089 emit_int8(imm8);
6090 }
6091 }
6092
6093
6094 void Assembler::shldl(Register dst, Register src) {
6095 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6096 emit_int24(0x0F, (unsigned char)0xA5, (0xC0 | encode));
6097 }
6098
6099 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6100 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6101 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6102 }
6103
6104 void Assembler::shrdl(Register dst, Register src) {
6105 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6106 emit_int24(0x0F, (unsigned char)0xAD, (0xC0 | encode));
6107 }
6108
6109 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
6110 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6111 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6112 }
6113
6114 #ifdef _LP64
6115 void Assembler::shldq(Register dst, Register src, int8_t imm8) {
6116 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6117 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6118 }
6119
6120 void Assembler::shrdq(Register dst, Register src, int8_t imm8) {
6121 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6122 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6123 }
6124 #endif
6125
6126 // copies a single word from [esi] to [edi]
6127 void Assembler::smovl() {
6128 emit_int8((unsigned char)0xA5);
6129 }
6130
6131 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
6132 assert(VM_Version::supports_sse4_1(), "");
6133 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6134 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6135 emit_int24(0x0B, (0xC0 | encode), (unsigned char)rmode);
6136 }
6137
6138 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
6139 assert(VM_Version::supports_sse4_1(), "");
6140 InstructionMark im(this);
6141 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6142 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6143 emit_int8(0x0B);
6144 emit_operand(dst, src, 1);
6145 emit_int8((unsigned char)rmode);
6146 }
6147
6148 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
6149 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6150 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6151 attributes.set_rex_vex_w_reverted();
6152 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6153 emit_int16(0x51, (0xC0 | encode));
6154 }
6155
6156 void Assembler::sqrtsd(XMMRegister dst, Address src) {
6157 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6158 InstructionMark im(this);
6159 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6160 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6161 attributes.set_rex_vex_w_reverted();
6162 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6163 emit_int8(0x51);
6164 emit_operand(dst, src, 0);
6165 }
6166
6167 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
6168 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6169 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6170 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6171 emit_int16(0x51, (0xC0 | encode));
6172 }
6173
6174 void Assembler::std() {
6175 emit_int8((unsigned char)0xFD);
6176 }
6177
6178 void Assembler::sqrtss(XMMRegister dst, Address src) {
6179 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6180 InstructionMark im(this);
6181 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6182 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6183 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6184 emit_int8(0x51);
6185 emit_operand(dst, src, 0);
6186 }
6187
6188 void Assembler::stmxcsr( Address dst) {
6189 if (UseAVX > 0 ) {
6190 assert(VM_Version::supports_avx(), "");
6191 InstructionMark im(this);
6192 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6193 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6194 emit_int8((unsigned char)0xAE);
6195 emit_operand(as_Register(3), dst, 0);
6196 } else {
6197 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6198 InstructionMark im(this);
6199 prefix(dst);
6200 emit_int16(0x0F, (unsigned char)0xAE);
6201 emit_operand(as_Register(3), dst, 0);
6202 }
6203 }
6204
6205 void Assembler::subl(Address dst, int32_t imm32) {
6206 InstructionMark im(this);
6207 prefix(dst);
6208 emit_arith_operand(0x81, rbp, dst, imm32);
6209 }
6210
6211 void Assembler::subl(Address dst, Register src) {
6212 InstructionMark im(this);
6213 prefix(dst, src);
6214 emit_int8(0x29);
6215 emit_operand(src, dst, 0);
6216 }
6217
6218 void Assembler::subl(Register dst, int32_t imm32) {
6219 prefix(dst);
6220 emit_arith(0x81, 0xE8, dst, imm32);
6221 }
6222
6223 // Force generation of a 4 byte immediate value even if it fits into 8bit
6224 void Assembler::subl_imm32(Register dst, int32_t imm32) {
6225 prefix(dst);
6226 emit_arith_imm32(0x81, 0xE8, dst, imm32);
6227 }
6228
6229 void Assembler::subl(Register dst, Address src) {
6230 InstructionMark im(this);
6231 prefix(src, dst);
6232 emit_int8(0x2B);
6233 emit_operand(dst, src, 0);
6234 }
6235
6236 void Assembler::subl(Register dst, Register src) {
6237 (void) prefix_and_encode(dst->encoding(), src->encoding());
6238 emit_arith(0x2B, 0xC0, dst, src);
6239 }
6240
6241 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
6242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6243 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6244 attributes.set_rex_vex_w_reverted();
6245 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6246 emit_int16(0x5C, (0xC0 | encode));
6247 }
6248
6249 void Assembler::subsd(XMMRegister dst, Address src) {
6250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6251 InstructionMark im(this);
6252 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6253 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6254 attributes.set_rex_vex_w_reverted();
6255 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6256 emit_int8(0x5C);
6257 emit_operand(dst, src, 0);
6258 }
6259
6260 void Assembler::subss(XMMRegister dst, XMMRegister src) {
6261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
6263 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6264 emit_int16(0x5C, (0xC0 | encode));
6265 }
6266
6267 void Assembler::subss(XMMRegister dst, Address src) {
6268 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6269 InstructionMark im(this);
6270 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6271 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6272 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6273 emit_int8(0x5C);
6274 emit_operand(dst, src, 0);
6275 }
6276
6277 void Assembler::testb(Register dst, int imm8, bool use_ral) {
6278 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
6279 if (dst == rax) {
6280 if (use_ral) {
6281 emit_int8((unsigned char)0xA8);
6282 emit_int8(imm8);
6283 } else {
6284 emit_int8((unsigned char)0xF6);
6285 emit_int8((unsigned char)0xC4);
6286 emit_int8(imm8);
6287 }
6288 } else {
6289 (void) prefix_and_encode(dst->encoding(), true);
6290 emit_arith_b(0xF6, 0xC0, dst, imm8);
6291 }
6292 }
6293
6294 void Assembler::testb(Address dst, int imm8) {
6295 InstructionMark im(this);
6296 prefix(dst);
6297 emit_int8((unsigned char)0xF6);
6298 emit_operand(rax, dst, 1);
6299 emit_int8(imm8);
6300 }
6301
6302 void Assembler::testl(Address dst, int32_t imm32) {
6303 InstructionMark im(this);
6304 prefix(dst);
6305 emit_int8((unsigned char)0xF7);
6306 emit_operand(as_Register(0), dst, 4);
6307 emit_int32(imm32);
6308 }
6309
6310 void Assembler::testl(Register dst, int32_t imm32) {
6311 // not using emit_arith because test
6312 // doesn't support sign-extension of
6313 // 8bit operands
6314 if (dst == rax) {
6315 emit_int8((unsigned char)0xA9);
6316 emit_int32(imm32);
6317 } else {
6318 int encode = dst->encoding();
6319 encode = prefix_and_encode(encode);
6320 emit_int16((unsigned char)0xF7, (0xC0 | encode));
6321 emit_int32(imm32);
6322 }
6323 }
6324
6325 void Assembler::testl(Register dst, Register src) {
6326 (void) prefix_and_encode(dst->encoding(), src->encoding());
6327 emit_arith(0x85, 0xC0, dst, src);
6328 }
6329
6330 void Assembler::testl(Register dst, Address src) {
6331 InstructionMark im(this);
6332 prefix(src, dst);
6333 emit_int8((unsigned char)0x85);
6334 emit_operand(dst, src, 0);
6335 }
6336
6337 void Assembler::tzcntl(Register dst, Register src) {
6338 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6339 emit_int8((unsigned char)0xF3);
6340 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6341 emit_int24(0x0F,
6342 (unsigned char)0xBC,
6343 0xC0 | encode);
6344 }
6345
6346 void Assembler::tzcntl(Register dst, Address src) {
6347 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6348 InstructionMark im(this);
6349 emit_int8((unsigned char)0xF3);
6350 prefix(src, dst);
6351 emit_int16(0x0F, (unsigned char)0xBC);
6352 emit_operand(dst, src, 0);
6353 }
6354
6355 void Assembler::tzcntq(Register dst, Register src) {
6356 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6357 emit_int8((unsigned char)0xF3);
6358 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6359 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
6360 }
6361
6362 void Assembler::tzcntq(Register dst, Address src) {
6363 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6364 InstructionMark im(this);
6365 emit_int8((unsigned char)0xF3);
6366 prefixq(src, dst);
6367 emit_int16(0x0F, (unsigned char)0xBC);
6368 emit_operand(dst, src, 0);
6369 }
6370
6371 void Assembler::ucomisd(XMMRegister dst, Address src) {
6372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6373 InstructionMark im(this);
6374 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6375 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6376 attributes.set_rex_vex_w_reverted();
6377 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6378 emit_int8(0x2E);
6379 emit_operand(dst, src, 0);
6380 }
6381
6382 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
6383 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6384 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6385 attributes.set_rex_vex_w_reverted();
6386 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6387 emit_int16(0x2E, (0xC0 | encode));
6388 }
6389
6390 void Assembler::ucomiss(XMMRegister dst, Address src) {
6391 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6392 InstructionMark im(this);
6393 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6394 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6395 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6396 emit_int8(0x2E);
6397 emit_operand(dst, src, 0);
6398 }
6399
6400 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
6401 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6402 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6403 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6404 emit_int16(0x2E, (0xC0 | encode));
6405 }
6406
6407 void Assembler::xabort(int8_t imm8) {
6408 emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF));
6409 }
6410
6411 void Assembler::xaddb(Address dst, Register src) {
6412 InstructionMark im(this);
6413 prefix(dst, src, true);
6414 emit_int16(0x0F, (unsigned char)0xC0);
6415 emit_operand(src, dst, 0);
6416 }
6417
6418 void Assembler::xaddw(Address dst, Register src) {
6419 InstructionMark im(this);
6420 emit_int8(0x66);
6421 prefix(dst, src);
6422 emit_int16(0x0F, (unsigned char)0xC1);
6423 emit_operand(src, dst, 0);
6424 }
6425
6426 void Assembler::xaddl(Address dst, Register src) {
6427 InstructionMark im(this);
6428 prefix(dst, src);
6429 emit_int16(0x0F, (unsigned char)0xC1);
6430 emit_operand(src, dst, 0);
6431 }
6432
6433 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
6434 InstructionMark im(this);
6435 relocate(rtype);
6436 if (abort.is_bound()) {
6437 address entry = target(abort);
6438 assert(entry != nullptr, "abort entry null");
6439 int offset = checked_cast<int>(entry - pc());
6440 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6441 emit_int32(offset - 6); // 2 opcode + 4 address
6442 } else {
6443 abort.add_patch_at(code(), locator());
6444 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6445 emit_int32(0);
6446 }
6447 }
6448
6449 void Assembler::xchgb(Register dst, Address src) { // xchg
6450 InstructionMark im(this);
6451 prefix(src, dst, true);
6452 emit_int8((unsigned char)0x86);
6453 emit_operand(dst, src, 0);
6454 }
6455
6456 void Assembler::xchgw(Register dst, Address src) { // xchg
6457 InstructionMark im(this);
6458 emit_int8(0x66);
6459 prefix(src, dst);
6460 emit_int8((unsigned char)0x87);
6461 emit_operand(dst, src, 0);
6462 }
6463
6464 void Assembler::xchgl(Register dst, Address src) { // xchg
6465 InstructionMark im(this);
6466 prefix(src, dst);
6467 emit_int8((unsigned char)0x87);
6468 emit_operand(dst, src, 0);
6469 }
6470
6471 void Assembler::xchgl(Register dst, Register src) {
6472 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6473 emit_int16((unsigned char)0x87, (0xC0 | encode));
6474 }
6475
6476 void Assembler::xend() {
6477 emit_int24(0x0F, 0x01, (unsigned char)0xD5);
6478 }
6479
6480 void Assembler::xgetbv() {
6481 emit_int24(0x0F, 0x01, (unsigned char)0xD0);
6482 }
6483
6484 void Assembler::xorl(Address dst, int32_t imm32) {
6485 InstructionMark im(this);
6486 prefix(dst);
6487 emit_arith_operand(0x81, as_Register(6), dst, imm32);
6488 }
6489
6490 void Assembler::xorl(Register dst, int32_t imm32) {
6491 prefix(dst);
6492 emit_arith(0x81, 0xF0, dst, imm32);
6493 }
6494
6495 void Assembler::xorl(Register dst, Address src) {
6496 InstructionMark im(this);
6497 prefix(src, dst);
6498 emit_int8(0x33);
6499 emit_operand(dst, src, 0);
6500 }
6501
6502 void Assembler::xorl(Register dst, Register src) {
6503 (void) prefix_and_encode(dst->encoding(), src->encoding());
6504 emit_arith(0x33, 0xC0, dst, src);
6505 }
6506
6507 void Assembler::xorl(Address dst, Register src) {
6508 InstructionMark im(this);
6509 prefix(dst, src);
6510 emit_int8(0x31);
6511 emit_operand(src, dst, 0);
6512 }
6513
6514 void Assembler::xorb(Register dst, Address src) {
6515 InstructionMark im(this);
6516 prefix(src, dst);
6517 emit_int8(0x32);
6518 emit_operand(dst, src, 0);
6519 }
6520
6521 void Assembler::xorb(Address dst, Register src) {
6522 InstructionMark im(this);
6523 prefix(dst, src, true);
6524 emit_int8(0x30);
6525 emit_operand(src, dst, 0);
6526 }
6527
6528 void Assembler::xorw(Register dst, Register src) {
6529 (void)prefix_and_encode(dst->encoding(), src->encoding());
6530 emit_arith(0x33, 0xC0, dst, src);
6531 }
6532
6533 // AVX 3-operands scalar float-point arithmetic instructions
6534
6535 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
6536 assert(VM_Version::supports_avx(), "");
6537 InstructionMark im(this);
6538 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6539 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6540 attributes.set_rex_vex_w_reverted();
6541 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6542 emit_int8(0x58);
6543 emit_operand(dst, src, 0);
6544 }
6545
6546 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6547 assert(VM_Version::supports_avx(), "");
6548 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6549 attributes.set_rex_vex_w_reverted();
6550 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6551 emit_int16(0x58, (0xC0 | encode));
6552 }
6553
6554 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
6555 assert(VM_Version::supports_avx(), "");
6556 InstructionMark im(this);
6557 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6558 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6559 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6560 emit_int8(0x58);
6561 emit_operand(dst, src, 0);
6562 }
6563
6564 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6565 assert(VM_Version::supports_avx(), "");
6566 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6567 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6568 emit_int16(0x58, (0xC0 | encode));
6569 }
6570
6571 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
6572 assert(VM_Version::supports_avx(), "");
6573 InstructionMark im(this);
6574 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6575 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6576 attributes.set_rex_vex_w_reverted();
6577 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6578 emit_int8(0x5E);
6579 emit_operand(dst, src, 0);
6580 }
6581
6582 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6583 assert(VM_Version::supports_avx(), "");
6584 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6585 attributes.set_rex_vex_w_reverted();
6586 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6587 emit_int16(0x5E, (0xC0 | encode));
6588 }
6589
6590 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
6591 assert(VM_Version::supports_avx(), "");
6592 InstructionMark im(this);
6593 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6594 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6595 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6596 emit_int8(0x5E);
6597 emit_operand(dst, src, 0);
6598 }
6599
6600 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6601 assert(VM_Version::supports_avx(), "");
6602 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6603 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6604 emit_int16(0x5E, (0xC0 | encode));
6605 }
6606
6607 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6608 assert(VM_Version::supports_fma(), "");
6609 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6610 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6611 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6612 }
6613
6614 void Assembler::evfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2, EvexRoundPrefix rmode) { // Need to add rmode for rounding mode support
6615 assert(VM_Version::supports_evex(), "");
6616 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6617 attributes.set_extended_context();
6618 attributes.set_is_evex_instruction();
6619 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6620 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6621 }
6622
6623 void Assembler::vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6624 assert(VM_Version::supports_fma(), "");
6625 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6626 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6627 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6628 }
6629
6630 void Assembler::vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6631 assert(VM_Version::supports_fma(), "");
6632 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6633 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6634 emit_int16((unsigned char)0xBD, (0xC0 | encode));
6635 }
6636
6637 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6638 assert(VM_Version::supports_fma(), "");
6639 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6640 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6641 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6642 }
6643
6644 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
6645 assert(VM_Version::supports_avx(), "");
6646 InstructionMark im(this);
6647 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6648 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6649 attributes.set_rex_vex_w_reverted();
6650 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6651 emit_int8(0x59);
6652 emit_operand(dst, src, 0);
6653 }
6654
6655 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6656 assert(VM_Version::supports_avx(), "");
6657 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6658 attributes.set_rex_vex_w_reverted();
6659 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6660 emit_int16(0x59, (0xC0 | encode));
6661 }
6662
6663 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
6664 assert(VM_Version::supports_avx(), "");
6665 InstructionMark im(this);
6666 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6667 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6668 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6669 emit_int8(0x59);
6670 emit_operand(dst, src, 0);
6671 }
6672
6673 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6674 assert(VM_Version::supports_avx(), "");
6675 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6676 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6677 emit_int16(0x59, (0xC0 | encode));
6678 }
6679
6680 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
6681 assert(VM_Version::supports_avx(), "");
6682 InstructionMark im(this);
6683 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6684 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6685 attributes.set_rex_vex_w_reverted();
6686 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6687 emit_int8(0x5C);
6688 emit_operand(dst, src, 0);
6689 }
6690
6691 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6692 assert(VM_Version::supports_avx(), "");
6693 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6694 attributes.set_rex_vex_w_reverted();
6695 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6696 emit_int16(0x5C, (0xC0 | encode));
6697 }
6698
6699 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
6700 assert(VM_Version::supports_avx(), "");
6701 InstructionMark im(this);
6702 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6703 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6704 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6705 emit_int8(0x5C);
6706 emit_operand(dst, src, 0);
6707 }
6708
6709 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6710 assert(VM_Version::supports_avx(), "");
6711 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6712 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6713 emit_int16(0x5C, (0xC0 | encode));
6714 }
6715
6716 //====================VECTOR ARITHMETIC=====================================
6717
6718 // Float-point vector arithmetic
6719
6720 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
6721 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6722 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6723 attributes.set_rex_vex_w_reverted();
6724 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6725 emit_int16(0x58, (0xC0 | encode));
6726 }
6727
6728 void Assembler::addpd(XMMRegister dst, Address src) {
6729 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6730 InstructionMark im(this);
6731 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6732 attributes.set_rex_vex_w_reverted();
6733 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6734 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6735 emit_int8(0x58);
6736 emit_operand(dst, src, 0);
6737 }
6738
6739
6740 void Assembler::addps(XMMRegister dst, XMMRegister src) {
6741 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6742 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6743 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6744 emit_int16(0x58, (0xC0 | encode));
6745 }
6746
6747 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6748 assert(VM_Version::supports_avx(), "");
6749 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6750 attributes.set_rex_vex_w_reverted();
6751 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6752 emit_int16(0x58, (0xC0 | encode));
6753 }
6754
6755 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6756 assert(VM_Version::supports_avx(), "");
6757 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6758 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6759 emit_int16(0x58, (0xC0 | encode));
6760 }
6761
6762 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6763 assert(VM_Version::supports_avx(), "");
6764 InstructionMark im(this);
6765 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6766 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6767 attributes.set_rex_vex_w_reverted();
6768 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6769 emit_int8(0x58);
6770 emit_operand(dst, src, 0);
6771 }
6772
6773 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6774 assert(VM_Version::supports_avx(), "");
6775 InstructionMark im(this);
6776 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6777 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6778 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6779 emit_int8(0x58);
6780 emit_operand(dst, src, 0);
6781 }
6782
6783 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
6784 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6785 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6786 attributes.set_rex_vex_w_reverted();
6787 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6788 emit_int16(0x5C, (0xC0 | encode));
6789 }
6790
6791 void Assembler::subps(XMMRegister dst, XMMRegister src) {
6792 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6793 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6794 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6795 emit_int16(0x5C, (0xC0 | encode));
6796 }
6797
6798 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6799 assert(VM_Version::supports_avx(), "");
6800 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6801 attributes.set_rex_vex_w_reverted();
6802 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6803 emit_int16(0x5C, (0xC0 | encode));
6804 }
6805
6806 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6807 assert(VM_Version::supports_avx(), "");
6808 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6809 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6810 emit_int16(0x5C, (0xC0 | encode));
6811 }
6812
6813 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6814 assert(VM_Version::supports_avx(), "");
6815 InstructionMark im(this);
6816 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6817 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6818 attributes.set_rex_vex_w_reverted();
6819 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6820 emit_int8(0x5C);
6821 emit_operand(dst, src, 0);
6822 }
6823
6824 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6825 assert(VM_Version::supports_avx(), "");
6826 InstructionMark im(this);
6827 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6828 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6829 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6830 emit_int8(0x5C);
6831 emit_operand(dst, src, 0);
6832 }
6833
6834 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
6835 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6836 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6837 attributes.set_rex_vex_w_reverted();
6838 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6839 emit_int16(0x59, (0xC0 | encode));
6840 }
6841
6842 void Assembler::mulpd(XMMRegister dst, Address src) {
6843 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6844 InstructionMark im(this);
6845 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6846 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6847 attributes.set_rex_vex_w_reverted();
6848 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6849 emit_int8(0x59);
6850 emit_operand(dst, src, 0);
6851 }
6852
6853 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
6854 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6857 emit_int16(0x59, (0xC0 | encode));
6858 }
6859
6860 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6861 assert(VM_Version::supports_avx(), "");
6862 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6863 attributes.set_rex_vex_w_reverted();
6864 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6865 emit_int16(0x59, (0xC0 | encode));
6866 }
6867
6868 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6869 assert(VM_Version::supports_avx(), "");
6870 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6871 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6872 emit_int16(0x59, (0xC0 | encode));
6873 }
6874
6875 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6876 assert(VM_Version::supports_avx(), "");
6877 InstructionMark im(this);
6878 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6879 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6880 attributes.set_rex_vex_w_reverted();
6881 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6882 emit_int8(0x59);
6883 emit_operand(dst, src, 0);
6884 }
6885
6886 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6887 assert(VM_Version::supports_avx(), "");
6888 InstructionMark im(this);
6889 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6890 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6891 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6892 emit_int8(0x59);
6893 emit_operand(dst, src, 0);
6894 }
6895
6896 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6897 assert(VM_Version::supports_fma(), "");
6898 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6899 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6900 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6901 }
6902
6903 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6904 assert(VM_Version::supports_fma(), "");
6905 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6906 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6907 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6908 }
6909
6910 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6911 assert(VM_Version::supports_fma(), "");
6912 InstructionMark im(this);
6913 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6914 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6915 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6916 emit_int8((unsigned char)0xB8);
6917 emit_operand(dst, src2, 0);
6918 }
6919
6920 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6921 assert(VM_Version::supports_fma(), "");
6922 InstructionMark im(this);
6923 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6924 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6925 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6926 emit_int8((unsigned char)0xB8);
6927 emit_operand(dst, src2, 0);
6928 }
6929
6930 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
6931 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6932 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6933 attributes.set_rex_vex_w_reverted();
6934 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6935 emit_int16(0x5E, (0xC0 | encode));
6936 }
6937
6938 void Assembler::divps(XMMRegister dst, XMMRegister src) {
6939 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6940 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6941 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6942 emit_int16(0x5E, (0xC0 | encode));
6943 }
6944
6945 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6946 assert(VM_Version::supports_avx(), "");
6947 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6948 attributes.set_rex_vex_w_reverted();
6949 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6950 emit_int16(0x5E, (0xC0 | encode));
6951 }
6952
6953 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6954 assert(VM_Version::supports_avx(), "");
6955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6956 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6957 emit_int16(0x5E, (0xC0 | encode));
6958 }
6959
6960 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6961 assert(VM_Version::supports_avx(), "");
6962 InstructionMark im(this);
6963 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6964 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6965 attributes.set_rex_vex_w_reverted();
6966 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6967 emit_int8(0x5E);
6968 emit_operand(dst, src, 0);
6969 }
6970
6971 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6972 assert(VM_Version::supports_avx(), "");
6973 InstructionMark im(this);
6974 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6975 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6976 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6977 emit_int8(0x5E);
6978 emit_operand(dst, src, 0);
6979 }
6980
6981 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
6982 assert(VM_Version::supports_avx(), "");
6983 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6984 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6985 emit_int24(0x09, (0xC0 | encode), (rmode));
6986 }
6987
6988 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
6989 assert(VM_Version::supports_avx(), "");
6990 InstructionMark im(this);
6991 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6992 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6993 emit_int8(0x09);
6994 emit_operand(dst, src, 1);
6995 emit_int8((rmode));
6996 }
6997
6998 void Assembler::vroundsd(XMMRegister dst, XMMRegister src, XMMRegister src2, int32_t rmode) {
6999 assert(VM_Version::supports_avx(), "");
7000 assert(rmode <= 0x0f, "rmode 0x%x", rmode);
7001 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7002 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7003 emit_int24(0x0B, (0xC0 | encode), (rmode));
7004 }
7005
7006 void Assembler::vrndscalesd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int32_t rmode) {
7007 assert(VM_Version::supports_evex(), "requires EVEX support");
7008 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
7009 attributes.set_is_evex_instruction();
7010 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7011 emit_int24(0x0B, (0xC0 | encode), (rmode));
7012 }
7013
7014 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
7015 assert(VM_Version::supports_evex(), "requires EVEX support");
7016 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7017 attributes.set_is_evex_instruction();
7018 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7019 emit_int24(0x09, (0xC0 | encode), (rmode));
7020 }
7021
7022 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
7023 assert(VM_Version::supports_evex(), "requires EVEX support");
7024 assert(dst != xnoreg, "sanity");
7025 InstructionMark im(this);
7026 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7027 attributes.set_is_evex_instruction();
7028 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7029 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7030 emit_int8(0x09);
7031 emit_operand(dst, src, 1);
7032 emit_int8((rmode));
7033 }
7034
7035 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
7036 assert(VM_Version::supports_avx(), "");
7037 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7038 attributes.set_rex_vex_w_reverted();
7039 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7040 emit_int16(0x51, (0xC0 | encode));
7041 }
7042
7043 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
7044 assert(VM_Version::supports_avx(), "");
7045 InstructionMark im(this);
7046 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7047 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7048 attributes.set_rex_vex_w_reverted();
7049 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7050 emit_int8(0x51);
7051 emit_operand(dst, src, 0);
7052 }
7053
7054 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
7055 assert(VM_Version::supports_avx(), "");
7056 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7057 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7058 emit_int16(0x51, (0xC0 | encode));
7059 }
7060
7061 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
7062 assert(VM_Version::supports_avx(), "");
7063 InstructionMark im(this);
7064 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7065 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7066 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7067 emit_int8(0x51);
7068 emit_operand(dst, src, 0);
7069 }
7070
7071 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
7072 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7073 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7074 attributes.set_rex_vex_w_reverted();
7075 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7076 emit_int16(0x54, (0xC0 | encode));
7077 }
7078
7079 void Assembler::andps(XMMRegister dst, XMMRegister src) {
7080 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7081 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7082 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7083 emit_int16(0x54, (0xC0 | encode));
7084 }
7085
7086 void Assembler::andps(XMMRegister dst, Address src) {
7087 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7088 InstructionMark im(this);
7089 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7090 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7091 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7092 emit_int8(0x54);
7093 emit_operand(dst, src, 0);
7094 }
7095
7096 void Assembler::andpd(XMMRegister dst, Address src) {
7097 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7098 InstructionMark im(this);
7099 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7100 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7101 attributes.set_rex_vex_w_reverted();
7102 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7103 emit_int8(0x54);
7104 emit_operand(dst, src, 0);
7105 }
7106
7107 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7108 assert(VM_Version::supports_avx(), "");
7109 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7110 attributes.set_rex_vex_w_reverted();
7111 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7112 emit_int16(0x54, (0xC0 | encode));
7113 }
7114
7115 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7116 assert(VM_Version::supports_avx(), "");
7117 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7118 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7119 emit_int16(0x54, (0xC0 | encode));
7120 }
7121
7122 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7123 assert(VM_Version::supports_avx(), "");
7124 InstructionMark im(this);
7125 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7126 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7127 attributes.set_rex_vex_w_reverted();
7128 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7129 emit_int8(0x54);
7130 emit_operand(dst, src, 0);
7131 }
7132
7133 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7134 assert(VM_Version::supports_avx(), "");
7135 InstructionMark im(this);
7136 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7137 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7138 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7139 emit_int8(0x54);
7140 emit_operand(dst, src, 0);
7141 }
7142
7143 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
7144 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7145 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7146 attributes.set_rex_vex_w_reverted();
7147 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7148 emit_int8(0x15);
7149 emit_int8((0xC0 | encode));
7150 }
7151
7152 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
7153 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7154 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7155 attributes.set_rex_vex_w_reverted();
7156 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7157 emit_int16(0x14, (0xC0 | encode));
7158 }
7159
7160 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
7161 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7162 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7163 attributes.set_rex_vex_w_reverted();
7164 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7165 emit_int16(0x57, (0xC0 | encode));
7166 }
7167
7168 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
7169 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7170 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7171 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7172 emit_int16(0x57, (0xC0 | encode));
7173 }
7174
7175 void Assembler::xorpd(XMMRegister dst, Address src) {
7176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7177 InstructionMark im(this);
7178 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7179 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7180 attributes.set_rex_vex_w_reverted();
7181 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7182 emit_int8(0x57);
7183 emit_operand(dst, src, 0);
7184 }
7185
7186 void Assembler::xorps(XMMRegister dst, Address src) {
7187 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7188 InstructionMark im(this);
7189 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7190 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7191 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7192 emit_int8(0x57);
7193 emit_operand(dst, src, 0);
7194 }
7195
7196 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7197 assert(VM_Version::supports_avx(), "");
7198 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7199 attributes.set_rex_vex_w_reverted();
7200 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7201 emit_int16(0x57, (0xC0 | encode));
7202 }
7203
7204 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7205 assert(VM_Version::supports_avx(), "");
7206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7207 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7208 emit_int16(0x57, (0xC0 | encode));
7209 }
7210
7211 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7212 assert(VM_Version::supports_avx(), "");
7213 InstructionMark im(this);
7214 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7215 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7216 attributes.set_rex_vex_w_reverted();
7217 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7218 emit_int8(0x57);
7219 emit_operand(dst, src, 0);
7220 }
7221
7222 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7223 assert(VM_Version::supports_avx(), "");
7224 InstructionMark im(this);
7225 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7226 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7227 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7228 emit_int8(0x57);
7229 emit_operand(dst, src, 0);
7230 }
7231
7232 // Integer vector arithmetic
7233 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7234 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7235 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7236 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7237 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7238 emit_int16(0x01, (0xC0 | encode));
7239 }
7240
7241 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7242 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7243 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7244 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7245 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7246 emit_int16(0x02, (0xC0 | encode));
7247 }
7248
7249 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
7250 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7253 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7254 }
7255
7256 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
7257 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7260 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7261 }
7262
7263 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
7264 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7265 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7266 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7267 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7268 }
7269
7270 void Assembler::paddd(XMMRegister dst, Address src) {
7271 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7272 InstructionMark im(this);
7273 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7274 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7275 emit_int8((unsigned char)0xFE);
7276 emit_operand(dst, src, 0);
7277 }
7278
7279 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
7280 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7281 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7282 attributes.set_rex_vex_w_reverted();
7283 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7284 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7285 }
7286
7287 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
7288 assert(VM_Version::supports_sse3(), "");
7289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7290 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7291 emit_int16(0x01, (0xC0 | encode));
7292 }
7293
7294 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
7295 assert(VM_Version::supports_sse3(), "");
7296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7298 emit_int16(0x02, (0xC0 | encode));
7299 }
7300
7301 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7302 assert(UseAVX > 0, "requires some form of AVX");
7303 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7304 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7305 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7306 }
7307
7308 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7309 assert(UseAVX > 0, "requires some form of AVX");
7310 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7311 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7312 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7313 }
7314
7315 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7316 assert(UseAVX > 0, "requires some form of AVX");
7317 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7318 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7319 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7320 }
7321
7322 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7323 assert(UseAVX > 0, "requires some form of AVX");
7324 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7325 attributes.set_rex_vex_w_reverted();
7326 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7327 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7328 }
7329
7330 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7331 assert(UseAVX > 0, "requires some form of AVX");
7332 InstructionMark im(this);
7333 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7334 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7335 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7336 emit_int8((unsigned char)0xFC);
7337 emit_operand(dst, src, 0);
7338 }
7339
7340 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7341 assert(UseAVX > 0, "requires some form of AVX");
7342 InstructionMark im(this);
7343 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7344 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7345 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7346 emit_int8((unsigned char)0xFD);
7347 emit_operand(dst, src, 0);
7348 }
7349
7350 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7351 assert(UseAVX > 0, "requires some form of AVX");
7352 InstructionMark im(this);
7353 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7354 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7355 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7356 emit_int8((unsigned char)0xFE);
7357 emit_operand(dst, src, 0);
7358 }
7359
7360 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7361 assert(UseAVX > 0, "requires some form of AVX");
7362 InstructionMark im(this);
7363 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7364 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7365 attributes.set_rex_vex_w_reverted();
7366 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7367 emit_int8((unsigned char)0xD4);
7368 emit_operand(dst, src, 0);
7369 }
7370
7371 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
7372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7373 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7374 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7375 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7376 }
7377
7378 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
7379 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7380 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7381 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7382 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7383 }
7384
7385 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
7386 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7387 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7388 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7389 }
7390
7391 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
7392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7393 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7394 attributes.set_rex_vex_w_reverted();
7395 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7396 emit_int8((unsigned char)0xFB);
7397 emit_int8((0xC0 | encode));
7398 }
7399
7400 void Assembler::vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7401 assert(UseAVX > 0, "requires some form of AVX");
7402 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7403 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7404 emit_int16((unsigned char)0xD8, (0xC0 | encode));
7405 }
7406
7407 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7408 assert(UseAVX > 0, "requires some form of AVX");
7409 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7410 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7411 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7412 }
7413
7414 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7415 assert(UseAVX > 0, "requires some form of AVX");
7416 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7417 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7418 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7419 }
7420
7421 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7422 assert(UseAVX > 0, "requires some form of AVX");
7423 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7424 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7425 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7426 }
7427
7428 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7429 assert(UseAVX > 0, "requires some form of AVX");
7430 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7431 attributes.set_rex_vex_w_reverted();
7432 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7433 emit_int16((unsigned char)0xFB, (0xC0 | encode));
7434 }
7435
7436 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7437 assert(UseAVX > 0, "requires some form of AVX");
7438 InstructionMark im(this);
7439 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7440 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7441 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7442 emit_int8((unsigned char)0xF8);
7443 emit_operand(dst, src, 0);
7444 }
7445
7446 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7447 assert(UseAVX > 0, "requires some form of AVX");
7448 InstructionMark im(this);
7449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7450 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7451 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7452 emit_int8((unsigned char)0xF9);
7453 emit_operand(dst, src, 0);
7454 }
7455
7456 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7457 assert(UseAVX > 0, "requires some form of AVX");
7458 InstructionMark im(this);
7459 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7460 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7461 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7462 emit_int8((unsigned char)0xFA);
7463 emit_operand(dst, src, 0);
7464 }
7465
7466 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7467 assert(UseAVX > 0, "requires some form of AVX");
7468 InstructionMark im(this);
7469 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7470 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7471 attributes.set_rex_vex_w_reverted();
7472 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7473 emit_int8((unsigned char)0xFB);
7474 emit_operand(dst, src, 0);
7475 }
7476
7477 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
7478 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7479 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7480 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7481 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7482 }
7483
7484 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
7485 assert(VM_Version::supports_sse4_1(), "");
7486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7487 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7488 emit_int16(0x40, (0xC0 | encode));
7489 }
7490
7491 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
7492 assert(VM_Version::supports_sse2(), "");
7493 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7494 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7495 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7496 }
7497
7498 void Assembler::vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7499 assert((vector_len == AVX_128bit && VM_Version::supports_avx()) ||
7500 (vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
7501 (vector_len == AVX_512bit && VM_Version::supports_avx512bw()), "");
7502 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7503 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7504 emit_int16((unsigned char)0xE4, (0xC0 | encode));
7505 }
7506
7507 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7508 assert(UseAVX > 0, "requires some form of AVX");
7509 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7510 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7511 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7512 }
7513
7514 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7515 assert(UseAVX > 0, "requires some form of AVX");
7516 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7517 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7518 emit_int16(0x40, (0xC0 | encode));
7519 }
7520
7521 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7522 assert(UseAVX > 2, "requires some form of EVEX");
7523 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7524 attributes.set_is_evex_instruction();
7525 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7526 emit_int16(0x40, (0xC0 | encode));
7527 }
7528
7529 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7530 assert(UseAVX > 0, "requires some form of AVX");
7531 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7532 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7533 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7534 }
7535
7536 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7537 assert(UseAVX > 0, "requires some form of AVX");
7538 InstructionMark im(this);
7539 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7540 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7541 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7542 emit_int8((unsigned char)0xD5);
7543 emit_operand(dst, src, 0);
7544 }
7545
7546 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7547 assert(UseAVX > 0, "requires some form of AVX");
7548 InstructionMark im(this);
7549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7550 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7551 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7552 emit_int8(0x40);
7553 emit_operand(dst, src, 0);
7554 }
7555
7556 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7557 assert(UseAVX > 2, "requires some form of EVEX");
7558 InstructionMark im(this);
7559 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7560 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7561 attributes.set_is_evex_instruction();
7562 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7563 emit_int8(0x40);
7564 emit_operand(dst, src, 0);
7565 }
7566
7567 // Min, max
7568 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
7569 assert(VM_Version::supports_sse4_1(), "");
7570 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7571 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7572 emit_int16(0x38, (0xC0 | encode));
7573 }
7574
7575 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7576 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7577 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7578 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7579 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7580 emit_int16(0x38, (0xC0 | encode));
7581 }
7582
7583 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
7584 assert(VM_Version::supports_sse2(), "");
7585 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7586 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7587 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7588 }
7589
7590 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7591 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7592 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7593 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7594 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7595 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7596 }
7597
7598 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
7599 assert(VM_Version::supports_sse4_1(), "");
7600 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7601 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7602 emit_int16(0x39, (0xC0 | encode));
7603 }
7604
7605 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7606 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7607 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7608 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7609 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7610 emit_int16(0x39, (0xC0 | encode));
7611 }
7612
7613 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7614 assert(UseAVX > 2, "requires AVX512F");
7615 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7616 attributes.set_is_evex_instruction();
7617 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7618 emit_int16(0x39, (0xC0 | encode));
7619 }
7620
7621 void Assembler::minps(XMMRegister dst, XMMRegister src) {
7622 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7623 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7624 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7625 emit_int16(0x5D, (0xC0 | encode));
7626 }
7627 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7628 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7629 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7630 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7631 emit_int16(0x5D, (0xC0 | encode));
7632 }
7633
7634 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
7635 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7636 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7637 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7638 emit_int16(0x5D, (0xC0 | encode));
7639 }
7640 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7641 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7642 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7643 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7644 emit_int16(0x5D, (0xC0 | encode));
7645 }
7646
7647 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
7648 assert(VM_Version::supports_sse4_1(), "");
7649 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7650 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7651 emit_int16(0x3C, (0xC0 | encode));
7652 }
7653
7654 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7655 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7656 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7657 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7658 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7659 emit_int16(0x3C, (0xC0 | encode));
7660 }
7661
7662 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
7663 assert(VM_Version::supports_sse2(), "");
7664 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7665 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7666 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7667 }
7668
7669 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7670 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7671 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7672 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7673 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7674 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7675 }
7676
7677 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
7678 assert(VM_Version::supports_sse4_1(), "");
7679 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7680 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7681 emit_int16(0x3D, (0xC0 | encode));
7682 }
7683
7684 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7685 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7686 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7687 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7688 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7689 emit_int16(0x3D, (0xC0 | encode));
7690 }
7691
7692 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7693 assert(UseAVX > 2, "requires AVX512F");
7694 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7695 attributes.set_is_evex_instruction();
7696 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7697 emit_int16(0x3D, (0xC0 | encode));
7698 }
7699
7700 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
7701 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7702 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7703 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7704 emit_int16(0x5F, (0xC0 | encode));
7705 }
7706
7707 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7708 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7709 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7710 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7711 emit_int16(0x5F, (0xC0 | encode));
7712 }
7713
7714 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
7715 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7716 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7717 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7718 emit_int16(0x5F, (0xC0 | encode));
7719 }
7720
7721 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7722 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7723 InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7724 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7725 emit_int16(0x5F, (0xC0 | encode));
7726 }
7727
7728 // Shift packed integers left by specified number of bits.
7729 void Assembler::psllw(XMMRegister dst, int shift) {
7730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7731 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7732 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7733 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7734 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7735 }
7736
7737 void Assembler::pslld(XMMRegister dst, int shift) {
7738 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7739 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7740 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7741 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7742 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7743 }
7744
7745 void Assembler::psllq(XMMRegister dst, int shift) {
7746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7747 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7748 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7749 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7750 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7751 }
7752
7753 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
7754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7755 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7756 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7757 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7758 }
7759
7760 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
7761 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7763 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7764 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7765 }
7766
7767 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
7768 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7769 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7770 attributes.set_rex_vex_w_reverted();
7771 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7772 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7773 }
7774
7775 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7776 assert(UseAVX > 0, "requires some form of AVX");
7777 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7778 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7779 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7780 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7781 }
7782
7783 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7784 assert(UseAVX > 0, "requires some form of AVX");
7785 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7786 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7787 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7788 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7789 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7790 }
7791
7792 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7793 assert(UseAVX > 0, "requires some form of AVX");
7794 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7795 attributes.set_rex_vex_w_reverted();
7796 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7797 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7798 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7799 }
7800
7801 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7802 assert(UseAVX > 0, "requires some form of AVX");
7803 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7804 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7805 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7806 }
7807
7808 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7809 assert(UseAVX > 0, "requires some form of AVX");
7810 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7811 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7812 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7813 }
7814
7815 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7816 assert(UseAVX > 0, "requires some form of AVX");
7817 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7818 attributes.set_rex_vex_w_reverted();
7819 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7820 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7821 }
7822
7823 // Shift packed integers logically right by specified number of bits.
7824 void Assembler::psrlw(XMMRegister dst, int shift) {
7825 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7826 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7827 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7828 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7829 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7830 }
7831
7832 void Assembler::psrld(XMMRegister dst, int shift) {
7833 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7834 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7835 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7836 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7837 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7838 }
7839
7840 void Assembler::psrlq(XMMRegister dst, int shift) {
7841 // Do not confuse it with psrldq SSE2 instruction which
7842 // shifts 128 bit value in xmm register by number of bytes.
7843 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7844 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7845 attributes.set_rex_vex_w_reverted();
7846 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7847 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7848 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7849 }
7850
7851 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
7852 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7853 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7854 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7855 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7856 }
7857
7858 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
7859 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7860 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7861 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7862 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7863 }
7864
7865 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
7866 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7867 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7868 attributes.set_rex_vex_w_reverted();
7869 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7870 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7871 }
7872
7873 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7874 assert(UseAVX > 0, "requires some form of AVX");
7875 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7876 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7877 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7878 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7879 }
7880
7881 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7882 assert(UseAVX > 0, "requires some form of AVX");
7883 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7884 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7885 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7886 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7887 }
7888
7889 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7890 assert(UseAVX > 0, "requires some form of AVX");
7891 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7892 attributes.set_rex_vex_w_reverted();
7893 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7894 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7895 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7896 }
7897
7898 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7899 assert(UseAVX > 0, "requires some form of AVX");
7900 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7901 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7902 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7903 }
7904
7905 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7906 assert(UseAVX > 0, "requires some form of AVX");
7907 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7908 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7909 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7910 }
7911
7912 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7913 assert(UseAVX > 0, "requires some form of AVX");
7914 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7915 attributes.set_rex_vex_w_reverted();
7916 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7917 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7918 }
7919
7920 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7921 assert(VM_Version::supports_avx512bw(), "");
7922 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7923 attributes.set_is_evex_instruction();
7924 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7925 emit_int16(0x10, (0xC0 | encode));
7926 }
7927
7928 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7929 assert(VM_Version::supports_avx512bw(), "");
7930 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7931 attributes.set_is_evex_instruction();
7932 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7933 emit_int16(0x12, (0xC0 | encode));
7934 }
7935
7936 // Shift packed integers arithmetically right by specified number of bits.
7937 void Assembler::psraw(XMMRegister dst, int shift) {
7938 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7939 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7940 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7941 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7942 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7943 }
7944
7945 void Assembler::psrad(XMMRegister dst, int shift) {
7946 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7948 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
7949 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7950 emit_int8(0x72);
7951 emit_int8((0xC0 | encode));
7952 emit_int8(shift & 0xFF);
7953 }
7954
7955 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
7956 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7957 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7958 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7959 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7960 }
7961
7962 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
7963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7964 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7965 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7966 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7967 }
7968
7969 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7970 assert(UseAVX > 0, "requires some form of AVX");
7971 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7972 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7973 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7974 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7975 }
7976
7977 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7978 assert(UseAVX > 0, "requires some form of AVX");
7979 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7980 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7981 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7982 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7983 }
7984
7985 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7986 assert(UseAVX > 0, "requires some form of AVX");
7987 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7988 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7989 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7990 }
7991
7992 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7993 assert(UseAVX > 0, "requires some form of AVX");
7994 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7995 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7996 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7997 }
7998
7999 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8000 assert(UseAVX > 2, "requires AVX512");
8001 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
8002 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8003 attributes.set_is_evex_instruction();
8004 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8005 emit_int24((unsigned char)0x72, (0xC0 | encode), shift & 0xFF);
8006 }
8007
8008 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8009 assert(UseAVX > 2, "requires AVX512");
8010 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
8011 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8012 attributes.set_is_evex_instruction();
8013 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8014 emit_int16((unsigned char)0xE2, (0xC0 | encode));
8015 }
8016
8017 // logical operations packed integers
8018 void Assembler::pand(XMMRegister dst, XMMRegister src) {
8019 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8020 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8021 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8022 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8023 }
8024
8025 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8026 assert(UseAVX > 0, "requires some form of AVX");
8027 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8028 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8029 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8030 }
8031
8032 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8033 assert(UseAVX > 0, "requires some form of AVX");
8034 InstructionMark im(this);
8035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8036 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8037 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8038 emit_int8((unsigned char)0xDB);
8039 emit_operand(dst, src, 0);
8040 }
8041
8042 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8043 evpandq(dst, k0, nds, src, false, vector_len);
8044 }
8045
8046 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8047 evpandq(dst, k0, nds, src, false, vector_len);
8048 }
8049
8050 //Variable Shift packed integers logically left.
8051 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8052 assert(UseAVX > 1, "requires AVX2");
8053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8054 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8055 emit_int16(0x47, (0xC0 | encode));
8056 }
8057
8058 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8059 assert(UseAVX > 1, "requires AVX2");
8060 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8061 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8062 emit_int16(0x47, (0xC0 | encode));
8063 }
8064
8065 //Variable Shift packed integers logically right.
8066 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8067 assert(UseAVX > 1, "requires AVX2");
8068 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8069 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8070 emit_int16(0x45, (0xC0 | encode));
8071 }
8072
8073 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8074 assert(UseAVX > 1, "requires AVX2");
8075 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8076 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8077 emit_int16(0x45, (0xC0 | encode));
8078 }
8079
8080 //Variable right Shift arithmetic packed integers .
8081 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8082 assert(UseAVX > 1, "requires AVX2");
8083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8084 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8085 emit_int16(0x46, (0xC0 | encode));
8086 }
8087
8088 void Assembler::evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8089 assert(VM_Version::supports_avx512bw(), "");
8090 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8091 attributes.set_is_evex_instruction();
8092 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8093 emit_int16(0x11, (0xC0 | encode));
8094 }
8095
8096 void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8097 assert(UseAVX > 2, "requires AVX512");
8098 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8099 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8100 attributes.set_is_evex_instruction();
8101 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8102 emit_int16(0x46, (0xC0 | encode));
8103 }
8104
8105 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8106 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8108 attributes.set_is_evex_instruction();
8109 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8110 emit_int16(0x71, (0xC0 | encode));
8111 }
8112
8113 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8114 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8115 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8116 attributes.set_is_evex_instruction();
8117 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8118 emit_int16(0x73, (0xC0 | encode));
8119 }
8120
8121 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
8122 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8123 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8124 attributes.set_rex_vex_w_reverted();
8125 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8126 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8127 }
8128
8129 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8130 assert(UseAVX > 0, "requires some form of AVX");
8131 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8132 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8133 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8134 }
8135
8136 void Assembler::por(XMMRegister dst, XMMRegister src) {
8137 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8138 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8139 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8140 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8141 }
8142
8143 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8144 assert(UseAVX > 0, "requires some form of AVX");
8145 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8146 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8147 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8148 }
8149
8150 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8151 assert(UseAVX > 0, "requires some form of AVX");
8152 InstructionMark im(this);
8153 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8154 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8155 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8156 emit_int8((unsigned char)0xEB);
8157 emit_operand(dst, src, 0);
8158 }
8159
8160 void Assembler::evporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8161 evporq(dst, k0, nds, src, false, vector_len);
8162 }
8163
8164 void Assembler::evporq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8165 evporq(dst, k0, nds, src, false, vector_len);
8166 }
8167
8168 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8169 assert(VM_Version::supports_evex(), "");
8170 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8171 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8172 attributes.set_is_evex_instruction();
8173 attributes.set_embedded_opmask_register_specifier(mask);
8174 if (merge) {
8175 attributes.reset_is_clear_context();
8176 }
8177 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8178 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8179 }
8180
8181 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8182 assert(VM_Version::supports_evex(), "");
8183 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8184 InstructionMark im(this);
8185 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8186 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8187 attributes.set_is_evex_instruction();
8188 attributes.set_embedded_opmask_register_specifier(mask);
8189 if (merge) {
8190 attributes.reset_is_clear_context();
8191 }
8192 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8193 emit_int8((unsigned char)0xEB);
8194 emit_operand(dst, src, 0);
8195 }
8196
8197 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
8198 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8200 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8201 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8202 }
8203
8204 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8205 assert(UseAVX > 0, "requires some form of AVX");
8206 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8207 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8208 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8209 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8210 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8211 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8212 }
8213
8214 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8215 assert(UseAVX > 0, "requires some form of AVX");
8216 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8217 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8218 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8219 InstructionMark im(this);
8220 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8221 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8222 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8223 emit_int8((unsigned char)0xEF);
8224 emit_operand(dst, src, 0);
8225 }
8226
8227 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8228 assert(UseAVX > 2, "requires some form of EVEX");
8229 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8230 attributes.set_rex_vex_w_reverted();
8231 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8232 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8233 }
8234
8235 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8236 // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
8237 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8239 attributes.set_is_evex_instruction();
8240 attributes.set_embedded_opmask_register_specifier(mask);
8241 if (merge) {
8242 attributes.reset_is_clear_context();
8243 }
8244 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8245 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8246 }
8247
8248 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8249 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8250 InstructionMark im(this);
8251 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8252 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8253 attributes.set_is_evex_instruction();
8254 attributes.set_embedded_opmask_register_specifier(mask);
8255 if (merge) {
8256 attributes.reset_is_clear_context();
8257 }
8258 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8259 emit_int8((unsigned char)0xEF);
8260 emit_operand(dst, src, 0);
8261 }
8262
8263 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8264 // Encoding: EVEX.NDS.XXX.66.0F.W1 EF /r
8265 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8266 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8267 attributes.set_is_evex_instruction();
8268 attributes.set_embedded_opmask_register_specifier(mask);
8269 if (merge) {
8270 attributes.reset_is_clear_context();
8271 }
8272 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8273 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8274 }
8275
8276 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8277 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8278 InstructionMark im(this);
8279 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8280 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8281 attributes.set_is_evex_instruction();
8282 attributes.set_embedded_opmask_register_specifier(mask);
8283 if (merge) {
8284 attributes.reset_is_clear_context();
8285 }
8286 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8287 emit_int8((unsigned char)0xEF);
8288 emit_operand(dst, src, 0);
8289 }
8290
8291 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8292 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8293 InstructionMark im(this);
8294 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8295 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8296 attributes.set_is_evex_instruction();
8297 attributes.set_embedded_opmask_register_specifier(mask);
8298 if (merge) {
8299 attributes.reset_is_clear_context();
8300 }
8301 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8302 emit_int8((unsigned char)0xDB);
8303 emit_operand(dst, src, 0);
8304 }
8305
8306 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8307 assert(VM_Version::supports_evex(), "requires AVX512F");
8308 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8309 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8310 attributes.set_is_evex_instruction();
8311 attributes.set_embedded_opmask_register_specifier(mask);
8312 if (merge) {
8313 attributes.reset_is_clear_context();
8314 }
8315 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8316 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8317 }
8318
8319 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8320 assert(VM_Version::supports_evex(), "requires AVX512F");
8321 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8322 InstructionMark im(this);
8323 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8324 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8325 attributes.set_is_evex_instruction();
8326 attributes.set_embedded_opmask_register_specifier(mask);
8327 if (merge) {
8328 attributes.reset_is_clear_context();
8329 }
8330 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8331 emit_int8((unsigned char)0xDB);
8332 emit_operand(dst, src, 0);
8333 }
8334
8335 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8336 assert(VM_Version::supports_evex(), "requires AVX512F");
8337 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8338 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8339 attributes.set_is_evex_instruction();
8340 attributes.set_embedded_opmask_register_specifier(mask);
8341 if (merge) {
8342 attributes.reset_is_clear_context();
8343 }
8344 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8345 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8346 }
8347
8348 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8349 assert(VM_Version::supports_evex(), "requires AVX512F");
8350 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8351 InstructionMark im(this);
8352 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8353 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8354 attributes.set_is_evex_instruction();
8355 attributes.set_embedded_opmask_register_specifier(mask);
8356 if (merge) {
8357 attributes.reset_is_clear_context();
8358 }
8359 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8360 emit_int8((unsigned char)0xEB);
8361 emit_operand(dst, src, 0);
8362 }
8363
8364 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8365 assert(VM_Version::supports_evex(), "requires EVEX support");
8366 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8367 attributes.set_is_evex_instruction();
8368 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8369 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8370 }
8371
8372 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8373 assert(VM_Version::supports_evex(), "requires EVEX support");
8374 assert(dst != xnoreg, "sanity");
8375 InstructionMark im(this);
8376 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8377 attributes.set_is_evex_instruction();
8378 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8379 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8380 emit_int8((unsigned char)0xEF);
8381 emit_operand(dst, src, 0);
8382 }
8383
8384 void Assembler::evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8385 assert(VM_Version::supports_evex(), "requires EVEX support");
8386 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8387 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8388 attributes.set_is_evex_instruction();
8389 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8390 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8391 }
8392
8393 void Assembler::evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8394 assert(VM_Version::supports_evex(), "requires EVEX support");
8395 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8396 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8397 attributes.set_is_evex_instruction();
8398 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8399 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8400 }
8401
8402 void Assembler::evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8403 assert(VM_Version::supports_evex(), "requires EVEX support");
8404 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8405 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8406 attributes.set_is_evex_instruction();
8407 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8408 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8409 }
8410
8411 void Assembler::evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8412 assert(VM_Version::supports_evex(), "requires EVEX support");
8413 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8414 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8415 attributes.set_is_evex_instruction();
8416 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8417 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8418 }
8419
8420 void Assembler::evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8421 assert(VM_Version::supports_evex(), "requires EVEX support");
8422 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8423 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8424 attributes.set_is_evex_instruction();
8425 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8426 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8427 }
8428
8429 void Assembler::evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8430 assert(VM_Version::supports_evex(), "requires EVEX support");
8431 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8432 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8433 attributes.set_is_evex_instruction();
8434 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8435 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8436 }
8437
8438 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8439 assert(VM_Version::supports_evex(), "requires EVEX support");
8440 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8441 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8442 attributes.set_is_evex_instruction();
8443 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8444 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8445 }
8446
8447 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8448 assert(VM_Version::supports_evex(), "requires EVEX support");
8449 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8450 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8451 attributes.set_is_evex_instruction();
8452 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8453 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8454 }
8455
8456 void Assembler::evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8457 assert(VM_Version::supports_avx512cd(), "");
8458 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8459 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8460 attributes.set_is_evex_instruction();
8461 attributes.set_embedded_opmask_register_specifier(mask);
8462 if (merge) {
8463 attributes.reset_is_clear_context();
8464 }
8465 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8466 emit_int16(0x44, (0xC0 | encode));
8467 }
8468
8469 void Assembler::evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8470 assert(VM_Version::supports_avx512cd(), "");
8471 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8472 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8473 attributes.set_is_evex_instruction();
8474 attributes.set_embedded_opmask_register_specifier(mask);
8475 if (merge) {
8476 attributes.reset_is_clear_context();
8477 }
8478 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8479 emit_int16(0x44, (0xC0 | encode));
8480 }
8481
8482 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8483 assert(VM_Version::supports_evex(), "requires EVEX support");
8484 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8485 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8486 attributes.set_is_evex_instruction();
8487 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8488 emit_int8(0x25);
8489 emit_int8((unsigned char)(0xC0 | encode));
8490 emit_int8(imm8);
8491 }
8492
8493 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8494 assert(VM_Version::supports_evex(), "requires EVEX support");
8495 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8496 assert(dst != xnoreg, "sanity");
8497 InstructionMark im(this);
8498 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8499 attributes.set_is_evex_instruction();
8500 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8501 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8502 emit_int8(0x25);
8503 emit_operand(dst, src3, 1);
8504 emit_int8(imm8);
8505 }
8506
8507 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8508 assert(VM_Version::supports_evex(), "requires AVX512F");
8509 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8510 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8511 attributes.set_is_evex_instruction();
8512 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8513 emit_int8(0x25);
8514 emit_int8((unsigned char)(0xC0 | encode));
8515 emit_int8(imm8);
8516 }
8517
8518 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8519 assert(VM_Version::supports_evex(), "requires EVEX support");
8520 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8521 assert(dst != xnoreg, "sanity");
8522 InstructionMark im(this);
8523 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8524 attributes.set_is_evex_instruction();
8525 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8526 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8527 emit_int8(0x25);
8528 emit_operand(dst, src3, 1);
8529 emit_int8(imm8);
8530 }
8531
8532 void Assembler::evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8533 assert(VM_Version::supports_evex(), "");
8534 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8535 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8536 attributes.set_is_evex_instruction();
8537 attributes.set_embedded_opmask_register_specifier(mask);
8538 if (merge) {
8539 attributes.reset_is_clear_context();
8540 }
8541 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8542 emit_int16((unsigned char)0x88, (0xC0 | encode));
8543 }
8544
8545 void Assembler::evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8546 assert(VM_Version::supports_evex(), "");
8547 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8548 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8549 attributes.set_is_evex_instruction();
8550 attributes.set_embedded_opmask_register_specifier(mask);
8551 if (merge) {
8552 attributes.reset_is_clear_context();
8553 }
8554 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8555 emit_int16((unsigned char)0x88, (0xC0 | encode));
8556 }
8557
8558 void Assembler::evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8559 assert(VM_Version::supports_avx512_vbmi2(), "");
8560 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8561 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8562 attributes.set_is_evex_instruction();
8563 attributes.set_embedded_opmask_register_specifier(mask);
8564 if (merge) {
8565 attributes.reset_is_clear_context();
8566 }
8567 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8568 emit_int16(0x62, (0xC0 | encode));
8569 }
8570
8571 void Assembler::evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8572 assert(VM_Version::supports_avx512_vbmi2(), "");
8573 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8574 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8575 attributes.set_is_evex_instruction();
8576 attributes.set_embedded_opmask_register_specifier(mask);
8577 if (merge) {
8578 attributes.reset_is_clear_context();
8579 }
8580 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8581 emit_int16(0x62, (0xC0 | encode));
8582 }
8583
8584 void Assembler::evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8585 assert(VM_Version::supports_evex(), "");
8586 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8587 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8588 attributes.set_is_evex_instruction();
8589 attributes.set_embedded_opmask_register_specifier(mask);
8590 if (merge) {
8591 attributes.reset_is_clear_context();
8592 }
8593 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8594 emit_int16((unsigned char)0x89, (0xC0 | encode));
8595 }
8596
8597 void Assembler::evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8598 assert(VM_Version::supports_evex(), "");
8599 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8600 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8601 attributes.set_is_evex_instruction();
8602 attributes.set_embedded_opmask_register_specifier(mask);
8603 if (merge) {
8604 attributes.reset_is_clear_context();
8605 }
8606 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8607 emit_int16((unsigned char)0x89, (0xC0 | encode));
8608 }
8609
8610 // vinserti forms
8611
8612 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8613 assert(VM_Version::supports_avx2(), "");
8614 assert(imm8 <= 0x01, "imm8: %u", imm8);
8615 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8616 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8617 // last byte:
8618 // 0x00 - insert into lower 128 bits
8619 // 0x01 - insert into upper 128 bits
8620 emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
8621 }
8622
8623 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8624 assert(VM_Version::supports_avx2(), "");
8625 assert(dst != xnoreg, "sanity");
8626 assert(imm8 <= 0x01, "imm8: %u", imm8);
8627 InstructionMark im(this);
8628 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8629 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8630 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8631 emit_int8(0x38);
8632 emit_operand(dst, src, 1);
8633 // 0x00 - insert into lower 128 bits
8634 // 0x01 - insert into upper 128 bits
8635 emit_int8(imm8 & 0x01);
8636 }
8637
8638 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8639 assert(VM_Version::supports_evex(), "");
8640 assert(imm8 <= 0x03, "imm8: %u", imm8);
8641 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8642 attributes.set_is_evex_instruction();
8643 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8644 // imm8:
8645 // 0x00 - insert into q0 128 bits (0..127)
8646 // 0x01 - insert into q1 128 bits (128..255)
8647 // 0x02 - insert into q2 128 bits (256..383)
8648 // 0x03 - insert into q3 128 bits (384..511)
8649 emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
8650 }
8651
8652 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8653 assert(VM_Version::supports_evex(), "");
8654 assert(dst != xnoreg, "sanity");
8655 assert(imm8 <= 0x03, "imm8: %u", imm8);
8656 InstructionMark im(this);
8657 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8658 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8659 attributes.set_is_evex_instruction();
8660 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8661 emit_int8(0x18);
8662 emit_operand(dst, src, 1);
8663 // 0x00 - insert into q0 128 bits (0..127)
8664 // 0x01 - insert into q1 128 bits (128..255)
8665 // 0x02 - insert into q2 128 bits (256..383)
8666 // 0x03 - insert into q3 128 bits (384..511)
8667 emit_int8(imm8 & 0x03);
8668 }
8669
8670 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8671 assert(VM_Version::supports_evex(), "");
8672 assert(imm8 <= 0x01, "imm8: %u", imm8);
8673 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8674 attributes.set_is_evex_instruction();
8675 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8676 //imm8:
8677 // 0x00 - insert into lower 256 bits
8678 // 0x01 - insert into upper 256 bits
8679 emit_int24(0x3A, (0xC0 | encode), imm8 & 0x01);
8680 }
8681
8682
8683 // vinsertf forms
8684
8685 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8686 assert(VM_Version::supports_avx(), "");
8687 assert(imm8 <= 0x01, "imm8: %u", imm8);
8688 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8689 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8690 // imm8:
8691 // 0x00 - insert into lower 128 bits
8692 // 0x01 - insert into upper 128 bits
8693 emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
8694 }
8695
8696 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8697 assert(VM_Version::supports_avx(), "");
8698 assert(dst != xnoreg, "sanity");
8699 assert(imm8 <= 0x01, "imm8: %u", imm8);
8700 InstructionMark im(this);
8701 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8702 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8703 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8704 emit_int8(0x18);
8705 emit_operand(dst, src, 1);
8706 // 0x00 - insert into lower 128 bits
8707 // 0x01 - insert into upper 128 bits
8708 emit_int8(imm8 & 0x01);
8709 }
8710
8711 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8712 assert(VM_Version::supports_evex(), "");
8713 assert(imm8 <= 0x03, "imm8: %u", imm8);
8714 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8715 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8716 // imm8:
8717 // 0x00 - insert into q0 128 bits (0..127)
8718 // 0x01 - insert into q1 128 bits (128..255)
8719 // 0x02 - insert into q0 128 bits (256..383)
8720 // 0x03 - insert into q1 128 bits (384..512)
8721 emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
8722 }
8723
8724 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8725 assert(VM_Version::supports_evex(), "");
8726 assert(dst != xnoreg, "sanity");
8727 assert(imm8 <= 0x03, "imm8: %u", imm8);
8728 InstructionMark im(this);
8729 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8730 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8731 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8732 emit_int8(0x18);
8733 emit_operand(dst, src, 1);
8734 // 0x00 - insert into q0 128 bits (0..127)
8735 // 0x01 - insert into q1 128 bits (128..255)
8736 // 0x02 - insert into q0 128 bits (256..383)
8737 // 0x03 - insert into q1 128 bits (384..512)
8738 emit_int8(imm8 & 0x03);
8739 }
8740
8741 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8742 assert(VM_Version::supports_evex(), "");
8743 assert(imm8 <= 0x01, "imm8: %u", imm8);
8744 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8745 attributes.set_is_evex_instruction();
8746 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8747 // imm8:
8748 // 0x00 - insert into lower 256 bits
8749 // 0x01 - insert into upper 256 bits
8750 emit_int24(0x1A, (0xC0 | encode), imm8 & 0x01);
8751 }
8752
8753 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8754 assert(VM_Version::supports_evex(), "");
8755 assert(dst != xnoreg, "sanity");
8756 assert(imm8 <= 0x01, "imm8: %u", imm8);
8757 InstructionMark im(this);
8758 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8759 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8760 attributes.set_is_evex_instruction();
8761 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8762 emit_int8(0x1A);
8763 emit_operand(dst, src, 1);
8764 // 0x00 - insert into lower 256 bits
8765 // 0x01 - insert into upper 256 bits
8766 emit_int8(imm8 & 0x01);
8767 }
8768
8769
8770 // vextracti forms
8771
8772 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8773 assert(VM_Version::supports_avx2(), "");
8774 assert(imm8 <= 0x01, "imm8: %u", imm8);
8775 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8776 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8777 // imm8:
8778 // 0x00 - extract from lower 128 bits
8779 // 0x01 - extract from upper 128 bits
8780 emit_int24(0x39, (0xC0 | encode), imm8 & 0x01);
8781 }
8782
8783 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
8784 assert(VM_Version::supports_avx2(), "");
8785 assert(src != xnoreg, "sanity");
8786 assert(imm8 <= 0x01, "imm8: %u", imm8);
8787 InstructionMark im(this);
8788 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8789 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8790 attributes.reset_is_clear_context();
8791 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8792 emit_int8(0x39);
8793 emit_operand(src, dst, 1);
8794 // 0x00 - extract from lower 128 bits
8795 // 0x01 - extract from upper 128 bits
8796 emit_int8(imm8 & 0x01);
8797 }
8798
8799 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8800 assert(VM_Version::supports_evex(), "");
8801 assert(imm8 <= 0x03, "imm8: %u", imm8);
8802 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8803 attributes.set_is_evex_instruction();
8804 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8805 // imm8:
8806 // 0x00 - extract from bits 127:0
8807 // 0x01 - extract from bits 255:128
8808 // 0x02 - extract from bits 383:256
8809 // 0x03 - extract from bits 511:384
8810 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8811 }
8812
8813 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
8814 assert(VM_Version::supports_evex(), "");
8815 assert(src != xnoreg, "sanity");
8816 assert(imm8 <= 0x03, "imm8: %u", imm8);
8817 InstructionMark im(this);
8818 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8819 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8820 attributes.reset_is_clear_context();
8821 attributes.set_is_evex_instruction();
8822 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8823 emit_int8(0x39);
8824 emit_operand(src, dst, 1);
8825 // 0x00 - extract from bits 127:0
8826 // 0x01 - extract from bits 255:128
8827 // 0x02 - extract from bits 383:256
8828 // 0x03 - extract from bits 511:384
8829 emit_int8(imm8 & 0x03);
8830 }
8831
8832 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8833 assert(VM_Version::supports_avx512dq(), "");
8834 assert(imm8 <= 0x03, "imm8: %u", imm8);
8835 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8836 attributes.set_is_evex_instruction();
8837 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8838 // imm8:
8839 // 0x00 - extract from bits 127:0
8840 // 0x01 - extract from bits 255:128
8841 // 0x02 - extract from bits 383:256
8842 // 0x03 - extract from bits 511:384
8843 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8844 }
8845
8846 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8847 assert(VM_Version::supports_evex(), "");
8848 assert(imm8 <= 0x01, "imm8: %u", imm8);
8849 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8850 attributes.set_is_evex_instruction();
8851 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8852 // imm8:
8853 // 0x00 - extract from lower 256 bits
8854 // 0x01 - extract from upper 256 bits
8855 emit_int24(0x3B, (0xC0 | encode), imm8 & 0x01);
8856 }
8857
8858 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
8859 assert(VM_Version::supports_evex(), "");
8860 assert(src != xnoreg, "sanity");
8861 assert(imm8 <= 0x01, "imm8: %u", imm8);
8862 InstructionMark im(this);
8863 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8864 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8865 attributes.reset_is_clear_context();
8866 attributes.set_is_evex_instruction();
8867 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8868 emit_int8(0x38);
8869 emit_operand(src, dst, 1);
8870 // 0x00 - extract from lower 256 bits
8871 // 0x01 - extract from upper 256 bits
8872 emit_int8(imm8 & 0x01);
8873 }
8874 // vextractf forms
8875
8876 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8877 assert(VM_Version::supports_avx(), "");
8878 assert(imm8 <= 0x01, "imm8: %u", imm8);
8879 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8880 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8881 // imm8:
8882 // 0x00 - extract from lower 128 bits
8883 // 0x01 - extract from upper 128 bits
8884 emit_int24(0x19, (0xC0 | encode), imm8 & 0x01);
8885 }
8886
8887 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
8888 assert(VM_Version::supports_avx(), "");
8889 assert(src != xnoreg, "sanity");
8890 assert(imm8 <= 0x01, "imm8: %u", imm8);
8891 InstructionMark im(this);
8892 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8893 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8894 attributes.reset_is_clear_context();
8895 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8896 emit_int8(0x19);
8897 emit_operand(src, dst, 1);
8898 // 0x00 - extract from lower 128 bits
8899 // 0x01 - extract from upper 128 bits
8900 emit_int8(imm8 & 0x01);
8901 }
8902
8903 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8904 assert(VM_Version::supports_evex(), "");
8905 assert(imm8 <= 0x03, "imm8: %u", imm8);
8906 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8907 attributes.set_is_evex_instruction();
8908 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8909 // imm8:
8910 // 0x00 - extract from bits 127:0
8911 // 0x01 - extract from bits 255:128
8912 // 0x02 - extract from bits 383:256
8913 // 0x03 - extract from bits 511:384
8914 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8915 }
8916
8917 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
8918 assert(VM_Version::supports_evex(), "");
8919 assert(src != xnoreg, "sanity");
8920 assert(imm8 <= 0x03, "imm8: %u", imm8);
8921 InstructionMark im(this);
8922 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8923 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8924 attributes.reset_is_clear_context();
8925 attributes.set_is_evex_instruction();
8926 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8927 emit_int8(0x19);
8928 emit_operand(src, dst, 1);
8929 // 0x00 - extract from bits 127:0
8930 // 0x01 - extract from bits 255:128
8931 // 0x02 - extract from bits 383:256
8932 // 0x03 - extract from bits 511:384
8933 emit_int8(imm8 & 0x03);
8934 }
8935
8936 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8937 assert(VM_Version::supports_avx512dq(), "");
8938 assert(imm8 <= 0x03, "imm8: %u", imm8);
8939 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8940 attributes.set_is_evex_instruction();
8941 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8942 // imm8:
8943 // 0x00 - extract from bits 127:0
8944 // 0x01 - extract from bits 255:128
8945 // 0x02 - extract from bits 383:256
8946 // 0x03 - extract from bits 511:384
8947 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8948 }
8949
8950 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8951 assert(VM_Version::supports_evex(), "");
8952 assert(imm8 <= 0x01, "imm8: %u", imm8);
8953 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8954 attributes.set_is_evex_instruction();
8955 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8956 // imm8:
8957 // 0x00 - extract from lower 256 bits
8958 // 0x01 - extract from upper 256 bits
8959 emit_int24(0x1B, (0xC0 | encode), imm8 & 0x01);
8960 }
8961
8962 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
8963 assert(VM_Version::supports_evex(), "");
8964 assert(src != xnoreg, "sanity");
8965 assert(imm8 <= 0x01, "imm8: %u", imm8);
8966 InstructionMark im(this);
8967 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8968 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
8969 attributes.reset_is_clear_context();
8970 attributes.set_is_evex_instruction();
8971 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8972 emit_int8(0x1B);
8973 emit_operand(src, dst, 1);
8974 // 0x00 - extract from lower 256 bits
8975 // 0x01 - extract from upper 256 bits
8976 emit_int8(imm8 & 0x01);
8977 }
8978
8979 void Assembler::extractps(Register dst, XMMRegister src, uint8_t imm8) {
8980 assert(VM_Version::supports_sse4_1(), "");
8981 assert(imm8 <= 0x03, "imm8: %u", imm8);
8982 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8983 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8984 // imm8:
8985 // 0x00 - extract from bits 31:0
8986 // 0x01 - extract from bits 63:32
8987 // 0x02 - extract from bits 95:64
8988 // 0x03 - extract from bits 127:96
8989 emit_int24(0x17, (0xC0 | encode), imm8 & 0x03);
8990 }
8991
8992 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
8993 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
8994 assert(VM_Version::supports_avx2(), "");
8995 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8996 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8997 emit_int16(0x78, (0xC0 | encode));
8998 }
8999
9000 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
9001 assert(VM_Version::supports_avx2(), "");
9002 assert(dst != xnoreg, "sanity");
9003 InstructionMark im(this);
9004 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9005 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
9006 // swap src<->dst for encoding
9007 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9008 emit_int8(0x78);
9009 emit_operand(dst, src, 0);
9010 }
9011
9012 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
9013 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
9014 assert(VM_Version::supports_avx2(), "");
9015 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9016 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9017 emit_int16(0x79, (0xC0 | encode));
9018 }
9019
9020 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
9021 assert(VM_Version::supports_avx2(), "");
9022 assert(dst != xnoreg, "sanity");
9023 InstructionMark im(this);
9024 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9025 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
9026 // swap src<->dst for encoding
9027 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9028 emit_int8(0x79);
9029 emit_operand(dst, src, 0);
9030 }
9031
9032 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9033 assert(UseAVX > 0, "requires some form of AVX");
9034 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
9035 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9036 emit_int16((unsigned char)0xF6, (0xC0 | encode));
9037 }
9038
9039 void Assembler::vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9040 assert(UseAVX > 0, "requires some form of AVX");
9041 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9042 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9043 emit_int16(0x69, (0xC0 | encode));
9044 }
9045
9046 void Assembler::vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9047 assert(UseAVX > 0, "requires some form of AVX");
9048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9049 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9050 emit_int16(0x61, (0xC0 | encode));
9051 }
9052
9053 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9054 assert(UseAVX > 0, "requires some form of AVX");
9055 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9056 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9057 emit_int16(0x6A, (0xC0 | encode));
9058 }
9059
9060 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9061 assert(UseAVX > 0, "requires some form of AVX");
9062 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9063 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9064 emit_int16(0x62, (0xC0 | encode));
9065 }
9066
9067 // xmm/mem sourced byte/word/dword/qword replicate
9068 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9069 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9070 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9071 attributes.set_is_evex_instruction();
9072 attributes.set_embedded_opmask_register_specifier(mask);
9073 if (merge) {
9074 attributes.reset_is_clear_context();
9075 }
9076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9077 emit_int16((unsigned char)0xFC, (0xC0 | encode));
9078 }
9079
9080 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9081 InstructionMark im(this);
9082 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9083 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9084 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9085 attributes.set_is_evex_instruction();
9086 attributes.set_embedded_opmask_register_specifier(mask);
9087 if (merge) {
9088 attributes.reset_is_clear_context();
9089 }
9090 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9091 emit_int8((unsigned char)0xFC);
9092 emit_operand(dst, src, 0);
9093 }
9094
9095 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9096 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9097 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9098 attributes.set_is_evex_instruction();
9099 attributes.set_embedded_opmask_register_specifier(mask);
9100 if (merge) {
9101 attributes.reset_is_clear_context();
9102 }
9103 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9104 emit_int16((unsigned char)0xFD, (0xC0 | encode));
9105 }
9106
9107 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9108 InstructionMark im(this);
9109 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9110 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9111 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9112 attributes.set_is_evex_instruction();
9113 attributes.set_embedded_opmask_register_specifier(mask);
9114 if (merge) {
9115 attributes.reset_is_clear_context();
9116 }
9117 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9118 emit_int8((unsigned char)0xFD);
9119 emit_operand(dst, src, 0);
9120 }
9121
9122 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9123 assert(VM_Version::supports_evex(), "");
9124 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9125 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9126 attributes.set_is_evex_instruction();
9127 attributes.set_embedded_opmask_register_specifier(mask);
9128 if (merge) {
9129 attributes.reset_is_clear_context();
9130 }
9131 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9132 emit_int16((unsigned char)0xFE, (0xC0 | encode));
9133 }
9134
9135 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9136 InstructionMark im(this);
9137 assert(VM_Version::supports_evex(), "");
9138 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9139 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9140 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9141 attributes.set_is_evex_instruction();
9142 attributes.set_embedded_opmask_register_specifier(mask);
9143 if (merge) {
9144 attributes.reset_is_clear_context();
9145 }
9146 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9147 emit_int8((unsigned char)0xFE);
9148 emit_operand(dst, src, 0);
9149 }
9150
9151 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9152 assert(VM_Version::supports_evex(), "");
9153 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9154 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9155 attributes.set_is_evex_instruction();
9156 attributes.set_embedded_opmask_register_specifier(mask);
9157 if (merge) {
9158 attributes.reset_is_clear_context();
9159 }
9160 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9161 emit_int16((unsigned char)0xD4, (0xC0 | encode));
9162 }
9163
9164 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9165 InstructionMark im(this);
9166 assert(VM_Version::supports_evex(), "");
9167 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9168 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9169 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9170 attributes.set_is_evex_instruction();
9171 attributes.set_embedded_opmask_register_specifier(mask);
9172 if (merge) {
9173 attributes.reset_is_clear_context();
9174 }
9175 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9176 emit_int8((unsigned char)0xD4);
9177 emit_operand(dst, src, 0);
9178 }
9179
9180 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9181 assert(VM_Version::supports_evex(), "");
9182 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9184 attributes.set_is_evex_instruction();
9185 attributes.set_embedded_opmask_register_specifier(mask);
9186 if (merge) {
9187 attributes.reset_is_clear_context();
9188 }
9189 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9190 emit_int16(0x58, (0xC0 | encode));
9191 }
9192
9193 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9194 InstructionMark im(this);
9195 assert(VM_Version::supports_evex(), "");
9196 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9197 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9198 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9199 attributes.set_is_evex_instruction();
9200 attributes.set_embedded_opmask_register_specifier(mask);
9201 if (merge) {
9202 attributes.reset_is_clear_context();
9203 }
9204 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9205 emit_int8(0x58);
9206 emit_operand(dst, src, 0);
9207 }
9208
9209 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9210 assert(VM_Version::supports_evex(), "");
9211 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9212 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9213 attributes.set_is_evex_instruction();
9214 attributes.set_embedded_opmask_register_specifier(mask);
9215 if (merge) {
9216 attributes.reset_is_clear_context();
9217 }
9218 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9219 emit_int16(0x58, (0xC0 | encode));
9220 }
9221
9222 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9223 InstructionMark im(this);
9224 assert(VM_Version::supports_evex(), "");
9225 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9226 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9227 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9228 attributes.set_is_evex_instruction();
9229 attributes.set_embedded_opmask_register_specifier(mask);
9230 if (merge) {
9231 attributes.reset_is_clear_context();
9232 }
9233 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9234 emit_int8(0x58);
9235 emit_operand(dst, src, 0);
9236 }
9237
9238 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9239 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9240 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9241 attributes.set_is_evex_instruction();
9242 attributes.set_embedded_opmask_register_specifier(mask);
9243 if (merge) {
9244 attributes.reset_is_clear_context();
9245 }
9246 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9247 emit_int16((unsigned char)0xF8, (0xC0 | encode));
9248 }
9249
9250 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9251 InstructionMark im(this);
9252 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9253 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9254 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9255 attributes.set_is_evex_instruction();
9256 attributes.set_embedded_opmask_register_specifier(mask);
9257 if (merge) {
9258 attributes.reset_is_clear_context();
9259 }
9260 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9261 emit_int8((unsigned char)0xF8);
9262 emit_operand(dst, src, 0);
9263 }
9264
9265 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9266 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9267 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9268 attributes.set_is_evex_instruction();
9269 attributes.set_embedded_opmask_register_specifier(mask);
9270 if (merge) {
9271 attributes.reset_is_clear_context();
9272 }
9273 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9274 emit_int16((unsigned char)0xF9, (0xC0 | encode));
9275 }
9276
9277 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9278 InstructionMark im(this);
9279 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9280 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9281 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9282 attributes.set_is_evex_instruction();
9283 attributes.set_embedded_opmask_register_specifier(mask);
9284 if (merge) {
9285 attributes.reset_is_clear_context();
9286 }
9287 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9288 emit_int8((unsigned char)0xF9);
9289 emit_operand(dst, src, 0);
9290 }
9291
9292 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9293 assert(VM_Version::supports_evex(), "");
9294 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9295 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9296 attributes.set_is_evex_instruction();
9297 attributes.set_embedded_opmask_register_specifier(mask);
9298 if (merge) {
9299 attributes.reset_is_clear_context();
9300 }
9301 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9302 emit_int16((unsigned char)0xFA, (0xC0 | encode));
9303 }
9304
9305 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9306 InstructionMark im(this);
9307 assert(VM_Version::supports_evex(), "");
9308 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9309 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9310 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9311 attributes.set_is_evex_instruction();
9312 attributes.set_embedded_opmask_register_specifier(mask);
9313 if (merge) {
9314 attributes.reset_is_clear_context();
9315 }
9316 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9317 emit_int8((unsigned char)0xFA);
9318 emit_operand(dst, src, 0);
9319 }
9320
9321 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9322 assert(VM_Version::supports_evex(), "");
9323 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9324 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9325 attributes.set_is_evex_instruction();
9326 attributes.set_embedded_opmask_register_specifier(mask);
9327 if (merge) {
9328 attributes.reset_is_clear_context();
9329 }
9330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9331 emit_int16((unsigned char)0xFB, (0xC0 | encode));
9332 }
9333
9334 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9335 InstructionMark im(this);
9336 assert(VM_Version::supports_evex(), "");
9337 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9338 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9339 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9340 attributes.set_is_evex_instruction();
9341 attributes.set_embedded_opmask_register_specifier(mask);
9342 if (merge) {
9343 attributes.reset_is_clear_context();
9344 }
9345 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9346 emit_int8((unsigned char)0xFB);
9347 emit_operand(dst, src, 0);
9348 }
9349
9350 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9351 assert(VM_Version::supports_evex(), "");
9352 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9353 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9354 attributes.set_is_evex_instruction();
9355 attributes.set_embedded_opmask_register_specifier(mask);
9356 if (merge) {
9357 attributes.reset_is_clear_context();
9358 }
9359 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9360 emit_int16(0x5C, (0xC0 | encode));
9361 }
9362
9363 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9364 InstructionMark im(this);
9365 assert(VM_Version::supports_evex(), "");
9366 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9367 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9368 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9369 attributes.set_is_evex_instruction();
9370 attributes.set_embedded_opmask_register_specifier(mask);
9371 if (merge) {
9372 attributes.reset_is_clear_context();
9373 }
9374 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9375 emit_int8(0x5C);
9376 emit_operand(dst, src, 0);
9377 }
9378
9379 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9380 assert(VM_Version::supports_evex(), "");
9381 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9382 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9383 attributes.set_is_evex_instruction();
9384 attributes.set_embedded_opmask_register_specifier(mask);
9385 if (merge) {
9386 attributes.reset_is_clear_context();
9387 }
9388 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9389 emit_int16(0x5C, (0xC0 | encode));
9390 }
9391
9392 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9393 InstructionMark im(this);
9394 assert(VM_Version::supports_evex(), "");
9395 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9396 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9397 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9398 attributes.set_is_evex_instruction();
9399 attributes.set_embedded_opmask_register_specifier(mask);
9400 if (merge) {
9401 attributes.reset_is_clear_context();
9402 }
9403 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9404 emit_int8(0x5C);
9405 emit_operand(dst, src, 0);
9406 }
9407
9408 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9409 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9410 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9411 attributes.set_is_evex_instruction();
9412 attributes.set_embedded_opmask_register_specifier(mask);
9413 if (merge) {
9414 attributes.reset_is_clear_context();
9415 }
9416 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9417 emit_int16((unsigned char)0xD5, (0xC0 | encode));
9418 }
9419
9420 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9421 InstructionMark im(this);
9422 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9423 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9424 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9425 attributes.set_is_evex_instruction();
9426 attributes.set_embedded_opmask_register_specifier(mask);
9427 if (merge) {
9428 attributes.reset_is_clear_context();
9429 }
9430 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9431 emit_int8((unsigned char)0xD5);
9432 emit_operand(dst, src, 0);
9433 }
9434
9435 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9436 assert(VM_Version::supports_evex(), "");
9437 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9438 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9439 attributes.set_is_evex_instruction();
9440 attributes.set_embedded_opmask_register_specifier(mask);
9441 if (merge) {
9442 attributes.reset_is_clear_context();
9443 }
9444 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9445 emit_int16(0x40, (0xC0 | encode));
9446 }
9447
9448 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9449 InstructionMark im(this);
9450 assert(VM_Version::supports_evex(), "");
9451 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9452 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9453 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9454 attributes.set_is_evex_instruction();
9455 attributes.set_embedded_opmask_register_specifier(mask);
9456 if (merge) {
9457 attributes.reset_is_clear_context();
9458 }
9459 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9460 emit_int8(0x40);
9461 emit_operand(dst, src, 0);
9462 }
9463
9464 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9465 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9466 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9467 attributes.set_is_evex_instruction();
9468 attributes.set_embedded_opmask_register_specifier(mask);
9469 if (merge) {
9470 attributes.reset_is_clear_context();
9471 }
9472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9473 emit_int16(0x40, (0xC0 | encode));
9474 }
9475
9476 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9477 InstructionMark im(this);
9478 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9479 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9480 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9481 attributes.set_is_evex_instruction();
9482 attributes.set_embedded_opmask_register_specifier(mask);
9483 if (merge) {
9484 attributes.reset_is_clear_context();
9485 }
9486 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9487 emit_int8(0x40);
9488 emit_operand(dst, src, 0);
9489 }
9490
9491 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9492 assert(VM_Version::supports_evex(), "");
9493 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9494 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9495 attributes.set_is_evex_instruction();
9496 attributes.set_embedded_opmask_register_specifier(mask);
9497 if (merge) {
9498 attributes.reset_is_clear_context();
9499 }
9500 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9501 emit_int16(0x59, (0xC0 | encode));
9502 }
9503
9504 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9505 InstructionMark im(this);
9506 assert(VM_Version::supports_evex(), "");
9507 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9508 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9509 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9510 attributes.set_is_evex_instruction();
9511 attributes.set_embedded_opmask_register_specifier(mask);
9512 if (merge) {
9513 attributes.reset_is_clear_context();
9514 }
9515 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9516 emit_int8(0x59);
9517 emit_operand(dst, src, 0);
9518 }
9519
9520 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9521 assert(VM_Version::supports_evex(), "");
9522 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9523 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9524 attributes.set_is_evex_instruction();
9525 attributes.set_embedded_opmask_register_specifier(mask);
9526 if (merge) {
9527 attributes.reset_is_clear_context();
9528 }
9529 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9530 emit_int16(0x59, (0xC0 | encode));
9531 }
9532
9533 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9534 InstructionMark im(this);
9535 assert(VM_Version::supports_evex(), "");
9536 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9537 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9538 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9539 attributes.set_is_evex_instruction();
9540 attributes.set_embedded_opmask_register_specifier(mask);
9541 if (merge) {
9542 attributes.reset_is_clear_context();
9543 }
9544 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9545 emit_int8(0x59);
9546 emit_operand(dst, src, 0);
9547 }
9548
9549 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9550 assert(VM_Version::supports_evex(), "");
9551 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9552 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9553 attributes.set_is_evex_instruction();
9554 attributes.set_embedded_opmask_register_specifier(mask);
9555 if (merge) {
9556 attributes.reset_is_clear_context();
9557 }
9558 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9559 emit_int16(0x51, (0xC0 | encode));
9560 }
9561
9562 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9563 InstructionMark im(this);
9564 assert(VM_Version::supports_evex(), "");
9565 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9566 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9567 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9568 attributes.set_is_evex_instruction();
9569 attributes.set_embedded_opmask_register_specifier(mask);
9570 if (merge) {
9571 attributes.reset_is_clear_context();
9572 }
9573 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9574 emit_int8(0x51);
9575 emit_operand(dst, src, 0);
9576 }
9577
9578 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9579 assert(VM_Version::supports_evex(), "");
9580 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9581 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9582 attributes.set_is_evex_instruction();
9583 attributes.set_embedded_opmask_register_specifier(mask);
9584 if (merge) {
9585 attributes.reset_is_clear_context();
9586 }
9587 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9588 emit_int16(0x51, (0xC0 | encode));
9589 }
9590
9591 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9592 InstructionMark im(this);
9593 assert(VM_Version::supports_evex(), "");
9594 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9595 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9596 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9597 attributes.set_is_evex_instruction();
9598 attributes.set_embedded_opmask_register_specifier(mask);
9599 if (merge) {
9600 attributes.reset_is_clear_context();
9601 }
9602 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9603 emit_int8(0x51);
9604 emit_operand(dst, src, 0);
9605 }
9606
9607
9608 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9609 assert(VM_Version::supports_evex(), "");
9610 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9611 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9612 attributes.set_is_evex_instruction();
9613 attributes.set_embedded_opmask_register_specifier(mask);
9614 if (merge) {
9615 attributes.reset_is_clear_context();
9616 }
9617 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9618 emit_int16(0x5E, (0xC0 | encode));
9619 }
9620
9621 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9622 InstructionMark im(this);
9623 assert(VM_Version::supports_evex(), "");
9624 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9625 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9626 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9627 attributes.set_is_evex_instruction();
9628 attributes.set_embedded_opmask_register_specifier(mask);
9629 if (merge) {
9630 attributes.reset_is_clear_context();
9631 }
9632 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9633 emit_int8(0x5E);
9634 emit_operand(dst, src, 0);
9635 }
9636
9637 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9638 assert(VM_Version::supports_evex(), "");
9639 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9640 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9641 attributes.set_is_evex_instruction();
9642 attributes.set_embedded_opmask_register_specifier(mask);
9643 if (merge) {
9644 attributes.reset_is_clear_context();
9645 }
9646 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9647 emit_int16(0x5E, (0xC0 | encode));
9648 }
9649
9650 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9651 InstructionMark im(this);
9652 assert(VM_Version::supports_evex(), "");
9653 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9654 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9655 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9656 attributes.set_is_evex_instruction();
9657 attributes.set_embedded_opmask_register_specifier(mask);
9658 if (merge) {
9659 attributes.reset_is_clear_context();
9660 }
9661 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9662 emit_int8(0x5E);
9663 emit_operand(dst, src, 0);
9664 }
9665
9666 void Assembler::evdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src, EvexRoundPrefix rmode) {
9667 assert(VM_Version::supports_evex(), "");
9668 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9669 attributes.set_extended_context();
9670 attributes.set_is_evex_instruction();
9671 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9672 emit_int16(0x5E, (0xC0 | encode));
9673 }
9674
9675 void Assembler::evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9676 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9677 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9678 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9679 attributes.set_is_evex_instruction();
9680 attributes.set_embedded_opmask_register_specifier(mask);
9681 if (merge) {
9682 attributes.reset_is_clear_context();
9683 }
9684 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9685 emit_int16(0x1C, (0xC0 | encode));
9686 }
9687
9688
9689 void Assembler::evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9690 InstructionMark im(this);
9691 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9692 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9693 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9694 attributes.set_is_evex_instruction();
9695 attributes.set_embedded_opmask_register_specifier(mask);
9696 if (merge) {
9697 attributes.reset_is_clear_context();
9698 }
9699 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9700 emit_int8(0x1C);
9701 emit_operand(dst, src, 0);
9702 }
9703
9704 void Assembler::evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9705 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9706 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9707 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9708 attributes.set_is_evex_instruction();
9709 attributes.set_embedded_opmask_register_specifier(mask);
9710 if (merge) {
9711 attributes.reset_is_clear_context();
9712 }
9713 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9714 emit_int16(0x1D, (0xC0 | encode));
9715 }
9716
9717
9718 void Assembler::evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9719 InstructionMark im(this);
9720 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9721 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9722 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9723 attributes.set_is_evex_instruction();
9724 attributes.set_embedded_opmask_register_specifier(mask);
9725 if (merge) {
9726 attributes.reset_is_clear_context();
9727 }
9728 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9729 emit_int8(0x1D);
9730 emit_operand(dst, src, 0);
9731 }
9732
9733 void Assembler::evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9734 assert(VM_Version::supports_evex(), "");
9735 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9736 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9737 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9738 attributes.set_is_evex_instruction();
9739 attributes.set_embedded_opmask_register_specifier(mask);
9740 if (merge) {
9741 attributes.reset_is_clear_context();
9742 }
9743 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9744 emit_int16(0x1E, (0xC0 | encode));
9745 }
9746
9747
9748 void Assembler::evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9749 InstructionMark im(this);
9750 assert(VM_Version::supports_evex(), "");
9751 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9752 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9753 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9754 attributes.set_is_evex_instruction();
9755 attributes.set_embedded_opmask_register_specifier(mask);
9756 if (merge) {
9757 attributes.reset_is_clear_context();
9758 }
9759 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9760 emit_int8(0x1E);
9761 emit_operand(dst, src, 0);
9762 }
9763
9764 void Assembler::evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9765 assert(VM_Version::supports_evex(), "");
9766 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9767 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9768 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9769 attributes.set_is_evex_instruction();
9770 attributes.set_embedded_opmask_register_specifier(mask);
9771 if (merge) {
9772 attributes.reset_is_clear_context();
9773 }
9774 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9775 emit_int16(0x1F, (0xC0 | encode));
9776 }
9777
9778
9779 void Assembler::evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9780 InstructionMark im(this);
9781 assert(VM_Version::supports_evex(), "");
9782 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9783 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9784 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9785 attributes.set_is_evex_instruction();
9786 attributes.set_embedded_opmask_register_specifier(mask);
9787 if (merge) {
9788 attributes.reset_is_clear_context();
9789 }
9790 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9791 emit_int8(0x1F);
9792 emit_operand(dst, src, 0);
9793 }
9794
9795 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9796 assert(VM_Version::supports_evex(), "");
9797 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9798 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9799 attributes.set_is_evex_instruction();
9800 attributes.set_embedded_opmask_register_specifier(mask);
9801 if (merge) {
9802 attributes.reset_is_clear_context();
9803 }
9804 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9805 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9806 }
9807
9808 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9809 InstructionMark im(this);
9810 assert(VM_Version::supports_evex(), "");
9811 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9812 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9813 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9814 attributes.set_is_evex_instruction();
9815 attributes.set_embedded_opmask_register_specifier(mask);
9816 if (merge) {
9817 attributes.reset_is_clear_context();
9818 }
9819 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9820 emit_int8((unsigned char)0xA8);
9821 emit_operand(dst, src, 0);
9822 }
9823
9824 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9825 assert(VM_Version::supports_evex(), "");
9826 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9827 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9828 attributes.set_is_evex_instruction();
9829 attributes.set_embedded_opmask_register_specifier(mask);
9830 if (merge) {
9831 attributes.reset_is_clear_context();
9832 }
9833 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9834 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9835 }
9836
9837 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9838 InstructionMark im(this);
9839 assert(VM_Version::supports_evex(), "");
9840 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9841 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9842 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9843 attributes.set_is_evex_instruction();
9844 attributes.set_embedded_opmask_register_specifier(mask);
9845 if (merge) {
9846 attributes.reset_is_clear_context();
9847 }
9848 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9849 emit_int8((unsigned char)0xA8);
9850 emit_operand(dst, src, 0);
9851 }
9852
9853 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9854 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9855 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9856 attributes.set_is_evex_instruction();
9857 attributes.set_embedded_opmask_register_specifier(mask);
9858 if (merge) {
9859 attributes.reset_is_clear_context();
9860 }
9861 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9862 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9863 }
9864
9865 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9866 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9867 InstructionMark im(this);
9868 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9869 attributes.set_is_evex_instruction();
9870 attributes.set_embedded_opmask_register_specifier(mask);
9871 if (merge) {
9872 attributes.reset_is_clear_context();
9873 }
9874 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9875 emit_int8((unsigned char)0x8D);
9876 emit_operand(dst, src, 0);
9877 }
9878
9879 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9880 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9881 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9882 attributes.set_is_evex_instruction();
9883 attributes.set_embedded_opmask_register_specifier(mask);
9884 if (merge) {
9885 attributes.reset_is_clear_context();
9886 }
9887 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9888 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9889 }
9890
9891 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9892 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9893 InstructionMark im(this);
9894 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9895 attributes.set_is_evex_instruction();
9896 attributes.set_embedded_opmask_register_specifier(mask);
9897 if (merge) {
9898 attributes.reset_is_clear_context();
9899 }
9900 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9901 emit_int8((unsigned char)0x8D);
9902 emit_operand(dst, src, 0);
9903 }
9904
9905 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9906 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9907 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9908 attributes.set_is_evex_instruction();
9909 attributes.set_embedded_opmask_register_specifier(mask);
9910 if (merge) {
9911 attributes.reset_is_clear_context();
9912 }
9913 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9914 emit_int16(0x36, (0xC0 | encode));
9915 }
9916
9917 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9918 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9919 InstructionMark im(this);
9920 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9921 attributes.set_is_evex_instruction();
9922 attributes.set_embedded_opmask_register_specifier(mask);
9923 if (merge) {
9924 attributes.reset_is_clear_context();
9925 }
9926 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9927 emit_int8(0x36);
9928 emit_operand(dst, src, 0);
9929 }
9930
9931 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9932 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9933 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9934 attributes.set_is_evex_instruction();
9935 attributes.set_embedded_opmask_register_specifier(mask);
9936 if (merge) {
9937 attributes.reset_is_clear_context();
9938 }
9939 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9940 emit_int16(0x36, (0xC0 | encode));
9941 }
9942
9943 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9944 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9945 InstructionMark im(this);
9946 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9947 attributes.set_is_evex_instruction();
9948 attributes.set_embedded_opmask_register_specifier(mask);
9949 if (merge) {
9950 attributes.reset_is_clear_context();
9951 }
9952 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9953 emit_int8(0x36);
9954 emit_operand(dst, src, 0);
9955 }
9956
9957 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9958 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9959 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9960 attributes.set_is_evex_instruction();
9961 attributes.set_embedded_opmask_register_specifier(mask);
9962 if (merge) {
9963 attributes.reset_is_clear_context();
9964 }
9965 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9966 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
9967 }
9968
9969 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9970 assert(VM_Version::supports_evex(), "");
9971 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9972 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9973 attributes.set_is_evex_instruction();
9974 attributes.set_embedded_opmask_register_specifier(mask);
9975 if (merge) {
9976 attributes.reset_is_clear_context();
9977 }
9978 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9979 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
9980 }
9981
9982 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9983 assert(VM_Version::supports_evex(), "");
9984 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9985 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9986 attributes.set_is_evex_instruction();
9987 attributes.set_embedded_opmask_register_specifier(mask);
9988 if (merge) {
9989 attributes.reset_is_clear_context();
9990 }
9991 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9992 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
9993 }
9994
9995 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9996 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9998 attributes.set_is_evex_instruction();
9999 attributes.set_embedded_opmask_register_specifier(mask);
10000 if (merge) {
10001 attributes.reset_is_clear_context();
10002 }
10003 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10004 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
10005 }
10006
10007 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10008 assert(VM_Version::supports_evex(), "");
10009 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10010 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10011 attributes.set_is_evex_instruction();
10012 attributes.set_embedded_opmask_register_specifier(mask);
10013 if (merge) {
10014 attributes.reset_is_clear_context();
10015 }
10016 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10017 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10018 }
10019
10020 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10021 assert(VM_Version::supports_evex(), "");
10022 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10023 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10024 attributes.set_is_evex_instruction();
10025 attributes.set_embedded_opmask_register_specifier(mask);
10026 if (merge) {
10027 attributes.reset_is_clear_context();
10028 }
10029 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10030 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
10031 }
10032
10033 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10034 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10035 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10036 attributes.set_is_evex_instruction();
10037 attributes.set_embedded_opmask_register_specifier(mask);
10038 if (merge) {
10039 attributes.reset_is_clear_context();
10040 }
10041 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10042 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
10043 }
10044
10045 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10046 assert(VM_Version::supports_evex(), "");
10047 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10049 attributes.set_is_evex_instruction();
10050 attributes.set_embedded_opmask_register_specifier(mask);
10051 if (merge) {
10052 attributes.reset_is_clear_context();
10053 }
10054 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10055 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10056 }
10057
10058 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10059 assert(VM_Version::supports_evex(), "");
10060 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10061 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10062 attributes.set_is_evex_instruction();
10063 attributes.set_embedded_opmask_register_specifier(mask);
10064 if (merge) {
10065 attributes.reset_is_clear_context();
10066 }
10067 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10068 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10069 }
10070
10071 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10072 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10073 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10074 attributes.set_is_evex_instruction();
10075 attributes.set_embedded_opmask_register_specifier(mask);
10076 if (merge) {
10077 attributes.reset_is_clear_context();
10078 }
10079 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10080 emit_int16((unsigned char)0xF1, (0xC0 | encode));
10081 }
10082
10083 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10084 assert(VM_Version::supports_evex(), "");
10085 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10086 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10087 attributes.set_is_evex_instruction();
10088 attributes.set_embedded_opmask_register_specifier(mask);
10089 if (merge) {
10090 attributes.reset_is_clear_context();
10091 }
10092 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10093 emit_int16((unsigned char)0xF2, (0xC0 | encode));
10094 }
10095
10096 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10097 assert(VM_Version::supports_evex(), "");
10098 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10099 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10100 attributes.set_is_evex_instruction();
10101 attributes.set_embedded_opmask_register_specifier(mask);
10102 if (merge) {
10103 attributes.reset_is_clear_context();
10104 }
10105 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10106 emit_int16((unsigned char)0xF3, (0xC0 | encode));
10107 }
10108
10109 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10110 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10111 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10112 attributes.set_is_evex_instruction();
10113 attributes.set_embedded_opmask_register_specifier(mask);
10114 if (merge) {
10115 attributes.reset_is_clear_context();
10116 }
10117 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10118 emit_int16((unsigned char)0xD1, (0xC0 | encode));
10119 }
10120
10121 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10122 assert(VM_Version::supports_evex(), "");
10123 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10125 attributes.set_is_evex_instruction();
10126 attributes.set_embedded_opmask_register_specifier(mask);
10127 if (merge) {
10128 attributes.reset_is_clear_context();
10129 }
10130 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10131 emit_int16((unsigned char)0xD2, (0xC0 | encode));
10132 }
10133
10134 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10135 assert(VM_Version::supports_evex(), "");
10136 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10137 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10138 attributes.set_is_evex_instruction();
10139 attributes.set_embedded_opmask_register_specifier(mask);
10140 if (merge) {
10141 attributes.reset_is_clear_context();
10142 }
10143 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10144 emit_int16((unsigned char)0xD3, (0xC0 | encode));
10145 }
10146
10147 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10148 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10149 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10150 attributes.set_is_evex_instruction();
10151 attributes.set_embedded_opmask_register_specifier(mask);
10152 if (merge) {
10153 attributes.reset_is_clear_context();
10154 }
10155 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10156 emit_int16((unsigned char)0xE1, (0xC0 | encode));
10157 }
10158
10159 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10160 assert(VM_Version::supports_evex(), "");
10161 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10162 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10163 attributes.set_is_evex_instruction();
10164 attributes.set_embedded_opmask_register_specifier(mask);
10165 if (merge) {
10166 attributes.reset_is_clear_context();
10167 }
10168 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10169 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10170 }
10171
10172 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10173 assert(VM_Version::supports_evex(), "");
10174 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10175 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10176 attributes.set_is_evex_instruction();
10177 attributes.set_embedded_opmask_register_specifier(mask);
10178 if (merge) {
10179 attributes.reset_is_clear_context();
10180 }
10181 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10182 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10183 }
10184
10185 void Assembler::evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10186 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10187 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10188 attributes.set_is_evex_instruction();
10189 attributes.set_embedded_opmask_register_specifier(mask);
10190 if (merge) {
10191 attributes.reset_is_clear_context();
10192 }
10193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10194 emit_int16(0x12, (0xC0 | encode));
10195 }
10196
10197 void Assembler::evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10198 assert(VM_Version::supports_evex(), "");
10199 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10200 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10201 attributes.set_is_evex_instruction();
10202 attributes.set_embedded_opmask_register_specifier(mask);
10203 if (merge) {
10204 attributes.reset_is_clear_context();
10205 }
10206 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10207 emit_int16(0x47, (0xC0 | encode));
10208 }
10209
10210 void Assembler::evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10211 assert(VM_Version::supports_evex(), "");
10212 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10213 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10214 attributes.set_is_evex_instruction();
10215 attributes.set_embedded_opmask_register_specifier(mask);
10216 if (merge) {
10217 attributes.reset_is_clear_context();
10218 }
10219 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10220 emit_int16(0x47, (0xC0 | encode));
10221 }
10222
10223 void Assembler::evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10224 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10225 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10226 attributes.set_is_evex_instruction();
10227 attributes.set_embedded_opmask_register_specifier(mask);
10228 if (merge) {
10229 attributes.reset_is_clear_context();
10230 }
10231 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10232 emit_int16(0x10, (0xC0 | encode));
10233 }
10234
10235 void Assembler::evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10236 assert(VM_Version::supports_evex(), "");
10237 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10239 attributes.set_is_evex_instruction();
10240 attributes.set_embedded_opmask_register_specifier(mask);
10241 if (merge) {
10242 attributes.reset_is_clear_context();
10243 }
10244 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10245 emit_int16(0x45, (0xC0 | encode));
10246 }
10247
10248 void Assembler::evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10249 assert(VM_Version::supports_evex(), "");
10250 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10251 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10252 attributes.set_is_evex_instruction();
10253 attributes.set_embedded_opmask_register_specifier(mask);
10254 if (merge) {
10255 attributes.reset_is_clear_context();
10256 }
10257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10258 emit_int16(0x45, (0xC0 | encode));
10259 }
10260
10261 void Assembler::evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10262 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10263 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10264 attributes.set_is_evex_instruction();
10265 attributes.set_embedded_opmask_register_specifier(mask);
10266 if (merge) {
10267 attributes.reset_is_clear_context();
10268 }
10269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10270 emit_int16(0x11, (0xC0 | encode));
10271 }
10272
10273 void Assembler::evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10274 assert(VM_Version::supports_evex(), "");
10275 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10277 attributes.set_is_evex_instruction();
10278 attributes.set_embedded_opmask_register_specifier(mask);
10279 if (merge) {
10280 attributes.reset_is_clear_context();
10281 }
10282 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10283 emit_int16(0x46, (0xC0 | encode));
10284 }
10285
10286 void Assembler::evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10287 assert(VM_Version::supports_evex(), "");
10288 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10289 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10290 attributes.set_is_evex_instruction();
10291 attributes.set_embedded_opmask_register_specifier(mask);
10292 if (merge) {
10293 attributes.reset_is_clear_context();
10294 }
10295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10296 emit_int16(0x46, (0xC0 | encode));
10297 }
10298
10299 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10300 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10301 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10302 attributes.set_is_evex_instruction();
10303 attributes.set_embedded_opmask_register_specifier(mask);
10304 if (merge) {
10305 attributes.reset_is_clear_context();
10306 }
10307 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10308 emit_int16(0x38, (0xC0 | encode));
10309 }
10310
10311 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10312 assert(VM_Version::supports_avx512bw(), "");
10313 InstructionMark im(this);
10314 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10315 attributes.set_is_evex_instruction();
10316 attributes.set_embedded_opmask_register_specifier(mask);
10317 if (merge) {
10318 attributes.reset_is_clear_context();
10319 }
10320 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10321 emit_int8(0x38);
10322 emit_operand(dst, src, 0);
10323 }
10324
10325 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10326 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10328 attributes.set_is_evex_instruction();
10329 attributes.set_embedded_opmask_register_specifier(mask);
10330 if (merge) {
10331 attributes.reset_is_clear_context();
10332 }
10333 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10334 emit_int16((unsigned char)0xEA, (0xC0 | encode));
10335 }
10336
10337 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10338 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10339 InstructionMark im(this);
10340 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10341 attributes.set_is_evex_instruction();
10342 attributes.set_embedded_opmask_register_specifier(mask);
10343 if (merge) {
10344 attributes.reset_is_clear_context();
10345 }
10346 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10347 emit_int8((unsigned char)0xEA);
10348 emit_operand(dst, src, 0);
10349 }
10350
10351 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10352 assert(VM_Version::supports_evex(), "");
10353 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10354 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10355 attributes.set_is_evex_instruction();
10356 attributes.set_embedded_opmask_register_specifier(mask);
10357 if (merge) {
10358 attributes.reset_is_clear_context();
10359 }
10360 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10361 emit_int16(0x39, (0xC0 | encode));
10362 }
10363
10364 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10365 assert(VM_Version::supports_evex(), "");
10366 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10367 InstructionMark im(this);
10368 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10369 attributes.set_is_evex_instruction();
10370 attributes.set_embedded_opmask_register_specifier(mask);
10371 if (merge) {
10372 attributes.reset_is_clear_context();
10373 }
10374 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10375 emit_int8(0x39);
10376 emit_operand(dst, src, 0);
10377 }
10378
10379 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10380 assert(VM_Version::supports_evex(), "");
10381 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10382 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10383 attributes.set_is_evex_instruction();
10384 attributes.set_embedded_opmask_register_specifier(mask);
10385 if (merge) {
10386 attributes.reset_is_clear_context();
10387 }
10388 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10389 emit_int16(0x39, (0xC0 | encode));
10390 }
10391
10392 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10393 assert(VM_Version::supports_evex(), "");
10394 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10395 InstructionMark im(this);
10396 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10397 attributes.set_is_evex_instruction();
10398 attributes.set_embedded_opmask_register_specifier(mask);
10399 if (merge) {
10400 attributes.reset_is_clear_context();
10401 }
10402 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10403 emit_int8(0x39);
10404 emit_operand(dst, src, 0);
10405 }
10406
10407
10408 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10409 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10410 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10411 attributes.set_is_evex_instruction();
10412 attributes.set_embedded_opmask_register_specifier(mask);
10413 if (merge) {
10414 attributes.reset_is_clear_context();
10415 }
10416 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10417 emit_int16(0x3C, (0xC0 | encode));
10418 }
10419
10420 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10421 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10422 InstructionMark im(this);
10423 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10424 attributes.set_is_evex_instruction();
10425 attributes.set_embedded_opmask_register_specifier(mask);
10426 if (merge) {
10427 attributes.reset_is_clear_context();
10428 }
10429 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10430 emit_int8(0x3C);
10431 emit_operand(dst, src, 0);
10432 }
10433
10434 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10435 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10436 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10437 attributes.set_is_evex_instruction();
10438 attributes.set_embedded_opmask_register_specifier(mask);
10439 if (merge) {
10440 attributes.reset_is_clear_context();
10441 }
10442 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10443 emit_int16((unsigned char)0xEE, (0xC0 | encode));
10444 }
10445
10446 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10447 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10448 InstructionMark im(this);
10449 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10450 attributes.set_is_evex_instruction();
10451 attributes.set_embedded_opmask_register_specifier(mask);
10452 if (merge) {
10453 attributes.reset_is_clear_context();
10454 }
10455 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10456 emit_int8((unsigned char)0xEE);
10457 emit_operand(dst, src, 0);
10458 }
10459
10460 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10461 assert(VM_Version::supports_evex(), "");
10462 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10464 attributes.set_is_evex_instruction();
10465 attributes.set_embedded_opmask_register_specifier(mask);
10466 if (merge) {
10467 attributes.reset_is_clear_context();
10468 }
10469 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10470 emit_int16(0x3D, (0xC0 | encode));
10471 }
10472
10473 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10474 assert(VM_Version::supports_evex(), "");
10475 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10476 InstructionMark im(this);
10477 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10478 attributes.set_is_evex_instruction();
10479 attributes.set_embedded_opmask_register_specifier(mask);
10480 if (merge) {
10481 attributes.reset_is_clear_context();
10482 }
10483 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10484 emit_int8(0x3D);
10485 emit_operand(dst, src, 0);
10486 }
10487
10488 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10489 assert(VM_Version::supports_evex(), "");
10490 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10491 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10492 attributes.set_is_evex_instruction();
10493 attributes.set_embedded_opmask_register_specifier(mask);
10494 if (merge) {
10495 attributes.reset_is_clear_context();
10496 }
10497 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10498 emit_int16(0x3D, (0xC0 | encode));
10499 }
10500
10501 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10502 assert(VM_Version::supports_evex(), "");
10503 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10504 InstructionMark im(this);
10505 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10506 attributes.set_is_evex_instruction();
10507 attributes.set_embedded_opmask_register_specifier(mask);
10508 if (merge) {
10509 attributes.reset_is_clear_context();
10510 }
10511 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10512 emit_int8(0x3D);
10513 emit_operand(dst, src, 0);
10514 }
10515
10516 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10517 assert(VM_Version::supports_evex(), "requires EVEX support");
10518 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10519 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10520 attributes.set_is_evex_instruction();
10521 attributes.set_embedded_opmask_register_specifier(mask);
10522 if (merge) {
10523 attributes.reset_is_clear_context();
10524 }
10525 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10526 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10527 }
10528
10529 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10530 assert(VM_Version::supports_evex(), "requires EVEX support");
10531 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10532 assert(dst != xnoreg, "sanity");
10533 InstructionMark im(this);
10534 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10535 attributes.set_is_evex_instruction();
10536 attributes.set_embedded_opmask_register_specifier(mask);
10537 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10538 if (merge) {
10539 attributes.reset_is_clear_context();
10540 }
10541 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10542 emit_int8(0x25);
10543 emit_operand(dst, src3, 1);
10544 emit_int8(imm8);
10545 }
10546
10547 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10548 assert(VM_Version::supports_evex(), "requires EVEX support");
10549 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10550 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10551 attributes.set_is_evex_instruction();
10552 attributes.set_embedded_opmask_register_specifier(mask);
10553 if (merge) {
10554 attributes.reset_is_clear_context();
10555 }
10556 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10557 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10558 }
10559
10560 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10561 assert(VM_Version::supports_evex(), "requires EVEX support");
10562 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10563 assert(dst != xnoreg, "sanity");
10564 InstructionMark im(this);
10565 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10566 attributes.set_is_evex_instruction();
10567 attributes.set_embedded_opmask_register_specifier(mask);
10568 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10569 if (merge) {
10570 attributes.reset_is_clear_context();
10571 }
10572 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10573 emit_int8(0x25);
10574 emit_operand(dst, src3, 1);
10575 emit_int8(imm8);
10576 }
10577
10578 void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
10579 assert(VM_Version::supports_gfni(), "");
10580 assert(VM_Version::supports_sse(), "");
10581 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
10582 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10583 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10584 }
10585
10586 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
10587 assert(VM_Version::supports_gfni(), "requires GFNI support");
10588 assert(VM_Version::supports_sse(), "");
10589 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10590 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10591 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10592 }
10593
10594 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10595 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
10596 assert(UseAVX >= 2, "");
10597 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10598 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10599 emit_int16(0x58, (0xC0 | encode));
10600 }
10601
10602 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
10603 assert(VM_Version::supports_avx2(), "");
10604 assert(dst != xnoreg, "sanity");
10605 InstructionMark im(this);
10606 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10607 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10608 // swap src<->dst for encoding
10609 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10610 emit_int8(0x58);
10611 emit_operand(dst, src, 0);
10612 }
10613
10614 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10615 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
10616 assert(VM_Version::supports_avx2(), "");
10617 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10618 attributes.set_rex_vex_w_reverted();
10619 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10620 emit_int16(0x59, (0xC0 | encode));
10621 }
10622
10623 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
10624 assert(VM_Version::supports_avx2(), "");
10625 assert(dst != xnoreg, "sanity");
10626 InstructionMark im(this);
10627 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10628 attributes.set_rex_vex_w_reverted();
10629 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10630 // swap src<->dst for encoding
10631 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10632 emit_int8(0x59);
10633 emit_operand(dst, src, 0);
10634 }
10635
10636 void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) {
10637 assert(vector_len != Assembler::AVX_128bit, "");
10638 assert(VM_Version::supports_evex(), "");
10639 assert(dst != xnoreg, "sanity");
10640 InstructionMark im(this);
10641 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10642 attributes.set_rex_vex_w_reverted();
10643 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10644 // swap src<->dst for encoding
10645 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10646 emit_int8(0x5A);
10647 emit_operand(dst, src, 0);
10648 }
10649
10650 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
10651 assert(vector_len != Assembler::AVX_128bit, "");
10652 assert(VM_Version::supports_avx512dq(), "");
10653 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10654 attributes.set_rex_vex_w_reverted();
10655 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10656 emit_int16(0x5A, (0xC0 | encode));
10657 }
10658
10659 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
10660 assert(vector_len != Assembler::AVX_128bit, "");
10661 assert(VM_Version::supports_avx512dq(), "");
10662 assert(dst != xnoreg, "sanity");
10663 InstructionMark im(this);
10664 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10665 attributes.set_rex_vex_w_reverted();
10666 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
10667 // swap src<->dst for encoding
10668 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10669 emit_int8(0x5A);
10670 emit_operand(dst, src, 0);
10671 }
10672
10673 // scalar single/double precision replicate
10674
10675 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
10676 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
10677 assert(VM_Version::supports_avx2(), "");
10678 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10679 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10680 emit_int16(0x18, (0xC0 | encode));
10681 }
10682
10683 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
10684 assert(VM_Version::supports_avx(), "");
10685 assert(dst != xnoreg, "sanity");
10686 InstructionMark im(this);
10687 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10688 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10689 // swap src<->dst for encoding
10690 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10691 emit_int8(0x18);
10692 emit_operand(dst, src, 0);
10693 }
10694
10695 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
10696 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
10697 assert(VM_Version::supports_avx2(), "");
10698 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10699 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10700 attributes.set_rex_vex_w_reverted();
10701 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10702 emit_int16(0x19, (0xC0 | encode));
10703 }
10704
10705 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
10706 assert(VM_Version::supports_avx(), "");
10707 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10708 assert(dst != xnoreg, "sanity");
10709 InstructionMark im(this);
10710 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10711 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10712 attributes.set_rex_vex_w_reverted();
10713 // swap src<->dst for encoding
10714 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10715 emit_int8(0x19);
10716 emit_operand(dst, src, 0);
10717 }
10718
10719 void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
10720 assert(VM_Version::supports_avx(), "");
10721 assert(vector_len == AVX_256bit, "");
10722 assert(dst != xnoreg, "sanity");
10723 InstructionMark im(this);
10724 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10725 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10726 // swap src<->dst for encoding
10727 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10728 emit_int8(0x1A);
10729 emit_operand(dst, src, 0);
10730 }
10731
10732 // gpr source broadcast forms
10733
10734 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10735 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
10736 assert(VM_Version::supports_avx512bw(), "");
10737 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10738 attributes.set_is_evex_instruction();
10739 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10740 emit_int16(0x7A, (0xC0 | encode));
10741 }
10742
10743 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10744 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
10745 assert(VM_Version::supports_avx512bw(), "");
10746 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10747 attributes.set_is_evex_instruction();
10748 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10749 emit_int16(0x7B, (0xC0 | encode));
10750 }
10751
10752 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10753 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
10754 assert(VM_Version::supports_evex(), "");
10755 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10756 attributes.set_is_evex_instruction();
10757 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10758 emit_int16(0x7C, (0xC0 | encode));
10759 }
10760
10761 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10762 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
10763 assert(VM_Version::supports_evex(), "");
10764 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10765 attributes.set_is_evex_instruction();
10766 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10767 emit_int16(0x7C, (0xC0 | encode));
10768 }
10769
10770 void Assembler::vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10771 assert(VM_Version::supports_avx2(), "");
10772 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10773 assert(dst != xnoreg, "sanity");
10774 assert(src.isxmmindex(),"expected to be xmm index");
10775 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10776 InstructionMark im(this);
10777 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10778 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10779 emit_int8((unsigned char)0x90);
10780 emit_operand(dst, src, 0);
10781 }
10782
10783 void Assembler::vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10784 assert(VM_Version::supports_avx2(), "");
10785 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10786 assert(dst != xnoreg, "sanity");
10787 assert(src.isxmmindex(),"expected to be xmm index");
10788 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10789 InstructionMark im(this);
10790 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10791 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10792 emit_int8((unsigned char)0x90);
10793 emit_operand(dst, src, 0);
10794 }
10795
10796 void Assembler::vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10797 assert(VM_Version::supports_avx2(), "");
10798 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10799 assert(dst != xnoreg, "sanity");
10800 assert(src.isxmmindex(),"expected to be xmm index");
10801 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10802 InstructionMark im(this);
10803 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10804 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10805 emit_int8((unsigned char)0x92);
10806 emit_operand(dst, src, 0);
10807 }
10808
10809 void Assembler::vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10810 assert(VM_Version::supports_avx2(), "");
10811 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10812 assert(dst != xnoreg, "sanity");
10813 assert(src.isxmmindex(),"expected to be xmm index");
10814 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10815 InstructionMark im(this);
10816 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
10817 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10818 emit_int8((unsigned char)0x92);
10819 emit_operand(dst, src, 0);
10820 }
10821 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10822 assert(VM_Version::supports_evex(), "");
10823 assert(dst != xnoreg, "sanity");
10824 assert(src.isxmmindex(),"expected to be xmm index");
10825 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10826 assert(mask != k0, "instruction will #UD if mask is in k0");
10827 InstructionMark im(this);
10828 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10829 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10830 attributes.reset_is_clear_context();
10831 attributes.set_embedded_opmask_register_specifier(mask);
10832 attributes.set_is_evex_instruction();
10833 // swap src<->dst for encoding
10834 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10835 emit_int8((unsigned char)0x90);
10836 emit_operand(dst, src, 0);
10837 }
10838
10839 void Assembler::evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10840 assert(VM_Version::supports_evex(), "");
10841 assert(dst != xnoreg, "sanity");
10842 assert(src.isxmmindex(),"expected to be xmm index");
10843 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10844 assert(mask != k0, "instruction will #UD if mask is in k0");
10845 InstructionMark im(this);
10846 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10847 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10848 attributes.reset_is_clear_context();
10849 attributes.set_embedded_opmask_register_specifier(mask);
10850 attributes.set_is_evex_instruction();
10851 // swap src<->dst for encoding
10852 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10853 emit_int8((unsigned char)0x90);
10854 emit_operand(dst, src, 0);
10855 }
10856
10857 void Assembler::evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10858 assert(VM_Version::supports_evex(), "");
10859 assert(dst != xnoreg, "sanity");
10860 assert(src.isxmmindex(),"expected to be xmm index");
10861 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10862 assert(mask != k0, "instruction will #UD if mask is in k0");
10863 InstructionMark im(this);
10864 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10865 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10866 attributes.reset_is_clear_context();
10867 attributes.set_embedded_opmask_register_specifier(mask);
10868 attributes.set_is_evex_instruction();
10869 // swap src<->dst for encoding
10870 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10871 emit_int8((unsigned char)0x92);
10872 emit_operand(dst, src, 0);
10873 }
10874
10875 void Assembler::evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10876 assert(VM_Version::supports_evex(), "");
10877 assert(dst != xnoreg, "sanity");
10878 assert(src.isxmmindex(),"expected to be xmm index");
10879 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10880 assert(mask != k0, "instruction will #UD if mask is in k0");
10881 InstructionMark im(this);
10882 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10883 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10884 attributes.reset_is_clear_context();
10885 attributes.set_embedded_opmask_register_specifier(mask);
10886 attributes.set_is_evex_instruction();
10887 // swap src<->dst for encoding
10888 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10889 emit_int8((unsigned char)0x92);
10890 emit_operand(dst, src, 0);
10891 }
10892
10893 void Assembler::evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10894 assert(VM_Version::supports_evex(), "");
10895 assert(mask != k0, "instruction will #UD if mask is in k0");
10896 InstructionMark im(this);
10897 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10898 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10899 attributes.reset_is_clear_context();
10900 attributes.set_embedded_opmask_register_specifier(mask);
10901 attributes.set_is_evex_instruction();
10902 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10903 emit_int8((unsigned char)0xA0);
10904 emit_operand(src, dst, 0);
10905 }
10906
10907 void Assembler::evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10908 assert(VM_Version::supports_evex(), "");
10909 assert(mask != k0, "instruction will #UD if mask is in k0");
10910 InstructionMark im(this);
10911 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10912 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10913 attributes.reset_is_clear_context();
10914 attributes.set_embedded_opmask_register_specifier(mask);
10915 attributes.set_is_evex_instruction();
10916 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10917 emit_int8((unsigned char)0xA0);
10918 emit_operand(src, dst, 0);
10919 }
10920
10921 void Assembler::evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10922 assert(VM_Version::supports_evex(), "");
10923 assert(mask != k0, "instruction will #UD if mask is in k0");
10924 InstructionMark im(this);
10925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10926 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10927 attributes.reset_is_clear_context();
10928 attributes.set_embedded_opmask_register_specifier(mask);
10929 attributes.set_is_evex_instruction();
10930 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10931 emit_int8((unsigned char)0xA2);
10932 emit_operand(src, dst, 0);
10933 }
10934
10935 void Assembler::evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10936 assert(VM_Version::supports_evex(), "");
10937 assert(mask != k0, "instruction will #UD if mask is in k0");
10938 InstructionMark im(this);
10939 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10940 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10941 attributes.reset_is_clear_context();
10942 attributes.set_embedded_opmask_register_specifier(mask);
10943 attributes.set_is_evex_instruction();
10944 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10945 emit_int8((unsigned char)0xA2);
10946 emit_operand(src, dst, 0);
10947 }
10948 // Carry-Less Multiplication Quadword
10949 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
10950 assert(VM_Version::supports_clmul(), "");
10951 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10952 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10953 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10954 }
10955
10956 // Carry-Less Multiplication Quadword
10957 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
10958 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
10959 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10960 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10961 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10962 }
10963
10964 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
10965 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
10966 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10967 attributes.set_is_evex_instruction();
10968 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10969 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10970 }
10971
10972 void Assembler::vzeroupper_uncached() {
10973 if (VM_Version::supports_vzeroupper()) {
10974 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10975 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
10976 emit_int8(0x77);
10977 }
10978 }
10979
10980 void Assembler::vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8) {
10981 // Encoding: EVEX.LIG.66.0F3A.W0 67 /r ib
10982 assert(VM_Version::supports_evex(), "");
10983 assert(VM_Version::supports_avx512dq(), "");
10984 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10985 attributes.set_is_evex_instruction();
10986 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10987 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10988 }
10989
10990 void Assembler::vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8) {
10991 // Encoding: EVEX.LIG.66.0F3A.W1 67 /r ib
10992 assert(VM_Version::supports_evex(), "");
10993 assert(VM_Version::supports_avx512dq(), "");
10994 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10995 attributes.set_is_evex_instruction();
10996 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10997 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10998 }
10999
11000 void Assembler::fld_x(Address adr) {
11001 InstructionMark im(this);
11002 emit_int8((unsigned char)0xDB);
11003 emit_operand32(rbp, adr, 0);
11004 }
11005
11006 void Assembler::fstp_x(Address adr) {
11007 InstructionMark im(this);
11008 emit_int8((unsigned char)0xDB);
11009 emit_operand32(rdi, adr, 0);
11010 }
11011
11012 void Assembler::emit_operand32(Register reg, Address adr, int post_addr_length) {
11013 assert(reg->encoding() < 8, "no extended registers");
11014 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
11015 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
11016 }
11017
11018 void Assembler::fld_d(Address adr) {
11019 InstructionMark im(this);
11020 emit_int8((unsigned char)0xDD);
11021 emit_operand32(rax, adr, 0);
11022 }
11023
11024 void Assembler::fprem() {
11025 emit_int16((unsigned char)0xD9, (unsigned char)0xF8);
11026 }
11027
11028 void Assembler::fnstsw_ax() {
11029 emit_int16((unsigned char)0xDF, (unsigned char)0xE0);
11030 }
11031
11032 void Assembler::fstp_d(Address adr) {
11033 InstructionMark im(this);
11034 emit_int8((unsigned char)0xDD);
11035 emit_operand32(rbx, adr, 0);
11036 }
11037
11038 void Assembler::fstp_d(int index) {
11039 emit_farith(0xDD, 0xD8, index);
11040 }
11041
11042 void Assembler::emit_farith(int b1, int b2, int i) {
11043 assert(isByte(b1) && isByte(b2), "wrong opcode");
11044 assert(0 <= i && i < 8, "illegal stack offset");
11045 emit_int16(b1, b2 + i);
11046 }
11047
11048 #ifndef _LP64
11049 // 32bit only pieces of the assembler
11050
11051 void Assembler::emms() {
11052 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
11053 emit_int16(0x0F, 0x77);
11054 }
11055
11056 void Assembler::vzeroupper() {
11057 vzeroupper_uncached();
11058 }
11059
11060 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
11061 // NO PREFIX AS NEVER 64BIT
11062 InstructionMark im(this);
11063 emit_int16((unsigned char)0x81, (0xF8 | src1->encoding()));
11064 emit_data(imm32, rspec, 0);
11065 }
11066
11067 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
11068 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
11069 InstructionMark im(this);
11070 emit_int8((unsigned char)0x81);
11071 emit_operand(rdi, src1, 4);
11072 emit_data(imm32, rspec, 0);
11073 }
11074
11075 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
11076 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
11077 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
11078 void Assembler::cmpxchg8(Address adr) {
11079 InstructionMark im(this);
11080 emit_int16(0x0F, (unsigned char)0xC7);
11081 emit_operand(rcx, adr, 0);
11082 }
11083
11084 void Assembler::decl(Register dst) {
11085 // Don't use it directly. Use MacroAssembler::decrementl() instead.
11086 emit_int8(0x48 | dst->encoding());
11087 }
11088
11089 // 64bit doesn't use the x87
11090
11091 void Assembler::fabs() {
11092 emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
11093 }
11094
11095 void Assembler::fadd(int i) {
11096 emit_farith(0xD8, 0xC0, i);
11097 }
11098
11099 void Assembler::fadd_d(Address src) {
11100 InstructionMark im(this);
11101 emit_int8((unsigned char)0xDC);
11102 emit_operand32(rax, src, 0);
11103 }
11104
11105 void Assembler::fadd_s(Address src) {
11106 InstructionMark im(this);
11107 emit_int8((unsigned char)0xD8);
11108 emit_operand32(rax, src, 0);
11109 }
11110
11111 void Assembler::fadda(int i) {
11112 emit_farith(0xDC, 0xC0, i);
11113 }
11114
11115 void Assembler::faddp(int i) {
11116 emit_farith(0xDE, 0xC0, i);
11117 }
11118
11119 void Assembler::fchs() {
11120 emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
11121 }
11122
11123 void Assembler::fcom(int i) {
11124 emit_farith(0xD8, 0xD0, i);
11125 }
11126
11127 void Assembler::fcomp(int i) {
11128 emit_farith(0xD8, 0xD8, i);
11129 }
11130
11131 void Assembler::fcomp_d(Address src) {
11132 InstructionMark im(this);
11133 emit_int8((unsigned char)0xDC);
11134 emit_operand32(rbx, src, 0);
11135 }
11136
11137 void Assembler::fcomp_s(Address src) {
11138 InstructionMark im(this);
11139 emit_int8((unsigned char)0xD8);
11140 emit_operand32(rbx, src, 0);
11141 }
11142
11143 void Assembler::fcompp() {
11144 emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
11145 }
11146
11147 void Assembler::fcos() {
11148 emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
11149 }
11150
11151 void Assembler::fdecstp() {
11152 emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
11153 }
11154
11155 void Assembler::fdiv(int i) {
11156 emit_farith(0xD8, 0xF0, i);
11157 }
11158
11159 void Assembler::fdiv_d(Address src) {
11160 InstructionMark im(this);
11161 emit_int8((unsigned char)0xDC);
11162 emit_operand32(rsi, src, 0);
11163 }
11164
11165 void Assembler::fdiv_s(Address src) {
11166 InstructionMark im(this);
11167 emit_int8((unsigned char)0xD8);
11168 emit_operand32(rsi, src, 0);
11169 }
11170
11171 void Assembler::fdiva(int i) {
11172 emit_farith(0xDC, 0xF8, i);
11173 }
11174
11175 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
11176 // is erroneous for some of the floating-point instructions below.
11177
11178 void Assembler::fdivp(int i) {
11179 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
11180 }
11181
11182 void Assembler::fdivr(int i) {
11183 emit_farith(0xD8, 0xF8, i);
11184 }
11185
11186 void Assembler::fdivr_d(Address src) {
11187 InstructionMark im(this);
11188 emit_int8((unsigned char)0xDC);
11189 emit_operand32(rdi, src, 0);
11190 }
11191
11192 void Assembler::fdivr_s(Address src) {
11193 InstructionMark im(this);
11194 emit_int8((unsigned char)0xD8);
11195 emit_operand32(rdi, src, 0);
11196 }
11197
11198 void Assembler::fdivra(int i) {
11199 emit_farith(0xDC, 0xF0, i);
11200 }
11201
11202 void Assembler::fdivrp(int i) {
11203 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
11204 }
11205
11206 void Assembler::ffree(int i) {
11207 emit_farith(0xDD, 0xC0, i);
11208 }
11209
11210 void Assembler::fild_d(Address adr) {
11211 InstructionMark im(this);
11212 emit_int8((unsigned char)0xDF);
11213 emit_operand32(rbp, adr, 0);
11214 }
11215
11216 void Assembler::fild_s(Address adr) {
11217 InstructionMark im(this);
11218 emit_int8((unsigned char)0xDB);
11219 emit_operand32(rax, adr, 0);
11220 }
11221
11222 void Assembler::fincstp() {
11223 emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
11224 }
11225
11226 void Assembler::finit() {
11227 emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
11228 }
11229
11230 void Assembler::fist_s(Address adr) {
11231 InstructionMark im(this);
11232 emit_int8((unsigned char)0xDB);
11233 emit_operand32(rdx, adr, 0);
11234 }
11235
11236 void Assembler::fistp_d(Address adr) {
11237 InstructionMark im(this);
11238 emit_int8((unsigned char)0xDF);
11239 emit_operand32(rdi, adr, 0);
11240 }
11241
11242 void Assembler::fistp_s(Address adr) {
11243 InstructionMark im(this);
11244 emit_int8((unsigned char)0xDB);
11245 emit_operand32(rbx, adr, 0);
11246 }
11247
11248 void Assembler::fld1() {
11249 emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
11250 }
11251
11252 void Assembler::fld_s(Address adr) {
11253 InstructionMark im(this);
11254 emit_int8((unsigned char)0xD9);
11255 emit_operand32(rax, adr, 0);
11256 }
11257
11258
11259 void Assembler::fld_s(int index) {
11260 emit_farith(0xD9, 0xC0, index);
11261 }
11262
11263 void Assembler::fldcw(Address src) {
11264 InstructionMark im(this);
11265 emit_int8((unsigned char)0xD9);
11266 emit_operand32(rbp, src, 0);
11267 }
11268
11269 void Assembler::fldenv(Address src) {
11270 InstructionMark im(this);
11271 emit_int8((unsigned char)0xD9);
11272 emit_operand32(rsp, src, 0);
11273 }
11274
11275 void Assembler::fldlg2() {
11276 emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
11277 }
11278
11279 void Assembler::fldln2() {
11280 emit_int16((unsigned char)0xD9, (unsigned char)0xED);
11281 }
11282
11283 void Assembler::fldz() {
11284 emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
11285 }
11286
11287 void Assembler::flog() {
11288 fldln2();
11289 fxch();
11290 fyl2x();
11291 }
11292
11293 void Assembler::flog10() {
11294 fldlg2();
11295 fxch();
11296 fyl2x();
11297 }
11298
11299 void Assembler::fmul(int i) {
11300 emit_farith(0xD8, 0xC8, i);
11301 }
11302
11303 void Assembler::fmul_d(Address src) {
11304 InstructionMark im(this);
11305 emit_int8((unsigned char)0xDC);
11306 emit_operand32(rcx, src, 0);
11307 }
11308
11309 void Assembler::fmul_s(Address src) {
11310 InstructionMark im(this);
11311 emit_int8((unsigned char)0xD8);
11312 emit_operand32(rcx, src, 0);
11313 }
11314
11315 void Assembler::fmula(int i) {
11316 emit_farith(0xDC, 0xC8, i);
11317 }
11318
11319 void Assembler::fmulp(int i) {
11320 emit_farith(0xDE, 0xC8, i);
11321 }
11322
11323 void Assembler::fnsave(Address dst) {
11324 InstructionMark im(this);
11325 emit_int8((unsigned char)0xDD);
11326 emit_operand32(rsi, dst, 0);
11327 }
11328
11329 void Assembler::fnstcw(Address src) {
11330 InstructionMark im(this);
11331 emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
11332 emit_operand32(rdi, src, 0);
11333 }
11334
11335 void Assembler::fprem1() {
11336 emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
11337 }
11338
11339 void Assembler::frstor(Address src) {
11340 InstructionMark im(this);
11341 emit_int8((unsigned char)0xDD);
11342 emit_operand32(rsp, src, 0);
11343 }
11344
11345 void Assembler::fsin() {
11346 emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
11347 }
11348
11349 void Assembler::fsqrt() {
11350 emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
11351 }
11352
11353 void Assembler::fst_d(Address adr) {
11354 InstructionMark im(this);
11355 emit_int8((unsigned char)0xDD);
11356 emit_operand32(rdx, adr, 0);
11357 }
11358
11359 void Assembler::fst_s(Address adr) {
11360 InstructionMark im(this);
11361 emit_int8((unsigned char)0xD9);
11362 emit_operand32(rdx, adr, 0);
11363 }
11364
11365 void Assembler::fstp_s(Address adr) {
11366 InstructionMark im(this);
11367 emit_int8((unsigned char)0xD9);
11368 emit_operand32(rbx, adr, 0);
11369 }
11370
11371 void Assembler::fsub(int i) {
11372 emit_farith(0xD8, 0xE0, i);
11373 }
11374
11375 void Assembler::fsub_d(Address src) {
11376 InstructionMark im(this);
11377 emit_int8((unsigned char)0xDC);
11378 emit_operand32(rsp, src, 0);
11379 }
11380
11381 void Assembler::fsub_s(Address src) {
11382 InstructionMark im(this);
11383 emit_int8((unsigned char)0xD8);
11384 emit_operand32(rsp, src, 0);
11385 }
11386
11387 void Assembler::fsuba(int i) {
11388 emit_farith(0xDC, 0xE8, i);
11389 }
11390
11391 void Assembler::fsubp(int i) {
11392 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
11393 }
11394
11395 void Assembler::fsubr(int i) {
11396 emit_farith(0xD8, 0xE8, i);
11397 }
11398
11399 void Assembler::fsubr_d(Address src) {
11400 InstructionMark im(this);
11401 emit_int8((unsigned char)0xDC);
11402 emit_operand32(rbp, src, 0);
11403 }
11404
11405 void Assembler::fsubr_s(Address src) {
11406 InstructionMark im(this);
11407 emit_int8((unsigned char)0xD8);
11408 emit_operand32(rbp, src, 0);
11409 }
11410
11411 void Assembler::fsubra(int i) {
11412 emit_farith(0xDC, 0xE0, i);
11413 }
11414
11415 void Assembler::fsubrp(int i) {
11416 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
11417 }
11418
11419 void Assembler::ftan() {
11420 emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
11421 }
11422
11423 void Assembler::ftst() {
11424 emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
11425 }
11426
11427 void Assembler::fucomi(int i) {
11428 // make sure the instruction is supported (introduced for P6, together with cmov)
11429 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11430 emit_farith(0xDB, 0xE8, i);
11431 }
11432
11433 void Assembler::fucomip(int i) {
11434 // make sure the instruction is supported (introduced for P6, together with cmov)
11435 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11436 emit_farith(0xDF, 0xE8, i);
11437 }
11438
11439 void Assembler::fwait() {
11440 emit_int8((unsigned char)0x9B);
11441 }
11442
11443 void Assembler::fxch(int i) {
11444 emit_farith(0xD9, 0xC8, i);
11445 }
11446
11447 void Assembler::fyl2x() {
11448 emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
11449 }
11450
11451 void Assembler::frndint() {
11452 emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
11453 }
11454
11455 void Assembler::f2xm1() {
11456 emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
11457 }
11458
11459 void Assembler::fldl2e() {
11460 emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
11461 }
11462 #endif // !_LP64
11463
11464 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
11465 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
11466 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
11467 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
11468
11469 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
11470 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11471 if (pre > 0) {
11472 emit_int8(simd_pre[pre]);
11473 }
11474 if (rex_w) {
11475 prefixq(adr, xreg);
11476 } else {
11477 prefix(adr, xreg);
11478 }
11479 if (opc > 0) {
11480 emit_int8(0x0F);
11481 int opc2 = simd_opc[opc];
11482 if (opc2 > 0) {
11483 emit_int8(opc2);
11484 }
11485 }
11486 }
11487
11488 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11489 if (pre > 0) {
11490 emit_int8(simd_pre[pre]);
11491 }
11492 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
11493 if (opc > 0) {
11494 emit_int8(0x0F);
11495 int opc2 = simd_opc[opc];
11496 if (opc2 > 0) {
11497 emit_int8(opc2);
11498 }
11499 }
11500 return encode;
11501 }
11502
11503
11504 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
11505 int vector_len = _attributes->get_vector_len();
11506 bool vex_w = _attributes->is_rex_vex_w();
11507 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
11508 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
11509 byte1 = (~byte1) & 0xE0;
11510 byte1 |= opc;
11511
11512 int byte2 = ((~nds_enc) & 0xf) << 3;
11513 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
11514
11515 emit_int24((unsigned char)VEX_3bytes, byte1, byte2);
11516 } else {
11517 int byte1 = vex_r ? VEX_R : 0;
11518 byte1 = (~byte1) & 0x80;
11519 byte1 |= ((~nds_enc) & 0xf) << 3;
11520 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
11521 emit_int16((unsigned char)VEX_2bytes, byte1);
11522 }
11523 }
11524
11525 // This is a 4 byte encoding
11526 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
11527 // EVEX 0x62 prefix
11528 // byte1 = EVEX_4bytes;
11529
11530 bool vex_w = _attributes->is_rex_vex_w();
11531 int evex_encoding = (vex_w ? VEX_W : 0);
11532 // EVEX.b is not currently used for broadcast of single element or data rounding modes
11533 _attributes->set_evex_encoding(evex_encoding);
11534
11535 // P0: byte 2, initialized to RXBR`00mm
11536 // instead of not'd
11537 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
11538 byte2 = (~byte2) & 0xF0;
11539 // confine opc opcode extensions in mm bits to lower two bits
11540 // of form {0F, 0F_38, 0F_3A}
11541 byte2 |= opc;
11542
11543 // P1: byte 3 as Wvvvv1pp
11544 int byte3 = ((~nds_enc) & 0xf) << 3;
11545 // p[10] is always 1
11546 byte3 |= EVEX_F;
11547 byte3 |= (vex_w & 1) << 7;
11548 // confine pre opcode extensions in pp bits to lower two bits
11549 // of form {66, F3, F2}
11550 byte3 |= pre;
11551
11552 // P2: byte 4 as zL'Lbv'aaa
11553 // kregs are implemented in the low 3 bits as aaa
11554 int byte4 = (_attributes->is_no_reg_mask()) ?
11555 0 :
11556 _attributes->get_embedded_opmask_register_specifier();
11557 // EVEX.v` for extending EVEX.vvvv or VIDX
11558 byte4 |= (evex_v ? 0: EVEX_V);
11559 // third EXEC.b for broadcast actions
11560 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
11561 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
11562 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
11563 // last is EVEX.z for zero/merge actions
11564 if (_attributes->is_no_reg_mask() == false &&
11565 _attributes->get_embedded_opmask_register_specifier() != 0) {
11566 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
11567 }
11568
11569 emit_int32(EVEX_4bytes, byte2, byte3, byte4);
11570 }
11571
11572 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11573 bool vex_r = (xreg_enc & 8) == 8;
11574 bool vex_b = adr.base_needs_rex();
11575 bool vex_x;
11576 if (adr.isxmmindex()) {
11577 vex_x = adr.xmmindex_needs_rex();
11578 } else {
11579 vex_x = adr.index_needs_rex();
11580 }
11581 set_attributes(attributes);
11582
11583 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11584 // is allowed in legacy mode and has resources which will fit in it.
11585 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11586 if (!attributes->is_legacy_mode()) {
11587 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11588 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
11589 attributes->set_is_legacy_mode();
11590 }
11591 }
11592 }
11593
11594 if (UseAVX > 2) {
11595 assert(((!attributes->uses_vl()) ||
11596 (attributes->get_vector_len() == AVX_512bit) ||
11597 (!_legacy_mode_vl) ||
11598 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11599 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11600 }
11601
11602 clear_managed();
11603 if (UseAVX > 2 && !attributes->is_legacy_mode())
11604 {
11605 bool evex_r = (xreg_enc >= 16);
11606 bool evex_v;
11607 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
11608 if (adr.isxmmindex()) {
11609 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
11610 } else {
11611 evex_v = (nds_enc >= 16);
11612 }
11613 attributes->set_is_evex_instruction();
11614 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11615 } else {
11616 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11617 attributes->set_rex_vex_w(false);
11618 }
11619 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11620 }
11621 }
11622
11623 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11624 bool vex_r = (dst_enc & 8) == 8;
11625 bool vex_b = (src_enc & 8) == 8;
11626 bool vex_x = false;
11627 set_attributes(attributes);
11628
11629 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11630 // is allowed in legacy mode and has resources which will fit in it.
11631 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11632 if (!attributes->is_legacy_mode()) {
11633 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11634 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
11635 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
11636 attributes->set_is_legacy_mode();
11637 }
11638 }
11639 }
11640
11641 if (UseAVX > 2) {
11642 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
11643 // Instruction with uses_vl true are vector instructions
11644 // All the vector instructions with AVX_512bit length can have legacy_mode as false
11645 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
11646 // Rest all should have legacy_mode set as true
11647 assert(((!attributes->uses_vl()) ||
11648 (attributes->get_vector_len() == AVX_512bit) ||
11649 (!_legacy_mode_vl) ||
11650 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11651 // Instruction with legacy_mode true should have dst, nds and src < 15
11652 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11653 }
11654
11655 clear_managed();
11656 if (UseAVX > 2 && !attributes->is_legacy_mode())
11657 {
11658 bool evex_r = (dst_enc >= 16);
11659 bool evex_v = (nds_enc >= 16);
11660 // can use vex_x as bank extender on rm encoding
11661 vex_x = (src_enc >= 16);
11662 attributes->set_is_evex_instruction();
11663 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11664 } else {
11665 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11666 attributes->set_rex_vex_w(false);
11667 }
11668 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11669 }
11670
11671 // return modrm byte components for operands
11672 return (((dst_enc & 7) << 3) | (src_enc & 7));
11673 }
11674
11675
11676 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
11677 VexOpcode opc, InstructionAttr *attributes) {
11678 if (UseAVX > 0) {
11679 int xreg_enc = xreg->encoding();
11680 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11681 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
11682 } else {
11683 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
11684 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
11685 }
11686 }
11687
11688 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
11689 VexOpcode opc, InstructionAttr *attributes) {
11690 int dst_enc = dst->encoding();
11691 int src_enc = src->encoding();
11692 if (UseAVX > 0) {
11693 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11694 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
11695 } else {
11696 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
11697 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
11698 }
11699 }
11700
11701 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11702 assert(VM_Version::supports_avx(), "");
11703 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11704 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11705 emit_int16(0x5F, (0xC0 | encode));
11706 }
11707
11708 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11709 assert(VM_Version::supports_avx(), "");
11710 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11711 attributes.set_rex_vex_w_reverted();
11712 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11713 emit_int16(0x5F, (0xC0 | encode));
11714 }
11715
11716 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11717 assert(VM_Version::supports_avx(), "");
11718 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11719 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11720 emit_int16(0x5D, (0xC0 | encode));
11721 }
11722
11723 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11724 assert(VM_Version::supports_avx(), "");
11725 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11726 attributes.set_rex_vex_w_reverted();
11727 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11728 emit_int16(0x5D, (0xC0 | encode));
11729 }
11730
11731 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
11732 assert(VM_Version::supports_avx(), "");
11733 assert(vector_len <= AVX_256bit, "");
11734 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11735 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11736 emit_int24((unsigned char)0xC2, (0xC0 | encode), (0xF & cop));
11737 }
11738
11739 void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11740 assert(VM_Version::supports_avx(), "");
11741 assert(vector_len <= AVX_256bit, "");
11742 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11743 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11744 int src2_enc = src2->encoding();
11745 emit_int24(0x4C, (0xC0 | encode), (0xF0 & src2_enc << 4));
11746 }
11747
11748 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11749 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11750 assert(vector_len <= AVX_256bit, "");
11751 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11752 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11753 int src2_enc = src2->encoding();
11754 emit_int24(0x4B, (0xC0 | encode), (0xF0 & src2_enc << 4));
11755 }
11756
11757 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11758 assert(VM_Version::supports_avx2(), "");
11759 assert(vector_len <= AVX_256bit, "");
11760 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11761 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11762 emit_int24(0x02, (0xC0 | encode), (unsigned char)imm8);
11763 }
11764
11765 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
11766 assert(VM_Version::supports_avx(), "");
11767 assert(vector_len <= AVX_256bit, "");
11768 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11769 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11770 emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison);
11771 }
11772
11773 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11774 ComparisonPredicateFP comparison, int vector_len) {
11775 assert(VM_Version::supports_evex(), "");
11776 // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
11777 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11778 attributes.set_is_evex_instruction();
11779 attributes.set_embedded_opmask_register_specifier(mask);
11780 attributes.reset_is_clear_context();
11781 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11782 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11783 }
11784
11785 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11786 ComparisonPredicateFP comparison, int vector_len) {
11787 assert(VM_Version::supports_evex(), "");
11788 // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
11789 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11790 attributes.set_is_evex_instruction();
11791 attributes.set_embedded_opmask_register_specifier(mask);
11792 attributes.reset_is_clear_context();
11793 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11794 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11795 }
11796
11797 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
11798 assert(VM_Version::supports_sse4_1(), "");
11799 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11800 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11801 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11802 emit_int16(0x14, (0xC0 | encode));
11803 }
11804
11805 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
11806 assert(VM_Version::supports_sse4_1(), "");
11807 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11808 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11809 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11810 emit_int16(0x15, (0xC0 | encode));
11811 }
11812
11813 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
11814 assert(VM_Version::supports_sse4_1(), "");
11815 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11816 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11817 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11818 emit_int16(0x10, (0xC0 | encode));
11819 }
11820
11821 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11822 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11823 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11824 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11825 int src2_enc = src2->encoding();
11826 emit_int24(0x4A, (0xC0 | encode), (0xF0 & src2_enc << 4));
11827 }
11828
11829 void Assembler::vblendps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11830 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11831 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11832 emit_int24(0x0C, (0xC0 | encode), imm8);
11833 }
11834
11835 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11836 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11837 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11838 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11839 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11840 emit_int16(0x64, (0xC0 | encode));
11841 }
11842
11843 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11844 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11845 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11846 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11847 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11848 emit_int16(0x65, (0xC0 | encode));
11849 }
11850
11851 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11852 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11853 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11854 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11855 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11856 emit_int16(0x66, (0xC0 | encode));
11857 }
11858
11859 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11860 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11861 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11862 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11863 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11864 emit_int16(0x37, (0xC0 | encode));
11865 }
11866
11867 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11868 int comparison, bool is_signed, int vector_len) {
11869 assert(VM_Version::supports_evex(), "");
11870 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11871 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11872 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11873 attributes.set_is_evex_instruction();
11874 attributes.set_embedded_opmask_register_specifier(mask);
11875 attributes.reset_is_clear_context();
11876 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11877 int opcode = is_signed ? 0x1F : 0x1E;
11878 emit_int24(opcode, (0xC0 | encode), comparison);
11879 }
11880
11881 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11882 int comparison, bool is_signed, int vector_len) {
11883 assert(VM_Version::supports_evex(), "");
11884 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11885 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11886 InstructionMark im(this);
11887 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11888 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11889 attributes.set_is_evex_instruction();
11890 attributes.set_embedded_opmask_register_specifier(mask);
11891 attributes.reset_is_clear_context();
11892 int dst_enc = kdst->encoding();
11893 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11894 int opcode = is_signed ? 0x1F : 0x1E;
11895 emit_int8((unsigned char)opcode);
11896 emit_operand(as_Register(dst_enc), src, 1);
11897 emit_int8((unsigned char)comparison);
11898 }
11899
11900 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11901 int comparison, bool is_signed, int vector_len) {
11902 assert(VM_Version::supports_evex(), "");
11903 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11904 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11905 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11906 attributes.set_is_evex_instruction();
11907 attributes.set_embedded_opmask_register_specifier(mask);
11908 attributes.reset_is_clear_context();
11909 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11910 int opcode = is_signed ? 0x1F : 0x1E;
11911 emit_int24(opcode, (0xC0 | encode), comparison);
11912 }
11913
11914 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11915 int comparison, bool is_signed, int vector_len) {
11916 assert(VM_Version::supports_evex(), "");
11917 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11918 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11919 InstructionMark im(this);
11920 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11921 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11922 attributes.set_is_evex_instruction();
11923 attributes.set_embedded_opmask_register_specifier(mask);
11924 attributes.reset_is_clear_context();
11925 int dst_enc = kdst->encoding();
11926 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11927 int opcode = is_signed ? 0x1F : 0x1E;
11928 emit_int8((unsigned char)opcode);
11929 emit_operand(as_Register(dst_enc), src, 1);
11930 emit_int8((unsigned char)comparison);
11931 }
11932
11933 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11934 int comparison, bool is_signed, int vector_len) {
11935 assert(VM_Version::supports_evex(), "");
11936 assert(VM_Version::supports_avx512bw(), "");
11937 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11938 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11939 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11940 attributes.set_is_evex_instruction();
11941 attributes.set_embedded_opmask_register_specifier(mask);
11942 attributes.reset_is_clear_context();
11943 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11944 int opcode = is_signed ? 0x3F : 0x3E;
11945 emit_int24(opcode, (0xC0 | encode), comparison);
11946 }
11947
11948 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11949 int comparison, bool is_signed, int vector_len) {
11950 assert(VM_Version::supports_evex(), "");
11951 assert(VM_Version::supports_avx512bw(), "");
11952 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11953 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11954 InstructionMark im(this);
11955 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11956 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11957 attributes.set_is_evex_instruction();
11958 attributes.set_embedded_opmask_register_specifier(mask);
11959 attributes.reset_is_clear_context();
11960 int dst_enc = kdst->encoding();
11961 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11962 int opcode = is_signed ? 0x3F : 0x3E;
11963 emit_int8((unsigned char)opcode);
11964 emit_operand(as_Register(dst_enc), src, 1);
11965 emit_int8((unsigned char)comparison);
11966 }
11967
11968 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11969 int comparison, bool is_signed, int vector_len) {
11970 assert(VM_Version::supports_evex(), "");
11971 assert(VM_Version::supports_avx512bw(), "");
11972 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11973 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11974 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11975 attributes.set_is_evex_instruction();
11976 attributes.set_embedded_opmask_register_specifier(mask);
11977 attributes.reset_is_clear_context();
11978 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11979 int opcode = is_signed ? 0x3F : 0x3E;
11980 emit_int24(opcode, (0xC0 | encode), comparison);
11981 }
11982
11983 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11984 int comparison, bool is_signed, int vector_len) {
11985 assert(VM_Version::supports_evex(), "");
11986 assert(VM_Version::supports_avx512bw(), "");
11987 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11988 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11989 InstructionMark im(this);
11990 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11991 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11992 attributes.set_is_evex_instruction();
11993 attributes.set_embedded_opmask_register_specifier(mask);
11994 attributes.reset_is_clear_context();
11995 int dst_enc = kdst->encoding();
11996 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11997 int opcode = is_signed ? 0x3F : 0x3E;
11998 emit_int8((unsigned char)opcode);
11999 emit_operand(as_Register(dst_enc), src, 1);
12000 emit_int8((unsigned char)comparison);
12001 }
12002
12003 void Assembler::evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12004 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12005 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12006 attributes.set_is_evex_instruction();
12007 attributes.set_embedded_opmask_register_specifier(mask);
12008 if (merge) {
12009 attributes.reset_is_clear_context();
12010 }
12011 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12012 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12013 }
12014
12015 void Assembler::evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12016 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12017 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12018 attributes.set_is_evex_instruction();
12019 attributes.set_embedded_opmask_register_specifier(mask);
12020 if (merge) {
12021 attributes.reset_is_clear_context();
12022 }
12023 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12024 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12025 }
12026
12027 void Assembler::evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12028 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12029 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12030 attributes.set_is_evex_instruction();
12031 attributes.set_embedded_opmask_register_specifier(mask);
12032 if (merge) {
12033 attributes.reset_is_clear_context();
12034 }
12035 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12036 emit_int16(0x14, (0xC0 | encode));
12037 }
12038
12039 void Assembler::evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12040 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12041 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12042 attributes.set_is_evex_instruction();
12043 attributes.set_embedded_opmask_register_specifier(mask);
12044 if (merge) {
12045 attributes.reset_is_clear_context();
12046 }
12047 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12048 emit_int16(0x14, (0xC0 | encode));
12049 }
12050
12051 void Assembler::evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12052 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12053 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12054 attributes.set_is_evex_instruction();
12055 attributes.set_embedded_opmask_register_specifier(mask);
12056 if (merge) {
12057 attributes.reset_is_clear_context();
12058 }
12059 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12060 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12061 }
12062
12063 void Assembler::evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12064 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12065 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12066 attributes.set_is_evex_instruction();
12067 attributes.set_embedded_opmask_register_specifier(mask);
12068 if (merge) {
12069 attributes.reset_is_clear_context();
12070 }
12071 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12072 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12073 }
12074
12075 void Assembler::evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12076 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12077 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12078 attributes.set_is_evex_instruction();
12079 attributes.set_embedded_opmask_register_specifier(mask);
12080 if (merge) {
12081 attributes.reset_is_clear_context();
12082 }
12083 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12084 emit_int16(0x15, (0xC0 | encode));
12085 }
12086
12087 void Assembler::evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12088 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12089 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12090 attributes.set_is_evex_instruction();
12091 attributes.set_embedded_opmask_register_specifier(mask);
12092 if (merge) {
12093 attributes.reset_is_clear_context();
12094 }
12095 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12096 emit_int16(0x15, (0xC0 | encode));
12097 }
12098
12099 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
12100 assert(VM_Version::supports_avx(), "");
12101 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12102 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
12103 int mask_enc = mask->encoding();
12104 emit_int24(0x4C, (0xC0 | encode), 0xF0 & mask_enc << 4);
12105 }
12106
12107 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12108 assert(VM_Version::supports_evex(), "");
12109 // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
12110 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12111 attributes.set_is_evex_instruction();
12112 attributes.set_embedded_opmask_register_specifier(mask);
12113 if (merge) {
12114 attributes.reset_is_clear_context();
12115 }
12116 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12117 emit_int16(0x65, (0xC0 | encode));
12118 }
12119
12120 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12121 assert(VM_Version::supports_evex(), "");
12122 // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
12123 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12124 attributes.set_is_evex_instruction();
12125 attributes.set_embedded_opmask_register_specifier(mask);
12126 if (merge) {
12127 attributes.reset_is_clear_context();
12128 }
12129 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12130 emit_int16(0x65, (0xC0 | encode));
12131 }
12132
12133 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12134 assert(VM_Version::supports_evex(), "");
12135 assert(VM_Version::supports_avx512bw(), "");
12136 // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
12137 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12138 attributes.set_is_evex_instruction();
12139 attributes.set_embedded_opmask_register_specifier(mask);
12140 if (merge) {
12141 attributes.reset_is_clear_context();
12142 }
12143 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12144 emit_int16(0x66, (0xC0 | encode));
12145 }
12146
12147 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12148 assert(VM_Version::supports_evex(), "");
12149 assert(VM_Version::supports_avx512bw(), "");
12150 // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
12151 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12152 attributes.set_is_evex_instruction();
12153 attributes.set_embedded_opmask_register_specifier(mask);
12154 if (merge) {
12155 attributes.reset_is_clear_context();
12156 }
12157 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12158 emit_int16(0x66, (0xC0 | encode));
12159 }
12160
12161 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12162 assert(VM_Version::supports_evex(), "");
12163 //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
12164 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12165 attributes.set_is_evex_instruction();
12166 attributes.set_embedded_opmask_register_specifier(mask);
12167 if (merge) {
12168 attributes.reset_is_clear_context();
12169 }
12170 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12171 emit_int16(0x64, (0xC0 | encode));
12172 }
12173
12174 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12175 assert(VM_Version::supports_evex(), "");
12176 //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
12177 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12178 attributes.set_is_evex_instruction();
12179 attributes.set_embedded_opmask_register_specifier(mask);
12180 if (merge) {
12181 attributes.reset_is_clear_context();
12182 }
12183 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12184 emit_int16(0x64, (0xC0 | encode));
12185 }
12186
12187 void Assembler::bzhiq(Register dst, Register src1, Register src2) {
12188 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12189 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12190 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12191 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12192 }
12193
12194 void Assembler::pextl(Register dst, Register src1, Register src2) {
12195 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12196 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12197 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12198 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12199 }
12200
12201 void Assembler::pdepl(Register dst, Register src1, Register src2) {
12202 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12203 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12204 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12205 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12206 }
12207
12208 void Assembler::pextq(Register dst, Register src1, Register src2) {
12209 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12210 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12211 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12212 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12213 }
12214
12215 void Assembler::pdepq(Register dst, Register src1, Register src2) {
12216 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12217 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12218 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12219 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12220 }
12221
12222 void Assembler::pextl(Register dst, Register src1, Address src2) {
12223 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12224 InstructionMark im(this);
12225 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12226 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12227 emit_int8((unsigned char)0xF5);
12228 emit_operand(dst, src2, 0);
12229 }
12230
12231 void Assembler::pdepl(Register dst, Register src1, Address src2) {
12232 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12233 InstructionMark im(this);
12234 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12235 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12236 emit_int8((unsigned char)0xF5);
12237 emit_operand(dst, src2, 0);
12238 }
12239
12240 void Assembler::pextq(Register dst, Register src1, Address src2) {
12241 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12242 InstructionMark im(this);
12243 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12244 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12245 emit_int8((unsigned char)0xF5);
12246 emit_operand(dst, src2, 0);
12247 }
12248
12249 void Assembler::pdepq(Register dst, Register src1, Address src2) {
12250 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12251 InstructionMark im(this);
12252 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12253 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12254 emit_int8((unsigned char)0xF5);
12255 emit_operand(dst, src2, 0);
12256 }
12257
12258 void Assembler::sarxl(Register dst, Register src1, Register src2) {
12259 assert(VM_Version::supports_bmi2(), "");
12260 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12261 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12262 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12263 }
12264
12265 void Assembler::sarxl(Register dst, Address src1, Register src2) {
12266 assert(VM_Version::supports_bmi2(), "");
12267 InstructionMark im(this);
12268 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12269 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12270 emit_int8((unsigned char)0xF7);
12271 emit_operand(dst, src1, 0);
12272 }
12273
12274 void Assembler::sarxq(Register dst, Register src1, Register src2) {
12275 assert(VM_Version::supports_bmi2(), "");
12276 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12277 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12278 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12279 }
12280
12281 void Assembler::sarxq(Register dst, Address src1, Register src2) {
12282 assert(VM_Version::supports_bmi2(), "");
12283 InstructionMark im(this);
12284 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12285 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12286 emit_int8((unsigned char)0xF7);
12287 emit_operand(dst, src1, 0);
12288 }
12289
12290 void Assembler::shlxl(Register dst, Register src1, Register src2) {
12291 assert(VM_Version::supports_bmi2(), "");
12292 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12293 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12294 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12295 }
12296
12297 void Assembler::shlxl(Register dst, Address src1, Register src2) {
12298 assert(VM_Version::supports_bmi2(), "");
12299 InstructionMark im(this);
12300 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12301 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12302 emit_int8((unsigned char)0xF7);
12303 emit_operand(dst, src1, 0);
12304 }
12305
12306 void Assembler::shlxq(Register dst, Register src1, Register src2) {
12307 assert(VM_Version::supports_bmi2(), "");
12308 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12309 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12310 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12311 }
12312
12313 void Assembler::shlxq(Register dst, Address src1, Register src2) {
12314 assert(VM_Version::supports_bmi2(), "");
12315 InstructionMark im(this);
12316 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12317 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12318 emit_int8((unsigned char)0xF7);
12319 emit_operand(dst, src1, 0);
12320 }
12321
12322 void Assembler::shrxl(Register dst, Register src1, Register src2) {
12323 assert(VM_Version::supports_bmi2(), "");
12324 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12325 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12326 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12327 }
12328
12329 void Assembler::shrxl(Register dst, Address src1, Register src2) {
12330 assert(VM_Version::supports_bmi2(), "");
12331 InstructionMark im(this);
12332 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12333 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12334 emit_int8((unsigned char)0xF7);
12335 emit_operand(dst, src1, 0);
12336 }
12337
12338 void Assembler::shrxq(Register dst, Register src1, Register src2) {
12339 assert(VM_Version::supports_bmi2(), "");
12340 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12341 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12342 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12343 }
12344
12345 void Assembler::shrxq(Register dst, Address src1, Register src2) {
12346 assert(VM_Version::supports_bmi2(), "");
12347 InstructionMark im(this);
12348 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12349 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12350 emit_int8((unsigned char)0xF7);
12351 emit_operand(dst, src1, 0);
12352 }
12353
12354 void Assembler::evpmovq2m(KRegister dst, XMMRegister src, int vector_len) {
12355 assert(VM_Version::supports_avx512vldq(), "");
12356 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12357 attributes.set_is_evex_instruction();
12358 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12359 emit_int16(0x39, (0xC0 | encode));
12360 }
12361
12362 void Assembler::evpmovd2m(KRegister dst, XMMRegister src, int vector_len) {
12363 assert(VM_Version::supports_avx512vldq(), "");
12364 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12365 attributes.set_is_evex_instruction();
12366 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12367 emit_int16(0x39, (0xC0 | encode));
12368 }
12369
12370 void Assembler::evpmovw2m(KRegister dst, XMMRegister src, int vector_len) {
12371 assert(VM_Version::supports_avx512vlbw(), "");
12372 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12373 attributes.set_is_evex_instruction();
12374 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12375 emit_int16(0x29, (0xC0 | encode));
12376 }
12377
12378 void Assembler::evpmovb2m(KRegister dst, XMMRegister src, int vector_len) {
12379 assert(VM_Version::supports_avx512vlbw(), "");
12380 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12381 attributes.set_is_evex_instruction();
12382 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12383 emit_int16(0x29, (0xC0 | encode));
12384 }
12385
12386 void Assembler::evpmovm2q(XMMRegister dst, KRegister src, int vector_len) {
12387 assert(VM_Version::supports_avx512vldq(), "");
12388 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12389 attributes.set_is_evex_instruction();
12390 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12391 emit_int16(0x38, (0xC0 | encode));
12392 }
12393
12394 void Assembler::evpmovm2d(XMMRegister dst, KRegister src, int vector_len) {
12395 assert(VM_Version::supports_avx512vldq(), "");
12396 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12397 attributes.set_is_evex_instruction();
12398 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12399 emit_int16(0x38, (0xC0 | encode));
12400 }
12401
12402 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
12403 assert(VM_Version::supports_avx512vlbw(), "");
12404 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12405 attributes.set_is_evex_instruction();
12406 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12407 emit_int16(0x28, (0xC0 | encode));
12408 }
12409
12410 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
12411 assert(VM_Version::supports_avx512vlbw(), "");
12412 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12413 attributes.set_is_evex_instruction();
12414 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12415 emit_int16(0x28, (0xC0 | encode));
12416 }
12417
12418 void Assembler::evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12419 assert(VM_Version::supports_avx512_vbmi2(), "");
12420 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12421 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12422 attributes.set_embedded_opmask_register_specifier(mask);
12423 attributes.set_is_evex_instruction();
12424 if (merge) {
12425 attributes.reset_is_clear_context();
12426 }
12427 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12428 emit_int16((unsigned char)0x63, (0xC0 | encode));
12429 }
12430
12431 void Assembler::evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12432 assert(VM_Version::supports_avx512_vbmi2(), "");
12433 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12434 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12435 attributes.set_embedded_opmask_register_specifier(mask);
12436 attributes.set_is_evex_instruction();
12437 if (merge) {
12438 attributes.reset_is_clear_context();
12439 }
12440 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12441 emit_int16((unsigned char)0x63, (0xC0 | encode));
12442 }
12443
12444 void Assembler::evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12445 assert(VM_Version::supports_evex(), "");
12446 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12448 attributes.set_embedded_opmask_register_specifier(mask);
12449 attributes.set_is_evex_instruction();
12450 if (merge) {
12451 attributes.reset_is_clear_context();
12452 }
12453 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12454 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12455 }
12456
12457 void Assembler::evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12458 assert(VM_Version::supports_evex(), "");
12459 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12460 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12461 attributes.set_embedded_opmask_register_specifier(mask);
12462 attributes.set_is_evex_instruction();
12463 if (merge) {
12464 attributes.reset_is_clear_context();
12465 }
12466 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12467 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12468 }
12469
12470 void Assembler::evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12471 assert(VM_Version::supports_evex(), "");
12472 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12473 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12474 attributes.set_embedded_opmask_register_specifier(mask);
12475 attributes.set_is_evex_instruction();
12476 if (merge) {
12477 attributes.reset_is_clear_context();
12478 }
12479 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12480 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12481 }
12482
12483 void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12484 assert(VM_Version::supports_evex(), "");
12485 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12486 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12487 attributes.set_embedded_opmask_register_specifier(mask);
12488 attributes.set_is_evex_instruction();
12489 if (merge) {
12490 attributes.reset_is_clear_context();
12491 }
12492 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12493 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12494 }
12495
12496 #ifndef _LP64
12497
12498 void Assembler::incl(Register dst) {
12499 // Don't use it directly. Use MacroAssembler::incrementl() instead.
12500 emit_int8(0x40 | dst->encoding());
12501 }
12502
12503 void Assembler::lea(Register dst, Address src) {
12504 leal(dst, src);
12505 }
12506
12507 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
12508 InstructionMark im(this);
12509 emit_int8((unsigned char)0xC7);
12510 emit_operand(rax, dst, 4);
12511 emit_data((int)imm32, rspec, 0);
12512 }
12513
12514 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
12515 InstructionMark im(this);
12516 int encode = prefix_and_encode(dst->encoding());
12517 emit_int8((0xB8 | encode));
12518 emit_data((int)imm32, rspec, 0);
12519 }
12520
12521 void Assembler::popa() { // 32bit
12522 emit_int8(0x61);
12523 }
12524
12525 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
12526 InstructionMark im(this);
12527 emit_int8(0x68);
12528 emit_data(imm32, rspec, 0);
12529 }
12530
12531 void Assembler::pusha() { // 32bit
12532 emit_int8(0x60);
12533 }
12534
12535 #else // LP64
12536
12537 // 64bit only pieces of the assembler
12538
12539 // This should only be used by 64bit instructions that can use rip-relative
12540 // it cannot be used by instructions that want an immediate value.
12541
12542 // Determine whether an address is always reachable in rip-relative addressing mode
12543 // when accessed from the code cache.
12544 static bool is_always_reachable(address target, relocInfo::relocType reloc_type) {
12545 switch (reloc_type) {
12546 // This should be rip-relative and easily reachable.
12547 case relocInfo::internal_word_type: {
12548 return true;
12549 }
12550 // This should be rip-relative within the code cache and easily
12551 // reachable until we get huge code caches. (At which point
12552 // IC code is going to have issues).
12553 case relocInfo::virtual_call_type:
12554 case relocInfo::opt_virtual_call_type:
12555 case relocInfo::static_call_type:
12556 case relocInfo::static_stub_type: {
12557 return true;
12558 }
12559 case relocInfo::runtime_call_type:
12560 case relocInfo::external_word_type:
12561 case relocInfo::poll_return_type: // these are really external_word but need special
12562 case relocInfo::poll_type: { // relocs to identify them
12563 return CodeCache::contains(target);
12564 }
12565 default: {
12566 return false;
12567 }
12568 }
12569 }
12570
12571 // Determine whether an address is reachable in rip-relative addressing mode from the code cache.
12572 static bool is_reachable(address target, relocInfo::relocType reloc_type) {
12573 if (is_always_reachable(target, reloc_type)) {
12574 return true;
12575 }
12576 switch (reloc_type) {
12577 // None will force a 64bit literal to the code stream. Likely a placeholder
12578 // for something that will be patched later and we need to certain it will
12579 // always be reachable.
12580 case relocInfo::none: {
12581 return false;
12582 }
12583 case relocInfo::runtime_call_type:
12584 case relocInfo::external_word_type:
12585 case relocInfo::poll_return_type: // these are really external_word but need special
12586 case relocInfo::poll_type: { // relocs to identify them
12587 assert(!CodeCache::contains(target), "always reachable");
12588 if (ForceUnreachable) {
12589 return false; // stress the correction code
12590 }
12591 // For external_word_type/runtime_call_type if it is reachable from where we
12592 // are now (possibly a temp buffer) and where we might end up
12593 // anywhere in the code cache then we are always reachable.
12594 // This would have to change if we ever save/restore shared code to be more pessimistic.
12595 // Code buffer has to be allocated in the code cache, so check against
12596 // code cache boundaries cover that case.
12597 //
12598 // In rip-relative addressing mode, an effective address is formed by adding displacement
12599 // to the 64-bit RIP of the next instruction which is not known yet. Considering target address
12600 // is guaranteed to be outside of the code cache, checking against code cache boundaries is enough
12601 // to account for that.
12602 return Assembler::is_simm32(target - CodeCache::low_bound()) &&
12603 Assembler::is_simm32(target - CodeCache::high_bound());
12604 }
12605 default: {
12606 return false;
12607 }
12608 }
12609 }
12610
12611 bool Assembler::reachable(AddressLiteral adr) {
12612 assert(CodeCache::contains(pc()), "required");
12613 if (adr.is_lval()) {
12614 return false;
12615 }
12616 return is_reachable(adr.target(), adr.reloc());
12617 }
12618
12619 bool Assembler::always_reachable(AddressLiteral adr) {
12620 assert(CodeCache::contains(pc()), "required");
12621 if (adr.is_lval()) {
12622 return false;
12623 }
12624 return is_always_reachable(adr.target(), adr.reloc());
12625 }
12626
12627 void Assembler::emit_data64(jlong data,
12628 relocInfo::relocType rtype,
12629 int format) {
12630 if (rtype == relocInfo::none) {
12631 emit_int64(data);
12632 } else {
12633 emit_data64(data, Relocation::spec_simple(rtype), format);
12634 }
12635 }
12636
12637 void Assembler::emit_data64(jlong data,
12638 RelocationHolder const& rspec,
12639 int format) {
12640 assert(imm_operand == 0, "default format must be immediate in this file");
12641 assert(imm_operand == format, "must be immediate");
12642 assert(inst_mark() != nullptr, "must be inside InstructionMark");
12643 // Do not use AbstractAssembler::relocate, which is not intended for
12644 // embedded words. Instead, relocate to the enclosing instruction.
12645 code_section()->relocate(inst_mark(), rspec, format);
12646 #ifdef ASSERT
12647 check_relocation(rspec, format);
12648 #endif
12649 emit_int64(data);
12650 }
12651
12652 void Assembler::prefix(Register reg) {
12653 if (reg->encoding() >= 8) {
12654 prefix(REX_B);
12655 }
12656 }
12657
12658 void Assembler::prefix(Register dst, Register src, Prefix p) {
12659 if (src->encoding() >= 8) {
12660 p = (Prefix)(p | REX_B);
12661 }
12662 if (dst->encoding() >= 8) {
12663 p = (Prefix)(p | REX_R);
12664 }
12665 if (p != Prefix_EMPTY) {
12666 // do not generate an empty prefix
12667 prefix(p);
12668 }
12669 }
12670
12671 void Assembler::prefix(Register dst, Address adr, Prefix p) {
12672 if (adr.base_needs_rex()) {
12673 if (adr.index_needs_rex()) {
12674 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12675 } else {
12676 p = (Prefix)(p | REX_B);
12677 }
12678 } else {
12679 if (adr.index_needs_rex()) {
12680 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12681 }
12682 }
12683 if (dst->encoding() >= 8) {
12684 p = (Prefix)(p | REX_R);
12685 }
12686 if (p != Prefix_EMPTY) {
12687 // do not generate an empty prefix
12688 prefix(p);
12689 }
12690 }
12691
12692 void Assembler::prefix(Address adr) {
12693 if (adr.base_needs_rex()) {
12694 if (adr.index_needs_rex()) {
12695 prefix(REX_XB);
12696 } else {
12697 prefix(REX_B);
12698 }
12699 } else {
12700 if (adr.index_needs_rex()) {
12701 prefix(REX_X);
12702 }
12703 }
12704 }
12705
12706 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
12707 if (reg->encoding() < 8) {
12708 if (adr.base_needs_rex()) {
12709 if (adr.index_needs_rex()) {
12710 prefix(REX_XB);
12711 } else {
12712 prefix(REX_B);
12713 }
12714 } else {
12715 if (adr.index_needs_rex()) {
12716 prefix(REX_X);
12717 } else if (byteinst && reg->encoding() >= 4) {
12718 prefix(REX);
12719 }
12720 }
12721 } else {
12722 if (adr.base_needs_rex()) {
12723 if (adr.index_needs_rex()) {
12724 prefix(REX_RXB);
12725 } else {
12726 prefix(REX_RB);
12727 }
12728 } else {
12729 if (adr.index_needs_rex()) {
12730 prefix(REX_RX);
12731 } else {
12732 prefix(REX_R);
12733 }
12734 }
12735 }
12736 }
12737
12738 void Assembler::prefix(Address adr, XMMRegister reg) {
12739 if (reg->encoding() < 8) {
12740 if (adr.base_needs_rex()) {
12741 if (adr.index_needs_rex()) {
12742 prefix(REX_XB);
12743 } else {
12744 prefix(REX_B);
12745 }
12746 } else {
12747 if (adr.index_needs_rex()) {
12748 prefix(REX_X);
12749 }
12750 }
12751 } else {
12752 if (adr.base_needs_rex()) {
12753 if (adr.index_needs_rex()) {
12754 prefix(REX_RXB);
12755 } else {
12756 prefix(REX_RB);
12757 }
12758 } else {
12759 if (adr.index_needs_rex()) {
12760 prefix(REX_RX);
12761 } else {
12762 prefix(REX_R);
12763 }
12764 }
12765 }
12766 }
12767
12768 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
12769 if (reg_enc >= 8) {
12770 prefix(REX_B);
12771 reg_enc -= 8;
12772 } else if (byteinst && reg_enc >= 4) {
12773 prefix(REX);
12774 }
12775 return reg_enc;
12776 }
12777
12778 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
12779 if (dst_enc < 8) {
12780 if (src_enc >= 8) {
12781 prefix(REX_B);
12782 src_enc -= 8;
12783 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
12784 prefix(REX);
12785 }
12786 } else {
12787 if (src_enc < 8) {
12788 prefix(REX_R);
12789 } else {
12790 prefix(REX_RB);
12791 src_enc -= 8;
12792 }
12793 dst_enc -= 8;
12794 }
12795 return dst_enc << 3 | src_enc;
12796 }
12797
12798 int8_t Assembler::get_prefixq(Address adr) {
12799 int8_t prfx = get_prefixq(adr, rax);
12800 assert(REX_W <= prfx && prfx <= REX_WXB, "must be");
12801 return prfx;
12802 }
12803
12804 int8_t Assembler::get_prefixq(Address adr, Register src) {
12805 int8_t prfx = (int8_t)(REX_W +
12806 ((int)adr.base_needs_rex()) +
12807 ((int)adr.index_needs_rex() << 1) +
12808 ((int)(src->encoding() >= 8) << 2));
12809 #ifdef ASSERT
12810 if (src->encoding() < 8) {
12811 if (adr.base_needs_rex()) {
12812 if (adr.index_needs_rex()) {
12813 assert(prfx == REX_WXB, "must be");
12814 } else {
12815 assert(prfx == REX_WB, "must be");
12816 }
12817 } else {
12818 if (adr.index_needs_rex()) {
12819 assert(prfx == REX_WX, "must be");
12820 } else {
12821 assert(prfx == REX_W, "must be");
12822 }
12823 }
12824 } else {
12825 if (adr.base_needs_rex()) {
12826 if (adr.index_needs_rex()) {
12827 assert(prfx == REX_WRXB, "must be");
12828 } else {
12829 assert(prfx == REX_WRB, "must be");
12830 }
12831 } else {
12832 if (adr.index_needs_rex()) {
12833 assert(prfx == REX_WRX, "must be");
12834 } else {
12835 assert(prfx == REX_WR, "must be");
12836 }
12837 }
12838 }
12839 #endif
12840 return prfx;
12841 }
12842
12843 void Assembler::prefixq(Address adr) {
12844 emit_int8(get_prefixq(adr));
12845 }
12846
12847 void Assembler::prefixq(Address adr, Register src) {
12848 emit_int8(get_prefixq(adr, src));
12849 }
12850
12851 void Assembler::prefixq(Address adr, XMMRegister src) {
12852 if (src->encoding() < 8) {
12853 if (adr.base_needs_rex()) {
12854 if (adr.index_needs_rex()) {
12855 prefix(REX_WXB);
12856 } else {
12857 prefix(REX_WB);
12858 }
12859 } else {
12860 if (adr.index_needs_rex()) {
12861 prefix(REX_WX);
12862 } else {
12863 prefix(REX_W);
12864 }
12865 }
12866 } else {
12867 if (adr.base_needs_rex()) {
12868 if (adr.index_needs_rex()) {
12869 prefix(REX_WRXB);
12870 } else {
12871 prefix(REX_WRB);
12872 }
12873 } else {
12874 if (adr.index_needs_rex()) {
12875 prefix(REX_WRX);
12876 } else {
12877 prefix(REX_WR);
12878 }
12879 }
12880 }
12881 }
12882
12883 int Assembler::prefixq_and_encode(int reg_enc) {
12884 if (reg_enc < 8) {
12885 prefix(REX_W);
12886 } else {
12887 prefix(REX_WB);
12888 reg_enc -= 8;
12889 }
12890 return reg_enc;
12891 }
12892
12893 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
12894 if (dst_enc < 8) {
12895 if (src_enc < 8) {
12896 prefix(REX_W);
12897 } else {
12898 prefix(REX_WB);
12899 src_enc -= 8;
12900 }
12901 } else {
12902 if (src_enc < 8) {
12903 prefix(REX_WR);
12904 } else {
12905 prefix(REX_WRB);
12906 src_enc -= 8;
12907 }
12908 dst_enc -= 8;
12909 }
12910 return dst_enc << 3 | src_enc;
12911 }
12912
12913 void Assembler::adcq(Register dst, int32_t imm32) {
12914 (void) prefixq_and_encode(dst->encoding());
12915 emit_arith(0x81, 0xD0, dst, imm32);
12916 }
12917
12918 void Assembler::adcq(Register dst, Address src) {
12919 InstructionMark im(this);
12920 emit_int16(get_prefixq(src, dst), 0x13);
12921 emit_operand(dst, src, 0);
12922 }
12923
12924 void Assembler::adcq(Register dst, Register src) {
12925 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12926 emit_arith(0x13, 0xC0, dst, src);
12927 }
12928
12929 void Assembler::addq(Address dst, int32_t imm32) {
12930 InstructionMark im(this);
12931 prefixq(dst);
12932 emit_arith_operand(0x81, rax, dst, imm32);
12933 }
12934
12935 void Assembler::addq(Address dst, Register src) {
12936 InstructionMark im(this);
12937 emit_int16(get_prefixq(dst, src), 0x01);
12938 emit_operand(src, dst, 0);
12939 }
12940
12941 void Assembler::addq(Register dst, int32_t imm32) {
12942 (void) prefixq_and_encode(dst->encoding());
12943 emit_arith(0x81, 0xC0, dst, imm32);
12944 }
12945
12946 void Assembler::addq(Register dst, Address src) {
12947 InstructionMark im(this);
12948 emit_int16(get_prefixq(src, dst), 0x03);
12949 emit_operand(dst, src, 0);
12950 }
12951
12952 void Assembler::addq(Register dst, Register src) {
12953 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12954 emit_arith(0x03, 0xC0, dst, src);
12955 }
12956
12957 void Assembler::adcxq(Register dst, Register src) {
12958 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12959 emit_int8(0x66);
12960 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12961 emit_int32(0x0F,
12962 0x38,
12963 (unsigned char)0xF6,
12964 (0xC0 | encode));
12965 }
12966
12967 void Assembler::adoxq(Register dst, Register src) {
12968 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12969 emit_int8((unsigned char)0xF3);
12970 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12971 emit_int32(0x0F,
12972 0x38,
12973 (unsigned char)0xF6,
12974 (0xC0 | encode));
12975 }
12976
12977 void Assembler::andq(Address dst, int32_t imm32) {
12978 InstructionMark im(this);
12979 prefixq(dst);
12980 emit_arith_operand(0x81, as_Register(4), dst, imm32);
12981 }
12982
12983 void Assembler::andq(Register dst, int32_t imm32) {
12984 (void) prefixq_and_encode(dst->encoding());
12985 emit_arith(0x81, 0xE0, dst, imm32);
12986 }
12987
12988 void Assembler::andq(Register dst, Address src) {
12989 InstructionMark im(this);
12990 emit_int16(get_prefixq(src, dst), 0x23);
12991 emit_operand(dst, src, 0);
12992 }
12993
12994 void Assembler::andq(Register dst, Register src) {
12995 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12996 emit_arith(0x23, 0xC0, dst, src);
12997 }
12998
12999 void Assembler::andq(Address dst, Register src) {
13000 InstructionMark im(this);
13001 emit_int16(get_prefixq(dst, src), 0x21);
13002 emit_operand(src, dst, 0);
13003 }
13004
13005 void Assembler::andnq(Register dst, Register src1, Register src2) {
13006 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13007 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13008 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13009 emit_int16((unsigned char)0xF2, (0xC0 | encode));
13010 }
13011
13012 void Assembler::andnq(Register dst, Register src1, Address src2) {
13013 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13014 InstructionMark im(this);
13015 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13016 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13017 emit_int8((unsigned char)0xF2);
13018 emit_operand(dst, src2, 0);
13019 }
13020
13021 void Assembler::bsfq(Register dst, Register src) {
13022 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13023 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
13024 }
13025
13026 void Assembler::bsrq(Register dst, Register src) {
13027 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13028 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
13029 }
13030
13031 void Assembler::bswapq(Register reg) {
13032 int encode = prefixq_and_encode(reg->encoding());
13033 emit_int16(0x0F, (0xC8 | encode));
13034 }
13035
13036 void Assembler::blsiq(Register dst, Register src) {
13037 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13038 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13039 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13040 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13041 }
13042
13043 void Assembler::blsiq(Register dst, Address src) {
13044 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13045 InstructionMark im(this);
13046 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13047 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13048 emit_int8((unsigned char)0xF3);
13049 emit_operand(rbx, src, 0);
13050 }
13051
13052 void Assembler::blsmskq(Register dst, Register src) {
13053 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13054 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13055 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13056 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13057 }
13058
13059 void Assembler::blsmskq(Register dst, Address src) {
13060 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13061 InstructionMark im(this);
13062 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13063 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13064 emit_int8((unsigned char)0xF3);
13065 emit_operand(rdx, src, 0);
13066 }
13067
13068 void Assembler::blsrq(Register dst, Register src) {
13069 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13070 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13071 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13072 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13073 }
13074
13075 void Assembler::blsrq(Register dst, Address src) {
13076 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13077 InstructionMark im(this);
13078 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13079 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13080 emit_int8((unsigned char)0xF3);
13081 emit_operand(rcx, src, 0);
13082 }
13083
13084 void Assembler::cdqq() {
13085 emit_int16(REX_W, (unsigned char)0x99);
13086 }
13087
13088 void Assembler::clflush(Address adr) {
13089 assert(VM_Version::supports_clflush(), "should do");
13090 prefix(adr);
13091 emit_int16(0x0F, (unsigned char)0xAE);
13092 emit_operand(rdi, adr, 0);
13093 }
13094
13095 void Assembler::clflushopt(Address adr) {
13096 assert(VM_Version::supports_clflushopt(), "should do!");
13097 // adr should be base reg only with no index or offset
13098 assert(adr.index() == noreg, "index should be noreg");
13099 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13100 assert(adr.disp() == 0, "displacement should be 0");
13101 // instruction prefix is 0x66
13102 emit_int8(0x66);
13103 prefix(adr);
13104 // opcode family is 0x0F 0xAE
13105 emit_int16(0x0F, (unsigned char)0xAE);
13106 // extended opcode byte is 7 == rdi
13107 emit_operand(rdi, adr, 0);
13108 }
13109
13110 void Assembler::clwb(Address adr) {
13111 assert(VM_Version::supports_clwb(), "should do!");
13112 // adr should be base reg only with no index or offset
13113 assert(adr.index() == noreg, "index should be noreg");
13114 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13115 assert(adr.disp() == 0, "displacement should be 0");
13116 // instruction prefix is 0x66
13117 emit_int8(0x66);
13118 prefix(adr);
13119 // opcode family is 0x0f 0xAE
13120 emit_int16(0x0F, (unsigned char)0xAE);
13121 // extended opcode byte is 6 == rsi
13122 emit_operand(rsi, adr, 0);
13123 }
13124
13125 void Assembler::cmovq(Condition cc, Register dst, Register src) {
13126 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13127 emit_int24(0x0F, (0x40 | cc), (0xC0 | encode));
13128 }
13129
13130 void Assembler::cmovq(Condition cc, Register dst, Address src) {
13131 InstructionMark im(this);
13132 emit_int24(get_prefixq(src, dst), 0x0F, (0x40 | cc));
13133 emit_operand(dst, src, 0);
13134 }
13135
13136 void Assembler::cmpq(Address dst, int32_t imm32) {
13137 InstructionMark im(this);
13138 prefixq(dst);
13139 emit_arith_operand(0x81, as_Register(7), dst, imm32);
13140 }
13141
13142 void Assembler::cmpq(Register dst, int32_t imm32) {
13143 (void) prefixq_and_encode(dst->encoding());
13144 emit_arith(0x81, 0xF8, dst, imm32);
13145 }
13146
13147 void Assembler::cmpq(Address dst, Register src) {
13148 InstructionMark im(this);
13149 emit_int16(get_prefixq(dst, src), 0x39);
13150 emit_operand(src, dst, 0);
13151 }
13152
13153 void Assembler::cmpq(Register dst, Register src) {
13154 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13155 emit_arith(0x3B, 0xC0, dst, src);
13156 }
13157
13158 void Assembler::cmpq(Register dst, Address src) {
13159 InstructionMark im(this);
13160 emit_int16(get_prefixq(src, dst), 0x3B);
13161 emit_operand(dst, src, 0);
13162 }
13163
13164 void Assembler::cmpxchgq(Register reg, Address adr) {
13165 InstructionMark im(this);
13166 emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1);
13167 emit_operand(reg, adr, 0);
13168 }
13169
13170 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
13171 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13172 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13173 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13174 emit_int16(0x2A, (0xC0 | encode));
13175 }
13176
13177 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
13178 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13179 InstructionMark im(this);
13180 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13181 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13182 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13183 emit_int8(0x2A);
13184 emit_operand(dst, src, 0);
13185 }
13186
13187 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
13188 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13189 InstructionMark im(this);
13190 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13191 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13192 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13193 emit_int8(0x2A);
13194 emit_operand(dst, src, 0);
13195 }
13196
13197 void Assembler::cvttsd2siq(Register dst, Address src) {
13198 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13199 // F2 REX.W 0F 2C /r
13200 // CVTTSD2SI r64, xmm1/m64
13201 InstructionMark im(this);
13202 emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C);
13203 emit_operand(dst, src, 0);
13204 }
13205
13206 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
13207 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13208 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13209 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13210 emit_int16(0x2C, (0xC0 | encode));
13211 }
13212
13213 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
13214 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13215 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13216 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13217 emit_int16(0x2D, (0xC0 | encode));
13218 }
13219
13220 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
13221 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13222 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13223 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13224 emit_int16(0x2C, (0xC0 | encode));
13225 }
13226
13227 void Assembler::decl(Register dst) {
13228 // Don't use it directly. Use MacroAssembler::decrementl() instead.
13229 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
13230 int encode = prefix_and_encode(dst->encoding());
13231 emit_int16((unsigned char)0xFF, (0xC8 | encode));
13232 }
13233
13234 void Assembler::decq(Register dst) {
13235 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13236 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13237 int encode = prefixq_and_encode(dst->encoding());
13238 emit_int16((unsigned char)0xFF, 0xC8 | encode);
13239 }
13240
13241 void Assembler::decq(Address dst) {
13242 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13243 InstructionMark im(this);
13244 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13245 emit_operand(rcx, dst, 0);
13246 }
13247
13248 void Assembler::fxrstor(Address src) {
13249 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13250 emit_operand(as_Register(1), src, 0);
13251 }
13252
13253 void Assembler::xrstor(Address src) {
13254 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13255 emit_operand(as_Register(5), src, 0);
13256 }
13257
13258 void Assembler::fxsave(Address dst) {
13259 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13260 emit_operand(as_Register(0), dst, 0);
13261 }
13262
13263 void Assembler::xsave(Address dst) {
13264 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13265 emit_operand(as_Register(4), dst, 0);
13266 }
13267
13268 void Assembler::idivq(Register src) {
13269 int encode = prefixq_and_encode(src->encoding());
13270 emit_int16((unsigned char)0xF7, (0xF8 | encode));
13271 }
13272
13273 void Assembler::divq(Register src) {
13274 int encode = prefixq_and_encode(src->encoding());
13275 emit_int16((unsigned char)0xF7, (0xF0 | encode));
13276 }
13277
13278 void Assembler::imulq(Register dst, Register src) {
13279 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13280 emit_int24(0x0F, (unsigned char)0xAF, (0xC0 | encode));
13281 }
13282
13283 void Assembler::imulq(Register src) {
13284 int encode = prefixq_and_encode(src->encoding());
13285 emit_int16((unsigned char)0xF7, (0xE8 | encode));
13286 }
13287
13288 void Assembler::imulq(Register dst, Address src, int32_t value) {
13289 InstructionMark im(this);
13290 prefixq(src, dst);
13291 if (is8bit(value)) {
13292 emit_int8((unsigned char)0x6B);
13293 emit_operand(dst, src, 1);
13294 emit_int8(value);
13295 } else {
13296 emit_int8((unsigned char)0x69);
13297 emit_operand(dst, src, 4);
13298 emit_int32(value);
13299 }
13300 }
13301
13302 void Assembler::imulq(Register dst, Register src, int value) {
13303 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13304 if (is8bit(value)) {
13305 emit_int24(0x6B, (0xC0 | encode), (value & 0xFF));
13306 } else {
13307 emit_int16(0x69, (0xC0 | encode));
13308 emit_int32(value);
13309 }
13310 }
13311
13312 void Assembler::imulq(Register dst, Address src) {
13313 InstructionMark im(this);
13314 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF);
13315 emit_operand(dst, src, 0);
13316 }
13317
13318 void Assembler::incl(Register dst) {
13319 // Don't use it directly. Use MacroAssembler::incrementl() instead.
13320 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13321 int encode = prefix_and_encode(dst->encoding());
13322 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13323 }
13324
13325 void Assembler::incq(Register dst) {
13326 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13327 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13328 int encode = prefixq_and_encode(dst->encoding());
13329 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13330 }
13331
13332 void Assembler::incq(Address dst) {
13333 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13334 InstructionMark im(this);
13335 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13336 emit_operand(rax, dst, 0);
13337 }
13338
13339 void Assembler::lea(Register dst, Address src) {
13340 leaq(dst, src);
13341 }
13342
13343 void Assembler::leaq(Register dst, Address src) {
13344 InstructionMark im(this);
13345 emit_int16(get_prefixq(src, dst), (unsigned char)0x8D);
13346 emit_operand(dst, src, 0);
13347 }
13348
13349 void Assembler::mov64(Register dst, int64_t imm64) {
13350 InstructionMark im(this);
13351 int encode = prefixq_and_encode(dst->encoding());
13352 emit_int8(0xB8 | encode);
13353 emit_int64(imm64);
13354 }
13355
13356 void Assembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
13357 InstructionMark im(this);
13358 int encode = prefixq_and_encode(dst->encoding());
13359 emit_int8(0xB8 | encode);
13360 emit_data64(imm64, rtype, format);
13361 }
13362
13363 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
13364 InstructionMark im(this);
13365 int encode = prefixq_and_encode(dst->encoding());
13366 emit_int8(0xB8 | encode);
13367 emit_data64(imm64, rspec);
13368 }
13369
13370 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
13371 InstructionMark im(this);
13372 int encode = prefix_and_encode(dst->encoding());
13373 emit_int8(0xB8 | encode);
13374 emit_data((int)imm32, rspec, narrow_oop_operand);
13375 }
13376
13377 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
13378 InstructionMark im(this);
13379 prefix(dst);
13380 emit_int8((unsigned char)0xC7);
13381 emit_operand(rax, dst, 4);
13382 emit_data((int)imm32, rspec, narrow_oop_operand);
13383 }
13384
13385 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
13386 InstructionMark im(this);
13387 int encode = prefix_and_encode(src1->encoding());
13388 emit_int16((unsigned char)0x81, (0xF8 | encode));
13389 emit_data((int)imm32, rspec, narrow_oop_operand);
13390 }
13391
13392 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
13393 InstructionMark im(this);
13394 prefix(src1);
13395 emit_int8((unsigned char)0x81);
13396 emit_operand(rax, src1, 4);
13397 emit_data((int)imm32, rspec, narrow_oop_operand);
13398 }
13399
13400 void Assembler::lzcntq(Register dst, Register src) {
13401 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13402 emit_int8((unsigned char)0xF3);
13403 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13404 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
13405 }
13406
13407 void Assembler::lzcntq(Register dst, Address src) {
13408 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13409 InstructionMark im(this);
13410 emit_int8((unsigned char)0xF3);
13411 prefixq(src, dst);
13412 emit_int16(0x0F, (unsigned char)0xBD);
13413 emit_operand(dst, src, 0);
13414 }
13415
13416 void Assembler::movdq(XMMRegister dst, Register src) {
13417 // table D-1 says MMX/SSE2
13418 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13419 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13420 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13421 emit_int16(0x6E, (0xC0 | encode));
13422 }
13423
13424 void Assembler::movdq(Register dst, XMMRegister src) {
13425 // table D-1 says MMX/SSE2
13426 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13427 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13428 // swap src/dst to get correct prefix
13429 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13430 emit_int16(0x7E,
13431 (0xC0 | encode));
13432 }
13433
13434 void Assembler::movq(Register dst, Register src) {
13435 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13436 emit_int16((unsigned char)0x8B,
13437 (0xC0 | encode));
13438 }
13439
13440 void Assembler::movq(Register dst, Address src) {
13441 InstructionMark im(this);
13442 emit_int16(get_prefixq(src, dst), (unsigned char)0x8B);
13443 emit_operand(dst, src, 0);
13444 }
13445
13446 void Assembler::movq(Address dst, Register src) {
13447 InstructionMark im(this);
13448 emit_int16(get_prefixq(dst, src), (unsigned char)0x89);
13449 emit_operand(src, dst, 0);
13450 }
13451
13452 void Assembler::movq(Address dst, int32_t imm32) {
13453 InstructionMark im(this);
13454 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13455 emit_operand(as_Register(0), dst, 4);
13456 emit_int32(imm32);
13457 }
13458
13459 void Assembler::movq(Register dst, int32_t imm32) {
13460 int encode = prefixq_and_encode(dst->encoding());
13461 emit_int16((unsigned char)0xC7, (0xC0 | encode));
13462 emit_int32(imm32);
13463 }
13464
13465 void Assembler::movsbq(Register dst, Address src) {
13466 InstructionMark im(this);
13467 emit_int24(get_prefixq(src, dst),
13468 0x0F,
13469 (unsigned char)0xBE);
13470 emit_operand(dst, src, 0);
13471 }
13472
13473 void Assembler::movsbq(Register dst, Register src) {
13474 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13475 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
13476 }
13477
13478 void Assembler::movslq(Address dst, int32_t imm32) {
13479 assert(is_simm32(imm32), "lost bits");
13480 InstructionMark im(this);
13481 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13482 emit_operand(rax, dst, 4);
13483 emit_int32(imm32);
13484 }
13485
13486 void Assembler::movslq(Register dst, Address src) {
13487 InstructionMark im(this);
13488 emit_int16(get_prefixq(src, dst), 0x63);
13489 emit_operand(dst, src, 0);
13490 }
13491
13492 void Assembler::movslq(Register dst, Register src) {
13493 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13494 emit_int16(0x63, (0xC0 | encode));
13495 }
13496
13497 void Assembler::movswq(Register dst, Address src) {
13498 InstructionMark im(this);
13499 emit_int24(get_prefixq(src, dst),
13500 0x0F,
13501 (unsigned char)0xBF);
13502 emit_operand(dst, src, 0);
13503 }
13504
13505 void Assembler::movswq(Register dst, Register src) {
13506 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13507 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
13508 }
13509
13510 void Assembler::movzbq(Register dst, Address src) {
13511 InstructionMark im(this);
13512 emit_int24(get_prefixq(src, dst),
13513 0x0F,
13514 (unsigned char)0xB6);
13515 emit_operand(dst, src, 0);
13516 }
13517
13518 void Assembler::movzbq(Register dst, Register src) {
13519 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13520 emit_int24(0x0F, (unsigned char)0xB6, (0xC0 | encode));
13521 }
13522
13523 void Assembler::movzwq(Register dst, Address src) {
13524 InstructionMark im(this);
13525 emit_int24(get_prefixq(src, dst),
13526 0x0F,
13527 (unsigned char)0xB7);
13528 emit_operand(dst, src, 0);
13529 }
13530
13531 void Assembler::movzwq(Register dst, Register src) {
13532 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13533 emit_int24(0x0F, (unsigned char)0xB7, (0xC0 | encode));
13534 }
13535
13536 void Assembler::mulq(Address src) {
13537 InstructionMark im(this);
13538 emit_int16(get_prefixq(src), (unsigned char)0xF7);
13539 emit_operand(rsp, src, 0);
13540 }
13541
13542 void Assembler::mulq(Register src) {
13543 int encode = prefixq_and_encode(src->encoding());
13544 emit_int16((unsigned char)0xF7, (0xE0 | encode));
13545 }
13546
13547 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
13548 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13549 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13550 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
13551 emit_int16((unsigned char)0xF6, (0xC0 | encode));
13552 }
13553
13554 void Assembler::negq(Register dst) {
13555 int encode = prefixq_and_encode(dst->encoding());
13556 emit_int16((unsigned char)0xF7, (0xD8 | encode));
13557 }
13558
13559 void Assembler::negq(Address dst) {
13560 InstructionMark im(this);
13561 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
13562 emit_operand(as_Register(3), dst, 0);
13563 }
13564
13565 void Assembler::notq(Register dst) {
13566 int encode = prefixq_and_encode(dst->encoding());
13567 emit_int16((unsigned char)0xF7, (0xD0 | encode));
13568 }
13569
13570 void Assembler::btsq(Address dst, int imm8) {
13571 assert(isByte(imm8), "not a byte");
13572 InstructionMark im(this);
13573 emit_int24(get_prefixq(dst),
13574 0x0F,
13575 (unsigned char)0xBA);
13576 emit_operand(rbp /* 5 */, dst, 1);
13577 emit_int8(imm8);
13578 }
13579
13580 void Assembler::btrq(Address dst, int imm8) {
13581 assert(isByte(imm8), "not a byte");
13582 InstructionMark im(this);
13583 emit_int24(get_prefixq(dst),
13584 0x0F,
13585 (unsigned char)0xBA);
13586 emit_operand(rsi /* 6 */, dst, 1);
13587 emit_int8(imm8);
13588 }
13589
13590 void Assembler::orq(Address dst, int32_t imm32) {
13591 InstructionMark im(this);
13592 prefixq(dst);
13593 emit_arith_operand(0x81, as_Register(1), dst, imm32);
13594 }
13595
13596 void Assembler::orq(Address dst, Register src) {
13597 InstructionMark im(this);
13598 emit_int16(get_prefixq(dst, src), (unsigned char)0x09);
13599 emit_operand(src, dst, 0);
13600 }
13601
13602 void Assembler::orq(Register dst, int32_t imm32) {
13603 (void) prefixq_and_encode(dst->encoding());
13604 emit_arith(0x81, 0xC8, dst, imm32);
13605 }
13606
13607 void Assembler::orq_imm32(Register dst, int32_t imm32) {
13608 (void) prefixq_and_encode(dst->encoding());
13609 emit_arith_imm32(0x81, 0xC8, dst, imm32);
13610 }
13611
13612 void Assembler::orq(Register dst, Address src) {
13613 InstructionMark im(this);
13614 emit_int16(get_prefixq(src, dst), 0x0B);
13615 emit_operand(dst, src, 0);
13616 }
13617
13618 void Assembler::orq(Register dst, Register src) {
13619 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13620 emit_arith(0x0B, 0xC0, dst, src);
13621 }
13622
13623 void Assembler::popcntq(Register dst, Address src) {
13624 assert(VM_Version::supports_popcnt(), "must support");
13625 InstructionMark im(this);
13626 emit_int32((unsigned char)0xF3,
13627 get_prefixq(src, dst),
13628 0x0F,
13629 (unsigned char)0xB8);
13630 emit_operand(dst, src, 0);
13631 }
13632
13633 void Assembler::popcntq(Register dst, Register src) {
13634 assert(VM_Version::supports_popcnt(), "must support");
13635 emit_int8((unsigned char)0xF3);
13636 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13637 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
13638 }
13639
13640 void Assembler::popq(Address dst) {
13641 InstructionMark im(this);
13642 emit_int16(get_prefixq(dst), (unsigned char)0x8F);
13643 emit_operand(rax, dst, 0);
13644 }
13645
13646 void Assembler::popq(Register dst) {
13647 emit_int8((unsigned char)0x58 | dst->encoding());
13648 }
13649
13650 // Precomputable: popa, pusha, vzeroupper
13651
13652 // The result of these routines are invariant from one invocation to another
13653 // invocation for the duration of a run. Caching the result on bootstrap
13654 // and copying it out on subsequent invocations can thus be beneficial
13655 static bool precomputed = false;
13656
13657 static u_char* popa_code = nullptr;
13658 static int popa_len = 0;
13659
13660 static u_char* pusha_code = nullptr;
13661 static int pusha_len = 0;
13662
13663 static u_char* vzup_code = nullptr;
13664 static int vzup_len = 0;
13665
13666 void Assembler::precompute_instructions() {
13667 assert(!Universe::is_fully_initialized(), "must still be single threaded");
13668 guarantee(!precomputed, "only once");
13669 precomputed = true;
13670 ResourceMark rm;
13671
13672 // Make a temporary buffer big enough for the routines we're capturing
13673 int size = 256;
13674 char* tmp_code = NEW_RESOURCE_ARRAY(char, size);
13675 CodeBuffer buffer((address)tmp_code, size);
13676 MacroAssembler masm(&buffer);
13677
13678 address begin_popa = masm.code_section()->end();
13679 masm.popa_uncached();
13680 address end_popa = masm.code_section()->end();
13681 masm.pusha_uncached();
13682 address end_pusha = masm.code_section()->end();
13683 masm.vzeroupper_uncached();
13684 address end_vzup = masm.code_section()->end();
13685
13686 // Save the instructions to permanent buffers.
13687 popa_len = (int)(end_popa - begin_popa);
13688 popa_code = NEW_C_HEAP_ARRAY(u_char, popa_len, mtInternal);
13689 memcpy(popa_code, begin_popa, popa_len);
13690
13691 pusha_len = (int)(end_pusha - end_popa);
13692 pusha_code = NEW_C_HEAP_ARRAY(u_char, pusha_len, mtInternal);
13693 memcpy(pusha_code, end_popa, pusha_len);
13694
13695 vzup_len = (int)(end_vzup - end_pusha);
13696 if (vzup_len > 0) {
13697 vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
13698 memcpy(vzup_code, end_pusha, vzup_len);
13699 } else {
13700 vzup_code = pusha_code; // dummy
13701 }
13702
13703 assert(masm.code()->total_oop_size() == 0 &&
13704 masm.code()->total_metadata_size() == 0 &&
13705 masm.code()->total_relocation_size() == 0,
13706 "pre-computed code can't reference oops, metadata or contain relocations");
13707 }
13708
13709 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
13710 assert(src != nullptr, "code to copy must have been pre-computed");
13711 assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
13712 address end = code_section->end();
13713 memcpy(end, src, src_len);
13714 code_section->set_end(end + src_len);
13715 }
13716
13717 void Assembler::popa() { // 64bit
13718 emit_copy(code_section(), popa_code, popa_len);
13719 }
13720
13721 void Assembler::popa_uncached() { // 64bit
13722 movq(r15, Address(rsp, 0));
13723 movq(r14, Address(rsp, wordSize));
13724 movq(r13, Address(rsp, 2 * wordSize));
13725 movq(r12, Address(rsp, 3 * wordSize));
13726 movq(r11, Address(rsp, 4 * wordSize));
13727 movq(r10, Address(rsp, 5 * wordSize));
13728 movq(r9, Address(rsp, 6 * wordSize));
13729 movq(r8, Address(rsp, 7 * wordSize));
13730 movq(rdi, Address(rsp, 8 * wordSize));
13731 movq(rsi, Address(rsp, 9 * wordSize));
13732 movq(rbp, Address(rsp, 10 * wordSize));
13733 // Skip rsp as it is restored automatically to the value
13734 // before the corresponding pusha when popa is done.
13735 movq(rbx, Address(rsp, 12 * wordSize));
13736 movq(rdx, Address(rsp, 13 * wordSize));
13737 movq(rcx, Address(rsp, 14 * wordSize));
13738 movq(rax, Address(rsp, 15 * wordSize));
13739
13740 addq(rsp, 16 * wordSize);
13741 }
13742
13743 // Does not actually store the value of rsp on the stack.
13744 // The slot for rsp just contains an arbitrary value.
13745 void Assembler::pusha() { // 64bit
13746 emit_copy(code_section(), pusha_code, pusha_len);
13747 }
13748
13749 // Does not actually store the value of rsp on the stack.
13750 // The slot for rsp just contains an arbitrary value.
13751 void Assembler::pusha_uncached() { // 64bit
13752 subq(rsp, 16 * wordSize);
13753
13754 movq(Address(rsp, 15 * wordSize), rax);
13755 movq(Address(rsp, 14 * wordSize), rcx);
13756 movq(Address(rsp, 13 * wordSize), rdx);
13757 movq(Address(rsp, 12 * wordSize), rbx);
13758 // Skip rsp as the value is normally not used. There are a few places where
13759 // the original value of rsp needs to be known but that can be computed
13760 // from the value of rsp immediately after pusha (rsp + 16 * wordSize).
13761 movq(Address(rsp, 10 * wordSize), rbp);
13762 movq(Address(rsp, 9 * wordSize), rsi);
13763 movq(Address(rsp, 8 * wordSize), rdi);
13764 movq(Address(rsp, 7 * wordSize), r8);
13765 movq(Address(rsp, 6 * wordSize), r9);
13766 movq(Address(rsp, 5 * wordSize), r10);
13767 movq(Address(rsp, 4 * wordSize), r11);
13768 movq(Address(rsp, 3 * wordSize), r12);
13769 movq(Address(rsp, 2 * wordSize), r13);
13770 movq(Address(rsp, wordSize), r14);
13771 movq(Address(rsp, 0), r15);
13772 }
13773
13774 void Assembler::vzeroupper() {
13775 emit_copy(code_section(), vzup_code, vzup_len);
13776 }
13777
13778 void Assembler::vzeroall() {
13779 assert(VM_Version::supports_avx(), "requires AVX");
13780 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13781 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
13782 emit_int8(0x77);
13783 }
13784
13785 void Assembler::pushq(Address src) {
13786 InstructionMark im(this);
13787 emit_int16(get_prefixq(src), (unsigned char)0xFF);
13788 emit_operand(rsi, src, 0);
13789 }
13790
13791 void Assembler::rclq(Register dst, int imm8) {
13792 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13793 int encode = prefixq_and_encode(dst->encoding());
13794 if (imm8 == 1) {
13795 emit_int16((unsigned char)0xD1, (0xD0 | encode));
13796 } else {
13797 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
13798 }
13799 }
13800
13801 void Assembler::rcrq(Register dst, int imm8) {
13802 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13803 int encode = prefixq_and_encode(dst->encoding());
13804 if (imm8 == 1) {
13805 emit_int16((unsigned char)0xD1, (0xD8 | encode));
13806 } else {
13807 emit_int24((unsigned char)0xC1, (0xD8 | encode), imm8);
13808 }
13809 }
13810
13811 void Assembler::rorxl(Register dst, Register src, int imm8) {
13812 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13813 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13814 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13815 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13816 }
13817
13818 void Assembler::rorxl(Register dst, Address src, int imm8) {
13819 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13820 InstructionMark im(this);
13821 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13822 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13823 emit_int8((unsigned char)0xF0);
13824 emit_operand(dst, src, 1);
13825 emit_int8(imm8);
13826 }
13827
13828 void Assembler::rorxq(Register dst, Register src, int imm8) {
13829 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13830 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13831 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13832 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13833 }
13834
13835 void Assembler::rorxq(Register dst, Address src, int imm8) {
13836 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13837 InstructionMark im(this);
13838 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13839 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13840 emit_int8((unsigned char)0xF0);
13841 emit_operand(dst, src, 1);
13842 emit_int8(imm8);
13843 }
13844
13845 #ifdef _LP64
13846 void Assembler::salq(Address dst, int imm8) {
13847 InstructionMark im(this);
13848 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13849 if (imm8 == 1) {
13850 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13851 emit_operand(as_Register(4), dst, 0);
13852 }
13853 else {
13854 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13855 emit_operand(as_Register(4), dst, 1);
13856 emit_int8(imm8);
13857 }
13858 }
13859
13860 void Assembler::salq(Address dst) {
13861 InstructionMark im(this);
13862 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13863 emit_operand(as_Register(4), dst, 0);
13864 }
13865
13866 void Assembler::salq(Register dst, int imm8) {
13867 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13868 int encode = prefixq_and_encode(dst->encoding());
13869 if (imm8 == 1) {
13870 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13871 } else {
13872 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13873 }
13874 }
13875
13876 void Assembler::salq(Register dst) {
13877 int encode = prefixq_and_encode(dst->encoding());
13878 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13879 }
13880
13881 void Assembler::sarq(Address dst, int imm8) {
13882 InstructionMark im(this);
13883 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13884 if (imm8 == 1) {
13885 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13886 emit_operand(as_Register(7), dst, 0);
13887 }
13888 else {
13889 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13890 emit_operand(as_Register(7), dst, 1);
13891 emit_int8(imm8);
13892 }
13893 }
13894
13895 void Assembler::sarq(Address dst) {
13896 InstructionMark im(this);
13897 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13898 emit_operand(as_Register(7), dst, 0);
13899 }
13900
13901 void Assembler::sarq(Register dst, int imm8) {
13902 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13903 int encode = prefixq_and_encode(dst->encoding());
13904 if (imm8 == 1) {
13905 emit_int16((unsigned char)0xD1, (0xF8 | encode));
13906 } else {
13907 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
13908 }
13909 }
13910
13911 void Assembler::sarq(Register dst) {
13912 int encode = prefixq_and_encode(dst->encoding());
13913 emit_int16((unsigned char)0xD3, (0xF8 | encode));
13914 }
13915 #endif
13916
13917 void Assembler::sbbq(Address dst, int32_t imm32) {
13918 InstructionMark im(this);
13919 prefixq(dst);
13920 emit_arith_operand(0x81, rbx, dst, imm32);
13921 }
13922
13923 void Assembler::sbbq(Register dst, int32_t imm32) {
13924 (void) prefixq_and_encode(dst->encoding());
13925 emit_arith(0x81, 0xD8, dst, imm32);
13926 }
13927
13928 void Assembler::sbbq(Register dst, Address src) {
13929 InstructionMark im(this);
13930 emit_int16(get_prefixq(src, dst), 0x1B);
13931 emit_operand(dst, src, 0);
13932 }
13933
13934 void Assembler::sbbq(Register dst, Register src) {
13935 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13936 emit_arith(0x1B, 0xC0, dst, src);
13937 }
13938
13939 void Assembler::shlq(Register dst, int imm8) {
13940 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13941 int encode = prefixq_and_encode(dst->encoding());
13942 if (imm8 == 1) {
13943 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13944 } else {
13945 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13946 }
13947 }
13948
13949 void Assembler::shlq(Register dst) {
13950 int encode = prefixq_and_encode(dst->encoding());
13951 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13952 }
13953
13954 void Assembler::shrq(Register dst, int imm8) {
13955 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13956 int encode = prefixq_and_encode(dst->encoding());
13957 if (imm8 == 1) {
13958 emit_int16((unsigned char)0xD1, (0xE8 | encode));
13959 }
13960 else {
13961 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
13962 }
13963 }
13964
13965 void Assembler::shrq(Register dst) {
13966 int encode = prefixq_and_encode(dst->encoding());
13967 emit_int16((unsigned char)0xD3, 0xE8 | encode);
13968 }
13969
13970 void Assembler::shrq(Address dst) {
13971 InstructionMark im(this);
13972 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13973 emit_operand(as_Register(5), dst, 0);
13974 }
13975
13976 void Assembler::shrq(Address dst, int imm8) {
13977 InstructionMark im(this);
13978 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13979 if (imm8 == 1) {
13980 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13981 emit_operand(as_Register(5), dst, 0);
13982 }
13983 else {
13984 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13985 emit_operand(as_Register(5), dst, 1);
13986 emit_int8(imm8);
13987 }
13988 }
13989
13990 void Assembler::subq(Address dst, int32_t imm32) {
13991 InstructionMark im(this);
13992 prefixq(dst);
13993 emit_arith_operand(0x81, rbp, dst, imm32);
13994 }
13995
13996 void Assembler::subq(Address dst, Register src) {
13997 InstructionMark im(this);
13998 emit_int16(get_prefixq(dst, src), 0x29);
13999 emit_operand(src, dst, 0);
14000 }
14001
14002 void Assembler::subq(Register dst, int32_t imm32) {
14003 (void) prefixq_and_encode(dst->encoding());
14004 emit_arith(0x81, 0xE8, dst, imm32);
14005 }
14006
14007 // Force generation of a 4 byte immediate value even if it fits into 8bit
14008 void Assembler::subq_imm32(Register dst, int32_t imm32) {
14009 (void) prefixq_and_encode(dst->encoding());
14010 emit_arith_imm32(0x81, 0xE8, dst, imm32);
14011 }
14012
14013 void Assembler::subq(Register dst, Address src) {
14014 InstructionMark im(this);
14015 emit_int16(get_prefixq(src, dst), 0x2B);
14016 emit_operand(dst, src, 0);
14017 }
14018
14019 void Assembler::subq(Register dst, Register src) {
14020 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14021 emit_arith(0x2B, 0xC0, dst, src);
14022 }
14023
14024 void Assembler::testq(Address dst, int32_t imm32) {
14025 InstructionMark im(this);
14026 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
14027 emit_operand(as_Register(0), dst, 4);
14028 emit_int32(imm32);
14029 }
14030
14031 void Assembler::testq(Register dst, int32_t imm32) {
14032 // not using emit_arith because test
14033 // doesn't support sign-extension of
14034 // 8bit operands
14035 if (dst == rax) {
14036 prefix(REX_W);
14037 emit_int8((unsigned char)0xA9);
14038 emit_int32(imm32);
14039 } else {
14040 int encode = dst->encoding();
14041 encode = prefixq_and_encode(encode);
14042 emit_int16((unsigned char)0xF7, (0xC0 | encode));
14043 emit_int32(imm32);
14044 }
14045 }
14046
14047 void Assembler::testq(Register dst, Register src) {
14048 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14049 emit_arith(0x85, 0xC0, dst, src);
14050 }
14051
14052 void Assembler::testq(Register dst, Address src) {
14053 InstructionMark im(this);
14054 emit_int16(get_prefixq(src, dst), (unsigned char)0x85);
14055 emit_operand(dst, src, 0);
14056 }
14057
14058 void Assembler::xaddq(Address dst, Register src) {
14059 InstructionMark im(this);
14060 emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1);
14061 emit_operand(src, dst, 0);
14062 }
14063
14064 void Assembler::xchgq(Register dst, Address src) {
14065 InstructionMark im(this);
14066 emit_int16(get_prefixq(src, dst), (unsigned char)0x87);
14067 emit_operand(dst, src, 0);
14068 }
14069
14070 void Assembler::xchgq(Register dst, Register src) {
14071 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
14072 emit_int16((unsigned char)0x87, (0xc0 | encode));
14073 }
14074
14075 void Assembler::xorq(Register dst, Register src) {
14076 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14077 emit_arith(0x33, 0xC0, dst, src);
14078 }
14079
14080 void Assembler::xorq(Register dst, Address src) {
14081 InstructionMark im(this);
14082 emit_int16(get_prefixq(src, dst), 0x33);
14083 emit_operand(dst, src, 0);
14084 }
14085
14086 void Assembler::xorq(Register dst, int32_t imm32) {
14087 (void) prefixq_and_encode(dst->encoding());
14088 emit_arith(0x81, 0xF0, dst, imm32);
14089 }
14090
14091 void Assembler::xorq(Address dst, int32_t imm32) {
14092 InstructionMark im(this);
14093 prefixq(dst);
14094 emit_arith_operand(0x81, as_Register(6), dst, imm32);
14095 }
14096
14097 void Assembler::xorq(Address dst, Register src) {
14098 InstructionMark im(this);
14099 emit_int16(get_prefixq(dst, src), 0x31);
14100 emit_operand(src, dst, 0);
14101 }
14102
14103 #endif // !LP64
14104
14105 void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) {
14106 if (VM_Version::supports_evex()) {
14107 _tuple_type = tuple_type;
14108 _input_size_in_bits = input_size_in_bits;
14109 }
14110 }