1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "interpreter/interpreter.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "memory/universe.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/objectMonitor.hpp"
34 #include "runtime/os.hpp"
35 #include "runtime/sharedRuntime.hpp"
36 #include "runtime/stubRoutines.hpp"
37 #include "runtime/vm_version.hpp"
38 #include "utilities/checkedCast.hpp"
39 #include "utilities/macros.hpp"
40
41 #ifdef PRODUCT
42 #define BLOCK_COMMENT(str) /* nothing */
43 #define STOP(error) stop(error)
44 #else
45 #define BLOCK_COMMENT(str) block_comment(str)
46 #define STOP(error) block_comment(error); stop(error)
47 #endif
48
49 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
50 // Implementation of AddressLiteral
51
52 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
53 static const unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
54 // -----------------Table 4.5 -------------------- //
55 16, 32, 64, // EVEX_FV(0)
56 4, 4, 4, // EVEX_FV(1) - with Evex.b
57 16, 32, 64, // EVEX_FV(2) - with Evex.w
58 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
59 8, 16, 32, // EVEX_HV(0)
60 4, 4, 4, // EVEX_HV(1) - with Evex.b
61 // -----------------Table 4.6 -------------------- //
62 16, 32, 64, // EVEX_FVM(0)
63 1, 1, 1, // EVEX_T1S(0)
64 2, 2, 2, // EVEX_T1S(1)
65 4, 4, 4, // EVEX_T1S(2)
66 8, 8, 8, // EVEX_T1S(3)
67 4, 4, 4, // EVEX_T1F(0)
68 8, 8, 8, // EVEX_T1F(1)
69 8, 8, 8, // EVEX_T2(0)
70 0, 16, 16, // EVEX_T2(1)
71 0, 16, 16, // EVEX_T4(0)
72 0, 0, 32, // EVEX_T4(1)
73 0, 0, 32, // EVEX_T8(0)
74 8, 16, 32, // EVEX_HVM(0)
75 4, 8, 16, // EVEX_QVM(0)
76 2, 4, 8, // EVEX_OVM(0)
77 16, 16, 16, // EVEX_M128(0)
78 8, 32, 64, // EVEX_DUP(0)
79 0, 0, 0 // EVEX_NTUP
80 };
81
82 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
83 _is_lval = false;
84 _target = target;
85 switch (rtype) {
86 case relocInfo::oop_type:
87 case relocInfo::metadata_type:
88 // Oops are a special case. Normally they would be their own section
89 // but in cases like icBuffer they are literals in the code stream that
90 // we don't have a section for. We use none so that we get a literal address
91 // which is always patchable.
92 break;
93 case relocInfo::external_word_type:
94 _rspec = external_word_Relocation::spec(target);
95 break;
96 case relocInfo::internal_word_type:
97 _rspec = internal_word_Relocation::spec(target);
98 break;
99 case relocInfo::opt_virtual_call_type:
100 _rspec = opt_virtual_call_Relocation::spec();
101 break;
102 case relocInfo::static_call_type:
103 _rspec = static_call_Relocation::spec();
104 break;
105 case relocInfo::runtime_call_type:
106 _rspec = runtime_call_Relocation::spec();
107 break;
108 case relocInfo::poll_type:
109 case relocInfo::poll_return_type:
110 _rspec = Relocation::spec_simple(rtype);
111 break;
112 case relocInfo::none:
113 break;
114 default:
115 ShouldNotReachHere();
116 break;
117 }
118 }
119
120 // Implementation of Address
121
122 #ifdef _LP64
123
124 Address Address::make_array(ArrayAddress adr) {
125 // Not implementable on 64bit machines
126 // Should have been handled higher up the call chain.
127 ShouldNotReachHere();
128 return Address();
129 }
130
131 // exceedingly dangerous constructor
132 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
133 _base = noreg;
134 _index = noreg;
135 _scale = no_scale;
136 _disp = disp;
137 _xmmindex = xnoreg;
138 _isxmmindex = false;
139 switch (rtype) {
140 case relocInfo::external_word_type:
141 _rspec = external_word_Relocation::spec(loc);
142 break;
143 case relocInfo::internal_word_type:
144 _rspec = internal_word_Relocation::spec(loc);
145 break;
146 case relocInfo::runtime_call_type:
147 // HMM
148 _rspec = runtime_call_Relocation::spec();
149 break;
150 case relocInfo::poll_type:
151 case relocInfo::poll_return_type:
152 _rspec = Relocation::spec_simple(rtype);
153 break;
154 case relocInfo::none:
155 break;
156 default:
157 ShouldNotReachHere();
158 }
159 }
160 #else // LP64
161
162 Address Address::make_array(ArrayAddress adr) {
163 AddressLiteral base = adr.base();
164 Address index = adr.index();
165 assert(index._disp == 0, "must not have disp"); // maybe it can?
166 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
167 array._rspec = base._rspec;
168 return array;
169 }
170
171 // exceedingly dangerous constructor
172 Address::Address(address loc, RelocationHolder spec) {
173 _base = noreg;
174 _index = noreg;
175 _scale = no_scale;
176 _disp = (intptr_t) loc;
177 _rspec = spec;
178 _xmmindex = xnoreg;
179 _isxmmindex = false;
180 }
181
182 #endif // _LP64
183
184
185
186 // Convert the raw encoding form into the form expected by the constructor for
187 // Address. An index of 4 (rsp) corresponds to having no index, so convert
188 // that to noreg for the Address constructor.
189 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
190 RelocationHolder rspec = RelocationHolder::none;
191 if (disp_reloc != relocInfo::none) {
192 rspec = Relocation::spec_simple(disp_reloc);
193 }
194 bool valid_index = index != rsp->encoding();
195 if (valid_index) {
196 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
197 madr._rspec = rspec;
198 return madr;
199 } else {
200 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
201 madr._rspec = rspec;
202 return madr;
203 }
204 }
205
206 // Implementation of Assembler
207
208 int AbstractAssembler::code_fill_byte() {
209 return (u_char)'\xF4'; // hlt
210 }
211
212 void Assembler::init_attributes(void) {
213 _legacy_mode_bw = (VM_Version::supports_avx512bw() == false);
214 _legacy_mode_dq = (VM_Version::supports_avx512dq() == false);
215 _legacy_mode_vl = (VM_Version::supports_avx512vl() == false);
216 _legacy_mode_vlbw = (VM_Version::supports_avx512vlbw() == false);
217 NOT_LP64(_is_managed = false;)
218 _attributes = nullptr;
219 }
220
221 void Assembler::set_attributes(InstructionAttr* attributes) {
222 // Record the assembler in the attributes, so the attributes destructor can
223 // clear the assembler's attributes, cleaning up the otherwise dangling
224 // pointer. gcc13 has a false positive warning, because it doesn't tie that
225 // cleanup to the assignment of _attributes here.
226 attributes->set_current_assembler(this);
227 PRAGMA_DIAG_PUSH
228 PRAGMA_DANGLING_POINTER_IGNORED
229 _attributes = attributes;
230 PRAGMA_DIAG_POP
231 }
232
233 void Assembler::membar(Membar_mask_bits order_constraint) {
234 // We only have to handle StoreLoad
235 if (order_constraint & StoreLoad) {
236 // All usable chips support "locked" instructions which suffice
237 // as barriers, and are much faster than the alternative of
238 // using cpuid instruction. We use here a locked add [esp-C],0.
239 // This is conveniently otherwise a no-op except for blowing
240 // flags, and introducing a false dependency on target memory
241 // location. We can't do anything with flags, but we can avoid
242 // memory dependencies in the current method by locked-adding
243 // somewhere else on the stack. Doing [esp+C] will collide with
244 // something on stack in current method, hence we go for [esp-C].
245 // It is convenient since it is almost always in data cache, for
246 // any small C. We need to step back from SP to avoid data
247 // dependencies with other things on below SP (callee-saves, for
248 // example). Without a clear way to figure out the minimal safe
249 // distance from SP, it makes sense to step back the complete
250 // cache line, as this will also avoid possible second-order effects
251 // with locked ops against the cache line. Our choice of offset
252 // is bounded by x86 operand encoding, which should stay within
253 // [-128; +127] to have the 8-byte displacement encoding.
254 //
255 // Any change to this code may need to revisit other places in
256 // the code where this idiom is used, in particular the
257 // orderAccess code.
258
259 int offset = -VM_Version::L1_line_size();
260 if (offset < -128) {
261 offset = -128;
262 }
263
264 lock();
265 addl(Address(rsp, offset), 0);// Assert the lock# signal here
266 }
267 }
268
269 // make this go away someday
270 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
271 if (rtype == relocInfo::none)
272 emit_int32(data);
273 else
274 emit_data(data, Relocation::spec_simple(rtype), format);
275 }
276
277 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
278 assert(imm_operand == 0, "default format must be immediate in this file");
279 assert(inst_mark() != nullptr, "must be inside InstructionMark");
280 if (rspec.type() != relocInfo::none) {
281 #ifdef ASSERT
282 check_relocation(rspec, format);
283 #endif
284 // Do not use AbstractAssembler::relocate, which is not intended for
285 // embedded words. Instead, relocate to the enclosing instruction.
286
287 // hack. call32 is too wide for mask so use disp32
288 if (format == call32_operand)
289 code_section()->relocate(inst_mark(), rspec, disp32_operand);
290 else
291 code_section()->relocate(inst_mark(), rspec, format);
292 }
293 emit_int32(data);
294 }
295
296 static int encode(Register r) {
297 int enc = r->encoding();
298 if (enc >= 8) {
299 enc -= 8;
300 }
301 return enc;
302 }
303
304 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
305 assert(dst->has_byte_register(), "must have byte register");
306 assert(isByte(op1) && isByte(op2), "wrong opcode");
307 assert(isByte(imm8), "not a byte");
308 assert((op1 & 0x01) == 0, "should be 8bit operation");
309 emit_int24(op1, (op2 | encode(dst)), imm8);
310 }
311
312
313 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
314 assert(isByte(op1) && isByte(op2), "wrong opcode");
315 assert(op1 == 0x81, "Unexpected opcode");
316 if (is8bit(imm32)) {
317 emit_int24(op1 | 0x02, // set sign bit
318 op2 | encode(dst),
319 imm32 & 0xFF);
320 } else if (dst == rax) {
321 switch (op2) {
322 case 0xD0: emit_int8(0x15); break; // adc
323 case 0xC0: emit_int8(0x05); break; // add
324 case 0xE0: emit_int8(0x25); break; // and
325 case 0xF8: emit_int8(0x3D); break; // cmp
326 case 0xC8: emit_int8(0x0D); break; // or
327 case 0xD8: emit_int8(0x1D); break; // sbb
328 case 0xE8: emit_int8(0x2D); break; // sub
329 case 0xF0: emit_int8(0x35); break; // xor
330 default: ShouldNotReachHere();
331 }
332 emit_int32(imm32);
333 } else {
334 emit_int16(op1, (op2 | encode(dst)));
335 emit_int32(imm32);
336 }
337 }
338
339 // Force generation of a 4 byte immediate value even if it fits into 8bit
340 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
341 assert(isByte(op1) && isByte(op2), "wrong opcode");
342 assert((op1 & 0x01) == 1, "should be 32bit operation");
343 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
344 emit_int16(op1, (op2 | encode(dst)));
345 emit_int32(imm32);
346 }
347
348 // immediate-to-memory forms
349 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
350 assert((op1 & 0x01) == 1, "should be 32bit operation");
351 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
352 if (is8bit(imm32)) {
353 emit_int8(op1 | 0x02); // set sign bit
354 emit_operand(rm, adr, 1);
355 emit_int8(imm32 & 0xFF);
356 } else {
357 emit_int8(op1);
358 emit_operand(rm, adr, 4);
359 emit_int32(imm32);
360 }
361 }
362
363 void Assembler::emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32) {
364 assert(op1 == 0x81, "unexpected opcode");
365 emit_int8(op1);
366 emit_operand(rm, adr, 4);
367 emit_int32(imm32);
368 }
369
370 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
371 assert(isByte(op1) && isByte(op2), "wrong opcode");
372 emit_int16(op1, (op2 | encode(dst) << 3 | encode(src)));
373 }
374
375
376 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
377 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
378 int mod_idx = 0;
379 // We will test if the displacement fits the compressed format and if so
380 // apply the compression to the displacement iff the result is8bit.
381 if (VM_Version::supports_evex() && is_evex_inst) {
382 switch (cur_tuple_type) {
383 case EVEX_FV:
384 if ((cur_encoding & VEX_W) == VEX_W) {
385 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
386 } else {
387 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
388 }
389 break;
390
391 case EVEX_HV:
392 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
393 break;
394
395 case EVEX_FVM:
396 break;
397
398 case EVEX_T1S:
399 switch (in_size_in_bits) {
400 case EVEX_8bit:
401 break;
402
403 case EVEX_16bit:
404 mod_idx = 1;
405 break;
406
407 case EVEX_32bit:
408 mod_idx = 2;
409 break;
410
411 case EVEX_64bit:
412 mod_idx = 3;
413 break;
414 }
415 break;
416
417 case EVEX_T1F:
418 case EVEX_T2:
419 case EVEX_T4:
420 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
421 break;
422
423 case EVEX_T8:
424 break;
425
426 case EVEX_HVM:
427 break;
428
429 case EVEX_QVM:
430 break;
431
432 case EVEX_OVM:
433 break;
434
435 case EVEX_M128:
436 break;
437
438 case EVEX_DUP:
439 break;
440
441 default:
442 assert(0, "no valid evex tuple_table entry");
443 break;
444 }
445
446 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
447 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
448 if ((disp % disp_factor) == 0) {
449 int new_disp = disp / disp_factor;
450 if ((-0x80 <= new_disp && new_disp < 0x80)) {
451 disp = new_disp;
452 }
453 } else {
454 return false;
455 }
456 }
457 }
458 return (-0x80 <= disp && disp < 0x80);
459 }
460
461
462 bool Assembler::emit_compressed_disp_byte(int &disp) {
463 int mod_idx = 0;
464 // We will test if the displacement fits the compressed format and if so
465 // apply the compression to the displacement iff the result is8bit.
466 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
467 int evex_encoding = _attributes->get_evex_encoding();
468 int tuple_type = _attributes->get_tuple_type();
469 switch (tuple_type) {
470 case EVEX_FV:
471 if ((evex_encoding & VEX_W) == VEX_W) {
472 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
473 } else {
474 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
475 }
476 break;
477
478 case EVEX_HV:
479 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
480 break;
481
482 case EVEX_FVM:
483 break;
484
485 case EVEX_T1S:
486 switch (_attributes->get_input_size()) {
487 case EVEX_8bit:
488 break;
489
490 case EVEX_16bit:
491 mod_idx = 1;
492 break;
493
494 case EVEX_32bit:
495 mod_idx = 2;
496 break;
497
498 case EVEX_64bit:
499 mod_idx = 3;
500 break;
501 }
502 break;
503
504 case EVEX_T1F:
505 case EVEX_T2:
506 case EVEX_T4:
507 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
508 break;
509
510 case EVEX_T8:
511 break;
512
513 case EVEX_HVM:
514 break;
515
516 case EVEX_QVM:
517 break;
518
519 case EVEX_OVM:
520 break;
521
522 case EVEX_M128:
523 break;
524
525 case EVEX_DUP:
526 break;
527
528 default:
529 assert(0, "no valid evex tuple_table entry");
530 break;
531 }
532
533 int vector_len = _attributes->get_vector_len();
534 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
535 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
536 if ((disp % disp_factor) == 0) {
537 int new_disp = disp / disp_factor;
538 if (is8bit(new_disp)) {
539 disp = new_disp;
540 }
541 } else {
542 return false;
543 }
544 }
545 }
546 return is8bit(disp);
547 }
548
549 static bool is_valid_encoding(int reg_enc) {
550 return reg_enc >= 0;
551 }
552
553 static int raw_encode(Register reg) {
554 assert(reg == noreg || reg->is_valid(), "sanity");
555 int reg_enc = reg->raw_encoding();
556 assert(reg_enc == -1 || is_valid_encoding(reg_enc), "sanity");
557 return reg_enc;
558 }
559
560 static int raw_encode(XMMRegister xmmreg) {
561 assert(xmmreg == xnoreg || xmmreg->is_valid(), "sanity");
562 int xmmreg_enc = xmmreg->raw_encoding();
563 assert(xmmreg_enc == -1 || is_valid_encoding(xmmreg_enc), "sanity");
564 return xmmreg_enc;
565 }
566
567 static int raw_encode(KRegister kreg) {
568 assert(kreg == knoreg || kreg->is_valid(), "sanity");
569 int kreg_enc = kreg->raw_encoding();
570 assert(kreg_enc == -1 || is_valid_encoding(kreg_enc), "sanity");
571 return kreg_enc;
572 }
573
574 static int modrm_encoding(int mod, int dst_enc, int src_enc) {
575 return (mod & 3) << 6 | (dst_enc & 7) << 3 | (src_enc & 7);
576 }
577
578 static int sib_encoding(Address::ScaleFactor scale, int index_enc, int base_enc) {
579 return (scale & 3) << 6 | (index_enc & 7) << 3 | (base_enc & 7);
580 }
581
582 inline void Assembler::emit_modrm(int mod, int dst_enc, int src_enc) {
583 assert((mod & 3) != 0b11, "forbidden");
584 int modrm = modrm_encoding(mod, dst_enc, src_enc);
585 emit_int8(modrm);
586 }
587
588 inline void Assembler::emit_modrm_disp8(int mod, int dst_enc, int src_enc,
589 int disp) {
590 int modrm = modrm_encoding(mod, dst_enc, src_enc);
591 emit_int16(modrm, disp & 0xFF);
592 }
593
594 inline void Assembler::emit_modrm_sib(int mod, int dst_enc, int src_enc,
595 Address::ScaleFactor scale, int index_enc, int base_enc) {
596 int modrm = modrm_encoding(mod, dst_enc, src_enc);
597 int sib = sib_encoding(scale, index_enc, base_enc);
598 emit_int16(modrm, sib);
599 }
600
601 inline void Assembler::emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
602 Address::ScaleFactor scale, int index_enc, int base_enc,
603 int disp) {
604 int modrm = modrm_encoding(mod, dst_enc, src_enc);
605 int sib = sib_encoding(scale, index_enc, base_enc);
606 emit_int24(modrm, sib, disp & 0xFF);
607 }
608
609 void Assembler::emit_operand_helper(int reg_enc, int base_enc, int index_enc,
610 Address::ScaleFactor scale, int disp,
611 RelocationHolder const& rspec,
612 int post_addr_length) {
613 bool no_relocation = (rspec.type() == relocInfo::none);
614
615 if (is_valid_encoding(base_enc)) {
616 if (is_valid_encoding(index_enc)) {
617 assert(scale != Address::no_scale, "inconsistent address");
618 // [base + index*scale + disp]
619 if (disp == 0 && no_relocation &&
620 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
621 // [base + index*scale]
622 // [00 reg 100][ss index base]
623 emit_modrm_sib(0b00, reg_enc, 0b100,
624 scale, index_enc, base_enc);
625 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
626 // [base + index*scale + imm8]
627 // [01 reg 100][ss index base] imm8
628 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
629 scale, index_enc, base_enc,
630 disp);
631 } else {
632 // [base + index*scale + disp32]
633 // [10 reg 100][ss index base] disp32
634 emit_modrm_sib(0b10, reg_enc, 0b100,
635 scale, index_enc, base_enc);
636 emit_data(disp, rspec, disp32_operand);
637 }
638 } else if (base_enc == rsp->encoding() LP64_ONLY(|| base_enc == r12->encoding())) {
639 // [rsp + disp]
640 if (disp == 0 && no_relocation) {
641 // [rsp]
642 // [00 reg 100][00 100 100]
643 emit_modrm_sib(0b00, reg_enc, 0b100,
644 Address::times_1, 0b100, 0b100);
645 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
646 // [rsp + imm8]
647 // [01 reg 100][00 100 100] disp8
648 emit_modrm_sib_disp8(0b01, reg_enc, 0b100,
649 Address::times_1, 0b100, 0b100,
650 disp);
651 } else {
652 // [rsp + imm32]
653 // [10 reg 100][00 100 100] disp32
654 emit_modrm_sib(0b10, reg_enc, 0b100,
655 Address::times_1, 0b100, 0b100);
656 emit_data(disp, rspec, disp32_operand);
657 }
658 } else {
659 // [base + disp]
660 assert(base_enc != rsp->encoding() LP64_ONLY(&& base_enc != r12->encoding()), "illegal addressing mode");
661 if (disp == 0 && no_relocation &&
662 base_enc != rbp->encoding() LP64_ONLY(&& base_enc != r13->encoding())) {
663 // [base]
664 // [00 reg base]
665 emit_modrm(0, reg_enc, base_enc);
666 } else if (emit_compressed_disp_byte(disp) && no_relocation) {
667 // [base + disp8]
668 // [01 reg base] disp8
669 emit_modrm_disp8(0b01, reg_enc, base_enc,
670 disp);
671 } else {
672 // [base + disp32]
673 // [10 reg base] disp32
674 emit_modrm(0b10, reg_enc, base_enc);
675 emit_data(disp, rspec, disp32_operand);
676 }
677 }
678 } else {
679 if (is_valid_encoding(index_enc)) {
680 assert(scale != Address::no_scale, "inconsistent address");
681 // base == noreg
682 // [index*scale + disp]
683 // [00 reg 100][ss index 101] disp32
684 emit_modrm_sib(0b00, reg_enc, 0b100,
685 scale, index_enc, 0b101 /* no base */);
686 emit_data(disp, rspec, disp32_operand);
687 } else if (!no_relocation) {
688 // base == noreg, index == noreg
689 // [disp] (64bit) RIP-RELATIVE (32bit) abs
690 // [00 reg 101] disp32
691
692 emit_modrm(0b00, reg_enc, 0b101 /* no base */);
693 // Note that the RIP-rel. correction applies to the generated
694 // disp field, but _not_ to the target address in the rspec.
695
696 // disp was created by converting the target address minus the pc
697 // at the start of the instruction. That needs more correction here.
698 // intptr_t disp = target - next_ip;
699 assert(inst_mark() != nullptr, "must be inside InstructionMark");
700 address next_ip = pc() + sizeof(int32_t) + post_addr_length;
701 int64_t adjusted = disp;
702 // Do rip-rel adjustment for 64bit
703 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
704 assert(is_simm32(adjusted),
705 "must be 32bit offset (RIP relative address)");
706 emit_data((int32_t) adjusted, rspec, disp32_operand);
707
708 } else {
709 // base == noreg, index == noreg, no_relocation == true
710 // 32bit never did this, did everything as the rip-rel/disp code above
711 // [disp] ABSOLUTE
712 // [00 reg 100][00 100 101] disp32
713 emit_modrm_sib(0b00, reg_enc, 0b100 /* no base */,
714 Address::times_1, 0b100, 0b101);
715 emit_data(disp, rspec, disp32_operand);
716 }
717 }
718 }
719
720 void Assembler::emit_operand(Register reg, Register base, Register index,
721 Address::ScaleFactor scale, int disp,
722 RelocationHolder const& rspec,
723 int post_addr_length) {
724 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
725 emit_operand_helper(raw_encode(reg), raw_encode(base), raw_encode(index),
726 scale, disp, rspec, post_addr_length);
727
728 }
729 void Assembler::emit_operand(XMMRegister xmmreg, Register base, Register index,
730 Address::ScaleFactor scale, int disp,
731 RelocationHolder const& rspec,
732 int post_addr_length) {
733 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
734 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
735 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(index),
736 scale, disp, rspec, post_addr_length);
737 }
738
739 void Assembler::emit_operand(XMMRegister xmmreg, Register base, XMMRegister xmmindex,
740 Address::ScaleFactor scale, int disp,
741 RelocationHolder const& rspec,
742 int post_addr_length) {
743 assert(xmmreg->encoding() < 16 || UseAVX > 2, "not supported");
744 assert(xmmindex->encoding() < 16 || UseAVX > 2, "not supported");
745 emit_operand_helper(raw_encode(xmmreg), raw_encode(base), raw_encode(xmmindex),
746 scale, disp, rspec, post_addr_length);
747 }
748
749 void Assembler::emit_operand(KRegister kreg, Address adr,
750 int post_addr_length) {
751 emit_operand(kreg, adr._base, adr._index, adr._scale, adr._disp,
752 adr._rspec,
753 post_addr_length);
754 }
755
756 void Assembler::emit_operand(KRegister kreg, Register base, Register index,
757 Address::ScaleFactor scale, int disp,
758 RelocationHolder const& rspec,
759 int post_addr_length) {
760 assert(!index->is_valid() || index != rsp, "illegal addressing mode");
761 emit_operand_helper(raw_encode(kreg), raw_encode(base), raw_encode(index),
762 scale, disp, rspec, post_addr_length);
763 }
764
765 // Secret local extension to Assembler::WhichOperand:
766 #define end_pc_operand (_WhichOperand_limit)
767
768 address Assembler::locate_operand(address inst, WhichOperand which) {
769 // Decode the given instruction, and return the address of
770 // an embedded 32-bit operand word.
771
772 // If "which" is disp32_operand, selects the displacement portion
773 // of an effective address specifier.
774 // If "which" is imm64_operand, selects the trailing immediate constant.
775 // If "which" is call32_operand, selects the displacement of a call or jump.
776 // Caller is responsible for ensuring that there is such an operand,
777 // and that it is 32/64 bits wide.
778
779 // If "which" is end_pc_operand, find the end of the instruction.
780
781 address ip = inst;
782 bool is_64bit = false;
783
784 debug_only(bool has_disp32 = false);
785 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
786
787 again_after_prefix:
788 switch (0xFF & *ip++) {
789
790 // These convenience macros generate groups of "case" labels for the switch.
791 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
792 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
793 case (x)+4: case (x)+5: case (x)+6: case (x)+7
794 #define REP16(x) REP8((x)+0): \
795 case REP8((x)+8)
796
797 case CS_segment:
798 case SS_segment:
799 case DS_segment:
800 case ES_segment:
801 case FS_segment:
802 case GS_segment:
803 // Seems dubious
804 LP64_ONLY(assert(false, "shouldn't have that prefix"));
805 assert(ip == inst+1, "only one prefix allowed");
806 goto again_after_prefix;
807
808 case 0x67:
809 case REX:
810 case REX_B:
811 case REX_X:
812 case REX_XB:
813 case REX_R:
814 case REX_RB:
815 case REX_RX:
816 case REX_RXB:
817 NOT_LP64(assert(false, "64bit prefixes"));
818 goto again_after_prefix;
819
820 case REX_W:
821 case REX_WB:
822 case REX_WX:
823 case REX_WXB:
824 case REX_WR:
825 case REX_WRB:
826 case REX_WRX:
827 case REX_WRXB:
828 NOT_LP64(assert(false, "64bit prefixes"));
829 is_64bit = true;
830 goto again_after_prefix;
831
832 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
833 case 0x88: // movb a, r
834 case 0x89: // movl a, r
835 case 0x8A: // movb r, a
836 case 0x8B: // movl r, a
837 case 0x8F: // popl a
838 debug_only(has_disp32 = true);
839 break;
840
841 case 0x68: // pushq #32
842 if (which == end_pc_operand) {
843 return ip + 4;
844 }
845 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
846 return ip; // not produced by emit_operand
847
848 case 0x66: // movw ... (size prefix)
849 again_after_size_prefix2:
850 switch (0xFF & *ip++) {
851 case REX:
852 case REX_B:
853 case REX_X:
854 case REX_XB:
855 case REX_R:
856 case REX_RB:
857 case REX_RX:
858 case REX_RXB:
859 case REX_W:
860 case REX_WB:
861 case REX_WX:
862 case REX_WXB:
863 case REX_WR:
864 case REX_WRB:
865 case REX_WRX:
866 case REX_WRXB:
867 NOT_LP64(assert(false, "64bit prefix found"));
868 goto again_after_size_prefix2;
869 case 0x8B: // movw r, a
870 case 0x89: // movw a, r
871 debug_only(has_disp32 = true);
872 break;
873 case 0xC7: // movw a, #16
874 debug_only(has_disp32 = true);
875 tail_size = 2; // the imm16
876 break;
877 case 0x0F: // several SSE/SSE2 variants
878 ip--; // reparse the 0x0F
879 goto again_after_prefix;
880 default:
881 ShouldNotReachHere();
882 }
883 break;
884
885 case REP8(0xB8): // movl/q r, #32/#64(oop?)
886 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
887 // these asserts are somewhat nonsensical
888 #ifndef _LP64
889 assert(which == imm_operand || which == disp32_operand,
890 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
891 #else
892 assert((which == call32_operand || which == imm_operand) && is_64bit ||
893 which == narrow_oop_operand && !is_64bit,
894 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
895 #endif // _LP64
896 return ip;
897
898 case 0x69: // imul r, a, #32
899 case 0xC7: // movl a, #32(oop?)
900 tail_size = 4;
901 debug_only(has_disp32 = true); // has both kinds of operands!
902 break;
903
904 case 0x0F: // movx..., etc.
905 switch (0xFF & *ip++) {
906 case 0x3A: // pcmpestri
907 tail_size = 1;
908 case 0x38: // ptest, pmovzxbw
909 ip++; // skip opcode
910 debug_only(has_disp32 = true); // has both kinds of operands!
911 break;
912
913 case 0x70: // pshufd r, r/a, #8
914 debug_only(has_disp32 = true); // has both kinds of operands!
915 case 0x73: // psrldq r, #8
916 tail_size = 1;
917 break;
918
919 case 0x10: // movups
920 case 0x11: // movups
921 case 0x12: // movlps
922 case 0x28: // movaps
923 case 0x2E: // ucomiss
924 case 0x2F: // comiss
925 case 0x54: // andps
926 case 0x55: // andnps
927 case 0x56: // orps
928 case 0x57: // xorps
929 case 0x58: // addpd
930 case 0x59: // mulpd
931 case 0x6E: // movd
932 case 0x7E: // movd
933 case 0x6F: // movdq
934 case 0x7F: // movdq
935 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
936 case 0xFE: // paddd
937 debug_only(has_disp32 = true);
938 break;
939
940 case 0xAD: // shrd r, a, %cl
941 case 0xAF: // imul r, a
942 case 0xBE: // movsbl r, a (movsxb)
943 case 0xBF: // movswl r, a (movsxw)
944 case 0xB6: // movzbl r, a (movzxb)
945 case 0xB7: // movzwl r, a (movzxw)
946 case REP16(0x40): // cmovl cc, r, a
947 case 0xB0: // cmpxchgb
948 case 0xB1: // cmpxchg
949 case 0xC1: // xaddl
950 case 0xC7: // cmpxchg8
951 case REP16(0x90): // setcc a
952 debug_only(has_disp32 = true);
953 // fall out of the switch to decode the address
954 break;
955
956 case 0xC4: // pinsrw r, a, #8
957 debug_only(has_disp32 = true);
958 case 0xC5: // pextrw r, r, #8
959 tail_size = 1; // the imm8
960 break;
961
962 case 0xAC: // shrd r, a, #8
963 debug_only(has_disp32 = true);
964 tail_size = 1; // the imm8
965 break;
966
967 case REP16(0x80): // jcc rdisp32
968 if (which == end_pc_operand) return ip + 4;
969 assert(which == call32_operand, "jcc has no disp32 or imm");
970 return ip;
971 default:
972 ShouldNotReachHere();
973 }
974 break;
975
976 case 0x81: // addl a, #32; addl r, #32
977 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
978 // on 32bit in the case of cmpl, the imm might be an oop
979 tail_size = 4;
980 debug_only(has_disp32 = true); // has both kinds of operands!
981 break;
982
983 case 0x83: // addl a, #8; addl r, #8
984 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
985 debug_only(has_disp32 = true); // has both kinds of operands!
986 tail_size = 1;
987 break;
988
989 case 0x15: // adc rax, #32
990 case 0x05: // add rax, #32
991 case 0x25: // and rax, #32
992 case 0x3D: // cmp rax, #32
993 case 0x0D: // or rax, #32
994 case 0x1D: // sbb rax, #32
995 case 0x2D: // sub rax, #32
996 case 0x35: // xor rax, #32
997 return which == end_pc_operand ? ip + 4 : ip;
998
999 case 0x9B:
1000 switch (0xFF & *ip++) {
1001 case 0xD9: // fnstcw a
1002 debug_only(has_disp32 = true);
1003 break;
1004 default:
1005 ShouldNotReachHere();
1006 }
1007 break;
1008
1009 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
1010 case REP4(0x10): // adc...
1011 case REP4(0x20): // and...
1012 case REP4(0x30): // xor...
1013 case REP4(0x08): // or...
1014 case REP4(0x18): // sbb...
1015 case REP4(0x28): // sub...
1016 case 0xF7: // mull a
1017 case 0x8D: // lea r, a
1018 case 0x87: // xchg r, a
1019 case REP4(0x38): // cmp...
1020 case 0x85: // test r, a
1021 debug_only(has_disp32 = true); // has both kinds of operands!
1022 break;
1023
1024 case 0xA8: // testb rax, #8
1025 return which == end_pc_operand ? ip + 1 : ip;
1026 case 0xA9: // testl/testq rax, #32
1027 return which == end_pc_operand ? ip + 4 : ip;
1028
1029 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
1030 case 0xC6: // movb a, #8
1031 case 0x80: // cmpb a, #8
1032 case 0x6B: // imul r, a, #8
1033 debug_only(has_disp32 = true); // has both kinds of operands!
1034 tail_size = 1; // the imm8
1035 break;
1036
1037 case 0xC4: // VEX_3bytes
1038 case 0xC5: // VEX_2bytes
1039 assert((UseAVX > 0), "shouldn't have VEX prefix");
1040 assert(ip == inst+1, "no prefixes allowed");
1041 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
1042 // but they have prefix 0x0F and processed when 0x0F processed above.
1043 //
1044 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
1045 // instructions (these instructions are not supported in 64-bit mode).
1046 // To distinguish them bits [7:6] are set in the VEX second byte since
1047 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
1048 // those VEX bits REX and vvvv bits are inverted.
1049 //
1050 // Fortunately C2 doesn't generate these instructions so we don't need
1051 // to check for them in product version.
1052
1053 // Check second byte
1054 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
1055
1056 int vex_opcode;
1057 // First byte
1058 if ((0xFF & *inst) == VEX_3bytes) {
1059 vex_opcode = VEX_OPCODE_MASK & *ip;
1060 ip++; // third byte
1061 is_64bit = ((VEX_W & *ip) == VEX_W);
1062 } else {
1063 vex_opcode = VEX_OPCODE_0F;
1064 }
1065 ip++; // opcode
1066 // To find the end of instruction (which == end_pc_operand).
1067 switch (vex_opcode) {
1068 case VEX_OPCODE_0F:
1069 switch (0xFF & *ip) {
1070 case 0x70: // pshufd r, r/a, #8
1071 case 0x71: // ps[rl|ra|ll]w r, #8
1072 case 0x72: // ps[rl|ra|ll]d r, #8
1073 case 0x73: // ps[rl|ra|ll]q r, #8
1074 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
1075 case 0xC4: // pinsrw r, r, r/a, #8
1076 case 0xC5: // pextrw r/a, r, #8
1077 case 0xC6: // shufp[s|d] r, r, r/a, #8
1078 tail_size = 1; // the imm8
1079 break;
1080 }
1081 break;
1082 case VEX_OPCODE_0F_3A:
1083 tail_size = 1;
1084 break;
1085 }
1086 ip++; // skip opcode
1087 debug_only(has_disp32 = true); // has both kinds of operands!
1088 break;
1089
1090 case 0x62: // EVEX_4bytes
1091 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
1092 assert(ip == inst+1, "no prefixes allowed");
1093 // no EVEX collisions, all instructions that have 0x62 opcodes
1094 // have EVEX versions and are subopcodes of 0x66
1095 ip++; // skip P0 and examine W in P1
1096 is_64bit = ((VEX_W & *ip) == VEX_W);
1097 ip++; // move to P2
1098 ip++; // skip P2, move to opcode
1099 // To find the end of instruction (which == end_pc_operand).
1100 switch (0xFF & *ip) {
1101 case 0x22: // pinsrd r, r/a, #8
1102 case 0x61: // pcmpestri r, r/a, #8
1103 case 0x70: // pshufd r, r/a, #8
1104 case 0x73: // psrldq r, #8
1105 case 0x1f: // evpcmpd/evpcmpq
1106 case 0x3f: // evpcmpb/evpcmpw
1107 tail_size = 1; // the imm8
1108 break;
1109 default:
1110 break;
1111 }
1112 ip++; // skip opcode
1113 debug_only(has_disp32 = true); // has both kinds of operands!
1114 break;
1115
1116 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
1117 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
1118 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
1119 case 0xDD: // fld_d a; fst_d a; fstp_d a
1120 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
1121 case 0xDF: // fild_d a; fistp_d a
1122 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
1123 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
1124 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
1125 debug_only(has_disp32 = true);
1126 break;
1127
1128 case 0xE8: // call rdisp32
1129 case 0xE9: // jmp rdisp32
1130 if (which == end_pc_operand) return ip + 4;
1131 assert(which == call32_operand, "call has no disp32 or imm");
1132 return ip;
1133
1134 case 0xF0: // Lock
1135 goto again_after_prefix;
1136
1137 case 0xF3: // For SSE
1138 case 0xF2: // For SSE2
1139 switch (0xFF & *ip++) {
1140 case REX:
1141 case REX_B:
1142 case REX_X:
1143 case REX_XB:
1144 case REX_R:
1145 case REX_RB:
1146 case REX_RX:
1147 case REX_RXB:
1148 case REX_W:
1149 case REX_WB:
1150 case REX_WX:
1151 case REX_WXB:
1152 case REX_WR:
1153 case REX_WRB:
1154 case REX_WRX:
1155 case REX_WRXB:
1156 NOT_LP64(assert(false, "found 64bit prefix"));
1157 ip++;
1158 default:
1159 ip++;
1160 }
1161 debug_only(has_disp32 = true); // has both kinds of operands!
1162 break;
1163
1164 default:
1165 ShouldNotReachHere();
1166
1167 #undef REP8
1168 #undef REP16
1169 }
1170
1171 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
1172 #ifdef _LP64
1173 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1174 #else
1175 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1176 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1177 #endif // LP64
1178 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1179
1180 // parse the output of emit_operand
1181 int op2 = 0xFF & *ip++;
1182 int base = op2 & 0x07;
1183 int op3 = -1;
1184 const int b100 = 4;
1185 const int b101 = 5;
1186 if (base == b100 && (op2 >> 6) != 3) {
1187 op3 = 0xFF & *ip++;
1188 base = op3 & 0x07; // refetch the base
1189 }
1190 // now ip points at the disp (if any)
1191
1192 switch (op2 >> 6) {
1193 case 0:
1194 // [00 reg 100][ss index base]
1195 // [00 reg 100][00 100 esp]
1196 // [00 reg base]
1197 // [00 reg 100][ss index 101][disp32]
1198 // [00 reg 101] [disp32]
1199
1200 if (base == b101) {
1201 if (which == disp32_operand)
1202 return ip; // caller wants the disp32
1203 ip += 4; // skip the disp32
1204 }
1205 break;
1206
1207 case 1:
1208 // [01 reg 100][ss index base][disp8]
1209 // [01 reg 100][00 100 esp][disp8]
1210 // [01 reg base] [disp8]
1211 ip += 1; // skip the disp8
1212 break;
1213
1214 case 2:
1215 // [10 reg 100][ss index base][disp32]
1216 // [10 reg 100][00 100 esp][disp32]
1217 // [10 reg base] [disp32]
1218 if (which == disp32_operand)
1219 return ip; // caller wants the disp32
1220 ip += 4; // skip the disp32
1221 break;
1222
1223 case 3:
1224 // [11 reg base] (not a memory addressing mode)
1225 break;
1226 }
1227
1228 if (which == end_pc_operand) {
1229 return ip + tail_size;
1230 }
1231
1232 #ifdef _LP64
1233 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1234 #else
1235 assert(which == imm_operand, "instruction has only an imm field");
1236 #endif // LP64
1237 return ip;
1238 }
1239
1240 address Assembler::locate_next_instruction(address inst) {
1241 // Secretly share code with locate_operand:
1242 return locate_operand(inst, end_pc_operand);
1243 }
1244
1245
1246 #ifdef ASSERT
1247 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1248 address inst = inst_mark();
1249 assert(inst != nullptr && inst < pc(), "must point to beginning of instruction");
1250 address opnd;
1251
1252 Relocation* r = rspec.reloc();
1253 if (r->type() == relocInfo::none) {
1254 return;
1255 } else if (r->is_call() || format == call32_operand) {
1256 // assert(format == imm32_operand, "cannot specify a nonzero format");
1257 opnd = locate_operand(inst, call32_operand);
1258 } else if (r->is_data()) {
1259 assert(format == imm_operand || format == disp32_operand
1260 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1261 opnd = locate_operand(inst, (WhichOperand)format);
1262 } else {
1263 assert(format == imm_operand, "cannot specify a format");
1264 return;
1265 }
1266 assert(opnd == pc(), "must put operand where relocs can find it");
1267 }
1268 #endif // ASSERT
1269
1270 void Assembler::emit_operand(Register reg, Address adr, int post_addr_length) {
1271 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1272 }
1273
1274 void Assembler::emit_operand(XMMRegister reg, Address adr, int post_addr_length) {
1275 if (adr.isxmmindex()) {
1276 emit_operand(reg, adr._base, adr._xmmindex, adr._scale, adr._disp, adr._rspec, post_addr_length);
1277 } else {
1278 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
1279 }
1280 }
1281
1282 // Now the Assembler instructions (identical for 32/64 bits)
1283
1284 void Assembler::adcl(Address dst, int32_t imm32) {
1285 InstructionMark im(this);
1286 prefix(dst);
1287 emit_arith_operand(0x81, rdx, dst, imm32);
1288 }
1289
1290 void Assembler::adcl(Address dst, Register src) {
1291 InstructionMark im(this);
1292 prefix(dst, src);
1293 emit_int8(0x11);
1294 emit_operand(src, dst, 0);
1295 }
1296
1297 void Assembler::adcl(Register dst, int32_t imm32) {
1298 prefix(dst);
1299 emit_arith(0x81, 0xD0, dst, imm32);
1300 }
1301
1302 void Assembler::adcl(Register dst, Address src) {
1303 InstructionMark im(this);
1304 prefix(src, dst);
1305 emit_int8(0x13);
1306 emit_operand(dst, src, 0);
1307 }
1308
1309 void Assembler::adcl(Register dst, Register src) {
1310 (void) prefix_and_encode(dst->encoding(), src->encoding());
1311 emit_arith(0x13, 0xC0, dst, src);
1312 }
1313
1314 void Assembler::addl(Address dst, int32_t imm32) {
1315 InstructionMark im(this);
1316 prefix(dst);
1317 emit_arith_operand(0x81, rax, dst, imm32);
1318 }
1319
1320 void Assembler::addb(Address dst, int imm8) {
1321 InstructionMark im(this);
1322 prefix(dst);
1323 emit_int8((unsigned char)0x80);
1324 emit_operand(rax, dst, 1);
1325 emit_int8(imm8);
1326 }
1327
1328 void Assembler::addb(Address dst, Register src) {
1329 InstructionMark im(this);
1330 prefix(dst, src);
1331 emit_int8(0x00);
1332 emit_operand(src, dst, 0);
1333 }
1334
1335 void Assembler::addw(Register dst, Register src) {
1336 emit_int8(0x66);
1337 (void)prefix_and_encode(dst->encoding(), src->encoding());
1338 emit_arith(0x03, 0xC0, dst, src);
1339 }
1340
1341 void Assembler::addw(Address dst, int imm16) {
1342 InstructionMark im(this);
1343 emit_int8(0x66);
1344 prefix(dst);
1345 emit_int8((unsigned char)0x81);
1346 emit_operand(rax, dst, 2);
1347 emit_int16(imm16);
1348 }
1349
1350 void Assembler::addw(Address dst, Register src) {
1351 InstructionMark im(this);
1352 emit_int8(0x66);
1353 prefix(dst, src);
1354 emit_int8(0x01);
1355 emit_operand(src, dst, 0);
1356 }
1357
1358 void Assembler::addl(Address dst, Register src) {
1359 InstructionMark im(this);
1360 prefix(dst, src);
1361 emit_int8(0x01);
1362 emit_operand(src, dst, 0);
1363 }
1364
1365 void Assembler::addl(Register dst, int32_t imm32) {
1366 prefix(dst);
1367 emit_arith(0x81, 0xC0, dst, imm32);
1368 }
1369
1370 void Assembler::addl(Register dst, Address src) {
1371 InstructionMark im(this);
1372 prefix(src, dst);
1373 emit_int8(0x03);
1374 emit_operand(dst, src, 0);
1375 }
1376
1377 void Assembler::addl(Register dst, Register src) {
1378 (void) prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_arith(0x03, 0xC0, dst, src);
1380 }
1381
1382 void Assembler::addr_nop_4() {
1383 assert(UseAddressNop, "no CPU support");
1384 // 4 bytes: NOP DWORD PTR [EAX+0]
1385 emit_int32(0x0F,
1386 0x1F,
1387 0x40, // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1388 0); // 8-bits offset (1 byte)
1389 }
1390
1391 void Assembler::addr_nop_5() {
1392 assert(UseAddressNop, "no CPU support");
1393 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1394 emit_int32(0x0F,
1395 0x1F,
1396 0x44, // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1397 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1398 emit_int8(0); // 8-bits offset (1 byte)
1399 }
1400
1401 void Assembler::addr_nop_7() {
1402 assert(UseAddressNop, "no CPU support");
1403 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1404 emit_int24(0x0F,
1405 0x1F,
1406 (unsigned char)0x80);
1407 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1408 emit_int32(0); // 32-bits offset (4 bytes)
1409 }
1410
1411 void Assembler::addr_nop_8() {
1412 assert(UseAddressNop, "no CPU support");
1413 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1414 emit_int32(0x0F,
1415 0x1F,
1416 (unsigned char)0x84,
1417 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1418 0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1419 emit_int32(0); // 32-bits offset (4 bytes)
1420 }
1421
1422 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1423 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1424 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1425 attributes.set_rex_vex_w_reverted();
1426 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1427 emit_int16(0x58, (0xC0 | encode));
1428 }
1429
1430 void Assembler::addsd(XMMRegister dst, Address src) {
1431 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1432 InstructionMark im(this);
1433 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1434 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1435 attributes.set_rex_vex_w_reverted();
1436 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1437 emit_int8(0x58);
1438 emit_operand(dst, src, 0);
1439 }
1440
1441 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1442 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1443 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1444 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1445 emit_int16(0x58, (0xC0 | encode));
1446 }
1447
1448 void Assembler::addss(XMMRegister dst, Address src) {
1449 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1450 InstructionMark im(this);
1451 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1452 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1453 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1454 emit_int8(0x58);
1455 emit_operand(dst, src, 0);
1456 }
1457
1458 void Assembler::aesdec(XMMRegister dst, Address src) {
1459 assert(VM_Version::supports_aes(), "");
1460 InstructionMark im(this);
1461 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1462 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1463 emit_int8((unsigned char)0xDE);
1464 emit_operand(dst, src, 0);
1465 }
1466
1467 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1468 assert(VM_Version::supports_aes(), "");
1469 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1470 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1471 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1472 }
1473
1474 void Assembler::vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1475 assert(VM_Version::supports_avx512_vaes(), "");
1476 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1477 attributes.set_is_evex_instruction();
1478 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1479 emit_int16((unsigned char)0xDE, (0xC0 | encode));
1480 }
1481
1482
1483 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1484 assert(VM_Version::supports_aes(), "");
1485 InstructionMark im(this);
1486 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1487 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1488 emit_int8((unsigned char)0xDF);
1489 emit_operand(dst, src, 0);
1490 }
1491
1492 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1493 assert(VM_Version::supports_aes(), "");
1494 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1495 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1496 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1497 }
1498
1499 void Assembler::vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1500 assert(VM_Version::supports_avx512_vaes(), "");
1501 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1502 attributes.set_is_evex_instruction();
1503 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1504 emit_int16((unsigned char)0xDF, (0xC0 | encode));
1505 }
1506
1507 void Assembler::aesenc(XMMRegister dst, Address src) {
1508 assert(VM_Version::supports_aes(), "");
1509 InstructionMark im(this);
1510 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1511 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1512 emit_int8((unsigned char)0xDC);
1513 emit_operand(dst, src, 0);
1514 }
1515
1516 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1517 assert(VM_Version::supports_aes(), "");
1518 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1519 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1520 emit_int16((unsigned char)0xDC, 0xC0 | encode);
1521 }
1522
1523 void Assembler::vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1524 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1525 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1526 attributes.set_is_evex_instruction();
1527 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1528 emit_int16((unsigned char)0xDC, (0xC0 | encode));
1529 }
1530
1531 void Assembler::aesenclast(XMMRegister dst, Address src) {
1532 assert(VM_Version::supports_aes(), "");
1533 InstructionMark im(this);
1534 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1535 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1536 emit_int8((unsigned char)0xDD);
1537 emit_operand(dst, src, 0);
1538 }
1539
1540 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1541 assert(VM_Version::supports_aes(), "");
1542 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1543 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1544 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1545 }
1546
1547 void Assembler::vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
1548 assert(VM_Version::supports_avx512_vaes(), "requires vaes support/enabling");
1549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1550 attributes.set_is_evex_instruction();
1551 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1552 emit_int16((unsigned char)0xDD, (0xC0 | encode));
1553 }
1554
1555 void Assembler::andb(Address dst, Register src) {
1556 InstructionMark im(this);
1557 prefix(dst, src, true);
1558 emit_int8(0x20);
1559 emit_operand(src, dst, 0);
1560 }
1561
1562 void Assembler::andw(Register dst, Register src) {
1563 (void)prefix_and_encode(dst->encoding(), src->encoding());
1564 emit_arith(0x23, 0xC0, dst, src);
1565 }
1566
1567 void Assembler::andl(Address dst, int32_t imm32) {
1568 InstructionMark im(this);
1569 prefix(dst);
1570 emit_arith_operand(0x81, as_Register(4), dst, imm32);
1571 }
1572
1573 void Assembler::andl(Register dst, int32_t imm32) {
1574 prefix(dst);
1575 emit_arith(0x81, 0xE0, dst, imm32);
1576 }
1577
1578 void Assembler::andl(Address dst, Register src) {
1579 InstructionMark im(this);
1580 prefix(dst, src);
1581 emit_int8(0x21);
1582 emit_operand(src, dst, 0);
1583 }
1584
1585 void Assembler::andl(Register dst, Address src) {
1586 InstructionMark im(this);
1587 prefix(src, dst);
1588 emit_int8(0x23);
1589 emit_operand(dst, src, 0);
1590 }
1591
1592 void Assembler::andl(Register dst, Register src) {
1593 (void) prefix_and_encode(dst->encoding(), src->encoding());
1594 emit_arith(0x23, 0xC0, dst, src);
1595 }
1596
1597 void Assembler::andnl(Register dst, Register src1, Register src2) {
1598 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1599 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1600 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1601 emit_int16((unsigned char)0xF2, (0xC0 | encode));
1602 }
1603
1604 void Assembler::andnl(Register dst, Register src1, Address src2) {
1605 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1606 InstructionMark im(this);
1607 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1608 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1609 emit_int8((unsigned char)0xF2);
1610 emit_operand(dst, src2, 0);
1611 }
1612
1613 void Assembler::bsfl(Register dst, Register src) {
1614 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1615 emit_int24(0x0F,
1616 (unsigned char)0xBC,
1617 0xC0 | encode);
1618 }
1619
1620 void Assembler::bsrl(Register dst, Register src) {
1621 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1622 emit_int24(0x0F,
1623 (unsigned char)0xBD,
1624 0xC0 | encode);
1625 }
1626
1627 void Assembler::bswapl(Register reg) { // bswap
1628 int encode = prefix_and_encode(reg->encoding());
1629 emit_int16(0x0F, (0xC8 | encode));
1630 }
1631
1632 void Assembler::blsil(Register dst, Register src) {
1633 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1634 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1635 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1636 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1637 }
1638
1639 void Assembler::blsil(Register dst, Address src) {
1640 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1641 InstructionMark im(this);
1642 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1643 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1644 emit_int8((unsigned char)0xF3);
1645 emit_operand(rbx, src, 0);
1646 }
1647
1648 void Assembler::blsmskl(Register dst, Register src) {
1649 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1650 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1651 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1652 emit_int16((unsigned char)0xF3,
1653 0xC0 | encode);
1654 }
1655
1656 void Assembler::blsmskl(Register dst, Address src) {
1657 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1658 InstructionMark im(this);
1659 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1660 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1661 emit_int8((unsigned char)0xF3);
1662 emit_operand(rdx, src, 0);
1663 }
1664
1665 void Assembler::blsrl(Register dst, Register src) {
1666 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1667 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1668 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1669 emit_int16((unsigned char)0xF3, (0xC0 | encode));
1670 }
1671
1672 void Assembler::blsrl(Register dst, Address src) {
1673 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1674 InstructionMark im(this);
1675 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1676 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1677 emit_int8((unsigned char)0xF3);
1678 emit_operand(rcx, src, 0);
1679 }
1680
1681 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1682 // suspect disp32 is always good
1683 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1684
1685 if (L.is_bound()) {
1686 const int long_size = 5;
1687 int offs = (int)( target(L) - pc() );
1688 assert(offs <= 0, "assembler error");
1689 InstructionMark im(this);
1690 // 1110 1000 #32-bit disp
1691 emit_int8((unsigned char)0xE8);
1692 emit_data(offs - long_size, rtype, operand);
1693 } else {
1694 InstructionMark im(this);
1695 // 1110 1000 #32-bit disp
1696 L.add_patch_at(code(), locator());
1697
1698 emit_int8((unsigned char)0xE8);
1699 emit_data(int(0), rtype, operand);
1700 }
1701 }
1702
1703 void Assembler::call(Register dst) {
1704 int encode = prefix_and_encode(dst->encoding());
1705 emit_int16((unsigned char)0xFF, (0xD0 | encode));
1706 }
1707
1708
1709 void Assembler::call(Address adr) {
1710 InstructionMark im(this);
1711 prefix(adr);
1712 emit_int8((unsigned char)0xFF);
1713 emit_operand(rdx, adr, 0);
1714 }
1715
1716 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1717 InstructionMark im(this);
1718 emit_int8((unsigned char)0xE8);
1719 intptr_t disp = entry - (pc() + sizeof(int32_t));
1720 // Entry is null in case of a scratch emit.
1721 assert(entry == nullptr || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1722 // Technically, should use call32_operand, but this format is
1723 // implied by the fact that we're emitting a call instruction.
1724
1725 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1726 emit_data((int) disp, rspec, operand);
1727 }
1728
1729 void Assembler::cdql() {
1730 emit_int8((unsigned char)0x99);
1731 }
1732
1733 void Assembler::cld() {
1734 emit_int8((unsigned char)0xFC);
1735 }
1736
1737 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1738 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1739 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1740 emit_int24(0x0F,
1741 0x40 | cc,
1742 0xC0 | encode);
1743 }
1744
1745
1746 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1747 InstructionMark im(this);
1748 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1749 prefix(src, dst);
1750 emit_int16(0x0F, (0x40 | cc));
1751 emit_operand(dst, src, 0);
1752 }
1753
1754 void Assembler::cmpb(Address dst, int imm8) {
1755 InstructionMark im(this);
1756 prefix(dst);
1757 emit_int8((unsigned char)0x80);
1758 emit_operand(rdi, dst, 1);
1759 emit_int8(imm8);
1760 }
1761
1762 void Assembler::cmpl(Address dst, int32_t imm32) {
1763 InstructionMark im(this);
1764 prefix(dst);
1765 emit_arith_operand(0x81, as_Register(7), dst, imm32);
1766 }
1767
1768 void Assembler::cmpl(Register dst, int32_t imm32) {
1769 prefix(dst);
1770 emit_arith(0x81, 0xF8, dst, imm32);
1771 }
1772
1773 void Assembler::cmpl(Register dst, Register src) {
1774 (void) prefix_and_encode(dst->encoding(), src->encoding());
1775 emit_arith(0x3B, 0xC0, dst, src);
1776 }
1777
1778 void Assembler::cmpl(Register dst, Address src) {
1779 InstructionMark im(this);
1780 prefix(src, dst);
1781 emit_int8(0x3B);
1782 emit_operand(dst, src, 0);
1783 }
1784
1785 void Assembler::cmpl_imm32(Address dst, int32_t imm32) {
1786 InstructionMark im(this);
1787 prefix(dst);
1788 emit_arith_operand_imm32(0x81, as_Register(7), dst, imm32);
1789 }
1790
1791 void Assembler::cmpw(Address dst, int imm16) {
1792 InstructionMark im(this);
1793 emit_int8(0x66);
1794 prefix(dst);
1795 emit_int8((unsigned char)0x81);
1796 emit_operand(rdi, dst, 2);
1797 emit_int16(imm16);
1798 }
1799
1800 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1801 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1802 // The ZF is set if the compared values were equal, and cleared otherwise.
1803 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1804 InstructionMark im(this);
1805 prefix(adr, reg);
1806 emit_int16(0x0F, (unsigned char)0xB1);
1807 emit_operand(reg, adr, 0);
1808 }
1809
1810 void Assembler::cmpxchgw(Register reg, Address adr) { // cmpxchg
1811 InstructionMark im(this);
1812 size_prefix();
1813 prefix(adr, reg);
1814 emit_int16(0x0F, (unsigned char)0xB1);
1815 emit_operand(reg, adr, 0);
1816 }
1817
1818 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1819 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1820 // The ZF is set if the compared values were equal, and cleared otherwise.
1821 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1822 InstructionMark im(this);
1823 prefix(adr, reg, true);
1824 emit_int16(0x0F, (unsigned char)0xB0);
1825 emit_operand(reg, adr, 0);
1826 }
1827
1828 void Assembler::comisd(XMMRegister dst, Address src) {
1829 // NOTE: dbx seems to decode this as comiss even though the
1830 // 0x66 is there. Strangely ucomisd comes out correct
1831 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1832 InstructionMark im(this);
1833 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1834 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1835 attributes.set_rex_vex_w_reverted();
1836 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1837 emit_int8(0x2F);
1838 emit_operand(dst, src, 0);
1839 }
1840
1841 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1842 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1843 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1844 attributes.set_rex_vex_w_reverted();
1845 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1846 emit_int16(0x2F, (0xC0 | encode));
1847 }
1848
1849 void Assembler::comiss(XMMRegister dst, Address src) {
1850 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1851 InstructionMark im(this);
1852 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1853 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1854 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1855 emit_int8(0x2F);
1856 emit_operand(dst, src, 0);
1857 }
1858
1859 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1860 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1861 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1862 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1863 emit_int16(0x2F, (0xC0 | encode));
1864 }
1865
1866 void Assembler::cpuid() {
1867 emit_int16(0x0F, (unsigned char)0xA2);
1868 }
1869
1870 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1871 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1872 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1873 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1874 //
1875 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1876 //
1877 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1878 //
1879 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1880 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1881 assert(VM_Version::supports_sse4_2(), "");
1882 int8_t w = 0x01;
1883 Prefix p = Prefix_EMPTY;
1884
1885 emit_int8((unsigned char)0xF2);
1886 switch (sizeInBytes) {
1887 case 1:
1888 w = 0;
1889 break;
1890 case 2:
1891 case 4:
1892 break;
1893 LP64_ONLY(case 8:)
1894 // This instruction is not valid in 32 bits
1895 // Note:
1896 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1897 //
1898 // Page B - 72 Vol. 2C says
1899 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1900 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1901 // F0!!!
1902 // while 3 - 208 Vol. 2A
1903 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1904 //
1905 // the 0 on a last bit is reserved for a different flavor of this instruction :
1906 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1907 p = REX_W;
1908 break;
1909 default:
1910 assert(0, "Unsupported value for a sizeInBytes argument");
1911 break;
1912 }
1913 LP64_ONLY(prefix(crc, v, p);)
1914 emit_int32(0x0F,
1915 0x38,
1916 0xF0 | w,
1917 0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1918 }
1919
1920 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1921 assert(VM_Version::supports_sse4_2(), "");
1922 InstructionMark im(this);
1923 int8_t w = 0x01;
1924 Prefix p = Prefix_EMPTY;
1925
1926 emit_int8((uint8_t)0xF2);
1927 switch (sizeInBytes) {
1928 case 1:
1929 w = 0;
1930 break;
1931 case 2:
1932 case 4:
1933 break;
1934 LP64_ONLY(case 8:)
1935 // This instruction is not valid in 32 bits
1936 p = REX_W;
1937 break;
1938 default:
1939 assert(0, "Unsupported value for a sizeInBytes argument");
1940 break;
1941 }
1942 LP64_ONLY(prefix(crc, adr, p);)
1943 emit_int24(0x0F, 0x38, (0xF0 | w));
1944 emit_operand(crc, adr, 0);
1945 }
1946
1947 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1948 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1949 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1950 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1951 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1952 }
1953
1954 void Assembler::vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1955 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
1956 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
1957 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1958 emit_int16((unsigned char)0xE6, (0xC0 | encode));
1959 }
1960
1961 void Assembler::vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
1962 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1963 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1964 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1965 emit_int24(0x1D, (0xC0 | encode), imm8);
1966 }
1967
1968 void Assembler::evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len) {
1969 assert(VM_Version::supports_evex(), "");
1970 InstructionMark im(this);
1971 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
1972 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_64bit);
1973 attributes.reset_is_clear_context();
1974 attributes.set_embedded_opmask_register_specifier(mask);
1975 attributes.set_is_evex_instruction();
1976 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1977 emit_int8(0x1D);
1978 emit_operand(src, dst, 1);
1979 emit_int8(imm8);
1980 }
1981
1982 void Assembler::vcvtps2ph(Address dst, XMMRegister src, int imm8, int vector_len) {
1983 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1984 InstructionMark im(this);
1985 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /*uses_vl */ true);
1986 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
1987 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
1988 emit_int8(0x1D);
1989 emit_operand(src, dst, 1);
1990 emit_int8(imm8);
1991 }
1992
1993 void Assembler::vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len) {
1994 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
1995 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ true);
1996 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1997 emit_int16(0x13, (0xC0 | encode));
1998 }
1999
2000 void Assembler::vcvtph2ps(XMMRegister dst, Address src, int vector_len) {
2001 assert(VM_Version::supports_evex() || VM_Version::supports_f16c(), "");
2002 InstructionMark im(this);
2003 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /*uses_vl */ true);
2004 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
2005 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2006 emit_int8(0x13);
2007 emit_operand(dst, src, 0);
2008 }
2009
2010 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
2011 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2013 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2014 emit_int16(0x5B, (0xC0 | encode));
2015 }
2016
2017 void Assembler::vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2018 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2019 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2020 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2021 emit_int16(0x5B, (0xC0 | encode));
2022 }
2023
2024 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
2025 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2026 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2027 attributes.set_rex_vex_w_reverted();
2028 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2029 emit_int16(0x5A, (0xC0 | encode));
2030 }
2031
2032 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
2033 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2034 InstructionMark im(this);
2035 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2036 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2037 attributes.set_rex_vex_w_reverted();
2038 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2039 emit_int8(0x5A);
2040 emit_operand(dst, src, 0);
2041 }
2042
2043 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
2044 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2045 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2046 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2047 emit_int16(0x2A, (0xC0 | encode));
2048 }
2049
2050 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
2051 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2052 InstructionMark im(this);
2053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2054 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2055 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2056 emit_int8(0x2A);
2057 emit_operand(dst, src, 0);
2058 }
2059
2060 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
2061 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2062 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2063 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2064 emit_int16(0x2A, (0xC0 | encode));
2065 }
2066
2067 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
2068 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2069 InstructionMark im(this);
2070 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2071 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2072 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2073 emit_int8(0x2A);
2074 emit_operand(dst, src, 0);
2075 }
2076
2077 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
2078 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2079 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2080 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2081 emit_int16(0x2A, (0xC0 | encode));
2082 }
2083
2084 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
2085 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2086 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2088 emit_int16(0x5A, (0xC0 | encode));
2089 }
2090
2091 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
2092 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2093 InstructionMark im(this);
2094 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2095 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2096 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2097 emit_int8(0x5A);
2098 emit_operand(dst, src, 0);
2099 }
2100
2101
2102 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
2103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2104 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2105 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2106 emit_int16(0x2C, (0xC0 | encode));
2107 }
2108
2109 void Assembler::cvtss2sil(Register dst, XMMRegister src) {
2110 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2111 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2112 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2113 emit_int16(0x2D, (0xC0 | encode));
2114 }
2115
2116 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
2117 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2118 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2119 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2120 emit_int16(0x2C, (0xC0 | encode));
2121 }
2122
2123 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
2124 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2125 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2126 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2127 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2128 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2129 }
2130
2131 void Assembler::pabsb(XMMRegister dst, XMMRegister src) {
2132 assert(VM_Version::supports_ssse3(), "");
2133 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2134 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2135 emit_int16(0x1C, (0xC0 | encode));
2136 }
2137
2138 void Assembler::pabsw(XMMRegister dst, XMMRegister src) {
2139 assert(VM_Version::supports_ssse3(), "");
2140 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2141 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2142 emit_int16(0x1D, (0xC0 | encode));
2143 }
2144
2145 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
2146 assert(VM_Version::supports_ssse3(), "");
2147 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2148 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2149 emit_int16(0x1E, (0xC0 | encode));
2150 }
2151
2152 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
2153 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2154 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2155 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
2156 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2157 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2158 emit_int16(0x1C, (0xC0 | encode));
2159 }
2160
2161 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
2162 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
2163 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
2164 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "");
2165 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2166 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2167 emit_int16(0x1D, (0xC0 | encode));
2168 }
2169
2170 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
2171 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
2172 vector_len == AVX_256bit? VM_Version::supports_avx2() :
2173 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, "");
2174 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2175 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2176 emit_int16(0x1E, (0xC0 | encode));
2177 }
2178
2179 void Assembler::evpabsq(XMMRegister dst, XMMRegister src, int vector_len) {
2180 assert(UseAVX > 2, "");
2181 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2182 attributes.set_is_evex_instruction();
2183 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
2184 emit_int16(0x1F, (0xC0 | encode));
2185 }
2186
2187 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2188 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2189 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2190 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2191 emit_int16(0x5A, (0xC0 | encode));
2192 }
2193
2194 void Assembler::vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2195 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2196 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2197 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2198 attributes.set_rex_vex_w_reverted();
2199 emit_int16(0x5A, (0xC0 | encode));
2200 }
2201
2202 void Assembler::vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2203 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2204 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2205 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2206 emit_int16(0x5B, (0xC0 | encode));
2207 }
2208
2209 void Assembler::vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2210 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2211 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2212 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2213 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2214 }
2215
2216 void Assembler::vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len) {
2217 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
2218 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2219 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2220 emit_int16(0x5B, (0xC0 | encode));
2221 }
2222
2223 void Assembler::evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2224 assert(VM_Version::supports_avx512dq(), "");
2225 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2226 attributes.set_is_evex_instruction();
2227 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2228 emit_int16(0x7A, (0xC0 | encode));
2229 }
2230
2231 void Assembler::evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2232 assert(VM_Version::supports_avx512dq(), "");
2233 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2234 attributes.set_is_evex_instruction();
2235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2236 emit_int16(0x7B, (0xC0 | encode));
2237 }
2238
2239 void Assembler::evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len) {
2240 assert(VM_Version::supports_avx512dq(), "");
2241 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2242 attributes.set_is_evex_instruction();
2243 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2244 emit_int16(0x5B, (0xC0 | encode));
2245 }
2246
2247 void Assembler::evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len) {
2248 assert(VM_Version::supports_avx512dq(), "");
2249 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2250 attributes.set_is_evex_instruction();
2251 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2252 emit_int16(0x7A, (0xC0 | encode));
2253 }
2254
2255 void Assembler::evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len) {
2256 assert(VM_Version::supports_avx512dq(), "");
2257 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2258 attributes.set_is_evex_instruction();
2259 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2260 emit_int16((unsigned char)0xE6, (0xC0 | encode));
2261 }
2262
2263 void Assembler::evpmovwb(XMMRegister dst, XMMRegister src, int vector_len) {
2264 assert(VM_Version::supports_avx512bw(), "");
2265 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2266 attributes.set_is_evex_instruction();
2267 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2268 emit_int16(0x30, (0xC0 | encode));
2269 }
2270
2271 void Assembler::evpmovdw(XMMRegister dst, XMMRegister src, int vector_len) {
2272 assert(UseAVX > 2, "");
2273 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2274 attributes.set_is_evex_instruction();
2275 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2276 emit_int16(0x33, (0xC0 | encode));
2277 }
2278
2279 void Assembler::evpmovdb(XMMRegister dst, XMMRegister src, int vector_len) {
2280 assert(UseAVX > 2, "");
2281 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2282 attributes.set_is_evex_instruction();
2283 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2284 emit_int16(0x31, (0xC0 | encode));
2285 }
2286
2287 void Assembler::evpmovqd(XMMRegister dst, XMMRegister src, int vector_len) {
2288 assert(UseAVX > 2, "");
2289 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2290 attributes.set_is_evex_instruction();
2291 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2292 emit_int16(0x35, (0xC0 | encode));
2293 }
2294
2295 void Assembler::evpmovqb(XMMRegister dst, XMMRegister src, int vector_len) {
2296 assert(UseAVX > 2, "");
2297 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2298 attributes.set_is_evex_instruction();
2299 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2300 emit_int16(0x32, (0xC0 | encode));
2301 }
2302
2303 void Assembler::evpmovqw(XMMRegister dst, XMMRegister src, int vector_len) {
2304 assert(UseAVX > 2, "");
2305 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2306 attributes.set_is_evex_instruction();
2307 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2308 emit_int16(0x34, (0xC0 | encode));
2309 }
2310
2311 void Assembler::evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len) {
2312 assert(UseAVX > 2, "");
2313 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2314 attributes.set_is_evex_instruction();
2315 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
2316 emit_int16(0x25, (0xC0 | encode));
2317 }
2318
2319 void Assembler::decl(Address dst) {
2320 // Don't use it directly. Use MacroAssembler::decrement() instead.
2321 InstructionMark im(this);
2322 prefix(dst);
2323 emit_int8((unsigned char)0xFF);
2324 emit_operand(rcx, dst, 0);
2325 }
2326
2327 void Assembler::divsd(XMMRegister dst, Address src) {
2328 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2329 InstructionMark im(this);
2330 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2331 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2332 attributes.set_rex_vex_w_reverted();
2333 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2334 emit_int8(0x5E);
2335 emit_operand(dst, src, 0);
2336 }
2337
2338 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
2339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2340 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2341 attributes.set_rex_vex_w_reverted();
2342 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2343 emit_int16(0x5E, (0xC0 | encode));
2344 }
2345
2346 void Assembler::divss(XMMRegister dst, Address src) {
2347 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2348 InstructionMark im(this);
2349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2350 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2351 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2352 emit_int8(0x5E);
2353 emit_operand(dst, src, 0);
2354 }
2355
2356 void Assembler::divss(XMMRegister dst, XMMRegister src) {
2357 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2358 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2359 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2360 emit_int16(0x5E, (0xC0 | encode));
2361 }
2362
2363 void Assembler::hlt() {
2364 emit_int8((unsigned char)0xF4);
2365 }
2366
2367 void Assembler::idivl(Register src) {
2368 int encode = prefix_and_encode(src->encoding());
2369 emit_int16((unsigned char)0xF7, (0xF8 | encode));
2370 }
2371
2372 void Assembler::divl(Register src) { // Unsigned
2373 int encode = prefix_and_encode(src->encoding());
2374 emit_int16((unsigned char)0xF7, (0xF0 | encode));
2375 }
2376
2377 void Assembler::imull(Register src) {
2378 int encode = prefix_and_encode(src->encoding());
2379 emit_int16((unsigned char)0xF7, (0xE8 | encode));
2380 }
2381
2382 void Assembler::imull(Register dst, Register src) {
2383 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2384 emit_int24(0x0F,
2385 (unsigned char)0xAF,
2386 (0xC0 | encode));
2387 }
2388
2389 void Assembler::imull(Register dst, Address src, int32_t value) {
2390 InstructionMark im(this);
2391 prefix(src, dst);
2392 if (is8bit(value)) {
2393 emit_int8((unsigned char)0x6B);
2394 emit_operand(dst, src, 1);
2395 emit_int8(value);
2396 } else {
2397 emit_int8((unsigned char)0x69);
2398 emit_operand(dst, src, 4);
2399 emit_int32(value);
2400 }
2401 }
2402
2403 void Assembler::imull(Register dst, Register src, int value) {
2404 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2405 if (is8bit(value)) {
2406 emit_int24(0x6B, (0xC0 | encode), value & 0xFF);
2407 } else {
2408 emit_int16(0x69, (0xC0 | encode));
2409 emit_int32(value);
2410 }
2411 }
2412
2413 void Assembler::imull(Register dst, Address src) {
2414 InstructionMark im(this);
2415 prefix(src, dst);
2416 emit_int16(0x0F, (unsigned char)0xAF);
2417 emit_operand(dst, src, 0);
2418 }
2419
2420
2421 void Assembler::incl(Address dst) {
2422 // Don't use it directly. Use MacroAssembler::increment() instead.
2423 InstructionMark im(this);
2424 prefix(dst);
2425 emit_int8((unsigned char)0xFF);
2426 emit_operand(rax, dst, 0);
2427 }
2428
2429 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2430 InstructionMark im(this);
2431 assert((0 <= cc) && (cc < 16), "illegal cc");
2432 if (L.is_bound()) {
2433 address dst = target(L);
2434 assert(dst != nullptr, "jcc most probably wrong");
2435
2436 const int short_size = 2;
2437 const int long_size = 6;
2438 int offs = checked_cast<int>((intptr_t)dst - (intptr_t)pc());
2439 if (maybe_short && is8bit(offs - short_size)) {
2440 // 0111 tttn #8-bit disp
2441 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2442 } else {
2443 // 0000 1111 1000 tttn #32-bit disp
2444 assert(is_simm32(offs - long_size),
2445 "must be 32bit offset (call4)");
2446 emit_int16(0x0F, (0x80 | cc));
2447 emit_int32(offs - long_size);
2448 }
2449 } else {
2450 // Note: could eliminate cond. jumps to this jump if condition
2451 // is the same however, seems to be rather unlikely case.
2452 // Note: use jccb() if label to be bound is very close to get
2453 // an 8-bit displacement
2454 L.add_patch_at(code(), locator());
2455 emit_int16(0x0F, (0x80 | cc));
2456 emit_int32(0);
2457 }
2458 }
2459
2460 void Assembler::jccb_0(Condition cc, Label& L, const char* file, int line) {
2461 if (L.is_bound()) {
2462 const int short_size = 2;
2463 address entry = target(L);
2464 #ifdef ASSERT
2465 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2466 int delta = short_branch_delta();
2467 if (delta != 0) {
2468 dist += (dist < 0 ? (-delta) :delta);
2469 }
2470 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2471 #endif
2472 int offs = checked_cast<int>((intptr_t)entry - (intptr_t)pc());
2473 // 0111 tttn #8-bit disp
2474 emit_int16(0x70 | cc, (offs - short_size) & 0xFF);
2475 } else {
2476 InstructionMark im(this);
2477 L.add_patch_at(code(), locator(), file, line);
2478 emit_int16(0x70 | cc, 0);
2479 }
2480 }
2481
2482 void Assembler::jmp(Address adr) {
2483 InstructionMark im(this);
2484 prefix(adr);
2485 emit_int8((unsigned char)0xFF);
2486 emit_operand(rsp, adr, 0);
2487 }
2488
2489 void Assembler::jmp(Label& L, bool maybe_short) {
2490 if (L.is_bound()) {
2491 address entry = target(L);
2492 assert(entry != nullptr, "jmp most probably wrong");
2493 InstructionMark im(this);
2494 const int short_size = 2;
2495 const int long_size = 5;
2496 int offs = checked_cast<int>(entry - pc());
2497 if (maybe_short && is8bit(offs - short_size)) {
2498 emit_int16((unsigned char)0xEB, ((offs - short_size) & 0xFF));
2499 } else {
2500 emit_int8((unsigned char)0xE9);
2501 emit_int32(offs - long_size);
2502 }
2503 } else {
2504 // By default, forward jumps are always 32-bit displacements, since
2505 // we can't yet know where the label will be bound. If you're sure that
2506 // the forward jump will not run beyond 256 bytes, use jmpb to
2507 // force an 8-bit displacement.
2508 InstructionMark im(this);
2509 L.add_patch_at(code(), locator());
2510 emit_int8((unsigned char)0xE9);
2511 emit_int32(0);
2512 }
2513 }
2514
2515 void Assembler::jmp(Register entry) {
2516 int encode = prefix_and_encode(entry->encoding());
2517 emit_int16((unsigned char)0xFF, (0xE0 | encode));
2518 }
2519
2520 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2521 InstructionMark im(this);
2522 emit_int8((unsigned char)0xE9);
2523 assert(dest != nullptr, "must have a target");
2524 intptr_t disp = dest - (pc() + sizeof(int32_t));
2525 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2526 emit_data(checked_cast<int32_t>(disp), rspec, call32_operand);
2527 }
2528
2529 void Assembler::jmpb_0(Label& L, const char* file, int line) {
2530 if (L.is_bound()) {
2531 const int short_size = 2;
2532 address entry = target(L);
2533 assert(entry != nullptr, "jmp most probably wrong");
2534 #ifdef ASSERT
2535 int dist = checked_cast<int>((intptr_t)entry - (intptr_t)(pc() + short_size));
2536 int delta = short_branch_delta();
2537 if (delta != 0) {
2538 dist += (dist < 0 ? (-delta) :delta);
2539 }
2540 assert(is8bit(dist), "Displacement too large for a short jmp at %s:%d", file, line);
2541 #endif
2542 intptr_t offs = entry - pc();
2543 emit_int16((unsigned char)0xEB, (offs - short_size) & 0xFF);
2544 } else {
2545 InstructionMark im(this);
2546 L.add_patch_at(code(), locator(), file, line);
2547 emit_int16((unsigned char)0xEB, 0);
2548 }
2549 }
2550
2551 void Assembler::ldmxcsr( Address src) {
2552 if (UseAVX > 0 ) {
2553 InstructionMark im(this);
2554 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2555 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2556 emit_int8((unsigned char)0xAE);
2557 emit_operand(as_Register(2), src, 0);
2558 } else {
2559 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2560 InstructionMark im(this);
2561 prefix(src);
2562 emit_int16(0x0F, (unsigned char)0xAE);
2563 emit_operand(as_Register(2), src, 0);
2564 }
2565 }
2566
2567 void Assembler::leal(Register dst, Address src) {
2568 InstructionMark im(this);
2569 prefix(src, dst);
2570 emit_int8((unsigned char)0x8D);
2571 emit_operand(dst, src, 0);
2572 }
2573
2574 void Assembler::lfence() {
2575 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xE8);
2576 }
2577
2578 void Assembler::lock() {
2579 emit_int8((unsigned char)0xF0);
2580 }
2581
2582 void Assembler::size_prefix() {
2583 emit_int8(0x66);
2584 }
2585
2586 void Assembler::lzcntl(Register dst, Register src) {
2587 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2588 emit_int8((unsigned char)0xF3);
2589 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2590 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
2591 }
2592
2593 void Assembler::lzcntl(Register dst, Address src) {
2594 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2595 InstructionMark im(this);
2596 emit_int8((unsigned char)0xF3);
2597 prefix(src, dst);
2598 emit_int16(0x0F, (unsigned char)0xBD);
2599 emit_operand(dst, src, 0);
2600 }
2601
2602 // Emit mfence instruction
2603 void Assembler::mfence() {
2604 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2605 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF0);
2606 }
2607
2608 // Emit sfence instruction
2609 void Assembler::sfence() {
2610 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2611 emit_int24(0x0F, (unsigned char)0xAE, (unsigned char)0xF8);
2612 }
2613
2614 void Assembler::mov(Register dst, Register src) {
2615 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2616 }
2617
2618 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2619 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2620 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2621 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2622 attributes.set_rex_vex_w_reverted();
2623 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2624 emit_int16(0x28, (0xC0 | encode));
2625 }
2626
2627 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2628 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2629 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2630 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2631 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2632 emit_int16(0x28, (0xC0 | encode));
2633 }
2634
2635 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2636 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2637 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2638 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2639 emit_int16(0x16, (0xC0 | encode));
2640 }
2641
2642 void Assembler::movb(Register dst, Address src) {
2643 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2644 InstructionMark im(this);
2645 prefix(src, dst, true);
2646 emit_int8((unsigned char)0x8A);
2647 emit_operand(dst, src, 0);
2648 }
2649
2650 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2651 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2652 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2653 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2654 attributes.set_rex_vex_w_reverted();
2655 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2656 emit_int16(0x12, 0xC0 | encode);
2657 }
2658
2659 void Assembler::movddup(XMMRegister dst, Address src) {
2660 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2661 InstructionMark im(this);
2662 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2663 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2664 attributes.set_rex_vex_w_reverted();
2665 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2666 emit_int8(0x12);
2667 emit_operand(dst, src, 0);
2668 }
2669
2670 void Assembler::vmovddup(XMMRegister dst, Address src, int vector_len) {
2671 assert(VM_Version::supports_avx(), "");
2672 InstructionMark im(this);
2673 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
2674 attributes.set_address_attributes(/* tuple_type */ EVEX_DUP, /* input_size_in_bits */ EVEX_64bit);
2675 attributes.set_rex_vex_w_reverted();
2676 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2677 emit_int8(0x12);
2678 emit_operand(dst, src, 0);
2679 }
2680
2681 void Assembler::kmovbl(KRegister dst, KRegister src) {
2682 assert(VM_Version::supports_avx512dq(), "");
2683 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2684 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2685 emit_int16((unsigned char)0x90, (0xC0 | encode));
2686 }
2687
2688 void Assembler::kmovbl(KRegister dst, Register src) {
2689 assert(VM_Version::supports_avx512dq(), "");
2690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2691 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2692 emit_int16((unsigned char)0x92, (0xC0 | encode));
2693 }
2694
2695 void Assembler::kmovbl(Register dst, KRegister src) {
2696 assert(VM_Version::supports_avx512dq(), "");
2697 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2698 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2699 emit_int16((unsigned char)0x93, (0xC0 | encode));
2700 }
2701
2702 void Assembler::kmovwl(KRegister dst, Register src) {
2703 assert(VM_Version::supports_evex(), "");
2704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2705 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2706 emit_int16((unsigned char)0x92, (0xC0 | encode));
2707 }
2708
2709 void Assembler::kmovwl(Register dst, KRegister src) {
2710 assert(VM_Version::supports_evex(), "");
2711 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2712 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2713 emit_int16((unsigned char)0x93, (0xC0 | encode));
2714 }
2715
2716 void Assembler::kmovwl(KRegister dst, Address src) {
2717 assert(VM_Version::supports_evex(), "");
2718 InstructionMark im(this);
2719 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2720 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2721 emit_int8((unsigned char)0x90);
2722 emit_operand(dst, src, 0);
2723 }
2724
2725 void Assembler::kmovwl(Address dst, KRegister src) {
2726 assert(VM_Version::supports_evex(), "");
2727 InstructionMark im(this);
2728 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2729 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2730 emit_int8((unsigned char)0x91);
2731 emit_operand(src, dst, 0);
2732 }
2733
2734 void Assembler::kmovwl(KRegister dst, KRegister src) {
2735 assert(VM_Version::supports_evex(), "");
2736 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2737 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2738 emit_int16((unsigned char)0x90, (0xC0 | encode));
2739 }
2740
2741 void Assembler::kmovdl(KRegister dst, Register src) {
2742 assert(VM_Version::supports_avx512bw(), "");
2743 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2744 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2745 emit_int16((unsigned char)0x92, (0xC0 | encode));
2746 }
2747
2748 void Assembler::kmovdl(Register dst, KRegister src) {
2749 assert(VM_Version::supports_avx512bw(), "");
2750 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2751 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2752 emit_int16((unsigned char)0x93, (0xC0 | encode));
2753 }
2754
2755 void Assembler::kmovql(KRegister dst, KRegister src) {
2756 assert(VM_Version::supports_avx512bw(), "");
2757 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2758 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2759 emit_int16((unsigned char)0x90, (0xC0 | encode));
2760 }
2761
2762 void Assembler::kmovql(KRegister dst, Address src) {
2763 assert(VM_Version::supports_avx512bw(), "");
2764 InstructionMark im(this);
2765 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2766 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2767 emit_int8((unsigned char)0x90);
2768 emit_operand(dst, src, 0);
2769 }
2770
2771 void Assembler::kmovql(Address dst, KRegister src) {
2772 assert(VM_Version::supports_avx512bw(), "");
2773 InstructionMark im(this);
2774 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2775 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2776 emit_int8((unsigned char)0x91);
2777 emit_operand(src, dst, 0);
2778 }
2779
2780 void Assembler::kmovql(KRegister dst, Register src) {
2781 assert(VM_Version::supports_avx512bw(), "");
2782 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2783 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2784 emit_int16((unsigned char)0x92, (0xC0 | encode));
2785 }
2786
2787 void Assembler::kmovql(Register dst, KRegister src) {
2788 assert(VM_Version::supports_avx512bw(), "");
2789 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2790 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2791 emit_int16((unsigned char)0x93, (0xC0 | encode));
2792 }
2793
2794 void Assembler::knotwl(KRegister dst, KRegister src) {
2795 assert(VM_Version::supports_evex(), "");
2796 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2797 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2798 emit_int16(0x44, (0xC0 | encode));
2799 }
2800
2801 void Assembler::knotbl(KRegister dst, KRegister src) {
2802 assert(VM_Version::supports_evex(), "");
2803 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2804 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2805 emit_int16(0x44, (0xC0 | encode));
2806 }
2807
2808 void Assembler::korbl(KRegister dst, KRegister src1, KRegister src2) {
2809 assert(VM_Version::supports_avx512dq(), "");
2810 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2811 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2812 emit_int16(0x45, (0xC0 | encode));
2813 }
2814
2815 void Assembler::korwl(KRegister dst, KRegister src1, KRegister src2) {
2816 assert(VM_Version::supports_evex(), "");
2817 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2818 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2819 emit_int16(0x45, (0xC0 | encode));
2820 }
2821
2822 void Assembler::kordl(KRegister dst, KRegister src1, KRegister src2) {
2823 assert(VM_Version::supports_avx512bw(), "");
2824 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2825 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2826 emit_int16(0x45, (0xC0 | encode));
2827 }
2828
2829 void Assembler::korql(KRegister dst, KRegister src1, KRegister src2) {
2830 assert(VM_Version::supports_avx512bw(), "");
2831 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2832 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2833 emit_int16(0x45, (0xC0 | encode));
2834 }
2835
2836 void Assembler::kxorbl(KRegister dst, KRegister src1, KRegister src2) {
2837 assert(VM_Version::supports_avx512dq(), "");
2838 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2839 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2840 emit_int16(0x47, (0xC0 | encode));
2841 }
2842
2843 void Assembler::kxorwl(KRegister dst, KRegister src1, KRegister src2) {
2844 assert(VM_Version::supports_evex(), "");
2845 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2846 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2847 emit_int16(0x47, (0xC0 | encode));
2848 }
2849
2850 void Assembler::kxordl(KRegister dst, KRegister src1, KRegister src2) {
2851 assert(VM_Version::supports_avx512bw(), "");
2852 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2853 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2854 emit_int16(0x47, (0xC0 | encode));
2855 }
2856
2857 void Assembler::kxorql(KRegister dst, KRegister src1, KRegister src2) {
2858 assert(VM_Version::supports_avx512bw(), "");
2859 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2860 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2861 emit_int16(0x47, (0xC0 | encode));
2862 }
2863
2864 void Assembler::kandbl(KRegister dst, KRegister src1, KRegister src2) {
2865 assert(VM_Version::supports_avx512dq(), "");
2866 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2867 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2868 emit_int16(0x41, (0xC0 | encode));
2869 }
2870
2871 void Assembler::kandwl(KRegister dst, KRegister src1, KRegister src2) {
2872 assert(VM_Version::supports_evex(), "");
2873 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2874 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2875 emit_int16(0x41, (0xC0 | encode));
2876 }
2877
2878 void Assembler::kanddl(KRegister dst, KRegister src1, KRegister src2) {
2879 assert(VM_Version::supports_avx512bw(), "");
2880 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2881 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2882 emit_int16(0x41, (0xC0 | encode));
2883 }
2884
2885 void Assembler::kandql(KRegister dst, KRegister src1, KRegister src2) {
2886 assert(VM_Version::supports_avx512bw(), "");
2887 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2888 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2889 emit_int16(0x41, (0xC0 | encode));
2890 }
2891
2892 void Assembler::knotdl(KRegister dst, KRegister src) {
2893 assert(VM_Version::supports_avx512bw(), "");
2894 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2895 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2896 emit_int16(0x44, (0xC0 | encode));
2897 }
2898
2899 void Assembler::knotql(KRegister dst, KRegister src) {
2900 assert(VM_Version::supports_avx512bw(), "");
2901 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2902 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2903 emit_int16(0x44, (0xC0 | encode));
2904 }
2905
2906 // This instruction produces ZF or CF flags
2907 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2908 assert(VM_Version::supports_avx512dq(), "");
2909 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2910 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2911 emit_int16((unsigned char)0x98, (0xC0 | encode));
2912 }
2913
2914 // This instruction produces ZF or CF flags
2915 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2916 assert(VM_Version::supports_evex(), "");
2917 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2918 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2919 emit_int16((unsigned char)0x98, (0xC0 | encode));
2920 }
2921
2922 // This instruction produces ZF or CF flags
2923 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2924 assert(VM_Version::supports_avx512bw(), "");
2925 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2926 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2927 emit_int16((unsigned char)0x98, (0xC0 | encode));
2928 }
2929
2930 // This instruction produces ZF or CF flags
2931 void Assembler::kortestql(KRegister src1, KRegister src2) {
2932 assert(VM_Version::supports_avx512bw(), "");
2933 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2934 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2935 emit_int16((unsigned char)0x98, (0xC0 | encode));
2936 }
2937
2938 // This instruction produces ZF or CF flags
2939 void Assembler::ktestql(KRegister src1, KRegister src2) {
2940 assert(VM_Version::supports_avx512bw(), "");
2941 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2942 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2943 emit_int16((unsigned char)0x99, (0xC0 | encode));
2944 }
2945
2946 void Assembler::ktestdl(KRegister src1, KRegister src2) {
2947 assert(VM_Version::supports_avx512bw(), "");
2948 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2949 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2950 emit_int16((unsigned char)0x99, (0xC0 | encode));
2951 }
2952
2953 void Assembler::ktestwl(KRegister src1, KRegister src2) {
2954 assert(VM_Version::supports_avx512dq(), "");
2955 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2956 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2957 emit_int16((unsigned char)0x99, (0xC0 | encode));
2958 }
2959
2960 void Assembler::ktestbl(KRegister src1, KRegister src2) {
2961 assert(VM_Version::supports_avx512dq(), "");
2962 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2963 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2964 emit_int16((unsigned char)0x99, (0xC0 | encode));
2965 }
2966
2967 void Assembler::ktestq(KRegister src1, KRegister src2) {
2968 assert(VM_Version::supports_avx512bw(), "");
2969 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2970 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2971 emit_int16((unsigned char)0x99, (0xC0 | encode));
2972 }
2973
2974 void Assembler::ktestd(KRegister src1, KRegister src2) {
2975 assert(VM_Version::supports_avx512bw(), "");
2976 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2977 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2978 emit_int16((unsigned char)0x99, (0xC0 | encode));
2979 }
2980
2981 void Assembler::kxnorbl(KRegister dst, KRegister src1, KRegister src2) {
2982 assert(VM_Version::supports_avx512dq(), "");
2983 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2984 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2985 emit_int16(0x46, (0xC0 | encode));
2986 }
2987
2988 void Assembler::kshiftlbl(KRegister dst, KRegister src, int imm8) {
2989 assert(VM_Version::supports_avx512dq(), "");
2990 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2991 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
2992 emit_int16(0x32, (0xC0 | encode));
2993 emit_int8(imm8);
2994 }
2995
2996 void Assembler::kshiftlql(KRegister dst, KRegister src, int imm8) {
2997 assert(VM_Version::supports_avx512bw(), "");
2998 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2999 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3000 emit_int16(0x33, (0xC0 | encode));
3001 emit_int8(imm8);
3002 }
3003
3004
3005 void Assembler::kshiftrbl(KRegister dst, KRegister src, int imm8) {
3006 assert(VM_Version::supports_avx512dq(), "");
3007 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3008 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3009 emit_int16(0x30, (0xC0 | encode));
3010 }
3011
3012 void Assembler::kshiftrwl(KRegister dst, KRegister src, int imm8) {
3013 assert(VM_Version::supports_evex(), "");
3014 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3015 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3016 emit_int16(0x30, (0xC0 | encode));
3017 emit_int8(imm8);
3018 }
3019
3020 void Assembler::kshiftrdl(KRegister dst, KRegister src, int imm8) {
3021 assert(VM_Version::supports_avx512bw(), "");
3022 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3023 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3024 emit_int16(0x31, (0xC0 | encode));
3025 emit_int8(imm8);
3026 }
3027
3028 void Assembler::kshiftrql(KRegister dst, KRegister src, int imm8) {
3029 assert(VM_Version::supports_avx512bw(), "");
3030 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3031 int encode = vex_prefix_and_encode(dst->encoding(), 0 , src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3032 emit_int16(0x31, (0xC0 | encode));
3033 emit_int8(imm8);
3034 }
3035
3036 void Assembler::kunpckdql(KRegister dst, KRegister src1, KRegister src2) {
3037 assert(VM_Version::supports_avx512bw(), "");
3038 InstructionAttr attributes(AVX_256bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3039 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3040 emit_int16(0x4B, (0xC0 | encode));
3041 }
3042
3043 void Assembler::movb(Address dst, int imm8) {
3044 InstructionMark im(this);
3045 prefix(dst);
3046 emit_int8((unsigned char)0xC6);
3047 emit_operand(rax, dst, 1);
3048 emit_int8(imm8);
3049 }
3050
3051
3052 void Assembler::movb(Address dst, Register src) {
3053 assert(src->has_byte_register(), "must have byte register");
3054 InstructionMark im(this);
3055 prefix(dst, src, true);
3056 emit_int8((unsigned char)0x88);
3057 emit_operand(src, dst, 0);
3058 }
3059
3060 void Assembler::movdl(XMMRegister dst, Register src) {
3061 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3062 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3063 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3064 emit_int16(0x6E, (0xC0 | encode));
3065 }
3066
3067 void Assembler::movdl(Register dst, XMMRegister src) {
3068 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3069 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3070 // swap src/dst to get correct prefix
3071 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3072 emit_int16(0x7E, (0xC0 | encode));
3073 }
3074
3075 void Assembler::movdl(XMMRegister dst, Address src) {
3076 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3077 InstructionMark im(this);
3078 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3079 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3080 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3081 emit_int8(0x6E);
3082 emit_operand(dst, src, 0);
3083 }
3084
3085 void Assembler::movdl(Address dst, XMMRegister src) {
3086 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3087 InstructionMark im(this);
3088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3089 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3090 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3091 emit_int8(0x7E);
3092 emit_operand(src, dst, 0);
3093 }
3094
3095 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
3096 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3097 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3098 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3099 emit_int16(0x6F, (0xC0 | encode));
3100 }
3101
3102 void Assembler::movdqa(XMMRegister dst, Address src) {
3103 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3104 InstructionMark im(this);
3105 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3106 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3107 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3108 emit_int8(0x6F);
3109 emit_operand(dst, src, 0);
3110 }
3111
3112 void Assembler::movdqu(XMMRegister dst, Address src) {
3113 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3114 InstructionMark im(this);
3115 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3116 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3117 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3118 emit_int8(0x6F);
3119 emit_operand(dst, src, 0);
3120 }
3121
3122 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
3123 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3124 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3125 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3126 emit_int16(0x6F, (0xC0 | encode));
3127 }
3128
3129 void Assembler::movdqu(Address dst, XMMRegister src) {
3130 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3131 InstructionMark im(this);
3132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3133 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3134 attributes.reset_is_clear_context();
3135 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3136 emit_int8(0x7F);
3137 emit_operand(src, dst, 0);
3138 }
3139
3140 // Move Unaligned 256bit Vector
3141 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
3142 assert(UseAVX > 0, "");
3143 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3144 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3145 emit_int16(0x6F, (0xC0 | encode));
3146 }
3147
3148 void Assembler::vmovdqu(XMMRegister dst, Address src) {
3149 assert(UseAVX > 0, "");
3150 InstructionMark im(this);
3151 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3152 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3153 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3154 emit_int8(0x6F);
3155 emit_operand(dst, src, 0);
3156 }
3157
3158 void Assembler::vmovdqu(Address dst, XMMRegister src) {
3159 assert(UseAVX > 0, "");
3160 InstructionMark im(this);
3161 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3162 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3163 attributes.reset_is_clear_context();
3164 // swap src<->dst for encoding
3165 assert(src != xnoreg, "sanity");
3166 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3167 emit_int8(0x7F);
3168 emit_operand(src, dst, 0);
3169 }
3170
3171 void Assembler::vpmaskmovd(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3172 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3173 InstructionMark im(this);
3174 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3175 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3176 emit_int8((unsigned char)0x8C);
3177 emit_operand(dst, src, 0);
3178 }
3179
3180 void Assembler::vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len) {
3181 assert((VM_Version::supports_avx2() && vector_len == AVX_256bit), "");
3182 InstructionMark im(this);
3183 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3184 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3185 emit_int8((unsigned char)0x8C);
3186 emit_operand(dst, src, 0);
3187 }
3188
3189 void Assembler::vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3190 assert(UseAVX > 0, "requires some form of AVX");
3191 InstructionMark im(this);
3192 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3193 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3194 emit_int8(0x2C);
3195 emit_operand(dst, src, 0);
3196 }
3197
3198 void Assembler::vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
3199 assert(UseAVX > 0, "requires some form of AVX");
3200 InstructionMark im(this);
3201 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3202 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3203 emit_int8(0x2D);
3204 emit_operand(dst, src, 0);
3205 }
3206
3207 void Assembler::vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3208 assert(UseAVX > 0, "");
3209 InstructionMark im(this);
3210 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3211 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3212 emit_int8(0x2E);
3213 emit_operand(src, dst, 0);
3214 }
3215
3216 void Assembler::vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len) {
3217 assert(UseAVX > 0, "");
3218 InstructionMark im(this);
3219 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3220 vex_prefix(dst, mask->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3221 emit_int8(0x2F);
3222 emit_operand(src, dst, 0);
3223 }
3224
3225 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
3226 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3227 assert(VM_Version::supports_avx512vlbw(), "");
3228 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3229 attributes.set_embedded_opmask_register_specifier(mask);
3230 attributes.set_is_evex_instruction();
3231 if (merge) {
3232 attributes.reset_is_clear_context();
3233 }
3234 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3235 emit_int16(0x6F, (0xC0 | encode));
3236 }
3237
3238 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, int vector_len) {
3239 // Unmasked instruction
3240 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3241 }
3242
3243 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3244 assert(VM_Version::supports_avx512vlbw(), "");
3245 InstructionMark im(this);
3246 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3247 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3248 attributes.set_embedded_opmask_register_specifier(mask);
3249 attributes.set_is_evex_instruction();
3250 if (merge) {
3251 attributes.reset_is_clear_context();
3252 }
3253 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3254 emit_int8(0x6F);
3255 emit_operand(dst, src, 0);
3256 }
3257
3258 void Assembler::evmovdqub(XMMRegister dst, Address src, int vector_len) {
3259 // Unmasked instruction
3260 evmovdqub(dst, k0, src, /*merge*/ false, vector_len);
3261 }
3262
3263 void Assembler::evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3264 assert(VM_Version::supports_avx512vlbw(), "");
3265 assert(src != xnoreg, "sanity");
3266 InstructionMark im(this);
3267 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3268 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3269 attributes.set_embedded_opmask_register_specifier(mask);
3270 attributes.set_is_evex_instruction();
3271 if (merge) {
3272 attributes.reset_is_clear_context();
3273 }
3274 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3275 emit_int8(0x7F);
3276 emit_operand(src, dst, 0);
3277 }
3278
3279 void Assembler::evmovdquw(XMMRegister dst, Address src, int vector_len) {
3280 // Unmasked instruction
3281 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3282 }
3283
3284 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3285 assert(VM_Version::supports_avx512vlbw(), "");
3286 InstructionMark im(this);
3287 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3288 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3289 attributes.set_embedded_opmask_register_specifier(mask);
3290 attributes.set_is_evex_instruction();
3291 if (merge) {
3292 attributes.reset_is_clear_context();
3293 }
3294 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3295 emit_int8(0x6F);
3296 emit_operand(dst, src, 0);
3297 }
3298
3299 void Assembler::evmovdquw(Address dst, XMMRegister src, int vector_len) {
3300 // Unmasked instruction
3301 evmovdquw(dst, k0, src, /*merge*/ false, vector_len);
3302 }
3303
3304 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3305 assert(VM_Version::supports_avx512vlbw(), "");
3306 assert(src != xnoreg, "sanity");
3307 InstructionMark im(this);
3308 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
3309 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3310 attributes.set_embedded_opmask_register_specifier(mask);
3311 attributes.set_is_evex_instruction();
3312 if (merge) {
3313 attributes.reset_is_clear_context();
3314 }
3315 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3316 emit_int8(0x7F);
3317 emit_operand(src, dst, 0);
3318 }
3319
3320 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
3321 // Unmasked instruction
3322 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3323 }
3324
3325 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3326 assert(VM_Version::supports_evex(), "");
3327 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3328 attributes.set_embedded_opmask_register_specifier(mask);
3329 attributes.set_is_evex_instruction();
3330 if (merge) {
3331 attributes.reset_is_clear_context();
3332 }
3333 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3334 emit_int16(0x6F, (0xC0 | encode));
3335 }
3336
3337 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
3338 // Unmasked instruction
3339 evmovdqul(dst, k0, src, /*merge*/ false, vector_len);
3340 }
3341
3342 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3343 assert(VM_Version::supports_evex(), "");
3344 InstructionMark im(this);
3345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
3346 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3347 attributes.set_embedded_opmask_register_specifier(mask);
3348 attributes.set_is_evex_instruction();
3349 if (merge) {
3350 attributes.reset_is_clear_context();
3351 }
3352 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3353 emit_int8(0x6F);
3354 emit_operand(dst, src, 0);
3355 }
3356
3357 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
3358 // Unmasked isntruction
3359 evmovdqul(dst, k0, src, /*merge*/ true, vector_len);
3360 }
3361
3362 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3363 assert(VM_Version::supports_evex(), "");
3364 assert(src != xnoreg, "sanity");
3365 InstructionMark im(this);
3366 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3367 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3368 attributes.set_embedded_opmask_register_specifier(mask);
3369 attributes.set_is_evex_instruction();
3370 if (merge) {
3371 attributes.reset_is_clear_context();
3372 }
3373 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3374 emit_int8(0x7F);
3375 emit_operand(src, dst, 0);
3376 }
3377
3378 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
3379 // Unmasked instruction
3380 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3381 }
3382
3383 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3384 assert(VM_Version::supports_evex(), "");
3385 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3386 attributes.set_embedded_opmask_register_specifier(mask);
3387 attributes.set_is_evex_instruction();
3388 if (merge) {
3389 attributes.reset_is_clear_context();
3390 }
3391 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3392 emit_int16(0x6F, (0xC0 | encode));
3393 }
3394
3395 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
3396 // Unmasked instruction
3397 evmovdquq(dst, k0, src, /*merge*/ false, vector_len);
3398 }
3399
3400 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
3401 assert(VM_Version::supports_evex(), "");
3402 InstructionMark im(this);
3403 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3404 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3405 attributes.set_embedded_opmask_register_specifier(mask);
3406 attributes.set_is_evex_instruction();
3407 if (merge) {
3408 attributes.reset_is_clear_context();
3409 }
3410 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3411 emit_int8(0x6F);
3412 emit_operand(dst, src, 0);
3413 }
3414
3415 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
3416 // Unmasked instruction
3417 evmovdquq(dst, k0, src, /*merge*/ true, vector_len);
3418 }
3419
3420 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
3421 assert(VM_Version::supports_evex(), "");
3422 assert(src != xnoreg, "sanity");
3423 InstructionMark im(this);
3424 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3425 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3426 attributes.set_embedded_opmask_register_specifier(mask);
3427 if (merge) {
3428 attributes.reset_is_clear_context();
3429 }
3430 attributes.set_is_evex_instruction();
3431 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3432 emit_int8(0x7F);
3433 emit_operand(src, dst, 0);
3434 }
3435
3436 // Uses zero extension on 64bit
3437
3438 void Assembler::movl(Register dst, int32_t imm32) {
3439 int encode = prefix_and_encode(dst->encoding());
3440 emit_int8(0xB8 | encode);
3441 emit_int32(imm32);
3442 }
3443
3444 void Assembler::movl(Register dst, Register src) {
3445 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3446 emit_int16((unsigned char)0x8B, (0xC0 | encode));
3447 }
3448
3449 void Assembler::movl(Register dst, Address src) {
3450 InstructionMark im(this);
3451 prefix(src, dst);
3452 emit_int8((unsigned char)0x8B);
3453 emit_operand(dst, src, 0);
3454 }
3455
3456 void Assembler::movl(Address dst, int32_t imm32) {
3457 InstructionMark im(this);
3458 prefix(dst);
3459 emit_int8((unsigned char)0xC7);
3460 emit_operand(rax, dst, 4);
3461 emit_int32(imm32);
3462 }
3463
3464 void Assembler::movl(Address dst, Register src) {
3465 InstructionMark im(this);
3466 prefix(dst, src);
3467 emit_int8((unsigned char)0x89);
3468 emit_operand(src, dst, 0);
3469 }
3470
3471 // New cpus require to use movsd and movss to avoid partial register stall
3472 // when loading from memory. But for old Opteron use movlpd instead of movsd.
3473 // The selection is done in MacroAssembler::movdbl() and movflt().
3474 void Assembler::movlpd(XMMRegister dst, Address src) {
3475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3476 InstructionMark im(this);
3477 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3478 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3479 attributes.set_rex_vex_w_reverted();
3480 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3481 emit_int8(0x12);
3482 emit_operand(dst, src, 0);
3483 }
3484
3485 void Assembler::movq(XMMRegister dst, Address src) {
3486 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3487 InstructionMark im(this);
3488 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3489 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3490 attributes.set_rex_vex_w_reverted();
3491 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3492 emit_int8(0x7E);
3493 emit_operand(dst, src, 0);
3494 }
3495
3496 void Assembler::movq(Address dst, XMMRegister src) {
3497 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3498 InstructionMark im(this);
3499 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3500 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3501 attributes.set_rex_vex_w_reverted();
3502 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3503 emit_int8((unsigned char)0xD6);
3504 emit_operand(src, dst, 0);
3505 }
3506
3507 void Assembler::movq(XMMRegister dst, XMMRegister src) {
3508 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3509 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3510 attributes.set_rex_vex_w_reverted();
3511 int encode = simd_prefix_and_encode(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3512 emit_int16((unsigned char)0xD6, (0xC0 | encode));
3513 }
3514
3515 void Assembler::movq(Register dst, XMMRegister src) {
3516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3517 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3518 // swap src/dst to get correct prefix
3519 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3520 emit_int16(0x7E, (0xC0 | encode));
3521 }
3522
3523 void Assembler::movq(XMMRegister dst, Register src) {
3524 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3525 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3526 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3527 emit_int16(0x6E, (0xC0 | encode));
3528 }
3529
3530 void Assembler::movsbl(Register dst, Address src) { // movsxb
3531 InstructionMark im(this);
3532 prefix(src, dst);
3533 emit_int16(0x0F, (unsigned char)0xBE);
3534 emit_operand(dst, src, 0);
3535 }
3536
3537 void Assembler::movsbl(Register dst, Register src) { // movsxb
3538 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3539 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3540 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
3541 }
3542
3543 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
3544 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3545 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3546 attributes.set_rex_vex_w_reverted();
3547 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3548 emit_int16(0x10, (0xC0 | encode));
3549 }
3550
3551 void Assembler::movsd(XMMRegister dst, Address src) {
3552 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3553 InstructionMark im(this);
3554 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3555 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3556 attributes.set_rex_vex_w_reverted();
3557 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3558 emit_int8(0x10);
3559 emit_operand(dst, src, 0);
3560 }
3561
3562 void Assembler::movsd(Address dst, XMMRegister src) {
3563 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3564 InstructionMark im(this);
3565 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3566 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3567 attributes.reset_is_clear_context();
3568 attributes.set_rex_vex_w_reverted();
3569 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3570 emit_int8(0x11);
3571 emit_operand(src, dst, 0);
3572 }
3573
3574 void Assembler::vmovsd(XMMRegister dst, XMMRegister src, XMMRegister src2) {
3575 assert(UseAVX > 0, "Requires some form of AVX");
3576 InstructionMark im(this);
3577 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3578 int encode = vex_prefix_and_encode(src2->encoding(), src->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3579 emit_int16(0x11, (0xC0 | encode));
3580 }
3581
3582 void Assembler::movss(XMMRegister dst, XMMRegister src) {
3583 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3584 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3585 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3586 emit_int16(0x10, (0xC0 | encode));
3587 }
3588
3589 void Assembler::movss(XMMRegister dst, Address src) {
3590 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3591 InstructionMark im(this);
3592 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3593 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3594 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3595 emit_int8(0x10);
3596 emit_operand(dst, src, 0);
3597 }
3598
3599 void Assembler::movss(Address dst, XMMRegister src) {
3600 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3601 InstructionMark im(this);
3602 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3603 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3604 attributes.reset_is_clear_context();
3605 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3606 emit_int8(0x11);
3607 emit_operand(src, dst, 0);
3608 }
3609
3610 void Assembler::movswl(Register dst, Address src) { // movsxw
3611 InstructionMark im(this);
3612 prefix(src, dst);
3613 emit_int16(0x0F, (unsigned char)0xBF);
3614 emit_operand(dst, src, 0);
3615 }
3616
3617 void Assembler::movswl(Register dst, Register src) { // movsxw
3618 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3619 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
3620 }
3621
3622 void Assembler::movups(XMMRegister dst, Address src) {
3623 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3624 InstructionMark im(this);
3625 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3626 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3627 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3628 emit_int8(0x10);
3629 emit_operand(dst, src, 0);
3630 }
3631
3632 void Assembler::vmovups(XMMRegister dst, Address src, int vector_len) {
3633 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3634 InstructionMark im(this);
3635 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3636 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3637 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3638 emit_int8(0x10);
3639 emit_operand(dst, src, 0);
3640 }
3641
3642 void Assembler::movups(Address dst, XMMRegister src) {
3643 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3644 InstructionMark im(this);
3645 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3646 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3647 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3648 emit_int8(0x11);
3649 emit_operand(src, dst, 0);
3650 }
3651
3652 void Assembler::vmovups(Address dst, XMMRegister src, int vector_len) {
3653 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
3654 InstructionMark im(this);
3655 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3656 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_32bit);
3657 simd_prefix(src, xnoreg, dst, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
3658 emit_int8(0x11);
3659 emit_operand(src, dst, 0);
3660 }
3661
3662 void Assembler::movw(Address dst, int imm16) {
3663 InstructionMark im(this);
3664
3665 emit_int8(0x66); // switch to 16-bit mode
3666 prefix(dst);
3667 emit_int8((unsigned char)0xC7);
3668 emit_operand(rax, dst, 2);
3669 emit_int16(imm16);
3670 }
3671
3672 void Assembler::movw(Register dst, Address src) {
3673 InstructionMark im(this);
3674 emit_int8(0x66);
3675 prefix(src, dst);
3676 emit_int8((unsigned char)0x8B);
3677 emit_operand(dst, src, 0);
3678 }
3679
3680 void Assembler::movw(Address dst, Register src) {
3681 InstructionMark im(this);
3682 emit_int8(0x66);
3683 prefix(dst, src);
3684 emit_int8((unsigned char)0x89);
3685 emit_operand(src, dst, 0);
3686 }
3687
3688 void Assembler::movzbl(Register dst, Address src) { // movzxb
3689 InstructionMark im(this);
3690 prefix(src, dst);
3691 emit_int16(0x0F, (unsigned char)0xB6);
3692 emit_operand(dst, src, 0);
3693 }
3694
3695 void Assembler::movzbl(Register dst, Register src) { // movzxb
3696 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3697 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3698 emit_int24(0x0F, (unsigned char)0xB6, 0xC0 | encode);
3699 }
3700
3701 void Assembler::movzwl(Register dst, Address src) { // movzxw
3702 InstructionMark im(this);
3703 prefix(src, dst);
3704 emit_int16(0x0F, (unsigned char)0xB7);
3705 emit_operand(dst, src, 0);
3706 }
3707
3708 void Assembler::movzwl(Register dst, Register src) { // movzxw
3709 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3710 emit_int24(0x0F, (unsigned char)0xB7, 0xC0 | encode);
3711 }
3712
3713 void Assembler::mull(Address src) {
3714 InstructionMark im(this);
3715 prefix(src);
3716 emit_int8((unsigned char)0xF7);
3717 emit_operand(rsp, src, 0);
3718 }
3719
3720 void Assembler::mull(Register src) {
3721 int encode = prefix_and_encode(src->encoding());
3722 emit_int16((unsigned char)0xF7, (0xE0 | encode));
3723 }
3724
3725 void Assembler::mulsd(XMMRegister dst, Address src) {
3726 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3727 InstructionMark im(this);
3728 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3729 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3730 attributes.set_rex_vex_w_reverted();
3731 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3732 emit_int8(0x59);
3733 emit_operand(dst, src, 0);
3734 }
3735
3736 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3737 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3738 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3739 attributes.set_rex_vex_w_reverted();
3740 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3741 emit_int16(0x59, (0xC0 | encode));
3742 }
3743
3744 void Assembler::mulss(XMMRegister dst, Address src) {
3745 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3746 InstructionMark im(this);
3747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3748 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3749 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3750 emit_int8(0x59);
3751 emit_operand(dst, src, 0);
3752 }
3753
3754 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3755 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3756 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3757 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3758 emit_int16(0x59, (0xC0 | encode));
3759 }
3760
3761 void Assembler::negl(Register dst) {
3762 int encode = prefix_and_encode(dst->encoding());
3763 emit_int16((unsigned char)0xF7, (0xD8 | encode));
3764 }
3765
3766 void Assembler::negl(Address dst) {
3767 InstructionMark im(this);
3768 prefix(dst);
3769 emit_int8((unsigned char)0xF7);
3770 emit_operand(as_Register(3), dst, 0);
3771 }
3772
3773 void Assembler::nop(int i) {
3774 #ifdef ASSERT
3775 assert(i > 0, " ");
3776 // The fancy nops aren't currently recognized by debuggers making it a
3777 // pain to disassemble code while debugging. If asserts are on clearly
3778 // speed is not an issue so simply use the single byte traditional nop
3779 // to do alignment.
3780
3781 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3782 return;
3783
3784 #endif // ASSERT
3785
3786 if (UseAddressNop && VM_Version::is_intel()) {
3787 //
3788 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3789 // 1: 0x90
3790 // 2: 0x66 0x90
3791 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3792 // 4: 0x0F 0x1F 0x40 0x00
3793 // 5: 0x0F 0x1F 0x44 0x00 0x00
3794 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3795 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3796 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3797 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3798 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3799 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3800
3801 // The rest coding is Intel specific - don't use consecutive address nops
3802
3803 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3804 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3805 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3806 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3807
3808 while(i >= 15) {
3809 // For Intel don't generate consecutive address nops (mix with regular nops)
3810 i -= 15;
3811 emit_int24(0x66, 0x66, 0x66);
3812 addr_nop_8();
3813 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3814 }
3815 switch (i) {
3816 case 14:
3817 emit_int8(0x66); // size prefix
3818 case 13:
3819 emit_int8(0x66); // size prefix
3820 case 12:
3821 addr_nop_8();
3822 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3823 break;
3824 case 11:
3825 emit_int8(0x66); // size prefix
3826 case 10:
3827 emit_int8(0x66); // size prefix
3828 case 9:
3829 emit_int8(0x66); // size prefix
3830 case 8:
3831 addr_nop_8();
3832 break;
3833 case 7:
3834 addr_nop_7();
3835 break;
3836 case 6:
3837 emit_int8(0x66); // size prefix
3838 case 5:
3839 addr_nop_5();
3840 break;
3841 case 4:
3842 addr_nop_4();
3843 break;
3844 case 3:
3845 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3846 emit_int8(0x66); // size prefix
3847 case 2:
3848 emit_int8(0x66); // size prefix
3849 case 1:
3850 emit_int8((unsigned char)0x90);
3851 // nop
3852 break;
3853 default:
3854 assert(i == 0, " ");
3855 }
3856 return;
3857 }
3858 if (UseAddressNop && VM_Version::is_amd_family()) {
3859 //
3860 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3861 // 1: 0x90
3862 // 2: 0x66 0x90
3863 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3864 // 4: 0x0F 0x1F 0x40 0x00
3865 // 5: 0x0F 0x1F 0x44 0x00 0x00
3866 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3867 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3868 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3869 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3870 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3871 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3872
3873 // The rest coding is AMD specific - use consecutive address nops
3874
3875 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3876 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3877 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3878 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3879 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3880 // Size prefixes (0x66) are added for larger sizes
3881
3882 while(i >= 22) {
3883 i -= 11;
3884 emit_int24(0x66, 0x66, 0x66);
3885 addr_nop_8();
3886 }
3887 // Generate first nop for size between 21-12
3888 switch (i) {
3889 case 21:
3890 i -= 1;
3891 emit_int8(0x66); // size prefix
3892 case 20:
3893 case 19:
3894 i -= 1;
3895 emit_int8(0x66); // size prefix
3896 case 18:
3897 case 17:
3898 i -= 1;
3899 emit_int8(0x66); // size prefix
3900 case 16:
3901 case 15:
3902 i -= 8;
3903 addr_nop_8();
3904 break;
3905 case 14:
3906 case 13:
3907 i -= 7;
3908 addr_nop_7();
3909 break;
3910 case 12:
3911 i -= 6;
3912 emit_int8(0x66); // size prefix
3913 addr_nop_5();
3914 break;
3915 default:
3916 assert(i < 12, " ");
3917 }
3918
3919 // Generate second nop for size between 11-1
3920 switch (i) {
3921 case 11:
3922 emit_int8(0x66); // size prefix
3923 case 10:
3924 emit_int8(0x66); // size prefix
3925 case 9:
3926 emit_int8(0x66); // size prefix
3927 case 8:
3928 addr_nop_8();
3929 break;
3930 case 7:
3931 addr_nop_7();
3932 break;
3933 case 6:
3934 emit_int8(0x66); // size prefix
3935 case 5:
3936 addr_nop_5();
3937 break;
3938 case 4:
3939 addr_nop_4();
3940 break;
3941 case 3:
3942 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3943 emit_int8(0x66); // size prefix
3944 case 2:
3945 emit_int8(0x66); // size prefix
3946 case 1:
3947 emit_int8((unsigned char)0x90);
3948 // nop
3949 break;
3950 default:
3951 assert(i == 0, " ");
3952 }
3953 return;
3954 }
3955
3956 if (UseAddressNop && VM_Version::is_zx()) {
3957 //
3958 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3959 // 1: 0x90
3960 // 2: 0x66 0x90
3961 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3962 // 4: 0x0F 0x1F 0x40 0x00
3963 // 5: 0x0F 0x1F 0x44 0x00 0x00
3964 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3965 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3966 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3967 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3968 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3969 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3970
3971 // The rest coding is ZX specific - don't use consecutive address nops
3972
3973 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3974 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3975 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3976 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3977
3978 while (i >= 15) {
3979 // For ZX don't generate consecutive address nops (mix with regular nops)
3980 i -= 15;
3981 emit_int24(0x66, 0x66, 0x66);
3982 addr_nop_8();
3983 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3984 }
3985 switch (i) {
3986 case 14:
3987 emit_int8(0x66); // size prefix
3988 case 13:
3989 emit_int8(0x66); // size prefix
3990 case 12:
3991 addr_nop_8();
3992 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
3993 break;
3994 case 11:
3995 emit_int8(0x66); // size prefix
3996 case 10:
3997 emit_int8(0x66); // size prefix
3998 case 9:
3999 emit_int8(0x66); // size prefix
4000 case 8:
4001 addr_nop_8();
4002 break;
4003 case 7:
4004 addr_nop_7();
4005 break;
4006 case 6:
4007 emit_int8(0x66); // size prefix
4008 case 5:
4009 addr_nop_5();
4010 break;
4011 case 4:
4012 addr_nop_4();
4013 break;
4014 case 3:
4015 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
4016 emit_int8(0x66); // size prefix
4017 case 2:
4018 emit_int8(0x66); // size prefix
4019 case 1:
4020 emit_int8((unsigned char)0x90);
4021 // nop
4022 break;
4023 default:
4024 assert(i == 0, " ");
4025 }
4026 return;
4027 }
4028
4029 // Using nops with size prefixes "0x66 0x90".
4030 // From AMD Optimization Guide:
4031 // 1: 0x90
4032 // 2: 0x66 0x90
4033 // 3: 0x66 0x66 0x90
4034 // 4: 0x66 0x66 0x66 0x90
4035 // 5: 0x66 0x66 0x90 0x66 0x90
4036 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
4037 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
4038 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
4039 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4040 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
4041 //
4042 while (i > 12) {
4043 i -= 4;
4044 emit_int32(0x66, 0x66, 0x66, (unsigned char)0x90);
4045 }
4046 // 1 - 12 nops
4047 if (i > 8) {
4048 if (i > 9) {
4049 i -= 1;
4050 emit_int8(0x66);
4051 }
4052 i -= 3;
4053 emit_int24(0x66, 0x66, (unsigned char)0x90);
4054 }
4055 // 1 - 8 nops
4056 if (i > 4) {
4057 if (i > 6) {
4058 i -= 1;
4059 emit_int8(0x66);
4060 }
4061 i -= 3;
4062 emit_int24(0x66, 0x66, (unsigned char)0x90);
4063 }
4064 switch (i) {
4065 case 4:
4066 emit_int8(0x66);
4067 case 3:
4068 emit_int8(0x66);
4069 case 2:
4070 emit_int8(0x66);
4071 case 1:
4072 emit_int8((unsigned char)0x90);
4073 break;
4074 default:
4075 assert(i == 0, " ");
4076 }
4077 }
4078
4079 void Assembler::notl(Register dst) {
4080 int encode = prefix_and_encode(dst->encoding());
4081 emit_int16((unsigned char)0xF7, (0xD0 | encode));
4082 }
4083
4084 void Assembler::orw(Register dst, Register src) {
4085 (void)prefix_and_encode(dst->encoding(), src->encoding());
4086 emit_arith(0x0B, 0xC0, dst, src);
4087 }
4088
4089 void Assembler::orl(Address dst, int32_t imm32) {
4090 InstructionMark im(this);
4091 prefix(dst);
4092 emit_arith_operand(0x81, rcx, dst, imm32);
4093 }
4094
4095 void Assembler::orl(Register dst, int32_t imm32) {
4096 prefix(dst);
4097 emit_arith(0x81, 0xC8, dst, imm32);
4098 }
4099
4100 void Assembler::orl(Register dst, Address src) {
4101 InstructionMark im(this);
4102 prefix(src, dst);
4103 emit_int8(0x0B);
4104 emit_operand(dst, src, 0);
4105 }
4106
4107 void Assembler::orl(Register dst, Register src) {
4108 (void) prefix_and_encode(dst->encoding(), src->encoding());
4109 emit_arith(0x0B, 0xC0, dst, src);
4110 }
4111
4112 void Assembler::orl(Address dst, Register src) {
4113 InstructionMark im(this);
4114 prefix(dst, src);
4115 emit_int8(0x09);
4116 emit_operand(src, dst, 0);
4117 }
4118
4119 void Assembler::orb(Address dst, int imm8) {
4120 InstructionMark im(this);
4121 prefix(dst);
4122 emit_int8((unsigned char)0x80);
4123 emit_operand(rcx, dst, 1);
4124 emit_int8(imm8);
4125 }
4126
4127 void Assembler::orb(Address dst, Register src) {
4128 InstructionMark im(this);
4129 prefix(dst, src, true);
4130 emit_int8(0x08);
4131 emit_operand(src, dst, 0);
4132 }
4133
4134 void Assembler::packsswb(XMMRegister dst, XMMRegister src) {
4135 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4136 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4137 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4138 emit_int16(0x63, (0xC0 | encode));
4139 }
4140
4141 void Assembler::vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4142 assert(UseAVX > 0, "some form of AVX must be enabled");
4143 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4144 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4145 emit_int16(0x63, (0xC0 | encode));
4146 }
4147
4148 void Assembler::packssdw(XMMRegister dst, XMMRegister src) {
4149 assert(VM_Version::supports_sse2(), "");
4150 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4151 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4152 emit_int16(0x6B, (0xC0 | encode));
4153 }
4154
4155 void Assembler::vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4156 assert(UseAVX > 0, "some form of AVX must be enabled");
4157 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4158 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4159 emit_int16(0x6B, (0xC0 | encode));
4160 }
4161
4162 void Assembler::packuswb(XMMRegister dst, Address src) {
4163 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4164 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4165 InstructionMark im(this);
4166 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4167 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4168 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4169 emit_int8(0x67);
4170 emit_operand(dst, src, 0);
4171 }
4172
4173 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
4174 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4175 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4176 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4177 emit_int16(0x67, (0xC0 | encode));
4178 }
4179
4180 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4181 assert(UseAVX > 0, "some form of AVX must be enabled");
4182 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4183 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4184 emit_int16(0x67, (0xC0 | encode));
4185 }
4186
4187 void Assembler::packusdw(XMMRegister dst, XMMRegister src) {
4188 assert(VM_Version::supports_sse4_1(), "");
4189 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4190 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4191 emit_int16(0x2B, (0xC0 | encode));
4192 }
4193
4194 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4195 assert(UseAVX > 0, "some form of AVX must be enabled");
4196 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4197 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4198 emit_int16(0x2B, (0xC0 | encode));
4199 }
4200
4201 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4202 assert(VM_Version::supports_avx2(), "");
4203 assert(vector_len != AVX_128bit, "");
4204 // VEX.256.66.0F3A.W1 00 /r ib
4205 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4206 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4207 emit_int24(0x00, (0xC0 | encode), imm8);
4208 }
4209
4210 void Assembler::vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4211 assert(vector_len == AVX_256bit ? VM_Version::supports_avx512vl() :
4212 vector_len == AVX_512bit ? VM_Version::supports_evex() : false, "not supported");
4213 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4214 attributes.set_is_evex_instruction();
4215 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4216 emit_int16(0x36, (0xC0 | encode));
4217 }
4218
4219 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4220 assert(VM_Version::supports_avx512_vbmi(), "");
4221 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4222 attributes.set_is_evex_instruction();
4223 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4224 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4225 }
4226
4227 void Assembler::vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4228 assert(VM_Version::supports_avx512_vbmi(), "");
4229 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4230 attributes.set_is_evex_instruction();
4231 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4232 emit_int8((unsigned char)0x8D);
4233 emit_operand(dst, src, 0);
4234 }
4235
4236 void Assembler::vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4237 assert(vector_len == AVX_128bit ? VM_Version::supports_avx512vlbw() :
4238 vector_len == AVX_256bit ? VM_Version::supports_avx512vlbw() :
4239 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false, "not supported");
4240 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4241 attributes.set_is_evex_instruction();
4242 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4243 emit_int16((unsigned char)0x8D, (0xC0 | encode));
4244 }
4245
4246 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4247 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4248 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4249 // VEX.NDS.256.66.0F38.W0 36 /r
4250 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4251 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4252 emit_int16(0x36, (0xC0 | encode));
4253 }
4254
4255 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
4256 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4257 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4258 // VEX.NDS.256.66.0F38.W0 36 /r
4259 InstructionMark im(this);
4260 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4261 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4262 emit_int8(0x36);
4263 emit_operand(dst, src, 0);
4264 }
4265
4266 void Assembler::vpermps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4267 assert((vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
4268 (vector_len == AVX_512bit && VM_Version::supports_evex()), "");
4269 // VEX.NDS.XXX.66.0F38.W0 16 /r
4270 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4271 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4272 emit_int16(0x16, (0xC0 | encode));
4273 }
4274
4275 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4276 assert(VM_Version::supports_avx2(), "");
4277 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4278 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4279 emit_int24(0x46, (0xC0 | encode), imm8);
4280 }
4281
4282 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4283 assert(VM_Version::supports_avx(), "");
4284 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4285 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4286 emit_int24(0x06, (0xC0 | encode), imm8);
4287 }
4288
4289 void Assembler::vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4290 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4291 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4292 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4293 emit_int24(0x04, (0xC0 | encode), imm8);
4294 }
4295
4296 void Assembler::vpermilps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4297 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4298 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4299 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4300 emit_int16(0x0C, (0xC0 | encode));
4301 }
4302
4303 void Assembler::vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4304 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx() : VM_Version::supports_evex(), "");
4305 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(),/* legacy_mode */ false,/* no_mask_reg */ true, /* uses_vl */ false);
4306 attributes.set_rex_vex_w_reverted();
4307 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4308 emit_int24(0x05, (0xC0 | encode), imm8);
4309 }
4310
4311 void Assembler::vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
4312 assert(vector_len <= AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex(), "");
4313 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */false, /* no_mask_reg */ true, /* uses_vl */ false);
4314 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4315 emit_int24(0x01, (0xC0 | encode), imm8);
4316 }
4317
4318 void Assembler::evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4319 assert(VM_Version::supports_evex(), "");
4320 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4321 attributes.set_is_evex_instruction();
4322 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4323 emit_int16(0x76, (0xC0 | encode));
4324 }
4325
4326 void Assembler::evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4327 assert(VM_Version::supports_avx512_vbmi(), "");
4328 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4329 attributes.set_is_evex_instruction();
4330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4331 emit_int16(0x7D, (0xC0 | encode));
4332 }
4333
4334 void Assembler::evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len) {
4335 assert(VM_Version::supports_avx512_vbmi(), "");
4336 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4337 attributes.set_is_evex_instruction();
4338 int encode = vex_prefix_and_encode(dst->encoding(), ctl->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4339 emit_int16((unsigned char)0x83, (unsigned char)(0xC0 | encode));
4340 }
4341
4342 void Assembler::pause() {
4343 emit_int16((unsigned char)0xF3, (unsigned char)0x90);
4344 }
4345
4346 void Assembler::ud2() {
4347 emit_int16(0x0F, 0x0B);
4348 }
4349
4350 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
4351 assert(VM_Version::supports_sse4_2(), "");
4352 InstructionMark im(this);
4353 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4354 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4355 emit_int8(0x61);
4356 emit_operand(dst, src, 1);
4357 emit_int8(imm8);
4358 }
4359
4360 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
4361 assert(VM_Version::supports_sse4_2(), "");
4362 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4363 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4364 emit_int24(0x61, (0xC0 | encode), imm8);
4365 }
4366
4367 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4368 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
4369 assert(VM_Version::supports_sse2(), "");
4370 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4371 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4372 emit_int16(0x74, (0xC0 | encode));
4373 }
4374
4375 void Assembler::vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4376 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4377 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4378 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4379 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4380 emit_int16(cond_encoding, (0xC0 | encode));
4381 }
4382
4383 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4384 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4385 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4386 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4387 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4388 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4389 emit_int16(0x74, (0xC0 | encode));
4390 }
4391
4392 // In this context, kdst is written the mask used to process the equal components
4393 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4394 assert(VM_Version::supports_avx512bw(), "");
4395 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4396 attributes.set_is_evex_instruction();
4397 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4398 emit_int16(0x74, (0xC0 | encode));
4399 }
4400
4401 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4402 assert(VM_Version::supports_avx512vlbw(), "");
4403 InstructionMark im(this);
4404 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4405 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4406 attributes.set_is_evex_instruction();
4407 int dst_enc = kdst->encoding();
4408 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4409 emit_int8(0x64);
4410 emit_operand(as_Register(dst_enc), src, 0);
4411 }
4412
4413 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4414 assert(VM_Version::supports_avx512vlbw(), "");
4415 InstructionMark im(this);
4416 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4417 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4418 attributes.reset_is_clear_context();
4419 attributes.set_embedded_opmask_register_specifier(mask);
4420 attributes.set_is_evex_instruction();
4421 int dst_enc = kdst->encoding();
4422 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4423 emit_int8(0x64);
4424 emit_operand(as_Register(dst_enc), src, 0);
4425 }
4426
4427 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4428 assert(VM_Version::supports_avx512vlbw(), "");
4429 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4430 attributes.set_is_evex_instruction();
4431 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4432 emit_int24(0x3E, (0xC0 | encode), vcc);
4433 }
4434
4435 void Assembler::evpcmpuq(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
4436 assert(VM_Version::supports_avx512vl(), "");
4437 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4438 attributes.set_is_evex_instruction();
4439 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4440 emit_int24(0x1E, (0xC0 | encode), vcc);
4441 }
4442
4443 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
4444 assert(VM_Version::supports_avx512vlbw(), "");
4445 InstructionMark im(this);
4446 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4447 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4448 attributes.set_is_evex_instruction();
4449 int dst_enc = kdst->encoding();
4450 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4451 emit_int8(0x3E);
4452 emit_operand(as_Register(dst_enc), src, 1);
4453 emit_int8(vcc);
4454 }
4455
4456 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4457 assert(VM_Version::supports_avx512bw(), "");
4458 InstructionMark im(this);
4459 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4460 attributes.set_is_evex_instruction();
4461 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4462 int dst_enc = kdst->encoding();
4463 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4464 emit_int8(0x74);
4465 emit_operand(as_Register(dst_enc), src, 0);
4466 }
4467
4468 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4469 assert(VM_Version::supports_avx512vlbw(), "");
4470 InstructionMark im(this);
4471 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4472 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4473 attributes.reset_is_clear_context();
4474 attributes.set_embedded_opmask_register_specifier(mask);
4475 attributes.set_is_evex_instruction();
4476 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4477 emit_int8(0x74);
4478 emit_operand(as_Register(kdst->encoding()), src, 0);
4479 }
4480
4481 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4482 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
4483 assert(VM_Version::supports_sse2(), "");
4484 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4485 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4486 emit_int16(0x75, (0xC0 | encode));
4487 }
4488
4489 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4490 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4491 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4492 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4493 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4494 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4495 emit_int16(0x75, (0xC0 | encode));
4496 }
4497
4498 // In this context, kdst is written the mask used to process the equal components
4499 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4500 assert(VM_Version::supports_avx512bw(), "");
4501 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4502 attributes.set_is_evex_instruction();
4503 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4504 emit_int16(0x75, (0xC0 | encode));
4505 }
4506
4507 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4508 assert(VM_Version::supports_avx512bw(), "");
4509 InstructionMark im(this);
4510 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4511 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4512 attributes.set_is_evex_instruction();
4513 int dst_enc = kdst->encoding();
4514 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4515 emit_int8(0x75);
4516 emit_operand(as_Register(dst_enc), src, 0);
4517 }
4518
4519 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4520 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
4521 assert(VM_Version::supports_sse2(), "");
4522 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4523 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4524 emit_int16(0x76, (0xC0 | encode));
4525 }
4526
4527 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4528 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4529 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
4530 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
4531 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4532 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4533 emit_int16(0x76, (0xC0 | encode));
4534 }
4535
4536 // In this context, kdst is written the mask used to process the equal components
4537 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4538 assert(VM_Version::supports_evex(), "");
4539 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4540 attributes.set_is_evex_instruction();
4541 attributes.reset_is_clear_context();
4542 attributes.set_embedded_opmask_register_specifier(mask);
4543 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4544 emit_int16(0x76, (0xC0 | encode));
4545 }
4546
4547 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
4548 assert(VM_Version::supports_evex(), "");
4549 InstructionMark im(this);
4550 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4551 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4552 attributes.set_is_evex_instruction();
4553 attributes.reset_is_clear_context();
4554 attributes.set_embedded_opmask_register_specifier(mask);
4555 int dst_enc = kdst->encoding();
4556 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4557 emit_int8(0x76);
4558 emit_operand(as_Register(dst_enc), src, 0);
4559 }
4560
4561 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4562 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
4563 assert(VM_Version::supports_sse4_1(), "");
4564 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4565 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4566 emit_int16(0x29, (0xC0 | encode));
4567 }
4568
4569 void Assembler::evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
4570 assert(VM_Version::supports_evex(), "");
4571 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4572 attributes.set_is_evex_instruction();
4573 attributes.reset_is_clear_context();
4574 attributes.set_embedded_opmask_register_specifier(mask);
4575 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4576 emit_int16(0x29, (0xC0 | encode));
4577 }
4578
4579 void Assembler::vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len) {
4580 assert(VM_Version::supports_avx(), "");
4581 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4582 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4583 emit_int16(cond_encoding, (0xC0 | encode));
4584 }
4585
4586 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
4587 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4588 assert(VM_Version::supports_avx(), "");
4589 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4590 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4591 emit_int16(0x29, (0xC0 | encode));
4592 }
4593
4594 // In this context, kdst is written the mask used to process the equal components
4595 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
4596 assert(VM_Version::supports_evex(), "");
4597 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4598 attributes.reset_is_clear_context();
4599 attributes.set_is_evex_instruction();
4600 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4601 emit_int16(0x29, (0xC0 | encode));
4602 }
4603
4604 // In this context, kdst is written the mask used to process the equal components
4605 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
4606 assert(VM_Version::supports_evex(), "");
4607 InstructionMark im(this);
4608 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4609 attributes.reset_is_clear_context();
4610 attributes.set_is_evex_instruction();
4611 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
4612 int dst_enc = kdst->encoding();
4613 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4614 emit_int8(0x29);
4615 emit_operand(as_Register(dst_enc), src, 0);
4616 }
4617
4618 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
4619 assert(VM_Version::supports_sse4_1(), "");
4620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4621 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4622 emit_int16(0x37, (0xC0 | encode));
4623 }
4624
4625 void Assembler::pmovmskb(Register dst, XMMRegister src) {
4626 assert(VM_Version::supports_sse2(), "");
4627 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4628 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4629 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4630 }
4631
4632 void Assembler::vpmovmskb(Register dst, XMMRegister src, int vec_enc) {
4633 assert((VM_Version::supports_avx() && vec_enc == AVX_128bit) ||
4634 (VM_Version::supports_avx2() && vec_enc == AVX_256bit), "");
4635 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4636 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4637 emit_int16((unsigned char)0xD7, (0xC0 | encode));
4638 }
4639
4640 void Assembler::vmovmskps(Register dst, XMMRegister src, int vec_enc) {
4641 assert(VM_Version::supports_avx(), "");
4642 InstructionAttr attributes(vec_enc, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4643 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4644 emit_int16(0x50, (0xC0 | encode));
4645 }
4646
4647 void Assembler::vmovmskpd(Register dst, XMMRegister src, int vec_enc) {
4648 assert(VM_Version::supports_avx(), "");
4649 InstructionAttr attributes(vec_enc, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4650 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4651 emit_int16(0x50, (0xC0 | encode));
4652 }
4653
4654
4655 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
4656 assert(VM_Version::supports_sse4_1(), "");
4657 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4658 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4659 emit_int24(0x16, (0xC0 | encode), imm8);
4660 }
4661
4662 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
4663 assert(VM_Version::supports_sse4_1(), "");
4664 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4665 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4666 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4667 emit_int8(0x16);
4668 emit_operand(src, dst, 1);
4669 emit_int8(imm8);
4670 }
4671
4672 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
4673 assert(VM_Version::supports_sse4_1(), "");
4674 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4675 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4676 emit_int24(0x16, (0xC0 | encode), imm8);
4677 }
4678
4679 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
4680 assert(VM_Version::supports_sse4_1(), "");
4681 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4682 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4683 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4684 emit_int8(0x16);
4685 emit_operand(src, dst, 1);
4686 emit_int8(imm8);
4687 }
4688
4689 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
4690 assert(VM_Version::supports_sse2(), "");
4691 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4692 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4693 emit_int24((unsigned char)0xC5, (0xC0 | encode), imm8);
4694 }
4695
4696 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
4697 assert(VM_Version::supports_sse4_1(), "");
4698 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4699 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4700 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4701 emit_int8(0x15);
4702 emit_operand(src, dst, 1);
4703 emit_int8(imm8);
4704 }
4705
4706 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
4707 assert(VM_Version::supports_sse4_1(), "");
4708 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4709 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4710 emit_int24(0x14, (0xC0 | encode), imm8);
4711 }
4712
4713 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
4714 assert(VM_Version::supports_sse4_1(), "");
4715 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4716 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4717 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4718 emit_int8(0x14);
4719 emit_operand(src, dst, 1);
4720 emit_int8(imm8);
4721 }
4722
4723 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
4724 assert(VM_Version::supports_sse4_1(), "");
4725 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4726 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4727 emit_int24(0x22, (0xC0 | encode), imm8);
4728 }
4729
4730 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
4731 assert(VM_Version::supports_sse4_1(), "");
4732 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4733 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4734 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4735 emit_int8(0x22);
4736 emit_operand(dst, src, 1);
4737 emit_int8(imm8);
4738 }
4739
4740 void Assembler::vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4741 assert(VM_Version::supports_avx(), "");
4742 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4743 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4744 emit_int24(0x22, (0xC0 | encode), imm8);
4745 }
4746
4747 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
4748 assert(VM_Version::supports_sse4_1(), "");
4749 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4750 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4751 emit_int24(0x22, (0xC0 | encode), imm8);
4752 }
4753
4754 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
4755 assert(VM_Version::supports_sse4_1(), "");
4756 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4757 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4758 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4759 emit_int8(0x22);
4760 emit_operand(dst, src, 1);
4761 emit_int8(imm8);
4762 }
4763
4764 void Assembler::vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4765 assert(VM_Version::supports_avx(), "");
4766 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4767 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4768 emit_int24(0x22, (0xC0 | encode), imm8);
4769 }
4770
4771 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
4772 assert(VM_Version::supports_sse2(), "");
4773 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4774 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4775 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4776 }
4777
4778 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
4779 assert(VM_Version::supports_sse2(), "");
4780 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4781 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4782 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4783 emit_int8((unsigned char)0xC4);
4784 emit_operand(dst, src, 1);
4785 emit_int8(imm8);
4786 }
4787
4788 void Assembler::vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4789 assert(VM_Version::supports_avx(), "");
4790 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4791 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4792 emit_int24((unsigned char)0xC4, (0xC0 | encode), imm8);
4793 }
4794
4795 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
4796 assert(VM_Version::supports_sse4_1(), "");
4797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4798 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4799 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4800 emit_int8(0x20);
4801 emit_operand(dst, src, 1);
4802 emit_int8(imm8);
4803 }
4804
4805 void Assembler::pinsrb(XMMRegister dst, Register src, int imm8) {
4806 assert(VM_Version::supports_sse4_1(), "");
4807 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4808 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4809 emit_int24(0x20, (0xC0 | encode), imm8);
4810 }
4811
4812 void Assembler::vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8) {
4813 assert(VM_Version::supports_avx(), "");
4814 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4815 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4816 emit_int24(0x20, (0xC0 | encode), imm8);
4817 }
4818
4819 void Assembler::insertps(XMMRegister dst, XMMRegister src, int imm8) {
4820 assert(VM_Version::supports_sse4_1(), "");
4821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4822 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4823 emit_int24(0x21, (0xC0 | encode), imm8);
4824 }
4825
4826 void Assembler::vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
4827 assert(VM_Version::supports_avx(), "");
4828 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4829 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4830 emit_int24(0x21, (0xC0 | encode), imm8);
4831 }
4832
4833 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
4834 assert(VM_Version::supports_sse4_1(), "");
4835 InstructionMark im(this);
4836 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4837 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4838 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4839 emit_int8(0x30);
4840 emit_operand(dst, src, 0);
4841 }
4842
4843 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4844 assert(VM_Version::supports_sse4_1(), "");
4845 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4846 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4847 emit_int16(0x30, (0xC0 | encode));
4848 }
4849
4850 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
4851 assert(VM_Version::supports_sse4_1(), "");
4852 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4853 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4854 emit_int16(0x20, (0xC0 | encode));
4855 }
4856
4857 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
4858 assert(VM_Version::supports_sse4_1(), "");
4859 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4860 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4861 emit_int16(0x35, (0xC0 | encode));
4862 }
4863
4864 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
4865 assert(VM_Version::supports_sse4_1(), "");
4866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4867 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4868 emit_int16(0x21, (0xC0 | encode));
4869 }
4870
4871 void Assembler::pmovzxbd(XMMRegister dst, XMMRegister src) {
4872 assert(VM_Version::supports_sse4_1(), "");
4873 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4874 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4875 emit_int16(0x31, (0xC0 | encode));
4876 }
4877
4878 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
4879 assert(VM_Version::supports_sse4_1(), "");
4880 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4881 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4882 emit_int16(0x22, (0xC0 | encode));
4883 }
4884
4885 void Assembler::pmovsxwd(XMMRegister dst, XMMRegister src) {
4886 assert(VM_Version::supports_sse4_1(), "");
4887 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4888 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4889 emit_int16(0x23, (0xC0 | encode));
4890 }
4891
4892 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4893 assert(VM_Version::supports_avx(), "");
4894 InstructionMark im(this);
4895 assert(dst != xnoreg, "sanity");
4896 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4897 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4898 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4899 emit_int8(0x30);
4900 emit_operand(dst, src, 0);
4901 }
4902
4903 void Assembler::vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4904 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4905 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4906 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4907 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4908 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4909 emit_int16(0x30, (unsigned char) (0xC0 | encode));
4910 }
4911
4912 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4913 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4914 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4915 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
4916 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4917 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4918 emit_int16(0x20, (0xC0 | encode));
4919 }
4920
4921 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4922 assert(VM_Version::supports_avx512vlbw(), "");
4923 assert(dst != xnoreg, "sanity");
4924 InstructionMark im(this);
4925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4926 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4927 attributes.set_embedded_opmask_register_specifier(mask);
4928 attributes.set_is_evex_instruction();
4929 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4930 emit_int8(0x30);
4931 emit_operand(dst, src, 0);
4932 }
4933
4934 void Assembler::evpmovzxbd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4935 assert(VM_Version::supports_avx512vl(), "");
4936 assert(dst != xnoreg, "sanity");
4937 InstructionMark im(this);
4938 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4939 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4940 attributes.set_embedded_opmask_register_specifier(mask);
4941 attributes.set_is_evex_instruction();
4942 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4943 emit_int8(0x31);
4944 emit_operand(dst, src, 0);
4945 }
4946
4947 void Assembler::evpmovzxbd(XMMRegister dst, Address src, int vector_len) {
4948 evpmovzxbd(dst, k0, src, vector_len);
4949 }
4950
4951 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
4952 assert(VM_Version::supports_evex(), "");
4953 // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
4954 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4955 attributes.set_is_evex_instruction();
4956 attributes.set_embedded_opmask_register_specifier(mask);
4957 if (merge) {
4958 attributes.reset_is_clear_context();
4959 }
4960 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4961 emit_int16((unsigned char)0xDB, (0xC0 | encode));
4962 }
4963
4964 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4965 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4966 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4967 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4968 emit_int16(0x35, (0xC0 | encode));
4969 }
4970
4971 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4972 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4973 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4974 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4975 emit_int16(0x31, (0xC0 | encode));
4976 }
4977
4978 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4979 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4980 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4981 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4982 emit_int16(0x32, (0xC0 | encode));
4983 }
4984
4985 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4986 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4987 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4988 VM_Version::supports_evex(), "");
4989 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4990 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4991 emit_int16(0x21, (0xC0 | encode));
4992 }
4993
4994 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4995 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
4996 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
4997 VM_Version::supports_evex(), "");
4998 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
4999 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5000 emit_int16(0x22, (0xC0 | encode));
5001 }
5002
5003 void Assembler::vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5004 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5005 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5006 VM_Version::supports_evex(), "");
5007 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5008 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5009 emit_int16(0x23, (0xC0 | encode));
5010 }
5011
5012 void Assembler::vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5013 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5014 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5015 VM_Version::supports_evex(), "");
5016 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5017 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5018 emit_int16(0x24, (0xC0 | encode));
5019 }
5020
5021 void Assembler::vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len) {
5022 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5023 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5024 VM_Version::supports_evex(), "");
5025 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5026 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5027 emit_int16(0x25, (0xC0 | encode));
5028 }
5029
5030 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
5031 assert(VM_Version::supports_avx512vlbw(), "");
5032 assert(src != xnoreg, "sanity");
5033 InstructionMark im(this);
5034 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5035 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5036 attributes.set_is_evex_instruction();
5037 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5038 emit_int8(0x30);
5039 emit_operand(src, dst, 0);
5040 }
5041
5042 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
5043 assert(VM_Version::supports_avx512vlbw(), "");
5044 assert(src != xnoreg, "sanity");
5045 InstructionMark im(this);
5046 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5047 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
5048 attributes.reset_is_clear_context();
5049 attributes.set_embedded_opmask_register_specifier(mask);
5050 attributes.set_is_evex_instruction();
5051 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5052 emit_int8(0x30);
5053 emit_operand(src, dst, 0);
5054 }
5055
5056 void Assembler::evpmovdb(Address dst, XMMRegister src, int vector_len) {
5057 assert(VM_Version::supports_evex(), "");
5058 assert(src != xnoreg, "sanity");
5059 InstructionMark im(this);
5060 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5061 attributes.set_address_attributes(/* tuple_type */ EVEX_QVM, /* input_size_in_bits */ EVEX_NObit);
5062 attributes.set_is_evex_instruction();
5063 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5064 emit_int8(0x31);
5065 emit_operand(src, dst, 0);
5066 }
5067
5068 void Assembler::vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len) {
5069 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5070 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5071 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5072 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5073 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5074 emit_int16(0x33, (0xC0 | encode));
5075 }
5076
5077 void Assembler::vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len) {
5078 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5079 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5080 vector_len == AVX_512bit? VM_Version::supports_evex() : 0, " ");
5081 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5082 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5083 emit_int16(0x34, (0xC0 | encode));
5084 }
5085
5086 void Assembler::pmaddwd(XMMRegister dst, XMMRegister src) {
5087 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5088 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5089 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5090 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5091 }
5092
5093 void Assembler::vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5094 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5095 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5096 (vector_len == AVX_512bit ? VM_Version::supports_evex() : 0)), "");
5097 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5098 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5099 emit_int16((unsigned char)0xF5, (0xC0 | encode));
5100 }
5101
5102 void Assembler::vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5103 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5104 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5105 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5106 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5107 int encode = simd_prefix_and_encode(dst, src1, src2, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5108 emit_int16(0x04, (0xC0 | encode));
5109 }
5110
5111 void Assembler::evpmadd52luq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5112 evpmadd52luq(dst, k0, src1, src2, false, vector_len);
5113 }
5114
5115 void Assembler::evpmadd52luq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5116 assert(VM_Version::supports_avx512ifma(), "");
5117 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5118 attributes.set_is_evex_instruction();
5119 attributes.set_embedded_opmask_register_specifier(mask);
5120 if (merge) {
5121 attributes.reset_is_clear_context();
5122 }
5123
5124 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5125 emit_int16((unsigned char)0xB4, (0xC0 | encode));
5126 }
5127
5128 void Assembler::evpmadd52huq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5129 evpmadd52huq(dst, k0, src1, src2, false, vector_len);
5130 }
5131
5132 void Assembler::evpmadd52huq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5133 assert(VM_Version::supports_avx512ifma(), "");
5134 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5135 attributes.set_is_evex_instruction();
5136 attributes.set_embedded_opmask_register_specifier(mask);
5137 if (merge) {
5138 attributes.reset_is_clear_context();
5139 }
5140
5141 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5142 emit_int16((unsigned char)0xB5, (0xC0 | encode));
5143 }
5144
5145 void Assembler::evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5146 assert(VM_Version::supports_evex(), "");
5147 assert(VM_Version::supports_avx512_vnni(), "must support vnni");
5148 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5149 attributes.set_is_evex_instruction();
5150 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5151 emit_int16(0x52, (0xC0 | encode));
5152 }
5153
5154 // generic
5155 void Assembler::pop(Register dst) {
5156 int encode = prefix_and_encode(dst->encoding());
5157 emit_int8(0x58 | encode);
5158 }
5159
5160 void Assembler::popcntl(Register dst, Address src) {
5161 assert(VM_Version::supports_popcnt(), "must support");
5162 InstructionMark im(this);
5163 emit_int8((unsigned char)0xF3);
5164 prefix(src, dst);
5165 emit_int16(0x0F, (unsigned char)0xB8);
5166 emit_operand(dst, src, 0);
5167 }
5168
5169 void Assembler::popcntl(Register dst, Register src) {
5170 assert(VM_Version::supports_popcnt(), "must support");
5171 emit_int8((unsigned char)0xF3);
5172 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5173 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
5174 }
5175
5176 void Assembler::evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5177 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5178 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5179 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5180 attributes.set_embedded_opmask_register_specifier(mask);
5181 attributes.set_is_evex_instruction();
5182 if (merge) {
5183 attributes.reset_is_clear_context();
5184 }
5185 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5186 emit_int16(0x54, (0xC0 | encode));
5187 }
5188
5189 void Assembler::evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5190 assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
5191 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5192 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5193 attributes.set_is_evex_instruction();
5194 attributes.set_embedded_opmask_register_specifier(mask);
5195 if (merge) {
5196 attributes.reset_is_clear_context();
5197 }
5198 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5199 emit_int16(0x54, (0xC0 | encode));
5200 }
5201
5202 void Assembler::evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5203 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5204 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5205 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5206 attributes.set_is_evex_instruction();
5207 attributes.set_embedded_opmask_register_specifier(mask);
5208 if (merge) {
5209 attributes.reset_is_clear_context();
5210 }
5211 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5212 emit_int16(0x55, (0xC0 | encode));
5213 }
5214
5215 void Assembler::evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
5216 assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
5217 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
5218 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5219 attributes.set_is_evex_instruction();
5220 attributes.set_embedded_opmask_register_specifier(mask);
5221 if (merge) {
5222 attributes.reset_is_clear_context();
5223 }
5224 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5225 emit_int16(0x55, (0xC0 | encode));
5226 }
5227
5228 void Assembler::popf() {
5229 emit_int8((unsigned char)0x9D);
5230 }
5231
5232 #ifndef _LP64 // no 32bit push/pop on amd64
5233 void Assembler::popl(Address dst) {
5234 // NOTE: this will adjust stack by 8byte on 64bits
5235 InstructionMark im(this);
5236 prefix(dst);
5237 emit_int8((unsigned char)0x8F);
5238 emit_operand(rax, dst, 0);
5239 }
5240 #endif
5241
5242 void Assembler::prefetchnta(Address src) {
5243 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5244 InstructionMark im(this);
5245 prefix(src);
5246 emit_int16(0x0F, 0x18);
5247 emit_operand(rax, src, 0); // 0, src
5248 }
5249
5250 void Assembler::prefetchr(Address src) {
5251 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5252 InstructionMark im(this);
5253 prefix(src);
5254 emit_int16(0x0F, 0x0D);
5255 emit_operand(rax, src, 0); // 0, src
5256 }
5257
5258 void Assembler::prefetcht0(Address src) {
5259 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5260 InstructionMark im(this);
5261 prefix(src);
5262 emit_int16(0x0F, 0x18);
5263 emit_operand(rcx, src, 0); // 1, src
5264 }
5265
5266 void Assembler::prefetcht1(Address src) {
5267 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5268 InstructionMark im(this);
5269 prefix(src);
5270 emit_int16(0x0F, 0x18);
5271 emit_operand(rdx, src, 0); // 2, src
5272 }
5273
5274 void Assembler::prefetcht2(Address src) {
5275 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
5276 InstructionMark im(this);
5277 prefix(src);
5278 emit_int16(0x0F, 0x18);
5279 emit_operand(rbx, src, 0); // 3, src
5280 }
5281
5282 void Assembler::prefetchw(Address src) {
5283 assert(VM_Version::supports_3dnow_prefetch(), "must support");
5284 InstructionMark im(this);
5285 prefix(src);
5286 emit_int16(0x0F, 0x0D);
5287 emit_operand(rcx, src, 0); // 1, src
5288 }
5289
5290 void Assembler::prefix(Prefix p) {
5291 emit_int8(p);
5292 }
5293
5294 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
5295 assert(VM_Version::supports_ssse3(), "");
5296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5297 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5298 emit_int16(0x00, (0xC0 | encode));
5299 }
5300
5301 void Assembler::evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
5302 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
5303 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5304 attributes.set_is_evex_instruction();
5305 attributes.set_embedded_opmask_register_specifier(mask);
5306 if (merge) {
5307 attributes.reset_is_clear_context();
5308 }
5309 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5310 emit_int16(0x00, (0xC0 | encode));
5311 }
5312
5313 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5314 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5315 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5316 vector_len == AVX_512bit? VM_Version::supports_avx512bw() : 0, "");
5317 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5318 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5319 emit_int16(0x00, (0xC0 | encode));
5320 }
5321
5322 void Assembler::pshufb(XMMRegister dst, Address src) {
5323 assert(VM_Version::supports_ssse3(), "");
5324 InstructionMark im(this);
5325 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5326 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5327 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5328 emit_int8(0x00);
5329 emit_operand(dst, src, 0);
5330 }
5331
5332 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
5333 assert(isByte(mode), "invalid value");
5334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5335 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
5336 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5337 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5338 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5339 }
5340
5341 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5342 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5343 (vector_len == AVX_256bit? VM_Version::supports_avx2() :
5344 (vector_len == AVX_512bit? VM_Version::supports_evex() : 0)), "");
5345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5346 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5347 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5348 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5349 }
5350
5351 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
5352 assert(isByte(mode), "invalid value");
5353 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5354 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5355 InstructionMark im(this);
5356 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5357 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5358 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5359 emit_int8(0x70);
5360 emit_operand(dst, src, 1);
5361 emit_int8(mode & 0xFF);
5362 }
5363
5364 void Assembler::pshufhw(XMMRegister dst, XMMRegister src, int mode) {
5365 assert(isByte(mode), "invalid value");
5366 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5367 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5368 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5369 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5370 }
5371
5372 void Assembler::vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5373 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5374 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5375 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5376 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5377 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5378 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5379 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5380 }
5381
5382 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
5383 assert(isByte(mode), "invalid value");
5384 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5385 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5386 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5387 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5388 }
5389
5390 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
5391 assert(isByte(mode), "invalid value");
5392 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5393 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5394 InstructionMark im(this);
5395 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5396 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5397 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5398 emit_int8(0x70);
5399 emit_operand(dst, src, 1);
5400 emit_int8(mode & 0xFF);
5401 }
5402
5403 void Assembler::vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
5404 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5405 (vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5406 (vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : false)), "");
5407 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5408 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5409 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5410 emit_int24(0x70, (0xC0 | encode), mode & 0xFF);
5411 }
5412
5413 void Assembler::evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5414 assert(VM_Version::supports_evex(), "requires EVEX support");
5415 assert(vector_len == Assembler::AVX_256bit || vector_len == Assembler::AVX_512bit, "");
5416 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5417 attributes.set_is_evex_instruction();
5418 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5419 emit_int24(0x43, (0xC0 | encode), imm8 & 0xFF);
5420 }
5421
5422 void Assembler::shufpd(XMMRegister dst, XMMRegister src, int imm8) {
5423 assert(isByte(imm8), "invalid value");
5424 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5425 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5426 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5427 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5428 }
5429
5430 void Assembler::vshufpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5431 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5432 attributes.set_rex_vex_w_reverted();
5433 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5434 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5435 }
5436
5437 void Assembler::shufps(XMMRegister dst, XMMRegister src, int imm8) {
5438 assert(isByte(imm8), "invalid value");
5439 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5440 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5441 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5442 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5443 }
5444
5445 void Assembler::vshufps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5446 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5447 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5448 emit_int24((unsigned char)0xC6, (0xC0 | encode), imm8 & 0xFF);
5449 }
5450
5451 void Assembler::psrldq(XMMRegister dst, int shift) {
5452 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5453 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5454 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5455 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5456 emit_int24(0x73, (0xC0 | encode), shift);
5457 }
5458
5459 void Assembler::vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5460 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5461 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5462 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5463 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5464 int encode = vex_prefix_and_encode(xmm3->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5465 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5466 }
5467
5468 void Assembler::pslldq(XMMRegister dst, int shift) {
5469 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
5470 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5471 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5472 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
5473 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5474 emit_int24(0x73, (0xC0 | encode), shift);
5475 }
5476
5477 void Assembler::vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
5478 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
5479 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
5480 vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : 0, "");
5481 InstructionAttr attributes(vector_len, /*vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5482 int encode = vex_prefix_and_encode(xmm7->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5483 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
5484 }
5485
5486 void Assembler::ptest(XMMRegister dst, Address src) {
5487 assert(VM_Version::supports_sse4_1(), "");
5488 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5489 InstructionMark im(this);
5490 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5491 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5492 emit_int8(0x17);
5493 emit_operand(dst, src, 0);
5494 }
5495
5496 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
5497 assert(VM_Version::supports_sse4_1() || VM_Version::supports_avx(), "");
5498 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5499 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5500 emit_int8(0x17);
5501 emit_int8((0xC0 | encode));
5502 }
5503
5504 void Assembler::vptest(XMMRegister dst, Address src) {
5505 assert(VM_Version::supports_avx(), "");
5506 InstructionMark im(this);
5507 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5508 assert(dst != xnoreg, "sanity");
5509 // swap src<->dst for encoding
5510 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5511 emit_int8(0x17);
5512 emit_operand(dst, src, 0);
5513 }
5514
5515 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
5516 assert(VM_Version::supports_avx(), "");
5517 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5518 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5519 emit_int16(0x17, (0xC0 | encode));
5520 }
5521
5522 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
5523 assert(VM_Version::supports_avx(), "");
5524 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5525 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5526 emit_int16(0x17, (0xC0 | encode));
5527 }
5528
5529 void Assembler::vtestps(XMMRegister dst, XMMRegister src, int vector_len) {
5530 assert(VM_Version::supports_avx(), "");
5531 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5532 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5533 emit_int16(0x0E, (0xC0 | encode));
5534 }
5535
5536 void Assembler::evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5537 assert(vector_len == AVX_512bit ? VM_Version::supports_avx512bw() : VM_Version::supports_avx512vlbw(), "");
5538 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5539 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5540 attributes.set_is_evex_instruction();
5541 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5542 emit_int16(0x26, (0xC0 | encode));
5543 }
5544
5545 void Assembler::evptestmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5546 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5547 // Encoding: EVEX.NDS.XXX.66.0F38.W0 DB /r
5548 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5549 attributes.set_is_evex_instruction();
5550 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5551 emit_int16(0x27, (0xC0 | encode));
5552 }
5553
5554 void Assembler::evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5555 assert(vector_len == AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx512vl(), "");
5556 // Encoding: EVEX.NDS.XXX.F3.0F38.W0 DB /r
5557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5558 attributes.set_is_evex_instruction();
5559 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
5560 emit_int16(0x27, (0xC0 | encode));
5561 }
5562
5563 void Assembler::punpcklbw(XMMRegister dst, Address src) {
5564 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5565 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5566 InstructionMark im(this);
5567 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5568 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5569 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5570 emit_int8(0x60);
5571 emit_operand(dst, src, 0);
5572 }
5573
5574 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
5575 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5576 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ true, /* uses_vl */ true);
5577 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5578 emit_int16(0x60, (0xC0 | encode));
5579 }
5580
5581 void Assembler::punpckldq(XMMRegister dst, Address src) {
5582 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5583 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
5584 InstructionMark im(this);
5585 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5586 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5587 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5588 emit_int8(0x62);
5589 emit_operand(dst, src, 0);
5590 }
5591
5592 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
5593 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5594 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5595 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5596 emit_int16(0x62, (0xC0 | encode));
5597 }
5598
5599 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
5600 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5601 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5602 attributes.set_rex_vex_w_reverted();
5603 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5604 emit_int16(0x6C, (0xC0 | encode));
5605 }
5606
5607 void Assembler::evpunpcklqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5608 evpunpcklqdq(dst, k0, src1, src2, false, vector_len);
5609 }
5610
5611 void Assembler::evpunpcklqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5612 assert(VM_Version::supports_evex(), "requires AVX512F");
5613 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5614 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5615 attributes.set_is_evex_instruction();
5616 attributes.set_embedded_opmask_register_specifier(mask);
5617 if (merge) {
5618 attributes.reset_is_clear_context();
5619 }
5620
5621 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5622 emit_int16(0x6C, (0xC0 | encode));
5623 }
5624
5625 void Assembler::evpunpckhqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5626 evpunpckhqdq(dst, k0, src1, src2, false, vector_len);
5627 }
5628
5629 void Assembler::evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len) {
5630 assert(VM_Version::supports_evex(), "requires AVX512F");
5631 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
5632 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5633 attributes.set_is_evex_instruction();
5634 attributes.set_embedded_opmask_register_specifier(mask);
5635 if (merge) {
5636 attributes.reset_is_clear_context();
5637 }
5638
5639 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5640 emit_int16(0x6D, (0xC0 | encode));
5641 }
5642
5643 void Assembler::push(int32_t imm32) {
5644 // in 64bits we push 64bits onto the stack but only
5645 // take a 32bit immediate
5646 emit_int8(0x68);
5647 emit_int32(imm32);
5648 }
5649
5650 void Assembler::push(Register src) {
5651 int encode = prefix_and_encode(src->encoding());
5652 emit_int8(0x50 | encode);
5653 }
5654
5655 void Assembler::pushf() {
5656 emit_int8((unsigned char)0x9C);
5657 }
5658
5659 #ifndef _LP64 // no 32bit push/pop on amd64
5660 void Assembler::pushl(Address src) {
5661 // Note this will push 64bit on 64bit
5662 InstructionMark im(this);
5663 prefix(src);
5664 emit_int8((unsigned char)0xFF);
5665 emit_operand(rsi, src, 0);
5666 }
5667 #endif
5668
5669 void Assembler::rcll(Register dst, int imm8) {
5670 assert(isShiftCount(imm8), "illegal shift count");
5671 int encode = prefix_and_encode(dst->encoding());
5672 if (imm8 == 1) {
5673 emit_int16((unsigned char)0xD1, (0xD0 | encode));
5674 } else {
5675 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
5676 }
5677 }
5678
5679 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
5680 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5681 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5682 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5683 emit_int16(0x53, (0xC0 | encode));
5684 }
5685
5686 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
5687 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5688 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5689 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5690 emit_int16(0x53, (0xC0 | encode));
5691 }
5692
5693 void Assembler::rdtsc() {
5694 emit_int16(0x0F, 0x31);
5695 }
5696
5697 void Assembler::rdtscp() {
5698 emit_int24(0x0F, 0x01, (unsigned char)0xF9);
5699 }
5700
5701 // copies data from [esi] to [edi] using rcx pointer sized words
5702 // generic
5703 void Assembler::rep_mov() {
5704 // REP
5705 // MOVSQ
5706 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xA5);)
5707 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xA5);)
5708 }
5709
5710 // sets rcx bytes with rax, value at [edi]
5711 void Assembler::rep_stosb() {
5712 // REP
5713 // STOSB
5714 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAA);)
5715 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAA);)
5716 }
5717
5718 // sets rcx pointer sized words with rax, value at [edi]
5719 // generic
5720 void Assembler::rep_stos() {
5721 // REP
5722 // LP64:STOSQ, LP32:STOSD
5723 LP64_ONLY(emit_int24((unsigned char)0xF3, REX_W, (unsigned char)0xAB);)
5724 NOT_LP64( emit_int16((unsigned char)0xF3, (unsigned char)0xAB);)
5725 }
5726
5727 // scans rcx pointer sized words at [edi] for occurrence of rax,
5728 // generic
5729 void Assembler::repne_scan() { // repne_scan
5730 // SCASQ
5731 LP64_ONLY(emit_int24((unsigned char)0xF2, REX_W, (unsigned char)0xAF);)
5732 NOT_LP64( emit_int16((unsigned char)0xF2, (unsigned char)0xAF);)
5733 }
5734
5735 #ifdef _LP64
5736 // scans rcx 4 byte words at [edi] for occurrence of rax,
5737 // generic
5738 void Assembler::repne_scanl() { // repne_scan
5739 // SCASL
5740 emit_int16((unsigned char)0xF2, (unsigned char)0xAF);
5741 }
5742 #endif
5743
5744 void Assembler::ret(int imm16) {
5745 if (imm16 == 0) {
5746 emit_int8((unsigned char)0xC3);
5747 } else {
5748 emit_int8((unsigned char)0xC2);
5749 emit_int16(imm16);
5750 }
5751 }
5752
5753 void Assembler::roll(Register dst, int imm8) {
5754 assert(isShiftCount(imm8), "illegal shift count");
5755 int encode = prefix_and_encode(dst->encoding());
5756 if (imm8 == 1) {
5757 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5758 } else {
5759 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5760 }
5761 }
5762
5763 void Assembler::roll(Register dst) {
5764 int encode = prefix_and_encode(dst->encoding());
5765 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5766 }
5767
5768 void Assembler::rorl(Register dst, int imm8) {
5769 assert(isShiftCount(imm8), "illegal shift count");
5770 int encode = prefix_and_encode(dst->encoding());
5771 if (imm8 == 1) {
5772 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5773 } else {
5774 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5775 }
5776 }
5777
5778 void Assembler::rorl(Register dst) {
5779 int encode = prefix_and_encode(dst->encoding());
5780 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5781 }
5782
5783 #ifdef _LP64
5784 void Assembler::rorq(Register dst) {
5785 int encode = prefixq_and_encode(dst->encoding());
5786 emit_int16((unsigned char)0xD3, (0xC8 | encode));
5787 }
5788
5789 void Assembler::rorq(Register dst, int imm8) {
5790 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5791 int encode = prefixq_and_encode(dst->encoding());
5792 if (imm8 == 1) {
5793 emit_int16((unsigned char)0xD1, (0xC8 | encode));
5794 } else {
5795 emit_int24((unsigned char)0xC1, (0xc8 | encode), imm8);
5796 }
5797 }
5798
5799 void Assembler::rolq(Register dst) {
5800 int encode = prefixq_and_encode(dst->encoding());
5801 emit_int16((unsigned char)0xD3, (0xC0 | encode));
5802 }
5803
5804 void Assembler::rolq(Register dst, int imm8) {
5805 assert(isShiftCount(imm8 >> 1), "illegal shift count");
5806 int encode = prefixq_and_encode(dst->encoding());
5807 if (imm8 == 1) {
5808 emit_int16((unsigned char)0xD1, (0xC0 | encode));
5809 } else {
5810 emit_int24((unsigned char)0xC1, (0xc0 | encode), imm8);
5811 }
5812 }
5813 #endif
5814
5815 void Assembler::sahf() {
5816 #ifdef _LP64
5817 // Not supported in 64bit mode
5818 ShouldNotReachHere();
5819 #endif
5820 emit_int8((unsigned char)0x9E);
5821 }
5822
5823 void Assembler::sall(Address dst, int imm8) {
5824 InstructionMark im(this);
5825 assert(isShiftCount(imm8), "illegal shift count");
5826 prefix(dst);
5827 if (imm8 == 1) {
5828 emit_int8((unsigned char)0xD1);
5829 emit_operand(as_Register(4), dst, 0);
5830 }
5831 else {
5832 emit_int8((unsigned char)0xC1);
5833 emit_operand(as_Register(4), dst, 1);
5834 emit_int8(imm8);
5835 }
5836 }
5837
5838 void Assembler::sall(Address dst) {
5839 InstructionMark im(this);
5840 prefix(dst);
5841 emit_int8((unsigned char)0xD3);
5842 emit_operand(as_Register(4), dst, 0);
5843 }
5844
5845 void Assembler::sall(Register dst, int imm8) {
5846 assert(isShiftCount(imm8), "illegal shift count");
5847 int encode = prefix_and_encode(dst->encoding());
5848 if (imm8 == 1) {
5849 emit_int16((unsigned char)0xD1, (0xE0 | encode));
5850 } else {
5851 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
5852 }
5853 }
5854
5855 void Assembler::sall(Register dst) {
5856 int encode = prefix_and_encode(dst->encoding());
5857 emit_int16((unsigned char)0xD3, (0xE0 | encode));
5858 }
5859
5860 void Assembler::sarl(Address dst, int imm8) {
5861 assert(isShiftCount(imm8), "illegal shift count");
5862 InstructionMark im(this);
5863 prefix(dst);
5864 if (imm8 == 1) {
5865 emit_int8((unsigned char)0xD1);
5866 emit_operand(as_Register(7), dst, 0);
5867 }
5868 else {
5869 emit_int8((unsigned char)0xC1);
5870 emit_operand(as_Register(7), dst, 1);
5871 emit_int8(imm8);
5872 }
5873 }
5874
5875 void Assembler::sarl(Address dst) {
5876 InstructionMark im(this);
5877 prefix(dst);
5878 emit_int8((unsigned char)0xD3);
5879 emit_operand(as_Register(7), dst, 0);
5880 }
5881
5882 void Assembler::sarl(Register dst, int imm8) {
5883 int encode = prefix_and_encode(dst->encoding());
5884 assert(isShiftCount(imm8), "illegal shift count");
5885 if (imm8 == 1) {
5886 emit_int16((unsigned char)0xD1, (0xF8 | encode));
5887 } else {
5888 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
5889 }
5890 }
5891
5892 void Assembler::sarl(Register dst) {
5893 int encode = prefix_and_encode(dst->encoding());
5894 emit_int16((unsigned char)0xD3, (0xF8 | encode));
5895 }
5896
5897 void Assembler::sbbl(Address dst, int32_t imm32) {
5898 InstructionMark im(this);
5899 prefix(dst);
5900 emit_arith_operand(0x81, rbx, dst, imm32);
5901 }
5902
5903 void Assembler::sbbl(Register dst, int32_t imm32) {
5904 prefix(dst);
5905 emit_arith(0x81, 0xD8, dst, imm32);
5906 }
5907
5908
5909 void Assembler::sbbl(Register dst, Address src) {
5910 InstructionMark im(this);
5911 prefix(src, dst);
5912 emit_int8(0x1B);
5913 emit_operand(dst, src, 0);
5914 }
5915
5916 void Assembler::sbbl(Register dst, Register src) {
5917 (void) prefix_and_encode(dst->encoding(), src->encoding());
5918 emit_arith(0x1B, 0xC0, dst, src);
5919 }
5920
5921 void Assembler::setb(Condition cc, Register dst) {
5922 assert(0 <= cc && cc < 16, "illegal cc");
5923 int encode = prefix_and_encode(dst->encoding(), true);
5924 emit_int24(0x0F, (unsigned char)0x90 | cc, (0xC0 | encode));
5925 }
5926
5927 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
5928 assert(VM_Version::supports_ssse3(), "");
5929 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5930 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5931 emit_int24(0x0F, (0xC0 | encode), imm8);
5932 }
5933
5934 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
5935 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
5936 vector_len == AVX_256bit? VM_Version::supports_avx2() :
5937 0, "");
5938 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5939 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5940 emit_int24(0x0F, (0xC0 | encode), imm8);
5941 }
5942
5943 void Assembler::evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
5944 assert(VM_Version::supports_evex(), "");
5945 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
5946 attributes.set_is_evex_instruction();
5947 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5948 emit_int24(0x3, (0xC0 | encode), imm8);
5949 }
5950
5951 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
5952 assert(VM_Version::supports_sse4_1(), "");
5953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5954 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
5955 emit_int24(0x0E, (0xC0 | encode), imm8);
5956 }
5957
5958 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
5959 assert(VM_Version::supports_sha(), "");
5960 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
5961 emit_int24((unsigned char)0xCC, (0xC0 | encode), (unsigned char)imm8);
5962 }
5963
5964 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
5965 assert(VM_Version::supports_sha(), "");
5966 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5967 emit_int16((unsigned char)0xC8, (0xC0 | encode));
5968 }
5969
5970 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
5971 assert(VM_Version::supports_sha(), "");
5972 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5973 emit_int16((unsigned char)0xC9, (0xC0 | encode));
5974 }
5975
5976 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
5977 assert(VM_Version::supports_sha(), "");
5978 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5979 emit_int16((unsigned char)0xCA, (0xC0 | encode));
5980 }
5981
5982 // xmm0 is implicit additional source to this instruction.
5983 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
5984 assert(VM_Version::supports_sha(), "");
5985 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5986 emit_int16((unsigned char)0xCB, (0xC0 | encode));
5987 }
5988
5989 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
5990 assert(VM_Version::supports_sha(), "");
5991 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5992 emit_int16((unsigned char)0xCC, (0xC0 | encode));
5993 }
5994
5995 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
5996 assert(VM_Version::supports_sha(), "");
5997 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
5998 emit_int16((unsigned char)0xCD, (0xC0 | encode));
5999 }
6000
6001
6002 void Assembler::shll(Register dst, int imm8) {
6003 assert(isShiftCount(imm8), "illegal shift count");
6004 int encode = prefix_and_encode(dst->encoding());
6005 if (imm8 == 1 ) {
6006 emit_int16((unsigned char)0xD1, (0xE0 | encode));
6007 } else {
6008 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
6009 }
6010 }
6011
6012 void Assembler::shll(Register dst) {
6013 int encode = prefix_and_encode(dst->encoding());
6014 emit_int16((unsigned char)0xD3, (0xE0 | encode));
6015 }
6016
6017 void Assembler::shrl(Register dst, int imm8) {
6018 assert(isShiftCount(imm8), "illegal shift count");
6019 int encode = prefix_and_encode(dst->encoding());
6020 if (imm8 == 1) {
6021 emit_int16((unsigned char)0xD1, (0xE8 | encode));
6022 }
6023 else {
6024 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
6025 }
6026 }
6027
6028 void Assembler::shrl(Register dst) {
6029 int encode = prefix_and_encode(dst->encoding());
6030 emit_int16((unsigned char)0xD3, (0xE8 | encode));
6031 }
6032
6033 void Assembler::shrl(Address dst) {
6034 InstructionMark im(this);
6035 prefix(dst);
6036 emit_int8((unsigned char)0xD3);
6037 emit_operand(as_Register(5), dst, 0);
6038 }
6039
6040 void Assembler::shrl(Address dst, int imm8) {
6041 InstructionMark im(this);
6042 assert(isShiftCount(imm8), "illegal shift count");
6043 prefix(dst);
6044 if (imm8 == 1) {
6045 emit_int8((unsigned char)0xD1);
6046 emit_operand(as_Register(5), dst, 0);
6047 }
6048 else {
6049 emit_int8((unsigned char)0xC1);
6050 emit_operand(as_Register(5), dst, 1);
6051 emit_int8(imm8);
6052 }
6053 }
6054
6055
6056 void Assembler::shldl(Register dst, Register src) {
6057 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6058 emit_int24(0x0F, (unsigned char)0xA5, (0xC0 | encode));
6059 }
6060
6061 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
6062 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6063 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6064 }
6065
6066 void Assembler::shrdl(Register dst, Register src) {
6067 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6068 emit_int24(0x0F, (unsigned char)0xAD, (0xC0 | encode));
6069 }
6070
6071 void Assembler::shrdl(Register dst, Register src, int8_t imm8) {
6072 int encode = prefix_and_encode(src->encoding(), dst->encoding());
6073 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6074 }
6075
6076 #ifdef _LP64
6077 void Assembler::shldq(Register dst, Register src, int8_t imm8) {
6078 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6079 emit_int32(0x0F, (unsigned char)0xA4, (0xC0 | encode), imm8);
6080 }
6081
6082 void Assembler::shrdq(Register dst, Register src, int8_t imm8) {
6083 int encode = prefixq_and_encode(src->encoding(), dst->encoding());
6084 emit_int32(0x0F, (unsigned char)0xAC, (0xC0 | encode), imm8);
6085 }
6086 #endif
6087
6088 // copies a single word from [esi] to [edi]
6089 void Assembler::smovl() {
6090 emit_int8((unsigned char)0xA5);
6091 }
6092
6093 void Assembler::roundsd(XMMRegister dst, XMMRegister src, int32_t rmode) {
6094 assert(VM_Version::supports_sse4_1(), "");
6095 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6096 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6097 emit_int24(0x0B, (0xC0 | encode), (unsigned char)rmode);
6098 }
6099
6100 void Assembler::roundsd(XMMRegister dst, Address src, int32_t rmode) {
6101 assert(VM_Version::supports_sse4_1(), "");
6102 InstructionMark im(this);
6103 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6104 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6105 emit_int8(0x0B);
6106 emit_operand(dst, src, 1);
6107 emit_int8((unsigned char)rmode);
6108 }
6109
6110 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
6111 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6112 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6113 attributes.set_rex_vex_w_reverted();
6114 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6115 emit_int16(0x51, (0xC0 | encode));
6116 }
6117
6118 void Assembler::sqrtsd(XMMRegister dst, Address src) {
6119 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6120 InstructionMark im(this);
6121 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6122 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6123 attributes.set_rex_vex_w_reverted();
6124 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6125 emit_int8(0x51);
6126 emit_operand(dst, src, 0);
6127 }
6128
6129 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
6130 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6131 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6132 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6133 emit_int16(0x51, (0xC0 | encode));
6134 }
6135
6136 void Assembler::std() {
6137 emit_int8((unsigned char)0xFD);
6138 }
6139
6140 void Assembler::sqrtss(XMMRegister dst, Address src) {
6141 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6142 InstructionMark im(this);
6143 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6144 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6145 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6146 emit_int8(0x51);
6147 emit_operand(dst, src, 0);
6148 }
6149
6150 void Assembler::stmxcsr( Address dst) {
6151 if (UseAVX > 0 ) {
6152 assert(VM_Version::supports_avx(), "");
6153 InstructionMark im(this);
6154 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6155 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6156 emit_int8((unsigned char)0xAE);
6157 emit_operand(as_Register(3), dst, 0);
6158 } else {
6159 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6160 InstructionMark im(this);
6161 prefix(dst);
6162 emit_int16(0x0F, (unsigned char)0xAE);
6163 emit_operand(as_Register(3), dst, 0);
6164 }
6165 }
6166
6167 void Assembler::subl(Address dst, int32_t imm32) {
6168 InstructionMark im(this);
6169 prefix(dst);
6170 emit_arith_operand(0x81, rbp, dst, imm32);
6171 }
6172
6173 void Assembler::subl(Address dst, Register src) {
6174 InstructionMark im(this);
6175 prefix(dst, src);
6176 emit_int8(0x29);
6177 emit_operand(src, dst, 0);
6178 }
6179
6180 void Assembler::subl(Register dst, int32_t imm32) {
6181 prefix(dst);
6182 emit_arith(0x81, 0xE8, dst, imm32);
6183 }
6184
6185 // Force generation of a 4 byte immediate value even if it fits into 8bit
6186 void Assembler::subl_imm32(Register dst, int32_t imm32) {
6187 prefix(dst);
6188 emit_arith_imm32(0x81, 0xE8, dst, imm32);
6189 }
6190
6191 void Assembler::subl(Register dst, Address src) {
6192 InstructionMark im(this);
6193 prefix(src, dst);
6194 emit_int8(0x2B);
6195 emit_operand(dst, src, 0);
6196 }
6197
6198 void Assembler::subl(Register dst, Register src) {
6199 (void) prefix_and_encode(dst->encoding(), src->encoding());
6200 emit_arith(0x2B, 0xC0, dst, src);
6201 }
6202
6203 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
6204 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6205 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6206 attributes.set_rex_vex_w_reverted();
6207 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6208 emit_int16(0x5C, (0xC0 | encode));
6209 }
6210
6211 void Assembler::subsd(XMMRegister dst, Address src) {
6212 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6213 InstructionMark im(this);
6214 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6215 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6216 attributes.set_rex_vex_w_reverted();
6217 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6218 emit_int8(0x5C);
6219 emit_operand(dst, src, 0);
6220 }
6221
6222 void Assembler::subss(XMMRegister dst, XMMRegister src) {
6223 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6224 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
6225 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6226 emit_int16(0x5C, (0xC0 | encode));
6227 }
6228
6229 void Assembler::subss(XMMRegister dst, Address src) {
6230 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6231 InstructionMark im(this);
6232 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6233 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6234 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6235 emit_int8(0x5C);
6236 emit_operand(dst, src, 0);
6237 }
6238
6239 void Assembler::testb(Register dst, int imm8, bool use_ral) {
6240 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
6241 if (dst == rax) {
6242 if (use_ral) {
6243 emit_int8((unsigned char)0xA8);
6244 emit_int8(imm8);
6245 } else {
6246 emit_int8((unsigned char)0xF6);
6247 emit_int8((unsigned char)0xC4);
6248 emit_int8(imm8);
6249 }
6250 } else {
6251 (void) prefix_and_encode(dst->encoding(), true);
6252 emit_arith_b(0xF6, 0xC0, dst, imm8);
6253 }
6254 }
6255
6256 void Assembler::testb(Address dst, int imm8) {
6257 InstructionMark im(this);
6258 prefix(dst);
6259 emit_int8((unsigned char)0xF6);
6260 emit_operand(rax, dst, 1);
6261 emit_int8(imm8);
6262 }
6263
6264 void Assembler::testl(Address dst, int32_t imm32) {
6265 InstructionMark im(this);
6266 prefix(dst);
6267 emit_int8((unsigned char)0xF7);
6268 emit_operand(as_Register(0), dst, 4);
6269 emit_int32(imm32);
6270 }
6271
6272 void Assembler::testl(Register dst, int32_t imm32) {
6273 // not using emit_arith because test
6274 // doesn't support sign-extension of
6275 // 8bit operands
6276 if (dst == rax) {
6277 emit_int8((unsigned char)0xA9);
6278 emit_int32(imm32);
6279 } else {
6280 int encode = dst->encoding();
6281 encode = prefix_and_encode(encode);
6282 emit_int16((unsigned char)0xF7, (0xC0 | encode));
6283 emit_int32(imm32);
6284 }
6285 }
6286
6287 void Assembler::testl(Register dst, Register src) {
6288 (void) prefix_and_encode(dst->encoding(), src->encoding());
6289 emit_arith(0x85, 0xC0, dst, src);
6290 }
6291
6292 void Assembler::testl(Register dst, Address src) {
6293 InstructionMark im(this);
6294 prefix(src, dst);
6295 emit_int8((unsigned char)0x85);
6296 emit_operand(dst, src, 0);
6297 }
6298
6299 void Assembler::tzcntl(Register dst, Register src) {
6300 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6301 emit_int8((unsigned char)0xF3);
6302 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6303 emit_int24(0x0F,
6304 (unsigned char)0xBC,
6305 0xC0 | encode);
6306 }
6307
6308 void Assembler::tzcntl(Register dst, Address src) {
6309 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6310 InstructionMark im(this);
6311 emit_int8((unsigned char)0xF3);
6312 prefix(src, dst);
6313 emit_int16(0x0F, (unsigned char)0xBC);
6314 emit_operand(dst, src, 0);
6315 }
6316
6317 void Assembler::tzcntq(Register dst, Register src) {
6318 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6319 emit_int8((unsigned char)0xF3);
6320 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
6321 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
6322 }
6323
6324 void Assembler::tzcntq(Register dst, Address src) {
6325 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
6326 InstructionMark im(this);
6327 emit_int8((unsigned char)0xF3);
6328 prefixq(src, dst);
6329 emit_int16(0x0F, (unsigned char)0xBC);
6330 emit_operand(dst, src, 0);
6331 }
6332
6333 void Assembler::ucomisd(XMMRegister dst, Address src) {
6334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6335 InstructionMark im(this);
6336 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6337 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6338 attributes.set_rex_vex_w_reverted();
6339 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6340 emit_int8(0x2E);
6341 emit_operand(dst, src, 0);
6342 }
6343
6344 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
6345 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6346 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6347 attributes.set_rex_vex_w_reverted();
6348 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6349 emit_int16(0x2E, (0xC0 | encode));
6350 }
6351
6352 void Assembler::ucomiss(XMMRegister dst, Address src) {
6353 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6354 InstructionMark im(this);
6355 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6356 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6357 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6358 emit_int8(0x2E);
6359 emit_operand(dst, src, 0);
6360 }
6361
6362 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
6363 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6364 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6365 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6366 emit_int16(0x2E, (0xC0 | encode));
6367 }
6368
6369 void Assembler::xabort(int8_t imm8) {
6370 emit_int24((unsigned char)0xC6, (unsigned char)0xF8, (imm8 & 0xFF));
6371 }
6372
6373 void Assembler::xaddb(Address dst, Register src) {
6374 InstructionMark im(this);
6375 prefix(dst, src, true);
6376 emit_int16(0x0F, (unsigned char)0xC0);
6377 emit_operand(src, dst, 0);
6378 }
6379
6380 void Assembler::xaddw(Address dst, Register src) {
6381 InstructionMark im(this);
6382 emit_int8(0x66);
6383 prefix(dst, src);
6384 emit_int16(0x0F, (unsigned char)0xC1);
6385 emit_operand(src, dst, 0);
6386 }
6387
6388 void Assembler::xaddl(Address dst, Register src) {
6389 InstructionMark im(this);
6390 prefix(dst, src);
6391 emit_int16(0x0F, (unsigned char)0xC1);
6392 emit_operand(src, dst, 0);
6393 }
6394
6395 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
6396 InstructionMark im(this);
6397 relocate(rtype);
6398 if (abort.is_bound()) {
6399 address entry = target(abort);
6400 assert(entry != nullptr, "abort entry null");
6401 int offset = checked_cast<int>(entry - pc());
6402 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6403 emit_int32(offset - 6); // 2 opcode + 4 address
6404 } else {
6405 abort.add_patch_at(code(), locator());
6406 emit_int16((unsigned char)0xC7, (unsigned char)0xF8);
6407 emit_int32(0);
6408 }
6409 }
6410
6411 void Assembler::xchgb(Register dst, Address src) { // xchg
6412 InstructionMark im(this);
6413 prefix(src, dst, true);
6414 emit_int8((unsigned char)0x86);
6415 emit_operand(dst, src, 0);
6416 }
6417
6418 void Assembler::xchgw(Register dst, Address src) { // xchg
6419 InstructionMark im(this);
6420 emit_int8(0x66);
6421 prefix(src, dst);
6422 emit_int8((unsigned char)0x87);
6423 emit_operand(dst, src, 0);
6424 }
6425
6426 void Assembler::xchgl(Register dst, Address src) { // xchg
6427 InstructionMark im(this);
6428 prefix(src, dst);
6429 emit_int8((unsigned char)0x87);
6430 emit_operand(dst, src, 0);
6431 }
6432
6433 void Assembler::xchgl(Register dst, Register src) {
6434 int encode = prefix_and_encode(dst->encoding(), src->encoding());
6435 emit_int16((unsigned char)0x87, (0xC0 | encode));
6436 }
6437
6438 void Assembler::xend() {
6439 emit_int24(0x0F, 0x01, (unsigned char)0xD5);
6440 }
6441
6442 void Assembler::xgetbv() {
6443 emit_int24(0x0F, 0x01, (unsigned char)0xD0);
6444 }
6445
6446 void Assembler::xorl(Address dst, int32_t imm32) {
6447 InstructionMark im(this);
6448 prefix(dst);
6449 emit_arith_operand(0x81, as_Register(6), dst, imm32);
6450 }
6451
6452 void Assembler::xorl(Register dst, int32_t imm32) {
6453 prefix(dst);
6454 emit_arith(0x81, 0xF0, dst, imm32);
6455 }
6456
6457 void Assembler::xorl(Register dst, Address src) {
6458 InstructionMark im(this);
6459 prefix(src, dst);
6460 emit_int8(0x33);
6461 emit_operand(dst, src, 0);
6462 }
6463
6464 void Assembler::xorl(Register dst, Register src) {
6465 (void) prefix_and_encode(dst->encoding(), src->encoding());
6466 emit_arith(0x33, 0xC0, dst, src);
6467 }
6468
6469 void Assembler::xorl(Address dst, Register src) {
6470 InstructionMark im(this);
6471 prefix(dst, src);
6472 emit_int8(0x31);
6473 emit_operand(src, dst, 0);
6474 }
6475
6476 void Assembler::xorb(Register dst, Address src) {
6477 InstructionMark im(this);
6478 prefix(src, dst);
6479 emit_int8(0x32);
6480 emit_operand(dst, src, 0);
6481 }
6482
6483 void Assembler::xorb(Address dst, Register src) {
6484 InstructionMark im(this);
6485 prefix(dst, src, true);
6486 emit_int8(0x30);
6487 emit_operand(src, dst, 0);
6488 }
6489
6490 void Assembler::xorw(Register dst, Register src) {
6491 (void)prefix_and_encode(dst->encoding(), src->encoding());
6492 emit_arith(0x33, 0xC0, dst, src);
6493 }
6494
6495 // AVX 3-operands scalar float-point arithmetic instructions
6496
6497 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
6498 assert(VM_Version::supports_avx(), "");
6499 InstructionMark im(this);
6500 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6501 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6502 attributes.set_rex_vex_w_reverted();
6503 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6504 emit_int8(0x58);
6505 emit_operand(dst, src, 0);
6506 }
6507
6508 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6509 assert(VM_Version::supports_avx(), "");
6510 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6511 attributes.set_rex_vex_w_reverted();
6512 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6513 emit_int16(0x58, (0xC0 | encode));
6514 }
6515
6516 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
6517 assert(VM_Version::supports_avx(), "");
6518 InstructionMark im(this);
6519 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6520 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6521 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6522 emit_int8(0x58);
6523 emit_operand(dst, src, 0);
6524 }
6525
6526 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6527 assert(VM_Version::supports_avx(), "");
6528 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6529 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6530 emit_int16(0x58, (0xC0 | encode));
6531 }
6532
6533 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
6534 assert(VM_Version::supports_avx(), "");
6535 InstructionMark im(this);
6536 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6537 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6538 attributes.set_rex_vex_w_reverted();
6539 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6540 emit_int8(0x5E);
6541 emit_operand(dst, src, 0);
6542 }
6543
6544 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6545 assert(VM_Version::supports_avx(), "");
6546 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6547 attributes.set_rex_vex_w_reverted();
6548 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6549 emit_int16(0x5E, (0xC0 | encode));
6550 }
6551
6552 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
6553 assert(VM_Version::supports_avx(), "");
6554 InstructionMark im(this);
6555 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6556 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6557 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6558 emit_int8(0x5E);
6559 emit_operand(dst, src, 0);
6560 }
6561
6562 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6563 assert(VM_Version::supports_avx(), "");
6564 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6565 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6566 emit_int16(0x5E, (0xC0 | encode));
6567 }
6568
6569 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6570 assert(VM_Version::supports_fma(), "");
6571 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6572 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6573 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6574 }
6575
6576 void Assembler::evfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2, EvexRoundPrefix rmode) { // Need to add rmode for rounding mode support
6577 assert(VM_Version::supports_evex(), "");
6578 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6579 attributes.set_extended_context();
6580 attributes.set_is_evex_instruction();
6581 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6582 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6583 }
6584
6585 void Assembler::vfnmadd213sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6586 assert(VM_Version::supports_fma(), "");
6587 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6588 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6589 emit_int16((unsigned char)0xAD, (0xC0 | encode));
6590 }
6591
6592 void Assembler::vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6593 assert(VM_Version::supports_fma(), "");
6594 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6595 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6596 emit_int16((unsigned char)0xBD, (0xC0 | encode));
6597 }
6598
6599 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
6600 assert(VM_Version::supports_fma(), "");
6601 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6602 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6603 emit_int16((unsigned char)0xB9, (0xC0 | encode));
6604 }
6605
6606 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
6607 assert(VM_Version::supports_avx(), "");
6608 InstructionMark im(this);
6609 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6610 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6611 attributes.set_rex_vex_w_reverted();
6612 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6613 emit_int8(0x59);
6614 emit_operand(dst, src, 0);
6615 }
6616
6617 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6618 assert(VM_Version::supports_avx(), "");
6619 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6620 attributes.set_rex_vex_w_reverted();
6621 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6622 emit_int16(0x59, (0xC0 | encode));
6623 }
6624
6625 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
6626 assert(VM_Version::supports_avx(), "");
6627 InstructionMark im(this);
6628 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6629 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6630 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6631 emit_int8(0x59);
6632 emit_operand(dst, src, 0);
6633 }
6634
6635 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6636 assert(VM_Version::supports_avx(), "");
6637 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6638 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6639 emit_int16(0x59, (0xC0 | encode));
6640 }
6641
6642 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
6643 assert(VM_Version::supports_avx(), "");
6644 InstructionMark im(this);
6645 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6646 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
6647 attributes.set_rex_vex_w_reverted();
6648 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6649 emit_int8(0x5C);
6650 emit_operand(dst, src, 0);
6651 }
6652
6653 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6654 assert(VM_Version::supports_avx(), "");
6655 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6656 attributes.set_rex_vex_w_reverted();
6657 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
6658 emit_int16(0x5C, (0xC0 | encode));
6659 }
6660
6661 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
6662 assert(VM_Version::supports_avx(), "");
6663 InstructionMark im(this);
6664 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6665 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
6666 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6667 emit_int8(0x5C);
6668 emit_operand(dst, src, 0);
6669 }
6670
6671 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
6672 assert(VM_Version::supports_avx(), "");
6673 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6674 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
6675 emit_int16(0x5C, (0xC0 | encode));
6676 }
6677
6678 //====================VECTOR ARITHMETIC=====================================
6679
6680 // Float-point vector arithmetic
6681
6682 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
6683 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6684 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6685 attributes.set_rex_vex_w_reverted();
6686 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6687 emit_int16(0x58, (0xC0 | encode));
6688 }
6689
6690 void Assembler::addpd(XMMRegister dst, Address src) {
6691 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6692 InstructionMark im(this);
6693 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6694 attributes.set_rex_vex_w_reverted();
6695 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6696 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6697 emit_int8(0x58);
6698 emit_operand(dst, src, 0);
6699 }
6700
6701
6702 void Assembler::addps(XMMRegister dst, XMMRegister src) {
6703 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6704 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6705 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6706 emit_int16(0x58, (0xC0 | encode));
6707 }
6708
6709 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6710 assert(VM_Version::supports_avx(), "");
6711 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6712 attributes.set_rex_vex_w_reverted();
6713 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6714 emit_int16(0x58, (0xC0 | encode));
6715 }
6716
6717 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6718 assert(VM_Version::supports_avx(), "");
6719 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6720 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6721 emit_int16(0x58, (0xC0 | encode));
6722 }
6723
6724 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6725 assert(VM_Version::supports_avx(), "");
6726 InstructionMark im(this);
6727 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6728 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6729 attributes.set_rex_vex_w_reverted();
6730 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6731 emit_int8(0x58);
6732 emit_operand(dst, src, 0);
6733 }
6734
6735 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6736 assert(VM_Version::supports_avx(), "");
6737 InstructionMark im(this);
6738 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6739 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6740 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6741 emit_int8(0x58);
6742 emit_operand(dst, src, 0);
6743 }
6744
6745 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
6746 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6747 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6748 attributes.set_rex_vex_w_reverted();
6749 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6750 emit_int16(0x5C, (0xC0 | encode));
6751 }
6752
6753 void Assembler::subps(XMMRegister dst, XMMRegister src) {
6754 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6755 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6756 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6757 emit_int16(0x5C, (0xC0 | encode));
6758 }
6759
6760 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6761 assert(VM_Version::supports_avx(), "");
6762 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6763 attributes.set_rex_vex_w_reverted();
6764 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6765 emit_int16(0x5C, (0xC0 | encode));
6766 }
6767
6768 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6769 assert(VM_Version::supports_avx(), "");
6770 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6771 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6772 emit_int16(0x5C, (0xC0 | encode));
6773 }
6774
6775 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6776 assert(VM_Version::supports_avx(), "");
6777 InstructionMark im(this);
6778 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6779 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6780 attributes.set_rex_vex_w_reverted();
6781 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6782 emit_int8(0x5C);
6783 emit_operand(dst, src, 0);
6784 }
6785
6786 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6787 assert(VM_Version::supports_avx(), "");
6788 InstructionMark im(this);
6789 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6790 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6791 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6792 emit_int8(0x5C);
6793 emit_operand(dst, src, 0);
6794 }
6795
6796 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
6797 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6798 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6799 attributes.set_rex_vex_w_reverted();
6800 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6801 emit_int16(0x59, (0xC0 | encode));
6802 }
6803
6804 void Assembler::mulpd(XMMRegister dst, Address src) {
6805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6806 InstructionMark im(this);
6807 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6808 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6809 attributes.set_rex_vex_w_reverted();
6810 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6811 emit_int8(0x59);
6812 emit_operand(dst, src, 0);
6813 }
6814
6815 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
6816 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6817 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6818 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6819 emit_int16(0x59, (0xC0 | encode));
6820 }
6821
6822 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6823 assert(VM_Version::supports_avx(), "");
6824 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6825 attributes.set_rex_vex_w_reverted();
6826 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6827 emit_int16(0x59, (0xC0 | encode));
6828 }
6829
6830 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6831 assert(VM_Version::supports_avx(), "");
6832 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6833 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6834 emit_int16(0x59, (0xC0 | encode));
6835 }
6836
6837 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6838 assert(VM_Version::supports_avx(), "");
6839 InstructionMark im(this);
6840 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6841 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6842 attributes.set_rex_vex_w_reverted();
6843 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6844 emit_int8(0x59);
6845 emit_operand(dst, src, 0);
6846 }
6847
6848 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6849 assert(VM_Version::supports_avx(), "");
6850 InstructionMark im(this);
6851 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6852 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6853 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6854 emit_int8(0x59);
6855 emit_operand(dst, src, 0);
6856 }
6857
6858 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6859 assert(VM_Version::supports_fma(), "");
6860 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6861 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6862 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6863 }
6864
6865 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
6866 assert(VM_Version::supports_fma(), "");
6867 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6868 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6869 emit_int16((unsigned char)0xB8, (0xC0 | encode));
6870 }
6871
6872 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6873 assert(VM_Version::supports_fma(), "");
6874 InstructionMark im(this);
6875 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6876 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6877 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6878 emit_int8((unsigned char)0xB8);
6879 emit_operand(dst, src2, 0);
6880 }
6881
6882 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
6883 assert(VM_Version::supports_fma(), "");
6884 InstructionMark im(this);
6885 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6886 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6887 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6888 emit_int8((unsigned char)0xB8);
6889 emit_operand(dst, src2, 0);
6890 }
6891
6892 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
6893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6894 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6895 attributes.set_rex_vex_w_reverted();
6896 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6897 emit_int16(0x5E, (0xC0 | encode));
6898 }
6899
6900 void Assembler::divps(XMMRegister dst, XMMRegister src) {
6901 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6902 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6903 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6904 emit_int16(0x5E, (0xC0 | encode));
6905 }
6906
6907 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6908 assert(VM_Version::supports_avx(), "");
6909 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6910 attributes.set_rex_vex_w_reverted();
6911 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6912 emit_int16(0x5E, (0xC0 | encode));
6913 }
6914
6915 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6916 assert(VM_Version::supports_avx(), "");
6917 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6918 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6919 emit_int16(0x5E, (0xC0 | encode));
6920 }
6921
6922 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6923 assert(VM_Version::supports_avx(), "");
6924 InstructionMark im(this);
6925 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6926 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6927 attributes.set_rex_vex_w_reverted();
6928 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6929 emit_int8(0x5E);
6930 emit_operand(dst, src, 0);
6931 }
6932
6933 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6934 assert(VM_Version::supports_avx(), "");
6935 InstructionMark im(this);
6936 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6937 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6938 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6939 emit_int8(0x5E);
6940 emit_operand(dst, src, 0);
6941 }
6942
6943 void Assembler::vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
6944 assert(VM_Version::supports_avx(), "");
6945 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6946 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6947 emit_int24(0x09, (0xC0 | encode), (rmode));
6948 }
6949
6950 void Assembler::vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
6951 assert(VM_Version::supports_avx(), "");
6952 InstructionMark im(this);
6953 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
6954 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6955 emit_int8(0x09);
6956 emit_operand(dst, src, 1);
6957 emit_int8((rmode));
6958 }
6959
6960 void Assembler::vroundsd(XMMRegister dst, XMMRegister src, XMMRegister src2, int32_t rmode) {
6961 assert(VM_Version::supports_avx(), "");
6962 assert(rmode <= 0x0f, "rmode 0x%x", rmode);
6963 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6964 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6965 emit_int24(0x0B, (0xC0 | encode), (rmode));
6966 }
6967
6968 void Assembler::vrndscalesd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int32_t rmode) {
6969 assert(VM_Version::supports_evex(), "requires EVEX support");
6970 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6971 attributes.set_is_evex_instruction();
6972 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6973 emit_int24(0x0B, (0xC0 | encode), (rmode));
6974 }
6975
6976 void Assembler::vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len) {
6977 assert(VM_Version::supports_evex(), "requires EVEX support");
6978 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6979 attributes.set_is_evex_instruction();
6980 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6981 emit_int24(0x09, (0xC0 | encode), (rmode));
6982 }
6983
6984 void Assembler::vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len) {
6985 assert(VM_Version::supports_evex(), "requires EVEX support");
6986 assert(dst != xnoreg, "sanity");
6987 InstructionMark im(this);
6988 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
6989 attributes.set_is_evex_instruction();
6990 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6991 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6992 emit_int8(0x09);
6993 emit_operand(dst, src, 1);
6994 emit_int8((rmode));
6995 }
6996
6997 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
6998 assert(VM_Version::supports_avx(), "");
6999 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7000 attributes.set_rex_vex_w_reverted();
7001 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7002 emit_int16(0x51, (0xC0 | encode));
7003 }
7004
7005 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
7006 assert(VM_Version::supports_avx(), "");
7007 InstructionMark im(this);
7008 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7009 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7010 attributes.set_rex_vex_w_reverted();
7011 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7012 emit_int8(0x51);
7013 emit_operand(dst, src, 0);
7014 }
7015
7016 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
7017 assert(VM_Version::supports_avx(), "");
7018 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7019 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7020 emit_int16(0x51, (0xC0 | encode));
7021 }
7022
7023 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
7024 assert(VM_Version::supports_avx(), "");
7025 InstructionMark im(this);
7026 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7027 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7028 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7029 emit_int8(0x51);
7030 emit_operand(dst, src, 0);
7031 }
7032
7033 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
7034 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7035 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7036 attributes.set_rex_vex_w_reverted();
7037 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7038 emit_int16(0x54, (0xC0 | encode));
7039 }
7040
7041 void Assembler::andps(XMMRegister dst, XMMRegister src) {
7042 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7043 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7044 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7045 emit_int16(0x54, (0xC0 | encode));
7046 }
7047
7048 void Assembler::andps(XMMRegister dst, Address src) {
7049 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7050 InstructionMark im(this);
7051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7052 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7053 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7054 emit_int8(0x54);
7055 emit_operand(dst, src, 0);
7056 }
7057
7058 void Assembler::andpd(XMMRegister dst, Address src) {
7059 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7060 InstructionMark im(this);
7061 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7062 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7063 attributes.set_rex_vex_w_reverted();
7064 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7065 emit_int8(0x54);
7066 emit_operand(dst, src, 0);
7067 }
7068
7069 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7070 assert(VM_Version::supports_avx(), "");
7071 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7072 attributes.set_rex_vex_w_reverted();
7073 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7074 emit_int16(0x54, (0xC0 | encode));
7075 }
7076
7077 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7078 assert(VM_Version::supports_avx(), "");
7079 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7080 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7081 emit_int16(0x54, (0xC0 | encode));
7082 }
7083
7084 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7085 assert(VM_Version::supports_avx(), "");
7086 InstructionMark im(this);
7087 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7088 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7089 attributes.set_rex_vex_w_reverted();
7090 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7091 emit_int8(0x54);
7092 emit_operand(dst, src, 0);
7093 }
7094
7095 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7096 assert(VM_Version::supports_avx(), "");
7097 InstructionMark im(this);
7098 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7099 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7100 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7101 emit_int8(0x54);
7102 emit_operand(dst, src, 0);
7103 }
7104
7105 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
7106 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7107 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7108 attributes.set_rex_vex_w_reverted();
7109 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7110 emit_int8(0x15);
7111 emit_int8((0xC0 | encode));
7112 }
7113
7114 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
7115 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7116 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7117 attributes.set_rex_vex_w_reverted();
7118 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7119 emit_int16(0x14, (0xC0 | encode));
7120 }
7121
7122 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
7123 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7124 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7125 attributes.set_rex_vex_w_reverted();
7126 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7127 emit_int16(0x57, (0xC0 | encode));
7128 }
7129
7130 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
7131 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7132 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7133 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7134 emit_int16(0x57, (0xC0 | encode));
7135 }
7136
7137 void Assembler::xorpd(XMMRegister dst, Address src) {
7138 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7139 InstructionMark im(this);
7140 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7141 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7142 attributes.set_rex_vex_w_reverted();
7143 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7144 emit_int8(0x57);
7145 emit_operand(dst, src, 0);
7146 }
7147
7148 void Assembler::xorps(XMMRegister dst, Address src) {
7149 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7150 InstructionMark im(this);
7151 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7152 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7153 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7154 emit_int8(0x57);
7155 emit_operand(dst, src, 0);
7156 }
7157
7158 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7159 assert(VM_Version::supports_avx(), "");
7160 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7161 attributes.set_rex_vex_w_reverted();
7162 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7163 emit_int16(0x57, (0xC0 | encode));
7164 }
7165
7166 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7167 assert(VM_Version::supports_avx(), "");
7168 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7169 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7170 emit_int16(0x57, (0xC0 | encode));
7171 }
7172
7173 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7174 assert(VM_Version::supports_avx(), "");
7175 InstructionMark im(this);
7176 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7177 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7178 attributes.set_rex_vex_w_reverted();
7179 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7180 emit_int8(0x57);
7181 emit_operand(dst, src, 0);
7182 }
7183
7184 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7185 assert(VM_Version::supports_avx(), "");
7186 InstructionMark im(this);
7187 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7188 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7189 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7190 emit_int8(0x57);
7191 emit_operand(dst, src, 0);
7192 }
7193
7194 // Integer vector arithmetic
7195 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7196 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7197 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7198 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7199 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7200 emit_int16(0x01, (0xC0 | encode));
7201 }
7202
7203 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7204 assert(VM_Version::supports_avx() && (vector_len == 0) ||
7205 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
7206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7207 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7208 emit_int16(0x02, (0xC0 | encode));
7209 }
7210
7211 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
7212 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7213 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7214 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7215 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7216 }
7217
7218 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
7219 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7220 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7221 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7222 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7223 }
7224
7225 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
7226 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7227 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7228 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7229 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7230 }
7231
7232 void Assembler::paddd(XMMRegister dst, Address src) {
7233 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7234 InstructionMark im(this);
7235 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7236 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7237 emit_int8((unsigned char)0xFE);
7238 emit_operand(dst, src, 0);
7239 }
7240
7241 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
7242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7243 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7244 attributes.set_rex_vex_w_reverted();
7245 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7246 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7247 }
7248
7249 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
7250 assert(VM_Version::supports_sse3(), "");
7251 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7252 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7253 emit_int16(0x01, (0xC0 | encode));
7254 }
7255
7256 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
7257 assert(VM_Version::supports_sse3(), "");
7258 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
7259 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7260 emit_int16(0x02, (0xC0 | encode));
7261 }
7262
7263 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7264 assert(UseAVX > 0, "requires some form of AVX");
7265 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7266 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7267 emit_int16((unsigned char)0xFC, (0xC0 | encode));
7268 }
7269
7270 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7271 assert(UseAVX > 0, "requires some form of AVX");
7272 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7273 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7274 emit_int16((unsigned char)0xFD, (0xC0 | encode));
7275 }
7276
7277 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7278 assert(UseAVX > 0, "requires some form of AVX");
7279 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7280 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7281 emit_int16((unsigned char)0xFE, (0xC0 | encode));
7282 }
7283
7284 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7285 assert(UseAVX > 0, "requires some form of AVX");
7286 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7287 attributes.set_rex_vex_w_reverted();
7288 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7289 emit_int16((unsigned char)0xD4, (0xC0 | encode));
7290 }
7291
7292 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7293 assert(UseAVX > 0, "requires some form of AVX");
7294 InstructionMark im(this);
7295 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7296 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7297 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7298 emit_int8((unsigned char)0xFC);
7299 emit_operand(dst, src, 0);
7300 }
7301
7302 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7303 assert(UseAVX > 0, "requires some form of AVX");
7304 InstructionMark im(this);
7305 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7306 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7307 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7308 emit_int8((unsigned char)0xFD);
7309 emit_operand(dst, src, 0);
7310 }
7311
7312 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7313 assert(UseAVX > 0, "requires some form of AVX");
7314 InstructionMark im(this);
7315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7316 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7317 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7318 emit_int8((unsigned char)0xFE);
7319 emit_operand(dst, src, 0);
7320 }
7321
7322 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7323 assert(UseAVX > 0, "requires some form of AVX");
7324 InstructionMark im(this);
7325 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7326 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7327 attributes.set_rex_vex_w_reverted();
7328 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7329 emit_int8((unsigned char)0xD4);
7330 emit_operand(dst, src, 0);
7331 }
7332
7333 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
7334 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7335 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7336 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7337 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7338 }
7339
7340 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
7341 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7342 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7343 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7344 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7345 }
7346
7347 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
7348 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7349 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7350 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7351 }
7352
7353 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
7354 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7355 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7356 attributes.set_rex_vex_w_reverted();
7357 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7358 emit_int8((unsigned char)0xFB);
7359 emit_int8((0xC0 | encode));
7360 }
7361
7362 void Assembler::vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7363 assert(UseAVX > 0, "requires some form of AVX");
7364 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7365 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7366 emit_int16((unsigned char)0xD8, (0xC0 | encode));
7367 }
7368
7369 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7370 assert(UseAVX > 0, "requires some form of AVX");
7371 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7372 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7373 emit_int16((unsigned char)0xF8, (0xC0 | encode));
7374 }
7375
7376 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7377 assert(UseAVX > 0, "requires some form of AVX");
7378 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7379 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7380 emit_int16((unsigned char)0xF9, (0xC0 | encode));
7381 }
7382
7383 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7384 assert(UseAVX > 0, "requires some form of AVX");
7385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7386 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7387 emit_int16((unsigned char)0xFA, (0xC0 | encode));
7388 }
7389
7390 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7391 assert(UseAVX > 0, "requires some form of AVX");
7392 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7393 attributes.set_rex_vex_w_reverted();
7394 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7395 emit_int16((unsigned char)0xFB, (0xC0 | encode));
7396 }
7397
7398 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7399 assert(UseAVX > 0, "requires some form of AVX");
7400 InstructionMark im(this);
7401 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7402 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7403 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7404 emit_int8((unsigned char)0xF8);
7405 emit_operand(dst, src, 0);
7406 }
7407
7408 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7409 assert(UseAVX > 0, "requires some form of AVX");
7410 InstructionMark im(this);
7411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7412 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7413 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7414 emit_int8((unsigned char)0xF9);
7415 emit_operand(dst, src, 0);
7416 }
7417
7418 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7419 assert(UseAVX > 0, "requires some form of AVX");
7420 InstructionMark im(this);
7421 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7422 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7423 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7424 emit_int8((unsigned char)0xFA);
7425 emit_operand(dst, src, 0);
7426 }
7427
7428 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7429 assert(UseAVX > 0, "requires some form of AVX");
7430 InstructionMark im(this);
7431 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7432 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7433 attributes.set_rex_vex_w_reverted();
7434 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7435 emit_int8((unsigned char)0xFB);
7436 emit_operand(dst, src, 0);
7437 }
7438
7439 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
7440 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7441 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7442 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7443 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7444 }
7445
7446 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
7447 assert(VM_Version::supports_sse4_1(), "");
7448 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7449 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7450 emit_int16(0x40, (0xC0 | encode));
7451 }
7452
7453 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
7454 assert(VM_Version::supports_sse2(), "");
7455 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7456 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7457 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7458 }
7459
7460 void Assembler::vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7461 assert((vector_len == AVX_128bit && VM_Version::supports_avx()) ||
7462 (vector_len == AVX_256bit && VM_Version::supports_avx2()) ||
7463 (vector_len == AVX_512bit && VM_Version::supports_avx512bw()), "");
7464 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7465 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7466 emit_int16((unsigned char)0xE4, (0xC0 | encode));
7467 }
7468
7469 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7470 assert(UseAVX > 0, "requires some form of AVX");
7471 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7472 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7473 emit_int16((unsigned char)0xD5, (0xC0 | encode));
7474 }
7475
7476 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7477 assert(UseAVX > 0, "requires some form of AVX");
7478 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7479 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7480 emit_int16(0x40, (0xC0 | encode));
7481 }
7482
7483 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7484 assert(UseAVX > 2, "requires some form of EVEX");
7485 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7486 attributes.set_is_evex_instruction();
7487 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7488 emit_int16(0x40, (0xC0 | encode));
7489 }
7490
7491 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7492 assert(UseAVX > 0, "requires some form of AVX");
7493 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7494 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7495 emit_int16((unsigned char)0xF4, (0xC0 | encode));
7496 }
7497
7498 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7499 assert(UseAVX > 0, "requires some form of AVX");
7500 InstructionMark im(this);
7501 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7502 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
7503 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7504 emit_int8((unsigned char)0xD5);
7505 emit_operand(dst, src, 0);
7506 }
7507
7508 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7509 assert(UseAVX > 0, "requires some form of AVX");
7510 InstructionMark im(this);
7511 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7512 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7513 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7514 emit_int8(0x40);
7515 emit_operand(dst, src, 0);
7516 }
7517
7518 void Assembler::evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7519 assert(UseAVX > 2, "requires some form of EVEX");
7520 InstructionMark im(this);
7521 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ true);
7522 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
7523 attributes.set_is_evex_instruction();
7524 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7525 emit_int8(0x40);
7526 emit_operand(dst, src, 0);
7527 }
7528
7529 // Min, max
7530 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
7531 assert(VM_Version::supports_sse4_1(), "");
7532 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7533 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7534 emit_int16(0x38, (0xC0 | encode));
7535 }
7536
7537 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7538 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7539 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7540 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7541 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7542 emit_int16(0x38, (0xC0 | encode));
7543 }
7544
7545 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
7546 assert(VM_Version::supports_sse2(), "");
7547 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7548 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7549 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7550 }
7551
7552 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7553 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7554 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7555 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7556 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7557 emit_int16((unsigned char)0xEA, (0xC0 | encode));
7558 }
7559
7560 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
7561 assert(VM_Version::supports_sse4_1(), "");
7562 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7563 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7564 emit_int16(0x39, (0xC0 | encode));
7565 }
7566
7567 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7568 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7569 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7570 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7571 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7572 emit_int16(0x39, (0xC0 | encode));
7573 }
7574
7575 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7576 assert(UseAVX > 2, "requires AVX512F");
7577 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7578 attributes.set_is_evex_instruction();
7579 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7580 emit_int16(0x39, (0xC0 | encode));
7581 }
7582
7583 void Assembler::minps(XMMRegister dst, XMMRegister src) {
7584 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7585 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7586 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7587 emit_int16(0x5D, (0xC0 | encode));
7588 }
7589 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7590 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7591 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7592 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7593 emit_int16(0x5D, (0xC0 | encode));
7594 }
7595
7596 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
7597 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7598 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7599 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7600 emit_int16(0x5D, (0xC0 | encode));
7601 }
7602 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7603 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7604 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7605 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7606 emit_int16(0x5D, (0xC0 | encode));
7607 }
7608
7609 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
7610 assert(VM_Version::supports_sse4_1(), "");
7611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7612 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7613 emit_int16(0x3C, (0xC0 | encode));
7614 }
7615
7616 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7617 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7618 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7619 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7620 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7621 emit_int16(0x3C, (0xC0 | encode));
7622 }
7623
7624 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
7625 assert(VM_Version::supports_sse2(), "");
7626 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7627 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7628 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7629 }
7630
7631 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7632 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7633 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
7634 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7635 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7636 emit_int16((unsigned char)0xEE, (0xC0 | encode));
7637 }
7638
7639 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
7640 assert(VM_Version::supports_sse4_1(), "");
7641 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7642 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7643 emit_int16(0x3D, (0xC0 | encode));
7644 }
7645
7646 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7647 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
7648 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
7649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7650 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7651 emit_int16(0x3D, (0xC0 | encode));
7652 }
7653
7654 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7655 assert(UseAVX > 2, "requires AVX512F");
7656 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7657 attributes.set_is_evex_instruction();
7658 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7659 emit_int16(0x3D, (0xC0 | encode));
7660 }
7661
7662 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
7663 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7664 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7665 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7666 emit_int16(0x5F, (0xC0 | encode));
7667 }
7668
7669 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7670 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7671 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7673 emit_int16(0x5F, (0xC0 | encode));
7674 }
7675
7676 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
7677 NOT_LP64(assert(VM_Version::supports_sse(), ""));
7678 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7679 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7680 emit_int16(0x5F, (0xC0 | encode));
7681 }
7682
7683 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7684 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
7685 InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7686 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7687 emit_int16(0x5F, (0xC0 | encode));
7688 }
7689
7690 // Shift packed integers left by specified number of bits.
7691 void Assembler::psllw(XMMRegister dst, int shift) {
7692 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7693 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7694 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7695 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7696 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7697 }
7698
7699 void Assembler::pslld(XMMRegister dst, int shift) {
7700 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7701 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7702 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7703 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7704 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7705 }
7706
7707 void Assembler::psllq(XMMRegister dst, int shift) {
7708 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7709 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7710 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7711 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7712 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7713 }
7714
7715 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
7716 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7717 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7718 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7719 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7720 }
7721
7722 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
7723 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7724 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7725 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7726 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7727 }
7728
7729 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
7730 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7731 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7732 attributes.set_rex_vex_w_reverted();
7733 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7734 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7735 }
7736
7737 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7738 assert(UseAVX > 0, "requires some form of AVX");
7739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7740 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
7741 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7742 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7743 }
7744
7745 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7746 assert(UseAVX > 0, "requires some form of AVX");
7747 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7748 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7749 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
7750 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7751 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7752 }
7753
7754 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7755 assert(UseAVX > 0, "requires some form of AVX");
7756 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7757 attributes.set_rex_vex_w_reverted();
7758 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
7759 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7760 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7761 }
7762
7763 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7764 assert(UseAVX > 0, "requires some form of AVX");
7765 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7766 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7767 emit_int16((unsigned char)0xF1, (0xC0 | encode));
7768 }
7769
7770 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7771 assert(UseAVX > 0, "requires some form of AVX");
7772 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7773 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7774 emit_int16((unsigned char)0xF2, (0xC0 | encode));
7775 }
7776
7777 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7778 assert(UseAVX > 0, "requires some form of AVX");
7779 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7780 attributes.set_rex_vex_w_reverted();
7781 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7782 emit_int16((unsigned char)0xF3, (0xC0 | encode));
7783 }
7784
7785 // Shift packed integers logically right by specified number of bits.
7786 void Assembler::psrlw(XMMRegister dst, int shift) {
7787 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7788 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7789 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7790 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7791 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7792 }
7793
7794 void Assembler::psrld(XMMRegister dst, int shift) {
7795 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7796 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7797 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7798 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7799 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7800 }
7801
7802 void Assembler::psrlq(XMMRegister dst, int shift) {
7803 // Do not confuse it with psrldq SSE2 instruction which
7804 // shifts 128 bit value in xmm register by number of bytes.
7805 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7806 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7807 attributes.set_rex_vex_w_reverted();
7808 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7809 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7810 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7811 }
7812
7813 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
7814 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7815 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7816 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7817 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7818 }
7819
7820 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
7821 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7823 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7824 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7825 }
7826
7827 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
7828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7829 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7830 attributes.set_rex_vex_w_reverted();
7831 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7832 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7833 }
7834
7835 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7836 assert(UseAVX > 0, "requires some form of AVX");
7837 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7838 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
7839 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7840 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7841 }
7842
7843 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7844 assert(UseAVX > 0, "requires some form of AVX");
7845 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7846 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
7847 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7848 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7849 }
7850
7851 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7852 assert(UseAVX > 0, "requires some form of AVX");
7853 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7854 attributes.set_rex_vex_w_reverted();
7855 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
7856 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7857 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
7858 }
7859
7860 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7861 assert(UseAVX > 0, "requires some form of AVX");
7862 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7863 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7864 emit_int16((unsigned char)0xD1, (0xC0 | encode));
7865 }
7866
7867 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7868 assert(UseAVX > 0, "requires some form of AVX");
7869 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7870 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7871 emit_int16((unsigned char)0xD2, (0xC0 | encode));
7872 }
7873
7874 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7875 assert(UseAVX > 0, "requires some form of AVX");
7876 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7877 attributes.set_rex_vex_w_reverted();
7878 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7879 emit_int16((unsigned char)0xD3, (0xC0 | encode));
7880 }
7881
7882 void Assembler::evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7883 assert(VM_Version::supports_avx512bw(), "");
7884 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7885 attributes.set_is_evex_instruction();
7886 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7887 emit_int16(0x10, (0xC0 | encode));
7888 }
7889
7890 void Assembler::evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7891 assert(VM_Version::supports_avx512bw(), "");
7892 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7893 attributes.set_is_evex_instruction();
7894 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7895 emit_int16(0x12, (0xC0 | encode));
7896 }
7897
7898 // Shift packed integers arithmetically right by specified number of bits.
7899 void Assembler::psraw(XMMRegister dst, int shift) {
7900 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7901 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7902 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7903 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7904 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7905 }
7906
7907 void Assembler::psrad(XMMRegister dst, int shift) {
7908 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7909 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7910 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
7911 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7912 emit_int8(0x72);
7913 emit_int8((0xC0 | encode));
7914 emit_int8(shift & 0xFF);
7915 }
7916
7917 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
7918 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7919 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7920 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7921 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7922 }
7923
7924 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
7925 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7926 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7927 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7928 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7929 }
7930
7931 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7932 assert(UseAVX > 0, "requires some form of AVX");
7933 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7934 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7935 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7936 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
7937 }
7938
7939 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7940 assert(UseAVX > 0, "requires some form of AVX");
7941 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7942 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
7943 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7944 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
7945 }
7946
7947 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7948 assert(UseAVX > 0, "requires some form of AVX");
7949 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7950 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7951 emit_int16((unsigned char)0xE1, (0xC0 | encode));
7952 }
7953
7954 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7955 assert(UseAVX > 0, "requires some form of AVX");
7956 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7957 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7958 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7959 }
7960
7961 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
7962 assert(UseAVX > 2, "requires AVX512");
7963 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
7964 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7965 attributes.set_is_evex_instruction();
7966 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7967 emit_int24((unsigned char)0x72, (0xC0 | encode), shift & 0xFF);
7968 }
7969
7970 void Assembler::evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
7971 assert(UseAVX > 2, "requires AVX512");
7972 assert ((VM_Version::supports_avx512vl() || vector_len == 2), "requires AVX512vl");
7973 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7974 attributes.set_is_evex_instruction();
7975 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7976 emit_int16((unsigned char)0xE2, (0xC0 | encode));
7977 }
7978
7979 // logical operations packed integers
7980 void Assembler::pand(XMMRegister dst, XMMRegister src) {
7981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
7982 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7983 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7984 emit_int16((unsigned char)0xDB, (0xC0 | encode));
7985 }
7986
7987 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
7988 assert(UseAVX > 0, "requires some form of AVX");
7989 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7990 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
7991 emit_int16((unsigned char)0xDB, (0xC0 | encode));
7992 }
7993
7994 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
7995 assert(UseAVX > 0, "requires some form of AVX");
7996 InstructionMark im(this);
7997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
7998 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
7999 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8000 emit_int8((unsigned char)0xDB);
8001 emit_operand(dst, src, 0);
8002 }
8003
8004 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8005 evpandq(dst, k0, nds, src, false, vector_len);
8006 }
8007
8008 void Assembler::evpandq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8009 evpandq(dst, k0, nds, src, false, vector_len);
8010 }
8011
8012 //Variable Shift packed integers logically left.
8013 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8014 assert(UseAVX > 1, "requires AVX2");
8015 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8016 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8017 emit_int16(0x47, (0xC0 | encode));
8018 }
8019
8020 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8021 assert(UseAVX > 1, "requires AVX2");
8022 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8023 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8024 emit_int16(0x47, (0xC0 | encode));
8025 }
8026
8027 //Variable Shift packed integers logically right.
8028 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8029 assert(UseAVX > 1, "requires AVX2");
8030 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8031 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8032 emit_int16(0x45, (0xC0 | encode));
8033 }
8034
8035 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8036 assert(UseAVX > 1, "requires AVX2");
8037 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8038 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8039 emit_int16(0x45, (0xC0 | encode));
8040 }
8041
8042 //Variable right Shift arithmetic packed integers .
8043 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8044 assert(UseAVX > 1, "requires AVX2");
8045 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8046 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8047 emit_int16(0x46, (0xC0 | encode));
8048 }
8049
8050 void Assembler::evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8051 assert(VM_Version::supports_avx512bw(), "");
8052 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8053 attributes.set_is_evex_instruction();
8054 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8055 emit_int16(0x11, (0xC0 | encode));
8056 }
8057
8058 void Assembler::evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8059 assert(UseAVX > 2, "requires AVX512");
8060 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8061 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8062 attributes.set_is_evex_instruction();
8063 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8064 emit_int16(0x46, (0xC0 | encode));
8065 }
8066
8067 void Assembler::vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8068 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8069 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8070 attributes.set_is_evex_instruction();
8071 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8072 emit_int16(0x71, (0xC0 | encode));
8073 }
8074
8075 void Assembler::vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8076 assert(VM_Version::supports_avx512_vbmi2(), "requires vbmi2");
8077 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8078 attributes.set_is_evex_instruction();
8079 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8080 emit_int16(0x73, (0xC0 | encode));
8081 }
8082
8083 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
8084 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8085 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8086 attributes.set_rex_vex_w_reverted();
8087 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8088 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8089 }
8090
8091 void Assembler::vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8092 assert(UseAVX > 0, "requires some form of AVX");
8093 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8094 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8095 emit_int16((unsigned char)0xDF, (0xC0 | encode));
8096 }
8097
8098 void Assembler::por(XMMRegister dst, XMMRegister src) {
8099 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8100 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8101 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8102 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8103 }
8104
8105 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8106 assert(UseAVX > 0, "requires some form of AVX");
8107 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8108 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8109 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8110 }
8111
8112 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8113 assert(UseAVX > 0, "requires some form of AVX");
8114 InstructionMark im(this);
8115 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8116 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8117 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8118 emit_int8((unsigned char)0xEB);
8119 emit_operand(dst, src, 0);
8120 }
8121
8122 void Assembler::evporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8123 evporq(dst, k0, nds, src, false, vector_len);
8124 }
8125
8126 void Assembler::evporq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8127 evporq(dst, k0, nds, src, false, vector_len);
8128 }
8129
8130 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8131 assert(VM_Version::supports_evex(), "");
8132 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8133 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8134 attributes.set_is_evex_instruction();
8135 attributes.set_embedded_opmask_register_specifier(mask);
8136 if (merge) {
8137 attributes.reset_is_clear_context();
8138 }
8139 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8140 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8141 }
8142
8143 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8144 assert(VM_Version::supports_evex(), "");
8145 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
8146 InstructionMark im(this);
8147 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8148 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8149 attributes.set_is_evex_instruction();
8150 attributes.set_embedded_opmask_register_specifier(mask);
8151 if (merge) {
8152 attributes.reset_is_clear_context();
8153 }
8154 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8155 emit_int8((unsigned char)0xEB);
8156 emit_operand(dst, src, 0);
8157 }
8158
8159 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
8160 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
8161 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8162 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8163 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8164 }
8165
8166 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8167 assert(UseAVX > 0, "requires some form of AVX");
8168 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8169 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8170 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8171 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8172 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8173 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8174 }
8175
8176 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8177 assert(UseAVX > 0, "requires some form of AVX");
8178 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
8179 vector_len == AVX_256bit ? VM_Version::supports_avx2() :
8180 vector_len == AVX_512bit ? VM_Version::supports_evex() : 0, "");
8181 InstructionMark im(this);
8182 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8183 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
8184 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8185 emit_int8((unsigned char)0xEF);
8186 emit_operand(dst, src, 0);
8187 }
8188
8189 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8190 assert(UseAVX > 2, "requires some form of EVEX");
8191 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8192 attributes.set_rex_vex_w_reverted();
8193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8194 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8195 }
8196
8197 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8198 // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
8199 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8200 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8201 attributes.set_is_evex_instruction();
8202 attributes.set_embedded_opmask_register_specifier(mask);
8203 if (merge) {
8204 attributes.reset_is_clear_context();
8205 }
8206 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8207 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8208 }
8209
8210 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8211 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8212 InstructionMark im(this);
8213 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8214 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8215 attributes.set_is_evex_instruction();
8216 attributes.set_embedded_opmask_register_specifier(mask);
8217 if (merge) {
8218 attributes.reset_is_clear_context();
8219 }
8220 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8221 emit_int8((unsigned char)0xEF);
8222 emit_operand(dst, src, 0);
8223 }
8224
8225 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8226 // Encoding: EVEX.NDS.XXX.66.0F.W1 EF /r
8227 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8228 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8229 attributes.set_is_evex_instruction();
8230 attributes.set_embedded_opmask_register_specifier(mask);
8231 if (merge) {
8232 attributes.reset_is_clear_context();
8233 }
8234 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8235 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8236 }
8237
8238 void Assembler::evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8239 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8240 InstructionMark im(this);
8241 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8242 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8243 attributes.set_is_evex_instruction();
8244 attributes.set_embedded_opmask_register_specifier(mask);
8245 if (merge) {
8246 attributes.reset_is_clear_context();
8247 }
8248 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8249 emit_int8((unsigned char)0xEF);
8250 emit_operand(dst, src, 0);
8251 }
8252
8253 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8254 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8255 InstructionMark im(this);
8256 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8257 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8258 attributes.set_is_evex_instruction();
8259 attributes.set_embedded_opmask_register_specifier(mask);
8260 if (merge) {
8261 attributes.reset_is_clear_context();
8262 }
8263 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8264 emit_int8((unsigned char)0xDB);
8265 emit_operand(dst, src, 0);
8266 }
8267
8268 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8269 assert(VM_Version::supports_evex(), "requires AVX512F");
8270 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8271 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8272 attributes.set_is_evex_instruction();
8273 attributes.set_embedded_opmask_register_specifier(mask);
8274 if (merge) {
8275 attributes.reset_is_clear_context();
8276 }
8277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8278 emit_int16((unsigned char)0xDB, (0xC0 | encode));
8279 }
8280
8281 void Assembler::evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8282 assert(VM_Version::supports_evex(), "requires AVX512F");
8283 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8284 InstructionMark im(this);
8285 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8286 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8287 attributes.set_is_evex_instruction();
8288 attributes.set_embedded_opmask_register_specifier(mask);
8289 if (merge) {
8290 attributes.reset_is_clear_context();
8291 }
8292 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8293 emit_int8((unsigned char)0xDB);
8294 emit_operand(dst, src, 0);
8295 }
8296
8297 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8298 assert(VM_Version::supports_evex(), "requires AVX512F");
8299 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8300 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8301 attributes.set_is_evex_instruction();
8302 attributes.set_embedded_opmask_register_specifier(mask);
8303 if (merge) {
8304 attributes.reset_is_clear_context();
8305 }
8306 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8307 emit_int16((unsigned char)0xEB, (0xC0 | encode));
8308 }
8309
8310 void Assembler::evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8311 assert(VM_Version::supports_evex(), "requires AVX512F");
8312 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8313 InstructionMark im(this);
8314 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8315 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
8316 attributes.set_is_evex_instruction();
8317 attributes.set_embedded_opmask_register_specifier(mask);
8318 if (merge) {
8319 attributes.reset_is_clear_context();
8320 }
8321 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8322 emit_int8((unsigned char)0xEB);
8323 emit_operand(dst, src, 0);
8324 }
8325
8326 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8327 assert(VM_Version::supports_evex(), "requires EVEX support");
8328 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8329 attributes.set_is_evex_instruction();
8330 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8331 emit_int16((unsigned char)0xEF, (0xC0 | encode));
8332 }
8333
8334 void Assembler::evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
8335 assert(VM_Version::supports_evex(), "requires EVEX support");
8336 assert(dst != xnoreg, "sanity");
8337 InstructionMark im(this);
8338 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8339 attributes.set_is_evex_instruction();
8340 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8341 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8342 emit_int8((unsigned char)0xEF);
8343 emit_operand(dst, src, 0);
8344 }
8345
8346 void Assembler::evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8347 assert(VM_Version::supports_evex(), "requires EVEX support");
8348 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8349 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8350 attributes.set_is_evex_instruction();
8351 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8352 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8353 }
8354
8355 void Assembler::evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8356 assert(VM_Version::supports_evex(), "requires EVEX support");
8357 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8358 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8359 attributes.set_is_evex_instruction();
8360 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8361 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8362 }
8363
8364 void Assembler::evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8365 assert(VM_Version::supports_evex(), "requires EVEX support");
8366 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8367 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8368 attributes.set_is_evex_instruction();
8369 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8370 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8371 }
8372
8373 void Assembler::evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
8374 assert(VM_Version::supports_evex(), "requires EVEX support");
8375 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8376 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8377 attributes.set_is_evex_instruction();
8378 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8379 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
8380 }
8381
8382 void Assembler::evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8383 assert(VM_Version::supports_evex(), "requires EVEX support");
8384 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8386 attributes.set_is_evex_instruction();
8387 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8388 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8389 }
8390
8391 void Assembler::evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8392 assert(VM_Version::supports_evex(), "requires EVEX support");
8393 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8394 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8395 attributes.set_is_evex_instruction();
8396 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8397 emit_int16(0x15, (unsigned char)(0xC0 | encode));
8398 }
8399
8400 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8401 assert(VM_Version::supports_evex(), "requires EVEX support");
8402 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8403 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8404 attributes.set_is_evex_instruction();
8405 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8406 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8407 }
8408
8409 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
8410 assert(VM_Version::supports_evex(), "requires EVEX support");
8411 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8412 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8413 attributes.set_is_evex_instruction();
8414 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8415 emit_int16(0x14, (unsigned char)(0xC0 | encode));
8416 }
8417
8418 void Assembler::evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8419 assert(VM_Version::supports_avx512cd(), "");
8420 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8421 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8422 attributes.set_is_evex_instruction();
8423 attributes.set_embedded_opmask_register_specifier(mask);
8424 if (merge) {
8425 attributes.reset_is_clear_context();
8426 }
8427 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8428 emit_int16(0x44, (0xC0 | encode));
8429 }
8430
8431 void Assembler::evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8432 assert(VM_Version::supports_avx512cd(), "");
8433 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8434 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8435 attributes.set_is_evex_instruction();
8436 attributes.set_embedded_opmask_register_specifier(mask);
8437 if (merge) {
8438 attributes.reset_is_clear_context();
8439 }
8440 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8441 emit_int16(0x44, (0xC0 | encode));
8442 }
8443
8444 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8445 assert(VM_Version::supports_evex(), "requires EVEX support");
8446 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8447 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8448 attributes.set_is_evex_instruction();
8449 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8450 emit_int8(0x25);
8451 emit_int8((unsigned char)(0xC0 | encode));
8452 emit_int8(imm8);
8453 }
8454
8455 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8456 assert(VM_Version::supports_evex(), "requires EVEX support");
8457 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8458 assert(dst != xnoreg, "sanity");
8459 InstructionMark im(this);
8460 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8461 attributes.set_is_evex_instruction();
8462 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8463 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8464 emit_int8(0x25);
8465 emit_operand(dst, src3, 1);
8466 emit_int8(imm8);
8467 }
8468
8469 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
8470 assert(VM_Version::supports_evex(), "requires AVX512F");
8471 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires AVX512VL");
8472 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8473 attributes.set_is_evex_instruction();
8474 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8475 emit_int8(0x25);
8476 emit_int8((unsigned char)(0xC0 | encode));
8477 emit_int8(imm8);
8478 }
8479
8480 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
8481 assert(VM_Version::supports_evex(), "requires EVEX support");
8482 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
8483 assert(dst != xnoreg, "sanity");
8484 InstructionMark im(this);
8485 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8486 attributes.set_is_evex_instruction();
8487 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
8488 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8489 emit_int8(0x25);
8490 emit_operand(dst, src3, 1);
8491 emit_int8(imm8);
8492 }
8493
8494 void Assembler::evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8495 assert(VM_Version::supports_evex(), "");
8496 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8497 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8498 attributes.set_is_evex_instruction();
8499 attributes.set_embedded_opmask_register_specifier(mask);
8500 if (merge) {
8501 attributes.reset_is_clear_context();
8502 }
8503 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8504 emit_int16((unsigned char)0x88, (0xC0 | encode));
8505 }
8506
8507 void Assembler::evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8508 assert(VM_Version::supports_evex(), "");
8509 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8510 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8511 attributes.set_is_evex_instruction();
8512 attributes.set_embedded_opmask_register_specifier(mask);
8513 if (merge) {
8514 attributes.reset_is_clear_context();
8515 }
8516 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8517 emit_int16((unsigned char)0x88, (0xC0 | encode));
8518 }
8519
8520 void Assembler::evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8521 assert(VM_Version::supports_avx512_vbmi2(), "");
8522 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8523 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8524 attributes.set_is_evex_instruction();
8525 attributes.set_embedded_opmask_register_specifier(mask);
8526 if (merge) {
8527 attributes.reset_is_clear_context();
8528 }
8529 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8530 emit_int16(0x62, (0xC0 | encode));
8531 }
8532
8533 void Assembler::evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8534 assert(VM_Version::supports_avx512_vbmi2(), "");
8535 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8536 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8537 attributes.set_is_evex_instruction();
8538 attributes.set_embedded_opmask_register_specifier(mask);
8539 if (merge) {
8540 attributes.reset_is_clear_context();
8541 }
8542 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8543 emit_int16(0x62, (0xC0 | encode));
8544 }
8545
8546 void Assembler::evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8547 assert(VM_Version::supports_evex(), "");
8548 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8549 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8550 attributes.set_is_evex_instruction();
8551 attributes.set_embedded_opmask_register_specifier(mask);
8552 if (merge) {
8553 attributes.reset_is_clear_context();
8554 }
8555 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8556 emit_int16((unsigned char)0x89, (0xC0 | encode));
8557 }
8558
8559 void Assembler::evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
8560 assert(VM_Version::supports_evex(), "");
8561 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
8562 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
8563 attributes.set_is_evex_instruction();
8564 attributes.set_embedded_opmask_register_specifier(mask);
8565 if (merge) {
8566 attributes.reset_is_clear_context();
8567 }
8568 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8569 emit_int16((unsigned char)0x89, (0xC0 | encode));
8570 }
8571
8572 // vinserti forms
8573
8574 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8575 assert(VM_Version::supports_avx2(), "");
8576 assert(imm8 <= 0x01, "imm8: %u", imm8);
8577 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8578 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8579 // last byte:
8580 // 0x00 - insert into lower 128 bits
8581 // 0x01 - insert into upper 128 bits
8582 emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
8583 }
8584
8585 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8586 assert(VM_Version::supports_avx2(), "");
8587 assert(dst != xnoreg, "sanity");
8588 assert(imm8 <= 0x01, "imm8: %u", imm8);
8589 InstructionMark im(this);
8590 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8591 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8592 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8593 emit_int8(0x38);
8594 emit_operand(dst, src, 1);
8595 // 0x00 - insert into lower 128 bits
8596 // 0x01 - insert into upper 128 bits
8597 emit_int8(imm8 & 0x01);
8598 }
8599
8600 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8601 assert(VM_Version::supports_evex(), "");
8602 assert(imm8 <= 0x03, "imm8: %u", imm8);
8603 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8604 attributes.set_is_evex_instruction();
8605 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8606 // imm8:
8607 // 0x00 - insert into q0 128 bits (0..127)
8608 // 0x01 - insert into q1 128 bits (128..255)
8609 // 0x02 - insert into q2 128 bits (256..383)
8610 // 0x03 - insert into q3 128 bits (384..511)
8611 emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
8612 }
8613
8614 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8615 assert(VM_Version::supports_evex(), "");
8616 assert(dst != xnoreg, "sanity");
8617 assert(imm8 <= 0x03, "imm8: %u", imm8);
8618 InstructionMark im(this);
8619 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8620 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8621 attributes.set_is_evex_instruction();
8622 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8623 emit_int8(0x18);
8624 emit_operand(dst, src, 1);
8625 // 0x00 - insert into q0 128 bits (0..127)
8626 // 0x01 - insert into q1 128 bits (128..255)
8627 // 0x02 - insert into q2 128 bits (256..383)
8628 // 0x03 - insert into q3 128 bits (384..511)
8629 emit_int8(imm8 & 0x03);
8630 }
8631
8632 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8633 assert(VM_Version::supports_evex(), "");
8634 assert(imm8 <= 0x01, "imm8: %u", imm8);
8635 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8636 attributes.set_is_evex_instruction();
8637 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8638 //imm8:
8639 // 0x00 - insert into lower 256 bits
8640 // 0x01 - insert into upper 256 bits
8641 emit_int24(0x3A, (0xC0 | encode), imm8 & 0x01);
8642 }
8643
8644
8645 // vinsertf forms
8646
8647 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8648 assert(VM_Version::supports_avx(), "");
8649 assert(imm8 <= 0x01, "imm8: %u", imm8);
8650 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8651 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8652 // imm8:
8653 // 0x00 - insert into lower 128 bits
8654 // 0x01 - insert into upper 128 bits
8655 emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
8656 }
8657
8658 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8659 assert(VM_Version::supports_avx(), "");
8660 assert(dst != xnoreg, "sanity");
8661 assert(imm8 <= 0x01, "imm8: %u", imm8);
8662 InstructionMark im(this);
8663 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8664 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8665 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8666 emit_int8(0x18);
8667 emit_operand(dst, src, 1);
8668 // 0x00 - insert into lower 128 bits
8669 // 0x01 - insert into upper 128 bits
8670 emit_int8(imm8 & 0x01);
8671 }
8672
8673 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8674 assert(VM_Version::supports_evex(), "");
8675 assert(imm8 <= 0x03, "imm8: %u", imm8);
8676 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8677 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8678 // imm8:
8679 // 0x00 - insert into q0 128 bits (0..127)
8680 // 0x01 - insert into q1 128 bits (128..255)
8681 // 0x02 - insert into q0 128 bits (256..383)
8682 // 0x03 - insert into q1 128 bits (384..512)
8683 emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
8684 }
8685
8686 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8687 assert(VM_Version::supports_evex(), "");
8688 assert(dst != xnoreg, "sanity");
8689 assert(imm8 <= 0x03, "imm8: %u", imm8);
8690 InstructionMark im(this);
8691 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8692 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8693 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8694 emit_int8(0x18);
8695 emit_operand(dst, src, 1);
8696 // 0x00 - insert into q0 128 bits (0..127)
8697 // 0x01 - insert into q1 128 bits (128..255)
8698 // 0x02 - insert into q0 128 bits (256..383)
8699 // 0x03 - insert into q1 128 bits (384..512)
8700 emit_int8(imm8 & 0x03);
8701 }
8702
8703 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
8704 assert(VM_Version::supports_evex(), "");
8705 assert(imm8 <= 0x01, "imm8: %u", imm8);
8706 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8707 attributes.set_is_evex_instruction();
8708 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8709 // imm8:
8710 // 0x00 - insert into lower 256 bits
8711 // 0x01 - insert into upper 256 bits
8712 emit_int24(0x1A, (0xC0 | encode), imm8 & 0x01);
8713 }
8714
8715 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
8716 assert(VM_Version::supports_evex(), "");
8717 assert(dst != xnoreg, "sanity");
8718 assert(imm8 <= 0x01, "imm8: %u", imm8);
8719 InstructionMark im(this);
8720 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8721 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8722 attributes.set_is_evex_instruction();
8723 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8724 emit_int8(0x1A);
8725 emit_operand(dst, src, 1);
8726 // 0x00 - insert into lower 256 bits
8727 // 0x01 - insert into upper 256 bits
8728 emit_int8(imm8 & 0x01);
8729 }
8730
8731
8732 // vextracti forms
8733
8734 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8735 assert(VM_Version::supports_avx2(), "");
8736 assert(imm8 <= 0x01, "imm8: %u", imm8);
8737 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8738 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8739 // imm8:
8740 // 0x00 - extract from lower 128 bits
8741 // 0x01 - extract from upper 128 bits
8742 emit_int24(0x39, (0xC0 | encode), imm8 & 0x01);
8743 }
8744
8745 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
8746 assert(VM_Version::supports_avx2(), "");
8747 assert(src != xnoreg, "sanity");
8748 assert(imm8 <= 0x01, "imm8: %u", imm8);
8749 InstructionMark im(this);
8750 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8751 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8752 attributes.reset_is_clear_context();
8753 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8754 emit_int8(0x39);
8755 emit_operand(src, dst, 1);
8756 // 0x00 - extract from lower 128 bits
8757 // 0x01 - extract from upper 128 bits
8758 emit_int8(imm8 & 0x01);
8759 }
8760
8761 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8762 assert(VM_Version::supports_evex(), "");
8763 assert(imm8 <= 0x03, "imm8: %u", imm8);
8764 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8765 attributes.set_is_evex_instruction();
8766 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8767 // imm8:
8768 // 0x00 - extract from bits 127:0
8769 // 0x01 - extract from bits 255:128
8770 // 0x02 - extract from bits 383:256
8771 // 0x03 - extract from bits 511:384
8772 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8773 }
8774
8775 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
8776 assert(VM_Version::supports_evex(), "");
8777 assert(src != xnoreg, "sanity");
8778 assert(imm8 <= 0x03, "imm8: %u", imm8);
8779 InstructionMark im(this);
8780 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8781 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8782 attributes.reset_is_clear_context();
8783 attributes.set_is_evex_instruction();
8784 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8785 emit_int8(0x39);
8786 emit_operand(src, dst, 1);
8787 // 0x00 - extract from bits 127:0
8788 // 0x01 - extract from bits 255:128
8789 // 0x02 - extract from bits 383:256
8790 // 0x03 - extract from bits 511:384
8791 emit_int8(imm8 & 0x03);
8792 }
8793
8794 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8795 assert(VM_Version::supports_avx512dq(), "");
8796 assert(imm8 <= 0x03, "imm8: %u", imm8);
8797 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8798 attributes.set_is_evex_instruction();
8799 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8800 // imm8:
8801 // 0x00 - extract from bits 127:0
8802 // 0x01 - extract from bits 255:128
8803 // 0x02 - extract from bits 383:256
8804 // 0x03 - extract from bits 511:384
8805 emit_int24(0x39, (0xC0 | encode), imm8 & 0x03);
8806 }
8807
8808 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8809 assert(VM_Version::supports_evex(), "");
8810 assert(imm8 <= 0x01, "imm8: %u", imm8);
8811 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8812 attributes.set_is_evex_instruction();
8813 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8814 // imm8:
8815 // 0x00 - extract from lower 256 bits
8816 // 0x01 - extract from upper 256 bits
8817 emit_int24(0x3B, (0xC0 | encode), imm8 & 0x01);
8818 }
8819
8820 void Assembler::vextracti64x4(Address dst, XMMRegister src, uint8_t imm8) {
8821 assert(VM_Version::supports_evex(), "");
8822 assert(src != xnoreg, "sanity");
8823 assert(imm8 <= 0x01, "imm8: %u", imm8);
8824 InstructionMark im(this);
8825 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8826 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
8827 attributes.reset_is_clear_context();
8828 attributes.set_is_evex_instruction();
8829 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8830 emit_int8(0x38);
8831 emit_operand(src, dst, 1);
8832 // 0x00 - extract from lower 256 bits
8833 // 0x01 - extract from upper 256 bits
8834 emit_int8(imm8 & 0x01);
8835 }
8836 // vextractf forms
8837
8838 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8839 assert(VM_Version::supports_avx(), "");
8840 assert(imm8 <= 0x01, "imm8: %u", imm8);
8841 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8842 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8843 // imm8:
8844 // 0x00 - extract from lower 128 bits
8845 // 0x01 - extract from upper 128 bits
8846 emit_int24(0x19, (0xC0 | encode), imm8 & 0x01);
8847 }
8848
8849 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
8850 assert(VM_Version::supports_avx(), "");
8851 assert(src != xnoreg, "sanity");
8852 assert(imm8 <= 0x01, "imm8: %u", imm8);
8853 InstructionMark im(this);
8854 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8855 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8856 attributes.reset_is_clear_context();
8857 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8858 emit_int8(0x19);
8859 emit_operand(src, dst, 1);
8860 // 0x00 - extract from lower 128 bits
8861 // 0x01 - extract from upper 128 bits
8862 emit_int8(imm8 & 0x01);
8863 }
8864
8865 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8866 assert(VM_Version::supports_evex(), "");
8867 assert(imm8 <= 0x03, "imm8: %u", imm8);
8868 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8869 attributes.set_is_evex_instruction();
8870 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8871 // imm8:
8872 // 0x00 - extract from bits 127:0
8873 // 0x01 - extract from bits 255:128
8874 // 0x02 - extract from bits 383:256
8875 // 0x03 - extract from bits 511:384
8876 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8877 }
8878
8879 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
8880 assert(VM_Version::supports_evex(), "");
8881 assert(src != xnoreg, "sanity");
8882 assert(imm8 <= 0x03, "imm8: %u", imm8);
8883 InstructionMark im(this);
8884 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8885 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
8886 attributes.reset_is_clear_context();
8887 attributes.set_is_evex_instruction();
8888 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8889 emit_int8(0x19);
8890 emit_operand(src, dst, 1);
8891 // 0x00 - extract from bits 127:0
8892 // 0x01 - extract from bits 255:128
8893 // 0x02 - extract from bits 383:256
8894 // 0x03 - extract from bits 511:384
8895 emit_int8(imm8 & 0x03);
8896 }
8897
8898 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8899 assert(VM_Version::supports_avx512dq(), "");
8900 assert(imm8 <= 0x03, "imm8: %u", imm8);
8901 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8902 attributes.set_is_evex_instruction();
8903 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8904 // imm8:
8905 // 0x00 - extract from bits 127:0
8906 // 0x01 - extract from bits 255:128
8907 // 0x02 - extract from bits 383:256
8908 // 0x03 - extract from bits 511:384
8909 emit_int24(0x19, (0xC0 | encode), imm8 & 0x03);
8910 }
8911
8912 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
8913 assert(VM_Version::supports_evex(), "");
8914 assert(imm8 <= 0x01, "imm8: %u", imm8);
8915 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8916 attributes.set_is_evex_instruction();
8917 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8918 // imm8:
8919 // 0x00 - extract from lower 256 bits
8920 // 0x01 - extract from upper 256 bits
8921 emit_int24(0x1B, (0xC0 | encode), imm8 & 0x01);
8922 }
8923
8924 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
8925 assert(VM_Version::supports_evex(), "");
8926 assert(src != xnoreg, "sanity");
8927 assert(imm8 <= 0x01, "imm8: %u", imm8);
8928 InstructionMark im(this);
8929 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
8930 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
8931 attributes.reset_is_clear_context();
8932 attributes.set_is_evex_instruction();
8933 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8934 emit_int8(0x1B);
8935 emit_operand(src, dst, 1);
8936 // 0x00 - extract from lower 256 bits
8937 // 0x01 - extract from upper 256 bits
8938 emit_int8(imm8 & 0x01);
8939 }
8940
8941 void Assembler::extractps(Register dst, XMMRegister src, uint8_t imm8) {
8942 assert(VM_Version::supports_sse4_1(), "");
8943 assert(imm8 <= 0x03, "imm8: %u", imm8);
8944 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
8945 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8946 // imm8:
8947 // 0x00 - extract from bits 31:0
8948 // 0x01 - extract from bits 63:32
8949 // 0x02 - extract from bits 95:64
8950 // 0x03 - extract from bits 127:96
8951 emit_int24(0x17, (0xC0 | encode), imm8 & 0x03);
8952 }
8953
8954 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
8955 void Assembler::vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
8956 assert(VM_Version::supports_avx2(), "");
8957 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8958 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8959 emit_int16(0x78, (0xC0 | encode));
8960 }
8961
8962 void Assembler::vpbroadcastb(XMMRegister dst, Address src, int vector_len) {
8963 assert(VM_Version::supports_avx2(), "");
8964 assert(dst != xnoreg, "sanity");
8965 InstructionMark im(this);
8966 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8967 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
8968 // swap src<->dst for encoding
8969 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8970 emit_int8(0x78);
8971 emit_operand(dst, src, 0);
8972 }
8973
8974 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
8975 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
8976 assert(VM_Version::supports_avx2(), "");
8977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8978 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8979 emit_int16(0x79, (0xC0 | encode));
8980 }
8981
8982 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
8983 assert(VM_Version::supports_avx2(), "");
8984 assert(dst != xnoreg, "sanity");
8985 InstructionMark im(this);
8986 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8987 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
8988 // swap src<->dst for encoding
8989 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8990 emit_int8(0x79);
8991 emit_operand(dst, src, 0);
8992 }
8993
8994 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8995 assert(UseAVX > 0, "requires some form of AVX");
8996 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
8997 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8998 emit_int16((unsigned char)0xF6, (0xC0 | encode));
8999 }
9000
9001 void Assembler::vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9002 assert(UseAVX > 0, "requires some form of AVX");
9003 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9004 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9005 emit_int16(0x69, (0xC0 | encode));
9006 }
9007
9008 void Assembler::vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9009 assert(UseAVX > 0, "requires some form of AVX");
9010 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9011 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9012 emit_int16(0x61, (0xC0 | encode));
9013 }
9014
9015 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9016 assert(UseAVX > 0, "requires some form of AVX");
9017 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9018 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9019 emit_int16(0x6A, (0xC0 | encode));
9020 }
9021
9022 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
9023 assert(UseAVX > 0, "requires some form of AVX");
9024 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
9025 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9026 emit_int16(0x62, (0xC0 | encode));
9027 }
9028
9029 // xmm/mem sourced byte/word/dword/qword replicate
9030 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9031 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9032 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9033 attributes.set_is_evex_instruction();
9034 attributes.set_embedded_opmask_register_specifier(mask);
9035 if (merge) {
9036 attributes.reset_is_clear_context();
9037 }
9038 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9039 emit_int16((unsigned char)0xFC, (0xC0 | encode));
9040 }
9041
9042 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9043 InstructionMark im(this);
9044 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9045 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9046 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9047 attributes.set_is_evex_instruction();
9048 attributes.set_embedded_opmask_register_specifier(mask);
9049 if (merge) {
9050 attributes.reset_is_clear_context();
9051 }
9052 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9053 emit_int8((unsigned char)0xFC);
9054 emit_operand(dst, src, 0);
9055 }
9056
9057 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9058 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9059 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9060 attributes.set_is_evex_instruction();
9061 attributes.set_embedded_opmask_register_specifier(mask);
9062 if (merge) {
9063 attributes.reset_is_clear_context();
9064 }
9065 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9066 emit_int16((unsigned char)0xFD, (0xC0 | encode));
9067 }
9068
9069 void Assembler::evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9070 InstructionMark im(this);
9071 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9072 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9073 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9074 attributes.set_is_evex_instruction();
9075 attributes.set_embedded_opmask_register_specifier(mask);
9076 if (merge) {
9077 attributes.reset_is_clear_context();
9078 }
9079 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9080 emit_int8((unsigned char)0xFD);
9081 emit_operand(dst, src, 0);
9082 }
9083
9084 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9085 assert(VM_Version::supports_evex(), "");
9086 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9087 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9088 attributes.set_is_evex_instruction();
9089 attributes.set_embedded_opmask_register_specifier(mask);
9090 if (merge) {
9091 attributes.reset_is_clear_context();
9092 }
9093 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9094 emit_int16((unsigned char)0xFE, (0xC0 | encode));
9095 }
9096
9097 void Assembler::evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9098 InstructionMark im(this);
9099 assert(VM_Version::supports_evex(), "");
9100 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9101 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9102 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9103 attributes.set_is_evex_instruction();
9104 attributes.set_embedded_opmask_register_specifier(mask);
9105 if (merge) {
9106 attributes.reset_is_clear_context();
9107 }
9108 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9109 emit_int8((unsigned char)0xFE);
9110 emit_operand(dst, src, 0);
9111 }
9112
9113 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9114 assert(VM_Version::supports_evex(), "");
9115 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9116 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9117 attributes.set_is_evex_instruction();
9118 attributes.set_embedded_opmask_register_specifier(mask);
9119 if (merge) {
9120 attributes.reset_is_clear_context();
9121 }
9122 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9123 emit_int16((unsigned char)0xD4, (0xC0 | encode));
9124 }
9125
9126 void Assembler::evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9127 InstructionMark im(this);
9128 assert(VM_Version::supports_evex(), "");
9129 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9130 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9131 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9132 attributes.set_is_evex_instruction();
9133 attributes.set_embedded_opmask_register_specifier(mask);
9134 if (merge) {
9135 attributes.reset_is_clear_context();
9136 }
9137 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9138 emit_int8((unsigned char)0xD4);
9139 emit_operand(dst, src, 0);
9140 }
9141
9142 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9143 assert(VM_Version::supports_evex(), "");
9144 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9145 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9146 attributes.set_is_evex_instruction();
9147 attributes.set_embedded_opmask_register_specifier(mask);
9148 if (merge) {
9149 attributes.reset_is_clear_context();
9150 }
9151 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9152 emit_int16(0x58, (0xC0 | encode));
9153 }
9154
9155 void Assembler::evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9156 InstructionMark im(this);
9157 assert(VM_Version::supports_evex(), "");
9158 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9159 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9160 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9161 attributes.set_is_evex_instruction();
9162 attributes.set_embedded_opmask_register_specifier(mask);
9163 if (merge) {
9164 attributes.reset_is_clear_context();
9165 }
9166 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9167 emit_int8(0x58);
9168 emit_operand(dst, src, 0);
9169 }
9170
9171 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9172 assert(VM_Version::supports_evex(), "");
9173 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9174 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9175 attributes.set_is_evex_instruction();
9176 attributes.set_embedded_opmask_register_specifier(mask);
9177 if (merge) {
9178 attributes.reset_is_clear_context();
9179 }
9180 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9181 emit_int16(0x58, (0xC0 | encode));
9182 }
9183
9184 void Assembler::evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9185 InstructionMark im(this);
9186 assert(VM_Version::supports_evex(), "");
9187 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9188 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9189 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9190 attributes.set_is_evex_instruction();
9191 attributes.set_embedded_opmask_register_specifier(mask);
9192 if (merge) {
9193 attributes.reset_is_clear_context();
9194 }
9195 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9196 emit_int8(0x58);
9197 emit_operand(dst, src, 0);
9198 }
9199
9200 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9201 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9202 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9203 attributes.set_is_evex_instruction();
9204 attributes.set_embedded_opmask_register_specifier(mask);
9205 if (merge) {
9206 attributes.reset_is_clear_context();
9207 }
9208 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9209 emit_int16((unsigned char)0xF8, (0xC0 | encode));
9210 }
9211
9212 void Assembler::evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9213 InstructionMark im(this);
9214 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9215 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9216 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9217 attributes.set_is_evex_instruction();
9218 attributes.set_embedded_opmask_register_specifier(mask);
9219 if (merge) {
9220 attributes.reset_is_clear_context();
9221 }
9222 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9223 emit_int8((unsigned char)0xF8);
9224 emit_operand(dst, src, 0);
9225 }
9226
9227 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9228 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9229 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9230 attributes.set_is_evex_instruction();
9231 attributes.set_embedded_opmask_register_specifier(mask);
9232 if (merge) {
9233 attributes.reset_is_clear_context();
9234 }
9235 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9236 emit_int16((unsigned char)0xF9, (0xC0 | encode));
9237 }
9238
9239 void Assembler::evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9240 InstructionMark im(this);
9241 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9242 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9243 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9244 attributes.set_is_evex_instruction();
9245 attributes.set_embedded_opmask_register_specifier(mask);
9246 if (merge) {
9247 attributes.reset_is_clear_context();
9248 }
9249 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9250 emit_int8((unsigned char)0xF9);
9251 emit_operand(dst, src, 0);
9252 }
9253
9254 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9255 assert(VM_Version::supports_evex(), "");
9256 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9257 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9258 attributes.set_is_evex_instruction();
9259 attributes.set_embedded_opmask_register_specifier(mask);
9260 if (merge) {
9261 attributes.reset_is_clear_context();
9262 }
9263 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9264 emit_int16((unsigned char)0xFA, (0xC0 | encode));
9265 }
9266
9267 void Assembler::evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9268 InstructionMark im(this);
9269 assert(VM_Version::supports_evex(), "");
9270 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9271 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9272 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9273 attributes.set_is_evex_instruction();
9274 attributes.set_embedded_opmask_register_specifier(mask);
9275 if (merge) {
9276 attributes.reset_is_clear_context();
9277 }
9278 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9279 emit_int8((unsigned char)0xFA);
9280 emit_operand(dst, src, 0);
9281 }
9282
9283 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9284 assert(VM_Version::supports_evex(), "");
9285 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9286 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9287 attributes.set_is_evex_instruction();
9288 attributes.set_embedded_opmask_register_specifier(mask);
9289 if (merge) {
9290 attributes.reset_is_clear_context();
9291 }
9292 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9293 emit_int16((unsigned char)0xFB, (0xC0 | encode));
9294 }
9295
9296 void Assembler::evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9297 InstructionMark im(this);
9298 assert(VM_Version::supports_evex(), "");
9299 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9300 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9301 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9302 attributes.set_is_evex_instruction();
9303 attributes.set_embedded_opmask_register_specifier(mask);
9304 if (merge) {
9305 attributes.reset_is_clear_context();
9306 }
9307 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9308 emit_int8((unsigned char)0xFB);
9309 emit_operand(dst, src, 0);
9310 }
9311
9312 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9313 assert(VM_Version::supports_evex(), "");
9314 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9315 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9316 attributes.set_is_evex_instruction();
9317 attributes.set_embedded_opmask_register_specifier(mask);
9318 if (merge) {
9319 attributes.reset_is_clear_context();
9320 }
9321 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9322 emit_int16(0x5C, (0xC0 | encode));
9323 }
9324
9325 void Assembler::evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9326 InstructionMark im(this);
9327 assert(VM_Version::supports_evex(), "");
9328 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9329 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9330 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9331 attributes.set_is_evex_instruction();
9332 attributes.set_embedded_opmask_register_specifier(mask);
9333 if (merge) {
9334 attributes.reset_is_clear_context();
9335 }
9336 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9337 emit_int8(0x5C);
9338 emit_operand(dst, src, 0);
9339 }
9340
9341 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9342 assert(VM_Version::supports_evex(), "");
9343 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9344 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9345 attributes.set_is_evex_instruction();
9346 attributes.set_embedded_opmask_register_specifier(mask);
9347 if (merge) {
9348 attributes.reset_is_clear_context();
9349 }
9350 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9351 emit_int16(0x5C, (0xC0 | encode));
9352 }
9353
9354 void Assembler::evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9355 InstructionMark im(this);
9356 assert(VM_Version::supports_evex(), "");
9357 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9358 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9359 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9360 attributes.set_is_evex_instruction();
9361 attributes.set_embedded_opmask_register_specifier(mask);
9362 if (merge) {
9363 attributes.reset_is_clear_context();
9364 }
9365 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9366 emit_int8(0x5C);
9367 emit_operand(dst, src, 0);
9368 }
9369
9370 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9371 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9372 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9373 attributes.set_is_evex_instruction();
9374 attributes.set_embedded_opmask_register_specifier(mask);
9375 if (merge) {
9376 attributes.reset_is_clear_context();
9377 }
9378 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9379 emit_int16((unsigned char)0xD5, (0xC0 | encode));
9380 }
9381
9382 void Assembler::evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9383 InstructionMark im(this);
9384 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9385 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9386 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9387 attributes.set_is_evex_instruction();
9388 attributes.set_embedded_opmask_register_specifier(mask);
9389 if (merge) {
9390 attributes.reset_is_clear_context();
9391 }
9392 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9393 emit_int8((unsigned char)0xD5);
9394 emit_operand(dst, src, 0);
9395 }
9396
9397 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9398 assert(VM_Version::supports_evex(), "");
9399 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9400 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9401 attributes.set_is_evex_instruction();
9402 attributes.set_embedded_opmask_register_specifier(mask);
9403 if (merge) {
9404 attributes.reset_is_clear_context();
9405 }
9406 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9407 emit_int16(0x40, (0xC0 | encode));
9408 }
9409
9410 void Assembler::evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9411 InstructionMark im(this);
9412 assert(VM_Version::supports_evex(), "");
9413 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9414 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9415 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9416 attributes.set_is_evex_instruction();
9417 attributes.set_embedded_opmask_register_specifier(mask);
9418 if (merge) {
9419 attributes.reset_is_clear_context();
9420 }
9421 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9422 emit_int8(0x40);
9423 emit_operand(dst, src, 0);
9424 }
9425
9426 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9427 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9428 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9429 attributes.set_is_evex_instruction();
9430 attributes.set_embedded_opmask_register_specifier(mask);
9431 if (merge) {
9432 attributes.reset_is_clear_context();
9433 }
9434 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9435 emit_int16(0x40, (0xC0 | encode));
9436 }
9437
9438 void Assembler::evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9439 InstructionMark im(this);
9440 assert(VM_Version::supports_avx512dq() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9441 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9442 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9443 attributes.set_is_evex_instruction();
9444 attributes.set_embedded_opmask_register_specifier(mask);
9445 if (merge) {
9446 attributes.reset_is_clear_context();
9447 }
9448 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9449 emit_int8(0x40);
9450 emit_operand(dst, src, 0);
9451 }
9452
9453 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9454 assert(VM_Version::supports_evex(), "");
9455 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9456 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9457 attributes.set_is_evex_instruction();
9458 attributes.set_embedded_opmask_register_specifier(mask);
9459 if (merge) {
9460 attributes.reset_is_clear_context();
9461 }
9462 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9463 emit_int16(0x59, (0xC0 | encode));
9464 }
9465
9466 void Assembler::evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9467 InstructionMark im(this);
9468 assert(VM_Version::supports_evex(), "");
9469 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9470 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9471 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9472 attributes.set_is_evex_instruction();
9473 attributes.set_embedded_opmask_register_specifier(mask);
9474 if (merge) {
9475 attributes.reset_is_clear_context();
9476 }
9477 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9478 emit_int8(0x59);
9479 emit_operand(dst, src, 0);
9480 }
9481
9482 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9483 assert(VM_Version::supports_evex(), "");
9484 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9485 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9486 attributes.set_is_evex_instruction();
9487 attributes.set_embedded_opmask_register_specifier(mask);
9488 if (merge) {
9489 attributes.reset_is_clear_context();
9490 }
9491 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9492 emit_int16(0x59, (0xC0 | encode));
9493 }
9494
9495 void Assembler::evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9496 InstructionMark im(this);
9497 assert(VM_Version::supports_evex(), "");
9498 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9499 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9500 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9501 attributes.set_is_evex_instruction();
9502 attributes.set_embedded_opmask_register_specifier(mask);
9503 if (merge) {
9504 attributes.reset_is_clear_context();
9505 }
9506 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9507 emit_int8(0x59);
9508 emit_operand(dst, src, 0);
9509 }
9510
9511 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9512 assert(VM_Version::supports_evex(), "");
9513 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9514 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9515 attributes.set_is_evex_instruction();
9516 attributes.set_embedded_opmask_register_specifier(mask);
9517 if (merge) {
9518 attributes.reset_is_clear_context();
9519 }
9520 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9521 emit_int16(0x51, (0xC0 | encode));
9522 }
9523
9524 void Assembler::evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9525 InstructionMark im(this);
9526 assert(VM_Version::supports_evex(), "");
9527 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9528 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9529 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9530 attributes.set_is_evex_instruction();
9531 attributes.set_embedded_opmask_register_specifier(mask);
9532 if (merge) {
9533 attributes.reset_is_clear_context();
9534 }
9535 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9536 emit_int8(0x51);
9537 emit_operand(dst, src, 0);
9538 }
9539
9540 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9541 assert(VM_Version::supports_evex(), "");
9542 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9543 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9544 attributes.set_is_evex_instruction();
9545 attributes.set_embedded_opmask_register_specifier(mask);
9546 if (merge) {
9547 attributes.reset_is_clear_context();
9548 }
9549 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9550 emit_int16(0x51, (0xC0 | encode));
9551 }
9552
9553 void Assembler::evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9554 InstructionMark im(this);
9555 assert(VM_Version::supports_evex(), "");
9556 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9557 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9558 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9559 attributes.set_is_evex_instruction();
9560 attributes.set_embedded_opmask_register_specifier(mask);
9561 if (merge) {
9562 attributes.reset_is_clear_context();
9563 }
9564 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9565 emit_int8(0x51);
9566 emit_operand(dst, src, 0);
9567 }
9568
9569
9570 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9571 assert(VM_Version::supports_evex(), "");
9572 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9573 InstructionAttr attributes(vector_len,/* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9574 attributes.set_is_evex_instruction();
9575 attributes.set_embedded_opmask_register_specifier(mask);
9576 if (merge) {
9577 attributes.reset_is_clear_context();
9578 }
9579 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9580 emit_int16(0x5E, (0xC0 | encode));
9581 }
9582
9583 void Assembler::evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9584 InstructionMark im(this);
9585 assert(VM_Version::supports_evex(), "");
9586 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9587 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9588 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9589 attributes.set_is_evex_instruction();
9590 attributes.set_embedded_opmask_register_specifier(mask);
9591 if (merge) {
9592 attributes.reset_is_clear_context();
9593 }
9594 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
9595 emit_int8(0x5E);
9596 emit_operand(dst, src, 0);
9597 }
9598
9599 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9600 assert(VM_Version::supports_evex(), "");
9601 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9602 InstructionAttr attributes(vector_len,/* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9603 attributes.set_is_evex_instruction();
9604 attributes.set_embedded_opmask_register_specifier(mask);
9605 if (merge) {
9606 attributes.reset_is_clear_context();
9607 }
9608 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9609 emit_int16(0x5E, (0xC0 | encode));
9610 }
9611
9612 void Assembler::evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9613 InstructionMark im(this);
9614 assert(VM_Version::supports_evex(), "");
9615 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9616 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9617 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9618 attributes.set_is_evex_instruction();
9619 attributes.set_embedded_opmask_register_specifier(mask);
9620 if (merge) {
9621 attributes.reset_is_clear_context();
9622 }
9623 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9624 emit_int8(0x5E);
9625 emit_operand(dst, src, 0);
9626 }
9627
9628 void Assembler::evdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src, EvexRoundPrefix rmode) {
9629 assert(VM_Version::supports_evex(), "");
9630 InstructionAttr attributes(rmode, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9631 attributes.set_extended_context();
9632 attributes.set_is_evex_instruction();
9633 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9634 emit_int16(0x5E, (0xC0 | encode));
9635 }
9636
9637 void Assembler::evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9638 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9639 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9640 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9641 attributes.set_is_evex_instruction();
9642 attributes.set_embedded_opmask_register_specifier(mask);
9643 if (merge) {
9644 attributes.reset_is_clear_context();
9645 }
9646 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9647 emit_int16(0x1C, (0xC0 | encode));
9648 }
9649
9650
9651 void Assembler::evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9652 InstructionMark im(this);
9653 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9654 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9655 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9656 attributes.set_is_evex_instruction();
9657 attributes.set_embedded_opmask_register_specifier(mask);
9658 if (merge) {
9659 attributes.reset_is_clear_context();
9660 }
9661 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9662 emit_int8(0x1C);
9663 emit_operand(dst, src, 0);
9664 }
9665
9666 void Assembler::evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9667 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9668 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9669 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9670 attributes.set_is_evex_instruction();
9671 attributes.set_embedded_opmask_register_specifier(mask);
9672 if (merge) {
9673 attributes.reset_is_clear_context();
9674 }
9675 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9676 emit_int16(0x1D, (0xC0 | encode));
9677 }
9678
9679
9680 void Assembler::evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9681 InstructionMark im(this);
9682 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9683 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9684 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9685 attributes.set_is_evex_instruction();
9686 attributes.set_embedded_opmask_register_specifier(mask);
9687 if (merge) {
9688 attributes.reset_is_clear_context();
9689 }
9690 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9691 emit_int8(0x1D);
9692 emit_operand(dst, src, 0);
9693 }
9694
9695 void Assembler::evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9696 assert(VM_Version::supports_evex(), "");
9697 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9698 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9699 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9700 attributes.set_is_evex_instruction();
9701 attributes.set_embedded_opmask_register_specifier(mask);
9702 if (merge) {
9703 attributes.reset_is_clear_context();
9704 }
9705 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9706 emit_int16(0x1E, (0xC0 | encode));
9707 }
9708
9709
9710 void Assembler::evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9711 InstructionMark im(this);
9712 assert(VM_Version::supports_evex(), "");
9713 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9714 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9715 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9716 attributes.set_is_evex_instruction();
9717 attributes.set_embedded_opmask_register_specifier(mask);
9718 if (merge) {
9719 attributes.reset_is_clear_context();
9720 }
9721 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9722 emit_int8(0x1E);
9723 emit_operand(dst, src, 0);
9724 }
9725
9726 void Assembler::evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
9727 assert(VM_Version::supports_evex(), "");
9728 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9729 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9730 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9731 attributes.set_is_evex_instruction();
9732 attributes.set_embedded_opmask_register_specifier(mask);
9733 if (merge) {
9734 attributes.reset_is_clear_context();
9735 }
9736 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9737 emit_int16(0x1F, (0xC0 | encode));
9738 }
9739
9740
9741 void Assembler::evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
9742 InstructionMark im(this);
9743 assert(VM_Version::supports_evex(), "");
9744 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9745 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9746 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9747 attributes.set_is_evex_instruction();
9748 attributes.set_embedded_opmask_register_specifier(mask);
9749 if (merge) {
9750 attributes.reset_is_clear_context();
9751 }
9752 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9753 emit_int8(0x1F);
9754 emit_operand(dst, src, 0);
9755 }
9756
9757 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9758 assert(VM_Version::supports_evex(), "");
9759 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9760 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9761 attributes.set_is_evex_instruction();
9762 attributes.set_embedded_opmask_register_specifier(mask);
9763 if (merge) {
9764 attributes.reset_is_clear_context();
9765 }
9766 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9767 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9768 }
9769
9770 void Assembler::evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9771 InstructionMark im(this);
9772 assert(VM_Version::supports_evex(), "");
9773 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9774 InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9775 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9776 attributes.set_is_evex_instruction();
9777 attributes.set_embedded_opmask_register_specifier(mask);
9778 if (merge) {
9779 attributes.reset_is_clear_context();
9780 }
9781 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9782 emit_int8((unsigned char)0xA8);
9783 emit_operand(dst, src, 0);
9784 }
9785
9786 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9787 assert(VM_Version::supports_evex(), "");
9788 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9789 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9790 attributes.set_is_evex_instruction();
9791 attributes.set_embedded_opmask_register_specifier(mask);
9792 if (merge) {
9793 attributes.reset_is_clear_context();
9794 }
9795 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9796 emit_int16((unsigned char)0xA8, (0xC0 | encode));
9797 }
9798
9799 void Assembler::evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9800 InstructionMark im(this);
9801 assert(VM_Version::supports_evex(), "");
9802 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9803 InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
9804 attributes.set_address_attributes(/* tuple_type */ EVEX_FV,/* input_size_in_bits */ EVEX_32bit);
9805 attributes.set_is_evex_instruction();
9806 attributes.set_embedded_opmask_register_specifier(mask);
9807 if (merge) {
9808 attributes.reset_is_clear_context();
9809 }
9810 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9811 emit_int8((unsigned char)0xA8);
9812 emit_operand(dst, src, 0);
9813 }
9814
9815 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9816 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9817 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9818 attributes.set_is_evex_instruction();
9819 attributes.set_embedded_opmask_register_specifier(mask);
9820 if (merge) {
9821 attributes.reset_is_clear_context();
9822 }
9823 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9824 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9825 }
9826
9827 void Assembler::evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9828 assert(VM_Version::supports_avx512_vbmi() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9829 InstructionMark im(this);
9830 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9831 attributes.set_is_evex_instruction();
9832 attributes.set_embedded_opmask_register_specifier(mask);
9833 if (merge) {
9834 attributes.reset_is_clear_context();
9835 }
9836 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9837 emit_int8((unsigned char)0x8D);
9838 emit_operand(dst, src, 0);
9839 }
9840
9841 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9842 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9843 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9844 attributes.set_is_evex_instruction();
9845 attributes.set_embedded_opmask_register_specifier(mask);
9846 if (merge) {
9847 attributes.reset_is_clear_context();
9848 }
9849 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9850 emit_int16((unsigned char)0x8D, (0xC0 | encode));
9851 }
9852
9853 void Assembler::evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9854 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9855 InstructionMark im(this);
9856 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9857 attributes.set_is_evex_instruction();
9858 attributes.set_embedded_opmask_register_specifier(mask);
9859 if (merge) {
9860 attributes.reset_is_clear_context();
9861 }
9862 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9863 emit_int8((unsigned char)0x8D);
9864 emit_operand(dst, src, 0);
9865 }
9866
9867 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9868 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9869 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9870 attributes.set_is_evex_instruction();
9871 attributes.set_embedded_opmask_register_specifier(mask);
9872 if (merge) {
9873 attributes.reset_is_clear_context();
9874 }
9875 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9876 emit_int16(0x36, (0xC0 | encode));
9877 }
9878
9879 void Assembler::evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9880 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9881 InstructionMark im(this);
9882 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9883 attributes.set_is_evex_instruction();
9884 attributes.set_embedded_opmask_register_specifier(mask);
9885 if (merge) {
9886 attributes.reset_is_clear_context();
9887 }
9888 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9889 emit_int8(0x36);
9890 emit_operand(dst, src, 0);
9891 }
9892
9893 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
9894 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9895 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9896 attributes.set_is_evex_instruction();
9897 attributes.set_embedded_opmask_register_specifier(mask);
9898 if (merge) {
9899 attributes.reset_is_clear_context();
9900 }
9901 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9902 emit_int16(0x36, (0xC0 | encode));
9903 }
9904
9905 void Assembler::evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
9906 assert(VM_Version::supports_evex() && vector_len > AVX_128bit, "");
9907 InstructionMark im(this);
9908 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9909 attributes.set_is_evex_instruction();
9910 attributes.set_embedded_opmask_register_specifier(mask);
9911 if (merge) {
9912 attributes.reset_is_clear_context();
9913 }
9914 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
9915 emit_int8(0x36);
9916 emit_operand(dst, src, 0);
9917 }
9918
9919 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9920 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9921 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9922 attributes.set_is_evex_instruction();
9923 attributes.set_embedded_opmask_register_specifier(mask);
9924 if (merge) {
9925 attributes.reset_is_clear_context();
9926 }
9927 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9928 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
9929 }
9930
9931 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9932 assert(VM_Version::supports_evex(), "");
9933 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9934 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9935 attributes.set_is_evex_instruction();
9936 attributes.set_embedded_opmask_register_specifier(mask);
9937 if (merge) {
9938 attributes.reset_is_clear_context();
9939 }
9940 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9941 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
9942 }
9943
9944 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9945 assert(VM_Version::supports_evex(), "");
9946 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9947 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9948 attributes.set_is_evex_instruction();
9949 attributes.set_embedded_opmask_register_specifier(mask);
9950 if (merge) {
9951 attributes.reset_is_clear_context();
9952 }
9953 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9954 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
9955 }
9956
9957 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9958 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9959 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9960 attributes.set_is_evex_instruction();
9961 attributes.set_embedded_opmask_register_specifier(mask);
9962 if (merge) {
9963 attributes.reset_is_clear_context();
9964 }
9965 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9966 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
9967 }
9968
9969 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9970 assert(VM_Version::supports_evex(), "");
9971 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9972 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9973 attributes.set_is_evex_instruction();
9974 attributes.set_embedded_opmask_register_specifier(mask);
9975 if (merge) {
9976 attributes.reset_is_clear_context();
9977 }
9978 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9979 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
9980 }
9981
9982 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9983 assert(VM_Version::supports_evex(), "");
9984 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
9985 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9986 attributes.set_is_evex_instruction();
9987 attributes.set_embedded_opmask_register_specifier(mask);
9988 if (merge) {
9989 attributes.reset_is_clear_context();
9990 }
9991 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9992 emit_int24(0x73, (0xC0 | encode), shift & 0xFF);
9993 }
9994
9995 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
9996 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
9997 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
9998 attributes.set_is_evex_instruction();
9999 attributes.set_embedded_opmask_register_specifier(mask);
10000 if (merge) {
10001 attributes.reset_is_clear_context();
10002 }
10003 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10004 emit_int24(0x71, (0xC0 | encode), shift & 0xFF);
10005 }
10006
10007 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10008 assert(VM_Version::supports_evex(), "");
10009 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10010 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10011 attributes.set_is_evex_instruction();
10012 attributes.set_embedded_opmask_register_specifier(mask);
10013 if (merge) {
10014 attributes.reset_is_clear_context();
10015 }
10016 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10017 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10018 }
10019
10020 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
10021 assert(VM_Version::supports_evex(), "");
10022 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10023 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10024 attributes.set_is_evex_instruction();
10025 attributes.set_embedded_opmask_register_specifier(mask);
10026 if (merge) {
10027 attributes.reset_is_clear_context();
10028 }
10029 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10030 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
10031 }
10032
10033 void Assembler::evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10034 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10035 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10036 attributes.set_is_evex_instruction();
10037 attributes.set_embedded_opmask_register_specifier(mask);
10038 if (merge) {
10039 attributes.reset_is_clear_context();
10040 }
10041 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10042 emit_int16((unsigned char)0xF1, (0xC0 | encode));
10043 }
10044
10045 void Assembler::evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10046 assert(VM_Version::supports_evex(), "");
10047 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10048 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10049 attributes.set_is_evex_instruction();
10050 attributes.set_embedded_opmask_register_specifier(mask);
10051 if (merge) {
10052 attributes.reset_is_clear_context();
10053 }
10054 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10055 emit_int16((unsigned char)0xF2, (0xC0 | encode));
10056 }
10057
10058 void Assembler::evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10059 assert(VM_Version::supports_evex(), "");
10060 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10061 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10062 attributes.set_is_evex_instruction();
10063 attributes.set_embedded_opmask_register_specifier(mask);
10064 if (merge) {
10065 attributes.reset_is_clear_context();
10066 }
10067 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10068 emit_int16((unsigned char)0xF3, (0xC0 | encode));
10069 }
10070
10071 void Assembler::evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10072 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10073 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10074 attributes.set_is_evex_instruction();
10075 attributes.set_embedded_opmask_register_specifier(mask);
10076 if (merge) {
10077 attributes.reset_is_clear_context();
10078 }
10079 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10080 emit_int16((unsigned char)0xD1, (0xC0 | encode));
10081 }
10082
10083 void Assembler::evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10084 assert(VM_Version::supports_evex(), "");
10085 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10086 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10087 attributes.set_is_evex_instruction();
10088 attributes.set_embedded_opmask_register_specifier(mask);
10089 if (merge) {
10090 attributes.reset_is_clear_context();
10091 }
10092 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10093 emit_int16((unsigned char)0xD2, (0xC0 | encode));
10094 }
10095
10096 void Assembler::evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10097 assert(VM_Version::supports_evex(), "");
10098 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10099 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10100 attributes.set_is_evex_instruction();
10101 attributes.set_embedded_opmask_register_specifier(mask);
10102 if (merge) {
10103 attributes.reset_is_clear_context();
10104 }
10105 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10106 emit_int16((unsigned char)0xD3, (0xC0 | encode));
10107 }
10108
10109 void Assembler::evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10110 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10111 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10112 attributes.set_is_evex_instruction();
10113 attributes.set_embedded_opmask_register_specifier(mask);
10114 if (merge) {
10115 attributes.reset_is_clear_context();
10116 }
10117 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10118 emit_int16((unsigned char)0xE1, (0xC0 | encode));
10119 }
10120
10121 void Assembler::evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10122 assert(VM_Version::supports_evex(), "");
10123 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10125 attributes.set_is_evex_instruction();
10126 attributes.set_embedded_opmask_register_specifier(mask);
10127 if (merge) {
10128 attributes.reset_is_clear_context();
10129 }
10130 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10131 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10132 }
10133
10134 void Assembler::evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10135 assert(VM_Version::supports_evex(), "");
10136 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10137 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10138 attributes.set_is_evex_instruction();
10139 attributes.set_embedded_opmask_register_specifier(mask);
10140 if (merge) {
10141 attributes.reset_is_clear_context();
10142 }
10143 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10144 emit_int16((unsigned char)0xE2, (0xC0 | encode));
10145 }
10146
10147 void Assembler::evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10148 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10149 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10150 attributes.set_is_evex_instruction();
10151 attributes.set_embedded_opmask_register_specifier(mask);
10152 if (merge) {
10153 attributes.reset_is_clear_context();
10154 }
10155 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10156 emit_int16(0x12, (0xC0 | encode));
10157 }
10158
10159 void Assembler::evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10160 assert(VM_Version::supports_evex(), "");
10161 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10162 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10163 attributes.set_is_evex_instruction();
10164 attributes.set_embedded_opmask_register_specifier(mask);
10165 if (merge) {
10166 attributes.reset_is_clear_context();
10167 }
10168 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10169 emit_int16(0x47, (0xC0 | encode));
10170 }
10171
10172 void Assembler::evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10173 assert(VM_Version::supports_evex(), "");
10174 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10175 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10176 attributes.set_is_evex_instruction();
10177 attributes.set_embedded_opmask_register_specifier(mask);
10178 if (merge) {
10179 attributes.reset_is_clear_context();
10180 }
10181 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10182 emit_int16(0x47, (0xC0 | encode));
10183 }
10184
10185 void Assembler::evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10186 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10187 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10188 attributes.set_is_evex_instruction();
10189 attributes.set_embedded_opmask_register_specifier(mask);
10190 if (merge) {
10191 attributes.reset_is_clear_context();
10192 }
10193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10194 emit_int16(0x10, (0xC0 | encode));
10195 }
10196
10197 void Assembler::evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10198 assert(VM_Version::supports_evex(), "");
10199 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10200 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10201 attributes.set_is_evex_instruction();
10202 attributes.set_embedded_opmask_register_specifier(mask);
10203 if (merge) {
10204 attributes.reset_is_clear_context();
10205 }
10206 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10207 emit_int16(0x45, (0xC0 | encode));
10208 }
10209
10210 void Assembler::evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10211 assert(VM_Version::supports_evex(), "");
10212 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10213 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10214 attributes.set_is_evex_instruction();
10215 attributes.set_embedded_opmask_register_specifier(mask);
10216 if (merge) {
10217 attributes.reset_is_clear_context();
10218 }
10219 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10220 emit_int16(0x45, (0xC0 | encode));
10221 }
10222
10223 void Assembler::evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10224 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10225 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10226 attributes.set_is_evex_instruction();
10227 attributes.set_embedded_opmask_register_specifier(mask);
10228 if (merge) {
10229 attributes.reset_is_clear_context();
10230 }
10231 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10232 emit_int16(0x11, (0xC0 | encode));
10233 }
10234
10235 void Assembler::evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10236 assert(VM_Version::supports_evex(), "");
10237 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10238 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10239 attributes.set_is_evex_instruction();
10240 attributes.set_embedded_opmask_register_specifier(mask);
10241 if (merge) {
10242 attributes.reset_is_clear_context();
10243 }
10244 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10245 emit_int16(0x46, (0xC0 | encode));
10246 }
10247
10248 void Assembler::evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10249 assert(VM_Version::supports_evex(), "");
10250 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10251 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10252 attributes.set_is_evex_instruction();
10253 attributes.set_embedded_opmask_register_specifier(mask);
10254 if (merge) {
10255 attributes.reset_is_clear_context();
10256 }
10257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10258 emit_int16(0x46, (0xC0 | encode));
10259 }
10260
10261 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10262 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10263 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10264 attributes.set_is_evex_instruction();
10265 attributes.set_embedded_opmask_register_specifier(mask);
10266 if (merge) {
10267 attributes.reset_is_clear_context();
10268 }
10269 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10270 emit_int16(0x38, (0xC0 | encode));
10271 }
10272
10273 void Assembler::evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10274 assert(VM_Version::supports_avx512bw(), "");
10275 InstructionMark im(this);
10276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10277 attributes.set_is_evex_instruction();
10278 attributes.set_embedded_opmask_register_specifier(mask);
10279 if (merge) {
10280 attributes.reset_is_clear_context();
10281 }
10282 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10283 emit_int8(0x38);
10284 emit_operand(dst, src, 0);
10285 }
10286
10287 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10288 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10289 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10290 attributes.set_is_evex_instruction();
10291 attributes.set_embedded_opmask_register_specifier(mask);
10292 if (merge) {
10293 attributes.reset_is_clear_context();
10294 }
10295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10296 emit_int16((unsigned char)0xEA, (0xC0 | encode));
10297 }
10298
10299 void Assembler::evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10300 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10301 InstructionMark im(this);
10302 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10303 attributes.set_is_evex_instruction();
10304 attributes.set_embedded_opmask_register_specifier(mask);
10305 if (merge) {
10306 attributes.reset_is_clear_context();
10307 }
10308 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10309 emit_int8((unsigned char)0xEA);
10310 emit_operand(dst, src, 0);
10311 }
10312
10313 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10314 assert(VM_Version::supports_evex(), "");
10315 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10316 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10317 attributes.set_is_evex_instruction();
10318 attributes.set_embedded_opmask_register_specifier(mask);
10319 if (merge) {
10320 attributes.reset_is_clear_context();
10321 }
10322 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10323 emit_int16(0x39, (0xC0 | encode));
10324 }
10325
10326 void Assembler::evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10327 assert(VM_Version::supports_evex(), "");
10328 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10329 InstructionMark im(this);
10330 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10331 attributes.set_is_evex_instruction();
10332 attributes.set_embedded_opmask_register_specifier(mask);
10333 if (merge) {
10334 attributes.reset_is_clear_context();
10335 }
10336 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10337 emit_int8(0x39);
10338 emit_operand(dst, src, 0);
10339 }
10340
10341 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10342 assert(VM_Version::supports_evex(), "");
10343 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10344 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10345 attributes.set_is_evex_instruction();
10346 attributes.set_embedded_opmask_register_specifier(mask);
10347 if (merge) {
10348 attributes.reset_is_clear_context();
10349 }
10350 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10351 emit_int16(0x39, (0xC0 | encode));
10352 }
10353
10354 void Assembler::evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10355 assert(VM_Version::supports_evex(), "");
10356 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10357 InstructionMark im(this);
10358 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10359 attributes.set_is_evex_instruction();
10360 attributes.set_embedded_opmask_register_specifier(mask);
10361 if (merge) {
10362 attributes.reset_is_clear_context();
10363 }
10364 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10365 emit_int8(0x39);
10366 emit_operand(dst, src, 0);
10367 }
10368
10369
10370 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10371 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10373 attributes.set_is_evex_instruction();
10374 attributes.set_embedded_opmask_register_specifier(mask);
10375 if (merge) {
10376 attributes.reset_is_clear_context();
10377 }
10378 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10379 emit_int16(0x3C, (0xC0 | encode));
10380 }
10381
10382 void Assembler::evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10383 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10384 InstructionMark im(this);
10385 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10386 attributes.set_is_evex_instruction();
10387 attributes.set_embedded_opmask_register_specifier(mask);
10388 if (merge) {
10389 attributes.reset_is_clear_context();
10390 }
10391 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10392 emit_int8(0x3C);
10393 emit_operand(dst, src, 0);
10394 }
10395
10396 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10397 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10398 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10399 attributes.set_is_evex_instruction();
10400 attributes.set_embedded_opmask_register_specifier(mask);
10401 if (merge) {
10402 attributes.reset_is_clear_context();
10403 }
10404 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10405 emit_int16((unsigned char)0xEE, (0xC0 | encode));
10406 }
10407
10408 void Assembler::evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10409 assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
10410 InstructionMark im(this);
10411 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10412 attributes.set_is_evex_instruction();
10413 attributes.set_embedded_opmask_register_specifier(mask);
10414 if (merge) {
10415 attributes.reset_is_clear_context();
10416 }
10417 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
10418 emit_int8((unsigned char)0xEE);
10419 emit_operand(dst, src, 0);
10420 }
10421
10422 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10423 assert(VM_Version::supports_evex(), "");
10424 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10425 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10426 attributes.set_is_evex_instruction();
10427 attributes.set_embedded_opmask_register_specifier(mask);
10428 if (merge) {
10429 attributes.reset_is_clear_context();
10430 }
10431 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10432 emit_int16(0x3D, (0xC0 | encode));
10433 }
10434
10435 void Assembler::evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10436 assert(VM_Version::supports_evex(), "");
10437 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10438 InstructionMark im(this);
10439 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10440 attributes.set_is_evex_instruction();
10441 attributes.set_embedded_opmask_register_specifier(mask);
10442 if (merge) {
10443 attributes.reset_is_clear_context();
10444 }
10445 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10446 emit_int8(0x3D);
10447 emit_operand(dst, src, 0);
10448 }
10449
10450 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
10451 assert(VM_Version::supports_evex(), "");
10452 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10453 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10454 attributes.set_is_evex_instruction();
10455 attributes.set_embedded_opmask_register_specifier(mask);
10456 if (merge) {
10457 attributes.reset_is_clear_context();
10458 }
10459 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10460 emit_int16(0x3D, (0xC0 | encode));
10461 }
10462
10463 void Assembler::evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
10464 assert(VM_Version::supports_evex(), "");
10465 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
10466 InstructionMark im(this);
10467 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10468 attributes.set_is_evex_instruction();
10469 attributes.set_embedded_opmask_register_specifier(mask);
10470 if (merge) {
10471 attributes.reset_is_clear_context();
10472 }
10473 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10474 emit_int8(0x3D);
10475 emit_operand(dst, src, 0);
10476 }
10477
10478 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10479 assert(VM_Version::supports_evex(), "requires EVEX support");
10480 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10481 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10482 attributes.set_is_evex_instruction();
10483 attributes.set_embedded_opmask_register_specifier(mask);
10484 if (merge) {
10485 attributes.reset_is_clear_context();
10486 }
10487 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10488 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10489 }
10490
10491 void Assembler::evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10492 assert(VM_Version::supports_evex(), "requires EVEX support");
10493 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10494 assert(dst != xnoreg, "sanity");
10495 InstructionMark im(this);
10496 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10497 attributes.set_is_evex_instruction();
10498 attributes.set_embedded_opmask_register_specifier(mask);
10499 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10500 if (merge) {
10501 attributes.reset_is_clear_context();
10502 }
10503 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10504 emit_int8(0x25);
10505 emit_operand(dst, src3, 1);
10506 emit_int8(imm8);
10507 }
10508
10509 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len) {
10510 assert(VM_Version::supports_evex(), "requires EVEX support");
10511 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10512 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10513 attributes.set_is_evex_instruction();
10514 attributes.set_embedded_opmask_register_specifier(mask);
10515 if (merge) {
10516 attributes.reset_is_clear_context();
10517 }
10518 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10519 emit_int24(0x25, (unsigned char)(0xC0 | encode), imm8);
10520 }
10521
10522 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10523 assert(VM_Version::supports_evex(), "requires EVEX support");
10524 assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10525 assert(dst != xnoreg, "sanity");
10526 InstructionMark im(this);
10527 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10528 attributes.set_is_evex_instruction();
10529 attributes.set_embedded_opmask_register_specifier(mask);
10530 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10531 if (merge) {
10532 attributes.reset_is_clear_context();
10533 }
10534 vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10535 emit_int8(0x25);
10536 emit_operand(dst, src3, 1);
10537 emit_int8(imm8);
10538 }
10539
10540 void Assembler::gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8) {
10541 assert(VM_Version::supports_gfni(), "");
10542 assert(VM_Version::supports_sse(), "");
10543 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
10544 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10545 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10546 }
10547
10548 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
10549 assert(VM_Version::supports_gfni(), "requires GFNI support");
10550 assert(VM_Version::supports_sse(), "");
10551 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10552 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10553 emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10554 }
10555
10556 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10557 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
10558 assert(UseAVX >= 2, "");
10559 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10560 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10561 emit_int16(0x58, (0xC0 | encode));
10562 }
10563
10564 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
10565 assert(VM_Version::supports_avx2(), "");
10566 assert(dst != xnoreg, "sanity");
10567 InstructionMark im(this);
10568 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10569 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10570 // swap src<->dst for encoding
10571 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10572 emit_int8(0x58);
10573 emit_operand(dst, src, 0);
10574 }
10575
10576 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10577 void Assembler::vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
10578 assert(VM_Version::supports_avx2(), "");
10579 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10580 attributes.set_rex_vex_w_reverted();
10581 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10582 emit_int16(0x59, (0xC0 | encode));
10583 }
10584
10585 void Assembler::vpbroadcastq(XMMRegister dst, Address src, int vector_len) {
10586 assert(VM_Version::supports_avx2(), "");
10587 assert(dst != xnoreg, "sanity");
10588 InstructionMark im(this);
10589 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10590 attributes.set_rex_vex_w_reverted();
10591 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10592 // swap src<->dst for encoding
10593 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10594 emit_int8(0x59);
10595 emit_operand(dst, src, 0);
10596 }
10597
10598 void Assembler::evbroadcasti32x4(XMMRegister dst, Address src, int vector_len) {
10599 assert(vector_len != Assembler::AVX_128bit, "");
10600 assert(VM_Version::supports_evex(), "");
10601 assert(dst != xnoreg, "sanity");
10602 InstructionMark im(this);
10603 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10604 attributes.set_rex_vex_w_reverted();
10605 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10606 // swap src<->dst for encoding
10607 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10608 emit_int8(0x5A);
10609 emit_operand(dst, src, 0);
10610 }
10611
10612 void Assembler::evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len) {
10613 assert(vector_len != Assembler::AVX_128bit, "");
10614 assert(VM_Version::supports_avx512dq(), "");
10615 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10616 attributes.set_rex_vex_w_reverted();
10617 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10618 emit_int16(0x5A, (0xC0 | encode));
10619 }
10620
10621 void Assembler::evbroadcasti64x2(XMMRegister dst, Address src, int vector_len) {
10622 assert(vector_len != Assembler::AVX_128bit, "");
10623 assert(VM_Version::supports_avx512dq(), "");
10624 assert(dst != xnoreg, "sanity");
10625 InstructionMark im(this);
10626 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10627 attributes.set_rex_vex_w_reverted();
10628 attributes.set_address_attributes(/* tuple_type */ EVEX_T2, /* input_size_in_bits */ EVEX_64bit);
10629 // swap src<->dst for encoding
10630 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10631 emit_int8(0x5A);
10632 emit_operand(dst, src, 0);
10633 }
10634
10635 // scalar single/double precision replicate
10636
10637 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
10638 void Assembler::vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
10639 assert(VM_Version::supports_avx2(), "");
10640 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10641 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10642 emit_int16(0x18, (0xC0 | encode));
10643 }
10644
10645 void Assembler::vbroadcastss(XMMRegister dst, Address src, int vector_len) {
10646 assert(VM_Version::supports_avx(), "");
10647 assert(dst != xnoreg, "sanity");
10648 InstructionMark im(this);
10649 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10650 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10651 // swap src<->dst for encoding
10652 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10653 emit_int8(0x18);
10654 emit_operand(dst, src, 0);
10655 }
10656
10657 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
10658 void Assembler::vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
10659 assert(VM_Version::supports_avx2(), "");
10660 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10661 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10662 attributes.set_rex_vex_w_reverted();
10663 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10664 emit_int16(0x19, (0xC0 | encode));
10665 }
10666
10667 void Assembler::vbroadcastsd(XMMRegister dst, Address src, int vector_len) {
10668 assert(VM_Version::supports_avx(), "");
10669 assert(vector_len == AVX_256bit || vector_len == AVX_512bit, "");
10670 assert(dst != xnoreg, "sanity");
10671 InstructionMark im(this);
10672 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10673 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
10674 attributes.set_rex_vex_w_reverted();
10675 // swap src<->dst for encoding
10676 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10677 emit_int8(0x19);
10678 emit_operand(dst, src, 0);
10679 }
10680
10681 void Assembler::vbroadcastf128(XMMRegister dst, Address src, int vector_len) {
10682 assert(VM_Version::supports_avx(), "");
10683 assert(vector_len == AVX_256bit, "");
10684 assert(dst != xnoreg, "sanity");
10685 InstructionMark im(this);
10686 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10687 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
10688 // swap src<->dst for encoding
10689 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10690 emit_int8(0x1A);
10691 emit_operand(dst, src, 0);
10692 }
10693
10694 // gpr source broadcast forms
10695
10696 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10697 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
10698 assert(VM_Version::supports_avx512bw(), "");
10699 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10700 attributes.set_is_evex_instruction();
10701 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10702 emit_int16(0x7A, (0xC0 | encode));
10703 }
10704
10705 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
10706 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
10707 assert(VM_Version::supports_avx512bw(), "");
10708 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
10709 attributes.set_is_evex_instruction();
10710 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10711 emit_int16(0x7B, (0xC0 | encode));
10712 }
10713
10714 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10715 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
10716 assert(VM_Version::supports_evex(), "");
10717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10718 attributes.set_is_evex_instruction();
10719 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10720 emit_int16(0x7C, (0xC0 | encode));
10721 }
10722
10723 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
10724 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
10725 assert(VM_Version::supports_evex(), "");
10726 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10727 attributes.set_is_evex_instruction();
10728 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10729 emit_int16(0x7C, (0xC0 | encode));
10730 }
10731
10732 void Assembler::vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10733 assert(VM_Version::supports_avx2(), "");
10734 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10735 assert(dst != xnoreg, "sanity");
10736 assert(src.isxmmindex(),"expected to be xmm index");
10737 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10738 InstructionMark im(this);
10739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10740 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10741 emit_int8((unsigned char)0x90);
10742 emit_operand(dst, src, 0);
10743 }
10744
10745 void Assembler::vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10746 assert(VM_Version::supports_avx2(), "");
10747 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10748 assert(dst != xnoreg, "sanity");
10749 assert(src.isxmmindex(),"expected to be xmm index");
10750 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10751 InstructionMark im(this);
10752 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10753 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10754 emit_int8((unsigned char)0x90);
10755 emit_operand(dst, src, 0);
10756 }
10757
10758 void Assembler::vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10759 assert(VM_Version::supports_avx2(), "");
10760 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10761 assert(dst != xnoreg, "sanity");
10762 assert(src.isxmmindex(),"expected to be xmm index");
10763 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10764 InstructionMark im(this);
10765 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10766 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10767 emit_int8((unsigned char)0x92);
10768 emit_operand(dst, src, 0);
10769 }
10770
10771 void Assembler::vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len) {
10772 assert(VM_Version::supports_avx2(), "");
10773 assert(vector_len == Assembler::AVX_128bit || vector_len == Assembler::AVX_256bit, "");
10774 assert(dst != xnoreg, "sanity");
10775 assert(src.isxmmindex(),"expected to be xmm index");
10776 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10777 InstructionMark im(this);
10778 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
10779 vex_prefix(src, mask->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10780 emit_int8((unsigned char)0x92);
10781 emit_operand(dst, src, 0);
10782 }
10783 void Assembler::evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10784 assert(VM_Version::supports_evex(), "");
10785 assert(dst != xnoreg, "sanity");
10786 assert(src.isxmmindex(),"expected to be xmm index");
10787 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10788 assert(mask != k0, "instruction will #UD if mask is in k0");
10789 InstructionMark im(this);
10790 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10791 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10792 attributes.reset_is_clear_context();
10793 attributes.set_embedded_opmask_register_specifier(mask);
10794 attributes.set_is_evex_instruction();
10795 // swap src<->dst for encoding
10796 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10797 emit_int8((unsigned char)0x90);
10798 emit_operand(dst, src, 0);
10799 }
10800
10801 void Assembler::evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10802 assert(VM_Version::supports_evex(), "");
10803 assert(dst != xnoreg, "sanity");
10804 assert(src.isxmmindex(),"expected to be xmm index");
10805 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10806 assert(mask != k0, "instruction will #UD if mask is in k0");
10807 InstructionMark im(this);
10808 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10809 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10810 attributes.reset_is_clear_context();
10811 attributes.set_embedded_opmask_register_specifier(mask);
10812 attributes.set_is_evex_instruction();
10813 // swap src<->dst for encoding
10814 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10815 emit_int8((unsigned char)0x90);
10816 emit_operand(dst, src, 0);
10817 }
10818
10819 void Assembler::evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10820 assert(VM_Version::supports_evex(), "");
10821 assert(dst != xnoreg, "sanity");
10822 assert(src.isxmmindex(),"expected to be xmm index");
10823 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10824 assert(mask != k0, "instruction will #UD if mask is in k0");
10825 InstructionMark im(this);
10826 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10827 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10828 attributes.reset_is_clear_context();
10829 attributes.set_embedded_opmask_register_specifier(mask);
10830 attributes.set_is_evex_instruction();
10831 // swap src<->dst for encoding
10832 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10833 emit_int8((unsigned char)0x92);
10834 emit_operand(dst, src, 0);
10835 }
10836
10837 void Assembler::evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len) {
10838 assert(VM_Version::supports_evex(), "");
10839 assert(dst != xnoreg, "sanity");
10840 assert(src.isxmmindex(),"expected to be xmm index");
10841 assert(dst != src.xmmindex(), "instruction will #UD if dst and index are the same");
10842 assert(mask != k0, "instruction will #UD if mask is in k0");
10843 InstructionMark im(this);
10844 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10845 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10846 attributes.reset_is_clear_context();
10847 attributes.set_embedded_opmask_register_specifier(mask);
10848 attributes.set_is_evex_instruction();
10849 // swap src<->dst for encoding
10850 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10851 emit_int8((unsigned char)0x92);
10852 emit_operand(dst, src, 0);
10853 }
10854
10855 void Assembler::evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10856 assert(VM_Version::supports_evex(), "");
10857 assert(mask != k0, "instruction will #UD if mask is in k0");
10858 InstructionMark im(this);
10859 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10860 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10861 attributes.reset_is_clear_context();
10862 attributes.set_embedded_opmask_register_specifier(mask);
10863 attributes.set_is_evex_instruction();
10864 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10865 emit_int8((unsigned char)0xA0);
10866 emit_operand(src, dst, 0);
10867 }
10868
10869 void Assembler::evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10870 assert(VM_Version::supports_evex(), "");
10871 assert(mask != k0, "instruction will #UD if mask is in k0");
10872 InstructionMark im(this);
10873 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10874 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10875 attributes.reset_is_clear_context();
10876 attributes.set_embedded_opmask_register_specifier(mask);
10877 attributes.set_is_evex_instruction();
10878 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10879 emit_int8((unsigned char)0xA0);
10880 emit_operand(src, dst, 0);
10881 }
10882
10883 void Assembler::evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10884 assert(VM_Version::supports_evex(), "");
10885 assert(mask != k0, "instruction will #UD if mask is in k0");
10886 InstructionMark im(this);
10887 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10888 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10889 attributes.reset_is_clear_context();
10890 attributes.set_embedded_opmask_register_specifier(mask);
10891 attributes.set_is_evex_instruction();
10892 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10893 emit_int8((unsigned char)0xA2);
10894 emit_operand(src, dst, 0);
10895 }
10896
10897 void Assembler::evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len) {
10898 assert(VM_Version::supports_evex(), "");
10899 assert(mask != k0, "instruction will #UD if mask is in k0");
10900 InstructionMark im(this);
10901 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10902 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10903 attributes.reset_is_clear_context();
10904 attributes.set_embedded_opmask_register_specifier(mask);
10905 attributes.set_is_evex_instruction();
10906 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10907 emit_int8((unsigned char)0xA2);
10908 emit_operand(src, dst, 0);
10909 }
10910 // Carry-Less Multiplication Quadword
10911 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
10912 assert(VM_Version::supports_clmul(), "");
10913 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10914 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10915 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10916 }
10917
10918 // Carry-Less Multiplication Quadword
10919 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
10920 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
10921 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
10922 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10923 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10924 }
10925
10926 void Assembler::evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len) {
10927 assert(VM_Version::supports_avx512_vpclmulqdq(), "Requires vector carryless multiplication support");
10928 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10929 attributes.set_is_evex_instruction();
10930 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10931 emit_int24(0x44, (0xC0 | encode), (unsigned char)mask);
10932 }
10933
10934 void Assembler::vzeroupper_uncached() {
10935 if (VM_Version::supports_vzeroupper()) {
10936 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
10937 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
10938 emit_int8(0x77);
10939 }
10940 }
10941
10942 void Assembler::vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8) {
10943 // Encoding: EVEX.LIG.66.0F3A.W0 67 /r ib
10944 assert(VM_Version::supports_evex(), "");
10945 assert(VM_Version::supports_avx512dq(), "");
10946 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10947 attributes.set_is_evex_instruction();
10948 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10949 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10950 }
10951
10952 void Assembler::vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8) {
10953 // Encoding: EVEX.LIG.66.0F3A.W1 67 /r ib
10954 assert(VM_Version::supports_evex(), "");
10955 assert(VM_Version::supports_avx512dq(), "");
10956 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
10957 attributes.set_is_evex_instruction();
10958 int encode = vex_prefix_and_encode(kdst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10959 emit_int24((unsigned char)0x67, (unsigned char)(0xC0 | encode), imm8);
10960 }
10961
10962 void Assembler::fld_x(Address adr) {
10963 InstructionMark im(this);
10964 emit_int8((unsigned char)0xDB);
10965 emit_operand32(rbp, adr, 0);
10966 }
10967
10968 void Assembler::fstp_x(Address adr) {
10969 InstructionMark im(this);
10970 emit_int8((unsigned char)0xDB);
10971 emit_operand32(rdi, adr, 0);
10972 }
10973
10974 void Assembler::emit_operand32(Register reg, Address adr, int post_addr_length) {
10975 assert(reg->encoding() < 8, "no extended registers");
10976 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
10977 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec, post_addr_length);
10978 }
10979
10980 void Assembler::fld_d(Address adr) {
10981 InstructionMark im(this);
10982 emit_int8((unsigned char)0xDD);
10983 emit_operand32(rax, adr, 0);
10984 }
10985
10986 void Assembler::fprem() {
10987 emit_int16((unsigned char)0xD9, (unsigned char)0xF8);
10988 }
10989
10990 void Assembler::fnstsw_ax() {
10991 emit_int16((unsigned char)0xDF, (unsigned char)0xE0);
10992 }
10993
10994 void Assembler::fstp_d(Address adr) {
10995 InstructionMark im(this);
10996 emit_int8((unsigned char)0xDD);
10997 emit_operand32(rbx, adr, 0);
10998 }
10999
11000 void Assembler::fstp_d(int index) {
11001 emit_farith(0xDD, 0xD8, index);
11002 }
11003
11004 void Assembler::emit_farith(int b1, int b2, int i) {
11005 assert(isByte(b1) && isByte(b2), "wrong opcode");
11006 assert(0 <= i && i < 8, "illegal stack offset");
11007 emit_int16(b1, b2 + i);
11008 }
11009
11010 #ifndef _LP64
11011 // 32bit only pieces of the assembler
11012
11013 void Assembler::emms() {
11014 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
11015 emit_int16(0x0F, 0x77);
11016 }
11017
11018 void Assembler::vzeroupper() {
11019 vzeroupper_uncached();
11020 }
11021
11022 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
11023 // NO PREFIX AS NEVER 64BIT
11024 InstructionMark im(this);
11025 emit_int16((unsigned char)0x81, (0xF8 | src1->encoding()));
11026 emit_data(imm32, rspec, 0);
11027 }
11028
11029 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
11030 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
11031 InstructionMark im(this);
11032 emit_int8((unsigned char)0x81);
11033 emit_operand(rdi, src1, 4);
11034 emit_data(imm32, rspec, 0);
11035 }
11036
11037 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
11038 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
11039 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
11040 void Assembler::cmpxchg8(Address adr) {
11041 InstructionMark im(this);
11042 emit_int16(0x0F, (unsigned char)0xC7);
11043 emit_operand(rcx, adr, 0);
11044 }
11045
11046 void Assembler::decl(Register dst) {
11047 // Don't use it directly. Use MacroAssembler::decrementl() instead.
11048 emit_int8(0x48 | dst->encoding());
11049 }
11050
11051 // 64bit doesn't use the x87
11052
11053 void Assembler::fabs() {
11054 emit_int16((unsigned char)0xD9, (unsigned char)0xE1);
11055 }
11056
11057 void Assembler::fadd(int i) {
11058 emit_farith(0xD8, 0xC0, i);
11059 }
11060
11061 void Assembler::fadd_d(Address src) {
11062 InstructionMark im(this);
11063 emit_int8((unsigned char)0xDC);
11064 emit_operand32(rax, src, 0);
11065 }
11066
11067 void Assembler::fadd_s(Address src) {
11068 InstructionMark im(this);
11069 emit_int8((unsigned char)0xD8);
11070 emit_operand32(rax, src, 0);
11071 }
11072
11073 void Assembler::fadda(int i) {
11074 emit_farith(0xDC, 0xC0, i);
11075 }
11076
11077 void Assembler::faddp(int i) {
11078 emit_farith(0xDE, 0xC0, i);
11079 }
11080
11081 void Assembler::fchs() {
11082 emit_int16((unsigned char)0xD9, (unsigned char)0xE0);
11083 }
11084
11085 void Assembler::fcom(int i) {
11086 emit_farith(0xD8, 0xD0, i);
11087 }
11088
11089 void Assembler::fcomp(int i) {
11090 emit_farith(0xD8, 0xD8, i);
11091 }
11092
11093 void Assembler::fcomp_d(Address src) {
11094 InstructionMark im(this);
11095 emit_int8((unsigned char)0xDC);
11096 emit_operand32(rbx, src, 0);
11097 }
11098
11099 void Assembler::fcomp_s(Address src) {
11100 InstructionMark im(this);
11101 emit_int8((unsigned char)0xD8);
11102 emit_operand32(rbx, src, 0);
11103 }
11104
11105 void Assembler::fcompp() {
11106 emit_int16((unsigned char)0xDE, (unsigned char)0xD9);
11107 }
11108
11109 void Assembler::fcos() {
11110 emit_int16((unsigned char)0xD9, (unsigned char)0xFF);
11111 }
11112
11113 void Assembler::fdecstp() {
11114 emit_int16((unsigned char)0xD9, (unsigned char)0xF6);
11115 }
11116
11117 void Assembler::fdiv(int i) {
11118 emit_farith(0xD8, 0xF0, i);
11119 }
11120
11121 void Assembler::fdiv_d(Address src) {
11122 InstructionMark im(this);
11123 emit_int8((unsigned char)0xDC);
11124 emit_operand32(rsi, src, 0);
11125 }
11126
11127 void Assembler::fdiv_s(Address src) {
11128 InstructionMark im(this);
11129 emit_int8((unsigned char)0xD8);
11130 emit_operand32(rsi, src, 0);
11131 }
11132
11133 void Assembler::fdiva(int i) {
11134 emit_farith(0xDC, 0xF8, i);
11135 }
11136
11137 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
11138 // is erroneous for some of the floating-point instructions below.
11139
11140 void Assembler::fdivp(int i) {
11141 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
11142 }
11143
11144 void Assembler::fdivr(int i) {
11145 emit_farith(0xD8, 0xF8, i);
11146 }
11147
11148 void Assembler::fdivr_d(Address src) {
11149 InstructionMark im(this);
11150 emit_int8((unsigned char)0xDC);
11151 emit_operand32(rdi, src, 0);
11152 }
11153
11154 void Assembler::fdivr_s(Address src) {
11155 InstructionMark im(this);
11156 emit_int8((unsigned char)0xD8);
11157 emit_operand32(rdi, src, 0);
11158 }
11159
11160 void Assembler::fdivra(int i) {
11161 emit_farith(0xDC, 0xF0, i);
11162 }
11163
11164 void Assembler::fdivrp(int i) {
11165 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
11166 }
11167
11168 void Assembler::ffree(int i) {
11169 emit_farith(0xDD, 0xC0, i);
11170 }
11171
11172 void Assembler::fild_d(Address adr) {
11173 InstructionMark im(this);
11174 emit_int8((unsigned char)0xDF);
11175 emit_operand32(rbp, adr, 0);
11176 }
11177
11178 void Assembler::fild_s(Address adr) {
11179 InstructionMark im(this);
11180 emit_int8((unsigned char)0xDB);
11181 emit_operand32(rax, adr, 0);
11182 }
11183
11184 void Assembler::fincstp() {
11185 emit_int16((unsigned char)0xD9, (unsigned char)0xF7);
11186 }
11187
11188 void Assembler::finit() {
11189 emit_int24((unsigned char)0x9B, (unsigned char)0xDB, (unsigned char)0xE3);
11190 }
11191
11192 void Assembler::fist_s(Address adr) {
11193 InstructionMark im(this);
11194 emit_int8((unsigned char)0xDB);
11195 emit_operand32(rdx, adr, 0);
11196 }
11197
11198 void Assembler::fistp_d(Address adr) {
11199 InstructionMark im(this);
11200 emit_int8((unsigned char)0xDF);
11201 emit_operand32(rdi, adr, 0);
11202 }
11203
11204 void Assembler::fistp_s(Address adr) {
11205 InstructionMark im(this);
11206 emit_int8((unsigned char)0xDB);
11207 emit_operand32(rbx, adr, 0);
11208 }
11209
11210 void Assembler::fld1() {
11211 emit_int16((unsigned char)0xD9, (unsigned char)0xE8);
11212 }
11213
11214 void Assembler::fld_s(Address adr) {
11215 InstructionMark im(this);
11216 emit_int8((unsigned char)0xD9);
11217 emit_operand32(rax, adr, 0);
11218 }
11219
11220
11221 void Assembler::fld_s(int index) {
11222 emit_farith(0xD9, 0xC0, index);
11223 }
11224
11225 void Assembler::fldcw(Address src) {
11226 InstructionMark im(this);
11227 emit_int8((unsigned char)0xD9);
11228 emit_operand32(rbp, src, 0);
11229 }
11230
11231 void Assembler::fldenv(Address src) {
11232 InstructionMark im(this);
11233 emit_int8((unsigned char)0xD9);
11234 emit_operand32(rsp, src, 0);
11235 }
11236
11237 void Assembler::fldlg2() {
11238 emit_int16((unsigned char)0xD9, (unsigned char)0xEC);
11239 }
11240
11241 void Assembler::fldln2() {
11242 emit_int16((unsigned char)0xD9, (unsigned char)0xED);
11243 }
11244
11245 void Assembler::fldz() {
11246 emit_int16((unsigned char)0xD9, (unsigned char)0xEE);
11247 }
11248
11249 void Assembler::flog() {
11250 fldln2();
11251 fxch();
11252 fyl2x();
11253 }
11254
11255 void Assembler::flog10() {
11256 fldlg2();
11257 fxch();
11258 fyl2x();
11259 }
11260
11261 void Assembler::fmul(int i) {
11262 emit_farith(0xD8, 0xC8, i);
11263 }
11264
11265 void Assembler::fmul_d(Address src) {
11266 InstructionMark im(this);
11267 emit_int8((unsigned char)0xDC);
11268 emit_operand32(rcx, src, 0);
11269 }
11270
11271 void Assembler::fmul_s(Address src) {
11272 InstructionMark im(this);
11273 emit_int8((unsigned char)0xD8);
11274 emit_operand32(rcx, src, 0);
11275 }
11276
11277 void Assembler::fmula(int i) {
11278 emit_farith(0xDC, 0xC8, i);
11279 }
11280
11281 void Assembler::fmulp(int i) {
11282 emit_farith(0xDE, 0xC8, i);
11283 }
11284
11285 void Assembler::fnsave(Address dst) {
11286 InstructionMark im(this);
11287 emit_int8((unsigned char)0xDD);
11288 emit_operand32(rsi, dst, 0);
11289 }
11290
11291 void Assembler::fnstcw(Address src) {
11292 InstructionMark im(this);
11293 emit_int16((unsigned char)0x9B, (unsigned char)0xD9);
11294 emit_operand32(rdi, src, 0);
11295 }
11296
11297 void Assembler::fprem1() {
11298 emit_int16((unsigned char)0xD9, (unsigned char)0xF5);
11299 }
11300
11301 void Assembler::frstor(Address src) {
11302 InstructionMark im(this);
11303 emit_int8((unsigned char)0xDD);
11304 emit_operand32(rsp, src, 0);
11305 }
11306
11307 void Assembler::fsin() {
11308 emit_int16((unsigned char)0xD9, (unsigned char)0xFE);
11309 }
11310
11311 void Assembler::fsqrt() {
11312 emit_int16((unsigned char)0xD9, (unsigned char)0xFA);
11313 }
11314
11315 void Assembler::fst_d(Address adr) {
11316 InstructionMark im(this);
11317 emit_int8((unsigned char)0xDD);
11318 emit_operand32(rdx, adr, 0);
11319 }
11320
11321 void Assembler::fst_s(Address adr) {
11322 InstructionMark im(this);
11323 emit_int8((unsigned char)0xD9);
11324 emit_operand32(rdx, adr, 0);
11325 }
11326
11327 void Assembler::fstp_s(Address adr) {
11328 InstructionMark im(this);
11329 emit_int8((unsigned char)0xD9);
11330 emit_operand32(rbx, adr, 0);
11331 }
11332
11333 void Assembler::fsub(int i) {
11334 emit_farith(0xD8, 0xE0, i);
11335 }
11336
11337 void Assembler::fsub_d(Address src) {
11338 InstructionMark im(this);
11339 emit_int8((unsigned char)0xDC);
11340 emit_operand32(rsp, src, 0);
11341 }
11342
11343 void Assembler::fsub_s(Address src) {
11344 InstructionMark im(this);
11345 emit_int8((unsigned char)0xD8);
11346 emit_operand32(rsp, src, 0);
11347 }
11348
11349 void Assembler::fsuba(int i) {
11350 emit_farith(0xDC, 0xE8, i);
11351 }
11352
11353 void Assembler::fsubp(int i) {
11354 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
11355 }
11356
11357 void Assembler::fsubr(int i) {
11358 emit_farith(0xD8, 0xE8, i);
11359 }
11360
11361 void Assembler::fsubr_d(Address src) {
11362 InstructionMark im(this);
11363 emit_int8((unsigned char)0xDC);
11364 emit_operand32(rbp, src, 0);
11365 }
11366
11367 void Assembler::fsubr_s(Address src) {
11368 InstructionMark im(this);
11369 emit_int8((unsigned char)0xD8);
11370 emit_operand32(rbp, src, 0);
11371 }
11372
11373 void Assembler::fsubra(int i) {
11374 emit_farith(0xDC, 0xE0, i);
11375 }
11376
11377 void Assembler::fsubrp(int i) {
11378 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
11379 }
11380
11381 void Assembler::ftan() {
11382 emit_int32((unsigned char)0xD9, (unsigned char)0xF2, (unsigned char)0xDD, (unsigned char)0xD8);
11383 }
11384
11385 void Assembler::ftst() {
11386 emit_int16((unsigned char)0xD9, (unsigned char)0xE4);
11387 }
11388
11389 void Assembler::fucomi(int i) {
11390 // make sure the instruction is supported (introduced for P6, together with cmov)
11391 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11392 emit_farith(0xDB, 0xE8, i);
11393 }
11394
11395 void Assembler::fucomip(int i) {
11396 // make sure the instruction is supported (introduced for P6, together with cmov)
11397 guarantee(VM_Version::supports_cmov(), "illegal instruction");
11398 emit_farith(0xDF, 0xE8, i);
11399 }
11400
11401 void Assembler::fwait() {
11402 emit_int8((unsigned char)0x9B);
11403 }
11404
11405 void Assembler::fxch(int i) {
11406 emit_farith(0xD9, 0xC8, i);
11407 }
11408
11409 void Assembler::fyl2x() {
11410 emit_int16((unsigned char)0xD9, (unsigned char)0xF1);
11411 }
11412
11413 void Assembler::frndint() {
11414 emit_int16((unsigned char)0xD9, (unsigned char)0xFC);
11415 }
11416
11417 void Assembler::f2xm1() {
11418 emit_int16((unsigned char)0xD9, (unsigned char)0xF0);
11419 }
11420
11421 void Assembler::fldl2e() {
11422 emit_int16((unsigned char)0xD9, (unsigned char)0xEA);
11423 }
11424 #endif // !_LP64
11425
11426 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
11427 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
11428 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
11429 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
11430
11431 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
11432 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11433 if (pre > 0) {
11434 emit_int8(simd_pre[pre]);
11435 }
11436 if (rex_w) {
11437 prefixq(adr, xreg);
11438 } else {
11439 prefix(adr, xreg);
11440 }
11441 if (opc > 0) {
11442 emit_int8(0x0F);
11443 int opc2 = simd_opc[opc];
11444 if (opc2 > 0) {
11445 emit_int8(opc2);
11446 }
11447 }
11448 }
11449
11450 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
11451 if (pre > 0) {
11452 emit_int8(simd_pre[pre]);
11453 }
11454 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
11455 if (opc > 0) {
11456 emit_int8(0x0F);
11457 int opc2 = simd_opc[opc];
11458 if (opc2 > 0) {
11459 emit_int8(opc2);
11460 }
11461 }
11462 return encode;
11463 }
11464
11465
11466 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
11467 int vector_len = _attributes->get_vector_len();
11468 bool vex_w = _attributes->is_rex_vex_w();
11469 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
11470 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
11471 byte1 = (~byte1) & 0xE0;
11472 byte1 |= opc;
11473
11474 int byte2 = ((~nds_enc) & 0xf) << 3;
11475 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
11476
11477 emit_int24((unsigned char)VEX_3bytes, byte1, byte2);
11478 } else {
11479 int byte1 = vex_r ? VEX_R : 0;
11480 byte1 = (~byte1) & 0x80;
11481 byte1 |= ((~nds_enc) & 0xf) << 3;
11482 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
11483 emit_int16((unsigned char)VEX_2bytes, byte1);
11484 }
11485 }
11486
11487 // This is a 4 byte encoding
11488 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
11489 // EVEX 0x62 prefix
11490 // byte1 = EVEX_4bytes;
11491
11492 bool vex_w = _attributes->is_rex_vex_w();
11493 int evex_encoding = (vex_w ? VEX_W : 0);
11494 // EVEX.b is not currently used for broadcast of single element or data rounding modes
11495 _attributes->set_evex_encoding(evex_encoding);
11496
11497 // P0: byte 2, initialized to RXBR`00mm
11498 // instead of not'd
11499 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
11500 byte2 = (~byte2) & 0xF0;
11501 // confine opc opcode extensions in mm bits to lower two bits
11502 // of form {0F, 0F_38, 0F_3A}
11503 byte2 |= opc;
11504
11505 // P1: byte 3 as Wvvvv1pp
11506 int byte3 = ((~nds_enc) & 0xf) << 3;
11507 // p[10] is always 1
11508 byte3 |= EVEX_F;
11509 byte3 |= (vex_w & 1) << 7;
11510 // confine pre opcode extensions in pp bits to lower two bits
11511 // of form {66, F3, F2}
11512 byte3 |= pre;
11513
11514 // P2: byte 4 as zL'Lbv'aaa
11515 // kregs are implemented in the low 3 bits as aaa
11516 int byte4 = (_attributes->is_no_reg_mask()) ?
11517 0 :
11518 _attributes->get_embedded_opmask_register_specifier();
11519 // EVEX.v` for extending EVEX.vvvv or VIDX
11520 byte4 |= (evex_v ? 0: EVEX_V);
11521 // third EXEC.b for broadcast actions
11522 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
11523 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
11524 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
11525 // last is EVEX.z for zero/merge actions
11526 if (_attributes->is_no_reg_mask() == false &&
11527 _attributes->get_embedded_opmask_register_specifier() != 0) {
11528 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
11529 }
11530
11531 emit_int32(EVEX_4bytes, byte2, byte3, byte4);
11532 }
11533
11534 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11535 bool vex_r = (xreg_enc & 8) == 8;
11536 bool vex_b = adr.base_needs_rex();
11537 bool vex_x;
11538 if (adr.isxmmindex()) {
11539 vex_x = adr.xmmindex_needs_rex();
11540 } else {
11541 vex_x = adr.index_needs_rex();
11542 }
11543 set_attributes(attributes);
11544
11545 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11546 // is allowed in legacy mode and has resources which will fit in it.
11547 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11548 if (!attributes->is_legacy_mode()) {
11549 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11550 if ((attributes->get_vector_len() != AVX_512bit) && (nds_enc < 16) && (xreg_enc < 16)) {
11551 attributes->set_is_legacy_mode();
11552 }
11553 }
11554 }
11555
11556 if (UseAVX > 2) {
11557 assert(((!attributes->uses_vl()) ||
11558 (attributes->get_vector_len() == AVX_512bit) ||
11559 (!_legacy_mode_vl) ||
11560 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11561 assert(((nds_enc < 16 && xreg_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11562 }
11563
11564 clear_managed();
11565 if (UseAVX > 2 && !attributes->is_legacy_mode())
11566 {
11567 bool evex_r = (xreg_enc >= 16);
11568 bool evex_v;
11569 // EVEX.V' is set to true when VSIB is used as we may need to use higher order XMM registers (16-31)
11570 if (adr.isxmmindex()) {
11571 evex_v = ((adr._xmmindex->encoding() > 15) ? true : false);
11572 } else {
11573 evex_v = (nds_enc >= 16);
11574 }
11575 attributes->set_is_evex_instruction();
11576 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11577 } else {
11578 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11579 attributes->set_rex_vex_w(false);
11580 }
11581 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11582 }
11583 }
11584
11585 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
11586 bool vex_r = (dst_enc & 8) == 8;
11587 bool vex_b = (src_enc & 8) == 8;
11588 bool vex_x = false;
11589 set_attributes(attributes);
11590
11591 // For EVEX instruction (which is not marked as pure EVEX instruction) check and see if this instruction
11592 // is allowed in legacy mode and has resources which will fit in it.
11593 // Pure EVEX instructions will have is_evex_instruction set in their definition.
11594 if (!attributes->is_legacy_mode()) {
11595 if (UseAVX > 2 && !attributes->is_evex_instruction() && !is_managed()) {
11596 if ((!attributes->uses_vl() || (attributes->get_vector_len() != AVX_512bit)) &&
11597 (dst_enc < 16) && (nds_enc < 16) && (src_enc < 16)) {
11598 attributes->set_is_legacy_mode();
11599 }
11600 }
11601 }
11602
11603 if (UseAVX > 2) {
11604 // All the scalar fp instructions (with uses_vl as false) can have legacy_mode as false
11605 // Instruction with uses_vl true are vector instructions
11606 // All the vector instructions with AVX_512bit length can have legacy_mode as false
11607 // All the vector instructions with < AVX_512bit length can have legacy_mode as false if AVX512vl() is supported
11608 // Rest all should have legacy_mode set as true
11609 assert(((!attributes->uses_vl()) ||
11610 (attributes->get_vector_len() == AVX_512bit) ||
11611 (!_legacy_mode_vl) ||
11612 (attributes->is_legacy_mode())),"XMM register should be 0-15");
11613 // Instruction with legacy_mode true should have dst, nds and src < 15
11614 assert(((dst_enc < 16 && nds_enc < 16 && src_enc < 16) || (!attributes->is_legacy_mode())),"XMM register should be 0-15");
11615 }
11616
11617 clear_managed();
11618 if (UseAVX > 2 && !attributes->is_legacy_mode())
11619 {
11620 bool evex_r = (dst_enc >= 16);
11621 bool evex_v = (nds_enc >= 16);
11622 // can use vex_x as bank extender on rm encoding
11623 vex_x = (src_enc >= 16);
11624 attributes->set_is_evex_instruction();
11625 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
11626 } else {
11627 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
11628 attributes->set_rex_vex_w(false);
11629 }
11630 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
11631 }
11632
11633 // return modrm byte components for operands
11634 return (((dst_enc & 7) << 3) | (src_enc & 7));
11635 }
11636
11637
11638 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
11639 VexOpcode opc, InstructionAttr *attributes) {
11640 if (UseAVX > 0) {
11641 int xreg_enc = xreg->encoding();
11642 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11643 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
11644 } else {
11645 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
11646 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
11647 }
11648 }
11649
11650 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
11651 VexOpcode opc, InstructionAttr *attributes) {
11652 int dst_enc = dst->encoding();
11653 int src_enc = src->encoding();
11654 if (UseAVX > 0) {
11655 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
11656 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
11657 } else {
11658 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
11659 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
11660 }
11661 }
11662
11663 void Assembler::vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11664 assert(VM_Version::supports_avx(), "");
11665 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11666 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11667 emit_int16(0x5F, (0xC0 | encode));
11668 }
11669
11670 void Assembler::vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11671 assert(VM_Version::supports_avx(), "");
11672 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11673 attributes.set_rex_vex_w_reverted();
11674 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11675 emit_int16(0x5F, (0xC0 | encode));
11676 }
11677
11678 void Assembler::vminss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11679 assert(VM_Version::supports_avx(), "");
11680 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11681 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
11682 emit_int16(0x5D, (0xC0 | encode));
11683 }
11684
11685 void Assembler::vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
11686 assert(VM_Version::supports_avx(), "");
11687 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
11688 attributes.set_rex_vex_w_reverted();
11689 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
11690 emit_int16(0x5D, (0xC0 | encode));
11691 }
11692
11693 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
11694 assert(VM_Version::supports_avx(), "");
11695 assert(vector_len <= AVX_256bit, "");
11696 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11697 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11698 emit_int24((unsigned char)0xC2, (0xC0 | encode), (0xF & cop));
11699 }
11700
11701 void Assembler::blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11702 assert(VM_Version::supports_avx(), "");
11703 assert(vector_len <= AVX_256bit, "");
11704 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11705 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11706 int src2_enc = src2->encoding();
11707 emit_int24(0x4C, (0xC0 | encode), (0xF0 & src2_enc << 4));
11708 }
11709
11710 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11711 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11712 assert(vector_len <= AVX_256bit, "");
11713 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11714 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11715 int src2_enc = src2->encoding();
11716 emit_int24(0x4B, (0xC0 | encode), (0xF0 & src2_enc << 4));
11717 }
11718
11719 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11720 assert(VM_Version::supports_avx2(), "");
11721 assert(vector_len <= AVX_256bit, "");
11722 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11723 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11724 emit_int24(0x02, (0xC0 | encode), (unsigned char)imm8);
11725 }
11726
11727 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
11728 assert(VM_Version::supports_avx(), "");
11729 assert(vector_len <= AVX_256bit, "");
11730 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
11731 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11732 emit_int24((unsigned char)0xC2, (0xC0 | encode), (unsigned char)comparison);
11733 }
11734
11735 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11736 ComparisonPredicateFP comparison, int vector_len) {
11737 assert(VM_Version::supports_evex(), "");
11738 // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
11739 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11740 attributes.set_is_evex_instruction();
11741 attributes.set_embedded_opmask_register_specifier(mask);
11742 attributes.reset_is_clear_context();
11743 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
11744 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11745 }
11746
11747 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11748 ComparisonPredicateFP comparison, int vector_len) {
11749 assert(VM_Version::supports_evex(), "");
11750 // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
11751 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11752 attributes.set_is_evex_instruction();
11753 attributes.set_embedded_opmask_register_specifier(mask);
11754 attributes.reset_is_clear_context();
11755 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11756 emit_int24((unsigned char)0xC2, (0xC0 | encode), comparison);
11757 }
11758
11759 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
11760 assert(VM_Version::supports_sse4_1(), "");
11761 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11762 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11763 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11764 emit_int16(0x14, (0xC0 | encode));
11765 }
11766
11767 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
11768 assert(VM_Version::supports_sse4_1(), "");
11769 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11770 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11771 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11772 emit_int16(0x15, (0xC0 | encode));
11773 }
11774
11775 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
11776 assert(VM_Version::supports_sse4_1(), "");
11777 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
11778 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11779 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11780 emit_int16(0x10, (0xC0 | encode));
11781 }
11782
11783 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
11784 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
11785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11786 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11787 int src2_enc = src2->encoding();
11788 emit_int24(0x4A, (0xC0 | encode), (0xF0 & src2_enc << 4));
11789 }
11790
11791 void Assembler::vblendps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
11792 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11793 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11794 emit_int24(0x0C, (0xC0 | encode), imm8);
11795 }
11796
11797 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11798 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11799 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11800 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11801 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11802 emit_int16(0x64, (0xC0 | encode));
11803 }
11804
11805 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11806 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11807 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11808 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11809 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11810 emit_int16(0x65, (0xC0 | encode));
11811 }
11812
11813 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11814 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11815 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11816 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11817 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11818 emit_int16(0x66, (0xC0 | encode));
11819 }
11820
11821 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
11822 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
11823 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
11824 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
11825 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11826 emit_int16(0x37, (0xC0 | encode));
11827 }
11828
11829 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11830 int comparison, bool is_signed, int vector_len) {
11831 assert(VM_Version::supports_evex(), "");
11832 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11833 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11834 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11835 attributes.set_is_evex_instruction();
11836 attributes.set_embedded_opmask_register_specifier(mask);
11837 attributes.reset_is_clear_context();
11838 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11839 int opcode = is_signed ? 0x1F : 0x1E;
11840 emit_int24(opcode, (0xC0 | encode), comparison);
11841 }
11842
11843 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11844 int comparison, bool is_signed, int vector_len) {
11845 assert(VM_Version::supports_evex(), "");
11846 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11847 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
11848 InstructionMark im(this);
11849 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11850 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11851 attributes.set_is_evex_instruction();
11852 attributes.set_embedded_opmask_register_specifier(mask);
11853 attributes.reset_is_clear_context();
11854 int dst_enc = kdst->encoding();
11855 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11856 int opcode = is_signed ? 0x1F : 0x1E;
11857 emit_int8((unsigned char)opcode);
11858 emit_operand(as_Register(dst_enc), src, 1);
11859 emit_int8((unsigned char)comparison);
11860 }
11861
11862 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11863 int comparison, bool is_signed, int vector_len) {
11864 assert(VM_Version::supports_evex(), "");
11865 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11866 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11867 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11868 attributes.set_is_evex_instruction();
11869 attributes.set_embedded_opmask_register_specifier(mask);
11870 attributes.reset_is_clear_context();
11871 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11872 int opcode = is_signed ? 0x1F : 0x1E;
11873 emit_int24(opcode, (0xC0 | encode), comparison);
11874 }
11875
11876 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11877 int comparison, bool is_signed, int vector_len) {
11878 assert(VM_Version::supports_evex(), "");
11879 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11880 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
11881 InstructionMark im(this);
11882 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11883 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
11884 attributes.set_is_evex_instruction();
11885 attributes.set_embedded_opmask_register_specifier(mask);
11886 attributes.reset_is_clear_context();
11887 int dst_enc = kdst->encoding();
11888 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11889 int opcode = is_signed ? 0x1F : 0x1E;
11890 emit_int8((unsigned char)opcode);
11891 emit_operand(as_Register(dst_enc), src, 1);
11892 emit_int8((unsigned char)comparison);
11893 }
11894
11895 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11896 int comparison, bool is_signed, int vector_len) {
11897 assert(VM_Version::supports_evex(), "");
11898 assert(VM_Version::supports_avx512bw(), "");
11899 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11900 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11901 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11902 attributes.set_is_evex_instruction();
11903 attributes.set_embedded_opmask_register_specifier(mask);
11904 attributes.reset_is_clear_context();
11905 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11906 int opcode = is_signed ? 0x3F : 0x3E;
11907 emit_int24(opcode, (0xC0 | encode), comparison);
11908 }
11909
11910 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11911 int comparison, bool is_signed, int vector_len) {
11912 assert(VM_Version::supports_evex(), "");
11913 assert(VM_Version::supports_avx512bw(), "");
11914 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11915 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
11916 InstructionMark im(this);
11917 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11918 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11919 attributes.set_is_evex_instruction();
11920 attributes.set_embedded_opmask_register_specifier(mask);
11921 attributes.reset_is_clear_context();
11922 int dst_enc = kdst->encoding();
11923 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11924 int opcode = is_signed ? 0x3F : 0x3E;
11925 emit_int8((unsigned char)opcode);
11926 emit_operand(as_Register(dst_enc), src, 1);
11927 emit_int8((unsigned char)comparison);
11928 }
11929
11930 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
11931 int comparison, bool is_signed, int vector_len) {
11932 assert(VM_Version::supports_evex(), "");
11933 assert(VM_Version::supports_avx512bw(), "");
11934 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11935 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11936 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11937 attributes.set_is_evex_instruction();
11938 attributes.set_embedded_opmask_register_specifier(mask);
11939 attributes.reset_is_clear_context();
11940 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11941 int opcode = is_signed ? 0x3F : 0x3E;
11942 emit_int24(opcode, (0xC0 | encode), comparison);
11943 }
11944
11945 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
11946 int comparison, bool is_signed, int vector_len) {
11947 assert(VM_Version::supports_evex(), "");
11948 assert(VM_Version::supports_avx512bw(), "");
11949 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
11950 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
11951 InstructionMark im(this);
11952 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
11953 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
11954 attributes.set_is_evex_instruction();
11955 attributes.set_embedded_opmask_register_specifier(mask);
11956 attributes.reset_is_clear_context();
11957 int dst_enc = kdst->encoding();
11958 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
11959 int opcode = is_signed ? 0x3F : 0x3E;
11960 emit_int8((unsigned char)opcode);
11961 emit_operand(as_Register(dst_enc), src, 1);
11962 emit_int8((unsigned char)comparison);
11963 }
11964
11965 void Assembler::evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11966 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11967 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11968 attributes.set_is_evex_instruction();
11969 attributes.set_embedded_opmask_register_specifier(mask);
11970 if (merge) {
11971 attributes.reset_is_clear_context();
11972 }
11973 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11974 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11975 }
11976
11977 void Assembler::evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
11978 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11979 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11980 attributes.set_is_evex_instruction();
11981 attributes.set_embedded_opmask_register_specifier(mask);
11982 if (merge) {
11983 attributes.reset_is_clear_context();
11984 }
11985 int encode = vex_prefix_and_encode(xmm0->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
11986 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
11987 }
11988
11989 void Assembler::evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
11990 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
11991 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11992 attributes.set_is_evex_instruction();
11993 attributes.set_embedded_opmask_register_specifier(mask);
11994 if (merge) {
11995 attributes.reset_is_clear_context();
11996 }
11997 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11998 emit_int16(0x14, (0xC0 | encode));
11999 }
12000
12001 void Assembler::evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12002 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12003 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12004 attributes.set_is_evex_instruction();
12005 attributes.set_embedded_opmask_register_specifier(mask);
12006 if (merge) {
12007 attributes.reset_is_clear_context();
12008 }
12009 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12010 emit_int16(0x14, (0xC0 | encode));
12011 }
12012
12013 void Assembler::evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12014 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12015 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12016 attributes.set_is_evex_instruction();
12017 attributes.set_embedded_opmask_register_specifier(mask);
12018 if (merge) {
12019 attributes.reset_is_clear_context();
12020 }
12021 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12022 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12023 }
12024
12025 void Assembler::evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len) {
12026 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12027 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12028 attributes.set_is_evex_instruction();
12029 attributes.set_embedded_opmask_register_specifier(mask);
12030 if (merge) {
12031 attributes.reset_is_clear_context();
12032 }
12033 int encode = vex_prefix_and_encode(xmm1->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
12034 emit_int24(0x72, (0xC0 | encode), shift & 0xFF);
12035 }
12036
12037 void Assembler::evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12038 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12039 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12040 attributes.set_is_evex_instruction();
12041 attributes.set_embedded_opmask_register_specifier(mask);
12042 if (merge) {
12043 attributes.reset_is_clear_context();
12044 }
12045 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12046 emit_int16(0x15, (0xC0 | encode));
12047 }
12048
12049 void Assembler::evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12050 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12051 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12052 attributes.set_is_evex_instruction();
12053 attributes.set_embedded_opmask_register_specifier(mask);
12054 if (merge) {
12055 attributes.reset_is_clear_context();
12056 }
12057 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12058 emit_int16(0x15, (0xC0 | encode));
12059 }
12060
12061 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
12062 assert(VM_Version::supports_avx(), "");
12063 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12064 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
12065 int mask_enc = mask->encoding();
12066 emit_int24(0x4C, (0xC0 | encode), 0xF0 & mask_enc << 4);
12067 }
12068
12069 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12070 assert(VM_Version::supports_evex(), "");
12071 // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
12072 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12073 attributes.set_is_evex_instruction();
12074 attributes.set_embedded_opmask_register_specifier(mask);
12075 if (merge) {
12076 attributes.reset_is_clear_context();
12077 }
12078 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12079 emit_int16(0x65, (0xC0 | encode));
12080 }
12081
12082 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12083 assert(VM_Version::supports_evex(), "");
12084 // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
12085 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12086 attributes.set_is_evex_instruction();
12087 attributes.set_embedded_opmask_register_specifier(mask);
12088 if (merge) {
12089 attributes.reset_is_clear_context();
12090 }
12091 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12092 emit_int16(0x65, (0xC0 | encode));
12093 }
12094
12095 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12096 assert(VM_Version::supports_evex(), "");
12097 assert(VM_Version::supports_avx512bw(), "");
12098 // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
12099 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12100 attributes.set_is_evex_instruction();
12101 attributes.set_embedded_opmask_register_specifier(mask);
12102 if (merge) {
12103 attributes.reset_is_clear_context();
12104 }
12105 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12106 emit_int16(0x66, (0xC0 | encode));
12107 }
12108
12109 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12110 assert(VM_Version::supports_evex(), "");
12111 assert(VM_Version::supports_avx512bw(), "");
12112 // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
12113 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
12114 attributes.set_is_evex_instruction();
12115 attributes.set_embedded_opmask_register_specifier(mask);
12116 if (merge) {
12117 attributes.reset_is_clear_context();
12118 }
12119 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12120 emit_int16(0x66, (0xC0 | encode));
12121 }
12122
12123 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12124 assert(VM_Version::supports_evex(), "");
12125 //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
12126 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12127 attributes.set_is_evex_instruction();
12128 attributes.set_embedded_opmask_register_specifier(mask);
12129 if (merge) {
12130 attributes.reset_is_clear_context();
12131 }
12132 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12133 emit_int16(0x64, (0xC0 | encode));
12134 }
12135
12136 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
12137 assert(VM_Version::supports_evex(), "");
12138 //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
12139 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12140 attributes.set_is_evex_instruction();
12141 attributes.set_embedded_opmask_register_specifier(mask);
12142 if (merge) {
12143 attributes.reset_is_clear_context();
12144 }
12145 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12146 emit_int16(0x64, (0xC0 | encode));
12147 }
12148
12149 void Assembler::bzhiq(Register dst, Register src1, Register src2) {
12150 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12151 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12152 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12153 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12154 }
12155
12156 void Assembler::pextl(Register dst, Register src1, Register src2) {
12157 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12158 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12159 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12160 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12161 }
12162
12163 void Assembler::pdepl(Register dst, Register src1, Register src2) {
12164 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12165 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12166 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12167 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12168 }
12169
12170 void Assembler::pextq(Register dst, Register src1, Register src2) {
12171 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12172 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12173 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12174 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12175 }
12176
12177 void Assembler::pdepq(Register dst, Register src1, Register src2) {
12178 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12179 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12180 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12181 emit_int16((unsigned char)0xF5, (0xC0 | encode));
12182 }
12183
12184 void Assembler::pextl(Register dst, Register src1, Address src2) {
12185 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12186 InstructionMark im(this);
12187 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12188 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12189 emit_int8((unsigned char)0xF5);
12190 emit_operand(dst, src2, 0);
12191 }
12192
12193 void Assembler::pdepl(Register dst, Register src1, Address src2) {
12194 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12195 InstructionMark im(this);
12196 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12197 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12198 emit_int8((unsigned char)0xF5);
12199 emit_operand(dst, src2, 0);
12200 }
12201
12202 void Assembler::pextq(Register dst, Register src1, Address src2) {
12203 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12204 InstructionMark im(this);
12205 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12206 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12207 emit_int8((unsigned char)0xF5);
12208 emit_operand(dst, src2, 0);
12209 }
12210
12211 void Assembler::pdepq(Register dst, Register src1, Address src2) {
12212 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
12213 InstructionMark im(this);
12214 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12215 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12216 emit_int8((unsigned char)0xF5);
12217 emit_operand(dst, src2, 0);
12218 }
12219
12220 void Assembler::sarxl(Register dst, Register src1, Register src2) {
12221 assert(VM_Version::supports_bmi2(), "");
12222 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12223 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12224 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12225 }
12226
12227 void Assembler::sarxl(Register dst, Address src1, Register src2) {
12228 assert(VM_Version::supports_bmi2(), "");
12229 InstructionMark im(this);
12230 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12231 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12232 emit_int8((unsigned char)0xF7);
12233 emit_operand(dst, src1, 0);
12234 }
12235
12236 void Assembler::sarxq(Register dst, Register src1, Register src2) {
12237 assert(VM_Version::supports_bmi2(), "");
12238 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12239 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12240 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12241 }
12242
12243 void Assembler::sarxq(Register dst, Address src1, Register src2) {
12244 assert(VM_Version::supports_bmi2(), "");
12245 InstructionMark im(this);
12246 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12247 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12248 emit_int8((unsigned char)0xF7);
12249 emit_operand(dst, src1, 0);
12250 }
12251
12252 void Assembler::shlxl(Register dst, Register src1, Register src2) {
12253 assert(VM_Version::supports_bmi2(), "");
12254 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12255 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12256 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12257 }
12258
12259 void Assembler::shlxl(Register dst, Address src1, Register src2) {
12260 assert(VM_Version::supports_bmi2(), "");
12261 InstructionMark im(this);
12262 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12263 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12264 emit_int8((unsigned char)0xF7);
12265 emit_operand(dst, src1, 0);
12266 }
12267
12268 void Assembler::shlxq(Register dst, Register src1, Register src2) {
12269 assert(VM_Version::supports_bmi2(), "");
12270 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12271 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12272 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12273 }
12274
12275 void Assembler::shlxq(Register dst, Address src1, Register src2) {
12276 assert(VM_Version::supports_bmi2(), "");
12277 InstructionMark im(this);
12278 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12279 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12280 emit_int8((unsigned char)0xF7);
12281 emit_operand(dst, src1, 0);
12282 }
12283
12284 void Assembler::shrxl(Register dst, Register src1, Register src2) {
12285 assert(VM_Version::supports_bmi2(), "");
12286 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12287 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12288 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12289 }
12290
12291 void Assembler::shrxl(Register dst, Address src1, Register src2) {
12292 assert(VM_Version::supports_bmi2(), "");
12293 InstructionMark im(this);
12294 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12295 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12296 emit_int8((unsigned char)0xF7);
12297 emit_operand(dst, src1, 0);
12298 }
12299
12300 void Assembler::shrxq(Register dst, Register src1, Register src2) {
12301 assert(VM_Version::supports_bmi2(), "");
12302 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12303 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12304 emit_int16((unsigned char)0xF7, (0xC0 | encode));
12305 }
12306
12307 void Assembler::shrxq(Register dst, Address src1, Register src2) {
12308 assert(VM_Version::supports_bmi2(), "");
12309 InstructionMark im(this);
12310 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
12311 vex_prefix(src1, src2->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
12312 emit_int8((unsigned char)0xF7);
12313 emit_operand(dst, src1, 0);
12314 }
12315
12316 void Assembler::evpmovq2m(KRegister dst, XMMRegister src, int vector_len) {
12317 assert(VM_Version::supports_avx512vldq(), "");
12318 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12319 attributes.set_is_evex_instruction();
12320 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12321 emit_int16(0x39, (0xC0 | encode));
12322 }
12323
12324 void Assembler::evpmovd2m(KRegister dst, XMMRegister src, int vector_len) {
12325 assert(VM_Version::supports_avx512vldq(), "");
12326 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12327 attributes.set_is_evex_instruction();
12328 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12329 emit_int16(0x39, (0xC0 | encode));
12330 }
12331
12332 void Assembler::evpmovw2m(KRegister dst, XMMRegister src, int vector_len) {
12333 assert(VM_Version::supports_avx512vlbw(), "");
12334 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12335 attributes.set_is_evex_instruction();
12336 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12337 emit_int16(0x29, (0xC0 | encode));
12338 }
12339
12340 void Assembler::evpmovb2m(KRegister dst, XMMRegister src, int vector_len) {
12341 assert(VM_Version::supports_avx512vlbw(), "");
12342 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12343 attributes.set_is_evex_instruction();
12344 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12345 emit_int16(0x29, (0xC0 | encode));
12346 }
12347
12348 void Assembler::evpmovm2q(XMMRegister dst, KRegister src, int vector_len) {
12349 assert(VM_Version::supports_avx512vldq(), "");
12350 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12351 attributes.set_is_evex_instruction();
12352 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12353 emit_int16(0x38, (0xC0 | encode));
12354 }
12355
12356 void Assembler::evpmovm2d(XMMRegister dst, KRegister src, int vector_len) {
12357 assert(VM_Version::supports_avx512vldq(), "");
12358 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12359 attributes.set_is_evex_instruction();
12360 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12361 emit_int16(0x38, (0xC0 | encode));
12362 }
12363
12364 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
12365 assert(VM_Version::supports_avx512vlbw(), "");
12366 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12367 attributes.set_is_evex_instruction();
12368 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12369 emit_int16(0x28, (0xC0 | encode));
12370 }
12371
12372 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
12373 assert(VM_Version::supports_avx512vlbw(), "");
12374 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
12375 attributes.set_is_evex_instruction();
12376 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
12377 emit_int16(0x28, (0xC0 | encode));
12378 }
12379
12380 void Assembler::evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12381 assert(VM_Version::supports_avx512_vbmi2(), "");
12382 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12383 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12384 attributes.set_embedded_opmask_register_specifier(mask);
12385 attributes.set_is_evex_instruction();
12386 if (merge) {
12387 attributes.reset_is_clear_context();
12388 }
12389 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12390 emit_int16((unsigned char)0x63, (0xC0 | encode));
12391 }
12392
12393 void Assembler::evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12394 assert(VM_Version::supports_avx512_vbmi2(), "");
12395 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12396 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12397 attributes.set_embedded_opmask_register_specifier(mask);
12398 attributes.set_is_evex_instruction();
12399 if (merge) {
12400 attributes.reset_is_clear_context();
12401 }
12402 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12403 emit_int16((unsigned char)0x63, (0xC0 | encode));
12404 }
12405
12406 void Assembler::evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12407 assert(VM_Version::supports_evex(), "");
12408 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12409 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12410 attributes.set_embedded_opmask_register_specifier(mask);
12411 attributes.set_is_evex_instruction();
12412 if (merge) {
12413 attributes.reset_is_clear_context();
12414 }
12415 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12416 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12417 }
12418
12419 void Assembler::evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12420 assert(VM_Version::supports_evex(), "");
12421 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12422 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12423 attributes.set_embedded_opmask_register_specifier(mask);
12424 attributes.set_is_evex_instruction();
12425 if (merge) {
12426 attributes.reset_is_clear_context();
12427 }
12428 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12429 emit_int16((unsigned char)0x8B, (0xC0 | encode));
12430 }
12431
12432 void Assembler::evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12433 assert(VM_Version::supports_evex(), "");
12434 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12435 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12436 attributes.set_embedded_opmask_register_specifier(mask);
12437 attributes.set_is_evex_instruction();
12438 if (merge) {
12439 attributes.reset_is_clear_context();
12440 }
12441 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12442 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12443 }
12444
12445 void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
12446 assert(VM_Version::supports_evex(), "");
12447 assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
12448 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
12449 attributes.set_embedded_opmask_register_specifier(mask);
12450 attributes.set_is_evex_instruction();
12451 if (merge) {
12452 attributes.reset_is_clear_context();
12453 }
12454 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
12455 emit_int16((unsigned char)0x8A, (0xC0 | encode));
12456 }
12457
12458 #ifndef _LP64
12459
12460 void Assembler::incl(Register dst) {
12461 // Don't use it directly. Use MacroAssembler::incrementl() instead.
12462 emit_int8(0x40 | dst->encoding());
12463 }
12464
12465 void Assembler::lea(Register dst, Address src) {
12466 leal(dst, src);
12467 }
12468
12469 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
12470 InstructionMark im(this);
12471 emit_int8((unsigned char)0xC7);
12472 emit_operand(rax, dst, 4);
12473 emit_data((int)imm32, rspec, 0);
12474 }
12475
12476 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
12477 InstructionMark im(this);
12478 int encode = prefix_and_encode(dst->encoding());
12479 emit_int8((0xB8 | encode));
12480 emit_data((int)imm32, rspec, 0);
12481 }
12482
12483 void Assembler::popa() { // 32bit
12484 emit_int8(0x61);
12485 }
12486
12487 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
12488 InstructionMark im(this);
12489 emit_int8(0x68);
12490 emit_data(imm32, rspec, 0);
12491 }
12492
12493 void Assembler::pusha() { // 32bit
12494 emit_int8(0x60);
12495 }
12496
12497 #else // LP64
12498
12499 // 64bit only pieces of the assembler
12500
12501 // This should only be used by 64bit instructions that can use rip-relative
12502 // it cannot be used by instructions that want an immediate value.
12503
12504 // Determine whether an address is always reachable in rip-relative addressing mode
12505 // when accessed from the code cache.
12506 static bool is_always_reachable(address target, relocInfo::relocType reloc_type) {
12507 switch (reloc_type) {
12508 // This should be rip-relative and easily reachable.
12509 case relocInfo::internal_word_type: {
12510 return true;
12511 }
12512 // This should be rip-relative within the code cache and easily
12513 // reachable until we get huge code caches. (At which point
12514 // IC code is going to have issues).
12515 case relocInfo::virtual_call_type:
12516 case relocInfo::opt_virtual_call_type:
12517 case relocInfo::static_call_type:
12518 case relocInfo::static_stub_type: {
12519 return true;
12520 }
12521 case relocInfo::runtime_call_type:
12522 case relocInfo::external_word_type:
12523 case relocInfo::poll_return_type: // these are really external_word but need special
12524 case relocInfo::poll_type: { // relocs to identify them
12525 return CodeCache::contains(target);
12526 }
12527 default: {
12528 return false;
12529 }
12530 }
12531 }
12532
12533 // Determine whether an address is reachable in rip-relative addressing mode from the code cache.
12534 static bool is_reachable(address target, relocInfo::relocType reloc_type) {
12535 if (is_always_reachable(target, reloc_type)) {
12536 return true;
12537 }
12538 switch (reloc_type) {
12539 // None will force a 64bit literal to the code stream. Likely a placeholder
12540 // for something that will be patched later and we need to certain it will
12541 // always be reachable.
12542 case relocInfo::none: {
12543 return false;
12544 }
12545 case relocInfo::runtime_call_type:
12546 case relocInfo::external_word_type:
12547 case relocInfo::poll_return_type: // these are really external_word but need special
12548 case relocInfo::poll_type: { // relocs to identify them
12549 assert(!CodeCache::contains(target), "always reachable");
12550 if (ForceUnreachable) {
12551 return false; // stress the correction code
12552 }
12553 // For external_word_type/runtime_call_type if it is reachable from where we
12554 // are now (possibly a temp buffer) and where we might end up
12555 // anywhere in the code cache then we are always reachable.
12556 // This would have to change if we ever save/restore shared code to be more pessimistic.
12557 // Code buffer has to be allocated in the code cache, so check against
12558 // code cache boundaries cover that case.
12559 //
12560 // In rip-relative addressing mode, an effective address is formed by adding displacement
12561 // to the 64-bit RIP of the next instruction which is not known yet. Considering target address
12562 // is guaranteed to be outside of the code cache, checking against code cache boundaries is enough
12563 // to account for that.
12564 return Assembler::is_simm32(target - CodeCache::low_bound()) &&
12565 Assembler::is_simm32(target - CodeCache::high_bound());
12566 }
12567 default: {
12568 return false;
12569 }
12570 }
12571 }
12572
12573 bool Assembler::reachable(AddressLiteral adr) {
12574 assert(CodeCache::contains(pc()), "required");
12575 if (adr.is_lval()) {
12576 return false;
12577 }
12578 return is_reachable(adr.target(), adr.reloc());
12579 }
12580
12581 bool Assembler::always_reachable(AddressLiteral adr) {
12582 assert(CodeCache::contains(pc()), "required");
12583 if (adr.is_lval()) {
12584 return false;
12585 }
12586 return is_always_reachable(adr.target(), adr.reloc());
12587 }
12588
12589 void Assembler::emit_data64(jlong data,
12590 relocInfo::relocType rtype,
12591 int format) {
12592 if (rtype == relocInfo::none) {
12593 emit_int64(data);
12594 } else {
12595 emit_data64(data, Relocation::spec_simple(rtype), format);
12596 }
12597 }
12598
12599 void Assembler::emit_data64(jlong data,
12600 RelocationHolder const& rspec,
12601 int format) {
12602 assert(imm_operand == 0, "default format must be immediate in this file");
12603 assert(imm_operand == format, "must be immediate");
12604 assert(inst_mark() != nullptr, "must be inside InstructionMark");
12605 // Do not use AbstractAssembler::relocate, which is not intended for
12606 // embedded words. Instead, relocate to the enclosing instruction.
12607 code_section()->relocate(inst_mark(), rspec, format);
12608 #ifdef ASSERT
12609 check_relocation(rspec, format);
12610 #endif
12611 emit_int64(data);
12612 }
12613
12614 void Assembler::prefix(Register reg) {
12615 if (reg->encoding() >= 8) {
12616 prefix(REX_B);
12617 }
12618 }
12619
12620 void Assembler::prefix(Register dst, Register src, Prefix p) {
12621 if (src->encoding() >= 8) {
12622 p = (Prefix)(p | REX_B);
12623 }
12624 if (dst->encoding() >= 8) {
12625 p = (Prefix)(p | REX_R);
12626 }
12627 if (p != Prefix_EMPTY) {
12628 // do not generate an empty prefix
12629 prefix(p);
12630 }
12631 }
12632
12633 void Assembler::prefix(Register dst, Address adr, Prefix p) {
12634 if (adr.base_needs_rex()) {
12635 if (adr.index_needs_rex()) {
12636 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12637 } else {
12638 p = (Prefix)(p | REX_B);
12639 }
12640 } else {
12641 if (adr.index_needs_rex()) {
12642 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
12643 }
12644 }
12645 if (dst->encoding() >= 8) {
12646 p = (Prefix)(p | REX_R);
12647 }
12648 if (p != Prefix_EMPTY) {
12649 // do not generate an empty prefix
12650 prefix(p);
12651 }
12652 }
12653
12654 void Assembler::prefix(Address adr) {
12655 if (adr.base_needs_rex()) {
12656 if (adr.index_needs_rex()) {
12657 prefix(REX_XB);
12658 } else {
12659 prefix(REX_B);
12660 }
12661 } else {
12662 if (adr.index_needs_rex()) {
12663 prefix(REX_X);
12664 }
12665 }
12666 }
12667
12668 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
12669 if (reg->encoding() < 8) {
12670 if (adr.base_needs_rex()) {
12671 if (adr.index_needs_rex()) {
12672 prefix(REX_XB);
12673 } else {
12674 prefix(REX_B);
12675 }
12676 } else {
12677 if (adr.index_needs_rex()) {
12678 prefix(REX_X);
12679 } else if (byteinst && reg->encoding() >= 4) {
12680 prefix(REX);
12681 }
12682 }
12683 } else {
12684 if (adr.base_needs_rex()) {
12685 if (adr.index_needs_rex()) {
12686 prefix(REX_RXB);
12687 } else {
12688 prefix(REX_RB);
12689 }
12690 } else {
12691 if (adr.index_needs_rex()) {
12692 prefix(REX_RX);
12693 } else {
12694 prefix(REX_R);
12695 }
12696 }
12697 }
12698 }
12699
12700 void Assembler::prefix(Address adr, XMMRegister reg) {
12701 if (reg->encoding() < 8) {
12702 if (adr.base_needs_rex()) {
12703 if (adr.index_needs_rex()) {
12704 prefix(REX_XB);
12705 } else {
12706 prefix(REX_B);
12707 }
12708 } else {
12709 if (adr.index_needs_rex()) {
12710 prefix(REX_X);
12711 }
12712 }
12713 } else {
12714 if (adr.base_needs_rex()) {
12715 if (adr.index_needs_rex()) {
12716 prefix(REX_RXB);
12717 } else {
12718 prefix(REX_RB);
12719 }
12720 } else {
12721 if (adr.index_needs_rex()) {
12722 prefix(REX_RX);
12723 } else {
12724 prefix(REX_R);
12725 }
12726 }
12727 }
12728 }
12729
12730 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
12731 if (reg_enc >= 8) {
12732 prefix(REX_B);
12733 reg_enc -= 8;
12734 } else if (byteinst && reg_enc >= 4) {
12735 prefix(REX);
12736 }
12737 return reg_enc;
12738 }
12739
12740 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
12741 if (dst_enc < 8) {
12742 if (src_enc >= 8) {
12743 prefix(REX_B);
12744 src_enc -= 8;
12745 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
12746 prefix(REX);
12747 }
12748 } else {
12749 if (src_enc < 8) {
12750 prefix(REX_R);
12751 } else {
12752 prefix(REX_RB);
12753 src_enc -= 8;
12754 }
12755 dst_enc -= 8;
12756 }
12757 return dst_enc << 3 | src_enc;
12758 }
12759
12760 int8_t Assembler::get_prefixq(Address adr) {
12761 int8_t prfx = get_prefixq(adr, rax);
12762 assert(REX_W <= prfx && prfx <= REX_WXB, "must be");
12763 return prfx;
12764 }
12765
12766 int8_t Assembler::get_prefixq(Address adr, Register src) {
12767 int8_t prfx = (int8_t)(REX_W +
12768 ((int)adr.base_needs_rex()) +
12769 ((int)adr.index_needs_rex() << 1) +
12770 ((int)(src->encoding() >= 8) << 2));
12771 #ifdef ASSERT
12772 if (src->encoding() < 8) {
12773 if (adr.base_needs_rex()) {
12774 if (adr.index_needs_rex()) {
12775 assert(prfx == REX_WXB, "must be");
12776 } else {
12777 assert(prfx == REX_WB, "must be");
12778 }
12779 } else {
12780 if (adr.index_needs_rex()) {
12781 assert(prfx == REX_WX, "must be");
12782 } else {
12783 assert(prfx == REX_W, "must be");
12784 }
12785 }
12786 } else {
12787 if (adr.base_needs_rex()) {
12788 if (adr.index_needs_rex()) {
12789 assert(prfx == REX_WRXB, "must be");
12790 } else {
12791 assert(prfx == REX_WRB, "must be");
12792 }
12793 } else {
12794 if (adr.index_needs_rex()) {
12795 assert(prfx == REX_WRX, "must be");
12796 } else {
12797 assert(prfx == REX_WR, "must be");
12798 }
12799 }
12800 }
12801 #endif
12802 return prfx;
12803 }
12804
12805 void Assembler::prefixq(Address adr) {
12806 emit_int8(get_prefixq(adr));
12807 }
12808
12809 void Assembler::prefixq(Address adr, Register src) {
12810 emit_int8(get_prefixq(adr, src));
12811 }
12812
12813 void Assembler::prefixq(Address adr, XMMRegister src) {
12814 if (src->encoding() < 8) {
12815 if (adr.base_needs_rex()) {
12816 if (adr.index_needs_rex()) {
12817 prefix(REX_WXB);
12818 } else {
12819 prefix(REX_WB);
12820 }
12821 } else {
12822 if (adr.index_needs_rex()) {
12823 prefix(REX_WX);
12824 } else {
12825 prefix(REX_W);
12826 }
12827 }
12828 } else {
12829 if (adr.base_needs_rex()) {
12830 if (adr.index_needs_rex()) {
12831 prefix(REX_WRXB);
12832 } else {
12833 prefix(REX_WRB);
12834 }
12835 } else {
12836 if (adr.index_needs_rex()) {
12837 prefix(REX_WRX);
12838 } else {
12839 prefix(REX_WR);
12840 }
12841 }
12842 }
12843 }
12844
12845 int Assembler::prefixq_and_encode(int reg_enc) {
12846 if (reg_enc < 8) {
12847 prefix(REX_W);
12848 } else {
12849 prefix(REX_WB);
12850 reg_enc -= 8;
12851 }
12852 return reg_enc;
12853 }
12854
12855 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
12856 if (dst_enc < 8) {
12857 if (src_enc < 8) {
12858 prefix(REX_W);
12859 } else {
12860 prefix(REX_WB);
12861 src_enc -= 8;
12862 }
12863 } else {
12864 if (src_enc < 8) {
12865 prefix(REX_WR);
12866 } else {
12867 prefix(REX_WRB);
12868 src_enc -= 8;
12869 }
12870 dst_enc -= 8;
12871 }
12872 return dst_enc << 3 | src_enc;
12873 }
12874
12875 void Assembler::adcq(Register dst, int32_t imm32) {
12876 (void) prefixq_and_encode(dst->encoding());
12877 emit_arith(0x81, 0xD0, dst, imm32);
12878 }
12879
12880 void Assembler::adcq(Register dst, Address src) {
12881 InstructionMark im(this);
12882 emit_int16(get_prefixq(src, dst), 0x13);
12883 emit_operand(dst, src, 0);
12884 }
12885
12886 void Assembler::adcq(Register dst, Register src) {
12887 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12888 emit_arith(0x13, 0xC0, dst, src);
12889 }
12890
12891 void Assembler::addq(Address dst, int32_t imm32) {
12892 InstructionMark im(this);
12893 prefixq(dst);
12894 emit_arith_operand(0x81, rax, dst, imm32);
12895 }
12896
12897 void Assembler::addq(Address dst, Register src) {
12898 InstructionMark im(this);
12899 emit_int16(get_prefixq(dst, src), 0x01);
12900 emit_operand(src, dst, 0);
12901 }
12902
12903 void Assembler::addq(Register dst, int32_t imm32) {
12904 (void) prefixq_and_encode(dst->encoding());
12905 emit_arith(0x81, 0xC0, dst, imm32);
12906 }
12907
12908 void Assembler::addq(Register dst, Address src) {
12909 InstructionMark im(this);
12910 emit_int16(get_prefixq(src, dst), 0x03);
12911 emit_operand(dst, src, 0);
12912 }
12913
12914 void Assembler::addq(Register dst, Register src) {
12915 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12916 emit_arith(0x03, 0xC0, dst, src);
12917 }
12918
12919 void Assembler::adcxq(Register dst, Register src) {
12920 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12921 emit_int8(0x66);
12922 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12923 emit_int32(0x0F,
12924 0x38,
12925 (unsigned char)0xF6,
12926 (0xC0 | encode));
12927 }
12928
12929 void Assembler::adoxq(Register dst, Register src) {
12930 //assert(VM_Version::supports_adx(), "adx instructions not supported");
12931 emit_int8((unsigned char)0xF3);
12932 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12933 emit_int32(0x0F,
12934 0x38,
12935 (unsigned char)0xF6,
12936 (0xC0 | encode));
12937 }
12938
12939 void Assembler::andq(Address dst, int32_t imm32) {
12940 InstructionMark im(this);
12941 prefixq(dst);
12942 emit_arith_operand(0x81, as_Register(4), dst, imm32);
12943 }
12944
12945 void Assembler::andq(Register dst, int32_t imm32) {
12946 (void) prefixq_and_encode(dst->encoding());
12947 emit_arith(0x81, 0xE0, dst, imm32);
12948 }
12949
12950 void Assembler::andq(Register dst, Address src) {
12951 InstructionMark im(this);
12952 emit_int16(get_prefixq(src, dst), 0x23);
12953 emit_operand(dst, src, 0);
12954 }
12955
12956 void Assembler::andq(Register dst, Register src) {
12957 (void) prefixq_and_encode(dst->encoding(), src->encoding());
12958 emit_arith(0x23, 0xC0, dst, src);
12959 }
12960
12961 void Assembler::andq(Address dst, Register src) {
12962 InstructionMark im(this);
12963 emit_int16(get_prefixq(dst, src), 0x21);
12964 emit_operand(src, dst, 0);
12965 }
12966
12967 void Assembler::andnq(Register dst, Register src1, Register src2) {
12968 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12969 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12970 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12971 emit_int16((unsigned char)0xF2, (0xC0 | encode));
12972 }
12973
12974 void Assembler::andnq(Register dst, Register src1, Address src2) {
12975 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
12976 InstructionMark im(this);
12977 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
12978 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
12979 emit_int8((unsigned char)0xF2);
12980 emit_operand(dst, src2, 0);
12981 }
12982
12983 void Assembler::bsfq(Register dst, Register src) {
12984 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12985 emit_int24(0x0F, (unsigned char)0xBC, (0xC0 | encode));
12986 }
12987
12988 void Assembler::bsrq(Register dst, Register src) {
12989 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
12990 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
12991 }
12992
12993 void Assembler::bswapq(Register reg) {
12994 int encode = prefixq_and_encode(reg->encoding());
12995 emit_int16(0x0F, (0xC8 | encode));
12996 }
12997
12998 void Assembler::blsiq(Register dst, Register src) {
12999 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13000 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13001 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13002 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13003 }
13004
13005 void Assembler::blsiq(Register dst, Address src) {
13006 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13007 InstructionMark im(this);
13008 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13009 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13010 emit_int8((unsigned char)0xF3);
13011 emit_operand(rbx, src, 0);
13012 }
13013
13014 void Assembler::blsmskq(Register dst, Register src) {
13015 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13016 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13017 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13018 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13019 }
13020
13021 void Assembler::blsmskq(Register dst, Address src) {
13022 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13023 InstructionMark im(this);
13024 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13025 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13026 emit_int8((unsigned char)0xF3);
13027 emit_operand(rdx, src, 0);
13028 }
13029
13030 void Assembler::blsrq(Register dst, Register src) {
13031 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13032 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13033 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13034 emit_int16((unsigned char)0xF3, (0xC0 | encode));
13035 }
13036
13037 void Assembler::blsrq(Register dst, Address src) {
13038 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
13039 InstructionMark im(this);
13040 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13041 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
13042 emit_int8((unsigned char)0xF3);
13043 emit_operand(rcx, src, 0);
13044 }
13045
13046 void Assembler::cdqq() {
13047 emit_int16(REX_W, (unsigned char)0x99);
13048 }
13049
13050 void Assembler::clflush(Address adr) {
13051 assert(VM_Version::supports_clflush(), "should do");
13052 prefix(adr);
13053 emit_int16(0x0F, (unsigned char)0xAE);
13054 emit_operand(rdi, adr, 0);
13055 }
13056
13057 void Assembler::clflushopt(Address adr) {
13058 assert(VM_Version::supports_clflushopt(), "should do!");
13059 // adr should be base reg only with no index or offset
13060 assert(adr.index() == noreg, "index should be noreg");
13061 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13062 assert(adr.disp() == 0, "displacement should be 0");
13063 // instruction prefix is 0x66
13064 emit_int8(0x66);
13065 prefix(adr);
13066 // opcode family is 0x0F 0xAE
13067 emit_int16(0x0F, (unsigned char)0xAE);
13068 // extended opcode byte is 7 == rdi
13069 emit_operand(rdi, adr, 0);
13070 }
13071
13072 void Assembler::clwb(Address adr) {
13073 assert(VM_Version::supports_clwb(), "should do!");
13074 // adr should be base reg only with no index or offset
13075 assert(adr.index() == noreg, "index should be noreg");
13076 assert(adr.scale() == Address::no_scale, "scale should be no_scale");
13077 assert(adr.disp() == 0, "displacement should be 0");
13078 // instruction prefix is 0x66
13079 emit_int8(0x66);
13080 prefix(adr);
13081 // opcode family is 0x0f 0xAE
13082 emit_int16(0x0F, (unsigned char)0xAE);
13083 // extended opcode byte is 6 == rsi
13084 emit_operand(rsi, adr, 0);
13085 }
13086
13087 void Assembler::cmovq(Condition cc, Register dst, Register src) {
13088 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13089 emit_int24(0x0F, (0x40 | cc), (0xC0 | encode));
13090 }
13091
13092 void Assembler::cmovq(Condition cc, Register dst, Address src) {
13093 InstructionMark im(this);
13094 emit_int24(get_prefixq(src, dst), 0x0F, (0x40 | cc));
13095 emit_operand(dst, src, 0);
13096 }
13097
13098 void Assembler::cmpq(Address dst, int32_t imm32) {
13099 InstructionMark im(this);
13100 prefixq(dst);
13101 emit_arith_operand(0x81, as_Register(7), dst, imm32);
13102 }
13103
13104 void Assembler::cmpq(Register dst, int32_t imm32) {
13105 (void) prefixq_and_encode(dst->encoding());
13106 emit_arith(0x81, 0xF8, dst, imm32);
13107 }
13108
13109 void Assembler::cmpq(Address dst, Register src) {
13110 InstructionMark im(this);
13111 emit_int16(get_prefixq(dst, src), 0x39);
13112 emit_operand(src, dst, 0);
13113 }
13114
13115 void Assembler::cmpq(Register dst, Register src) {
13116 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13117 emit_arith(0x3B, 0xC0, dst, src);
13118 }
13119
13120 void Assembler::cmpq(Register dst, Address src) {
13121 InstructionMark im(this);
13122 emit_int16(get_prefixq(src, dst), 0x3B);
13123 emit_operand(dst, src, 0);
13124 }
13125
13126 void Assembler::cmpxchgq(Register reg, Address adr) {
13127 InstructionMark im(this);
13128 emit_int24(get_prefixq(adr, reg), 0x0F, (unsigned char)0xB1);
13129 emit_operand(reg, adr, 0);
13130 }
13131
13132 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
13133 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13134 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13135 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13136 emit_int16(0x2A, (0xC0 | encode));
13137 }
13138
13139 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
13140 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13141 InstructionMark im(this);
13142 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13143 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13144 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13145 emit_int8(0x2A);
13146 emit_operand(dst, src, 0);
13147 }
13148
13149 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
13150 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13151 InstructionMark im(this);
13152 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13153 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
13154 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13155 emit_int8(0x2A);
13156 emit_operand(dst, src, 0);
13157 }
13158
13159 void Assembler::cvttsd2siq(Register dst, Address src) {
13160 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13161 // F2 REX.W 0F 2C /r
13162 // CVTTSD2SI r64, xmm1/m64
13163 InstructionMark im(this);
13164 emit_int32((unsigned char)0xF2, REX_W, 0x0F, 0x2C);
13165 emit_operand(dst, src, 0);
13166 }
13167
13168 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
13169 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13170 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13171 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13172 emit_int16(0x2C, (0xC0 | encode));
13173 }
13174
13175 void Assembler::cvtsd2siq(Register dst, XMMRegister src) {
13176 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13177 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13178 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
13179 emit_int16(0x2D, (0xC0 | encode));
13180 }
13181
13182 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
13183 NOT_LP64(assert(VM_Version::supports_sse(), ""));
13184 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13185 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
13186 emit_int16(0x2C, (0xC0 | encode));
13187 }
13188
13189 void Assembler::decl(Register dst) {
13190 // Don't use it directly. Use MacroAssembler::decrementl() instead.
13191 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
13192 int encode = prefix_and_encode(dst->encoding());
13193 emit_int16((unsigned char)0xFF, (0xC8 | encode));
13194 }
13195
13196 void Assembler::decq(Register dst) {
13197 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13198 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13199 int encode = prefixq_and_encode(dst->encoding());
13200 emit_int16((unsigned char)0xFF, 0xC8 | encode);
13201 }
13202
13203 void Assembler::decq(Address dst) {
13204 // Don't use it directly. Use MacroAssembler::decrementq() instead.
13205 InstructionMark im(this);
13206 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13207 emit_operand(rcx, dst, 0);
13208 }
13209
13210 void Assembler::fxrstor(Address src) {
13211 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13212 emit_operand(as_Register(1), src, 0);
13213 }
13214
13215 void Assembler::xrstor(Address src) {
13216 emit_int24(get_prefixq(src), 0x0F, (unsigned char)0xAE);
13217 emit_operand(as_Register(5), src, 0);
13218 }
13219
13220 void Assembler::fxsave(Address dst) {
13221 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13222 emit_operand(as_Register(0), dst, 0);
13223 }
13224
13225 void Assembler::xsave(Address dst) {
13226 emit_int24(get_prefixq(dst), 0x0F, (unsigned char)0xAE);
13227 emit_operand(as_Register(4), dst, 0);
13228 }
13229
13230 void Assembler::idivq(Register src) {
13231 int encode = prefixq_and_encode(src->encoding());
13232 emit_int16((unsigned char)0xF7, (0xF8 | encode));
13233 }
13234
13235 void Assembler::divq(Register src) {
13236 int encode = prefixq_and_encode(src->encoding());
13237 emit_int16((unsigned char)0xF7, (0xF0 | encode));
13238 }
13239
13240 void Assembler::imulq(Register dst, Register src) {
13241 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13242 emit_int24(0x0F, (unsigned char)0xAF, (0xC0 | encode));
13243 }
13244
13245 void Assembler::imulq(Register src) {
13246 int encode = prefixq_and_encode(src->encoding());
13247 emit_int16((unsigned char)0xF7, (0xE8 | encode));
13248 }
13249
13250 void Assembler::imulq(Register dst, Address src, int32_t value) {
13251 InstructionMark im(this);
13252 prefixq(src, dst);
13253 if (is8bit(value)) {
13254 emit_int8((unsigned char)0x6B);
13255 emit_operand(dst, src, 1);
13256 emit_int8(value);
13257 } else {
13258 emit_int8((unsigned char)0x69);
13259 emit_operand(dst, src, 4);
13260 emit_int32(value);
13261 }
13262 }
13263
13264 void Assembler::imulq(Register dst, Register src, int value) {
13265 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13266 if (is8bit(value)) {
13267 emit_int24(0x6B, (0xC0 | encode), (value & 0xFF));
13268 } else {
13269 emit_int16(0x69, (0xC0 | encode));
13270 emit_int32(value);
13271 }
13272 }
13273
13274 void Assembler::imulq(Register dst, Address src) {
13275 InstructionMark im(this);
13276 emit_int24(get_prefixq(src, dst), 0x0F, (unsigned char)0xAF);
13277 emit_operand(dst, src, 0);
13278 }
13279
13280 void Assembler::incl(Register dst) {
13281 // Don't use it directly. Use MacroAssembler::incrementl() instead.
13282 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13283 int encode = prefix_and_encode(dst->encoding());
13284 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13285 }
13286
13287 void Assembler::incq(Register dst) {
13288 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13289 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
13290 int encode = prefixq_and_encode(dst->encoding());
13291 emit_int16((unsigned char)0xFF, (0xC0 | encode));
13292 }
13293
13294 void Assembler::incq(Address dst) {
13295 // Don't use it directly. Use MacroAssembler::incrementq() instead.
13296 InstructionMark im(this);
13297 emit_int16(get_prefixq(dst), (unsigned char)0xFF);
13298 emit_operand(rax, dst, 0);
13299 }
13300
13301 void Assembler::lea(Register dst, Address src) {
13302 leaq(dst, src);
13303 }
13304
13305 void Assembler::leaq(Register dst, Address src) {
13306 InstructionMark im(this);
13307 emit_int16(get_prefixq(src, dst), (unsigned char)0x8D);
13308 emit_operand(dst, src, 0);
13309 }
13310
13311 void Assembler::mov64(Register dst, int64_t imm64) {
13312 InstructionMark im(this);
13313 int encode = prefixq_and_encode(dst->encoding());
13314 emit_int8(0xB8 | encode);
13315 emit_int64(imm64);
13316 }
13317
13318 void Assembler::mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format) {
13319 InstructionMark im(this);
13320 int encode = prefixq_and_encode(dst->encoding());
13321 emit_int8(0xB8 | encode);
13322 emit_data64(imm64, rtype, format);
13323 }
13324
13325 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
13326 InstructionMark im(this);
13327 int encode = prefixq_and_encode(dst->encoding());
13328 emit_int8(0xB8 | encode);
13329 emit_data64(imm64, rspec);
13330 }
13331
13332 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
13333 InstructionMark im(this);
13334 int encode = prefix_and_encode(dst->encoding());
13335 emit_int8(0xB8 | encode);
13336 emit_data((int)imm32, rspec, narrow_oop_operand);
13337 }
13338
13339 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
13340 InstructionMark im(this);
13341 prefix(dst);
13342 emit_int8((unsigned char)0xC7);
13343 emit_operand(rax, dst, 4);
13344 emit_data((int)imm32, rspec, narrow_oop_operand);
13345 }
13346
13347 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
13348 InstructionMark im(this);
13349 int encode = prefix_and_encode(src1->encoding());
13350 emit_int16((unsigned char)0x81, (0xF8 | encode));
13351 emit_data((int)imm32, rspec, narrow_oop_operand);
13352 }
13353
13354 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
13355 InstructionMark im(this);
13356 prefix(src1);
13357 emit_int8((unsigned char)0x81);
13358 emit_operand(rax, src1, 4);
13359 emit_data((int)imm32, rspec, narrow_oop_operand);
13360 }
13361
13362 void Assembler::lzcntq(Register dst, Register src) {
13363 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13364 emit_int8((unsigned char)0xF3);
13365 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13366 emit_int24(0x0F, (unsigned char)0xBD, (0xC0 | encode));
13367 }
13368
13369 void Assembler::lzcntq(Register dst, Address src) {
13370 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
13371 InstructionMark im(this);
13372 emit_int8((unsigned char)0xF3);
13373 prefixq(src, dst);
13374 emit_int16(0x0F, (unsigned char)0xBD);
13375 emit_operand(dst, src, 0);
13376 }
13377
13378 void Assembler::movdq(XMMRegister dst, Register src) {
13379 // table D-1 says MMX/SSE2
13380 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13381 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13382 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13383 emit_int16(0x6E, (0xC0 | encode));
13384 }
13385
13386 void Assembler::movdq(Register dst, XMMRegister src) {
13387 // table D-1 says MMX/SSE2
13388 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
13389 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
13390 // swap src/dst to get correct prefix
13391 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
13392 emit_int16(0x7E,
13393 (0xC0 | encode));
13394 }
13395
13396 void Assembler::movq(Register dst, Register src) {
13397 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13398 emit_int16((unsigned char)0x8B,
13399 (0xC0 | encode));
13400 }
13401
13402 void Assembler::movq(Register dst, Address src) {
13403 InstructionMark im(this);
13404 emit_int16(get_prefixq(src, dst), (unsigned char)0x8B);
13405 emit_operand(dst, src, 0);
13406 }
13407
13408 void Assembler::movq(Address dst, Register src) {
13409 InstructionMark im(this);
13410 emit_int16(get_prefixq(dst, src), (unsigned char)0x89);
13411 emit_operand(src, dst, 0);
13412 }
13413
13414 void Assembler::movq(Address dst, int32_t imm32) {
13415 InstructionMark im(this);
13416 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13417 emit_operand(as_Register(0), dst, 4);
13418 emit_int32(imm32);
13419 }
13420
13421 void Assembler::movq(Register dst, int32_t imm32) {
13422 int encode = prefixq_and_encode(dst->encoding());
13423 emit_int16((unsigned char)0xC7, (0xC0 | encode));
13424 emit_int32(imm32);
13425 }
13426
13427 void Assembler::movsbq(Register dst, Address src) {
13428 InstructionMark im(this);
13429 emit_int24(get_prefixq(src, dst),
13430 0x0F,
13431 (unsigned char)0xBE);
13432 emit_operand(dst, src, 0);
13433 }
13434
13435 void Assembler::movsbq(Register dst, Register src) {
13436 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13437 emit_int24(0x0F, (unsigned char)0xBE, (0xC0 | encode));
13438 }
13439
13440 void Assembler::movslq(Register dst, int32_t imm32) {
13441 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
13442 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
13443 // as a result we shouldn't use until tested at runtime...
13444 ShouldNotReachHere();
13445 InstructionMark im(this);
13446 int encode = prefixq_and_encode(dst->encoding());
13447 emit_int8(0xC7 | encode);
13448 emit_int32(imm32);
13449 }
13450
13451 void Assembler::movslq(Address dst, int32_t imm32) {
13452 assert(is_simm32(imm32), "lost bits");
13453 InstructionMark im(this);
13454 emit_int16(get_prefixq(dst), (unsigned char)0xC7);
13455 emit_operand(rax, dst, 4);
13456 emit_int32(imm32);
13457 }
13458
13459 void Assembler::movslq(Register dst, Address src) {
13460 InstructionMark im(this);
13461 emit_int16(get_prefixq(src, dst), 0x63);
13462 emit_operand(dst, src, 0);
13463 }
13464
13465 void Assembler::movslq(Register dst, Register src) {
13466 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13467 emit_int16(0x63, (0xC0 | encode));
13468 }
13469
13470 void Assembler::movswq(Register dst, Address src) {
13471 InstructionMark im(this);
13472 emit_int24(get_prefixq(src, dst),
13473 0x0F,
13474 (unsigned char)0xBF);
13475 emit_operand(dst, src, 0);
13476 }
13477
13478 void Assembler::movswq(Register dst, Register src) {
13479 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13480 emit_int24(0x0F, (unsigned char)0xBF, (0xC0 | encode));
13481 }
13482
13483 void Assembler::movzbq(Register dst, Address src) {
13484 InstructionMark im(this);
13485 emit_int24(get_prefixq(src, dst),
13486 0x0F,
13487 (unsigned char)0xB6);
13488 emit_operand(dst, src, 0);
13489 }
13490
13491 void Assembler::movzbq(Register dst, Register src) {
13492 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13493 emit_int24(0x0F, (unsigned char)0xB6, (0xC0 | encode));
13494 }
13495
13496 void Assembler::movzwq(Register dst, Address src) {
13497 InstructionMark im(this);
13498 emit_int24(get_prefixq(src, dst),
13499 0x0F,
13500 (unsigned char)0xB7);
13501 emit_operand(dst, src, 0);
13502 }
13503
13504 void Assembler::movzwq(Register dst, Register src) {
13505 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13506 emit_int24(0x0F, (unsigned char)0xB7, (0xC0 | encode));
13507 }
13508
13509 void Assembler::mulq(Address src) {
13510 InstructionMark im(this);
13511 emit_int16(get_prefixq(src), (unsigned char)0xF7);
13512 emit_operand(rsp, src, 0);
13513 }
13514
13515 void Assembler::mulq(Register src) {
13516 int encode = prefixq_and_encode(src->encoding());
13517 emit_int16((unsigned char)0xF7, (0xE0 | encode));
13518 }
13519
13520 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
13521 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13522 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13523 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
13524 emit_int16((unsigned char)0xF6, (0xC0 | encode));
13525 }
13526
13527 void Assembler::negq(Register dst) {
13528 int encode = prefixq_and_encode(dst->encoding());
13529 emit_int16((unsigned char)0xF7, (0xD8 | encode));
13530 }
13531
13532 void Assembler::negq(Address dst) {
13533 InstructionMark im(this);
13534 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
13535 emit_operand(as_Register(3), dst, 0);
13536 }
13537
13538 void Assembler::notq(Register dst) {
13539 int encode = prefixq_and_encode(dst->encoding());
13540 emit_int16((unsigned char)0xF7, (0xD0 | encode));
13541 }
13542
13543 void Assembler::btsq(Address dst, int imm8) {
13544 assert(isByte(imm8), "not a byte");
13545 InstructionMark im(this);
13546 emit_int24(get_prefixq(dst),
13547 0x0F,
13548 (unsigned char)0xBA);
13549 emit_operand(rbp /* 5 */, dst, 1);
13550 emit_int8(imm8);
13551 }
13552
13553 void Assembler::btrq(Address dst, int imm8) {
13554 assert(isByte(imm8), "not a byte");
13555 InstructionMark im(this);
13556 emit_int24(get_prefixq(dst),
13557 0x0F,
13558 (unsigned char)0xBA);
13559 emit_operand(rsi /* 6 */, dst, 1);
13560 emit_int8(imm8);
13561 }
13562
13563 void Assembler::orq(Address dst, int32_t imm32) {
13564 InstructionMark im(this);
13565 prefixq(dst);
13566 emit_arith_operand(0x81, as_Register(1), dst, imm32);
13567 }
13568
13569 void Assembler::orq(Address dst, Register src) {
13570 InstructionMark im(this);
13571 emit_int16(get_prefixq(dst, src), (unsigned char)0x09);
13572 emit_operand(src, dst, 0);
13573 }
13574
13575 void Assembler::orq(Register dst, int32_t imm32) {
13576 (void) prefixq_and_encode(dst->encoding());
13577 emit_arith(0x81, 0xC8, dst, imm32);
13578 }
13579
13580 void Assembler::orq_imm32(Register dst, int32_t imm32) {
13581 (void) prefixq_and_encode(dst->encoding());
13582 emit_arith_imm32(0x81, 0xC8, dst, imm32);
13583 }
13584
13585 void Assembler::orq(Register dst, Address src) {
13586 InstructionMark im(this);
13587 emit_int16(get_prefixq(src, dst), 0x0B);
13588 emit_operand(dst, src, 0);
13589 }
13590
13591 void Assembler::orq(Register dst, Register src) {
13592 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13593 emit_arith(0x0B, 0xC0, dst, src);
13594 }
13595
13596 void Assembler::popcntq(Register dst, Address src) {
13597 assert(VM_Version::supports_popcnt(), "must support");
13598 InstructionMark im(this);
13599 emit_int32((unsigned char)0xF3,
13600 get_prefixq(src, dst),
13601 0x0F,
13602 (unsigned char)0xB8);
13603 emit_operand(dst, src, 0);
13604 }
13605
13606 void Assembler::popcntq(Register dst, Register src) {
13607 assert(VM_Version::supports_popcnt(), "must support");
13608 emit_int8((unsigned char)0xF3);
13609 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
13610 emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
13611 }
13612
13613 void Assembler::popq(Address dst) {
13614 InstructionMark im(this);
13615 emit_int16(get_prefixq(dst), (unsigned char)0x8F);
13616 emit_operand(rax, dst, 0);
13617 }
13618
13619 void Assembler::popq(Register dst) {
13620 emit_int8((unsigned char)0x58 | dst->encoding());
13621 }
13622
13623 // Precomputable: popa, pusha, vzeroupper
13624
13625 // The result of these routines are invariant from one invocation to another
13626 // invocation for the duration of a run. Caching the result on bootstrap
13627 // and copying it out on subsequent invocations can thus be beneficial
13628 static bool precomputed = false;
13629
13630 static u_char* popa_code = nullptr;
13631 static int popa_len = 0;
13632
13633 static u_char* pusha_code = nullptr;
13634 static int pusha_len = 0;
13635
13636 static u_char* vzup_code = nullptr;
13637 static int vzup_len = 0;
13638
13639 void Assembler::precompute_instructions() {
13640 assert(!Universe::is_fully_initialized(), "must still be single threaded");
13641 guarantee(!precomputed, "only once");
13642 precomputed = true;
13643 ResourceMark rm;
13644
13645 // Make a temporary buffer big enough for the routines we're capturing
13646 int size = 256;
13647 char* tmp_code = NEW_RESOURCE_ARRAY(char, size);
13648 CodeBuffer buffer((address)tmp_code, size);
13649 MacroAssembler masm(&buffer);
13650
13651 address begin_popa = masm.code_section()->end();
13652 masm.popa_uncached();
13653 address end_popa = masm.code_section()->end();
13654 masm.pusha_uncached();
13655 address end_pusha = masm.code_section()->end();
13656 masm.vzeroupper_uncached();
13657 address end_vzup = masm.code_section()->end();
13658
13659 // Save the instructions to permanent buffers.
13660 popa_len = (int)(end_popa - begin_popa);
13661 popa_code = NEW_C_HEAP_ARRAY(u_char, popa_len, mtInternal);
13662 memcpy(popa_code, begin_popa, popa_len);
13663
13664 pusha_len = (int)(end_pusha - end_popa);
13665 pusha_code = NEW_C_HEAP_ARRAY(u_char, pusha_len, mtInternal);
13666 memcpy(pusha_code, end_popa, pusha_len);
13667
13668 vzup_len = (int)(end_vzup - end_pusha);
13669 if (vzup_len > 0) {
13670 vzup_code = NEW_C_HEAP_ARRAY(u_char, vzup_len, mtInternal);
13671 memcpy(vzup_code, end_pusha, vzup_len);
13672 } else {
13673 vzup_code = pusha_code; // dummy
13674 }
13675
13676 assert(masm.code()->total_oop_size() == 0 &&
13677 masm.code()->total_metadata_size() == 0 &&
13678 masm.code()->total_relocation_size() == 0,
13679 "pre-computed code can't reference oops, metadata or contain relocations");
13680 }
13681
13682 static void emit_copy(CodeSection* code_section, u_char* src, int src_len) {
13683 assert(src != nullptr, "code to copy must have been pre-computed");
13684 assert(code_section->limit() - code_section->end() > src_len, "code buffer not large enough");
13685 address end = code_section->end();
13686 memcpy(end, src, src_len);
13687 code_section->set_end(end + src_len);
13688 }
13689
13690 void Assembler::popa() { // 64bit
13691 emit_copy(code_section(), popa_code, popa_len);
13692 }
13693
13694 void Assembler::popa_uncached() { // 64bit
13695 movq(r15, Address(rsp, 0));
13696 movq(r14, Address(rsp, wordSize));
13697 movq(r13, Address(rsp, 2 * wordSize));
13698 movq(r12, Address(rsp, 3 * wordSize));
13699 movq(r11, Address(rsp, 4 * wordSize));
13700 movq(r10, Address(rsp, 5 * wordSize));
13701 movq(r9, Address(rsp, 6 * wordSize));
13702 movq(r8, Address(rsp, 7 * wordSize));
13703 movq(rdi, Address(rsp, 8 * wordSize));
13704 movq(rsi, Address(rsp, 9 * wordSize));
13705 movq(rbp, Address(rsp, 10 * wordSize));
13706 // Skip rsp as it is restored automatically to the value
13707 // before the corresponding pusha when popa is done.
13708 movq(rbx, Address(rsp, 12 * wordSize));
13709 movq(rdx, Address(rsp, 13 * wordSize));
13710 movq(rcx, Address(rsp, 14 * wordSize));
13711 movq(rax, Address(rsp, 15 * wordSize));
13712
13713 addq(rsp, 16 * wordSize);
13714 }
13715
13716 // Does not actually store the value of rsp on the stack.
13717 // The slot for rsp just contains an arbitrary value.
13718 void Assembler::pusha() { // 64bit
13719 emit_copy(code_section(), pusha_code, pusha_len);
13720 }
13721
13722 // Does not actually store the value of rsp on the stack.
13723 // The slot for rsp just contains an arbitrary value.
13724 void Assembler::pusha_uncached() { // 64bit
13725 subq(rsp, 16 * wordSize);
13726
13727 movq(Address(rsp, 15 * wordSize), rax);
13728 movq(Address(rsp, 14 * wordSize), rcx);
13729 movq(Address(rsp, 13 * wordSize), rdx);
13730 movq(Address(rsp, 12 * wordSize), rbx);
13731 // Skip rsp as the value is normally not used. There are a few places where
13732 // the original value of rsp needs to be known but that can be computed
13733 // from the value of rsp immediately after pusha (rsp + 16 * wordSize).
13734 movq(Address(rsp, 10 * wordSize), rbp);
13735 movq(Address(rsp, 9 * wordSize), rsi);
13736 movq(Address(rsp, 8 * wordSize), rdi);
13737 movq(Address(rsp, 7 * wordSize), r8);
13738 movq(Address(rsp, 6 * wordSize), r9);
13739 movq(Address(rsp, 5 * wordSize), r10);
13740 movq(Address(rsp, 4 * wordSize), r11);
13741 movq(Address(rsp, 3 * wordSize), r12);
13742 movq(Address(rsp, 2 * wordSize), r13);
13743 movq(Address(rsp, wordSize), r14);
13744 movq(Address(rsp, 0), r15);
13745 }
13746
13747 void Assembler::vzeroupper() {
13748 emit_copy(code_section(), vzup_code, vzup_len);
13749 }
13750
13751 void Assembler::vzeroall() {
13752 assert(VM_Version::supports_avx(), "requires AVX");
13753 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13754 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
13755 emit_int8(0x77);
13756 }
13757
13758 void Assembler::pushq(Address src) {
13759 InstructionMark im(this);
13760 emit_int16(get_prefixq(src), (unsigned char)0xFF);
13761 emit_operand(rsi, src, 0);
13762 }
13763
13764 void Assembler::rclq(Register dst, int imm8) {
13765 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13766 int encode = prefixq_and_encode(dst->encoding());
13767 if (imm8 == 1) {
13768 emit_int16((unsigned char)0xD1, (0xD0 | encode));
13769 } else {
13770 emit_int24((unsigned char)0xC1, (0xD0 | encode), imm8);
13771 }
13772 }
13773
13774 void Assembler::rcrq(Register dst, int imm8) {
13775 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13776 int encode = prefixq_and_encode(dst->encoding());
13777 if (imm8 == 1) {
13778 emit_int16((unsigned char)0xD1, (0xD8 | encode));
13779 } else {
13780 emit_int24((unsigned char)0xC1, (0xD8 | encode), imm8);
13781 }
13782 }
13783
13784 void Assembler::rorxl(Register dst, Register src, int imm8) {
13785 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13786 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13787 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13788 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13789 }
13790
13791 void Assembler::rorxl(Register dst, Address src, int imm8) {
13792 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13793 InstructionMark im(this);
13794 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13795 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13796 emit_int8((unsigned char)0xF0);
13797 emit_operand(dst, src, 1);
13798 emit_int8(imm8);
13799 }
13800
13801 void Assembler::rorxq(Register dst, Register src, int imm8) {
13802 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13803 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13804 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13805 emit_int24((unsigned char)0xF0, (0xC0 | encode), imm8);
13806 }
13807
13808 void Assembler::rorxq(Register dst, Address src, int imm8) {
13809 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
13810 InstructionMark im(this);
13811 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
13812 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
13813 emit_int8((unsigned char)0xF0);
13814 emit_operand(dst, src, 1);
13815 emit_int8(imm8);
13816 }
13817
13818 #ifdef _LP64
13819 void Assembler::salq(Address dst, int imm8) {
13820 InstructionMark im(this);
13821 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13822 if (imm8 == 1) {
13823 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13824 emit_operand(as_Register(4), dst, 0);
13825 }
13826 else {
13827 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13828 emit_operand(as_Register(4), dst, 1);
13829 emit_int8(imm8);
13830 }
13831 }
13832
13833 void Assembler::salq(Address dst) {
13834 InstructionMark im(this);
13835 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13836 emit_operand(as_Register(4), dst, 0);
13837 }
13838
13839 void Assembler::salq(Register dst, int imm8) {
13840 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13841 int encode = prefixq_and_encode(dst->encoding());
13842 if (imm8 == 1) {
13843 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13844 } else {
13845 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13846 }
13847 }
13848
13849 void Assembler::salq(Register dst) {
13850 int encode = prefixq_and_encode(dst->encoding());
13851 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13852 }
13853
13854 void Assembler::sarq(Address dst, int imm8) {
13855 InstructionMark im(this);
13856 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13857 if (imm8 == 1) {
13858 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13859 emit_operand(as_Register(7), dst, 0);
13860 }
13861 else {
13862 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13863 emit_operand(as_Register(7), dst, 1);
13864 emit_int8(imm8);
13865 }
13866 }
13867
13868 void Assembler::sarq(Address dst) {
13869 InstructionMark im(this);
13870 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13871 emit_operand(as_Register(7), dst, 0);
13872 }
13873
13874 void Assembler::sarq(Register dst, int imm8) {
13875 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13876 int encode = prefixq_and_encode(dst->encoding());
13877 if (imm8 == 1) {
13878 emit_int16((unsigned char)0xD1, (0xF8 | encode));
13879 } else {
13880 emit_int24((unsigned char)0xC1, (0xF8 | encode), imm8);
13881 }
13882 }
13883
13884 void Assembler::sarq(Register dst) {
13885 int encode = prefixq_and_encode(dst->encoding());
13886 emit_int16((unsigned char)0xD3, (0xF8 | encode));
13887 }
13888 #endif
13889
13890 void Assembler::sbbq(Address dst, int32_t imm32) {
13891 InstructionMark im(this);
13892 prefixq(dst);
13893 emit_arith_operand(0x81, rbx, dst, imm32);
13894 }
13895
13896 void Assembler::sbbq(Register dst, int32_t imm32) {
13897 (void) prefixq_and_encode(dst->encoding());
13898 emit_arith(0x81, 0xD8, dst, imm32);
13899 }
13900
13901 void Assembler::sbbq(Register dst, Address src) {
13902 InstructionMark im(this);
13903 emit_int16(get_prefixq(src, dst), 0x1B);
13904 emit_operand(dst, src, 0);
13905 }
13906
13907 void Assembler::sbbq(Register dst, Register src) {
13908 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13909 emit_arith(0x1B, 0xC0, dst, src);
13910 }
13911
13912 void Assembler::shlq(Register dst, int imm8) {
13913 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13914 int encode = prefixq_and_encode(dst->encoding());
13915 if (imm8 == 1) {
13916 emit_int16((unsigned char)0xD1, (0xE0 | encode));
13917 } else {
13918 emit_int24((unsigned char)0xC1, (0xE0 | encode), imm8);
13919 }
13920 }
13921
13922 void Assembler::shlq(Register dst) {
13923 int encode = prefixq_and_encode(dst->encoding());
13924 emit_int16((unsigned char)0xD3, (0xE0 | encode));
13925 }
13926
13927 void Assembler::shrq(Register dst, int imm8) {
13928 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13929 int encode = prefixq_and_encode(dst->encoding());
13930 if (imm8 == 1) {
13931 emit_int16((unsigned char)0xD1, (0xE8 | encode));
13932 }
13933 else {
13934 emit_int24((unsigned char)0xC1, (0xE8 | encode), imm8);
13935 }
13936 }
13937
13938 void Assembler::shrq(Register dst) {
13939 int encode = prefixq_and_encode(dst->encoding());
13940 emit_int16((unsigned char)0xD3, 0xE8 | encode);
13941 }
13942
13943 void Assembler::shrq(Address dst) {
13944 InstructionMark im(this);
13945 emit_int16(get_prefixq(dst), (unsigned char)0xD3);
13946 emit_operand(as_Register(5), dst, 0);
13947 }
13948
13949 void Assembler::shrq(Address dst, int imm8) {
13950 InstructionMark im(this);
13951 assert(isShiftCount(imm8 >> 1), "illegal shift count");
13952 if (imm8 == 1) {
13953 emit_int16(get_prefixq(dst), (unsigned char)0xD1);
13954 emit_operand(as_Register(5), dst, 0);
13955 }
13956 else {
13957 emit_int16(get_prefixq(dst), (unsigned char)0xC1);
13958 emit_operand(as_Register(5), dst, 1);
13959 emit_int8(imm8);
13960 }
13961 }
13962
13963 void Assembler::subq(Address dst, int32_t imm32) {
13964 InstructionMark im(this);
13965 prefixq(dst);
13966 emit_arith_operand(0x81, rbp, dst, imm32);
13967 }
13968
13969 void Assembler::subq(Address dst, Register src) {
13970 InstructionMark im(this);
13971 emit_int16(get_prefixq(dst, src), 0x29);
13972 emit_operand(src, dst, 0);
13973 }
13974
13975 void Assembler::subq(Register dst, int32_t imm32) {
13976 (void) prefixq_and_encode(dst->encoding());
13977 emit_arith(0x81, 0xE8, dst, imm32);
13978 }
13979
13980 // Force generation of a 4 byte immediate value even if it fits into 8bit
13981 void Assembler::subq_imm32(Register dst, int32_t imm32) {
13982 (void) prefixq_and_encode(dst->encoding());
13983 emit_arith_imm32(0x81, 0xE8, dst, imm32);
13984 }
13985
13986 void Assembler::subq(Register dst, Address src) {
13987 InstructionMark im(this);
13988 emit_int16(get_prefixq(src, dst), 0x2B);
13989 emit_operand(dst, src, 0);
13990 }
13991
13992 void Assembler::subq(Register dst, Register src) {
13993 (void) prefixq_and_encode(dst->encoding(), src->encoding());
13994 emit_arith(0x2B, 0xC0, dst, src);
13995 }
13996
13997 void Assembler::testq(Address dst, int32_t imm32) {
13998 InstructionMark im(this);
13999 emit_int16(get_prefixq(dst), (unsigned char)0xF7);
14000 emit_operand(as_Register(0), dst, 4);
14001 emit_int32(imm32);
14002 }
14003
14004 void Assembler::testq(Register dst, int32_t imm32) {
14005 // not using emit_arith because test
14006 // doesn't support sign-extension of
14007 // 8bit operands
14008 if (dst == rax) {
14009 prefix(REX_W);
14010 emit_int8((unsigned char)0xA9);
14011 emit_int32(imm32);
14012 } else {
14013 int encode = dst->encoding();
14014 encode = prefixq_and_encode(encode);
14015 emit_int16((unsigned char)0xF7, (0xC0 | encode));
14016 emit_int32(imm32);
14017 }
14018 }
14019
14020 void Assembler::testq(Register dst, Register src) {
14021 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14022 emit_arith(0x85, 0xC0, dst, src);
14023 }
14024
14025 void Assembler::testq(Register dst, Address src) {
14026 InstructionMark im(this);
14027 emit_int16(get_prefixq(src, dst), (unsigned char)0x85);
14028 emit_operand(dst, src, 0);
14029 }
14030
14031 void Assembler::xaddq(Address dst, Register src) {
14032 InstructionMark im(this);
14033 emit_int24(get_prefixq(dst, src), 0x0F, (unsigned char)0xC1);
14034 emit_operand(src, dst, 0);
14035 }
14036
14037 void Assembler::xchgq(Register dst, Address src) {
14038 InstructionMark im(this);
14039 emit_int16(get_prefixq(src, dst), (unsigned char)0x87);
14040 emit_operand(dst, src, 0);
14041 }
14042
14043 void Assembler::xchgq(Register dst, Register src) {
14044 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
14045 emit_int16((unsigned char)0x87, (0xc0 | encode));
14046 }
14047
14048 void Assembler::xorq(Register dst, Register src) {
14049 (void) prefixq_and_encode(dst->encoding(), src->encoding());
14050 emit_arith(0x33, 0xC0, dst, src);
14051 }
14052
14053 void Assembler::xorq(Register dst, Address src) {
14054 InstructionMark im(this);
14055 emit_int16(get_prefixq(src, dst), 0x33);
14056 emit_operand(dst, src, 0);
14057 }
14058
14059 void Assembler::xorq(Register dst, int32_t imm32) {
14060 (void) prefixq_and_encode(dst->encoding());
14061 emit_arith(0x81, 0xF0, dst, imm32);
14062 }
14063
14064 void Assembler::xorq(Address dst, int32_t imm32) {
14065 InstructionMark im(this);
14066 prefixq(dst);
14067 emit_arith_operand(0x81, as_Register(6), dst, imm32);
14068 }
14069
14070 void Assembler::xorq(Address dst, Register src) {
14071 InstructionMark im(this);
14072 emit_int16(get_prefixq(dst, src), 0x31);
14073 emit_operand(src, dst, 0);
14074 }
14075
14076 #endif // !LP64
14077
14078 void InstructionAttr::set_address_attributes(int tuple_type, int input_size_in_bits) {
14079 if (VM_Version::supports_evex()) {
14080 _tuple_type = tuple_type;
14081 _input_size_in_bits = input_size_in_bits;
14082 }
14083 }