1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
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23 */
24
25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
26 #define CPU_X86_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "utilities/powerOfTwo.hpp"
30
31 // Contains all the definitions needed for x86 assembly code generation.
32
33 // Calling convention
34 class Argument {
35 public:
36 enum {
37 #ifdef _LP64
38 #ifdef _WIN64
39 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
40 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
41 n_int_register_returns_c = 1, // rax
42 n_float_register_returns_c = 1, // xmm0
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 n_int_register_returns_c = 2, // rax, rdx
47 n_float_register_returns_c = 2, // xmm0, xmm1
48 #endif // _WIN64
49 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
50 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
51 #else
52 n_register_parameters = 0, // 0 registers used to pass arguments
53 n_int_register_parameters_j = 0,
54 n_float_register_parameters_j = 0
55 #endif // _LP64
56 };
57 };
58
59
60 #ifdef _LP64
61 // Symbolically name the register arguments used by the c calling convention.
62 // Windows is different from linux/solaris. So much for standards...
63
64 #ifdef _WIN64
65
66 constexpr Register c_rarg0 = rcx;
67 constexpr Register c_rarg1 = rdx;
68 constexpr Register c_rarg2 = r8;
69 constexpr Register c_rarg3 = r9;
70
71 constexpr XMMRegister c_farg0 = xmm0;
72 constexpr XMMRegister c_farg1 = xmm1;
73 constexpr XMMRegister c_farg2 = xmm2;
74 constexpr XMMRegister c_farg3 = xmm3;
75
76 #else
77
78 constexpr Register c_rarg0 = rdi;
79 constexpr Register c_rarg1 = rsi;
80 constexpr Register c_rarg2 = rdx;
81 constexpr Register c_rarg3 = rcx;
82 constexpr Register c_rarg4 = r8;
83 constexpr Register c_rarg5 = r9;
84
85 constexpr XMMRegister c_farg0 = xmm0;
86 constexpr XMMRegister c_farg1 = xmm1;
87 constexpr XMMRegister c_farg2 = xmm2;
88 constexpr XMMRegister c_farg3 = xmm3;
89 constexpr XMMRegister c_farg4 = xmm4;
90 constexpr XMMRegister c_farg5 = xmm5;
91 constexpr XMMRegister c_farg6 = xmm6;
92 constexpr XMMRegister c_farg7 = xmm7;
93
94 #endif // _WIN64
95
96 // Symbolically name the register arguments used by the Java calling convention.
97 // We have control over the convention for java so we can do what we please.
98 // What pleases us is to offset the java calling convention so that when
99 // we call a suitable jni method the arguments are lined up and we don't
100 // have to do little shuffling. A suitable jni method is non-static and a
101 // small number of arguments (two fewer args on windows)
102 //
103 // |-------------------------------------------------------|
104 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
105 // |-------------------------------------------------------|
106 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
107 // | rdi rsi rdx rcx r8 r9 | solaris/linux
108 // |-------------------------------------------------------|
109 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
110 // |-------------------------------------------------------|
111
112 constexpr Register j_rarg0 = c_rarg1;
113 constexpr Register j_rarg1 = c_rarg2;
114 constexpr Register j_rarg2 = c_rarg3;
115 // Windows runs out of register args here
116 #ifdef _WIN64
117 constexpr Register j_rarg3 = rdi;
118 constexpr Register j_rarg4 = rsi;
119 #else
120 constexpr Register j_rarg3 = c_rarg4;
121 constexpr Register j_rarg4 = c_rarg5;
122 #endif /* _WIN64 */
123 constexpr Register j_rarg5 = c_rarg0;
124
125 constexpr XMMRegister j_farg0 = xmm0;
126 constexpr XMMRegister j_farg1 = xmm1;
127 constexpr XMMRegister j_farg2 = xmm2;
128 constexpr XMMRegister j_farg3 = xmm3;
129 constexpr XMMRegister j_farg4 = xmm4;
130 constexpr XMMRegister j_farg5 = xmm5;
131 constexpr XMMRegister j_farg6 = xmm6;
132 constexpr XMMRegister j_farg7 = xmm7;
133
134 constexpr Register rscratch1 = r10; // volatile
135 constexpr Register rscratch2 = r11; // volatile
136
137 constexpr Register r12_heapbase = r12; // callee-saved
138 constexpr Register r15_thread = r15; // callee-saved
139
140 #else
141 // rscratch1 will appear in 32bit code that is dead but of course must compile
142 // Using noreg ensures if the dead code is incorrectly live and executed it
143 // will cause an assertion failure
144 #define rscratch1 noreg
145 #define rscratch2 noreg
146
147 #endif // _LP64
148
149 // JSR 292
150 // On x86, the SP does not have to be saved when invoking method handle intrinsics
151 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
152 constexpr Register rbp_mh_SP_save = noreg;
153
154 // Address is an abstraction used to represent a memory location
155 // using any of the amd64 addressing modes with one object.
156 //
157 // Note: A register location is represented via a Register, not
158 // via an address for efficiency & simplicity reasons.
159
160 class ArrayAddress;
161
162 class Address {
163 public:
164 enum ScaleFactor {
165 no_scale = -1,
166 times_1 = 0,
167 times_2 = 1,
168 times_4 = 2,
169 times_8 = 3,
170 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
171 };
172 static ScaleFactor times(int size) {
173 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
174 if (size == 8) return times_8;
175 if (size == 4) return times_4;
176 if (size == 2) return times_2;
177 return times_1;
178 }
179 static int scale_size(ScaleFactor scale) {
180 assert(scale != no_scale, "");
181 assert(((1 << (int)times_1) == 1 &&
182 (1 << (int)times_2) == 2 &&
183 (1 << (int)times_4) == 4 &&
184 (1 << (int)times_8) == 8), "");
185 return (1 << (int)scale);
186 }
187
188 private:
189 Register _base;
190 Register _index;
191 XMMRegister _xmmindex;
192 ScaleFactor _scale;
193 int _disp;
194 bool _isxmmindex;
195 RelocationHolder _rspec;
196
197 // Easily misused constructors make them private
198 // %%% can we make these go away?
199 NOT_LP64(Address(address loc, RelocationHolder spec);)
200 Address(int disp, address loc, relocInfo::relocType rtype);
201 Address(int disp, address loc, RelocationHolder spec);
202
203 public:
204
205 int disp() { return _disp; }
206 // creation
207 Address()
208 : _base(noreg),
209 _index(noreg),
210 _xmmindex(xnoreg),
211 _scale(no_scale),
212 _disp(0),
213 _isxmmindex(false){
214 }
215
216 // No default displacement otherwise Register can be implicitly
217 // converted to 0(Register) which is quite a different animal.
218
219 Address(Register base, int disp)
220 : _base(base),
221 _index(noreg),
222 _xmmindex(xnoreg),
223 _scale(no_scale),
224 _disp(disp),
225 _isxmmindex(false){
226 }
227
228 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
229 : _base (base),
230 _index(index),
231 _xmmindex(xnoreg),
232 _scale(scale),
233 _disp (disp),
234 _isxmmindex(false) {
235 assert(!index->is_valid() == (scale == Address::no_scale),
236 "inconsistent address");
237 }
238
239 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
240 : _base (base),
241 _index(index.register_or_noreg()),
242 _xmmindex(xnoreg),
243 _scale(scale),
244 _disp (disp + (index.constant_or_zero() * scale_size(scale))),
245 _isxmmindex(false){
246 if (!index.is_register()) scale = Address::no_scale;
247 assert(!_index->is_valid() == (scale == Address::no_scale),
248 "inconsistent address");
249 }
250
251 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
252 : _base (base),
253 _index(noreg),
254 _xmmindex(index),
255 _scale(scale),
256 _disp(disp),
257 _isxmmindex(true) {
258 assert(!index->is_valid() == (scale == Address::no_scale),
259 "inconsistent address");
260 }
261
262 // The following overloads are used in connection with the
263 // ByteSize type (see sizes.hpp). They simplify the use of
264 // ByteSize'd arguments in assembly code.
265
266 Address(Register base, ByteSize disp)
267 : Address(base, in_bytes(disp)) {}
268
269 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
270 : Address(base, index, scale, in_bytes(disp)) {}
271
272 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
273 : Address(base, index, scale, in_bytes(disp)) {}
274
275 Address plus_disp(int disp) const {
276 Address a = (*this);
277 a._disp += disp;
278 return a;
279 }
280 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
281 Address a = (*this);
282 a._disp += disp.constant_or_zero() * scale_size(scale);
283 if (disp.is_register()) {
284 assert(!a.index()->is_valid(), "competing indexes");
285 a._index = disp.as_register();
286 a._scale = scale;
287 }
288 return a;
289 }
290 bool is_same_address(Address a) const {
291 // disregard _rspec
292 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
293 }
294
295 // accessors
296 bool uses(Register reg) const { return _base == reg || _index == reg; }
297 Register base() const { return _base; }
298 Register index() const { return _index; }
299 XMMRegister xmmindex() const { return _xmmindex; }
300 ScaleFactor scale() const { return _scale; }
301 int disp() const { return _disp; }
302 bool isxmmindex() const { return _isxmmindex; }
303
304 // Convert the raw encoding form into the form expected by the constructor for
305 // Address. An index of 4 (rsp) corresponds to having no index, so convert
306 // that to noreg for the Address constructor.
307 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
308
309 static Address make_array(ArrayAddress);
310
311 private:
312 bool base_needs_rex() const {
313 return _base->is_valid() && _base->encoding() >= 8;
314 }
315
316 bool index_needs_rex() const {
317 return _index->is_valid() &&_index->encoding() >= 8;
318 }
319
320 bool xmmindex_needs_rex() const {
321 return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
322 }
323
324 relocInfo::relocType reloc() const { return _rspec.type(); }
325
326 friend class Assembler;
327 friend class MacroAssembler;
328 friend class LIR_Assembler; // base/index/scale/disp
329 };
330
331 //
332 // AddressLiteral has been split out from Address because operands of this type
333 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
334 // the few instructions that need to deal with address literals are unique and the
335 // MacroAssembler does not have to implement every instruction in the Assembler
336 // in order to search for address literals that may need special handling depending
337 // on the instruction and the platform. As small step on the way to merging i486/amd64
338 // directories.
339 //
340 class AddressLiteral {
341 friend class ArrayAddress;
342 RelocationHolder _rspec;
343 // Typically we use AddressLiterals we want to use their rval
344 // However in some situations we want the lval (effect address) of the item.
345 // We provide a special factory for making those lvals.
346 bool _is_lval;
347
348 // If the target is far we'll need to load the ea of this to
349 // a register to reach it. Otherwise if near we can do rip
350 // relative addressing.
351
352 address _target;
353
354 protected:
355 // creation
356 AddressLiteral()
357 : _is_lval(false),
358 _target(NULL)
359 {}
360
361 public:
362
363
364 AddressLiteral(address target, relocInfo::relocType rtype);
365
366 AddressLiteral(address target, RelocationHolder const& rspec)
367 : _rspec(rspec),
368 _is_lval(false),
369 _target(target)
370 {}
371
372 AddressLiteral addr() {
373 AddressLiteral ret = *this;
374 ret._is_lval = true;
375 return ret;
376 }
377
378
379 private:
380
381 address target() { return _target; }
382 bool is_lval() const { return _is_lval; }
383
384 relocInfo::relocType reloc() const { return _rspec.type(); }
385 const RelocationHolder& rspec() const { return _rspec; }
386
387 friend class Assembler;
388 friend class MacroAssembler;
389 friend class Address;
390 friend class LIR_Assembler;
391 };
392
393 // Convenience classes
394 class RuntimeAddress: public AddressLiteral {
395
396 public:
397
398 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
399
400 };
401
402 class ExternalAddress: public AddressLiteral {
403 private:
404 static relocInfo::relocType reloc_for_target(address target) {
405 // Sometimes ExternalAddress is used for values which aren't
406 // exactly addresses, like the card table base.
407 // external_word_type can't be used for values in the first page
408 // so just skip the reloc in that case.
409 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
410 }
411
412 public:
413
414 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
415
416 };
417
418 class InternalAddress: public AddressLiteral {
419
420 public:
421
422 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
423
424 };
425
426 // x86 can do array addressing as a single operation since disp can be an absolute
427 // address amd64 can't. We create a class that expresses the concept but does extra
428 // magic on amd64 to get the final result
429
430 class ArrayAddress {
431 private:
432
433 AddressLiteral _base;
434 Address _index;
435
436 public:
437
438 ArrayAddress() {};
439 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
440 AddressLiteral base() { return _base; }
441 Address index() { return _index; }
442
443 };
444
445 class InstructionAttr;
446
447 // 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
448 // See fxsave and xsave(EVEX enabled) documentation for layout
449 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
450
451 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
452 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
453 // is what you get. The Assembler is generating code into a CodeBuffer.
454
455 class Assembler : public AbstractAssembler {
456 friend class AbstractAssembler; // for the non-virtual hack
457 friend class LIR_Assembler; // as_Address()
458 friend class StubGenerator;
459
460 public:
461 enum Condition { // The x86 condition codes used for conditional jumps/moves.
462 zero = 0x4,
463 notZero = 0x5,
464 equal = 0x4,
465 notEqual = 0x5,
466 less = 0xc,
467 lessEqual = 0xe,
468 greater = 0xf,
469 greaterEqual = 0xd,
470 below = 0x2,
471 belowEqual = 0x6,
472 above = 0x7,
473 aboveEqual = 0x3,
474 overflow = 0x0,
475 noOverflow = 0x1,
476 carrySet = 0x2,
477 carryClear = 0x3,
478 negative = 0x8,
479 positive = 0x9,
480 parity = 0xa,
481 noParity = 0xb
482 };
483
484 enum Prefix {
485 // segment overrides
486 CS_segment = 0x2e,
487 SS_segment = 0x36,
488 DS_segment = 0x3e,
489 ES_segment = 0x26,
490 FS_segment = 0x64,
491 GS_segment = 0x65,
492
493 REX = 0x40,
494
495 REX_B = 0x41,
496 REX_X = 0x42,
497 REX_XB = 0x43,
498 REX_R = 0x44,
499 REX_RB = 0x45,
500 REX_RX = 0x46,
501 REX_RXB = 0x47,
502
503 REX_W = 0x48,
504
505 REX_WB = 0x49,
506 REX_WX = 0x4A,
507 REX_WXB = 0x4B,
508 REX_WR = 0x4C,
509 REX_WRB = 0x4D,
510 REX_WRX = 0x4E,
511 REX_WRXB = 0x4F,
512
513 VEX_3bytes = 0xC4,
514 VEX_2bytes = 0xC5,
515 EVEX_4bytes = 0x62,
516 Prefix_EMPTY = 0x0
517 };
518
519 enum VexPrefix {
520 VEX_B = 0x20,
521 VEX_X = 0x40,
522 VEX_R = 0x80,
523 VEX_W = 0x80
524 };
525
526 enum ExexPrefix {
527 EVEX_F = 0x04,
528 EVEX_V = 0x08,
529 EVEX_Rb = 0x10,
530 EVEX_X = 0x40,
531 EVEX_Z = 0x80
532 };
533
534 enum VexSimdPrefix {
535 VEX_SIMD_NONE = 0x0,
536 VEX_SIMD_66 = 0x1,
537 VEX_SIMD_F3 = 0x2,
538 VEX_SIMD_F2 = 0x3
539 };
540
541 enum VexOpcode {
542 VEX_OPCODE_NONE = 0x0,
543 VEX_OPCODE_0F = 0x1,
544 VEX_OPCODE_0F_38 = 0x2,
545 VEX_OPCODE_0F_3A = 0x3,
546 VEX_OPCODE_MASK = 0x1F
547 };
548
549 enum AvxVectorLen {
550 AVX_128bit = 0x0,
551 AVX_256bit = 0x1,
552 AVX_512bit = 0x2,
553 AVX_NoVec = 0x4
554 };
555
556 enum EvexTupleType {
557 EVEX_FV = 0,
558 EVEX_HV = 4,
559 EVEX_FVM = 6,
560 EVEX_T1S = 7,
561 EVEX_T1F = 11,
562 EVEX_T2 = 13,
563 EVEX_T4 = 15,
564 EVEX_T8 = 17,
565 EVEX_HVM = 18,
566 EVEX_QVM = 19,
567 EVEX_OVM = 20,
568 EVEX_M128 = 21,
569 EVEX_DUP = 22,
570 EVEX_ETUP = 23
571 };
572
573 enum EvexInputSizeInBits {
574 EVEX_8bit = 0,
575 EVEX_16bit = 1,
576 EVEX_32bit = 2,
577 EVEX_64bit = 3,
578 EVEX_NObit = 4
579 };
580
581 enum WhichOperand {
582 // input to locate_operand, and format code for relocations
583 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
584 disp32_operand = 1, // embedded 32-bit displacement or address
585 call32_operand = 2, // embedded 32-bit self-relative displacement
586 #ifndef _LP64
587 _WhichOperand_limit = 3
588 #else
589 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
590 _WhichOperand_limit = 4
591 #endif
592 };
593
594 // Comparison predicates for integral types & FP types when using SSE
595 enum ComparisonPredicate {
596 eq = 0,
597 lt = 1,
598 le = 2,
599 _false = 3,
600 neq = 4,
601 nlt = 5,
602 nle = 6,
603 _true = 7
604 };
605
606 // Comparison predicates for FP types when using AVX
607 // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
608 // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
609 enum ComparisonPredicateFP {
610 EQ_OQ = 0,
611 LT_OS = 1,
612 LE_OS = 2,
613 UNORD_Q = 3,
614 NEQ_UQ = 4,
615 NLT_US = 5,
616 NLE_US = 6,
617 ORD_Q = 7,
618 EQ_UQ = 8,
619 NGE_US = 9,
620 NGT_US = 0xA,
621 FALSE_OQ = 0XB,
622 NEQ_OQ = 0xC,
623 GE_OS = 0xD,
624 GT_OS = 0xE,
625 TRUE_UQ = 0xF,
626 EQ_OS = 0x10,
627 LT_OQ = 0x11,
628 LE_OQ = 0x12,
629 UNORD_S = 0x13,
630 NEQ_US = 0x14,
631 NLT_UQ = 0x15,
632 NLE_UQ = 0x16,
633 ORD_S = 0x17,
634 EQ_US = 0x18,
635 NGE_UQ = 0x19,
636 NGT_UQ = 0x1A,
637 FALSE_OS = 0x1B,
638 NEQ_OS = 0x1C,
639 GE_OQ = 0x1D,
640 GT_OQ = 0x1E,
641 TRUE_US =0x1F
642 };
643
644 enum Width {
645 B = 0,
646 W = 1,
647 D = 2,
648 Q = 3
649 };
650
651 //---< calculate length of instruction >---
652 // As instruction size can't be found out easily on x86/x64,
653 // we just use '4' for len and maxlen.
654 // instruction must start at passed address
655 static unsigned int instr_len(unsigned char *instr) { return 4; }
656
657 //---< longest instructions >---
658 // Max instruction length is not specified in architecture documentation.
659 // We could use a "safe enough" estimate (15), but just default to
660 // instruction length guess from above.
661 static unsigned int instr_maxlen() { return 4; }
662
663 // NOTE: The general philopsophy of the declarations here is that 64bit versions
664 // of instructions are freely declared without the need for wrapping them an ifdef.
665 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
666 // In the .cpp file the implementations are wrapped so that they are dropped out
667 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
668 // to the size it was prior to merging up the 32bit and 64bit assemblers.
669 //
670 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
671 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
672
673 private:
674
675 bool _legacy_mode_bw;
676 bool _legacy_mode_dq;
677 bool _legacy_mode_vl;
678 bool _legacy_mode_vlbw;
679 NOT_LP64(bool _is_managed;)
680
681 class InstructionAttr *_attributes;
682
683 // 64bit prefixes
684 void prefix(Register reg);
685 void prefix(Register dst, Register src, Prefix p);
686 void prefix(Register dst, Address adr, Prefix p);
687
688 void prefix(Address adr);
689 void prefix(Address adr, Register reg, bool byteinst = false);
690 void prefix(Address adr, XMMRegister reg);
691
692 int prefix_and_encode(int reg_enc, bool byteinst = false);
693 int prefix_and_encode(int dst_enc, int src_enc) {
694 return prefix_and_encode(dst_enc, false, src_enc, false);
695 }
696 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
697
698 // Some prefixq variants always emit exactly one prefix byte, so besides a
699 // prefix-emitting method we provide a method to get the prefix byte to emit,
700 // which can then be folded into a byte stream.
701 int8_t get_prefixq(Address adr);
702 int8_t get_prefixq(Address adr, Register reg);
703
704 void prefixq(Address adr);
705 void prefixq(Address adr, Register reg);
706 void prefixq(Address adr, XMMRegister reg);
707
708 int prefixq_and_encode(int reg_enc);
709 int prefixq_and_encode(int dst_enc, int src_enc);
710
711 void rex_prefix(Address adr, XMMRegister xreg,
712 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
713 int rex_prefix_and_encode(int dst_enc, int src_enc,
714 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
715
716 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
717
718 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
719 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
720
721 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
722 VexSimdPrefix pre, VexOpcode opc,
723 InstructionAttr *attributes);
724
725 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
726 VexSimdPrefix pre, VexOpcode opc,
727 InstructionAttr *attributes);
728
729 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
730 VexOpcode opc, InstructionAttr *attributes);
731
732 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
733 VexOpcode opc, InstructionAttr *attributes);
734
735 // Helper functions for groups of instructions
736 void emit_arith_b(int op1, int op2, Register dst, int imm8);
737
738 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
739 // Force generation of a 4 byte immediate value even if it fits into 8bit
740 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
741 void emit_arith(int op1, int op2, Register dst, Register src);
742
743 bool emit_compressed_disp_byte(int &disp);
744
745 void emit_modrm(int mod, int dst_enc, int src_enc);
746 void emit_modrm_disp8(int mod, int dst_enc, int src_enc,
747 int disp);
748 void emit_modrm_sib(int mod, int dst_enc, int src_enc,
749 Address::ScaleFactor scale, int index_enc, int base_enc);
750 void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
751 Address::ScaleFactor scale, int index_enc, int base_enc,
752 int disp);
753
754 void emit_operand_helper(int reg_enc,
755 int base_enc, int index_enc, Address::ScaleFactor scale,
756 int disp,
757 RelocationHolder const& rspec,
758 int post_addr_length);
759
760 void emit_operand(Register reg,
761 Register base, Register index, Address::ScaleFactor scale,
762 int disp,
763 RelocationHolder const& rspec,
764 int post_addr_length);
765
766 void emit_operand(Register reg,
767 Register base, XMMRegister index, Address::ScaleFactor scale,
768 int disp,
769 RelocationHolder const& rspec,
770 int post_addr_length);
771
772 void emit_operand(XMMRegister xreg,
773 Register base, XMMRegister xindex, Address::ScaleFactor scale,
774 int disp,
775 RelocationHolder const& rspec,
776 int post_addr_length);
777
778 void emit_operand(Register reg, Address adr,
779 int post_addr_length);
780
781 void emit_operand(XMMRegister reg,
782 Register base, Register index, Address::ScaleFactor scale,
783 int disp,
784 RelocationHolder const& rspec,
785 int post_addr_length);
786
787 void emit_operand_helper(KRegister kreg,
788 int base_enc, int index_enc, Address::ScaleFactor scale,
789 int disp,
790 RelocationHolder const& rspec,
791 int post_addr_length);
792
793 void emit_operand(KRegister kreg, Address adr,
794 int post_addr_length);
795
796 void emit_operand(KRegister kreg,
797 Register base, Register index, Address::ScaleFactor scale,
798 int disp,
799 RelocationHolder const& rspec,
800 int post_addr_length);
801
802 void emit_operand(XMMRegister reg, Address adr, int post_addr_length);
803
804 // Immediate-to-memory forms
805 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
806 void emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32);
807
808 protected:
809 #ifdef ASSERT
810 void check_relocation(RelocationHolder const& rspec, int format);
811 #endif
812
813 void emit_data(jint data, relocInfo::relocType rtype, int format);
814 void emit_data(jint data, RelocationHolder const& rspec, int format);
815 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
816 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
817
818 bool always_reachable(AddressLiteral adr) NOT_LP64( { return true; } );
819 bool reachable(AddressLiteral adr) NOT_LP64( { return true; } );
820
821
822 // These are all easily abused and hence protected
823
824 // 32BIT ONLY SECTION
825 #ifndef _LP64
826 // Make these disappear in 64bit mode since they would never be correct
827 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
828 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
829
830 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
831 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
832
833 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
834 #else
835 // 64BIT ONLY SECTION
836 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
837
838 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
839 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
840
841 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
842 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
843 #endif // _LP64
844
845 // These are unique in that we are ensured by the caller that the 32bit
846 // relative in these instructions will always be able to reach the potentially
847 // 64bit address described by entry. Since they can take a 64bit address they
848 // don't have the 32 suffix like the other instructions in this class.
849
850 void call_literal(address entry, RelocationHolder const& rspec);
851 void jmp_literal(address entry, RelocationHolder const& rspec);
852
853 // Avoid using directly section
854 // Instructions in this section are actually usable by anyone without danger
855 // of failure but have performance issues that are addressed my enhanced
856 // instructions which will do the proper thing base on the particular cpu.
857 // We protect them because we don't trust you...
858
859 // Don't use next inc() and dec() methods directly. INC & DEC instructions
860 // could cause a partial flag stall since they don't set CF flag.
861 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
862 // which call inc() & dec() or add() & sub() in accordance with
863 // the product flag UseIncDec value.
864
865 void decl(Register dst);
866 void decl(Address dst);
867 void decq(Address dst);
868
869 void incl(Register dst);
870 void incl(Address dst);
871 void incq(Register dst);
872 void incq(Address dst);
873
874 // New cpus require use of movsd and movss to avoid partial register stall
875 // when loading from memory. But for old Opteron use movlpd instead of movsd.
876 // The selection is done in MacroAssembler::movdbl() and movflt().
877
878 // Move Scalar Single-Precision Floating-Point Values
879 void movss(XMMRegister dst, Address src);
880 void movss(XMMRegister dst, XMMRegister src);
881 void movss(Address dst, XMMRegister src);
882
883 // Move Scalar Double-Precision Floating-Point Values
884 void movsd(XMMRegister dst, Address src);
885 void movsd(XMMRegister dst, XMMRegister src);
886 void movsd(Address dst, XMMRegister src);
887 void movlpd(XMMRegister dst, Address src);
888
889 // New cpus require use of movaps and movapd to avoid partial register stall
890 // when moving between registers.
891 void movaps(XMMRegister dst, XMMRegister src);
892 void movapd(XMMRegister dst, XMMRegister src);
893
894 // End avoid using directly
895
896
897 // Instruction prefixes
898 void prefix(Prefix p);
899
900 public:
901
902 // Creation
903 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
904 init_attributes();
905 }
906
907 // Decoding
908 static address locate_operand(address inst, WhichOperand which);
909 static address locate_next_instruction(address inst);
910
911 // Utilities
912 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
913 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
914
915 // Generic instructions
916 // Does 32bit or 64bit as needed for the platform. In some sense these
917 // belong in macro assembler but there is no need for both varieties to exist
918
919 void init_attributes(void);
920
921 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
922 void clear_attributes(void) { _attributes = NULL; }
923
924 void set_managed(void) { NOT_LP64(_is_managed = true;) }
925 void clear_managed(void) { NOT_LP64(_is_managed = false;) }
926 bool is_managed(void) {
927 NOT_LP64(return _is_managed;)
928 LP64_ONLY(return false;) }
929
930 void lea(Register dst, Address src);
931
932 void mov(Register dst, Register src);
933
934 #ifdef _LP64
935 // support caching the result of some routines
936
937 // must be called before pusha(), popa(), vzeroupper() - checked with asserts
938 static void precompute_instructions();
939
940 void pusha_uncached();
941 void popa_uncached();
942 #endif
943 void vzeroupper_uncached();
944 void decq(Register dst);
945
946 void pusha();
947 void popa();
948
949 void pushf();
950 void popf();
951
952 void push(int32_t imm32);
953
954 void push(Register src);
955
956 void pop(Register dst);
957
958 // These do register sized moves/scans
959 void rep_mov();
960 void rep_stos();
961 void rep_stosb();
962 void repne_scan();
963 #ifdef _LP64
964 void repne_scanl();
965 #endif
966
967 // Vanilla instructions in lexical order
968
969 void adcl(Address dst, int32_t imm32);
970 void adcl(Address dst, Register src);
971 void adcl(Register dst, int32_t imm32);
972 void adcl(Register dst, Address src);
973 void adcl(Register dst, Register src);
974
975 void adcq(Register dst, int32_t imm32);
976 void adcq(Register dst, Address src);
977 void adcq(Register dst, Register src);
978
979 void addb(Address dst, int imm8);
980 void addw(Register dst, Register src);
981 void addw(Address dst, int imm16);
982
983 void addl(Address dst, int32_t imm32);
984 void addl(Address dst, Register src);
985 void addl(Register dst, int32_t imm32);
986 void addl(Register dst, Address src);
987 void addl(Register dst, Register src);
988
989 void addq(Address dst, int32_t imm32);
990 void addq(Address dst, Register src);
991 void addq(Register dst, int32_t imm32);
992 void addq(Register dst, Address src);
993 void addq(Register dst, Register src);
994
995 #ifdef _LP64
996 //Add Unsigned Integers with Carry Flag
997 void adcxq(Register dst, Register src);
998
999 //Add Unsigned Integers with Overflow Flag
1000 void adoxq(Register dst, Register src);
1001 #endif
1002
1003 void addr_nop_4();
1004 void addr_nop_5();
1005 void addr_nop_7();
1006 void addr_nop_8();
1007
1008 // Add Scalar Double-Precision Floating-Point Values
1009 void addsd(XMMRegister dst, Address src);
1010 void addsd(XMMRegister dst, XMMRegister src);
1011
1012 // Add Scalar Single-Precision Floating-Point Values
1013 void addss(XMMRegister dst, Address src);
1014 void addss(XMMRegister dst, XMMRegister src);
1015
1016 // AES instructions
1017 void aesdec(XMMRegister dst, Address src);
1018 void aesdec(XMMRegister dst, XMMRegister src);
1019 void aesdeclast(XMMRegister dst, Address src);
1020 void aesdeclast(XMMRegister dst, XMMRegister src);
1021 void aesenc(XMMRegister dst, Address src);
1022 void aesenc(XMMRegister dst, XMMRegister src);
1023 void aesenclast(XMMRegister dst, Address src);
1024 void aesenclast(XMMRegister dst, XMMRegister src);
1025 // Vector AES instructions
1026 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1027 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1028 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1029 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1030
1031 void andw(Register dst, Register src);
1032 void andb(Address dst, Register src);
1033
1034 void andl(Address dst, int32_t imm32);
1035 void andl(Register dst, int32_t imm32);
1036 void andl(Register dst, Address src);
1037 void andl(Register dst, Register src);
1038 void andl(Address dst, Register src);
1039
1040 void andq(Address dst, int32_t imm32);
1041 void andq(Register dst, int32_t imm32);
1042 void andq(Register dst, Address src);
1043 void andq(Register dst, Register src);
1044 void andq(Address dst, Register src);
1045
1046 // BMI instructions
1047 void andnl(Register dst, Register src1, Register src2);
1048 void andnl(Register dst, Register src1, Address src2);
1049 void andnq(Register dst, Register src1, Register src2);
1050 void andnq(Register dst, Register src1, Address src2);
1051
1052 void blsil(Register dst, Register src);
1053 void blsil(Register dst, Address src);
1054 void blsiq(Register dst, Register src);
1055 void blsiq(Register dst, Address src);
1056
1057 void blsmskl(Register dst, Register src);
1058 void blsmskl(Register dst, Address src);
1059 void blsmskq(Register dst, Register src);
1060 void blsmskq(Register dst, Address src);
1061
1062 void blsrl(Register dst, Register src);
1063 void blsrl(Register dst, Address src);
1064 void blsrq(Register dst, Register src);
1065 void blsrq(Register dst, Address src);
1066
1067 void bsfl(Register dst, Register src);
1068 void bsrl(Register dst, Register src);
1069
1070 #ifdef _LP64
1071 void bsfq(Register dst, Register src);
1072 void bsrq(Register dst, Register src);
1073 #endif
1074
1075 void bswapl(Register reg);
1076
1077 void bswapq(Register reg);
1078
1079 void call(Label& L, relocInfo::relocType rtype);
1080 void call(Register reg); // push pc; pc <- reg
1081 void call(Address adr); // push pc; pc <- adr
1082
1083 void cdql();
1084
1085 void cdqq();
1086
1087 void cld();
1088
1089 void clflush(Address adr);
1090 void clflushopt(Address adr);
1091 void clwb(Address adr);
1092
1093 void cmovl(Condition cc, Register dst, Register src);
1094 void cmovl(Condition cc, Register dst, Address src);
1095
1096 void cmovq(Condition cc, Register dst, Register src);
1097 void cmovq(Condition cc, Register dst, Address src);
1098
1099
1100 void cmpb(Address dst, int imm8);
1101
1102 void cmpl(Address dst, int32_t imm32);
1103 void cmpl(Register dst, int32_t imm32);
1104 void cmpl(Register dst, Register src);
1105 void cmpl(Register dst, Address src);
1106 void cmpl_imm32(Address dst, int32_t imm32);
1107
1108 void cmpq(Address dst, int32_t imm32);
1109 void cmpq(Address dst, Register src);
1110 void cmpq(Register dst, int32_t imm32);
1111 void cmpq(Register dst, Register src);
1112 void cmpq(Register dst, Address src);
1113
1114 void cmpw(Address dst, int imm16);
1115
1116 void cmpxchg8 (Address adr);
1117
1118 void cmpxchgb(Register reg, Address adr);
1119 void cmpxchgl(Register reg, Address adr);
1120
1121 void cmpxchgq(Register reg, Address adr);
1122 void cmpxchgw(Register reg, Address adr);
1123
1124 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1125 void comisd(XMMRegister dst, Address src);
1126 void comisd(XMMRegister dst, XMMRegister src);
1127
1128 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1129 void comiss(XMMRegister dst, Address src);
1130 void comiss(XMMRegister dst, XMMRegister src);
1131
1132 // Identify processor type and features
1133 void cpuid();
1134
1135 // CRC32C
1136 void crc32(Register crc, Register v, int8_t sizeInBytes);
1137 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1138
1139 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1140 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1141 void cvtsd2ss(XMMRegister dst, Address src);
1142
1143 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1144 void cvtsi2sdl(XMMRegister dst, Register src);
1145 void cvtsi2sdl(XMMRegister dst, Address src);
1146 void cvtsi2sdq(XMMRegister dst, Register src);
1147 void cvtsi2sdq(XMMRegister dst, Address src);
1148
1149 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1150 void cvtsi2ssl(XMMRegister dst, Register src);
1151 void cvtsi2ssl(XMMRegister dst, Address src);
1152 void cvtsi2ssq(XMMRegister dst, Register src);
1153 void cvtsi2ssq(XMMRegister dst, Address src);
1154
1155 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1156 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1157 void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1158
1159 // Convert Halffloat to Single Precision Floating-Point value
1160 void vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1161 void vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len);
1162 void evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len);
1163 void vcvtps2ph(Address dst, XMMRegister src, int imm8, int vector_len);
1164 void vcvtph2ps(XMMRegister dst, Address src, int vector_len);
1165
1166 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1167 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1168 void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1169
1170 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1171 void cvtss2sd(XMMRegister dst, XMMRegister src);
1172 void cvtss2sd(XMMRegister dst, Address src);
1173
1174 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1175 void cvtsd2siq(Register dst, XMMRegister src);
1176 void cvttsd2sil(Register dst, Address src);
1177 void cvttsd2sil(Register dst, XMMRegister src);
1178 void cvttsd2siq(Register dst, Address src);
1179 void cvttsd2siq(Register dst, XMMRegister src);
1180
1181 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1182 void cvttss2sil(Register dst, XMMRegister src);
1183 void cvttss2siq(Register dst, XMMRegister src);
1184 void cvtss2sil(Register dst, XMMRegister src);
1185
1186 // Convert vector double to int
1187 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1188
1189 // Convert vector float and double
1190 void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1191 void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1192
1193 // Convert vector float to int/long
1194 void vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1195 void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1196 void evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len);
1197
1198 // Convert vector long to vector FP
1199 void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1200 void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1201
1202 // Convert vector double to long
1203 void evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1204 void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1205
1206 // Convert vector double to int
1207 void vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len);
1208
1209 // Evex casts with truncation
1210 void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
1211 void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
1212 void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
1213 void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
1214 void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
1215 void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);
1216
1217 // Evex casts with signed saturation
1218 void evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len);
1219
1220 //Abs of packed Integer values
1221 void pabsb(XMMRegister dst, XMMRegister src);
1222 void pabsw(XMMRegister dst, XMMRegister src);
1223 void pabsd(XMMRegister dst, XMMRegister src);
1224 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1225 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1226 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1227 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1228
1229 // Divide Scalar Double-Precision Floating-Point Values
1230 void divsd(XMMRegister dst, Address src);
1231 void divsd(XMMRegister dst, XMMRegister src);
1232
1233 // Divide Scalar Single-Precision Floating-Point Values
1234 void divss(XMMRegister dst, Address src);
1235 void divss(XMMRegister dst, XMMRegister src);
1236
1237
1238 #ifndef _LP64
1239 private:
1240
1241 void emit_farith(int b1, int b2, int i);
1242
1243 public:
1244 void emms();
1245
1246 void fabs();
1247
1248 void fadd(int i);
1249
1250 void fadd_d(Address src);
1251 void fadd_s(Address src);
1252
1253 // "Alternate" versions of x87 instructions place result down in FPU
1254 // stack instead of on TOS
1255
1256 void fadda(int i); // "alternate" fadd
1257 void faddp(int i = 1);
1258
1259 void fchs();
1260
1261 void fcom(int i);
1262
1263 void fcomp(int i = 1);
1264 void fcomp_d(Address src);
1265 void fcomp_s(Address src);
1266
1267 void fcompp();
1268
1269 void fcos();
1270
1271 void fdecstp();
1272
1273 void fdiv(int i);
1274 void fdiv_d(Address src);
1275 void fdivr_s(Address src);
1276 void fdiva(int i); // "alternate" fdiv
1277 void fdivp(int i = 1);
1278
1279 void fdivr(int i);
1280 void fdivr_d(Address src);
1281 void fdiv_s(Address src);
1282
1283 void fdivra(int i); // "alternate" reversed fdiv
1284
1285 void fdivrp(int i = 1);
1286
1287 void ffree(int i = 0);
1288
1289 void fild_d(Address adr);
1290 void fild_s(Address adr);
1291
1292 void fincstp();
1293
1294 void finit();
1295
1296 void fist_s (Address adr);
1297 void fistp_d(Address adr);
1298 void fistp_s(Address adr);
1299
1300 void fld1();
1301
1302 void fld_d(Address adr);
1303 void fld_s(Address adr);
1304 void fld_s(int index);
1305
1306 void fldcw(Address src);
1307
1308 void fldenv(Address src);
1309
1310 void fldlg2();
1311
1312 void fldln2();
1313
1314 void fldz();
1315
1316 void flog();
1317 void flog10();
1318
1319 void fmul(int i);
1320
1321 void fmul_d(Address src);
1322 void fmul_s(Address src);
1323
1324 void fmula(int i); // "alternate" fmul
1325
1326 void fmulp(int i = 1);
1327
1328 void fnsave(Address dst);
1329
1330 void fnstcw(Address src);
1331
1332 void fnstsw_ax();
1333
1334 void fprem();
1335 void fprem1();
1336
1337 void frstor(Address src);
1338
1339 void fsin();
1340
1341 void fsqrt();
1342
1343 void fst_d(Address adr);
1344 void fst_s(Address adr);
1345
1346 void fstp_d(Address adr);
1347 void fstp_d(int index);
1348 void fstp_s(Address adr);
1349
1350 void fsub(int i);
1351 void fsub_d(Address src);
1352 void fsub_s(Address src);
1353
1354 void fsuba(int i); // "alternate" fsub
1355
1356 void fsubp(int i = 1);
1357
1358 void fsubr(int i);
1359 void fsubr_d(Address src);
1360 void fsubr_s(Address src);
1361
1362 void fsubra(int i); // "alternate" reversed fsub
1363
1364 void fsubrp(int i = 1);
1365
1366 void ftan();
1367
1368 void ftst();
1369
1370 void fucomi(int i = 1);
1371 void fucomip(int i = 1);
1372
1373 void fwait();
1374
1375 void fxch(int i = 1);
1376
1377 void fyl2x();
1378 void frndint();
1379 void f2xm1();
1380 void fldl2e();
1381 #endif // !_LP64
1382
1383 // operands that only take the original 32bit registers
1384 void emit_operand32(Register reg, Address adr, int post_addr_length);
1385
1386 void fld_x(Address adr); // extended-precision (80-bit) format
1387 void fstp_x(Address adr); // extended-precision (80-bit) format
1388 void fxrstor(Address src);
1389 void xrstor(Address src);
1390
1391 void fxsave(Address dst);
1392 void xsave(Address dst);
1393
1394 void hlt();
1395
1396 void idivl(Register src);
1397 void divl(Register src); // Unsigned division
1398
1399 #ifdef _LP64
1400 void idivq(Register src);
1401 void divq(Register src); // Unsigned division
1402 #endif
1403
1404 void imull(Register src);
1405 void imull(Register dst, Register src);
1406 void imull(Register dst, Register src, int value);
1407 void imull(Register dst, Address src, int value);
1408 void imull(Register dst, Address src);
1409
1410 #ifdef _LP64
1411 void imulq(Register dst, Register src);
1412 void imulq(Register dst, Register src, int value);
1413 void imulq(Register dst, Address src, int value);
1414 void imulq(Register dst, Address src);
1415 void imulq(Register dst);
1416 #endif
1417
1418 // jcc is the generic conditional branch generator to run-
1419 // time routines, jcc is used for branches to labels. jcc
1420 // takes a branch opcode (cc) and a label (L) and generates
1421 // either a backward branch or a forward branch and links it
1422 // to the label fixup chain. Usage:
1423 //
1424 // Label L; // unbound label
1425 // jcc(cc, L); // forward branch to unbound label
1426 // bind(L); // bind label to the current pc
1427 // jcc(cc, L); // backward branch to bound label
1428 // bind(L); // illegal: a label may be bound only once
1429 //
1430 // Note: The same Label can be used for forward and backward branches
1431 // but it may be bound only once.
1432
1433 void jcc(Condition cc, Label& L, bool maybe_short = true);
1434
1435 // Conditional jump to a 8-bit offset to L.
1436 // WARNING: be very careful using this for forward jumps. If the label is
1437 // not bound within an 8-bit offset of this instruction, a run-time error
1438 // will occur.
1439
1440 // Use macro to record file and line number.
1441 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1442
1443 void jccb_0(Condition cc, Label& L, const char* file, int line);
1444
1445 void jmp(Address entry); // pc <- entry
1446
1447 // Label operations & relative jumps (PPUM Appendix D)
1448 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1449
1450 void jmp(Register entry); // pc <- entry
1451
1452 // Unconditional 8-bit offset jump to L.
1453 // WARNING: be very careful using this for forward jumps. If the label is
1454 // not bound within an 8-bit offset of this instruction, a run-time error
1455 // will occur.
1456
1457 // Use macro to record file and line number.
1458 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1459
1460 void jmpb_0(Label& L, const char* file, int line);
1461
1462 void ldmxcsr( Address src );
1463
1464 void leal(Register dst, Address src);
1465
1466 void leaq(Register dst, Address src);
1467
1468 void lfence();
1469
1470 void lock();
1471 void size_prefix();
1472
1473 void lzcntl(Register dst, Register src);
1474 void lzcntl(Register dst, Address src);
1475
1476 #ifdef _LP64
1477 void lzcntq(Register dst, Register src);
1478 void lzcntq(Register dst, Address src);
1479 #endif
1480
1481 enum Membar_mask_bits {
1482 StoreStore = 1 << 3,
1483 LoadStore = 1 << 2,
1484 StoreLoad = 1 << 1,
1485 LoadLoad = 1 << 0
1486 };
1487
1488 // Serializes memory and blows flags
1489 void membar(Membar_mask_bits order_constraint);
1490
1491 void mfence();
1492 void sfence();
1493
1494 // Moves
1495
1496 void mov64(Register dst, int64_t imm64);
1497 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1498
1499 void movb(Address dst, Register src);
1500 void movb(Address dst, int imm8);
1501 void movb(Register dst, Address src);
1502
1503 void movddup(XMMRegister dst, XMMRegister src);
1504 void movddup(XMMRegister dst, Address src);
1505 void vmovddup(XMMRegister dst, Address src, int vector_len);
1506
1507 void kandbl(KRegister dst, KRegister src1, KRegister src2);
1508 void kandwl(KRegister dst, KRegister src1, KRegister src2);
1509 void kanddl(KRegister dst, KRegister src1, KRegister src2);
1510 void kandql(KRegister dst, KRegister src1, KRegister src2);
1511
1512 void korbl(KRegister dst, KRegister src1, KRegister src2);
1513 void korwl(KRegister dst, KRegister src1, KRegister src2);
1514 void kordl(KRegister dst, KRegister src1, KRegister src2);
1515 void korql(KRegister dst, KRegister src1, KRegister src2);
1516
1517 void kxorbl(KRegister dst, KRegister src1, KRegister src2);
1518 void kxorwl(KRegister dst, KRegister src1, KRegister src2);
1519 void kxordl(KRegister dst, KRegister src1, KRegister src2);
1520 void kxorql(KRegister dst, KRegister src1, KRegister src2);
1521 void kmovbl(KRegister dst, Register src);
1522 void kmovbl(Register dst, KRegister src);
1523 void kmovbl(KRegister dst, KRegister src);
1524 void kmovwl(KRegister dst, Register src);
1525 void kmovwl(KRegister dst, Address src);
1526 void kmovwl(Register dst, KRegister src);
1527 void kmovwl(Address dst, KRegister src);
1528 void kmovwl(KRegister dst, KRegister src);
1529 void kmovdl(KRegister dst, Register src);
1530 void kmovdl(Register dst, KRegister src);
1531 void kmovql(KRegister dst, KRegister src);
1532 void kmovql(Address dst, KRegister src);
1533 void kmovql(KRegister dst, Address src);
1534 void kmovql(KRegister dst, Register src);
1535 void kmovql(Register dst, KRegister src);
1536
1537 void knotbl(KRegister dst, KRegister src);
1538 void knotwl(KRegister dst, KRegister src);
1539 void knotdl(KRegister dst, KRegister src);
1540 void knotql(KRegister dst, KRegister src);
1541
1542 void kortestbl(KRegister dst, KRegister src);
1543 void kortestwl(KRegister dst, KRegister src);
1544 void kortestdl(KRegister dst, KRegister src);
1545 void kortestql(KRegister dst, KRegister src);
1546
1547 void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
1548 void kshiftlbl(KRegister dst, KRegister src, int imm8);
1549 void kshiftlql(KRegister dst, KRegister src, int imm8);
1550 void kshiftrbl(KRegister dst, KRegister src, int imm8);
1551 void kshiftrwl(KRegister dst, KRegister src, int imm8);
1552 void kshiftrdl(KRegister dst, KRegister src, int imm8);
1553 void kshiftrql(KRegister dst, KRegister src, int imm8);
1554 void ktestq(KRegister src1, KRegister src2);
1555 void ktestd(KRegister src1, KRegister src2);
1556 void kunpckdql(KRegister dst, KRegister src1, KRegister src2);
1557
1558
1559 void ktestql(KRegister dst, KRegister src);
1560 void ktestdl(KRegister dst, KRegister src);
1561 void ktestwl(KRegister dst, KRegister src);
1562 void ktestbl(KRegister dst, KRegister src);
1563
1564 void movdl(XMMRegister dst, Register src);
1565 void movdl(Register dst, XMMRegister src);
1566 void movdl(XMMRegister dst, Address src);
1567 void movdl(Address dst, XMMRegister src);
1568
1569 // Move Double Quadword
1570 void movdq(XMMRegister dst, Register src);
1571 void movdq(Register dst, XMMRegister src);
1572
1573 // Move Aligned Double Quadword
1574 void movdqa(XMMRegister dst, XMMRegister src);
1575 void movdqa(XMMRegister dst, Address src);
1576
1577 // Move Unaligned Double Quadword
1578 void movdqu(Address dst, XMMRegister src);
1579 void movdqu(XMMRegister dst, Address src);
1580 void movdqu(XMMRegister dst, XMMRegister src);
1581
1582 // Move Unaligned 256bit Vector
1583 void vmovdqu(Address dst, XMMRegister src);
1584 void vmovdqu(XMMRegister dst, Address src);
1585 void vmovdqu(XMMRegister dst, XMMRegister src);
1586
1587 // Move Unaligned 512bit Vector
1588 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1589 void evmovdqub(XMMRegister dst, Address src, int vector_len);
1590 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1591 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1592 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1593
1594 void evmovdquw(XMMRegister dst, Address src, int vector_len);
1595 void evmovdquw(Address dst, XMMRegister src, int vector_len);
1596 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1597 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1598 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1599
1600 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1601 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1602 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1603
1604 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1605 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1606 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1607
1608 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1609 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1610 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1611
1612 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1613 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1614 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1615
1616 // Move lower 64bit to high 64bit in 128bit register
1617 void movlhps(XMMRegister dst, XMMRegister src);
1618
1619 void movl(Register dst, int32_t imm32);
1620 void movl(Address dst, int32_t imm32);
1621 void movl(Register dst, Register src);
1622 void movl(Register dst, Address src);
1623 void movl(Address dst, Register src);
1624
1625 #ifdef _LP64
1626 void movq(Register dst, Register src);
1627 void movq(Register dst, Address src);
1628 void movq(Address dst, Register src);
1629 void movq(Address dst, int32_t imm32);
1630 void movq(Register dst, int32_t imm32);
1631 #endif
1632
1633 // Move Quadword
1634 void movq(Address dst, XMMRegister src);
1635 void movq(XMMRegister dst, Address src);
1636 void movq(XMMRegister dst, XMMRegister src);
1637 void movq(Register dst, XMMRegister src);
1638 void movq(XMMRegister dst, Register src);
1639
1640 void movsbl(Register dst, Address src);
1641 void movsbl(Register dst, Register src);
1642
1643 #ifdef _LP64
1644 void movsbq(Register dst, Address src);
1645 void movsbq(Register dst, Register src);
1646
1647 // Move signed 32bit immediate to 64bit extending sign
1648 void movslq(Address dst, int32_t imm64);
1649 void movslq(Register dst, int32_t imm64);
1650
1651 void movslq(Register dst, Address src);
1652 void movslq(Register dst, Register src);
1653 #endif
1654
1655 void movswl(Register dst, Address src);
1656 void movswl(Register dst, Register src);
1657
1658 #ifdef _LP64
1659 void movswq(Register dst, Address src);
1660 void movswq(Register dst, Register src);
1661 #endif
1662
1663 void movups(XMMRegister dst, Address src);
1664 void vmovups(XMMRegister dst, Address src, int vector_len);
1665 void movups(Address dst, XMMRegister src);
1666 void vmovups(Address dst, XMMRegister src, int vector_len);
1667
1668 void movw(Address dst, int imm16);
1669 void movw(Register dst, Address src);
1670 void movw(Address dst, Register src);
1671
1672 void movzbl(Register dst, Address src);
1673 void movzbl(Register dst, Register src);
1674
1675 #ifdef _LP64
1676 void movzbq(Register dst, Address src);
1677 void movzbq(Register dst, Register src);
1678 #endif
1679
1680 void movzwl(Register dst, Address src);
1681 void movzwl(Register dst, Register src);
1682
1683 #ifdef _LP64
1684 void movzwq(Register dst, Address src);
1685 void movzwq(Register dst, Register src);
1686 #endif
1687
1688 // Unsigned multiply with RAX destination register
1689 void mull(Address src);
1690 void mull(Register src);
1691
1692 #ifdef _LP64
1693 void mulq(Address src);
1694 void mulq(Register src);
1695 void mulxq(Register dst1, Register dst2, Register src);
1696 #endif
1697
1698 // Multiply Scalar Double-Precision Floating-Point Values
1699 void mulsd(XMMRegister dst, Address src);
1700 void mulsd(XMMRegister dst, XMMRegister src);
1701
1702 // Multiply Scalar Single-Precision Floating-Point Values
1703 void mulss(XMMRegister dst, Address src);
1704 void mulss(XMMRegister dst, XMMRegister src);
1705
1706 void negl(Register dst);
1707 void negl(Address dst);
1708
1709 #ifdef _LP64
1710 void negq(Register dst);
1711 void negq(Address dst);
1712 #endif
1713
1714 void nop(int i = 1);
1715
1716 void notl(Register dst);
1717
1718 #ifdef _LP64
1719 void notq(Register dst);
1720
1721 void btsq(Address dst, int imm8);
1722 void btrq(Address dst, int imm8);
1723 #endif
1724
1725 void orw(Register dst, Register src);
1726
1727 void orl(Address dst, int32_t imm32);
1728 void orl(Register dst, int32_t imm32);
1729 void orl(Register dst, Address src);
1730 void orl(Register dst, Register src);
1731 void orl(Address dst, Register src);
1732
1733 void orb(Address dst, int imm8);
1734 void orb(Address dst, Register src);
1735
1736 void orq(Address dst, int32_t imm32);
1737 void orq(Address dst, Register src);
1738 void orq(Register dst, int32_t imm32);
1739 void orq_imm32(Register dst, int32_t imm32);
1740 void orq(Register dst, Address src);
1741 void orq(Register dst, Register src);
1742
1743 // Pack with signed saturation
1744 void packsswb(XMMRegister dst, XMMRegister src);
1745 void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1746 void packssdw(XMMRegister dst, XMMRegister src);
1747 void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1748
1749 // Pack with unsigned saturation
1750 void packuswb(XMMRegister dst, XMMRegister src);
1751 void packuswb(XMMRegister dst, Address src);
1752 void packusdw(XMMRegister dst, XMMRegister src);
1753 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1754 void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1755
1756 // Permutations
1757 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1758 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1759 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1760 void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1761 void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1762 void vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1763 void vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1764 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1765 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1766 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1767 void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1768 void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1769 void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1770 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1771 void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1772 void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len);
1773
1774 void pause();
1775
1776 // Undefined Instruction
1777 void ud2();
1778
1779 // SSE4.2 string instructions
1780 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1781 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1782
1783 void pcmpeqb(XMMRegister dst, XMMRegister src);
1784 void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1785
1786 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1787 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1788 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1789 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1790
1791 void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1792 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1793 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1794
1795 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1796 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1797
1798 void pcmpeqw(XMMRegister dst, XMMRegister src);
1799 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1800 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1801 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1802
1803 void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1804
1805 void pcmpeqd(XMMRegister dst, XMMRegister src);
1806 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1807 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1808 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1809
1810 void pcmpeqq(XMMRegister dst, XMMRegister src);
1811 void evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1812 void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1813 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1814 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1815 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1816
1817 void pcmpgtq(XMMRegister dst, XMMRegister src);
1818 void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1819
1820 void pmovmskb(Register dst, XMMRegister src);
1821 void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
1822 void vmovmskps(Register dst, XMMRegister src, int vec_enc);
1823 void vmovmskpd(Register dst, XMMRegister src, int vec_enc);
1824 void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1825 void vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len);
1826
1827
1828 void vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1829 void vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1830 void vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1831 void vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1832
1833 // SSE 4.1 extract
1834 void pextrd(Register dst, XMMRegister src, int imm8);
1835 void pextrq(Register dst, XMMRegister src, int imm8);
1836 void pextrd(Address dst, XMMRegister src, int imm8);
1837 void pextrq(Address dst, XMMRegister src, int imm8);
1838 void pextrb(Register dst, XMMRegister src, int imm8);
1839 void pextrb(Address dst, XMMRegister src, int imm8);
1840 // SSE 2 extract
1841 void pextrw(Register dst, XMMRegister src, int imm8);
1842 void pextrw(Address dst, XMMRegister src, int imm8);
1843
1844 // SSE 4.1 insert
1845 void pinsrd(XMMRegister dst, Register src, int imm8);
1846 void pinsrq(XMMRegister dst, Register src, int imm8);
1847 void pinsrb(XMMRegister dst, Register src, int imm8);
1848 void pinsrd(XMMRegister dst, Address src, int imm8);
1849 void pinsrq(XMMRegister dst, Address src, int imm8);
1850 void pinsrb(XMMRegister dst, Address src, int imm8);
1851 void insertps(XMMRegister dst, XMMRegister src, int imm8);
1852 // SSE 2 insert
1853 void pinsrw(XMMRegister dst, Register src, int imm8);
1854 void pinsrw(XMMRegister dst, Address src, int imm8);
1855
1856 // AVX insert
1857 void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1858 void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1859 void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1860 void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1861 void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1862
1863 // Zero extend moves
1864 void pmovzxbw(XMMRegister dst, XMMRegister src);
1865 void pmovzxbw(XMMRegister dst, Address src);
1866 void pmovzxbd(XMMRegister dst, XMMRegister src);
1867 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1868 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1869 void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
1870 void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
1871 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1872 void vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len);
1873 void pmovzxdq(XMMRegister dst, XMMRegister src);
1874 void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
1875 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1876 void evpmovzxbd(XMMRegister dst, KRegister mask, Address src, int vector_len);
1877 void evpmovzxbd(XMMRegister dst, Address src, int vector_len);
1878
1879 // Sign extend moves
1880 void pmovsxbd(XMMRegister dst, XMMRegister src);
1881 void pmovsxbq(XMMRegister dst, XMMRegister src);
1882 void pmovsxbw(XMMRegister dst, XMMRegister src);
1883 void pmovsxwd(XMMRegister dst, XMMRegister src);
1884 void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
1885 void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
1886 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1887 void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
1888 void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
1889 void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);
1890
1891 void evpmovwb(Address dst, XMMRegister src, int vector_len);
1892 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1893 void evpmovdb(Address dst, XMMRegister src, int vector_len);
1894
1895 // Multiply add
1896 void pmaddwd(XMMRegister dst, XMMRegister src);
1897 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1898 void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1899 void evpmadd52luq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1900 void evpmadd52luq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
1901 void evpmadd52huq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1902 void evpmadd52huq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
1903
1904 // Multiply add accumulate
1905 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1906
1907 #ifndef _LP64 // no 32bit push/pop on amd64
1908 void popl(Address dst);
1909 #endif
1910
1911 #ifdef _LP64
1912 void popq(Address dst);
1913 void popq(Register dst);
1914 #endif
1915
1916 void popcntl(Register dst, Address src);
1917 void popcntl(Register dst, Register src);
1918
1919 void evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1920 void evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1921 void evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1922 void evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1923
1924 #ifdef _LP64
1925 void popcntq(Register dst, Address src);
1926 void popcntq(Register dst, Register src);
1927 #endif
1928
1929 // Prefetches (SSE, SSE2, 3DNOW only)
1930
1931 void prefetchnta(Address src);
1932 void prefetchr(Address src);
1933 void prefetcht0(Address src);
1934 void prefetcht1(Address src);
1935 void prefetcht2(Address src);
1936 void prefetchw(Address src);
1937
1938 // Shuffle Bytes
1939 void pshufb(XMMRegister dst, XMMRegister src);
1940 void pshufb(XMMRegister dst, Address src);
1941 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1942 void evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1943
1944
1945 // Shuffle Packed Doublewords
1946 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1947 void pshufd(XMMRegister dst, Address src, int mode);
1948 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1949
1950 // Shuffle Packed High/Low Words
1951 void pshufhw(XMMRegister dst, XMMRegister src, int mode);
1952 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1953 void pshuflw(XMMRegister dst, Address src, int mode);
1954 void vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1955 void vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1956
1957 //shuffle floats and doubles
1958 void shufps(XMMRegister, XMMRegister, int);
1959 void shufpd(XMMRegister, XMMRegister, int);
1960 void vshufps(XMMRegister, XMMRegister, XMMRegister, int, int);
1961 void vshufpd(XMMRegister, XMMRegister, XMMRegister, int, int);
1962
1963 // Shuffle packed values at 128 bit granularity
1964 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1965
1966 // Shift Right by bytes Logical DoubleQuadword Immediate
1967 void psrldq(XMMRegister dst, int shift);
1968 // Shift Left by bytes Logical DoubleQuadword Immediate
1969 void pslldq(XMMRegister dst, int shift);
1970
1971 // Logical Compare 128bit
1972 void ptest(XMMRegister dst, XMMRegister src);
1973 void ptest(XMMRegister dst, Address src);
1974 // Logical Compare 256bit
1975 void vptest(XMMRegister dst, XMMRegister src);
1976 void vptest(XMMRegister dst, Address src);
1977
1978 void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1979 void evptestmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1980 void evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1981
1982 // Vector compare
1983 void vptest(XMMRegister dst, XMMRegister src, int vector_len);
1984 void vtestps(XMMRegister dst, XMMRegister src, int vector_len);
1985
1986 // Interleave Low Bytes
1987 void punpcklbw(XMMRegister dst, XMMRegister src);
1988 void punpcklbw(XMMRegister dst, Address src);
1989
1990 // Interleave Low Doublewords
1991 void punpckldq(XMMRegister dst, XMMRegister src);
1992 void punpckldq(XMMRegister dst, Address src);
1993 void vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1994
1995 // Interleave High Word
1996 void vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1997
1998 // Interleave Low Word
1999 void vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2000
2001 // Interleave High Doublewords
2002 void vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2003
2004 // Interleave Low Quadwords
2005 void punpcklqdq(XMMRegister dst, XMMRegister src);
2006
2007 void evpunpcklqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2008 void evpunpcklqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
2009 void evpunpckhqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2010 void evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
2011
2012 // Vector sum of absolute difference.
2013 void vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2014
2015 #ifndef _LP64 // no 32bit push/pop on amd64
2016 void pushl(Address src);
2017 #endif
2018
2019 void pushq(Address src);
2020
2021 void rcll(Register dst, int imm8);
2022
2023 void rclq(Register dst, int imm8);
2024
2025 void rcrq(Register dst, int imm8);
2026
2027 void rcpps(XMMRegister dst, XMMRegister src);
2028
2029 void rcpss(XMMRegister dst, XMMRegister src);
2030
2031 void rdtsc();
2032
2033 void ret(int imm16);
2034
2035 void roll(Register dst);
2036
2037 void roll(Register dst, int imm8);
2038
2039 void rorl(Register dst);
2040
2041 void rorl(Register dst, int imm8);
2042
2043 #ifdef _LP64
2044 void rolq(Register dst);
2045 void rolq(Register dst, int imm8);
2046 void rorq(Register dst);
2047 void rorq(Register dst, int imm8);
2048 void rorxl(Register dst, Register src, int imm8);
2049 void rorxl(Register dst, Address src, int imm8);
2050 void rorxq(Register dst, Register src, int imm8);
2051 void rorxq(Register dst, Address src, int imm8);
2052 #endif
2053
2054 void sahf();
2055
2056 void sall(Register dst, int imm8);
2057 void sall(Register dst);
2058 void sall(Address dst, int imm8);
2059 void sall(Address dst);
2060
2061 void sarl(Address dst, int imm8);
2062 void sarl(Address dst);
2063 void sarl(Register dst, int imm8);
2064 void sarl(Register dst);
2065
2066 #ifdef _LP64
2067 void salq(Register dst, int imm8);
2068 void salq(Register dst);
2069 void salq(Address dst, int imm8);
2070 void salq(Address dst);
2071
2072 void sarq(Address dst, int imm8);
2073 void sarq(Address dst);
2074 void sarq(Register dst, int imm8);
2075 void sarq(Register dst);
2076 #endif
2077
2078 void sbbl(Address dst, int32_t imm32);
2079 void sbbl(Register dst, int32_t imm32);
2080 void sbbl(Register dst, Address src);
2081 void sbbl(Register dst, Register src);
2082
2083 void sbbq(Address dst, int32_t imm32);
2084 void sbbq(Register dst, int32_t imm32);
2085 void sbbq(Register dst, Address src);
2086 void sbbq(Register dst, Register src);
2087
2088 void setb(Condition cc, Register dst);
2089
2090 void sete(Register dst);
2091 void setl(Register dst);
2092 void setne(Register dst);
2093
2094 void palignr(XMMRegister dst, XMMRegister src, int imm8);
2095 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2096 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2097
2098 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
2099 void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2100
2101 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
2102 void sha1nexte(XMMRegister dst, XMMRegister src);
2103 void sha1msg1(XMMRegister dst, XMMRegister src);
2104 void sha1msg2(XMMRegister dst, XMMRegister src);
2105 // xmm0 is implicit additional source to the following instruction.
2106 void sha256rnds2(XMMRegister dst, XMMRegister src);
2107 void sha256msg1(XMMRegister dst, XMMRegister src);
2108 void sha256msg2(XMMRegister dst, XMMRegister src);
2109
2110 void shldl(Register dst, Register src);
2111 void shldl(Register dst, Register src, int8_t imm8);
2112 void shrdl(Register dst, Register src);
2113 void shrdl(Register dst, Register src, int8_t imm8);
2114 #ifdef _LP64
2115 void shldq(Register dst, Register src, int8_t imm8);
2116 void shrdq(Register dst, Register src, int8_t imm8);
2117 #endif
2118
2119 void shll(Register dst, int imm8);
2120 void shll(Register dst);
2121
2122 void shlq(Register dst, int imm8);
2123 void shlq(Register dst);
2124
2125 void shrl(Register dst, int imm8);
2126 void shrl(Register dst);
2127 void shrl(Address dst);
2128 void shrl(Address dst, int imm8);
2129
2130 void shrq(Register dst, int imm8);
2131 void shrq(Register dst);
2132 void shrq(Address dst);
2133 void shrq(Address dst, int imm8);
2134
2135 void smovl(); // QQQ generic?
2136
2137 // Compute Square Root of Scalar Double-Precision Floating-Point Value
2138 void sqrtsd(XMMRegister dst, Address src);
2139 void sqrtsd(XMMRegister dst, XMMRegister src);
2140
2141 void roundsd(XMMRegister dst, Address src, int32_t rmode);
2142 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
2143
2144 // Compute Square Root of Scalar Single-Precision Floating-Point Value
2145 void sqrtss(XMMRegister dst, Address src);
2146 void sqrtss(XMMRegister dst, XMMRegister src);
2147
2148 void std();
2149
2150 void stmxcsr( Address dst );
2151
2152 void subl(Address dst, int32_t imm32);
2153 void subl(Address dst, Register src);
2154 void subl(Register dst, int32_t imm32);
2155 void subl(Register dst, Address src);
2156 void subl(Register dst, Register src);
2157
2158 void subq(Address dst, int32_t imm32);
2159 void subq(Address dst, Register src);
2160 void subq(Register dst, int32_t imm32);
2161 void subq(Register dst, Address src);
2162 void subq(Register dst, Register src);
2163
2164 // Force generation of a 4 byte immediate value even if it fits into 8bit
2165 void subl_imm32(Register dst, int32_t imm32);
2166 void subq_imm32(Register dst, int32_t imm32);
2167
2168 // Subtract Scalar Double-Precision Floating-Point Values
2169 void subsd(XMMRegister dst, Address src);
2170 void subsd(XMMRegister dst, XMMRegister src);
2171
2172 // Subtract Scalar Single-Precision Floating-Point Values
2173 void subss(XMMRegister dst, Address src);
2174 void subss(XMMRegister dst, XMMRegister src);
2175
2176 void testb(Address dst, int imm8);
2177 void testb(Register dst, int imm8);
2178
2179 void testl(Address dst, int32_t imm32);
2180 void testl(Register dst, int32_t imm32);
2181 void testl(Register dst, Register src);
2182 void testl(Register dst, Address src);
2183
2184 void testq(Address dst, int32_t imm32);
2185 void testq(Register dst, int32_t imm32);
2186 void testq(Register dst, Register src);
2187 void testq(Register dst, Address src);
2188
2189 // BMI - count trailing zeros
2190 void tzcntl(Register dst, Register src);
2191 void tzcntl(Register dst, Address src);
2192 void tzcntq(Register dst, Register src);
2193 void tzcntq(Register dst, Address src);
2194
2195 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
2196 void ucomisd(XMMRegister dst, Address src);
2197 void ucomisd(XMMRegister dst, XMMRegister src);
2198
2199 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
2200 void ucomiss(XMMRegister dst, Address src);
2201 void ucomiss(XMMRegister dst, XMMRegister src);
2202
2203 void xabort(int8_t imm8);
2204
2205 void xaddb(Address dst, Register src);
2206 void xaddw(Address dst, Register src);
2207 void xaddl(Address dst, Register src);
2208 void xaddq(Address dst, Register src);
2209
2210 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
2211
2212 void xchgb(Register reg, Address adr);
2213 void xchgw(Register reg, Address adr);
2214 void xchgl(Register reg, Address adr);
2215 void xchgl(Register dst, Register src);
2216
2217 void xchgq(Register reg, Address adr);
2218 void xchgq(Register dst, Register src);
2219
2220 void xend();
2221
2222 // Get Value of Extended Control Register
2223 void xgetbv();
2224
2225 void xorl(Register dst, int32_t imm32);
2226 void xorl(Address dst, int32_t imm32);
2227 void xorl(Register dst, Address src);
2228 void xorl(Register dst, Register src);
2229 void xorl(Address dst, Register src);
2230
2231 void xorb(Address dst, Register src);
2232 void xorb(Register dst, Address src);
2233 void xorw(Register dst, Register src);
2234
2235 void xorq(Register dst, Address src);
2236 void xorq(Address dst, int32_t imm32);
2237 void xorq(Register dst, Register src);
2238 void xorq(Register dst, int32_t imm32);
2239 void xorq(Address dst, Register src);
2240
2241 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
2242
2243 // AVX 3-operands scalar instructions (encoded with VEX prefix)
2244
2245 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
2246 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2247 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
2248 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2249 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
2250 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2251 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
2252 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2253 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2254 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2255 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
2256 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2257 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
2258 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2259 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
2260 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2261 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
2262 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2263
2264 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2265 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2266 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2267 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2268
2269 void sarxl(Register dst, Register src1, Register src2);
2270 void sarxl(Register dst, Address src1, Register src2);
2271 void sarxq(Register dst, Register src1, Register src2);
2272 void sarxq(Register dst, Address src1, Register src2);
2273 void shlxl(Register dst, Register src1, Register src2);
2274 void shlxl(Register dst, Address src1, Register src2);
2275 void shlxq(Register dst, Register src1, Register src2);
2276 void shlxq(Register dst, Address src1, Register src2);
2277 void shrxl(Register dst, Register src1, Register src2);
2278 void shrxl(Register dst, Address src1, Register src2);
2279 void shrxq(Register dst, Register src1, Register src2);
2280 void shrxq(Register dst, Address src1, Register src2);
2281
2282 void bzhiq(Register dst, Register src1, Register src2);
2283
2284 void pextl(Register dst, Register src1, Register src2);
2285 void pdepl(Register dst, Register src1, Register src2);
2286 void pextq(Register dst, Register src1, Register src2);
2287 void pdepq(Register dst, Register src1, Register src2);
2288 void pextl(Register dst, Register src1, Address src2);
2289 void pdepl(Register dst, Register src1, Address src2);
2290 void pextq(Register dst, Register src1, Address src2);
2291 void pdepq(Register dst, Register src1, Address src2);
2292
2293
2294 //====================VECTOR ARITHMETIC=====================================
2295 // Add Packed Floating-Point Values
2296 void addpd(XMMRegister dst, XMMRegister src);
2297 void addpd(XMMRegister dst, Address src);
2298 void addps(XMMRegister dst, XMMRegister src);
2299 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2300 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2301 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2302 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2303
2304 // Subtract Packed Floating-Point Values
2305 void subpd(XMMRegister dst, XMMRegister src);
2306 void subps(XMMRegister dst, XMMRegister src);
2307 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2308 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2309 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2310 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2311
2312 // Multiply Packed Floating-Point Values
2313 void mulpd(XMMRegister dst, XMMRegister src);
2314 void mulpd(XMMRegister dst, Address src);
2315 void mulps(XMMRegister dst, XMMRegister src);
2316 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2317 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2318 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2319 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2320
2321 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2322 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2323 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2324 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2325
2326 // Divide Packed Floating-Point Values
2327 void divpd(XMMRegister dst, XMMRegister src);
2328 void divps(XMMRegister dst, XMMRegister src);
2329 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2330 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2331 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2332 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2333
2334 // Sqrt Packed Floating-Point Values
2335 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2336 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2337 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2338 void vsqrtps(XMMRegister dst, Address src, int vector_len);
2339
2340 // Round Packed Double precision value.
2341 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2342 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2343 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2344 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2345
2346 // Bitwise Logical AND of Packed Floating-Point Values
2347 void andpd(XMMRegister dst, XMMRegister src);
2348 void andps(XMMRegister dst, XMMRegister src);
2349 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2350 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2351 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2352 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2353
2354 void unpckhpd(XMMRegister dst, XMMRegister src);
2355 void unpcklpd(XMMRegister dst, XMMRegister src);
2356
2357 // Bitwise Logical XOR of Packed Floating-Point Values
2358 void xorpd(XMMRegister dst, XMMRegister src);
2359 void xorps(XMMRegister dst, XMMRegister src);
2360 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2361 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2362 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2363 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2364
2365 // Add horizontal packed integers
2366 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2367 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2368 void phaddw(XMMRegister dst, XMMRegister src);
2369 void phaddd(XMMRegister dst, XMMRegister src);
2370
2371 // Add packed integers
2372 void paddb(XMMRegister dst, XMMRegister src);
2373 void paddw(XMMRegister dst, XMMRegister src);
2374 void paddd(XMMRegister dst, XMMRegister src);
2375 void paddd(XMMRegister dst, Address src);
2376 void paddq(XMMRegister dst, XMMRegister src);
2377 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2378 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2379 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2380 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2381 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2382 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2383 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2384 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2385
2386 // Leaf level assembler routines for masked operations.
2387 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2388 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2389 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2390 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2391 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2392 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2393 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2394 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2395 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2396 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2397 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2398 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2399 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2400 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2401 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2402 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2403 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2404 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2405 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2406 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2407 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2408 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2409 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2410 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2411 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2412 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2413 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2414 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2415 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2416 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2417 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2418 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2419 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2420 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2421 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2422 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2423 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2424 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2425 void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2426 void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2427 void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2428 void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2429 void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2430 void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2431 void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2432 void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2433 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2434 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2435 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2436 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2437 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2438 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2439 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2440 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2441 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2442 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2443 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2444 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2445 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2446 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2447 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2448 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2449 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2450 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2451 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2452 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2453 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2454 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2455 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2456 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2457 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2458
2459 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2460 void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2461 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2462 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2463 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2464 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2465 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2466 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2467 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2468
2469 void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2470 void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2471 void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2472 void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2473 void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2474 void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2475 void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2476 void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2477 void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2478 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2479 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2480 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2481 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2482 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2483 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2484 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2485 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2486 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2487 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2488 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2489 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2490 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2491 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2492 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2493 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2494 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2495 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2496 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2497 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2498 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2499 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2500 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2501 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2502 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2503 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2504 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2505 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2506
2507 void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2508 void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2509 void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2510 void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2511 void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2512 void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2513 void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2514 void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2515
2516 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2517 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2518 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2519 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2520
2521 void evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2522 void evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2523
2524 // Sub packed integers
2525 void psubb(XMMRegister dst, XMMRegister src);
2526 void psubw(XMMRegister dst, XMMRegister src);
2527 void psubd(XMMRegister dst, XMMRegister src);
2528 void psubq(XMMRegister dst, XMMRegister src);
2529 void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2530 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2531 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2532 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2533 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2534 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2535 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2536 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2537 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2538
2539 // Multiply packed integers (only shorts and ints)
2540 void pmullw(XMMRegister dst, XMMRegister src);
2541 void pmulld(XMMRegister dst, XMMRegister src);
2542 void pmuludq(XMMRegister dst, XMMRegister src);
2543 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2544 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2545 void evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2546 void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2547 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2548 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2549 void evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2550 void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2551
2552 // Minimum of packed integers
2553 void pminsb(XMMRegister dst, XMMRegister src);
2554 void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2555 void pminsw(XMMRegister dst, XMMRegister src);
2556 void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2557 void pminsd(XMMRegister dst, XMMRegister src);
2558 void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2559 void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2560 void minps(XMMRegister dst, XMMRegister src);
2561 void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2562 void minpd(XMMRegister dst, XMMRegister src);
2563 void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2564
2565 // Maximum of packed integers
2566 void pmaxsb(XMMRegister dst, XMMRegister src);
2567 void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2568 void pmaxsw(XMMRegister dst, XMMRegister src);
2569 void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2570 void pmaxsd(XMMRegister dst, XMMRegister src);
2571 void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2572 void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2573 void maxps(XMMRegister dst, XMMRegister src);
2574 void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2575 void maxpd(XMMRegister dst, XMMRegister src);
2576 void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2577
2578 // Shift left packed integers
2579 void psllw(XMMRegister dst, int shift);
2580 void pslld(XMMRegister dst, int shift);
2581 void psllq(XMMRegister dst, int shift);
2582 void psllw(XMMRegister dst, XMMRegister shift);
2583 void pslld(XMMRegister dst, XMMRegister shift);
2584 void psllq(XMMRegister dst, XMMRegister shift);
2585 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2586 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2587 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2588 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2589 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2590 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2591 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2592
2593 // Logical shift right packed integers
2594 void psrlw(XMMRegister dst, int shift);
2595 void psrld(XMMRegister dst, int shift);
2596 void psrlq(XMMRegister dst, int shift);
2597 void psrlw(XMMRegister dst, XMMRegister shift);
2598 void psrld(XMMRegister dst, XMMRegister shift);
2599 void psrlq(XMMRegister dst, XMMRegister shift);
2600 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2601 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2602 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2603 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2604 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2605 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2606 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2607 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2608 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2609
2610 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2611 void psraw(XMMRegister dst, int shift);
2612 void psrad(XMMRegister dst, int shift);
2613 void psraw(XMMRegister dst, XMMRegister shift);
2614 void psrad(XMMRegister dst, XMMRegister shift);
2615 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2616 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2617 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2618 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2619 void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2620 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2621 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2622
2623 // Variable shift left packed integers
2624 void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2625 void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2626
2627 // Variable shift right packed integers
2628 void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2629 void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2630
2631 // Variable shift right arithmetic packed integers
2632 void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2633 void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2634
2635 void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2636 void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2637
2638 // And packed integers
2639 void pand(XMMRegister dst, XMMRegister src);
2640 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2641 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2642 void evpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2643 void evpandq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2644
2645 // Andn packed integers
2646 void pandn(XMMRegister dst, XMMRegister src);
2647 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2648
2649 // Or packed integers
2650 void por(XMMRegister dst, XMMRegister src);
2651 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2652 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2653 void evporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2654 void evporq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2655
2656 // Xor packed integers
2657 void pxor(XMMRegister dst, XMMRegister src);
2658 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2659 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2660 void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2661 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2662 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2663
2664 // Ternary logic instruction.
2665 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2666 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len);
2667 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2668 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len);
2669
2670 // Vector compress/expand instructions.
2671 void evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2672 void evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2673 void evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2674 void evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2675 void evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2676 void evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2677
2678 void evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2679 void evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2680 void evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2681 void evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2682 void evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2683 void evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2684
2685 // Vector Rotate Left/Right instruction.
2686 void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2687 void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2688 void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2689 void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2690 void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2691 void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2692 void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2693 void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2694
2695 // vinserti forms
2696 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2697 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2698 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2699 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2700 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2701
2702 // vinsertf forms
2703 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2704 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2705 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2706 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2707 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2708 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2709
2710 // vextracti forms
2711 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2712 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2713 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2714 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2715 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2716 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2717 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2718
2719 // vextractf forms
2720 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2721 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2722 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2723 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2724 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2725 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2726 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2727
2728 // xmm/mem sourced byte/word/dword/qword replicate
2729 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2730 void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2731 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2732 void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2733 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2734 void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2735 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2736 void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2737
2738 void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
2739 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2740 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2741
2742 // scalar single/double/128bit precision replicate
2743 void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2744 void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2745 void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2746 void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2747 void vbroadcastf128(XMMRegister dst, Address src, int vector_len);
2748
2749 // gpr sourced byte/word/dword/qword replicate
2750 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2751 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2752 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2753 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2754
2755 // Gather AVX2 and AVX3
2756 void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2757 void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2758 void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2759 void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2760 void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2761 void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len);
2762 void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2763 void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len);
2764
2765 //Scatter AVX3 only
2766 void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2767 void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len);
2768 void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len);
2769 void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2770
2771 // Carry-Less Multiplication Quadword
2772 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2773 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2774 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2775 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2776 // to avoid transaction penalty between AVX and SSE states. There is no
2777 // penalty if legacy SSE instructions are encoded using VEX prefix because
2778 // they always clear upper 128 bits. It should be used before calling
2779 // runtime code and native libraries.
2780 void vzeroupper();
2781
2782 void vzeroall();
2783
2784 // Vector double compares
2785 void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2786 void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2787 ComparisonPredicateFP comparison, int vector_len);
2788
2789 // Vector float compares
2790 void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
2791 void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2792 ComparisonPredicateFP comparison, int vector_len);
2793
2794 // Vector integer compares
2795 void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2796 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2797 int comparison, bool is_signed, int vector_len);
2798 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2799 int comparison, bool is_signed, int vector_len);
2800
2801 // Vector long compares
2802 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2803 int comparison, bool is_signed, int vector_len);
2804 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2805 int comparison, bool is_signed, int vector_len);
2806
2807 // Vector byte compares
2808 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2809 int comparison, bool is_signed, int vector_len);
2810 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2811 int comparison, bool is_signed, int vector_len);
2812
2813 // Vector short compares
2814 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2815 int comparison, bool is_signed, int vector_len);
2816 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2817 int comparison, bool is_signed, int vector_len);
2818
2819 void evpmovb2m(KRegister dst, XMMRegister src, int vector_len);
2820 void evpmovw2m(KRegister dst, XMMRegister src, int vector_len);
2821 void evpmovd2m(KRegister dst, XMMRegister src, int vector_len);
2822 void evpmovq2m(KRegister dst, XMMRegister src, int vector_len);
2823 void evpmovm2b(XMMRegister dst, KRegister src, int vector_len);
2824 void evpmovm2w(XMMRegister dst, KRegister src, int vector_len);
2825 void evpmovm2d(XMMRegister dst, KRegister src, int vector_len);
2826 void evpmovm2q(XMMRegister dst, KRegister src, int vector_len);
2827
2828 // floating point class tests
2829 void vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8);
2830 void vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8);
2831
2832 // Vector blends
2833 void blendvps(XMMRegister dst, XMMRegister src);
2834 void blendvpd(XMMRegister dst, XMMRegister src);
2835 void pblendvb(XMMRegister dst, XMMRegister src);
2836 void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2837 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2838 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2839 void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2840 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2841 void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2842 void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2843 void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2844 void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2845 void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2846 void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2847
2848 // Galois field affine transformation instructions.
2849 void gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8);
2850 void vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len);
2851
2852 protected:
2853 // Next instructions require address alignment 16 bytes SSE mode.
2854 // They should be called only from corresponding MacroAssembler instructions.
2855 void andpd(XMMRegister dst, Address src);
2856 void andps(XMMRegister dst, Address src);
2857 void xorpd(XMMRegister dst, Address src);
2858 void xorps(XMMRegister dst, Address src);
2859
2860 };
2861
2862 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2863 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2864 // are applied.
2865 class InstructionAttr {
2866 public:
2867 InstructionAttr(
2868 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2869 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2870 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2871 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2872 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2873 :
2874 _rex_vex_w(rex_vex_w),
2875 _legacy_mode(legacy_mode || UseAVX < 3),
2876 _no_reg_mask(no_reg_mask),
2877 _uses_vl(uses_vl),
2878 _rex_vex_w_reverted(false),
2879 _is_evex_instruction(false),
2880 _is_clear_context(true),
2881 _is_extended_context(false),
2882 _avx_vector_len(vector_len),
2883 _tuple_type(Assembler::EVEX_ETUP),
2884 _input_size_in_bits(Assembler::EVEX_NObit),
2885 _evex_encoding(0),
2886 _embedded_opmask_register_specifier(0), // hard code k0
2887 _current_assembler(NULL) { }
2888
2889 ~InstructionAttr() {
2890 if (_current_assembler != NULL) {
2891 _current_assembler->clear_attributes();
2892 }
2893 _current_assembler = NULL;
2894 }
2895
2896 private:
2897 bool _rex_vex_w;
2898 bool _legacy_mode;
2899 bool _no_reg_mask;
2900 bool _uses_vl;
2901 bool _rex_vex_w_reverted;
2902 bool _is_evex_instruction;
2903 bool _is_clear_context;
2904 bool _is_extended_context;
2905 int _avx_vector_len;
2906 int _tuple_type;
2907 int _input_size_in_bits;
2908 int _evex_encoding;
2909 int _embedded_opmask_register_specifier;
2910
2911 Assembler *_current_assembler;
2912
2913 public:
2914 // query functions for field accessors
2915 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2916 bool is_legacy_mode(void) const { return _legacy_mode; }
2917 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2918 bool uses_vl(void) const { return _uses_vl; }
2919 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2920 bool is_evex_instruction(void) const { return _is_evex_instruction; }
2921 bool is_clear_context(void) const { return _is_clear_context; }
2922 bool is_extended_context(void) const { return _is_extended_context; }
2923 int get_vector_len(void) const { return _avx_vector_len; }
2924 int get_tuple_type(void) const { return _tuple_type; }
2925 int get_input_size(void) const { return _input_size_in_bits; }
2926 int get_evex_encoding(void) const { return _evex_encoding; }
2927 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2928
2929 // Set the vector len manually
2930 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2931
2932 // Set revert rex_vex_w for avx encoding
2933 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2934
2935 // Set rex_vex_w based on state
2936 void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2937
2938 // Set the instruction to be encoded in AVX mode
2939 void set_is_legacy_mode(void) { _legacy_mode = true; }
2940
2941 // Set the current instruction to be encoded as an EVEX instruction
2942 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2943
2944 // Internal encoding data used in compressed immediate offset programming
2945 void set_evex_encoding(int value) { _evex_encoding = value; }
2946
2947 // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
2948 // This method unsets it so that merge semantics are used instead.
2949 void reset_is_clear_context(void) { _is_clear_context = false; }
2950
2951 // Map back to current assembler so that we can manage object level association
2952 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2953
2954 // Address modifiers used for compressed displacement calculation
2955 void set_address_attributes(int tuple_type, int input_size_in_bits);
2956
2957 // Set embedded opmask register specifier.
2958 void set_embedded_opmask_register_specifier(KRegister mask) {
2959 _embedded_opmask_register_specifier = mask->encoding() & 0x7;
2960 }
2961
2962 };
2963
2964 #endif // CPU_X86_ASSEMBLER_X86_HPP