1 /*
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   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
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   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
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  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
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  20  * or visit www.oracle.com if you need additional information or have any
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  24 
  25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
  26 #define CPU_X86_ASSEMBLER_X86_HPP
  27 
  28 #include "asm/register.hpp"
  29 #include "utilities/powerOfTwo.hpp"
  30 
  31 // Contains all the definitions needed for x86 assembly code generation.
  32 
  33 // Calling convention
  34 class Argument {
  35  public:
  36   enum {
  37 #ifdef _LP64
  38 #ifdef _WIN64
  39     n_int_register_parameters_c   = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
  40     n_float_register_parameters_c = 4,  // xmm0 - xmm3 (c_farg0, c_farg1, ... )
  41     n_int_register_returns_c = 1, // rax
  42     n_float_register_returns_c = 1, // xmm0
  43 #else
  44     n_int_register_parameters_c   = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
  45     n_float_register_parameters_c = 8,  // xmm0 - xmm7 (c_farg0, c_farg1, ... )
  46     n_int_register_returns_c = 2, // rax, rdx
  47     n_float_register_returns_c = 2, // xmm0, xmm1
  48 #endif // _WIN64
  49     n_int_register_parameters_j   = 6, // j_rarg0, j_rarg1, ...
  50     n_float_register_parameters_j = 8  // j_farg0, j_farg1, ...
  51 #else
  52     n_register_parameters = 0,   // 0 registers used to pass arguments
  53     n_int_register_parameters_j   = 0,
  54     n_float_register_parameters_j = 0
  55 #endif // _LP64
  56   };
  57 };
  58 
  59 
  60 #ifdef _LP64
  61 // Symbolically name the register arguments used by the c calling convention.
  62 // Windows is different from linux/solaris. So much for standards...
  63 
  64 #ifdef _WIN64
  65 
  66 constexpr Register c_rarg0 = rcx;
  67 constexpr Register c_rarg1 = rdx;
  68 constexpr Register c_rarg2 =  r8;
  69 constexpr Register c_rarg3 =  r9;
  70 
  71 constexpr XMMRegister c_farg0 = xmm0;
  72 constexpr XMMRegister c_farg1 = xmm1;
  73 constexpr XMMRegister c_farg2 = xmm2;
  74 constexpr XMMRegister c_farg3 = xmm3;
  75 
  76 #else
  77 
  78 constexpr Register c_rarg0 = rdi;
  79 constexpr Register c_rarg1 = rsi;
  80 constexpr Register c_rarg2 = rdx;
  81 constexpr Register c_rarg3 = rcx;
  82 constexpr Register c_rarg4 =  r8;
  83 constexpr Register c_rarg5 =  r9;
  84 
  85 constexpr XMMRegister c_farg0 = xmm0;
  86 constexpr XMMRegister c_farg1 = xmm1;
  87 constexpr XMMRegister c_farg2 = xmm2;
  88 constexpr XMMRegister c_farg3 = xmm3;
  89 constexpr XMMRegister c_farg4 = xmm4;
  90 constexpr XMMRegister c_farg5 = xmm5;
  91 constexpr XMMRegister c_farg6 = xmm6;
  92 constexpr XMMRegister c_farg7 = xmm7;
  93 
  94 #endif // _WIN64
  95 
  96 // Symbolically name the register arguments used by the Java calling convention.
  97 // We have control over the convention for java so we can do what we please.
  98 // What pleases us is to offset the java calling convention so that when
  99 // we call a suitable jni method the arguments are lined up and we don't
 100 // have to do little shuffling. A suitable jni method is non-static and a
 101 // small number of arguments (two fewer args on windows)
 102 //
 103 //        |-------------------------------------------------------|
 104 //        | c_rarg0   c_rarg1  c_rarg2 c_rarg3 c_rarg4 c_rarg5    |
 105 //        |-------------------------------------------------------|
 106 //        | rcx       rdx      r8      r9      rdi*    rsi*       | windows (* not a c_rarg)
 107 //        | rdi       rsi      rdx     rcx     r8      r9         | solaris/linux
 108 //        |-------------------------------------------------------|
 109 //        | j_rarg5   j_rarg0  j_rarg1 j_rarg2 j_rarg3 j_rarg4    |
 110 //        |-------------------------------------------------------|
 111 
 112 constexpr Register j_rarg0 = c_rarg1;
 113 constexpr Register j_rarg1 = c_rarg2;
 114 constexpr Register j_rarg2 = c_rarg3;
 115 // Windows runs out of register args here
 116 #ifdef _WIN64
 117 constexpr Register j_rarg3 = rdi;
 118 constexpr Register j_rarg4 = rsi;
 119 #else
 120 constexpr Register j_rarg3 = c_rarg4;
 121 constexpr Register j_rarg4 = c_rarg5;
 122 #endif /* _WIN64 */
 123 constexpr Register j_rarg5 = c_rarg0;
 124 
 125 constexpr XMMRegister j_farg0 = xmm0;
 126 constexpr XMMRegister j_farg1 = xmm1;
 127 constexpr XMMRegister j_farg2 = xmm2;
 128 constexpr XMMRegister j_farg3 = xmm3;
 129 constexpr XMMRegister j_farg4 = xmm4;
 130 constexpr XMMRegister j_farg5 = xmm5;
 131 constexpr XMMRegister j_farg6 = xmm6;
 132 constexpr XMMRegister j_farg7 = xmm7;
 133 
 134 constexpr Register rscratch1 = r10;  // volatile
 135 constexpr Register rscratch2 = r11;  // volatile
 136 
 137 constexpr Register r12_heapbase = r12; // callee-saved
 138 constexpr Register r15_thread   = r15; // callee-saved
 139 
 140 #else
 141 // rscratch1 will appear in 32bit code that is dead but of course must compile
 142 // Using noreg ensures if the dead code is incorrectly live and executed it
 143 // will cause an assertion failure
 144 #define rscratch1 noreg
 145 #define rscratch2 noreg
 146 
 147 #endif // _LP64
 148 
 149 // JSR 292
 150 // On x86, the SP does not have to be saved when invoking method handle intrinsics
 151 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
 152 constexpr Register rbp_mh_SP_save = noreg;
 153 
 154 // Address is an abstraction used to represent a memory location
 155 // using any of the amd64 addressing modes with one object.
 156 //
 157 // Note: A register location is represented via a Register, not
 158 //       via an address for efficiency & simplicity reasons.
 159 
 160 class ArrayAddress;
 161 
 162 class Address {
 163  public:
 164   enum ScaleFactor {
 165     no_scale = -1,
 166     times_1  =  0,
 167     times_2  =  1,
 168     times_4  =  2,
 169     times_8  =  3,
 170     times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
 171   };
 172   static ScaleFactor times(int size) {
 173     assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
 174     if (size == 8)  return times_8;
 175     if (size == 4)  return times_4;
 176     if (size == 2)  return times_2;
 177     return times_1;
 178   }
 179   static int scale_size(ScaleFactor scale) {
 180     assert(scale != no_scale, "");
 181     assert(((1 << (int)times_1) == 1 &&
 182             (1 << (int)times_2) == 2 &&
 183             (1 << (int)times_4) == 4 &&
 184             (1 << (int)times_8) == 8), "");
 185     return (1 << (int)scale);
 186   }
 187 
 188  private:
 189   Register         _base;
 190   Register         _index;
 191   XMMRegister      _xmmindex;
 192   ScaleFactor      _scale;
 193   int              _disp;
 194   bool             _isxmmindex;
 195   RelocationHolder _rspec;
 196 
 197   // Easily misused constructors make them private
 198   // %%% can we make these go away?
 199   NOT_LP64(Address(address loc, RelocationHolder spec);)
 200   Address(int disp, address loc, relocInfo::relocType rtype);
 201   Address(int disp, address loc, RelocationHolder spec);
 202 
 203  public:
 204 
 205  int disp() { return _disp; }
 206   // creation
 207   Address()
 208     : _base(noreg),
 209       _index(noreg),
 210       _xmmindex(xnoreg),
 211       _scale(no_scale),
 212       _disp(0),
 213       _isxmmindex(false){
 214   }
 215 
 216   // No default displacement otherwise Register can be implicitly
 217   // converted to 0(Register) which is quite a different animal.
 218 
 219   Address(Register base, int disp)
 220     : _base(base),
 221       _index(noreg),
 222       _xmmindex(xnoreg),
 223       _scale(no_scale),
 224       _disp(disp),
 225       _isxmmindex(false){
 226   }
 227 
 228   Address(Register base, Register index, ScaleFactor scale, int disp = 0)
 229     : _base (base),
 230       _index(index),
 231       _xmmindex(xnoreg),
 232       _scale(scale),
 233       _disp (disp),
 234       _isxmmindex(false) {
 235     assert(!index->is_valid() == (scale == Address::no_scale),
 236            "inconsistent address");
 237   }
 238 
 239   Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
 240     : _base (base),
 241       _index(index.register_or_noreg()),
 242       _xmmindex(xnoreg),
 243       _scale(scale),
 244       _disp (disp + (index.constant_or_zero() * scale_size(scale))),
 245       _isxmmindex(false){
 246     if (!index.is_register())  scale = Address::no_scale;
 247     assert(!_index->is_valid() == (scale == Address::no_scale),
 248            "inconsistent address");
 249   }
 250 
 251   Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
 252     : _base (base),
 253       _index(noreg),
 254       _xmmindex(index),
 255       _scale(scale),
 256       _disp(disp),
 257       _isxmmindex(true) {
 258       assert(!index->is_valid() == (scale == Address::no_scale),
 259              "inconsistent address");
 260   }
 261 
 262   // The following overloads are used in connection with the
 263   // ByteSize type (see sizes.hpp).  They simplify the use of
 264   // ByteSize'd arguments in assembly code.
 265 
 266   Address(Register base, ByteSize disp)
 267     : Address(base, in_bytes(disp)) {}
 268 
 269   Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
 270     : Address(base, index, scale, in_bytes(disp)) {}
 271 
 272   Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
 273     : Address(base, index, scale, in_bytes(disp)) {}
 274 
 275   Address plus_disp(int disp) const {
 276     Address a = (*this);
 277     a._disp += disp;
 278     return a;
 279   }
 280   Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
 281     Address a = (*this);
 282     a._disp += disp.constant_or_zero() * scale_size(scale);
 283     if (disp.is_register()) {
 284       assert(!a.index()->is_valid(), "competing indexes");
 285       a._index = disp.as_register();
 286       a._scale = scale;
 287     }
 288     return a;
 289   }
 290   bool is_same_address(Address a) const {
 291     // disregard _rspec
 292     return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
 293   }
 294 
 295   // accessors
 296   bool        uses(Register reg) const { return _base == reg || _index == reg; }
 297   Register    base()             const { return _base;  }
 298   Register    index()            const { return _index; }
 299   XMMRegister xmmindex()         const { return _xmmindex; }
 300   ScaleFactor scale()            const { return _scale; }
 301   int         disp()             const { return _disp;  }
 302   bool        isxmmindex()       const { return _isxmmindex; }
 303 
 304   // Convert the raw encoding form into the form expected by the constructor for
 305   // Address.  An index of 4 (rsp) corresponds to having no index, so convert
 306   // that to noreg for the Address constructor.
 307   static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
 308 
 309   static Address make_array(ArrayAddress);
 310 
 311  private:
 312   bool base_needs_rex() const {
 313     return _base->is_valid() && _base->encoding() >= 8;
 314   }
 315 
 316   bool index_needs_rex() const {
 317     return _index->is_valid() &&_index->encoding() >= 8;
 318   }
 319 
 320   bool xmmindex_needs_rex() const {
 321     return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
 322   }
 323 
 324   relocInfo::relocType reloc() const { return _rspec.type(); }
 325 
 326   friend class Assembler;
 327   friend class MacroAssembler;
 328   friend class LIR_Assembler; // base/index/scale/disp
 329 };
 330 
 331 //
 332 // AddressLiteral has been split out from Address because operands of this type
 333 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
 334 // the few instructions that need to deal with address literals are unique and the
 335 // MacroAssembler does not have to implement every instruction in the Assembler
 336 // in order to search for address literals that may need special handling depending
 337 // on the instruction and the platform. As small step on the way to merging i486/amd64
 338 // directories.
 339 //
 340 class AddressLiteral {
 341   friend class ArrayAddress;
 342   RelocationHolder _rspec;
 343   // Typically we use AddressLiterals we want to use their rval
 344   // However in some situations we want the lval (effect address) of the item.
 345   // We provide a special factory for making those lvals.
 346   bool _is_lval;
 347 
 348   // If the target is far we'll need to load the ea of this to
 349   // a register to reach it. Otherwise if near we can do rip
 350   // relative addressing.
 351 
 352   address          _target;
 353 
 354  protected:
 355   // creation
 356   AddressLiteral()
 357     : _is_lval(false),
 358       _target(NULL)
 359   {}
 360 
 361   public:
 362 
 363 
 364   AddressLiteral(address target, relocInfo::relocType rtype);
 365 
 366   AddressLiteral(address target, RelocationHolder const& rspec)
 367     : _rspec(rspec),
 368       _is_lval(false),
 369       _target(target)
 370   {}
 371 
 372   AddressLiteral addr() {
 373     AddressLiteral ret = *this;
 374     ret._is_lval = true;
 375     return ret;
 376   }
 377 
 378 
 379  private:
 380 
 381   address target() { return _target; }
 382   bool is_lval() const { return _is_lval; }
 383 
 384   relocInfo::relocType reloc() const { return _rspec.type(); }
 385   const RelocationHolder& rspec() const { return _rspec; }
 386 
 387   friend class Assembler;
 388   friend class MacroAssembler;
 389   friend class Address;
 390   friend class LIR_Assembler;
 391 };
 392 
 393 // Convenience classes
 394 class RuntimeAddress: public AddressLiteral {
 395 
 396   public:
 397 
 398   RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
 399 
 400 };
 401 
 402 class ExternalAddress: public AddressLiteral {
 403  private:
 404   static relocInfo::relocType reloc_for_target(address target) {
 405     // Sometimes ExternalAddress is used for values which aren't
 406     // exactly addresses, like the card table base.
 407     // external_word_type can't be used for values in the first page
 408     // so just skip the reloc in that case.
 409     return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
 410   }
 411 
 412  public:
 413 
 414   ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
 415 
 416 };
 417 
 418 class InternalAddress: public AddressLiteral {
 419 
 420   public:
 421 
 422   InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
 423 
 424 };
 425 
 426 // x86 can do array addressing as a single operation since disp can be an absolute
 427 // address amd64 can't. We create a class that expresses the concept but does extra
 428 // magic on amd64 to get the final result
 429 
 430 class ArrayAddress {
 431   private:
 432 
 433   AddressLiteral _base;
 434   Address        _index;
 435 
 436   public:
 437 
 438   ArrayAddress() {};
 439   ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
 440   AddressLiteral base() { return _base; }
 441   Address index() { return _index; }
 442 
 443 };
 444 
 445 class InstructionAttr;
 446 
 447 // 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
 448 // See fxsave and xsave(EVEX enabled) documentation for layout
 449 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
 450 
 451 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
 452 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
 453 // is what you get. The Assembler is generating code into a CodeBuffer.
 454 
 455 class Assembler : public AbstractAssembler  {
 456   friend class AbstractAssembler; // for the non-virtual hack
 457   friend class LIR_Assembler; // as_Address()
 458   friend class StubGenerator;
 459 
 460  public:
 461   enum Condition {                     // The x86 condition codes used for conditional jumps/moves.
 462     zero          = 0x4,
 463     notZero       = 0x5,
 464     equal         = 0x4,
 465     notEqual      = 0x5,
 466     less          = 0xc,
 467     lessEqual     = 0xe,
 468     greater       = 0xf,
 469     greaterEqual  = 0xd,
 470     below         = 0x2,
 471     belowEqual    = 0x6,
 472     above         = 0x7,
 473     aboveEqual    = 0x3,
 474     overflow      = 0x0,
 475     noOverflow    = 0x1,
 476     carrySet      = 0x2,
 477     carryClear    = 0x3,
 478     negative      = 0x8,
 479     positive      = 0x9,
 480     parity        = 0xa,
 481     noParity      = 0xb
 482   };
 483 
 484   enum Prefix {
 485     // segment overrides
 486     CS_segment = 0x2e,
 487     SS_segment = 0x36,
 488     DS_segment = 0x3e,
 489     ES_segment = 0x26,
 490     FS_segment = 0x64,
 491     GS_segment = 0x65,
 492 
 493     REX        = 0x40,
 494 
 495     REX_B      = 0x41,
 496     REX_X      = 0x42,
 497     REX_XB     = 0x43,
 498     REX_R      = 0x44,
 499     REX_RB     = 0x45,
 500     REX_RX     = 0x46,
 501     REX_RXB    = 0x47,
 502 
 503     REX_W      = 0x48,
 504 
 505     REX_WB     = 0x49,
 506     REX_WX     = 0x4A,
 507     REX_WXB    = 0x4B,
 508     REX_WR     = 0x4C,
 509     REX_WRB    = 0x4D,
 510     REX_WRX    = 0x4E,
 511     REX_WRXB   = 0x4F,
 512 
 513     VEX_3bytes = 0xC4,
 514     VEX_2bytes = 0xC5,
 515     EVEX_4bytes = 0x62,
 516     Prefix_EMPTY = 0x0
 517   };
 518 
 519   enum VexPrefix {
 520     VEX_B = 0x20,
 521     VEX_X = 0x40,
 522     VEX_R = 0x80,
 523     VEX_W = 0x80
 524   };
 525 
 526   enum ExexPrefix {
 527     EVEX_F  = 0x04,
 528     EVEX_V  = 0x08,
 529     EVEX_Rb = 0x10,
 530     EVEX_X  = 0x40,
 531     EVEX_Z  = 0x80
 532   };
 533 
 534   enum VexSimdPrefix {
 535     VEX_SIMD_NONE = 0x0,
 536     VEX_SIMD_66   = 0x1,
 537     VEX_SIMD_F3   = 0x2,
 538     VEX_SIMD_F2   = 0x3
 539   };
 540 
 541   enum VexOpcode {
 542     VEX_OPCODE_NONE  = 0x0,
 543     VEX_OPCODE_0F    = 0x1,
 544     VEX_OPCODE_0F_38 = 0x2,
 545     VEX_OPCODE_0F_3A = 0x3,
 546     VEX_OPCODE_MASK  = 0x1F
 547   };
 548 
 549   enum AvxVectorLen {
 550     AVX_128bit = 0x0,
 551     AVX_256bit = 0x1,
 552     AVX_512bit = 0x2,
 553     AVX_NoVec  = 0x4
 554   };
 555 
 556   enum EvexTupleType {
 557     EVEX_FV   = 0,
 558     EVEX_HV   = 4,
 559     EVEX_FVM  = 6,
 560     EVEX_T1S  = 7,
 561     EVEX_T1F  = 11,
 562     EVEX_T2   = 13,
 563     EVEX_T4   = 15,
 564     EVEX_T8   = 17,
 565     EVEX_HVM  = 18,
 566     EVEX_QVM  = 19,
 567     EVEX_OVM  = 20,
 568     EVEX_M128 = 21,
 569     EVEX_DUP  = 22,
 570     EVEX_ETUP = 23
 571   };
 572 
 573   enum EvexInputSizeInBits {
 574     EVEX_8bit  = 0,
 575     EVEX_16bit = 1,
 576     EVEX_32bit = 2,
 577     EVEX_64bit = 3,
 578     EVEX_NObit = 4
 579   };
 580 
 581   enum WhichOperand {
 582     // input to locate_operand, and format code for relocations
 583     imm_operand  = 0,            // embedded 32-bit|64-bit immediate operand
 584     disp32_operand = 1,          // embedded 32-bit displacement or address
 585     call32_operand = 2,          // embedded 32-bit self-relative displacement
 586 #ifndef _LP64
 587     _WhichOperand_limit = 3
 588 #else
 589      narrow_oop_operand = 3,     // embedded 32-bit immediate narrow oop
 590     _WhichOperand_limit = 4
 591 #endif
 592   };
 593 
 594   // Comparison predicates for integral types & FP types when using SSE
 595   enum ComparisonPredicate {
 596     eq = 0,
 597     lt = 1,
 598     le = 2,
 599     _false = 3,
 600     neq = 4,
 601     nlt = 5,
 602     nle = 6,
 603     _true = 7
 604   };
 605 
 606   // Comparison predicates for FP types when using AVX
 607   // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
 608   // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
 609   enum ComparisonPredicateFP {
 610     EQ_OQ = 0,
 611     LT_OS = 1,
 612     LE_OS = 2,
 613     UNORD_Q = 3,
 614     NEQ_UQ = 4,
 615     NLT_US = 5,
 616     NLE_US = 6,
 617     ORD_Q = 7,
 618     EQ_UQ = 8,
 619     NGE_US = 9,
 620     NGT_US = 0xA,
 621     FALSE_OQ = 0XB,
 622     NEQ_OQ = 0xC,
 623     GE_OS = 0xD,
 624     GT_OS = 0xE,
 625     TRUE_UQ = 0xF,
 626     EQ_OS = 0x10,
 627     LT_OQ = 0x11,
 628     LE_OQ = 0x12,
 629     UNORD_S = 0x13,
 630     NEQ_US = 0x14,
 631     NLT_UQ = 0x15,
 632     NLE_UQ = 0x16,
 633     ORD_S = 0x17,
 634     EQ_US = 0x18,
 635     NGE_UQ = 0x19,
 636     NGT_UQ = 0x1A,
 637     FALSE_OS = 0x1B,
 638     NEQ_OS = 0x1C,
 639     GE_OQ = 0x1D,
 640     GT_OQ = 0x1E,
 641     TRUE_US =0x1F
 642   };
 643 
 644   enum Width {
 645     B = 0,
 646     W = 1,
 647     D = 2,
 648     Q = 3
 649   };
 650 
 651   //---<  calculate length of instruction  >---
 652   // As instruction size can't be found out easily on x86/x64,
 653   // we just use '4' for len and maxlen.
 654   // instruction must start at passed address
 655   static unsigned int instr_len(unsigned char *instr) { return 4; }
 656 
 657   //---<  longest instructions  >---
 658   // Max instruction length is not specified in architecture documentation.
 659   // We could use a "safe enough" estimate (15), but just default to
 660   // instruction length guess from above.
 661   static unsigned int instr_maxlen() { return 4; }
 662 
 663   // NOTE: The general philopsophy of the declarations here is that 64bit versions
 664   // of instructions are freely declared without the need for wrapping them an ifdef.
 665   // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
 666   // In the .cpp file the implementations are wrapped so that they are dropped out
 667   // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
 668   // to the size it was prior to merging up the 32bit and 64bit assemblers.
 669   //
 670   // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
 671   // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
 672 
 673 private:
 674 
 675   bool _legacy_mode_bw;
 676   bool _legacy_mode_dq;
 677   bool _legacy_mode_vl;
 678   bool _legacy_mode_vlbw;
 679   NOT_LP64(bool _is_managed;)
 680 
 681   class InstructionAttr *_attributes;
 682 
 683   // 64bit prefixes
 684   void prefix(Register reg);
 685   void prefix(Register dst, Register src, Prefix p);
 686   void prefix(Register dst, Address adr, Prefix p);
 687 
 688   void prefix(Address adr);
 689   void prefix(Address adr, Register reg,  bool byteinst = false);
 690   void prefix(Address adr, XMMRegister reg);
 691 
 692   int prefix_and_encode(int reg_enc, bool byteinst = false);
 693   int prefix_and_encode(int dst_enc, int src_enc) {
 694     return prefix_and_encode(dst_enc, false, src_enc, false);
 695   }
 696   int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
 697 
 698   // Some prefixq variants always emit exactly one prefix byte, so besides a
 699   // prefix-emitting method we provide a method to get the prefix byte to emit,
 700   // which can then be folded into a byte stream.
 701   int8_t get_prefixq(Address adr);
 702   int8_t get_prefixq(Address adr, Register reg);
 703 
 704   void prefixq(Address adr);
 705   void prefixq(Address adr, Register reg);
 706   void prefixq(Address adr, XMMRegister reg);
 707 
 708   int prefixq_and_encode(int reg_enc);
 709   int prefixq_and_encode(int dst_enc, int src_enc);
 710 
 711   void rex_prefix(Address adr, XMMRegister xreg,
 712                   VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 713   int  rex_prefix_and_encode(int dst_enc, int src_enc,
 714                              VexSimdPrefix pre, VexOpcode opc, bool rex_w);
 715 
 716   void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 717 
 718   void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
 719                    int nds_enc, VexSimdPrefix pre, VexOpcode opc);
 720 
 721   void vex_prefix(Address adr, int nds_enc, int xreg_enc,
 722                   VexSimdPrefix pre, VexOpcode opc,
 723                   InstructionAttr *attributes);
 724 
 725   int  vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
 726                              VexSimdPrefix pre, VexOpcode opc,
 727                              InstructionAttr *attributes);
 728 
 729   void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
 730                    VexOpcode opc, InstructionAttr *attributes);
 731 
 732   int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
 733                              VexOpcode opc, InstructionAttr *attributes);
 734 
 735   // Helper functions for groups of instructions
 736   void emit_arith_b(int op1, int op2, Register dst, int imm8);
 737 
 738   void emit_arith(int op1, int op2, Register dst, int32_t imm32);
 739   // Force generation of a 4 byte immediate value even if it fits into 8bit
 740   void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
 741   void emit_arith(int op1, int op2, Register dst, Register src);
 742 
 743   bool emit_compressed_disp_byte(int &disp);
 744 
 745   void emit_modrm(int mod, int dst_enc, int src_enc);
 746   void emit_modrm_disp8(int mod, int dst_enc, int src_enc,
 747                         int disp);
 748   void emit_modrm_sib(int mod, int dst_enc, int src_enc,
 749                       Address::ScaleFactor scale, int index_enc, int base_enc);
 750   void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
 751                             Address::ScaleFactor scale, int index_enc, int base_enc,
 752                             int disp);
 753 
 754   void emit_operand_helper(int reg_enc,
 755                            int base_enc, int index_enc, Address::ScaleFactor scale,
 756                            int disp,
 757                            RelocationHolder const& rspec,
 758                            int post_addr_length);
 759 
 760   void emit_operand(Register reg,
 761                     Register base, Register index, Address::ScaleFactor scale,
 762                     int disp,
 763                     RelocationHolder const& rspec,
 764                     int post_addr_length);
 765 
 766   void emit_operand(Register reg,
 767                     Register base, XMMRegister index, Address::ScaleFactor scale,
 768                     int disp,
 769                     RelocationHolder const& rspec,
 770                     int post_addr_length);
 771 
 772   void emit_operand(XMMRegister xreg,
 773                     Register base, XMMRegister xindex, Address::ScaleFactor scale,
 774                     int disp,
 775                     RelocationHolder const& rspec,
 776                     int post_addr_length);
 777 
 778   void emit_operand(Register reg, Address adr,
 779                     int post_addr_length);
 780 
 781   void emit_operand(XMMRegister reg,
 782                     Register base, Register index, Address::ScaleFactor scale,
 783                     int disp,
 784                     RelocationHolder const& rspec,
 785                     int post_addr_length);
 786 
 787   void emit_operand_helper(KRegister kreg,
 788                            int base_enc, int index_enc, Address::ScaleFactor scale,
 789                            int disp,
 790                            RelocationHolder const& rspec,
 791                            int post_addr_length);
 792 
 793   void emit_operand(KRegister kreg, Address adr,
 794                     int post_addr_length);
 795 
 796   void emit_operand(KRegister kreg,
 797                     Register base, Register index, Address::ScaleFactor scale,
 798                     int disp,
 799                     RelocationHolder const& rspec,
 800                     int post_addr_length);
 801 
 802   void emit_operand(XMMRegister reg, Address adr, int post_addr_length);
 803 
 804   // Immediate-to-memory forms
 805   void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
 806   void emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32);
 807 
 808  protected:
 809 #ifdef ASSERT
 810   void check_relocation(RelocationHolder const& rspec, int format);
 811 #endif
 812 
 813   void emit_data(jint data, relocInfo::relocType    rtype, int format);
 814   void emit_data(jint data, RelocationHolder const& rspec, int format);
 815   void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
 816   void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
 817 
 818   bool always_reachable(AddressLiteral adr) NOT_LP64( { return true; } );
 819   bool        reachable(AddressLiteral adr) NOT_LP64( { return true; } );
 820 
 821 
 822   // These are all easily abused and hence protected
 823 
 824   // 32BIT ONLY SECTION
 825 #ifndef _LP64
 826   // Make these disappear in 64bit mode since they would never be correct
 827   void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec);   // 32BIT ONLY
 828   void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 829 
 830   void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec);    // 32BIT ONLY
 831   void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec);     // 32BIT ONLY
 832 
 833   void push_literal32(int32_t imm32, RelocationHolder const& rspec);                 // 32BIT ONLY
 834 #else
 835   // 64BIT ONLY SECTION
 836   void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec);   // 64BIT ONLY
 837 
 838   void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
 839   void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
 840 
 841   void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
 842   void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
 843 #endif // _LP64
 844 
 845   // These are unique in that we are ensured by the caller that the 32bit
 846   // relative in these instructions will always be able to reach the potentially
 847   // 64bit address described by entry. Since they can take a 64bit address they
 848   // don't have the 32 suffix like the other instructions in this class.
 849 
 850   void call_literal(address entry, RelocationHolder const& rspec);
 851   void jmp_literal(address entry, RelocationHolder const& rspec);
 852 
 853   // Avoid using directly section
 854   // Instructions in this section are actually usable by anyone without danger
 855   // of failure but have performance issues that are addressed my enhanced
 856   // instructions which will do the proper thing base on the particular cpu.
 857   // We protect them because we don't trust you...
 858 
 859   // Don't use next inc() and dec() methods directly. INC & DEC instructions
 860   // could cause a partial flag stall since they don't set CF flag.
 861   // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
 862   // which call inc() & dec() or add() & sub() in accordance with
 863   // the product flag UseIncDec value.
 864 
 865   void decl(Register dst);
 866   void decl(Address dst);
 867   void decq(Address dst);
 868 
 869   void incl(Register dst);
 870   void incl(Address dst);
 871   void incq(Register dst);
 872   void incq(Address dst);
 873 
 874   // New cpus require use of movsd and movss to avoid partial register stall
 875   // when loading from memory. But for old Opteron use movlpd instead of movsd.
 876   // The selection is done in MacroAssembler::movdbl() and movflt().
 877 
 878   // Move Scalar Single-Precision Floating-Point Values
 879   void movss(XMMRegister dst, Address src);
 880   void movss(XMMRegister dst, XMMRegister src);
 881   void movss(Address dst, XMMRegister src);
 882 
 883   // Move Scalar Double-Precision Floating-Point Values
 884   void movsd(XMMRegister dst, Address src);
 885   void movsd(XMMRegister dst, XMMRegister src);
 886   void movsd(Address dst, XMMRegister src);
 887   void movlpd(XMMRegister dst, Address src);
 888 
 889   // New cpus require use of movaps and movapd to avoid partial register stall
 890   // when moving between registers.
 891   void movaps(XMMRegister dst, XMMRegister src);
 892   void movapd(XMMRegister dst, XMMRegister src);
 893 
 894   // End avoid using directly
 895 
 896 
 897   // Instruction prefixes
 898   void prefix(Prefix p);
 899 
 900   public:
 901 
 902   // Creation
 903   Assembler(CodeBuffer* code) : AbstractAssembler(code) {
 904     init_attributes();
 905   }
 906 
 907   // Decoding
 908   static address locate_operand(address inst, WhichOperand which);
 909   static address locate_next_instruction(address inst);
 910 
 911   // Utilities
 912   static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
 913                                          int cur_tuple_type, int in_size_in_bits, int cur_encoding);
 914 
 915   // Generic instructions
 916   // Does 32bit or 64bit as needed for the platform. In some sense these
 917   // belong in macro assembler but there is no need for both varieties to exist
 918 
 919   void init_attributes(void);
 920 
 921   void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
 922   void clear_attributes(void) { _attributes = NULL; }
 923 
 924   void set_managed(void) { NOT_LP64(_is_managed = true;) }
 925   void clear_managed(void) { NOT_LP64(_is_managed = false;) }
 926   bool is_managed(void) {
 927     NOT_LP64(return _is_managed;)
 928     LP64_ONLY(return false;) }
 929 
 930   void lea(Register dst, Address src);
 931 
 932   void mov(Register dst, Register src);
 933 
 934 #ifdef _LP64
 935   // support caching the result of some routines
 936 
 937   // must be called before pusha(), popa(), vzeroupper() - checked with asserts
 938   static void precompute_instructions();
 939 
 940   void pusha_uncached();
 941   void popa_uncached();
 942 #endif
 943   void vzeroupper_uncached();
 944   void decq(Register dst);
 945 
 946   void pusha();
 947   void popa();
 948 
 949   void pushf();
 950   void popf();
 951 
 952   void push(int32_t imm32);
 953 
 954   void push(Register src);
 955 
 956   void pop(Register dst);
 957 
 958   // These do register sized moves/scans
 959   void rep_mov();
 960   void rep_stos();
 961   void rep_stosb();
 962   void repne_scan();
 963 #ifdef _LP64
 964   void repne_scanl();
 965 #endif
 966 
 967   // Vanilla instructions in lexical order
 968 
 969   void adcl(Address dst, int32_t imm32);
 970   void adcl(Address dst, Register src);
 971   void adcl(Register dst, int32_t imm32);
 972   void adcl(Register dst, Address src);
 973   void adcl(Register dst, Register src);
 974 
 975   void adcq(Register dst, int32_t imm32);
 976   void adcq(Register dst, Address src);
 977   void adcq(Register dst, Register src);
 978 
 979   void addb(Address dst, int imm8);
 980   void addw(Register dst, Register src);
 981   void addw(Address dst, int imm16);
 982 
 983   void addl(Address dst, int32_t imm32);
 984   void addl(Address dst, Register src);
 985   void addl(Register dst, int32_t imm32);
 986   void addl(Register dst, Address src);
 987   void addl(Register dst, Register src);
 988 
 989   void addq(Address dst, int32_t imm32);
 990   void addq(Address dst, Register src);
 991   void addq(Register dst, int32_t imm32);
 992   void addq(Register dst, Address src);
 993   void addq(Register dst, Register src);
 994 
 995 #ifdef _LP64
 996  //Add Unsigned Integers with Carry Flag
 997   void adcxq(Register dst, Register src);
 998 
 999  //Add Unsigned Integers with Overflow Flag
1000   void adoxq(Register dst, Register src);
1001 #endif
1002 
1003   void addr_nop_4();
1004   void addr_nop_5();
1005   void addr_nop_7();
1006   void addr_nop_8();
1007 
1008   // Add Scalar Double-Precision Floating-Point Values
1009   void addsd(XMMRegister dst, Address src);
1010   void addsd(XMMRegister dst, XMMRegister src);
1011 
1012   // Add Scalar Single-Precision Floating-Point Values
1013   void addss(XMMRegister dst, Address src);
1014   void addss(XMMRegister dst, XMMRegister src);
1015 
1016   // AES instructions
1017   void aesdec(XMMRegister dst, Address src);
1018   void aesdec(XMMRegister dst, XMMRegister src);
1019   void aesdeclast(XMMRegister dst, Address src);
1020   void aesdeclast(XMMRegister dst, XMMRegister src);
1021   void aesenc(XMMRegister dst, Address src);
1022   void aesenc(XMMRegister dst, XMMRegister src);
1023   void aesenclast(XMMRegister dst, Address src);
1024   void aesenclast(XMMRegister dst, XMMRegister src);
1025   // Vector AES instructions
1026   void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1027   void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1028   void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1029   void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1030 
1031   void andw(Register dst, Register src);
1032   void andb(Address dst, Register src);
1033 
1034   void andl(Address  dst, int32_t imm32);
1035   void andl(Register dst, int32_t imm32);
1036   void andl(Register dst, Address src);
1037   void andl(Register dst, Register src);
1038   void andl(Address dst, Register src);
1039 
1040   void andq(Address  dst, int32_t imm32);
1041   void andq(Register dst, int32_t imm32);
1042   void andq(Register dst, Address src);
1043   void andq(Register dst, Register src);
1044   void andq(Address dst, Register src);
1045 
1046   // BMI instructions
1047   void andnl(Register dst, Register src1, Register src2);
1048   void andnl(Register dst, Register src1, Address src2);
1049   void andnq(Register dst, Register src1, Register src2);
1050   void andnq(Register dst, Register src1, Address src2);
1051 
1052   void blsil(Register dst, Register src);
1053   void blsil(Register dst, Address src);
1054   void blsiq(Register dst, Register src);
1055   void blsiq(Register dst, Address src);
1056 
1057   void blsmskl(Register dst, Register src);
1058   void blsmskl(Register dst, Address src);
1059   void blsmskq(Register dst, Register src);
1060   void blsmskq(Register dst, Address src);
1061 
1062   void blsrl(Register dst, Register src);
1063   void blsrl(Register dst, Address src);
1064   void blsrq(Register dst, Register src);
1065   void blsrq(Register dst, Address src);
1066 
1067   void bsfl(Register dst, Register src);
1068   void bsrl(Register dst, Register src);
1069 
1070 #ifdef _LP64
1071   void bsfq(Register dst, Register src);
1072   void bsrq(Register dst, Register src);
1073 #endif
1074 
1075   void bswapl(Register reg);
1076 
1077   void bswapq(Register reg);
1078 
1079   void call(Label& L, relocInfo::relocType rtype);
1080   void call(Register reg);  // push pc; pc <- reg
1081   void call(Address adr);   // push pc; pc <- adr
1082 
1083   void cdql();
1084 
1085   void cdqq();
1086 
1087   void cld();
1088 
1089   void clflush(Address adr);
1090   void clflushopt(Address adr);
1091   void clwb(Address adr);
1092 
1093   void cmovl(Condition cc, Register dst, Register src);
1094   void cmovl(Condition cc, Register dst, Address src);
1095 
1096   void cmovq(Condition cc, Register dst, Register src);
1097   void cmovq(Condition cc, Register dst, Address src);
1098 
1099 
1100   void cmpb(Address dst, int imm8);
1101 
1102   void cmpl(Address dst, int32_t imm32);
1103   void cmpl(Register dst, int32_t imm32);
1104   void cmpl(Register dst, Register src);
1105   void cmpl(Register dst, Address src);
1106   void cmpl_imm32(Address dst, int32_t imm32);
1107 
1108   void cmpq(Address dst, int32_t imm32);
1109   void cmpq(Address dst, Register src);
1110   void cmpq(Register dst, int32_t imm32);
1111   void cmpq(Register dst, Register src);
1112   void cmpq(Register dst, Address src);
1113 
1114   void cmpw(Address dst, int imm16);
1115 
1116   void cmpxchg8 (Address adr);
1117 
1118   void cmpxchgb(Register reg, Address adr);
1119   void cmpxchgl(Register reg, Address adr);
1120 
1121   void cmpxchgq(Register reg, Address adr);
1122   void cmpxchgw(Register reg, Address adr);
1123 
1124   // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1125   void comisd(XMMRegister dst, Address src);
1126   void comisd(XMMRegister dst, XMMRegister src);
1127 
1128   // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1129   void comiss(XMMRegister dst, Address src);
1130   void comiss(XMMRegister dst, XMMRegister src);
1131 
1132   // Identify processor type and features
1133   void cpuid();
1134 
1135   // CRC32C
1136   void crc32(Register crc, Register v, int8_t sizeInBytes);
1137   void crc32(Register crc, Address adr, int8_t sizeInBytes);
1138 
1139   // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1140   void cvtsd2ss(XMMRegister dst, XMMRegister src);
1141   void cvtsd2ss(XMMRegister dst, Address src);
1142 
1143   // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1144   void cvtsi2sdl(XMMRegister dst, Register src);
1145   void cvtsi2sdl(XMMRegister dst, Address src);
1146   void cvtsi2sdq(XMMRegister dst, Register src);
1147   void cvtsi2sdq(XMMRegister dst, Address src);
1148 
1149   // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1150   void cvtsi2ssl(XMMRegister dst, Register src);
1151   void cvtsi2ssl(XMMRegister dst, Address src);
1152   void cvtsi2ssq(XMMRegister dst, Register src);
1153   void cvtsi2ssq(XMMRegister dst, Address src);
1154 
1155   // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1156   void cvtdq2pd(XMMRegister dst, XMMRegister src);
1157   void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1158 
1159   // Convert Halffloat to Single Precision Floating-Point value
1160   void vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1161   void vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len);
1162   void evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len);
1163 
1164   // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1165   void cvtdq2ps(XMMRegister dst, XMMRegister src);
1166   void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1167 
1168   // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1169   void cvtss2sd(XMMRegister dst, XMMRegister src);
1170   void cvtss2sd(XMMRegister dst, Address src);
1171 
1172   // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1173   void cvtsd2siq(Register dst, XMMRegister src);
1174   void cvttsd2sil(Register dst, Address src);
1175   void cvttsd2sil(Register dst, XMMRegister src);
1176   void cvttsd2siq(Register dst, Address src);
1177   void cvttsd2siq(Register dst, XMMRegister src);
1178 
1179   // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1180   void cvttss2sil(Register dst, XMMRegister src);
1181   void cvttss2siq(Register dst, XMMRegister src);
1182   void cvtss2sil(Register dst, XMMRegister src);
1183 
1184   // Convert vector double to int
1185   void cvttpd2dq(XMMRegister dst, XMMRegister src);
1186 
1187   // Convert vector float and double
1188   void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1189   void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1190 
1191   // Convert vector float to int/long
1192   void vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1193   void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1194   void evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len);
1195 
1196   // Convert vector long to vector FP
1197   void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1198   void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1199 
1200   // Convert vector double to long
1201   void evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1202   void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1203 
1204   // Convert vector double to int
1205   void vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len);
1206 
1207   // Evex casts with truncation
1208   void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
1209   void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
1210   void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
1211   void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
1212   void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
1213   void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);
1214 
1215   // Evex casts with signed saturation
1216   void evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len);
1217 
1218   //Abs of packed Integer values
1219   void pabsb(XMMRegister dst, XMMRegister src);
1220   void pabsw(XMMRegister dst, XMMRegister src);
1221   void pabsd(XMMRegister dst, XMMRegister src);
1222   void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1223   void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1224   void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1225   void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1226 
1227   // Divide Scalar Double-Precision Floating-Point Values
1228   void divsd(XMMRegister dst, Address src);
1229   void divsd(XMMRegister dst, XMMRegister src);
1230 
1231   // Divide Scalar Single-Precision Floating-Point Values
1232   void divss(XMMRegister dst, Address src);
1233   void divss(XMMRegister dst, XMMRegister src);
1234 
1235 
1236 #ifndef _LP64
1237  private:
1238 
1239   void emit_farith(int b1, int b2, int i);
1240 
1241  public:
1242   void emms();
1243 
1244   void fabs();
1245 
1246   void fadd(int i);
1247 
1248   void fadd_d(Address src);
1249   void fadd_s(Address src);
1250 
1251   // "Alternate" versions of x87 instructions place result down in FPU
1252   // stack instead of on TOS
1253 
1254   void fadda(int i); // "alternate" fadd
1255   void faddp(int i = 1);
1256 
1257   void fchs();
1258 
1259   void fcom(int i);
1260 
1261   void fcomp(int i = 1);
1262   void fcomp_d(Address src);
1263   void fcomp_s(Address src);
1264 
1265   void fcompp();
1266 
1267   void fcos();
1268 
1269   void fdecstp();
1270 
1271   void fdiv(int i);
1272   void fdiv_d(Address src);
1273   void fdivr_s(Address src);
1274   void fdiva(int i);  // "alternate" fdiv
1275   void fdivp(int i = 1);
1276 
1277   void fdivr(int i);
1278   void fdivr_d(Address src);
1279   void fdiv_s(Address src);
1280 
1281   void fdivra(int i); // "alternate" reversed fdiv
1282 
1283   void fdivrp(int i = 1);
1284 
1285   void ffree(int i = 0);
1286 
1287   void fild_d(Address adr);
1288   void fild_s(Address adr);
1289 
1290   void fincstp();
1291 
1292   void finit();
1293 
1294   void fist_s (Address adr);
1295   void fistp_d(Address adr);
1296   void fistp_s(Address adr);
1297 
1298   void fld1();
1299 
1300   void fld_d(Address adr);
1301   void fld_s(Address adr);
1302   void fld_s(int index);
1303 
1304   void fldcw(Address src);
1305 
1306   void fldenv(Address src);
1307 
1308   void fldlg2();
1309 
1310   void fldln2();
1311 
1312   void fldz();
1313 
1314   void flog();
1315   void flog10();
1316 
1317   void fmul(int i);
1318 
1319   void fmul_d(Address src);
1320   void fmul_s(Address src);
1321 
1322   void fmula(int i);  // "alternate" fmul
1323 
1324   void fmulp(int i = 1);
1325 
1326   void fnsave(Address dst);
1327 
1328   void fnstcw(Address src);
1329 
1330   void fnstsw_ax();
1331 
1332   void fprem();
1333   void fprem1();
1334 
1335   void frstor(Address src);
1336 
1337   void fsin();
1338 
1339   void fsqrt();
1340 
1341   void fst_d(Address adr);
1342   void fst_s(Address adr);
1343 
1344   void fstp_d(Address adr);
1345   void fstp_d(int index);
1346   void fstp_s(Address adr);
1347 
1348   void fsub(int i);
1349   void fsub_d(Address src);
1350   void fsub_s(Address src);
1351 
1352   void fsuba(int i);  // "alternate" fsub
1353 
1354   void fsubp(int i = 1);
1355 
1356   void fsubr(int i);
1357   void fsubr_d(Address src);
1358   void fsubr_s(Address src);
1359 
1360   void fsubra(int i); // "alternate" reversed fsub
1361 
1362   void fsubrp(int i = 1);
1363 
1364   void ftan();
1365 
1366   void ftst();
1367 
1368   void fucomi(int i = 1);
1369   void fucomip(int i = 1);
1370 
1371   void fwait();
1372 
1373   void fxch(int i = 1);
1374 
1375   void fyl2x();
1376   void frndint();
1377   void f2xm1();
1378   void fldl2e();
1379 #endif // !_LP64
1380 
1381   // operands that only take the original 32bit registers
1382   void emit_operand32(Register reg, Address adr, int post_addr_length);
1383 
1384   void fld_x(Address adr);  // extended-precision (80-bit) format
1385   void fstp_x(Address adr); // extended-precision (80-bit) format
1386   void fxrstor(Address src);
1387   void xrstor(Address src);
1388 
1389   void fxsave(Address dst);
1390   void xsave(Address dst);
1391 
1392   void hlt();
1393 
1394   void idivl(Register src);
1395   void divl(Register src); // Unsigned division
1396 
1397 #ifdef _LP64
1398   void idivq(Register src);
1399   void divq(Register src); // Unsigned division
1400 #endif
1401 
1402   void imull(Register src);
1403   void imull(Register dst, Register src);
1404   void imull(Register dst, Register src, int value);
1405   void imull(Register dst, Address src, int value);
1406   void imull(Register dst, Address src);
1407 
1408 #ifdef _LP64
1409   void imulq(Register dst, Register src);
1410   void imulq(Register dst, Register src, int value);
1411   void imulq(Register dst, Address src, int value);
1412   void imulq(Register dst, Address src);
1413   void imulq(Register dst);
1414 #endif
1415 
1416   // jcc is the generic conditional branch generator to run-
1417   // time routines, jcc is used for branches to labels. jcc
1418   // takes a branch opcode (cc) and a label (L) and generates
1419   // either a backward branch or a forward branch and links it
1420   // to the label fixup chain. Usage:
1421   //
1422   // Label L;      // unbound label
1423   // jcc(cc, L);   // forward branch to unbound label
1424   // bind(L);      // bind label to the current pc
1425   // jcc(cc, L);   // backward branch to bound label
1426   // bind(L);      // illegal: a label may be bound only once
1427   //
1428   // Note: The same Label can be used for forward and backward branches
1429   // but it may be bound only once.
1430 
1431   void jcc(Condition cc, Label& L, bool maybe_short = true);
1432 
1433   // Conditional jump to a 8-bit offset to L.
1434   // WARNING: be very careful using this for forward jumps.  If the label is
1435   // not bound within an 8-bit offset of this instruction, a run-time error
1436   // will occur.
1437 
1438   // Use macro to record file and line number.
1439   #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1440 
1441   void jccb_0(Condition cc, Label& L, const char* file, int line);
1442 
1443   void jmp(Address entry);    // pc <- entry
1444 
1445   // Label operations & relative jumps (PPUM Appendix D)
1446   void jmp(Label& L, bool maybe_short = true);   // unconditional jump to L
1447 
1448   void jmp(Register entry); // pc <- entry
1449 
1450   // Unconditional 8-bit offset jump to L.
1451   // WARNING: be very careful using this for forward jumps.  If the label is
1452   // not bound within an 8-bit offset of this instruction, a run-time error
1453   // will occur.
1454 
1455   // Use macro to record file and line number.
1456   #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1457 
1458   void jmpb_0(Label& L, const char* file, int line);
1459 
1460   void ldmxcsr( Address src );
1461 
1462   void leal(Register dst, Address src);
1463 
1464   void leaq(Register dst, Address src);
1465 
1466   void lfence();
1467 
1468   void lock();
1469   void size_prefix();
1470 
1471   void lzcntl(Register dst, Register src);
1472   void lzcntl(Register dst, Address src);
1473 
1474 #ifdef _LP64
1475   void lzcntq(Register dst, Register src);
1476   void lzcntq(Register dst, Address src);
1477 #endif
1478 
1479   enum Membar_mask_bits {
1480     StoreStore = 1 << 3,
1481     LoadStore  = 1 << 2,
1482     StoreLoad  = 1 << 1,
1483     LoadLoad   = 1 << 0
1484   };
1485 
1486   // Serializes memory and blows flags
1487   void membar(Membar_mask_bits order_constraint);
1488 
1489   void mfence();
1490   void sfence();
1491 
1492   // Moves
1493 
1494   void mov64(Register dst, int64_t imm64);
1495   void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1496 
1497   void movb(Address dst, Register src);
1498   void movb(Address dst, int imm8);
1499   void movb(Register dst, Address src);
1500 
1501   void movddup(XMMRegister dst, XMMRegister src);
1502   void movddup(XMMRegister dst, Address src);
1503   void vmovddup(XMMRegister dst, Address src, int vector_len);
1504 
1505   void kandbl(KRegister dst, KRegister src1, KRegister src2);
1506   void kandwl(KRegister dst, KRegister src1, KRegister src2);
1507   void kanddl(KRegister dst, KRegister src1, KRegister src2);
1508   void kandql(KRegister dst, KRegister src1, KRegister src2);
1509 
1510   void korbl(KRegister dst, KRegister src1, KRegister src2);
1511   void korwl(KRegister dst, KRegister src1, KRegister src2);
1512   void kordl(KRegister dst, KRegister src1, KRegister src2);
1513   void korql(KRegister dst, KRegister src1, KRegister src2);
1514 
1515   void kxorbl(KRegister dst, KRegister src1, KRegister src2);
1516   void kxorwl(KRegister dst, KRegister src1, KRegister src2);
1517   void kxordl(KRegister dst, KRegister src1, KRegister src2);
1518   void kxorql(KRegister dst, KRegister src1, KRegister src2);
1519   void kmovbl(KRegister dst, Register src);
1520   void kmovbl(Register dst, KRegister src);
1521   void kmovbl(KRegister dst, KRegister src);
1522   void kmovwl(KRegister dst, Register src);
1523   void kmovwl(KRegister dst, Address src);
1524   void kmovwl(Register dst, KRegister src);
1525   void kmovwl(Address dst, KRegister src);
1526   void kmovwl(KRegister dst, KRegister src);
1527   void kmovdl(KRegister dst, Register src);
1528   void kmovdl(Register dst, KRegister src);
1529   void kmovql(KRegister dst, KRegister src);
1530   void kmovql(Address dst, KRegister src);
1531   void kmovql(KRegister dst, Address src);
1532   void kmovql(KRegister dst, Register src);
1533   void kmovql(Register dst, KRegister src);
1534 
1535   void knotbl(KRegister dst, KRegister src);
1536   void knotwl(KRegister dst, KRegister src);
1537   void knotdl(KRegister dst, KRegister src);
1538   void knotql(KRegister dst, KRegister src);
1539 
1540   void kortestbl(KRegister dst, KRegister src);
1541   void kortestwl(KRegister dst, KRegister src);
1542   void kortestdl(KRegister dst, KRegister src);
1543   void kortestql(KRegister dst, KRegister src);
1544 
1545   void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
1546   void kshiftlbl(KRegister dst, KRegister src, int imm8);
1547   void kshiftlql(KRegister dst, KRegister src, int imm8);
1548   void kshiftrbl(KRegister dst, KRegister src, int imm8);
1549   void kshiftrwl(KRegister dst, KRegister src, int imm8);
1550   void kshiftrdl(KRegister dst, KRegister src, int imm8);
1551   void kshiftrql(KRegister dst, KRegister src, int imm8);
1552   void ktestq(KRegister src1, KRegister src2);
1553   void ktestd(KRegister src1, KRegister src2);
1554   void kunpckdql(KRegister dst, KRegister src1, KRegister src2);
1555 
1556 
1557   void ktestql(KRegister dst, KRegister src);
1558   void ktestdl(KRegister dst, KRegister src);
1559   void ktestwl(KRegister dst, KRegister src);
1560   void ktestbl(KRegister dst, KRegister src);
1561 
1562   void movdl(XMMRegister dst, Register src);
1563   void movdl(Register dst, XMMRegister src);
1564   void movdl(XMMRegister dst, Address src);
1565   void movdl(Address dst, XMMRegister src);
1566 
1567   // Move Double Quadword
1568   void movdq(XMMRegister dst, Register src);
1569   void movdq(Register dst, XMMRegister src);
1570 
1571   // Move Aligned Double Quadword
1572   void movdqa(XMMRegister dst, XMMRegister src);
1573   void movdqa(XMMRegister dst, Address src);
1574 
1575   // Move Unaligned Double Quadword
1576   void movdqu(Address     dst, XMMRegister src);
1577   void movdqu(XMMRegister dst, Address src);
1578   void movdqu(XMMRegister dst, XMMRegister src);
1579 
1580   // Move Unaligned 256bit Vector
1581   void vmovdqu(Address dst, XMMRegister src);
1582   void vmovdqu(XMMRegister dst, Address src);
1583   void vmovdqu(XMMRegister dst, XMMRegister src);
1584 
1585    // Move Unaligned 512bit Vector
1586   void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1587   void evmovdqub(XMMRegister dst, Address src, int vector_len);
1588   void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1589   void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1590   void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1591 
1592   void evmovdquw(XMMRegister dst, Address src, int vector_len);
1593   void evmovdquw(Address dst, XMMRegister src, int vector_len);
1594   void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1595   void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1596   void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1597 
1598   void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1599   void evmovdqul(XMMRegister dst, Address src, int vector_len);
1600   void evmovdqul(Address dst, XMMRegister src, int vector_len);
1601 
1602   void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1603   void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1604   void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1605 
1606   void evmovdquq(Address dst, XMMRegister src, int vector_len);
1607   void evmovdquq(XMMRegister dst, Address src, int vector_len);
1608   void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1609 
1610   void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1611   void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1612   void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1613 
1614   // Move lower 64bit to high 64bit in 128bit register
1615   void movlhps(XMMRegister dst, XMMRegister src);
1616 
1617   void movl(Register dst, int32_t imm32);
1618   void movl(Address dst, int32_t imm32);
1619   void movl(Register dst, Register src);
1620   void movl(Register dst, Address src);
1621   void movl(Address dst, Register src);
1622 
1623 #ifdef _LP64
1624   void movq(Register dst, Register src);
1625   void movq(Register dst, Address src);
1626   void movq(Address  dst, Register src);
1627   void movq(Address  dst, int32_t imm32);
1628   void movq(Register  dst, int32_t imm32);
1629 #endif
1630 
1631   // Move Quadword
1632   void movq(Address     dst, XMMRegister src);
1633   void movq(XMMRegister dst, Address src);
1634   void movq(XMMRegister dst, XMMRegister src);
1635   void movq(Register dst, XMMRegister src);
1636   void movq(XMMRegister dst, Register src);
1637 
1638   void movsbl(Register dst, Address src);
1639   void movsbl(Register dst, Register src);
1640 
1641 #ifdef _LP64
1642   void movsbq(Register dst, Address src);
1643   void movsbq(Register dst, Register src);
1644 
1645   // Move signed 32bit immediate to 64bit extending sign
1646   void movslq(Address  dst, int32_t imm64);
1647   void movslq(Register dst, int32_t imm64);
1648 
1649   void movslq(Register dst, Address src);
1650   void movslq(Register dst, Register src);
1651 #endif
1652 
1653   void movswl(Register dst, Address src);
1654   void movswl(Register dst, Register src);
1655 
1656 #ifdef _LP64
1657   void movswq(Register dst, Address src);
1658   void movswq(Register dst, Register src);
1659 #endif
1660 
1661   void movups(XMMRegister dst, Address src);
1662   void vmovups(XMMRegister dst, Address src, int vector_len);
1663   void movups(Address dst, XMMRegister src);
1664   void vmovups(Address dst, XMMRegister src, int vector_len);
1665 
1666   void movw(Address dst, int imm16);
1667   void movw(Register dst, Address src);
1668   void movw(Address dst, Register src);
1669 
1670   void movzbl(Register dst, Address src);
1671   void movzbl(Register dst, Register src);
1672 
1673 #ifdef _LP64
1674   void movzbq(Register dst, Address src);
1675   void movzbq(Register dst, Register src);
1676 #endif
1677 
1678   void movzwl(Register dst, Address src);
1679   void movzwl(Register dst, Register src);
1680 
1681 #ifdef _LP64
1682   void movzwq(Register dst, Address src);
1683   void movzwq(Register dst, Register src);
1684 #endif
1685 
1686   // Unsigned multiply with RAX destination register
1687   void mull(Address src);
1688   void mull(Register src);
1689 
1690 #ifdef _LP64
1691   void mulq(Address src);
1692   void mulq(Register src);
1693   void mulxq(Register dst1, Register dst2, Register src);
1694 #endif
1695 
1696   // Multiply Scalar Double-Precision Floating-Point Values
1697   void mulsd(XMMRegister dst, Address src);
1698   void mulsd(XMMRegister dst, XMMRegister src);
1699 
1700   // Multiply Scalar Single-Precision Floating-Point Values
1701   void mulss(XMMRegister dst, Address src);
1702   void mulss(XMMRegister dst, XMMRegister src);
1703 
1704   void negl(Register dst);
1705   void negl(Address dst);
1706 
1707 #ifdef _LP64
1708   void negq(Register dst);
1709   void negq(Address dst);
1710 #endif
1711 
1712   void nop(int i = 1);
1713 
1714   void notl(Register dst);
1715 
1716 #ifdef _LP64
1717   void notq(Register dst);
1718 
1719   void btsq(Address dst, int imm8);
1720   void btrq(Address dst, int imm8);
1721 #endif
1722 
1723   void orw(Register dst, Register src);
1724 
1725   void orl(Address dst, int32_t imm32);
1726   void orl(Register dst, int32_t imm32);
1727   void orl(Register dst, Address src);
1728   void orl(Register dst, Register src);
1729   void orl(Address dst, Register src);
1730 
1731   void orb(Address dst, int imm8);
1732   void orb(Address dst, Register src);
1733 
1734   void orq(Address dst, int32_t imm32);
1735   void orq(Address dst, Register src);
1736   void orq(Register dst, int32_t imm32);
1737   void orq(Register dst, Address src);
1738   void orq(Register dst, Register src);
1739 
1740   // Pack with signed saturation
1741   void packsswb(XMMRegister dst, XMMRegister src);
1742   void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1743   void packssdw(XMMRegister dst, XMMRegister src);
1744   void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1745 
1746   // Pack with unsigned saturation
1747   void packuswb(XMMRegister dst, XMMRegister src);
1748   void packuswb(XMMRegister dst, Address src);
1749   void packusdw(XMMRegister dst, XMMRegister src);
1750   void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1751   void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1752 
1753   // Permutations
1754   void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1755   void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1756   void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1757   void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1758   void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1759   void vpermw(XMMRegister dst,  XMMRegister nds, XMMRegister src, int vector_len);
1760   void vpermd(XMMRegister dst,  XMMRegister nds, Address src, int vector_len);
1761   void vpermd(XMMRegister dst,  XMMRegister nds, XMMRegister src, int vector_len);
1762   void vperm2i128(XMMRegister dst,  XMMRegister nds, XMMRegister src, int imm8);
1763   void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1764   void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1765   void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1766   void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1767   void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1768   void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1769   void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len);
1770 
1771   void pause();
1772 
1773   // Undefined Instruction
1774   void ud2();
1775 
1776   // SSE4.2 string instructions
1777   void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1778   void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1779 
1780   void pcmpeqb(XMMRegister dst, XMMRegister src);
1781   void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1782 
1783   void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1784   void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1785   void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1786   void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1787 
1788   void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1789   void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1790   void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1791 
1792   void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1793   void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1794 
1795   void pcmpeqw(XMMRegister dst, XMMRegister src);
1796   void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1797   void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1798   void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1799 
1800   void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1801 
1802   void pcmpeqd(XMMRegister dst, XMMRegister src);
1803   void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1804   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1805   void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1806 
1807   void pcmpeqq(XMMRegister dst, XMMRegister src);
1808   void evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1809   void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1810   void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1811   void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1812   void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1813 
1814   void pcmpgtq(XMMRegister dst, XMMRegister src);
1815   void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1816 
1817   void pmovmskb(Register dst, XMMRegister src);
1818   void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
1819   void vmovmskps(Register dst, XMMRegister src, int vec_enc);
1820   void vmovmskpd(Register dst, XMMRegister src, int vec_enc);
1821   void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1822   void vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len);
1823 
1824 
1825   void vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1826   void vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1827   void vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1828   void vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1829 
1830   // SSE 4.1 extract
1831   void pextrd(Register dst, XMMRegister src, int imm8);
1832   void pextrq(Register dst, XMMRegister src, int imm8);
1833   void pextrd(Address dst, XMMRegister src, int imm8);
1834   void pextrq(Address dst, XMMRegister src, int imm8);
1835   void pextrb(Register dst, XMMRegister src, int imm8);
1836   void pextrb(Address dst, XMMRegister src, int imm8);
1837   // SSE 2 extract
1838   void pextrw(Register dst, XMMRegister src, int imm8);
1839   void pextrw(Address dst, XMMRegister src, int imm8);
1840 
1841   // SSE 4.1 insert
1842   void pinsrd(XMMRegister dst, Register src, int imm8);
1843   void pinsrq(XMMRegister dst, Register src, int imm8);
1844   void pinsrb(XMMRegister dst, Register src, int imm8);
1845   void pinsrd(XMMRegister dst, Address src, int imm8);
1846   void pinsrq(XMMRegister dst, Address src, int imm8);
1847   void pinsrb(XMMRegister dst, Address src, int imm8);
1848   void insertps(XMMRegister dst, XMMRegister src, int imm8);
1849   // SSE 2 insert
1850   void pinsrw(XMMRegister dst, Register src, int imm8);
1851   void pinsrw(XMMRegister dst, Address src, int imm8);
1852 
1853   // AVX insert
1854   void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1855   void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1856   void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1857   void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1858   void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1859 
1860   // Zero extend moves
1861   void pmovzxbw(XMMRegister dst, XMMRegister src);
1862   void pmovzxbw(XMMRegister dst, Address src);
1863   void pmovzxbd(XMMRegister dst, XMMRegister src);
1864   void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1865   void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1866   void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
1867   void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
1868   void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1869   void vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len);
1870   void pmovzxdq(XMMRegister dst, XMMRegister src);
1871   void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
1872   void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1873 
1874   // Sign extend moves
1875   void pmovsxbd(XMMRegister dst, XMMRegister src);
1876   void pmovsxbq(XMMRegister dst, XMMRegister src);
1877   void pmovsxbw(XMMRegister dst, XMMRegister src);
1878   void pmovsxwd(XMMRegister dst, XMMRegister src);
1879   void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
1880   void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
1881   void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1882   void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
1883   void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
1884   void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);
1885 
1886   void evpmovwb(Address dst, XMMRegister src, int vector_len);
1887   void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1888   void evpmovdb(Address dst, XMMRegister src, int vector_len);
1889 
1890   // Multiply add
1891   void pmaddwd(XMMRegister dst, XMMRegister src);
1892   void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1893   void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1894 
1895   // Multiply add accumulate
1896   void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1897 
1898 #ifndef _LP64 // no 32bit push/pop on amd64
1899   void popl(Address dst);
1900 #endif
1901 
1902 #ifdef _LP64
1903   void popq(Address dst);
1904   void popq(Register dst);
1905 #endif
1906 
1907   void popcntl(Register dst, Address src);
1908   void popcntl(Register dst, Register src);
1909 
1910   void evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1911   void evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1912   void evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1913   void evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1914 
1915 #ifdef _LP64
1916   void popcntq(Register dst, Address src);
1917   void popcntq(Register dst, Register src);
1918 #endif
1919 
1920   // Prefetches (SSE, SSE2, 3DNOW only)
1921 
1922   void prefetchnta(Address src);
1923   void prefetchr(Address src);
1924   void prefetcht0(Address src);
1925   void prefetcht1(Address src);
1926   void prefetcht2(Address src);
1927   void prefetchw(Address src);
1928 
1929   // Shuffle Bytes
1930   void pshufb(XMMRegister dst, XMMRegister src);
1931   void pshufb(XMMRegister dst, Address src);
1932   void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1933   void evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1934 
1935 
1936   // Shuffle Packed Doublewords
1937   void pshufd(XMMRegister dst, XMMRegister src, int mode);
1938   void pshufd(XMMRegister dst, Address src,     int mode);
1939   void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1940 
1941   // Shuffle Packed High/Low Words
1942   void pshufhw(XMMRegister dst, XMMRegister src, int mode);
1943   void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1944   void pshuflw(XMMRegister dst, Address src,     int mode);
1945 
1946   //shuffle floats and doubles
1947   void shufps(XMMRegister, XMMRegister, int);
1948   void shufpd(XMMRegister, XMMRegister, int);
1949   void vshufps(XMMRegister, XMMRegister, XMMRegister, int, int);
1950   void vshufpd(XMMRegister, XMMRegister, XMMRegister, int, int);
1951 
1952   // Shuffle packed values at 128 bit granularity
1953   void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1954 
1955   // Shift Right by bytes Logical DoubleQuadword Immediate
1956   void psrldq(XMMRegister dst, int shift);
1957   // Shift Left by bytes Logical DoubleQuadword Immediate
1958   void pslldq(XMMRegister dst, int shift);
1959 
1960   // Logical Compare 128bit
1961   void ptest(XMMRegister dst, XMMRegister src);
1962   void ptest(XMMRegister dst, Address src);
1963   // Logical Compare 256bit
1964   void vptest(XMMRegister dst, XMMRegister src);
1965   void vptest(XMMRegister dst, Address src);
1966 
1967   void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1968 
1969   // Vector compare
1970   void vptest(XMMRegister dst, XMMRegister src, int vector_len);
1971 
1972   // Interleave Low Bytes
1973   void punpcklbw(XMMRegister dst, XMMRegister src);
1974   void punpcklbw(XMMRegister dst, Address src);
1975 
1976   // Interleave Low Doublewords
1977   void punpckldq(XMMRegister dst, XMMRegister src);
1978   void punpckldq(XMMRegister dst, Address src);
1979   void vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1980 
1981   // Interleave High Word
1982   void vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1983 
1984   // Interleave Low Word
1985   void vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1986 
1987   // Interleave High Doublewords
1988   void vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1989 
1990   // Interleave Low Quadwords
1991   void punpcklqdq(XMMRegister dst, XMMRegister src);
1992 
1993   // Vector sum of absolute difference.
1994   void vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1995 
1996 #ifndef _LP64 // no 32bit push/pop on amd64
1997   void pushl(Address src);
1998 #endif
1999 
2000   void pushq(Address src);
2001 
2002   void rcll(Register dst, int imm8);
2003 
2004   void rclq(Register dst, int imm8);
2005 
2006   void rcrq(Register dst, int imm8);
2007 
2008   void rcpps(XMMRegister dst, XMMRegister src);
2009 
2010   void rcpss(XMMRegister dst, XMMRegister src);
2011 
2012   void rdtsc();
2013   void rdtscp();
2014 
2015   void ret(int imm16);
2016 
2017   void roll(Register dst);
2018 
2019   void roll(Register dst, int imm8);
2020 
2021   void rorl(Register dst);
2022 
2023   void rorl(Register dst, int imm8);
2024 
2025 #ifdef _LP64
2026   void rolq(Register dst);
2027   void rolq(Register dst, int imm8);
2028   void rorq(Register dst);
2029   void rorq(Register dst, int imm8);
2030   void rorxl(Register dst, Register src, int imm8);
2031   void rorxl(Register dst, Address src, int imm8);
2032   void rorxq(Register dst, Register src, int imm8);
2033   void rorxq(Register dst, Address src, int imm8);
2034 #endif
2035 
2036   void sahf();
2037 
2038   void sall(Register dst, int imm8);
2039   void sall(Register dst);
2040   void sall(Address dst, int imm8);
2041   void sall(Address dst);
2042 
2043   void sarl(Address dst, int imm8);
2044   void sarl(Address dst);
2045   void sarl(Register dst, int imm8);
2046   void sarl(Register dst);
2047 
2048 #ifdef _LP64
2049   void salq(Register dst, int imm8);
2050   void salq(Register dst);
2051   void salq(Address dst, int imm8);
2052   void salq(Address dst);
2053 
2054   void sarq(Address dst, int imm8);
2055   void sarq(Address dst);
2056   void sarq(Register dst, int imm8);
2057   void sarq(Register dst);
2058 #endif
2059 
2060   void sbbl(Address dst, int32_t imm32);
2061   void sbbl(Register dst, int32_t imm32);
2062   void sbbl(Register dst, Address src);
2063   void sbbl(Register dst, Register src);
2064 
2065   void sbbq(Address dst, int32_t imm32);
2066   void sbbq(Register dst, int32_t imm32);
2067   void sbbq(Register dst, Address src);
2068   void sbbq(Register dst, Register src);
2069 
2070   void setb(Condition cc, Register dst);
2071 
2072   void sete(Register dst);
2073   void setl(Register dst);
2074   void setne(Register dst);
2075 
2076   void palignr(XMMRegister dst, XMMRegister src, int imm8);
2077   void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2078   void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2079 
2080   void pblendw(XMMRegister dst, XMMRegister src, int imm8);
2081   void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2082 
2083   void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
2084   void sha1nexte(XMMRegister dst, XMMRegister src);
2085   void sha1msg1(XMMRegister dst, XMMRegister src);
2086   void sha1msg2(XMMRegister dst, XMMRegister src);
2087   // xmm0 is implicit additional source to the following instruction.
2088   void sha256rnds2(XMMRegister dst, XMMRegister src);
2089   void sha256msg1(XMMRegister dst, XMMRegister src);
2090   void sha256msg2(XMMRegister dst, XMMRegister src);
2091 
2092   void shldl(Register dst, Register src);
2093   void shldl(Register dst, Register src, int8_t imm8);
2094   void shrdl(Register dst, Register src);
2095   void shrdl(Register dst, Register src, int8_t imm8);
2096 
2097   void shll(Register dst, int imm8);
2098   void shll(Register dst);
2099 
2100   void shlq(Register dst, int imm8);
2101   void shlq(Register dst);
2102 
2103   void shrl(Register dst, int imm8);
2104   void shrl(Register dst);
2105   void shrl(Address dst);
2106   void shrl(Address dst, int imm8);
2107 
2108   void shrq(Register dst, int imm8);
2109   void shrq(Register dst);
2110   void shrq(Address dst);
2111   void shrq(Address dst, int imm8);
2112 
2113   void smovl(); // QQQ generic?
2114 
2115   // Compute Square Root of Scalar Double-Precision Floating-Point Value
2116   void sqrtsd(XMMRegister dst, Address src);
2117   void sqrtsd(XMMRegister dst, XMMRegister src);
2118 
2119   void roundsd(XMMRegister dst, Address src, int32_t rmode);
2120   void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
2121 
2122   // Compute Square Root of Scalar Single-Precision Floating-Point Value
2123   void sqrtss(XMMRegister dst, Address src);
2124   void sqrtss(XMMRegister dst, XMMRegister src);
2125 
2126   void std();
2127 
2128   void stmxcsr( Address dst );
2129 
2130   void subl(Address dst, int32_t imm32);
2131   void subl(Address dst, Register src);
2132   void subl(Register dst, int32_t imm32);
2133   void subl(Register dst, Address src);
2134   void subl(Register dst, Register src);
2135 
2136   void subq(Address dst, int32_t imm32);
2137   void subq(Address dst, Register src);
2138   void subq(Register dst, int32_t imm32);
2139   void subq(Register dst, Address src);
2140   void subq(Register dst, Register src);
2141 
2142   // Force generation of a 4 byte immediate value even if it fits into 8bit
2143   void subl_imm32(Register dst, int32_t imm32);
2144   void subq_imm32(Register dst, int32_t imm32);
2145 
2146   // Subtract Scalar Double-Precision Floating-Point Values
2147   void subsd(XMMRegister dst, Address src);
2148   void subsd(XMMRegister dst, XMMRegister src);
2149 
2150   // Subtract Scalar Single-Precision Floating-Point Values
2151   void subss(XMMRegister dst, Address src);
2152   void subss(XMMRegister dst, XMMRegister src);
2153 
2154   void testb(Address dst, int imm8);
2155   void testb(Register dst, int imm8);
2156 
2157   void testl(Address dst, int32_t imm32);
2158   void testl(Register dst, int32_t imm32);
2159   void testl(Register dst, Register src);
2160   void testl(Register dst, Address src);
2161 
2162   void testq(Address dst, int32_t imm32);
2163   void testq(Register dst, int32_t imm32);
2164   void testq(Register dst, Register src);
2165   void testq(Register dst, Address src);
2166 
2167   // BMI - count trailing zeros
2168   void tzcntl(Register dst, Register src);
2169   void tzcntl(Register dst, Address src);
2170   void tzcntq(Register dst, Register src);
2171   void tzcntq(Register dst, Address src);
2172 
2173   // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
2174   void ucomisd(XMMRegister dst, Address src);
2175   void ucomisd(XMMRegister dst, XMMRegister src);
2176 
2177   // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
2178   void ucomiss(XMMRegister dst, Address src);
2179   void ucomiss(XMMRegister dst, XMMRegister src);
2180 
2181   void xabort(int8_t imm8);
2182 
2183   void xaddb(Address dst, Register src);
2184   void xaddw(Address dst, Register src);
2185   void xaddl(Address dst, Register src);
2186   void xaddq(Address dst, Register src);
2187 
2188   void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
2189 
2190   void xchgb(Register reg, Address adr);
2191   void xchgw(Register reg, Address adr);
2192   void xchgl(Register reg, Address adr);
2193   void xchgl(Register dst, Register src);
2194 
2195   void xchgq(Register reg, Address adr);
2196   void xchgq(Register dst, Register src);
2197 
2198   void xend();
2199 
2200   // Get Value of Extended Control Register
2201   void xgetbv();
2202 
2203   void xorl(Register dst, int32_t imm32);
2204   void xorl(Address dst, int32_t imm32);
2205   void xorl(Register dst, Address src);
2206   void xorl(Register dst, Register src);
2207   void xorl(Address dst, Register src);
2208 
2209   void xorb(Address dst, Register src);
2210   void xorb(Register dst, Address src);
2211   void xorw(Register dst, Register src);
2212 
2213   void xorq(Register dst, Address src);
2214   void xorq(Address dst, int32_t imm32);
2215   void xorq(Register dst, Register src);
2216   void xorq(Register dst, int32_t imm32);
2217   void xorq(Address dst, Register src);
2218 
2219   void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
2220 
2221   // AVX 3-operands scalar instructions (encoded with VEX prefix)
2222 
2223   void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
2224   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2225   void vaddss(XMMRegister dst, XMMRegister nds, Address src);
2226   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2227   void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
2228   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2229   void vdivss(XMMRegister dst, XMMRegister nds, Address src);
2230   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2231   void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2232   void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2233   void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
2234   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2235   void vmulss(XMMRegister dst, XMMRegister nds, Address src);
2236   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2237   void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
2238   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2239   void vsubss(XMMRegister dst, XMMRegister nds, Address src);
2240   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2241 
2242   void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2243   void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2244   void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2245   void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2246 
2247   void sarxl(Register dst, Register src1, Register src2);
2248   void sarxl(Register dst, Address src1, Register src2);
2249   void sarxq(Register dst, Register src1, Register src2);
2250   void sarxq(Register dst, Address src1, Register src2);
2251   void shlxl(Register dst, Register src1, Register src2);
2252   void shlxl(Register dst, Address src1, Register src2);
2253   void shlxq(Register dst, Register src1, Register src2);
2254   void shlxq(Register dst, Address src1, Register src2);
2255   void shrxl(Register dst, Register src1, Register src2);
2256   void shrxl(Register dst, Address src1, Register src2);
2257   void shrxq(Register dst, Register src1, Register src2);
2258   void shrxq(Register dst, Address src1, Register src2);
2259 
2260   void bzhiq(Register dst, Register src1, Register src2);
2261 
2262   void pextl(Register dst, Register src1, Register src2);
2263   void pdepl(Register dst, Register src1, Register src2);
2264   void pextq(Register dst, Register src1, Register src2);
2265   void pdepq(Register dst, Register src1, Register src2);
2266   void pextl(Register dst, Register src1, Address src2);
2267   void pdepl(Register dst, Register src1, Address src2);
2268   void pextq(Register dst, Register src1, Address src2);
2269   void pdepq(Register dst, Register src1, Address src2);
2270 
2271 
2272   //====================VECTOR ARITHMETIC=====================================
2273   // Add Packed Floating-Point Values
2274   void addpd(XMMRegister dst, XMMRegister src);
2275   void addpd(XMMRegister dst, Address src);
2276   void addps(XMMRegister dst, XMMRegister src);
2277   void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2278   void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2279   void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2280   void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2281 
2282   // Subtract Packed Floating-Point Values
2283   void subpd(XMMRegister dst, XMMRegister src);
2284   void subps(XMMRegister dst, XMMRegister src);
2285   void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2286   void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2287   void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2288   void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2289 
2290   // Multiply Packed Floating-Point Values
2291   void mulpd(XMMRegister dst, XMMRegister src);
2292   void mulpd(XMMRegister dst, Address src);
2293   void mulps(XMMRegister dst, XMMRegister src);
2294   void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2295   void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2296   void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2297   void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2298 
2299   void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2300   void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2301   void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2302   void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2303 
2304   // Divide Packed Floating-Point Values
2305   void divpd(XMMRegister dst, XMMRegister src);
2306   void divps(XMMRegister dst, XMMRegister src);
2307   void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2308   void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2309   void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2310   void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2311 
2312   // Sqrt Packed Floating-Point Values
2313   void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2314   void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2315   void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2316   void vsqrtps(XMMRegister dst, Address src, int vector_len);
2317 
2318   // Round Packed Double precision value.
2319   void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2320   void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2321   void vrndscalepd(XMMRegister dst,  XMMRegister src,  int32_t rmode, int vector_len);
2322   void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2323 
2324   // Bitwise Logical AND of Packed Floating-Point Values
2325   void andpd(XMMRegister dst, XMMRegister src);
2326   void andps(XMMRegister dst, XMMRegister src);
2327   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2328   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2329   void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2330   void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2331 
2332   void unpckhpd(XMMRegister dst, XMMRegister src);
2333   void unpcklpd(XMMRegister dst, XMMRegister src);
2334 
2335   // Bitwise Logical XOR of Packed Floating-Point Values
2336   void xorpd(XMMRegister dst, XMMRegister src);
2337   void xorps(XMMRegister dst, XMMRegister src);
2338   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2339   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2340   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2341   void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2342 
2343   // Add horizontal packed integers
2344   void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2345   void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2346   void phaddw(XMMRegister dst, XMMRegister src);
2347   void phaddd(XMMRegister dst, XMMRegister src);
2348 
2349   // Add packed integers
2350   void paddb(XMMRegister dst, XMMRegister src);
2351   void paddw(XMMRegister dst, XMMRegister src);
2352   void paddd(XMMRegister dst, XMMRegister src);
2353   void paddd(XMMRegister dst, Address src);
2354   void paddq(XMMRegister dst, XMMRegister src);
2355   void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2356   void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2357   void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2358   void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2359   void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2360   void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2361   void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2362   void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2363 
2364   // Leaf level assembler routines for masked operations.
2365   void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2366   void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2367   void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2368   void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2369   void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2370   void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2371   void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2372   void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2373   void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2374   void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2375   void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2376   void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2377   void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2378   void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2379   void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2380   void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2381   void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2382   void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2383   void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2384   void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2385   void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2386   void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2387   void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2388   void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2389   void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2390   void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2391   void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2392   void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2393   void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2394   void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2395   void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2396   void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2397   void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2398   void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2399   void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2400   void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2401   void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2402   void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2403   void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2404   void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2405   void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2406   void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2407   void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2408   void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2409   void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2410   void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2411   void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2412   void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2413   void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2414   void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2415   void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2416   void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2417   void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2418   void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2419   void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2420   void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2421   void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2422   void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2423   void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2424   void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2425   void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2426   void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2427   void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2428   void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2429   void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2430   void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2431   void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2432   void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2433   void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2434   void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2435   void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2436 
2437   void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2438   void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2439   void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2440   void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2441   void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2442   void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2443   void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2444   void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2445   void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2446 
2447   void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2448   void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2449   void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2450   void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2451   void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2452   void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2453   void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2454   void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2455   void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2456   void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2457   void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2458   void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2459   void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2460   void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2461   void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2462   void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2463   void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2464   void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2465   void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2466   void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2467   void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2468   void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2469   void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2470   void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2471   void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2472   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2473   void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2474   void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2475   void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2476   void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2477   void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2478   void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2479   void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2480   void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2481   void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2482   void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2483   void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2484 
2485   void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2486   void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2487   void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2488   void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2489   void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2490   void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2491   void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2492   void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2493 
2494   void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2495   void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2496   void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2497   void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2498 
2499   void evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2500   void evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2501 
2502   // Sub packed integers
2503   void psubb(XMMRegister dst, XMMRegister src);
2504   void psubw(XMMRegister dst, XMMRegister src);
2505   void psubd(XMMRegister dst, XMMRegister src);
2506   void psubq(XMMRegister dst, XMMRegister src);
2507   void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2508   void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2509   void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2510   void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2511   void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2512   void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2513   void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2514   void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2515   void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2516 
2517   // Multiply packed integers (only shorts and ints)
2518   void pmullw(XMMRegister dst, XMMRegister src);
2519   void pmulld(XMMRegister dst, XMMRegister src);
2520   void pmuludq(XMMRegister dst, XMMRegister src);
2521   void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2522   void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2523   void evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2524   void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2525   void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2526   void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2527   void evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2528   void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2529 
2530   // Minimum of packed integers
2531   void pminsb(XMMRegister dst, XMMRegister src);
2532   void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2533   void pminsw(XMMRegister dst, XMMRegister src);
2534   void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2535   void pminsd(XMMRegister dst, XMMRegister src);
2536   void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2537   void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2538   void minps(XMMRegister dst, XMMRegister src);
2539   void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2540   void minpd(XMMRegister dst, XMMRegister src);
2541   void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2542 
2543   // Maximum of packed integers
2544   void pmaxsb(XMMRegister dst, XMMRegister src);
2545   void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2546   void pmaxsw(XMMRegister dst, XMMRegister src);
2547   void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2548   void pmaxsd(XMMRegister dst, XMMRegister src);
2549   void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2550   void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2551   void maxps(XMMRegister dst, XMMRegister src);
2552   void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2553   void maxpd(XMMRegister dst, XMMRegister src);
2554   void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2555 
2556   // Shift left packed integers
2557   void psllw(XMMRegister dst, int shift);
2558   void pslld(XMMRegister dst, int shift);
2559   void psllq(XMMRegister dst, int shift);
2560   void psllw(XMMRegister dst, XMMRegister shift);
2561   void pslld(XMMRegister dst, XMMRegister shift);
2562   void psllq(XMMRegister dst, XMMRegister shift);
2563   void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2564   void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2565   void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2566   void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2567   void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2568   void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2569   void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2570 
2571   // Logical shift right packed integers
2572   void psrlw(XMMRegister dst, int shift);
2573   void psrld(XMMRegister dst, int shift);
2574   void psrlq(XMMRegister dst, int shift);
2575   void psrlw(XMMRegister dst, XMMRegister shift);
2576   void psrld(XMMRegister dst, XMMRegister shift);
2577   void psrlq(XMMRegister dst, XMMRegister shift);
2578   void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2579   void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2580   void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2581   void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2582   void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2583   void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2584   void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2585   void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2586   void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2587 
2588   // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2589   void psraw(XMMRegister dst, int shift);
2590   void psrad(XMMRegister dst, int shift);
2591   void psraw(XMMRegister dst, XMMRegister shift);
2592   void psrad(XMMRegister dst, XMMRegister shift);
2593   void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2594   void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2595   void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2596   void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2597   void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2598   void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2599   void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2600 
2601   // Variable shift left packed integers
2602   void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2603   void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2604 
2605   // Variable shift right packed integers
2606   void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2607   void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2608 
2609   // Variable shift right arithmetic packed integers
2610   void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2611   void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2612 
2613   void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2614   void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2615 
2616   // And packed integers
2617   void pand(XMMRegister dst, XMMRegister src);
2618   void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2619   void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2620   void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2621 
2622   // Andn packed integers
2623   void pandn(XMMRegister dst, XMMRegister src);
2624   void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2625 
2626   // Or packed integers
2627   void por(XMMRegister dst, XMMRegister src);
2628   void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2629   void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2630   void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2631 
2632   // Xor packed integers
2633   void pxor(XMMRegister dst, XMMRegister src);
2634   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2635   void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2636   void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2637   void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2638   void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2639 
2640   // Ternary logic instruction.
2641   void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2642   void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address     src3, int vector_len);
2643   void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2644 
2645   // Vector compress/expand instructions.
2646   void evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2647   void evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2648   void evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2649   void evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2650   void evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2651   void evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2652 
2653   void evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2654   void evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2655   void evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2656   void evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2657   void evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2658   void evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2659 
2660   // Vector Rotate Left/Right instruction.
2661   void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2662   void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2663   void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2664   void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2665   void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2666   void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2667   void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2668   void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2669 
2670   // vinserti forms
2671   void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2672   void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2673   void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2674   void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2675   void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2676 
2677   // vinsertf forms
2678   void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2679   void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2680   void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2681   void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2682   void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2683   void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2684 
2685   // vextracti forms
2686   void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2687   void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2688   void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2689   void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2690   void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2691   void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2692   void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2693 
2694   // vextractf forms
2695   void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2696   void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2697   void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2698   void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2699   void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2700   void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2701   void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2702 
2703   // xmm/mem sourced byte/word/dword/qword replicate
2704   void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2705   void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2706   void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2707   void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2708   void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2709   void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2710   void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2711   void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2712 
2713   void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
2714   void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2715   void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2716 
2717   // scalar single/double/128bit precision replicate
2718   void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2719   void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2720   void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2721   void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2722   void vbroadcastf128(XMMRegister dst, Address src, int vector_len);
2723 
2724   // gpr sourced byte/word/dword/qword replicate
2725   void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2726   void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2727   void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2728   void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2729 
2730   // Gather AVX2 and AVX3
2731   void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2732   void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2733   void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2734   void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2735   void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2736   void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len);
2737   void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2738   void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len);
2739 
2740   //Scatter AVX3 only
2741   void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2742   void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len);
2743   void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len);
2744   void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2745 
2746   // Carry-Less Multiplication Quadword
2747   void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2748   void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2749   void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2750   // AVX instruction which is used to clear upper 128 bits of YMM registers and
2751   // to avoid transaction penalty between AVX and SSE states. There is no
2752   // penalty if legacy SSE instructions are encoded using VEX prefix because
2753   // they always clear upper 128 bits. It should be used before calling
2754   // runtime code and native libraries.
2755   void vzeroupper();
2756 
2757   // Vector double compares
2758   void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2759   void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2760                ComparisonPredicateFP comparison, int vector_len);
2761 
2762   // Vector float compares
2763   void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
2764   void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2765                ComparisonPredicateFP comparison, int vector_len);
2766 
2767   // Vector integer compares
2768   void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2769   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2770                int comparison, bool is_signed, int vector_len);
2771   void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2772                int comparison, bool is_signed, int vector_len);
2773 
2774   // Vector long compares
2775   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2776                int comparison, bool is_signed, int vector_len);
2777   void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2778                int comparison, bool is_signed, int vector_len);
2779 
2780   // Vector byte compares
2781   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2782                int comparison, bool is_signed, int vector_len);
2783   void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2784                int comparison, bool is_signed, int vector_len);
2785 
2786   // Vector short compares
2787   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2788                int comparison, bool is_signed, int vector_len);
2789   void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2790                int comparison, bool is_signed, int vector_len);
2791 
2792   void evpmovb2m(KRegister dst, XMMRegister src, int vector_len);
2793   void evpmovw2m(KRegister dst, XMMRegister src, int vector_len);
2794   void evpmovd2m(KRegister dst, XMMRegister src, int vector_len);
2795   void evpmovq2m(KRegister dst, XMMRegister src, int vector_len);
2796   void evpmovm2b(XMMRegister dst, KRegister src, int vector_len);
2797   void evpmovm2w(XMMRegister dst, KRegister src, int vector_len);
2798   void evpmovm2d(XMMRegister dst, KRegister src, int vector_len);
2799   void evpmovm2q(XMMRegister dst, KRegister src, int vector_len);
2800 
2801   // floating point class tests
2802   void vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8);
2803   void vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8);
2804 
2805   // Vector blends
2806   void blendvps(XMMRegister dst, XMMRegister src);
2807   void blendvpd(XMMRegister dst, XMMRegister src);
2808   void pblendvb(XMMRegister dst, XMMRegister src);
2809   void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2810   void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2811   void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2812   void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2813   void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2814   void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2815   void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2816   void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2817   void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2818   void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2819   void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2820 
2821   // Galois field affine transformation instructions.
2822   void gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8);
2823   void vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len);
2824 
2825  protected:
2826   // Next instructions require address alignment 16 bytes SSE mode.
2827   // They should be called only from corresponding MacroAssembler instructions.
2828   void andpd(XMMRegister dst, Address src);
2829   void andps(XMMRegister dst, Address src);
2830   void xorpd(XMMRegister dst, Address src);
2831   void xorps(XMMRegister dst, Address src);
2832 
2833 };
2834 
2835 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2836 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2837 // are applied.
2838 class InstructionAttr {
2839 public:
2840   InstructionAttr(
2841     int vector_len,     // The length of vector to be applied in encoding - for both AVX and EVEX
2842     bool rex_vex_w,     // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2843     bool legacy_mode,   // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2844     bool no_reg_mask,   // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2845     bool uses_vl)       // This instruction may have legacy constraints based on vector length for EVEX
2846     :
2847       _rex_vex_w(rex_vex_w),
2848       _legacy_mode(legacy_mode || UseAVX < 3),
2849       _no_reg_mask(no_reg_mask),
2850       _uses_vl(uses_vl),
2851       _rex_vex_w_reverted(false),
2852       _is_evex_instruction(false),
2853       _is_clear_context(true),
2854       _is_extended_context(false),
2855       _avx_vector_len(vector_len),
2856       _tuple_type(Assembler::EVEX_ETUP),
2857       _input_size_in_bits(Assembler::EVEX_NObit),
2858       _evex_encoding(0),
2859       _embedded_opmask_register_specifier(0), // hard code k0
2860       _current_assembler(NULL) { }
2861 
2862   ~InstructionAttr() {
2863     if (_current_assembler != NULL) {
2864       _current_assembler->clear_attributes();
2865     }
2866     _current_assembler = NULL;
2867   }
2868 
2869 private:
2870   bool _rex_vex_w;
2871   bool _legacy_mode;
2872   bool _no_reg_mask;
2873   bool _uses_vl;
2874   bool _rex_vex_w_reverted;
2875   bool _is_evex_instruction;
2876   bool _is_clear_context;
2877   bool _is_extended_context;
2878   int  _avx_vector_len;
2879   int  _tuple_type;
2880   int  _input_size_in_bits;
2881   int  _evex_encoding;
2882   int _embedded_opmask_register_specifier;
2883 
2884   Assembler *_current_assembler;
2885 
2886 public:
2887   // query functions for field accessors
2888   bool is_rex_vex_w(void) const { return _rex_vex_w; }
2889   bool is_legacy_mode(void) const { return _legacy_mode; }
2890   bool is_no_reg_mask(void) const { return _no_reg_mask; }
2891   bool uses_vl(void) const { return _uses_vl; }
2892   bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2893   bool is_evex_instruction(void) const { return _is_evex_instruction; }
2894   bool is_clear_context(void) const { return _is_clear_context; }
2895   bool is_extended_context(void) const { return _is_extended_context; }
2896   int  get_vector_len(void) const { return _avx_vector_len; }
2897   int  get_tuple_type(void) const { return _tuple_type; }
2898   int  get_input_size(void) const { return _input_size_in_bits; }
2899   int  get_evex_encoding(void) const { return _evex_encoding; }
2900   int  get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2901 
2902   // Set the vector len manually
2903   void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2904 
2905   // Set revert rex_vex_w for avx encoding
2906   void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2907 
2908   // Set rex_vex_w based on state
2909   void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2910 
2911   // Set the instruction to be encoded in AVX mode
2912   void set_is_legacy_mode(void) { _legacy_mode = true; }
2913 
2914   // Set the current instruction to be encoded as an EVEX instruction
2915   void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2916 
2917   // Internal encoding data used in compressed immediate offset programming
2918   void set_evex_encoding(int value) { _evex_encoding = value; }
2919 
2920   // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
2921   // This method unsets it so that merge semantics are used instead.
2922   void reset_is_clear_context(void) { _is_clear_context = false; }
2923 
2924   // Map back to current assembler so that we can manage object level association
2925   void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2926 
2927   // Address modifiers used for compressed displacement calculation
2928   void set_address_attributes(int tuple_type, int input_size_in_bits);
2929 
2930   // Set embedded opmask register specifier.
2931   void set_embedded_opmask_register_specifier(KRegister mask) {
2932     _embedded_opmask_register_specifier = mask->encoding() & 0x7;
2933   }
2934 
2935 };
2936 
2937 #endif // CPU_X86_ASSEMBLER_X86_HPP