1 /*
2 * Copyright (c) 1997, 2023, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
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23 */
24
25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
26 #define CPU_X86_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "utilities/checkedCast.hpp"
30 #include "utilities/powerOfTwo.hpp"
31
32 // Contains all the definitions needed for x86 assembly code generation.
33
34 // Calling convention
35 class Argument {
36 public:
37 enum {
38 #ifdef _LP64
39 #ifdef _WIN64
40 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
41 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
42 n_int_register_returns_c = 1, // rax
43 n_float_register_returns_c = 1, // xmm0
44 #else
45 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
46 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
47 n_int_register_returns_c = 2, // rax, rdx
48 n_float_register_returns_c = 2, // xmm0, xmm1
49 #endif // _WIN64
50 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
51 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
52 #else
53 n_register_parameters = 0, // 0 registers used to pass arguments
54 n_int_register_parameters_j = 0,
55 n_float_register_parameters_j = 0
56 #endif // _LP64
57 };
58 };
59
60
61 #ifdef _LP64
62 // Symbolically name the register arguments used by the c calling convention.
63 // Windows is different from linux/solaris. So much for standards...
64
65 #ifdef _WIN64
66
67 constexpr Register c_rarg0 = rcx;
68 constexpr Register c_rarg1 = rdx;
69 constexpr Register c_rarg2 = r8;
70 constexpr Register c_rarg3 = r9;
71
72 constexpr XMMRegister c_farg0 = xmm0;
73 constexpr XMMRegister c_farg1 = xmm1;
74 constexpr XMMRegister c_farg2 = xmm2;
75 constexpr XMMRegister c_farg3 = xmm3;
76
77 #else
78
79 constexpr Register c_rarg0 = rdi;
80 constexpr Register c_rarg1 = rsi;
81 constexpr Register c_rarg2 = rdx;
82 constexpr Register c_rarg3 = rcx;
83 constexpr Register c_rarg4 = r8;
84 constexpr Register c_rarg5 = r9;
85
86 constexpr XMMRegister c_farg0 = xmm0;
87 constexpr XMMRegister c_farg1 = xmm1;
88 constexpr XMMRegister c_farg2 = xmm2;
89 constexpr XMMRegister c_farg3 = xmm3;
90 constexpr XMMRegister c_farg4 = xmm4;
91 constexpr XMMRegister c_farg5 = xmm5;
92 constexpr XMMRegister c_farg6 = xmm6;
93 constexpr XMMRegister c_farg7 = xmm7;
94
95 #endif // _WIN64
96
97 // Symbolically name the register arguments used by the Java calling convention.
98 // We have control over the convention for java so we can do what we please.
99 // What pleases us is to offset the java calling convention so that when
100 // we call a suitable jni method the arguments are lined up and we don't
101 // have to do little shuffling. A suitable jni method is non-static and a
102 // small number of arguments (two fewer args on windows)
103 //
104 // |-------------------------------------------------------|
105 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
106 // |-------------------------------------------------------|
107 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
108 // | rdi rsi rdx rcx r8 r9 | solaris/linux
109 // |-------------------------------------------------------|
110 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
111 // |-------------------------------------------------------|
112
113 constexpr Register j_rarg0 = c_rarg1;
114 constexpr Register j_rarg1 = c_rarg2;
115 constexpr Register j_rarg2 = c_rarg3;
116 // Windows runs out of register args here
117 #ifdef _WIN64
118 constexpr Register j_rarg3 = rdi;
119 constexpr Register j_rarg4 = rsi;
120 #else
121 constexpr Register j_rarg3 = c_rarg4;
122 constexpr Register j_rarg4 = c_rarg5;
123 #endif /* _WIN64 */
124 constexpr Register j_rarg5 = c_rarg0;
125
126 constexpr XMMRegister j_farg0 = xmm0;
127 constexpr XMMRegister j_farg1 = xmm1;
128 constexpr XMMRegister j_farg2 = xmm2;
129 constexpr XMMRegister j_farg3 = xmm3;
130 constexpr XMMRegister j_farg4 = xmm4;
131 constexpr XMMRegister j_farg5 = xmm5;
132 constexpr XMMRegister j_farg6 = xmm6;
133 constexpr XMMRegister j_farg7 = xmm7;
134
135 constexpr Register rscratch1 = r10; // volatile
136 constexpr Register rscratch2 = r11; // volatile
137
138 constexpr Register r12_heapbase = r12; // callee-saved
139 constexpr Register r15_thread = r15; // callee-saved
140
141 #else
142 // rscratch1 will appear in 32bit code that is dead but of course must compile
143 // Using noreg ensures if the dead code is incorrectly live and executed it
144 // will cause an assertion failure
145 #define rscratch1 noreg
146 #define rscratch2 noreg
147
148 #endif // _LP64
149
150 // JSR 292
151 // On x86, the SP does not have to be saved when invoking method handle intrinsics
152 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
153 constexpr Register rbp_mh_SP_save = noreg;
154
155 // Address is an abstraction used to represent a memory location
156 // using any of the amd64 addressing modes with one object.
157 //
158 // Note: A register location is represented via a Register, not
159 // via an address for efficiency & simplicity reasons.
160
161 class ArrayAddress;
162
163 class Address {
164 public:
165 enum ScaleFactor {
166 no_scale = -1,
167 times_1 = 0,
168 times_2 = 1,
169 times_4 = 2,
170 times_8 = 3,
171 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
172 };
173 static ScaleFactor times(int size) {
174 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
175 if (size == 8) return times_8;
176 if (size == 4) return times_4;
177 if (size == 2) return times_2;
178 return times_1;
179 }
180 static int scale_size(ScaleFactor scale) {
181 assert(scale != no_scale, "");
182 assert(((1 << (int)times_1) == 1 &&
183 (1 << (int)times_2) == 2 &&
184 (1 << (int)times_4) == 4 &&
185 (1 << (int)times_8) == 8), "");
186 return (1 << (int)scale);
187 }
188
189 private:
190 Register _base;
191 Register _index;
192 XMMRegister _xmmindex;
193 ScaleFactor _scale;
194 int _disp;
195 bool _isxmmindex;
196 RelocationHolder _rspec;
197
198 // Easily misused constructors make them private
199 // %%% can we make these go away?
200 NOT_LP64(Address(address loc, RelocationHolder spec);)
201 Address(int disp, address loc, relocInfo::relocType rtype);
202 Address(int disp, address loc, RelocationHolder spec);
203
204 public:
205
206 int disp() { return _disp; }
207 // creation
208 Address()
209 : _base(noreg),
210 _index(noreg),
211 _xmmindex(xnoreg),
212 _scale(no_scale),
213 _disp(0),
214 _isxmmindex(false){
215 }
216
217 explicit Address(Register base, int disp = 0)
218 : _base(base),
219 _index(noreg),
220 _xmmindex(xnoreg),
221 _scale(no_scale),
222 _disp(disp),
223 _isxmmindex(false){
224 }
225
226 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
227 : _base (base),
228 _index(index),
229 _xmmindex(xnoreg),
230 _scale(scale),
231 _disp (disp),
232 _isxmmindex(false) {
233 assert(!index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
238 : _base (base),
239 _index(index.register_or_noreg()),
240 _xmmindex(xnoreg),
241 _scale(scale),
242 _disp (disp + checked_cast<int>(index.constant_or_zero() * scale_size(scale))),
243 _isxmmindex(false){
244 if (!index.is_register()) scale = Address::no_scale;
245 assert(!_index->is_valid() == (scale == Address::no_scale),
246 "inconsistent address");
247 }
248
249 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
250 : _base (base),
251 _index(noreg),
252 _xmmindex(index),
253 _scale(scale),
254 _disp(disp),
255 _isxmmindex(true) {
256 assert(!index->is_valid() == (scale == Address::no_scale),
257 "inconsistent address");
258 }
259
260 // The following overloads are used in connection with the
261 // ByteSize type (see sizes.hpp). They simplify the use of
262 // ByteSize'd arguments in assembly code.
263
264 Address(Register base, ByteSize disp)
265 : Address(base, in_bytes(disp)) {}
266
267 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
268 : Address(base, index, scale, in_bytes(disp)) {}
269
270 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
271 : Address(base, index, scale, in_bytes(disp)) {}
272
273 Address plus_disp(int disp) const {
274 Address a = (*this);
275 a._disp += disp;
276 return a;
277 }
278 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
279 Address a = (*this);
280 a._disp += checked_cast<int>(disp.constant_or_zero() * scale_size(scale));
281 if (disp.is_register()) {
282 assert(!a.index()->is_valid(), "competing indexes");
283 a._index = disp.as_register();
284 a._scale = scale;
285 }
286 return a;
287 }
288 bool is_same_address(Address a) const {
289 // disregard _rspec
290 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
291 }
292
293 // accessors
294 bool uses(Register reg) const { return _base == reg || _index == reg; }
295 Register base() const { return _base; }
296 Register index() const { return _index; }
297 XMMRegister xmmindex() const { return _xmmindex; }
298 ScaleFactor scale() const { return _scale; }
299 int disp() const { return _disp; }
300 bool isxmmindex() const { return _isxmmindex; }
301
302 // Convert the raw encoding form into the form expected by the constructor for
303 // Address. An index of 4 (rsp) corresponds to having no index, so convert
304 // that to noreg for the Address constructor.
305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
306
307 static Address make_array(ArrayAddress);
308
309 private:
310 bool base_needs_rex() const {
311 return _base->is_valid() && _base->encoding() >= 8;
312 }
313
314 bool index_needs_rex() const {
315 return _index->is_valid() &&_index->encoding() >= 8;
316 }
317
318 bool xmmindex_needs_rex() const {
319 return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
320 }
321
322 relocInfo::relocType reloc() const { return _rspec.type(); }
323
324 friend class Assembler;
325 friend class MacroAssembler;
326 friend class LIR_Assembler; // base/index/scale/disp
327 };
328
329 //
330 // AddressLiteral has been split out from Address because operands of this type
331 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
332 // the few instructions that need to deal with address literals are unique and the
333 // MacroAssembler does not have to implement every instruction in the Assembler
334 // in order to search for address literals that may need special handling depending
335 // on the instruction and the platform. As small step on the way to merging i486/amd64
336 // directories.
337 //
338 class AddressLiteral {
339 friend class ArrayAddress;
340 RelocationHolder _rspec;
341 // Typically we use AddressLiterals we want to use their rval
342 // However in some situations we want the lval (effect address) of the item.
343 // We provide a special factory for making those lvals.
344 bool _is_lval;
345
346 // If the target is far we'll need to load the ea of this to
347 // a register to reach it. Otherwise if near we can do rip
348 // relative addressing.
349
350 address _target;
351
352 protected:
353 // creation
354 AddressLiteral()
355 : _is_lval(false),
356 _target(nullptr)
357 {}
358
359 public:
360
361
362 AddressLiteral(address target, relocInfo::relocType rtype);
363
364 AddressLiteral(address target, RelocationHolder const& rspec)
365 : _rspec(rspec),
366 _is_lval(false),
367 _target(target)
368 {}
369
370 AddressLiteral addr() {
371 AddressLiteral ret = *this;
372 ret._is_lval = true;
373 return ret;
374 }
375
376
377 private:
378
379 address target() { return _target; }
380 bool is_lval() const { return _is_lval; }
381
382 relocInfo::relocType reloc() const { return _rspec.type(); }
383 const RelocationHolder& rspec() const { return _rspec; }
384
385 friend class Assembler;
386 friend class MacroAssembler;
387 friend class Address;
388 friend class LIR_Assembler;
389 };
390
391 // Convenience classes
392 class RuntimeAddress: public AddressLiteral {
393
394 public:
395
396 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
397
398 };
399
400 class ExternalAddress: public AddressLiteral {
401 private:
402 static relocInfo::relocType reloc_for_target(address target) {
403 // Sometimes ExternalAddress is used for values which aren't
404 // exactly addresses, like the card table base.
405 // external_word_type can't be used for values in the first page
406 // so just skip the reloc in that case.
407 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
408 }
409
410 public:
411
412 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
413
414 };
415
416 class InternalAddress: public AddressLiteral {
417
418 public:
419
420 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
421
422 };
423
424 // x86 can do array addressing as a single operation since disp can be an absolute
425 // address amd64 can't. We create a class that expresses the concept but does extra
426 // magic on amd64 to get the final result
427
428 class ArrayAddress {
429 private:
430
431 AddressLiteral _base;
432 Address _index;
433
434 public:
435
436 ArrayAddress() {};
437 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
438 AddressLiteral base() { return _base; }
439 Address index() { return _index; }
440
441 };
442
443 class InstructionAttr;
444
445 // 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
446 // See fxsave and xsave(EVEX enabled) documentation for layout
447 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
448
449 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
450 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
451 // is what you get. The Assembler is generating code into a CodeBuffer.
452
453 class Assembler : public AbstractAssembler {
454 friend class AbstractAssembler; // for the non-virtual hack
455 friend class LIR_Assembler; // as_Address()
456 friend class StubGenerator;
457
458 public:
459 enum Condition { // The x86 condition codes used for conditional jumps/moves.
460 zero = 0x4,
461 notZero = 0x5,
462 equal = 0x4,
463 notEqual = 0x5,
464 less = 0xc,
465 lessEqual = 0xe,
466 greater = 0xf,
467 greaterEqual = 0xd,
468 below = 0x2,
469 belowEqual = 0x6,
470 above = 0x7,
471 aboveEqual = 0x3,
472 overflow = 0x0,
473 noOverflow = 0x1,
474 carrySet = 0x2,
475 carryClear = 0x3,
476 negative = 0x8,
477 positive = 0x9,
478 parity = 0xa,
479 noParity = 0xb
480 };
481
482 enum Prefix {
483 // segment overrides
484 CS_segment = 0x2e,
485 SS_segment = 0x36,
486 DS_segment = 0x3e,
487 ES_segment = 0x26,
488 FS_segment = 0x64,
489 GS_segment = 0x65,
490
491 REX = 0x40,
492
493 REX_B = 0x41,
494 REX_X = 0x42,
495 REX_XB = 0x43,
496 REX_R = 0x44,
497 REX_RB = 0x45,
498 REX_RX = 0x46,
499 REX_RXB = 0x47,
500
501 REX_W = 0x48,
502
503 REX_WB = 0x49,
504 REX_WX = 0x4A,
505 REX_WXB = 0x4B,
506 REX_WR = 0x4C,
507 REX_WRB = 0x4D,
508 REX_WRX = 0x4E,
509 REX_WRXB = 0x4F,
510
511 VEX_3bytes = 0xC4,
512 VEX_2bytes = 0xC5,
513 EVEX_4bytes = 0x62,
514 Prefix_EMPTY = 0x0
515 };
516
517 enum VexPrefix {
518 VEX_B = 0x20,
519 VEX_X = 0x40,
520 VEX_R = 0x80,
521 VEX_W = 0x80
522 };
523
524 enum ExexPrefix {
525 EVEX_F = 0x04,
526 EVEX_V = 0x08,
527 EVEX_Rb = 0x10,
528 EVEX_X = 0x40,
529 EVEX_Z = 0x80
530 };
531
532 enum EvexRoundPrefix {
533 EVEX_RNE = 0x0,
534 EVEX_RD = 0x1,
535 EVEX_RU = 0x2,
536 EVEX_RZ = 0x3
537 };
538
539 enum VexSimdPrefix {
540 VEX_SIMD_NONE = 0x0,
541 VEX_SIMD_66 = 0x1,
542 VEX_SIMD_F3 = 0x2,
543 VEX_SIMD_F2 = 0x3
544 };
545
546 enum VexOpcode {
547 VEX_OPCODE_NONE = 0x0,
548 VEX_OPCODE_0F = 0x1,
549 VEX_OPCODE_0F_38 = 0x2,
550 VEX_OPCODE_0F_3A = 0x3,
551 VEX_OPCODE_MASK = 0x1F
552 };
553
554 enum AvxVectorLen {
555 AVX_128bit = 0x0,
556 AVX_256bit = 0x1,
557 AVX_512bit = 0x2,
558 AVX_NoVec = 0x4
559 };
560
561 enum EvexTupleType {
562 EVEX_FV = 0,
563 EVEX_HV = 4,
564 EVEX_FVM = 6,
565 EVEX_T1S = 7,
566 EVEX_T1F = 11,
567 EVEX_T2 = 13,
568 EVEX_T4 = 15,
569 EVEX_T8 = 17,
570 EVEX_HVM = 18,
571 EVEX_QVM = 19,
572 EVEX_OVM = 20,
573 EVEX_M128 = 21,
574 EVEX_DUP = 22,
575 EVEX_ETUP = 23
576 };
577
578 enum EvexInputSizeInBits {
579 EVEX_8bit = 0,
580 EVEX_16bit = 1,
581 EVEX_32bit = 2,
582 EVEX_64bit = 3,
583 EVEX_NObit = 4
584 };
585
586 enum WhichOperand {
587 // input to locate_operand, and format code for relocations
588 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
589 disp32_operand = 1, // embedded 32-bit displacement or address
590 call32_operand = 2, // embedded 32-bit self-relative displacement
591 #ifndef _LP64
592 _WhichOperand_limit = 3
593 #else
594 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
595 _WhichOperand_limit = 4
596 #endif
597 };
598
599 // Comparison predicates for integral types & FP types when using SSE
600 enum ComparisonPredicate {
601 eq = 0,
602 lt = 1,
603 le = 2,
604 _false = 3,
605 neq = 4,
606 nlt = 5,
607 nle = 6,
608 _true = 7
609 };
610
611 // Comparison predicates for FP types when using AVX
612 // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
613 // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
614 enum ComparisonPredicateFP {
615 EQ_OQ = 0,
616 LT_OS = 1,
617 LE_OS = 2,
618 UNORD_Q = 3,
619 NEQ_UQ = 4,
620 NLT_US = 5,
621 NLE_US = 6,
622 ORD_Q = 7,
623 EQ_UQ = 8,
624 NGE_US = 9,
625 NGT_US = 0xA,
626 FALSE_OQ = 0XB,
627 NEQ_OQ = 0xC,
628 GE_OS = 0xD,
629 GT_OS = 0xE,
630 TRUE_UQ = 0xF,
631 EQ_OS = 0x10,
632 LT_OQ = 0x11,
633 LE_OQ = 0x12,
634 UNORD_S = 0x13,
635 NEQ_US = 0x14,
636 NLT_UQ = 0x15,
637 NLE_UQ = 0x16,
638 ORD_S = 0x17,
639 EQ_US = 0x18,
640 NGE_UQ = 0x19,
641 NGT_UQ = 0x1A,
642 FALSE_OS = 0x1B,
643 NEQ_OS = 0x1C,
644 GE_OQ = 0x1D,
645 GT_OQ = 0x1E,
646 TRUE_US =0x1F
647 };
648
649 enum Width {
650 B = 0,
651 W = 1,
652 D = 2,
653 Q = 3
654 };
655
656 //---< calculate length of instruction >---
657 // As instruction size can't be found out easily on x86/x64,
658 // we just use '4' for len and maxlen.
659 // instruction must start at passed address
660 static unsigned int instr_len(unsigned char *instr) { return 4; }
661
662 //---< longest instructions >---
663 // Max instruction length is not specified in architecture documentation.
664 // We could use a "safe enough" estimate (15), but just default to
665 // instruction length guess from above.
666 static unsigned int instr_maxlen() { return 4; }
667
668 // NOTE: The general philopsophy of the declarations here is that 64bit versions
669 // of instructions are freely declared without the need for wrapping them an ifdef.
670 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
671 // In the .cpp file the implementations are wrapped so that they are dropped out
672 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
673 // to the size it was prior to merging up the 32bit and 64bit assemblers.
674 //
675 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
676 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
677
678 private:
679
680 bool _legacy_mode_bw;
681 bool _legacy_mode_dq;
682 bool _legacy_mode_vl;
683 bool _legacy_mode_vlbw;
684 NOT_LP64(bool _is_managed;)
685
686 InstructionAttr *_attributes;
687 void set_attributes(InstructionAttr* attributes);
688
689 // 64bit prefixes
690 void prefix(Register reg);
691 void prefix(Register dst, Register src, Prefix p);
692 void prefix(Register dst, Address adr, Prefix p);
693
694 void prefix(Address adr);
695 void prefix(Address adr, Register reg, bool byteinst = false);
696 void prefix(Address adr, XMMRegister reg);
697
698 int prefix_and_encode(int reg_enc, bool byteinst = false);
699 int prefix_and_encode(int dst_enc, int src_enc) {
700 return prefix_and_encode(dst_enc, false, src_enc, false);
701 }
702 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
703
704 // Some prefixq variants always emit exactly one prefix byte, so besides a
705 // prefix-emitting method we provide a method to get the prefix byte to emit,
706 // which can then be folded into a byte stream.
707 int8_t get_prefixq(Address adr);
708 int8_t get_prefixq(Address adr, Register reg);
709
710 void prefixq(Address adr);
711 void prefixq(Address adr, Register reg);
712 void prefixq(Address adr, XMMRegister reg);
713
714 int prefixq_and_encode(int reg_enc);
715 int prefixq_and_encode(int dst_enc, int src_enc);
716
717 void rex_prefix(Address adr, XMMRegister xreg,
718 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
719 int rex_prefix_and_encode(int dst_enc, int src_enc,
720 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
721
722 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
723
724 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
725 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
726
727 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
728 VexSimdPrefix pre, VexOpcode opc,
729 InstructionAttr *attributes);
730
731 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
732 VexSimdPrefix pre, VexOpcode opc,
733 InstructionAttr *attributes);
734
735 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
736 VexOpcode opc, InstructionAttr *attributes);
737
738 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
739 VexOpcode opc, InstructionAttr *attributes);
740
741 // Helper functions for groups of instructions
742 void emit_arith_b(int op1, int op2, Register dst, int imm8);
743
744 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
745 // Force generation of a 4 byte immediate value even if it fits into 8bit
746 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
747 void emit_arith(int op1, int op2, Register dst, Register src);
748
749 bool emit_compressed_disp_byte(int &disp);
750
751 void emit_modrm(int mod, int dst_enc, int src_enc);
752 void emit_modrm_disp8(int mod, int dst_enc, int src_enc,
753 int disp);
754 void emit_modrm_sib(int mod, int dst_enc, int src_enc,
755 Address::ScaleFactor scale, int index_enc, int base_enc);
756 void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
757 Address::ScaleFactor scale, int index_enc, int base_enc,
758 int disp);
759
760 void emit_operand_helper(int reg_enc,
761 int base_enc, int index_enc, Address::ScaleFactor scale,
762 int disp,
763 RelocationHolder const& rspec,
764 int post_addr_length);
765
766 void emit_operand(Register reg,
767 Register base, Register index, Address::ScaleFactor scale,
768 int disp,
769 RelocationHolder const& rspec,
770 int post_addr_length);
771
772 void emit_operand(Register reg,
773 Register base, XMMRegister index, Address::ScaleFactor scale,
774 int disp,
775 RelocationHolder const& rspec,
776 int post_addr_length);
777
778 void emit_operand(XMMRegister xreg,
779 Register base, XMMRegister xindex, Address::ScaleFactor scale,
780 int disp,
781 RelocationHolder const& rspec,
782 int post_addr_length);
783
784 void emit_operand(Register reg, Address adr,
785 int post_addr_length);
786
787 void emit_operand(XMMRegister reg,
788 Register base, Register index, Address::ScaleFactor scale,
789 int disp,
790 RelocationHolder const& rspec,
791 int post_addr_length);
792
793 void emit_operand_helper(KRegister kreg,
794 int base_enc, int index_enc, Address::ScaleFactor scale,
795 int disp,
796 RelocationHolder const& rspec,
797 int post_addr_length);
798
799 void emit_operand(KRegister kreg, Address adr,
800 int post_addr_length);
801
802 void emit_operand(KRegister kreg,
803 Register base, Register index, Address::ScaleFactor scale,
804 int disp,
805 RelocationHolder const& rspec,
806 int post_addr_length);
807
808 void emit_operand(XMMRegister reg, Address adr, int post_addr_length);
809
810 // Immediate-to-memory forms
811 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
812 void emit_arith_operand_imm32(int op1, Register rm, Address adr, int32_t imm32);
813
814 protected:
815 #ifdef ASSERT
816 void check_relocation(RelocationHolder const& rspec, int format);
817 #endif
818
819 void emit_data(jint data, relocInfo::relocType rtype, int format);
820 void emit_data(jint data, RelocationHolder const& rspec, int format);
821 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
822 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
823
824 bool always_reachable(AddressLiteral adr) NOT_LP64( { return true; } );
825 bool reachable(AddressLiteral adr) NOT_LP64( { return true; } );
826
827
828 // These are all easily abused and hence protected
829
830 public:
831 // 32BIT ONLY SECTION
832 #ifndef _LP64
833 // Make these disappear in 64bit mode since they would never be correct
834 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
835 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
836
837 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
838 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
839
840 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
841 #else
842 // 64BIT ONLY SECTION
843 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
844
845 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
846 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
847
848 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
849 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
850 #endif // _LP64
851
852 protected:
853 // These are unique in that we are ensured by the caller that the 32bit
854 // relative in these instructions will always be able to reach the potentially
855 // 64bit address described by entry. Since they can take a 64bit address they
856 // don't have the 32 suffix like the other instructions in this class.
857
858 void call_literal(address entry, RelocationHolder const& rspec);
859 void jmp_literal(address entry, RelocationHolder const& rspec);
860
861 // Avoid using directly section
862 // Instructions in this section are actually usable by anyone without danger
863 // of failure but have performance issues that are addressed my enhanced
864 // instructions which will do the proper thing base on the particular cpu.
865 // We protect them because we don't trust you...
866
867 // Don't use next inc() and dec() methods directly. INC & DEC instructions
868 // could cause a partial flag stall since they don't set CF flag.
869 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
870 // which call inc() & dec() or add() & sub() in accordance with
871 // the product flag UseIncDec value.
872
873 void decl(Register dst);
874 void decl(Address dst);
875 void decq(Address dst);
876
877 void incl(Register dst);
878 void incl(Address dst);
879 void incq(Register dst);
880 void incq(Address dst);
881
882 // New cpus require use of movsd and movss to avoid partial register stall
883 // when loading from memory. But for old Opteron use movlpd instead of movsd.
884 // The selection is done in MacroAssembler::movdbl() and movflt().
885
886 // Move Scalar Single-Precision Floating-Point Values
887 void movss(XMMRegister dst, Address src);
888 void movss(XMMRegister dst, XMMRegister src);
889 void movss(Address dst, XMMRegister src);
890
891 // Move Scalar Double-Precision Floating-Point Values
892 void movsd(XMMRegister dst, Address src);
893 void movsd(XMMRegister dst, XMMRegister src);
894 void movsd(Address dst, XMMRegister src);
895 void movlpd(XMMRegister dst, Address src);
896
897 void vmovsd(XMMRegister dst, XMMRegister src, XMMRegister src2);
898
899 // New cpus require use of movaps and movapd to avoid partial register stall
900 // when moving between registers.
901 void movaps(XMMRegister dst, XMMRegister src);
902 void movapd(XMMRegister dst, XMMRegister src);
903
904 // End avoid using directly
905
906
907 // Instruction prefixes
908 void prefix(Prefix p);
909
910 public:
911
912 // Creation
913 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
914 init_attributes();
915 }
916
917 // Decoding
918 static address locate_operand(address inst, WhichOperand which);
919 static address locate_next_instruction(address inst);
920
921 // Utilities
922 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
923 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
924
925 // Generic instructions
926 // Does 32bit or 64bit as needed for the platform. In some sense these
927 // belong in macro assembler but there is no need for both varieties to exist
928
929 void init_attributes(void);
930 void clear_attributes(void) { _attributes = nullptr; }
931
932 void set_managed(void) { NOT_LP64(_is_managed = true;) }
933 void clear_managed(void) { NOT_LP64(_is_managed = false;) }
934 bool is_managed(void) {
935 NOT_LP64(return _is_managed;)
936 LP64_ONLY(return false;) }
937
938 void lea(Register dst, Address src);
939
940 void mov(Register dst, Register src);
941
942 #ifdef _LP64
943 // support caching the result of some routines
944
945 // must be called before pusha(), popa(), vzeroupper() - checked with asserts
946 static void precompute_instructions();
947
948 void pusha_uncached();
949 void popa_uncached();
950 #endif
951 void vzeroupper_uncached();
952 void decq(Register dst);
953
954 void pusha();
955 void popa();
956
957 void pushf();
958 void popf();
959
960 void push(int32_t imm32);
961
962 void push(Register src);
963
964 void pop(Register dst);
965
966 // These do register sized moves/scans
967 void rep_mov();
968 void rep_stos();
969 void rep_stosb();
970 void repne_scan();
971 #ifdef _LP64
972 void repne_scanl();
973 #endif
974
975 // Vanilla instructions in lexical order
976
977 void adcl(Address dst, int32_t imm32);
978 void adcl(Address dst, Register src);
979 void adcl(Register dst, int32_t imm32);
980 void adcl(Register dst, Address src);
981 void adcl(Register dst, Register src);
982
983 void adcq(Register dst, int32_t imm32);
984 void adcq(Register dst, Address src);
985 void adcq(Register dst, Register src);
986
987 void addb(Address dst, int imm8);
988 void addb(Address dst, Register src);
989 void addb(Register dst, int imm8);
990 void addw(Register dst, Register src);
991 void addw(Address dst, int imm16);
992 void addw(Address dst, Register src);
993
994 void addl(Address dst, int32_t imm32);
995 void addl(Address dst, Register src);
996 void addl(Register dst, int32_t imm32);
997 void addl(Register dst, Address src);
998 void addl(Register dst, Register src);
999
1000 void addq(Address dst, int32_t imm32);
1001 void addq(Address dst, Register src);
1002 void addq(Register dst, int32_t imm32);
1003 void addq(Register dst, Address src);
1004 void addq(Register dst, Register src);
1005
1006 #ifdef _LP64
1007 //Add Unsigned Integers with Carry Flag
1008 void adcxq(Register dst, Register src);
1009
1010 //Add Unsigned Integers with Overflow Flag
1011 void adoxq(Register dst, Register src);
1012 #endif
1013
1014 void addr_nop_4();
1015 void addr_nop_5();
1016 void addr_nop_7();
1017 void addr_nop_8();
1018
1019 // Add Scalar Double-Precision Floating-Point Values
1020 void addsd(XMMRegister dst, Address src);
1021 void addsd(XMMRegister dst, XMMRegister src);
1022
1023 // Add Scalar Single-Precision Floating-Point Values
1024 void addss(XMMRegister dst, Address src);
1025 void addss(XMMRegister dst, XMMRegister src);
1026
1027 // AES instructions
1028 void aesdec(XMMRegister dst, Address src);
1029 void aesdec(XMMRegister dst, XMMRegister src);
1030 void aesdeclast(XMMRegister dst, Address src);
1031 void aesdeclast(XMMRegister dst, XMMRegister src);
1032 void aesenc(XMMRegister dst, Address src);
1033 void aesenc(XMMRegister dst, XMMRegister src);
1034 void aesenclast(XMMRegister dst, Address src);
1035 void aesenclast(XMMRegister dst, XMMRegister src);
1036 // Vector AES instructions
1037 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1038 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1039 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1040 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1041
1042 void andw(Register dst, Register src);
1043 void andb(Address dst, Register src);
1044
1045 void andl(Address dst, int32_t imm32);
1046 void andl(Register dst, int32_t imm32);
1047 void andl(Register dst, Address src);
1048 void andl(Register dst, Register src);
1049 void andl(Address dst, Register src);
1050
1051 void andq(Address dst, int32_t imm32);
1052 void andq(Register dst, int32_t imm32);
1053 void andq(Register dst, Address src);
1054 void andq(Register dst, Register src);
1055 void andq(Address dst, Register src);
1056
1057 // BMI instructions
1058 void andnl(Register dst, Register src1, Register src2);
1059 void andnl(Register dst, Register src1, Address src2);
1060 void andnq(Register dst, Register src1, Register src2);
1061 void andnq(Register dst, Register src1, Address src2);
1062
1063 void blsil(Register dst, Register src);
1064 void blsil(Register dst, Address src);
1065 void blsiq(Register dst, Register src);
1066 void blsiq(Register dst, Address src);
1067
1068 void blsmskl(Register dst, Register src);
1069 void blsmskl(Register dst, Address src);
1070 void blsmskq(Register dst, Register src);
1071 void blsmskq(Register dst, Address src);
1072
1073 void blsrl(Register dst, Register src);
1074 void blsrl(Register dst, Address src);
1075 void blsrq(Register dst, Register src);
1076 void blsrq(Register dst, Address src);
1077
1078 void bsfl(Register dst, Register src);
1079 void bsrl(Register dst, Register src);
1080
1081 #ifdef _LP64
1082 void bsfq(Register dst, Register src);
1083 void bsrq(Register dst, Register src);
1084 #endif
1085
1086 void bswapl(Register reg);
1087
1088 void bswapq(Register reg);
1089
1090 void call(Label& L, relocInfo::relocType rtype);
1091 void call(Register reg); // push pc; pc <- reg
1092 void call(Address adr); // push pc; pc <- adr
1093
1094 void cdql();
1095
1096 void cdqq();
1097
1098 void cld();
1099
1100 void clflush(Address adr);
1101 void clflushopt(Address adr);
1102 void clwb(Address adr);
1103
1104 void cmovl(Condition cc, Register dst, Register src);
1105 void cmovl(Condition cc, Register dst, Address src);
1106
1107 void cmovq(Condition cc, Register dst, Register src);
1108 void cmovq(Condition cc, Register dst, Address src);
1109
1110
1111 void cmpb(Address dst, int imm8);
1112
1113 void cmpl(Address dst, int32_t imm32);
1114 void cmpl(Register dst, int32_t imm32);
1115 void cmpl(Register dst, Register src);
1116 void cmpl(Register dst, Address src);
1117 void cmpl_imm32(Address dst, int32_t imm32);
1118
1119 void cmpq(Address dst, int32_t imm32);
1120 void cmpq(Address dst, Register src);
1121 void cmpq(Register dst, int32_t imm32);
1122 void cmpq(Register dst, Register src);
1123 void cmpq(Register dst, Address src);
1124
1125 void cmpw(Address dst, int imm16);
1126
1127 void cmpxchg8 (Address adr);
1128
1129 void cmpxchgb(Register reg, Address adr);
1130 void cmpxchgl(Register reg, Address adr);
1131
1132 void cmpxchgq(Register reg, Address adr);
1133 void cmpxchgw(Register reg, Address adr);
1134
1135 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1136 void comisd(XMMRegister dst, Address src);
1137 void comisd(XMMRegister dst, XMMRegister src);
1138
1139 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1140 void comiss(XMMRegister dst, Address src);
1141 void comiss(XMMRegister dst, XMMRegister src);
1142
1143 // Identify processor type and features
1144 void cpuid();
1145
1146 // CRC32C
1147 void crc32(Register crc, Register v, int8_t sizeInBytes);
1148 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1149
1150 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1151 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1152 void cvtsd2ss(XMMRegister dst, Address src);
1153
1154 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1155 void cvtsi2sdl(XMMRegister dst, Register src);
1156 void cvtsi2sdl(XMMRegister dst, Address src);
1157 void cvtsi2sdq(XMMRegister dst, Register src);
1158 void cvtsi2sdq(XMMRegister dst, Address src);
1159
1160 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1161 void cvtsi2ssl(XMMRegister dst, Register src);
1162 void cvtsi2ssl(XMMRegister dst, Address src);
1163 void cvtsi2ssq(XMMRegister dst, Register src);
1164 void cvtsi2ssq(XMMRegister dst, Address src);
1165
1166 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1167 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1168 void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1169
1170 // Convert Halffloat to Single Precision Floating-Point value
1171 void vcvtps2ph(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1172 void vcvtph2ps(XMMRegister dst, XMMRegister src, int vector_len);
1173 void evcvtps2ph(Address dst, KRegister mask, XMMRegister src, int imm8, int vector_len);
1174 void vcvtps2ph(Address dst, XMMRegister src, int imm8, int vector_len);
1175 void vcvtph2ps(XMMRegister dst, Address src, int vector_len);
1176
1177 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1178 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1179 void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1180
1181 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1182 void cvtss2sd(XMMRegister dst, XMMRegister src);
1183 void cvtss2sd(XMMRegister dst, Address src);
1184
1185 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1186 void cvtsd2siq(Register dst, XMMRegister src);
1187 void cvttsd2sil(Register dst, Address src);
1188 void cvttsd2sil(Register dst, XMMRegister src);
1189 void cvttsd2siq(Register dst, Address src);
1190 void cvttsd2siq(Register dst, XMMRegister src);
1191
1192 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1193 void cvttss2sil(Register dst, XMMRegister src);
1194 void cvttss2siq(Register dst, XMMRegister src);
1195 void cvtss2sil(Register dst, XMMRegister src);
1196
1197 // Convert vector double to int
1198 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1199
1200 // Convert vector float and double
1201 void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1202 void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1203
1204 // Convert vector float to int/long
1205 void vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1206 void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len);
1207 void evcvttps2qq(XMMRegister dst, XMMRegister src, int vector_len);
1208
1209 // Convert vector long to vector FP
1210 void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1211 void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1212
1213 // Convert vector double to long
1214 void evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1215 void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len);
1216
1217 // Convert vector double to int
1218 void vcvttpd2dq(XMMRegister dst, XMMRegister src, int vector_len);
1219
1220 // Evex casts with truncation
1221 void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
1222 void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
1223 void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
1224 void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
1225 void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
1226 void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);
1227
1228 // Evex casts with signed saturation
1229 void evpmovsqd(XMMRegister dst, XMMRegister src, int vector_len);
1230
1231 //Abs of packed Integer values
1232 void pabsb(XMMRegister dst, XMMRegister src);
1233 void pabsw(XMMRegister dst, XMMRegister src);
1234 void pabsd(XMMRegister dst, XMMRegister src);
1235 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1236 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1237 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1238 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1239
1240 // Divide Scalar Double-Precision Floating-Point Values
1241 void divsd(XMMRegister dst, Address src);
1242 void divsd(XMMRegister dst, XMMRegister src);
1243
1244 // Divide Scalar Single-Precision Floating-Point Values
1245 void divss(XMMRegister dst, Address src);
1246 void divss(XMMRegister dst, XMMRegister src);
1247
1248
1249 void fnstsw_ax();
1250 void fprem();
1251 void fld_d(Address adr);
1252 void fstp_d(Address adr);
1253 void fstp_d(int index);
1254
1255 private:
1256
1257 void emit_farith(int b1, int b2, int i);
1258
1259 public:
1260 #ifndef _LP64
1261 void emms();
1262
1263 void fabs();
1264
1265 void fadd(int i);
1266
1267 void fadd_d(Address src);
1268 void fadd_s(Address src);
1269
1270 // "Alternate" versions of x87 instructions place result down in FPU
1271 // stack instead of on TOS
1272
1273 void fadda(int i); // "alternate" fadd
1274 void faddp(int i = 1);
1275
1276 void fchs();
1277
1278 void fcom(int i);
1279
1280 void fcomp(int i = 1);
1281 void fcomp_d(Address src);
1282 void fcomp_s(Address src);
1283
1284 void fcompp();
1285
1286 void fcos();
1287
1288 void fdecstp();
1289
1290 void fdiv(int i);
1291 void fdiv_d(Address src);
1292 void fdivr_s(Address src);
1293 void fdiva(int i); // "alternate" fdiv
1294 void fdivp(int i = 1);
1295
1296 void fdivr(int i);
1297 void fdivr_d(Address src);
1298 void fdiv_s(Address src);
1299
1300 void fdivra(int i); // "alternate" reversed fdiv
1301
1302 void fdivrp(int i = 1);
1303
1304 void ffree(int i = 0);
1305
1306 void fild_d(Address adr);
1307 void fild_s(Address adr);
1308
1309 void fincstp();
1310
1311 void finit();
1312
1313 void fist_s (Address adr);
1314 void fistp_d(Address adr);
1315 void fistp_s(Address adr);
1316
1317 void fld1();
1318
1319 void fld_s(Address adr);
1320 void fld_s(int index);
1321
1322 void fldcw(Address src);
1323
1324 void fldenv(Address src);
1325
1326 void fldlg2();
1327
1328 void fldln2();
1329
1330 void fldz();
1331
1332 void flog();
1333 void flog10();
1334
1335 void fmul(int i);
1336
1337 void fmul_d(Address src);
1338 void fmul_s(Address src);
1339
1340 void fmula(int i); // "alternate" fmul
1341
1342 void fmulp(int i = 1);
1343
1344 void fnsave(Address dst);
1345
1346 void fnstcw(Address src);
1347 void fprem1();
1348
1349 void frstor(Address src);
1350
1351 void fsin();
1352
1353 void fsqrt();
1354
1355 void fst_d(Address adr);
1356 void fst_s(Address adr);
1357
1358 void fstp_s(Address adr);
1359
1360 void fsub(int i);
1361 void fsub_d(Address src);
1362 void fsub_s(Address src);
1363
1364 void fsuba(int i); // "alternate" fsub
1365
1366 void fsubp(int i = 1);
1367
1368 void fsubr(int i);
1369 void fsubr_d(Address src);
1370 void fsubr_s(Address src);
1371
1372 void fsubra(int i); // "alternate" reversed fsub
1373
1374 void fsubrp(int i = 1);
1375
1376 void ftan();
1377
1378 void ftst();
1379
1380 void fucomi(int i = 1);
1381 void fucomip(int i = 1);
1382
1383 void fwait();
1384
1385 void fxch(int i = 1);
1386
1387 void fyl2x();
1388 void frndint();
1389 void f2xm1();
1390 void fldl2e();
1391 #endif // !_LP64
1392
1393 // operands that only take the original 32bit registers
1394 void emit_operand32(Register reg, Address adr, int post_addr_length);
1395
1396 void fld_x(Address adr); // extended-precision (80-bit) format
1397 void fstp_x(Address adr); // extended-precision (80-bit) format
1398 void fxrstor(Address src);
1399 void xrstor(Address src);
1400
1401 void fxsave(Address dst);
1402 void xsave(Address dst);
1403
1404 void hlt();
1405
1406 void idivl(Register src);
1407 void divl(Register src); // Unsigned division
1408
1409 #ifdef _LP64
1410 void idivq(Register src);
1411 void divq(Register src); // Unsigned division
1412 #endif
1413
1414 void imull(Register src);
1415 void imull(Register dst, Register src);
1416 void imull(Register dst, Register src, int value);
1417 void imull(Register dst, Address src, int value);
1418 void imull(Register dst, Address src);
1419
1420 #ifdef _LP64
1421 void imulq(Register dst, Register src);
1422 void imulq(Register dst, Register src, int value);
1423 void imulq(Register dst, Address src, int value);
1424 void imulq(Register dst, Address src);
1425 void imulq(Register dst);
1426 #endif
1427
1428 // jcc is the generic conditional branch generator to run-
1429 // time routines, jcc is used for branches to labels. jcc
1430 // takes a branch opcode (cc) and a label (L) and generates
1431 // either a backward branch or a forward branch and links it
1432 // to the label fixup chain. Usage:
1433 //
1434 // Label L; // unbound label
1435 // jcc(cc, L); // forward branch to unbound label
1436 // bind(L); // bind label to the current pc
1437 // jcc(cc, L); // backward branch to bound label
1438 // bind(L); // illegal: a label may be bound only once
1439 //
1440 // Note: The same Label can be used for forward and backward branches
1441 // but it may be bound only once.
1442
1443 void jcc(Condition cc, Label& L, bool maybe_short = true);
1444
1445 // Conditional jump to a 8-bit offset to L.
1446 // WARNING: be very careful using this for forward jumps. If the label is
1447 // not bound within an 8-bit offset of this instruction, a run-time error
1448 // will occur.
1449
1450 // Use macro to record file and line number.
1451 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1452
1453 void jccb_0(Condition cc, Label& L, const char* file, int line);
1454
1455 void jmp(Address entry); // pc <- entry
1456
1457 // Label operations & relative jumps (PPUM Appendix D)
1458 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1459
1460 void jmp(Register entry); // pc <- entry
1461
1462 // Unconditional 8-bit offset jump to L.
1463 // WARNING: be very careful using this for forward jumps. If the label is
1464 // not bound within an 8-bit offset of this instruction, a run-time error
1465 // will occur.
1466
1467 // Use macro to record file and line number.
1468 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1469
1470 void jmpb_0(Label& L, const char* file, int line);
1471
1472 void ldmxcsr( Address src );
1473
1474 void leal(Register dst, Address src);
1475
1476 void leaq(Register dst, Address src);
1477
1478 void lfence();
1479
1480 void lock();
1481 void size_prefix();
1482
1483 void lzcntl(Register dst, Register src);
1484 void lzcntl(Register dst, Address src);
1485
1486 #ifdef _LP64
1487 void lzcntq(Register dst, Register src);
1488 void lzcntq(Register dst, Address src);
1489 #endif
1490
1491 enum Membar_mask_bits {
1492 StoreStore = 1 << 3,
1493 LoadStore = 1 << 2,
1494 StoreLoad = 1 << 1,
1495 LoadLoad = 1 << 0
1496 };
1497
1498 // Serializes memory and blows flags
1499 void membar(Membar_mask_bits order_constraint);
1500
1501 void mfence();
1502 void sfence();
1503
1504 // Moves
1505
1506 void mov64(Register dst, int64_t imm64);
1507 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1508
1509 void movb(Address dst, Register src);
1510 void movb(Address dst, int imm8);
1511 void movb(Register dst, Address src);
1512
1513 void movddup(XMMRegister dst, XMMRegister src);
1514 void movddup(XMMRegister dst, Address src);
1515 void vmovddup(XMMRegister dst, Address src, int vector_len);
1516
1517 void kandbl(KRegister dst, KRegister src1, KRegister src2);
1518 void kandwl(KRegister dst, KRegister src1, KRegister src2);
1519 void kanddl(KRegister dst, KRegister src1, KRegister src2);
1520 void kandql(KRegister dst, KRegister src1, KRegister src2);
1521
1522 void korbl(KRegister dst, KRegister src1, KRegister src2);
1523 void korwl(KRegister dst, KRegister src1, KRegister src2);
1524 void kordl(KRegister dst, KRegister src1, KRegister src2);
1525 void korql(KRegister dst, KRegister src1, KRegister src2);
1526
1527 void kxorbl(KRegister dst, KRegister src1, KRegister src2);
1528 void kxorwl(KRegister dst, KRegister src1, KRegister src2);
1529 void kxordl(KRegister dst, KRegister src1, KRegister src2);
1530 void kxorql(KRegister dst, KRegister src1, KRegister src2);
1531 void kmovbl(KRegister dst, Register src);
1532 void kmovbl(Register dst, KRegister src);
1533 void kmovbl(KRegister dst, KRegister src);
1534 void kmovwl(KRegister dst, Register src);
1535 void kmovwl(KRegister dst, Address src);
1536 void kmovwl(Register dst, KRegister src);
1537 void kmovwl(Address dst, KRegister src);
1538 void kmovwl(KRegister dst, KRegister src);
1539 void kmovdl(KRegister dst, Register src);
1540 void kmovdl(Register dst, KRegister src);
1541 void kmovql(KRegister dst, KRegister src);
1542 void kmovql(Address dst, KRegister src);
1543 void kmovql(KRegister dst, Address src);
1544 void kmovql(KRegister dst, Register src);
1545 void kmovql(Register dst, KRegister src);
1546
1547 void knotbl(KRegister dst, KRegister src);
1548 void knotwl(KRegister dst, KRegister src);
1549 void knotdl(KRegister dst, KRegister src);
1550 void knotql(KRegister dst, KRegister src);
1551
1552 void kortestbl(KRegister dst, KRegister src);
1553 void kortestwl(KRegister dst, KRegister src);
1554 void kortestdl(KRegister dst, KRegister src);
1555 void kortestql(KRegister dst, KRegister src);
1556
1557 void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
1558 void kshiftlbl(KRegister dst, KRegister src, int imm8);
1559 void kshiftlql(KRegister dst, KRegister src, int imm8);
1560 void kshiftrbl(KRegister dst, KRegister src, int imm8);
1561 void kshiftrwl(KRegister dst, KRegister src, int imm8);
1562 void kshiftrdl(KRegister dst, KRegister src, int imm8);
1563 void kshiftrql(KRegister dst, KRegister src, int imm8);
1564 void ktestq(KRegister src1, KRegister src2);
1565 void ktestd(KRegister src1, KRegister src2);
1566 void kunpckdql(KRegister dst, KRegister src1, KRegister src2);
1567
1568
1569 void ktestql(KRegister dst, KRegister src);
1570 void ktestdl(KRegister dst, KRegister src);
1571 void ktestwl(KRegister dst, KRegister src);
1572 void ktestbl(KRegister dst, KRegister src);
1573
1574 void movdl(XMMRegister dst, Register src);
1575 void movdl(Register dst, XMMRegister src);
1576 void movdl(XMMRegister dst, Address src);
1577 void movdl(Address dst, XMMRegister src);
1578
1579 // Move Double Quadword
1580 void movdq(XMMRegister dst, Register src);
1581 void movdq(Register dst, XMMRegister src);
1582
1583 // Move Aligned Double Quadword
1584 void movdqa(XMMRegister dst, XMMRegister src);
1585 void movdqa(XMMRegister dst, Address src);
1586
1587 // Move Unaligned Double Quadword
1588 void movdqu(Address dst, XMMRegister src);
1589 void movdqu(XMMRegister dst, Address src);
1590 void movdqu(XMMRegister dst, XMMRegister src);
1591
1592 // Move Unaligned 256bit Vector
1593 void vmovdqu(Address dst, XMMRegister src);
1594 void vmovdqu(XMMRegister dst, Address src);
1595 void vmovdqu(XMMRegister dst, XMMRegister src);
1596
1597 // Move Unaligned 512bit Vector
1598 void evmovdqub(XMMRegister dst, XMMRegister src, int vector_len);
1599 void evmovdqub(XMMRegister dst, Address src, int vector_len);
1600 void evmovdqub(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1601 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1602 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1603
1604 void evmovdquw(XMMRegister dst, Address src, int vector_len);
1605 void evmovdquw(Address dst, XMMRegister src, int vector_len);
1606 void evmovdquw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1607 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1608 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1609
1610 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1611 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1612 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1613
1614 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1615 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1616 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1617
1618 void evmovntdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1619 void evmovntdquq(Address dst, XMMRegister src, int vector_len);
1620
1621 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1622 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1623 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1624
1625 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1626 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1627 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1628
1629 // Move lower 64bit to high 64bit in 128bit register
1630 void movlhps(XMMRegister dst, XMMRegister src);
1631
1632 void movl(Register dst, int32_t imm32);
1633 void movl(Address dst, int32_t imm32);
1634 void movl(Register dst, Register src);
1635 void movl(Register dst, Address src);
1636 void movl(Address dst, Register src);
1637
1638 #ifdef _LP64
1639 void movq(Register dst, Register src);
1640 void movq(Register dst, Address src);
1641 void movq(Address dst, Register src);
1642 void movq(Address dst, int32_t imm32);
1643 void movq(Register dst, int32_t imm32);
1644 #endif
1645
1646 // Move Quadword
1647 void movq(Address dst, XMMRegister src);
1648 void movq(XMMRegister dst, Address src);
1649 void movq(XMMRegister dst, XMMRegister src);
1650 void movq(Register dst, XMMRegister src);
1651 void movq(XMMRegister dst, Register src);
1652
1653 void movsbl(Register dst, Address src);
1654 void movsbl(Register dst, Register src);
1655
1656 #ifdef _LP64
1657 void movsbq(Register dst, Address src);
1658 void movsbq(Register dst, Register src);
1659
1660 // Move signed 32bit immediate to 64bit extending sign
1661 void movslq(Address dst, int32_t imm64);
1662
1663 void movslq(Register dst, Address src);
1664 void movslq(Register dst, Register src);
1665 #endif
1666
1667 void movswl(Register dst, Address src);
1668 void movswl(Register dst, Register src);
1669
1670 #ifdef _LP64
1671 void movswq(Register dst, Address src);
1672 void movswq(Register dst, Register src);
1673 #endif
1674
1675 void movups(XMMRegister dst, Address src);
1676 void vmovups(XMMRegister dst, Address src, int vector_len);
1677 void movups(Address dst, XMMRegister src);
1678 void vmovups(Address dst, XMMRegister src, int vector_len);
1679
1680 void movw(Address dst, int imm16);
1681 void movw(Register dst, Address src);
1682 void movw(Address dst, Register src);
1683
1684 void movzbl(Register dst, Address src);
1685 void movzbl(Register dst, Register src);
1686
1687 #ifdef _LP64
1688 void movzbq(Register dst, Address src);
1689 void movzbq(Register dst, Register src);
1690 #endif
1691
1692 void movzwl(Register dst, Address src);
1693 void movzwl(Register dst, Register src);
1694
1695 #ifdef _LP64
1696 void movzwq(Register dst, Address src);
1697 void movzwq(Register dst, Register src);
1698 #endif
1699
1700 // Unsigned multiply with RAX destination register
1701 void mull(Address src);
1702 void mull(Register src);
1703
1704 #ifdef _LP64
1705 void mulq(Address src);
1706 void mulq(Register src);
1707 void mulxq(Register dst1, Register dst2, Register src);
1708 #endif
1709
1710 // Multiply Scalar Double-Precision Floating-Point Values
1711 void mulsd(XMMRegister dst, Address src);
1712 void mulsd(XMMRegister dst, XMMRegister src);
1713
1714 // Multiply Scalar Single-Precision Floating-Point Values
1715 void mulss(XMMRegister dst, Address src);
1716 void mulss(XMMRegister dst, XMMRegister src);
1717
1718 void negl(Register dst);
1719 void negl(Address dst);
1720
1721 #ifdef _LP64
1722 void negq(Register dst);
1723 void negq(Address dst);
1724 #endif
1725
1726 void nop(int i = 1);
1727
1728 void notl(Register dst);
1729
1730 #ifdef _LP64
1731 void notq(Register dst);
1732
1733 void btsq(Address dst, int imm8);
1734 void btrq(Address dst, int imm8);
1735 #endif
1736
1737 void orw(Register dst, Register src);
1738
1739 void orl(Address dst, int32_t imm32);
1740 void orl(Register dst, int32_t imm32);
1741 void orl(Register dst, Address src);
1742 void orl(Register dst, Register src);
1743 void orl(Address dst, Register src);
1744
1745 void orb(Address dst, int imm8);
1746 void orb(Address dst, Register src);
1747
1748 void orq(Address dst, int32_t imm32);
1749 void orq(Address dst, Register src);
1750 void orq(Register dst, int32_t imm32);
1751 void orq_imm32(Register dst, int32_t imm32);
1752 void orq(Register dst, Address src);
1753 void orq(Register dst, Register src);
1754
1755 // Pack with signed saturation
1756 void packsswb(XMMRegister dst, XMMRegister src);
1757 void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1758 void packssdw(XMMRegister dst, XMMRegister src);
1759 void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1760
1761 // Pack with unsigned saturation
1762 void packuswb(XMMRegister dst, XMMRegister src);
1763 void packuswb(XMMRegister dst, Address src);
1764 void packusdw(XMMRegister dst, XMMRegister src);
1765 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1766 void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1767
1768 // Permutations
1769 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1770 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1771 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1772 void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1773 void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1774 void vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1775 void vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1776 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1777 void vpermps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1778 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1779 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1780 void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1781 void vpermilps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1782 void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1783 void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1784 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1785 void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1786 void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len);
1787
1788 void pause();
1789
1790 // Undefined Instruction
1791 void ud2();
1792
1793 // SSE4.2 string instructions
1794 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1795 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1796
1797 void pcmpeqb(XMMRegister dst, XMMRegister src);
1798 void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1799
1800 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1801 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1802 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1803 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1804
1805 void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1806 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1807 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1808
1809 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1810 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1811
1812 void evpcmpuq(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1813
1814 void pcmpeqw(XMMRegister dst, XMMRegister src);
1815 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1816 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1817 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1818
1819 void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1820
1821 void pcmpeqd(XMMRegister dst, XMMRegister src);
1822 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1823 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1824 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1825
1826 void pcmpeqq(XMMRegister dst, XMMRegister src);
1827 void evpcmpeqq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1828 void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1829 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1830 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1831 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1832
1833 void pcmpgtq(XMMRegister dst, XMMRegister src);
1834 void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1835
1836 void pmovmskb(Register dst, XMMRegister src);
1837 void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
1838 void vmovmskps(Register dst, XMMRegister src, int vec_enc);
1839 void vmovmskpd(Register dst, XMMRegister src, int vec_enc);
1840 void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1841 void vpmaskmovq(XMMRegister dst, XMMRegister mask, Address src, int vector_len);
1842
1843
1844 void vmaskmovps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1845 void vmaskmovpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
1846 void vmaskmovps(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1847 void vmaskmovpd(Address dst, XMMRegister src, XMMRegister mask, int vector_len);
1848
1849 // SSE 4.1 extract
1850 void pextrd(Register dst, XMMRegister src, int imm8);
1851 void pextrq(Register dst, XMMRegister src, int imm8);
1852 void pextrd(Address dst, XMMRegister src, int imm8);
1853 void pextrq(Address dst, XMMRegister src, int imm8);
1854 void pextrb(Register dst, XMMRegister src, int imm8);
1855 void pextrb(Address dst, XMMRegister src, int imm8);
1856 // SSE 2 extract
1857 void pextrw(Register dst, XMMRegister src, int imm8);
1858 void pextrw(Address dst, XMMRegister src, int imm8);
1859
1860 // SSE 4.1 insert
1861 void pinsrd(XMMRegister dst, Register src, int imm8);
1862 void pinsrq(XMMRegister dst, Register src, int imm8);
1863 void pinsrb(XMMRegister dst, Register src, int imm8);
1864 void pinsrd(XMMRegister dst, Address src, int imm8);
1865 void pinsrq(XMMRegister dst, Address src, int imm8);
1866 void pinsrb(XMMRegister dst, Address src, int imm8);
1867 void insertps(XMMRegister dst, XMMRegister src, int imm8);
1868 // SSE 2 insert
1869 void pinsrw(XMMRegister dst, Register src, int imm8);
1870 void pinsrw(XMMRegister dst, Address src, int imm8);
1871
1872 // AVX insert
1873 void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1874 void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1875 void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1876 void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1877 void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1878
1879 // Zero extend moves
1880 void pmovzxbw(XMMRegister dst, XMMRegister src);
1881 void pmovzxbw(XMMRegister dst, Address src);
1882 void pmovzxbd(XMMRegister dst, XMMRegister src);
1883 void vpmovzxbw(XMMRegister dst, Address src, int vector_len);
1884 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1885 void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
1886 void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
1887 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1888 void vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len);
1889 void pmovzxdq(XMMRegister dst, XMMRegister src);
1890 void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
1891 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1892 void evpmovzxbd(XMMRegister dst, KRegister mask, Address src, int vector_len);
1893 void evpmovzxbd(XMMRegister dst, Address src, int vector_len);
1894
1895 // Sign extend moves
1896 void pmovsxbd(XMMRegister dst, XMMRegister src);
1897 void pmovsxbq(XMMRegister dst, XMMRegister src);
1898 void pmovsxbw(XMMRegister dst, XMMRegister src);
1899 void pmovsxwd(XMMRegister dst, XMMRegister src);
1900 void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
1901 void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
1902 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1903 void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
1904 void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
1905 void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);
1906
1907 void evpmovwb(Address dst, XMMRegister src, int vector_len);
1908 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1909 void evpmovdb(Address dst, XMMRegister src, int vector_len);
1910
1911 // Multiply add
1912 void pmaddwd(XMMRegister dst, XMMRegister src);
1913 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1914 void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1915 void evpmadd52luq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1916 void evpmadd52luq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
1917 void evpmadd52huq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1918 void evpmadd52huq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
1919
1920 // Multiply add accumulate
1921 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1922
1923 #ifndef _LP64 // no 32bit push/pop on amd64
1924 void popl(Address dst);
1925 #endif
1926
1927 #ifdef _LP64
1928 void popq(Address dst);
1929 void popq(Register dst);
1930 #endif
1931
1932 void popcntl(Register dst, Address src);
1933 void popcntl(Register dst, Register src);
1934
1935 void evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1936 void evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1937 void evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1938 void evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1939
1940 #ifdef _LP64
1941 void popcntq(Register dst, Address src);
1942 void popcntq(Register dst, Register src);
1943 #endif
1944
1945 // Prefetches (SSE, SSE2, 3DNOW only)
1946
1947 void prefetchnta(Address src);
1948 void prefetchr(Address src);
1949 void prefetcht0(Address src);
1950 void prefetcht1(Address src);
1951 void prefetcht2(Address src);
1952 void prefetchw(Address src);
1953
1954 // Shuffle Bytes
1955 void pshufb(XMMRegister dst, XMMRegister src);
1956 void pshufb(XMMRegister dst, Address src);
1957 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1958 void vpshufb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1959 void evpshufb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
1960
1961
1962 // Shuffle Packed Doublewords
1963 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1964 void pshufd(XMMRegister dst, Address src, int mode);
1965 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1966
1967 // Shuffle Packed High/Low Words
1968 void pshufhw(XMMRegister dst, XMMRegister src, int mode);
1969 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1970 void pshuflw(XMMRegister dst, Address src, int mode);
1971 void vpshufhw(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1972 void vpshuflw(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1973
1974 //shuffle floats and doubles
1975 void shufps(XMMRegister, XMMRegister, int);
1976 void shufpd(XMMRegister, XMMRegister, int);
1977 void vshufps(XMMRegister, XMMRegister, XMMRegister, int, int);
1978 void vshufpd(XMMRegister, XMMRegister, XMMRegister, int, int);
1979
1980 // Shuffle packed values at 128 bit granularity
1981 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1982
1983 // Shift Right by bytes Logical DoubleQuadword Immediate
1984 void psrldq(XMMRegister dst, int shift);
1985 // Shift Left by bytes Logical DoubleQuadword Immediate
1986 void pslldq(XMMRegister dst, int shift);
1987
1988 // Logical Compare 128bit
1989 void ptest(XMMRegister dst, XMMRegister src);
1990 void ptest(XMMRegister dst, Address src);
1991 // Logical Compare 256bit
1992 void vptest(XMMRegister dst, XMMRegister src);
1993 void vptest(XMMRegister dst, Address src);
1994
1995 void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1996 void evptestmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1997 void evptestnmd(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1998
1999 // Vector compare
2000 void vptest(XMMRegister dst, XMMRegister src, int vector_len);
2001 void vtestps(XMMRegister dst, XMMRegister src, int vector_len);
2002
2003 // Interleave Low Bytes
2004 void punpcklbw(XMMRegister dst, XMMRegister src);
2005 void punpcklbw(XMMRegister dst, Address src);
2006
2007 // Interleave Low Doublewords
2008 void punpckldq(XMMRegister dst, XMMRegister src);
2009 void punpckldq(XMMRegister dst, Address src);
2010 void vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2011
2012 // Interleave High Word
2013 void vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2014
2015 // Interleave Low Word
2016 void vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2017
2018 // Interleave High Doublewords
2019 void vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2020
2021 // Interleave Low Quadwords
2022 void punpcklqdq(XMMRegister dst, XMMRegister src);
2023
2024 void evpunpcklqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2025 void evpunpcklqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
2026 void evpunpckhqdq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2027 void evpunpckhqdq(XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vector_len);
2028
2029 // Vector sum of absolute difference.
2030 void vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2031
2032 #ifndef _LP64 // no 32bit push/pop on amd64
2033 void pushl(Address src);
2034 #endif
2035
2036 void pushq(Address src);
2037
2038 void rcll(Register dst, int imm8);
2039
2040 void rclq(Register dst, int imm8);
2041
2042 void rcrq(Register dst, int imm8);
2043
2044 void rcpps(XMMRegister dst, XMMRegister src);
2045
2046 void rcpss(XMMRegister dst, XMMRegister src);
2047
2048 void rdtsc();
2049 void rdtscp();
2050
2051 void ret(int imm16);
2052
2053 void roll(Register dst);
2054
2055 void roll(Register dst, int imm8);
2056
2057 void rorl(Register dst);
2058
2059 void rorl(Register dst, int imm8);
2060
2061 #ifdef _LP64
2062 void rolq(Register dst);
2063 void rolq(Register dst, int imm8);
2064 void rorq(Register dst);
2065 void rorq(Register dst, int imm8);
2066 void rorxl(Register dst, Register src, int imm8);
2067 void rorxl(Register dst, Address src, int imm8);
2068 void rorxq(Register dst, Register src, int imm8);
2069 void rorxq(Register dst, Address src, int imm8);
2070 #endif
2071
2072 void sahf();
2073
2074 void sall(Register dst, int imm8);
2075 void sall(Register dst);
2076 void sall(Address dst, int imm8);
2077 void sall(Address dst);
2078
2079 void sarl(Address dst, int imm8);
2080 void sarl(Address dst);
2081 void sarl(Register dst, int imm8);
2082 void sarl(Register dst);
2083
2084 #ifdef _LP64
2085 void salq(Register dst, int imm8);
2086 void salq(Register dst);
2087 void salq(Address dst, int imm8);
2088 void salq(Address dst);
2089
2090 void sarq(Address dst, int imm8);
2091 void sarq(Address dst);
2092 void sarq(Register dst, int imm8);
2093 void sarq(Register dst);
2094 #endif
2095
2096 void sbbl(Address dst, int32_t imm32);
2097 void sbbl(Register dst, int32_t imm32);
2098 void sbbl(Register dst, Address src);
2099 void sbbl(Register dst, Register src);
2100
2101 void sbbq(Address dst, int32_t imm32);
2102 void sbbq(Register dst, int32_t imm32);
2103 void sbbq(Register dst, Address src);
2104 void sbbq(Register dst, Register src);
2105
2106 void setb(Condition cc, Register dst);
2107
2108 void palignr(XMMRegister dst, XMMRegister src, int imm8);
2109 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2110 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2111
2112 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
2113 void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2114
2115 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
2116 void sha1nexte(XMMRegister dst, XMMRegister src);
2117 void sha1msg1(XMMRegister dst, XMMRegister src);
2118 void sha1msg2(XMMRegister dst, XMMRegister src);
2119 // xmm0 is implicit additional source to the following instruction.
2120 void sha256rnds2(XMMRegister dst, XMMRegister src);
2121 void sha256msg1(XMMRegister dst, XMMRegister src);
2122 void sha256msg2(XMMRegister dst, XMMRegister src);
2123
2124 void shldl(Register dst, Register src);
2125 void shldl(Register dst, Register src, int8_t imm8);
2126 void shrdl(Register dst, Register src);
2127 void shrdl(Register dst, Register src, int8_t imm8);
2128 #ifdef _LP64
2129 void shldq(Register dst, Register src, int8_t imm8);
2130 void shrdq(Register dst, Register src, int8_t imm8);
2131 #endif
2132
2133 void shll(Register dst, int imm8);
2134 void shll(Register dst);
2135
2136 void shlq(Register dst, int imm8);
2137 void shlq(Register dst);
2138
2139 void shrl(Register dst, int imm8);
2140 void shrl(Register dst);
2141 void shrl(Address dst);
2142 void shrl(Address dst, int imm8);
2143
2144 void shrq(Register dst, int imm8);
2145 void shrq(Register dst);
2146 void shrq(Address dst);
2147 void shrq(Address dst, int imm8);
2148
2149 void smovl(); // QQQ generic?
2150
2151 // Compute Square Root of Scalar Double-Precision Floating-Point Value
2152 void sqrtsd(XMMRegister dst, Address src);
2153 void sqrtsd(XMMRegister dst, XMMRegister src);
2154
2155 void roundsd(XMMRegister dst, Address src, int32_t rmode);
2156 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
2157
2158 // Compute Square Root of Scalar Single-Precision Floating-Point Value
2159 void sqrtss(XMMRegister dst, Address src);
2160 void sqrtss(XMMRegister dst, XMMRegister src);
2161
2162 void std();
2163
2164 void stmxcsr( Address dst );
2165
2166 void subl(Address dst, int32_t imm32);
2167 void subl(Address dst, Register src);
2168 void subl(Register dst, int32_t imm32);
2169 void subl(Register dst, Address src);
2170 void subl(Register dst, Register src);
2171
2172 void subq(Address dst, int32_t imm32);
2173 void subq(Address dst, Register src);
2174 void subq(Register dst, int32_t imm32);
2175 void subq(Register dst, Address src);
2176 void subq(Register dst, Register src);
2177
2178 // Force generation of a 4 byte immediate value even if it fits into 8bit
2179 void subl_imm32(Register dst, int32_t imm32);
2180 void subq_imm32(Register dst, int32_t imm32);
2181
2182 // Subtract Scalar Double-Precision Floating-Point Values
2183 void subsd(XMMRegister dst, Address src);
2184 void subsd(XMMRegister dst, XMMRegister src);
2185
2186 // Subtract Scalar Single-Precision Floating-Point Values
2187 void subss(XMMRegister dst, Address src);
2188 void subss(XMMRegister dst, XMMRegister src);
2189
2190 void testb(Address dst, int imm8);
2191 void testb(Register dst, int imm8, bool use_ral = true);
2192
2193 void testl(Address dst, int32_t imm32);
2194 void testl(Register dst, int32_t imm32);
2195 void testl(Register dst, Register src);
2196 void testl(Register dst, Address src);
2197
2198 void testq(Address dst, int32_t imm32);
2199 void testq(Register dst, int32_t imm32);
2200 void testq(Register dst, Register src);
2201 void testq(Register dst, Address src);
2202
2203 // BMI - count trailing zeros
2204 void tzcntl(Register dst, Register src);
2205 void tzcntl(Register dst, Address src);
2206 void tzcntq(Register dst, Register src);
2207 void tzcntq(Register dst, Address src);
2208
2209 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
2210 void ucomisd(XMMRegister dst, Address src);
2211 void ucomisd(XMMRegister dst, XMMRegister src);
2212
2213 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
2214 void ucomiss(XMMRegister dst, Address src);
2215 void ucomiss(XMMRegister dst, XMMRegister src);
2216
2217 void xabort(int8_t imm8);
2218
2219 void xaddb(Address dst, Register src);
2220 void xaddw(Address dst, Register src);
2221 void xaddl(Address dst, Register src);
2222 void xaddq(Address dst, Register src);
2223
2224 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
2225
2226 void xchgb(Register reg, Address adr);
2227 void xchgw(Register reg, Address adr);
2228 void xchgl(Register reg, Address adr);
2229 void xchgl(Register dst, Register src);
2230
2231 void xchgq(Register reg, Address adr);
2232 void xchgq(Register dst, Register src);
2233
2234 void xend();
2235
2236 // Get Value of Extended Control Register
2237 void xgetbv();
2238
2239 void xorl(Register dst, int32_t imm32);
2240 void xorl(Address dst, int32_t imm32);
2241 void xorl(Register dst, Address src);
2242 void xorl(Register dst, Register src);
2243 void xorl(Address dst, Register src);
2244
2245 void xorb(Address dst, Register src);
2246 void xorb(Register dst, Address src);
2247 void xorw(Register dst, Register src);
2248
2249 void xorq(Register dst, Address src);
2250 void xorq(Address dst, int32_t imm32);
2251 void xorq(Register dst, Register src);
2252 void xorq(Register dst, int32_t imm32);
2253 void xorq(Address dst, Register src);
2254
2255 // AVX 3-operands scalar instructions (encoded with VEX prefix)
2256
2257 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
2258 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2259 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
2260 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2261 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
2262 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2263 void evdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src, EvexRoundPrefix rmode);
2264 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
2265 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2266 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2267 void vfnmadd213sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2268 void evfnmadd213sd(XMMRegister dst, XMMRegister nds, XMMRegister src, EvexRoundPrefix rmode);
2269 void vfnmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2);
2270 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2271 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
2272 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2273 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
2274 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2275 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
2276 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2277 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
2278 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2279
2280 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2281 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2282 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2283 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2284
2285 void sarxl(Register dst, Register src1, Register src2);
2286 void sarxl(Register dst, Address src1, Register src2);
2287 void sarxq(Register dst, Register src1, Register src2);
2288 void sarxq(Register dst, Address src1, Register src2);
2289 void shlxl(Register dst, Register src1, Register src2);
2290 void shlxl(Register dst, Address src1, Register src2);
2291 void shlxq(Register dst, Register src1, Register src2);
2292 void shlxq(Register dst, Address src1, Register src2);
2293 void shrxl(Register dst, Register src1, Register src2);
2294 void shrxl(Register dst, Address src1, Register src2);
2295 void shrxq(Register dst, Register src1, Register src2);
2296 void shrxq(Register dst, Address src1, Register src2);
2297
2298 void bzhiq(Register dst, Register src1, Register src2);
2299
2300 void pextl(Register dst, Register src1, Register src2);
2301 void pdepl(Register dst, Register src1, Register src2);
2302 void pextq(Register dst, Register src1, Register src2);
2303 void pdepq(Register dst, Register src1, Register src2);
2304 void pextl(Register dst, Register src1, Address src2);
2305 void pdepl(Register dst, Register src1, Address src2);
2306 void pextq(Register dst, Register src1, Address src2);
2307 void pdepq(Register dst, Register src1, Address src2);
2308
2309
2310 //====================VECTOR ARITHMETIC=====================================
2311 // Add Packed Floating-Point Values
2312 void addpd(XMMRegister dst, XMMRegister src);
2313 void addpd(XMMRegister dst, Address src);
2314 void addps(XMMRegister dst, XMMRegister src);
2315 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2316 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2317 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2318 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2319
2320 // Subtract Packed Floating-Point Values
2321 void subpd(XMMRegister dst, XMMRegister src);
2322 void subps(XMMRegister dst, XMMRegister src);
2323 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2324 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2325 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2326 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2327
2328 // Multiply Packed Floating-Point Values
2329 void mulpd(XMMRegister dst, XMMRegister src);
2330 void mulpd(XMMRegister dst, Address src);
2331 void mulps(XMMRegister dst, XMMRegister src);
2332 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2333 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2334 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2335 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2336
2337 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2338 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2339 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2340 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2341
2342 // Divide Packed Floating-Point Values
2343 void divpd(XMMRegister dst, XMMRegister src);
2344 void divps(XMMRegister dst, XMMRegister src);
2345 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2346 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2347 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2348 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2349
2350 // Sqrt Packed Floating-Point Values
2351 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2352 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2353 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2354 void vsqrtps(XMMRegister dst, Address src, int vector_len);
2355
2356 // Round Packed Double precision value.
2357 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2358 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2359 void vrndscalesd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int32_t rmode);
2360 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2361 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2362 void vroundsd(XMMRegister dst, XMMRegister src, XMMRegister src2, int32_t rmode);
2363 void vroundsd(XMMRegister dst, XMMRegister src, Address src2, int32_t rmode);
2364
2365 // Bitwise Logical AND of Packed Floating-Point Values
2366 void andpd(XMMRegister dst, XMMRegister src);
2367 void andps(XMMRegister dst, XMMRegister src);
2368 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2369 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2370 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2371 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2372
2373 void unpckhpd(XMMRegister dst, XMMRegister src);
2374 void unpcklpd(XMMRegister dst, XMMRegister src);
2375
2376 // Bitwise Logical XOR of Packed Floating-Point Values
2377 void xorpd(XMMRegister dst, XMMRegister src);
2378 void xorps(XMMRegister dst, XMMRegister src);
2379 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2380 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2381 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2382 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2383
2384 // Add horizontal packed integers
2385 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2386 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2387 void phaddw(XMMRegister dst, XMMRegister src);
2388 void phaddd(XMMRegister dst, XMMRegister src);
2389
2390 // Add packed integers
2391 void paddb(XMMRegister dst, XMMRegister src);
2392 void paddw(XMMRegister dst, XMMRegister src);
2393 void paddd(XMMRegister dst, XMMRegister src);
2394 void paddd(XMMRegister dst, Address src);
2395 void paddq(XMMRegister dst, XMMRegister src);
2396 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2397 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2398 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2399 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2400 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2401 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2402 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2403 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2404
2405 // Leaf level assembler routines for masked operations.
2406 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2407 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2408 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2409 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2410 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2411 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2412 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2413 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2414 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2415 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2416 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2417 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2418 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2419 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2420 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2421 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2422 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2423 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2424 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2425 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2426 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2427 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2428 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2429 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2430 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2431 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2432 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2433 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2434 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2435 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2436 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2437 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2438 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2439 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2440 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2441 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2442 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2443 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2444 void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2445 void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2446 void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2447 void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2448 void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2449 void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2450 void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2451 void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2452 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2453 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2454 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2455 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2456 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2457 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2458 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2459 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2460 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2461 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2462 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2463 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2464 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2465 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2466 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2467 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2468 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2469 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2470 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2471 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2472 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2473 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2474 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2475 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2476 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2477
2478 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2479 void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2480 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2481 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2482 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2483 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2484 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2485 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2486 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2487
2488 void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2489 void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2490 void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2491 void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2492 void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2493 void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2494 void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2495 void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2496 void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2497 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2498 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2499 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2500 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2501 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2502 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2503 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2504 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2505 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2506 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2507 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2508 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2509 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2510 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2511 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2512 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2513 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2514 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2515 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2516 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2517 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2518 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2519 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2520 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2521 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2522 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2523 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2524 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2525
2526 void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2527 void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2528 void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2529 void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2530 void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2531 void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2532 void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2533 void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2534
2535 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2536 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2537 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len);
2538 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len);
2539
2540 void evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2541 void evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2542
2543 // Sub packed integers
2544 void psubb(XMMRegister dst, XMMRegister src);
2545 void psubw(XMMRegister dst, XMMRegister src);
2546 void psubd(XMMRegister dst, XMMRegister src);
2547 void psubq(XMMRegister dst, XMMRegister src);
2548 void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2549 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2550 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2551 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2552 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2553 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2554 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2555 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2556 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2557
2558 // Multiply packed integers (only shorts and ints)
2559 void pmullw(XMMRegister dst, XMMRegister src);
2560 void pmulld(XMMRegister dst, XMMRegister src);
2561 void pmuludq(XMMRegister dst, XMMRegister src);
2562 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2563 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2564 void evpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2565 void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2566 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2567 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2568 void evpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2569 void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2570
2571 // Minimum of packed integers
2572 void pminsb(XMMRegister dst, XMMRegister src);
2573 void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2574 void pminsw(XMMRegister dst, XMMRegister src);
2575 void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2576 void pminsd(XMMRegister dst, XMMRegister src);
2577 void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2578 void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2579 void minps(XMMRegister dst, XMMRegister src);
2580 void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2581 void minpd(XMMRegister dst, XMMRegister src);
2582 void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2583
2584 // Maximum of packed integers
2585 void pmaxsb(XMMRegister dst, XMMRegister src);
2586 void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2587 void pmaxsw(XMMRegister dst, XMMRegister src);
2588 void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2589 void pmaxsd(XMMRegister dst, XMMRegister src);
2590 void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2591 void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2592 void maxps(XMMRegister dst, XMMRegister src);
2593 void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2594 void maxpd(XMMRegister dst, XMMRegister src);
2595 void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2596
2597 // Shift left packed integers
2598 void psllw(XMMRegister dst, int shift);
2599 void pslld(XMMRegister dst, int shift);
2600 void psllq(XMMRegister dst, int shift);
2601 void psllw(XMMRegister dst, XMMRegister shift);
2602 void pslld(XMMRegister dst, XMMRegister shift);
2603 void psllq(XMMRegister dst, XMMRegister shift);
2604 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2605 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2606 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2607 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2608 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2609 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2610 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2611
2612 // Logical shift right packed integers
2613 void psrlw(XMMRegister dst, int shift);
2614 void psrld(XMMRegister dst, int shift);
2615 void psrlq(XMMRegister dst, int shift);
2616 void psrlw(XMMRegister dst, XMMRegister shift);
2617 void psrld(XMMRegister dst, XMMRegister shift);
2618 void psrlq(XMMRegister dst, XMMRegister shift);
2619 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2620 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2621 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2622 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2623 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2624 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2625 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2626 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2627 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2628
2629 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2630 void psraw(XMMRegister dst, int shift);
2631 void psrad(XMMRegister dst, int shift);
2632 void psraw(XMMRegister dst, XMMRegister shift);
2633 void psrad(XMMRegister dst, XMMRegister shift);
2634 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2635 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2636 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2637 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2638 void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2639 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2640 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2641
2642 // Variable shift left packed integers
2643 void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2644 void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2645
2646 // Variable shift right packed integers
2647 void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2648 void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2649
2650 // Variable shift right arithmetic packed integers
2651 void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2652 void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2653
2654 void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2655 void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2656
2657 // And packed integers
2658 void pand(XMMRegister dst, XMMRegister src);
2659 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2660 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2661 void evpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2662 void evpandq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2663
2664 // Andn packed integers
2665 void pandn(XMMRegister dst, XMMRegister src);
2666 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2667
2668 // Or packed integers
2669 void por(XMMRegister dst, XMMRegister src);
2670 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2671 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2672 void evporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2673 void evporq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2674
2675 // Xor packed integers
2676 void pxor(XMMRegister dst, XMMRegister src);
2677 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2678 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2679 void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2680 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2681 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2682
2683 // Ternary logic instruction.
2684 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2685 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len);
2686 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2687 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len);
2688
2689 // Vector compress/expand instructions.
2690 void evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2691 void evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2692 void evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2693 void evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2694 void evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2695 void evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2696
2697 void evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2698 void evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2699 void evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2700 void evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2701 void evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2702 void evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2703
2704 // Vector Rotate Left/Right instruction.
2705 void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2706 void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2707 void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2708 void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2709 void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2710 void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2711 void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2712 void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2713
2714 // vinserti forms
2715 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2716 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2717 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2718 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2719 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2720
2721 // vinsertf forms
2722 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2723 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2724 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2725 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2726 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2727 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2728
2729 // vextracti forms
2730 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2731 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2732 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2733 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2734 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2735 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2736 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2737
2738 // vextractf forms
2739 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2740 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2741 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2742 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2743 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2744 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2745 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2746
2747 void extractps(Register dst, XMMRegister src, uint8_t imm8);
2748
2749 // xmm/mem sourced byte/word/dword/qword replicate
2750 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2751 void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2752 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2753 void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2754 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2755 void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2756 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2757 void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2758
2759 void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
2760 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2761 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2762
2763 // scalar single/double/128bit precision replicate
2764 void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2765 void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2766 void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2767 void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2768 void vbroadcastf128(XMMRegister dst, Address src, int vector_len);
2769
2770 // gpr sourced byte/word/dword/qword replicate
2771 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2772 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2773 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2774 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2775
2776 // Gather AVX2 and AVX3
2777 void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2778 void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2779 void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2780 void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2781 void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2782 void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len);
2783 void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2784 void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len);
2785
2786 //Scatter AVX3 only
2787 void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2788 void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len);
2789 void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len);
2790 void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2791
2792 // Carry-Less Multiplication Quadword
2793 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2794 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2795 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2796 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2797 // to avoid transaction penalty between AVX and SSE states. There is no
2798 // penalty if legacy SSE instructions are encoded using VEX prefix because
2799 // they always clear upper 128 bits. It should be used before calling
2800 // runtime code and native libraries.
2801 void vzeroupper();
2802
2803 void vzeroall();
2804
2805 // Vector double compares
2806 void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2807 void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2808 ComparisonPredicateFP comparison, int vector_len);
2809
2810 // Vector float compares
2811 void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
2812 void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2813 ComparisonPredicateFP comparison, int vector_len);
2814
2815 // Vector integer compares
2816 void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2817 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2818 int comparison, bool is_signed, int vector_len);
2819 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2820 int comparison, bool is_signed, int vector_len);
2821
2822 // Vector long compares
2823 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2824 int comparison, bool is_signed, int vector_len);
2825 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2826 int comparison, bool is_signed, int vector_len);
2827
2828 // Vector byte compares
2829 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2830 int comparison, bool is_signed, int vector_len);
2831 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2832 int comparison, bool is_signed, int vector_len);
2833
2834 // Vector short compares
2835 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2836 int comparison, bool is_signed, int vector_len);
2837 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2838 int comparison, bool is_signed, int vector_len);
2839
2840 void evpmovb2m(KRegister dst, XMMRegister src, int vector_len);
2841 void evpmovw2m(KRegister dst, XMMRegister src, int vector_len);
2842 void evpmovd2m(KRegister dst, XMMRegister src, int vector_len);
2843 void evpmovq2m(KRegister dst, XMMRegister src, int vector_len);
2844 void evpmovm2b(XMMRegister dst, KRegister src, int vector_len);
2845 void evpmovm2w(XMMRegister dst, KRegister src, int vector_len);
2846 void evpmovm2d(XMMRegister dst, KRegister src, int vector_len);
2847 void evpmovm2q(XMMRegister dst, KRegister src, int vector_len);
2848
2849 // floating point class tests
2850 void vfpclassss(KRegister kdst, XMMRegister src, uint8_t imm8);
2851 void vfpclasssd(KRegister kdst, XMMRegister src, uint8_t imm8);
2852
2853 // Vector blends
2854 void blendvps(XMMRegister dst, XMMRegister src);
2855 void blendvpd(XMMRegister dst, XMMRegister src);
2856 void pblendvb(XMMRegister dst, XMMRegister src);
2857 void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2858 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2859 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2860 void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2861 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2862 void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2863 void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2864 void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2865 void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2866 void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2867 void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2868
2869 // Galois field affine transformation instructions.
2870 void gf2p8affineqb(XMMRegister dst, XMMRegister src, int imm8);
2871 void vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len);
2872
2873 protected:
2874 // Next instructions require address alignment 16 bytes SSE mode.
2875 // They should be called only from corresponding MacroAssembler instructions.
2876 void andpd(XMMRegister dst, Address src);
2877 void andps(XMMRegister dst, Address src);
2878 void xorpd(XMMRegister dst, Address src);
2879 void xorps(XMMRegister dst, Address src);
2880
2881 };
2882
2883 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2884 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2885 // are applied.
2886 class InstructionAttr {
2887 public:
2888 InstructionAttr(
2889 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2890 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2891 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2892 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2893 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2894 :
2895 _rex_vex_w(rex_vex_w),
2896 _legacy_mode(legacy_mode || UseAVX < 3),
2897 _no_reg_mask(no_reg_mask),
2898 _uses_vl(uses_vl),
2899 _rex_vex_w_reverted(false),
2900 _is_evex_instruction(false),
2901 _is_clear_context(true),
2902 _is_extended_context(false),
2903 _avx_vector_len(vector_len),
2904 _tuple_type(Assembler::EVEX_ETUP),
2905 _input_size_in_bits(Assembler::EVEX_NObit),
2906 _evex_encoding(0),
2907 _embedded_opmask_register_specifier(0), // hard code k0
2908 _current_assembler(nullptr) { }
2909
2910 ~InstructionAttr() {
2911 if (_current_assembler != nullptr) {
2912 _current_assembler->clear_attributes();
2913 }
2914 }
2915
2916 private:
2917 bool _rex_vex_w;
2918 bool _legacy_mode;
2919 bool _no_reg_mask;
2920 bool _uses_vl;
2921 bool _rex_vex_w_reverted;
2922 bool _is_evex_instruction;
2923 bool _is_clear_context;
2924 bool _is_extended_context;
2925 int _avx_vector_len;
2926 int _tuple_type;
2927 int _input_size_in_bits;
2928 int _evex_encoding;
2929 int _embedded_opmask_register_specifier;
2930
2931 Assembler *_current_assembler;
2932
2933 public:
2934 // query functions for field accessors
2935 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2936 bool is_legacy_mode(void) const { return _legacy_mode; }
2937 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2938 bool uses_vl(void) const { return _uses_vl; }
2939 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2940 bool is_evex_instruction(void) const { return _is_evex_instruction; }
2941 bool is_clear_context(void) const { return _is_clear_context; }
2942 bool is_extended_context(void) const { return _is_extended_context; }
2943 int get_vector_len(void) const { return _avx_vector_len; }
2944 int get_tuple_type(void) const { return _tuple_type; }
2945 int get_input_size(void) const { return _input_size_in_bits; }
2946 int get_evex_encoding(void) const { return _evex_encoding; }
2947 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2948
2949 // Set the vector len manually
2950 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2951
2952 // Set revert rex_vex_w for avx encoding
2953 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2954
2955 // Set rex_vex_w based on state
2956 void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2957
2958 // Set the instruction to be encoded in AVX mode
2959 void set_is_legacy_mode(void) { _legacy_mode = true; }
2960
2961 // Set the current instruction to be encoded as an EVEX instruction
2962 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2963
2964 // Internal encoding data used in compressed immediate offset programming
2965 void set_evex_encoding(int value) { _evex_encoding = value; }
2966
2967 // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
2968 // This method unsets it so that merge semantics are used instead.
2969 void reset_is_clear_context(void) { _is_clear_context = false; }
2970
2971 // Map back to current assembler so that we can manage object level association
2972 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2973
2974 // Address modifiers used for compressed displacement calculation
2975 void set_address_attributes(int tuple_type, int input_size_in_bits);
2976
2977 // Set embedded opmask register specifier.
2978 void set_embedded_opmask_register_specifier(KRegister mask) {
2979 _embedded_opmask_register_specifier = mask->encoding() & 0x7;
2980 }
2981
2982 void set_extended_context(void) { _is_extended_context = true; }
2983
2984 };
2985
2986 #endif // CPU_X86_ASSEMBLER_X86_HPP