1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2021, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.inline.hpp"
  30 #include "oops/compressedOops.hpp"
  31 #include "runtime/vm_version.hpp"
  32 #include "utilities/powerOfTwo.hpp"
  33 
  34 // MacroAssembler extends Assembler by frequently used macros.
  35 //
  36 // Instructions for which a 'better' code sequence exists depending
  37 // on arguments should also go in here.
  38 
  39 class MacroAssembler: public Assembler {
  40   friend class LIR_Assembler;
  41 
  42  public:
  43   using Assembler::mov;
  44   using Assembler::movi;
  45 
  46  protected:
  47 
  48   // Support for VM calls
  49   //
  50   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  51   // may customize this version by overriding it for its purposes (e.g., to save/restore
  52   // additional registers when doing a VM call).
  53   virtual void call_VM_leaf_base(
  54     address entry_point,               // the entry point
  55     int     number_of_arguments,        // the number of arguments to pop after the call
  56     Label *retaddr = NULL
  57   );
  58 
  59   virtual void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments,        // the number of arguments to pop after the call
  62     Label &retaddr) {
  63     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  64   }
  65 
  66   // This is the base routine called by the different versions of call_VM. The interpreter
  67   // may customize this version by overriding it for its purposes (e.g., to save/restore
  68   // additional registers when doing a VM call).
  69   //
  70   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  71   // returns the register which contains the thread upon return. If a thread register has been
  72   // specified, the return value will correspond to that register. If no last_java_sp is specified
  73   // (noreg) than rsp will be used instead.
  74   virtual void call_VM_base(           // returns the register containing the thread upon return
  75     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  76     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  77     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  78     address  entry_point,              // the entry point
  79     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  80     bool     check_exceptions          // whether to check for pending exceptions after return
  81   );
  82 
  83   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  84 
  85   enum KlassDecodeMode {
  86     KlassDecodeNone,
  87     KlassDecodeZero,
  88     KlassDecodeXor,
  89     KlassDecodeMovk
  90   };
  91 
  92   KlassDecodeMode klass_decode_mode();
  93 
  94  private:
  95   static KlassDecodeMode _klass_decode_mode;
  96 
  97  public:
  98   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  99 
 100  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
 101  // The implementation is only non-empty for the InterpreterMacroAssembler,
 102  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 103  virtual void check_and_handle_popframe(Register java_thread);
 104  virtual void check_and_handle_earlyret(Register java_thread);
 105 
 106   void safepoint_poll(Label& slow_path, bool at_return, bool acquire, bool in_nmethod);
 107 
 108   // Helper functions for statistics gathering.
 109   // Unconditional atomic increment.
 110   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 111   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 112     lea(tmp1, counter_addr);
 113     atomic_incw(tmp1, tmp2, tmp3);
 114   }
 115   // Load Effective Address
 116   void lea(Register r, const Address &a) {
 117     InstructionMark im(this);
 118     code_section()->relocate(inst_mark(), a.rspec());
 119     a.lea(this, r);
 120   }
 121 
 122   /* Sometimes we get misaligned loads and stores, usually from Unsafe
 123      accesses, and these can exceed the offset range. */
 124   Address legitimize_address(const Address &a, int size, Register scratch) {
 125     if (a.getMode() == Address::base_plus_offset) {
 126       if (! Address::offset_ok_for_immed(a.offset(), exact_log2(size))) {
 127         block_comment("legitimize_address {");
 128         lea(scratch, a);
 129         block_comment("} legitimize_address");
 130         return Address(scratch);
 131       }
 132     }
 133     return a;
 134   }
 135 
 136   void addmw(Address a, Register incr, Register scratch) {
 137     ldrw(scratch, a);
 138     addw(scratch, scratch, incr);
 139     strw(scratch, a);
 140   }
 141 
 142   // Add constant to memory word
 143   void addmw(Address a, int imm, Register scratch) {
 144     ldrw(scratch, a);
 145     if (imm > 0)
 146       addw(scratch, scratch, (unsigned)imm);
 147     else
 148       subw(scratch, scratch, (unsigned)-imm);
 149     strw(scratch, a);
 150   }
 151 
 152   void bind(Label& L) {
 153     Assembler::bind(L);
 154     code()->clear_last_insn();
 155   }
 156 
 157   void membar(Membar_mask_bits order_constraint);
 158 
 159   using Assembler::ldr;
 160   using Assembler::str;
 161   using Assembler::ldrw;
 162   using Assembler::strw;
 163 
 164   void ldr(Register Rx, const Address &adr);
 165   void ldrw(Register Rw, const Address &adr);
 166   void str(Register Rx, const Address &adr);
 167   void strw(Register Rx, const Address &adr);
 168 
 169   // Frame creation and destruction shared between JITs.
 170   void build_frame(int framesize);
 171   void remove_frame(int framesize);
 172 
 173   virtual void _call_Unimplemented(address call_site) {
 174     mov(rscratch2, call_site);
 175   }
 176 
 177 // Microsoft's MSVC team thinks that the __FUNCSIG__ is approximately (sympathy for calling conventions) equivalent to __PRETTY_FUNCTION__
 178 // Also, from Clang patch: "It is very similar to GCC's PRETTY_FUNCTION, except it prints the calling convention."
 179 // https://reviews.llvm.org/D3311
 180 
 181 #ifdef _WIN64
 182 #define call_Unimplemented() _call_Unimplemented((address)__FUNCSIG__)
 183 #else
 184 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 185 #endif
 186 
 187   // aliases defined in AARCH64 spec
 188 
 189   template<class T>
 190   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 191 
 192   inline void cmp(Register Rd, unsigned char imm8)  { subs(zr, Rd, imm8); }
 193   inline void cmp(Register Rd, unsigned imm) = delete;
 194 
 195   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 196   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 197 
 198   void cset(Register Rd, Assembler::Condition cond) {
 199     csinc(Rd, zr, zr, ~cond);
 200   }
 201   void csetw(Register Rd, Assembler::Condition cond) {
 202     csincw(Rd, zr, zr, ~cond);
 203   }
 204 
 205   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 206     csneg(Rd, Rn, Rn, ~cond);
 207   }
 208   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 209     csnegw(Rd, Rn, Rn, ~cond);
 210   }
 211 
 212   inline void movw(Register Rd, Register Rn) {
 213     if (Rd == sp || Rn == sp) {
 214       addw(Rd, Rn, 0U);
 215     } else {
 216       orrw(Rd, zr, Rn);
 217     }
 218   }
 219   inline void mov(Register Rd, Register Rn) {
 220     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 221     if (Rd == Rn) {
 222     } else if (Rd == sp || Rn == sp) {
 223       add(Rd, Rn, 0U);
 224     } else {
 225       orr(Rd, zr, Rn);
 226     }
 227   }
 228 
 229   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 230   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 231 
 232   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 233   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 234 
 235   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 236   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 237 
 238   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 240   }
 241   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 242     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 243   }
 244 
 245   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 247   }
 248   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     bfm(Rd, Rn, lsb , (lsb + width - 1));
 250   }
 251 
 252   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 254   }
 255   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 257   }
 258 
 259   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 261   }
 262   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 263     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 264   }
 265 
 266   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 267     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 268   }
 269   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 270     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 271   }
 272 
 273   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 274     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 275   }
 276   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 277     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 278   }
 279 
 280   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 281     sbfmw(Rd, Rn, imm, 31);
 282   }
 283 
 284   inline void asr(Register Rd, Register Rn, unsigned imm) {
 285     sbfm(Rd, Rn, imm, 63);
 286   }
 287 
 288   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 289     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 290   }
 291 
 292   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 293     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 294   }
 295 
 296   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 297     ubfmw(Rd, Rn, imm, 31);
 298   }
 299 
 300   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 301     ubfm(Rd, Rn, imm, 63);
 302   }
 303 
 304   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 305     extrw(Rd, Rn, Rn, imm);
 306   }
 307 
 308   inline void ror(Register Rd, Register Rn, unsigned imm) {
 309     extr(Rd, Rn, Rn, imm);
 310   }
 311 
 312   inline void sxtbw(Register Rd, Register Rn) {
 313     sbfmw(Rd, Rn, 0, 7);
 314   }
 315   inline void sxthw(Register Rd, Register Rn) {
 316     sbfmw(Rd, Rn, 0, 15);
 317   }
 318   inline void sxtb(Register Rd, Register Rn) {
 319     sbfm(Rd, Rn, 0, 7);
 320   }
 321   inline void sxth(Register Rd, Register Rn) {
 322     sbfm(Rd, Rn, 0, 15);
 323   }
 324   inline void sxtw(Register Rd, Register Rn) {
 325     sbfm(Rd, Rn, 0, 31);
 326   }
 327 
 328   inline void uxtbw(Register Rd, Register Rn) {
 329     ubfmw(Rd, Rn, 0, 7);
 330   }
 331   inline void uxthw(Register Rd, Register Rn) {
 332     ubfmw(Rd, Rn, 0, 15);
 333   }
 334   inline void uxtb(Register Rd, Register Rn) {
 335     ubfm(Rd, Rn, 0, 7);
 336   }
 337   inline void uxth(Register Rd, Register Rn) {
 338     ubfm(Rd, Rn, 0, 15);
 339   }
 340   inline void uxtw(Register Rd, Register Rn) {
 341     ubfm(Rd, Rn, 0, 31);
 342   }
 343 
 344   inline void cmnw(Register Rn, Register Rm) {
 345     addsw(zr, Rn, Rm);
 346   }
 347   inline void cmn(Register Rn, Register Rm) {
 348     adds(zr, Rn, Rm);
 349   }
 350 
 351   inline void cmpw(Register Rn, Register Rm) {
 352     subsw(zr, Rn, Rm);
 353   }
 354   inline void cmp(Register Rn, Register Rm) {
 355     subs(zr, Rn, Rm);
 356   }
 357 
 358   inline void negw(Register Rd, Register Rn) {
 359     subw(Rd, zr, Rn);
 360   }
 361 
 362   inline void neg(Register Rd, Register Rn) {
 363     sub(Rd, zr, Rn);
 364   }
 365 
 366   inline void negsw(Register Rd, Register Rn) {
 367     subsw(Rd, zr, Rn);
 368   }
 369 
 370   inline void negs(Register Rd, Register Rn) {
 371     subs(Rd, zr, Rn);
 372   }
 373 
 374   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 375     addsw(zr, Rn, Rm, kind, shift);
 376   }
 377   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 378     adds(zr, Rn, Rm, kind, shift);
 379   }
 380 
 381   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 382     subsw(zr, Rn, Rm, kind, shift);
 383   }
 384   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 385     subs(zr, Rn, Rm, kind, shift);
 386   }
 387 
 388   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 389     subw(Rd, zr, Rn, kind, shift);
 390   }
 391 
 392   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 393     sub(Rd, zr, Rn, kind, shift);
 394   }
 395 
 396   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 397     subsw(Rd, zr, Rn, kind, shift);
 398   }
 399 
 400   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 401     subs(Rd, zr, Rn, kind, shift);
 402   }
 403 
 404   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 405     msubw(Rd, Rn, Rm, zr);
 406   }
 407   inline void mneg(Register Rd, Register Rn, Register Rm) {
 408     msub(Rd, Rn, Rm, zr);
 409   }
 410 
 411   inline void mulw(Register Rd, Register Rn, Register Rm) {
 412     maddw(Rd, Rn, Rm, zr);
 413   }
 414   inline void mul(Register Rd, Register Rn, Register Rm) {
 415     madd(Rd, Rn, Rm, zr);
 416   }
 417 
 418   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 419     smsubl(Rd, Rn, Rm, zr);
 420   }
 421   inline void smull(Register Rd, Register Rn, Register Rm) {
 422     smaddl(Rd, Rn, Rm, zr);
 423   }
 424 
 425   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 426     umsubl(Rd, Rn, Rm, zr);
 427   }
 428   inline void umull(Register Rd, Register Rn, Register Rm) {
 429     umaddl(Rd, Rn, Rm, zr);
 430   }
 431 
 432 #define WRAP(INSN)                                                            \
 433   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 434     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 435       nop();                                                                  \
 436     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 437   }
 438 
 439   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 440   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 441 #undef WRAP
 442 
 443 
 444   // macro assembly operations needed for aarch64
 445 
 446   // first two private routines for loading 32 bit or 64 bit constants
 447 private:
 448 
 449   void mov_immediate64(Register dst, uint64_t imm64);
 450   void mov_immediate32(Register dst, uint32_t imm32);
 451 
 452   int push(unsigned int bitset, Register stack);
 453   int pop(unsigned int bitset, Register stack);
 454 
 455   int push_fp(unsigned int bitset, Register stack);
 456   int pop_fp(unsigned int bitset, Register stack);
 457 
 458   int push_p(unsigned int bitset, Register stack);
 459   int pop_p(unsigned int bitset, Register stack);
 460 
 461   void mov(Register dst, Address a);
 462 
 463 public:
 464   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 465   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 466 
 467   void push_fp(FloatRegSet regs, Register stack) { if (regs.bits()) push_fp(regs.bits(), stack); }
 468   void pop_fp(FloatRegSet regs, Register stack) { if (regs.bits()) pop_fp(regs.bits(), stack); }
 469 
 470   static RegSet call_clobbered_registers();
 471 
 472   void push_p(PRegSet regs, Register stack) { if (regs.bits()) push_p(regs.bits(), stack); }
 473   void pop_p(PRegSet regs, Register stack) { if (regs.bits()) pop_p(regs.bits(), stack); }
 474 
 475   // Push and pop everything that might be clobbered by a native
 476   // runtime call except rscratch1 and rscratch2.  (They are always
 477   // scratch, so we don't have to protect them.)  Only save the lower
 478   // 64 bits of each vector register. Additonal registers can be excluded
 479   // in a passed RegSet.
 480   void push_call_clobbered_registers_except(RegSet exclude);
 481   void pop_call_clobbered_registers_except(RegSet exclude);
 482 
 483   void push_call_clobbered_registers() {
 484     push_call_clobbered_registers_except(RegSet());
 485   }
 486   void pop_call_clobbered_registers() {
 487     pop_call_clobbered_registers_except(RegSet());
 488   }
 489 
 490 
 491   // now mov instructions for loading absolute addresses and 32 or
 492   // 64 bit integers
 493 
 494   inline void mov(Register dst, address addr)             { mov_immediate64(dst, (uint64_t)addr); }
 495 
 496   inline void mov(Register dst, int imm64)                { mov_immediate64(dst, (uint64_t)imm64); }
 497   inline void mov(Register dst, long imm64)               { mov_immediate64(dst, (uint64_t)imm64); }
 498   inline void mov(Register dst, long long imm64)          { mov_immediate64(dst, (uint64_t)imm64); }
 499   inline void mov(Register dst, unsigned int imm64)       { mov_immediate64(dst, (uint64_t)imm64); }
 500   inline void mov(Register dst, unsigned long imm64)      { mov_immediate64(dst, (uint64_t)imm64); }
 501   inline void mov(Register dst, unsigned long long imm64) { mov_immediate64(dst, (uint64_t)imm64); }
 502 
 503   inline void movw(Register dst, uint32_t imm32)
 504   {
 505     mov_immediate32(dst, imm32);
 506   }
 507 
 508   void mov(Register dst, RegisterOrConstant src) {
 509     if (src.is_register())
 510       mov(dst, src.as_register());
 511     else
 512       mov(dst, src.as_constant());
 513   }
 514 
 515   void movptr(Register r, uintptr_t imm64);
 516 
 517   void mov(FloatRegister Vd, SIMD_Arrangement T, uint32_t imm32);
 518 
 519   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 520     orr(Vd, T, Vn, Vn);
 521   }
 522 
 523 
 524 public:
 525 
 526   // Generalized Test Bit And Branch, including a "far" variety which
 527   // spans more than 32KiB.
 528   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool isfar = false) {
 529     assert(cond == EQ || cond == NE, "must be");
 530 
 531     if (isfar)
 532       cond = ~cond;
 533 
 534     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 535     if (cond == Assembler::EQ)
 536       branch = &Assembler::tbz;
 537     else
 538       branch = &Assembler::tbnz;
 539 
 540     if (isfar) {
 541       Label L;
 542       (this->*branch)(Rt, bitpos, L);
 543       b(dest);
 544       bind(L);
 545     } else {
 546       (this->*branch)(Rt, bitpos, dest);
 547     }
 548   }
 549 
 550   // macro instructions for accessing and updating floating point
 551   // status register
 552   //
 553   // FPSR : op1 == 011
 554   //        CRn == 0100
 555   //        CRm == 0100
 556   //        op2 == 001
 557 
 558   inline void get_fpsr(Register reg)
 559   {
 560     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 561   }
 562 
 563   inline void set_fpsr(Register reg)
 564   {
 565     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 566   }
 567 
 568   inline void clear_fpsr()
 569   {
 570     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 571   }
 572 
 573   // DCZID_EL0: op1 == 011
 574   //            CRn == 0000
 575   //            CRm == 0000
 576   //            op2 == 111
 577   inline void get_dczid_el0(Register reg)
 578   {
 579     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 580   }
 581 
 582   // CTR_EL0:   op1 == 011
 583   //            CRn == 0000
 584   //            CRm == 0000
 585   //            op2 == 001
 586   inline void get_ctr_el0(Register reg)
 587   {
 588     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 589   }
 590 
 591   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 592   int corrected_idivl(Register result, Register ra, Register rb,
 593                       bool want_remainder, Register tmp = rscratch1);
 594   int corrected_idivq(Register result, Register ra, Register rb,
 595                       bool want_remainder, Register tmp = rscratch1);
 596 
 597   // Support for NULL-checks
 598   //
 599   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 600   // If the accessed location is M[reg + offset] and the offset is known, provide the
 601   // offset. No explicit code generation is needed if the offset is within a certain
 602   // range (0 <= offset <= page_size).
 603 
 604   virtual void null_check(Register reg, int offset = -1);
 605   static bool needs_explicit_null_check(intptr_t offset);
 606   static bool uses_implicit_null_check(void* address);
 607 
 608   static address target_addr_for_insn(address insn_addr, unsigned insn);
 609   static address target_addr_for_insn(address insn_addr) {
 610     unsigned insn = *(unsigned*)insn_addr;
 611     return target_addr_for_insn(insn_addr, insn);
 612   }
 613 
 614   // Required platform-specific helpers for Label::patch_instructions.
 615   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 616   static int pd_patch_instruction_size(address branch, address target);
 617   static void pd_patch_instruction(address branch, address target, const char* file = NULL, int line = 0) {
 618     pd_patch_instruction_size(branch, target);
 619   }
 620   static address pd_call_destination(address branch) {
 621     return target_addr_for_insn(branch);
 622   }
 623 #ifndef PRODUCT
 624   static void pd_print_patched_instruction(address branch);
 625 #endif
 626 
 627   static int patch_oop(address insn_addr, address o);
 628   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 629 
 630   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 631   void emit_static_call_stub();
 632 
 633   // The following 4 methods return the offset of the appropriate move instruction
 634 
 635   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 636   int load_unsigned_byte(Register dst, Address src);
 637   int load_unsigned_short(Register dst, Address src);
 638 
 639   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 640   int load_signed_byte(Register dst, Address src);
 641   int load_signed_short(Register dst, Address src);
 642 
 643   int load_signed_byte32(Register dst, Address src);
 644   int load_signed_short32(Register dst, Address src);
 645 
 646   // Support for sign-extension (hi:lo = extend_sign(lo))
 647   void extend_sign(Register hi, Register lo);
 648 
 649   // Load and store values by size and signed-ness
 650   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 651   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 652 
 653   // Support for inc/dec with optimal instruction selection depending on value
 654 
 655   // x86_64 aliases an unqualified register/address increment and
 656   // decrement to call incrementq and decrementq but also supports
 657   // explicitly sized calls to incrementq/decrementq or
 658   // incrementl/decrementl
 659 
 660   // for aarch64 the proper convention would be to use
 661   // increment/decrement for 64 bit operatons and
 662   // incrementw/decrementw for 32 bit operations. so when porting
 663   // x86_64 code we can leave calls to increment/decrement as is,
 664   // replace incrementq/decrementq with increment/decrement and
 665   // replace incrementl/decrementl with incrementw/decrementw.
 666 
 667   // n.b. increment/decrement calls with an Address destination will
 668   // need to use a scratch register to load the value to be
 669   // incremented. increment/decrement calls which add or subtract a
 670   // constant value greater than 2^12 will need to use a 2nd scratch
 671   // register to hold the constant. so, a register increment/decrement
 672   // may trash rscratch2 and an address increment/decrement trash
 673   // rscratch and rscratch2
 674 
 675   void decrementw(Address dst, int value = 1);
 676   void decrementw(Register reg, int value = 1);
 677 
 678   void decrement(Register reg, int value = 1);
 679   void decrement(Address dst, int value = 1);
 680 
 681   void incrementw(Address dst, int value = 1);
 682   void incrementw(Register reg, int value = 1);
 683 
 684   void increment(Register reg, int value = 1);
 685   void increment(Address dst, int value = 1);
 686 
 687 
 688   // Alignment
 689   void align(int modulus);
 690 
 691   // Stack frame creation/removal
 692   void enter()
 693   {
 694     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 695     mov(rfp, sp);
 696   }
 697   void leave()
 698   {
 699     mov(sp, rfp);
 700     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 701   }
 702 
 703   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 704   // The pointer will be loaded into the thread register.
 705   void get_thread(Register thread);
 706 
 707 
 708   // Support for VM calls
 709   //
 710   // It is imperative that all calls into the VM are handled via the call_VM macros.
 711   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 712   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 713 
 714 
 715   void call_VM(Register oop_result,
 716                address entry_point,
 717                bool check_exceptions = true);
 718   void call_VM(Register oop_result,
 719                address entry_point,
 720                Register arg_1,
 721                bool check_exceptions = true);
 722   void call_VM(Register oop_result,
 723                address entry_point,
 724                Register arg_1, Register arg_2,
 725                bool check_exceptions = true);
 726   void call_VM(Register oop_result,
 727                address entry_point,
 728                Register arg_1, Register arg_2, Register arg_3,
 729                bool check_exceptions = true);
 730 
 731   // Overloadings with last_Java_sp
 732   void call_VM(Register oop_result,
 733                Register last_java_sp,
 734                address entry_point,
 735                int number_of_arguments = 0,
 736                bool check_exceptions = true);
 737   void call_VM(Register oop_result,
 738                Register last_java_sp,
 739                address entry_point,
 740                Register arg_1, bool
 741                check_exceptions = true);
 742   void call_VM(Register oop_result,
 743                Register last_java_sp,
 744                address entry_point,
 745                Register arg_1, Register arg_2,
 746                bool check_exceptions = true);
 747   void call_VM(Register oop_result,
 748                Register last_java_sp,
 749                address entry_point,
 750                Register arg_1, Register arg_2, Register arg_3,
 751                bool check_exceptions = true);
 752 
 753   void get_vm_result  (Register oop_result, Register thread);
 754   void get_vm_result_2(Register metadata_result, Register thread);
 755 
 756   // These always tightly bind to MacroAssembler::call_VM_base
 757   // bypassing the virtual implementation
 758   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 759   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 760   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 761   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 762   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 763 
 764   void call_VM_leaf(address entry_point,
 765                     int number_of_arguments = 0);
 766   void call_VM_leaf(address entry_point,
 767                     Register arg_1);
 768   void call_VM_leaf(address entry_point,
 769                     Register arg_1, Register arg_2);
 770   void call_VM_leaf(address entry_point,
 771                     Register arg_1, Register arg_2, Register arg_3);
 772 
 773   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 774   // bypassing the virtual implementation
 775   void super_call_VM_leaf(address entry_point);
 776   void super_call_VM_leaf(address entry_point, Register arg_1);
 777   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 778   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 779   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 780 
 781   // last Java Frame (fills frame anchor)
 782   void set_last_Java_frame(Register last_java_sp,
 783                            Register last_java_fp,
 784                            address last_java_pc,
 785                            Register scratch);
 786 
 787   void set_last_Java_frame(Register last_java_sp,
 788                            Register last_java_fp,
 789                            Label &last_java_pc,
 790                            Register scratch);
 791 
 792   void set_last_Java_frame(Register last_java_sp,
 793                            Register last_java_fp,
 794                            Register last_java_pc,
 795                            Register scratch);
 796 
 797   void reset_last_Java_frame(Register thread);
 798 
 799   // thread in the default location (rthread)
 800   void reset_last_Java_frame(bool clear_fp);
 801 
 802   // Stores
 803   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 804   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 805 
 806   void resolve_jobject(Register value, Register thread, Register tmp);
 807 
 808   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 809   void c2bool(Register x);
 810 
 811   void load_method_holder_cld(Register rresult, Register rmethod);
 812   void load_method_holder(Register holder, Register method);
 813 
 814   // oop manipulations
 815   void load_klass(Register dst, Register src);
 816   void store_klass(Register dst, Register src);
 817   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 818 
 819   void resolve_weak_handle(Register result, Register tmp);
 820   void resolve_oop_handle(Register result, Register tmp = r5);
 821   void load_mirror(Register dst, Register method, Register tmp = r5);
 822 
 823   void access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
 824                       Register tmp1, Register tmp_thread);
 825 
 826   void access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
 827                        Register tmp1, Register tmp_thread);
 828 
 829   void load_heap_oop(Register dst, Address src, Register tmp1 = noreg,
 830                      Register thread_tmp = noreg, DecoratorSet decorators = 0);
 831 
 832   void load_heap_oop_not_null(Register dst, Address src, Register tmp1 = noreg,
 833                               Register thread_tmp = noreg, DecoratorSet decorators = 0);
 834   void store_heap_oop(Address dst, Register src, Register tmp1 = noreg,
 835                       Register tmp_thread = noreg, DecoratorSet decorators = 0);
 836 
 837   // currently unimplemented
 838   // Used for storing NULL. All other oop constants should be
 839   // stored using routines that take a jobject.
 840   void store_heap_oop_null(Address dst);
 841 
 842   void store_klass_gap(Register dst, Register src);
 843 
 844   // This dummy is to prevent a call to store_heap_oop from
 845   // converting a zero (like NULL) into a Register by giving
 846   // the compiler two choices it can't resolve
 847 
 848   void store_heap_oop(Address dst, void* dummy);
 849 
 850   void encode_heap_oop(Register d, Register s);
 851   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 852   void decode_heap_oop(Register d, Register s);
 853   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 854   void encode_heap_oop_not_null(Register r);
 855   void decode_heap_oop_not_null(Register r);
 856   void encode_heap_oop_not_null(Register dst, Register src);
 857   void decode_heap_oop_not_null(Register dst, Register src);
 858 
 859   void set_narrow_oop(Register dst, jobject obj);
 860 
 861   void encode_klass_not_null(Register r);
 862   void decode_klass_not_null(Register r);
 863   void encode_klass_not_null(Register dst, Register src);
 864   void decode_klass_not_null(Register dst, Register src);
 865 
 866   void set_narrow_klass(Register dst, Klass* k);
 867 
 868   // if heap base register is used - reinit it with the correct value
 869   void reinit_heapbase();
 870 
 871   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 872 
 873   void push_CPU_state(bool save_vectors = false, bool use_sve = false,
 874                       int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 875   void pop_CPU_state(bool restore_vectors = false, bool use_sve = false,
 876                      int sve_vector_size_in_bytes = 0, int total_predicate_in_bytes = 0);
 877 
 878   // Round up to a power of two
 879   void round_to(Register reg, int modulus);
 880 
 881   // allocation
 882   void eden_allocate(
 883     Register obj,                      // result: pointer to object after successful allocation
 884     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 885     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 886     Register t1,                       // temp register
 887     Label&   slow_case                 // continuation point if fast allocation fails
 888   );
 889   void tlab_allocate(
 890     Register obj,                      // result: pointer to object after successful allocation
 891     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 892     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 893     Register t1,                       // temp register
 894     Register t2,                       // temp register
 895     Label&   slow_case                 // continuation point if fast allocation fails
 896   );
 897   void verify_tlab();
 898 
 899   // interface method calling
 900   void lookup_interface_method(Register recv_klass,
 901                                Register intf_klass,
 902                                RegisterOrConstant itable_index,
 903                                Register method_result,
 904                                Register scan_temp,
 905                                Label& no_such_interface,
 906                    bool return_method = true);
 907 
 908   // virtual method calling
 909   // n.b. x86 allows RegisterOrConstant for vtable_index
 910   void lookup_virtual_method(Register recv_klass,
 911                              RegisterOrConstant vtable_index,
 912                              Register method_result);
 913 
 914   // Test sub_klass against super_klass, with fast and slow paths.
 915 
 916   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 917   // One of the three labels can be NULL, meaning take the fall-through.
 918   // If super_check_offset is -1, the value is loaded up from super_klass.
 919   // No registers are killed, except temp_reg.
 920   void check_klass_subtype_fast_path(Register sub_klass,
 921                                      Register super_klass,
 922                                      Register temp_reg,
 923                                      Label* L_success,
 924                                      Label* L_failure,
 925                                      Label* L_slow_path,
 926                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 927 
 928   // The rest of the type check; must be wired to a corresponding fast path.
 929   // It does not repeat the fast path logic, so don't use it standalone.
 930   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 931   // Updates the sub's secondary super cache as necessary.
 932   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 933   void check_klass_subtype_slow_path(Register sub_klass,
 934                                      Register super_klass,
 935                                      Register temp_reg,
 936                                      Register temp2_reg,
 937                                      Label* L_success,
 938                                      Label* L_failure,
 939                                      bool set_cond_codes = false);
 940 
 941   // Simplified, combined version, good for typical uses.
 942   // Falls through on failure.
 943   void check_klass_subtype(Register sub_klass,
 944                            Register super_klass,
 945                            Register temp_reg,
 946                            Label& L_success);
 947 
 948   void clinit_barrier(Register klass,
 949                       Register thread,
 950                       Label* L_fast_path = NULL,
 951                       Label* L_slow_path = NULL);
 952 
 953   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 954 
 955   void verify_sve_vector_length();
 956   void reinitialize_ptrue() {
 957     if (UseSVE > 0) {
 958       sve_ptrue(ptrue, B);
 959     }
 960   }
 961   void verify_ptrue();
 962 
 963   // Debugging
 964 
 965   // only if +VerifyOops
 966   void verify_oop(Register reg, const char* s = "broken oop");
 967   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 968 
 969 // TODO: verify method and klass metadata (compare against vptr?)
 970   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 971   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 972 
 973 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 974 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 975 
 976   // only if +VerifyFPU
 977   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 978 
 979   // prints msg, dumps registers and stops execution
 980   void stop(const char* msg);
 981 
 982   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 983 
 984   void untested()                                { stop("untested"); }
 985 
 986   void unimplemented(const char* what = "");
 987 
 988   void should_not_reach_here()                   { stop("should not reach here"); }
 989 
 990   // Stack overflow checking
 991   void bang_stack_with_offset(int offset) {
 992     // stack grows down, caller passes positive offset
 993     assert(offset > 0, "must bang with negative offset");
 994     sub(rscratch2, sp, offset);
 995     str(zr, Address(rscratch2));
 996   }
 997 
 998   // Writes to stack successive pages until offset reached to check for
 999   // stack overflow + shadow pages.  Also, clobbers tmp
1000   void bang_stack_size(Register size, Register tmp);
1001 
1002   // Check for reserved stack access in method being exited (for JIT)
1003   void reserved_stack_check();
1004 
1005   // Arithmetics
1006 
1007   void addptr(const Address &dst, int32_t src);
1008   void cmpptr(Register src1, Address src2);
1009 
1010   void cmpoop(Register obj1, Register obj2);
1011 
1012   // Various forms of CAS
1013 
1014   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
1015                           Label &suceed, Label *fail);
1016   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
1017                   Label &suceed, Label *fail);
1018 
1019   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
1020                   Label &suceed, Label *fail);
1021 
1022   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
1023   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
1024   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
1025   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
1026 
1027   void atomic_xchg(Register prev, Register newv, Register addr);
1028   void atomic_xchgw(Register prev, Register newv, Register addr);
1029   void atomic_xchgl(Register prev, Register newv, Register addr);
1030   void atomic_xchglw(Register prev, Register newv, Register addr);
1031   void atomic_xchgal(Register prev, Register newv, Register addr);
1032   void atomic_xchgalw(Register prev, Register newv, Register addr);
1033 
1034   void orptr(Address adr, RegisterOrConstant src) {
1035     ldr(rscratch1, adr);
1036     if (src.is_register())
1037       orr(rscratch1, rscratch1, src.as_register());
1038     else
1039       orr(rscratch1, rscratch1, src.as_constant());
1040     str(rscratch1, adr);
1041   }
1042 
1043   // A generic CAS; success or failure is in the EQ flag.
1044   // Clobbers rscratch1
1045   void cmpxchg(Register addr, Register expected, Register new_val,
1046                enum operand_size size,
1047                bool acquire, bool release, bool weak,
1048                Register result);
1049 
1050 private:
1051   void compare_eq(Register rn, Register rm, enum operand_size size);
1052 
1053 #ifdef ASSERT
1054   // Template short-hand support to clean-up after a failed call to trampoline
1055   // call generation (see trampoline_call() below),  when a set of Labels must
1056   // be reset (before returning).
1057   template<typename Label, typename... More>
1058   void reset_labels(Label &lbl, More&... more) {
1059     lbl.reset(); reset_labels(more...);
1060   }
1061   template<typename Label>
1062   void reset_labels(Label &lbl) {
1063     lbl.reset();
1064   }
1065 #endif
1066 
1067 public:
1068   // Calls
1069 
1070   address trampoline_call(Address entry, CodeBuffer* cbuf = NULL);
1071 
1072   static bool far_branches() {
1073     return ReservedCodeCacheSize > branch_range;
1074   }
1075 
1076   // Jumps that can reach anywhere in the code cache.
1077   // Trashes tmp.
1078   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1079   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1080 
1081   static int far_branch_size() {
1082     if (far_branches()) {
1083       return 3 * 4;  // adrp, add, br
1084     } else {
1085       return 4;
1086     }
1087   }
1088 
1089   // Emit the CompiledIC call idiom
1090   address ic_call(address entry, jint method_index = 0);
1091 
1092 public:
1093 
1094   // Data
1095 
1096   void mov_metadata(Register dst, Metadata* obj);
1097   Address allocate_metadata_address(Metadata* obj);
1098   Address constant_oop_address(jobject obj);
1099 
1100   void movoop(Register dst, jobject obj, bool immediate = false);
1101 
1102   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1103   void kernel_crc32(Register crc, Register buf, Register len,
1104         Register table0, Register table1, Register table2, Register table3,
1105         Register tmp, Register tmp2, Register tmp3);
1106   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1107   void kernel_crc32c(Register crc, Register buf, Register len,
1108         Register table0, Register table1, Register table2, Register table3,
1109         Register tmp, Register tmp2, Register tmp3);
1110 
1111   // Stack push and pop individual 64 bit registers
1112   void push(Register src);
1113   void pop(Register dst);
1114 
1115   void repne_scan(Register addr, Register value, Register count,
1116                   Register scratch);
1117   void repne_scanw(Register addr, Register value, Register count,
1118                    Register scratch);
1119 
1120   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1121   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1122 
1123   // If a constant does not fit in an immediate field, generate some
1124   // number of MOV instructions and then perform the operation
1125   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1126                              add_sub_imm_insn insn1,
1127                              add_sub_reg_insn insn2);
1128   // Seperate vsn which sets the flags
1129   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1130                              add_sub_imm_insn insn1,
1131                              add_sub_reg_insn insn2);
1132 
1133 #define WRAP(INSN)                                                      \
1134   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1135     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1136   }                                                                     \
1137                                                                         \
1138   void INSN(Register Rd, Register Rn, Register Rm,                      \
1139              enum shift_kind kind, unsigned shift = 0) {                \
1140     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1141   }                                                                     \
1142                                                                         \
1143   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1144     Assembler::INSN(Rd, Rn, Rm);                                        \
1145   }                                                                     \
1146                                                                         \
1147   void INSN(Register Rd, Register Rn, Register Rm,                      \
1148            ext::operation option, int amount = 0) {                     \
1149     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1150   }
1151 
1152   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1153 
1154 #undef WRAP
1155 #define WRAP(INSN)                                                      \
1156   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1157     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1158   }                                                                     \
1159                                                                         \
1160   void INSN(Register Rd, Register Rn, Register Rm,                      \
1161              enum shift_kind kind, unsigned shift = 0) {                \
1162     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1163   }                                                                     \
1164                                                                         \
1165   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1166     Assembler::INSN(Rd, Rn, Rm);                                        \
1167   }                                                                     \
1168                                                                         \
1169   void INSN(Register Rd, Register Rn, Register Rm,                      \
1170            ext::operation option, int amount = 0) {                     \
1171     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1172   }
1173 
1174   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1175 
1176   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1177   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1178   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1179   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1180 
1181   void adrp(Register reg1, const Address &dest, uint64_t &byte_offset);
1182 
1183   void tableswitch(Register index, jint lowbound, jint highbound,
1184                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1185     adr(rscratch1, jumptable);
1186     subsw(rscratch2, index, lowbound);
1187     subsw(zr, rscratch2, highbound - lowbound);
1188     br(Assembler::HS, jumptable_end);
1189     add(rscratch1, rscratch1, rscratch2,
1190         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1191     br(rscratch1);
1192   }
1193 
1194   // Form an address from base + offset in Rd.  Rd may or may not
1195   // actually be used: you must use the Address that is returned.  It
1196   // is up to you to ensure that the shift provided matches the size
1197   // of your data.
1198   Address form_address(Register Rd, Register base, int64_t byte_offset, int shift);
1199 
1200   // Return true iff an address is within the 48-bit AArch64 address
1201   // space.
1202   bool is_valid_AArch64_address(address a) {
1203     return ((uint64_t)a >> 48) == 0;
1204   }
1205 
1206   // Load the base of the cardtable byte map into reg.
1207   void load_byte_map_base(Register reg);
1208 
1209   // Prolog generator routines to support switch between x86 code and
1210   // generated ARM code
1211 
1212   // routine to generate an x86 prolog for a stub function which
1213   // bootstraps into the generated ARM code which directly follows the
1214   // stub
1215   //
1216 
1217   public:
1218 
1219   void ldr_constant(Register dest, const Address &const_addr) {
1220     if (NearCpool) {
1221       ldr(dest, const_addr);
1222     } else {
1223       uint64_t offset;
1224       adrp(dest, InternalAddress(const_addr.target()), offset);
1225       ldr(dest, Address(dest, offset));
1226     }
1227   }
1228 
1229   address read_polling_page(Register r, relocInfo::relocType rtype);
1230   void get_polling_page(Register dest, relocInfo::relocType rtype);
1231 
1232   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1233   void update_byte_crc32(Register crc, Register val, Register table);
1234   void update_word_crc32(Register crc, Register v, Register tmp,
1235         Register table0, Register table1, Register table2, Register table3,
1236         bool upper = false);
1237 
1238   address has_negatives(Register ary1, Register len, Register result);
1239 
1240   address arrays_equals(Register a1, Register a2, Register result, Register cnt1,
1241                         Register tmp1, Register tmp2, Register tmp3, int elem_size);
1242 
1243   void string_equals(Register a1, Register a2, Register result, Register cnt1,
1244                      int elem_size);
1245 
1246   void fill_words(Register base, Register cnt, Register value);
1247   void zero_words(Register base, uint64_t cnt);
1248   address zero_words(Register ptr, Register cnt);
1249   void zero_dcache_blocks(Register base, Register cnt);
1250 
1251   static const int zero_words_block_size;
1252 
1253   address byte_array_inflate(Register src, Register dst, Register len,
1254                              FloatRegister vtmp1, FloatRegister vtmp2,
1255                              FloatRegister vtmp3, Register tmp4);
1256 
1257   void char_array_compress(Register src, Register dst, Register len,
1258                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1259                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1260                            Register result);
1261 
1262   void encode_iso_array(Register src, Register dst,
1263                         Register len, Register result,
1264                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1265                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1266   void fast_log(FloatRegister vtmp0, FloatRegister vtmp1, FloatRegister vtmp2,
1267                 FloatRegister vtmp3, FloatRegister vtmp4, FloatRegister vtmp5,
1268                 FloatRegister tmpC1, FloatRegister tmpC2, FloatRegister tmpC3,
1269                 FloatRegister tmpC4, Register tmp1, Register tmp2,
1270                 Register tmp3, Register tmp4, Register tmp5);
1271   void generate_dsin_dcos(bool isCos, address npio2_hw, address two_over_pi,
1272       address pio2, address dsin_coef, address dcos_coef);
1273  private:
1274   // begin trigonometric functions support block
1275   void generate__ieee754_rem_pio2(address npio2_hw, address two_over_pi, address pio2);
1276   void generate__kernel_rem_pio2(address two_over_pi, address pio2);
1277   void generate_kernel_sin(FloatRegister x, bool iyIsOne, address dsin_coef);
1278   void generate_kernel_cos(FloatRegister x, address dcos_coef);
1279   // end trigonometric functions support block
1280   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1281                        Register src1, Register src2);
1282   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1283     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1284   }
1285   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1286                              Register y, Register y_idx, Register z,
1287                              Register carry, Register product,
1288                              Register idx, Register kdx);
1289   void multiply_128_x_128_loop(Register y, Register z,
1290                                Register carry, Register carry2,
1291                                Register idx, Register jdx,
1292                                Register yz_idx1, Register yz_idx2,
1293                                Register tmp, Register tmp3, Register tmp4,
1294                                Register tmp7, Register product_hi);
1295   void kernel_crc32_using_crc32(Register crc, Register buf,
1296         Register len, Register tmp0, Register tmp1, Register tmp2,
1297         Register tmp3);
1298   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1299         Register len, Register tmp0, Register tmp1, Register tmp2,
1300         Register tmp3);
1301 
1302   void ghash_modmul (FloatRegister result,
1303                      FloatRegister result_lo, FloatRegister result_hi, FloatRegister b,
1304                      FloatRegister a, FloatRegister vzr, FloatRegister a1_xor_a0, FloatRegister p,
1305                      FloatRegister t1, FloatRegister t2, FloatRegister t3);
1306   void ghash_load_wide(int index, Register data, FloatRegister result, FloatRegister state);
1307 public:
1308   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1309                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1310                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1311   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1312   void ghash_multiply(FloatRegister result_lo, FloatRegister result_hi,
1313                       FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1314                       FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1315   void ghash_multiply_wide(int index,
1316                            FloatRegister result_lo, FloatRegister result_hi,
1317                            FloatRegister a, FloatRegister b, FloatRegister a1_xor_a0,
1318                            FloatRegister tmp1, FloatRegister tmp2, FloatRegister tmp3);
1319   void ghash_reduce(FloatRegister result, FloatRegister lo, FloatRegister hi,
1320                     FloatRegister p, FloatRegister z, FloatRegister t1);
1321   void ghash_reduce_wide(int index, FloatRegister result, FloatRegister lo, FloatRegister hi,
1322                     FloatRegister p, FloatRegister z, FloatRegister t1);
1323   void ghash_processBlocks_wide(address p, Register state, Register subkeyH,
1324                                 Register data, Register blocks, int unrolls);
1325 
1326 
1327   void aesenc_loadkeys(Register key, Register keylen);
1328   void aesecb_encrypt(Register from, Register to, Register keylen,
1329                       FloatRegister data = v0, int unrolls = 1);
1330   void aesecb_decrypt(Register from, Register to, Register key, Register keylen);
1331   void aes_round(FloatRegister input, FloatRegister subkey);
1332 
1333   // Place an ISB after code may have been modified due to a safepoint.
1334   void safepoint_isb();
1335 
1336 private:
1337   // Return the effective address r + (r1 << ext) + offset.
1338   // Uses rscratch2.
1339   Address offsetted_address(Register r, Register r1, Address::extend ext,
1340                             int offset, int size);
1341 
1342 private:
1343   // Returns an address on the stack which is reachable with a ldr/str of size
1344   // Uses rscratch2 if the address is not directly reachable
1345   Address spill_address(int size, int offset, Register tmp=rscratch2);
1346   Address sve_spill_address(int sve_reg_size_in_bytes, int offset, Register tmp=rscratch2);
1347 
1348   bool merge_alignment_check(Register base, size_t size, int64_t cur_offset, int64_t prev_offset) const;
1349 
1350   // Check whether two loads/stores can be merged into ldp/stp.
1351   bool ldst_can_merge(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store) const;
1352 
1353   // Merge current load/store with previous load/store into ldp/stp.
1354   void merge_ldst(Register rx, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1355 
1356   // Try to merge two loads/stores into ldp/stp. If success, returns true else false.
1357   bool try_merge_ldst(Register rt, const Address &adr, size_t cur_size_in_bytes, bool is_store);
1358 
1359 public:
1360   void spill(Register Rx, bool is64, int offset) {
1361     if (is64) {
1362       str(Rx, spill_address(8, offset));
1363     } else {
1364       strw(Rx, spill_address(4, offset));
1365     }
1366   }
1367   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1368     str(Vx, T, spill_address(1 << (int)T, offset));
1369   }
1370 
1371   void spill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1372     sve_str(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1373   }
1374   void spill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1375     sve_str(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1376   }
1377 
1378   void unspill(Register Rx, bool is64, int offset) {
1379     if (is64) {
1380       ldr(Rx, spill_address(8, offset));
1381     } else {
1382       ldrw(Rx, spill_address(4, offset));
1383     }
1384   }
1385   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1386     ldr(Vx, T, spill_address(1 << (int)T, offset));
1387   }
1388 
1389   void unspill_sve_vector(FloatRegister Zx, int offset, int vector_reg_size_in_bytes) {
1390     sve_ldr(Zx, sve_spill_address(vector_reg_size_in_bytes, offset));
1391   }
1392   void unspill_sve_predicate(PRegister pr, int offset, int predicate_reg_size_in_bytes) {
1393     sve_ldr(pr, sve_spill_address(predicate_reg_size_in_bytes, offset));
1394   }
1395 
1396   void spill_copy128(int src_offset, int dst_offset,
1397                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1398     if (src_offset < 512 && (src_offset & 7) == 0 &&
1399         dst_offset < 512 && (dst_offset & 7) == 0) {
1400       ldp(tmp1, tmp2, Address(sp, src_offset));
1401       stp(tmp1, tmp2, Address(sp, dst_offset));
1402     } else {
1403       unspill(tmp1, true, src_offset);
1404       spill(tmp1, true, dst_offset);
1405       unspill(tmp1, true, src_offset+8);
1406       spill(tmp1, true, dst_offset+8);
1407     }
1408   }
1409   void spill_copy_sve_vector_stack_to_stack(int src_offset, int dst_offset,
1410                                             int sve_vec_reg_size_in_bytes) {
1411     assert(sve_vec_reg_size_in_bytes % 16 == 0, "unexpected sve vector reg size");
1412     for (int i = 0; i < sve_vec_reg_size_in_bytes / 16; i++) {
1413       spill_copy128(src_offset, dst_offset);
1414       src_offset += 16;
1415       dst_offset += 16;
1416     }
1417   }
1418   void spill_copy_sve_predicate_stack_to_stack(int src_offset, int dst_offset,
1419                                                int sve_predicate_reg_size_in_bytes) {
1420     sve_ldr(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, src_offset));
1421     sve_str(ptrue, sve_spill_address(sve_predicate_reg_size_in_bytes, dst_offset));
1422     reinitialize_ptrue();
1423   }
1424   void cache_wb(Address line);
1425   void cache_wbsync(bool is_pre);
1426 
1427   // Code for java.lang.Thread::onSpinWait() intrinsic.
1428   void spin_wait();
1429 
1430 private:
1431   // Check the current thread doesn't need a cross modify fence.
1432   void verify_cross_modify_fence_not_required() PRODUCT_RETURN;
1433 
1434 };
1435 
1436 #ifdef ASSERT
1437 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1438 #endif
1439 
1440 /**
1441  * class SkipIfEqual:
1442  *
1443  * Instantiating this class will result in assembly code being output that will
1444  * jump around any code emitted between the creation of the instance and it's
1445  * automatic destruction at the end of a scope block, depending on the value of
1446  * the flag passed to the constructor, which will be checked at run-time.
1447  */
1448 class SkipIfEqual {
1449  private:
1450   MacroAssembler* _masm;
1451   Label _label;
1452 
1453  public:
1454    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1455    ~SkipIfEqual();
1456 };
1457 
1458 struct tableswitch {
1459   Register _reg;
1460   int _insn_index; jint _first_key; jint _last_key;
1461   Label _after;
1462   Label _branches;
1463 };
1464 
1465 #endif // CPU_AARCH64_MACROASSEMBLER_AARCH64_HPP