1 /*
   2  * Copyright (c) 2008, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "asm/assembler.inline.hpp"
  27 #include "code/debugInfoRec.hpp"
  28 #include "code/icBuffer.hpp"
  29 #include "code/vtableStubs.hpp"
  30 #include "compiler/oopMap.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 #include "logging/log.hpp"
  33 #include "memory/resourceArea.hpp"
  34 #include "oops/compiledICHolder.hpp"
  35 #include "oops/klass.inline.hpp"
  36 #include "prims/methodHandles.hpp"
  37 #include "runtime/jniHandles.hpp"
  38 #include "runtime/sharedRuntime.hpp"
  39 #include "runtime/safepointMechanism.hpp"
  40 #include "runtime/stubRoutines.hpp"
  41 #include "runtime/vframeArray.hpp"
  42 #include "utilities/align.hpp"
  43 #include "utilities/powerOfTwo.hpp"
  44 #include "vmreg_arm.inline.hpp"
  45 #ifdef COMPILER1
  46 #include "c1/c1_Runtime1.hpp"
  47 #endif
  48 #ifdef COMPILER2
  49 #include "opto/runtime.hpp"
  50 #endif
  51 
  52 #define __ masm->
  53 
  54 class RegisterSaver {
  55 public:
  56 
  57   // Special registers:
  58   //              32-bit ARM     64-bit ARM
  59   //  Rthread:       R10            R28
  60   //  LR:            R14            R30
  61 
  62   // Rthread is callee saved in the C ABI and never changed by compiled code:
  63   // no need to save it.
  64 
  65   // 2 slots for LR: the one at LR_offset and an other one at R14/R30_offset.
  66   // The one at LR_offset is a return address that is needed by stack walking.
  67   // A c2 method uses LR as a standard register so it may be live when we
  68   // branch to the runtime. The slot at R14/R30_offset is for the value of LR
  69   // in case it's live in the method we are coming from.
  70 
  71 
  72   enum RegisterLayout {
  73     fpu_save_size = FloatRegisterImpl::number_of_registers,
  74 #ifndef __SOFTFP__
  75     D0_offset = 0,
  76 #endif
  77     R0_offset = fpu_save_size,
  78     R1_offset,
  79     R2_offset,
  80     R3_offset,
  81     R4_offset,
  82     R5_offset,
  83     R6_offset,
  84 #if (FP_REG_NUM != 7)
  85     // if not saved as FP
  86     R7_offset,
  87 #endif
  88     R8_offset,
  89     R9_offset,
  90 #if (FP_REG_NUM != 11)
  91     // if not saved as FP
  92     R11_offset,
  93 #endif
  94     R12_offset,
  95     R14_offset,
  96     FP_offset,
  97     LR_offset,
  98     reg_save_size,
  99 
 100     Rmethod_offset = R9_offset,
 101     Rtemp_offset = R12_offset,
 102   };
 103 
 104   // all regs but Rthread (R10), FP (R7 or R11), SP and PC
 105   // (altFP_7_11 is the one amoung R7 and R11 which is not FP)
 106 #define SAVED_BASE_REGS (RegisterSet(R0, R6) | RegisterSet(R8, R9) | RegisterSet(R12) | R14 | altFP_7_11)
 107 
 108 
 109   //  When LR may be live in the nmethod from which we are comming
 110   //  then lr_saved is true, the return address is saved before the
 111   //  call to save_live_register by the caller and LR contains the
 112   //  live value.
 113 
 114   static OopMap* save_live_registers(MacroAssembler* masm,
 115                                      int* total_frame_words,
 116                                      bool lr_saved = false);
 117   static void restore_live_registers(MacroAssembler* masm, bool restore_lr = true);
 118 
 119 };
 120 
 121 
 122 
 123 
 124 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm,
 125                                            int* total_frame_words,
 126                                            bool lr_saved) {
 127   *total_frame_words = reg_save_size;
 128 
 129   OopMapSet *oop_maps = new OopMapSet();
 130   OopMap* map = new OopMap(VMRegImpl::slots_per_word * (*total_frame_words), 0);
 131 
 132   if (lr_saved) {
 133     __ push(RegisterSet(FP));
 134   } else {
 135     __ push(RegisterSet(FP) | RegisterSet(LR));
 136   }
 137   __ push(SAVED_BASE_REGS);
 138   if (HaveVFP) {
 139     if (VM_Version::has_vfp3_32()) {
 140       __ fpush(FloatRegisterSet(D16, 16));
 141     } else {
 142       if (FloatRegisterImpl::number_of_registers > 32) {
 143         assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");
 144         __ sub(SP, SP, 32 * wordSize);
 145       }
 146     }
 147     __ fpush(FloatRegisterSet(D0, 16));
 148   } else {
 149     __ sub(SP, SP, fpu_save_size * wordSize);
 150   }
 151 
 152   int i;
 153   int j=0;
 154   for (i = R0_offset; i <= R9_offset; i++) {
 155     if (j == FP_REG_NUM) {
 156       // skip the FP register, managed below.
 157       j++;
 158     }
 159     map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
 160     j++;
 161   }
 162   assert(j == R10->encoding(), "must be");
 163 #if (FP_REG_NUM != 11)
 164   // add R11, if not managed as FP
 165   map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
 166 #endif
 167   map->set_callee_saved(VMRegImpl::stack2reg(R12_offset), R12->as_VMReg());
 168   map->set_callee_saved(VMRegImpl::stack2reg(R14_offset), R14->as_VMReg());
 169   if (HaveVFP) {
 170     for (i = 0; i < (VM_Version::has_vfp3_32() ? 64 : 32); i+=2) {
 171       map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
 172       map->set_callee_saved(VMRegImpl::stack2reg(i + 1), as_FloatRegister(i)->as_VMReg()->next());
 173     }
 174   }
 175 
 176   return map;
 177 }
 178 
 179 void RegisterSaver::restore_live_registers(MacroAssembler* masm, bool restore_lr) {
 180   if (HaveVFP) {
 181     __ fpop(FloatRegisterSet(D0, 16));
 182     if (VM_Version::has_vfp3_32()) {
 183       __ fpop(FloatRegisterSet(D16, 16));
 184     } else {
 185       if (FloatRegisterImpl::number_of_registers > 32) {
 186         assert(FloatRegisterImpl::number_of_registers == 64, "nb fp registers should be 64");
 187         __ add(SP, SP, 32 * wordSize);
 188       }
 189     }
 190   } else {
 191     __ add(SP, SP, fpu_save_size * wordSize);
 192   }
 193   __ pop(SAVED_BASE_REGS);
 194   if (restore_lr) {
 195     __ pop(RegisterSet(FP) | RegisterSet(LR));
 196   } else {
 197     __ pop(RegisterSet(FP));
 198   }
 199 }
 200 
 201 
 202 static void push_result_registers(MacroAssembler* masm, BasicType ret_type) {
 203 #ifdef __ABI_HARD__
 204   if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
 205     __ sub(SP, SP, 8);
 206     __ fstd(D0, Address(SP));
 207     return;
 208   }
 209 #endif // __ABI_HARD__
 210   __ raw_push(R0, R1);
 211 }
 212 
 213 static void pop_result_registers(MacroAssembler* masm, BasicType ret_type) {
 214 #ifdef __ABI_HARD__
 215   if (ret_type == T_DOUBLE || ret_type == T_FLOAT) {
 216     __ fldd(D0, Address(SP));
 217     __ add(SP, SP, 8);
 218     return;
 219   }
 220 #endif // __ABI_HARD__
 221   __ raw_pop(R0, R1);
 222 }
 223 
 224 static void push_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
 225   // R1-R3 arguments need to be saved, but we push 4 registers for 8-byte alignment
 226   __ push(RegisterSet(R0, R3));
 227 
 228   // preserve arguments
 229   // Likely not needed as the locking code won't probably modify volatile FP registers,
 230   // but there is no way to guarantee that
 231   if (fp_regs_in_arguments) {
 232     // convert fp_regs_in_arguments to a number of double registers
 233     int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
 234     __ fpush_hardfp(FloatRegisterSet(D0, double_regs_num));
 235   }
 236 }
 237 
 238 static void pop_param_registers(MacroAssembler* masm, int fp_regs_in_arguments) {
 239   if (fp_regs_in_arguments) {
 240     int double_regs_num = (fp_regs_in_arguments + 1) >> 1;
 241     __ fpop_hardfp(FloatRegisterSet(D0, double_regs_num));
 242   }
 243   __ pop(RegisterSet(R0, R3));
 244 }
 245 
 246 
 247 
 248 // Is vector's size (in bytes) bigger than a size saved by default?
 249 // All vector registers are saved by default on ARM.
 250 bool SharedRuntime::is_wide_vector(int size) {
 251   return false;
 252 }
 253 
 254 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
 255                                         VMRegPair *regs,
 256                                         VMRegPair *regs2,
 257                                         int total_args_passed) {
 258   assert(regs2 == NULL, "not needed on arm");
 259 
 260   int slot = 0;
 261   int ireg = 0;
 262 #ifdef __ABI_HARD__
 263   int fp_slot = 0;
 264   int single_fpr_slot = 0;
 265 #endif // __ABI_HARD__
 266   for (int i = 0; i < total_args_passed; i++) {
 267     switch (sig_bt[i]) {
 268     case T_SHORT:
 269     case T_CHAR:
 270     case T_BYTE:
 271     case T_BOOLEAN:
 272     case T_INT:
 273     case T_ARRAY:
 274     case T_OBJECT:
 275     case T_ADDRESS:
 276     case T_METADATA:
 277 #ifndef __ABI_HARD__
 278     case T_FLOAT:
 279 #endif // !__ABI_HARD__
 280       if (ireg < 4) {
 281         Register r = as_Register(ireg);
 282         regs[i].set1(r->as_VMReg());
 283         ireg++;
 284       } else {
 285         regs[i].set1(VMRegImpl::stack2reg(slot));
 286         slot++;
 287       }
 288       break;
 289     case T_LONG:
 290 #ifndef __ABI_HARD__
 291     case T_DOUBLE:
 292 #endif // !__ABI_HARD__
 293       assert((i + 1) < total_args_passed && sig_bt[i+1] == T_VOID, "missing Half" );
 294       if (ireg <= 2) {
 295 #if (ALIGN_WIDE_ARGUMENTS == 1)
 296         if(ireg & 1) ireg++;  // Aligned location required
 297 #endif
 298         Register r1 = as_Register(ireg);
 299         Register r2 = as_Register(ireg + 1);
 300         regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
 301         ireg += 2;
 302 #if (ALIGN_WIDE_ARGUMENTS == 0)
 303       } else if (ireg == 3) {
 304         // uses R3 + one stack slot
 305         Register r = as_Register(ireg);
 306         regs[i].set_pair(VMRegImpl::stack2reg(slot), r->as_VMReg());
 307         ireg += 1;
 308         slot += 1;
 309 #endif
 310       } else {
 311         if (slot & 1) slot++; // Aligned location required
 312         regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
 313         slot += 2;
 314         ireg = 4;
 315       }
 316       break;
 317     case T_VOID:
 318       regs[i].set_bad();
 319       break;
 320 #ifdef __ABI_HARD__
 321     case T_FLOAT:
 322       if ((fp_slot < 16)||(single_fpr_slot & 1)) {
 323         if ((single_fpr_slot & 1) == 0) {
 324           single_fpr_slot = fp_slot;
 325           fp_slot += 2;
 326         }
 327         FloatRegister r = as_FloatRegister(single_fpr_slot);
 328         single_fpr_slot++;
 329         regs[i].set1(r->as_VMReg());
 330       } else {
 331         regs[i].set1(VMRegImpl::stack2reg(slot));
 332         slot++;
 333       }
 334       break;
 335     case T_DOUBLE:
 336       assert(ALIGN_WIDE_ARGUMENTS == 1, "ABI_HARD not supported with unaligned wide arguments");
 337       if (fp_slot <= 14) {
 338         FloatRegister r1 = as_FloatRegister(fp_slot);
 339         FloatRegister r2 = as_FloatRegister(fp_slot+1);
 340         regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
 341         fp_slot += 2;
 342       } else {
 343         if(slot & 1) slot++;
 344         regs[i].set_pair(VMRegImpl::stack2reg(slot+1), VMRegImpl::stack2reg(slot));
 345         slot += 2;
 346         single_fpr_slot = 16;
 347       }
 348       break;
 349 #endif // __ABI_HARD__
 350     default:
 351       ShouldNotReachHere();
 352     }
 353   }
 354   return slot;
 355 }
 356 
 357 int SharedRuntime::vector_calling_convention(VMRegPair *regs,
 358                                              uint num_bits,
 359                                              uint total_args_passed) {
 360   Unimplemented();
 361   return 0;
 362 }
 363 
 364 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
 365                                            VMRegPair *regs,
 366                                            int total_args_passed) {
 367 #ifdef __SOFTFP__
 368   // soft float is the same as the C calling convention.
 369   return c_calling_convention(sig_bt, regs, NULL, total_args_passed);
 370 #endif // __SOFTFP__
 371   int slot = 0;
 372   int ireg = 0;
 373   int freg = 0;
 374   int single_fpr = 0;
 375 
 376   for (int i = 0; i < total_args_passed; i++) {
 377     switch (sig_bt[i]) {
 378     case T_SHORT:
 379     case T_CHAR:
 380     case T_BYTE:
 381     case T_BOOLEAN:
 382     case T_INT:
 383     case T_ARRAY:
 384     case T_OBJECT:
 385     case T_ADDRESS:
 386       if (ireg < 4) {
 387         Register r = as_Register(ireg++);
 388         regs[i].set1(r->as_VMReg());
 389       } else {
 390         regs[i].set1(VMRegImpl::stack2reg(slot++));
 391       }
 392       break;
 393     case T_FLOAT:
 394       // C2 utilizes S14/S15 for mem-mem moves
 395       if ((freg < 16 COMPILER2_PRESENT(-2)) || (single_fpr & 1)) {
 396         if ((single_fpr & 1) == 0) {
 397           single_fpr = freg;
 398           freg += 2;
 399         }
 400         FloatRegister r = as_FloatRegister(single_fpr++);
 401         regs[i].set1(r->as_VMReg());
 402       } else {
 403         regs[i].set1(VMRegImpl::stack2reg(slot++));
 404       }
 405       break;
 406     case T_DOUBLE:
 407       // C2 utilizes S14/S15 for mem-mem moves
 408       if (freg <= 14 COMPILER2_PRESENT(-2)) {
 409         FloatRegister r1 = as_FloatRegister(freg);
 410         FloatRegister r2 = as_FloatRegister(freg + 1);
 411         regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
 412         freg += 2;
 413       } else {
 414         // Keep internally the aligned calling convention,
 415         // ignoring ALIGN_WIDE_ARGUMENTS
 416         if (slot & 1) slot++;
 417         regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
 418         slot += 2;
 419         single_fpr = 16;
 420       }
 421       break;
 422     case T_LONG:
 423       // Keep internally the aligned calling convention,
 424       // ignoring ALIGN_WIDE_ARGUMENTS
 425       if (ireg <= 2) {
 426         if (ireg & 1) ireg++;
 427         Register r1 = as_Register(ireg);
 428         Register r2 = as_Register(ireg + 1);
 429         regs[i].set_pair(r2->as_VMReg(), r1->as_VMReg());
 430         ireg += 2;
 431       } else {
 432         if (slot & 1) slot++;
 433         regs[i].set_pair(VMRegImpl::stack2reg(slot + 1), VMRegImpl::stack2reg(slot));
 434         slot += 2;
 435         ireg = 4;
 436       }
 437       break;
 438     case T_VOID:
 439       regs[i].set_bad();
 440       break;
 441     default:
 442       ShouldNotReachHere();
 443     }
 444   }
 445 
 446   if (slot & 1) slot++;
 447   return slot;
 448 }
 449 
 450 static void patch_callers_callsite(MacroAssembler *masm) {
 451   Label skip;
 452 
 453   __ ldr(Rtemp, Address(Rmethod, Method::code_offset()));
 454   __ cbz(Rtemp, skip);
 455 
 456   // Pushing an even number of registers for stack alignment.
 457   // Selecting R9, which had to be saved anyway for some platforms.
 458   __ push(RegisterSet(R0, R3) | R9 | LR);
 459   __ fpush_hardfp(FloatRegisterSet(D0, 8));
 460 
 461   __ mov(R0, Rmethod);
 462   __ mov(R1, LR);
 463   __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
 464 
 465   __ fpop_hardfp(FloatRegisterSet(D0, 8));
 466   __ pop(RegisterSet(R0, R3) | R9 | LR);
 467 
 468   __ bind(skip);
 469 }
 470 
 471 void SharedRuntime::gen_i2c_adapter(MacroAssembler *masm,
 472                                     int total_args_passed, int comp_args_on_stack,
 473                                     const BasicType *sig_bt, const VMRegPair *regs) {
 474   // TODO: ARM - May be can use ldm to load arguments
 475   const Register tmp = Rtemp; // avoid erasing R5_mh
 476 
 477   // Next assert may not be needed but safer. Extra analysis required
 478   // if this there is not enough free registers and we need to use R5 here.
 479   assert_different_registers(tmp, R5_mh);
 480 
 481   // 6243940 We might end up in handle_wrong_method if
 482   // the callee is deoptimized as we race thru here. If that
 483   // happens we don't want to take a safepoint because the
 484   // caller frame will look interpreted and arguments are now
 485   // "compiled" so it is much better to make this transition
 486   // invisible to the stack walking code. Unfortunately if
 487   // we try and find the callee by normal means a safepoint
 488   // is possible. So we stash the desired callee in the thread
 489   // and the vm will find there should this case occur.
 490   Address callee_target_addr(Rthread, JavaThread::callee_target_offset());
 491   __ str(Rmethod, callee_target_addr);
 492 
 493 
 494   assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, Rmethod);
 495 
 496   const Register initial_sp = Rmethod; // temporarily scratched
 497 
 498   // Old code was modifying R4 but this looks unsafe (particularly with JSR292)
 499   assert_different_registers(tmp, R0, R1, R2, R3, Rsender_sp, initial_sp);
 500 
 501   __ mov(initial_sp, SP);
 502 
 503   if (comp_args_on_stack) {
 504     __ sub_slow(SP, SP, comp_args_on_stack * VMRegImpl::stack_slot_size);
 505   }
 506   __ bic(SP, SP, StackAlignmentInBytes - 1);
 507 
 508   for (int i = 0; i < total_args_passed; i++) {
 509     if (sig_bt[i] == T_VOID) {
 510       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
 511       continue;
 512     }
 513     assert(!regs[i].second()->is_valid() || regs[i].first()->next() == regs[i].second(), "must be ordered");
 514     int arg_offset = Interpreter::expr_offset_in_bytes(total_args_passed - 1 - i);
 515 
 516     VMReg r_1 = regs[i].first();
 517     VMReg r_2 = regs[i].second();
 518     if (r_1->is_stack()) {
 519       int stack_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size;
 520       if (!r_2->is_valid()) {
 521         __ ldr(tmp, Address(initial_sp, arg_offset));
 522         __ str(tmp, Address(SP, stack_offset));
 523       } else {
 524         __ ldr(tmp, Address(initial_sp, arg_offset - Interpreter::stackElementSize));
 525         __ str(tmp, Address(SP, stack_offset));
 526         __ ldr(tmp, Address(initial_sp, arg_offset));
 527         __ str(tmp, Address(SP, stack_offset + wordSize));
 528       }
 529     } else if (r_1->is_Register()) {
 530       if (!r_2->is_valid()) {
 531         __ ldr(r_1->as_Register(), Address(initial_sp, arg_offset));
 532       } else {
 533         __ ldr(r_1->as_Register(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
 534         __ ldr(r_2->as_Register(), Address(initial_sp, arg_offset));
 535       }
 536     } else if (r_1->is_FloatRegister()) {
 537 #ifdef __SOFTFP__
 538       ShouldNotReachHere();
 539 #endif // __SOFTFP__
 540       if (!r_2->is_valid()) {
 541         __ flds(r_1->as_FloatRegister(), Address(initial_sp, arg_offset));
 542       } else {
 543         __ fldd(r_1->as_FloatRegister(), Address(initial_sp, arg_offset - Interpreter::stackElementSize));
 544       }
 545     } else {
 546       assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
 547     }
 548   }
 549 
 550   // restore Rmethod (scratched for initial_sp)
 551   __ ldr(Rmethod, callee_target_addr);
 552   __ ldr(PC, Address(Rmethod, Method::from_compiled_offset()));
 553 
 554 }
 555 
 556 static void gen_c2i_adapter(MacroAssembler *masm,
 557                             int total_args_passed,  int comp_args_on_stack,
 558                             const BasicType *sig_bt, const VMRegPair *regs,
 559                             Label& skip_fixup) {
 560   // TODO: ARM - May be can use stm to deoptimize arguments
 561   const Register tmp = Rtemp;
 562 
 563   patch_callers_callsite(masm);
 564   __ bind(skip_fixup);
 565 
 566   __ mov(Rsender_sp, SP); // not yet saved
 567 
 568 
 569   int extraspace = total_args_passed * Interpreter::stackElementSize;
 570   if (extraspace) {
 571     __ sub_slow(SP, SP, extraspace);
 572   }
 573 
 574   for (int i = 0; i < total_args_passed; i++) {
 575     if (sig_bt[i] == T_VOID) {
 576       assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
 577       continue;
 578     }
 579     int stack_offset = (total_args_passed - 1 - i) * Interpreter::stackElementSize;
 580 
 581     VMReg r_1 = regs[i].first();
 582     VMReg r_2 = regs[i].second();
 583     if (r_1->is_stack()) {
 584       int arg_offset = r_1->reg2stack() * VMRegImpl::stack_slot_size + extraspace;
 585       if (!r_2->is_valid()) {
 586         __ ldr(tmp, Address(SP, arg_offset));
 587         __ str(tmp, Address(SP, stack_offset));
 588       } else {
 589         __ ldr(tmp, Address(SP, arg_offset));
 590         __ str(tmp, Address(SP, stack_offset - Interpreter::stackElementSize));
 591         __ ldr(tmp, Address(SP, arg_offset + wordSize));
 592         __ str(tmp, Address(SP, stack_offset));
 593       }
 594     } else if (r_1->is_Register()) {
 595       if (!r_2->is_valid()) {
 596         __ str(r_1->as_Register(), Address(SP, stack_offset));
 597       } else {
 598         __ str(r_1->as_Register(), Address(SP, stack_offset - Interpreter::stackElementSize));
 599         __ str(r_2->as_Register(), Address(SP, stack_offset));
 600       }
 601     } else if (r_1->is_FloatRegister()) {
 602 #ifdef __SOFTFP__
 603       ShouldNotReachHere();
 604 #endif // __SOFTFP__
 605       if (!r_2->is_valid()) {
 606         __ fsts(r_1->as_FloatRegister(), Address(SP, stack_offset));
 607       } else {
 608         __ fstd(r_1->as_FloatRegister(), Address(SP, stack_offset - Interpreter::stackElementSize));
 609       }
 610     } else {
 611       assert(!r_1->is_valid() && !r_2->is_valid(), "must be");
 612     }
 613   }
 614 
 615   __ ldr(PC, Address(Rmethod, Method::interpreter_entry_offset()));
 616 
 617 }
 618 
 619 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
 620                                                             int total_args_passed,
 621                                                             int comp_args_on_stack,
 622                                                             const BasicType *sig_bt,
 623                                                             const VMRegPair *regs,
 624                                                             AdapterFingerPrint* fingerprint) {
 625   address i2c_entry = __ pc();
 626   gen_i2c_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs);
 627 
 628   address c2i_unverified_entry = __ pc();
 629   Label skip_fixup;
 630   const Register receiver       = R0;
 631   const Register holder_klass   = Rtemp; // XXX should be OK for C2 but not 100% sure
 632   const Register receiver_klass = R4;
 633 
 634   __ load_klass(receiver_klass, receiver);
 635   __ ldr(holder_klass, Address(Ricklass, CompiledICHolder::holder_klass_offset()));
 636   __ ldr(Rmethod, Address(Ricklass, CompiledICHolder::holder_metadata_offset()));
 637   __ cmp(receiver_klass, holder_klass);
 638 
 639   __ ldr(Rtemp, Address(Rmethod, Method::code_offset()), eq);
 640   __ cmp(Rtemp, 0, eq);
 641   __ b(skip_fixup, eq);
 642   __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, noreg, ne);
 643 
 644   address c2i_entry = __ pc();
 645   gen_c2i_adapter(masm, total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
 646 
 647   __ flush();
 648   return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
 649 }
 650 
 651 
 652 static int reg2offset_in(VMReg r) {
 653   // Account for saved FP and LR
 654   return r->reg2stack() * VMRegImpl::stack_slot_size + 2*wordSize;
 655 }
 656 
 657 static int reg2offset_out(VMReg r) {
 658   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 659 }
 660 
 661 
 662 static void verify_oop_args(MacroAssembler* masm,
 663                             const methodHandle& method,
 664                             const BasicType* sig_bt,
 665                             const VMRegPair* regs) {
 666   Register temp_reg = Rmethod;  // not part of any compiled calling seq
 667   if (VerifyOops) {
 668     for (int i = 0; i < method->size_of_parameters(); i++) {
 669       if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
 670         VMReg r = regs[i].first();
 671         assert(r->is_valid(), "bad oop arg");
 672         if (r->is_stack()) {
 673           __ ldr(temp_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
 674           __ verify_oop(temp_reg);
 675         } else {
 676           __ verify_oop(r->as_Register());
 677         }
 678       }
 679     }
 680   }
 681 }
 682 
 683 static void gen_special_dispatch(MacroAssembler* masm,
 684                                  const methodHandle& method,
 685                                  const BasicType* sig_bt,
 686                                  const VMRegPair* regs) {
 687   verify_oop_args(masm, method, sig_bt, regs);
 688   vmIntrinsics::ID iid = method->intrinsic_id();
 689 
 690   // Now write the args into the outgoing interpreter space
 691   bool     has_receiver   = false;
 692   Register receiver_reg   = noreg;
 693   int      member_arg_pos = -1;
 694   Register member_reg     = noreg;
 695   int      ref_kind       = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid);
 696   if (ref_kind != 0) {
 697     member_arg_pos = method->size_of_parameters() - 1;  // trailing MemberName argument
 698     member_reg = Rmethod;  // known to be free at this point
 699     has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind);
 700   } else if (iid == vmIntrinsics::_invokeBasic) {
 701     has_receiver = true;
 702   } else {
 703     fatal("unexpected intrinsic id %d", vmIntrinsics::as_int(iid));
 704   }
 705 
 706   if (member_reg != noreg) {
 707     // Load the member_arg into register, if necessary.
 708     SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs);
 709     VMReg r = regs[member_arg_pos].first();
 710     if (r->is_stack()) {
 711       __ ldr(member_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
 712     } else {
 713       // no data motion is needed
 714       member_reg = r->as_Register();
 715     }
 716   }
 717 
 718   if (has_receiver) {
 719     // Make sure the receiver is loaded into a register.
 720     assert(method->size_of_parameters() > 0, "oob");
 721     assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object");
 722     VMReg r = regs[0].first();
 723     assert(r->is_valid(), "bad receiver arg");
 724     if (r->is_stack()) {
 725       // Porting note:  This assumes that compiled calling conventions always
 726       // pass the receiver oop in a register.  If this is not true on some
 727       // platform, pick a temp and load the receiver from stack.
 728       assert(false, "receiver always in a register");
 729       receiver_reg = j_rarg0;  // known to be free at this point
 730       __ ldr(receiver_reg, Address(SP, r->reg2stack() * VMRegImpl::stack_slot_size));
 731     } else {
 732       // no data motion is needed
 733       receiver_reg = r->as_Register();
 734     }
 735   }
 736 
 737   // Figure out which address we are really jumping to:
 738   MethodHandles::generate_method_handle_dispatch(masm, iid,
 739                                                  receiver_reg, member_reg, /*for_compiler_entry:*/ true);
 740 }
 741 
 742 // ---------------------------------------------------------------------------
 743 // Generate a native wrapper for a given method.  The method takes arguments
 744 // in the Java compiled code convention, marshals them to the native
 745 // convention (handlizes oops, etc), transitions to native, makes the call,
 746 // returns to java state (possibly blocking), unhandlizes any result and
 747 // returns.
 748 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
 749                                                 const methodHandle& method,
 750                                                 int compile_id,
 751                                                 BasicType* in_sig_bt,
 752                                                 VMRegPair* in_regs,
 753                                                 BasicType ret_type) {
 754   if (method->is_method_handle_intrinsic()) {
 755     vmIntrinsics::ID iid = method->intrinsic_id();
 756     intptr_t start = (intptr_t)__ pc();
 757     int vep_offset = ((intptr_t)__ pc()) - start;
 758     gen_special_dispatch(masm,
 759                          method,
 760                          in_sig_bt,
 761                          in_regs);
 762     int frame_complete = ((intptr_t)__ pc()) - start;  // not complete, period
 763     __ flush();
 764     int stack_slots = SharedRuntime::out_preserve_stack_slots();  // no out slots at all, actually
 765     return nmethod::new_native_nmethod(method,
 766                                        compile_id,
 767                                        masm->code(),
 768                                        vep_offset,
 769                                        frame_complete,
 770                                        stack_slots / VMRegImpl::slots_per_word,
 771                                        in_ByteSize(-1),
 772                                        in_ByteSize(-1),
 773                                        (OopMapSet*)NULL);
 774   }
 775   // Arguments for JNI method include JNIEnv and Class if static
 776 
 777   // Usage of Rtemp should be OK since scratched by native call
 778 
 779   bool method_is_static = method->is_static();
 780 
 781   const int total_in_args = method->size_of_parameters();
 782   int total_c_args = total_in_args + (method_is_static ? 2 : 1);
 783 
 784   BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
 785   VMRegPair* out_regs   = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
 786 
 787   int argc = 0;
 788   out_sig_bt[argc++] = T_ADDRESS;
 789   if (method_is_static) {
 790     out_sig_bt[argc++] = T_OBJECT;
 791   }
 792 
 793   int i;
 794   for (i = 0; i < total_in_args; i++) {
 795     out_sig_bt[argc++] = in_sig_bt[i];
 796   }
 797 
 798   int out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args);
 799   int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
 800   // Since object arguments need to be wrapped, we must preserve space
 801   // for those object arguments which come in registers (GPR_PARAMS maximum)
 802   // plus one more slot for Klass handle (for static methods)
 803   int oop_handle_offset = stack_slots;
 804   stack_slots += (GPR_PARAMS + 1) * VMRegImpl::slots_per_word;
 805 
 806   // Plus a lock if needed
 807   int lock_slot_offset = 0;
 808   if (method->is_synchronized()) {
 809     lock_slot_offset = stack_slots;
 810     assert(sizeof(BasicLock) == wordSize, "adjust this code");
 811     stack_slots += VMRegImpl::slots_per_word;
 812   }
 813 
 814   // Space to save return address and FP
 815   stack_slots += 2 * VMRegImpl::slots_per_word;
 816 
 817   // Calculate the final stack size taking account of alignment
 818   stack_slots = align_up(stack_slots, StackAlignmentInBytes / VMRegImpl::stack_slot_size);
 819   int stack_size = stack_slots * VMRegImpl::stack_slot_size;
 820   int lock_slot_fp_offset = stack_size - 2 * wordSize -
 821     lock_slot_offset * VMRegImpl::stack_slot_size;
 822 
 823   // Unverified entry point
 824   address start = __ pc();
 825 
 826   // Inline cache check, same as in C1_MacroAssembler::inline_cache_check()
 827   const Register receiver = R0; // see receiverOpr()
 828   __ load_klass(Rtemp, receiver);
 829   __ cmp(Rtemp, Ricklass);
 830   Label verified;
 831 
 832   __ b(verified, eq); // jump over alignment no-ops too
 833   __ jump(SharedRuntime::get_ic_miss_stub(), relocInfo::runtime_call_type, Rtemp);
 834   __ align(CodeEntryAlignment);
 835 
 836   // Verified entry point
 837   __ bind(verified);
 838   int vep_offset = __ pc() - start;
 839 
 840 
 841   if ((InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) || (method->intrinsic_id() == vmIntrinsics::_identityHashCode)) {
 842     // Object.hashCode, System.identityHashCode can pull the hashCode from the header word
 843     // instead of doing a full VM transition once it's been computed.
 844     Label slow_case;
 845     const Register obj_reg = R0;
 846 
 847     // Unlike for Object.hashCode, System.identityHashCode is static method and
 848     // gets object as argument instead of the receiver.
 849     if (method->intrinsic_id() == vmIntrinsics::_identityHashCode) {
 850       assert(method->is_static(), "method should be static");
 851       // return 0 for null reference input, return val = R0 = obj_reg = 0
 852       __ cmp(obj_reg, 0);
 853       __ bx(LR, eq);
 854     }
 855 
 856     __ ldr(Rtemp, Address(obj_reg, oopDesc::mark_offset_in_bytes()));
 857 
 858     assert(markWord::unlocked_value == 1, "adjust this code");
 859     __ tbz(Rtemp, exact_log2(markWord::unlocked_value), slow_case);
 860 
 861     __ bics(Rtemp, Rtemp, ~markWord::hash_mask_in_place);
 862     __ mov(R0, AsmOperand(Rtemp, lsr, markWord::hash_shift), ne);
 863     __ bx(LR, ne);
 864 
 865     __ bind(slow_case);
 866   }
 867 
 868   // Bang stack pages
 869   __ arm_stack_overflow_check(stack_size, Rtemp);
 870 
 871   // Setup frame linkage
 872   __ raw_push(FP, LR);
 873   __ mov(FP, SP);
 874   __ sub_slow(SP, SP, stack_size - 2*wordSize);
 875 
 876   int frame_complete = __ pc() - start;
 877 
 878   OopMapSet* oop_maps = new OopMapSet();
 879   OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
 880   const int extra_args = method_is_static ? 2 : 1;
 881   int receiver_offset = -1;
 882   int fp_regs_in_arguments = 0;
 883 
 884   for (i = total_in_args; --i >= 0; ) {
 885     switch (in_sig_bt[i]) {
 886     case T_ARRAY:
 887     case T_OBJECT: {
 888       VMReg src = in_regs[i].first();
 889       VMReg dst = out_regs[i + extra_args].first();
 890       if (src->is_stack()) {
 891         assert(dst->is_stack(), "must be");
 892         assert(i != 0, "Incoming receiver is always in a register");
 893         __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
 894         __ cmp(Rtemp, 0);
 895         __ add(Rtemp, FP, reg2offset_in(src), ne);
 896         __ str(Rtemp, Address(SP, reg2offset_out(dst)));
 897         int offset_in_older_frame = src->reg2stack() + SharedRuntime::out_preserve_stack_slots();
 898         map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots));
 899       } else {
 900         int offset = oop_handle_offset * VMRegImpl::stack_slot_size;
 901         __ str(src->as_Register(), Address(SP, offset));
 902         map->set_oop(VMRegImpl::stack2reg(oop_handle_offset));
 903         if ((i == 0) && (!method_is_static)) {
 904           receiver_offset = offset;
 905         }
 906         oop_handle_offset += VMRegImpl::slots_per_word;
 907 
 908         if (dst->is_stack()) {
 909           __ movs(Rtemp, src->as_Register());
 910           __ add(Rtemp, SP, offset, ne);
 911           __ str(Rtemp, Address(SP, reg2offset_out(dst)));
 912         } else {
 913           __ movs(dst->as_Register(), src->as_Register());
 914           __ add(dst->as_Register(), SP, offset, ne);
 915         }
 916       }
 917     }
 918 
 919     case T_VOID:
 920       break;
 921 
 922 
 923 #ifdef __SOFTFP__
 924     case T_DOUBLE:
 925 #endif
 926     case T_LONG: {
 927       VMReg src_1 = in_regs[i].first();
 928       VMReg src_2 = in_regs[i].second();
 929       VMReg dst_1 = out_regs[i + extra_args].first();
 930       VMReg dst_2 = out_regs[i + extra_args].second();
 931 #if (ALIGN_WIDE_ARGUMENTS == 0)
 932       // C convention can mix a register and a stack slot for a
 933       // 64-bits native argument.
 934 
 935       // Note: following code should work independently of whether
 936       // the Java calling convention follows C convention or whether
 937       // it aligns 64-bit values.
 938       if (dst_2->is_Register()) {
 939         if (src_1->as_Register() != dst_1->as_Register()) {
 940           assert(src_1->as_Register() != dst_2->as_Register() &&
 941                  src_2->as_Register() != dst_2->as_Register(), "must be");
 942           __ mov(dst_2->as_Register(), src_2->as_Register());
 943           __ mov(dst_1->as_Register(), src_1->as_Register());
 944         } else {
 945           assert(src_2->as_Register() == dst_2->as_Register(), "must be");
 946         }
 947       } else if (src_2->is_Register()) {
 948         if (dst_1->is_Register()) {
 949           // dst mixes a register and a stack slot
 950           assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
 951           assert(src_1->as_Register() != dst_1->as_Register(), "must be");
 952           __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
 953           __ mov(dst_1->as_Register(), src_1->as_Register());
 954         } else {
 955           // registers to stack slots
 956           assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
 957           __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
 958           __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
 959         }
 960       } else if (src_1->is_Register()) {
 961         if (dst_1->is_Register()) {
 962           // src and dst must be R3 + stack slot
 963           assert(dst_1->as_Register() == src_1->as_Register(), "must be");
 964           __ ldr(Rtemp,    Address(FP, reg2offset_in(src_2)));
 965           __ str(Rtemp,    Address(SP, reg2offset_out(dst_2)));
 966         } else {
 967           // <R3,stack> -> <stack,stack>
 968           assert(dst_2->is_stack() && src_2->is_stack(), "must be");
 969           __ ldr(LR, Address(FP, reg2offset_in(src_2)));
 970           __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
 971           __ str(LR, Address(SP, reg2offset_out(dst_2)));
 972         }
 973       } else {
 974         assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
 975         __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
 976         __ ldr(LR,    Address(FP, reg2offset_in(src_2)));
 977         __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
 978         __ str(LR,    Address(SP, reg2offset_out(dst_2)));
 979       }
 980 #else // ALIGN_WIDE_ARGUMENTS
 981       if (src_1->is_stack()) {
 982         assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
 983         __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
 984         __ ldr(LR,    Address(FP, reg2offset_in(src_2)));
 985         __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
 986         __ str(LR,    Address(SP, reg2offset_out(dst_2)));
 987       } else if (dst_1->is_stack()) {
 988         assert(dst_2->is_stack() && src_1->is_Register() && src_2->is_Register(), "must be");
 989         __ str(src_1->as_Register(), Address(SP, reg2offset_out(dst_1)));
 990         __ str(src_2->as_Register(), Address(SP, reg2offset_out(dst_2)));
 991       } else if (src_1->as_Register() == dst_1->as_Register()) {
 992         assert(src_2->as_Register() == dst_2->as_Register(), "must be");
 993       } else {
 994         assert(src_1->as_Register() != dst_2->as_Register() &&
 995                src_2->as_Register() != dst_2->as_Register(), "must be");
 996         __ mov(dst_2->as_Register(), src_2->as_Register());
 997         __ mov(dst_1->as_Register(), src_1->as_Register());
 998       }
 999 #endif // ALIGN_WIDE_ARGUMENTS
1000       break;
1001     }
1002 
1003 #if (!defined __SOFTFP__ && !defined __ABI_HARD__)
1004     case T_FLOAT: {
1005       VMReg src = in_regs[i].first();
1006       VMReg dst = out_regs[i + extra_args].first();
1007       if (src->is_stack()) {
1008         assert(dst->is_stack(), "must be");
1009         __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1010         __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1011       } else if (dst->is_stack()) {
1012         __ fsts(src->as_FloatRegister(), Address(SP, reg2offset_out(dst)));
1013       } else {
1014         assert(src->is_FloatRegister() && dst->is_Register(), "must be");
1015         __ fmrs(dst->as_Register(), src->as_FloatRegister());
1016       }
1017       break;
1018     }
1019 
1020     case T_DOUBLE: {
1021       VMReg src_1 = in_regs[i].first();
1022       VMReg src_2 = in_regs[i].second();
1023       VMReg dst_1 = out_regs[i + extra_args].first();
1024       VMReg dst_2 = out_regs[i + extra_args].second();
1025       if (src_1->is_stack()) {
1026         assert(src_2->is_stack() && dst_1->is_stack() && dst_2->is_stack(), "must be");
1027         __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
1028         __ ldr(LR,    Address(FP, reg2offset_in(src_2)));
1029         __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
1030         __ str(LR,    Address(SP, reg2offset_out(dst_2)));
1031       } else if (dst_1->is_stack()) {
1032         assert(dst_2->is_stack() && src_1->is_FloatRegister(), "must be");
1033         __ fstd(src_1->as_FloatRegister(), Address(SP, reg2offset_out(dst_1)));
1034 #if (ALIGN_WIDE_ARGUMENTS == 0)
1035       } else if (dst_2->is_stack()) {
1036         assert(! src_2->is_stack(), "must be"); // assuming internal java convention is aligned
1037         // double register must go into R3 + one stack slot
1038         __ fmrrd(dst_1->as_Register(), Rtemp, src_1->as_FloatRegister());
1039         __ str(Rtemp, Address(SP, reg2offset_out(dst_2)));
1040 #endif
1041       } else {
1042         assert(src_1->is_FloatRegister() && dst_1->is_Register() && dst_2->is_Register(), "must be");
1043         __ fmrrd(dst_1->as_Register(), dst_2->as_Register(), src_1->as_FloatRegister());
1044       }
1045       break;
1046     }
1047 #endif // __SOFTFP__
1048 
1049 #ifdef __ABI_HARD__
1050     case T_FLOAT: {
1051       VMReg src = in_regs[i].first();
1052       VMReg dst = out_regs[i + extra_args].first();
1053       if (src->is_stack()) {
1054         if (dst->is_stack()) {
1055           __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1056           __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1057         } else {
1058           // C2 Java calling convention does not populate S14 and S15, therefore
1059           // those need to be loaded from stack here
1060           __ flds(dst->as_FloatRegister(), Address(FP, reg2offset_in(src)));
1061           fp_regs_in_arguments++;
1062         }
1063       } else {
1064         assert(src->is_FloatRegister(), "must be");
1065         fp_regs_in_arguments++;
1066       }
1067       break;
1068     }
1069     case T_DOUBLE: {
1070       VMReg src_1 = in_regs[i].first();
1071       VMReg src_2 = in_regs[i].second();
1072       VMReg dst_1 = out_regs[i + extra_args].first();
1073       VMReg dst_2 = out_regs[i + extra_args].second();
1074       if (src_1->is_stack()) {
1075         if (dst_1->is_stack()) {
1076           assert(dst_2->is_stack(), "must be");
1077           __ ldr(Rtemp, Address(FP, reg2offset_in(src_1)));
1078           __ ldr(LR,    Address(FP, reg2offset_in(src_2)));
1079           __ str(Rtemp, Address(SP, reg2offset_out(dst_1)));
1080           __ str(LR,    Address(SP, reg2offset_out(dst_2)));
1081         } else {
1082           // C2 Java calling convention does not populate S14 and S15, therefore
1083           // those need to be loaded from stack here
1084           __ fldd(dst_1->as_FloatRegister(), Address(FP, reg2offset_in(src_1)));
1085           fp_regs_in_arguments += 2;
1086         }
1087       } else {
1088         assert(src_1->is_FloatRegister() && src_2->is_FloatRegister(), "must be");
1089         fp_regs_in_arguments += 2;
1090       }
1091       break;
1092     }
1093 #endif // __ABI_HARD__
1094 
1095     default: {
1096       assert(in_sig_bt[i] != T_ADDRESS, "found T_ADDRESS in java args");
1097       VMReg src = in_regs[i].first();
1098       VMReg dst = out_regs[i + extra_args].first();
1099       if (src->is_stack()) {
1100         assert(dst->is_stack(), "must be");
1101         __ ldr(Rtemp, Address(FP, reg2offset_in(src)));
1102         __ str(Rtemp, Address(SP, reg2offset_out(dst)));
1103       } else if (dst->is_stack()) {
1104         __ str(src->as_Register(), Address(SP, reg2offset_out(dst)));
1105       } else {
1106         assert(src->is_Register() && dst->is_Register(), "must be");
1107         __ mov(dst->as_Register(), src->as_Register());
1108       }
1109     }
1110     }
1111   }
1112 
1113   // Get Klass mirror
1114   int klass_offset = -1;
1115   if (method_is_static) {
1116     klass_offset = oop_handle_offset * VMRegImpl::stack_slot_size;
1117     __ mov_oop(Rtemp, JNIHandles::make_local(method->method_holder()->java_mirror()));
1118     __ add(c_rarg1, SP, klass_offset);
1119     __ str(Rtemp, Address(SP, klass_offset));
1120     map->set_oop(VMRegImpl::stack2reg(oop_handle_offset));
1121   }
1122 
1123   // the PC offset given to add_gc_map must match the PC saved in set_last_Java_frame
1124   int pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp);
1125   assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1126   oop_maps->add_gc_map(pc_offset, map);
1127 
1128   // Order last_Java_pc store with the thread state transition (to _thread_in_native)
1129   __ membar(MacroAssembler::StoreStore, Rtemp);
1130 
1131   // RedefineClasses() tracing support for obsolete method entry
1132   if (log_is_enabled(Trace, redefine, class, obsolete)) {
1133     __ save_caller_save_registers();
1134     __ mov(R0, Rthread);
1135     __ mov_metadata(R1, method());
1136     __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), R0, R1);
1137     __ restore_caller_save_registers();
1138   }
1139 
1140   const Register sync_handle = R5;
1141   const Register sync_obj    = R6;
1142   const Register disp_hdr    = altFP_7_11;
1143   const Register tmp         = R8;
1144 
1145   Label slow_lock, lock_done, fast_lock;
1146   if (method->is_synchronized()) {
1147     // The first argument is a handle to sync object (a class or an instance)
1148     __ ldr(sync_obj, Address(R1));
1149     // Remember the handle for the unlocking code
1150     __ mov(sync_handle, R1);
1151 
1152     const Register mark = tmp;
1153     // On MP platforms the next load could return a 'stale' value if the memory location has been modified by another thread.
1154     // That would be acceptable as either CAS or slow case path is taken in that case
1155 
1156     __ ldr(mark, Address(sync_obj, oopDesc::mark_offset_in_bytes()));
1157     __ sub(disp_hdr, FP, lock_slot_fp_offset);
1158     __ tst(mark, markWord::unlocked_value);
1159     __ b(fast_lock, ne);
1160 
1161     // Check for recursive lock
1162     // See comments in InterpreterMacroAssembler::lock_object for
1163     // explanations on the fast recursive locking check.
1164     // Check independently the low bits and the distance to SP
1165     // -1- test low 2 bits
1166     __ movs(Rtemp, AsmOperand(mark, lsl, 30));
1167     // -2- test (hdr - SP) if the low two bits are 0
1168     __ sub(Rtemp, mark, SP, eq);
1169     __ movs(Rtemp, AsmOperand(Rtemp, lsr, exact_log2(os::vm_page_size())), eq);
1170     // If still 'eq' then recursive locking OK
1171     // set to zero if recursive lock, set to non zero otherwise (see discussion in JDK-8267042)
1172     __ str(Rtemp, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()));
1173     __ b(lock_done, eq);
1174     __ b(slow_lock);
1175 
1176     __ bind(fast_lock);
1177     __ str(mark, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()));
1178 
1179     __ cas_for_lock_acquire(mark, disp_hdr, sync_obj, Rtemp, slow_lock);
1180 
1181     __ bind(lock_done);
1182   }
1183 
1184   // Get JNIEnv*
1185   __ add(c_rarg0, Rthread, in_bytes(JavaThread::jni_environment_offset()));
1186 
1187   // Perform thread state transition
1188   __ mov(Rtemp, _thread_in_native);
1189   __ str(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1190 
1191   // Finally, call the native method
1192   __ call(method->native_function());
1193 
1194   // Set FPSCR/FPCR to a known state
1195   if (AlwaysRestoreFPU) {
1196     __ restore_default_fp_mode();
1197   }
1198 
1199   // Ensure a Boolean result is mapped to 0..1
1200   if (ret_type == T_BOOLEAN) {
1201     __ c2bool(R0);
1202   }
1203 
1204   // Do a safepoint check while thread is in transition state
1205   Label call_safepoint_runtime, return_to_java;
1206   __ mov(Rtemp, _thread_in_native_trans);
1207   __ str_32(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1208 
1209   // make sure the store is observed before reading the SafepointSynchronize state and further mem refs
1210   __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad | MacroAssembler::StoreStore), Rtemp);
1211 
1212   __ safepoint_poll(R2, call_safepoint_runtime);
1213   __ ldr_u32(R3, Address(Rthread, JavaThread::suspend_flags_offset()));
1214   __ cmp(R3, 0);
1215   __ b(call_safepoint_runtime, ne);
1216 
1217   __ bind(return_to_java);
1218 
1219   // Perform thread state transition and reguard stack yellow pages if needed
1220   Label reguard, reguard_done;
1221   __ mov(Rtemp, _thread_in_Java);
1222   __ ldr_s32(R2, Address(Rthread, JavaThread::stack_guard_state_offset()));
1223   __ str_32(Rtemp, Address(Rthread, JavaThread::thread_state_offset()));
1224 
1225   __ cmp(R2, StackOverflow::stack_guard_yellow_reserved_disabled);
1226   __ b(reguard, eq);
1227   __ bind(reguard_done);
1228 
1229   Label slow_unlock, unlock_done;
1230   if (method->is_synchronized()) {
1231     __ ldr(sync_obj, Address(sync_handle));
1232 
1233     // See C1_MacroAssembler::unlock_object() for more comments
1234     __ ldr(R2, Address(disp_hdr, BasicLock::displaced_header_offset_in_bytes()));
1235     __ cbz(R2, unlock_done);
1236 
1237     __ cas_for_lock_release(disp_hdr, R2, sync_obj, Rtemp, slow_unlock);
1238 
1239     __ bind(unlock_done);
1240   }
1241 
1242   // Set last java frame and handle block to zero
1243   __ ldr(LR, Address(Rthread, JavaThread::active_handles_offset()));
1244   __ reset_last_Java_frame(Rtemp); // sets Rtemp to 0 on 32-bit ARM
1245 
1246   __ str_32(Rtemp, Address(LR, JNIHandleBlock::top_offset_in_bytes()));
1247   if (CheckJNICalls) {
1248     __ str(__ zero_register(Rtemp), Address(Rthread, JavaThread::pending_jni_exception_check_fn_offset()));
1249   }
1250 
1251   // Unbox oop result, e.g. JNIHandles::resolve value in R0.
1252   if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
1253     __ resolve_jobject(R0,      // value
1254                        Rtemp,   // tmp1
1255                        R1_tmp); // tmp2
1256   }
1257 
1258   // Any exception pending?
1259   __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1260   __ mov(SP, FP);
1261 
1262   __ cmp(Rtemp, 0);
1263   // Pop the frame and return if no exception pending
1264   __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
1265   // Pop the frame and forward the exception. Rexception_pc contains return address.
1266   __ ldr(FP, Address(SP, wordSize, post_indexed), ne);
1267   __ ldr(Rexception_pc, Address(SP, wordSize, post_indexed), ne);
1268   __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1269 
1270   // Safepoint operation and/or pending suspend request is in progress.
1271   // Save the return values and call the runtime function by hand.
1272   __ bind(call_safepoint_runtime);
1273   push_result_registers(masm, ret_type);
1274   __ mov(R0, Rthread);
1275   __ call(CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans));
1276   pop_result_registers(masm, ret_type);
1277   __ b(return_to_java);
1278 
1279   // Reguard stack pages. Save native results around a call to C runtime.
1280   __ bind(reguard);
1281   push_result_registers(masm, ret_type);
1282   __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
1283   pop_result_registers(masm, ret_type);
1284   __ b(reguard_done);
1285 
1286   if (method->is_synchronized()) {
1287     // Locking slow case
1288     __ bind(slow_lock);
1289 
1290     push_param_registers(masm, fp_regs_in_arguments);
1291 
1292     // last_Java_frame is already set, so do call_VM manually; no exception can occur
1293     __ mov(R0, sync_obj);
1294     __ mov(R1, disp_hdr);
1295     __ mov(R2, Rthread);
1296     __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C));
1297 
1298     pop_param_registers(masm, fp_regs_in_arguments);
1299 
1300     __ b(lock_done);
1301 
1302     // Unlocking slow case
1303     __ bind(slow_unlock);
1304 
1305     push_result_registers(masm, ret_type);
1306 
1307     // Clear pending exception before reentering VM.
1308     // Can store the oop in register since it is a leaf call.
1309     assert_different_registers(Rtmp_save1, sync_obj, disp_hdr);
1310     __ ldr(Rtmp_save1, Address(Rthread, Thread::pending_exception_offset()));
1311     Register zero = __ zero_register(Rtemp);
1312     __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
1313     __ mov(R0, sync_obj);
1314     __ mov(R1, disp_hdr);
1315     __ mov(R2, Rthread);
1316     __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C));
1317     __ str(Rtmp_save1, Address(Rthread, Thread::pending_exception_offset()));
1318 
1319     pop_result_registers(masm, ret_type);
1320 
1321     __ b(unlock_done);
1322   }
1323 
1324   __ flush();
1325   return nmethod::new_native_nmethod(method,
1326                                      compile_id,
1327                                      masm->code(),
1328                                      vep_offset,
1329                                      frame_complete,
1330                                      stack_slots / VMRegImpl::slots_per_word,
1331                                      in_ByteSize(method_is_static ? klass_offset : receiver_offset),
1332                                      in_ByteSize(lock_slot_offset * VMRegImpl::stack_slot_size),
1333                                      oop_maps);
1334 }
1335 
1336 // this function returns the adjust size (in number of words) to a c2i adapter
1337 // activation for use during deoptimization
1338 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
1339   int extra_locals_size = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
1340   return extra_locals_size;
1341 }
1342 
1343 
1344 // Number of stack slots between incoming argument block and the start of
1345 // a new frame.  The PROLOG must add this many slots to the stack.  The
1346 // EPILOG must remove this many slots.
1347 // FP + LR
1348 uint SharedRuntime::in_preserve_stack_slots() {
1349   return 2 * VMRegImpl::slots_per_word;
1350 }
1351 
1352 uint SharedRuntime::out_preserve_stack_slots() {
1353   return 0;
1354 }
1355 
1356 //------------------------------generate_deopt_blob----------------------------
1357 void SharedRuntime::generate_deopt_blob() {
1358   ResourceMark rm;
1359   CodeBuffer buffer("deopt_blob", 1024, 1024);
1360   int frame_size_in_words;
1361   OopMapSet* oop_maps;
1362   int reexecute_offset;
1363   int exception_in_tls_offset;
1364   int exception_offset;
1365 
1366   MacroAssembler* masm = new MacroAssembler(&buffer);
1367   Label cont;
1368   const Register Rkind   = R9; // caller-saved
1369   const Register Rublock = R6;
1370   const Register Rsender = altFP_7_11;
1371   assert_different_registers(Rkind, Rublock, Rsender, Rexception_obj, Rexception_pc, R0, R1, R2, R3, R8, Rtemp);
1372 
1373   address start = __ pc();
1374 
1375   oop_maps = new OopMapSet();
1376   // LR saved by caller (can be live in c2 method)
1377 
1378   // A deopt is a case where LR may be live in the c2 nmethod. So it's
1379   // not possible to call the deopt blob from the nmethod and pass the
1380   // address of the deopt handler of the nmethod in LR. What happens
1381   // now is that the caller of the deopt blob pushes the current
1382   // address so the deopt blob doesn't have to do it. This way LR can
1383   // be preserved, contains the live value from the nmethod and is
1384   // saved at R14/R30_offset here.
1385   OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_in_words, true);
1386   __ mov(Rkind, Deoptimization::Unpack_deopt);
1387   __ b(cont);
1388 
1389   exception_offset = __ pc() - start;
1390 
1391   // Transfer Rexception_obj & Rexception_pc in TLS and fall thru to the
1392   // exception_in_tls_offset entry point.
1393   __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
1394   __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
1395   // Force return value to NULL to avoid confusing the escape analysis
1396   // logic. Everything is dead here anyway.
1397   __ mov(R0, 0);
1398 
1399   exception_in_tls_offset = __ pc() - start;
1400 
1401   // Exception data is in JavaThread structure
1402   // Patch the return address of the current frame
1403   __ ldr(LR, Address(Rthread, JavaThread::exception_pc_offset()));
1404   (void) RegisterSaver::save_live_registers(masm, &frame_size_in_words);
1405   {
1406     const Register Rzero = __ zero_register(Rtemp); // XXX should be OK for C2 but not 100% sure
1407     __ str(Rzero, Address(Rthread, JavaThread::exception_pc_offset()));
1408   }
1409   __ mov(Rkind, Deoptimization::Unpack_exception);
1410   __ b(cont);
1411 
1412   reexecute_offset = __ pc() - start;
1413 
1414   (void) RegisterSaver::save_live_registers(masm, &frame_size_in_words);
1415   __ mov(Rkind, Deoptimization::Unpack_reexecute);
1416 
1417   // Calculate UnrollBlock and save the result in Rublock
1418   __ bind(cont);
1419   __ mov(R0, Rthread);
1420   __ mov(R1, Rkind);
1421 
1422   int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp); // note: FP may not need to be saved (not on x86)
1423   assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1424   __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info));
1425   if (pc_offset == -1) {
1426     pc_offset = __ offset();
1427   }
1428   oop_maps->add_gc_map(pc_offset, map);
1429   __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1430 
1431   __ mov(Rublock, R0);
1432 
1433   // Reload Rkind from the UnrollBlock (might have changed)
1434   __ ldr_s32(Rkind, Address(Rublock, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()));
1435   Label noException;
1436   __ cmp_32(Rkind, Deoptimization::Unpack_exception);   // Was exception pending?
1437   __ b(noException, ne);
1438   // handle exception case
1439 #ifdef ASSERT
1440   // assert that exception_pc is zero in tls
1441   { Label L;
1442     __ ldr(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
1443     __ cbz(Rexception_pc, L);
1444     __ stop("exception pc should be null");
1445     __ bind(L);
1446   }
1447 #endif
1448   __ ldr(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
1449   __ verify_oop(Rexception_obj);
1450   {
1451     const Register Rzero = __ zero_register(Rtemp);
1452     __ str(Rzero, Address(Rthread, JavaThread::exception_oop_offset()));
1453   }
1454 
1455   __ bind(noException);
1456 
1457   // This frame is going away.  Fetch return value, so we can move it to
1458   // a new frame.
1459   __ ldr(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1460   __ ldr(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1461 #ifndef __SOFTFP__
1462   __ ldr_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1463 #endif
1464   // pop frame
1465   __ add(SP, SP, RegisterSaver::reg_save_size * wordSize);
1466 
1467   // Set initial stack state before pushing interpreter frames
1468   __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
1469   __ ldr(R2, Address(Rublock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
1470   __ ldr(R3, Address(Rublock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
1471 
1472   __ add(SP, SP, Rtemp);
1473 
1474 #ifdef ASSERT
1475   // Compilers generate code that bang the stack by as much as the
1476   // interpreter would need. So this stack banging should never
1477   // trigger a fault. Verify that it does not on non product builds.
1478   // See if it is enough stack to push deoptimized frames.
1479   //
1480   // The compiled method that we are deoptimizing was popped from the stack.
1481   // If the stack bang results in a stack overflow, we don't return to the
1482   // method that is being deoptimized. The stack overflow exception is
1483   // propagated to the caller of the deoptimized method. Need to get the pc
1484   // from the caller in LR and restore FP.
1485   __ ldr(LR, Address(R2, 0));
1486   __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
1487   __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
1488   __ arm_stack_overflow_check(R8, Rtemp);
1489 #endif
1490   __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
1491 
1492   // Pick up the initial fp we should save
1493   // XXX Note: was ldr(FP, Address(FP));
1494 
1495   // The compiler no longer uses FP as a frame pointer for the
1496   // compiled code. It can be used by the allocator in C2 or to
1497   // memorize the original SP for JSR292 call sites.
1498 
1499   // Hence, ldr(FP, Address(FP)) is probably not correct. For x86,
1500   // Deoptimization::fetch_unroll_info computes the right FP value and
1501   // stores it in Rublock.initial_info. This has been activated for ARM.
1502   __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
1503 
1504   __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
1505   __ mov(Rsender, SP);
1506   __ sub(SP, SP, Rtemp);
1507 
1508   // Push interpreter frames in a loop
1509   Label loop;
1510   __ bind(loop);
1511   __ ldr(LR, Address(R2, wordSize, post_indexed));         // load frame pc
1512   __ ldr(Rtemp, Address(R3, wordSize, post_indexed));      // load frame size
1513 
1514   __ raw_push(FP, LR);                                     // create new frame
1515   __ mov(FP, SP);
1516   __ sub(Rtemp, Rtemp, 2*wordSize);
1517 
1518   __ sub(SP, SP, Rtemp);
1519 
1520   __ str(Rsender, Address(FP, frame::interpreter_frame_sender_sp_offset * wordSize));
1521   __ mov(LR, 0);
1522   __ str(LR, Address(FP, frame::interpreter_frame_last_sp_offset * wordSize));
1523 
1524   __ subs(R8, R8, 1);                               // decrement counter
1525   __ mov(Rsender, SP);
1526   __ b(loop, ne);
1527 
1528   // Re-push self-frame
1529   __ ldr(LR, Address(R2));
1530   __ raw_push(FP, LR);
1531   __ mov(FP, SP);
1532   __ sub(SP, SP, (frame_size_in_words - 2) * wordSize);
1533 
1534   // Restore frame locals after moving the frame
1535   __ str(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1536   __ str(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1537 
1538 #ifndef __SOFTFP__
1539   __ str_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1540 #endif // !__SOFTFP__
1541 
1542 #ifdef ASSERT
1543   // Reload Rkind from the UnrollBlock and check that it was not overwritten (Rkind is not callee-saved)
1544   { Label L;
1545     __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()));
1546     __ cmp_32(Rkind, Rtemp);
1547     __ b(L, eq);
1548     __ stop("Rkind was overwritten");
1549     __ bind(L);
1550   }
1551 #endif
1552 
1553   // Call unpack_frames with proper arguments
1554   __ mov(R0, Rthread);
1555   __ mov(R1, Rkind);
1556 
1557   pc_offset = __ set_last_Java_frame(SP, FP, true, Rtemp);
1558   assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1559   __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
1560   if (pc_offset == -1) {
1561     pc_offset = __ offset();
1562   }
1563   oop_maps->add_gc_map(pc_offset, new OopMap(frame_size_in_words * VMRegImpl::slots_per_word, 0));
1564   __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1565 
1566   // Collect return values, pop self-frame and jump to interpreter
1567   __ ldr(R0, Address(SP, RegisterSaver::R0_offset * wordSize));
1568   __ ldr(R1, Address(SP, RegisterSaver::R1_offset * wordSize));
1569   // Interpreter floats controlled by __SOFTFP__, but compiler
1570   // float return value registers controlled by __ABI_HARD__
1571   // This matters for vfp-sflt builds.
1572 #ifndef __SOFTFP__
1573   // Interpreter hard float
1574 #ifdef __ABI_HARD__
1575   // Compiler float return value in FP registers
1576   __ ldr_double(D0, Address(SP, RegisterSaver::D0_offset * wordSize));
1577 #else
1578   // Compiler float return value in integer registers,
1579   // copy to D0 for interpreter (S0 <-- R0)
1580   __ fmdrr(D0_tos, R0, R1);
1581 #endif
1582 #endif // !__SOFTFP__
1583   __ mov(SP, FP);
1584 
1585   __ pop(RegisterSet(FP) | RegisterSet(PC));
1586 
1587   __ flush();
1588 
1589   _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset,
1590                                            reexecute_offset, frame_size_in_words);
1591   _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
1592 }
1593 
1594 #ifdef COMPILER2
1595 
1596 //------------------------------generate_uncommon_trap_blob--------------------
1597 // Ought to generate an ideal graph & compile, but here's some ASM
1598 // instead.
1599 void SharedRuntime::generate_uncommon_trap_blob() {
1600   // allocate space for the code
1601   ResourceMark rm;
1602 
1603   // setup code generation tools
1604   int pad = VerifyThread ? 512 : 0;
1605 #ifdef _LP64
1606   CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
1607 #else
1608   // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
1609   // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
1610   CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
1611 #endif
1612   // bypassed when code generation useless
1613   MacroAssembler* masm               = new MacroAssembler(&buffer);
1614   const Register Rublock = R6;
1615   const Register Rsender = altFP_7_11;
1616   assert_different_registers(Rublock, Rsender, Rexception_obj, R0, R1, R2, R3, R8, Rtemp);
1617 
1618   //
1619   // This is the entry point for all traps the compiler takes when it thinks
1620   // it cannot handle further execution of compilation code. The frame is
1621   // deoptimized in these cases and converted into interpreter frames for
1622   // execution
1623   // The steps taken by this frame are as follows:
1624   //   - push a fake "unpack_frame"
1625   //   - call the C routine Deoptimization::uncommon_trap (this function
1626   //     packs the current compiled frame into vframe arrays and returns
1627   //     information about the number and size of interpreter frames which
1628   //     are equivalent to the frame which is being deoptimized)
1629   //   - deallocate the "unpack_frame"
1630   //   - deallocate the deoptimization frame
1631   //   - in a loop using the information returned in the previous step
1632   //     push interpreter frames;
1633   //   - create a dummy "unpack_frame"
1634   //   - call the C routine: Deoptimization::unpack_frames (this function
1635   //     lays out values on the interpreter frame which was just created)
1636   //   - deallocate the dummy unpack_frame
1637   //   - return to the interpreter entry point
1638   //
1639   //  Refer to the following methods for more information:
1640   //   - Deoptimization::uncommon_trap
1641   //   - Deoptimization::unpack_frame
1642 
1643   // the unloaded class index is in R0 (first parameter to this blob)
1644 
1645   __ raw_push(FP, LR);
1646   __ set_last_Java_frame(SP, FP, false, Rtemp);
1647   __ mov(R2, Deoptimization::Unpack_uncommon_trap);
1648   __ mov(R1, R0);
1649   __ mov(R0, Rthread);
1650   __ call(CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap));
1651   __ mov(Rublock, R0);
1652   __ reset_last_Java_frame(Rtemp);
1653   __ raw_pop(FP, LR);
1654 
1655 #ifdef ASSERT
1656   { Label L;
1657     __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::unpack_kind_offset_in_bytes()));
1658     __ cmp_32(Rtemp, Deoptimization::Unpack_uncommon_trap);
1659     __ b(L, eq);
1660     __ stop("SharedRuntime::generate_uncommon_trap_blob: expected Unpack_uncommon_trap");
1661     __ bind(L);
1662   }
1663 #endif
1664 
1665 
1666   // Set initial stack state before pushing interpreter frames
1667   __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::size_of_deoptimized_frame_offset_in_bytes()));
1668   __ ldr(R2, Address(Rublock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes()));
1669   __ ldr(R3, Address(Rublock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes()));
1670 
1671   __ add(SP, SP, Rtemp);
1672 
1673   // See if it is enough stack to push deoptimized frames.
1674 #ifdef ASSERT
1675   // Compilers generate code that bang the stack by as much as the
1676   // interpreter would need. So this stack banging should never
1677   // trigger a fault. Verify that it does not on non product builds.
1678   //
1679   // The compiled method that we are deoptimizing was popped from the stack.
1680   // If the stack bang results in a stack overflow, we don't return to the
1681   // method that is being deoptimized. The stack overflow exception is
1682   // propagated to the caller of the deoptimized method. Need to get the pc
1683   // from the caller in LR and restore FP.
1684   __ ldr(LR, Address(R2, 0));
1685   __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
1686   __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes()));
1687   __ arm_stack_overflow_check(R8, Rtemp);
1688 #endif
1689   __ ldr_s32(R8, Address(Rublock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes()));
1690   __ ldr_s32(Rtemp, Address(Rublock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes()));
1691   __ mov(Rsender, SP);
1692   __ sub(SP, SP, Rtemp);
1693   //  __ ldr(FP, Address(FP));
1694   __ ldr(FP, Address(Rublock, Deoptimization::UnrollBlock::initial_info_offset_in_bytes()));
1695 
1696   // Push interpreter frames in a loop
1697   Label loop;
1698   __ bind(loop);
1699   __ ldr(LR, Address(R2, wordSize, post_indexed));         // load frame pc
1700   __ ldr(Rtemp, Address(R3, wordSize, post_indexed));      // load frame size
1701 
1702   __ raw_push(FP, LR);                                     // create new frame
1703   __ mov(FP, SP);
1704   __ sub(Rtemp, Rtemp, 2*wordSize);
1705 
1706   __ sub(SP, SP, Rtemp);
1707 
1708   __ str(Rsender, Address(FP, frame::interpreter_frame_sender_sp_offset * wordSize));
1709   __ mov(LR, 0);
1710   __ str(LR, Address(FP, frame::interpreter_frame_last_sp_offset * wordSize));
1711   __ subs(R8, R8, 1);                               // decrement counter
1712   __ mov(Rsender, SP);
1713   __ b(loop, ne);
1714 
1715   // Re-push self-frame
1716   __ ldr(LR, Address(R2));
1717   __ raw_push(FP, LR);
1718   __ mov(FP, SP);
1719 
1720   // Call unpack_frames with proper arguments
1721   __ mov(R0, Rthread);
1722   __ mov(R1, Deoptimization::Unpack_uncommon_trap);
1723   __ set_last_Java_frame(SP, FP, true, Rtemp);
1724   __ call_VM_leaf(CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames));
1725   //  oop_maps->add_gc_map(__ pc() - start, new OopMap(frame_size_in_words, 0));
1726   __ reset_last_Java_frame(Rtemp);
1727 
1728   __ mov(SP, FP);
1729   __ pop(RegisterSet(FP) | RegisterSet(PC));
1730 
1731   masm->flush();
1732   _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, 2 /* LR+FP */);
1733 }
1734 
1735 #endif // COMPILER2
1736 
1737 //------------------------------generate_handler_blob------
1738 //
1739 // Generate a special Compile2Runtime blob that saves all registers,
1740 // setup oopmap, and calls safepoint code to stop the compiled code for
1741 // a safepoint.
1742 //
1743 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) {
1744   assert(StubRoutines::forward_exception_entry() != NULL, "must be generated before");
1745 
1746   ResourceMark rm;
1747   CodeBuffer buffer("handler_blob", 256, 256);
1748   int frame_size_words;
1749   OopMapSet* oop_maps;
1750 
1751   bool cause_return = (poll_type == POLL_AT_RETURN);
1752 
1753   MacroAssembler* masm = new MacroAssembler(&buffer);
1754   address start = __ pc();
1755   oop_maps = new OopMapSet();
1756 
1757   if (!cause_return) {
1758     __ sub(SP, SP, 4); // make room for LR which may still be live
1759                        // here if we are coming from a c2 method
1760   }
1761 
1762   OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_words, !cause_return);
1763   if (!cause_return) {
1764     // update saved PC with correct value
1765     // need 2 steps because LR can be live in c2 method
1766     __ ldr(LR, Address(Rthread, JavaThread::saved_exception_pc_offset()));
1767     __ str(LR, Address(SP, RegisterSaver::LR_offset * wordSize));
1768   }
1769 
1770   __ mov(R0, Rthread);
1771   int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp); // note: FP may not need to be saved (not on x86)
1772   assert(((__ pc()) - start) == __ offset(), "warning: start differs from code_begin");
1773   __ call(call_ptr);
1774   if (pc_offset == -1) {
1775     pc_offset = __ offset();
1776   }
1777   oop_maps->add_gc_map(pc_offset, map);
1778   __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1779 
1780   if (!cause_return) {
1781     // If our stashed return pc was modified by the runtime we avoid touching it
1782     __ ldr(R3_tmp, Address(Rthread, JavaThread::saved_exception_pc_offset()));
1783     __ ldr(R2_tmp, Address(SP, RegisterSaver::LR_offset * wordSize));
1784     __ cmp(R2_tmp, R3_tmp);
1785     // Adjust return pc forward to step over the safepoint poll instruction
1786     __ add(R2_tmp, R2_tmp, 4, eq);
1787     __ str(R2_tmp, Address(SP, RegisterSaver::LR_offset * wordSize), eq);
1788 
1789     // Check for pending exception
1790     __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1791     __ cmp(Rtemp, 0);
1792 
1793     RegisterSaver::restore_live_registers(masm, false);
1794     __ pop(PC, eq);
1795     __ pop(Rexception_pc);
1796   } else {
1797     // Check for pending exception
1798     __ ldr(Rtemp, Address(Rthread, Thread::pending_exception_offset()));
1799     __ cmp(Rtemp, 0);
1800 
1801     RegisterSaver::restore_live_registers(masm);
1802     __ bx(LR, eq);
1803     __ mov(Rexception_pc, LR);
1804   }
1805 
1806   __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1807 
1808   __ flush();
1809 
1810   return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
1811 }
1812 
1813 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) {
1814   assert(StubRoutines::forward_exception_entry() != NULL, "must be generated before");
1815 
1816   ResourceMark rm;
1817   CodeBuffer buffer(name, 1000, 512);
1818   int frame_size_words;
1819   OopMapSet *oop_maps;
1820   int frame_complete;
1821 
1822   MacroAssembler* masm = new MacroAssembler(&buffer);
1823   Label pending_exception;
1824 
1825   int start = __ offset();
1826 
1827   oop_maps = new OopMapSet();
1828   OopMap* map = RegisterSaver::save_live_registers(masm, &frame_size_words);
1829 
1830   frame_complete = __ offset();
1831 
1832   __ mov(R0, Rthread);
1833 
1834   int pc_offset = __ set_last_Java_frame(SP, FP, false, Rtemp);
1835   assert(start == 0, "warning: start differs from code_begin");
1836   __ call(destination);
1837   if (pc_offset == -1) {
1838     pc_offset = __ offset();
1839   }
1840   oop_maps->add_gc_map(pc_offset, map);
1841   __ reset_last_Java_frame(Rtemp); // Rtemp free since scratched by far call
1842 
1843   __ ldr(R1, Address(Rthread, Thread::pending_exception_offset()));
1844   __ cbnz(R1, pending_exception);
1845 
1846   // Overwrite saved register values
1847 
1848   // Place metadata result of VM call into Rmethod
1849   __ get_vm_result_2(R1, Rtemp);
1850   __ str(R1, Address(SP, RegisterSaver::Rmethod_offset * wordSize));
1851 
1852   // Place target address (VM call result) into Rtemp
1853   __ str(R0, Address(SP, RegisterSaver::Rtemp_offset * wordSize));
1854 
1855   RegisterSaver::restore_live_registers(masm);
1856   __ jump(Rtemp);
1857 
1858   __ bind(pending_exception);
1859 
1860   RegisterSaver::restore_live_registers(masm);
1861   const Register Rzero = __ zero_register(Rtemp);
1862   __ str(Rzero, Address(Rthread, JavaThread::vm_result_2_offset()));
1863   __ mov(Rexception_pc, LR);
1864   __ jump(StubRoutines::forward_exception_entry(), relocInfo::runtime_call_type, Rtemp);
1865 
1866   __ flush();
1867 
1868   return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
1869 }