1 /*
   2  * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/compiler_globals.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "gc/shared/barrierSet.hpp"
  32 #include "gc/shared/barrierSetAssembler.hpp"
  33 #include "gc/shared/collectedHeap.inline.hpp"
  34 #include "gc/shared/tlab_globals.hpp"
  35 #include "interpreter/bytecodeHistogram.hpp"
  36 #include "interpreter/interpreter.hpp"
  37 #include "memory/resourceArea.hpp"
  38 #include "memory/universe.hpp"
  39 #include "oops/accessDecorators.hpp"
  40 #include "oops/compressedOops.inline.hpp"
  41 #include "oops/klass.inline.hpp"
  42 #include "prims/methodHandles.hpp"
  43 #include "runtime/flags/flagSetting.hpp"
  44 #include "runtime/interfaceSupport.inline.hpp"
  45 #include "runtime/jniHandles.hpp"
  46 #include "runtime/objectMonitor.hpp"
  47 #include "runtime/os.hpp"
  48 #include "runtime/safepoint.hpp"
  49 #include "runtime/safepointMechanism.hpp"
  50 #include "runtime/sharedRuntime.hpp"
  51 #include "runtime/stubRoutines.hpp"
  52 #include "runtime/thread.hpp"
  53 #include "utilities/macros.hpp"
  54 #include "crc32c.h"
  55 
  56 #ifdef PRODUCT
  57 #define BLOCK_COMMENT(str) /* nothing */
  58 #define STOP(error) stop(error)
  59 #else
  60 #define BLOCK_COMMENT(str) block_comment(str)
  61 #define STOP(error) block_comment(error); stop(error)
  62 #endif
  63 
  64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  65 
  66 #ifdef ASSERT
  67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  68 #endif
  69 
  70 static Assembler::Condition reverse[] = {
  71     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  72     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  73     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  74     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  75     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  76     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  77     Assembler::above          /* belowEqual    = 0x6 */ ,
  78     Assembler::belowEqual     /* above         = 0x7 */ ,
  79     Assembler::positive       /* negative      = 0x8 */ ,
  80     Assembler::negative       /* positive      = 0x9 */ ,
  81     Assembler::noParity       /* parity        = 0xa */ ,
  82     Assembler::parity         /* noParity      = 0xb */ ,
  83     Assembler::greaterEqual   /* less          = 0xc */ ,
  84     Assembler::less           /* greaterEqual  = 0xd */ ,
  85     Assembler::greater        /* lessEqual     = 0xe */ ,
  86     Assembler::lessEqual      /* greater       = 0xf, */
  87 
  88 };
  89 
  90 
  91 // Implementation of MacroAssembler
  92 
  93 // First all the versions that have distinct versions depending on 32/64 bit
  94 // Unless the difference is trivial (1 line or so).
  95 
  96 #ifndef _LP64
  97 
  98 // 32bit versions
  99 
 100 Address MacroAssembler::as_Address(AddressLiteral adr) {
 101   return Address(adr.target(), adr.rspec());
 102 }
 103 
 104 Address MacroAssembler::as_Address(ArrayAddress adr) {
 105   return Address::make_array(adr);
 106 }
 107 
 108 void MacroAssembler::call_VM_leaf_base(address entry_point,
 109                                        int number_of_arguments) {
 110   call(RuntimeAddress(entry_point));
 111   increment(rsp, number_of_arguments * wordSize);
 112 }
 113 
 114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 115   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 116 }
 117 
 118 
 119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 120   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 121 }
 122 
 123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 124   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 125 }
 126 
 127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 128   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 129 }
 130 
 131 void MacroAssembler::extend_sign(Register hi, Register lo) {
 132   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 133   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 134     cdql();
 135   } else {
 136     movl(hi, lo);
 137     sarl(hi, 31);
 138   }
 139 }
 140 
 141 void MacroAssembler::jC2(Register tmp, Label& L) {
 142   // set parity bit if FPU flag C2 is set (via rax)
 143   save_rax(tmp);
 144   fwait(); fnstsw_ax();
 145   sahf();
 146   restore_rax(tmp);
 147   // branch
 148   jcc(Assembler::parity, L);
 149 }
 150 
 151 void MacroAssembler::jnC2(Register tmp, Label& L) {
 152   // set parity bit if FPU flag C2 is set (via rax)
 153   save_rax(tmp);
 154   fwait(); fnstsw_ax();
 155   sahf();
 156   restore_rax(tmp);
 157   // branch
 158   jcc(Assembler::noParity, L);
 159 }
 160 
 161 // 32bit can do a case table jump in one instruction but we no longer allow the base
 162 // to be installed in the Address class
 163 void MacroAssembler::jump(ArrayAddress entry) {
 164   jmp(as_Address(entry));
 165 }
 166 
 167 // Note: y_lo will be destroyed
 168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 169   // Long compare for Java (semantics as described in JVM spec.)
 170   Label high, low, done;
 171 
 172   cmpl(x_hi, y_hi);
 173   jcc(Assembler::less, low);
 174   jcc(Assembler::greater, high);
 175   // x_hi is the return register
 176   xorl(x_hi, x_hi);
 177   cmpl(x_lo, y_lo);
 178   jcc(Assembler::below, low);
 179   jcc(Assembler::equal, done);
 180 
 181   bind(high);
 182   xorl(x_hi, x_hi);
 183   increment(x_hi);
 184   jmp(done);
 185 
 186   bind(low);
 187   xorl(x_hi, x_hi);
 188   decrementl(x_hi);
 189 
 190   bind(done);
 191 }
 192 
 193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 194     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 195 }
 196 
 197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 198   // leal(dst, as_Address(adr));
 199   // see note in movl as to why we must use a move
 200   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 201 }
 202 
 203 void MacroAssembler::leave() {
 204   mov(rsp, rbp);
 205   pop(rbp);
 206 }
 207 
 208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 209   // Multiplication of two Java long values stored on the stack
 210   // as illustrated below. Result is in rdx:rax.
 211   //
 212   // rsp ---> [  ??  ] \               \
 213   //            ....    | y_rsp_offset  |
 214   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 215   //          [ y_hi ]                  | (in bytes)
 216   //            ....                    |
 217   //          [ x_lo ]                 /
 218   //          [ x_hi ]
 219   //            ....
 220   //
 221   // Basic idea: lo(result) = lo(x_lo * y_lo)
 222   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 223   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 224   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 225   Label quick;
 226   // load x_hi, y_hi and check if quick
 227   // multiplication is possible
 228   movl(rbx, x_hi);
 229   movl(rcx, y_hi);
 230   movl(rax, rbx);
 231   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 232   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 233   // do full multiplication
 234   // 1st step
 235   mull(y_lo);                                    // x_hi * y_lo
 236   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 237   // 2nd step
 238   movl(rax, x_lo);
 239   mull(rcx);                                     // x_lo * y_hi
 240   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 241   // 3rd step
 242   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 243   movl(rax, x_lo);
 244   mull(y_lo);                                    // x_lo * y_lo
 245   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 246 }
 247 
 248 void MacroAssembler::lneg(Register hi, Register lo) {
 249   negl(lo);
 250   adcl(hi, 0);
 251   negl(hi);
 252 }
 253 
 254 void MacroAssembler::lshl(Register hi, Register lo) {
 255   // Java shift left long support (semantics as described in JVM spec., p.305)
 256   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 257   // shift value is in rcx !
 258   assert(hi != rcx, "must not use rcx");
 259   assert(lo != rcx, "must not use rcx");
 260   const Register s = rcx;                        // shift count
 261   const int      n = BitsPerWord;
 262   Label L;
 263   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 264   cmpl(s, n);                                    // if (s < n)
 265   jcc(Assembler::less, L);                       // else (s >= n)
 266   movl(hi, lo);                                  // x := x << n
 267   xorl(lo, lo);
 268   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 269   bind(L);                                       // s (mod n) < n
 270   shldl(hi, lo);                                 // x := x << s
 271   shll(lo);
 272 }
 273 
 274 
 275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 276   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 277   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 278   assert(hi != rcx, "must not use rcx");
 279   assert(lo != rcx, "must not use rcx");
 280   const Register s = rcx;                        // shift count
 281   const int      n = BitsPerWord;
 282   Label L;
 283   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 284   cmpl(s, n);                                    // if (s < n)
 285   jcc(Assembler::less, L);                       // else (s >= n)
 286   movl(lo, hi);                                  // x := x >> n
 287   if (sign_extension) sarl(hi, 31);
 288   else                xorl(hi, hi);
 289   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 290   bind(L);                                       // s (mod n) < n
 291   shrdl(lo, hi);                                 // x := x >> s
 292   if (sign_extension) sarl(hi);
 293   else                shrl(hi);
 294 }
 295 
 296 void MacroAssembler::movoop(Register dst, jobject obj) {
 297   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 298 }
 299 
 300 void MacroAssembler::movoop(Address dst, jobject obj) {
 301   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 302 }
 303 
 304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 305   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 309   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 313   // scratch register is not used,
 314   // it is defined to match parameters of 64-bit version of this method.
 315   if (src.is_lval()) {
 316     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 317   } else {
 318     movl(dst, as_Address(src));
 319   }
 320 }
 321 
 322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 323   movl(as_Address(dst), src);
 324 }
 325 
 326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 327   movl(dst, as_Address(src));
 328 }
 329 
 330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 331 void MacroAssembler::movptr(Address dst, intptr_t src) {
 332   movl(dst, src);
 333 }
 334 
 335 
 336 void MacroAssembler::pop_callee_saved_registers() {
 337   pop(rcx);
 338   pop(rdx);
 339   pop(rdi);
 340   pop(rsi);
 341 }
 342 
 343 void MacroAssembler::push_callee_saved_registers() {
 344   push(rsi);
 345   push(rdi);
 346   push(rdx);
 347   push(rcx);
 348 }
 349 
 350 void MacroAssembler::pushoop(jobject obj) {
 351   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 352 }
 353 
 354 void MacroAssembler::pushklass(Metadata* obj) {
 355   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 356 }
 357 
 358 void MacroAssembler::pushptr(AddressLiteral src) {
 359   if (src.is_lval()) {
 360     push_literal32((int32_t)src.target(), src.rspec());
 361   } else {
 362     pushl(as_Address(src));
 363   }
 364 }
 365 
 366 static void pass_arg0(MacroAssembler* masm, Register arg) {
 367   masm->push(arg);
 368 }
 369 
 370 static void pass_arg1(MacroAssembler* masm, Register arg) {
 371   masm->push(arg);
 372 }
 373 
 374 static void pass_arg2(MacroAssembler* masm, Register arg) {
 375   masm->push(arg);
 376 }
 377 
 378 static void pass_arg3(MacroAssembler* masm, Register arg) {
 379   masm->push(arg);
 380 }
 381 
 382 #ifndef PRODUCT
 383 extern "C" void findpc(intptr_t x);
 384 #endif
 385 
 386 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 387   // In order to get locks to work, we need to fake a in_VM state
 388   JavaThread* thread = JavaThread::current();
 389   JavaThreadState saved_state = thread->thread_state();
 390   thread->set_thread_state(_thread_in_vm);
 391   if (ShowMessageBoxOnError) {
 392     JavaThread* thread = JavaThread::current();
 393     JavaThreadState saved_state = thread->thread_state();
 394     thread->set_thread_state(_thread_in_vm);
 395     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 396       ttyLocker ttyl;
 397       BytecodeCounter::print();
 398     }
 399     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 400     // This is the value of eip which points to where verify_oop will return.
 401     if (os::message_box(msg, "Execution stopped, print registers?")) {
 402       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 403       BREAKPOINT;
 404     }
 405   }
 406   fatal("DEBUG MESSAGE: %s", msg);
 407 }
 408 
 409 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 410   ttyLocker ttyl;
 411   FlagSetting fs(Debugging, true);
 412   tty->print_cr("eip = 0x%08x", eip);
 413 #ifndef PRODUCT
 414   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 415     tty->cr();
 416     findpc(eip);
 417     tty->cr();
 418   }
 419 #endif
 420 #define PRINT_REG(rax) \
 421   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 422   PRINT_REG(rax);
 423   PRINT_REG(rbx);
 424   PRINT_REG(rcx);
 425   PRINT_REG(rdx);
 426   PRINT_REG(rdi);
 427   PRINT_REG(rsi);
 428   PRINT_REG(rbp);
 429   PRINT_REG(rsp);
 430 #undef PRINT_REG
 431   // Print some words near top of staack.
 432   int* dump_sp = (int*) rsp;
 433   for (int col1 = 0; col1 < 8; col1++) {
 434     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 435     os::print_location(tty, *dump_sp++);
 436   }
 437   for (int row = 0; row < 16; row++) {
 438     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 439     for (int col = 0; col < 8; col++) {
 440       tty->print(" 0x%08x", *dump_sp++);
 441     }
 442     tty->cr();
 443   }
 444   // Print some instructions around pc:
 445   Disassembler::decode((address)eip-64, (address)eip);
 446   tty->print_cr("--------");
 447   Disassembler::decode((address)eip, (address)eip+32);
 448 }
 449 
 450 void MacroAssembler::stop(const char* msg) {
 451   ExternalAddress message((address)msg);
 452   // push address of message
 453   pushptr(message.addr());
 454   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 455   pusha();                                            // push registers
 456   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 457   hlt();
 458 }
 459 
 460 void MacroAssembler::warn(const char* msg) {
 461   push_CPU_state();
 462 
 463   ExternalAddress message((address) msg);
 464   // push address of message
 465   pushptr(message.addr());
 466 
 467   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 468   addl(rsp, wordSize);       // discard argument
 469   pop_CPU_state();
 470 }
 471 
 472 void MacroAssembler::print_state() {
 473   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 474   pusha();                                            // push registers
 475 
 476   push_CPU_state();
 477   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 478   pop_CPU_state();
 479 
 480   popa();
 481   addl(rsp, wordSize);
 482 }
 483 
 484 #else // _LP64
 485 
 486 // 64 bit versions
 487 
 488 Address MacroAssembler::as_Address(AddressLiteral adr) {
 489   // amd64 always does this as a pc-rel
 490   // we can be absolute or disp based on the instruction type
 491   // jmp/call are displacements others are absolute
 492   assert(!adr.is_lval(), "must be rval");
 493   assert(reachable(adr), "must be");
 494   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 495 
 496 }
 497 
 498 Address MacroAssembler::as_Address(ArrayAddress adr) {
 499   AddressLiteral base = adr.base();
 500   lea(rscratch1, base);
 501   Address index = adr.index();
 502   assert(index._disp == 0, "must not have disp"); // maybe it can?
 503   Address array(rscratch1, index._index, index._scale, index._disp);
 504   return array;
 505 }
 506 
 507 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 508   Label L, E;
 509 
 510 #ifdef _WIN64
 511   // Windows always allocates space for it's register args
 512   assert(num_args <= 4, "only register arguments supported");
 513   subq(rsp,  frame::arg_reg_save_area_bytes);
 514 #endif
 515 
 516   // Align stack if necessary
 517   testl(rsp, 15);
 518   jcc(Assembler::zero, L);
 519 
 520   subq(rsp, 8);
 521   {
 522     call(RuntimeAddress(entry_point));
 523   }
 524   addq(rsp, 8);
 525   jmp(E);
 526 
 527   bind(L);
 528   {
 529     call(RuntimeAddress(entry_point));
 530   }
 531 
 532   bind(E);
 533 
 534 #ifdef _WIN64
 535   // restore stack pointer
 536   addq(rsp, frame::arg_reg_save_area_bytes);
 537 #endif
 538 
 539 }
 540 
 541 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 542   assert(!src2.is_lval(), "should use cmpptr");
 543 
 544   if (reachable(src2)) {
 545     cmpq(src1, as_Address(src2));
 546   } else {
 547     lea(rscratch1, src2);
 548     Assembler::cmpq(src1, Address(rscratch1, 0));
 549   }
 550 }
 551 
 552 int MacroAssembler::corrected_idivq(Register reg) {
 553   // Full implementation of Java ldiv and lrem; checks for special
 554   // case as described in JVM spec., p.243 & p.271.  The function
 555   // returns the (pc) offset of the idivl instruction - may be needed
 556   // for implicit exceptions.
 557   //
 558   //         normal case                           special case
 559   //
 560   // input : rax: dividend                         min_long
 561   //         reg: divisor   (may not be eax/edx)   -1
 562   //
 563   // output: rax: quotient  (= rax idiv reg)       min_long
 564   //         rdx: remainder (= rax irem reg)       0
 565   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 566   static const int64_t min_long = 0x8000000000000000;
 567   Label normal_case, special_case;
 568 
 569   // check for special case
 570   cmp64(rax, ExternalAddress((address) &min_long));
 571   jcc(Assembler::notEqual, normal_case);
 572   xorl(rdx, rdx); // prepare rdx for possible special case (where
 573                   // remainder = 0)
 574   cmpq(reg, -1);
 575   jcc(Assembler::equal, special_case);
 576 
 577   // handle normal case
 578   bind(normal_case);
 579   cdqq();
 580   int idivq_offset = offset();
 581   idivq(reg);
 582 
 583   // normal and special case exit
 584   bind(special_case);
 585 
 586   return idivq_offset;
 587 }
 588 
 589 void MacroAssembler::decrementq(Register reg, int value) {
 590   if (value == min_jint) { subq(reg, value); return; }
 591   if (value <  0) { incrementq(reg, -value); return; }
 592   if (value == 0) {                        ; return; }
 593   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 594   /* else */      { subq(reg, value)       ; return; }
 595 }
 596 
 597 void MacroAssembler::decrementq(Address dst, int value) {
 598   if (value == min_jint) { subq(dst, value); return; }
 599   if (value <  0) { incrementq(dst, -value); return; }
 600   if (value == 0) {                        ; return; }
 601   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 602   /* else */      { subq(dst, value)       ; return; }
 603 }
 604 
 605 void MacroAssembler::incrementq(AddressLiteral dst) {
 606   if (reachable(dst)) {
 607     incrementq(as_Address(dst));
 608   } else {
 609     lea(rscratch1, dst);
 610     incrementq(Address(rscratch1, 0));
 611   }
 612 }
 613 
 614 void MacroAssembler::incrementq(Register reg, int value) {
 615   if (value == min_jint) { addq(reg, value); return; }
 616   if (value <  0) { decrementq(reg, -value); return; }
 617   if (value == 0) {                        ; return; }
 618   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 619   /* else */      { addq(reg, value)       ; return; }
 620 }
 621 
 622 void MacroAssembler::incrementq(Address dst, int value) {
 623   if (value == min_jint) { addq(dst, value); return; }
 624   if (value <  0) { decrementq(dst, -value); return; }
 625   if (value == 0) {                        ; return; }
 626   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 627   /* else */      { addq(dst, value)       ; return; }
 628 }
 629 
 630 // 32bit can do a case table jump in one instruction but we no longer allow the base
 631 // to be installed in the Address class
 632 void MacroAssembler::jump(ArrayAddress entry) {
 633   lea(rscratch1, entry.base());
 634   Address dispatch = entry.index();
 635   assert(dispatch._base == noreg, "must be");
 636   dispatch._base = rscratch1;
 637   jmp(dispatch);
 638 }
 639 
 640 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 641   ShouldNotReachHere(); // 64bit doesn't use two regs
 642   cmpq(x_lo, y_lo);
 643 }
 644 
 645 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 646     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 647 }
 648 
 649 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 650   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 651   movptr(dst, rscratch1);
 652 }
 653 
 654 void MacroAssembler::leave() {
 655   // %%% is this really better? Why not on 32bit too?
 656   emit_int8((unsigned char)0xC9); // LEAVE
 657 }
 658 
 659 void MacroAssembler::lneg(Register hi, Register lo) {
 660   ShouldNotReachHere(); // 64bit doesn't use two regs
 661   negq(lo);
 662 }
 663 
 664 void MacroAssembler::movoop(Register dst, jobject obj) {
 665   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 666 }
 667 
 668 void MacroAssembler::movoop(Address dst, jobject obj) {
 669   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 670   movq(dst, rscratch1);
 671 }
 672 
 673 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 674   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 675 }
 676 
 677 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 678   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 679   movq(dst, rscratch1);
 680 }
 681 
 682 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 683   if (src.is_lval()) {
 684     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 685   } else {
 686     if (reachable(src)) {
 687       movq(dst, as_Address(src));
 688     } else {
 689       lea(scratch, src);
 690       movq(dst, Address(scratch, 0));
 691     }
 692   }
 693 }
 694 
 695 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 696   movq(as_Address(dst), src);
 697 }
 698 
 699 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 700   movq(dst, as_Address(src));
 701 }
 702 
 703 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 704 void MacroAssembler::movptr(Address dst, intptr_t src) {
 705   if (is_simm32(src)) {
 706     movptr(dst, checked_cast<int32_t>(src));
 707   } else {
 708     mov64(rscratch1, src);
 709     movq(dst, rscratch1);
 710   }
 711 }
 712 
 713 // These are mostly for initializing NULL
 714 void MacroAssembler::movptr(Address dst, int32_t src) {
 715   movslq(dst, src);
 716 }
 717 
 718 void MacroAssembler::movptr(Register dst, int32_t src) {
 719   mov64(dst, (intptr_t)src);
 720 }
 721 
 722 void MacroAssembler::pushoop(jobject obj) {
 723   movoop(rscratch1, obj);
 724   push(rscratch1);
 725 }
 726 
 727 void MacroAssembler::pushklass(Metadata* obj) {
 728   mov_metadata(rscratch1, obj);
 729   push(rscratch1);
 730 }
 731 
 732 void MacroAssembler::pushptr(AddressLiteral src) {
 733   lea(rscratch1, src);
 734   if (src.is_lval()) {
 735     push(rscratch1);
 736   } else {
 737     pushq(Address(rscratch1, 0));
 738   }
 739 }
 740 
 741 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 742   reset_last_Java_frame(r15_thread, clear_fp);
 743 }
 744 
 745 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 746                                          Register last_java_fp,
 747                                          address  last_java_pc) {
 748   vzeroupper();
 749   // determine last_java_sp register
 750   if (!last_java_sp->is_valid()) {
 751     last_java_sp = rsp;
 752   }
 753 
 754   // last_java_fp is optional
 755   if (last_java_fp->is_valid()) {
 756     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 757            last_java_fp);
 758   }
 759 
 760   // last_java_pc is optional
 761   if (last_java_pc != NULL) {
 762     Address java_pc(r15_thread,
 763                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 764     lea(rscratch1, InternalAddress(last_java_pc));
 765     movptr(java_pc, rscratch1);
 766   }
 767 
 768   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 769 }
 770 
 771 static void pass_arg0(MacroAssembler* masm, Register arg) {
 772   if (c_rarg0 != arg ) {
 773     masm->mov(c_rarg0, arg);
 774   }
 775 }
 776 
 777 static void pass_arg1(MacroAssembler* masm, Register arg) {
 778   if (c_rarg1 != arg ) {
 779     masm->mov(c_rarg1, arg);
 780   }
 781 }
 782 
 783 static void pass_arg2(MacroAssembler* masm, Register arg) {
 784   if (c_rarg2 != arg ) {
 785     masm->mov(c_rarg2, arg);
 786   }
 787 }
 788 
 789 static void pass_arg3(MacroAssembler* masm, Register arg) {
 790   if (c_rarg3 != arg ) {
 791     masm->mov(c_rarg3, arg);
 792   }
 793 }
 794 
 795 void MacroAssembler::stop(const char* msg) {
 796   if (ShowMessageBoxOnError) {
 797     address rip = pc();
 798     pusha(); // get regs on stack
 799     lea(c_rarg1, InternalAddress(rip));
 800     movq(c_rarg2, rsp); // pass pointer to regs array
 801   }
 802   lea(c_rarg0, ExternalAddress((address) msg));
 803   andq(rsp, -16); // align stack as required by ABI
 804   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 805   hlt();
 806 }
 807 
 808 void MacroAssembler::warn(const char* msg) {
 809   push(rbp);
 810   movq(rbp, rsp);
 811   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 812   push_CPU_state();   // keeps alignment at 16 bytes
 813   lea(c_rarg0, ExternalAddress((address) msg));
 814   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 815   call(rax);
 816   pop_CPU_state();
 817   mov(rsp, rbp);
 818   pop(rbp);
 819 }
 820 
 821 void MacroAssembler::print_state() {
 822   address rip = pc();
 823   pusha();            // get regs on stack
 824   push(rbp);
 825   movq(rbp, rsp);
 826   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 827   push_CPU_state();   // keeps alignment at 16 bytes
 828 
 829   lea(c_rarg0, InternalAddress(rip));
 830   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 831   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 832 
 833   pop_CPU_state();
 834   mov(rsp, rbp);
 835   pop(rbp);
 836   popa();
 837 }
 838 
 839 #ifndef PRODUCT
 840 extern "C" void findpc(intptr_t x);
 841 #endif
 842 
 843 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 844   // In order to get locks to work, we need to fake a in_VM state
 845   if (ShowMessageBoxOnError) {
 846     JavaThread* thread = JavaThread::current();
 847     JavaThreadState saved_state = thread->thread_state();
 848     thread->set_thread_state(_thread_in_vm);
 849 #ifndef PRODUCT
 850     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 851       ttyLocker ttyl;
 852       BytecodeCounter::print();
 853     }
 854 #endif
 855     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 856     // XXX correct this offset for amd64
 857     // This is the value of eip which points to where verify_oop will return.
 858     if (os::message_box(msg, "Execution stopped, print registers?")) {
 859       print_state64(pc, regs);
 860       BREAKPOINT;
 861     }
 862   }
 863   fatal("DEBUG MESSAGE: %s", msg);
 864 }
 865 
 866 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 867   ttyLocker ttyl;
 868   FlagSetting fs(Debugging, true);
 869   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 870 #ifndef PRODUCT
 871   tty->cr();
 872   findpc(pc);
 873   tty->cr();
 874 #endif
 875 #define PRINT_REG(rax, value) \
 876   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 877   PRINT_REG(rax, regs[15]);
 878   PRINT_REG(rbx, regs[12]);
 879   PRINT_REG(rcx, regs[14]);
 880   PRINT_REG(rdx, regs[13]);
 881   PRINT_REG(rdi, regs[8]);
 882   PRINT_REG(rsi, regs[9]);
 883   PRINT_REG(rbp, regs[10]);
 884   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
 885   PRINT_REG(rsp, (intptr_t)(&regs[16]));
 886   PRINT_REG(r8 , regs[7]);
 887   PRINT_REG(r9 , regs[6]);
 888   PRINT_REG(r10, regs[5]);
 889   PRINT_REG(r11, regs[4]);
 890   PRINT_REG(r12, regs[3]);
 891   PRINT_REG(r13, regs[2]);
 892   PRINT_REG(r14, regs[1]);
 893   PRINT_REG(r15, regs[0]);
 894 #undef PRINT_REG
 895   // Print some words near the top of the stack.
 896   int64_t* rsp = &regs[16];
 897   int64_t* dump_sp = rsp;
 898   for (int col1 = 0; col1 < 8; col1++) {
 899     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 900     os::print_location(tty, *dump_sp++);
 901   }
 902   for (int row = 0; row < 25; row++) {
 903     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 904     for (int col = 0; col < 4; col++) {
 905       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 906     }
 907     tty->cr();
 908   }
 909   // Print some instructions around pc:
 910   Disassembler::decode((address)pc-64, (address)pc);
 911   tty->print_cr("--------");
 912   Disassembler::decode((address)pc, (address)pc+32);
 913 }
 914 
 915 // The java_calling_convention describes stack locations as ideal slots on
 916 // a frame with no abi restrictions. Since we must observe abi restrictions
 917 // (like the placement of the register window) the slots must be biased by
 918 // the following value.
 919 static int reg2offset_in(VMReg r) {
 920   // Account for saved rbp and return address
 921   // This should really be in_preserve_stack_slots
 922   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 923 }
 924 
 925 static int reg2offset_out(VMReg r) {
 926   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 927 }
 928 
 929 // A long move
 930 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
 931 
 932   // The calling conventions assures us that each VMregpair is either
 933   // all really one physical register or adjacent stack slots.
 934 
 935   if (src.is_single_phys_reg() ) {
 936     if (dst.is_single_phys_reg()) {
 937       if (dst.first() != src.first()) {
 938         mov(dst.first()->as_Register(), src.first()->as_Register());
 939       }
 940     } else {
 941       assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
 942        src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
 943       movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
 944     }
 945   } else if (dst.is_single_phys_reg()) {
 946     assert(src.is_single_reg(),  "not a stack pair");
 947     movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 948   } else {
 949     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 950     movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 951     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
 952   }
 953 }
 954 
 955 // A double move
 956 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
 957 
 958   // The calling conventions assures us that each VMregpair is either
 959   // all really one physical register or adjacent stack slots.
 960 
 961   if (src.is_single_phys_reg() ) {
 962     if (dst.is_single_phys_reg()) {
 963       // In theory these overlap but the ordering is such that this is likely a nop
 964       if ( src.first() != dst.first()) {
 965         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
 966       }
 967     } else {
 968       assert(dst.is_single_reg(), "not a stack pair");
 969       movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
 970     }
 971   } else if (dst.is_single_phys_reg()) {
 972     assert(src.is_single_reg(),  "not a stack pair");
 973     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 974   } else {
 975     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 976     movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 977     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
 978   }
 979 }
 980 
 981 
 982 // A float arg may have to do float reg int reg conversion
 983 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
 984   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
 985 
 986   // The calling conventions assures us that each VMregpair is either
 987   // all really one physical register or adjacent stack slots.
 988 
 989   if (src.first()->is_stack()) {
 990     if (dst.first()->is_stack()) {
 991       movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 992       movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
 993     } else {
 994       // stack to reg
 995       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
 996       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
 997     }
 998   } else if (dst.first()->is_stack()) {
 999     // reg to stack
1000     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1001     movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
1002   } else {
1003     // reg to reg
1004     // In theory these overlap but the ordering is such that this is likely a nop
1005     if ( src.first() != dst.first()) {
1006       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
1007     }
1008   }
1009 }
1010 
1011 // On 64 bit we will store integer like items to the stack as
1012 // 64 bits items (x86_32/64 abi) even though java would only store
1013 // 32bits for a parameter. On 32bit it will simply be 32 bits
1014 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1015 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
1016   if (src.first()->is_stack()) {
1017     if (dst.first()->is_stack()) {
1018       // stack to stack
1019       movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1020       movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
1021     } else {
1022       // stack to reg
1023       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1024     }
1025   } else if (dst.first()->is_stack()) {
1026     // reg to stack
1027     // Do we really have to sign extend???
1028     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1029     movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1030   } else {
1031     // Do we really have to sign extend???
1032     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1033     if (dst.first() != src.first()) {
1034       movq(dst.first()->as_Register(), src.first()->as_Register());
1035     }
1036   }
1037 }
1038 
1039 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1040   if (src.first()->is_stack()) {
1041     if (dst.first()->is_stack()) {
1042       // stack to stack
1043       movq(rax, Address(rbp, reg2offset_in(src.first())));
1044       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1045     } else {
1046       // stack to reg
1047       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1048     }
1049   } else if (dst.first()->is_stack()) {
1050     // reg to stack
1051     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1052   } else {
1053     if (dst.first() != src.first()) {
1054       movq(dst.first()->as_Register(), src.first()->as_Register());
1055     }
1056   }
1057 }
1058 
1059 // An oop arg. Must pass a handle not the oop itself
1060 void MacroAssembler::object_move(OopMap* map,
1061                         int oop_handle_offset,
1062                         int framesize_in_slots,
1063                         VMRegPair src,
1064                         VMRegPair dst,
1065                         bool is_receiver,
1066                         int* receiver_offset) {
1067 
1068   // must pass a handle. First figure out the location we use as a handle
1069 
1070   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1071 
1072   // See if oop is NULL if it is we need no handle
1073 
1074   if (src.first()->is_stack()) {
1075 
1076     // Oop is already on the stack as an argument
1077     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1078     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1079     if (is_receiver) {
1080       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1081     }
1082 
1083     cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1084     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1085     // conditionally move a NULL
1086     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1087   } else {
1088 
1089     // Oop is in an a register we must store it to the space we reserve
1090     // on the stack for oop_handles and pass a handle if oop is non-NULL
1091 
1092     const Register rOop = src.first()->as_Register();
1093     int oop_slot;
1094     if (rOop == j_rarg0)
1095       oop_slot = 0;
1096     else if (rOop == j_rarg1)
1097       oop_slot = 1;
1098     else if (rOop == j_rarg2)
1099       oop_slot = 2;
1100     else if (rOop == j_rarg3)
1101       oop_slot = 3;
1102     else if (rOop == j_rarg4)
1103       oop_slot = 4;
1104     else {
1105       assert(rOop == j_rarg5, "wrong register");
1106       oop_slot = 5;
1107     }
1108 
1109     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1110     int offset = oop_slot*VMRegImpl::stack_slot_size;
1111 
1112     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1113     // Store oop in handle area, may be NULL
1114     movptr(Address(rsp, offset), rOop);
1115     if (is_receiver) {
1116       *receiver_offset = offset;
1117     }
1118 
1119     cmpptr(rOop, (int32_t)NULL_WORD);
1120     lea(rHandle, Address(rsp, offset));
1121     // conditionally move a NULL from the handle area where it was just stored
1122     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1123   }
1124 
1125   // If arg is on the stack then place it otherwise it is already in correct reg.
1126   if (dst.first()->is_stack()) {
1127     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1128   }
1129 }
1130 
1131 #endif // _LP64
1132 
1133 // Now versions that are common to 32/64 bit
1134 
1135 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1136   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1137 }
1138 
1139 void MacroAssembler::addptr(Register dst, Register src) {
1140   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1141 }
1142 
1143 void MacroAssembler::addptr(Address dst, Register src) {
1144   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1145 }
1146 
1147 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1148   if (reachable(src)) {
1149     Assembler::addsd(dst, as_Address(src));
1150   } else {
1151     lea(rscratch1, src);
1152     Assembler::addsd(dst, Address(rscratch1, 0));
1153   }
1154 }
1155 
1156 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1157   if (reachable(src)) {
1158     addss(dst, as_Address(src));
1159   } else {
1160     lea(rscratch1, src);
1161     addss(dst, Address(rscratch1, 0));
1162   }
1163 }
1164 
1165 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1166   if (reachable(src)) {
1167     Assembler::addpd(dst, as_Address(src));
1168   } else {
1169     lea(rscratch1, src);
1170     Assembler::addpd(dst, Address(rscratch1, 0));
1171   }
1172 }
1173 
1174 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
1175 // Stub code is generated once and never copied.
1176 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1177 void MacroAssembler::align64() {
1178   align(64, (unsigned long long) pc());
1179 }
1180 
1181 void MacroAssembler::align32() {
1182   align(32, (unsigned long long) pc());
1183 }
1184 
1185 void MacroAssembler::align(int modulus) {
1186   // 8273459: Ensure alignment is possible with current segment alignment
1187   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1188   align(modulus, offset());
1189 }
1190 
1191 void MacroAssembler::align(int modulus, int target) {
1192   if (target % modulus != 0) {
1193     nop(modulus - (target % modulus));
1194   }
1195 }
1196 
1197 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1198   // Used in sign-masking with aligned address.
1199   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1200   if (reachable(src)) {
1201     Assembler::andpd(dst, as_Address(src));
1202   } else {
1203     lea(scratch_reg, src);
1204     Assembler::andpd(dst, Address(scratch_reg, 0));
1205   }
1206 }
1207 
1208 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1209   // Used in sign-masking with aligned address.
1210   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1211   if (reachable(src)) {
1212     Assembler::andps(dst, as_Address(src));
1213   } else {
1214     lea(scratch_reg, src);
1215     Assembler::andps(dst, Address(scratch_reg, 0));
1216   }
1217 }
1218 
1219 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1220   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1221 }
1222 
1223 void MacroAssembler::atomic_incl(Address counter_addr) {
1224   lock();
1225   incrementl(counter_addr);
1226 }
1227 
1228 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1229   if (reachable(counter_addr)) {
1230     atomic_incl(as_Address(counter_addr));
1231   } else {
1232     lea(scr, counter_addr);
1233     atomic_incl(Address(scr, 0));
1234   }
1235 }
1236 
1237 #ifdef _LP64
1238 void MacroAssembler::atomic_incq(Address counter_addr) {
1239   lock();
1240   incrementq(counter_addr);
1241 }
1242 
1243 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1244   if (reachable(counter_addr)) {
1245     atomic_incq(as_Address(counter_addr));
1246   } else {
1247     lea(scr, counter_addr);
1248     atomic_incq(Address(scr, 0));
1249   }
1250 }
1251 #endif
1252 
1253 // Writes to stack successive pages until offset reached to check for
1254 // stack overflow + shadow pages.  This clobbers tmp.
1255 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1256   movptr(tmp, rsp);
1257   // Bang stack for total size given plus shadow page size.
1258   // Bang one page at a time because large size can bang beyond yellow and
1259   // red zones.
1260   Label loop;
1261   bind(loop);
1262   movl(Address(tmp, (-os::vm_page_size())), size );
1263   subptr(tmp, os::vm_page_size());
1264   subl(size, os::vm_page_size());
1265   jcc(Assembler::greater, loop);
1266 
1267   // Bang down shadow pages too.
1268   // At this point, (tmp-0) is the last address touched, so don't
1269   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1270   // was post-decremented.)  Skip this address by starting at i=1, and
1271   // touch a few more pages below.  N.B.  It is important to touch all
1272   // the way down including all pages in the shadow zone.
1273   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1274     // this could be any sized move but this is can be a debugging crumb
1275     // so the bigger the better.
1276     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1277   }
1278 }
1279 
1280 void MacroAssembler::reserved_stack_check() {
1281     // testing if reserved zone needs to be enabled
1282     Label no_reserved_zone_enabling;
1283     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1284     NOT_LP64(get_thread(rsi);)
1285 
1286     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1287     jcc(Assembler::below, no_reserved_zone_enabling);
1288 
1289     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1290     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1291     should_not_reach_here();
1292 
1293     bind(no_reserved_zone_enabling);
1294 }
1295 
1296 void MacroAssembler::c2bool(Register x) {
1297   // implements x == 0 ? 0 : 1
1298   // note: must only look at least-significant byte of x
1299   //       since C-style booleans are stored in one byte
1300   //       only! (was bug)
1301   andl(x, 0xFF);
1302   setb(Assembler::notZero, x);
1303 }
1304 
1305 // Wouldn't need if AddressLiteral version had new name
1306 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1307   Assembler::call(L, rtype);
1308 }
1309 
1310 void MacroAssembler::call(Register entry) {
1311   Assembler::call(entry);
1312 }
1313 
1314 void MacroAssembler::call(AddressLiteral entry) {
1315   if (reachable(entry)) {
1316     Assembler::call_literal(entry.target(), entry.rspec());
1317   } else {
1318     lea(rscratch1, entry);
1319     Assembler::call(rscratch1);
1320   }
1321 }
1322 
1323 void MacroAssembler::ic_call(address entry, jint method_index) {
1324   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1325   movptr(rax, (intptr_t)Universe::non_oop_word());
1326   call(AddressLiteral(entry, rh));
1327 }
1328 
1329 // Implementation of call_VM versions
1330 
1331 void MacroAssembler::call_VM(Register oop_result,
1332                              address entry_point,
1333                              bool check_exceptions) {
1334   Label C, E;
1335   call(C, relocInfo::none);
1336   jmp(E);
1337 
1338   bind(C);
1339   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1340   ret(0);
1341 
1342   bind(E);
1343 }
1344 
1345 void MacroAssembler::call_VM(Register oop_result,
1346                              address entry_point,
1347                              Register arg_1,
1348                              bool check_exceptions) {
1349   Label C, E;
1350   call(C, relocInfo::none);
1351   jmp(E);
1352 
1353   bind(C);
1354   pass_arg1(this, arg_1);
1355   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1356   ret(0);
1357 
1358   bind(E);
1359 }
1360 
1361 void MacroAssembler::call_VM(Register oop_result,
1362                              address entry_point,
1363                              Register arg_1,
1364                              Register arg_2,
1365                              bool check_exceptions) {
1366   Label C, E;
1367   call(C, relocInfo::none);
1368   jmp(E);
1369 
1370   bind(C);
1371 
1372   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1373 
1374   pass_arg2(this, arg_2);
1375   pass_arg1(this, arg_1);
1376   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1377   ret(0);
1378 
1379   bind(E);
1380 }
1381 
1382 void MacroAssembler::call_VM(Register oop_result,
1383                              address entry_point,
1384                              Register arg_1,
1385                              Register arg_2,
1386                              Register arg_3,
1387                              bool check_exceptions) {
1388   Label C, E;
1389   call(C, relocInfo::none);
1390   jmp(E);
1391 
1392   bind(C);
1393 
1394   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1395   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1396   pass_arg3(this, arg_3);
1397 
1398   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1399   pass_arg2(this, arg_2);
1400 
1401   pass_arg1(this, arg_1);
1402   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1403   ret(0);
1404 
1405   bind(E);
1406 }
1407 
1408 void MacroAssembler::call_VM(Register oop_result,
1409                              Register last_java_sp,
1410                              address entry_point,
1411                              int number_of_arguments,
1412                              bool check_exceptions) {
1413   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1414   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1415 }
1416 
1417 void MacroAssembler::call_VM(Register oop_result,
1418                              Register last_java_sp,
1419                              address entry_point,
1420                              Register arg_1,
1421                              bool check_exceptions) {
1422   pass_arg1(this, arg_1);
1423   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1424 }
1425 
1426 void MacroAssembler::call_VM(Register oop_result,
1427                              Register last_java_sp,
1428                              address entry_point,
1429                              Register arg_1,
1430                              Register arg_2,
1431                              bool check_exceptions) {
1432 
1433   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1434   pass_arg2(this, arg_2);
1435   pass_arg1(this, arg_1);
1436   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1437 }
1438 
1439 void MacroAssembler::call_VM(Register oop_result,
1440                              Register last_java_sp,
1441                              address entry_point,
1442                              Register arg_1,
1443                              Register arg_2,
1444                              Register arg_3,
1445                              bool check_exceptions) {
1446   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1447   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1448   pass_arg3(this, arg_3);
1449   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1450   pass_arg2(this, arg_2);
1451   pass_arg1(this, arg_1);
1452   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1453 }
1454 
1455 void MacroAssembler::super_call_VM(Register oop_result,
1456                                    Register last_java_sp,
1457                                    address entry_point,
1458                                    int number_of_arguments,
1459                                    bool check_exceptions) {
1460   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1461   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1462 }
1463 
1464 void MacroAssembler::super_call_VM(Register oop_result,
1465                                    Register last_java_sp,
1466                                    address entry_point,
1467                                    Register arg_1,
1468                                    bool check_exceptions) {
1469   pass_arg1(this, arg_1);
1470   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1471 }
1472 
1473 void MacroAssembler::super_call_VM(Register oop_result,
1474                                    Register last_java_sp,
1475                                    address entry_point,
1476                                    Register arg_1,
1477                                    Register arg_2,
1478                                    bool check_exceptions) {
1479 
1480   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1481   pass_arg2(this, arg_2);
1482   pass_arg1(this, arg_1);
1483   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1484 }
1485 
1486 void MacroAssembler::super_call_VM(Register oop_result,
1487                                    Register last_java_sp,
1488                                    address entry_point,
1489                                    Register arg_1,
1490                                    Register arg_2,
1491                                    Register arg_3,
1492                                    bool check_exceptions) {
1493   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1494   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1495   pass_arg3(this, arg_3);
1496   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1497   pass_arg2(this, arg_2);
1498   pass_arg1(this, arg_1);
1499   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1500 }
1501 
1502 void MacroAssembler::call_VM_base(Register oop_result,
1503                                   Register java_thread,
1504                                   Register last_java_sp,
1505                                   address  entry_point,
1506                                   int      number_of_arguments,
1507                                   bool     check_exceptions) {
1508   // determine java_thread register
1509   if (!java_thread->is_valid()) {
1510 #ifdef _LP64
1511     java_thread = r15_thread;
1512 #else
1513     java_thread = rdi;
1514     get_thread(java_thread);
1515 #endif // LP64
1516   }
1517   // determine last_java_sp register
1518   if (!last_java_sp->is_valid()) {
1519     last_java_sp = rsp;
1520   }
1521   // debugging support
1522   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1523   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1524 #ifdef ASSERT
1525   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1526   // r12 is the heapbase.
1527   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1528 #endif // ASSERT
1529 
1530   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1531   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1532 
1533   // push java thread (becomes first argument of C function)
1534 
1535   NOT_LP64(push(java_thread); number_of_arguments++);
1536   LP64_ONLY(mov(c_rarg0, r15_thread));
1537 
1538   // set last Java frame before call
1539   assert(last_java_sp != rbp, "can't use ebp/rbp");
1540 
1541   // Only interpreter should have to set fp
1542   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1543 
1544   // do the call, remove parameters
1545   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1546 
1547   // restore the thread (cannot use the pushed argument since arguments
1548   // may be overwritten by C code generated by an optimizing compiler);
1549   // however can use the register value directly if it is callee saved.
1550   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1551     // rdi & rsi (also r15) are callee saved -> nothing to do
1552 #ifdef ASSERT
1553     guarantee(java_thread != rax, "change this code");
1554     push(rax);
1555     { Label L;
1556       get_thread(rax);
1557       cmpptr(java_thread, rax);
1558       jcc(Assembler::equal, L);
1559       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1560       bind(L);
1561     }
1562     pop(rax);
1563 #endif
1564   } else {
1565     get_thread(java_thread);
1566   }
1567   // reset last Java frame
1568   // Only interpreter should have to clear fp
1569   reset_last_Java_frame(java_thread, true);
1570 
1571    // C++ interp handles this in the interpreter
1572   check_and_handle_popframe(java_thread);
1573   check_and_handle_earlyret(java_thread);
1574 
1575   if (check_exceptions) {
1576     // check for pending exceptions (java_thread is set upon return)
1577     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1578 #ifndef _LP64
1579     jump_cc(Assembler::notEqual,
1580             RuntimeAddress(StubRoutines::forward_exception_entry()));
1581 #else
1582     // This used to conditionally jump to forward_exception however it is
1583     // possible if we relocate that the branch will not reach. So we must jump
1584     // around so we can always reach
1585 
1586     Label ok;
1587     jcc(Assembler::equal, ok);
1588     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1589     bind(ok);
1590 #endif // LP64
1591   }
1592 
1593   // get oop result if there is one and reset the value in the thread
1594   if (oop_result->is_valid()) {
1595     get_vm_result(oop_result, java_thread);
1596   }
1597 }
1598 
1599 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1600 
1601   // Calculate the value for last_Java_sp
1602   // somewhat subtle. call_VM does an intermediate call
1603   // which places a return address on the stack just under the
1604   // stack pointer as the user finsihed with it. This allows
1605   // use to retrieve last_Java_pc from last_Java_sp[-1].
1606   // On 32bit we then have to push additional args on the stack to accomplish
1607   // the actual requested call. On 64bit call_VM only can use register args
1608   // so the only extra space is the return address that call_VM created.
1609   // This hopefully explains the calculations here.
1610 
1611 #ifdef _LP64
1612   // We've pushed one address, correct last_Java_sp
1613   lea(rax, Address(rsp, wordSize));
1614 #else
1615   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1616 #endif // LP64
1617 
1618   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1619 
1620 }
1621 
1622 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1623 void MacroAssembler::call_VM_leaf0(address entry_point) {
1624   MacroAssembler::call_VM_leaf_base(entry_point, 0);
1625 }
1626 
1627 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1628   call_VM_leaf_base(entry_point, number_of_arguments);
1629 }
1630 
1631 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1632   pass_arg0(this, arg_0);
1633   call_VM_leaf(entry_point, 1);
1634 }
1635 
1636 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1637 
1638   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1639   pass_arg1(this, arg_1);
1640   pass_arg0(this, arg_0);
1641   call_VM_leaf(entry_point, 2);
1642 }
1643 
1644 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1645   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1646   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1647   pass_arg2(this, arg_2);
1648   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1649   pass_arg1(this, arg_1);
1650   pass_arg0(this, arg_0);
1651   call_VM_leaf(entry_point, 3);
1652 }
1653 
1654 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1655   pass_arg0(this, arg_0);
1656   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1657 }
1658 
1659 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1660 
1661   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1662   pass_arg1(this, arg_1);
1663   pass_arg0(this, arg_0);
1664   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1665 }
1666 
1667 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1668   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1669   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1670   pass_arg2(this, arg_2);
1671   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1672   pass_arg1(this, arg_1);
1673   pass_arg0(this, arg_0);
1674   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1675 }
1676 
1677 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1678   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1679   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1680   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1681   pass_arg3(this, arg_3);
1682   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1683   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1684   pass_arg2(this, arg_2);
1685   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1686   pass_arg1(this, arg_1);
1687   pass_arg0(this, arg_0);
1688   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1689 }
1690 
1691 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1692   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1693   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1694   verify_oop_msg(oop_result, "broken oop in call_VM_base");
1695 }
1696 
1697 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1698   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1699   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1700 }
1701 
1702 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1703 }
1704 
1705 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1706 }
1707 
1708 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1709   if (reachable(src1)) {
1710     cmpl(as_Address(src1), imm);
1711   } else {
1712     lea(rscratch1, src1);
1713     cmpl(Address(rscratch1, 0), imm);
1714   }
1715 }
1716 
1717 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1718   assert(!src2.is_lval(), "use cmpptr");
1719   if (reachable(src2)) {
1720     cmpl(src1, as_Address(src2));
1721   } else {
1722     lea(rscratch1, src2);
1723     cmpl(src1, Address(rscratch1, 0));
1724   }
1725 }
1726 
1727 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1728   Assembler::cmpl(src1, imm);
1729 }
1730 
1731 void MacroAssembler::cmp32(Register src1, Address src2) {
1732   Assembler::cmpl(src1, src2);
1733 }
1734 
1735 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1736   ucomisd(opr1, opr2);
1737 
1738   Label L;
1739   if (unordered_is_less) {
1740     movl(dst, -1);
1741     jcc(Assembler::parity, L);
1742     jcc(Assembler::below , L);
1743     movl(dst, 0);
1744     jcc(Assembler::equal , L);
1745     increment(dst);
1746   } else { // unordered is greater
1747     movl(dst, 1);
1748     jcc(Assembler::parity, L);
1749     jcc(Assembler::above , L);
1750     movl(dst, 0);
1751     jcc(Assembler::equal , L);
1752     decrementl(dst);
1753   }
1754   bind(L);
1755 }
1756 
1757 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1758   ucomiss(opr1, opr2);
1759 
1760   Label L;
1761   if (unordered_is_less) {
1762     movl(dst, -1);
1763     jcc(Assembler::parity, L);
1764     jcc(Assembler::below , L);
1765     movl(dst, 0);
1766     jcc(Assembler::equal , L);
1767     increment(dst);
1768   } else { // unordered is greater
1769     movl(dst, 1);
1770     jcc(Assembler::parity, L);
1771     jcc(Assembler::above , L);
1772     movl(dst, 0);
1773     jcc(Assembler::equal , L);
1774     decrementl(dst);
1775   }
1776   bind(L);
1777 }
1778 
1779 
1780 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1781   if (reachable(src1)) {
1782     cmpb(as_Address(src1), imm);
1783   } else {
1784     lea(rscratch1, src1);
1785     cmpb(Address(rscratch1, 0), imm);
1786   }
1787 }
1788 
1789 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1790 #ifdef _LP64
1791   if (src2.is_lval()) {
1792     movptr(rscratch1, src2);
1793     Assembler::cmpq(src1, rscratch1);
1794   } else if (reachable(src2)) {
1795     cmpq(src1, as_Address(src2));
1796   } else {
1797     lea(rscratch1, src2);
1798     Assembler::cmpq(src1, Address(rscratch1, 0));
1799   }
1800 #else
1801   if (src2.is_lval()) {
1802     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1803   } else {
1804     cmpl(src1, as_Address(src2));
1805   }
1806 #endif // _LP64
1807 }
1808 
1809 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1810   assert(src2.is_lval(), "not a mem-mem compare");
1811 #ifdef _LP64
1812   // moves src2's literal address
1813   movptr(rscratch1, src2);
1814   Assembler::cmpq(src1, rscratch1);
1815 #else
1816   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1817 #endif // _LP64
1818 }
1819 
1820 void MacroAssembler::cmpoop(Register src1, Register src2) {
1821   cmpptr(src1, src2);
1822 }
1823 
1824 void MacroAssembler::cmpoop(Register src1, Address src2) {
1825   cmpptr(src1, src2);
1826 }
1827 
1828 #ifdef _LP64
1829 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1830   movoop(rscratch1, src2);
1831   cmpptr(src1, rscratch1);
1832 }
1833 #endif
1834 
1835 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1836   if (reachable(adr)) {
1837     lock();
1838     cmpxchgptr(reg, as_Address(adr));
1839   } else {
1840     lea(rscratch1, adr);
1841     lock();
1842     cmpxchgptr(reg, Address(rscratch1, 0));
1843   }
1844 }
1845 
1846 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1847   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1848 }
1849 
1850 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1851   if (reachable(src)) {
1852     Assembler::comisd(dst, as_Address(src));
1853   } else {
1854     lea(rscratch1, src);
1855     Assembler::comisd(dst, Address(rscratch1, 0));
1856   }
1857 }
1858 
1859 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1860   if (reachable(src)) {
1861     Assembler::comiss(dst, as_Address(src));
1862   } else {
1863     lea(rscratch1, src);
1864     Assembler::comiss(dst, Address(rscratch1, 0));
1865   }
1866 }
1867 
1868 
1869 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1870   Condition negated_cond = negate_condition(cond);
1871   Label L;
1872   jcc(negated_cond, L);
1873   pushf(); // Preserve flags
1874   atomic_incl(counter_addr);
1875   popf();
1876   bind(L);
1877 }
1878 
1879 int MacroAssembler::corrected_idivl(Register reg) {
1880   // Full implementation of Java idiv and irem; checks for
1881   // special case as described in JVM spec., p.243 & p.271.
1882   // The function returns the (pc) offset of the idivl
1883   // instruction - may be needed for implicit exceptions.
1884   //
1885   //         normal case                           special case
1886   //
1887   // input : rax,: dividend                         min_int
1888   //         reg: divisor   (may not be rax,/rdx)   -1
1889   //
1890   // output: rax,: quotient  (= rax, idiv reg)       min_int
1891   //         rdx: remainder (= rax, irem reg)       0
1892   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1893   const int min_int = 0x80000000;
1894   Label normal_case, special_case;
1895 
1896   // check for special case
1897   cmpl(rax, min_int);
1898   jcc(Assembler::notEqual, normal_case);
1899   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1900   cmpl(reg, -1);
1901   jcc(Assembler::equal, special_case);
1902 
1903   // handle normal case
1904   bind(normal_case);
1905   cdql();
1906   int idivl_offset = offset();
1907   idivl(reg);
1908 
1909   // normal and special case exit
1910   bind(special_case);
1911 
1912   return idivl_offset;
1913 }
1914 
1915 
1916 
1917 void MacroAssembler::decrementl(Register reg, int value) {
1918   if (value == min_jint) {subl(reg, value) ; return; }
1919   if (value <  0) { incrementl(reg, -value); return; }
1920   if (value == 0) {                        ; return; }
1921   if (value == 1 && UseIncDec) { decl(reg) ; return; }
1922   /* else */      { subl(reg, value)       ; return; }
1923 }
1924 
1925 void MacroAssembler::decrementl(Address dst, int value) {
1926   if (value == min_jint) {subl(dst, value) ; return; }
1927   if (value <  0) { incrementl(dst, -value); return; }
1928   if (value == 0) {                        ; return; }
1929   if (value == 1 && UseIncDec) { decl(dst) ; return; }
1930   /* else */      { subl(dst, value)       ; return; }
1931 }
1932 
1933 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1934   assert (shift_value > 0, "illegal shift value");
1935   Label _is_positive;
1936   testl (reg, reg);
1937   jcc (Assembler::positive, _is_positive);
1938   int offset = (1 << shift_value) - 1 ;
1939 
1940   if (offset == 1) {
1941     incrementl(reg);
1942   } else {
1943     addl(reg, offset);
1944   }
1945 
1946   bind (_is_positive);
1947   sarl(reg, shift_value);
1948 }
1949 
1950 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
1951   if (reachable(src)) {
1952     Assembler::divsd(dst, as_Address(src));
1953   } else {
1954     lea(rscratch1, src);
1955     Assembler::divsd(dst, Address(rscratch1, 0));
1956   }
1957 }
1958 
1959 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
1960   if (reachable(src)) {
1961     Assembler::divss(dst, as_Address(src));
1962   } else {
1963     lea(rscratch1, src);
1964     Assembler::divss(dst, Address(rscratch1, 0));
1965   }
1966 }
1967 
1968 void MacroAssembler::enter() {
1969   push(rbp);
1970   mov(rbp, rsp);
1971 }
1972 
1973 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1974 void MacroAssembler::fat_nop() {
1975   if (UseAddressNop) {
1976     addr_nop_5();
1977   } else {
1978     emit_int8(0x26); // es:
1979     emit_int8(0x2e); // cs:
1980     emit_int8(0x64); // fs:
1981     emit_int8(0x65); // gs:
1982     emit_int8((unsigned char)0x90);
1983   }
1984 }
1985 
1986 #ifndef _LP64
1987 void MacroAssembler::fcmp(Register tmp) {
1988   fcmp(tmp, 1, true, true);
1989 }
1990 
1991 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
1992   assert(!pop_right || pop_left, "usage error");
1993   if (VM_Version::supports_cmov()) {
1994     assert(tmp == noreg, "unneeded temp");
1995     if (pop_left) {
1996       fucomip(index);
1997     } else {
1998       fucomi(index);
1999     }
2000     if (pop_right) {
2001       fpop();
2002     }
2003   } else {
2004     assert(tmp != noreg, "need temp");
2005     if (pop_left) {
2006       if (pop_right) {
2007         fcompp();
2008       } else {
2009         fcomp(index);
2010       }
2011     } else {
2012       fcom(index);
2013     }
2014     // convert FPU condition into eflags condition via rax,
2015     save_rax(tmp);
2016     fwait(); fnstsw_ax();
2017     sahf();
2018     restore_rax(tmp);
2019   }
2020   // condition codes set as follows:
2021   //
2022   // CF (corresponds to C0) if x < y
2023   // PF (corresponds to C2) if unordered
2024   // ZF (corresponds to C3) if x = y
2025 }
2026 
2027 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2028   fcmp2int(dst, unordered_is_less, 1, true, true);
2029 }
2030 
2031 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2032   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2033   Label L;
2034   if (unordered_is_less) {
2035     movl(dst, -1);
2036     jcc(Assembler::parity, L);
2037     jcc(Assembler::below , L);
2038     movl(dst, 0);
2039     jcc(Assembler::equal , L);
2040     increment(dst);
2041   } else { // unordered is greater
2042     movl(dst, 1);
2043     jcc(Assembler::parity, L);
2044     jcc(Assembler::above , L);
2045     movl(dst, 0);
2046     jcc(Assembler::equal , L);
2047     decrementl(dst);
2048   }
2049   bind(L);
2050 }
2051 
2052 void MacroAssembler::fld_d(AddressLiteral src) {
2053   fld_d(as_Address(src));
2054 }
2055 
2056 void MacroAssembler::fld_s(AddressLiteral src) {
2057   fld_s(as_Address(src));
2058 }
2059 
2060 void MacroAssembler::fldcw(AddressLiteral src) {
2061   Assembler::fldcw(as_Address(src));
2062 }
2063 
2064 void MacroAssembler::fpop() {
2065   ffree();
2066   fincstp();
2067 }
2068 
2069 void MacroAssembler::fremr(Register tmp) {
2070   save_rax(tmp);
2071   { Label L;
2072     bind(L);
2073     fprem();
2074     fwait(); fnstsw_ax();
2075     sahf();
2076     jcc(Assembler::parity, L);
2077   }
2078   restore_rax(tmp);
2079   // Result is in ST0.
2080   // Note: fxch & fpop to get rid of ST1
2081   // (otherwise FPU stack could overflow eventually)
2082   fxch(1);
2083   fpop();
2084 }
2085 
2086 void MacroAssembler::empty_FPU_stack() {
2087   if (VM_Version::supports_mmx()) {
2088     emms();
2089   } else {
2090     for (int i = 8; i-- > 0; ) ffree(i);
2091   }
2092 }
2093 #endif // !LP64
2094 
2095 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2096   if (reachable(src)) {
2097     Assembler::mulpd(dst, as_Address(src));
2098   } else {
2099     lea(rscratch1, src);
2100     Assembler::mulpd(dst, Address(rscratch1, 0));
2101   }
2102 }
2103 
2104 void MacroAssembler::load_float(Address src) {
2105 #ifdef _LP64
2106   movflt(xmm0, src);
2107 #else
2108   if (UseSSE >= 1) {
2109     movflt(xmm0, src);
2110   } else {
2111     fld_s(src);
2112   }
2113 #endif // LP64
2114 }
2115 
2116 void MacroAssembler::store_float(Address dst) {
2117 #ifdef _LP64
2118   movflt(dst, xmm0);
2119 #else
2120   if (UseSSE >= 1) {
2121     movflt(dst, xmm0);
2122   } else {
2123     fstp_s(dst);
2124   }
2125 #endif // LP64
2126 }
2127 
2128 void MacroAssembler::load_double(Address src) {
2129 #ifdef _LP64
2130   movdbl(xmm0, src);
2131 #else
2132   if (UseSSE >= 2) {
2133     movdbl(xmm0, src);
2134   } else {
2135     fld_d(src);
2136   }
2137 #endif // LP64
2138 }
2139 
2140 void MacroAssembler::store_double(Address dst) {
2141 #ifdef _LP64
2142   movdbl(dst, xmm0);
2143 #else
2144   if (UseSSE >= 2) {
2145     movdbl(dst, xmm0);
2146   } else {
2147     fstp_d(dst);
2148   }
2149 #endif // LP64
2150 }
2151 
2152 // dst = c = a * b + c
2153 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2154   Assembler::vfmadd231sd(c, a, b);
2155   if (dst != c) {
2156     movdbl(dst, c);
2157   }
2158 }
2159 
2160 // dst = c = a * b + c
2161 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2162   Assembler::vfmadd231ss(c, a, b);
2163   if (dst != c) {
2164     movflt(dst, c);
2165   }
2166 }
2167 
2168 // dst = c = a * b + c
2169 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2170   Assembler::vfmadd231pd(c, a, b, vector_len);
2171   if (dst != c) {
2172     vmovdqu(dst, c);
2173   }
2174 }
2175 
2176 // dst = c = a * b + c
2177 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2178   Assembler::vfmadd231ps(c, a, b, vector_len);
2179   if (dst != c) {
2180     vmovdqu(dst, c);
2181   }
2182 }
2183 
2184 // dst = c = a * b + c
2185 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2186   Assembler::vfmadd231pd(c, a, b, vector_len);
2187   if (dst != c) {
2188     vmovdqu(dst, c);
2189   }
2190 }
2191 
2192 // dst = c = a * b + c
2193 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2194   Assembler::vfmadd231ps(c, a, b, vector_len);
2195   if (dst != c) {
2196     vmovdqu(dst, c);
2197   }
2198 }
2199 
2200 void MacroAssembler::incrementl(AddressLiteral dst) {
2201   if (reachable(dst)) {
2202     incrementl(as_Address(dst));
2203   } else {
2204     lea(rscratch1, dst);
2205     incrementl(Address(rscratch1, 0));
2206   }
2207 }
2208 
2209 void MacroAssembler::incrementl(ArrayAddress dst) {
2210   incrementl(as_Address(dst));
2211 }
2212 
2213 void MacroAssembler::incrementl(Register reg, int value) {
2214   if (value == min_jint) {addl(reg, value) ; return; }
2215   if (value <  0) { decrementl(reg, -value); return; }
2216   if (value == 0) {                        ; return; }
2217   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2218   /* else */      { addl(reg, value)       ; return; }
2219 }
2220 
2221 void MacroAssembler::incrementl(Address dst, int value) {
2222   if (value == min_jint) {addl(dst, value) ; return; }
2223   if (value <  0) { decrementl(dst, -value); return; }
2224   if (value == 0) {                        ; return; }
2225   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2226   /* else */      { addl(dst, value)       ; return; }
2227 }
2228 
2229 void MacroAssembler::jump(AddressLiteral dst) {
2230   if (reachable(dst)) {
2231     jmp_literal(dst.target(), dst.rspec());
2232   } else {
2233     lea(rscratch1, dst);
2234     jmp(rscratch1);
2235   }
2236 }
2237 
2238 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2239   if (reachable(dst)) {
2240     InstructionMark im(this);
2241     relocate(dst.reloc());
2242     const int short_size = 2;
2243     const int long_size = 6;
2244     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2245     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2246       // 0111 tttn #8-bit disp
2247       emit_int8(0x70 | cc);
2248       emit_int8((offs - short_size) & 0xFF);
2249     } else {
2250       // 0000 1111 1000 tttn #32-bit disp
2251       emit_int8(0x0F);
2252       emit_int8((unsigned char)(0x80 | cc));
2253       emit_int32(offs - long_size);
2254     }
2255   } else {
2256 #ifdef ASSERT
2257     warning("reversing conditional branch");
2258 #endif /* ASSERT */
2259     Label skip;
2260     jccb(reverse[cc], skip);
2261     lea(rscratch1, dst);
2262     Assembler::jmp(rscratch1);
2263     bind(skip);
2264   }
2265 }
2266 
2267 void MacroAssembler::fld_x(AddressLiteral src) {
2268   Assembler::fld_x(as_Address(src));
2269 }
2270 
2271 void MacroAssembler::ldmxcsr(AddressLiteral src) {
2272   if (reachable(src)) {
2273     Assembler::ldmxcsr(as_Address(src));
2274   } else {
2275     lea(rscratch1, src);
2276     Assembler::ldmxcsr(Address(rscratch1, 0));
2277   }
2278 }
2279 
2280 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2281   int off;
2282   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2283     off = offset();
2284     movsbl(dst, src); // movsxb
2285   } else {
2286     off = load_unsigned_byte(dst, src);
2287     shll(dst, 24);
2288     sarl(dst, 24);
2289   }
2290   return off;
2291 }
2292 
2293 // Note: load_signed_short used to be called load_signed_word.
2294 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2295 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2296 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2297 int MacroAssembler::load_signed_short(Register dst, Address src) {
2298   int off;
2299   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2300     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2301     // version but this is what 64bit has always done. This seems to imply
2302     // that users are only using 32bits worth.
2303     off = offset();
2304     movswl(dst, src); // movsxw
2305   } else {
2306     off = load_unsigned_short(dst, src);
2307     shll(dst, 16);
2308     sarl(dst, 16);
2309   }
2310   return off;
2311 }
2312 
2313 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2314   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2315   // and "3.9 Partial Register Penalties", p. 22).
2316   int off;
2317   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2318     off = offset();
2319     movzbl(dst, src); // movzxb
2320   } else {
2321     xorl(dst, dst);
2322     off = offset();
2323     movb(dst, src);
2324   }
2325   return off;
2326 }
2327 
2328 // Note: load_unsigned_short used to be called load_unsigned_word.
2329 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2330   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2331   // and "3.9 Partial Register Penalties", p. 22).
2332   int off;
2333   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2334     off = offset();
2335     movzwl(dst, src); // movzxw
2336   } else {
2337     xorl(dst, dst);
2338     off = offset();
2339     movw(dst, src);
2340   }
2341   return off;
2342 }
2343 
2344 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2345   switch (size_in_bytes) {
2346 #ifndef _LP64
2347   case  8:
2348     assert(dst2 != noreg, "second dest register required");
2349     movl(dst,  src);
2350     movl(dst2, src.plus_disp(BytesPerInt));
2351     break;
2352 #else
2353   case  8:  movq(dst, src); break;
2354 #endif
2355   case  4:  movl(dst, src); break;
2356   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2357   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2358   default:  ShouldNotReachHere();
2359   }
2360 }
2361 
2362 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2363   switch (size_in_bytes) {
2364 #ifndef _LP64
2365   case  8:
2366     assert(src2 != noreg, "second source register required");
2367     movl(dst,                        src);
2368     movl(dst.plus_disp(BytesPerInt), src2);
2369     break;
2370 #else
2371   case  8:  movq(dst, src); break;
2372 #endif
2373   case  4:  movl(dst, src); break;
2374   case  2:  movw(dst, src); break;
2375   case  1:  movb(dst, src); break;
2376   default:  ShouldNotReachHere();
2377   }
2378 }
2379 
2380 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2381   if (reachable(dst)) {
2382     movl(as_Address(dst), src);
2383   } else {
2384     lea(rscratch1, dst);
2385     movl(Address(rscratch1, 0), src);
2386   }
2387 }
2388 
2389 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2390   if (reachable(src)) {
2391     movl(dst, as_Address(src));
2392   } else {
2393     lea(rscratch1, src);
2394     movl(dst, Address(rscratch1, 0));
2395   }
2396 }
2397 
2398 // C++ bool manipulation
2399 
2400 void MacroAssembler::movbool(Register dst, Address src) {
2401   if(sizeof(bool) == 1)
2402     movb(dst, src);
2403   else if(sizeof(bool) == 2)
2404     movw(dst, src);
2405   else if(sizeof(bool) == 4)
2406     movl(dst, src);
2407   else
2408     // unsupported
2409     ShouldNotReachHere();
2410 }
2411 
2412 void MacroAssembler::movbool(Address dst, bool boolconst) {
2413   if(sizeof(bool) == 1)
2414     movb(dst, (int) boolconst);
2415   else if(sizeof(bool) == 2)
2416     movw(dst, (int) boolconst);
2417   else if(sizeof(bool) == 4)
2418     movl(dst, (int) boolconst);
2419   else
2420     // unsupported
2421     ShouldNotReachHere();
2422 }
2423 
2424 void MacroAssembler::movbool(Address dst, Register src) {
2425   if(sizeof(bool) == 1)
2426     movb(dst, src);
2427   else if(sizeof(bool) == 2)
2428     movw(dst, src);
2429   else if(sizeof(bool) == 4)
2430     movl(dst, src);
2431   else
2432     // unsupported
2433     ShouldNotReachHere();
2434 }
2435 
2436 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2437   movb(as_Address(dst), src);
2438 }
2439 
2440 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2441   if (reachable(src)) {
2442     movdl(dst, as_Address(src));
2443   } else {
2444     lea(rscratch1, src);
2445     movdl(dst, Address(rscratch1, 0));
2446   }
2447 }
2448 
2449 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2450   if (reachable(src)) {
2451     movq(dst, as_Address(src));
2452   } else {
2453     lea(rscratch1, src);
2454     movq(dst, Address(rscratch1, 0));
2455   }
2456 }
2457 
2458 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2459   if (reachable(src)) {
2460     if (UseXmmLoadAndClearUpper) {
2461       movsd (dst, as_Address(src));
2462     } else {
2463       movlpd(dst, as_Address(src));
2464     }
2465   } else {
2466     lea(rscratch1, src);
2467     if (UseXmmLoadAndClearUpper) {
2468       movsd (dst, Address(rscratch1, 0));
2469     } else {
2470       movlpd(dst, Address(rscratch1, 0));
2471     }
2472   }
2473 }
2474 
2475 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2476   if (reachable(src)) {
2477     movss(dst, as_Address(src));
2478   } else {
2479     lea(rscratch1, src);
2480     movss(dst, Address(rscratch1, 0));
2481   }
2482 }
2483 
2484 void MacroAssembler::movptr(Register dst, Register src) {
2485   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2486 }
2487 
2488 void MacroAssembler::movptr(Register dst, Address src) {
2489   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2490 }
2491 
2492 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2493 void MacroAssembler::movptr(Register dst, intptr_t src) {
2494   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2495 }
2496 
2497 void MacroAssembler::movptr(Address dst, Register src) {
2498   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2499 }
2500 
2501 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2502     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2503     Assembler::movdqu(dst, src);
2504 }
2505 
2506 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2507     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2508     Assembler::movdqu(dst, src);
2509 }
2510 
2511 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2512     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2513     Assembler::movdqu(dst, src);
2514 }
2515 
2516 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2517   if (reachable(src)) {
2518     movdqu(dst, as_Address(src));
2519   } else {
2520     lea(scratchReg, src);
2521     movdqu(dst, Address(scratchReg, 0));
2522   }
2523 }
2524 
2525 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2526     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2527     Assembler::vmovdqu(dst, src);
2528 }
2529 
2530 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2531     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2532     Assembler::vmovdqu(dst, src);
2533 }
2534 
2535 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2536     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2537     Assembler::vmovdqu(dst, src);
2538 }
2539 
2540 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2541   if (reachable(src)) {
2542     vmovdqu(dst, as_Address(src));
2543   }
2544   else {
2545     lea(scratch_reg, src);
2546     vmovdqu(dst, Address(scratch_reg, 0));
2547   }
2548 }
2549 
2550 void MacroAssembler::kmov(KRegister dst, Address src) {
2551   if (VM_Version::supports_avx512bw()) {
2552     kmovql(dst, src);
2553   } else {
2554     assert(VM_Version::supports_evex(), "");
2555     kmovwl(dst, src);
2556   }
2557 }
2558 
2559 void MacroAssembler::kmov(Address dst, KRegister src) {
2560   if (VM_Version::supports_avx512bw()) {
2561     kmovql(dst, src);
2562   } else {
2563     assert(VM_Version::supports_evex(), "");
2564     kmovwl(dst, src);
2565   }
2566 }
2567 
2568 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2569   if (VM_Version::supports_avx512bw()) {
2570     kmovql(dst, src);
2571   } else {
2572     assert(VM_Version::supports_evex(), "");
2573     kmovwl(dst, src);
2574   }
2575 }
2576 
2577 void MacroAssembler::kmov(Register dst, KRegister src) {
2578   if (VM_Version::supports_avx512bw()) {
2579     kmovql(dst, src);
2580   } else {
2581     assert(VM_Version::supports_evex(), "");
2582     kmovwl(dst, src);
2583   }
2584 }
2585 
2586 void MacroAssembler::kmov(KRegister dst, Register src) {
2587   if (VM_Version::supports_avx512bw()) {
2588     kmovql(dst, src);
2589   } else {
2590     assert(VM_Version::supports_evex(), "");
2591     kmovwl(dst, src);
2592   }
2593 }
2594 
2595 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2596   if (reachable(src)) {
2597     kmovql(dst, as_Address(src));
2598   } else {
2599     lea(scratch_reg, src);
2600     kmovql(dst, Address(scratch_reg, 0));
2601   }
2602 }
2603 
2604 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2605   if (reachable(src)) {
2606     kmovwl(dst, as_Address(src));
2607   } else {
2608     lea(scratch_reg, src);
2609     kmovwl(dst, Address(scratch_reg, 0));
2610   }
2611 }
2612 
2613 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2614                                int vector_len, Register scratch_reg) {
2615   if (reachable(src)) {
2616     if (mask == k0) {
2617       Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2618     } else {
2619       Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2620     }
2621   } else {
2622     lea(scratch_reg, src);
2623     if (mask == k0) {
2624       Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2625     } else {
2626       Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2627     }
2628   }
2629 }
2630 
2631 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2632                                int vector_len, Register scratch_reg) {
2633   if (reachable(src)) {
2634     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2635   } else {
2636     lea(scratch_reg, src);
2637     Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2638   }
2639 }
2640 
2641 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2642                                int vector_len, Register scratch_reg) {
2643   if (reachable(src)) {
2644     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2645   } else {
2646     lea(scratch_reg, src);
2647     Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2648   }
2649 }
2650 
2651 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2652                                int vector_len, Register scratch_reg) {
2653   if (reachable(src)) {
2654     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2655   } else {
2656     lea(scratch_reg, src);
2657     Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2658   }
2659 }
2660 
2661 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2662   if (reachable(src)) {
2663     Assembler::evmovdquq(dst, as_Address(src), vector_len);
2664   } else {
2665     lea(rscratch, src);
2666     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2667   }
2668 }
2669 
2670 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2671   if (reachable(src)) {
2672     Assembler::movdqa(dst, as_Address(src));
2673   } else {
2674     lea(rscratch1, src);
2675     Assembler::movdqa(dst, Address(rscratch1, 0));
2676   }
2677 }
2678 
2679 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2680   if (reachable(src)) {
2681     Assembler::movsd(dst, as_Address(src));
2682   } else {
2683     lea(rscratch1, src);
2684     Assembler::movsd(dst, Address(rscratch1, 0));
2685   }
2686 }
2687 
2688 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2689   if (reachable(src)) {
2690     Assembler::movss(dst, as_Address(src));
2691   } else {
2692     lea(rscratch1, src);
2693     Assembler::movss(dst, Address(rscratch1, 0));
2694   }
2695 }
2696 
2697 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2698   if (reachable(src)) {
2699     Assembler::mulsd(dst, as_Address(src));
2700   } else {
2701     lea(rscratch1, src);
2702     Assembler::mulsd(dst, Address(rscratch1, 0));
2703   }
2704 }
2705 
2706 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2707   if (reachable(src)) {
2708     Assembler::mulss(dst, as_Address(src));
2709   } else {
2710     lea(rscratch1, src);
2711     Assembler::mulss(dst, Address(rscratch1, 0));
2712   }
2713 }
2714 
2715 void MacroAssembler::null_check(Register reg, int offset) {
2716   if (needs_explicit_null_check(offset)) {
2717     // provoke OS NULL exception if reg = NULL by
2718     // accessing M[reg] w/o changing any (non-CC) registers
2719     // NOTE: cmpl is plenty here to provoke a segv
2720     cmpptr(rax, Address(reg, 0));
2721     // Note: should probably use testl(rax, Address(reg, 0));
2722     //       may be shorter code (however, this version of
2723     //       testl needs to be implemented first)
2724   } else {
2725     // nothing to do, (later) access of M[reg + offset]
2726     // will provoke OS NULL exception if reg = NULL
2727   }
2728 }
2729 
2730 void MacroAssembler::os_breakpoint() {
2731   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2732   // (e.g., MSVC can't call ps() otherwise)
2733   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2734 }
2735 
2736 void MacroAssembler::unimplemented(const char* what) {
2737   const char* buf = NULL;
2738   {
2739     ResourceMark rm;
2740     stringStream ss;
2741     ss.print("unimplemented: %s", what);
2742     buf = code_string(ss.as_string());
2743   }
2744   stop(buf);
2745 }
2746 
2747 #ifdef _LP64
2748 #define XSTATE_BV 0x200
2749 #endif
2750 
2751 void MacroAssembler::pop_CPU_state() {
2752   pop_FPU_state();
2753   pop_IU_state();
2754 }
2755 
2756 void MacroAssembler::pop_FPU_state() {
2757 #ifndef _LP64
2758   frstor(Address(rsp, 0));
2759 #else
2760   fxrstor(Address(rsp, 0));
2761 #endif
2762   addptr(rsp, FPUStateSizeInWords * wordSize);
2763 }
2764 
2765 void MacroAssembler::pop_IU_state() {
2766   popa();
2767   LP64_ONLY(addq(rsp, 8));
2768   popf();
2769 }
2770 
2771 // Save Integer and Float state
2772 // Warning: Stack must be 16 byte aligned (64bit)
2773 void MacroAssembler::push_CPU_state() {
2774   push_IU_state();
2775   push_FPU_state();
2776 }
2777 
2778 void MacroAssembler::push_FPU_state() {
2779   subptr(rsp, FPUStateSizeInWords * wordSize);
2780 #ifndef _LP64
2781   fnsave(Address(rsp, 0));
2782   fwait();
2783 #else
2784   fxsave(Address(rsp, 0));
2785 #endif // LP64
2786 }
2787 
2788 void MacroAssembler::push_IU_state() {
2789   // Push flags first because pusha kills them
2790   pushf();
2791   // Make sure rsp stays 16-byte aligned
2792   LP64_ONLY(subq(rsp, 8));
2793   pusha();
2794 }
2795 
2796 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2797   if (!java_thread->is_valid()) {
2798     java_thread = rdi;
2799     get_thread(java_thread);
2800   }
2801   // we must set sp to zero to clear frame
2802   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2803   // must clear fp, so that compiled frames are not confused; it is
2804   // possible that we need it only for debugging
2805   if (clear_fp) {
2806     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2807   }
2808   // Always clear the pc because it could have been set by make_walkable()
2809   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2810   vzeroupper();
2811 }
2812 
2813 void MacroAssembler::restore_rax(Register tmp) {
2814   if (tmp == noreg) pop(rax);
2815   else if (tmp != rax) mov(rax, tmp);
2816 }
2817 
2818 void MacroAssembler::round_to(Register reg, int modulus) {
2819   addptr(reg, modulus - 1);
2820   andptr(reg, -modulus);
2821 }
2822 
2823 void MacroAssembler::save_rax(Register tmp) {
2824   if (tmp == noreg) push(rax);
2825   else if (tmp != rax) mov(tmp, rax);
2826 }
2827 
2828 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2829   if (at_return) {
2830     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2831     // we may safely use rsp instead to perform the stack watermark check.
2832     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2833     jcc(Assembler::above, slow_path);
2834     return;
2835   }
2836   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2837   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2838 }
2839 
2840 // Calls to C land
2841 //
2842 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2843 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2844 // has to be reset to 0. This is required to allow proper stack traversal.
2845 void MacroAssembler::set_last_Java_frame(Register java_thread,
2846                                          Register last_java_sp,
2847                                          Register last_java_fp,
2848                                          address  last_java_pc) {
2849   vzeroupper();
2850   // determine java_thread register
2851   if (!java_thread->is_valid()) {
2852     java_thread = rdi;
2853     get_thread(java_thread);
2854   }
2855   // determine last_java_sp register
2856   if (!last_java_sp->is_valid()) {
2857     last_java_sp = rsp;
2858   }
2859 
2860   // last_java_fp is optional
2861 
2862   if (last_java_fp->is_valid()) {
2863     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2864   }
2865 
2866   // last_java_pc is optional
2867 
2868   if (last_java_pc != NULL) {
2869     lea(Address(java_thread,
2870                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
2871         InternalAddress(last_java_pc));
2872 
2873   }
2874   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2875 }
2876 
2877 void MacroAssembler::shlptr(Register dst, int imm8) {
2878   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
2879 }
2880 
2881 void MacroAssembler::shrptr(Register dst, int imm8) {
2882   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
2883 }
2884 
2885 void MacroAssembler::sign_extend_byte(Register reg) {
2886   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
2887     movsbl(reg, reg); // movsxb
2888   } else {
2889     shll(reg, 24);
2890     sarl(reg, 24);
2891   }
2892 }
2893 
2894 void MacroAssembler::sign_extend_short(Register reg) {
2895   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2896     movswl(reg, reg); // movsxw
2897   } else {
2898     shll(reg, 16);
2899     sarl(reg, 16);
2900   }
2901 }
2902 
2903 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2904   assert(reachable(src), "Address should be reachable");
2905   testl(dst, as_Address(src));
2906 }
2907 
2908 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2909   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2910   Assembler::pcmpeqb(dst, src);
2911 }
2912 
2913 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2914   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2915   Assembler::pcmpeqw(dst, src);
2916 }
2917 
2918 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2919   assert((dst->encoding() < 16),"XMM register should be 0-15");
2920   Assembler::pcmpestri(dst, src, imm8);
2921 }
2922 
2923 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2924   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2925   Assembler::pcmpestri(dst, src, imm8);
2926 }
2927 
2928 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2929   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2930   Assembler::pmovzxbw(dst, src);
2931 }
2932 
2933 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2934   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2935   Assembler::pmovzxbw(dst, src);
2936 }
2937 
2938 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2939   assert((src->encoding() < 16),"XMM register should be 0-15");
2940   Assembler::pmovmskb(dst, src);
2941 }
2942 
2943 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2944   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2945   Assembler::ptest(dst, src);
2946 }
2947 
2948 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
2949   if (reachable(src)) {
2950     Assembler::sqrtsd(dst, as_Address(src));
2951   } else {
2952     lea(rscratch1, src);
2953     Assembler::sqrtsd(dst, Address(rscratch1, 0));
2954   }
2955 }
2956 
2957 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
2958   if (reachable(src)) {
2959     Assembler::sqrtss(dst, as_Address(src));
2960   } else {
2961     lea(rscratch1, src);
2962     Assembler::sqrtss(dst, Address(rscratch1, 0));
2963   }
2964 }
2965 
2966 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
2967   if (reachable(src)) {
2968     Assembler::subsd(dst, as_Address(src));
2969   } else {
2970     lea(rscratch1, src);
2971     Assembler::subsd(dst, Address(rscratch1, 0));
2972   }
2973 }
2974 
2975 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
2976   if (reachable(src)) {
2977     Assembler::roundsd(dst, as_Address(src), rmode);
2978   } else {
2979     lea(scratch_reg, src);
2980     Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
2981   }
2982 }
2983 
2984 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
2985   if (reachable(src)) {
2986     Assembler::subss(dst, as_Address(src));
2987   } else {
2988     lea(rscratch1, src);
2989     Assembler::subss(dst, Address(rscratch1, 0));
2990   }
2991 }
2992 
2993 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2994   if (reachable(src)) {
2995     Assembler::ucomisd(dst, as_Address(src));
2996   } else {
2997     lea(rscratch1, src);
2998     Assembler::ucomisd(dst, Address(rscratch1, 0));
2999   }
3000 }
3001 
3002 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3003   if (reachable(src)) {
3004     Assembler::ucomiss(dst, as_Address(src));
3005   } else {
3006     lea(rscratch1, src);
3007     Assembler::ucomiss(dst, Address(rscratch1, 0));
3008   }
3009 }
3010 
3011 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3012   // Used in sign-bit flipping with aligned address.
3013   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3014   if (reachable(src)) {
3015     Assembler::xorpd(dst, as_Address(src));
3016   } else {
3017     lea(scratch_reg, src);
3018     Assembler::xorpd(dst, Address(scratch_reg, 0));
3019   }
3020 }
3021 
3022 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3023   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3024     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3025   }
3026   else {
3027     Assembler::xorpd(dst, src);
3028   }
3029 }
3030 
3031 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3032   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3033     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3034   } else {
3035     Assembler::xorps(dst, src);
3036   }
3037 }
3038 
3039 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3040   // Used in sign-bit flipping with aligned address.
3041   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3042   if (reachable(src)) {
3043     Assembler::xorps(dst, as_Address(src));
3044   } else {
3045     lea(scratch_reg, src);
3046     Assembler::xorps(dst, Address(scratch_reg, 0));
3047   }
3048 }
3049 
3050 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3051   // Used in sign-bit flipping with aligned address.
3052   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3053   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3054   if (reachable(src)) {
3055     Assembler::pshufb(dst, as_Address(src));
3056   } else {
3057     lea(rscratch1, src);
3058     Assembler::pshufb(dst, Address(rscratch1, 0));
3059   }
3060 }
3061 
3062 // AVX 3-operands instructions
3063 
3064 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3065   if (reachable(src)) {
3066     vaddsd(dst, nds, as_Address(src));
3067   } else {
3068     lea(rscratch1, src);
3069     vaddsd(dst, nds, Address(rscratch1, 0));
3070   }
3071 }
3072 
3073 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3074   if (reachable(src)) {
3075     vaddss(dst, nds, as_Address(src));
3076   } else {
3077     lea(rscratch1, src);
3078     vaddss(dst, nds, Address(rscratch1, 0));
3079   }
3080 }
3081 
3082 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3083   assert(UseAVX > 0, "requires some form of AVX");
3084   if (reachable(src)) {
3085     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3086   } else {
3087     lea(rscratch, src);
3088     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3089   }
3090 }
3091 
3092 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3093   assert(UseAVX > 0, "requires some form of AVX");
3094   if (reachable(src)) {
3095     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3096   } else {
3097     lea(rscratch, src);
3098     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3099   }
3100 }
3101 
3102 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3103   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3104   vandps(dst, nds, negate_field, vector_len);
3105 }
3106 
3107 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3108   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3109   vandpd(dst, nds, negate_field, vector_len);
3110 }
3111 
3112 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3113   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3114   Assembler::vpaddb(dst, nds, src, vector_len);
3115 }
3116 
3117 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3118   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3119   Assembler::vpaddb(dst, nds, src, vector_len);
3120 }
3121 
3122 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3123   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3124   Assembler::vpaddw(dst, nds, src, vector_len);
3125 }
3126 
3127 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3128   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3129   Assembler::vpaddw(dst, nds, src, vector_len);
3130 }
3131 
3132 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3133   if (reachable(src)) {
3134     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3135   } else {
3136     lea(scratch_reg, src);
3137     Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3138   }
3139 }
3140 
3141 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3142   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3143   Assembler::vpbroadcastw(dst, src, vector_len);
3144 }
3145 
3146 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3147   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3148   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3149 }
3150 
3151 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3152   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3153   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3154 }
3155 
3156 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3157                                AddressLiteral src, int vector_len, Register scratch_reg) {
3158   if (reachable(src)) {
3159     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3160   } else {
3161     lea(scratch_reg, src);
3162     Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3163   }
3164 }
3165 
3166 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3167                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3168   if (reachable(src)) {
3169     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3170   } else {
3171     lea(scratch_reg, src);
3172     Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3173   }
3174 }
3175 
3176 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3177                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3178   if (reachable(src)) {
3179     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3180   } else {
3181     lea(scratch_reg, src);
3182     Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3183   }
3184 }
3185 
3186 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3187                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3188   if (reachable(src)) {
3189     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3190   } else {
3191     lea(scratch_reg, src);
3192     Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3193   }
3194 }
3195 
3196 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3197                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3198   if (reachable(src)) {
3199     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3200   } else {
3201     lea(scratch_reg, src);
3202     Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3203   }
3204 }
3205 
3206 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3207   if (width == Assembler::Q) {
3208     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3209   } else {
3210     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3211   }
3212 }
3213 
3214 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, ComparisonPredicate cond, Width width, int vector_len, Register scratch_reg) {
3215   int eq_cond_enc = 0x29;
3216   int gt_cond_enc = 0x37;
3217   if (width != Assembler::Q) {
3218     eq_cond_enc = 0x74 + width;
3219     gt_cond_enc = 0x64 + width;
3220   }
3221   switch (cond) {
3222   case eq:
3223     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3224     break;
3225   case neq:
3226     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3227     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3228     break;
3229   case le:
3230     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3231     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3232     break;
3233   case nlt:
3234     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3235     vpxor(dst, dst, ExternalAddress(StubRoutines::x86::vector_all_bits_set()), vector_len, scratch_reg);
3236     break;
3237   case lt:
3238     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3239     break;
3240   case nle:
3241     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3242     break;
3243   default:
3244     assert(false, "Should not reach here");
3245   }
3246 }
3247 
3248 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3249   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3250   Assembler::vpmovzxbw(dst, src, vector_len);
3251 }
3252 
3253 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3254   assert((src->encoding() < 16),"XMM register should be 0-15");
3255   Assembler::vpmovmskb(dst, src, vector_len);
3256 }
3257 
3258 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3259   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3260   Assembler::vpmullw(dst, nds, src, vector_len);
3261 }
3262 
3263 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3264   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3265   Assembler::vpmullw(dst, nds, src, vector_len);
3266 }
3267 
3268 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3269   assert((UseAVX > 0), "AVX support is needed");
3270   if (reachable(src)) {
3271     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3272   } else {
3273     lea(scratch_reg, src);
3274     Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3275   }
3276 }
3277 
3278 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3279   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3280   Assembler::vpsubb(dst, nds, src, vector_len);
3281 }
3282 
3283 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3284   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3285   Assembler::vpsubb(dst, nds, src, vector_len);
3286 }
3287 
3288 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3289   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3290   Assembler::vpsubw(dst, nds, src, vector_len);
3291 }
3292 
3293 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3294   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3295   Assembler::vpsubw(dst, nds, src, vector_len);
3296 }
3297 
3298 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3299   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3300   Assembler::vpsraw(dst, nds, shift, vector_len);
3301 }
3302 
3303 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3304   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3305   Assembler::vpsraw(dst, nds, shift, vector_len);
3306 }
3307 
3308 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3309   assert(UseAVX > 2,"");
3310   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3311      vector_len = 2;
3312   }
3313   Assembler::evpsraq(dst, nds, shift, vector_len);
3314 }
3315 
3316 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3317   assert(UseAVX > 2,"");
3318   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3319      vector_len = 2;
3320   }
3321   Assembler::evpsraq(dst, nds, shift, vector_len);
3322 }
3323 
3324 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3325   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3326   Assembler::vpsrlw(dst, nds, shift, vector_len);
3327 }
3328 
3329 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3330   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3331   Assembler::vpsrlw(dst, nds, shift, vector_len);
3332 }
3333 
3334 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3335   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3336   Assembler::vpsllw(dst, nds, shift, vector_len);
3337 }
3338 
3339 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3340   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3341   Assembler::vpsllw(dst, nds, shift, vector_len);
3342 }
3343 
3344 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3345   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3346   Assembler::vptest(dst, src);
3347 }
3348 
3349 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3350   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3351   Assembler::punpcklbw(dst, src);
3352 }
3353 
3354 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3355   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3356   Assembler::pshufd(dst, src, mode);
3357 }
3358 
3359 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3360   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3361   Assembler::pshuflw(dst, src, mode);
3362 }
3363 
3364 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3365   if (reachable(src)) {
3366     vandpd(dst, nds, as_Address(src), vector_len);
3367   } else {
3368     lea(scratch_reg, src);
3369     vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3370   }
3371 }
3372 
3373 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3374   if (reachable(src)) {
3375     vandps(dst, nds, as_Address(src), vector_len);
3376   } else {
3377     lea(scratch_reg, src);
3378     vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3379   }
3380 }
3381 
3382 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3383                             bool merge, int vector_len, Register scratch_reg) {
3384   if (reachable(src)) {
3385     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3386   } else {
3387     lea(scratch_reg, src);
3388     Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3389   }
3390 }
3391 
3392 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3393   if (reachable(src)) {
3394     vdivsd(dst, nds, as_Address(src));
3395   } else {
3396     lea(rscratch1, src);
3397     vdivsd(dst, nds, Address(rscratch1, 0));
3398   }
3399 }
3400 
3401 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3402   if (reachable(src)) {
3403     vdivss(dst, nds, as_Address(src));
3404   } else {
3405     lea(rscratch1, src);
3406     vdivss(dst, nds, Address(rscratch1, 0));
3407   }
3408 }
3409 
3410 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3411   if (reachable(src)) {
3412     vmulsd(dst, nds, as_Address(src));
3413   } else {
3414     lea(rscratch1, src);
3415     vmulsd(dst, nds, Address(rscratch1, 0));
3416   }
3417 }
3418 
3419 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3420   if (reachable(src)) {
3421     vmulss(dst, nds, as_Address(src));
3422   } else {
3423     lea(rscratch1, src);
3424     vmulss(dst, nds, Address(rscratch1, 0));
3425   }
3426 }
3427 
3428 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3429   if (reachable(src)) {
3430     vsubsd(dst, nds, as_Address(src));
3431   } else {
3432     lea(rscratch1, src);
3433     vsubsd(dst, nds, Address(rscratch1, 0));
3434   }
3435 }
3436 
3437 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3438   if (reachable(src)) {
3439     vsubss(dst, nds, as_Address(src));
3440   } else {
3441     lea(rscratch1, src);
3442     vsubss(dst, nds, Address(rscratch1, 0));
3443   }
3444 }
3445 
3446 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3447   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3448   vxorps(dst, nds, src, Assembler::AVX_128bit);
3449 }
3450 
3451 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3452   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3453   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3454 }
3455 
3456 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3457   if (reachable(src)) {
3458     vxorpd(dst, nds, as_Address(src), vector_len);
3459   } else {
3460     lea(scratch_reg, src);
3461     vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3462   }
3463 }
3464 
3465 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3466   if (reachable(src)) {
3467     vxorps(dst, nds, as_Address(src), vector_len);
3468   } else {
3469     lea(scratch_reg, src);
3470     vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3471   }
3472 }
3473 
3474 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3475   if (UseAVX > 1 || (vector_len < 1)) {
3476     if (reachable(src)) {
3477       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3478     } else {
3479       lea(scratch_reg, src);
3480       Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3481     }
3482   }
3483   else {
3484     MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3485   }
3486 }
3487 
3488 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3489   if (reachable(src)) {
3490     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3491   } else {
3492     lea(scratch_reg, src);
3493     Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3494   }
3495 }
3496 
3497 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3498   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3499   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3500   // The inverted mask is sign-extended
3501   andptr(possibly_jweak, inverted_jweak_mask);
3502 }
3503 
3504 void MacroAssembler::resolve_jobject(Register value,
3505                                      Register thread,
3506                                      Register tmp) {
3507   assert_different_registers(value, thread, tmp);
3508   Label done, not_weak;
3509   testptr(value, value);
3510   jcc(Assembler::zero, done);                // Use NULL as-is.
3511   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3512   jcc(Assembler::zero, not_weak);
3513   // Resolve jweak.
3514   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3515                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3516   verify_oop(value);
3517   jmp(done);
3518   bind(not_weak);
3519   // Resolve (untagged) jobject.
3520   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3521   verify_oop(value);
3522   bind(done);
3523 }
3524 
3525 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3526   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3527 }
3528 
3529 // Force generation of a 4 byte immediate value even if it fits into 8bit
3530 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3531   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3532 }
3533 
3534 void MacroAssembler::subptr(Register dst, Register src) {
3535   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3536 }
3537 
3538 // C++ bool manipulation
3539 void MacroAssembler::testbool(Register dst) {
3540   if(sizeof(bool) == 1)
3541     testb(dst, 0xff);
3542   else if(sizeof(bool) == 2) {
3543     // testw implementation needed for two byte bools
3544     ShouldNotReachHere();
3545   } else if(sizeof(bool) == 4)
3546     testl(dst, dst);
3547   else
3548     // unsupported
3549     ShouldNotReachHere();
3550 }
3551 
3552 void MacroAssembler::testptr(Register dst, Register src) {
3553   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3554 }
3555 
3556 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3557 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3558                                    Register var_size_in_bytes,
3559                                    int con_size_in_bytes,
3560                                    Register t1,
3561                                    Register t2,
3562                                    Label& slow_case) {
3563   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3564   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3565 }
3566 
3567 // Defines obj, preserves var_size_in_bytes
3568 void MacroAssembler::eden_allocate(Register thread, Register obj,
3569                                    Register var_size_in_bytes,
3570                                    int con_size_in_bytes,
3571                                    Register t1,
3572                                    Label& slow_case) {
3573   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3574   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3575 }
3576 
3577 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3578 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3579   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3580   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3581   Label done;
3582 
3583   testptr(length_in_bytes, length_in_bytes);
3584   jcc(Assembler::zero, done);
3585 
3586   // initialize topmost word, divide index by 2, check if odd and test if zero
3587   // note: for the remaining code to work, index must be a multiple of BytesPerWord
3588 #ifdef ASSERT
3589   {
3590     Label L;
3591     testptr(length_in_bytes, BytesPerWord - 1);
3592     jcc(Assembler::zero, L);
3593     stop("length must be a multiple of BytesPerWord");
3594     bind(L);
3595   }
3596 #endif
3597   Register index = length_in_bytes;
3598   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
3599   if (UseIncDec) {
3600     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
3601   } else {
3602     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
3603     shrptr(index, 1);
3604   }
3605 #ifndef _LP64
3606   // index could have not been a multiple of 8 (i.e., bit 2 was set)
3607   {
3608     Label even;
3609     // note: if index was a multiple of 8, then it cannot
3610     //       be 0 now otherwise it must have been 0 before
3611     //       => if it is even, we don't need to check for 0 again
3612     jcc(Assembler::carryClear, even);
3613     // clear topmost word (no jump would be needed if conditional assignment worked here)
3614     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3615     // index could be 0 now, must check again
3616     jcc(Assembler::zero, done);
3617     bind(even);
3618   }
3619 #endif // !_LP64
3620   // initialize remaining object fields: index is a multiple of 2 now
3621   {
3622     Label loop;
3623     bind(loop);
3624     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3625     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3626     decrement(index);
3627     jcc(Assembler::notZero, loop);
3628   }
3629 
3630   bind(done);
3631 }
3632 
3633 // Look up the method for a megamorphic invokeinterface call.
3634 // The target method is determined by <intf_klass, itable_index>.
3635 // The receiver klass is in recv_klass.
3636 // On success, the result will be in method_result, and execution falls through.
3637 // On failure, execution transfers to the given label.
3638 void MacroAssembler::lookup_interface_method(Register recv_klass,
3639                                              Register intf_klass,
3640                                              RegisterOrConstant itable_index,
3641                                              Register method_result,
3642                                              Register scan_temp,
3643                                              Label& L_no_such_interface,
3644                                              bool return_method) {
3645   assert_different_registers(recv_klass, intf_klass, scan_temp);
3646   assert_different_registers(method_result, intf_klass, scan_temp);
3647   assert(recv_klass != method_result || !return_method,
3648          "recv_klass can be destroyed when method isn't needed");
3649 
3650   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3651          "caller must use same register for non-constant itable index as for method");
3652 
3653   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3654   int vtable_base = in_bytes(Klass::vtable_start_offset());
3655   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3656   int scan_step   = itableOffsetEntry::size() * wordSize;
3657   int vte_size    = vtableEntry::size_in_bytes();
3658   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3659   assert(vte_size == wordSize, "else adjust times_vte_scale");
3660 
3661   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3662 
3663   // %%% Could store the aligned, prescaled offset in the klassoop.
3664   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3665 
3666   if (return_method) {
3667     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3668     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3669     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3670   }
3671 
3672   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3673   //   if (scan->interface() == intf) {
3674   //     result = (klass + scan->offset() + itable_index);
3675   //   }
3676   // }
3677   Label search, found_method;
3678 
3679   for (int peel = 1; peel >= 0; peel--) {
3680     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3681     cmpptr(intf_klass, method_result);
3682 
3683     if (peel) {
3684       jccb(Assembler::equal, found_method);
3685     } else {
3686       jccb(Assembler::notEqual, search);
3687       // (invert the test to fall through to found_method...)
3688     }
3689 
3690     if (!peel)  break;
3691 
3692     bind(search);
3693 
3694     // Check that the previous entry is non-null.  A null entry means that
3695     // the receiver class doesn't implement the interface, and wasn't the
3696     // same as when the caller was compiled.
3697     testptr(method_result, method_result);
3698     jcc(Assembler::zero, L_no_such_interface);
3699     addptr(scan_temp, scan_step);
3700   }
3701 
3702   bind(found_method);
3703 
3704   if (return_method) {
3705     // Got a hit.
3706     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
3707     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3708   }
3709 }
3710 
3711 
3712 // virtual method calling
3713 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3714                                            RegisterOrConstant vtable_index,
3715                                            Register method_result) {
3716   const int base = in_bytes(Klass::vtable_start_offset());
3717   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3718   Address vtable_entry_addr(recv_klass,
3719                             vtable_index, Address::times_ptr,
3720                             base + vtableEntry::method_offset_in_bytes());
3721   movptr(method_result, vtable_entry_addr);
3722 }
3723 
3724 
3725 void MacroAssembler::check_klass_subtype(Register sub_klass,
3726                            Register super_klass,
3727                            Register temp_reg,
3728                            Label& L_success) {
3729   Label L_failure;
3730   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
3731   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3732   bind(L_failure);
3733 }
3734 
3735 
3736 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3737                                                    Register super_klass,
3738                                                    Register temp_reg,
3739                                                    Label* L_success,
3740                                                    Label* L_failure,
3741                                                    Label* L_slow_path,
3742                                         RegisterOrConstant super_check_offset) {
3743   assert_different_registers(sub_klass, super_klass, temp_reg);
3744   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3745   if (super_check_offset.is_register()) {
3746     assert_different_registers(sub_klass, super_klass,
3747                                super_check_offset.as_register());
3748   } else if (must_load_sco) {
3749     assert(temp_reg != noreg, "supply either a temp or a register offset");
3750   }
3751 
3752   Label L_fallthrough;
3753   int label_nulls = 0;
3754   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3755   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3756   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3757   assert(label_nulls <= 1, "at most one NULL in the batch");
3758 
3759   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3760   int sco_offset = in_bytes(Klass::super_check_offset_offset());
3761   Address super_check_offset_addr(super_klass, sco_offset);
3762 
3763   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3764   // range of a jccb.  If this routine grows larger, reconsider at
3765   // least some of these.
3766 #define local_jcc(assembler_cond, label)                                \
3767   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
3768   else                             jcc( assembler_cond, label) /*omit semi*/
3769 
3770   // Hacked jmp, which may only be used just before L_fallthrough.
3771 #define final_jmp(label)                                                \
3772   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3773   else                            jmp(label)                /*omit semi*/
3774 
3775   // If the pointers are equal, we are done (e.g., String[] elements).
3776   // This self-check enables sharing of secondary supertype arrays among
3777   // non-primary types such as array-of-interface.  Otherwise, each such
3778   // type would need its own customized SSA.
3779   // We move this check to the front of the fast path because many
3780   // type checks are in fact trivially successful in this manner,
3781   // so we get a nicely predicted branch right at the start of the check.
3782   cmpptr(sub_klass, super_klass);
3783   local_jcc(Assembler::equal, *L_success);
3784 
3785   // Check the supertype display:
3786   if (must_load_sco) {
3787     // Positive movl does right thing on LP64.
3788     movl(temp_reg, super_check_offset_addr);
3789     super_check_offset = RegisterOrConstant(temp_reg);
3790   }
3791   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3792   cmpptr(super_klass, super_check_addr); // load displayed supertype
3793 
3794   // This check has worked decisively for primary supers.
3795   // Secondary supers are sought in the super_cache ('super_cache_addr').
3796   // (Secondary supers are interfaces and very deeply nested subtypes.)
3797   // This works in the same check above because of a tricky aliasing
3798   // between the super_cache and the primary super display elements.
3799   // (The 'super_check_addr' can address either, as the case requires.)
3800   // Note that the cache is updated below if it does not help us find
3801   // what we need immediately.
3802   // So if it was a primary super, we can just fail immediately.
3803   // Otherwise, it's the slow path for us (no success at this point).
3804 
3805   if (super_check_offset.is_register()) {
3806     local_jcc(Assembler::equal, *L_success);
3807     cmpl(super_check_offset.as_register(), sc_offset);
3808     if (L_failure == &L_fallthrough) {
3809       local_jcc(Assembler::equal, *L_slow_path);
3810     } else {
3811       local_jcc(Assembler::notEqual, *L_failure);
3812       final_jmp(*L_slow_path);
3813     }
3814   } else if (super_check_offset.as_constant() == sc_offset) {
3815     // Need a slow path; fast failure is impossible.
3816     if (L_slow_path == &L_fallthrough) {
3817       local_jcc(Assembler::equal, *L_success);
3818     } else {
3819       local_jcc(Assembler::notEqual, *L_slow_path);
3820       final_jmp(*L_success);
3821     }
3822   } else {
3823     // No slow path; it's a fast decision.
3824     if (L_failure == &L_fallthrough) {
3825       local_jcc(Assembler::equal, *L_success);
3826     } else {
3827       local_jcc(Assembler::notEqual, *L_failure);
3828       final_jmp(*L_success);
3829     }
3830   }
3831 
3832   bind(L_fallthrough);
3833 
3834 #undef local_jcc
3835 #undef final_jmp
3836 }
3837 
3838 
3839 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
3840                                                    Register super_klass,
3841                                                    Register temp_reg,
3842                                                    Register temp2_reg,
3843                                                    Label* L_success,
3844                                                    Label* L_failure,
3845                                                    bool set_cond_codes) {
3846   assert_different_registers(sub_klass, super_klass, temp_reg);
3847   if (temp2_reg != noreg)
3848     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
3849 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
3850 
3851   Label L_fallthrough;
3852   int label_nulls = 0;
3853   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3854   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3855   assert(label_nulls <= 1, "at most one NULL in the batch");
3856 
3857   // a couple of useful fields in sub_klass:
3858   int ss_offset = in_bytes(Klass::secondary_supers_offset());
3859   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3860   Address secondary_supers_addr(sub_klass, ss_offset);
3861   Address super_cache_addr(     sub_klass, sc_offset);
3862 
3863   // Do a linear scan of the secondary super-klass chain.
3864   // This code is rarely used, so simplicity is a virtue here.
3865   // The repne_scan instruction uses fixed registers, which we must spill.
3866   // Don't worry too much about pre-existing connections with the input regs.
3867 
3868   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
3869   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
3870 
3871   // Get super_klass value into rax (even if it was in rdi or rcx).
3872   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
3873   if (super_klass != rax || UseCompressedOops) {
3874     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
3875     mov(rax, super_klass);
3876   }
3877   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
3878   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
3879 
3880 #ifndef PRODUCT
3881   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
3882   ExternalAddress pst_counter_addr((address) pst_counter);
3883   NOT_LP64(  incrementl(pst_counter_addr) );
3884   LP64_ONLY( lea(rcx, pst_counter_addr) );
3885   LP64_ONLY( incrementl(Address(rcx, 0)) );
3886 #endif //PRODUCT
3887 
3888   // We will consult the secondary-super array.
3889   movptr(rdi, secondary_supers_addr);
3890   // Load the array length.  (Positive movl does right thing on LP64.)
3891   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
3892   // Skip to start of data.
3893   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
3894 
3895   // Scan RCX words at [RDI] for an occurrence of RAX.
3896   // Set NZ/Z based on last compare.
3897   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
3898   // not change flags (only scas instruction which is repeated sets flags).
3899   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
3900 
3901     testptr(rax,rax); // Set Z = 0
3902     repne_scan();
3903 
3904   // Unspill the temp. registers:
3905   if (pushed_rdi)  pop(rdi);
3906   if (pushed_rcx)  pop(rcx);
3907   if (pushed_rax)  pop(rax);
3908 
3909   if (set_cond_codes) {
3910     // Special hack for the AD files:  rdi is guaranteed non-zero.
3911     assert(!pushed_rdi, "rdi must be left non-NULL");
3912     // Also, the condition codes are properly set Z/NZ on succeed/failure.
3913   }
3914 
3915   if (L_failure == &L_fallthrough)
3916         jccb(Assembler::notEqual, *L_failure);
3917   else  jcc(Assembler::notEqual, *L_failure);
3918 
3919   // Success.  Cache the super we found and proceed in triumph.
3920   movptr(super_cache_addr, super_klass);
3921 
3922   if (L_success != &L_fallthrough) {
3923     jmp(*L_success);
3924   }
3925 
3926 #undef IS_A_TEMP
3927 
3928   bind(L_fallthrough);
3929 }
3930 
3931 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
3932   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
3933 
3934   Label L_fallthrough;
3935   if (L_fast_path == NULL) {
3936     L_fast_path = &L_fallthrough;
3937   } else if (L_slow_path == NULL) {
3938     L_slow_path = &L_fallthrough;
3939   }
3940 
3941   // Fast path check: class is fully initialized
3942   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
3943   jcc(Assembler::equal, *L_fast_path);
3944 
3945   // Fast path check: current thread is initializer thread
3946   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
3947   if (L_slow_path == &L_fallthrough) {
3948     jcc(Assembler::equal, *L_fast_path);
3949     bind(*L_slow_path);
3950   } else if (L_fast_path == &L_fallthrough) {
3951     jcc(Assembler::notEqual, *L_slow_path);
3952     bind(*L_fast_path);
3953   } else {
3954     Unimplemented();
3955   }
3956 }
3957 
3958 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
3959   if (VM_Version::supports_cmov()) {
3960     cmovl(cc, dst, src);
3961   } else {
3962     Label L;
3963     jccb(negate_condition(cc), L);
3964     movl(dst, src);
3965     bind(L);
3966   }
3967 }
3968 
3969 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
3970   if (VM_Version::supports_cmov()) {
3971     cmovl(cc, dst, src);
3972   } else {
3973     Label L;
3974     jccb(negate_condition(cc), L);
3975     movl(dst, src);
3976     bind(L);
3977   }
3978 }
3979 
3980 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
3981   if (!VerifyOops) return;
3982 
3983   // Pass register number to verify_oop_subroutine
3984   const char* b = NULL;
3985   {
3986     ResourceMark rm;
3987     stringStream ss;
3988     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
3989     b = code_string(ss.as_string());
3990   }
3991   BLOCK_COMMENT("verify_oop {");
3992 #ifdef _LP64
3993   push(rscratch1);                    // save r10, trashed by movptr()
3994 #endif
3995   push(rax);                          // save rax,
3996   push(reg);                          // pass register argument
3997   ExternalAddress buffer((address) b);
3998   // avoid using pushptr, as it modifies scratch registers
3999   // and our contract is not to modify anything
4000   movptr(rax, buffer.addr());
4001   push(rax);
4002   // call indirectly to solve generation ordering problem
4003   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4004   call(rax);
4005   // Caller pops the arguments (oop, message) and restores rax, r10
4006   BLOCK_COMMENT("} verify_oop");
4007 }
4008 
4009 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4010   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4011     vpternlogd(dst, 0xFF, dst, dst, vector_len);
4012   } else {
4013     assert(UseAVX > 0, "");
4014     vpcmpeqb(dst, dst, dst, vector_len);
4015   }
4016 }
4017 
4018 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4019                                          int extra_slot_offset) {
4020   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4021   int stackElementSize = Interpreter::stackElementSize;
4022   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4023 #ifdef ASSERT
4024   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4025   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4026 #endif
4027   Register             scale_reg    = noreg;
4028   Address::ScaleFactor scale_factor = Address::no_scale;
4029   if (arg_slot.is_constant()) {
4030     offset += arg_slot.as_constant() * stackElementSize;
4031   } else {
4032     scale_reg    = arg_slot.as_register();
4033     scale_factor = Address::times(stackElementSize);
4034   }
4035   offset += wordSize;           // return PC is on stack
4036   return Address(rsp, scale_reg, scale_factor, offset);
4037 }
4038 
4039 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4040   if (!VerifyOops) return;
4041 
4042   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4043   // Pass register number to verify_oop_subroutine
4044   const char* b = NULL;
4045   {
4046     ResourceMark rm;
4047     stringStream ss;
4048     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4049     b = code_string(ss.as_string());
4050   }
4051 #ifdef _LP64
4052   push(rscratch1);                    // save r10, trashed by movptr()
4053 #endif
4054   push(rax);                          // save rax,
4055   // addr may contain rsp so we will have to adjust it based on the push
4056   // we just did (and on 64 bit we do two pushes)
4057   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4058   // stores rax into addr which is backwards of what was intended.
4059   if (addr.uses(rsp)) {
4060     lea(rax, addr);
4061     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4062   } else {
4063     pushptr(addr);
4064   }
4065 
4066   ExternalAddress buffer((address) b);
4067   // pass msg argument
4068   // avoid using pushptr, as it modifies scratch registers
4069   // and our contract is not to modify anything
4070   movptr(rax, buffer.addr());
4071   push(rax);
4072 
4073   // call indirectly to solve generation ordering problem
4074   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4075   call(rax);
4076   // Caller pops the arguments (addr, message) and restores rax, r10.
4077 }
4078 
4079 void MacroAssembler::verify_tlab() {
4080 #ifdef ASSERT
4081   if (UseTLAB && VerifyOops) {
4082     Label next, ok;
4083     Register t1 = rsi;
4084     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4085 
4086     push(t1);
4087     NOT_LP64(push(thread_reg));
4088     NOT_LP64(get_thread(thread_reg));
4089 
4090     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4091     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4092     jcc(Assembler::aboveEqual, next);
4093     STOP("assert(top >= start)");
4094     should_not_reach_here();
4095 
4096     bind(next);
4097     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4098     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4099     jcc(Assembler::aboveEqual, ok);
4100     STOP("assert(top <= end)");
4101     should_not_reach_here();
4102 
4103     bind(ok);
4104     NOT_LP64(pop(thread_reg));
4105     pop(t1);
4106   }
4107 #endif
4108 }
4109 
4110 class ControlWord {
4111  public:
4112   int32_t _value;
4113 
4114   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4115   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4116   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4117   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4118   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4119   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4120   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4121   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4122 
4123   void print() const {
4124     // rounding control
4125     const char* rc;
4126     switch (rounding_control()) {
4127       case 0: rc = "round near"; break;
4128       case 1: rc = "round down"; break;
4129       case 2: rc = "round up  "; break;
4130       case 3: rc = "chop      "; break;
4131       default:
4132         rc = NULL; // silence compiler warnings
4133         fatal("Unknown rounding control: %d", rounding_control());
4134     };
4135     // precision control
4136     const char* pc;
4137     switch (precision_control()) {
4138       case 0: pc = "24 bits "; break;
4139       case 1: pc = "reserved"; break;
4140       case 2: pc = "53 bits "; break;
4141       case 3: pc = "64 bits "; break;
4142       default:
4143         pc = NULL; // silence compiler warnings
4144         fatal("Unknown precision control: %d", precision_control());
4145     };
4146     // flags
4147     char f[9];
4148     f[0] = ' ';
4149     f[1] = ' ';
4150     f[2] = (precision   ()) ? 'P' : 'p';
4151     f[3] = (underflow   ()) ? 'U' : 'u';
4152     f[4] = (overflow    ()) ? 'O' : 'o';
4153     f[5] = (zero_divide ()) ? 'Z' : 'z';
4154     f[6] = (denormalized()) ? 'D' : 'd';
4155     f[7] = (invalid     ()) ? 'I' : 'i';
4156     f[8] = '\x0';
4157     // output
4158     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4159   }
4160 
4161 };
4162 
4163 class StatusWord {
4164  public:
4165   int32_t _value;
4166 
4167   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4168   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4169   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4170   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4171   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4172   int  top() const                     { return  (_value >> 11) & 7      ; }
4173   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4174   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4175   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4176   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4177   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4178   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4179   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4180   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4181 
4182   void print() const {
4183     // condition codes
4184     char c[5];
4185     c[0] = (C3()) ? '3' : '-';
4186     c[1] = (C2()) ? '2' : '-';
4187     c[2] = (C1()) ? '1' : '-';
4188     c[3] = (C0()) ? '0' : '-';
4189     c[4] = '\x0';
4190     // flags
4191     char f[9];
4192     f[0] = (error_status()) ? 'E' : '-';
4193     f[1] = (stack_fault ()) ? 'S' : '-';
4194     f[2] = (precision   ()) ? 'P' : '-';
4195     f[3] = (underflow   ()) ? 'U' : '-';
4196     f[4] = (overflow    ()) ? 'O' : '-';
4197     f[5] = (zero_divide ()) ? 'Z' : '-';
4198     f[6] = (denormalized()) ? 'D' : '-';
4199     f[7] = (invalid     ()) ? 'I' : '-';
4200     f[8] = '\x0';
4201     // output
4202     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4203   }
4204 
4205 };
4206 
4207 class TagWord {
4208  public:
4209   int32_t _value;
4210 
4211   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4212 
4213   void print() const {
4214     printf("%04x", _value & 0xFFFF);
4215   }
4216 
4217 };
4218 
4219 class FPU_Register {
4220  public:
4221   int32_t _m0;
4222   int32_t _m1;
4223   int16_t _ex;
4224 
4225   bool is_indefinite() const           {
4226     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4227   }
4228 
4229   void print() const {
4230     char  sign = (_ex < 0) ? '-' : '+';
4231     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4232     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4233   };
4234 
4235 };
4236 
4237 class FPU_State {
4238  public:
4239   enum {
4240     register_size       = 10,
4241     number_of_registers =  8,
4242     register_mask       =  7
4243   };
4244 
4245   ControlWord  _control_word;
4246   StatusWord   _status_word;
4247   TagWord      _tag_word;
4248   int32_t      _error_offset;
4249   int32_t      _error_selector;
4250   int32_t      _data_offset;
4251   int32_t      _data_selector;
4252   int8_t       _register[register_size * number_of_registers];
4253 
4254   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4255   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4256 
4257   const char* tag_as_string(int tag) const {
4258     switch (tag) {
4259       case 0: return "valid";
4260       case 1: return "zero";
4261       case 2: return "special";
4262       case 3: return "empty";
4263     }
4264     ShouldNotReachHere();
4265     return NULL;
4266   }
4267 
4268   void print() const {
4269     // print computation registers
4270     { int t = _status_word.top();
4271       for (int i = 0; i < number_of_registers; i++) {
4272         int j = (i - t) & register_mask;
4273         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4274         st(j)->print();
4275         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4276       }
4277     }
4278     printf("\n");
4279     // print control registers
4280     printf("ctrl = "); _control_word.print(); printf("\n");
4281     printf("stat = "); _status_word .print(); printf("\n");
4282     printf("tags = "); _tag_word    .print(); printf("\n");
4283   }
4284 
4285 };
4286 
4287 class Flag_Register {
4288  public:
4289   int32_t _value;
4290 
4291   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4292   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4293   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4294   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4295   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4296   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4297   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4298 
4299   void print() const {
4300     // flags
4301     char f[8];
4302     f[0] = (overflow       ()) ? 'O' : '-';
4303     f[1] = (direction      ()) ? 'D' : '-';
4304     f[2] = (sign           ()) ? 'S' : '-';
4305     f[3] = (zero           ()) ? 'Z' : '-';
4306     f[4] = (auxiliary_carry()) ? 'A' : '-';
4307     f[5] = (parity         ()) ? 'P' : '-';
4308     f[6] = (carry          ()) ? 'C' : '-';
4309     f[7] = '\x0';
4310     // output
4311     printf("%08x  flags = %s", _value, f);
4312   }
4313 
4314 };
4315 
4316 class IU_Register {
4317  public:
4318   int32_t _value;
4319 
4320   void print() const {
4321     printf("%08x  %11d", _value, _value);
4322   }
4323 
4324 };
4325 
4326 class IU_State {
4327  public:
4328   Flag_Register _eflags;
4329   IU_Register   _rdi;
4330   IU_Register   _rsi;
4331   IU_Register   _rbp;
4332   IU_Register   _rsp;
4333   IU_Register   _rbx;
4334   IU_Register   _rdx;
4335   IU_Register   _rcx;
4336   IU_Register   _rax;
4337 
4338   void print() const {
4339     // computation registers
4340     printf("rax,  = "); _rax.print(); printf("\n");
4341     printf("rbx,  = "); _rbx.print(); printf("\n");
4342     printf("rcx  = "); _rcx.print(); printf("\n");
4343     printf("rdx  = "); _rdx.print(); printf("\n");
4344     printf("rdi  = "); _rdi.print(); printf("\n");
4345     printf("rsi  = "); _rsi.print(); printf("\n");
4346     printf("rbp,  = "); _rbp.print(); printf("\n");
4347     printf("rsp  = "); _rsp.print(); printf("\n");
4348     printf("\n");
4349     // control registers
4350     printf("flgs = "); _eflags.print(); printf("\n");
4351   }
4352 };
4353 
4354 
4355 class CPU_State {
4356  public:
4357   FPU_State _fpu_state;
4358   IU_State  _iu_state;
4359 
4360   void print() const {
4361     printf("--------------------------------------------------\n");
4362     _iu_state .print();
4363     printf("\n");
4364     _fpu_state.print();
4365     printf("--------------------------------------------------\n");
4366   }
4367 
4368 };
4369 
4370 
4371 static void _print_CPU_state(CPU_State* state) {
4372   state->print();
4373 };
4374 
4375 
4376 void MacroAssembler::print_CPU_state() {
4377   push_CPU_state();
4378   push(rsp);                // pass CPU state
4379   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4380   addptr(rsp, wordSize);       // discard argument
4381   pop_CPU_state();
4382 }
4383 
4384 
4385 #ifndef _LP64
4386 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4387   static int counter = 0;
4388   FPU_State* fs = &state->_fpu_state;
4389   counter++;
4390   // For leaf calls, only verify that the top few elements remain empty.
4391   // We only need 1 empty at the top for C2 code.
4392   if( stack_depth < 0 ) {
4393     if( fs->tag_for_st(7) != 3 ) {
4394       printf("FPR7 not empty\n");
4395       state->print();
4396       assert(false, "error");
4397       return false;
4398     }
4399     return true;                // All other stack states do not matter
4400   }
4401 
4402   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4403          "bad FPU control word");
4404 
4405   // compute stack depth
4406   int i = 0;
4407   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4408   int d = i;
4409   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4410   // verify findings
4411   if (i != FPU_State::number_of_registers) {
4412     // stack not contiguous
4413     printf("%s: stack not contiguous at ST%d\n", s, i);
4414     state->print();
4415     assert(false, "error");
4416     return false;
4417   }
4418   // check if computed stack depth corresponds to expected stack depth
4419   if (stack_depth < 0) {
4420     // expected stack depth is -stack_depth or less
4421     if (d > -stack_depth) {
4422       // too many elements on the stack
4423       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4424       state->print();
4425       assert(false, "error");
4426       return false;
4427     }
4428   } else {
4429     // expected stack depth is stack_depth
4430     if (d != stack_depth) {
4431       // wrong stack depth
4432       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4433       state->print();
4434       assert(false, "error");
4435       return false;
4436     }
4437   }
4438   // everything is cool
4439   return true;
4440 }
4441 
4442 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4443   if (!VerifyFPU) return;
4444   push_CPU_state();
4445   push(rsp);                // pass CPU state
4446   ExternalAddress msg((address) s);
4447   // pass message string s
4448   pushptr(msg.addr());
4449   push(stack_depth);        // pass stack depth
4450   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4451   addptr(rsp, 3 * wordSize);   // discard arguments
4452   // check for error
4453   { Label L;
4454     testl(rax, rax);
4455     jcc(Assembler::notZero, L);
4456     int3();                  // break if error condition
4457     bind(L);
4458   }
4459   pop_CPU_state();
4460 }
4461 #endif // _LP64
4462 
4463 void MacroAssembler::restore_cpu_control_state_after_jni() {
4464   // Either restore the MXCSR register after returning from the JNI Call
4465   // or verify that it wasn't changed (with -Xcheck:jni flag).
4466   if (VM_Version::supports_sse()) {
4467     if (RestoreMXCSROnJNICalls) {
4468       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4469     } else if (CheckJNICalls) {
4470       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4471     }
4472   }
4473   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4474   vzeroupper();
4475   // Reset k1 to 0xffff.
4476 
4477 #ifdef COMPILER2
4478   if (PostLoopMultiversioning && VM_Version::supports_evex()) {
4479     push(rcx);
4480     movl(rcx, 0xffff);
4481     kmovwl(k1, rcx);
4482     pop(rcx);
4483   }
4484 #endif // COMPILER2
4485 
4486 #ifndef _LP64
4487   // Either restore the x87 floating pointer control word after returning
4488   // from the JNI call or verify that it wasn't changed.
4489   if (CheckJNICalls) {
4490     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4491   }
4492 #endif // _LP64
4493 }
4494 
4495 // ((OopHandle)result).resolve();
4496 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4497   assert_different_registers(result, tmp);
4498 
4499   // Only 64 bit platforms support GCs that require a tmp register
4500   // Only IN_HEAP loads require a thread_tmp register
4501   // OopHandle::resolve is an indirection like jobject.
4502   access_load_at(T_OBJECT, IN_NATIVE,
4503                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4504 }
4505 
4506 // ((WeakHandle)result).resolve();
4507 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4508   assert_different_registers(rresult, rtmp);
4509   Label resolved;
4510 
4511   // A null weak handle resolves to null.
4512   cmpptr(rresult, 0);
4513   jcc(Assembler::equal, resolved);
4514 
4515   // Only 64 bit platforms support GCs that require a tmp register
4516   // Only IN_HEAP loads require a thread_tmp register
4517   // WeakHandle::resolve is an indirection like jweak.
4518   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4519                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4520   bind(resolved);
4521 }
4522 
4523 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4524   // get mirror
4525   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4526   load_method_holder(mirror, method);
4527   movptr(mirror, Address(mirror, mirror_offset));
4528   resolve_oop_handle(mirror, tmp);
4529 }
4530 
4531 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4532   load_method_holder(rresult, rmethod);
4533   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4534 }
4535 
4536 void MacroAssembler::load_method_holder(Register holder, Register method) {
4537   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
4538   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
4539   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4540 }
4541 
4542 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4543   assert_different_registers(src, tmp);
4544   assert_different_registers(dst, tmp);
4545 #ifdef _LP64
4546   if (UseCompressedClassPointers) {
4547     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4548     decode_klass_not_null(dst, tmp);
4549   } else
4550 #endif
4551     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4552 }
4553 
4554 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4555   assert_different_registers(src, tmp);
4556   assert_different_registers(dst, tmp);
4557 #ifdef _LP64
4558   if (UseCompressedClassPointers) {
4559     encode_klass_not_null(src, tmp);
4560     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4561   } else
4562 #endif
4563     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4564 }
4565 
4566 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4567                                     Register tmp1, Register thread_tmp) {
4568   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4569   decorators = AccessInternal::decorator_fixup(decorators);
4570   bool as_raw = (decorators & AS_RAW) != 0;
4571   if (as_raw) {
4572     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4573   } else {
4574     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4575   }
4576 }
4577 
4578 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4579                                      Register tmp1, Register tmp2) {
4580   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4581   decorators = AccessInternal::decorator_fixup(decorators);
4582   bool as_raw = (decorators & AS_RAW) != 0;
4583   if (as_raw) {
4584     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2);
4585   } else {
4586     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2);
4587   }
4588 }
4589 
4590 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4591                                    Register thread_tmp, DecoratorSet decorators) {
4592   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4593 }
4594 
4595 // Doesn't do verfication, generates fixed size code
4596 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4597                                             Register thread_tmp, DecoratorSet decorators) {
4598   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4599 }
4600 
4601 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4602                                     Register tmp2, DecoratorSet decorators) {
4603   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2);
4604 }
4605 
4606 // Used for storing NULLs.
4607 void MacroAssembler::store_heap_oop_null(Address dst) {
4608   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg);
4609 }
4610 
4611 #ifdef _LP64
4612 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4613   if (UseCompressedClassPointers) {
4614     // Store to klass gap in destination
4615     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4616   }
4617 }
4618 
4619 #ifdef ASSERT
4620 void MacroAssembler::verify_heapbase(const char* msg) {
4621   assert (UseCompressedOops, "should be compressed");
4622   assert (Universe::heap() != NULL, "java heap should be initialized");
4623   if (CheckCompressedOops) {
4624     Label ok;
4625     push(rscratch1); // cmpptr trashes rscratch1
4626     cmpptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
4627     jcc(Assembler::equal, ok);
4628     STOP(msg);
4629     bind(ok);
4630     pop(rscratch1);
4631   }
4632 }
4633 #endif
4634 
4635 // Algorithm must match oop.inline.hpp encode_heap_oop.
4636 void MacroAssembler::encode_heap_oop(Register r) {
4637 #ifdef ASSERT
4638   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4639 #endif
4640   verify_oop_msg(r, "broken oop in encode_heap_oop");
4641   if (CompressedOops::base() == NULL) {
4642     if (CompressedOops::shift() != 0) {
4643       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4644       shrq(r, LogMinObjAlignmentInBytes);
4645     }
4646     return;
4647   }
4648   testq(r, r);
4649   cmovq(Assembler::equal, r, r12_heapbase);
4650   subq(r, r12_heapbase);
4651   shrq(r, LogMinObjAlignmentInBytes);
4652 }
4653 
4654 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4655 #ifdef ASSERT
4656   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4657   if (CheckCompressedOops) {
4658     Label ok;
4659     testq(r, r);
4660     jcc(Assembler::notEqual, ok);
4661     STOP("null oop passed to encode_heap_oop_not_null");
4662     bind(ok);
4663   }
4664 #endif
4665   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4666   if (CompressedOops::base() != NULL) {
4667     subq(r, r12_heapbase);
4668   }
4669   if (CompressedOops::shift() != 0) {
4670     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4671     shrq(r, LogMinObjAlignmentInBytes);
4672   }
4673 }
4674 
4675 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4676 #ifdef ASSERT
4677   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4678   if (CheckCompressedOops) {
4679     Label ok;
4680     testq(src, src);
4681     jcc(Assembler::notEqual, ok);
4682     STOP("null oop passed to encode_heap_oop_not_null2");
4683     bind(ok);
4684   }
4685 #endif
4686   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4687   if (dst != src) {
4688     movq(dst, src);
4689   }
4690   if (CompressedOops::base() != NULL) {
4691     subq(dst, r12_heapbase);
4692   }
4693   if (CompressedOops::shift() != 0) {
4694     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4695     shrq(dst, LogMinObjAlignmentInBytes);
4696   }
4697 }
4698 
4699 void  MacroAssembler::decode_heap_oop(Register r) {
4700 #ifdef ASSERT
4701   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4702 #endif
4703   if (CompressedOops::base() == NULL) {
4704     if (CompressedOops::shift() != 0) {
4705       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4706       shlq(r, LogMinObjAlignmentInBytes);
4707     }
4708   } else {
4709     Label done;
4710     shlq(r, LogMinObjAlignmentInBytes);
4711     jccb(Assembler::equal, done);
4712     addq(r, r12_heapbase);
4713     bind(done);
4714   }
4715   verify_oop_msg(r, "broken oop in decode_heap_oop");
4716 }
4717 
4718 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
4719   // Note: it will change flags
4720   assert (UseCompressedOops, "should only be used for compressed headers");
4721   assert (Universe::heap() != NULL, "java heap should be initialized");
4722   // Cannot assert, unverified entry point counts instructions (see .ad file)
4723   // vtableStubs also counts instructions in pd_code_size_limit.
4724   // Also do not verify_oop as this is called by verify_oop.
4725   if (CompressedOops::shift() != 0) {
4726     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4727     shlq(r, LogMinObjAlignmentInBytes);
4728     if (CompressedOops::base() != NULL) {
4729       addq(r, r12_heapbase);
4730     }
4731   } else {
4732     assert (CompressedOops::base() == NULL, "sanity");
4733   }
4734 }
4735 
4736 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4737   // Note: it will change flags
4738   assert (UseCompressedOops, "should only be used for compressed headers");
4739   assert (Universe::heap() != NULL, "java heap should be initialized");
4740   // Cannot assert, unverified entry point counts instructions (see .ad file)
4741   // vtableStubs also counts instructions in pd_code_size_limit.
4742   // Also do not verify_oop as this is called by verify_oop.
4743   if (CompressedOops::shift() != 0) {
4744     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4745     if (LogMinObjAlignmentInBytes == Address::times_8) {
4746       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
4747     } else {
4748       if (dst != src) {
4749         movq(dst, src);
4750       }
4751       shlq(dst, LogMinObjAlignmentInBytes);
4752       if (CompressedOops::base() != NULL) {
4753         addq(dst, r12_heapbase);
4754       }
4755     }
4756   } else {
4757     assert (CompressedOops::base() == NULL, "sanity");
4758     if (dst != src) {
4759       movq(dst, src);
4760     }
4761   }
4762 }
4763 
4764 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
4765   assert_different_registers(r, tmp);
4766   if (CompressedKlassPointers::base() != NULL) {
4767     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4768     subq(r, tmp);
4769   }
4770   if (CompressedKlassPointers::shift() != 0) {
4771     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4772     shrq(r, LogKlassAlignmentInBytes);
4773   }
4774 }
4775 
4776 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
4777   assert_different_registers(src, dst);
4778   if (CompressedKlassPointers::base() != NULL) {
4779     mov64(dst, -(int64_t)CompressedKlassPointers::base());
4780     addq(dst, src);
4781   } else {
4782     movptr(dst, src);
4783   }
4784   if (CompressedKlassPointers::shift() != 0) {
4785     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4786     shrq(dst, LogKlassAlignmentInBytes);
4787   }
4788 }
4789 
4790 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
4791   assert_different_registers(r, tmp);
4792   // Note: it will change flags
4793   assert(UseCompressedClassPointers, "should only be used for compressed headers");
4794   // Cannot assert, unverified entry point counts instructions (see .ad file)
4795   // vtableStubs also counts instructions in pd_code_size_limit.
4796   // Also do not verify_oop as this is called by verify_oop.
4797   if (CompressedKlassPointers::shift() != 0) {
4798     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4799     shlq(r, LogKlassAlignmentInBytes);
4800   }
4801   if (CompressedKlassPointers::base() != NULL) {
4802     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4803     addq(r, tmp);
4804   }
4805 }
4806 
4807 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
4808   assert_different_registers(src, dst);
4809   // Note: it will change flags
4810   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4811   // Cannot assert, unverified entry point counts instructions (see .ad file)
4812   // vtableStubs also counts instructions in pd_code_size_limit.
4813   // Also do not verify_oop as this is called by verify_oop.
4814 
4815   if (CompressedKlassPointers::base() == NULL &&
4816       CompressedKlassPointers::shift() == 0) {
4817     // The best case scenario is that there is no base or shift. Then it is already
4818     // a pointer that needs nothing but a register rename.
4819     movl(dst, src);
4820   } else {
4821     if (CompressedKlassPointers::base() != NULL) {
4822       mov64(dst, (int64_t)CompressedKlassPointers::base());
4823     } else {
4824       xorq(dst, dst);
4825     }
4826     if (CompressedKlassPointers::shift() != 0) {
4827       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4828       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
4829       leaq(dst, Address(dst, src, Address::times_8, 0));
4830     } else {
4831       addq(dst, src);
4832     }
4833   }
4834 }
4835 
4836 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
4837   assert (UseCompressedOops, "should only be used for compressed headers");
4838   assert (Universe::heap() != NULL, "java heap should be initialized");
4839   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4840   int oop_index = oop_recorder()->find_index(obj);
4841   RelocationHolder rspec = oop_Relocation::spec(oop_index);
4842   mov_narrow_oop(dst, oop_index, rspec);
4843 }
4844 
4845 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
4846   assert (UseCompressedOops, "should only be used for compressed headers");
4847   assert (Universe::heap() != NULL, "java heap should be initialized");
4848   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4849   int oop_index = oop_recorder()->find_index(obj);
4850   RelocationHolder rspec = oop_Relocation::spec(oop_index);
4851   mov_narrow_oop(dst, oop_index, rspec);
4852 }
4853 
4854 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
4855   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4856   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4857   int klass_index = oop_recorder()->find_index(k);
4858   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4859   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4860 }
4861 
4862 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
4863   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4864   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4865   int klass_index = oop_recorder()->find_index(k);
4866   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4867   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4868 }
4869 
4870 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
4871   assert (UseCompressedOops, "should only be used for compressed headers");
4872   assert (Universe::heap() != NULL, "java heap should be initialized");
4873   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4874   int oop_index = oop_recorder()->find_index(obj);
4875   RelocationHolder rspec = oop_Relocation::spec(oop_index);
4876   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
4877 }
4878 
4879 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
4880   assert (UseCompressedOops, "should only be used for compressed headers");
4881   assert (Universe::heap() != NULL, "java heap should be initialized");
4882   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4883   int oop_index = oop_recorder()->find_index(obj);
4884   RelocationHolder rspec = oop_Relocation::spec(oop_index);
4885   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
4886 }
4887 
4888 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
4889   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4890   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4891   int klass_index = oop_recorder()->find_index(k);
4892   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4893   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4894 }
4895 
4896 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
4897   assert (UseCompressedClassPointers, "should only be used for compressed headers");
4898   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
4899   int klass_index = oop_recorder()->find_index(k);
4900   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
4901   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
4902 }
4903 
4904 void MacroAssembler::reinit_heapbase() {
4905   if (UseCompressedOops) {
4906     if (Universe::heap() != NULL) {
4907       if (CompressedOops::base() == NULL) {
4908         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
4909       } else {
4910         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
4911       }
4912     } else {
4913       movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
4914     }
4915   }
4916 }
4917 
4918 #endif // _LP64
4919 
4920 // C2 compiled method's prolog code.
4921 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
4922 
4923   // WARNING: Initial instruction MUST be 5 bytes or longer so that
4924   // NativeJump::patch_verified_entry will be able to patch out the entry
4925   // code safely. The push to verify stack depth is ok at 5 bytes,
4926   // the frame allocation can be either 3 or 6 bytes. So if we don't do
4927   // stack bang then we must use the 6 byte frame allocation even if
4928   // we have no frame. :-(
4929   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
4930 
4931   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
4932   // Remove word for return addr
4933   framesize -= wordSize;
4934   stack_bang_size -= wordSize;
4935 
4936   // Calls to C2R adapters often do not accept exceptional returns.
4937   // We require that their callers must bang for them.  But be careful, because
4938   // some VM calls (such as call site linkage) can use several kilobytes of
4939   // stack.  But the stack safety zone should account for that.
4940   // See bugs 4446381, 4468289, 4497237.
4941   if (stack_bang_size > 0) {
4942     generate_stack_overflow_check(stack_bang_size);
4943 
4944     // We always push rbp, so that on return to interpreter rbp, will be
4945     // restored correctly and we can correct the stack.
4946     push(rbp);
4947     // Save caller's stack pointer into RBP if the frame pointer is preserved.
4948     if (PreserveFramePointer) {
4949       mov(rbp, rsp);
4950     }
4951     // Remove word for ebp
4952     framesize -= wordSize;
4953 
4954     // Create frame
4955     if (framesize) {
4956       subptr(rsp, framesize);
4957     }
4958   } else {
4959     // Create frame (force generation of a 4 byte immediate value)
4960     subptr_imm32(rsp, framesize);
4961 
4962     // Save RBP register now.
4963     framesize -= wordSize;
4964     movptr(Address(rsp, framesize), rbp);
4965     // Save caller's stack pointer into RBP if the frame pointer is preserved.
4966     if (PreserveFramePointer) {
4967       movptr(rbp, rsp);
4968       if (framesize > 0) {
4969         addptr(rbp, framesize);
4970       }
4971     }
4972   }
4973 
4974   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
4975     framesize -= wordSize;
4976     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
4977   }
4978 
4979 #ifndef _LP64
4980   // If method sets FPU control word do it now
4981   if (fp_mode_24b) {
4982     fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
4983   }
4984   if (UseSSE >= 2 && VerifyFPU) {
4985     verify_FPU(0, "FPU stack must be clean on entry");
4986   }
4987 #endif
4988 
4989 #ifdef ASSERT
4990   if (VerifyStackAtCalls) {
4991     Label L;
4992     push(rax);
4993     mov(rax, rsp);
4994     andptr(rax, StackAlignmentInBytes-1);
4995     cmpptr(rax, StackAlignmentInBytes-wordSize);
4996     pop(rax);
4997     jcc(Assembler::equal, L);
4998     STOP("Stack is not properly aligned!");
4999     bind(L);
5000   }
5001 #endif
5002 
5003   if (!is_stub) {
5004     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5005     bs->nmethod_entry_barrier(this);
5006   }
5007 }
5008 
5009 #if COMPILER2_OR_JVMCI
5010 
5011 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5012 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5013   // cnt - number of qwords (8-byte words).
5014   // base - start address, qword aligned.
5015   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5016   bool use64byteVector = MaxVectorSize == 64 && AVX3Threshold == 0;
5017   if (use64byteVector) {
5018     vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5019   } else if (MaxVectorSize >= 32) {
5020     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5021   } else {
5022     pxor(xtmp, xtmp);
5023   }
5024   jmp(L_zero_64_bytes);
5025 
5026   BIND(L_loop);
5027   if (MaxVectorSize >= 32) {
5028     fill64(base, 0, xtmp, use64byteVector);
5029   } else {
5030     movdqu(Address(base,  0), xtmp);
5031     movdqu(Address(base, 16), xtmp);
5032     movdqu(Address(base, 32), xtmp);
5033     movdqu(Address(base, 48), xtmp);
5034   }
5035   addptr(base, 64);
5036 
5037   BIND(L_zero_64_bytes);
5038   subptr(cnt, 8);
5039   jccb(Assembler::greaterEqual, L_loop);
5040 
5041   // Copy trailing 64 bytes
5042   if (use64byteVector) {
5043     addptr(cnt, 8);
5044     jccb(Assembler::equal, L_end);
5045     fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5046     jmp(L_end);
5047   } else {
5048     addptr(cnt, 4);
5049     jccb(Assembler::less, L_tail);
5050     if (MaxVectorSize >= 32) {
5051       vmovdqu(Address(base, 0), xtmp);
5052     } else {
5053       movdqu(Address(base,  0), xtmp);
5054       movdqu(Address(base, 16), xtmp);
5055     }
5056   }
5057   addptr(base, 32);
5058   subptr(cnt, 4);
5059 
5060   BIND(L_tail);
5061   addptr(cnt, 4);
5062   jccb(Assembler::lessEqual, L_end);
5063   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5064     fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5065   } else {
5066     decrement(cnt);
5067 
5068     BIND(L_sloop);
5069     movq(Address(base, 0), xtmp);
5070     addptr(base, 8);
5071     decrement(cnt);
5072     jccb(Assembler::greaterEqual, L_sloop);
5073   }
5074   BIND(L_end);
5075 }
5076 
5077 // Clearing constant sized memory using YMM/ZMM registers.
5078 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5079   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5080   bool use64byteVector = MaxVectorSize > 32 && AVX3Threshold == 0;
5081 
5082   int vector64_count = (cnt & (~0x7)) >> 3;
5083   cnt = cnt & 0x7;
5084 
5085   // 64 byte initialization loop.
5086   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5087   for (int i = 0; i < vector64_count; i++) {
5088     fill64(base, i * 64, xtmp, use64byteVector);
5089   }
5090 
5091   // Clear remaining 64 byte tail.
5092   int disp = vector64_count * 64;
5093   if (cnt) {
5094     switch (cnt) {
5095       case 1:
5096         movq(Address(base, disp), xtmp);
5097         break;
5098       case 2:
5099         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5100         break;
5101       case 3:
5102         movl(rtmp, 0x7);
5103         kmovwl(mask, rtmp);
5104         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5105         break;
5106       case 4:
5107         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5108         break;
5109       case 5:
5110         if (use64byteVector) {
5111           movl(rtmp, 0x1F);
5112           kmovwl(mask, rtmp);
5113           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5114         } else {
5115           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5116           movq(Address(base, disp + 32), xtmp);
5117         }
5118         break;
5119       case 6:
5120         if (use64byteVector) {
5121           movl(rtmp, 0x3F);
5122           kmovwl(mask, rtmp);
5123           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5124         } else {
5125           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5126           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5127         }
5128         break;
5129       case 7:
5130         if (use64byteVector) {
5131           movl(rtmp, 0x7F);
5132           kmovwl(mask, rtmp);
5133           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5134         } else {
5135           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5136           movl(rtmp, 0x7);
5137           kmovwl(mask, rtmp);
5138           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5139         }
5140         break;
5141       default:
5142         fatal("Unexpected length : %d\n",cnt);
5143         break;
5144     }
5145   }
5146 }
5147 
5148 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5149                                bool is_large, KRegister mask) {
5150   // cnt      - number of qwords (8-byte words).
5151   // base     - start address, qword aligned.
5152   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5153   assert(base==rdi, "base register must be edi for rep stos");
5154   assert(tmp==rax,   "tmp register must be eax for rep stos");
5155   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5156   assert(InitArrayShortSize % BytesPerLong == 0,
5157     "InitArrayShortSize should be the multiple of BytesPerLong");
5158 
5159   Label DONE;
5160   if (!is_large || !UseXMMForObjInit) {
5161     xorptr(tmp, tmp);
5162   }
5163 
5164   if (!is_large) {
5165     Label LOOP, LONG;
5166     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5167     jccb(Assembler::greater, LONG);
5168 
5169     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5170 
5171     decrement(cnt);
5172     jccb(Assembler::negative, DONE); // Zero length
5173 
5174     // Use individual pointer-sized stores for small counts:
5175     BIND(LOOP);
5176     movptr(Address(base, cnt, Address::times_ptr), tmp);
5177     decrement(cnt);
5178     jccb(Assembler::greaterEqual, LOOP);
5179     jmpb(DONE);
5180 
5181     BIND(LONG);
5182   }
5183 
5184   // Use longer rep-prefixed ops for non-small counts:
5185   if (UseFastStosb) {
5186     shlptr(cnt, 3); // convert to number of bytes
5187     rep_stosb();
5188   } else if (UseXMMForObjInit) {
5189     xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5190   } else {
5191     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5192     rep_stos();
5193   }
5194 
5195   BIND(DONE);
5196 }
5197 
5198 #endif //COMPILER2_OR_JVMCI
5199 
5200 
5201 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5202                                    Register to, Register value, Register count,
5203                                    Register rtmp, XMMRegister xtmp) {
5204   ShortBranchVerifier sbv(this);
5205   assert_different_registers(to, value, count, rtmp);
5206   Label L_exit;
5207   Label L_fill_2_bytes, L_fill_4_bytes;
5208 
5209 #if defined(COMPILER2) && defined(_LP64)
5210   if(MaxVectorSize >=32 &&
5211      VM_Version::supports_avx512vlbw() &&
5212      VM_Version::supports_bmi2()) {
5213     generate_fill_avx3(t, to, value, count, rtmp, xtmp);
5214     return;
5215   }
5216 #endif
5217 
5218   int shift = -1;
5219   switch (t) {
5220     case T_BYTE:
5221       shift = 2;
5222       break;
5223     case T_SHORT:
5224       shift = 1;
5225       break;
5226     case T_INT:
5227       shift = 0;
5228       break;
5229     default: ShouldNotReachHere();
5230   }
5231 
5232   if (t == T_BYTE) {
5233     andl(value, 0xff);
5234     movl(rtmp, value);
5235     shll(rtmp, 8);
5236     orl(value, rtmp);
5237   }
5238   if (t == T_SHORT) {
5239     andl(value, 0xffff);
5240   }
5241   if (t == T_BYTE || t == T_SHORT) {
5242     movl(rtmp, value);
5243     shll(rtmp, 16);
5244     orl(value, rtmp);
5245   }
5246 
5247   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5248   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5249   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5250     Label L_skip_align2;
5251     // align source address at 4 bytes address boundary
5252     if (t == T_BYTE) {
5253       Label L_skip_align1;
5254       // One byte misalignment happens only for byte arrays
5255       testptr(to, 1);
5256       jccb(Assembler::zero, L_skip_align1);
5257       movb(Address(to, 0), value);
5258       increment(to);
5259       decrement(count);
5260       BIND(L_skip_align1);
5261     }
5262     // Two bytes misalignment happens only for byte and short (char) arrays
5263     testptr(to, 2);
5264     jccb(Assembler::zero, L_skip_align2);
5265     movw(Address(to, 0), value);
5266     addptr(to, 2);
5267     subl(count, 1<<(shift-1));
5268     BIND(L_skip_align2);
5269   }
5270   if (UseSSE < 2) {
5271     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5272     // Fill 32-byte chunks
5273     subl(count, 8 << shift);
5274     jcc(Assembler::less, L_check_fill_8_bytes);
5275     align(16);
5276 
5277     BIND(L_fill_32_bytes_loop);
5278 
5279     for (int i = 0; i < 32; i += 4) {
5280       movl(Address(to, i), value);
5281     }
5282 
5283     addptr(to, 32);
5284     subl(count, 8 << shift);
5285     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5286     BIND(L_check_fill_8_bytes);
5287     addl(count, 8 << shift);
5288     jccb(Assembler::zero, L_exit);
5289     jmpb(L_fill_8_bytes);
5290 
5291     //
5292     // length is too short, just fill qwords
5293     //
5294     BIND(L_fill_8_bytes_loop);
5295     movl(Address(to, 0), value);
5296     movl(Address(to, 4), value);
5297     addptr(to, 8);
5298     BIND(L_fill_8_bytes);
5299     subl(count, 1 << (shift + 1));
5300     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5301     // fall through to fill 4 bytes
5302   } else {
5303     Label L_fill_32_bytes;
5304     if (!UseUnalignedLoadStores) {
5305       // align to 8 bytes, we know we are 4 byte aligned to start
5306       testptr(to, 4);
5307       jccb(Assembler::zero, L_fill_32_bytes);
5308       movl(Address(to, 0), value);
5309       addptr(to, 4);
5310       subl(count, 1<<shift);
5311     }
5312     BIND(L_fill_32_bytes);
5313     {
5314       assert( UseSSE >= 2, "supported cpu only" );
5315       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5316       movdl(xtmp, value);
5317       if (UseAVX >= 2 && UseUnalignedLoadStores) {
5318         Label L_check_fill_32_bytes;
5319         if (UseAVX > 2) {
5320           // Fill 64-byte chunks
5321           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
5322 
5323           // If number of bytes to fill < AVX3Threshold, perform fill using AVX2
5324           cmpl(count, AVX3Threshold);
5325           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
5326 
5327           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
5328 
5329           subl(count, 16 << shift);
5330           jccb(Assembler::less, L_check_fill_32_bytes);
5331           align(16);
5332 
5333           BIND(L_fill_64_bytes_loop_avx3);
5334           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
5335           addptr(to, 64);
5336           subl(count, 16 << shift);
5337           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
5338           jmpb(L_check_fill_32_bytes);
5339 
5340           BIND(L_check_fill_64_bytes_avx2);
5341         }
5342         // Fill 64-byte chunks
5343         Label L_fill_64_bytes_loop;
5344         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
5345 
5346         subl(count, 16 << shift);
5347         jcc(Assembler::less, L_check_fill_32_bytes);
5348         align(16);
5349 
5350         BIND(L_fill_64_bytes_loop);
5351         vmovdqu(Address(to, 0), xtmp);
5352         vmovdqu(Address(to, 32), xtmp);
5353         addptr(to, 64);
5354         subl(count, 16 << shift);
5355         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
5356 
5357         BIND(L_check_fill_32_bytes);
5358         addl(count, 8 << shift);
5359         jccb(Assembler::less, L_check_fill_8_bytes);
5360         vmovdqu(Address(to, 0), xtmp);
5361         addptr(to, 32);
5362         subl(count, 8 << shift);
5363 
5364         BIND(L_check_fill_8_bytes);
5365         // clean upper bits of YMM registers
5366         movdl(xtmp, value);
5367         pshufd(xtmp, xtmp, 0);
5368       } else {
5369         // Fill 32-byte chunks
5370         pshufd(xtmp, xtmp, 0);
5371 
5372         subl(count, 8 << shift);
5373         jcc(Assembler::less, L_check_fill_8_bytes);
5374         align(16);
5375 
5376         BIND(L_fill_32_bytes_loop);
5377 
5378         if (UseUnalignedLoadStores) {
5379           movdqu(Address(to, 0), xtmp);
5380           movdqu(Address(to, 16), xtmp);
5381         } else {
5382           movq(Address(to, 0), xtmp);
5383           movq(Address(to, 8), xtmp);
5384           movq(Address(to, 16), xtmp);
5385           movq(Address(to, 24), xtmp);
5386         }
5387 
5388         addptr(to, 32);
5389         subl(count, 8 << shift);
5390         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5391 
5392         BIND(L_check_fill_8_bytes);
5393       }
5394       addl(count, 8 << shift);
5395       jccb(Assembler::zero, L_exit);
5396       jmpb(L_fill_8_bytes);
5397 
5398       //
5399       // length is too short, just fill qwords
5400       //
5401       BIND(L_fill_8_bytes_loop);
5402       movq(Address(to, 0), xtmp);
5403       addptr(to, 8);
5404       BIND(L_fill_8_bytes);
5405       subl(count, 1 << (shift + 1));
5406       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5407     }
5408   }
5409   // fill trailing 4 bytes
5410   BIND(L_fill_4_bytes);
5411   testl(count, 1<<shift);
5412   jccb(Assembler::zero, L_fill_2_bytes);
5413   movl(Address(to, 0), value);
5414   if (t == T_BYTE || t == T_SHORT) {
5415     Label L_fill_byte;
5416     addptr(to, 4);
5417     BIND(L_fill_2_bytes);
5418     // fill trailing 2 bytes
5419     testl(count, 1<<(shift-1));
5420     jccb(Assembler::zero, L_fill_byte);
5421     movw(Address(to, 0), value);
5422     if (t == T_BYTE) {
5423       addptr(to, 2);
5424       BIND(L_fill_byte);
5425       // fill trailing byte
5426       testl(count, 1);
5427       jccb(Assembler::zero, L_exit);
5428       movb(Address(to, 0), value);
5429     } else {
5430       BIND(L_fill_byte);
5431     }
5432   } else {
5433     BIND(L_fill_2_bytes);
5434   }
5435   BIND(L_exit);
5436 }
5437 
5438 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
5439   switch(type) {
5440     case T_BYTE:
5441     case T_BOOLEAN:
5442       evpbroadcastb(dst, src, vector_len);
5443       break;
5444     case T_SHORT:
5445     case T_CHAR:
5446       evpbroadcastw(dst, src, vector_len);
5447       break;
5448     case T_INT:
5449     case T_FLOAT:
5450       evpbroadcastd(dst, src, vector_len);
5451       break;
5452     case T_LONG:
5453     case T_DOUBLE:
5454       evpbroadcastq(dst, src, vector_len);
5455       break;
5456     default:
5457       fatal("Unhandled type : %s", type2name(type));
5458       break;
5459   }
5460 }
5461 
5462 // encode char[] to byte[] in ISO_8859_1 or ASCII
5463    //@IntrinsicCandidate
5464    //private static int implEncodeISOArray(byte[] sa, int sp,
5465    //byte[] da, int dp, int len) {
5466    //  int i = 0;
5467    //  for (; i < len; i++) {
5468    //    char c = StringUTF16.getChar(sa, sp++);
5469    //    if (c > '\u00FF')
5470    //      break;
5471    //    da[dp++] = (byte)c;
5472    //  }
5473    //  return i;
5474    //}
5475    //
5476    //@IntrinsicCandidate
5477    //private static int implEncodeAsciiArray(char[] sa, int sp,
5478    //    byte[] da, int dp, int len) {
5479    //  int i = 0;
5480    //  for (; i < len; i++) {
5481    //    char c = sa[sp++];
5482    //    if (c >= '\u0080')
5483    //      break;
5484    //    da[dp++] = (byte)c;
5485    //  }
5486    //  return i;
5487    //}
5488 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
5489   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
5490   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
5491   Register tmp5, Register result, bool ascii) {
5492 
5493   // rsi: src
5494   // rdi: dst
5495   // rdx: len
5496   // rcx: tmp5
5497   // rax: result
5498   ShortBranchVerifier sbv(this);
5499   assert_different_registers(src, dst, len, tmp5, result);
5500   Label L_done, L_copy_1_char, L_copy_1_char_exit;
5501 
5502   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
5503   int short_mask = ascii ? 0xff80 : 0xff00;
5504 
5505   // set result
5506   xorl(result, result);
5507   // check for zero length
5508   testl(len, len);
5509   jcc(Assembler::zero, L_done);
5510 
5511   movl(result, len);
5512 
5513   // Setup pointers
5514   lea(src, Address(src, len, Address::times_2)); // char[]
5515   lea(dst, Address(dst, len, Address::times_1)); // byte[]
5516   negptr(len);
5517 
5518   if (UseSSE42Intrinsics || UseAVX >= 2) {
5519     Label L_copy_8_chars, L_copy_8_chars_exit;
5520     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
5521 
5522     if (UseAVX >= 2) {
5523       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
5524       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5525       movdl(tmp1Reg, tmp5);
5526       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
5527       jmp(L_chars_32_check);
5528 
5529       bind(L_copy_32_chars);
5530       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
5531       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
5532       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5533       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5534       jccb(Assembler::notZero, L_copy_32_chars_exit);
5535       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5536       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
5537       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
5538 
5539       bind(L_chars_32_check);
5540       addptr(len, 32);
5541       jcc(Assembler::lessEqual, L_copy_32_chars);
5542 
5543       bind(L_copy_32_chars_exit);
5544       subptr(len, 16);
5545       jccb(Assembler::greater, L_copy_16_chars_exit);
5546 
5547     } else if (UseSSE42Intrinsics) {
5548       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5549       movdl(tmp1Reg, tmp5);
5550       pshufd(tmp1Reg, tmp1Reg, 0);
5551       jmpb(L_chars_16_check);
5552     }
5553 
5554     bind(L_copy_16_chars);
5555     if (UseAVX >= 2) {
5556       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
5557       vptest(tmp2Reg, tmp1Reg);
5558       jcc(Assembler::notZero, L_copy_16_chars_exit);
5559       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
5560       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
5561     } else {
5562       if (UseAVX > 0) {
5563         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5564         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5565         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
5566       } else {
5567         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5568         por(tmp2Reg, tmp3Reg);
5569         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5570         por(tmp2Reg, tmp4Reg);
5571       }
5572       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5573       jccb(Assembler::notZero, L_copy_16_chars_exit);
5574       packuswb(tmp3Reg, tmp4Reg);
5575     }
5576     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
5577 
5578     bind(L_chars_16_check);
5579     addptr(len, 16);
5580     jcc(Assembler::lessEqual, L_copy_16_chars);
5581 
5582     bind(L_copy_16_chars_exit);
5583     if (UseAVX >= 2) {
5584       // clean upper bits of YMM registers
5585       vpxor(tmp2Reg, tmp2Reg);
5586       vpxor(tmp3Reg, tmp3Reg);
5587       vpxor(tmp4Reg, tmp4Reg);
5588       movdl(tmp1Reg, tmp5);
5589       pshufd(tmp1Reg, tmp1Reg, 0);
5590     }
5591     subptr(len, 8);
5592     jccb(Assembler::greater, L_copy_8_chars_exit);
5593 
5594     bind(L_copy_8_chars);
5595     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
5596     ptest(tmp3Reg, tmp1Reg);
5597     jccb(Assembler::notZero, L_copy_8_chars_exit);
5598     packuswb(tmp3Reg, tmp1Reg);
5599     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
5600     addptr(len, 8);
5601     jccb(Assembler::lessEqual, L_copy_8_chars);
5602 
5603     bind(L_copy_8_chars_exit);
5604     subptr(len, 8);
5605     jccb(Assembler::zero, L_done);
5606   }
5607 
5608   bind(L_copy_1_char);
5609   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
5610   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
5611   jccb(Assembler::notZero, L_copy_1_char_exit);
5612   movb(Address(dst, len, Address::times_1, 0), tmp5);
5613   addptr(len, 1);
5614   jccb(Assembler::less, L_copy_1_char);
5615 
5616   bind(L_copy_1_char_exit);
5617   addptr(result, len); // len is negative count of not processed elements
5618 
5619   bind(L_done);
5620 }
5621 
5622 #ifdef _LP64
5623 /**
5624  * Helper for multiply_to_len().
5625  */
5626 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
5627   addq(dest_lo, src1);
5628   adcq(dest_hi, 0);
5629   addq(dest_lo, src2);
5630   adcq(dest_hi, 0);
5631 }
5632 
5633 /**
5634  * Multiply 64 bit by 64 bit first loop.
5635  */
5636 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
5637                                            Register y, Register y_idx, Register z,
5638                                            Register carry, Register product,
5639                                            Register idx, Register kdx) {
5640   //
5641   //  jlong carry, x[], y[], z[];
5642   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5643   //    huge_128 product = y[idx] * x[xstart] + carry;
5644   //    z[kdx] = (jlong)product;
5645   //    carry  = (jlong)(product >>> 64);
5646   //  }
5647   //  z[xstart] = carry;
5648   //
5649 
5650   Label L_first_loop, L_first_loop_exit;
5651   Label L_one_x, L_one_y, L_multiply;
5652 
5653   decrementl(xstart);
5654   jcc(Assembler::negative, L_one_x);
5655 
5656   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
5657   rorq(x_xstart, 32); // convert big-endian to little-endian
5658 
5659   bind(L_first_loop);
5660   decrementl(idx);
5661   jcc(Assembler::negative, L_first_loop_exit);
5662   decrementl(idx);
5663   jcc(Assembler::negative, L_one_y);
5664   movq(y_idx, Address(y, idx, Address::times_4,  0));
5665   rorq(y_idx, 32); // convert big-endian to little-endian
5666   bind(L_multiply);
5667   movq(product, x_xstart);
5668   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
5669   addq(product, carry);
5670   adcq(rdx, 0);
5671   subl(kdx, 2);
5672   movl(Address(z, kdx, Address::times_4,  4), product);
5673   shrq(product, 32);
5674   movl(Address(z, kdx, Address::times_4,  0), product);
5675   movq(carry, rdx);
5676   jmp(L_first_loop);
5677 
5678   bind(L_one_y);
5679   movl(y_idx, Address(y,  0));
5680   jmp(L_multiply);
5681 
5682   bind(L_one_x);
5683   movl(x_xstart, Address(x,  0));
5684   jmp(L_first_loop);
5685 
5686   bind(L_first_loop_exit);
5687 }
5688 
5689 /**
5690  * Multiply 64 bit by 64 bit and add 128 bit.
5691  */
5692 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
5693                                             Register yz_idx, Register idx,
5694                                             Register carry, Register product, int offset) {
5695   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
5696   //     z[kdx] = (jlong)product;
5697 
5698   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
5699   rorq(yz_idx, 32); // convert big-endian to little-endian
5700   movq(product, x_xstart);
5701   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
5702   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
5703   rorq(yz_idx, 32); // convert big-endian to little-endian
5704 
5705   add2_with_carry(rdx, product, carry, yz_idx);
5706 
5707   movl(Address(z, idx, Address::times_4,  offset+4), product);
5708   shrq(product, 32);
5709   movl(Address(z, idx, Address::times_4,  offset), product);
5710 
5711 }
5712 
5713 /**
5714  * Multiply 128 bit by 128 bit. Unrolled inner loop.
5715  */
5716 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
5717                                              Register yz_idx, Register idx, Register jdx,
5718                                              Register carry, Register product,
5719                                              Register carry2) {
5720   //   jlong carry, x[], y[], z[];
5721   //   int kdx = ystart+1;
5722   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5723   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
5724   //     z[kdx+idx+1] = (jlong)product;
5725   //     jlong carry2  = (jlong)(product >>> 64);
5726   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
5727   //     z[kdx+idx] = (jlong)product;
5728   //     carry  = (jlong)(product >>> 64);
5729   //   }
5730   //   idx += 2;
5731   //   if (idx > 0) {
5732   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
5733   //     z[kdx+idx] = (jlong)product;
5734   //     carry  = (jlong)(product >>> 64);
5735   //   }
5736   //
5737 
5738   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5739 
5740   movl(jdx, idx);
5741   andl(jdx, 0xFFFFFFFC);
5742   shrl(jdx, 2);
5743 
5744   bind(L_third_loop);
5745   subl(jdx, 1);
5746   jcc(Assembler::negative, L_third_loop_exit);
5747   subl(idx, 4);
5748 
5749   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
5750   movq(carry2, rdx);
5751 
5752   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
5753   movq(carry, rdx);
5754   jmp(L_third_loop);
5755 
5756   bind (L_third_loop_exit);
5757 
5758   andl (idx, 0x3);
5759   jcc(Assembler::zero, L_post_third_loop_done);
5760 
5761   Label L_check_1;
5762   subl(idx, 2);
5763   jcc(Assembler::negative, L_check_1);
5764 
5765   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
5766   movq(carry, rdx);
5767 
5768   bind (L_check_1);
5769   addl (idx, 0x2);
5770   andl (idx, 0x1);
5771   subl(idx, 1);
5772   jcc(Assembler::negative, L_post_third_loop_done);
5773 
5774   movl(yz_idx, Address(y, idx, Address::times_4,  0));
5775   movq(product, x_xstart);
5776   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5777   movl(yz_idx, Address(z, idx, Address::times_4,  0));
5778 
5779   add2_with_carry(rdx, product, yz_idx, carry);
5780 
5781   movl(Address(z, idx, Address::times_4,  0), product);
5782   shrq(product, 32);
5783 
5784   shlq(rdx, 32);
5785   orq(product, rdx);
5786   movq(carry, product);
5787 
5788   bind(L_post_third_loop_done);
5789 }
5790 
5791 /**
5792  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
5793  *
5794  */
5795 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
5796                                                   Register carry, Register carry2,
5797                                                   Register idx, Register jdx,
5798                                                   Register yz_idx1, Register yz_idx2,
5799                                                   Register tmp, Register tmp3, Register tmp4) {
5800   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
5801 
5802   //   jlong carry, x[], y[], z[];
5803   //   int kdx = ystart+1;
5804   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5805   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
5806   //     jlong carry2  = (jlong)(tmp3 >>> 64);
5807   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
5808   //     carry  = (jlong)(tmp4 >>> 64);
5809   //     z[kdx+idx+1] = (jlong)tmp3;
5810   //     z[kdx+idx] = (jlong)tmp4;
5811   //   }
5812   //   idx += 2;
5813   //   if (idx > 0) {
5814   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
5815   //     z[kdx+idx] = (jlong)yz_idx1;
5816   //     carry  = (jlong)(yz_idx1 >>> 64);
5817   //   }
5818   //
5819 
5820   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5821 
5822   movl(jdx, idx);
5823   andl(jdx, 0xFFFFFFFC);
5824   shrl(jdx, 2);
5825 
5826   bind(L_third_loop);
5827   subl(jdx, 1);
5828   jcc(Assembler::negative, L_third_loop_exit);
5829   subl(idx, 4);
5830 
5831   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
5832   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
5833   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
5834   rorxq(yz_idx2, yz_idx2, 32);
5835 
5836   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
5837   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
5838 
5839   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
5840   rorxq(yz_idx1, yz_idx1, 32);
5841   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
5842   rorxq(yz_idx2, yz_idx2, 32);
5843 
5844   if (VM_Version::supports_adx()) {
5845     adcxq(tmp3, carry);
5846     adoxq(tmp3, yz_idx1);
5847 
5848     adcxq(tmp4, tmp);
5849     adoxq(tmp4, yz_idx2);
5850 
5851     movl(carry, 0); // does not affect flags
5852     adcxq(carry2, carry);
5853     adoxq(carry2, carry);
5854   } else {
5855     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
5856     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
5857   }
5858   movq(carry, carry2);
5859 
5860   movl(Address(z, idx, Address::times_4, 12), tmp3);
5861   shrq(tmp3, 32);
5862   movl(Address(z, idx, Address::times_4,  8), tmp3);
5863 
5864   movl(Address(z, idx, Address::times_4,  4), tmp4);
5865   shrq(tmp4, 32);
5866   movl(Address(z, idx, Address::times_4,  0), tmp4);
5867 
5868   jmp(L_third_loop);
5869 
5870   bind (L_third_loop_exit);
5871 
5872   andl (idx, 0x3);
5873   jcc(Assembler::zero, L_post_third_loop_done);
5874 
5875   Label L_check_1;
5876   subl(idx, 2);
5877   jcc(Assembler::negative, L_check_1);
5878 
5879   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
5880   rorxq(yz_idx1, yz_idx1, 32);
5881   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
5882   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
5883   rorxq(yz_idx2, yz_idx2, 32);
5884 
5885   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
5886 
5887   movl(Address(z, idx, Address::times_4,  4), tmp3);
5888   shrq(tmp3, 32);
5889   movl(Address(z, idx, Address::times_4,  0), tmp3);
5890   movq(carry, tmp4);
5891 
5892   bind (L_check_1);
5893   addl (idx, 0x2);
5894   andl (idx, 0x1);
5895   subl(idx, 1);
5896   jcc(Assembler::negative, L_post_third_loop_done);
5897   movl(tmp4, Address(y, idx, Address::times_4,  0));
5898   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
5899   movl(tmp4, Address(z, idx, Address::times_4,  0));
5900 
5901   add2_with_carry(carry2, tmp3, tmp4, carry);
5902 
5903   movl(Address(z, idx, Address::times_4,  0), tmp3);
5904   shrq(tmp3, 32);
5905 
5906   shlq(carry2, 32);
5907   orq(tmp3, carry2);
5908   movq(carry, tmp3);
5909 
5910   bind(L_post_third_loop_done);
5911 }
5912 
5913 /**
5914  * Code for BigInteger::multiplyToLen() instrinsic.
5915  *
5916  * rdi: x
5917  * rax: xlen
5918  * rsi: y
5919  * rcx: ylen
5920  * r8:  z
5921  * r11: zlen
5922  * r12: tmp1
5923  * r13: tmp2
5924  * r14: tmp3
5925  * r15: tmp4
5926  * rbx: tmp5
5927  *
5928  */
5929 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
5930                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
5931   ShortBranchVerifier sbv(this);
5932   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
5933 
5934   push(tmp1);
5935   push(tmp2);
5936   push(tmp3);
5937   push(tmp4);
5938   push(tmp5);
5939 
5940   push(xlen);
5941   push(zlen);
5942 
5943   const Register idx = tmp1;
5944   const Register kdx = tmp2;
5945   const Register xstart = tmp3;
5946 
5947   const Register y_idx = tmp4;
5948   const Register carry = tmp5;
5949   const Register product  = xlen;
5950   const Register x_xstart = zlen;  // reuse register
5951 
5952   // First Loop.
5953   //
5954   //  final static long LONG_MASK = 0xffffffffL;
5955   //  int xstart = xlen - 1;
5956   //  int ystart = ylen - 1;
5957   //  long carry = 0;
5958   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5959   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
5960   //    z[kdx] = (int)product;
5961   //    carry = product >>> 32;
5962   //  }
5963   //  z[xstart] = (int)carry;
5964   //
5965 
5966   movl(idx, ylen);      // idx = ylen;
5967   movl(kdx, zlen);      // kdx = xlen+ylen;
5968   xorq(carry, carry);   // carry = 0;
5969 
5970   Label L_done;
5971 
5972   movl(xstart, xlen);
5973   decrementl(xstart);
5974   jcc(Assembler::negative, L_done);
5975 
5976   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
5977 
5978   Label L_second_loop;
5979   testl(kdx, kdx);
5980   jcc(Assembler::zero, L_second_loop);
5981 
5982   Label L_carry;
5983   subl(kdx, 1);
5984   jcc(Assembler::zero, L_carry);
5985 
5986   movl(Address(z, kdx, Address::times_4,  0), carry);
5987   shrq(carry, 32);
5988   subl(kdx, 1);
5989 
5990   bind(L_carry);
5991   movl(Address(z, kdx, Address::times_4,  0), carry);
5992 
5993   // Second and third (nested) loops.
5994   //
5995   // for (int i = xstart-1; i >= 0; i--) { // Second loop
5996   //   carry = 0;
5997   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
5998   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
5999   //                    (z[k] & LONG_MASK) + carry;
6000   //     z[k] = (int)product;
6001   //     carry = product >>> 32;
6002   //   }
6003   //   z[i] = (int)carry;
6004   // }
6005   //
6006   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6007 
6008   const Register jdx = tmp1;
6009 
6010   bind(L_second_loop);
6011   xorl(carry, carry);    // carry = 0;
6012   movl(jdx, ylen);       // j = ystart+1
6013 
6014   subl(xstart, 1);       // i = xstart-1;
6015   jcc(Assembler::negative, L_done);
6016 
6017   push (z);
6018 
6019   Label L_last_x;
6020   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6021   subl(xstart, 1);       // i = xstart-1;
6022   jcc(Assembler::negative, L_last_x);
6023 
6024   if (UseBMI2Instructions) {
6025     movq(rdx,  Address(x, xstart, Address::times_4,  0));
6026     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6027   } else {
6028     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6029     rorq(x_xstart, 32);  // convert big-endian to little-endian
6030   }
6031 
6032   Label L_third_loop_prologue;
6033   bind(L_third_loop_prologue);
6034 
6035   push (x);
6036   push (xstart);
6037   push (ylen);
6038 
6039 
6040   if (UseBMI2Instructions) {
6041     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6042   } else { // !UseBMI2Instructions
6043     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6044   }
6045 
6046   pop(ylen);
6047   pop(xlen);
6048   pop(x);
6049   pop(z);
6050 
6051   movl(tmp3, xlen);
6052   addl(tmp3, 1);
6053   movl(Address(z, tmp3, Address::times_4,  0), carry);
6054   subl(tmp3, 1);
6055   jccb(Assembler::negative, L_done);
6056 
6057   shrq(carry, 32);
6058   movl(Address(z, tmp3, Address::times_4,  0), carry);
6059   jmp(L_second_loop);
6060 
6061   // Next infrequent code is moved outside loops.
6062   bind(L_last_x);
6063   if (UseBMI2Instructions) {
6064     movl(rdx, Address(x,  0));
6065   } else {
6066     movl(x_xstart, Address(x,  0));
6067   }
6068   jmp(L_third_loop_prologue);
6069 
6070   bind(L_done);
6071 
6072   pop(zlen);
6073   pop(xlen);
6074 
6075   pop(tmp5);
6076   pop(tmp4);
6077   pop(tmp3);
6078   pop(tmp2);
6079   pop(tmp1);
6080 }
6081 
6082 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6083   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6084   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6085   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6086   Label VECTOR8_TAIL, VECTOR4_TAIL;
6087   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6088   Label SAME_TILL_END, DONE;
6089   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6090 
6091   //scale is in rcx in both Win64 and Unix
6092   ShortBranchVerifier sbv(this);
6093 
6094   shlq(length);
6095   xorq(result, result);
6096 
6097   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6098       VM_Version::supports_avx512vlbw()) {
6099     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6100 
6101     cmpq(length, 64);
6102     jcc(Assembler::less, VECTOR32_TAIL);
6103 
6104     movq(tmp1, length);
6105     andq(tmp1, 0x3F);      // tail count
6106     andq(length, ~(0x3F)); //vector count
6107 
6108     bind(VECTOR64_LOOP);
6109     // AVX512 code to compare 64 byte vectors.
6110     evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6111     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6112     kortestql(k7, k7);
6113     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
6114     addq(result, 64);
6115     subq(length, 64);
6116     jccb(Assembler::notZero, VECTOR64_LOOP);
6117 
6118     //bind(VECTOR64_TAIL);
6119     testq(tmp1, tmp1);
6120     jcc(Assembler::zero, SAME_TILL_END);
6121 
6122     //bind(VECTOR64_TAIL);
6123     // AVX512 code to compare upto 63 byte vectors.
6124     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6125     shlxq(tmp2, tmp2, tmp1);
6126     notq(tmp2);
6127     kmovql(k3, tmp2);
6128 
6129     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6130     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6131 
6132     ktestql(k7, k3);
6133     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
6134 
6135     bind(VECTOR64_NOT_EQUAL);
6136     kmovql(tmp1, k7);
6137     notq(tmp1);
6138     tzcntq(tmp1, tmp1);
6139     addq(result, tmp1);
6140     shrq(result);
6141     jmp(DONE);
6142     bind(VECTOR32_TAIL);
6143   }
6144 
6145   cmpq(length, 8);
6146   jcc(Assembler::equal, VECTOR8_LOOP);
6147   jcc(Assembler::less, VECTOR4_TAIL);
6148 
6149   if (UseAVX >= 2) {
6150     Label VECTOR16_TAIL, VECTOR32_LOOP;
6151 
6152     cmpq(length, 16);
6153     jcc(Assembler::equal, VECTOR16_LOOP);
6154     jcc(Assembler::less, VECTOR8_LOOP);
6155 
6156     cmpq(length, 32);
6157     jccb(Assembler::less, VECTOR16_TAIL);
6158 
6159     subq(length, 32);
6160     bind(VECTOR32_LOOP);
6161     vmovdqu(rymm0, Address(obja, result));
6162     vmovdqu(rymm1, Address(objb, result));
6163     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6164     vptest(rymm2, rymm2);
6165     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6166     addq(result, 32);
6167     subq(length, 32);
6168     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6169     addq(length, 32);
6170     jcc(Assembler::equal, SAME_TILL_END);
6171     //falling through if less than 32 bytes left //close the branch here.
6172 
6173     bind(VECTOR16_TAIL);
6174     cmpq(length, 16);
6175     jccb(Assembler::less, VECTOR8_TAIL);
6176     bind(VECTOR16_LOOP);
6177     movdqu(rymm0, Address(obja, result));
6178     movdqu(rymm1, Address(objb, result));
6179     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6180     ptest(rymm2, rymm2);
6181     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6182     addq(result, 16);
6183     subq(length, 16);
6184     jcc(Assembler::equal, SAME_TILL_END);
6185     //falling through if less than 16 bytes left
6186   } else {//regular intrinsics
6187 
6188     cmpq(length, 16);
6189     jccb(Assembler::less, VECTOR8_TAIL);
6190 
6191     subq(length, 16);
6192     bind(VECTOR16_LOOP);
6193     movdqu(rymm0, Address(obja, result));
6194     movdqu(rymm1, Address(objb, result));
6195     pxor(rymm0, rymm1);
6196     ptest(rymm0, rymm0);
6197     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6198     addq(result, 16);
6199     subq(length, 16);
6200     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6201     addq(length, 16);
6202     jcc(Assembler::equal, SAME_TILL_END);
6203     //falling through if less than 16 bytes left
6204   }
6205 
6206   bind(VECTOR8_TAIL);
6207   cmpq(length, 8);
6208   jccb(Assembler::less, VECTOR4_TAIL);
6209   bind(VECTOR8_LOOP);
6210   movq(tmp1, Address(obja, result));
6211   movq(tmp2, Address(objb, result));
6212   xorq(tmp1, tmp2);
6213   testq(tmp1, tmp1);
6214   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6215   addq(result, 8);
6216   subq(length, 8);
6217   jcc(Assembler::equal, SAME_TILL_END);
6218   //falling through if less than 8 bytes left
6219 
6220   bind(VECTOR4_TAIL);
6221   cmpq(length, 4);
6222   jccb(Assembler::less, BYTES_TAIL);
6223   bind(VECTOR4_LOOP);
6224   movl(tmp1, Address(obja, result));
6225   xorl(tmp1, Address(objb, result));
6226   testl(tmp1, tmp1);
6227   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6228   addq(result, 4);
6229   subq(length, 4);
6230   jcc(Assembler::equal, SAME_TILL_END);
6231   //falling through if less than 4 bytes left
6232 
6233   bind(BYTES_TAIL);
6234   bind(BYTES_LOOP);
6235   load_unsigned_byte(tmp1, Address(obja, result));
6236   load_unsigned_byte(tmp2, Address(objb, result));
6237   xorl(tmp1, tmp2);
6238   testl(tmp1, tmp1);
6239   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6240   decq(length);
6241   jcc(Assembler::zero, SAME_TILL_END);
6242   incq(result);
6243   load_unsigned_byte(tmp1, Address(obja, result));
6244   load_unsigned_byte(tmp2, Address(objb, result));
6245   xorl(tmp1, tmp2);
6246   testl(tmp1, tmp1);
6247   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6248   decq(length);
6249   jcc(Assembler::zero, SAME_TILL_END);
6250   incq(result);
6251   load_unsigned_byte(tmp1, Address(obja, result));
6252   load_unsigned_byte(tmp2, Address(objb, result));
6253   xorl(tmp1, tmp2);
6254   testl(tmp1, tmp1);
6255   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6256   jmp(SAME_TILL_END);
6257 
6258   if (UseAVX >= 2) {
6259     bind(VECTOR32_NOT_EQUAL);
6260     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6261     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6262     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6263     vpmovmskb(tmp1, rymm0);
6264     bsfq(tmp1, tmp1);
6265     addq(result, tmp1);
6266     shrq(result);
6267     jmp(DONE);
6268   }
6269 
6270   bind(VECTOR16_NOT_EQUAL);
6271   if (UseAVX >= 2) {
6272     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6273     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6274     pxor(rymm0, rymm2);
6275   } else {
6276     pcmpeqb(rymm2, rymm2);
6277     pxor(rymm0, rymm1);
6278     pcmpeqb(rymm0, rymm1);
6279     pxor(rymm0, rymm2);
6280   }
6281   pmovmskb(tmp1, rymm0);
6282   bsfq(tmp1, tmp1);
6283   addq(result, tmp1);
6284   shrq(result);
6285   jmpb(DONE);
6286 
6287   bind(VECTOR8_NOT_EQUAL);
6288   bind(VECTOR4_NOT_EQUAL);
6289   bsfq(tmp1, tmp1);
6290   shrq(tmp1, 3);
6291   addq(result, tmp1);
6292   bind(BYTES_NOT_EQUAL);
6293   shrq(result);
6294   jmpb(DONE);
6295 
6296   bind(SAME_TILL_END);
6297   mov64(result, -1);
6298 
6299   bind(DONE);
6300 }
6301 
6302 //Helper functions for square_to_len()
6303 
6304 /**
6305  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6306  * Preserves x and z and modifies rest of the registers.
6307  */
6308 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6309   // Perform square and right shift by 1
6310   // Handle odd xlen case first, then for even xlen do the following
6311   // jlong carry = 0;
6312   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6313   //     huge_128 product = x[j:j+1] * x[j:j+1];
6314   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6315   //     z[i+2:i+3] = (jlong)(product >>> 1);
6316   //     carry = (jlong)product;
6317   // }
6318 
6319   xorq(tmp5, tmp5);     // carry
6320   xorq(rdxReg, rdxReg);
6321   xorl(tmp1, tmp1);     // index for x
6322   xorl(tmp4, tmp4);     // index for z
6323 
6324   Label L_first_loop, L_first_loop_exit;
6325 
6326   testl(xlen, 1);
6327   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
6328 
6329   // Square and right shift by 1 the odd element using 32 bit multiply
6330   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
6331   imulq(raxReg, raxReg);
6332   shrq(raxReg, 1);
6333   adcq(tmp5, 0);
6334   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
6335   incrementl(tmp1);
6336   addl(tmp4, 2);
6337 
6338   // Square and  right shift by 1 the rest using 64 bit multiply
6339   bind(L_first_loop);
6340   cmpptr(tmp1, xlen);
6341   jccb(Assembler::equal, L_first_loop_exit);
6342 
6343   // Square
6344   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
6345   rorq(raxReg, 32);    // convert big-endian to little-endian
6346   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
6347 
6348   // Right shift by 1 and save carry
6349   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
6350   rcrq(rdxReg, 1);
6351   rcrq(raxReg, 1);
6352   adcq(tmp5, 0);
6353 
6354   // Store result in z
6355   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
6356   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
6357 
6358   // Update indices for x and z
6359   addl(tmp1, 2);
6360   addl(tmp4, 4);
6361   jmp(L_first_loop);
6362 
6363   bind(L_first_loop_exit);
6364 }
6365 
6366 
6367 /**
6368  * Perform the following multiply add operation using BMI2 instructions
6369  * carry:sum = sum + op1*op2 + carry
6370  * op2 should be in rdx
6371  * op2 is preserved, all other registers are modified
6372  */
6373 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
6374   // assert op2 is rdx
6375   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
6376   addq(sum, carry);
6377   adcq(tmp2, 0);
6378   addq(sum, op1);
6379   adcq(tmp2, 0);
6380   movq(carry, tmp2);
6381 }
6382 
6383 /**
6384  * Perform the following multiply add operation:
6385  * carry:sum = sum + op1*op2 + carry
6386  * Preserves op1, op2 and modifies rest of registers
6387  */
6388 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
6389   // rdx:rax = op1 * op2
6390   movq(raxReg, op2);
6391   mulq(op1);
6392 
6393   //  rdx:rax = sum + carry + rdx:rax
6394   addq(sum, carry);
6395   adcq(rdxReg, 0);
6396   addq(sum, raxReg);
6397   adcq(rdxReg, 0);
6398 
6399   // carry:sum = rdx:sum
6400   movq(carry, rdxReg);
6401 }
6402 
6403 /**
6404  * Add 64 bit long carry into z[] with carry propogation.
6405  * Preserves z and carry register values and modifies rest of registers.
6406  *
6407  */
6408 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
6409   Label L_fourth_loop, L_fourth_loop_exit;
6410 
6411   movl(tmp1, 1);
6412   subl(zlen, 2);
6413   addq(Address(z, zlen, Address::times_4, 0), carry);
6414 
6415   bind(L_fourth_loop);
6416   jccb(Assembler::carryClear, L_fourth_loop_exit);
6417   subl(zlen, 2);
6418   jccb(Assembler::negative, L_fourth_loop_exit);
6419   addq(Address(z, zlen, Address::times_4, 0), tmp1);
6420   jmp(L_fourth_loop);
6421   bind(L_fourth_loop_exit);
6422 }
6423 
6424 /**
6425  * Shift z[] left by 1 bit.
6426  * Preserves x, len, z and zlen registers and modifies rest of the registers.
6427  *
6428  */
6429 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
6430 
6431   Label L_fifth_loop, L_fifth_loop_exit;
6432 
6433   // Fifth loop
6434   // Perform primitiveLeftShift(z, zlen, 1)
6435 
6436   const Register prev_carry = tmp1;
6437   const Register new_carry = tmp4;
6438   const Register value = tmp2;
6439   const Register zidx = tmp3;
6440 
6441   // int zidx, carry;
6442   // long value;
6443   // carry = 0;
6444   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
6445   //    (carry:value)  = (z[i] << 1) | carry ;
6446   //    z[i] = value;
6447   // }
6448 
6449   movl(zidx, zlen);
6450   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
6451 
6452   bind(L_fifth_loop);
6453   decl(zidx);  // Use decl to preserve carry flag
6454   decl(zidx);
6455   jccb(Assembler::negative, L_fifth_loop_exit);
6456 
6457   if (UseBMI2Instructions) {
6458      movq(value, Address(z, zidx, Address::times_4, 0));
6459      rclq(value, 1);
6460      rorxq(value, value, 32);
6461      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6462   }
6463   else {
6464     // clear new_carry
6465     xorl(new_carry, new_carry);
6466 
6467     // Shift z[i] by 1, or in previous carry and save new carry
6468     movq(value, Address(z, zidx, Address::times_4, 0));
6469     shlq(value, 1);
6470     adcl(new_carry, 0);
6471 
6472     orq(value, prev_carry);
6473     rorq(value, 0x20);
6474     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6475 
6476     // Set previous carry = new carry
6477     movl(prev_carry, new_carry);
6478   }
6479   jmp(L_fifth_loop);
6480 
6481   bind(L_fifth_loop_exit);
6482 }
6483 
6484 
6485 /**
6486  * Code for BigInteger::squareToLen() intrinsic
6487  *
6488  * rdi: x
6489  * rsi: len
6490  * r8:  z
6491  * rcx: zlen
6492  * r12: tmp1
6493  * r13: tmp2
6494  * r14: tmp3
6495  * r15: tmp4
6496  * rbx: tmp5
6497  *
6498  */
6499 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6500 
6501   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
6502   push(tmp1);
6503   push(tmp2);
6504   push(tmp3);
6505   push(tmp4);
6506   push(tmp5);
6507 
6508   // First loop
6509   // Store the squares, right shifted one bit (i.e., divided by 2).
6510   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
6511 
6512   // Add in off-diagonal sums.
6513   //
6514   // Second, third (nested) and fourth loops.
6515   // zlen +=2;
6516   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
6517   //    carry = 0;
6518   //    long op2 = x[xidx:xidx+1];
6519   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
6520   //       k -= 2;
6521   //       long op1 = x[j:j+1];
6522   //       long sum = z[k:k+1];
6523   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
6524   //       z[k:k+1] = sum;
6525   //    }
6526   //    add_one_64(z, k, carry, tmp_regs);
6527   // }
6528 
6529   const Register carry = tmp5;
6530   const Register sum = tmp3;
6531   const Register op1 = tmp4;
6532   Register op2 = tmp2;
6533 
6534   push(zlen);
6535   push(len);
6536   addl(zlen,2);
6537   bind(L_second_loop);
6538   xorq(carry, carry);
6539   subl(zlen, 4);
6540   subl(len, 2);
6541   push(zlen);
6542   push(len);
6543   cmpl(len, 0);
6544   jccb(Assembler::lessEqual, L_second_loop_exit);
6545 
6546   // Multiply an array by one 64 bit long.
6547   if (UseBMI2Instructions) {
6548     op2 = rdxReg;
6549     movq(op2, Address(x, len, Address::times_4,  0));
6550     rorxq(op2, op2, 32);
6551   }
6552   else {
6553     movq(op2, Address(x, len, Address::times_4,  0));
6554     rorq(op2, 32);
6555   }
6556 
6557   bind(L_third_loop);
6558   decrementl(len);
6559   jccb(Assembler::negative, L_third_loop_exit);
6560   decrementl(len);
6561   jccb(Assembler::negative, L_last_x);
6562 
6563   movq(op1, Address(x, len, Address::times_4,  0));
6564   rorq(op1, 32);
6565 
6566   bind(L_multiply);
6567   subl(zlen, 2);
6568   movq(sum, Address(z, zlen, Address::times_4,  0));
6569 
6570   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
6571   if (UseBMI2Instructions) {
6572     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
6573   }
6574   else {
6575     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6576   }
6577 
6578   movq(Address(z, zlen, Address::times_4, 0), sum);
6579 
6580   jmp(L_third_loop);
6581   bind(L_third_loop_exit);
6582 
6583   // Fourth loop
6584   // Add 64 bit long carry into z with carry propogation.
6585   // Uses offsetted zlen.
6586   add_one_64(z, zlen, carry, tmp1);
6587 
6588   pop(len);
6589   pop(zlen);
6590   jmp(L_second_loop);
6591 
6592   // Next infrequent code is moved outside loops.
6593   bind(L_last_x);
6594   movl(op1, Address(x, 0));
6595   jmp(L_multiply);
6596 
6597   bind(L_second_loop_exit);
6598   pop(len);
6599   pop(zlen);
6600   pop(len);
6601   pop(zlen);
6602 
6603   // Fifth loop
6604   // Shift z left 1 bit.
6605   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
6606 
6607   // z[zlen-1] |= x[len-1] & 1;
6608   movl(tmp3, Address(x, len, Address::times_4, -4));
6609   andl(tmp3, 1);
6610   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
6611 
6612   pop(tmp5);
6613   pop(tmp4);
6614   pop(tmp3);
6615   pop(tmp2);
6616   pop(tmp1);
6617 }
6618 
6619 /**
6620  * Helper function for mul_add()
6621  * Multiply the in[] by int k and add to out[] starting at offset offs using
6622  * 128 bit by 32 bit multiply and return the carry in tmp5.
6623  * Only quad int aligned length of in[] is operated on in this function.
6624  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
6625  * This function preserves out, in and k registers.
6626  * len and offset point to the appropriate index in "in" & "out" correspondingly
6627  * tmp5 has the carry.
6628  * other registers are temporary and are modified.
6629  *
6630  */
6631 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
6632   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
6633   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6634 
6635   Label L_first_loop, L_first_loop_exit;
6636 
6637   movl(tmp1, len);
6638   shrl(tmp1, 2);
6639 
6640   bind(L_first_loop);
6641   subl(tmp1, 1);
6642   jccb(Assembler::negative, L_first_loop_exit);
6643 
6644   subl(len, 4);
6645   subl(offset, 4);
6646 
6647   Register op2 = tmp2;
6648   const Register sum = tmp3;
6649   const Register op1 = tmp4;
6650   const Register carry = tmp5;
6651 
6652   if (UseBMI2Instructions) {
6653     op2 = rdxReg;
6654   }
6655 
6656   movq(op1, Address(in, len, Address::times_4,  8));
6657   rorq(op1, 32);
6658   movq(sum, Address(out, offset, Address::times_4,  8));
6659   rorq(sum, 32);
6660   if (UseBMI2Instructions) {
6661     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6662   }
6663   else {
6664     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6665   }
6666   // Store back in big endian from little endian
6667   rorq(sum, 0x20);
6668   movq(Address(out, offset, Address::times_4,  8), sum);
6669 
6670   movq(op1, Address(in, len, Address::times_4,  0));
6671   rorq(op1, 32);
6672   movq(sum, Address(out, offset, Address::times_4,  0));
6673   rorq(sum, 32);
6674   if (UseBMI2Instructions) {
6675     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6676   }
6677   else {
6678     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6679   }
6680   // Store back in big endian from little endian
6681   rorq(sum, 0x20);
6682   movq(Address(out, offset, Address::times_4,  0), sum);
6683 
6684   jmp(L_first_loop);
6685   bind(L_first_loop_exit);
6686 }
6687 
6688 /**
6689  * Code for BigInteger::mulAdd() intrinsic
6690  *
6691  * rdi: out
6692  * rsi: in
6693  * r11: offs (out.length - offset)
6694  * rcx: len
6695  * r8:  k
6696  * r12: tmp1
6697  * r13: tmp2
6698  * r14: tmp3
6699  * r15: tmp4
6700  * rbx: tmp5
6701  * Multiply the in[] by word k and add to out[], return the carry in rax
6702  */
6703 void MacroAssembler::mul_add(Register out, Register in, Register offs,
6704    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
6705    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6706 
6707   Label L_carry, L_last_in, L_done;
6708 
6709 // carry = 0;
6710 // for (int j=len-1; j >= 0; j--) {
6711 //    long product = (in[j] & LONG_MASK) * kLong +
6712 //                   (out[offs] & LONG_MASK) + carry;
6713 //    out[offs--] = (int)product;
6714 //    carry = product >>> 32;
6715 // }
6716 //
6717   push(tmp1);
6718   push(tmp2);
6719   push(tmp3);
6720   push(tmp4);
6721   push(tmp5);
6722 
6723   Register op2 = tmp2;
6724   const Register sum = tmp3;
6725   const Register op1 = tmp4;
6726   const Register carry =  tmp5;
6727 
6728   if (UseBMI2Instructions) {
6729     op2 = rdxReg;
6730     movl(op2, k);
6731   }
6732   else {
6733     movl(op2, k);
6734   }
6735 
6736   xorq(carry, carry);
6737 
6738   //First loop
6739 
6740   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
6741   //The carry is in tmp5
6742   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
6743 
6744   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
6745   decrementl(len);
6746   jccb(Assembler::negative, L_carry);
6747   decrementl(len);
6748   jccb(Assembler::negative, L_last_in);
6749 
6750   movq(op1, Address(in, len, Address::times_4,  0));
6751   rorq(op1, 32);
6752 
6753   subl(offs, 2);
6754   movq(sum, Address(out, offs, Address::times_4,  0));
6755   rorq(sum, 32);
6756 
6757   if (UseBMI2Instructions) {
6758     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6759   }
6760   else {
6761     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6762   }
6763 
6764   // Store back in big endian from little endian
6765   rorq(sum, 0x20);
6766   movq(Address(out, offs, Address::times_4,  0), sum);
6767 
6768   testl(len, len);
6769   jccb(Assembler::zero, L_carry);
6770 
6771   //Multiply the last in[] entry, if any
6772   bind(L_last_in);
6773   movl(op1, Address(in, 0));
6774   movl(sum, Address(out, offs, Address::times_4,  -4));
6775 
6776   movl(raxReg, k);
6777   mull(op1); //tmp4 * eax -> edx:eax
6778   addl(sum, carry);
6779   adcl(rdxReg, 0);
6780   addl(sum, raxReg);
6781   adcl(rdxReg, 0);
6782   movl(carry, rdxReg);
6783 
6784   movl(Address(out, offs, Address::times_4,  -4), sum);
6785 
6786   bind(L_carry);
6787   //return tmp5/carry as carry in rax
6788   movl(rax, carry);
6789 
6790   bind(L_done);
6791   pop(tmp5);
6792   pop(tmp4);
6793   pop(tmp3);
6794   pop(tmp2);
6795   pop(tmp1);
6796 }
6797 #endif
6798 
6799 /**
6800  * Emits code to update CRC-32 with a byte value according to constants in table
6801  *
6802  * @param [in,out]crc   Register containing the crc.
6803  * @param [in]val       Register containing the byte to fold into the CRC.
6804  * @param [in]table     Register containing the table of crc constants.
6805  *
6806  * uint32_t crc;
6807  * val = crc_table[(val ^ crc) & 0xFF];
6808  * crc = val ^ (crc >> 8);
6809  *
6810  */
6811 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6812   xorl(val, crc);
6813   andl(val, 0xFF);
6814   shrl(crc, 8); // unsigned shift
6815   xorl(crc, Address(table, val, Address::times_4, 0));
6816 }
6817 
6818 /**
6819  * Fold 128-bit data chunk
6820  */
6821 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
6822   if (UseAVX > 0) {
6823     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
6824     vpclmulldq(xcrc, xK, xcrc); // [63:0]
6825     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
6826     pxor(xcrc, xtmp);
6827   } else {
6828     movdqa(xtmp, xcrc);
6829     pclmulhdq(xtmp, xK);   // [123:64]
6830     pclmulldq(xcrc, xK);   // [63:0]
6831     pxor(xcrc, xtmp);
6832     movdqu(xtmp, Address(buf, offset));
6833     pxor(xcrc, xtmp);
6834   }
6835 }
6836 
6837 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
6838   if (UseAVX > 0) {
6839     vpclmulhdq(xtmp, xK, xcrc);
6840     vpclmulldq(xcrc, xK, xcrc);
6841     pxor(xcrc, xbuf);
6842     pxor(xcrc, xtmp);
6843   } else {
6844     movdqa(xtmp, xcrc);
6845     pclmulhdq(xtmp, xK);
6846     pclmulldq(xcrc, xK);
6847     pxor(xcrc, xbuf);
6848     pxor(xcrc, xtmp);
6849   }
6850 }
6851 
6852 /**
6853  * 8-bit folds to compute 32-bit CRC
6854  *
6855  * uint64_t xcrc;
6856  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
6857  */
6858 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
6859   movdl(tmp, xcrc);
6860   andl(tmp, 0xFF);
6861   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
6862   psrldq(xcrc, 1); // unsigned shift one byte
6863   pxor(xcrc, xtmp);
6864 }
6865 
6866 /**
6867  * uint32_t crc;
6868  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
6869  */
6870 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
6871   movl(tmp, crc);
6872   andl(tmp, 0xFF);
6873   shrl(crc, 8);
6874   xorl(crc, Address(table, tmp, Address::times_4, 0));
6875 }
6876 
6877 /**
6878  * @param crc   register containing existing CRC (32-bit)
6879  * @param buf   register pointing to input byte buffer (byte*)
6880  * @param len   register containing number of bytes
6881  * @param table register that will contain address of CRC table
6882  * @param tmp   scratch register
6883  */
6884 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
6885   assert_different_registers(crc, buf, len, table, tmp, rax);
6886 
6887   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
6888   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
6889 
6890   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
6891   // context for the registers used, where all instructions below are using 128-bit mode
6892   // On EVEX without VL and BW, these instructions will all be AVX.
6893   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
6894   notl(crc); // ~crc
6895   cmpl(len, 16);
6896   jcc(Assembler::less, L_tail);
6897 
6898   // Align buffer to 16 bytes
6899   movl(tmp, buf);
6900   andl(tmp, 0xF);
6901   jccb(Assembler::zero, L_aligned);
6902   subl(tmp,  16);
6903   addl(len, tmp);
6904 
6905   align(4);
6906   BIND(L_align_loop);
6907   movsbl(rax, Address(buf, 0)); // load byte with sign extension
6908   update_byte_crc32(crc, rax, table);
6909   increment(buf);
6910   incrementl(tmp);
6911   jccb(Assembler::less, L_align_loop);
6912 
6913   BIND(L_aligned);
6914   movl(tmp, len); // save
6915   shrl(len, 4);
6916   jcc(Assembler::zero, L_tail_restore);
6917 
6918   // Fold crc into first bytes of vector
6919   movdqa(xmm1, Address(buf, 0));
6920   movdl(rax, xmm1);
6921   xorl(crc, rax);
6922   if (VM_Version::supports_sse4_1()) {
6923     pinsrd(xmm1, crc, 0);
6924   } else {
6925     pinsrw(xmm1, crc, 0);
6926     shrl(crc, 16);
6927     pinsrw(xmm1, crc, 1);
6928   }
6929   addptr(buf, 16);
6930   subl(len, 4); // len > 0
6931   jcc(Assembler::less, L_fold_tail);
6932 
6933   movdqa(xmm2, Address(buf,  0));
6934   movdqa(xmm3, Address(buf, 16));
6935   movdqa(xmm4, Address(buf, 32));
6936   addptr(buf, 48);
6937   subl(len, 3);
6938   jcc(Assembler::lessEqual, L_fold_512b);
6939 
6940   // Fold total 512 bits of polynomial on each iteration,
6941   // 128 bits per each of 4 parallel streams.
6942   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
6943 
6944   align32();
6945   BIND(L_fold_512b_loop);
6946   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
6947   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
6948   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
6949   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
6950   addptr(buf, 64);
6951   subl(len, 4);
6952   jcc(Assembler::greater, L_fold_512b_loop);
6953 
6954   // Fold 512 bits to 128 bits.
6955   BIND(L_fold_512b);
6956   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6957   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
6958   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
6959   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
6960 
6961   // Fold the rest of 128 bits data chunks
6962   BIND(L_fold_tail);
6963   addl(len, 3);
6964   jccb(Assembler::lessEqual, L_fold_128b);
6965   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
6966 
6967   BIND(L_fold_tail_loop);
6968   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
6969   addptr(buf, 16);
6970   decrementl(len);
6971   jccb(Assembler::greater, L_fold_tail_loop);
6972 
6973   // Fold 128 bits in xmm1 down into 32 bits in crc register.
6974   BIND(L_fold_128b);
6975   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
6976   if (UseAVX > 0) {
6977     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
6978     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
6979     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
6980   } else {
6981     movdqa(xmm2, xmm0);
6982     pclmulqdq(xmm2, xmm1, 0x1);
6983     movdqa(xmm3, xmm0);
6984     pand(xmm3, xmm2);
6985     pclmulqdq(xmm0, xmm3, 0x1);
6986   }
6987   psrldq(xmm1, 8);
6988   psrldq(xmm2, 4);
6989   pxor(xmm0, xmm1);
6990   pxor(xmm0, xmm2);
6991 
6992   // 8 8-bit folds to compute 32-bit CRC.
6993   for (int j = 0; j < 4; j++) {
6994     fold_8bit_crc32(xmm0, table, xmm1, rax);
6995   }
6996   movdl(crc, xmm0); // mov 32 bits to general register
6997   for (int j = 0; j < 4; j++) {
6998     fold_8bit_crc32(crc, table, rax);
6999   }
7000 
7001   BIND(L_tail_restore);
7002   movl(len, tmp); // restore
7003   BIND(L_tail);
7004   andl(len, 0xf);
7005   jccb(Assembler::zero, L_exit);
7006 
7007   // Fold the rest of bytes
7008   align(4);
7009   BIND(L_tail_loop);
7010   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7011   update_byte_crc32(crc, rax, table);
7012   increment(buf);
7013   decrementl(len);
7014   jccb(Assembler::greater, L_tail_loop);
7015 
7016   BIND(L_exit);
7017   notl(crc); // ~c
7018 }
7019 
7020 #ifdef _LP64
7021 // Helper function for AVX 512 CRC32
7022 // Fold 512-bit data chunks
7023 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7024                                              Register pos, int offset) {
7025   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7026   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7027   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7028   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7029   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7030 }
7031 
7032 // Helper function for AVX 512 CRC32
7033 // Compute CRC32 for < 256B buffers
7034 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register key, Register pos,
7035                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7036                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7037 
7038   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7039   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7040   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7041 
7042   // check if there is enough buffer to be able to fold 16B at a time
7043   cmpl(len, 32);
7044   jcc(Assembler::less, L_less_than_32);
7045 
7046   // if there is, load the constants
7047   movdqu(xmm10, Address(key, 1 * 16));    //rk1 and rk2 in xmm10
7048   movdl(xmm0, crc);                        // get the initial crc value
7049   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7050   pxor(xmm7, xmm0);
7051 
7052   // update the buffer pointer
7053   addl(pos, 16);
7054   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7055   subl(len, 32);
7056   jmp(L_16B_reduction_loop);
7057 
7058   bind(L_less_than_32);
7059   //mov initial crc to the return value. this is necessary for zero - length buffers.
7060   movl(rax, crc);
7061   testl(len, len);
7062   jcc(Assembler::equal, L_cleanup);
7063 
7064   movdl(xmm0, crc);                        //get the initial crc value
7065 
7066   cmpl(len, 16);
7067   jcc(Assembler::equal, L_exact_16_left);
7068   jcc(Assembler::less, L_less_than_16_left);
7069 
7070   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7071   pxor(xmm7, xmm0);                       //xor the initial crc value
7072   addl(pos, 16);
7073   subl(len, 16);
7074   movdqu(xmm10, Address(key, 1 * 16));    // rk1 and rk2 in xmm10
7075   jmp(L_get_last_two_xmms);
7076 
7077   bind(L_less_than_16_left);
7078   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7079   pxor(xmm1, xmm1);
7080   movptr(tmp1, rsp);
7081   movdqu(Address(tmp1, 0 * 16), xmm1);
7082 
7083   cmpl(len, 4);
7084   jcc(Assembler::less, L_only_less_than_4);
7085 
7086   //backup the counter value
7087   movl(tmp2, len);
7088   cmpl(len, 8);
7089   jcc(Assembler::less, L_less_than_8_left);
7090 
7091   //load 8 Bytes
7092   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7093   movq(Address(tmp1, 0 * 16), rax);
7094   addptr(tmp1, 8);
7095   subl(len, 8);
7096   addl(pos, 8);
7097 
7098   bind(L_less_than_8_left);
7099   cmpl(len, 4);
7100   jcc(Assembler::less, L_less_than_4_left);
7101 
7102   //load 4 Bytes
7103   movl(rax, Address(buf, pos, Address::times_1, 0));
7104   movl(Address(tmp1, 0 * 16), rax);
7105   addptr(tmp1, 4);
7106   subl(len, 4);
7107   addl(pos, 4);
7108 
7109   bind(L_less_than_4_left);
7110   cmpl(len, 2);
7111   jcc(Assembler::less, L_less_than_2_left);
7112 
7113   // load 2 Bytes
7114   movw(rax, Address(buf, pos, Address::times_1, 0));
7115   movl(Address(tmp1, 0 * 16), rax);
7116   addptr(tmp1, 2);
7117   subl(len, 2);
7118   addl(pos, 2);
7119 
7120   bind(L_less_than_2_left);
7121   cmpl(len, 1);
7122   jcc(Assembler::less, L_zero_left);
7123 
7124   // load 1 Byte
7125   movb(rax, Address(buf, pos, Address::times_1, 0));
7126   movb(Address(tmp1, 0 * 16), rax);
7127 
7128   bind(L_zero_left);
7129   movdqu(xmm7, Address(rsp, 0));
7130   pxor(xmm7, xmm0);                       //xor the initial crc value
7131 
7132   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7133   movdqu(xmm0, Address(rax, tmp2));
7134   pshufb(xmm7, xmm0);
7135   jmp(L_128_done);
7136 
7137   bind(L_exact_16_left);
7138   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7139   pxor(xmm7, xmm0);                       //xor the initial crc value
7140   jmp(L_128_done);
7141 
7142   bind(L_only_less_than_4);
7143   cmpl(len, 3);
7144   jcc(Assembler::less, L_only_less_than_3);
7145 
7146   // load 3 Bytes
7147   movb(rax, Address(buf, pos, Address::times_1, 0));
7148   movb(Address(tmp1, 0), rax);
7149 
7150   movb(rax, Address(buf, pos, Address::times_1, 1));
7151   movb(Address(tmp1, 1), rax);
7152 
7153   movb(rax, Address(buf, pos, Address::times_1, 2));
7154   movb(Address(tmp1, 2), rax);
7155 
7156   movdqu(xmm7, Address(rsp, 0));
7157   pxor(xmm7, xmm0);                     //xor the initial crc value
7158 
7159   pslldq(xmm7, 0x5);
7160   jmp(L_barrett);
7161   bind(L_only_less_than_3);
7162   cmpl(len, 2);
7163   jcc(Assembler::less, L_only_less_than_2);
7164 
7165   // load 2 Bytes
7166   movb(rax, Address(buf, pos, Address::times_1, 0));
7167   movb(Address(tmp1, 0), rax);
7168 
7169   movb(rax, Address(buf, pos, Address::times_1, 1));
7170   movb(Address(tmp1, 1), rax);
7171 
7172   movdqu(xmm7, Address(rsp, 0));
7173   pxor(xmm7, xmm0);                     //xor the initial crc value
7174 
7175   pslldq(xmm7, 0x6);
7176   jmp(L_barrett);
7177 
7178   bind(L_only_less_than_2);
7179   //load 1 Byte
7180   movb(rax, Address(buf, pos, Address::times_1, 0));
7181   movb(Address(tmp1, 0), rax);
7182 
7183   movdqu(xmm7, Address(rsp, 0));
7184   pxor(xmm7, xmm0);                     //xor the initial crc value
7185 
7186   pslldq(xmm7, 0x7);
7187 }
7188 
7189 /**
7190 * Compute CRC32 using AVX512 instructions
7191 * param crc   register containing existing CRC (32-bit)
7192 * param buf   register pointing to input byte buffer (byte*)
7193 * param len   register containing number of bytes
7194 * param tmp1  scratch register
7195 * param tmp2  scratch register
7196 * return rax  result register
7197 */
7198 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register key, Register tmp1, Register tmp2) {
7199   assert_different_registers(crc, buf, len, key, tmp1, tmp2, rax);
7200 
7201   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7202   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7203   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7204   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7205   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7206 
7207   const Register pos = r12;
7208   push(r12);
7209   subptr(rsp, 16 * 2 + 8);
7210 
7211   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7212   // context for the registers used, where all instructions below are using 128-bit mode
7213   // On EVEX without VL and BW, these instructions will all be AVX.
7214   lea(key, ExternalAddress(StubRoutines::x86::crc_table_avx512_addr()));
7215   notl(crc);
7216   movl(pos, 0);
7217 
7218   // check if smaller than 256B
7219   cmpl(len, 256);
7220   jcc(Assembler::less, L_less_than_256);
7221 
7222   // load the initial crc value
7223   movdl(xmm10, crc);
7224 
7225   // receive the initial 64B data, xor the initial crc value
7226   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7227   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7228   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7229   evbroadcasti32x4(xmm10, Address(key, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7230 
7231   subl(len, 256);
7232   cmpl(len, 256);
7233   jcc(Assembler::less, L_fold_128_B_loop);
7234 
7235   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7236   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7237   evbroadcasti32x4(xmm16, Address(key, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7238   subl(len, 256);
7239 
7240   bind(L_fold_256_B_loop);
7241   addl(pos, 256);
7242   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7243   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7244   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7245   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7246 
7247   subl(len, 256);
7248   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7249 
7250   // Fold 256 into 128
7251   addl(pos, 256);
7252   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7253   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7254   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7255 
7256   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7257   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7258   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7259 
7260   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7261   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7262 
7263   addl(len, 128);
7264   jmp(L_fold_128_B_register);
7265 
7266   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7267   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7268 
7269   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7270   bind(L_fold_128_B_loop);
7271   addl(pos, 128);
7272   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7273   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7274 
7275   subl(len, 128);
7276   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7277 
7278   addl(pos, 128);
7279 
7280   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7281   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7282   bind(L_fold_128_B_register);
7283   evmovdquq(xmm16, Address(key, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7284   evmovdquq(xmm11, Address(key, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7285   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7286   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7287   // save last that has no multiplicand
7288   vextracti64x2(xmm7, xmm4, 3);
7289 
7290   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7291   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7292   // Needed later in reduction loop
7293   movdqu(xmm10, Address(key, 1 * 16));
7294   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7295   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7296 
7297   // Swap 1,0,3,2 - 01 00 11 10
7298   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7299   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7300   vextracti128(xmm5, xmm8, 1);
7301   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7302 
7303   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7304   // instead of a cmp instruction, we use the negative flag with the jl instruction
7305   addl(len, 128 - 16);
7306   jcc(Assembler::less, L_final_reduction_for_128);
7307 
7308   bind(L_16B_reduction_loop);
7309   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7310   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7311   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7312   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7313   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7314   addl(pos, 16);
7315   subl(len, 16);
7316   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7317 
7318   bind(L_final_reduction_for_128);
7319   addl(len, 16);
7320   jcc(Assembler::equal, L_128_done);
7321 
7322   bind(L_get_last_two_xmms);
7323   movdqu(xmm2, xmm7);
7324   addl(pos, len);
7325   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7326   subl(pos, len);
7327 
7328   // get rid of the extra data that was loaded before
7329   // load the shift constant
7330   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7331   movdqu(xmm0, Address(rax, len));
7332   addl(rax, len);
7333 
7334   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7335   //Change mask to 512
7336   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
7337   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
7338 
7339   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
7340   vpclmulqdq(xmm8, xmm7, xmm10, 0x1);
7341   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7342   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7343   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
7344 
7345   bind(L_128_done);
7346   // compute crc of a 128-bit value
7347   movdqu(xmm10, Address(key, 3 * 16));
7348   movdqu(xmm0, xmm7);
7349 
7350   // 64b fold
7351   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
7352   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
7353   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7354 
7355   // 32b fold
7356   movdqu(xmm0, xmm7);
7357   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
7358   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7359   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7360   jmp(L_barrett);
7361 
7362   bind(L_less_than_256);
7363   kernel_crc32_avx512_256B(crc, buf, len, key, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
7364 
7365   //barrett reduction
7366   bind(L_barrett);
7367   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
7368   movdqu(xmm1, xmm7);
7369   movdqu(xmm2, xmm7);
7370   movdqu(xmm10, Address(key, 4 * 16));
7371 
7372   pclmulqdq(xmm7, xmm10, 0x0);
7373   pxor(xmm7, xmm2);
7374   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
7375   movdqu(xmm2, xmm7);
7376   pclmulqdq(xmm7, xmm10, 0x10);
7377   pxor(xmm7, xmm2);
7378   pxor(xmm7, xmm1);
7379   pextrd(crc, xmm7, 2);
7380 
7381   bind(L_cleanup);
7382   notl(crc); // ~c
7383   addptr(rsp, 16 * 2 + 8);
7384   pop(r12);
7385 }
7386 
7387 // S. Gueron / Information Processing Letters 112 (2012) 184
7388 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
7389 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
7390 // Output: the 64-bit carry-less product of B * CONST
7391 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
7392                                      Register tmp1, Register tmp2, Register tmp3) {
7393   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7394   if (n > 0) {
7395     addq(tmp3, n * 256 * 8);
7396   }
7397   //    Q1 = TABLEExt[n][B & 0xFF];
7398   movl(tmp1, in);
7399   andl(tmp1, 0x000000FF);
7400   shll(tmp1, 3);
7401   addq(tmp1, tmp3);
7402   movq(tmp1, Address(tmp1, 0));
7403 
7404   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7405   movl(tmp2, in);
7406   shrl(tmp2, 8);
7407   andl(tmp2, 0x000000FF);
7408   shll(tmp2, 3);
7409   addq(tmp2, tmp3);
7410   movq(tmp2, Address(tmp2, 0));
7411 
7412   shlq(tmp2, 8);
7413   xorq(tmp1, tmp2);
7414 
7415   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7416   movl(tmp2, in);
7417   shrl(tmp2, 16);
7418   andl(tmp2, 0x000000FF);
7419   shll(tmp2, 3);
7420   addq(tmp2, tmp3);
7421   movq(tmp2, Address(tmp2, 0));
7422 
7423   shlq(tmp2, 16);
7424   xorq(tmp1, tmp2);
7425 
7426   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7427   shrl(in, 24);
7428   andl(in, 0x000000FF);
7429   shll(in, 3);
7430   addq(in, tmp3);
7431   movq(in, Address(in, 0));
7432 
7433   shlq(in, 24);
7434   xorq(in, tmp1);
7435   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7436 }
7437 
7438 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7439                                       Register in_out,
7440                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7441                                       XMMRegister w_xtmp2,
7442                                       Register tmp1,
7443                                       Register n_tmp2, Register n_tmp3) {
7444   if (is_pclmulqdq_supported) {
7445     movdl(w_xtmp1, in_out); // modified blindly
7446 
7447     movl(tmp1, const_or_pre_comp_const_index);
7448     movdl(w_xtmp2, tmp1);
7449     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7450 
7451     movdq(in_out, w_xtmp1);
7452   } else {
7453     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
7454   }
7455 }
7456 
7457 // Recombination Alternative 2: No bit-reflections
7458 // T1 = (CRC_A * U1) << 1
7459 // T2 = (CRC_B * U2) << 1
7460 // C1 = T1 >> 32
7461 // C2 = T2 >> 32
7462 // T1 = T1 & 0xFFFFFFFF
7463 // T2 = T2 & 0xFFFFFFFF
7464 // T1 = CRC32(0, T1)
7465 // T2 = CRC32(0, T2)
7466 // C1 = C1 ^ T1
7467 // C2 = C2 ^ T2
7468 // CRC = C1 ^ C2 ^ CRC_C
7469 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7470                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7471                                      Register tmp1, Register tmp2,
7472                                      Register n_tmp3) {
7473   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7474   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7475   shlq(in_out, 1);
7476   movl(tmp1, in_out);
7477   shrq(in_out, 32);
7478   xorl(tmp2, tmp2);
7479   crc32(tmp2, tmp1, 4);
7480   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
7481   shlq(in1, 1);
7482   movl(tmp1, in1);
7483   shrq(in1, 32);
7484   xorl(tmp2, tmp2);
7485   crc32(tmp2, tmp1, 4);
7486   xorl(in1, tmp2);
7487   xorl(in_out, in1);
7488   xorl(in_out, in2);
7489 }
7490 
7491 // Set N to predefined value
7492 // Subtract from a lenght of a buffer
7493 // execute in a loop:
7494 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
7495 // for i = 1 to N do
7496 //  CRC_A = CRC32(CRC_A, A[i])
7497 //  CRC_B = CRC32(CRC_B, B[i])
7498 //  CRC_C = CRC32(CRC_C, C[i])
7499 // end for
7500 // Recombine
7501 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7502                                        Register in_out1, Register in_out2, Register in_out3,
7503                                        Register tmp1, Register tmp2, Register tmp3,
7504                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7505                                        Register tmp4, Register tmp5,
7506                                        Register n_tmp6) {
7507   Label L_processPartitions;
7508   Label L_processPartition;
7509   Label L_exit;
7510 
7511   bind(L_processPartitions);
7512   cmpl(in_out1, 3 * size);
7513   jcc(Assembler::less, L_exit);
7514     xorl(tmp1, tmp1);
7515     xorl(tmp2, tmp2);
7516     movq(tmp3, in_out2);
7517     addq(tmp3, size);
7518 
7519     bind(L_processPartition);
7520       crc32(in_out3, Address(in_out2, 0), 8);
7521       crc32(tmp1, Address(in_out2, size), 8);
7522       crc32(tmp2, Address(in_out2, size * 2), 8);
7523       addq(in_out2, 8);
7524       cmpq(in_out2, tmp3);
7525       jcc(Assembler::less, L_processPartition);
7526     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7527             w_xtmp1, w_xtmp2, w_xtmp3,
7528             tmp4, tmp5,
7529             n_tmp6);
7530     addq(in_out2, 2 * size);
7531     subl(in_out1, 3 * size);
7532     jmp(L_processPartitions);
7533 
7534   bind(L_exit);
7535 }
7536 #else
7537 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
7538                                      Register tmp1, Register tmp2, Register tmp3,
7539                                      XMMRegister xtmp1, XMMRegister xtmp2) {
7540   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7541   if (n > 0) {
7542     addl(tmp3, n * 256 * 8);
7543   }
7544   //    Q1 = TABLEExt[n][B & 0xFF];
7545   movl(tmp1, in_out);
7546   andl(tmp1, 0x000000FF);
7547   shll(tmp1, 3);
7548   addl(tmp1, tmp3);
7549   movq(xtmp1, Address(tmp1, 0));
7550 
7551   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7552   movl(tmp2, in_out);
7553   shrl(tmp2, 8);
7554   andl(tmp2, 0x000000FF);
7555   shll(tmp2, 3);
7556   addl(tmp2, tmp3);
7557   movq(xtmp2, Address(tmp2, 0));
7558 
7559   psllq(xtmp2, 8);
7560   pxor(xtmp1, xtmp2);
7561 
7562   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7563   movl(tmp2, in_out);
7564   shrl(tmp2, 16);
7565   andl(tmp2, 0x000000FF);
7566   shll(tmp2, 3);
7567   addl(tmp2, tmp3);
7568   movq(xtmp2, Address(tmp2, 0));
7569 
7570   psllq(xtmp2, 16);
7571   pxor(xtmp1, xtmp2);
7572 
7573   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7574   shrl(in_out, 24);
7575   andl(in_out, 0x000000FF);
7576   shll(in_out, 3);
7577   addl(in_out, tmp3);
7578   movq(xtmp2, Address(in_out, 0));
7579 
7580   psllq(xtmp2, 24);
7581   pxor(xtmp1, xtmp2); // Result in CXMM
7582   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7583 }
7584 
7585 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7586                                       Register in_out,
7587                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7588                                       XMMRegister w_xtmp2,
7589                                       Register tmp1,
7590                                       Register n_tmp2, Register n_tmp3) {
7591   if (is_pclmulqdq_supported) {
7592     movdl(w_xtmp1, in_out);
7593 
7594     movl(tmp1, const_or_pre_comp_const_index);
7595     movdl(w_xtmp2, tmp1);
7596     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7597     // Keep result in XMM since GPR is 32 bit in length
7598   } else {
7599     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
7600   }
7601 }
7602 
7603 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7604                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7605                                      Register tmp1, Register tmp2,
7606                                      Register n_tmp3) {
7607   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7608   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7609 
7610   psllq(w_xtmp1, 1);
7611   movdl(tmp1, w_xtmp1);
7612   psrlq(w_xtmp1, 32);
7613   movdl(in_out, w_xtmp1);
7614 
7615   xorl(tmp2, tmp2);
7616   crc32(tmp2, tmp1, 4);
7617   xorl(in_out, tmp2);
7618 
7619   psllq(w_xtmp2, 1);
7620   movdl(tmp1, w_xtmp2);
7621   psrlq(w_xtmp2, 32);
7622   movdl(in1, w_xtmp2);
7623 
7624   xorl(tmp2, tmp2);
7625   crc32(tmp2, tmp1, 4);
7626   xorl(in1, tmp2);
7627   xorl(in_out, in1);
7628   xorl(in_out, in2);
7629 }
7630 
7631 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7632                                        Register in_out1, Register in_out2, Register in_out3,
7633                                        Register tmp1, Register tmp2, Register tmp3,
7634                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7635                                        Register tmp4, Register tmp5,
7636                                        Register n_tmp6) {
7637   Label L_processPartitions;
7638   Label L_processPartition;
7639   Label L_exit;
7640 
7641   bind(L_processPartitions);
7642   cmpl(in_out1, 3 * size);
7643   jcc(Assembler::less, L_exit);
7644     xorl(tmp1, tmp1);
7645     xorl(tmp2, tmp2);
7646     movl(tmp3, in_out2);
7647     addl(tmp3, size);
7648 
7649     bind(L_processPartition);
7650       crc32(in_out3, Address(in_out2, 0), 4);
7651       crc32(tmp1, Address(in_out2, size), 4);
7652       crc32(tmp2, Address(in_out2, size*2), 4);
7653       crc32(in_out3, Address(in_out2, 0+4), 4);
7654       crc32(tmp1, Address(in_out2, size+4), 4);
7655       crc32(tmp2, Address(in_out2, size*2+4), 4);
7656       addl(in_out2, 8);
7657       cmpl(in_out2, tmp3);
7658       jcc(Assembler::less, L_processPartition);
7659 
7660         push(tmp3);
7661         push(in_out1);
7662         push(in_out2);
7663         tmp4 = tmp3;
7664         tmp5 = in_out1;
7665         n_tmp6 = in_out2;
7666 
7667       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7668             w_xtmp1, w_xtmp2, w_xtmp3,
7669             tmp4, tmp5,
7670             n_tmp6);
7671 
7672         pop(in_out2);
7673         pop(in_out1);
7674         pop(tmp3);
7675 
7676     addl(in_out2, 2 * size);
7677     subl(in_out1, 3 * size);
7678     jmp(L_processPartitions);
7679 
7680   bind(L_exit);
7681 }
7682 #endif //LP64
7683 
7684 #ifdef _LP64
7685 // Algorithm 2: Pipelined usage of the CRC32 instruction.
7686 // Input: A buffer I of L bytes.
7687 // Output: the CRC32C value of the buffer.
7688 // Notations:
7689 // Write L = 24N + r, with N = floor (L/24).
7690 // r = L mod 24 (0 <= r < 24).
7691 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
7692 // N quadwords, and R consists of r bytes.
7693 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
7694 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
7695 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
7696 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
7697 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7698                                           Register tmp1, Register tmp2, Register tmp3,
7699                                           Register tmp4, Register tmp5, Register tmp6,
7700                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7701                                           bool is_pclmulqdq_supported) {
7702   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7703   Label L_wordByWord;
7704   Label L_byteByByteProlog;
7705   Label L_byteByByte;
7706   Label L_exit;
7707 
7708   if (is_pclmulqdq_supported ) {
7709     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7710     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
7711 
7712     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7713     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7714 
7715     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7716     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7717     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
7718   } else {
7719     const_or_pre_comp_const_index[0] = 1;
7720     const_or_pre_comp_const_index[1] = 0;
7721 
7722     const_or_pre_comp_const_index[2] = 3;
7723     const_or_pre_comp_const_index[3] = 2;
7724 
7725     const_or_pre_comp_const_index[4] = 5;
7726     const_or_pre_comp_const_index[5] = 4;
7727    }
7728   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7729                     in2, in1, in_out,
7730                     tmp1, tmp2, tmp3,
7731                     w_xtmp1, w_xtmp2, w_xtmp3,
7732                     tmp4, tmp5,
7733                     tmp6);
7734   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7735                     in2, in1, in_out,
7736                     tmp1, tmp2, tmp3,
7737                     w_xtmp1, w_xtmp2, w_xtmp3,
7738                     tmp4, tmp5,
7739                     tmp6);
7740   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7741                     in2, in1, in_out,
7742                     tmp1, tmp2, tmp3,
7743                     w_xtmp1, w_xtmp2, w_xtmp3,
7744                     tmp4, tmp5,
7745                     tmp6);
7746   movl(tmp1, in2);
7747   andl(tmp1, 0x00000007);
7748   negl(tmp1);
7749   addl(tmp1, in2);
7750   addq(tmp1, in1);
7751 
7752   BIND(L_wordByWord);
7753   cmpq(in1, tmp1);
7754   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7755     crc32(in_out, Address(in1, 0), 4);
7756     addq(in1, 4);
7757     jmp(L_wordByWord);
7758 
7759   BIND(L_byteByByteProlog);
7760   andl(in2, 0x00000007);
7761   movl(tmp2, 1);
7762 
7763   BIND(L_byteByByte);
7764   cmpl(tmp2, in2);
7765   jccb(Assembler::greater, L_exit);
7766     crc32(in_out, Address(in1, 0), 1);
7767     incq(in1);
7768     incl(tmp2);
7769     jmp(L_byteByByte);
7770 
7771   BIND(L_exit);
7772 }
7773 #else
7774 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7775                                           Register tmp1, Register  tmp2, Register tmp3,
7776                                           Register tmp4, Register  tmp5, Register tmp6,
7777                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7778                                           bool is_pclmulqdq_supported) {
7779   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7780   Label L_wordByWord;
7781   Label L_byteByByteProlog;
7782   Label L_byteByByte;
7783   Label L_exit;
7784 
7785   if (is_pclmulqdq_supported) {
7786     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7787     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
7788 
7789     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7790     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7791 
7792     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7793     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7794   } else {
7795     const_or_pre_comp_const_index[0] = 1;
7796     const_or_pre_comp_const_index[1] = 0;
7797 
7798     const_or_pre_comp_const_index[2] = 3;
7799     const_or_pre_comp_const_index[3] = 2;
7800 
7801     const_or_pre_comp_const_index[4] = 5;
7802     const_or_pre_comp_const_index[5] = 4;
7803   }
7804   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7805                     in2, in1, in_out,
7806                     tmp1, tmp2, tmp3,
7807                     w_xtmp1, w_xtmp2, w_xtmp3,
7808                     tmp4, tmp5,
7809                     tmp6);
7810   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7811                     in2, in1, in_out,
7812                     tmp1, tmp2, tmp3,
7813                     w_xtmp1, w_xtmp2, w_xtmp3,
7814                     tmp4, tmp5,
7815                     tmp6);
7816   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7817                     in2, in1, in_out,
7818                     tmp1, tmp2, tmp3,
7819                     w_xtmp1, w_xtmp2, w_xtmp3,
7820                     tmp4, tmp5,
7821                     tmp6);
7822   movl(tmp1, in2);
7823   andl(tmp1, 0x00000007);
7824   negl(tmp1);
7825   addl(tmp1, in2);
7826   addl(tmp1, in1);
7827 
7828   BIND(L_wordByWord);
7829   cmpl(in1, tmp1);
7830   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7831     crc32(in_out, Address(in1,0), 4);
7832     addl(in1, 4);
7833     jmp(L_wordByWord);
7834 
7835   BIND(L_byteByByteProlog);
7836   andl(in2, 0x00000007);
7837   movl(tmp2, 1);
7838 
7839   BIND(L_byteByByte);
7840   cmpl(tmp2, in2);
7841   jccb(Assembler::greater, L_exit);
7842     movb(tmp1, Address(in1, 0));
7843     crc32(in_out, tmp1, 1);
7844     incl(in1);
7845     incl(tmp2);
7846     jmp(L_byteByByte);
7847 
7848   BIND(L_exit);
7849 }
7850 #endif // LP64
7851 #undef BIND
7852 #undef BLOCK_COMMENT
7853 
7854 // Compress char[] array to byte[].
7855 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
7856 //   @IntrinsicCandidate
7857 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
7858 //     for (int i = 0; i < len; i++) {
7859 //       int c = src[srcOff++];
7860 //       if (c >>> 8 != 0) {
7861 //         return 0;
7862 //       }
7863 //       dst[dstOff++] = (byte)c;
7864 //     }
7865 //     return len;
7866 //   }
7867 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
7868   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
7869   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
7870   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
7871   Label copy_chars_loop, return_length, return_zero, done;
7872 
7873   // rsi: src
7874   // rdi: dst
7875   // rdx: len
7876   // rcx: tmp5
7877   // rax: result
7878 
7879   // rsi holds start addr of source char[] to be compressed
7880   // rdi holds start addr of destination byte[]
7881   // rdx holds length
7882 
7883   assert(len != result, "");
7884 
7885   // save length for return
7886   push(len);
7887 
7888   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
7889     VM_Version::supports_avx512vlbw() &&
7890     VM_Version::supports_bmi2()) {
7891 
7892     Label copy_32_loop, copy_loop_tail, below_threshold;
7893 
7894     // alignment
7895     Label post_alignment;
7896 
7897     // if length of the string is less than 16, handle it in an old fashioned way
7898     testl(len, -32);
7899     jcc(Assembler::zero, below_threshold);
7900 
7901     // First check whether a character is compressable ( <= 0xFF).
7902     // Create mask to test for Unicode chars inside zmm vector
7903     movl(result, 0x00FF);
7904     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
7905 
7906     testl(len, -64);
7907     jcc(Assembler::zero, post_alignment);
7908 
7909     movl(tmp5, dst);
7910     andl(tmp5, (32 - 1));
7911     negl(tmp5);
7912     andl(tmp5, (32 - 1));
7913 
7914     // bail out when there is nothing to be done
7915     testl(tmp5, 0xFFFFFFFF);
7916     jcc(Assembler::zero, post_alignment);
7917 
7918     // ~(~0 << len), where len is the # of remaining elements to process
7919     movl(result, 0xFFFFFFFF);
7920     shlxl(result, result, tmp5);
7921     notl(result);
7922     kmovdl(mask2, result);
7923 
7924     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
7925     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
7926     ktestd(mask1, mask2);
7927     jcc(Assembler::carryClear, return_zero);
7928 
7929     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
7930 
7931     addptr(src, tmp5);
7932     addptr(src, tmp5);
7933     addptr(dst, tmp5);
7934     subl(len, tmp5);
7935 
7936     bind(post_alignment);
7937     // end of alignment
7938 
7939     movl(tmp5, len);
7940     andl(tmp5, (32 - 1));    // tail count (in chars)
7941     andl(len, ~(32 - 1));    // vector count (in chars)
7942     jcc(Assembler::zero, copy_loop_tail);
7943 
7944     lea(src, Address(src, len, Address::times_2));
7945     lea(dst, Address(dst, len, Address::times_1));
7946     negptr(len);
7947 
7948     bind(copy_32_loop);
7949     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
7950     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
7951     kortestdl(mask1, mask1);
7952     jcc(Assembler::carryClear, return_zero);
7953 
7954     // All elements in current processed chunk are valid candidates for
7955     // compression. Write a truncated byte elements to the memory.
7956     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
7957     addptr(len, 32);
7958     jcc(Assembler::notZero, copy_32_loop);
7959 
7960     bind(copy_loop_tail);
7961     // bail out when there is nothing to be done
7962     testl(tmp5, 0xFFFFFFFF);
7963     jcc(Assembler::zero, return_length);
7964 
7965     movl(len, tmp5);
7966 
7967     // ~(~0 << len), where len is the # of remaining elements to process
7968     movl(result, 0xFFFFFFFF);
7969     shlxl(result, result, len);
7970     notl(result);
7971 
7972     kmovdl(mask2, result);
7973 
7974     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
7975     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
7976     ktestd(mask1, mask2);
7977     jcc(Assembler::carryClear, return_zero);
7978 
7979     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
7980     jmp(return_length);
7981 
7982     bind(below_threshold);
7983   }
7984 
7985   if (UseSSE42Intrinsics) {
7986     Label copy_32_loop, copy_16, copy_tail;
7987 
7988     movl(result, len);
7989 
7990     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
7991 
7992     // vectored compression
7993     andl(len, 0xfffffff0);    // vector count (in chars)
7994     andl(result, 0x0000000f);    // tail count (in chars)
7995     testl(len, len);
7996     jcc(Assembler::zero, copy_16);
7997 
7998     // compress 16 chars per iter
7999     movdl(tmp1Reg, tmp5);
8000     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8001     pxor(tmp4Reg, tmp4Reg);
8002 
8003     lea(src, Address(src, len, Address::times_2));
8004     lea(dst, Address(dst, len, Address::times_1));
8005     negptr(len);
8006 
8007     bind(copy_32_loop);
8008     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
8009     por(tmp4Reg, tmp2Reg);
8010     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8011     por(tmp4Reg, tmp3Reg);
8012     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
8013     jcc(Assembler::notZero, return_zero);
8014     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
8015     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8016     addptr(len, 16);
8017     jcc(Assembler::notZero, copy_32_loop);
8018 
8019     // compress next vector of 8 chars (if any)
8020     bind(copy_16);
8021     movl(len, result);
8022     andl(len, 0xfffffff8);    // vector count (in chars)
8023     andl(result, 0x00000007);    // tail count (in chars)
8024     testl(len, len);
8025     jccb(Assembler::zero, copy_tail);
8026 
8027     movdl(tmp1Reg, tmp5);
8028     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8029     pxor(tmp3Reg, tmp3Reg);
8030 
8031     movdqu(tmp2Reg, Address(src, 0));
8032     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
8033     jccb(Assembler::notZero, return_zero);
8034     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
8035     movq(Address(dst, 0), tmp2Reg);
8036     addptr(src, 16);
8037     addptr(dst, 8);
8038 
8039     bind(copy_tail);
8040     movl(len, result);
8041   }
8042   // compress 1 char per iter
8043   testl(len, len);
8044   jccb(Assembler::zero, return_length);
8045   lea(src, Address(src, len, Address::times_2));
8046   lea(dst, Address(dst, len, Address::times_1));
8047   negptr(len);
8048 
8049   bind(copy_chars_loop);
8050   load_unsigned_short(result, Address(src, len, Address::times_2));
8051   testl(result, 0xff00);      // check if Unicode char
8052   jccb(Assembler::notZero, return_zero);
8053   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
8054   increment(len);
8055   jcc(Assembler::notZero, copy_chars_loop);
8056 
8057   // if compression succeeded, return length
8058   bind(return_length);
8059   pop(result);
8060   jmpb(done);
8061 
8062   // if compression failed, return 0
8063   bind(return_zero);
8064   xorl(result, result);
8065   addptr(rsp, wordSize);
8066 
8067   bind(done);
8068 }
8069 
8070 // Inflate byte[] array to char[].
8071 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8072 //   @IntrinsicCandidate
8073 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8074 //     for (int i = 0; i < len; i++) {
8075 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8076 //     }
8077 //   }
8078 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8079   XMMRegister tmp1, Register tmp2, KRegister mask) {
8080   Label copy_chars_loop, done, below_threshold, avx3_threshold;
8081   // rsi: src
8082   // rdi: dst
8083   // rdx: len
8084   // rcx: tmp2
8085 
8086   // rsi holds start addr of source byte[] to be inflated
8087   // rdi holds start addr of destination char[]
8088   // rdx holds length
8089   assert_different_registers(src, dst, len, tmp2);
8090   movl(tmp2, len);
8091   if ((UseAVX > 2) && // AVX512
8092     VM_Version::supports_avx512vlbw() &&
8093     VM_Version::supports_bmi2()) {
8094 
8095     Label copy_32_loop, copy_tail;
8096     Register tmp3_aliased = len;
8097 
8098     // if length of the string is less than 16, handle it in an old fashioned way
8099     testl(len, -16);
8100     jcc(Assembler::zero, below_threshold);
8101 
8102     testl(len, -1 * AVX3Threshold);
8103     jcc(Assembler::zero, avx3_threshold);
8104 
8105     // In order to use only one arithmetic operation for the main loop we use
8106     // this pre-calculation
8107     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8108     andl(len, -32);     // vector count
8109     jccb(Assembler::zero, copy_tail);
8110 
8111     lea(src, Address(src, len, Address::times_1));
8112     lea(dst, Address(dst, len, Address::times_2));
8113     negptr(len);
8114 
8115 
8116     // inflate 32 chars per iter
8117     bind(copy_32_loop);
8118     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8119     evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8120     addptr(len, 32);
8121     jcc(Assembler::notZero, copy_32_loop);
8122 
8123     bind(copy_tail);
8124     // bail out when there is nothing to be done
8125     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8126     jcc(Assembler::zero, done);
8127 
8128     // ~(~0 << length), where length is the # of remaining elements to process
8129     movl(tmp3_aliased, -1);
8130     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8131     notl(tmp3_aliased);
8132     kmovdl(mask, tmp3_aliased);
8133     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8134     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8135 
8136     jmp(done);
8137     bind(avx3_threshold);
8138   }
8139   if (UseSSE42Intrinsics) {
8140     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8141 
8142     if (UseAVX > 1) {
8143       andl(tmp2, (16 - 1));
8144       andl(len, -16);
8145       jccb(Assembler::zero, copy_new_tail);
8146     } else {
8147       andl(tmp2, 0x00000007);   // tail count (in chars)
8148       andl(len, 0xfffffff8);    // vector count (in chars)
8149       jccb(Assembler::zero, copy_tail);
8150     }
8151 
8152     // vectored inflation
8153     lea(src, Address(src, len, Address::times_1));
8154     lea(dst, Address(dst, len, Address::times_2));
8155     negptr(len);
8156 
8157     if (UseAVX > 1) {
8158       bind(copy_16_loop);
8159       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8160       vmovdqu(Address(dst, len, Address::times_2), tmp1);
8161       addptr(len, 16);
8162       jcc(Assembler::notZero, copy_16_loop);
8163 
8164       bind(below_threshold);
8165       bind(copy_new_tail);
8166       movl(len, tmp2);
8167       andl(tmp2, 0x00000007);
8168       andl(len, 0xFFFFFFF8);
8169       jccb(Assembler::zero, copy_tail);
8170 
8171       pmovzxbw(tmp1, Address(src, 0));
8172       movdqu(Address(dst, 0), tmp1);
8173       addptr(src, 8);
8174       addptr(dst, 2 * 8);
8175 
8176       jmp(copy_tail, true);
8177     }
8178 
8179     // inflate 8 chars per iter
8180     bind(copy_8_loop);
8181     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
8182     movdqu(Address(dst, len, Address::times_2), tmp1);
8183     addptr(len, 8);
8184     jcc(Assembler::notZero, copy_8_loop);
8185 
8186     bind(copy_tail);
8187     movl(len, tmp2);
8188 
8189     cmpl(len, 4);
8190     jccb(Assembler::less, copy_bytes);
8191 
8192     movdl(tmp1, Address(src, 0));  // load 4 byte chars
8193     pmovzxbw(tmp1, tmp1);
8194     movq(Address(dst, 0), tmp1);
8195     subptr(len, 4);
8196     addptr(src, 4);
8197     addptr(dst, 8);
8198 
8199     bind(copy_bytes);
8200   } else {
8201     bind(below_threshold);
8202   }
8203 
8204   testl(len, len);
8205   jccb(Assembler::zero, done);
8206   lea(src, Address(src, len, Address::times_1));
8207   lea(dst, Address(dst, len, Address::times_2));
8208   negptr(len);
8209 
8210   // inflate 1 char per iter
8211   bind(copy_chars_loop);
8212   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
8213   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
8214   increment(len);
8215   jcc(Assembler::notZero, copy_chars_loop);
8216 
8217   bind(done);
8218 }
8219 
8220 
8221 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8222   switch(type) {
8223     case T_BYTE:
8224     case T_BOOLEAN:
8225       evmovdqub(dst, kmask, src, false, vector_len);
8226       break;
8227     case T_CHAR:
8228     case T_SHORT:
8229       evmovdquw(dst, kmask, src, false, vector_len);
8230       break;
8231     case T_INT:
8232     case T_FLOAT:
8233       evmovdqul(dst, kmask, src, false, vector_len);
8234       break;
8235     case T_LONG:
8236     case T_DOUBLE:
8237       evmovdquq(dst, kmask, src, false, vector_len);
8238       break;
8239     default:
8240       fatal("Unexpected type argument %s", type2name(type));
8241       break;
8242   }
8243 }
8244 
8245 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8246   switch(type) {
8247     case T_BYTE:
8248     case T_BOOLEAN:
8249       evmovdqub(dst, kmask, src, true, vector_len);
8250       break;
8251     case T_CHAR:
8252     case T_SHORT:
8253       evmovdquw(dst, kmask, src, true, vector_len);
8254       break;
8255     case T_INT:
8256     case T_FLOAT:
8257       evmovdqul(dst, kmask, src, true, vector_len);
8258       break;
8259     case T_LONG:
8260     case T_DOUBLE:
8261       evmovdquq(dst, kmask, src, true, vector_len);
8262       break;
8263     default:
8264       fatal("Unexpected type argument %s", type2name(type));
8265       break;
8266   }
8267 }
8268 
8269 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8270   switch(masklen) {
8271     case 2:
8272        knotbl(dst, src);
8273        movl(rtmp, 3);
8274        kmovbl(ktmp, rtmp);
8275        kandbl(dst, ktmp, dst);
8276        break;
8277     case 4:
8278        knotbl(dst, src);
8279        movl(rtmp, 15);
8280        kmovbl(ktmp, rtmp);
8281        kandbl(dst, ktmp, dst);
8282        break;
8283     case 8:
8284        knotbl(dst, src);
8285        break;
8286     case 16:
8287        knotwl(dst, src);
8288        break;
8289     case 32:
8290        knotdl(dst, src);
8291        break;
8292     case 64:
8293        knotql(dst, src);
8294        break;
8295     default:
8296       fatal("Unexpected vector length %d", masklen);
8297       break;
8298   }
8299 }
8300 
8301 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8302   switch(type) {
8303     case T_BOOLEAN:
8304     case T_BYTE:
8305        kandbl(dst, src1, src2);
8306        break;
8307     case T_CHAR:
8308     case T_SHORT:
8309        kandwl(dst, src1, src2);
8310        break;
8311     case T_INT:
8312     case T_FLOAT:
8313        kanddl(dst, src1, src2);
8314        break;
8315     case T_LONG:
8316     case T_DOUBLE:
8317        kandql(dst, src1, src2);
8318        break;
8319     default:
8320       fatal("Unexpected type argument %s", type2name(type));
8321       break;
8322   }
8323 }
8324 
8325 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8326   switch(type) {
8327     case T_BOOLEAN:
8328     case T_BYTE:
8329        korbl(dst, src1, src2);
8330        break;
8331     case T_CHAR:
8332     case T_SHORT:
8333        korwl(dst, src1, src2);
8334        break;
8335     case T_INT:
8336     case T_FLOAT:
8337        kordl(dst, src1, src2);
8338        break;
8339     case T_LONG:
8340     case T_DOUBLE:
8341        korql(dst, src1, src2);
8342        break;
8343     default:
8344       fatal("Unexpected type argument %s", type2name(type));
8345       break;
8346   }
8347 }
8348 
8349 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8350   switch(type) {
8351     case T_BOOLEAN:
8352     case T_BYTE:
8353        kxorbl(dst, src1, src2);
8354        break;
8355     case T_CHAR:
8356     case T_SHORT:
8357        kxorwl(dst, src1, src2);
8358        break;
8359     case T_INT:
8360     case T_FLOAT:
8361        kxordl(dst, src1, src2);
8362        break;
8363     case T_LONG:
8364     case T_DOUBLE:
8365        kxorql(dst, src1, src2);
8366        break;
8367     default:
8368       fatal("Unexpected type argument %s", type2name(type));
8369       break;
8370   }
8371 }
8372 
8373 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8374   switch(type) {
8375     case T_BOOLEAN:
8376     case T_BYTE:
8377       evpermb(dst, mask, nds, src, merge, vector_len); break;
8378     case T_CHAR:
8379     case T_SHORT:
8380       evpermw(dst, mask, nds, src, merge, vector_len); break;
8381     case T_INT:
8382     case T_FLOAT:
8383       evpermd(dst, mask, nds, src, merge, vector_len); break;
8384     case T_LONG:
8385     case T_DOUBLE:
8386       evpermq(dst, mask, nds, src, merge, vector_len); break;
8387     default:
8388       fatal("Unexpected type argument %s", type2name(type)); break;
8389   }
8390 }
8391 
8392 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8393   switch(type) {
8394     case T_BOOLEAN:
8395     case T_BYTE:
8396       evpermb(dst, mask, nds, src, merge, vector_len); break;
8397     case T_CHAR:
8398     case T_SHORT:
8399       evpermw(dst, mask, nds, src, merge, vector_len); break;
8400     case T_INT:
8401     case T_FLOAT:
8402       evpermd(dst, mask, nds, src, merge, vector_len); break;
8403     case T_LONG:
8404     case T_DOUBLE:
8405       evpermq(dst, mask, nds, src, merge, vector_len); break;
8406     default:
8407       fatal("Unexpected type argument %s", type2name(type)); break;
8408   }
8409 }
8410 
8411 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8412   switch(type) {
8413     case T_BYTE:
8414       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8415     case T_SHORT:
8416       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8417     case T_INT:
8418       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8419     case T_LONG:
8420       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8421     default:
8422       fatal("Unexpected type argument %s", type2name(type)); break;
8423   }
8424 }
8425 
8426 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8427   switch(type) {
8428     case T_BYTE:
8429       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8430     case T_SHORT:
8431       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8432     case T_INT:
8433       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8434     case T_LONG:
8435       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8436     default:
8437       fatal("Unexpected type argument %s", type2name(type)); break;
8438   }
8439 }
8440 
8441 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8442   switch(type) {
8443     case T_BYTE:
8444       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8445     case T_SHORT:
8446       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8447     case T_INT:
8448       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8449     case T_LONG:
8450       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8451     default:
8452       fatal("Unexpected type argument %s", type2name(type)); break;
8453   }
8454 }
8455 
8456 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8457   switch(type) {
8458     case T_BYTE:
8459       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8460     case T_SHORT:
8461       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8462     case T_INT:
8463       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8464     case T_LONG:
8465       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8466     default:
8467       fatal("Unexpected type argument %s", type2name(type)); break;
8468   }
8469 }
8470 
8471 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8472   switch(type) {
8473     case T_INT:
8474       evpxord(dst, mask, nds, src, merge, vector_len); break;
8475     case T_LONG:
8476       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8477     default:
8478       fatal("Unexpected type argument %s", type2name(type)); break;
8479   }
8480 }
8481 
8482 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8483   switch(type) {
8484     case T_INT:
8485       evpxord(dst, mask, nds, src, merge, vector_len); break;
8486     case T_LONG:
8487       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8488     default:
8489       fatal("Unexpected type argument %s", type2name(type)); break;
8490   }
8491 }
8492 
8493 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8494   switch(type) {
8495     case T_INT:
8496       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8497     case T_LONG:
8498       evporq(dst, mask, nds, src, merge, vector_len); break;
8499     default:
8500       fatal("Unexpected type argument %s", type2name(type)); break;
8501   }
8502 }
8503 
8504 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8505   switch(type) {
8506     case T_INT:
8507       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8508     case T_LONG:
8509       evporq(dst, mask, nds, src, merge, vector_len); break;
8510     default:
8511       fatal("Unexpected type argument %s", type2name(type)); break;
8512   }
8513 }
8514 
8515 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8516   switch(type) {
8517     case T_INT:
8518       evpandd(dst, mask, nds, src, merge, vector_len); break;
8519     case T_LONG:
8520       evpandq(dst, mask, nds, src, merge, vector_len); break;
8521     default:
8522       fatal("Unexpected type argument %s", type2name(type)); break;
8523   }
8524 }
8525 
8526 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8527   switch(type) {
8528     case T_INT:
8529       evpandd(dst, mask, nds, src, merge, vector_len); break;
8530     case T_LONG:
8531       evpandq(dst, mask, nds, src, merge, vector_len); break;
8532     default:
8533       fatal("Unexpected type argument %s", type2name(type)); break;
8534   }
8535 }
8536 
8537 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) {
8538    masklen = masklen < 8 ? 8 : masklen;
8539    ktest(masklen, src1, src2);
8540    setb(Assembler::notZero, dst);
8541    movzbl(dst, dst);
8542 }
8543 
8544 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) {
8545   if (masklen < 8) {
8546     knotbl(kscratch, src2);
8547     kortestbl(src1, kscratch);
8548     setb(Assembler::carrySet, dst);
8549     movzbl(dst, dst);
8550   } else {
8551     ktest(masklen, src1, src2);
8552     setb(Assembler::carrySet, dst);
8553     movzbl(dst, dst);
8554   }
8555 }
8556 
8557 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
8558   switch(masklen) {
8559     case 8:
8560        kortestbl(src1, src2);
8561        break;
8562     case 16:
8563        kortestwl(src1, src2);
8564        break;
8565     case 32:
8566        kortestdl(src1, src2);
8567        break;
8568     case 64:
8569        kortestql(src1, src2);
8570        break;
8571     default:
8572       fatal("Unexpected mask length %d", masklen);
8573       break;
8574   }
8575 }
8576 
8577 
8578 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
8579   switch(masklen)  {
8580     case 8:
8581        ktestbl(src1, src2);
8582        break;
8583     case 16:
8584        ktestwl(src1, src2);
8585        break;
8586     case 32:
8587        ktestdl(src1, src2);
8588        break;
8589     case 64:
8590        ktestql(src1, src2);
8591        break;
8592     default:
8593       fatal("Unexpected mask length %d", masklen);
8594       break;
8595   }
8596 }
8597 
8598 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8599   switch(type) {
8600     case T_INT:
8601       evprold(dst, mask, src, shift, merge, vlen_enc); break;
8602     case T_LONG:
8603       evprolq(dst, mask, src, shift, merge, vlen_enc); break;
8604     default:
8605       fatal("Unexpected type argument %s", type2name(type)); break;
8606       break;
8607   }
8608 }
8609 
8610 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8611   switch(type) {
8612     case T_INT:
8613       evprord(dst, mask, src, shift, merge, vlen_enc); break;
8614     case T_LONG:
8615       evprorq(dst, mask, src, shift, merge, vlen_enc); break;
8616     default:
8617       fatal("Unexpected type argument %s", type2name(type)); break;
8618   }
8619 }
8620 
8621 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8622   switch(type) {
8623     case T_INT:
8624       evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
8625     case T_LONG:
8626       evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
8627     default:
8628       fatal("Unexpected type argument %s", type2name(type)); break;
8629   }
8630 }
8631 
8632 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8633   switch(type) {
8634     case T_INT:
8635       evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
8636     case T_LONG:
8637       evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
8638     default:
8639       fatal("Unexpected type argument %s", type2name(type)); break;
8640   }
8641 }
8642 #if COMPILER2_OR_JVMCI
8643 
8644 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
8645                                  Register length, Register temp, int vec_enc) {
8646   // Computing mask for predicated vector store.
8647   movptr(temp, -1);
8648   bzhiq(temp, temp, length);
8649   kmov(mask, temp);
8650   evmovdqu(bt, mask, dst, xmm, vec_enc);
8651 }
8652 
8653 // Set memory operation for length "less than" 64 bytes.
8654 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
8655                                        XMMRegister xmm, KRegister mask, Register length,
8656                                        Register temp, bool use64byteVector) {
8657   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8658   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8659   if (!use64byteVector) {
8660     fill32(dst, disp, xmm);
8661     subptr(length, 32 >> shift);
8662     fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
8663   } else {
8664     assert(MaxVectorSize == 64, "vector length != 64");
8665     fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
8666   }
8667 }
8668 
8669 
8670 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
8671                                        XMMRegister xmm, KRegister mask, Register length,
8672                                        Register temp) {
8673   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8674   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8675   fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
8676 }
8677 
8678 
8679 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
8680   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8681   vmovdqu(Address(dst, disp), xmm);
8682 }
8683 
8684 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8685   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8686   BasicType type[] = {T_BYTE,  T_SHORT,  T_INT,   T_LONG};
8687   if (!use64byteVector) {
8688     fill32(dst, disp, xmm);
8689     fill32(dst, disp + 32, xmm);
8690   } else {
8691     evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8692   }
8693 }
8694 
8695 #ifdef _LP64
8696 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
8697                                         Register count, Register rtmp, XMMRegister xtmp) {
8698   Label L_exit;
8699   Label L_fill_start;
8700   Label L_fill_64_bytes;
8701   Label L_fill_96_bytes;
8702   Label L_fill_128_bytes;
8703   Label L_fill_128_bytes_loop;
8704   Label L_fill_128_loop_header;
8705   Label L_fill_128_bytes_loop_header;
8706   Label L_fill_128_bytes_loop_pre_header;
8707   Label L_fill_zmm_sequence;
8708 
8709   int shift = -1;
8710   switch(type) {
8711     case T_BYTE:  shift = 0;
8712       break;
8713     case T_SHORT: shift = 1;
8714       break;
8715     case T_INT:   shift = 2;
8716       break;
8717     /* Uncomment when LONG fill stubs are supported.
8718     case T_LONG:  shift = 3;
8719       break;
8720     */
8721     default:
8722       fatal("Unhandled type: %s\n", type2name(type));
8723   }
8724 
8725   if (AVX3Threshold != 0  || MaxVectorSize == 32) {
8726 
8727     if (MaxVectorSize == 64) {
8728       cmpq(count, AVX3Threshold >> shift);
8729       jcc(Assembler::greater, L_fill_zmm_sequence);
8730     }
8731 
8732     evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
8733 
8734     bind(L_fill_start);
8735 
8736     cmpq(count, 32 >> shift);
8737     jccb(Assembler::greater, L_fill_64_bytes);
8738     fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
8739     jmp(L_exit);
8740 
8741     bind(L_fill_64_bytes);
8742     cmpq(count, 64 >> shift);
8743     jccb(Assembler::greater, L_fill_96_bytes);
8744     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
8745     jmp(L_exit);
8746 
8747     bind(L_fill_96_bytes);
8748     cmpq(count, 96 >> shift);
8749     jccb(Assembler::greater, L_fill_128_bytes);
8750     fill64(to, 0, xtmp);
8751     subq(count, 64 >> shift);
8752     fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
8753     jmp(L_exit);
8754 
8755     bind(L_fill_128_bytes);
8756     cmpq(count, 128 >> shift);
8757     jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
8758     fill64(to, 0, xtmp);
8759     fill32(to, 64, xtmp);
8760     subq(count, 96 >> shift);
8761     fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
8762     jmp(L_exit);
8763 
8764     bind(L_fill_128_bytes_loop_pre_header);
8765     {
8766       mov(rtmp, to);
8767       andq(rtmp, 31);
8768       jccb(Assembler::zero, L_fill_128_bytes_loop_header);
8769       negq(rtmp);
8770       addq(rtmp, 32);
8771       mov64(r8, -1L);
8772       bzhiq(r8, r8, rtmp);
8773       kmovql(k2, r8);
8774       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_256bit);
8775       addq(to, rtmp);
8776       shrq(rtmp, shift);
8777       subq(count, rtmp);
8778     }
8779 
8780     cmpq(count, 128 >> shift);
8781     jcc(Assembler::less, L_fill_start);
8782 
8783     bind(L_fill_128_bytes_loop_header);
8784     subq(count, 128 >> shift);
8785 
8786     align32();
8787     bind(L_fill_128_bytes_loop);
8788       fill64(to, 0, xtmp);
8789       fill64(to, 64, xtmp);
8790       addq(to, 128);
8791       subq(count, 128 >> shift);
8792       jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
8793 
8794     addq(count, 128 >> shift);
8795     jcc(Assembler::zero, L_exit);
8796     jmp(L_fill_start);
8797   }
8798 
8799   if (MaxVectorSize == 64) {
8800     // Sequence using 64 byte ZMM register.
8801     Label L_fill_128_bytes_zmm;
8802     Label L_fill_192_bytes_zmm;
8803     Label L_fill_192_bytes_loop_zmm;
8804     Label L_fill_192_bytes_loop_header_zmm;
8805     Label L_fill_192_bytes_loop_pre_header_zmm;
8806     Label L_fill_start_zmm_sequence;
8807 
8808     bind(L_fill_zmm_sequence);
8809     evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
8810 
8811     bind(L_fill_start_zmm_sequence);
8812     cmpq(count, 64 >> shift);
8813     jccb(Assembler::greater, L_fill_128_bytes_zmm);
8814     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
8815     jmp(L_exit);
8816 
8817     bind(L_fill_128_bytes_zmm);
8818     cmpq(count, 128 >> shift);
8819     jccb(Assembler::greater, L_fill_192_bytes_zmm);
8820     fill64(to, 0, xtmp, true);
8821     subq(count, 64 >> shift);
8822     fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
8823     jmp(L_exit);
8824 
8825     bind(L_fill_192_bytes_zmm);
8826     cmpq(count, 192 >> shift);
8827     jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
8828     fill64(to, 0, xtmp, true);
8829     fill64(to, 64, xtmp, true);
8830     subq(count, 128 >> shift);
8831     fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
8832     jmp(L_exit);
8833 
8834     bind(L_fill_192_bytes_loop_pre_header_zmm);
8835     {
8836       movq(rtmp, to);
8837       andq(rtmp, 63);
8838       jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
8839       negq(rtmp);
8840       addq(rtmp, 64);
8841       mov64(r8, -1L);
8842       bzhiq(r8, r8, rtmp);
8843       kmovql(k2, r8);
8844       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_512bit);
8845       addq(to, rtmp);
8846       shrq(rtmp, shift);
8847       subq(count, rtmp);
8848     }
8849 
8850     cmpq(count, 192 >> shift);
8851     jcc(Assembler::less, L_fill_start_zmm_sequence);
8852 
8853     bind(L_fill_192_bytes_loop_header_zmm);
8854     subq(count, 192 >> shift);
8855 
8856     align32();
8857     bind(L_fill_192_bytes_loop_zmm);
8858       fill64(to, 0, xtmp, true);
8859       fill64(to, 64, xtmp, true);
8860       fill64(to, 128, xtmp, true);
8861       addq(to, 192);
8862       subq(count, 192 >> shift);
8863       jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
8864 
8865     addq(count, 192 >> shift);
8866     jcc(Assembler::zero, L_exit);
8867     jmp(L_fill_start_zmm_sequence);
8868   }
8869   bind(L_exit);
8870 }
8871 #endif
8872 #endif //COMPILER2_OR_JVMCI
8873 
8874 
8875 #ifdef _LP64
8876 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
8877   Label done;
8878   cvttss2sil(dst, src);
8879   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8880   cmpl(dst, 0x80000000); // float_sign_flip
8881   jccb(Assembler::notEqual, done);
8882   subptr(rsp, 8);
8883   movflt(Address(rsp, 0), src);
8884   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
8885   pop(dst);
8886   bind(done);
8887 }
8888 
8889 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
8890   Label done;
8891   cvttsd2sil(dst, src);
8892   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
8893   cmpl(dst, 0x80000000); // float_sign_flip
8894   jccb(Assembler::notEqual, done);
8895   subptr(rsp, 8);
8896   movdbl(Address(rsp, 0), src);
8897   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
8898   pop(dst);
8899   bind(done);
8900 }
8901 
8902 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
8903   Label done;
8904   cvttss2siq(dst, src);
8905   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8906   jccb(Assembler::notEqual, done);
8907   subptr(rsp, 8);
8908   movflt(Address(rsp, 0), src);
8909   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
8910   pop(dst);
8911   bind(done);
8912 }
8913 
8914 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
8915   Label done;
8916   cvttsd2siq(dst, src);
8917   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
8918   jccb(Assembler::notEqual, done);
8919   subptr(rsp, 8);
8920   movdbl(Address(rsp, 0), src);
8921   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
8922   pop(dst);
8923   bind(done);
8924 }
8925 
8926 void MacroAssembler::cache_wb(Address line)
8927 {
8928   // 64 bit cpus always support clflush
8929   assert(VM_Version::supports_clflush(), "clflush should be available");
8930   bool optimized = VM_Version::supports_clflushopt();
8931   bool no_evict = VM_Version::supports_clwb();
8932 
8933   // prefer clwb (writeback without evict) otherwise
8934   // prefer clflushopt (potentially parallel writeback with evict)
8935   // otherwise fallback on clflush (serial writeback with evict)
8936 
8937   if (optimized) {
8938     if (no_evict) {
8939       clwb(line);
8940     } else {
8941       clflushopt(line);
8942     }
8943   } else {
8944     // no need for fence when using CLFLUSH
8945     clflush(line);
8946   }
8947 }
8948 
8949 void MacroAssembler::cache_wbsync(bool is_pre)
8950 {
8951   assert(VM_Version::supports_clflush(), "clflush should be available");
8952   bool optimized = VM_Version::supports_clflushopt();
8953   bool no_evict = VM_Version::supports_clwb();
8954 
8955   // pick the correct implementation
8956 
8957   if (!is_pre && (optimized || no_evict)) {
8958     // need an sfence for post flush when using clflushopt or clwb
8959     // otherwise no no need for any synchroniaztion
8960 
8961     sfence();
8962   }
8963 }
8964 
8965 #endif // _LP64
8966 
8967 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
8968   switch (cond) {
8969     // Note some conditions are synonyms for others
8970     case Assembler::zero:         return Assembler::notZero;
8971     case Assembler::notZero:      return Assembler::zero;
8972     case Assembler::less:         return Assembler::greaterEqual;
8973     case Assembler::lessEqual:    return Assembler::greater;
8974     case Assembler::greater:      return Assembler::lessEqual;
8975     case Assembler::greaterEqual: return Assembler::less;
8976     case Assembler::below:        return Assembler::aboveEqual;
8977     case Assembler::belowEqual:   return Assembler::above;
8978     case Assembler::above:        return Assembler::belowEqual;
8979     case Assembler::aboveEqual:   return Assembler::below;
8980     case Assembler::overflow:     return Assembler::noOverflow;
8981     case Assembler::noOverflow:   return Assembler::overflow;
8982     case Assembler::negative:     return Assembler::positive;
8983     case Assembler::positive:     return Assembler::negative;
8984     case Assembler::parity:       return Assembler::noParity;
8985     case Assembler::noParity:     return Assembler::parity;
8986   }
8987   ShouldNotReachHere(); return Assembler::overflow;
8988 }
8989 
8990 SkipIfEqual::SkipIfEqual(
8991     MacroAssembler* masm, const bool* flag_addr, bool value) {
8992   _masm = masm;
8993   _masm->cmp8(ExternalAddress((address)flag_addr), value);
8994   _masm->jcc(Assembler::equal, _label);
8995 }
8996 
8997 SkipIfEqual::~SkipIfEqual() {
8998   _masm->bind(_label);
8999 }
9000 
9001 // 32-bit Windows has its own fast-path implementation
9002 // of get_thread
9003 #if !defined(WIN32) || defined(_LP64)
9004 
9005 // This is simply a call to Thread::current()
9006 void MacroAssembler::get_thread(Register thread) {
9007   if (thread != rax) {
9008     push(rax);
9009   }
9010   LP64_ONLY(push(rdi);)
9011   LP64_ONLY(push(rsi);)
9012   push(rdx);
9013   push(rcx);
9014 #ifdef _LP64
9015   push(r8);
9016   push(r9);
9017   push(r10);
9018   push(r11);
9019 #endif
9020 
9021   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9022 
9023 #ifdef _LP64
9024   pop(r11);
9025   pop(r10);
9026   pop(r9);
9027   pop(r8);
9028 #endif
9029   pop(rcx);
9030   pop(rdx);
9031   LP64_ONLY(pop(rsi);)
9032   LP64_ONLY(pop(rdi);)
9033   if (thread != rax) {
9034     mov(thread, rax);
9035     pop(rax);
9036   }
9037 }
9038 
9039 #endif // !WIN32 || _LP64