910 Disassembler::decode((address)pc-64, (address)pc);
911 tty->print_cr("--------");
912 Disassembler::decode((address)pc, (address)pc+32);
913 }
914
915 // The java_calling_convention describes stack locations as ideal slots on
916 // a frame with no abi restrictions. Since we must observe abi restrictions
917 // (like the placement of the register window) the slots must be biased by
918 // the following value.
919 static int reg2offset_in(VMReg r) {
920 // Account for saved rbp and return address
921 // This should really be in_preserve_stack_slots
922 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
923 }
924
925 static int reg2offset_out(VMReg r) {
926 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
927 }
928
929 // A long move
930 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
931
932 // The calling conventions assures us that each VMregpair is either
933 // all really one physical register or adjacent stack slots.
934
935 if (src.is_single_phys_reg() ) {
936 if (dst.is_single_phys_reg()) {
937 if (dst.first() != src.first()) {
938 mov(dst.first()->as_Register(), src.first()->as_Register());
939 }
940 } else {
941 assert(dst.is_single_reg(), "not a stack pair");
942 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
943 }
944 } else if (dst.is_single_phys_reg()) {
945 assert(src.is_single_reg(), "not a stack pair");
946 movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
947 } else {
948 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
949 movq(rax, Address(rbp, reg2offset_in(src.first())));
950 movq(Address(rsp, reg2offset_out(dst.first())), rax);
951 }
952 }
953
954 // A double move
955 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
956
957 // The calling conventions assures us that each VMregpair is either
958 // all really one physical register or adjacent stack slots.
959
960 if (src.is_single_phys_reg() ) {
961 if (dst.is_single_phys_reg()) {
962 // In theory these overlap but the ordering is such that this is likely a nop
963 if ( src.first() != dst.first()) {
964 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
965 }
966 } else {
967 assert(dst.is_single_reg(), "not a stack pair");
968 movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
969 }
970 } else if (dst.is_single_phys_reg()) {
971 assert(src.is_single_reg(), "not a stack pair");
972 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
973 } else {
974 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
975 movq(rax, Address(rbp, reg2offset_in(src.first())));
976 movq(Address(rsp, reg2offset_out(dst.first())), rax);
977 }
978 }
979
980
981 // A float arg may have to do float reg int reg conversion
982 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
983 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
984
985 // The calling conventions assures us that each VMregpair is either
986 // all really one physical register or adjacent stack slots.
987
988 if (src.first()->is_stack()) {
989 if (dst.first()->is_stack()) {
990 movl(rax, Address(rbp, reg2offset_in(src.first())));
991 movptr(Address(rsp, reg2offset_out(dst.first())), rax);
992 } else {
993 // stack to reg
994 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
995 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
996 }
997 } else if (dst.first()->is_stack()) {
998 // reg to stack
999 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1000 movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
1001 } else {
1002 // reg to reg
1003 // In theory these overlap but the ordering is such that this is likely a nop
1004 if ( src.first() != dst.first()) {
1005 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1006 }
1007 }
1008 }
1009
1010 // On 64 bit we will store integer like items to the stack as
1011 // 64 bits items (x86_32/64 abi) even though java would only store
1012 // 32bits for a parameter. On 32bit it will simply be 32 bits
1013 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1014 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1015 if (src.first()->is_stack()) {
1016 if (dst.first()->is_stack()) {
1017 // stack to stack
1018 movslq(rax, Address(rbp, reg2offset_in(src.first())));
1019 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1020 } else {
1021 // stack to reg
1022 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1023 }
1024 } else if (dst.first()->is_stack()) {
1025 // reg to stack
1026 // Do we really have to sign extend???
1027 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1028 movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1029 } else {
1030 // Do we really have to sign extend???
1031 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1032 if (dst.first() != src.first()) {
1033 movq(dst.first()->as_Register(), src.first()->as_Register());
1034 }
1035 }
1036 }
1037
1038 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1039 if (src.first()->is_stack()) {
1040 if (dst.first()->is_stack()) {
1041 // stack to stack
1042 movq(rax, Address(rbp, reg2offset_in(src.first())));
1043 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1044 } else {
1045 // stack to reg
1046 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1047 }
1048 } else if (dst.first()->is_stack()) {
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910 Disassembler::decode((address)pc-64, (address)pc);
911 tty->print_cr("--------");
912 Disassembler::decode((address)pc, (address)pc+32);
913 }
914
915 // The java_calling_convention describes stack locations as ideal slots on
916 // a frame with no abi restrictions. Since we must observe abi restrictions
917 // (like the placement of the register window) the slots must be biased by
918 // the following value.
919 static int reg2offset_in(VMReg r) {
920 // Account for saved rbp and return address
921 // This should really be in_preserve_stack_slots
922 return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
923 }
924
925 static int reg2offset_out(VMReg r) {
926 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
927 }
928
929 // A long move
930 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
931
932 // The calling conventions assures us that each VMregpair is either
933 // all really one physical register or adjacent stack slots.
934
935 if (src.is_single_phys_reg() ) {
936 if (dst.is_single_phys_reg()) {
937 if (dst.first() != src.first()) {
938 mov(dst.first()->as_Register(), src.first()->as_Register());
939 }
940 } else {
941 assert(dst.is_single_reg(), "not a stack pair: (%s, %s), (%s, %s)",
942 src.first()->name(), src.second()->name(), dst.first()->name(), dst.second()->name());
943 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
944 }
945 } else if (dst.is_single_phys_reg()) {
946 assert(src.is_single_reg(), "not a stack pair");
947 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
948 } else {
949 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
950 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
951 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
952 }
953 }
954
955 // A double move
956 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
957
958 // The calling conventions assures us that each VMregpair is either
959 // all really one physical register or adjacent stack slots.
960
961 if (src.is_single_phys_reg() ) {
962 if (dst.is_single_phys_reg()) {
963 // In theory these overlap but the ordering is such that this is likely a nop
964 if ( src.first() != dst.first()) {
965 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
966 }
967 } else {
968 assert(dst.is_single_reg(), "not a stack pair");
969 movdbl(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
970 }
971 } else if (dst.is_single_phys_reg()) {
972 assert(src.is_single_reg(), "not a stack pair");
973 movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
974 } else {
975 assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
976 movq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
977 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
978 }
979 }
980
981
982 // A float arg may have to do float reg int reg conversion
983 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
984 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
985
986 // The calling conventions assures us that each VMregpair is either
987 // all really one physical register or adjacent stack slots.
988
989 if (src.first()->is_stack()) {
990 if (dst.first()->is_stack()) {
991 movl(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
992 movptr(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
993 } else {
994 // stack to reg
995 assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
996 movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
997 }
998 } else if (dst.first()->is_stack()) {
999 // reg to stack
1000 assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
1001 movflt(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_XMMRegister());
1002 } else {
1003 // reg to reg
1004 // In theory these overlap but the ordering is such that this is likely a nop
1005 if ( src.first() != dst.first()) {
1006 movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
1007 }
1008 }
1009 }
1010
1011 // On 64 bit we will store integer like items to the stack as
1012 // 64 bits items (x86_32/64 abi) even though java would only store
1013 // 32bits for a parameter. On 32bit it will simply be 32 bits
1014 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1015 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst, Register tmp, int in_stk_bias, int out_stk_bias) {
1016 if (src.first()->is_stack()) {
1017 if (dst.first()->is_stack()) {
1018 // stack to stack
1019 movslq(tmp, Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1020 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), tmp);
1021 } else {
1022 // stack to reg
1023 movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first()) + in_stk_bias));
1024 }
1025 } else if (dst.first()->is_stack()) {
1026 // reg to stack
1027 // Do we really have to sign extend???
1028 // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1029 movq(Address(rsp, reg2offset_out(dst.first()) + out_stk_bias), src.first()->as_Register());
1030 } else {
1031 // Do we really have to sign extend???
1032 // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1033 if (dst.first() != src.first()) {
1034 movq(dst.first()->as_Register(), src.first()->as_Register());
1035 }
1036 }
1037 }
1038
1039 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1040 if (src.first()->is_stack()) {
1041 if (dst.first()->is_stack()) {
1042 // stack to stack
1043 movq(rax, Address(rbp, reg2offset_in(src.first())));
1044 movq(Address(rsp, reg2offset_out(dst.first())), rax);
1045 } else {
1046 // stack to reg
1047 movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1048 }
1049 } else if (dst.first()->is_stack()) {
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