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src/hotspot/cpu/aarch64/aarch64.ad

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 2443     case Op_VectorMaskCmp:
 2444       if (vlen < 2 || bit_size < 64) {
 2445         return false;
 2446       }
 2447       break;
 2448     case Op_MulAddVS2VI:
 2449       if (bit_size < 128) {
 2450         return false;
 2451       }
 2452       break;
 2453     case Op_MulVL:
 2454       return false;
 2455     case Op_VectorLoadShuffle:
 2456     case Op_VectorRearrange:
 2457       if (vlen < 4) {
 2458         return false;
 2459       }
 2460       break;
 2461     case Op_LoadVectorGather:
 2462     case Op_StoreVectorScatter:


 2463       return false;
 2464     default:
 2465       break;
 2466     }
 2467   }
 2468   return vector_size_supported(bt, vlen);
 2469 }
 2470 
 2471 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 2472   // Only SVE supports masked operations.
 2473   if (UseSVE == 0) {
 2474     return false;
 2475   }
 2476   return match_rule_supported(opcode) &&
 2477          masked_op_sve_supported(opcode, vlen, bt);
 2478 }
 2479 
 2480 const RegMask* Matcher::predicate_reg_mask(void) {
 2481   return &_PR_REG_mask;
 2482 }

 2443     case Op_VectorMaskCmp:
 2444       if (vlen < 2 || bit_size < 64) {
 2445         return false;
 2446       }
 2447       break;
 2448     case Op_MulAddVS2VI:
 2449       if (bit_size < 128) {
 2450         return false;
 2451       }
 2452       break;
 2453     case Op_MulVL:
 2454       return false;
 2455     case Op_VectorLoadShuffle:
 2456     case Op_VectorRearrange:
 2457       if (vlen < 4) {
 2458         return false;
 2459       }
 2460       break;
 2461     case Op_LoadVectorGather:
 2462     case Op_StoreVectorScatter:
 2463     case Op_CompressV:
 2464     case Op_CompressM:
 2465       return false;
 2466     default:
 2467       break;
 2468     }
 2469   }
 2470   return vector_size_supported(bt, vlen);
 2471 }
 2472 
 2473 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 2474   // Only SVE supports masked operations.
 2475   if (UseSVE == 0) {
 2476     return false;
 2477   }
 2478   return match_rule_supported(opcode) &&
 2479          masked_op_sve_supported(opcode, vlen, bt);
 2480 }
 2481 
 2482 const RegMask* Matcher::predicate_reg_mask(void) {
 2483   return &_PR_REG_mask;
 2484 }
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