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src/hotspot/cpu/aarch64/aarch64_neon_ad.m4

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2428   format %{ "frint  $dst, $src, $rmode" %}
2429   ins_encode %{
2430     switch ($rmode$$constant) {
2431       case RoundDoubleModeNode::rmode_rint:
2432         __ frintn(as_FloatRegister($dst$$reg), __ T2D,
2433                   as_FloatRegister($src$$reg));
2434         break;
2435       case RoundDoubleModeNode::rmode_floor:
2436         __ frintm(as_FloatRegister($dst$$reg), __ T2D,
2437                   as_FloatRegister($src$$reg));
2438         break;
2439       case RoundDoubleModeNode::rmode_ceil:
2440         __ frintp(as_FloatRegister($dst$$reg), __ T2D,
2441                   as_FloatRegister($src$$reg));
2442         break;
2443     }
2444   %}
2445   ins_pipe(vdop_fp128);
2446 %}
2447 dnl
2448 define(`VPOPCOUNT', `
2449 instruct vpopcount$1$2`'(vec$5 dst, vec$5 src) %{
2450   predicate(UsePopCountInstruction && n->as_Vector()->length() == $1);
2451   match(Set dst (PopCountVI src));
2452   format %{
2453     "cnt     $dst, $src\t# vector ($3B)\n\t"
2454     "uaddlp  $dst, $dst\t# vector ($3B)\n\t"
2455     "uaddlp  $dst, $dst\t# vector ($4H)"
2456   %}
2457   ins_encode %{
2458     __ cnt(as_FloatRegister($dst$$reg), __ T$3B,
2459            as_FloatRegister($src$$reg));
2460     __ uaddlp(as_FloatRegister($dst$$reg), __ T$3B,








2461               as_FloatRegister($dst$$reg));
2462     __ uaddlp(as_FloatRegister($dst$$reg), __ T$4H,
2463               as_FloatRegister($dst$$reg));













2464   %}
2465   ins_pipe(pipe_class_default);
2466 %}')dnl
2467 dnl       $1 $2 $3  $4 $5
2468 VPOPCOUNT(4, I, 16, 8, X)
2469 VPOPCOUNT(2, I, 8,  4, D)


2470 dnl
2471 dnl VMASK_TRUECOUNT($1,     $2 )
2472 dnl VMASK_TRUECOUNT(suffix, reg)
2473 define(`VMASK_TRUECOUNT', `
2474 instruct vmask_truecount$1(iRegINoSp dst, $2 src, $2 tmp) %{
2475   predicate(n->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BOOLEAN);
2476   match(Set dst (VectorMaskTrueCount src));
2477   effect(TEMP tmp);
2478   ins_cost(2 * INSN_COST);
2479   format %{ "addv $tmp, $src\n\t"
2480             "umov $dst, $tmp, B, 0\t# vector ($1)" %}
2481   ins_encode %{
2482     // Input "src" is a vector of boolean represented as bytes with
2483     // 0x00/0x01 as element values.
2484     __ addv(as_FloatRegister($tmp$$reg), __ T$1, as_FloatRegister($src$$reg));
2485     __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
2486   %}
2487   ins_pipe(pipe_slow);
2488 %}')dnl
2489 dnl

2630   ins_pipe(pipe_slow);
2631 %}
2632 
2633 instruct vmask_tolong16B(iRegLNoSp dst, vecX src) %{
2634   match(Set dst (VectorMaskToLong src));
2635   ins_cost(11 * INSN_COST);
2636   format %{ "vmask_tolong $dst, $src\t# convert mask to long (16B)" %}
2637   ins_encode %{
2638     // Input "src" is a vector of boolean represented as
2639     // bytes with 0x00/0x01 as element values.
2640 
2641     __ umov(as_Register($dst$$reg), as_FloatRegister($src$$reg), __ D, 0);
2642     __ umov(rscratch1, as_FloatRegister($src$$reg), __ D, 1);
2643     __ bytemask_compress(as_Register($dst$$reg));
2644     __ bytemask_compress(rscratch1);
2645     __ orr(as_Register($dst$$reg), as_Register($dst$$reg),
2646            rscratch1, Assembler::LSL, 8);
2647   %}
2648   ins_pipe(pipe_slow);
2649 %}















































































2428   format %{ "frint  $dst, $src, $rmode" %}
2429   ins_encode %{
2430     switch ($rmode$$constant) {
2431       case RoundDoubleModeNode::rmode_rint:
2432         __ frintn(as_FloatRegister($dst$$reg), __ T2D,
2433                   as_FloatRegister($src$$reg));
2434         break;
2435       case RoundDoubleModeNode::rmode_floor:
2436         __ frintm(as_FloatRegister($dst$$reg), __ T2D,
2437                   as_FloatRegister($src$$reg));
2438         break;
2439       case RoundDoubleModeNode::rmode_ceil:
2440         __ frintp(as_FloatRegister($dst$$reg), __ T2D,
2441                   as_FloatRegister($src$$reg));
2442         break;
2443     }
2444   %}
2445   ins_pipe(vdop_fp128);
2446 %}
2447 dnl
2448 define(`VPOPCOUNT', `dnl
2449 ifelse($1$2, `LD', `
2450 // If the PopCountVL is generated by auto-vectorization, the dst basic
2451 // type is T_INT. And once we have unified the type definition for
2452 // Vector API and auto-vectorization, this rule can be merged with
2453 // "vpopcountLX" rule.', `')
2454 instruct vpopcount$1$2`'(vec$2 dst, vec$3 src) %{
2455   predicate(n->as_Vector()->length_in_bytes() $4 16`'ifelse($1$2, `LD', ` &&
2456             n->bottom_type()->is_vect()->element_basic_type() == T_INT', $1$2, `LX', ` &&
2457             n->bottom_type()->is_vect()->element_basic_type() == T_LONG', `'));
2458   match(Set dst (PopCountV$1 src));
2459   ins_cost($5 * INSN_COST);
2460   format %{ "vpopcount$1  $dst, $src\t# vector ($6)" %}
2461   ins_encode %{
2462     assert(UsePopCountInstruction, "unsupported");dnl
2463 ifelse($1, `I', `
2464     BasicType bt = Matcher::vector_element_basic_type(this);', `')
2465     __ cnt(as_FloatRegister($dst$$reg), __ T`'ifelse($3, D, 8, 16)B,
2466            as_FloatRegister($src$$reg));dnl
2467 ifelse($1, `L', `
2468     __ uaddlp(as_FloatRegister($dst$$reg), __ T16B,
2469               as_FloatRegister($dst$$reg));
2470     __ uaddlp(as_FloatRegister($dst$$reg), __ T8H,
2471               as_FloatRegister($dst$$reg));
2472     __ uaddlp(as_FloatRegister($dst$$reg), __ T4S,
2473               as_FloatRegister($dst$$reg));', `
2474     if (bt == T_SHORT || bt == T_INT) {
2475       __ uaddlp(as_FloatRegister($dst$$reg), __ T`'ifelse($2, D, 8, 16)B,
2476                 as_FloatRegister($dst$$reg));
2477     }
2478     if (bt == T_INT) {
2479       __ uaddlp(as_FloatRegister($dst$$reg), __ T`'ifelse($2, D, 4, 8)H,
2480                 as_FloatRegister($dst$$reg));
2481     }')dnl
2482 ifelse($1$2, `LD', `
2483     __ xtn(as_FloatRegister($dst$$reg), __ T2S,
2484            as_FloatRegister($dst$$reg), __ T2D);', `')
2485   %}
2486   ins_pipe(pipe_class_default);
2487 %}')dnl
2488 dnl       $1 $2 $3 $4  $5 $6
2489 VPOPCOUNT(I, D, D, <,  3, 8B/4H/2S)
2490 VPOPCOUNT(I, X, X, ==, 3, 16B/8H/4S)
2491 VPOPCOUNT(L, D, X, <,  5, 2S)
2492 VPOPCOUNT(L, X, X, ==, 4, 2D)
2493 dnl
2494 dnl VMASK_TRUECOUNT($1,     $2 )
2495 dnl VMASK_TRUECOUNT(suffix, reg)
2496 define(`VMASK_TRUECOUNT', `
2497 instruct vmask_truecount$1(iRegINoSp dst, $2 src, $2 tmp) %{
2498   predicate(n->in(1)->bottom_type()->is_vect()->element_basic_type() == T_BOOLEAN);
2499   match(Set dst (VectorMaskTrueCount src));
2500   effect(TEMP tmp);
2501   ins_cost(2 * INSN_COST);
2502   format %{ "addv $tmp, $src\n\t"
2503             "umov $dst, $tmp, B, 0\t# vector ($1)" %}
2504   ins_encode %{
2505     // Input "src" is a vector of boolean represented as bytes with
2506     // 0x00/0x01 as element values.
2507     __ addv(as_FloatRegister($tmp$$reg), __ T$1, as_FloatRegister($src$$reg));
2508     __ umov($dst$$Register, as_FloatRegister($tmp$$reg), __ B, 0);
2509   %}
2510   ins_pipe(pipe_slow);
2511 %}')dnl
2512 dnl

2653   ins_pipe(pipe_slow);
2654 %}
2655 
2656 instruct vmask_tolong16B(iRegLNoSp dst, vecX src) %{
2657   match(Set dst (VectorMaskToLong src));
2658   ins_cost(11 * INSN_COST);
2659   format %{ "vmask_tolong $dst, $src\t# convert mask to long (16B)" %}
2660   ins_encode %{
2661     // Input "src" is a vector of boolean represented as
2662     // bytes with 0x00/0x01 as element values.
2663 
2664     __ umov(as_Register($dst$$reg), as_FloatRegister($src$$reg), __ D, 0);
2665     __ umov(rscratch1, as_FloatRegister($src$$reg), __ D, 1);
2666     __ bytemask_compress(as_Register($dst$$reg));
2667     __ bytemask_compress(rscratch1);
2668     __ orr(as_Register($dst$$reg), as_Register($dst$$reg),
2669            rscratch1, Assembler::LSL, 8);
2670   %}
2671   ins_pipe(pipe_slow);
2672 %}
2673 
2674 dnl
2675 dnl CLTZ_D($1     )
2676 dnl CLTZ_D(op_name)
2677 define(`CLTZ_D', `
2678 instruct count$1D(vecD dst, vecD src) %{
2679   predicate(n->as_Vector()->length_in_bytes() == 8);
2680   match(Set dst (Count$1 src));
2681   ins_cost(ifelse($1, `TrailingZerosV', `3 * ', `')INSN_COST);
2682   format %{ "count$1 $dst, $src\t# vector (8B/4H/2S)" %}
2683   ins_encode %{
2684     BasicType bt = Matcher::vector_element_basic_type(this);
2685     Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), false);dnl
2686 ifelse($1, `TrailingZerosV', `
2687     __ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, false);', `')
2688     __ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg));
2689   %}
2690   ins_pipe(pipe_slow);
2691 %}')dnl
2692 dnl
2693 dnl CLTZ_X($1     )
2694 dnl CLTZ_X(op_name)
2695 define(`CLTZ_X', `
2696 instruct count$1X(vecX dst, vecX src) %{
2697   predicate(n->as_Vector()->length_in_bytes() == 16);
2698   match(Set dst (Count$1 src));
2699   ins_cost(ifelse($1, `TrailingZerosV', `3 * ', `')INSN_COST);
2700   format %{ "count$1 $dst, $src\t# vector (16B/8H/4S/2D)" %}
2701   ins_encode %{
2702     BasicType bt = Matcher::vector_element_basic_type(this);
2703     Assembler::SIMD_Arrangement size = __ esize2arrangement((unsigned)type2aelembytes(bt), true);dnl
2704 ifelse($1, `TrailingZerosV', `
2705     __ neon_reverse_bits(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, true);', `')
2706     if (bt != T_LONG) {
2707       __ clz(as_FloatRegister($dst$$reg), size, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg));
2708     } else {
2709       __ umov(rscratch1, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg), __ D, 0);
2710       __ clz(rscratch1, rscratch1);
2711       __ mov(as_FloatRegister($dst$$reg), __ D, 0, rscratch1);
2712       __ umov(rscratch1, as_FloatRegister($ifelse($1, `TrailingZerosV', dst, src)$$reg), __ D, 1);
2713       __ clz(rscratch1, rscratch1);
2714       __ mov(as_FloatRegister($dst$$reg), __ D, 1, rscratch1);
2715     }
2716   %}
2717   ins_pipe(pipe_slow);
2718 %}')dnl
2719 dnl
2720 //------------------------- CountLeadingZerosV -----------------------------
2721 CLTZ_D(LeadingZerosV)
2722 CLTZ_X(LeadingZerosV)
2723 
2724 //------------------------- CountTrailingZerosV ----------------------------
2725 CLTZ_D(TrailingZerosV)
2726 CLTZ_X(TrailingZerosV)
2727 
2728 dnl
2729 dnl REVERSE($1,        $2,      $3,   $4  )
2730 dnl REVERSE(insn_name, op_name, type, insn)
2731 define(`REVERSE', `
2732 instruct $1(vec$3 dst, vec$3 src) %{
2733   predicate(n->as_Vector()->length_in_bytes() == ifelse($3, D, 8, 16));
2734   match(Set dst ($2 src));
2735   ins_cost(ifelse($2, `ReverseV', `2 * ', `')INSN_COST);
2736   format %{ "$2 $dst, $src\t# vector ($3)" %}
2737   ins_encode %{
2738     BasicType bt = Matcher::vector_element_basic_type(this);
2739     __ $4(as_FloatRegister($dst$$reg), as_FloatRegister($src$$reg), bt, ifelse($3, D, false, true));
2740   %}
2741   ins_pipe(pipe_slow);
2742 %}')dnl
2743 dnl
2744 //------------------------------ ReverseV -----------------------------------
2745 REVERSE(vreverseD, ReverseV, D, neon_reverse_bits)
2746 REVERSE(vreverseX, ReverseV, X, neon_reverse_bits)
2747 
2748 //---------------------------- ReverseBytesV --------------------------------
2749 REVERSE(vreverseBytesD, ReverseBytesV, D, neon_reverse_bytes)
2750 REVERSE(vreverseBytesX, ReverseBytesV, X, neon_reverse_bytes)
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