1 /*
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 3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 5  * This code is free software; you can redistribute it and/or modify it
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 9  * This code is distributed in the hope that it will be useful, but WITHOUT
10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12  * version 2 for more details (a copy is included in the LICENSE file that
13  * accompanied this code).
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24 
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27 
28 // C2_MacroAssembler contains high-level macros for C2
29 
30  public:
31 
32   void string_compare(Register str1, Register str2,
33                       Register cnt1, Register cnt2, Register result,
34                       Register tmp1, Register tmp2, FloatRegister vtmp1,
35                       FloatRegister vtmp2, FloatRegister vtmp3, int ae);
36 
37   void string_indexof(Register str1, Register str2,
38                       Register cnt1, Register cnt2,
39                       Register tmp1, Register tmp2,
40                       Register tmp3, Register tmp4,
41                       Register tmp5, Register tmp6,
42                       int int_cnt1, Register result, int ae);
43 
44   void string_indexof_char(Register str1, Register cnt1,
45                            Register ch, Register result,
46                            Register tmp1, Register tmp2, Register tmp3);
47 
48   void stringL_indexof_char(Register str1, Register cnt1,
49                             Register ch, Register result,
50                             Register tmp1, Register tmp2, Register tmp3);
51 
52   void string_indexof_char_sve(Register str1, Register cnt1,
53                                Register ch, Register result,
54                                FloatRegister ztmp1, FloatRegister ztmp2,
55                                PRegister pgtmp, PRegister ptmp, bool isL);
56 
57   // SIMD&FP comparison
58   void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
59                     FloatRegister src2, int cond, bool isQ);
60 
61   void sve_compare(PRegister pd, BasicType bt, PRegister pg,
62                    FloatRegister zn, FloatRegister zm, int cond);
63 
64   void sve_vmask_reduction(int opc, Register dst, SIMD_RegVariant size, FloatRegister src,
65                            PRegister pg, PRegister pn, int length = MaxVectorSize);
66 
67   // Generate predicate through whilelo, by comparing ZR with an unsigned
68   // immediate. rscratch1 will be clobbered.
69   inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
70     assert(UseSVE > 0, "not supported");
71     mov(rscratch1, imm);
72     sve_whilelo(pd, size, zr, rscratch1);
73   }
74 
75   // Extract a scalar element from an sve vector at position 'idx'.
76   // rscratch1 will be clobbered.
77   // T could be FloatRegister or Register.
78   template<class T>
79   inline void sve_extract(T dst, SIMD_RegVariant size, PRegister pg, FloatRegister src, int idx) {
80     assert(UseSVE > 0, "not supported");
81     assert(pg->is_governing(), "This register has to be a governing predicate register");
82     mov(rscratch1, idx);
83     sve_whilele(pg, size, zr, rscratch1);
84     sve_lastb(dst, size, pg, src);
85   }
86 
87 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP