1 /*
2 * Copyright (c) 2020, 2022, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 public:
31
32 void string_compare(Register str1, Register str2,
33 Register cnt1, Register cnt2, Register result,
34 Register tmp1, Register tmp2, FloatRegister vtmp1,
35 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
36
37 void string_indexof(Register str1, Register str2,
38 Register cnt1, Register cnt2,
39 Register tmp1, Register tmp2,
40 Register tmp3, Register tmp4,
41 Register tmp5, Register tmp6,
42 int int_cnt1, Register result, int ae);
43
44 void string_indexof_char(Register str1, Register cnt1,
45 Register ch, Register result,
46 Register tmp1, Register tmp2, Register tmp3);
47
48 void stringL_indexof_char(Register str1, Register cnt1,
49 Register ch, Register result,
50 Register tmp1, Register tmp2, Register tmp3);
51
52 void string_indexof_char_sve(Register str1, Register cnt1,
53 Register ch, Register result,
54 FloatRegister ztmp1, FloatRegister ztmp2,
55 PRegister pgtmp, PRegister ptmp, bool isL);
56
57 // Compress the least significant bit of each byte to the rightmost and clear
58 // the higher garbage bits.
59 void bytemask_compress(Register dst);
60
61 // Pack the lowest-numbered bit of each mask element in src into a long value
62 // in dst, at most the first 64 lane elements.
63 void sve_vmask_tolong(Register dst, PRegister src, BasicType bt, int lane_cnt,
64 FloatRegister vtmp1, FloatRegister vtmp2);
65
66 // SIMD&FP comparison
67 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
68 FloatRegister src2, int cond, bool isQ);
69
70 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
71 FloatRegister zn, FloatRegister zm, int cond);
72
73 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
74
75 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
76 FloatRegister src, SIMD_RegVariant src_size);
77
78 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
79 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
80
81 void sve_vmaskcast_extend(PRegister dst, PRegister src,
82 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
83
84 void sve_vmaskcast_narrow(PRegister dst, PRegister src,
85 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
86
87 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
88 FloatRegister src2, PRegister pg, FloatRegister tmp);
89
90 // Set elements of the dst predicate to true if the element number is
91 // in the range of [0, lane_cnt), or to false otherwise.
92 void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);
93
94 // Extract a scalar element from an sve vector at position 'idx'.
95 // The input elements in src are expected to be of integral type.
96 void sve_extract_integral(Register dst, SIMD_RegVariant size, FloatRegister src, int idx,
97 bool is_signed, FloatRegister vtmp);
98
99 // java.lang.Math::round intrinsics
100 void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
101 FloatRegister tmp2, FloatRegister tmp3,
102 SIMD_Arrangement T);
103 void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
104 FloatRegister tmp2, PRegister ptmp,
105 SIMD_RegVariant T);
106
107 // Pack active elements of src, under the control of mask, into the
108 // lowest-numbered elements of dst. Any remaining elements of dst will
109 // be filled with zero.
110 void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
111 FloatRegister vtmp1, FloatRegister vtmp2,
112 FloatRegister vtmp3, FloatRegister vtmp4,
113 PRegister ptmp, PRegister pgtmp);
114
115 void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
116 FloatRegister vtmp1, FloatRegister vtmp2,
117 PRegister pgtmp);
118
119 void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
120
121 void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
122
123 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP