1 /*
2 * Copyright (c) 2020, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
26 #define CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
27
28 // C2_MacroAssembler contains high-level macros for C2
29
30 public:
31
32 void string_compare(Register str1, Register str2,
33 Register cnt1, Register cnt2, Register result,
34 Register tmp1, Register tmp2, FloatRegister vtmp1,
35 FloatRegister vtmp2, FloatRegister vtmp3, int ae);
36
37 void string_indexof(Register str1, Register str2,
38 Register cnt1, Register cnt2,
39 Register tmp1, Register tmp2,
40 Register tmp3, Register tmp4,
41 Register tmp5, Register tmp6,
42 int int_cnt1, Register result, int ae);
43
44 void string_indexof_char(Register str1, Register cnt1,
45 Register ch, Register result,
46 Register tmp1, Register tmp2, Register tmp3);
47
48 void stringL_indexof_char(Register str1, Register cnt1,
49 Register ch, Register result,
50 Register tmp1, Register tmp2, Register tmp3);
51
52 void string_indexof_char_sve(Register str1, Register cnt1,
53 Register ch, Register result,
54 FloatRegister ztmp1, FloatRegister ztmp2,
55 PRegister pgtmp, PRegister ptmp, bool isL);
56
57 // SIMD&FP comparison
58 void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
59 FloatRegister src2, int cond, bool isQ);
60
61 void sve_compare(PRegister pd, BasicType bt, PRegister pg,
62 FloatRegister zn, FloatRegister zm, int cond);
63
64 void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
65
66 void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
67 FloatRegister src, SIMD_RegVariant src_size);
68
69 void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
70 FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
71
72 void sve_vmaskcast_extend(PRegister dst, PRegister src,
73 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
74
75 void sve_vmaskcast_narrow(PRegister dst, PRegister src,
76 uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
77
78 void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
79 FloatRegister src2, PRegister pg, FloatRegister tmp);
80
81 // Generate predicate through whilelo, by comparing ZR with an unsigned
82 // immediate. rscratch1 will be clobbered.
83 inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
84 assert(UseSVE > 0, "not supported");
85 mov(rscratch1, imm);
86 sve_whilelo(pd, size, zr, rscratch1);
87 }
88
89 // Extract a scalar element from an sve vector at position 'idx'.
90 // rscratch1 will be clobbered.
91 // T could be FloatRegister or Register.
92 template<class T>
93 inline void sve_extract(T dst, SIMD_RegVariant size, PRegister pg, FloatRegister src, int idx) {
94 assert(UseSVE > 0, "not supported");
95 assert(pg->is_governing(), "This register has to be a governing predicate register");
96 mov(rscratch1, idx);
97 sve_whilele(pg, size, zr, rscratch1);
98 sve_lastb(dst, size, pg, src);
99 }
100
101 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP