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src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

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 44   void string_indexof_char(Register str1, Register cnt1,
 45                            Register ch, Register result,
 46                            Register tmp1, Register tmp2, Register tmp3);
 47 
 48   void stringL_indexof_char(Register str1, Register cnt1,
 49                             Register ch, Register result,
 50                             Register tmp1, Register tmp2, Register tmp3);
 51 
 52   void string_indexof_char_sve(Register str1, Register cnt1,
 53                                Register ch, Register result,
 54                                FloatRegister ztmp1, FloatRegister ztmp2,
 55                                PRegister pgtmp, PRegister ptmp, bool isL);
 56 
 57   // SIMD&FP comparison
 58   void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
 59                     FloatRegister src2, int cond, bool isQ);
 60 
 61   void sve_compare(PRegister pd, BasicType bt, PRegister pg,
 62                    FloatRegister zn, FloatRegister zm, int cond);
 63 
 64   void sve_vmask_reduction(int opc, Register dst, SIMD_RegVariant size, FloatRegister src,
 65                            PRegister pg, PRegister pn, int length = MaxVectorSize);














 66 
 67   // Generate predicate through whilelo, by comparing ZR with an unsigned
 68   // immediate. rscratch1 will be clobbered.
 69   inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
 70     assert(UseSVE > 0, "not supported");
 71     mov(rscratch1, imm);
 72     sve_whilelo(pd, size, zr, rscratch1);
 73   }
 74 
 75   // Extract a scalar element from an sve vector at position 'idx'.
 76   // rscratch1 will be clobbered.
 77   // T could be FloatRegister or Register.
 78   template<class T>
 79   inline void sve_extract(T dst, SIMD_RegVariant size, PRegister pg, FloatRegister src, int idx) {
 80     assert(UseSVE > 0, "not supported");
 81     assert(pg->is_governing(), "This register has to be a governing predicate register");
 82     mov(rscratch1, idx);
 83     sve_whilele(pg, size, zr, rscratch1);
 84     sve_lastb(dst, size, pg, src);
 85   }

 44   void string_indexof_char(Register str1, Register cnt1,
 45                            Register ch, Register result,
 46                            Register tmp1, Register tmp2, Register tmp3);
 47 
 48   void stringL_indexof_char(Register str1, Register cnt1,
 49                             Register ch, Register result,
 50                             Register tmp1, Register tmp2, Register tmp3);
 51 
 52   void string_indexof_char_sve(Register str1, Register cnt1,
 53                                Register ch, Register result,
 54                                FloatRegister ztmp1, FloatRegister ztmp2,
 55                                PRegister pgtmp, PRegister ptmp, bool isL);
 56 
 57   // SIMD&FP comparison
 58   void neon_compare(FloatRegister dst, BasicType bt, FloatRegister src1,
 59                     FloatRegister src2, int cond, bool isQ);
 60 
 61   void sve_compare(PRegister pd, BasicType bt, PRegister pg,
 62                    FloatRegister zn, FloatRegister zm, int cond);
 63 
 64   void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
 65 
 66   void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
 67                          FloatRegister src, SIMD_RegVariant src_size);
 68 
 69   void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
 70                          FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
 71 
 72   void sve_vmaskcast_extend(PRegister dst, PRegister src,
 73                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
 74 
 75   void sve_vmaskcast_narrow(PRegister dst, PRegister src,
 76                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
 77 
 78   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
 79                            FloatRegister src2, PRegister pg, FloatRegister tmp);
 80 
 81   // Generate predicate through whilelo, by comparing ZR with an unsigned
 82   // immediate. rscratch1 will be clobbered.
 83   inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
 84     assert(UseSVE > 0, "not supported");
 85     mov(rscratch1, imm);
 86     sve_whilelo(pd, size, zr, rscratch1);
 87   }
 88 
 89   // Extract a scalar element from an sve vector at position 'idx'.
 90   // rscratch1 will be clobbered.
 91   // T could be FloatRegister or Register.
 92   template<class T>
 93   inline void sve_extract(T dst, SIMD_RegVariant size, PRegister pg, FloatRegister src, int idx) {
 94     assert(UseSVE > 0, "not supported");
 95     assert(pg->is_governing(), "This register has to be a governing predicate register");
 96     mov(rscratch1, idx);
 97     sve_whilele(pg, size, zr, rscratch1);
 98     sve_lastb(dst, size, pg, src);
 99   }
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