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src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

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 87   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
 88                            FloatRegister src2, PRegister pg, FloatRegister tmp);
 89 
 90   // Set elements of the dst predicate to true if the element number is
 91   // in the range of [0, lane_cnt), or to false otherwise.
 92   void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);
 93 
 94   // Extract a scalar element from an sve vector at position 'idx'.
 95   // The input elements in src are expected to be of integral type.
 96   void sve_extract_integral(Register dst, SIMD_RegVariant size, FloatRegister src, int idx,
 97                             bool is_signed, FloatRegister vtmp);
 98 
 99   // java.lang.Math::round intrinsics
100   void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
101                          FloatRegister tmp2, FloatRegister tmp3,
102                          SIMD_Arrangement T);
103   void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
104                         FloatRegister tmp2, PRegister ptmp,
105                         SIMD_RegVariant T);
106 
















107 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP

 87   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
 88                            FloatRegister src2, PRegister pg, FloatRegister tmp);
 89 
 90   // Set elements of the dst predicate to true if the element number is
 91   // in the range of [0, lane_cnt), or to false otherwise.
 92   void sve_ptrue_lanecnt(PRegister dst, SIMD_RegVariant size, int lane_cnt);
 93 
 94   // Extract a scalar element from an sve vector at position 'idx'.
 95   // The input elements in src are expected to be of integral type.
 96   void sve_extract_integral(Register dst, SIMD_RegVariant size, FloatRegister src, int idx,
 97                             bool is_signed, FloatRegister vtmp);
 98 
 99   // java.lang.Math::round intrinsics
100   void vector_round_neon(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
101                          FloatRegister tmp2, FloatRegister tmp3,
102                          SIMD_Arrangement T);
103   void vector_round_sve(FloatRegister dst, FloatRegister src, FloatRegister tmp1,
104                         FloatRegister tmp2, PRegister ptmp,
105                         SIMD_RegVariant T);
106 
107   // Pack active elements of src, under the control of mask, into the
108   // lowest-numbered elements of dst. Any remaining elements of dst will
109   // be filled with zero.
110   void sve_compress_byte(FloatRegister dst, FloatRegister src, PRegister mask,
111                          FloatRegister vtmp1, FloatRegister vtmp2,
112                          FloatRegister vtmp3, FloatRegister vtmp4,
113                          PRegister ptmp, PRegister pgtmp);
114 
115   void sve_compress_short(FloatRegister dst, FloatRegister src, PRegister mask,
116                           FloatRegister vtmp1, FloatRegister vtmp2,
117                           PRegister pgtmp);
118 
119   void neon_reverse_bits(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
120 
121   void neon_reverse_bytes(FloatRegister dst, FloatRegister src, BasicType bt, bool isQ);
122 
123 #endif // CPU_AARCH64_C2_MACROASSEMBLER_AARCH64_HPP
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