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src/hotspot/cpu/aarch64/c2_MacroAssembler_aarch64.hpp

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@@ -59,12 +59,26 @@
                      FloatRegister src2, int cond, bool isQ);
  
    void sve_compare(PRegister pd, BasicType bt, PRegister pg,
                     FloatRegister zn, FloatRegister zm, int cond);
  
-   void sve_vmask_reduction(int opc, Register dst, SIMD_RegVariant size, FloatRegister src,
-                            PRegister pg, PRegister pn, int length = MaxVectorSize);
+   void sve_vmask_lasttrue(Register dst, BasicType bt, PRegister src, PRegister ptmp);
+ 
+   void sve_vector_extend(FloatRegister dst, SIMD_RegVariant dst_size,
+                          FloatRegister src, SIMD_RegVariant src_size);
+ 
+   void sve_vector_narrow(FloatRegister dst, SIMD_RegVariant dst_size,
+                          FloatRegister src, SIMD_RegVariant src_size, FloatRegister tmp);
+ 
+   void sve_vmaskcast_extend(PRegister dst, PRegister src,
+                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
+ 
+   void sve_vmaskcast_narrow(PRegister dst, PRegister src,
+                             uint dst_element_length_in_bytes, uint src_element_lenght_in_bytes);
+ 
+   void sve_reduce_integral(int opc, Register dst, BasicType bt, Register src1,
+                            FloatRegister src2, PRegister pg, FloatRegister tmp);
  
    // Generate predicate through whilelo, by comparing ZR with an unsigned
    // immediate. rscratch1 will be clobbered.
    inline void sve_whilelo_zr_imm(PRegister pd, SIMD_RegVariant size, uint imm) {
      assert(UseSVE > 0, "not supported");
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