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src/hotspot/cpu/aarch64/sharedRuntime_aarch64.cpp

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  84     framesize
  85   };
  86 };
  87 
  88 // FIXME -- this is used by C1
  89 class RegisterSaver {
  90   const bool _save_vectors;
  91  public:
  92   RegisterSaver(bool save_vectors) : _save_vectors(save_vectors) {}
  93 
  94   OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
  95   void restore_live_registers(MacroAssembler* masm);
  96 
  97   // Offsets into the register save area
  98   // Used by deoptimization when it is managing result register
  99   // values on its own
 100 
 101   int reg_offset_in_bytes(Register r);
 102   int r0_offset_in_bytes()    { return reg_offset_in_bytes(r0); }
 103   int rscratch1_offset_in_bytes()    { return reg_offset_in_bytes(rscratch1); }
 104   int v0_offset_in_bytes(void)   { return 0; }



 105 
 106   // Capture info about frame layout
 107   // Note this is only correct when not saving full vectors.
 108   enum layout {
 109                 fpu_state_off = 0,
 110                 fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1,
 111                 // The frame sender code expects that rfp will be in
 112                 // the "natural" place and will override any oopMap
 113                 // setting for it. We must therefore force the layout
 114                 // so that it agrees with the frame sender code.
 115                 r0_off = fpu_state_off + FPUStateSizeInWords,
 116                 rfp_off = r0_off + (RegisterImpl::number_of_registers - 2) * RegisterImpl::max_slots_per_register,
 117                 return_off = rfp_off + RegisterImpl::max_slots_per_register,      // slot for return address
 118                 reg_save_size = return_off + RegisterImpl::max_slots_per_register};
 119 
 120 };
 121 
 122 int RegisterSaver::reg_offset_in_bytes(Register r) {
 123   // The integer registers are located above the floating point
 124   // registers in the stack frame pushed by save_live_registers() so the
 125   // offset depends on whether we are saving full vectors, and whether
 126   // those vectors are NEON or SVE.
 127 
 128   int slots_per_vect = FloatRegisterImpl::save_slots_per_register;
 129 
 130 #if COMPILER2_OR_JVMCI
 131   if (_save_vectors) {
 132     slots_per_vect = FloatRegisterImpl::slots_per_neon_register;
 133 
 134 #ifdef COMPILER2
 135     if (Matcher::supports_scalable_vector()) {
 136       slots_per_vect = Matcher::scalable_vector_reg_size(T_FLOAT);
 137     }
 138 #endif
 139   }
 140 #endif
 141 
 142   int r0_offset = (slots_per_vect * FloatRegisterImpl::number_of_registers) * BytesPerInt;
 143   return r0_offset + r->encoding() * wordSize;
 144 }
 145 




















 146 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
 147   bool use_sve = false;
 148   int sve_vector_size_in_bytes = 0;
 149   int sve_vector_size_in_slots = 0;



 150 
 151 #ifdef COMPILER2
 152   use_sve = Matcher::supports_scalable_vector();
 153   sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 154   sve_vector_size_in_slots = Matcher::scalable_vector_reg_size(T_FLOAT);



 155 #endif
 156 
 157 #if COMPILER2_OR_JVMCI
 158   if (_save_vectors) {
 159     int vect_words = 0;
 160     int extra_save_slots_per_register = 0;
 161     // Save upper half of vector registers
 162     if (use_sve) {
 163       extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegisterImpl::save_slots_per_register;
 164     } else {
 165       extra_save_slots_per_register = FloatRegisterImpl::extra_save_slots_per_neon_register;
 166     }
 167     vect_words = FloatRegisterImpl::number_of_registers * extra_save_slots_per_register /
 168                  VMRegImpl::slots_per_word;
 169     additional_frame_words += vect_words;

 170   }
 171 #else
 172   assert(!_save_vectors, "vectors are generated only by C2 and JVMCI");
 173 #endif
 174 
 175   int frame_size_in_bytes = align_up(additional_frame_words * wordSize +
 176                                      reg_save_size * BytesPerInt, 16);
 177   // OopMap frame size is in compiler stack slots (jint's) not bytes or words
 178   int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
 179   // The caller will allocate additional_frame_words
 180   int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt;
 181   // CodeBlob frame size is in words.
 182   int frame_size_in_words = frame_size_in_bytes / wordSize;
 183   *total_frame_words = frame_size_in_words;
 184 
 185   // Save Integer and Float registers.
 186   __ enter();
 187   __ push_CPU_state(_save_vectors, use_sve, sve_vector_size_in_bytes);
 188 
 189   // Set an oopmap for the call site.  This oopmap will map all
 190   // oop-registers and debug-info registers as callee-saved.  This
 191   // will allow deoptimization at this safepoint to find all possible
 192   // debug-info recordings, as well as let GC find all oops.
 193 
 194   OopMapSet *oop_maps = new OopMapSet();
 195   OopMap* oop_map = new OopMap(frame_size_in_slots, 0);
 196 
 197   for (int i = 0; i < RegisterImpl::number_of_registers; i++) {
 198     Register r = as_Register(i);
 199     if (r <= rfp && r != rscratch1 && r != rscratch2) {
 200       // SP offsets are in 4-byte words.
 201       // Register slots are 8 bytes wide, 32 floating-point registers.
 202       int sp_offset = RegisterImpl::max_slots_per_register * i +
 203                       FloatRegisterImpl::save_slots_per_register * FloatRegisterImpl::number_of_registers;
 204       oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots),
 205                                 r->as_VMReg());
 206     }
 207   }
 208 
 209   for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) {
 210     FloatRegister r = as_FloatRegister(i);
 211     int sp_offset = 0;
 212     if (_save_vectors) {
 213       sp_offset = use_sve ? (sve_vector_size_in_slots * i) :
 214                             (FloatRegisterImpl::slots_per_neon_register * i);
 215     } else {
 216       sp_offset = FloatRegisterImpl::save_slots_per_register * i;
 217     }
 218     oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset),
 219                               r->as_VMReg());







 220   }
 221 
 222   return oop_map;
 223 }
 224 
 225 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
 226 #ifdef COMPILER2
 227   __ pop_CPU_state(_save_vectors, Matcher::supports_scalable_vector(),
 228                    Matcher::scalable_vector_reg_size(T_BYTE));
 229 #else
 230 #if !INCLUDE_JVMCI
 231   assert(!_save_vectors, "vectors are generated only by C2 and JVMCI");
 232 #endif
 233   __ pop_CPU_state(_save_vectors);
 234 #endif
 235   __ leave();
 236 
 237 }
 238 
 239 // Is vector's size (in bytes) bigger than a size saved by default?
 240 // 8 bytes vector registers are saved by default on AArch64.


 241 bool SharedRuntime::is_wide_vector(int size) {
 242   return size > 8;
 243 }
 244 
 245 // The java_calling_convention describes stack locations as ideal slots on
 246 // a frame with no abi restrictions. Since we must observe abi restrictions
 247 // (like the placement of the register window) the slots must be biased by
 248 // the following value.
 249 static int reg2offset_in(VMReg r) {
 250   // Account for saved rfp and lr
 251   // This should really be in_preserve_stack_slots
 252   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 253 }
 254 
 255 static int reg2offset_out(VMReg r) {
 256   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 257 }
 258 
 259 // ---------------------------------------------------------------------------
 260 // Read the array of BasicTypes from a signature, and compute where the
 261 // arguments should go.  Values in the VMRegPair regs array refer to 4-byte
 262 // quantities.  Values less than VMRegImpl::stack0 are registers, those above

  84     framesize
  85   };
  86 };
  87 
  88 // FIXME -- this is used by C1
  89 class RegisterSaver {
  90   const bool _save_vectors;
  91  public:
  92   RegisterSaver(bool save_vectors) : _save_vectors(save_vectors) {}
  93 
  94   OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
  95   void restore_live_registers(MacroAssembler* masm);
  96 
  97   // Offsets into the register save area
  98   // Used by deoptimization when it is managing result register
  99   // values on its own
 100 
 101   int reg_offset_in_bytes(Register r);
 102   int r0_offset_in_bytes()    { return reg_offset_in_bytes(r0); }
 103   int rscratch1_offset_in_bytes()    { return reg_offset_in_bytes(rscratch1); }
 104   int v0_offset_in_bytes();
 105 
 106   // Total stack size in bytes for saving sve predicate registers.
 107   int total_sve_predicate_in_bytes();
 108 
 109   // Capture info about frame layout
 110   // Note this is only correct when not saving full vectors.
 111   enum layout {
 112                 fpu_state_off = 0,
 113                 fpu_state_end = fpu_state_off + FPUStateSizeInWords - 1,
 114                 // The frame sender code expects that rfp will be in
 115                 // the "natural" place and will override any oopMap
 116                 // setting for it. We must therefore force the layout
 117                 // so that it agrees with the frame sender code.
 118                 r0_off = fpu_state_off + FPUStateSizeInWords,
 119                 rfp_off = r0_off + (RegisterImpl::number_of_registers - 2) * RegisterImpl::max_slots_per_register,
 120                 return_off = rfp_off + RegisterImpl::max_slots_per_register,      // slot for return address
 121                 reg_save_size = return_off + RegisterImpl::max_slots_per_register};
 122 
 123 };
 124 
 125 int RegisterSaver::reg_offset_in_bytes(Register r) {
 126   // The integer registers are located above the floating point
 127   // registers in the stack frame pushed by save_live_registers() so the
 128   // offset depends on whether we are saving full vectors, and whether
 129   // those vectors are NEON or SVE.
 130 
 131   int slots_per_vect = FloatRegisterImpl::save_slots_per_register;
 132 
 133 #if COMPILER2_OR_JVMCI
 134   if (_save_vectors) {
 135     slots_per_vect = FloatRegisterImpl::slots_per_neon_register;
 136 
 137 #ifdef COMPILER2
 138     if (Matcher::supports_scalable_vector()) {
 139       slots_per_vect = Matcher::scalable_vector_reg_size(T_FLOAT);
 140     }
 141 #endif
 142   }
 143 #endif
 144 
 145   int r0_offset = v0_offset_in_bytes() + (slots_per_vect * FloatRegisterImpl::number_of_registers) * BytesPerInt;
 146   return r0_offset + r->encoding() * wordSize;
 147 }
 148 
 149 int RegisterSaver::v0_offset_in_bytes() {
 150   // The floating point registers are located above the predicate registers if
 151   // they are present in the stack frame pushed by save_live_registers(). So the
 152   // offset depends on the saved total predicate vectors in the stack frame.
 153   return (total_sve_predicate_in_bytes() / VMRegImpl::stack_slot_size) * BytesPerInt;
 154 }
 155 
 156 int RegisterSaver::total_sve_predicate_in_bytes() {
 157 #ifdef COMPILER2
 158   if (_save_vectors && Matcher::supports_scalable_vector()) {
 159     // The number of total predicate bytes is unlikely to be a multiple
 160     // of 16 bytes so we manually align it up.
 161     return align_up(Matcher::scalable_predicate_reg_slots() *
 162                     VMRegImpl::stack_slot_size *
 163                     PRegisterImpl::number_of_saved_registers, 16);
 164   }
 165 #endif
 166   return 0;
 167 }
 168 
 169 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
 170   bool use_sve = false;
 171   int sve_vector_size_in_bytes = 0;
 172   int sve_vector_size_in_slots = 0;
 173   int sve_predicate_size_in_slots = 0;
 174   int total_predicate_in_bytes = total_sve_predicate_in_bytes();
 175   int total_predicate_in_slots = total_predicate_in_bytes / VMRegImpl::stack_slot_size;
 176 
 177 #ifdef COMPILER2
 178   use_sve = Matcher::supports_scalable_vector();
 179   if (use_sve) {
 180     sve_vector_size_in_bytes = Matcher::scalable_vector_reg_size(T_BYTE);
 181     sve_vector_size_in_slots = Matcher::scalable_vector_reg_size(T_FLOAT);
 182     sve_predicate_size_in_slots = Matcher::scalable_predicate_reg_slots();
 183   }
 184 #endif
 185 
 186 #if COMPILER2_OR_JVMCI
 187   if (_save_vectors) {

 188     int extra_save_slots_per_register = 0;
 189     // Save upper half of vector registers
 190     if (use_sve) {
 191       extra_save_slots_per_register = sve_vector_size_in_slots - FloatRegisterImpl::save_slots_per_register;
 192     } else {
 193       extra_save_slots_per_register = FloatRegisterImpl::extra_save_slots_per_neon_register;
 194     }
 195     int extra_vector_bytes = extra_save_slots_per_register *
 196                              VMRegImpl::stack_slot_size *
 197                              FloatRegisterImpl::number_of_registers;
 198     additional_frame_words += ((extra_vector_bytes + total_predicate_in_bytes) / wordSize);
 199   }
 200 #else
 201   assert(!_save_vectors, "vectors are generated only by C2 and JVMCI");
 202 #endif
 203 
 204   int frame_size_in_bytes = align_up(additional_frame_words * wordSize +
 205                                      reg_save_size * BytesPerInt, 16);
 206   // OopMap frame size is in compiler stack slots (jint's) not bytes or words
 207   int frame_size_in_slots = frame_size_in_bytes / BytesPerInt;
 208   // The caller will allocate additional_frame_words
 209   int additional_frame_slots = additional_frame_words * wordSize / BytesPerInt;
 210   // CodeBlob frame size is in words.
 211   int frame_size_in_words = frame_size_in_bytes / wordSize;
 212   *total_frame_words = frame_size_in_words;
 213 
 214   // Save Integer and Float registers.
 215   __ enter();
 216   __ push_CPU_state(_save_vectors, use_sve, sve_vector_size_in_bytes, total_predicate_in_bytes);
 217 
 218   // Set an oopmap for the call site.  This oopmap will map all
 219   // oop-registers and debug-info registers as callee-saved.  This
 220   // will allow deoptimization at this safepoint to find all possible
 221   // debug-info recordings, as well as let GC find all oops.
 222 
 223   OopMapSet *oop_maps = new OopMapSet();
 224   OopMap* oop_map = new OopMap(frame_size_in_slots, 0);
 225 
 226   for (int i = 0; i < RegisterImpl::number_of_registers; i++) {
 227     Register r = as_Register(i);
 228     if (r <= rfp && r != rscratch1 && r != rscratch2) {
 229       // SP offsets are in 4-byte words.
 230       // Register slots are 8 bytes wide, 32 floating-point registers.
 231       int sp_offset = RegisterImpl::max_slots_per_register * i +
 232                       FloatRegisterImpl::save_slots_per_register * FloatRegisterImpl::number_of_registers;
 233       oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset + additional_frame_slots), r->as_VMReg());

 234     }
 235   }
 236 
 237   for (int i = 0; i < FloatRegisterImpl::number_of_registers; i++) {
 238     FloatRegister r = as_FloatRegister(i);
 239     int sp_offset = 0;
 240     if (_save_vectors) {
 241       sp_offset = use_sve ? (total_predicate_in_slots + sve_vector_size_in_slots * i) :
 242                             (FloatRegisterImpl::slots_per_neon_register * i);
 243     } else {
 244       sp_offset = FloatRegisterImpl::save_slots_per_register * i;
 245     }
 246     oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), r->as_VMReg());
 247   }
 248 
 249   if (_save_vectors && use_sve) {
 250     for (int i = 0; i < PRegisterImpl::number_of_saved_registers; i++) {
 251       PRegister r = as_PRegister(i);
 252       int sp_offset = sve_predicate_size_in_slots * i;
 253       oop_map->set_callee_saved(VMRegImpl::stack2reg(sp_offset), r->as_VMReg());
 254     }
 255   }
 256 
 257   return oop_map;
 258 }
 259 
 260 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
 261 #ifdef COMPILER2
 262   __ pop_CPU_state(_save_vectors, Matcher::supports_scalable_vector(),
 263                    Matcher::scalable_vector_reg_size(T_BYTE), total_sve_predicate_in_bytes());
 264 #else
 265 #if !INCLUDE_JVMCI
 266   assert(!_save_vectors, "vectors are generated only by C2 and JVMCI");
 267 #endif
 268   __ pop_CPU_state(_save_vectors);
 269 #endif
 270   __ leave();
 271 
 272 }
 273 
 274 // Is vector's size (in bytes) bigger than a size saved by default?
 275 // 8 bytes vector registers are saved by default on AArch64.
 276 // The SVE supported min vector size is 8 bytes and we need to save
 277 // predicate registers when the vector size is 8 bytes as well.
 278 bool SharedRuntime::is_wide_vector(int size) {
 279   return size > 8 || (UseSVE > 0 && size >= 8);
 280 }
 281 
 282 // The java_calling_convention describes stack locations as ideal slots on
 283 // a frame with no abi restrictions. Since we must observe abi restrictions
 284 // (like the placement of the register window) the slots must be biased by
 285 // the following value.
 286 static int reg2offset_in(VMReg r) {
 287   // Account for saved rfp and lr
 288   // This should really be in_preserve_stack_slots
 289   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 290 }
 291 
 292 static int reg2offset_out(VMReg r) {
 293   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 294 }
 295 
 296 // ---------------------------------------------------------------------------
 297 // Read the array of BasicTypes from a signature, and compute where the
 298 // arguments should go.  Values in the VMRegPair regs array refer to 4-byte
 299 // quantities.  Values less than VMRegImpl::stack0 are registers, those above
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