1 //
    2 // Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2017, 2020 SAP SE. All rights reserved.
    4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    5 //
    6 // This code is free software; you can redistribute it and/or modify it
    7 // under the terms of the GNU General Public License version 2 only, as
    8 // published by the Free Software Foundation.
    9 //
   10 // This code is distributed in the hope that it will be useful, but WITHOUT
   11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   13 // version 2 for more details (a copy is included in the LICENSE file that
   14 // accompanied this code).
   15 //
   16 // You should have received a copy of the GNU General Public License version
   17 // 2 along with this work; if not, write to the Free Software Foundation,
   18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   19 //
   20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   21 // or visit www.oracle.com if you need additional information or have any
   22 // questions.
   23 //
   24 
   25 // z/Architecture Architecture Description File
   26 
   27 // Major contributions by AS, JL, LS.
   28 
   29 //
   30 // Following information is derived from private mail communication
   31 // (Oct. 2011).
   32 //
   33 // General branch target alignment considerations
   34 //
   35 // z/Architecture does not imply a general branch target alignment requirement.
   36 // There are side effects and side considerations, though, which may
   37 // provide some performance benefit. These are:
   38 //  - Align branch target on octoword (32-byte) boundary
   39 //    On more recent models (from z9 on), I-fetch is done on a Octoword
   40 //    (32 bytes at a time) basis. To avoid I-fetching unnecessary
   41 //    instructions, branch targets should be 32-byte aligend. If this
   42 //    exact alingment cannot be achieved, having the branch target in
   43 //    the first doubleword still provides some benefit.
   44 //  - Avoid branch targets at the end of cache lines (> 64 bytes distance).
   45 //    Sequential instruction prefetching after the branch target starts
   46 //    immediately after having fetched the octoword containing the
   47 //    branch target. When I-fetching crosses a cache line, there may be
   48 //    a small stall. The worst case: the branch target (at the end of
   49 //    a cache line) is a L1 I-cache miss and the next line as well.
   50 //    Then, the entire target line must be filled first (to contine at the
   51 //    branch target). Only then can the next sequential line be filled.
   52 //  - Avoid multiple poorly predicted branches in a row.
   53 //
   54 
   55 //----------REGISTER DEFINITION BLOCK------------------------------------------
   56 // This information is used by the matcher and the register allocator to
   57 // describe individual registers and classes of registers within the target
   58 // architecture.
   59 
   60 register %{
   61 
   62 //----------Architecture Description Register Definitions----------------------
   63 // General Registers
   64 // "reg_def" name (register save type, C convention save type,
   65 //                   ideal register type, encoding);
   66 //
   67 // Register Save Types:
   68 //
   69 //   NS  = No-Save:     The register allocator assumes that these registers
   70 //                      can be used without saving upon entry to the method, &
   71 //                      that they do not need to be saved at call sites.
   72 //
   73 //   SOC = Save-On-Call: The register allocator assumes that these registers
   74 //                      can be used without saving upon entry to the method,
   75 //                      but that they must be saved at call sites.
   76 //
   77 //   SOE = Save-On-Entry: The register allocator assumes that these registers
   78 //                      must be saved before using them upon entry to the
   79 //                      method, but they do not need to be saved at call sites.
   80 //
   81 //   AS  = Always-Save: The register allocator assumes that these registers
   82 //                      must be saved before using them upon entry to the
   83 //                      method, & that they must be saved at call sites.
   84 //
   85 // Ideal Register Type is used to determine how to save & restore a
   86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
   88 //
   89 // The encoding number is the actual bit-pattern placed into the opcodes.
   90 
   91 // z/Architecture register definitions, based on the z/Architecture Principles
   92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
   93 // 5th Edition, March 2001.
   94 //
   95 // For each 64-bit register we must define two registers: the register
   96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
   97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
   98 // for stores, loads, etc.
   99 
  100   // Integer/Long Registers
  101   // ----------------------------
  102 
  103   // z/Architecture has 16 64-bit integer registers.
  104 
  105   // types: v = volatile, nv = non-volatile, s = system
  106   reg_def Z_R0   (SOC, SOC, Op_RegI,  0, Z_R0->as_VMReg());   // v   scratch1
  107   reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
  108   reg_def Z_R1   (SOC, SOC, Op_RegI,  1, Z_R1->as_VMReg());   // v   scratch2
  109   reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
  110   reg_def Z_R2   (SOC, SOC, Op_RegI,  2, Z_R2->as_VMReg());   // v   iarg1 & iret
  111   reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
  112   reg_def Z_R3   (SOC, SOC, Op_RegI,  3, Z_R3->as_VMReg());   // v   iarg2
  113   reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
  114   reg_def Z_R4   (SOC, SOC, Op_RegI,  4, Z_R4->as_VMReg());   // v   iarg3
  115   reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
  116   reg_def Z_R5   (SOC, SOC, Op_RegI,  5, Z_R5->as_VMReg());   // v   iarg4
  117   reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
  118   reg_def Z_R6   (SOC, SOE, Op_RegI,  6, Z_R6->as_VMReg());   // v   iarg5
  119   reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
  120   reg_def Z_R7   (SOC, SOE, Op_RegI,  7, Z_R7->as_VMReg());
  121   reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
  122   reg_def Z_R8   (SOC, SOE, Op_RegI,  8, Z_R8->as_VMReg());
  123   reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
  124   reg_def Z_R9   (SOC, SOE, Op_RegI,  9, Z_R9->as_VMReg());
  125   reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
  126   reg_def Z_R10  (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
  127   reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
  128   reg_def Z_R11  (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
  129   reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
  130   reg_def Z_R12  (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
  131   reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
  132   reg_def Z_R13  (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
  133   reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
  134   reg_def Z_R14  (NS,  NS,  Op_RegI, 14, Z_R14->as_VMReg());   // s  return_pc
  135   reg_def Z_R14_H(NS,  NS,  Op_RegI, 99, Z_R14->as_VMReg()->next());
  136   reg_def Z_R15  (NS,  NS,  Op_RegI, 15, Z_R15->as_VMReg());   // s  SP
  137   reg_def Z_R15_H(NS,  NS,  Op_RegI, 99, Z_R15->as_VMReg()->next());
  138 
  139   // Float/Double Registers
  140 
  141   // The rules of ADL require that double registers be defined in pairs.
  142   // Each pair must be two 32-bit values, but not necessarily a pair of
  143   // single float registers. In each pair, ADLC-assigned register numbers
  144   // must be adjacent, with the lower number even. Finally, when the
  145   // CPU stores such a register pair to memory, the word associated with
  146   // the lower ADLC-assigned number must be stored to the lower address.
  147 
  148   // z/Architecture has 16 64-bit floating-point registers. Each can store a single
  149   // or double precision floating-point value.
  150 
  151   // types: v = volatile, nv = non-volatile, s = system
  152   reg_def Z_F0   (SOC, SOC, Op_RegF,  0, Z_F0->as_VMReg());   // v   farg1 & fret
  153   reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
  154   reg_def Z_F1   (SOC, SOC, Op_RegF,  1, Z_F1->as_VMReg());
  155   reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
  156   reg_def Z_F2   (SOC, SOC, Op_RegF,  2, Z_F2->as_VMReg());   // v   farg2
  157   reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
  158   reg_def Z_F3   (SOC, SOC, Op_RegF,  3, Z_F3->as_VMReg());
  159   reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
  160   reg_def Z_F4   (SOC, SOC, Op_RegF,  4, Z_F4->as_VMReg());   // v   farg3
  161   reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
  162   reg_def Z_F5   (SOC, SOC, Op_RegF,  5, Z_F5->as_VMReg());
  163   reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
  164   reg_def Z_F6   (SOC, SOC, Op_RegF,  6, Z_F6->as_VMReg());
  165   reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
  166   reg_def Z_F7   (SOC, SOC, Op_RegF,  7, Z_F7->as_VMReg());
  167   reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
  168   reg_def Z_F8   (SOC, SOE, Op_RegF,  8, Z_F8->as_VMReg());
  169   reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
  170   reg_def Z_F9   (SOC, SOE, Op_RegF,  9, Z_F9->as_VMReg());
  171   reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
  172   reg_def Z_F10  (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
  173   reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
  174   reg_def Z_F11  (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
  175   reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
  176   reg_def Z_F12  (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
  177   reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
  178   reg_def Z_F13  (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
  179   reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
  180   reg_def Z_F14  (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
  181   reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
  182   reg_def Z_F15  (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
  183   reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
  184 
  185 
  186   // Special Registers
  187 
  188   // Condition Codes Flag Registers
  189 
  190   // z/Architecture has the PSW (program status word) that contains
  191   // (among other information) the condition code. We treat this
  192   // part of the PSW as a condition register CR. It consists of 4
  193   // bits. Floating point instructions influence the same condition register CR.
  194 
  195   reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg());   // volatile
  196 
  197 
  198 // Specify priority of register selection within phases of register
  199 // allocation. Highest priority is first. A useful heuristic is to
  200 // give registers a low priority when they are required by machine
  201 // instructions, and choose no-save registers before save-on-call, and
  202 // save-on-call before save-on-entry. Registers which participate in
  203 // fix calling sequences should come last. Registers which are used
  204 // as pairs must fall on an even boundary.
  205 
  206 // It's worth about 1% on SPEC geomean to get this right.
  207 
  208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
  209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
  210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
  211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
  212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
  213 // Additionally, the function
  214 //   static enum RC rc_class(OptoReg::Name reg)
  215 // maps a given <register>_num value to its chunk type (except for flags)
  216 // and its current implementation relies on chunk0 and chunk1 having a
  217 // size of 64 each.
  218 
  219 alloc_class chunk0(
  220   // chunk0 contains *all* 32 integer registers halves.
  221 
  222   // potential SOE regs
  223   Z_R13,Z_R13_H,
  224   Z_R12,Z_R12_H,
  225   Z_R11,Z_R11_H,
  226   Z_R10,Z_R10_H,
  227 
  228   Z_R9,Z_R9_H,
  229   Z_R8,Z_R8_H,
  230   Z_R7,Z_R7_H,
  231 
  232   Z_R1,Z_R1_H,
  233   Z_R0,Z_R0_H,
  234 
  235   // argument registers
  236   Z_R6,Z_R6_H,
  237   Z_R5,Z_R5_H,
  238   Z_R4,Z_R4_H,
  239   Z_R3,Z_R3_H,
  240   Z_R2,Z_R2_H,
  241 
  242   // special registers
  243   Z_R14,Z_R14_H,
  244   Z_R15,Z_R15_H
  245 );
  246 
  247 alloc_class chunk1(
  248   // Chunk1 contains *all* 64 floating-point registers halves.
  249 
  250   Z_F15,Z_F15_H,
  251   Z_F14,Z_F14_H,
  252   Z_F13,Z_F13_H,
  253   Z_F12,Z_F12_H,
  254   Z_F11,Z_F11_H,
  255   Z_F10,Z_F10_H,
  256   Z_F9,Z_F9_H,
  257   Z_F8,Z_F8_H,
  258   // scratch register
  259   Z_F7,Z_F7_H,
  260   Z_F5,Z_F5_H,
  261   Z_F3,Z_F3_H,
  262   Z_F1,Z_F1_H,
  263   // argument registers
  264   Z_F6,Z_F6_H,
  265   Z_F4,Z_F4_H,
  266   Z_F2,Z_F2_H,
  267   Z_F0,Z_F0_H
  268 );
  269 
  270 alloc_class chunk2(
  271   Z_CR
  272 );
  273 
  274 
  275 //-------Architecture Description Register Classes-----------------------
  276 
  277 // Several register classes are automatically defined based upon
  278 // information in this architecture description.
  279 
  280 // 1) reg_class inline_cache_reg           (as defined in frame section)
  281 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
  282 
  283 // Integer Register Classes
  284 reg_class z_int_reg(
  285 /*Z_R0*/              // R0
  286 /*Z_R1*/
  287   Z_R2,
  288   Z_R3,
  289   Z_R4,
  290   Z_R5,
  291   Z_R6,
  292   Z_R7,
  293 /*Z_R8,*/             // Z_thread
  294   Z_R9,
  295   Z_R10,
  296   Z_R11,
  297   Z_R12,
  298   Z_R13
  299 /*Z_R14*/             // return_pc
  300 /*Z_R15*/             // SP
  301 );
  302 
  303 reg_class z_no_odd_int_reg(
  304 /*Z_R0*/              // R0
  305 /*Z_R1*/
  306   Z_R2,
  307   Z_R3,
  308   Z_R4,
  309 /*Z_R5,*/             // odd part of fix register pair
  310   Z_R6,
  311   Z_R7,
  312 /*Z_R8,*/             // Z_thread
  313   Z_R9,
  314   Z_R10,
  315   Z_R11,
  316   Z_R12,
  317   Z_R13
  318 /*Z_R14*/             // return_pc
  319 /*Z_R15*/             // SP
  320 );
  321 
  322 reg_class z_no_arg_int_reg(
  323 /*Z_R0*/              // R0
  324 /*Z_R1*/              // scratch
  325 /*Z_R2*/
  326 /*Z_R3*/
  327 /*Z_R4*/
  328 /*Z_R5*/
  329 /*Z_R6*/
  330   Z_R7,
  331 /*Z_R8*/              // Z_thread
  332   Z_R9,
  333   Z_R10,
  334   Z_R11,
  335   Z_R12,
  336   Z_R13
  337 /*Z_R14*/             // return_pc
  338 /*Z_R15*/             // SP
  339 );
  340 
  341 reg_class z_rarg1_int_reg(Z_R2);
  342 reg_class z_rarg2_int_reg(Z_R3);
  343 reg_class z_rarg3_int_reg(Z_R4);
  344 reg_class z_rarg4_int_reg(Z_R5);
  345 reg_class z_rarg5_int_reg(Z_R6);
  346 
  347 // Pointer Register Classes
  348 
  349 // 64-bit build means 64-bit pointers means hi/lo pairs.
  350 
  351 reg_class z_rarg5_ptrN_reg(Z_R6);
  352 
  353 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
  354 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
  355 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
  356 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
  357 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
  358 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
  359 
  360 reg_class z_ptr_reg(
  361 /*Z_R0_H,Z_R0*/     // R0
  362 /*Z_R1_H,Z_R1*/
  363   Z_R2_H,Z_R2,
  364   Z_R3_H,Z_R3,
  365   Z_R4_H,Z_R4,
  366   Z_R5_H,Z_R5,
  367   Z_R6_H,Z_R6,
  368   Z_R7_H,Z_R7,
  369 /*Z_R8_H,Z_R8,*/    // Z_thread
  370   Z_R9_H,Z_R9,
  371   Z_R10_H,Z_R10,
  372   Z_R11_H,Z_R11,
  373   Z_R12_H,Z_R12,
  374   Z_R13_H,Z_R13
  375 /*Z_R14_H,Z_R14*/   // return_pc
  376 /*Z_R15_H,Z_R15*/   // SP
  377 );
  378 
  379 reg_class z_lock_ptr_reg(
  380 /*Z_R0_H,Z_R0*/     // R0
  381 /*Z_R1_H,Z_R1*/
  382   Z_R2_H,Z_R2,
  383   Z_R3_H,Z_R3,
  384   Z_R4_H,Z_R4,
  385 /*Z_R5_H,Z_R5,*/
  386 /*Z_R6_H,Z_R6,*/
  387   Z_R7_H,Z_R7,
  388 /*Z_R8_H,Z_R8,*/    // Z_thread
  389   Z_R9_H,Z_R9,
  390   Z_R10_H,Z_R10,
  391   Z_R11_H,Z_R11,
  392   Z_R12_H,Z_R12,
  393   Z_R13_H,Z_R13
  394 /*Z_R14_H,Z_R14*/   // return_pc
  395 /*Z_R15_H,Z_R15*/   // SP
  396 );
  397 
  398 reg_class z_no_arg_ptr_reg(
  399 /*Z_R0_H,Z_R0*/        // R0
  400 /*Z_R1_H,Z_R1*/        // scratch
  401 /*Z_R2_H,Z_R2*/
  402 /*Z_R3_H,Z_R3*/
  403 /*Z_R4_H,Z_R4*/
  404 /*Z_R5_H,Z_R5*/
  405 /*Z_R6_H,Z_R6*/
  406   Z_R7_H, Z_R7,
  407 /*Z_R8_H,Z_R8*/        // Z_thread
  408   Z_R9_H,Z_R9,
  409   Z_R10_H,Z_R10,
  410   Z_R11_H,Z_R11,
  411   Z_R12_H,Z_R12,
  412   Z_R13_H,Z_R13
  413 /*Z_R14_H,Z_R14*/      // return_pc
  414 /*Z_R15_H,Z_R15*/      // SP
  415 );
  416 
  417 // Special class for storeP instructions, which can store SP or RPC to
  418 // TLS. (Note: Do not generalize this to "any_reg". If you add
  419 // another register, such as FP, to this mask, the allocator may try
  420 // to put a temp in it.)
  421 // Register class for memory access base registers,
  422 // This class is a superset of z_ptr_reg including Z_thread.
  423 reg_class z_memory_ptr_reg(
  424 /*Z_R0_H,Z_R0*/     // R0
  425 /*Z_R1_H,Z_R1*/
  426   Z_R2_H,Z_R2,
  427   Z_R3_H,Z_R3,
  428   Z_R4_H,Z_R4,
  429   Z_R5_H,Z_R5,
  430   Z_R6_H,Z_R6,
  431   Z_R7_H,Z_R7,
  432   Z_R8_H,Z_R8,      // Z_thread
  433   Z_R9_H,Z_R9,
  434   Z_R10_H,Z_R10,
  435   Z_R11_H,Z_R11,
  436   Z_R12_H,Z_R12,
  437   Z_R13_H,Z_R13
  438 /*Z_R14_H,Z_R14*/   // return_pc
  439 /*Z_R15_H,Z_R15*/   // SP
  440 );
  441 
  442 // Other special pointer regs.
  443 reg_class z_r1_regP(Z_R1_H,Z_R1);
  444 reg_class z_r9_regP(Z_R9_H,Z_R9);
  445 
  446 
  447 // Long Register Classes
  448 
  449 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
  450 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
  451 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
  452 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
  453 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
  454 
  455 // Longs in 1 register. Aligned adjacent hi/lo pairs.
  456 reg_class z_long_reg(
  457 /*Z_R0_H,Z_R0*/     // R0
  458 /*Z_R1_H,Z_R1*/
  459   Z_R2_H,Z_R2,
  460   Z_R3_H,Z_R3,
  461   Z_R4_H,Z_R4,
  462   Z_R5_H,Z_R5,
  463   Z_R6_H,Z_R6,
  464   Z_R7_H,Z_R7,
  465 /*Z_R8_H,Z_R8,*/    // Z_thread
  466   Z_R9_H,Z_R9,
  467   Z_R10_H,Z_R10,
  468   Z_R11_H,Z_R11,
  469   Z_R12_H,Z_R12,
  470   Z_R13_H,Z_R13
  471 /*Z_R14_H,Z_R14,*/  // return_pc
  472 /*Z_R15_H,Z_R15*/   // SP
  473 );
  474 
  475 // z_long_reg without even registers
  476 reg_class z_long_odd_reg(
  477 /*Z_R0_H,Z_R0*/     // R0
  478 /*Z_R1_H,Z_R1*/
  479   Z_R3_H,Z_R3,
  480   Z_R5_H,Z_R5,
  481   Z_R7_H,Z_R7,
  482   Z_R9_H,Z_R9,
  483   Z_R11_H,Z_R11,
  484   Z_R13_H,Z_R13
  485 /*Z_R14_H,Z_R14,*/  // return_pc
  486 /*Z_R15_H,Z_R15*/   // SP
  487 );
  488 
  489 // Special Class for Condition Code Flags Register
  490 
  491 reg_class z_condition_reg(
  492   Z_CR
  493 );
  494 
  495 // Scratch register for late profiling. Callee saved.
  496 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
  497 
  498 
  499 // Float Register Classes
  500 
  501 reg_class z_flt_reg(
  502   Z_F0,
  503 /*Z_F1,*/ // scratch
  504   Z_F2,
  505   Z_F3,
  506   Z_F4,
  507   Z_F5,
  508   Z_F6,
  509   Z_F7,
  510   Z_F8,
  511   Z_F9,
  512   Z_F10,
  513   Z_F11,
  514   Z_F12,
  515   Z_F13,
  516   Z_F14,
  517   Z_F15
  518 );
  519 reg_class z_rscratch1_flt_reg(Z_F1);
  520 
  521 // Double precision float registers have virtual `high halves' that
  522 // are needed by the allocator.
  523 reg_class z_dbl_reg(
  524   Z_F0,Z_F0_H,
  525 /*Z_F1,Z_F1_H,*/ // scratch
  526   Z_F2,Z_F2_H,
  527   Z_F3,Z_F3_H,
  528   Z_F4,Z_F4_H,
  529   Z_F5,Z_F5_H,
  530   Z_F6,Z_F6_H,
  531   Z_F7,Z_F7_H,
  532   Z_F8,Z_F8_H,
  533   Z_F9,Z_F9_H,
  534   Z_F10,Z_F10_H,
  535   Z_F11,Z_F11_H,
  536   Z_F12,Z_F12_H,
  537   Z_F13,Z_F13_H,
  538   Z_F14,Z_F14_H,
  539   Z_F15,Z_F15_H
  540 );
  541 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
  542 
  543 %}
  544 
  545 //----------DEFINITION BLOCK---------------------------------------------------
  546 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
  547 // Current support includes integer values in the range [0, 0x7FFFFFFF].
  548 // Format:
  549 //        int_def  <name>         (<int_value>, <expression>);
  550 // Generated Code in ad_<arch>.hpp
  551 //        #define  <name>   (<expression>)
  552 //        // value == <int_value>
  553 // Generated code in ad_<arch>.cpp adlc_verification()
  554 //        assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  555 //
  556 definitions %{
  557   // The default cost (of an ALU instruction).
  558   int_def DEFAULT_COST      (   100,     100);
  559   int_def DEFAULT_COST_LOW  (    80,      80);
  560   int_def DEFAULT_COST_HIGH (   120,     120);
  561   int_def HUGE_COST         (1000000, 1000000);
  562 
  563   // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
  564   int_def ALU_REG_COST      (   100, DEFAULT_COST);
  565   int_def ALU_MEMORY_COST   (   150,          150);
  566 
  567   // Memory refs are twice as expensive as run-of-the-mill.
  568   int_def MEMORY_REF_COST_HI (   220, 2 * DEFAULT_COST+20);
  569   int_def MEMORY_REF_COST    (   200, 2 * DEFAULT_COST);
  570   int_def MEMORY_REF_COST_LO (   180, 2 * DEFAULT_COST-20);
  571 
  572   // Branches are even more expensive.
  573   int_def BRANCH_COST       (   300, DEFAULT_COST * 3);
  574   int_def CALL_COST         (   300, DEFAULT_COST * 3);
  575 %}
  576 
  577 source %{
  578 
  579 #ifdef PRODUCT
  580 #define BLOCK_COMMENT(str)
  581 #define BIND(label)        __ bind(label)
  582 #else
  583 #define BLOCK_COMMENT(str) __ block_comment(str)
  584 #define BIND(label)        __ bind(label); BLOCK_COMMENT(#label ":")
  585 #endif
  586 
  587 #define __ _masm.
  588 
  589 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ?  4 : 6
  590 #define Z_DISP3_SIZE 6
  591 
  592 // Tertiary op of a LoadP or StoreP encoding.
  593 #define REGP_OP true
  594 
  595 // Given a register encoding, produce an Integer Register object.
  596 static Register reg_to_register_object(int register_encoding);
  597 
  598 // ****************************************************************************
  599 
  600 // REQUIRED FUNCTIONALITY
  601 
  602 // !!!!! Special hack to get all type of calls to specify the byte offset
  603 //       from the start of the call to the point where the return address
  604 //       will point.
  605 
  606 void PhaseOutput::pd_perform_mach_node_analysis() {
  607 }
  608 
  609 int MachNode::pd_alignment_required() const {
  610   return 1;
  611 }
  612 
  613 int MachNode::compute_padding(int current_offset) const {
  614   return 0;
  615 }
  616 
  617 int MachCallStaticJavaNode::ret_addr_offset() {
  618   if (_method) {
  619     return 8;
  620   } else {
  621     return MacroAssembler::call_far_patchable_ret_addr_offset();
  622   }
  623 }
  624 
  625 int MachCallDynamicJavaNode::ret_addr_offset() {
  626   // Consider size of receiver type profiling (C2 tiers).
  627   int profile_receiver_type_size = 0;
  628 
  629   int vtable_index = this->_vtable_index;
  630   if (vtable_index == -4) {
  631     return 14 + profile_receiver_type_size;
  632   } else {
  633     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
  634     return 36 + profile_receiver_type_size;
  635   }
  636 }
  637 
  638 int MachCallRuntimeNode::ret_addr_offset() {
  639   return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
  640 }
  641 
  642 int MachCallNativeNode::ret_addr_offset() {
  643   Unimplemented();
  644   return -1;
  645 }
  646 
  647 // Compute padding required for nodes which need alignment
  648 //
  649 // The addresses of the call instructions needs to be 4-byte aligned to
  650 // ensure that they don't span a cache line so that they are atomically patchable.
  651 // The actual calls get emitted at different offsets within the node emitters.
  652 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
  653 
  654 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
  655   return (0 - current_offset) & 2;
  656 }
  657 
  658 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
  659   return (6 - current_offset) & 2;
  660 }
  661 
  662 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
  663   return (12 - current_offset) & 2;
  664 }
  665 
  666 int CallLeafDirectNode::compute_padding(int current_offset) const {
  667   return (12 - current_offset) & 2;
  668 }
  669 
  670 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
  671   return (12 - current_offset) & 2;
  672 }
  673 
  674 void emit_nop(CodeBuffer &cbuf) {
  675   C2_MacroAssembler _masm(&cbuf);
  676   __ z_nop();
  677 }
  678 
  679 // Emit an interrupt that is caught by the debugger (for debugging compiler).
  680 void emit_break(CodeBuffer &cbuf) {
  681   C2_MacroAssembler _masm(&cbuf);
  682   __ z_illtrap();
  683 }
  684 
  685 #if !defined(PRODUCT)
  686 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
  687   os->print("TA");
  688 }
  689 #endif
  690 
  691 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  692   emit_break(cbuf);
  693 }
  694 
  695 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
  696   return MachNode::size(ra_);
  697 }
  698 
  699 static inline void z_emit16(CodeBuffer &cbuf, long value) {
  700   // 32bit instructions may become sign extended.
  701   assert(value >= 0, "unintended sign extension (int->long)");
  702   assert(value < (1L << 16), "instruction too large");
  703   *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
  704   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
  705 }
  706 
  707 static inline void z_emit32(CodeBuffer &cbuf, long value) {
  708   // 32bit instructions may become sign extended.
  709   assert(value < (1L << 32), "instruction too large");
  710   *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
  711   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
  712 }
  713 
  714 static inline void z_emit48(CodeBuffer &cbuf, long value) {
  715   // 32bit instructions may become sign extended.
  716   assert(value >= 0, "unintended sign extension (int->long)");
  717   assert(value < (1L << 48), "instruction too large");
  718   value = value<<16;
  719   memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
  720   cbuf.set_insts_end(cbuf.insts_end() + 6);
  721 }
  722 
  723 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
  724   if (value < 0) {
  725     // There obviously has been an unintended sign extension (int->long). Revert it.
  726     value = (long)((unsigned long)((unsigned int)value));
  727   }
  728 
  729   if (value < (1L << 16)) { // 2-byte instruction
  730     z_emit16(cbuf, value);
  731     return 2;
  732   }
  733 
  734   if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
  735     z_emit32(cbuf, value);
  736     return 4;
  737   }
  738 
  739   // 6-byte instruction, probably unaligned store.
  740   z_emit48(cbuf, value);
  741   return 6;
  742 }
  743 
  744 // Check effective address (at runtime) for required alignment.
  745 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
  746   C2_MacroAssembler _masm(&cbuf);
  747 
  748   __ z_lay(Z_R0, disp, index, base);
  749   __ z_nill(Z_R0, alignment-1);
  750   __ z_brc(Assembler::bcondEqual, +3);
  751   __ z_illtrap();
  752 }
  753 
  754 int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
  755                     PhaseRegAlloc* ra_, bool is_native_call = false) {
  756   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
  757   address old_mark = __ inst_mark();
  758   unsigned int start_off = __ offset();
  759 
  760   if (is_native_call) {
  761     ShouldNotReachHere();
  762   }
  763 
  764   if (rtype == relocInfo::runtime_call_w_cp_type) {
  765     assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
  766     address call_addr = __ call_c_opt((address)entry_point);
  767     if (call_addr == NULL) {
  768       Compile::current()->env()->record_out_of_memory_failure();
  769       return -1;
  770     }
  771   } else {
  772     assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
  773            rtype == relocInfo::static_call_type, "unexpected rtype");
  774     __ relocate(rtype);
  775     // BRASL must be prepended with a nop to identify it in the instruction stream.
  776     __ z_nop();
  777     __ z_brasl(Z_R14, (address)entry_point);
  778   }
  779 
  780   unsigned int ret_off = __ offset();
  781 
  782   return (ret_off - start_off);
  783 }
  784 
  785 static int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
  786   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
  787   address old_mark = __ inst_mark();
  788   unsigned int start_off = __ offset();
  789 
  790   relocInfo::relocType rtype = rspec.type();
  791   assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
  792          "unexpected rtype");
  793 
  794   __ relocate(rspec);
  795   __ z_nop();
  796   __ z_brasl(Z_R14, (address)entry_point);
  797 
  798   unsigned int ret_off = __ offset();
  799 
  800   return (ret_off - start_off);
  801 }
  802 
  803 //=============================================================================
  804 
  805 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
  806 int ConstantTable::calculate_table_base_offset() const {
  807   return 0;  // absolute addressing, no offset
  808 }
  809 
  810 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
  811 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
  812   ShouldNotReachHere();
  813 }
  814 
  815 // Even with PC-relative TOC addressing, we still need this node.
  816 // Float loads/stores do not support PC-relative addresses.
  817 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
  818   C2_MacroAssembler _masm(&cbuf);
  819   Register Rtoc = as_Register(ra_->get_encode(this));
  820   __ load_toc(Rtoc);
  821 }
  822 
  823 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
  824   // PCrelative TOC access.
  825   return 6;   // sizeof(LARL)
  826 }
  827 
  828 #if !defined(PRODUCT)
  829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  830   Register r = as_Register(ra_->get_encode(this));
  831   st->print("LARL    %s,&constant_pool # MachConstantBaseNode", r->name());
  832 }
  833 #endif
  834 
  835 //=============================================================================
  836 
  837 #if !defined(PRODUCT)
  838 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
  839   Compile* C = ra_->C;
  840   st->print_cr("--- MachPrologNode ---");
  841   st->print("\t");
  842   for (int i = 0; i < OptoPrologueNops; i++) {
  843     st->print_cr("NOP"); st->print("\t");
  844   }
  845 
  846   if (VerifyThread) {
  847     st->print_cr("Verify_Thread");
  848     st->print("\t");
  849   }
  850 
  851   long framesize = C->output()->frame_size_in_bytes();
  852   int bangsize   = C->output()->bang_size_in_bytes();
  853 
  854   // Calls to C2R adapters often do not accept exceptional returns.
  855   // We require that their callers must bang for them. But be
  856   // careful, because some VM calls (such as call site linkage) can
  857   // use several kilobytes of stack. But the stack safety zone should
  858   // account for that. See bugs 4446381, 4468289, 4497237.
  859   if (C->output()->need_stack_bang(bangsize)) {
  860     st->print_cr("# stack bang"); st->print("\t");
  861   }
  862   st->print_cr("push_frame %d", (int)-framesize);
  863   st->print("\t");
  864 }
  865 #endif
  866 
  867 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  868   Compile* C = ra_->C;
  869   C2_MacroAssembler _masm(&cbuf);
  870 
  871   __ verify_thread();
  872 
  873   size_t framesize = C->output()->frame_size_in_bytes();
  874   size_t bangsize  = C->output()->bang_size_in_bytes();
  875 
  876   assert(framesize % wordSize == 0, "must preserve wordSize alignment");
  877 
  878   if (C->clinit_barrier_on_entry()) {
  879     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
  880 
  881     Label L_skip_barrier;
  882     Register klass = Z_R1_scratch;
  883 
  884     // Notify OOP recorder (don't need the relocation)
  885     AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
  886     __ load_const_optimized(klass, md.value());
  887     __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
  888 
  889     __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
  890     __ z_br(klass);
  891 
  892     __ bind(L_skip_barrier);
  893   }
  894 
  895   // Calls to C2R adapters often do not accept exceptional returns.
  896   // We require that their callers must bang for them. But be
  897   // careful, because some VM calls (such as call site linkage) can
  898   // use several kilobytes of stack. But the stack safety zone should
  899   // account for that. See bugs 4446381, 4468289, 4497237.
  900   if (C->output()->need_stack_bang(bangsize)) {
  901     __ generate_stack_overflow_check(bangsize);
  902   }
  903 
  904   assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
  905   __ save_return_pc();
  906 
  907   // The z/Architecture abi is already accounted for in `framesize' via the
  908   // 'out_preserve_stack_slots' declaration.
  909   __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
  910 
  911   if (C->has_mach_constant_base_node()) {
  912     // NOTE: We set the table base offset here because users might be
  913     // emitted before MachConstantBaseNode.
  914     ConstantTable& constant_table = C->output()->constant_table();
  915     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
  916   }
  917 }
  918 
  919 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
  920   // Variable size. Determine dynamically.
  921   return MachNode::size(ra_);
  922 }
  923 
  924 int MachPrologNode::reloc() const {
  925   // Return number of relocatable values contained in this instruction.
  926   return 1; // One reloc entry for load_const(toc).
  927 }
  928 
  929 //=============================================================================
  930 
  931 #if !defined(PRODUCT)
  932 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
  933   os->print_cr("epilog");
  934   os->print("\t");
  935   if (do_polling() && ra_->C->is_method_compilation()) {
  936     os->print_cr("load_from_polling_page Z_R1_scratch");
  937     os->print("\t");
  938   }
  939 }
  940 #endif
  941 
  942 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  943   C2_MacroAssembler _masm(&cbuf);
  944   Compile* C = ra_->C;
  945   __ verify_thread();
  946 
  947   // If this does safepoint polling, then do it here.
  948   bool need_polling = do_polling() && C->is_method_compilation();
  949 
  950   // Pop frame, restore return_pc, and all stuff needed by interpreter.
  951   int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
  952   __ pop_frame_restore_retPC(frame_size_in_bytes);
  953 
  954   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
  955     __ reserved_stack_check(Z_R14);
  956   }
  957 
  958   // Touch the polling page.
  959   if (need_polling) {
  960     __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
  961     // We need to mark the code position where the load from the safepoint
  962     // polling page was emitted as relocInfo::poll_return_type here.
  963     __ relocate(relocInfo::poll_return_type);
  964     __ load_from_polling_page(Z_R1_scratch);
  965   }
  966 }
  967 
  968 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
  969   // Variable size. determine dynamically.
  970   return MachNode::size(ra_);
  971 }
  972 
  973 int MachEpilogNode::reloc() const {
  974   // Return number of relocatable values contained in this instruction.
  975   return 1; // One for load_from_polling_page.
  976 }
  977 
  978 const Pipeline * MachEpilogNode::pipeline() const {
  979   return MachNode::pipeline_class();
  980 }
  981 
  982 //=============================================================================
  983 
  984 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
  985 enum RC { rc_bad, rc_int, rc_float, rc_stack };
  986 
  987 static enum RC rc_class(OptoReg::Name reg) {
  988   // Return the register class for the given register. The given register
  989   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
  990   // enumeration in adGlobals_s390.hpp.
  991 
  992   if (reg == OptoReg::Bad) {
  993     return rc_bad;
  994   }
  995 
  996   // We have 32 integer register halves, starting at index 0.
  997   if (reg < 32) {
  998     return rc_int;
  999   }
 1000 
 1001   // We have 32 floating-point register halves, starting at index 32.
 1002   if (reg < 32+32) {
 1003     return rc_float;
 1004   }
 1005 
 1006   // Between float regs & stack are the flags regs.
 1007   assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
 1008   return rc_stack;
 1009 }
 1010 
 1011 // Returns size as obtained from z_emit_instr.
 1012 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
 1013                                    int reg, int offset, bool do_print, outputStream *os) {
 1014 
 1015   if (cbuf) {
 1016     if (opcode > (1L<<32)) {
 1017       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
 1018                          Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
 1019     } else {
 1020       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
 1021                          Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
 1022     }
 1023   }
 1024 
 1025 #if !defined(PRODUCT)
 1026   if (do_print) {
 1027     os->print("%s    %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
 1028   }
 1029 #endif
 1030   return (opcode > (1L << 32)) ? 6 : 4;
 1031 }
 1032 
 1033 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
 1034   if (cbuf) {
 1035     C2_MacroAssembler _masm(cbuf);
 1036     __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
 1037   }
 1038 
 1039 #if !defined(PRODUCT)
 1040   else if (do_print) {
 1041     os->print("MVC     %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
 1042   }
 1043 #endif
 1044 
 1045   return 6;
 1046 }
 1047 
 1048 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
 1049   // Get registers to move.
 1050   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1051   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1052   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1053   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1054 
 1055   enum RC src_hi_rc = rc_class(src_hi);
 1056   enum RC src_lo_rc = rc_class(src_lo);
 1057   enum RC dst_hi_rc = rc_class(dst_hi);
 1058   enum RC dst_lo_rc = rc_class(dst_lo);
 1059 
 1060   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1061   bool is64 = (src_hi_rc != rc_bad);
 1062   assert(!is64 ||
 1063          ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
 1064          "expected aligned-adjacent pairs");
 1065 
 1066   // Generate spill code!
 1067 
 1068   if (src_lo == dst_lo && src_hi == dst_hi) {
 1069     return 0;            // Self copy, no move.
 1070   }
 1071 
 1072   int  src_offset = ra_->reg2offset(src_lo);
 1073   int  dst_offset = ra_->reg2offset(dst_lo);
 1074   bool print = !do_size;
 1075   bool src12 = Immediate::is_uimm12(src_offset);
 1076   bool dst12 = Immediate::is_uimm12(dst_offset);
 1077 
 1078   const char   *mnemo = NULL;
 1079   unsigned long opc = 0;
 1080 
 1081   // Memory->Memory Spill. Use Z_R0 to hold the value.
 1082   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1083 
 1084     assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
 1085            "expected same type of move for high parts");
 1086 
 1087     if (src12 && dst12) {
 1088       return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
 1089     }
 1090 
 1091     int r0 = Z_R0_num;
 1092     if (is64) {
 1093       return z_ld_st_helper(cbuf, "LG  ", LG_ZOPC, r0, src_offset, print, os) +
 1094              z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
 1095     }
 1096 
 1097     return z_ld_st_helper(cbuf, "LY   ", LY_ZOPC, r0, src_offset, print, os) +
 1098            z_ld_st_helper(cbuf, "STY  ", STY_ZOPC, r0, dst_offset, print, os);
 1099   }
 1100 
 1101   // Check for float->int copy. Requires a trip through memory.
 1102   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
 1103     Unimplemented();  // Unsafe, do not remove!
 1104   }
 1105 
 1106   // Check for integer reg-reg copy.
 1107   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
 1108     if (cbuf) {
 1109       C2_MacroAssembler _masm(cbuf);
 1110       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
 1111       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
 1112       __ z_lgr(Rdst, Rsrc);
 1113       return 4;
 1114     }
 1115 #if !defined(PRODUCT)
 1116     // else
 1117     if (print) {
 1118       os->print("LGR     %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 1119     }
 1120 #endif
 1121     return 4;
 1122   }
 1123 
 1124   // Check for integer store.
 1125   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
 1126     assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
 1127            "expected same type of move for high parts");
 1128 
 1129     if (is64) {
 1130       return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
 1131     }
 1132 
 1133     // else
 1134     mnemo = dst12 ? "ST  " : "STY ";
 1135     opc = dst12 ? ST_ZOPC : STY_ZOPC;
 1136 
 1137     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1138   }
 1139 
 1140   // Check for integer load
 1141   // Always load cOops zero-extended. That doesn't hurt int loads.
 1142   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
 1143 
 1144     assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
 1145            "expected same type of move for high parts");
 1146 
 1147     mnemo = is64 ? "LG  " : "LLGF";
 1148     opc = is64 ? LG_ZOPC : LLGF_ZOPC;
 1149 
 1150     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1151   }
 1152 
 1153   // Check for float reg-reg copy.
 1154   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
 1155     if (cbuf) {
 1156       C2_MacroAssembler _masm(cbuf);
 1157       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
 1158       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
 1159       __ z_ldr(Rdst, Rsrc);
 1160       return 2;
 1161     }
 1162 #if !defined(PRODUCT)
 1163     // else
 1164     if (print) {
 1165       os->print("LDR      %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 1166     }
 1167 #endif
 1168     return 2;
 1169   }
 1170 
 1171   // Check for float store.
 1172   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
 1173     assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
 1174            "expected same type of move for high parts");
 1175 
 1176     if (is64) {
 1177       mnemo = dst12 ? "STD  " : "STDY ";
 1178       opc = dst12 ? STD_ZOPC : STDY_ZOPC;
 1179       return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1180     }
 1181     // else
 1182 
 1183     mnemo = dst12 ? "STE  " : "STEY ";
 1184     opc = dst12 ? STE_ZOPC : STEY_ZOPC;
 1185     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1186   }
 1187 
 1188   // Check for float load.
 1189   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
 1190     assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
 1191            "expected same type of move for high parts");
 1192 
 1193     if (is64) {
 1194       mnemo = src12 ? "LD   " : "LDY  ";
 1195       opc = src12 ? LD_ZOPC : LDY_ZOPC;
 1196       return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1197     }
 1198     // else
 1199 
 1200     mnemo = src12 ? "LE   " : "LEY  ";
 1201     opc = src12 ? LE_ZOPC : LEY_ZOPC;
 1202     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1203   }
 1204 
 1205   // --------------------------------------------------------------------
 1206   // Check for hi bits still needing moving. Only happens for misaligned
 1207   // arguments to native calls.
 1208   if (src_hi == dst_hi) {
 1209     return 0;               // Self copy, no move.
 1210   }
 1211 
 1212   assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
 1213   Unimplemented();  // Unsafe, do not remove!
 1214 
 1215   return 0; // never reached, but make the compiler shut up!
 1216 }
 1217 
 1218 #if !defined(PRODUCT)
 1219 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1220   if (ra_ && ra_->node_regs_max_index() > 0) {
 1221     implementation(NULL, ra_, false, os);
 1222   } else {
 1223     if (req() == 2 && in(1)) {
 1224       os->print("N%d = N%d\n", _idx, in(1)->_idx);
 1225     } else {
 1226       const char *c = "(";
 1227       os->print("N%d = ", _idx);
 1228       for (uint i = 1; i < req(); ++i) {
 1229         os->print("%sN%d", c, in(i)->_idx);
 1230         c = ", ";
 1231       }
 1232       os->print(")");
 1233     }
 1234   }
 1235 }
 1236 #endif
 1237 
 1238 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1239   implementation(&cbuf, ra_, false, NULL);
 1240 }
 1241 
 1242 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1243   return implementation(NULL, ra_, true, NULL);
 1244 }
 1245 
 1246 //=============================================================================
 1247 
 1248 #if !defined(PRODUCT)
 1249 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
 1250   os->print("NOP     # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
 1251 }
 1252 #endif
 1253 
 1254 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
 1255   C2_MacroAssembler _masm(&cbuf);
 1256 
 1257   int rem_space = 0;
 1258   if (!(ra_->C->output()->in_scratch_emit_size())) {
 1259     rem_space = cbuf.insts()->remaining();
 1260     if (rem_space <= _count*2 + 8) {
 1261       tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
 1262     }
 1263   }
 1264 
 1265   for (int i = 0; i < _count; i++) {
 1266     __ z_nop();
 1267   }
 1268 
 1269   if (!(ra_->C->output()->in_scratch_emit_size())) {
 1270     if (rem_space <= _count*2 + 8) {
 1271       int rem_space2 = cbuf.insts()->remaining();
 1272       tty->print_cr(", after = %d", rem_space2);
 1273     }
 1274   }
 1275 }
 1276 
 1277 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
 1278    return 2 * _count;
 1279 }
 1280 
 1281 #if !defined(PRODUCT)
 1282 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1283   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1284   if (ra_ && ra_->node_regs_max_index() > 0) {
 1285     int reg = ra_->get_reg_first(this);
 1286     os->print("ADDHI  %s, SP, %d\t//box node", Matcher::regName[reg], offset);
 1287   } else {
 1288     os->print("ADDHI  N%d = SP + %d\t// box node", _idx, offset);
 1289   }
 1290 }
 1291 #endif
 1292 
 1293 // Take care of the size function, if you make changes here!
 1294 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1295   C2_MacroAssembler _masm(&cbuf);
 1296 
 1297   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1298   int reg = ra_->get_encode(this);
 1299   __ z_lay(as_Register(reg), offset, Z_SP);
 1300 }
 1301 
 1302 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1303   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
 1304   return 6;
 1305 }
 1306 
 1307  %} // end source section
 1308 
 1309 //----------SOURCE BLOCK-------------------------------------------------------
 1310 // This is a block of C++ code which provides values, functions, and
 1311 // definitions necessary in the rest of the architecture description
 1312 
 1313 source_hpp %{
 1314 
 1315 // Header information of the source block.
 1316 // Method declarations/definitions which are used outside
 1317 // the ad-scope can conveniently be defined here.
 1318 //
 1319 // To keep related declarations/definitions/uses close together,
 1320 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 1321 
 1322 #include "oops/klass.inline.hpp"
 1323 
 1324 //--------------------------------------------------------------
 1325 // Used for optimization in Compile::Shorten_branches
 1326 //--------------------------------------------------------------
 1327 
 1328 class CallStubImpl {
 1329  public:
 1330 
 1331   // call trampolines
 1332   // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
 1333   static uint size_call_trampoline() {
 1334     return 0; // no call trampolines on this platform
 1335   }
 1336 
 1337   // call trampolines
 1338   // Number of relocations needed by a call trampoline stub.
 1339   static uint reloc_call_trampoline() {
 1340     return 0; // No call trampolines on this platform.
 1341   }
 1342 };
 1343 
 1344 %} // end source_hpp section
 1345 
 1346 source %{
 1347 
 1348 #if !defined(PRODUCT)
 1349 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1350   os->print_cr("---- MachUEPNode ----");
 1351   os->print_cr("\tTA");
 1352   os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
 1353   os->print_cr("\tBR(Z_R1)");
 1354   os->print_cr("\tTA  # pad with illtraps");
 1355   os->print_cr("\t...");
 1356   os->print_cr("\tTA");
 1357   os->print_cr("\tLTGR    Z_R2, Z_R2");
 1358   os->print_cr("\tBRU     ic_miss");
 1359 }
 1360 #endif
 1361 
 1362 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1363   C2_MacroAssembler _masm(&cbuf);
 1364   const int ic_miss_offset = 2;
 1365 
 1366   // Inline_cache contains a klass.
 1367   Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
 1368   // ARG1 is the receiver oop.
 1369   Register R2_receiver = Z_ARG1;
 1370   int      klass_offset = oopDesc::klass_offset_in_bytes();
 1371   AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
 1372   Register R1_ic_miss_stub_addr = Z_R1_scratch;
 1373 
 1374   // Null check of receiver.
 1375   // This is the null check of the receiver that actually should be
 1376   // done in the caller. It's here because in case of implicit null
 1377   // checks we get it for free.
 1378   assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
 1379          "second word in oop should not require explicit null check.");
 1380   if (!ImplicitNullChecks) {
 1381     Label valid;
 1382     if (VM_Version::has_CompareBranch()) {
 1383       __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
 1384     } else {
 1385       __ z_ltgr(R2_receiver, R2_receiver);
 1386       __ z_bre(valid);
 1387     }
 1388     // The ic_miss_stub will handle the null pointer exception.
 1389     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
 1390     __ z_br(R1_ic_miss_stub_addr);
 1391     __ bind(valid);
 1392   }
 1393 
 1394   // Check whether this method is the proper implementation for the class of
 1395   // the receiver (ic miss check).
 1396   {
 1397     Label valid;
 1398     // Compare cached class against klass from receiver.
 1399     // This also does an implicit null check!
 1400     __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
 1401     __ z_bre(valid);
 1402     // The inline cache points to the wrong method. Call the
 1403     // ic_miss_stub to find the proper method.
 1404     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
 1405     __ z_br(R1_ic_miss_stub_addr);
 1406     __ bind(valid);
 1407   }
 1408 }
 1409 
 1410 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
 1411   // Determine size dynamically.
 1412   return MachNode::size(ra_);
 1413 }
 1414 
 1415 //=============================================================================
 1416 
 1417 %} // interrupt source section
 1418 
 1419 source_hpp %{ // Header information of the source block.
 1420 
 1421 class HandlerImpl {
 1422  public:
 1423 
 1424   static int emit_exception_handler(CodeBuffer &cbuf);
 1425   static int emit_deopt_handler(CodeBuffer& cbuf);
 1426 
 1427   static uint size_exception_handler() {
 1428     return NativeJump::max_instruction_size();
 1429   }
 1430 
 1431   static uint size_deopt_handler() {
 1432     return NativeCall::max_instruction_size();
 1433   }
 1434 };
 1435 
 1436 class Node::PD {
 1437 public:
 1438   enum NodeFlags {
 1439     _last_flag = Node::_last_flag
 1440   };
 1441 };
 1442 
 1443 %} // end source_hpp section
 1444 
 1445 source %{
 1446 
 1447 // This exception handler code snippet is placed after the method's
 1448 // code. It is the return point if an exception occurred. it jumps to
 1449 // the exception blob.
 1450 //
 1451 // If the method gets deoptimized, the method and this code snippet
 1452 // get patched.
 1453 //
 1454 // 1) Trampoline code gets patched into the end of this exception
 1455 //   handler. the trampoline code jumps to the deoptimization blob.
 1456 //
 1457 // 2) The return address in the method's code will get patched such
 1458 //   that it jumps to the trampoline.
 1459 //
 1460 // 3) The handler will get patched such that it does not jump to the
 1461 //   exception blob, but to an entry in the deoptimization blob being
 1462 //   aware of the exception.
 1463 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
 1464   Register temp_reg = Z_R1;
 1465   C2_MacroAssembler _masm(&cbuf);
 1466 
 1467   address base = __ start_a_stub(size_exception_handler());
 1468   if (base == NULL) {
 1469     return 0;          // CodeBuffer::expand failed
 1470   }
 1471 
 1472   int offset = __ offset();
 1473   // Use unconditional pc-relative jump with 32-bit range here.
 1474   __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
 1475   __ z_br(temp_reg);
 1476 
 1477   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1478 
 1479   __ end_a_stub();
 1480 
 1481   return offset;
 1482 }
 1483 
 1484 // Emit deopt handler code.
 1485 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
 1486   C2_MacroAssembler _masm(&cbuf);
 1487   address        base = __ start_a_stub(size_deopt_handler());
 1488 
 1489   if (base == NULL) {
 1490     return 0;  // CodeBuffer::expand failed
 1491   }
 1492 
 1493   int offset = __ offset();
 1494 
 1495   // Size_deopt_handler() must be exact on zarch, so for simplicity
 1496   // we do not use load_const_opt here.
 1497   __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
 1498   __ call(Z_R1);
 1499   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
 1500 
 1501   __ end_a_stub();
 1502   return offset;
 1503 }
 1504 
 1505 //=============================================================================
 1506 
 1507 
 1508 // Given a register encoding, produce an Integer Register object.
 1509 static Register reg_to_register_object(int register_encoding) {
 1510   assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
 1511   return as_Register(register_encoding);
 1512 }
 1513 
 1514 const bool Matcher::match_rule_supported(int opcode) {
 1515   if (!has_match_rule(opcode)) {
 1516     return false; // no match rule present
 1517   }
 1518 
 1519   switch (opcode) {
 1520     case Op_ReverseBytesI:
 1521     case Op_ReverseBytesL:
 1522       return UseByteReverseInstruction;
 1523     case Op_PopCountI:
 1524     case Op_PopCountL:
 1525       // PopCount supported by H/W from z/Architecture G5 (z196) on.
 1526       return (UsePopCountInstruction && VM_Version::has_PopCount());
 1527   }
 1528 
 1529   return true; // Per default match rules are supported.
 1530 }
 1531 
 1532 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1533   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1534     return false;
 1535   }
 1536   return true; // Per default match rules are supported.
 1537 }
 1538 
 1539 const RegMask* Matcher::predicate_reg_mask(void) {
 1540   return NULL;
 1541 }
 1542 
 1543 const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1544   return NULL;
 1545 }
 1546 
 1547 // Vector calling convention not yet implemented.
 1548 const bool Matcher::supports_vector_calling_convention(void) {
 1549   return false;
 1550 }
 1551 
 1552 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1553   Unimplemented();
 1554   return OptoRegPair(0, 0);
 1555 }
 1556 
 1557 //----------SUPERWORD HELPERS----------------------------------------
 1558 
 1559 // Vector width in bytes.
 1560 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1561   assert(MaxVectorSize == 8, "");
 1562   return 8;
 1563 }
 1564 
 1565 // Vector ideal reg.
 1566 const uint Matcher::vector_ideal_reg(int size) {
 1567   assert(MaxVectorSize == 8 && size == 8, "");
 1568   return Op_RegL;
 1569 }
 1570 
 1571 // Limits on vector size (number of elements) loaded into vector.
 1572 const int Matcher::max_vector_size(const BasicType bt) {
 1573   assert(is_java_primitive(bt), "only primitive type vectors");
 1574   return vector_width_in_bytes(bt)/type2aelembytes(bt);
 1575 }
 1576 
 1577 const int Matcher::min_vector_size(const BasicType bt) {
 1578   return max_vector_size(bt); // Same as max.
 1579 }
 1580 
 1581 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1582   return -1;
 1583 }
 1584 
 1585 // RETURNS: whether this branch offset is short enough that a short
 1586 // branch can be used.
 1587 //
 1588 // If the platform does not provide any short branch variants, then
 1589 // this method should return `false' for offset 0.
 1590 //
 1591 // `Compile::Fill_buffer' will decide on basis of this information
 1592 // whether to do the pass `Compile::Shorten_branches' at all.
 1593 //
 1594 // And `Compile::Shorten_branches' will decide on basis of this
 1595 // information whether to replace particular branch sites by short
 1596 // ones.
 1597 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1598   // On zarch short branches use a 16 bit signed immediate that
 1599   // is the pc-relative offset in halfword (= 2 bytes) units.
 1600   return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
 1601 }
 1602 
 1603 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1604   ShouldNotReachHere(); // generic vector operands not supported
 1605   return NULL;
 1606 }
 1607 
 1608 bool Matcher::is_reg2reg_move(MachNode* m) {
 1609   ShouldNotReachHere();  // generic vector operands not supported
 1610   return false;
 1611 }
 1612 
 1613 bool Matcher::is_generic_vector(MachOper* opnd)  {
 1614   ShouldNotReachHere();  // generic vector operands not supported
 1615   return false;
 1616 }
 1617 
 1618 // Constants for c2c and c calling conventions.
 1619 
 1620 const MachRegisterNumbers z_iarg_reg[5] = {
 1621   Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
 1622 };
 1623 
 1624 const MachRegisterNumbers z_farg_reg[4] = {
 1625   Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
 1626 };
 1627 
 1628 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
 1629 
 1630 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
 1631 
 1632 // Return whether or not this register is ever used as an argument. This
 1633 // function is used on startup to build the trampoline stubs in generateOptoStub.
 1634 // Registers not mentioned will be killed by the VM call in the trampoline, and
 1635 // arguments in those registers not be available to the callee.
 1636 bool Matcher::can_be_java_arg(int reg) {
 1637   // We return true for all registers contained in z_iarg_reg[] and
 1638   // z_farg_reg[] and their virtual halves.
 1639   // We must include the virtual halves in order to get STDs and LDs
 1640   // instead of STWs and LWs in the trampoline stubs.
 1641 
 1642   if (reg == Z_R2_num || reg == Z_R2_H_num ||
 1643       reg == Z_R3_num || reg == Z_R3_H_num ||
 1644       reg == Z_R4_num || reg == Z_R4_H_num ||
 1645       reg == Z_R5_num || reg == Z_R5_H_num ||
 1646       reg == Z_R6_num || reg == Z_R6_H_num) {
 1647     return true;
 1648   }
 1649 
 1650   if (reg == Z_F0_num || reg == Z_F0_H_num ||
 1651       reg == Z_F2_num || reg == Z_F2_H_num ||
 1652       reg == Z_F4_num || reg == Z_F4_H_num ||
 1653       reg == Z_F6_num || reg == Z_F6_H_num) {
 1654     return true;
 1655   }
 1656 
 1657   return false;
 1658 }
 1659 
 1660 bool Matcher::is_spillable_arg(int reg) {
 1661   return can_be_java_arg(reg);
 1662 }
 1663 
 1664 uint Matcher::int_pressure_limit()
 1665 {
 1666   // Medium size register set, 6 special purpose regs, 3 SOE regs.
 1667   return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
 1668 }
 1669 
 1670 uint Matcher::float_pressure_limit()
 1671 {
 1672   return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
 1673 }
 1674 
 1675 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 1676   return false;
 1677 }
 1678 
 1679 // Register for DIVI projection of divmodI
 1680 RegMask Matcher::divI_proj_mask() {
 1681   return _Z_RARG4_INT_REG_mask;
 1682 }
 1683 
 1684 // Register for MODI projection of divmodI
 1685 RegMask Matcher::modI_proj_mask() {
 1686   return _Z_RARG3_INT_REG_mask;
 1687 }
 1688 
 1689 // Register for DIVL projection of divmodL
 1690 RegMask Matcher::divL_proj_mask() {
 1691   return _Z_RARG4_LONG_REG_mask;
 1692 }
 1693 
 1694 // Register for MODL projection of divmodL
 1695 RegMask Matcher::modL_proj_mask() {
 1696   return _Z_RARG3_LONG_REG_mask;
 1697 }
 1698 
 1699 // Copied from sparc.
 1700 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1701   return RegMask();
 1702 }
 1703 
 1704 // Should the matcher clone input 'm' of node 'n'?
 1705 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 1706   return false;
 1707 }
 1708 
 1709 // Should the Matcher clone shifts on addressing modes, expecting them
 1710 // to be subsumed into complex addressing expressions or compute them
 1711 // into registers?
 1712 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 1713   return clone_base_plus_offset_address(m, mstack, address_visited);
 1714 }
 1715 
 1716 %} // source
 1717 
 1718 //----------ENCODING BLOCK-----------------------------------------------------
 1719 // This block specifies the encoding classes used by the compiler to output
 1720 // byte streams. Encoding classes are parameterized macros used by
 1721 // Machine Instruction Nodes in order to generate the bit encoding of the
 1722 // instruction. Operands specify their base encoding interface with the
 1723 // interface keyword. There are currently supported four interfaces,
 1724 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
 1725 // operand to generate a function which returns its register number when
 1726 // queried. CONST_INTER causes an operand to generate a function which
 1727 // returns the value of the constant when queried. MEMORY_INTER causes an
 1728 // operand to generate four functions which return the Base Register, the
 1729 // Index Register, the Scale Value, and the Offset Value of the operand when
 1730 // queried. COND_INTER causes an operand to generate six functions which
 1731 // return the encoding code (ie - encoding bits for the instruction)
 1732 // associated with each basic boolean condition for a conditional instruction.
 1733 //
 1734 // Instructions specify two basic values for encoding. Again, a function
 1735 // is available to check if the constant displacement is an oop. They use the
 1736 // ins_encode keyword to specify their encoding classes (which must be
 1737 // a sequence of enc_class names, and their parameters, specified in
 1738 // the encoding block), and they use the
 1739 // opcode keyword to specify, in order, their primary, secondary, and
 1740 // tertiary opcode. Only the opcode sections which a particular instruction
 1741 // needs for encoding need to be specified.
 1742 encode %{
 1743   enc_class enc_unimplemented %{
 1744     C2_MacroAssembler _masm(&cbuf);
 1745     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
 1746   %}
 1747 
 1748   enc_class enc_untested %{
 1749 #ifdef ASSERT
 1750     C2_MacroAssembler _masm(&cbuf);
 1751     __ untested("Untested mach node encoding in AD file.");
 1752 #endif
 1753   %}
 1754 
 1755   enc_class z_rrform(iRegI dst, iRegI src) %{
 1756     assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
 1757     assert( ($primary >> 16)         == 0, "Instruction format error");
 1758     z_emit16(cbuf, $primary |
 1759              Assembler::reg($dst$$reg,8,16) |
 1760              Assembler::reg($src$$reg,12,16));
 1761   %}
 1762 
 1763   enc_class z_rreform(iRegI dst1, iRegI src2) %{
 1764     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
 1765     z_emit32(cbuf, $primary |
 1766              Assembler::reg($dst1$$reg,24,32) |
 1767              Assembler::reg($src2$$reg,28,32));
 1768   %}
 1769 
 1770   enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
 1771     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
 1772     z_emit32(cbuf, $primary |
 1773              Assembler::reg($dst1$$reg,24,32) |
 1774              Assembler::reg($src2$$reg,28,32) |
 1775              Assembler::reg($src3$$reg,16,32));
 1776   %}
 1777 
 1778   enc_class z_riform_signed(iRegI dst, immI16 src) %{
 1779     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
 1780     z_emit32(cbuf, $primary |
 1781              Assembler::reg($dst$$reg,8,32) |
 1782              Assembler::simm16($src$$constant,16,32));
 1783   %}
 1784 
 1785   enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
 1786     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
 1787     z_emit32(cbuf, $primary |
 1788              Assembler::reg($dst$$reg,8,32) |
 1789              Assembler::uimm16($src$$constant,16,32));
 1790   %}
 1791 
 1792   enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
 1793     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1794     z_emit48(cbuf, $primary |
 1795              Assembler::reg($dst1$$reg,8,48) |
 1796              Assembler::reg($src3$$reg,12,48) |
 1797              Assembler::simm16($src2$$constant,16,48));
 1798   %}
 1799 
 1800   enc_class z_rilform_signed(iRegI dst, immL32 src) %{
 1801     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1802     z_emit48(cbuf, $primary |
 1803              Assembler::reg($dst$$reg,8,48) |
 1804              Assembler::simm32($src$$constant,16,48));
 1805   %}
 1806 
 1807   enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
 1808     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1809     z_emit48(cbuf, $primary |
 1810              Assembler::reg($dst$$reg,8,48) |
 1811              Assembler::uimm32($src$$constant,16,48));
 1812   %}
 1813 
 1814   enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
 1815     z_emit48(cbuf, $primary |
 1816              Assembler::reg($dst$$reg,8,48) |
 1817              Assembler::reg($src1$$reg,12,48) |
 1818              Assembler::simm20($src2$$constant));
 1819   %}
 1820 
 1821   enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
 1822     z_emit48(cbuf, $primary |
 1823              Assembler::reg($dst$$reg,8,48) |
 1824              Assembler::reg($src$$reg,12,48) |
 1825              Assembler::reg($shft$$reg,16,48) |
 1826              Assembler::simm20(0));
 1827   %}
 1828 
 1829   enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
 1830     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
 1831     z_emit32(cbuf, $primary |
 1832              Assembler::reg($dst$$reg,8,32) |
 1833              Assembler::reg($src1$$reg,12,32) |
 1834              Assembler::reg($src2$$reg,16,32) |
 1835              Assembler::uimm12($con$$constant,20,32));
 1836   %}
 1837 
 1838   enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
 1839     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
 1840     z_emit32(cbuf, $primary |
 1841              Assembler::reg($dst$$reg,8,32) |
 1842              Assembler::reg($src$$reg,16,32) |
 1843              Assembler::uimm12($con$$constant,20,32));
 1844   %}
 1845 
 1846   enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
 1847     z_emit48(cbuf, $primary |
 1848              Assembler::reg($dst$$reg,8,48) |
 1849              Assembler::reg($src1$$reg,12,48) |
 1850              Assembler::reg($src2$$reg,16,48) |
 1851              Assembler::simm20($con$$constant));
 1852   %}
 1853 
 1854   enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
 1855     z_emit48(cbuf, $primary |
 1856              Assembler::reg($dst$$reg,8,48) |
 1857              Assembler::reg($src$$reg,16,48) |
 1858              Assembler::simm20($con$$constant));
 1859   %}
 1860 
 1861   // Direct memory arithmetic.
 1862   enc_class z_siyform(memoryRSY mem, immI8 src) %{
 1863     int      disp = $mem$$disp;
 1864     Register base = reg_to_register_object($mem$$base);
 1865     int      con  = $src$$constant;
 1866 
 1867     assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
 1868     z_emit_inst(cbuf, $primary |
 1869                 Assembler::regz(base,16,48) |
 1870                 Assembler::simm20(disp) |
 1871                 Assembler::simm8(con,8,48));
 1872   %}
 1873 
 1874   enc_class z_silform(memoryRS mem, immI16 src) %{
 1875     z_emit_inst(cbuf, $primary |
 1876                 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
 1877                 Assembler::uimm12($mem$$disp,20,48) |
 1878                 Assembler::simm16($src$$constant,32,48));
 1879   %}
 1880 
 1881   // Encoder for FP ALU reg/mem instructions (support only short displacements).
 1882   enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
 1883     Register Ridx = $mem$$index$$Register;
 1884     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1885     if ($primary > (1L << 32)) {
 1886       z_emit_inst(cbuf, $primary |
 1887                   Assembler::reg($dst$$reg, 8, 48) |
 1888                   Assembler::uimm12($mem$$disp, 20, 48) |
 1889                   Assembler::reg(Ridx, 12, 48) |
 1890                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1891     } else {
 1892       z_emit_inst(cbuf, $primary |
 1893                   Assembler::reg($dst$$reg, 8, 32) |
 1894                   Assembler::uimm12($mem$$disp, 20, 32) |
 1895                   Assembler::reg(Ridx, 12, 32) |
 1896                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
 1897     }
 1898   %}
 1899 
 1900   enc_class z_form_rt_mem(iRegI dst, memory mem) %{
 1901     Register Ridx = $mem$$index$$Register;
 1902     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1903     if ($primary > (1L<<32)) {
 1904       z_emit_inst(cbuf, $primary |
 1905                   Assembler::reg($dst$$reg, 8, 48) |
 1906                   Assembler::simm20($mem$$disp) |
 1907                   Assembler::reg(Ridx, 12, 48) |
 1908                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1909     } else {
 1910       z_emit_inst(cbuf, $primary |
 1911                   Assembler::reg($dst$$reg, 8, 32) |
 1912                   Assembler::uimm12($mem$$disp, 20, 32) |
 1913                   Assembler::reg(Ridx, 12, 32) |
 1914                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
 1915     }
 1916   %}
 1917 
 1918   enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
 1919     int isize = $secondary > 1L << 32 ? 48 : 32;
 1920     Register Ridx = $mem$$index$$Register;
 1921     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1922 
 1923     if (Displacement::is_shortDisp((long)$mem$$disp)) {
 1924       z_emit_inst(cbuf, $secondary |
 1925                   Assembler::reg($dst$$reg, 8, isize) |
 1926                   Assembler::uimm12($mem$$disp, 20, isize) |
 1927                   Assembler::reg(Ridx, 12, isize) |
 1928                   Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
 1929     } else if (Displacement::is_validDisp((long)$mem$$disp)) {
 1930       z_emit_inst(cbuf, $primary |
 1931                   Assembler::reg($dst$$reg, 8, 48) |
 1932                   Assembler::simm20($mem$$disp) |
 1933                   Assembler::reg(Ridx, 12, 48) |
 1934                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1935     } else {
 1936         C2_MacroAssembler _masm(&cbuf);
 1937         __ load_const_optimized(Z_R1_scratch, $mem$$disp);
 1938         if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
 1939         z_emit_inst(cbuf, $secondary |
 1940                     Assembler::reg($dst$$reg, 8, isize) |
 1941                     Assembler::uimm12(0, 20, isize) |
 1942                     Assembler::reg(Z_R1_scratch, 12, isize) |
 1943                     Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
 1944     }
 1945   %}
 1946 
 1947   enc_class z_enc_brul(Label lbl) %{
 1948     C2_MacroAssembler _masm(&cbuf);
 1949     Label* p = $lbl$$label;
 1950 
 1951     // 'p' is `NULL' when this encoding class is used only to
 1952     // determine the size of the encoded instruction.
 1953     // Use a bound dummy label in that case.
 1954     Label d;
 1955     __ bind(d);
 1956     Label& l = (NULL == p) ? d : *(p);
 1957     __ z_brul(l);
 1958   %}
 1959 
 1960   enc_class z_enc_bru(Label lbl) %{
 1961     C2_MacroAssembler _masm(&cbuf);
 1962     Label* p = $lbl$$label;
 1963 
 1964     // 'p' is `NULL' when this encoding class is used only to
 1965     // determine the size of the encoded instruction.
 1966     // Use a bound dummy label in that case.
 1967     Label d;
 1968     __ bind(d);
 1969     Label& l = (NULL == p) ? d : *(p);
 1970     __ z_bru(l);
 1971   %}
 1972 
 1973   enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
 1974     C2_MacroAssembler _masm(&cbuf);
 1975     Label* p = $lbl$$label;
 1976 
 1977     // 'p' is `NULL' when this encoding class is used only to
 1978     // determine the size of the encoded instruction.
 1979     // Use a bound dummy label in that case.
 1980     Label d;
 1981     __ bind(d);
 1982     Label& l = (NULL == p) ? d : *(p);
 1983     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 1984   %}
 1985 
 1986   enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
 1987     C2_MacroAssembler _masm(&cbuf);
 1988     Label* p = $lbl$$label;
 1989 
 1990     // 'p' is `NULL' when this encoding class is used only to
 1991     // determine the size of the encoded instruction.
 1992     // Use a bound dummy label in that case.
 1993     Label d;
 1994     __ bind(d);
 1995     Label& l = (NULL == p) ? d : *(p);
 1996     __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
 1997   %}
 1998 
 1999   enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
 2000     C2_MacroAssembler _masm(&cbuf);
 2001     Label* p = $lbl$$label;
 2002 
 2003     // 'p' is `NULL' when this encoding class is used only to
 2004     // determine the size of the encoded instruction.
 2005     // Use a bound dummy label in that case.
 2006     Label d;
 2007     __ bind(d);
 2008     Label& l = (NULL == p) ? d : *(p);
 2009     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2010     unsigned long instr = $primary;
 2011     if (instr == CRJ_ZOPC) {
 2012       __ z_crj($src1$$Register, $src2$$Register, cc, l);
 2013     } else if (instr == CLRJ_ZOPC) {
 2014       __ z_clrj($src1$$Register, $src2$$Register, cc, l);
 2015     } else if (instr == CGRJ_ZOPC) {
 2016       __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
 2017     } else {
 2018       guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
 2019       __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
 2020     }
 2021   %}
 2022 
 2023   enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
 2024     C2_MacroAssembler _masm(&cbuf);
 2025     Label* p = $lbl$$label;
 2026 
 2027     // 'p' is `NULL' when this encoding class is used only to
 2028     // determine the size of the encoded instruction.
 2029     // Use a bound dummy label in that case.
 2030     Label d;
 2031     __ bind(d);
 2032     Label& l = (NULL == p) ? d : *(p);
 2033 
 2034     unsigned long instr = $primary;
 2035     if (instr == CR_ZOPC) {
 2036       __ z_cr($src1$$Register, $src2$$Register);
 2037     } else if (instr == CLR_ZOPC) {
 2038       __ z_clr($src1$$Register, $src2$$Register);
 2039     } else if (instr == CGR_ZOPC) {
 2040       __ z_cgr($src1$$Register, $src2$$Register);
 2041     } else {
 2042       guarantee(instr == CLGR_ZOPC, "opcode not implemented");
 2043       __ z_clgr($src1$$Register, $src2$$Register);
 2044     }
 2045 
 2046     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 2047   %}
 2048 
 2049   enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
 2050     C2_MacroAssembler _masm(&cbuf);
 2051     Label* p = $lbl$$label;
 2052 
 2053     // 'p' is `NULL' when this encoding class is used only to
 2054     // determine the size of the encoded instruction.
 2055     // Use a bound dummy label in that case.
 2056     Label d;
 2057     __ bind(d);
 2058     Label& l = (NULL == p) ? d : *(p);
 2059 
 2060     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2061     unsigned long instr = $primary;
 2062     if (instr == CIJ_ZOPC) {
 2063       __ z_cij($src1$$Register, $src2$$constant, cc, l);
 2064     } else if (instr == CLIJ_ZOPC) {
 2065       __ z_clij($src1$$Register, $src2$$constant, cc, l);
 2066     } else if (instr == CGIJ_ZOPC) {
 2067       __ z_cgij($src1$$Register, $src2$$constant, cc, l);
 2068     } else {
 2069       guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
 2070       __ z_clgij($src1$$Register, $src2$$constant, cc, l);
 2071     }
 2072   %}
 2073 
 2074   enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
 2075     C2_MacroAssembler _masm(&cbuf);
 2076     Label* p = $lbl$$label;
 2077 
 2078     // 'p' is `NULL' when this encoding class is used only to
 2079     // determine the size of the encoded instruction.
 2080     // Use a bound dummy label in that case.
 2081     Label d;
 2082     __ bind(d);
 2083     Label& l = (NULL == p) ? d : *(p);
 2084 
 2085     unsigned long instr = $primary;
 2086     if (instr == CHI_ZOPC) {
 2087       __ z_chi($src1$$Register, $src2$$constant);
 2088     } else if (instr == CLFI_ZOPC) {
 2089       __ z_clfi($src1$$Register, $src2$$constant);
 2090     } else if (instr == CGHI_ZOPC) {
 2091       __ z_cghi($src1$$Register, $src2$$constant);
 2092     } else {
 2093       guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
 2094       __ z_clgfi($src1$$Register, $src2$$constant);
 2095     }
 2096 
 2097     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 2098   %}
 2099 
 2100   // Call from Java to runtime.
 2101   enc_class z_enc_java_to_runtime_call(method meth) %{
 2102     C2_MacroAssembler _masm(&cbuf);
 2103 
 2104     // Save return pc before call to the place where we need it, since
 2105     // callee doesn't.
 2106     unsigned int start_off = __ offset();
 2107     // Compute size of "larl + stg + call_c_opt".
 2108     const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
 2109     __ get_PC(Z_R14, size_of_code);
 2110     __ save_return_pc();
 2111     assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
 2112 
 2113     assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
 2114     address call_addr = __ call_c_opt((address)$meth$$method);
 2115     if (call_addr == NULL) {
 2116       Compile::current()->env()->record_out_of_memory_failure();
 2117       return;
 2118     }
 2119 
 2120 #ifdef ASSERT
 2121     // Plausibility check for size_of_code assumptions.
 2122     unsigned int actual_ret_off = __ offset();
 2123     assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
 2124 #endif
 2125   %}
 2126 
 2127   enc_class z_enc_java_static_call(method meth) %{
 2128     // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
 2129     // whom we intended to call.
 2130     C2_MacroAssembler _masm(&cbuf);
 2131     int ret_offset = 0;
 2132 
 2133     if (!_method) {
 2134       ret_offset = emit_call_reloc(_masm, $meth$$method,
 2135                                    relocInfo::runtime_call_w_cp_type, ra_);
 2136     } else {
 2137       int method_index = resolved_method_index(cbuf);
 2138       if (_optimized_virtual) {
 2139         ret_offset = emit_call_reloc(_masm, $meth$$method,
 2140                                      opt_virtual_call_Relocation::spec(method_index));
 2141       } else {
 2142         ret_offset = emit_call_reloc(_masm, $meth$$method,
 2143                                      static_call_Relocation::spec(method_index));
 2144       }
 2145     }
 2146     assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
 2147 
 2148     if (_method) { // Emit stub for static call.
 2149       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
 2150       if (stub == NULL) {
 2151         ciEnv::current()->record_failure("CodeCache is full");
 2152         return;
 2153       }
 2154     }
 2155   %}
 2156 
 2157   // Java dynamic call
 2158   enc_class z_enc_java_dynamic_call(method meth) %{
 2159     C2_MacroAssembler _masm(&cbuf);
 2160     unsigned int start_off = __ offset();
 2161 
 2162     int vtable_index = this->_vtable_index;
 2163     if (vtable_index == -4) {
 2164       Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
 2165       address virtual_call_oop_addr = NULL;
 2166 
 2167       AddressLiteral empty_ic((address) Universe::non_oop_word());
 2168       virtual_call_oop_addr = __ pc();
 2169       bool success = __ load_const_from_toc(ic_reg, empty_ic);
 2170       if (!success) {
 2171         Compile::current()->env()->record_out_of_memory_failure();
 2172         return;
 2173       }
 2174 
 2175       // Call to fixup routine. Fixup routine uses ScopeDesc info
 2176       // to determine who we intended to call.
 2177       int method_index = resolved_method_index(cbuf);
 2178       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
 2179       unsigned int ret_off = __ offset();
 2180       assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
 2181       ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
 2182       assert(_method, "lazy_constant may be wrong when _method==null");
 2183     } else {
 2184       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 2185       // Go through the vtable. Get receiver klass. Receiver already
 2186       // checked for non-null. If we'll go thru a C2I adapter, the
 2187       // interpreter expects method in Z_method.
 2188       // Use Z_method to temporarily hold the klass oop.
 2189       // Z_R1_scratch is destroyed.
 2190       __ load_klass(Z_method, Z_R2);
 2191 
 2192       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
 2193       int v_off        = entry_offset + vtableEntry::method_offset_in_bytes();
 2194 
 2195       if (Displacement::is_validDisp(v_off) ) {
 2196         // Can use load instruction with large offset.
 2197         __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
 2198       } else {
 2199         // Worse case, must load offset into register.
 2200         __ load_const(Z_R1_scratch, v_off);
 2201         __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
 2202       }
 2203       // NOTE: for vtable dispatches, the vtable entry will never be
 2204       // null. However it may very well end up in handle_wrong_method
 2205       // if the method is abstract for the particular class.
 2206       __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
 2207       // Call target. Either compiled code or C2I adapter.
 2208       __ z_basr(Z_R14, Z_R1_scratch);
 2209       unsigned int ret_off = __ offset();
 2210     }
 2211   %}
 2212 
 2213   enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
 2214     C2_MacroAssembler _masm(&cbuf);
 2215     Register Rdst = reg_to_register_object($dst$$reg);
 2216     Register Rsrc = reg_to_register_object($src$$reg);
 2217 
 2218     // Don't emit code if operands are identical (same register).
 2219     if (Rsrc != Rdst) {
 2220       Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2221 
 2222       if (VM_Version::has_LoadStoreConditional()) {
 2223         __ z_locgr(Rdst, Rsrc, cc);
 2224       } else {
 2225         // Branch if not (cmp cr).
 2226         Label done;
 2227         __ z_brc(Assembler::inverse_condition(cc), done);
 2228         __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
 2229         __ bind(done);
 2230       }
 2231     }
 2232   %}
 2233 
 2234   enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
 2235     C2_MacroAssembler _masm(&cbuf);
 2236     Register Rdst = reg_to_register_object($dst$$reg);
 2237     int      Csrc = $src$$constant;
 2238     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2239     Label done;
 2240     // Branch if not (cmp cr).
 2241     __ z_brc(Assembler::inverse_condition(cc), done);
 2242     if (Csrc == 0) {
 2243       // Don't set CC.
 2244       __ clear_reg(Rdst, true, false);  // Use for int, long & ptr.
 2245     } else {
 2246       __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
 2247     }
 2248     __ bind(done);
 2249   %}
 2250 
 2251   enc_class z_enc_cctobool(iRegI res) %{
 2252     C2_MacroAssembler _masm(&cbuf);
 2253     Register Rres = reg_to_register_object($res$$reg);
 2254 
 2255     if (VM_Version::has_LoadStoreConditional()) {
 2256       __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
 2257       __ load_const_optimized(Rres, 1L);         // true  (succeed)
 2258       __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
 2259     } else {
 2260       Label done;
 2261       __ load_const_optimized(Rres, 0L); // false (failed)
 2262       __ z_brne(done);                   // Assume true to be the common case.
 2263       __ load_const_optimized(Rres, 1L); // true  (succeed)
 2264       __ bind(done);
 2265     }
 2266   %}
 2267 
 2268   enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
 2269     C2_MacroAssembler _masm(&cbuf);
 2270     Register Rcomp = reg_to_register_object($compare_value$$reg);
 2271     Register Rnew  = reg_to_register_object($exchange_value$$reg);
 2272     Register Raddr = reg_to_register_object($addr_ptr$$reg);
 2273 
 2274     __ z_cs(Rcomp, Rnew, 0, Raddr);
 2275   %}
 2276 
 2277   enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
 2278     C2_MacroAssembler _masm(&cbuf);
 2279     Register Rcomp = reg_to_register_object($compare_value$$reg);
 2280     Register Rnew  = reg_to_register_object($exchange_value$$reg);
 2281     Register Raddr = reg_to_register_object($addr_ptr$$reg);
 2282 
 2283     __ z_csg(Rcomp, Rnew, 0, Raddr);
 2284   %}
 2285 
 2286   enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
 2287     C2_MacroAssembler _masm(&cbuf);
 2288     Register Rdst = reg_to_register_object($dst$$reg);
 2289     Register Rtmp = reg_to_register_object($tmp$$reg);
 2290     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
 2291     Label    retry;
 2292 
 2293     // Iterate until swap succeeds.
 2294     __ z_llgf(Rtmp, $mem$$Address);  // current contents
 2295     __ bind(retry);
 2296       // Calculate incremented value.
 2297       __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
 2298       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
 2299     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
 2300   %}
 2301 
 2302   enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
 2303     C2_MacroAssembler _masm(&cbuf);
 2304     Register Rdst = reg_to_register_object($dst$$reg);
 2305     Register Rtmp = reg_to_register_object($tmp$$reg);
 2306     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
 2307     Label    retry;
 2308 
 2309     // Iterate until swap succeeds.
 2310     __ z_lg(Rtmp, $mem$$Address);  // current contents
 2311     __ bind(retry);
 2312       // Calculate incremented value.
 2313       __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
 2314       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
 2315     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
 2316   %}
 2317 
 2318 %} // encode
 2319 
 2320 source %{
 2321 
 2322   // Check whether outs are all Stores. If so, we can omit clearing the upper
 2323   // 32 bits after encoding.
 2324   static bool all_outs_are_Stores(const Node *n) {
 2325     for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
 2326       Node *out = n->fast_out(k);
 2327       if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
 2328         // Most other outs are SpillCopy, but there are various other.
 2329         // jvm98 has arond 9% Encodes where we return false.
 2330         return false;
 2331       }
 2332     }
 2333     return true;
 2334   }
 2335 
 2336 %} // source
 2337 
 2338 
 2339 //----------FRAME--------------------------------------------------------------
 2340 // Definition of frame structure and management information.
 2341 
 2342 frame %{
 2343   // These two registers define part of the calling convention between
 2344   // compiled code and the interpreter.
 2345 
 2346   // Inline Cache Register
 2347   inline_cache_reg(Z_R9); // Z_inline_cache
 2348 
 2349   // Argument pointer for I2C adapters
 2350   //
 2351   // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
 2352   // interpreter_arg_ptr_reg(Z_R6);
 2353 
 2354   // Optional: name the operand used by cisc-spilling to access
 2355   // [stack_pointer + offset].
 2356   cisc_spilling_operand_name(indOffset12);
 2357 
 2358   // Number of stack slots consumed by a Monitor enter.
 2359   sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
 2360 
 2361   // Compiled code's Frame Pointer
 2362   //
 2363   // z/Architecture stack pointer
 2364   frame_pointer(Z_R15); // Z_SP
 2365 
 2366   // Interpreter stores its frame pointer in a register which is
 2367   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
 2368   // interpreted java to compiled java.
 2369   //
 2370   // Z_state holds pointer to caller's cInterpreter.
 2371   interpreter_frame_pointer(Z_R7); // Z_state
 2372 
 2373   // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
 2374   stack_alignment(frame::alignment_in_bytes);
 2375 
 2376   // A `slot' is assumed 4 bytes here!
 2377   // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
 2378 
 2379   // Number of outgoing stack slots killed above the
 2380   // out_preserve_stack_slots for calls to C. Supports the var-args
 2381   // backing area for register parms.
 2382   varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
 2383 
 2384   // The after-PROLOG location of the return address. Location of
 2385   // return address specifies a type (REG or STACK) and a number
 2386   // representing the register number (i.e. - use a register name) or
 2387   // stack slot.
 2388   return_addr(REG Z_R14);
 2389 
 2390   // Location of native (C/C++) and interpreter return values. This
 2391   // is specified to be the same as Java. In the 32-bit VM, long
 2392   // values are actually returned from native calls in O0:O1 and
 2393   // returned to the interpreter in I0:I1. The copying to and from
 2394   // the register pairs is done by the appropriate call and epilog
 2395   // opcodes. This simplifies the register allocator.
 2396   //
 2397   // Use register pair for c return value.
 2398   c_return_value %{
 2399     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
 2400     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
 2401     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
 2402     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
 2403   %}
 2404 
 2405   // Use register pair for return value.
 2406   // Location of compiled Java return values. Same as C
 2407   return_value %{
 2408     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
 2409     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
 2410     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
 2411     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
 2412   %}
 2413 %}
 2414 
 2415 
 2416 //----------ATTRIBUTES---------------------------------------------------------
 2417 
 2418 //----------Operand Attributes-------------------------------------------------
 2419 op_attrib op_cost(1);          // Required cost attribute
 2420 
 2421 //----------Instruction Attributes---------------------------------------------
 2422 
 2423 // Cost attribute. required.
 2424 ins_attrib ins_cost(DEFAULT_COST);
 2425 
 2426 // Is this instruction a non-matching short branch variant of some
 2427 // long branch? Not required.
 2428 ins_attrib ins_short_branch(0);
 2429 
 2430 // Indicates this is a trap based check node and final control-flow fixup
 2431 // must generate a proper fall through.
 2432 ins_attrib ins_is_TrapBasedCheckNode(true);
 2433 
 2434 // Attribute of instruction to tell how many constants the instruction will generate.
 2435 // (optional attribute). Default: 0.
 2436 ins_attrib ins_num_consts(0);
 2437 
 2438 // Required alignment attribute (must be a power of 2)
 2439 // specifies the alignment that some part of the instruction (not
 2440 // necessarily the start) requires. If > 1, a compute_padding()
 2441 // function must be provided for the instruction.
 2442 //
 2443 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
 2444 // instructions which depend on the proper alignment, because the
 2445 // desired alignment isn't guaranteed for the call to "emit()" during
 2446 // the size computation.
 2447 ins_attrib ins_alignment(1);
 2448 
 2449 // Enforce/prohibit rematerializations.
 2450 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
 2451 //   then rematerialization of that instruction is prohibited and the
 2452 //   instruction's value will be spilled if necessary.
 2453 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
 2454 //   then rematerialization is enforced and the instruction's value will
 2455 //   never get spilled. a copy of the instruction will be inserted if
 2456 //   necessary.
 2457 //   Note: this may result in rematerializations in front of every use.
 2458 // (optional attribute)
 2459 ins_attrib ins_cannot_rematerialize(false);
 2460 ins_attrib ins_should_rematerialize(false);
 2461 
 2462 //----------OPERANDS-----------------------------------------------------------
 2463 // Operand definitions must precede instruction definitions for correct
 2464 // parsing in the ADLC because operands constitute user defined types
 2465 // which are used in instruction definitions.
 2466 
 2467 //----------Simple Operands----------------------------------------------------
 2468 // Immediate Operands
 2469 // Please note:
 2470 // Formats are generated automatically for constants and base registers.
 2471 
 2472 //----------------------------------------------
 2473 // SIGNED (shorter than INT) immediate operands
 2474 //----------------------------------------------
 2475 
 2476 // Byte Immediate: constant 'int -1'
 2477 operand immB_minus1() %{
 2478   //         sign-ext constant      zero-ext constant
 2479   predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
 2480   match(ConI);
 2481   op_cost(1);
 2482   format %{ %}
 2483   interface(CONST_INTER);
 2484 %}
 2485 
 2486 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
 2487 operand immB_n0m1() %{
 2488   //                             sign-ext constant     zero-ext constant
 2489   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
 2490   match(ConI);
 2491   op_cost(1);
 2492   format %{ %}
 2493   interface(CONST_INTER);
 2494 %}
 2495 
 2496 // Short Immediate: constant 'int -1'
 2497 operand immS_minus1() %{
 2498   //         sign-ext constant      zero-ext constant
 2499   predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
 2500   match(ConI);
 2501   op_cost(1);
 2502   format %{ %}
 2503   interface(CONST_INTER);
 2504 %}
 2505 
 2506 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
 2507 operand immS_n0m1() %{
 2508   //                             sign-ext constant     zero-ext constant
 2509   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
 2510   match(ConI);
 2511   op_cost(1);
 2512   format %{ %}
 2513   interface(CONST_INTER);
 2514 %}
 2515 
 2516 //-----------------------------------------
 2517 //  SIGNED INT immediate operands
 2518 //-----------------------------------------
 2519 
 2520 // Integer Immediate: 32-bit
 2521 operand immI() %{
 2522   match(ConI);
 2523   op_cost(1);
 2524   format %{ %}
 2525   interface(CONST_INTER);
 2526 %}
 2527 
 2528 // Int Immediate: 20-bit
 2529 operand immI20() %{
 2530   predicate(Immediate::is_simm20(n->get_int()));
 2531   match(ConI);
 2532   op_cost(1);
 2533   format %{ %}
 2534   interface(CONST_INTER);
 2535 %}
 2536 
 2537 // Integer Immediate: 16-bit
 2538 operand immI16() %{
 2539   predicate(Immediate::is_simm16(n->get_int()));
 2540   match(ConI);
 2541   op_cost(1);
 2542   format %{ %}
 2543   interface(CONST_INTER);
 2544 %}
 2545 
 2546 // Integer Immediate: 8-bit
 2547 operand immI8() %{
 2548   predicate(Immediate::is_simm8(n->get_int()));
 2549   match(ConI);
 2550   op_cost(1);
 2551   format %{ %}
 2552   interface(CONST_INTER);
 2553 %}
 2554 
 2555 // Integer Immediate: constant 'int 0'
 2556 operand immI_0() %{
 2557   predicate(n->get_int() == 0);
 2558   match(ConI);
 2559   op_cost(1);
 2560   format %{ %}
 2561   interface(CONST_INTER);
 2562 %}
 2563 
 2564 // Integer Immediate: constant 'int -1'
 2565 operand immI_minus1() %{
 2566   predicate(n->get_int() == -1);
 2567   match(ConI);
 2568   op_cost(1);
 2569   format %{ %}
 2570   interface(CONST_INTER);
 2571 %}
 2572 
 2573 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
 2574 operand immI_n0m1() %{
 2575   predicate(n->get_int() != 0 && n->get_int() != -1);
 2576   match(ConI);
 2577   op_cost(1);
 2578   format %{ %}
 2579   interface(CONST_INTER);
 2580 %}
 2581 
 2582 //-------------------------------------------
 2583 // UNSIGNED INT immediate operands
 2584 //-------------------------------------------
 2585 
 2586 // Unsigned Integer Immediate: 32-bit
 2587 operand uimmI() %{
 2588   match(ConI);
 2589   op_cost(1);
 2590   format %{ %}
 2591   interface(CONST_INTER);
 2592 %}
 2593 
 2594 // Unsigned Integer Immediate: 16-bit
 2595 operand uimmI16() %{
 2596   predicate(Immediate::is_uimm16(n->get_int()));
 2597   match(ConI);
 2598   op_cost(1);
 2599   format %{ %}
 2600   interface(CONST_INTER);
 2601 %}
 2602 
 2603 // Unsigned Integer Immediate: 12-bit
 2604 operand uimmI12() %{
 2605   predicate(Immediate::is_uimm12(n->get_int()));
 2606   match(ConI);
 2607   op_cost(1);
 2608   format %{ %}
 2609   interface(CONST_INTER);
 2610 %}
 2611 
 2612 // Unsigned Integer Immediate: 12-bit
 2613 operand uimmI8() %{
 2614   predicate(Immediate::is_uimm8(n->get_int()));
 2615   match(ConI);
 2616   op_cost(1);
 2617   format %{ %}
 2618   interface(CONST_INTER);
 2619 %}
 2620 
 2621 // Integer Immediate: 6-bit
 2622 operand uimmI6() %{
 2623   predicate(Immediate::is_uimm(n->get_int(), 6));
 2624   match(ConI);
 2625   op_cost(1);
 2626   format %{ %}
 2627   interface(CONST_INTER);
 2628 %}
 2629 
 2630 // Integer Immediate: 5-bit
 2631 operand uimmI5() %{
 2632   predicate(Immediate::is_uimm(n->get_int(), 5));
 2633   match(ConI);
 2634   op_cost(1);
 2635   format %{ %}
 2636   interface(CONST_INTER);
 2637 %}
 2638 
 2639 // Length for SS instructions, given in DWs,
 2640 //   possible range [1..512], i.e. [8..4096] Bytes
 2641 //   used     range [1..256], i.e. [8..2048] Bytes
 2642 //   operand type int
 2643 // Unsigned Integer Immediate: 9-bit
 2644 operand SSlenDW() %{
 2645   predicate(Immediate::is_uimm8(n->get_long()-1));
 2646   match(ConL);
 2647   op_cost(1);
 2648   format %{ %}
 2649   interface(CONST_INTER);
 2650 %}
 2651 
 2652 //------------------------------------------
 2653 // (UN)SIGNED INT specific values
 2654 //------------------------------------------
 2655 
 2656 // Integer Immediate: the value 1
 2657 operand immI_1() %{
 2658   predicate(n->get_int() == 1);
 2659   match(ConI);
 2660   op_cost(1);
 2661   format %{ %}
 2662   interface(CONST_INTER);
 2663 %}
 2664 
 2665 // Integer Immediate: the value 16.
 2666 operand immI_16() %{
 2667   predicate(n->get_int() == 16);
 2668   match(ConI);
 2669   op_cost(1);
 2670   format %{ %}
 2671   interface(CONST_INTER);
 2672 %}
 2673 
 2674 // Integer Immediate: the value 24.
 2675 operand immI_24() %{
 2676   predicate(n->get_int() == 24);
 2677   match(ConI);
 2678   op_cost(1);
 2679   format %{ %}
 2680   interface(CONST_INTER);
 2681 %}
 2682 
 2683 // Integer Immediate: the value 255
 2684 operand immI_255() %{
 2685   predicate(n->get_int() == 255);
 2686   match(ConI);
 2687   op_cost(1);
 2688   format %{ %}
 2689   interface(CONST_INTER);
 2690 %}
 2691 
 2692 // Integer Immediate: the values 32-63
 2693 operand immI_32_63() %{
 2694   predicate(n->get_int() >= 32 && n->get_int() <= 63);
 2695   match(ConI);
 2696   op_cost(1);
 2697   format %{ %}
 2698   interface(CONST_INTER);
 2699 %}
 2700 
 2701 // Unsigned Integer Immediate: LL-part, extended by 1s.
 2702 operand uimmI_LL1() %{
 2703   predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
 2704   match(ConI);
 2705   op_cost(1);
 2706   format %{ %}
 2707   interface(CONST_INTER);
 2708 %}
 2709 
 2710 // Unsigned Integer Immediate: LH-part, extended by 1s.
 2711 operand uimmI_LH1() %{
 2712   predicate((n->get_int() & 0xFFFF) == 0xFFFF);
 2713   match(ConI);
 2714   op_cost(1);
 2715   format %{ %}
 2716   interface(CONST_INTER);
 2717 %}
 2718 
 2719 //------------------------------------------
 2720 // SIGNED LONG immediate operands
 2721 //------------------------------------------
 2722 
 2723 operand immL() %{
 2724   match(ConL);
 2725   op_cost(1);
 2726   format %{ %}
 2727   interface(CONST_INTER);
 2728 %}
 2729 
 2730 // Long Immediate: 32-bit
 2731 operand immL32() %{
 2732   predicate(Immediate::is_simm32(n->get_long()));
 2733   match(ConL);
 2734   op_cost(1);
 2735   format %{ %}
 2736   interface(CONST_INTER);
 2737 %}
 2738 
 2739 // Long Immediate: 20-bit
 2740 operand immL20() %{
 2741   predicate(Immediate::is_simm20(n->get_long()));
 2742   match(ConL);
 2743   op_cost(1);
 2744   format %{ %}
 2745   interface(CONST_INTER);
 2746 %}
 2747 
 2748 // Long Immediate: 16-bit
 2749 operand immL16() %{
 2750   predicate(Immediate::is_simm16(n->get_long()));
 2751   match(ConL);
 2752   op_cost(1);
 2753   format %{ %}
 2754   interface(CONST_INTER);
 2755 %}
 2756 
 2757 // Long Immediate: 8-bit
 2758 operand immL8() %{
 2759   predicate(Immediate::is_simm8(n->get_long()));
 2760   match(ConL);
 2761   op_cost(1);
 2762   format %{ %}
 2763   interface(CONST_INTER);
 2764 %}
 2765 
 2766 //--------------------------------------------
 2767 // UNSIGNED LONG immediate operands
 2768 //--------------------------------------------
 2769 
 2770 operand uimmL32() %{
 2771   predicate(Immediate::is_uimm32(n->get_long()));
 2772   match(ConL);
 2773   op_cost(1);
 2774   format %{ %}
 2775   interface(CONST_INTER);
 2776 %}
 2777 
 2778 // Unsigned Long Immediate: 16-bit
 2779 operand uimmL16() %{
 2780   predicate(Immediate::is_uimm16(n->get_long()));
 2781   match(ConL);
 2782   op_cost(1);
 2783   format %{ %}
 2784   interface(CONST_INTER);
 2785 %}
 2786 
 2787 // Unsigned Long Immediate: 12-bit
 2788 operand uimmL12() %{
 2789   predicate(Immediate::is_uimm12(n->get_long()));
 2790   match(ConL);
 2791   op_cost(1);
 2792   format %{ %}
 2793   interface(CONST_INTER);
 2794 %}
 2795 
 2796 // Unsigned Long Immediate: 8-bit
 2797 operand uimmL8() %{
 2798   predicate(Immediate::is_uimm8(n->get_long()));
 2799   match(ConL);
 2800   op_cost(1);
 2801   format %{ %}
 2802   interface(CONST_INTER);
 2803 %}
 2804 
 2805 //-------------------------------------------
 2806 // (UN)SIGNED LONG specific values
 2807 //-------------------------------------------
 2808 
 2809 // Long Immediate: the value FF
 2810 operand immL_FF() %{
 2811   predicate(n->get_long() == 0xFFL);
 2812   match(ConL);
 2813   op_cost(1);
 2814   format %{ %}
 2815   interface(CONST_INTER);
 2816 %}
 2817 
 2818 // Long Immediate: the value FFFF
 2819 operand immL_FFFF() %{
 2820   predicate(n->get_long() == 0xFFFFL);
 2821   match(ConL);
 2822   op_cost(1);
 2823   format %{ %}
 2824   interface(CONST_INTER);
 2825 %}
 2826 
 2827 // Long Immediate: the value FFFFFFFF
 2828 operand immL_FFFFFFFF() %{
 2829   predicate(n->get_long() == 0xFFFFFFFFL);
 2830   match(ConL);
 2831   op_cost(1);
 2832   format %{ %}
 2833   interface(CONST_INTER);
 2834 %}
 2835 
 2836 operand immL_0() %{
 2837   predicate(n->get_long() == 0L);
 2838   match(ConL);
 2839   op_cost(1);
 2840   format %{ %}
 2841   interface(CONST_INTER);
 2842 %}
 2843 
 2844 // Unsigned Long Immediate: LL-part, extended by 1s.
 2845 operand uimmL_LL1() %{
 2846   predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
 2847   match(ConL);
 2848   op_cost(1);
 2849   format %{ %}
 2850   interface(CONST_INTER);
 2851 %}
 2852 
 2853 // Unsigned Long Immediate: LH-part, extended by 1s.
 2854 operand uimmL_LH1() %{
 2855   predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
 2856   match(ConL);
 2857   op_cost(1);
 2858   format %{ %}
 2859   interface(CONST_INTER);
 2860 %}
 2861 
 2862 // Unsigned Long Immediate: HL-part, extended by 1s.
 2863 operand uimmL_HL1() %{
 2864   predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
 2865   match(ConL);
 2866   op_cost(1);
 2867   format %{ %}
 2868   interface(CONST_INTER);
 2869 %}
 2870 
 2871 // Unsigned Long Immediate: HH-part, extended by 1s.
 2872 operand uimmL_HH1() %{
 2873   predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
 2874   match(ConL);
 2875   op_cost(1);
 2876   format %{ %}
 2877   interface(CONST_INTER);
 2878 %}
 2879 
 2880 // Long Immediate: low 32-bit mask
 2881 operand immL_32bits() %{
 2882   predicate(n->get_long() == 0xFFFFFFFFL);
 2883   match(ConL);
 2884   op_cost(1);
 2885   format %{ %}
 2886   interface(CONST_INTER);
 2887 %}
 2888 
 2889 //--------------------------------------
 2890 //  POINTER immediate operands
 2891 //--------------------------------------
 2892 
 2893 // Pointer Immediate: 64-bit
 2894 operand immP() %{
 2895   match(ConP);
 2896   op_cost(1);
 2897   format %{ %}
 2898   interface(CONST_INTER);
 2899 %}
 2900 
 2901 // Pointer Immediate: 32-bit
 2902 operand immP32() %{
 2903   predicate(Immediate::is_uimm32(n->get_ptr()));
 2904   match(ConP);
 2905   op_cost(1);
 2906   format %{ %}
 2907   interface(CONST_INTER);
 2908 %}
 2909 
 2910 // Pointer Immediate: 16-bit
 2911 operand immP16() %{
 2912   predicate(Immediate::is_uimm16(n->get_ptr()));
 2913   match(ConP);
 2914   op_cost(1);
 2915   format %{ %}
 2916   interface(CONST_INTER);
 2917 %}
 2918 
 2919 // Pointer Immediate: 8-bit
 2920 operand immP8() %{
 2921   predicate(Immediate::is_uimm8(n->get_ptr()));
 2922   match(ConP);
 2923   op_cost(1);
 2924   format %{ %}
 2925   interface(CONST_INTER);
 2926 %}
 2927 
 2928 //-----------------------------------
 2929 // POINTER specific values
 2930 //-----------------------------------
 2931 
 2932 // Pointer Immediate: NULL
 2933 operand immP0() %{
 2934   predicate(n->get_ptr() == 0);
 2935   match(ConP);
 2936   op_cost(1);
 2937   format %{ %}
 2938   interface(CONST_INTER);
 2939 %}
 2940 
 2941 //---------------------------------------------
 2942 // NARROW POINTER immediate operands
 2943 //---------------------------------------------
 2944 
 2945 // Narrow Pointer Immediate
 2946 operand immN() %{
 2947   match(ConN);
 2948   op_cost(1);
 2949   format %{ %}
 2950   interface(CONST_INTER);
 2951 %}
 2952 
 2953 operand immNKlass() %{
 2954   match(ConNKlass);
 2955   op_cost(1);
 2956   format %{ %}
 2957   interface(CONST_INTER);
 2958 %}
 2959 
 2960 // Narrow Pointer Immediate
 2961 operand immN8() %{
 2962   predicate(Immediate::is_uimm8(n->get_narrowcon()));
 2963   match(ConN);
 2964   op_cost(1);
 2965   format %{ %}
 2966   interface(CONST_INTER);
 2967 %}
 2968 
 2969 // Narrow NULL Pointer Immediate
 2970 operand immN0() %{
 2971   predicate(n->get_narrowcon() == 0);
 2972   match(ConN);
 2973   op_cost(1);
 2974   format %{ %}
 2975   interface(CONST_INTER);
 2976 %}
 2977 
 2978 // FLOAT and DOUBLE immediate operands
 2979 
 2980 // Double Immediate
 2981 operand immD() %{
 2982   match(ConD);
 2983   op_cost(1);
 2984   format %{ %}
 2985   interface(CONST_INTER);
 2986 %}
 2987 
 2988 // Double Immediate: +-0
 2989 operand immDpm0() %{
 2990   predicate(n->getd() == 0);
 2991   match(ConD);
 2992   op_cost(1);
 2993   format %{ %}
 2994   interface(CONST_INTER);
 2995 %}
 2996 
 2997 // Double Immediate: +0
 2998 operand immDp0() %{
 2999   predicate(jlong_cast(n->getd()) == 0);
 3000   match(ConD);
 3001   op_cost(1);
 3002   format %{ %}
 3003   interface(CONST_INTER);
 3004 %}
 3005 
 3006 // Float Immediate
 3007 operand immF() %{
 3008   match(ConF);
 3009   op_cost(1);
 3010   format %{ %}
 3011   interface(CONST_INTER);
 3012 %}
 3013 
 3014 // Float Immediate: +-0
 3015 operand immFpm0() %{
 3016   predicate(n->getf() == 0);
 3017   match(ConF);
 3018   op_cost(1);
 3019   format %{ %}
 3020   interface(CONST_INTER);
 3021 %}
 3022 
 3023 // Float Immediate: +0
 3024 operand immFp0() %{
 3025   predicate(jint_cast(n->getf()) == 0);
 3026   match(ConF);
 3027   op_cost(1);
 3028   format %{ %}
 3029   interface(CONST_INTER);
 3030 %}
 3031 
 3032 // End of Immediate Operands
 3033 
 3034 // Integer Register Operands
 3035 // Integer Register
 3036 operand iRegI() %{
 3037   constraint(ALLOC_IN_RC(z_int_reg));
 3038   match(RegI);
 3039   match(noArg_iRegI);
 3040   match(rarg1RegI);
 3041   match(rarg2RegI);
 3042   match(rarg3RegI);
 3043   match(rarg4RegI);
 3044   match(rarg5RegI);
 3045   match(noOdd_iRegI);
 3046   match(revenRegI);
 3047   match(roddRegI);
 3048   format %{ %}
 3049   interface(REG_INTER);
 3050 %}
 3051 
 3052 operand noArg_iRegI() %{
 3053   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
 3054   match(RegI);
 3055   format %{ %}
 3056   interface(REG_INTER);
 3057 %}
 3058 
 3059 // revenRegI and roddRegI constitute and even-odd-pair.
 3060 operand revenRegI() %{
 3061   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3062   match(iRegI);
 3063   format %{ %}
 3064   interface(REG_INTER);
 3065 %}
 3066 
 3067 // revenRegI and roddRegI constitute and even-odd-pair.
 3068 operand roddRegI() %{
 3069   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3070   match(iRegI);
 3071   format %{ %}
 3072   interface(REG_INTER);
 3073 %}
 3074 
 3075 operand rarg1RegI() %{
 3076   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
 3077   match(iRegI);
 3078   format %{ %}
 3079   interface(REG_INTER);
 3080 %}
 3081 
 3082 operand rarg2RegI() %{
 3083   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
 3084   match(iRegI);
 3085   format %{ %}
 3086   interface(REG_INTER);
 3087 %}
 3088 
 3089 operand rarg3RegI() %{
 3090   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3091   match(iRegI);
 3092   format %{ %}
 3093   interface(REG_INTER);
 3094 %}
 3095 
 3096 operand rarg4RegI() %{
 3097   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3098   match(iRegI);
 3099   format %{ %}
 3100   interface(REG_INTER);
 3101 %}
 3102 
 3103 operand rarg5RegI() %{
 3104   constraint(ALLOC_IN_RC(z_rarg5_int_reg));
 3105   match(iRegI);
 3106   format %{ %}
 3107   interface(REG_INTER);
 3108 %}
 3109 
 3110 operand noOdd_iRegI() %{
 3111   constraint(ALLOC_IN_RC(z_no_odd_int_reg));
 3112   match(RegI);
 3113   match(revenRegI);
 3114   format %{ %}
 3115   interface(REG_INTER);
 3116 %}
 3117 
 3118 // Pointer Register
 3119 operand iRegP() %{
 3120   constraint(ALLOC_IN_RC(z_ptr_reg));
 3121   match(RegP);
 3122   match(noArg_iRegP);
 3123   match(rarg1RegP);
 3124   match(rarg2RegP);
 3125   match(rarg3RegP);
 3126   match(rarg4RegP);
 3127   match(rarg5RegP);
 3128   match(revenRegP);
 3129   match(roddRegP);
 3130   format %{ %}
 3131   interface(REG_INTER);
 3132 %}
 3133 
 3134 // thread operand
 3135 operand threadRegP() %{
 3136   constraint(ALLOC_IN_RC(z_thread_ptr_reg));
 3137   match(RegP);
 3138   format %{ "Z_THREAD" %}
 3139   interface(REG_INTER);
 3140 %}
 3141 
 3142 operand noArg_iRegP() %{
 3143   constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
 3144   match(iRegP);
 3145   format %{ %}
 3146   interface(REG_INTER);
 3147 %}
 3148 
 3149 operand rarg1RegP() %{
 3150   constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
 3151   match(iRegP);
 3152   format %{ %}
 3153   interface(REG_INTER);
 3154 %}
 3155 
 3156 operand rarg2RegP() %{
 3157   constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
 3158   match(iRegP);
 3159   format %{ %}
 3160   interface(REG_INTER);
 3161 %}
 3162 
 3163 operand rarg3RegP() %{
 3164   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
 3165   match(iRegP);
 3166   format %{ %}
 3167   interface(REG_INTER);
 3168 %}
 3169 
 3170 operand rarg4RegP() %{
 3171   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
 3172   match(iRegP);
 3173   format %{ %}
 3174   interface(REG_INTER);
 3175 %}
 3176 
 3177 operand rarg5RegP() %{
 3178   constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
 3179   match(iRegP);
 3180   format %{ %}
 3181   interface(REG_INTER);
 3182 %}
 3183 
 3184 operand memoryRegP() %{
 3185   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3186   match(RegP);
 3187   match(iRegP);
 3188   match(threadRegP);
 3189   format %{ %}
 3190   interface(REG_INTER);
 3191 %}
 3192 
 3193 // revenRegP and roddRegP constitute and even-odd-pair.
 3194 operand revenRegP() %{
 3195   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
 3196   match(iRegP);
 3197   format %{ %}
 3198   interface(REG_INTER);
 3199 %}
 3200 
 3201 // revenRegP and roddRegP constitute and even-odd-pair.
 3202 operand roddRegP() %{
 3203   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
 3204   match(iRegP);
 3205   format %{ %}
 3206   interface(REG_INTER);
 3207 %}
 3208 
 3209 operand lock_ptr_RegP() %{
 3210   constraint(ALLOC_IN_RC(z_lock_ptr_reg));
 3211   match(RegP);
 3212   format %{ %}
 3213   interface(REG_INTER);
 3214 %}
 3215 
 3216 operand rscratch2RegP() %{
 3217   constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
 3218   match(RegP);
 3219   format %{ %}
 3220   interface(REG_INTER);
 3221 %}
 3222 
 3223 operand iRegN() %{
 3224   constraint(ALLOC_IN_RC(z_int_reg));
 3225   match(RegN);
 3226   match(noArg_iRegN);
 3227   match(rarg1RegN);
 3228   match(rarg2RegN);
 3229   match(rarg3RegN);
 3230   match(rarg4RegN);
 3231   match(rarg5RegN);
 3232   format %{ %}
 3233   interface(REG_INTER);
 3234 %}
 3235 
 3236 operand noArg_iRegN() %{
 3237   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
 3238   match(iRegN);
 3239   format %{ %}
 3240   interface(REG_INTER);
 3241 %}
 3242 
 3243 operand rarg1RegN() %{
 3244   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
 3245   match(iRegN);
 3246   format %{ %}
 3247   interface(REG_INTER);
 3248 %}
 3249 
 3250 operand rarg2RegN() %{
 3251   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
 3252   match(iRegN);
 3253   format %{ %}
 3254   interface(REG_INTER);
 3255 %}
 3256 
 3257 operand rarg3RegN() %{
 3258   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3259   match(iRegN);
 3260   format %{ %}
 3261   interface(REG_INTER);
 3262 %}
 3263 
 3264 operand rarg4RegN() %{
 3265   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3266   match(iRegN);
 3267   format %{ %}
 3268   interface(REG_INTER);
 3269 %}
 3270 
 3271 operand rarg5RegN() %{
 3272   constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
 3273   match(iRegN);
 3274   format %{ %}
 3275   interface(REG_INTER);
 3276 %}
 3277 
 3278 // Long Register
 3279 operand iRegL() %{
 3280   constraint(ALLOC_IN_RC(z_long_reg));
 3281   match(RegL);
 3282   match(revenRegL);
 3283   match(roddRegL);
 3284   match(allRoddRegL);
 3285   match(rarg1RegL);
 3286   match(rarg5RegL);
 3287   format %{ %}
 3288   interface(REG_INTER);
 3289 %}
 3290 
 3291 // revenRegL and roddRegL constitute and even-odd-pair.
 3292 operand revenRegL() %{
 3293   constraint(ALLOC_IN_RC(z_rarg3_long_reg));
 3294   match(iRegL);
 3295   format %{ %}
 3296   interface(REG_INTER);
 3297 %}
 3298 
 3299 // revenRegL and roddRegL constitute and even-odd-pair.
 3300 operand roddRegL() %{
 3301   constraint(ALLOC_IN_RC(z_rarg4_long_reg));
 3302   match(iRegL);
 3303   format %{ %}
 3304   interface(REG_INTER);
 3305 %}
 3306 
 3307 // available odd registers for iRegL
 3308 operand allRoddRegL() %{
 3309   constraint(ALLOC_IN_RC(z_long_odd_reg));
 3310   match(iRegL);
 3311   format %{ %}
 3312   interface(REG_INTER);
 3313 %}
 3314 
 3315 operand rarg1RegL() %{
 3316   constraint(ALLOC_IN_RC(z_rarg1_long_reg));
 3317   match(iRegL);
 3318   format %{ %}
 3319   interface(REG_INTER);
 3320 %}
 3321 
 3322 operand rarg5RegL() %{
 3323   constraint(ALLOC_IN_RC(z_rarg5_long_reg));
 3324   match(iRegL);
 3325   format %{ %}
 3326   interface(REG_INTER);
 3327 %}
 3328 
 3329 // Condition Code Flag Registers
 3330 operand flagsReg() %{
 3331   constraint(ALLOC_IN_RC(z_condition_reg));
 3332   match(RegFlags);
 3333   format %{ "CR" %}
 3334   interface(REG_INTER);
 3335 %}
 3336 
 3337 // Condition Code Flag Registers for rules with result tuples
 3338 operand TD_flagsReg() %{
 3339   constraint(ALLOC_IN_RC(z_condition_reg));
 3340   match(RegFlags);
 3341   format %{ "CR" %}
 3342   interface(REG_TUPLE_DEST_INTER);
 3343 %}
 3344 
 3345 operand regD() %{
 3346   constraint(ALLOC_IN_RC(z_dbl_reg));
 3347   match(RegD);
 3348   format %{ %}
 3349   interface(REG_INTER);
 3350 %}
 3351 
 3352 operand rscratchRegD() %{
 3353   constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
 3354   match(RegD);
 3355   format %{ %}
 3356   interface(REG_INTER);
 3357 %}
 3358 
 3359 operand regF() %{
 3360   constraint(ALLOC_IN_RC(z_flt_reg));
 3361   match(RegF);
 3362   format %{ %}
 3363   interface(REG_INTER);
 3364 %}
 3365 
 3366 operand rscratchRegF() %{
 3367   constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
 3368   match(RegF);
 3369   format %{ %}
 3370   interface(REG_INTER);
 3371 %}
 3372 
 3373 // Special Registers
 3374 
 3375 // Method Register
 3376 operand inline_cache_regP(iRegP reg) %{
 3377   constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
 3378   match(reg);
 3379   format %{ %}
 3380   interface(REG_INTER);
 3381 %}
 3382 
 3383 // Operands to remove register moves in unscaled mode.
 3384 // Match read/write registers with an EncodeP node if neither shift nor add are required.
 3385 operand iRegP2N(iRegP reg) %{
 3386   predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
 3387   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3388   match(EncodeP reg);
 3389   format %{ "$reg" %}
 3390   interface(REG_INTER)
 3391 %}
 3392 
 3393 operand iRegN2P(iRegN reg) %{
 3394   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 &&
 3395             _leaf->as_DecodeN()->in(0) == NULL);
 3396   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3397   match(DecodeN reg);
 3398   format %{ "$reg" %}
 3399   interface(REG_INTER)
 3400 %}
 3401 
 3402 
 3403 //----------Complex Operands---------------------------------------------------
 3404 
 3405 // Indirect Memory Reference
 3406 operand indirect(memoryRegP base) %{
 3407   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3408   match(base);
 3409   op_cost(1);
 3410   format %{ "#0[,$base]" %}
 3411   interface(MEMORY_INTER) %{
 3412     base($base);
 3413     index(0xffffFFFF); // noreg
 3414     scale(0x0);
 3415     disp(0x0);
 3416   %}
 3417 %}
 3418 
 3419 // Indirect with Offset (long)
 3420 operand indOffset20(memoryRegP base, immL20 offset) %{
 3421   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3422   match(AddP base offset);
 3423   op_cost(1);
 3424   format %{ "$offset[,$base]" %}
 3425   interface(MEMORY_INTER) %{
 3426     base($base);
 3427     index(0xffffFFFF); // noreg
 3428     scale(0x0);
 3429     disp($offset);
 3430   %}
 3431 %}
 3432 
 3433 operand indOffset20Narrow(iRegN base, immL20 offset) %{
 3434   predicate(Matcher::narrow_oop_use_complex_address());
 3435   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3436   match(AddP (DecodeN base) offset);
 3437   op_cost(1);
 3438   format %{ "$offset[,$base]" %}
 3439   interface(MEMORY_INTER) %{
 3440     base($base);
 3441     index(0xffffFFFF); // noreg
 3442     scale(0x0);
 3443     disp($offset);
 3444   %}
 3445 %}
 3446 
 3447 // Indirect with Offset (short)
 3448 operand indOffset12(memoryRegP base, uimmL12 offset) %{
 3449   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3450   match(AddP base offset);
 3451   op_cost(1);
 3452   format %{ "$offset[[,$base]]" %}
 3453   interface(MEMORY_INTER) %{
 3454     base($base);
 3455     index(0xffffFFFF); // noreg
 3456     scale(0x0);
 3457     disp($offset);
 3458   %}
 3459 %}
 3460 
 3461 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
 3462   predicate(Matcher::narrow_oop_use_complex_address());
 3463   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3464   match(AddP (DecodeN base) offset);
 3465   op_cost(1);
 3466   format %{ "$offset[[,$base]]" %}
 3467   interface(MEMORY_INTER) %{
 3468     base($base);
 3469     index(0xffffFFFF); // noreg
 3470     scale(0x0);
 3471     disp($offset);
 3472   %}
 3473 %}
 3474 
 3475 // Indirect with Register Index
 3476 operand indIndex(memoryRegP base, iRegL index) %{
 3477   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3478   match(AddP base index);
 3479   op_cost(1);
 3480   format %{ "#0[($index,$base)]" %}
 3481   interface(MEMORY_INTER) %{
 3482     base($base);
 3483     index($index);
 3484     scale(0x0);
 3485     disp(0x0);
 3486   %}
 3487 %}
 3488 
 3489 // Indirect with Offset (long) and index
 3490 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
 3491   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3492   match(AddP (AddP base index) offset);
 3493   op_cost(1);
 3494   format %{ "$offset[($index,$base)]" %}
 3495   interface(MEMORY_INTER) %{
 3496     base($base);
 3497     index($index);
 3498     scale(0x0);
 3499     disp($offset);
 3500   %}
 3501 %}
 3502 
 3503 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
 3504   predicate(Matcher::narrow_oop_use_complex_address());
 3505   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3506   match(AddP (AddP (DecodeN base) index) offset);
 3507   op_cost(1);
 3508   format %{ "$offset[($index,$base)]" %}
 3509   interface(MEMORY_INTER) %{
 3510     base($base);
 3511     index($index);
 3512     scale(0x0);
 3513     disp($offset);
 3514   %}
 3515 %}
 3516 
 3517 // Indirect with Offset (short) and index
 3518 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
 3519   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3520   match(AddP (AddP base index) offset);
 3521   op_cost(1);
 3522   format %{ "$offset[[($index,$base)]]" %}
 3523   interface(MEMORY_INTER) %{
 3524     base($base);
 3525     index($index);
 3526     scale(0x0);
 3527     disp($offset);
 3528   %}
 3529 %}
 3530 
 3531 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
 3532   predicate(Matcher::narrow_oop_use_complex_address());
 3533   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3534   match(AddP (AddP (DecodeN base) index) offset);
 3535   op_cost(1);
 3536   format %{ "$offset[[($index,$base)]]" %}
 3537   interface(MEMORY_INTER) %{
 3538     base($base);
 3539     index($index);
 3540     scale(0x0);
 3541     disp($offset);
 3542   %}
 3543 %}
 3544 
 3545 //----------Special Memory Operands--------------------------------------------
 3546 
 3547 // Stack Slot Operand
 3548 // This operand is used for loading and storing temporary values on
 3549 // the stack where a match requires a value to flow through memory.
 3550 operand stackSlotI(sRegI reg) %{
 3551   constraint(ALLOC_IN_RC(stack_slots));
 3552   op_cost(1);
 3553   format %{ "[$reg(stackSlotI)]" %}
 3554   interface(MEMORY_INTER) %{
 3555     base(0xf);   // Z_SP
 3556     index(0xffffFFFF); // noreg
 3557     scale(0x0);
 3558     disp($reg);  // stack offset
 3559   %}
 3560 %}
 3561 
 3562 operand stackSlotP(sRegP reg) %{
 3563   constraint(ALLOC_IN_RC(stack_slots));
 3564   op_cost(1);
 3565   format %{ "[$reg(stackSlotP)]" %}
 3566   interface(MEMORY_INTER) %{
 3567     base(0xf);   // Z_SP
 3568     index(0xffffFFFF); // noreg
 3569     scale(0x0);
 3570     disp($reg);  // Stack Offset
 3571   %}
 3572 %}
 3573 
 3574 operand stackSlotF(sRegF reg) %{
 3575   constraint(ALLOC_IN_RC(stack_slots));
 3576   op_cost(1);
 3577   format %{ "[$reg(stackSlotF)]" %}
 3578   interface(MEMORY_INTER) %{
 3579     base(0xf);   // Z_SP
 3580     index(0xffffFFFF); // noreg
 3581     scale(0x0);
 3582     disp($reg);  // Stack Offset
 3583   %}
 3584 %}
 3585 
 3586 operand stackSlotD(sRegD reg) %{
 3587   constraint(ALLOC_IN_RC(stack_slots));
 3588   op_cost(1);
 3589   //match(RegD);
 3590   format %{ "[$reg(stackSlotD)]" %}
 3591   interface(MEMORY_INTER) %{
 3592     base(0xf);   // Z_SP
 3593     index(0xffffFFFF); // noreg
 3594     scale(0x0);
 3595     disp($reg);  // Stack Offset
 3596   %}
 3597 %}
 3598 
 3599 operand stackSlotL(sRegL reg) %{
 3600   constraint(ALLOC_IN_RC(stack_slots));
 3601   op_cost(1);  //match(RegL);
 3602   format %{ "[$reg(stackSlotL)]" %}
 3603   interface(MEMORY_INTER) %{
 3604     base(0xf);   // Z_SP
 3605     index(0xffffFFFF); // noreg
 3606     scale(0x0);
 3607     disp($reg);  // Stack Offset
 3608   %}
 3609 %}
 3610 
 3611 // Operands for expressing Control Flow
 3612 // NOTE: Label is a predefined operand which should not be redefined in
 3613 // the AD file. It is generically handled within the ADLC.
 3614 
 3615 //----------Conditional Branch Operands----------------------------------------
 3616 // Comparison Op  - This is the operation of the comparison, and is limited to
 3617 //                  the following set of codes:
 3618 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3619 //
 3620 // Other attributes of the comparison, such as unsignedness, are specified
 3621 // by the comparison instruction that sets a condition code flags register.
 3622 // That result is represented by a flags operand whose subtype is appropriate
 3623 // to the unsignedness (etc.) of the comparison.
 3624 //
 3625 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3626 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3627 // by matching a specific subtype of Bool operand below.
 3628 
 3629 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
 3630 // have mask bit #3 set.
 3631 operand cmpOpT() %{
 3632   match(Bool);
 3633   format %{ "" %}
 3634   interface(COND_INTER) %{
 3635     equal(0x8);         // Assembler::bcondEqual
 3636     not_equal(0x6);     // Assembler::bcondNotEqual
 3637     less(0x4);          // Assembler::bcondLow
 3638     greater_equal(0xa); // Assembler::bcondNotLow
 3639     less_equal(0xc);    // Assembler::bcondNotHigh
 3640     greater(0x2);       // Assembler::bcondHigh
 3641     overflow(0x1);      // Assembler::bcondOverflow
 3642     no_overflow(0xe);   // Assembler::bcondNotOverflow
 3643   %}
 3644 %}
 3645 
 3646 // When used for floating point comparisons: unordered is treated as less.
 3647 operand cmpOpF() %{
 3648   match(Bool);
 3649   format %{ "" %}
 3650   interface(COND_INTER) %{
 3651     equal(0x8);
 3652     not_equal(0x7);     // Includes 'unordered'.
 3653     less(0x5);          // Includes 'unordered'.
 3654     greater_equal(0xa);
 3655     less_equal(0xd);    // Includes 'unordered'.
 3656     greater(0x2);
 3657     overflow(0x0);      // Not meaningful on z/Architecture.
 3658     no_overflow(0x0);   // leave unchanged (zero) therefore
 3659   %}
 3660 %}
 3661 
 3662 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
 3663 operand cmpOp() %{
 3664   match(Bool);
 3665   format %{ "" %}
 3666   interface(COND_INTER) %{
 3667     equal(0x8);
 3668     not_equal(0x7);     // Includes 'unordered'.
 3669     less(0x5);          // Includes 'unordered'.
 3670     greater_equal(0xa);
 3671     less_equal(0xd);    // Includes 'unordered'.
 3672     greater(0x2);
 3673     overflow(0x1);      // Assembler::bcondOverflow
 3674     no_overflow(0xe);   // Assembler::bcondNotOverflow
 3675   %}
 3676 %}
 3677 
 3678 //----------OPERAND CLASSES----------------------------------------------------
 3679 // Operand Classes are groups of operands that are used to simplify
 3680 // instruction definitions by not requiring the AD writer to specify
 3681 // seperate instructions for every form of operand when the
 3682 // instruction accepts multiple operand types with the same basic
 3683 // encoding and format.  The classic case of this is memory operands.
 3684 // Indirect is not included since its use is limited to Compare & Swap
 3685 
 3686 // Most general memory operand, allows base, index, and long displacement.
 3687 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
 3688 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
 3689 
 3690 // General memory operand, allows base, index, and short displacement.
 3691 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
 3692 
 3693 // Memory operand, allows only base and long displacement.
 3694 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
 3695 
 3696 // Memory operand, allows only base and short displacement.
 3697 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
 3698 
 3699 // Operand classes to match encode and decode.
 3700 opclass iRegN_P2N(iRegN);
 3701 opclass iRegP_N2P(iRegP);
 3702 
 3703 
 3704 //----------PIPELINE-----------------------------------------------------------
 3705 pipeline %{
 3706 
 3707 //----------ATTRIBUTES---------------------------------------------------------
 3708 attributes %{
 3709   // z/Architecture instructions are of length 2, 4, or 6 bytes.
 3710   variable_size_instructions;
 3711   instruction_unit_size = 2;
 3712 
 3713   // Meaningless on z/Architecture.
 3714   max_instructions_per_bundle = 1;
 3715 
 3716   // The z/Architecture processor fetches 64 bytes...
 3717   instruction_fetch_unit_size = 64;
 3718 
 3719   // ...in one line.
 3720   instruction_fetch_units = 1
 3721 %}
 3722 
 3723 //----------RESOURCES----------------------------------------------------------
 3724 // Resources are the functional units available to the machine.
 3725 resources(
 3726    Z_BR,     // branch unit
 3727    Z_CR,     // condition unit
 3728    Z_FX1,    // integer arithmetic unit 1
 3729    Z_FX2,    // integer arithmetic unit 2
 3730    Z_LDST1,  // load/store unit 1
 3731    Z_LDST2,  // load/store unit 2
 3732    Z_FP1,    // float arithmetic unit 1
 3733    Z_FP2,    // float arithmetic unit 2
 3734    Z_LDST = Z_LDST1 | Z_LDST2,
 3735    Z_FX   = Z_FX1 | Z_FX2,
 3736    Z_FP   = Z_FP1 | Z_FP2
 3737   );
 3738 
 3739 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3740 // Pipeline Description specifies the stages in the machine's pipeline.
 3741 pipe_desc(
 3742    // TODO: adapt
 3743    Z_IF,  // instruction fetch
 3744    Z_IC,
 3745    Z_D0,  // decode
 3746    Z_D1,  // decode
 3747    Z_D2,  // decode
 3748    Z_D3,  // decode
 3749    Z_Xfer1,
 3750    Z_GD,  // group definition
 3751    Z_MP,  // map
 3752    Z_ISS, // issue
 3753    Z_RF,  // resource fetch
 3754    Z_EX1, // execute (all units)
 3755    Z_EX2, // execute (FP, LDST)
 3756    Z_EX3, // execute (FP, LDST)
 3757    Z_EX4, // execute (FP)
 3758    Z_EX5, // execute (FP)
 3759    Z_EX6, // execute (FP)
 3760    Z_WB,  // write back
 3761    Z_Xfer2,
 3762    Z_CP
 3763   );
 3764 
 3765 //----------PIPELINE CLASSES---------------------------------------------------
 3766 // Pipeline Classes describe the stages in which input and output are
 3767 // referenced by the hardware pipeline.
 3768 
 3769 // Providing the `ins_pipe' declarations in the instruction
 3770 // specifications seems to be of little use. So we use
 3771 // `pipe_class_dummy' for all our instructions at present.
 3772 pipe_class pipe_class_dummy() %{
 3773   single_instruction;
 3774   fixed_latency(4);
 3775 %}
 3776 
 3777 // SIGTRAP based implicit range checks in compiled code.
 3778 // Currently, no pipe classes are used on z/Architecture.
 3779 pipe_class pipe_class_trap() %{
 3780   single_instruction;
 3781 %}
 3782 
 3783 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
 3784   single_instruction;
 3785   dst  : Z_EX1(write);
 3786   src1 : Z_RF(read);
 3787   src2 : Z_RF(read);
 3788   Z_FX : Z_RF;
 3789 %}
 3790 
 3791 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
 3792   single_instruction;
 3793   mem : Z_RF(read);
 3794   dst : Z_WB(write);
 3795   Z_LDST : Z_RF;
 3796 %}
 3797 
 3798 define %{
 3799   MachNop = pipe_class_dummy;
 3800 %}
 3801 
 3802 %}
 3803 
 3804 //----------INSTRUCTIONS-------------------------------------------------------
 3805 
 3806 //---------- Chain stack slots between similar types --------
 3807 
 3808 // Load integer from stack slot.
 3809 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
 3810   match(Set dst src);
 3811   ins_cost(MEMORY_REF_COST);
 3812   // TODO: s390 port size(FIXED_SIZE);
 3813   format %{ "L       $dst,$src\t # stk reload int" %}
 3814   opcode(L_ZOPC);
 3815   ins_encode(z_form_rt_mem(dst, src));
 3816   ins_pipe(pipe_class_dummy);
 3817 %}
 3818 
 3819 // Store integer to stack slot.
 3820 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
 3821   match(Set dst src);
 3822   ins_cost(MEMORY_REF_COST);
 3823   // TODO: s390 port size(FIXED_SIZE);
 3824   format %{ "ST      $src,$dst\t # stk spill int" %}
 3825   opcode(ST_ZOPC);
 3826   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3827   ins_pipe(pipe_class_dummy);
 3828 %}
 3829 
 3830 // Load long from stack slot.
 3831 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
 3832   match(Set dst src);
 3833   ins_cost(MEMORY_REF_COST);
 3834   // TODO: s390 port size(FIXED_SIZE);
 3835   format %{ "LG      $dst,$src\t # stk reload long" %}
 3836   opcode(LG_ZOPC);
 3837   ins_encode(z_form_rt_mem(dst, src));
 3838   ins_pipe(pipe_class_dummy);
 3839 %}
 3840 
 3841 // Store long to stack slot.
 3842 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
 3843   match(Set dst src);
 3844   ins_cost(MEMORY_REF_COST);
 3845   size(6);
 3846   format %{ "STG     $src,$dst\t # stk spill long" %}
 3847   opcode(STG_ZOPC);
 3848   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3849   ins_pipe(pipe_class_dummy);
 3850 %}
 3851 
 3852 // Load pointer from stack slot, 64-bit encoding.
 3853 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
 3854   match(Set dst src);
 3855   ins_cost(MEMORY_REF_COST);
 3856   // TODO: s390 port size(FIXED_SIZE);
 3857   format %{ "LG      $dst,$src\t # stk reload ptr" %}
 3858   opcode(LG_ZOPC);
 3859   ins_encode(z_form_rt_mem(dst, src));
 3860   ins_pipe(pipe_class_dummy);
 3861 %}
 3862 
 3863 // Store pointer to stack slot.
 3864 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
 3865   match(Set dst src);
 3866   ins_cost(MEMORY_REF_COST);
 3867   // TODO: s390 port size(FIXED_SIZE);
 3868   format %{ "STG     $src,$dst\t # stk spill ptr" %}
 3869   opcode(STG_ZOPC);
 3870   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3871   ins_pipe(pipe_class_dummy);
 3872 %}
 3873 
 3874 //  Float types
 3875 
 3876 // Load float value from stack slot.
 3877 instruct stkF_to_regF(regF dst, stackSlotF src) %{
 3878   match(Set dst src);
 3879   ins_cost(MEMORY_REF_COST);
 3880   size(4);
 3881   format %{ "LE(Y)   $dst,$src\t # stk reload float" %}
 3882   opcode(LE_ZOPC);
 3883   ins_encode(z_form_rt_mem(dst, src));
 3884   ins_pipe(pipe_class_dummy);
 3885 %}
 3886 
 3887 // Store float value to stack slot.
 3888 instruct regF_to_stkF(stackSlotF dst, regF src) %{
 3889   match(Set dst src);
 3890   ins_cost(MEMORY_REF_COST);
 3891   size(4);
 3892   format %{ "STE(Y)  $src,$dst\t # stk spill float" %}
 3893   opcode(STE_ZOPC);
 3894   ins_encode(z_form_rt_mem(src, dst));
 3895   ins_pipe(pipe_class_dummy);
 3896 %}
 3897 
 3898 // Load double value from stack slot.
 3899 instruct stkD_to_regD(regD dst, stackSlotD src) %{
 3900   match(Set dst src);
 3901   ins_cost(MEMORY_REF_COST);
 3902   // TODO: s390 port size(FIXED_SIZE);
 3903   format %{ "LD(Y)   $dst,$src\t # stk reload double" %}
 3904   opcode(LD_ZOPC);
 3905   ins_encode(z_form_rt_mem(dst, src));
 3906   ins_pipe(pipe_class_dummy);
 3907 %}
 3908 
 3909 // Store double value to stack slot.
 3910 instruct regD_to_stkD(stackSlotD dst, regD src) %{
 3911   match(Set dst src);
 3912   ins_cost(MEMORY_REF_COST);
 3913   size(4);
 3914   format %{ "STD(Y)  $src,$dst\t # stk spill double" %}
 3915   opcode(STD_ZOPC);
 3916   ins_encode(z_form_rt_mem(src, dst));
 3917   ins_pipe(pipe_class_dummy);
 3918 %}
 3919 
 3920 //----------Load/Store/Move Instructions---------------------------------------
 3921 
 3922 //----------Load Instructions--------------------------------------------------
 3923 
 3924 //------------------
 3925 //  MEMORY
 3926 //------------------
 3927 
 3928 //  BYTE
 3929 // Load Byte (8bit signed)
 3930 instruct loadB(iRegI dst, memory mem) %{
 3931   match(Set dst (LoadB mem));
 3932   ins_cost(MEMORY_REF_COST);
 3933   size(Z_DISP3_SIZE);
 3934   format %{ "LB      $dst, $mem\t # sign-extend byte to int" %}
 3935   opcode(LB_ZOPC, LB_ZOPC);
 3936   ins_encode(z_form_rt_mem_opt(dst, mem));
 3937   ins_pipe(pipe_class_dummy);
 3938 %}
 3939 
 3940 // Load Byte (8bit signed)
 3941 instruct loadB2L(iRegL dst, memory mem) %{
 3942   match(Set dst (ConvI2L (LoadB mem)));
 3943   ins_cost(MEMORY_REF_COST);
 3944   size(Z_DISP3_SIZE);
 3945   format %{ "LGB     $dst, $mem\t # sign-extend byte to long" %}
 3946   opcode(LGB_ZOPC, LGB_ZOPC);
 3947   ins_encode(z_form_rt_mem_opt(dst, mem));
 3948   ins_pipe(pipe_class_dummy);
 3949 %}
 3950 
 3951 // Load Unsigned Byte (8bit UNsigned) into an int reg.
 3952 instruct loadUB(iRegI dst, memory mem) %{
 3953   match(Set dst (LoadUB mem));
 3954   ins_cost(MEMORY_REF_COST);
 3955   size(Z_DISP3_SIZE);
 3956   format %{ "LLGC    $dst,$mem\t # zero-extend byte to int" %}
 3957   opcode(LLGC_ZOPC, LLGC_ZOPC);
 3958   ins_encode(z_form_rt_mem_opt(dst, mem));
 3959   ins_pipe(pipe_class_dummy);
 3960 %}
 3961 
 3962 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
 3963 instruct loadUB2L(iRegL dst, memory mem) %{
 3964   match(Set dst (ConvI2L (LoadUB mem)));
 3965   ins_cost(MEMORY_REF_COST);
 3966   size(Z_DISP3_SIZE);
 3967   format %{ "LLGC    $dst,$mem\t # zero-extend byte to long" %}
 3968   opcode(LLGC_ZOPC, LLGC_ZOPC);
 3969   ins_encode(z_form_rt_mem_opt(dst, mem));
 3970   ins_pipe(pipe_class_dummy);
 3971 %}
 3972 
 3973 // CHAR/SHORT
 3974 
 3975 // Load Short (16bit signed)
 3976 instruct loadS(iRegI dst, memory mem) %{
 3977   match(Set dst (LoadS mem));
 3978   ins_cost(MEMORY_REF_COST);
 3979   size(Z_DISP_SIZE);
 3980   format %{ "LH(Y)   $dst,$mem\t # sign-extend short to int" %}
 3981   opcode(LHY_ZOPC, LH_ZOPC);
 3982   ins_encode(z_form_rt_mem_opt(dst, mem));
 3983   ins_pipe(pipe_class_dummy);
 3984 %}
 3985 
 3986 // Load Short (16bit signed)
 3987 instruct loadS2L(iRegL dst, memory mem) %{
 3988   match(Set dst (ConvI2L (LoadS mem)));
 3989   ins_cost(MEMORY_REF_COST);
 3990   size(Z_DISP3_SIZE);
 3991   format %{ "LGH     $dst,$mem\t # sign-extend short to long" %}
 3992   opcode(LGH_ZOPC, LGH_ZOPC);
 3993   ins_encode(z_form_rt_mem_opt(dst, mem));
 3994   ins_pipe(pipe_class_dummy);
 3995 %}
 3996 
 3997 // Load Char (16bit Unsigned)
 3998 instruct loadUS(iRegI dst, memory mem) %{
 3999   match(Set dst (LoadUS mem));
 4000   ins_cost(MEMORY_REF_COST);
 4001   size(Z_DISP3_SIZE);
 4002   format %{ "LLGH    $dst,$mem\t # zero-extend short to int" %}
 4003   opcode(LLGH_ZOPC, LLGH_ZOPC);
 4004   ins_encode(z_form_rt_mem_opt(dst, mem));
 4005   ins_pipe(pipe_class_dummy);
 4006 %}
 4007 
 4008 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
 4009 instruct loadUS2L(iRegL dst, memory mem) %{
 4010   match(Set dst (ConvI2L (LoadUS mem)));
 4011   ins_cost(MEMORY_REF_COST);
 4012   size(Z_DISP3_SIZE);
 4013   format %{ "LLGH    $dst,$mem\t # zero-extend short to long" %}
 4014   opcode(LLGH_ZOPC, LLGH_ZOPC);
 4015   ins_encode(z_form_rt_mem_opt(dst, mem));
 4016   ins_pipe(pipe_class_dummy);
 4017 %}
 4018 
 4019 // INT
 4020 
 4021 // Load Integer
 4022 instruct loadI(iRegI dst, memory mem) %{
 4023   match(Set dst (LoadI mem));
 4024   ins_cost(MEMORY_REF_COST);
 4025   size(Z_DISP_SIZE);
 4026   format %{ "L(Y)    $dst,$mem\t #" %}
 4027   opcode(LY_ZOPC, L_ZOPC);
 4028   ins_encode(z_form_rt_mem_opt(dst, mem));
 4029   ins_pipe(pipe_class_dummy);
 4030 %}
 4031 
 4032 // Load and convert to long.
 4033 instruct loadI2L(iRegL dst, memory mem) %{
 4034   match(Set dst (ConvI2L (LoadI mem)));
 4035   ins_cost(MEMORY_REF_COST);
 4036   size(Z_DISP3_SIZE);
 4037   format %{ "LGF     $dst,$mem\t #" %}
 4038   opcode(LGF_ZOPC, LGF_ZOPC);
 4039   ins_encode(z_form_rt_mem_opt(dst, mem));
 4040   ins_pipe(pipe_class_dummy);
 4041 %}
 4042 
 4043 // Load Unsigned Integer into a Long Register
 4044 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
 4045   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4046   ins_cost(MEMORY_REF_COST);
 4047   size(Z_DISP3_SIZE);
 4048   format %{ "LLGF    $dst,$mem\t # zero-extend int to long" %}
 4049   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4050   ins_encode(z_form_rt_mem_opt(dst, mem));
 4051   ins_pipe(pipe_class_dummy);
 4052 %}
 4053 
 4054 // range = array length (=jint)
 4055 // Load Range
 4056 instruct loadRange(iRegI dst, memory mem) %{
 4057   match(Set dst (LoadRange mem));
 4058   ins_cost(MEMORY_REF_COST);
 4059   size(Z_DISP_SIZE);
 4060   format %{ "L(Y)    $dst,$mem\t # range" %}
 4061   opcode(LY_ZOPC, L_ZOPC);
 4062   ins_encode(z_form_rt_mem_opt(dst, mem));
 4063   ins_pipe(pipe_class_dummy);
 4064 %}
 4065 
 4066 // LONG
 4067 
 4068 // Load Long - aligned
 4069 instruct loadL(iRegL dst, memory mem) %{
 4070   match(Set dst (LoadL mem));
 4071   ins_cost(MEMORY_REF_COST);
 4072   size(Z_DISP3_SIZE);
 4073   format %{ "LG      $dst,$mem\t # long" %}
 4074   opcode(LG_ZOPC, LG_ZOPC);
 4075   ins_encode(z_form_rt_mem_opt(dst, mem));
 4076   ins_pipe(pipe_class_dummy);
 4077 %}
 4078 
 4079 // Load Long - UNaligned
 4080 instruct loadL_unaligned(iRegL dst, memory mem) %{
 4081   match(Set dst (LoadL_unaligned mem));
 4082   ins_cost(MEMORY_REF_COST);
 4083   size(Z_DISP3_SIZE);
 4084   format %{ "LG      $dst,$mem\t # unaligned long" %}
 4085   opcode(LG_ZOPC, LG_ZOPC);
 4086   ins_encode(z_form_rt_mem_opt(dst, mem));
 4087   ins_pipe(pipe_class_dummy);
 4088 %}
 4089 
 4090 
 4091 // PTR
 4092 
 4093 // Load Pointer
 4094 instruct loadP(iRegP dst, memory mem) %{
 4095   match(Set dst (LoadP mem));
 4096   ins_cost(MEMORY_REF_COST);
 4097   size(Z_DISP3_SIZE);
 4098   format %{ "LG      $dst,$mem\t # ptr" %}
 4099   opcode(LG_ZOPC, LG_ZOPC);
 4100   ins_encode(z_form_rt_mem_opt(dst, mem));
 4101   ins_pipe(pipe_class_dummy);
 4102 %}
 4103 
 4104 // LoadP + CastP2L
 4105 instruct castP2X_loadP(iRegL dst, memory mem) %{
 4106   match(Set dst (CastP2X (LoadP mem)));
 4107   ins_cost(MEMORY_REF_COST);
 4108   size(Z_DISP3_SIZE);
 4109   format %{ "LG      $dst,$mem\t # ptr + p2x" %}
 4110   opcode(LG_ZOPC, LG_ZOPC);
 4111   ins_encode(z_form_rt_mem_opt(dst, mem));
 4112   ins_pipe(pipe_class_dummy);
 4113 %}
 4114 
 4115 // Load Klass Pointer
 4116 instruct loadKlass(iRegP dst, memory mem) %{
 4117   match(Set dst (LoadKlass mem));
 4118   ins_cost(MEMORY_REF_COST);
 4119   size(Z_DISP3_SIZE);
 4120   format %{ "LG      $dst,$mem\t # klass ptr" %}
 4121   opcode(LG_ZOPC, LG_ZOPC);
 4122   ins_encode(z_form_rt_mem_opt(dst, mem));
 4123   ins_pipe(pipe_class_dummy);
 4124 %}
 4125 
 4126 instruct loadTOC(iRegL dst) %{
 4127   effect(DEF dst);
 4128   ins_cost(DEFAULT_COST);
 4129   // TODO: s390 port size(FIXED_SIZE);
 4130   // TODO: check why this attribute causes many unnecessary rematerializations.
 4131   //
 4132   // The graphs I saw just had high register pressure. Further the
 4133   // register TOC is loaded to is overwritten by the constant short
 4134   // after. Here something as round robin register allocation might
 4135   // help. But rematerializing seems not to hurt, jack even seems to
 4136   // improve slightly.
 4137   //
 4138   // Without this flag we get spill-split recycle sanity check
 4139   // failures in
 4140   // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
 4141   // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
 4142   // tlsLoadP has a huge amount of outs and forces the TOC down to the
 4143   // stack. Later tlsLoadP is rematerialized, leaving the register
 4144   // allocator with TOC on the stack and a badly placed reload.
 4145   ins_should_rematerialize(true);
 4146   format %{ "LARL    $dst, &constant_pool\t; load dynTOC" %}
 4147   ins_encode %{ __ load_toc($dst$$Register); %}
 4148   ins_pipe(pipe_class_dummy);
 4149 %}
 4150 
 4151 // FLOAT
 4152 
 4153 // Load Float
 4154 instruct loadF(regF dst, memory mem) %{
 4155   match(Set dst (LoadF mem));
 4156   ins_cost(MEMORY_REF_COST);
 4157   size(Z_DISP_SIZE);
 4158   format %{ "LE(Y)    $dst,$mem" %}
 4159   opcode(LEY_ZOPC, LE_ZOPC);
 4160   ins_encode(z_form_rt_mem_opt(dst, mem));
 4161   ins_pipe(pipe_class_dummy);
 4162 %}
 4163 
 4164 // DOUBLE
 4165 
 4166 // Load Double
 4167 instruct loadD(regD dst, memory mem) %{
 4168   match(Set dst (LoadD mem));
 4169   ins_cost(MEMORY_REF_COST);
 4170   size(Z_DISP_SIZE);
 4171   format %{ "LD(Y)    $dst,$mem" %}
 4172   opcode(LDY_ZOPC, LD_ZOPC);
 4173   ins_encode(z_form_rt_mem_opt(dst, mem));
 4174   ins_pipe(pipe_class_dummy);
 4175 %}
 4176 
 4177 // Load Double - UNaligned
 4178 instruct loadD_unaligned(regD dst, memory mem) %{
 4179   match(Set dst (LoadD_unaligned mem));
 4180   ins_cost(MEMORY_REF_COST);
 4181   size(Z_DISP_SIZE);
 4182   format %{ "LD(Y)    $dst,$mem" %}
 4183   opcode(LDY_ZOPC, LD_ZOPC);
 4184   ins_encode(z_form_rt_mem_opt(dst, mem));
 4185   ins_pipe(pipe_class_dummy);
 4186 %}
 4187 
 4188 
 4189 //----------------------
 4190 //  IMMEDIATES
 4191 //----------------------
 4192 
 4193 instruct loadConI(iRegI dst, immI src) %{
 4194   match(Set dst src);
 4195   ins_cost(DEFAULT_COST);
 4196   size(6);
 4197   format %{ "LGFI    $dst,$src\t # (int)" %}
 4198   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4199   ins_pipe(pipe_class_dummy);
 4200 %}
 4201 
 4202 instruct loadConI16(iRegI dst, immI16 src) %{
 4203   match(Set dst src);
 4204   ins_cost(DEFAULT_COST_LOW);
 4205   size(4);
 4206   format %{ "LGHI    $dst,$src\t # (int)" %}
 4207   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4208   ins_pipe(pipe_class_dummy);
 4209 %}
 4210 
 4211 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
 4212   match(Set dst src);
 4213   effect(KILL cr);
 4214   ins_cost(DEFAULT_COST_LOW);
 4215   size(4);
 4216   format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
 4217   opcode(XGR_ZOPC);
 4218   ins_encode(z_rreform(dst, dst));
 4219   ins_pipe(pipe_class_dummy);
 4220 %}
 4221 
 4222 instruct loadConUI16(iRegI dst, uimmI16 src) %{
 4223   match(Set dst src);
 4224   // TODO: s390 port size(FIXED_SIZE);
 4225   format %{ "LLILL    $dst,$src" %}
 4226   opcode(LLILL_ZOPC);
 4227   ins_encode(z_riform_unsigned(dst, src) );
 4228   ins_pipe(pipe_class_dummy);
 4229 %}
 4230 
 4231 // Load long constant from TOC with pcrelative address.
 4232 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
 4233   match(Set dst src);
 4234   ins_cost(MEMORY_REF_COST_LO);
 4235   size(6);
 4236   format %{ "LGRL    $dst,[pcrelTOC]\t # load long $src from table" %}
 4237   ins_encode %{
 4238     address long_address = __ long_constant($src$$constant);
 4239     if (long_address == NULL) {
 4240       Compile::current()->env()->record_out_of_memory_failure();
 4241       return;
 4242     }
 4243     __ load_long_pcrelative($dst$$Register, long_address);
 4244   %}
 4245   ins_pipe(pipe_class_dummy);
 4246 %}
 4247 
 4248 instruct loadConL32(iRegL dst, immL32 src) %{
 4249   match(Set dst src);
 4250   ins_cost(DEFAULT_COST);
 4251   size(6);
 4252   format %{ "LGFI     $dst,$src\t # (long)" %}
 4253   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4254   ins_pipe(pipe_class_dummy);
 4255 %}
 4256 
 4257 instruct loadConL16(iRegL dst, immL16 src) %{
 4258   match(Set dst src);
 4259   ins_cost(DEFAULT_COST_LOW);
 4260   size(4);
 4261   format %{ "LGHI     $dst,$src\t # (long)" %}
 4262   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4263   ins_pipe(pipe_class_dummy);
 4264 %}
 4265 
 4266 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
 4267   match(Set dst src);
 4268   effect(KILL cr);
 4269   ins_cost(DEFAULT_COST_LOW);
 4270   format %{ "LoadConL    $dst,$src\t # (long) XGR because ZERO is loaded" %}
 4271   opcode(XGR_ZOPC);
 4272   ins_encode(z_rreform(dst, dst));
 4273   ins_pipe(pipe_class_dummy);
 4274 %}
 4275 
 4276 // Load ptr constant from TOC with pc relative address.
 4277 // Special handling for oop constants required.
 4278 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
 4279   match(Set dst src);
 4280   ins_cost(MEMORY_REF_COST_LO);
 4281   size(6);
 4282   format %{ "LGRL    $dst,[pcrelTOC]\t # load ptr $src from table" %}
 4283   ins_encode %{
 4284     relocInfo::relocType constant_reloc = $src->constant_reloc();
 4285     if (constant_reloc == relocInfo::oop_type) {
 4286       AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
 4287       bool success = __ load_oop_from_toc($dst$$Register, a);
 4288       if (!success) {
 4289         Compile::current()->env()->record_out_of_memory_failure();
 4290         return;
 4291       }
 4292     } else if (constant_reloc == relocInfo::metadata_type) {
 4293       AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
 4294       address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
 4295       if (const_toc_addr == NULL) {
 4296         Compile::current()->env()->record_out_of_memory_failure();
 4297         return;
 4298       }
 4299       __ load_long_pcrelative($dst$$Register, const_toc_addr);
 4300     } else {          // Non-oop pointers, e.g. card mark base, heap top.
 4301       address long_address = __ long_constant((jlong)$src$$constant);
 4302       if (long_address == NULL) {
 4303         Compile::current()->env()->record_out_of_memory_failure();
 4304         return;
 4305       }
 4306       __ load_long_pcrelative($dst$$Register, long_address);
 4307     }
 4308   %}
 4309   ins_pipe(pipe_class_dummy);
 4310 %}
 4311 
 4312 // We don't use immP16 to avoid problems with oops.
 4313 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
 4314   match(Set dst src);
 4315   effect(KILL cr);
 4316   size(4);
 4317   format %{ "XGR     $dst,$dst\t # NULL ptr" %}
 4318   opcode(XGR_ZOPC);
 4319   ins_encode(z_rreform(dst, dst));
 4320   ins_pipe(pipe_class_dummy);
 4321 %}
 4322 
 4323 //----------Load Float Constant Instructions-------------------------------------------------
 4324 
 4325 // We may not specify this instruction via an `expand' rule. If we do,
 4326 // code selection will forget that this instruction needs a floating
 4327 // point constant inserted into the code buffer. So `Shorten_branches'
 4328 // will fail.
 4329 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
 4330   match(Set dst src);
 4331   effect(KILL cr);
 4332   ins_cost(MEMORY_REF_COST);
 4333   size(6);
 4334   // If this instruction rematerializes, it prolongs the live range
 4335   // of the toc node, causing illegal graphs.
 4336   ins_cannot_rematerialize(true);
 4337   format %{ "LE(Y)    $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
 4338   ins_encode %{
 4339     __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
 4340   %}
 4341   ins_pipe(pipe_class_dummy);
 4342 %}
 4343 
 4344 // E may not specify this instruction via an `expand' rule. If we do,
 4345 // code selection will forget that this instruction needs a floating
 4346 // point constant inserted into the code buffer. So `Shorten_branches'
 4347 // will fail.
 4348 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
 4349   match(Set dst src);
 4350   effect(KILL cr);
 4351   ins_cost(MEMORY_REF_COST);
 4352   size(6);
 4353   // If this instruction rematerializes, it prolongs the live range
 4354   // of the toc node, causing illegal graphs.
 4355   ins_cannot_rematerialize(true);
 4356   format %{ "LD(Y)    $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
 4357   ins_encode %{
 4358     __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
 4359   %}
 4360   ins_pipe(pipe_class_dummy);
 4361 %}
 4362 
 4363 // Special case: Load Const 0.0F
 4364 
 4365 // There's a special instr to clear a FP register.
 4366 instruct loadConF0(regF dst, immFp0 src) %{
 4367   match(Set dst src);
 4368   ins_cost(DEFAULT_COST_LOW);
 4369   size(4);
 4370   format %{ "LZER     $dst,$src\t # clear to zero" %}
 4371   opcode(LZER_ZOPC);
 4372   ins_encode(z_rreform(dst, Z_F0));
 4373   ins_pipe(pipe_class_dummy);
 4374 %}
 4375 
 4376 // There's a special instr to clear a FP register.
 4377 instruct loadConD0(regD dst, immDp0 src) %{
 4378   match(Set dst src);
 4379   ins_cost(DEFAULT_COST_LOW);
 4380   size(4);
 4381   format %{ "LZDR     $dst,$src\t # clear to zero" %}
 4382   opcode(LZDR_ZOPC);
 4383   ins_encode(z_rreform(dst, Z_F0));
 4384   ins_pipe(pipe_class_dummy);
 4385 %}
 4386 
 4387 
 4388 //----------Store Instructions-------------------------------------------------
 4389 
 4390 // BYTE
 4391 
 4392 // Store Byte
 4393 instruct storeB(memory mem, iRegI src) %{
 4394   match(Set mem (StoreB mem src));
 4395   ins_cost(MEMORY_REF_COST);
 4396   size(Z_DISP_SIZE);
 4397   format %{ "STC(Y)  $src,$mem\t # byte" %}
 4398   opcode(STCY_ZOPC, STC_ZOPC);
 4399   ins_encode(z_form_rt_mem_opt(src, mem));
 4400   ins_pipe(pipe_class_dummy);
 4401 %}
 4402 
 4403 instruct storeCM(memory mem, immI_0 src) %{
 4404   match(Set mem (StoreCM mem src));
 4405   ins_cost(MEMORY_REF_COST);
 4406   // TODO: s390 port size(VARIABLE_SIZE);
 4407   format %{ "STC(Y)  $src,$mem\t # CMS card-mark byte (must be 0!)" %}
 4408   ins_encode %{
 4409     guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
 4410     if ($mem$$index$$Register != noreg) {
 4411       // Can't use clear_mem --> load const zero and store character.
 4412       __ load_const_optimized(Z_R0_scratch, (long)0);
 4413       if (Immediate::is_uimm12($mem$$disp)) {
 4414         __ z_stc(Z_R0_scratch, $mem$$Address);
 4415       } else {
 4416         __ z_stcy(Z_R0_scratch, $mem$$Address);
 4417       }
 4418     } else {
 4419       __ clear_mem(Address($mem$$Address), 1);
 4420     }
 4421   %}
 4422   ins_pipe(pipe_class_dummy);
 4423 %}
 4424 
 4425 // CHAR/SHORT
 4426 
 4427 // Store Char/Short
 4428 instruct storeC(memory mem, iRegI src) %{
 4429   match(Set mem (StoreC mem src));
 4430   ins_cost(MEMORY_REF_COST);
 4431   size(Z_DISP_SIZE);
 4432   format %{ "STH(Y)  $src,$mem\t # short" %}
 4433   opcode(STHY_ZOPC, STH_ZOPC);
 4434   ins_encode(z_form_rt_mem_opt(src, mem));
 4435   ins_pipe(pipe_class_dummy);
 4436 %}
 4437 
 4438 // INT
 4439 
 4440 // Store Integer
 4441 instruct storeI(memory mem, iRegI src) %{
 4442   match(Set mem (StoreI mem src));
 4443   ins_cost(MEMORY_REF_COST);
 4444   size(Z_DISP_SIZE);
 4445   format %{ "ST(Y)   $src,$mem\t # int" %}
 4446   opcode(STY_ZOPC, ST_ZOPC);
 4447   ins_encode(z_form_rt_mem_opt(src, mem));
 4448   ins_pipe(pipe_class_dummy);
 4449 %}
 4450 
 4451 // LONG
 4452 
 4453 // Store Long
 4454 instruct storeL(memory mem, iRegL src) %{
 4455   match(Set mem (StoreL mem src));
 4456   ins_cost(MEMORY_REF_COST);
 4457   size(Z_DISP3_SIZE);
 4458   format %{ "STG     $src,$mem\t # long" %}
 4459   opcode(STG_ZOPC, STG_ZOPC);
 4460   ins_encode(z_form_rt_mem_opt(src, mem));
 4461   ins_pipe(pipe_class_dummy);
 4462 %}
 4463 
 4464 // PTR
 4465 
 4466 // Store Pointer
 4467 instruct storeP(memory dst, memoryRegP src) %{
 4468   match(Set dst (StoreP dst src));
 4469   ins_cost(MEMORY_REF_COST);
 4470   size(Z_DISP3_SIZE);
 4471   format %{ "STG     $src,$dst\t # ptr" %}
 4472   opcode(STG_ZOPC, STG_ZOPC);
 4473   ins_encode(z_form_rt_mem_opt(src, dst));
 4474   ins_pipe(pipe_class_dummy);
 4475 %}
 4476 
 4477 // FLOAT
 4478 
 4479 // Store Float
 4480 instruct storeF(memory mem, regF src) %{
 4481   match(Set mem (StoreF mem src));
 4482   ins_cost(MEMORY_REF_COST);
 4483   size(Z_DISP_SIZE);
 4484   format %{ "STE(Y)   $src,$mem\t # float" %}
 4485   opcode(STEY_ZOPC, STE_ZOPC);
 4486   ins_encode(z_form_rt_mem_opt(src, mem));
 4487   ins_pipe(pipe_class_dummy);
 4488 %}
 4489 
 4490 // DOUBLE
 4491 
 4492 // Store Double
 4493 instruct storeD(memory mem, regD src) %{
 4494   match(Set mem (StoreD mem src));
 4495   ins_cost(MEMORY_REF_COST);
 4496   size(Z_DISP_SIZE);
 4497   format %{ "STD(Y)   $src,$mem\t # double" %}
 4498   opcode(STDY_ZOPC, STD_ZOPC);
 4499   ins_encode(z_form_rt_mem_opt(src, mem));
 4500   ins_pipe(pipe_class_dummy);
 4501 %}
 4502 
 4503 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
 4504 
 4505 // Should support match rule for PrefetchAllocation.
 4506 // Still needed after 8068977 for PrefetchAllocate.
 4507 instruct prefetchAlloc(memory mem) %{
 4508   match(PrefetchAllocation mem);
 4509   predicate(VM_Version::has_Prefetch());
 4510   ins_cost(DEFAULT_COST);
 4511   format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
 4512   ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
 4513   ins_pipe(pipe_class_dummy);
 4514 %}
 4515 
 4516 //----------Memory init instructions------------------------------------------
 4517 
 4518 // Move Immediate to 1-byte memory.
 4519 instruct memInitB(memoryRSY mem, immI8 src) %{
 4520   match(Set mem (StoreB mem src));
 4521   ins_cost(MEMORY_REF_COST);
 4522   // TODO: s390 port size(VARIABLE_SIZE);
 4523   format %{ "MVI     $mem,$src\t # direct mem init 1" %}
 4524   ins_encode %{
 4525     if (Immediate::is_uimm12((long)$mem$$disp)) {
 4526       __ z_mvi($mem$$Address, $src$$constant);
 4527     } else {
 4528       __ z_mviy($mem$$Address, $src$$constant);
 4529     }
 4530   %}
 4531   ins_pipe(pipe_class_dummy);
 4532 %}
 4533 
 4534 // Move Immediate to 2-byte memory.
 4535 instruct memInitC(memoryRS mem, immI16 src) %{
 4536   match(Set mem (StoreC mem src));
 4537   ins_cost(MEMORY_REF_COST);
 4538   size(6);
 4539   format %{ "MVHHI   $mem,$src\t # direct mem init 2" %}
 4540   opcode(MVHHI_ZOPC);
 4541   ins_encode(z_silform(mem, src));
 4542   ins_pipe(pipe_class_dummy);
 4543 %}
 4544 
 4545 // Move Immediate to 4-byte memory.
 4546 instruct memInitI(memoryRS mem, immI16 src) %{
 4547   match(Set mem (StoreI mem src));
 4548   ins_cost(MEMORY_REF_COST);
 4549   size(6);
 4550   format %{ "MVHI    $mem,$src\t # direct mem init 4" %}
 4551   opcode(MVHI_ZOPC);
 4552   ins_encode(z_silform(mem, src));
 4553   ins_pipe(pipe_class_dummy);
 4554 %}
 4555 
 4556 
 4557 // Move Immediate to 8-byte memory.
 4558 instruct memInitL(memoryRS mem, immL16 src) %{
 4559   match(Set mem (StoreL mem src));
 4560   ins_cost(MEMORY_REF_COST);
 4561   size(6);
 4562   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
 4563   opcode(MVGHI_ZOPC);
 4564   ins_encode(z_silform(mem, src));
 4565   ins_pipe(pipe_class_dummy);
 4566 %}
 4567 
 4568 // Move Immediate to 8-byte memory.
 4569 instruct memInitP(memoryRS mem, immP16 src) %{
 4570   match(Set mem (StoreP mem src));
 4571   ins_cost(MEMORY_REF_COST);
 4572   size(6);
 4573   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
 4574   opcode(MVGHI_ZOPC);
 4575   ins_encode(z_silform(mem, src));
 4576   ins_pipe(pipe_class_dummy);
 4577 %}
 4578 
 4579 
 4580 //----------Instructions for compressed pointers (cOop and NKlass)-------------
 4581 
 4582 // See cOop encoding classes for elaborate comment.
 4583 
 4584 // Moved here because it is needed in expand rules for encode.
 4585 // Long negation.
 4586 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
 4587   match(Set dst (SubL zero src));
 4588   effect(KILL cr);
 4589   size(4);
 4590   format %{ "NEG     $dst, $src\t # long" %}
 4591   ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
 4592   ins_pipe(pipe_class_dummy);
 4593 %}
 4594 
 4595 // Load Compressed Pointer
 4596 
 4597 // Load narrow oop
 4598 instruct loadN(iRegN dst, memory mem) %{
 4599   match(Set dst (LoadN mem));
 4600   ins_cost(MEMORY_REF_COST);
 4601   size(Z_DISP3_SIZE);
 4602   format %{ "LoadN   $dst,$mem\t # (cOop)" %}
 4603   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4604   ins_encode(z_form_rt_mem_opt(dst, mem));
 4605   ins_pipe(pipe_class_dummy);
 4606 %}
 4607 
 4608 // Load narrow Klass Pointer
 4609 instruct loadNKlass(iRegN dst, memory mem) %{
 4610   match(Set dst (LoadNKlass mem));
 4611   ins_cost(MEMORY_REF_COST);
 4612   size(Z_DISP3_SIZE);
 4613   format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
 4614   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4615   ins_encode(z_form_rt_mem_opt(dst, mem));
 4616   ins_pipe(pipe_class_dummy);
 4617 %}
 4618 
 4619 // Load constant Compressed Pointer
 4620 
 4621 instruct loadConN(iRegN dst, immN src) %{
 4622   match(Set dst src);
 4623   ins_cost(DEFAULT_COST);
 4624   size(6);
 4625   format %{ "loadConN    $dst,$src\t # (cOop)" %}
 4626   ins_encode %{
 4627     AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
 4628     __ relocate(cOop.rspec(), 1);
 4629     __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
 4630   %}
 4631   ins_pipe(pipe_class_dummy);
 4632 %}
 4633 
 4634 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
 4635   match(Set dst src);
 4636   effect(KILL cr);
 4637   ins_cost(DEFAULT_COST_LOW);
 4638   size(4);
 4639   format %{ "loadConN    $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
 4640   opcode(XGR_ZOPC);
 4641   ins_encode(z_rreform(dst, dst));
 4642   ins_pipe(pipe_class_dummy);
 4643 %}
 4644 
 4645 instruct loadConNKlass(iRegN dst, immNKlass src) %{
 4646   match(Set dst src);
 4647   ins_cost(DEFAULT_COST);
 4648   size(6);
 4649   format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
 4650   ins_encode %{
 4651     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
 4652     __ relocate(NKlass.rspec(), 1);
 4653     __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
 4654   %}
 4655   ins_pipe(pipe_class_dummy);
 4656 %}
 4657 
 4658 // Load and Decode Compressed Pointer
 4659 // optimized variants for Unscaled cOops
 4660 
 4661 instruct decodeLoadN(iRegP dst, memory mem) %{
 4662   match(Set dst (DecodeN (LoadN mem)));
 4663   predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0));
 4664   ins_cost(MEMORY_REF_COST);
 4665   size(Z_DISP3_SIZE);
 4666   format %{ "DecodeLoadN  $dst,$mem\t # (cOop Load+Decode)" %}
 4667   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4668   ins_encode(z_form_rt_mem_opt(dst, mem));
 4669   ins_pipe(pipe_class_dummy);
 4670 %}
 4671 
 4672 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
 4673   match(Set dst (DecodeNKlass (LoadNKlass mem)));
 4674   predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0));
 4675   ins_cost(MEMORY_REF_COST);
 4676   size(Z_DISP3_SIZE);
 4677   format %{ "DecodeLoadNKlass  $dst,$mem\t # (load/decode NKlass)" %}
 4678   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4679   ins_encode(z_form_rt_mem_opt(dst, mem));
 4680   ins_pipe(pipe_class_dummy);
 4681 %}
 4682 
 4683 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
 4684   match(Set dst (DecodeNKlass src));
 4685   ins_cost(3 * DEFAULT_COST);
 4686   size(12);
 4687   format %{ "DecodeLoadConNKlass  $dst,$src\t # decode(cKlass)" %}
 4688   ins_encode %{
 4689     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
 4690     __ relocate(NKlass.rspec(), 1);
 4691     __ load_const($dst$$Register, (Klass*)NKlass.value());
 4692   %}
 4693   ins_pipe(pipe_class_dummy);
 4694 %}
 4695 
 4696 // Decode Compressed Pointer
 4697 
 4698 // General decoder
 4699 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
 4700   match(Set dst (DecodeN src));
 4701   effect(KILL cr);
 4702   predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode);
 4703   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
 4704   // TODO: s390 port size(VARIABLE_SIZE);
 4705   format %{ "decodeN  $dst,$src\t # (decode cOop)" %}
 4706   ins_encode %{  __ oop_decoder($dst$$Register, $src$$Register, true); %}
 4707   ins_pipe(pipe_class_dummy);
 4708 %}
 4709 
 4710 // General Klass decoder
 4711 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
 4712   match(Set dst (DecodeNKlass src));
 4713   effect(KILL cr);
 4714   ins_cost(3 * DEFAULT_COST);
 4715   format %{ "decode_klass $dst,$src" %}
 4716   ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
 4717   ins_pipe(pipe_class_dummy);
 4718 %}
 4719 
 4720 // General decoder
 4721 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
 4722   match(Set dst (DecodeN src));
 4723   effect(KILL cr);
 4724   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
 4725              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
 4726             (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN));
 4727   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4728   // TODO: s390 port size(VARIABLE_SIZE);
 4729   format %{ "decodeN  $dst,$src\t # (decode cOop NN)" %}
 4730   ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
 4731   ins_pipe(pipe_class_dummy);
 4732 %}
 4733 
 4734   instruct loadBase(iRegL dst, immL baseImm) %{
 4735     effect(DEF dst, USE baseImm);
 4736     predicate(false);
 4737     format %{ "llihl    $dst=$baseImm \t// load heap base" %}
 4738     ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
 4739     ins_pipe(pipe_class_dummy);
 4740   %}
 4741 
 4742   // Decoder for heapbased mode peeling off loading the base.
 4743   instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
 4744     match(Set dst (DecodeN src base));
 4745     // Note: Effect TEMP dst was used with the intention to get
 4746     // different regs for dst and base, but this has caused ADLC to
 4747     // generate wrong code. Oop_decoder generates additional lgr when
 4748     // dst==base.
 4749     effect(KILL cr);
 4750     predicate(false);
 4751     // TODO: s390 port size(VARIABLE_SIZE);
 4752     format %{ "decodeN  $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
 4753     ins_encode %{
 4754       __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
 4755                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
 4756     %}
 4757     ins_pipe(pipe_class_dummy);
 4758   %}
 4759 
 4760   // Decoder for heapbased mode peeling off loading the base.
 4761   instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
 4762     match(Set dst (DecodeN src base));
 4763     effect(KILL cr);
 4764     predicate(false);
 4765     // TODO: s390 port size(VARIABLE_SIZE);
 4766     format %{ "decodeN  $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
 4767     ins_encode %{
 4768       __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
 4769                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
 4770     %}
 4771     ins_pipe(pipe_class_dummy);
 4772   %}
 4773 
 4774 // Decoder for heapbased mode peeling off loading the base.
 4775 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
 4776   match(Set dst (DecodeN src));
 4777   predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode);
 4778   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
 4779   // TODO: s390 port size(VARIABLE_SIZE);
 4780   expand %{
 4781     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4782     iRegL base;
 4783     loadBase(base, baseImm);
 4784     decodeN_base(dst, src, base, cr);
 4785   %}
 4786 %}
 4787 
 4788 // Decoder for heapbased mode peeling off loading the base.
 4789 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
 4790   match(Set dst (DecodeN src));
 4791   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
 4792              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
 4793             CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN);
 4794   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4795   // TODO: s390 port size(VARIABLE_SIZE);
 4796   expand %{
 4797     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4798     iRegL base;
 4799     loadBase(base, baseImm);
 4800     decodeN_NN_base(dst, src, base, cr);
 4801   %}
 4802 %}
 4803 
 4804 //  Encode Compressed Pointer
 4805 
 4806 // General encoder
 4807 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
 4808   match(Set dst (EncodeP src));
 4809   effect(KILL cr);
 4810   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
 4811             (CompressedOops::base() == 0 ||
 4812              CompressedOops::base_disjoint() ||
 4813              !ExpandLoadingBaseEncode));
 4814   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4815   // TODO: s390 port size(VARIABLE_SIZE);
 4816   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
 4817   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
 4818   ins_pipe(pipe_class_dummy);
 4819 %}
 4820 
 4821 // General class encoder
 4822 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
 4823   match(Set dst (EncodePKlass src));
 4824   effect(KILL cr);
 4825   format %{ "encode_klass $dst,$src" %}
 4826   ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
 4827   ins_pipe(pipe_class_dummy);
 4828 %}
 4829 
 4830 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
 4831   match(Set dst (EncodeP src));
 4832   effect(KILL cr);
 4833   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
 4834             (CompressedOops::base() == 0 ||
 4835              CompressedOops::base_disjoint() ||
 4836              !ExpandLoadingBaseEncode_NN));
 4837   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4838   // TODO: s390 port size(VARIABLE_SIZE);
 4839   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
 4840   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
 4841   ins_pipe(pipe_class_dummy);
 4842 %}
 4843 
 4844   // Encoder for heapbased mode peeling off loading the base.
 4845   instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
 4846     match(Set dst (EncodeP src (Binary base dst)));
 4847     effect(TEMP_DEF dst);
 4848     predicate(false);
 4849     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4850     // TODO: s390 port size(VARIABLE_SIZE);
 4851     format %{ "encodeP  $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
 4852     ins_encode %{
 4853       jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
 4854         (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
 4855       __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
 4856     %}
 4857     ins_pipe(pipe_class_dummy);
 4858   %}
 4859 
 4860   // Encoder for heapbased mode peeling off loading the base.
 4861   instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
 4862     match(Set dst (EncodeP src base));
 4863     effect(USE pow2_offset);
 4864     predicate(false);
 4865     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4866     // TODO: s390 port size(VARIABLE_SIZE);
 4867     format %{ "encodeP  $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
 4868     ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
 4869     ins_pipe(pipe_class_dummy);
 4870   %}
 4871 
 4872 // Encoder for heapbased mode peeling off loading the base.
 4873 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
 4874   match(Set dst (EncodeP src));
 4875   effect(KILL cr);
 4876   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
 4877             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
 4878   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4879   // TODO: s390 port size(VARIABLE_SIZE);
 4880   expand %{
 4881     immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
 4882     immL_0 zero %{ (0) %}
 4883     flagsReg ccr;
 4884     iRegL base;
 4885     iRegL negBase;
 4886     loadBase(base, baseImm);
 4887     negL_reg_reg(negBase, zero, base, ccr);
 4888     encodeP_base(dst, src, negBase);
 4889   %}
 4890 %}
 4891 
 4892 // Encoder for heapbased mode peeling off loading the base.
 4893 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
 4894   match(Set dst (EncodeP src));
 4895   effect(KILL cr);
 4896   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
 4897             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
 4898   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4899   // TODO: s390 port size(VARIABLE_SIZE);
 4900   expand %{
 4901     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4902     immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
 4903     immL_0 zero %{ 0 %}
 4904     flagsReg ccr;
 4905     iRegL base;
 4906     iRegL negBase;
 4907     loadBase(base, baseImm);
 4908     negL_reg_reg(negBase, zero, base, ccr);
 4909     encodeP_NN_base(dst, src, negBase, pow2_offset);
 4910   %}
 4911 %}
 4912 
 4913 //  Store Compressed Pointer
 4914 
 4915 // Store Compressed Pointer
 4916 instruct storeN(memory mem, iRegN_P2N src) %{
 4917   match(Set mem (StoreN mem src));
 4918   ins_cost(MEMORY_REF_COST);
 4919   size(Z_DISP_SIZE);
 4920   format %{ "ST      $src,$mem\t # (cOop)" %}
 4921   opcode(STY_ZOPC, ST_ZOPC);
 4922   ins_encode(z_form_rt_mem_opt(src, mem));
 4923   ins_pipe(pipe_class_dummy);
 4924 %}
 4925 
 4926 // Store Compressed Klass pointer
 4927 instruct storeNKlass(memory mem, iRegN src) %{
 4928   match(Set mem (StoreNKlass mem src));
 4929   ins_cost(MEMORY_REF_COST);
 4930   size(Z_DISP_SIZE);
 4931   format %{ "ST      $src,$mem\t # (cKlass)" %}
 4932   opcode(STY_ZOPC, ST_ZOPC);
 4933   ins_encode(z_form_rt_mem_opt(src, mem));
 4934   ins_pipe(pipe_class_dummy);
 4935 %}
 4936 
 4937 // Compare Compressed Pointers
 4938 
 4939 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
 4940   match(Set cr (CmpN src1 src2));
 4941   ins_cost(DEFAULT_COST);
 4942   size(2);
 4943   format %{ "CLR     $src1,$src2\t # (cOop)" %}
 4944   opcode(CLR_ZOPC);
 4945   ins_encode(z_rrform(src1, src2));
 4946   ins_pipe(pipe_class_dummy);
 4947 %}
 4948 
 4949 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
 4950   match(Set cr (CmpN src1 src2));
 4951   ins_cost(DEFAULT_COST);
 4952   size(6);
 4953   format %{ "CLFI    $src1,$src2\t # (cOop) compare immediate narrow" %}
 4954   ins_encode %{
 4955     AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
 4956     __ relocate(cOop.rspec(), 1);
 4957     __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
 4958   %}
 4959   ins_pipe(pipe_class_dummy);
 4960 %}
 4961 
 4962 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
 4963   match(Set cr (CmpN src1 src2));
 4964   ins_cost(DEFAULT_COST);
 4965   size(6);
 4966   format %{ "CLFI    $src1,$src2\t # (NKlass) compare immediate narrow" %}
 4967   ins_encode %{
 4968     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
 4969     __ relocate(NKlass.rspec(), 1);
 4970     __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
 4971   %}
 4972   ins_pipe(pipe_class_dummy);
 4973 %}
 4974 
 4975 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
 4976   match(Set cr (CmpN src1 src2));
 4977   ins_cost(DEFAULT_COST);
 4978   size(2);
 4979   format %{ "LTR     $src1,$src2\t # (cOop) LTR because comparing against zero" %}
 4980   opcode(LTR_ZOPC);
 4981   ins_encode(z_rrform(src1, src1));
 4982   ins_pipe(pipe_class_dummy);
 4983 %}
 4984 
 4985 
 4986 //----------MemBar Instructions-----------------------------------------------
 4987 
 4988 // Memory barrier flavors
 4989 
 4990 instruct membar_acquire() %{
 4991   match(MemBarAcquire);
 4992   match(LoadFence);
 4993   ins_cost(4*MEMORY_REF_COST);
 4994   size(0);
 4995   format %{ "MEMBAR-acquire" %}
 4996   ins_encode %{ __ z_acquire(); %}
 4997   ins_pipe(pipe_class_dummy);
 4998 %}
 4999 
 5000 instruct membar_acquire_lock() %{
 5001   match(MemBarAcquireLock);
 5002   ins_cost(0);
 5003   size(0);
 5004   format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
 5005   ins_encode(/*empty*/);
 5006   ins_pipe(pipe_class_dummy);
 5007 %}
 5008 
 5009 instruct membar_release() %{
 5010   match(MemBarRelease);
 5011   match(StoreFence);
 5012   ins_cost(4 * MEMORY_REF_COST);
 5013   size(0);
 5014   format %{ "MEMBAR-release" %}
 5015   ins_encode %{ __ z_release(); %}
 5016   ins_pipe(pipe_class_dummy);
 5017 %}
 5018 
 5019 instruct membar_release_lock() %{
 5020   match(MemBarReleaseLock);
 5021   ins_cost(0);
 5022   size(0);
 5023   format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
 5024   ins_encode(/*empty*/);
 5025   ins_pipe(pipe_class_dummy);
 5026 %}
 5027 
 5028 instruct membar_volatile() %{
 5029   match(MemBarVolatile);
 5030   ins_cost(4 * MEMORY_REF_COST);
 5031   size(2);
 5032   format %{ "MEMBAR-volatile" %}
 5033   ins_encode %{ __ z_fence(); %}
 5034   ins_pipe(pipe_class_dummy);
 5035 %}
 5036 
 5037 instruct unnecessary_membar_volatile() %{
 5038   match(MemBarVolatile);
 5039   predicate(Matcher::post_store_load_barrier(n));
 5040   ins_cost(0);
 5041   size(0);
 5042   format %{ "# MEMBAR-volatile (empty)" %}
 5043   ins_encode(/*empty*/);
 5044   ins_pipe(pipe_class_dummy);
 5045 %}
 5046 
 5047 instruct membar_CPUOrder() %{
 5048   match(MemBarCPUOrder);
 5049   ins_cost(0);
 5050   // TODO: s390 port size(FIXED_SIZE);
 5051   format %{ "MEMBAR-CPUOrder (empty)" %}
 5052   ins_encode(/*empty*/);
 5053   ins_pipe(pipe_class_dummy);
 5054 %}
 5055 
 5056 instruct membar_storestore() %{
 5057   match(MemBarStoreStore);
 5058   ins_cost(0);
 5059   size(0);
 5060   format %{ "MEMBAR-storestore (empty)" %}
 5061   ins_encode();
 5062   ins_pipe(pipe_class_dummy);
 5063 %}
 5064 
 5065 
 5066 //----------Register Move Instructions-----------------------------------------
 5067 instruct roundDouble_nop(regD dst) %{
 5068   match(Set dst (RoundDouble dst));
 5069   ins_cost(0);
 5070   // TODO: s390 port size(FIXED_SIZE);
 5071   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
 5072   ins_encode();
 5073   ins_pipe(pipe_class_dummy);
 5074 %}
 5075 
 5076 instruct roundFloat_nop(regF dst) %{
 5077   match(Set dst (RoundFloat dst));
 5078   ins_cost(0);
 5079   // TODO: s390 port size(FIXED_SIZE);
 5080   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
 5081   ins_encode();
 5082   ins_pipe(pipe_class_dummy);
 5083 %}
 5084 
 5085 // Cast Long to Pointer for unsafe natives.
 5086 instruct castX2P(iRegP dst, iRegL src) %{
 5087   match(Set dst (CastX2P src));
 5088   // TODO: s390 port size(VARIABLE_SIZE);
 5089   format %{ "LGR     $dst,$src\t # CastX2P" %}
 5090   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
 5091   ins_pipe(pipe_class_dummy);
 5092 %}
 5093 
 5094 // Cast Pointer to Long for unsafe natives.
 5095 instruct castP2X(iRegL dst, iRegP_N2P src) %{
 5096   match(Set dst (CastP2X src));
 5097   // TODO: s390 port size(VARIABLE_SIZE);
 5098   format %{ "LGR     $dst,$src\t # CastP2X" %}
 5099   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
 5100   ins_pipe(pipe_class_dummy);
 5101 %}
 5102 
 5103 instruct stfSSD(stackSlotD stkSlot, regD src) %{
 5104   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
 5105   match(Set stkSlot src);   // chain rule
 5106   ins_cost(MEMORY_REF_COST);
 5107   // TODO: s390 port size(FIXED_SIZE);
 5108   format %{ " STD   $src,$stkSlot\t # stk" %}
 5109   opcode(STD_ZOPC);
 5110   ins_encode(z_form_rt_mem(src, stkSlot));
 5111   ins_pipe(pipe_class_dummy);
 5112 %}
 5113 
 5114 instruct stfSSF(stackSlotF stkSlot, regF src) %{
 5115   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
 5116   match(Set stkSlot src);   // chain rule
 5117   ins_cost(MEMORY_REF_COST);
 5118   // TODO: s390 port size(FIXED_SIZE);
 5119   format %{ "STE   $src,$stkSlot\t # stk" %}
 5120   opcode(STE_ZOPC);
 5121   ins_encode(z_form_rt_mem(src, stkSlot));
 5122   ins_pipe(pipe_class_dummy);
 5123 %}
 5124 
 5125 //----------Conditional Move---------------------------------------------------
 5126 
 5127 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
 5128   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
 5129   ins_cost(DEFAULT_COST + BRANCH_COST);
 5130   // TODO: s390 port size(VARIABLE_SIZE);
 5131   format %{ "CMoveN,$cmp   $dst,$src" %}
 5132   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5133   ins_pipe(pipe_class_dummy);
 5134 %}
 5135 
 5136 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
 5137   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
 5138   ins_cost(DEFAULT_COST + BRANCH_COST);
 5139   // TODO: s390 port size(VARIABLE_SIZE);
 5140   format %{ "CMoveN,$cmp   $dst,$src" %}
 5141   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5142   ins_pipe(pipe_class_dummy);
 5143 %}
 5144 
 5145 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
 5146   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
 5147   ins_cost(DEFAULT_COST + BRANCH_COST);
 5148   // TODO: s390 port size(VARIABLE_SIZE);
 5149   format %{ "CMoveI,$cmp   $dst,$src" %}
 5150   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5151   ins_pipe(pipe_class_dummy);
 5152 %}
 5153 
 5154 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
 5155   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
 5156   ins_cost(DEFAULT_COST + BRANCH_COST);
 5157   // TODO: s390 port size(VARIABLE_SIZE);
 5158   format %{ "CMoveI,$cmp   $dst,$src" %}
 5159   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5160   ins_pipe(pipe_class_dummy);
 5161 %}
 5162 
 5163 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
 5164   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
 5165   ins_cost(DEFAULT_COST + BRANCH_COST);
 5166   // TODO: s390 port size(VARIABLE_SIZE);
 5167   format %{ "CMoveP,$cmp    $dst,$src" %}
 5168   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5169   ins_pipe(pipe_class_dummy);
 5170 %}
 5171 
 5172 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
 5173   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
 5174   ins_cost(DEFAULT_COST + BRANCH_COST);
 5175   // TODO: s390 port size(VARIABLE_SIZE);
 5176   format %{ "CMoveP,$cmp  $dst,$src" %}
 5177   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5178   ins_pipe(pipe_class_dummy);
 5179 %}
 5180 
 5181 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
 5182   match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
 5183   ins_cost(DEFAULT_COST + BRANCH_COST);
 5184   // TODO: s390 port size(VARIABLE_SIZE);
 5185   format %{ "CMoveF,$cmp   $dst,$src" %}
 5186   ins_encode %{
 5187     // Don't emit code if operands are identical (same register).
 5188     if ($dst$$FloatRegister != $src$$FloatRegister) {
 5189       Label done;
 5190       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
 5191       __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
 5192       __ bind(done);
 5193     }
 5194   %}
 5195   ins_pipe(pipe_class_dummy);
 5196 %}
 5197 
 5198 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
 5199   match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
 5200   ins_cost(DEFAULT_COST + BRANCH_COST);
 5201   // TODO: s390 port size(VARIABLE_SIZE);
 5202   format %{ "CMoveD,$cmp   $dst,$src" %}
 5203   ins_encode %{
 5204     // Don't emit code if operands are identical (same register).
 5205     if ($dst$$FloatRegister != $src$$FloatRegister) {
 5206       Label done;
 5207       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
 5208       __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
 5209       __ bind(done);
 5210     }
 5211   %}
 5212   ins_pipe(pipe_class_dummy);
 5213 %}
 5214 
 5215 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
 5216   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
 5217   ins_cost(DEFAULT_COST + BRANCH_COST);
 5218   // TODO: s390 port size(VARIABLE_SIZE);
 5219   format %{ "CMoveL,$cmp  $dst,$src" %}
 5220   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5221   ins_pipe(pipe_class_dummy);
 5222 %}
 5223 
 5224 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
 5225   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
 5226   ins_cost(DEFAULT_COST + BRANCH_COST);
 5227   // TODO: s390 port size(VARIABLE_SIZE);
 5228   format %{ "CMoveL,$cmp  $dst,$src" %}
 5229   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5230   ins_pipe(pipe_class_dummy);
 5231 %}
 5232 
 5233 //----------OS and Locking Instructions----------------------------------------
 5234 
 5235 // This name is KNOWN by the ADLC and cannot be changed.
 5236 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
 5237 // for this guy.
 5238 instruct tlsLoadP(threadRegP dst) %{
 5239   match(Set dst (ThreadLocal));
 5240   ins_cost(0);
 5241   size(0);
 5242   ins_should_rematerialize(true);
 5243   format %{ "# $dst=ThreadLocal" %}
 5244   ins_encode(/* empty */);
 5245   ins_pipe(pipe_class_dummy);
 5246 %}
 5247 
 5248 instruct checkCastPP(iRegP dst) %{
 5249   match(Set dst (CheckCastPP dst));
 5250   size(0);
 5251   format %{ "# checkcastPP of $dst" %}
 5252   ins_encode(/*empty*/);
 5253   ins_pipe(pipe_class_dummy);
 5254 %}
 5255 
 5256 instruct castPP(iRegP dst) %{
 5257   match(Set dst (CastPP dst));
 5258   size(0);
 5259   format %{ "# castPP of $dst" %}
 5260   ins_encode(/*empty*/);
 5261   ins_pipe(pipe_class_dummy);
 5262 %}
 5263 
 5264 instruct castII(iRegI dst) %{
 5265   match(Set dst (CastII dst));
 5266   size(0);
 5267   format %{ "# castII of $dst" %}
 5268   ins_encode(/*empty*/);
 5269   ins_pipe(pipe_class_dummy);
 5270 %}
 5271 
 5272 instruct castLL(iRegL dst) %{
 5273   match(Set dst (CastLL dst));
 5274   size(0);
 5275   format %{ "# castLL of $dst" %}
 5276   ins_encode(/*empty*/);
 5277   ins_pipe(pipe_class_dummy);
 5278 %}
 5279 
 5280 instruct castFF(regF dst) %{
 5281   match(Set dst (CastFF dst));
 5282   size(0);
 5283   format %{ "# castFF of $dst" %}
 5284   ins_encode(/*empty*/);
 5285   ins_pipe(pipe_class_dummy);
 5286 %}
 5287 
 5288 instruct castDD(regD dst) %{
 5289   match(Set dst (CastDD dst));
 5290   size(0);
 5291   format %{ "# castDD of $dst" %}
 5292   ins_encode(/*empty*/);
 5293   ins_pipe(pipe_class_dummy);
 5294 %}
 5295 
 5296 instruct castVV(iRegL dst) %{
 5297   match(Set dst (CastVV dst));
 5298   size(0);
 5299   format %{ "# castVV of $dst" %}
 5300   ins_encode(/*empty*/);
 5301   ins_pipe(pipe_class_dummy);
 5302 %}
 5303 
 5304 //----------Conditional_store--------------------------------------------------
 5305 // Conditional-store of the updated heap-top.
 5306 // Used during allocation of the shared heap.
 5307 // Sets flags (EQ) on success.
 5308 
 5309 // Implement LoadPLocked. Must be ordered against changes of the memory location
 5310 // by storePConditional.
 5311 // Don't know whether this is ever used.
 5312 instruct loadPLocked(iRegP dst, memory mem) %{
 5313   match(Set dst (LoadPLocked mem));
 5314   ins_cost(MEMORY_REF_COST);
 5315   size(Z_DISP3_SIZE);
 5316   format %{ "LG      $dst,$mem\t # LoadPLocked" %}
 5317   opcode(LG_ZOPC, LG_ZOPC);
 5318   ins_encode(z_form_rt_mem_opt(dst, mem));
 5319   ins_pipe(pipe_class_dummy);
 5320 %}
 5321 
 5322 // As compareAndSwapP, but return flag register instead of boolean value in
 5323 // int register.
 5324 // This instruction is matched if UseTLAB is off. Needed to pass
 5325 // option tests.  Mem_ptr must be a memory operand, else this node
 5326 // does not get Flag_needs_anti_dependence_check set by adlc. If this
 5327 // is not set this node can be rematerialized which leads to errors.
 5328 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
 5329   match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
 5330   effect(KILL oldval);
 5331   // TODO: s390 port size(FIXED_SIZE);
 5332   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
 5333   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
 5334   ins_pipe(pipe_class_dummy);
 5335 %}
 5336 
 5337 // As compareAndSwapL, but return flag register instead of boolean value in
 5338 // int register.
 5339 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
 5340 // operand, else this node does not get
 5341 // Flag_needs_anti_dependence_check set by adlc. If this is not set
 5342 // this node can be rematerialized which leads to errors.
 5343 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
 5344   match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
 5345   effect(KILL oldval);
 5346   // TODO: s390 port size(FIXED_SIZE);
 5347   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
 5348   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
 5349   ins_pipe(pipe_class_dummy);
 5350 %}
 5351 
 5352 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
 5353 
 5354 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
 5355   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
 5356   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5357   size(16);
 5358   format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
 5359   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
 5360              z_enc_cctobool(res));
 5361   ins_pipe(pipe_class_dummy);
 5362 %}
 5363 
 5364 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
 5365   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
 5366   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5367   size(18);
 5368   format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
 5369   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
 5370              z_enc_cctobool(res));
 5371   ins_pipe(pipe_class_dummy);
 5372 %}
 5373 
 5374 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
 5375   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
 5376   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5377   size(18);
 5378   format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
 5379   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
 5380              z_enc_cctobool(res));
 5381   ins_pipe(pipe_class_dummy);
 5382 %}
 5383 
 5384 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
 5385   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
 5386   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5387   size(16);
 5388   format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
 5389   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
 5390              z_enc_cctobool(res));
 5391   ins_pipe(pipe_class_dummy);
 5392 %}
 5393 
 5394 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
 5395 
 5396 // Exploit: direct memory arithmetic
 5397 // Prereqs: - instructions available
 5398 //          - instructions guarantee atomicity
 5399 //          - immediate operand to be added
 5400 //          - immediate operand is small enough (8-bit signed).
 5401 //          - result of instruction is not used
 5402 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
 5403   match(Set dummy (GetAndAddI mem src));
 5404   effect(KILL cr);
 5405   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
 5406   ins_cost(MEMORY_REF_COST);
 5407   size(6);
 5408   format %{ "ASI     [$mem],$src\t # GetAndAddI (atomic)" %}
 5409   opcode(ASI_ZOPC);
 5410   ins_encode(z_siyform(mem, src));
 5411   ins_pipe(pipe_class_dummy);
 5412 %}
 5413 
 5414 // Fallback: direct memory arithmetic not available
 5415 // Disadvantages: - CS-Loop required, very expensive.
 5416 //                - more code generated (26 to xx bytes vs. 6 bytes)
 5417 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
 5418   match(Set dst (GetAndAddI mem src));
 5419   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5420   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5421   format %{ "BEGIN ATOMIC {\n\t"
 5422             "  LGF     $dst,[$mem]\n\t"
 5423             "  AHIK    $tmp,$dst,$src\n\t"
 5424             "  CSY     $dst,$tmp,$mem\n\t"
 5425             "  retry if failed\n\t"
 5426             "} END ATOMIC"
 5427          %}
 5428   ins_encode %{
 5429     Register Rdst = $dst$$Register;
 5430     Register Rtmp = $tmp$$Register;
 5431     int      Isrc = $src$$constant;
 5432     Label    retry;
 5433 
 5434     // Iterate until update with incremented value succeeds.
 5435     __ z_lgf(Rdst, $mem$$Address);    // current contents
 5436     __ bind(retry);
 5437       // Calculate incremented value.
 5438       if (VM_Version::has_DistinctOpnds()) {
 5439         __ z_ahik(Rtmp, Rdst, Isrc);
 5440       } else {
 5441         __ z_lr(Rtmp, Rdst);
 5442         __ z_ahi(Rtmp, Isrc);
 5443       }
 5444       // Swap into memory location.
 5445       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5446     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5447   %}
 5448   ins_pipe(pipe_class_dummy);
 5449 %}
 5450 
 5451 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
 5452   match(Set dst (GetAndAddI mem src));
 5453   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5454   ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
 5455   format %{ "BEGIN ATOMIC {\n\t"
 5456             "  LGF     $dst,[$mem]\n\t"
 5457             "  LGR     $tmp,$dst\n\t"
 5458             "  AFI     $tmp,$src\n\t"
 5459             "  CSY     $dst,$tmp,$mem\n\t"
 5460             "  retry if failed\n\t"
 5461             "} END ATOMIC"
 5462          %}
 5463   ins_encode %{
 5464     Register Rdst = $dst$$Register;
 5465     Register Rtmp = $tmp$$Register;
 5466     int      Isrc = $src$$constant;
 5467     Label    retry;
 5468 
 5469     // Iterate until update with incremented value succeeds.
 5470     __ z_lgf(Rdst, $mem$$Address);    // current contents
 5471     __ bind(retry);
 5472       // Calculate incremented value.
 5473       __ z_lr(Rtmp, Rdst);
 5474       __ z_afi(Rtmp, Isrc);
 5475       // Swap into memory location.
 5476       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5477     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5478   %}
 5479   ins_pipe(pipe_class_dummy);
 5480 %}
 5481 
 5482 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
 5483   match(Set dst (GetAndAddI mem src));
 5484   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5485   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5486   format %{ "BEGIN ATOMIC {\n\t"
 5487             "  LGF     $dst,[$mem]\n\t"
 5488             "  ARK     $tmp,$dst,$src\n\t"
 5489             "  CSY     $dst,$tmp,$mem\n\t"
 5490             "  retry if failed\n\t"
 5491             "} END ATOMIC"
 5492          %}
 5493   ins_encode %{
 5494     Register Rsrc = $src$$Register;
 5495     Register Rdst = $dst$$Register;
 5496     Register Rtmp = $tmp$$Register;
 5497     Label    retry;
 5498 
 5499     // Iterate until update with incremented value succeeds.
 5500     __ z_lgf(Rdst, $mem$$Address);  // current contents
 5501     __ bind(retry);
 5502       // Calculate incremented value.
 5503       if (VM_Version::has_DistinctOpnds()) {
 5504         __ z_ark(Rtmp, Rdst, Rsrc);
 5505       } else {
 5506         __ z_lr(Rtmp, Rdst);
 5507         __ z_ar(Rtmp, Rsrc);
 5508       }
 5509       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5510     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5511   %}
 5512   ins_pipe(pipe_class_dummy);
 5513 %}
 5514 
 5515 
 5516 // Exploit: direct memory arithmetic
 5517 // Prereqs: - instructions available
 5518 //          - instructions guarantee atomicity
 5519 //          - immediate operand to be added
 5520 //          - immediate operand is small enough (8-bit signed).
 5521 //          - result of instruction is not used
 5522 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
 5523   match(Set dummy (GetAndAddL mem src));
 5524   effect(KILL cr);
 5525   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
 5526   ins_cost(MEMORY_REF_COST);
 5527   size(6);
 5528   format %{ "AGSI    [$mem],$src\t # GetAndAddL (atomic)" %}
 5529   opcode(AGSI_ZOPC);
 5530   ins_encode(z_siyform(mem, src));
 5531   ins_pipe(pipe_class_dummy);
 5532 %}
 5533 
 5534 // Fallback: direct memory arithmetic not available
 5535 // Disadvantages: - CS-Loop required, very expensive.
 5536 //                - more code generated (26 to xx bytes vs. 6 bytes)
 5537 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
 5538   match(Set dst (GetAndAddL mem src));
 5539   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5540   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5541   format %{ "BEGIN ATOMIC {\n\t"
 5542             "  LG      $dst,[$mem]\n\t"
 5543             "  AGHIK   $tmp,$dst,$src\n\t"
 5544             "  CSG     $dst,$tmp,$mem\n\t"
 5545             "  retry if failed\n\t"
 5546             "} END ATOMIC"
 5547          %}
 5548   ins_encode %{
 5549     Register Rdst = $dst$$Register;
 5550     Register Rtmp = $tmp$$Register;
 5551     int      Isrc = $src$$constant;
 5552     Label    retry;
 5553 
 5554     // Iterate until update with incremented value succeeds.
 5555     __ z_lg(Rdst, $mem$$Address);  // current contents
 5556     __ bind(retry);
 5557       // Calculate incremented value.
 5558       if (VM_Version::has_DistinctOpnds()) {
 5559         __ z_aghik(Rtmp, Rdst, Isrc);
 5560       } else {
 5561         __ z_lgr(Rtmp, Rdst);
 5562         __ z_aghi(Rtmp, Isrc);
 5563       }
 5564       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5565     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5566   %}
 5567   ins_pipe(pipe_class_dummy);
 5568 %}
 5569 
 5570 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
 5571   match(Set dst (GetAndAddL mem src));
 5572   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5573   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5574   format %{ "BEGIN ATOMIC {\n\t"
 5575             "  LG      $dst,[$mem]\n\t"
 5576             "  LGR     $tmp,$dst\n\t"
 5577             "  AGFI    $tmp,$src\n\t"
 5578             "  CSG     $dst,$tmp,$mem\n\t"
 5579             "  retry if failed\n\t"
 5580             "} END ATOMIC"
 5581          %}
 5582   ins_encode %{
 5583     Register Rdst = $dst$$Register;
 5584     Register Rtmp = $tmp$$Register;
 5585     int      Isrc = $src$$constant;
 5586     Label    retry;
 5587 
 5588     // Iterate until update with incremented value succeeds.
 5589     __ z_lg(Rdst, $mem$$Address);  // current contents
 5590     __ bind(retry);
 5591       // Calculate incremented value.
 5592       __ z_lgr(Rtmp, Rdst);
 5593       __ z_agfi(Rtmp, Isrc);
 5594       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5595     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5596   %}
 5597   ins_pipe(pipe_class_dummy);
 5598 %}
 5599 
 5600 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
 5601   match(Set dst (GetAndAddL mem src));
 5602   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5603   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5604   format %{ "BEGIN ATOMIC {\n\t"
 5605             "  LG      $dst,[$mem]\n\t"
 5606             "  AGRK    $tmp,$dst,$src\n\t"
 5607             "  CSG     $dst,$tmp,$mem\n\t"
 5608             "  retry if failed\n\t"
 5609             "} END ATOMIC"
 5610          %}
 5611   ins_encode %{
 5612     Register Rsrc = $src$$Register;
 5613     Register Rdst = $dst$$Register;
 5614     Register Rtmp = $tmp$$Register;
 5615     Label    retry;
 5616 
 5617     // Iterate until update with incremented value succeeds.
 5618     __ z_lg(Rdst, $mem$$Address);  // current contents
 5619     __ bind(retry);
 5620       // Calculate incremented value.
 5621       if (VM_Version::has_DistinctOpnds()) {
 5622         __ z_agrk(Rtmp, Rdst, Rsrc);
 5623       } else {
 5624         __ z_lgr(Rtmp, Rdst);
 5625         __ z_agr(Rtmp, Rsrc);
 5626       }
 5627       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5628     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5629   %}
 5630   ins_pipe(pipe_class_dummy);
 5631 %}
 5632 
 5633 // Increment value in memory, save old value in dst.
 5634 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
 5635   match(Set dst (GetAndAddI mem src));
 5636   predicate(VM_Version::has_LoadAndALUAtomicV1());
 5637   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
 5638   size(6);
 5639   format %{ "LAA     $dst,$src,[$mem]" %}
 5640   ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
 5641   ins_pipe(pipe_class_dummy);
 5642 %}
 5643 
 5644 // Increment value in memory, save old value in dst.
 5645 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
 5646   match(Set dst (GetAndAddL mem src));
 5647   predicate(VM_Version::has_LoadAndALUAtomicV1());
 5648   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
 5649   size(6);
 5650   format %{ "LAAG    $dst,$src,[$mem]" %}
 5651   ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
 5652   ins_pipe(pipe_class_dummy);
 5653 %}
 5654 
 5655 
 5656 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
 5657   match(Set dst (GetAndSetI mem dst));
 5658   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5659   format %{ "XCHGI   $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
 5660   ins_encode(z_enc_SwapI(mem, dst, tmp));
 5661   ins_pipe(pipe_class_dummy);
 5662 %}
 5663 
 5664 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
 5665   match(Set dst (GetAndSetL mem dst));
 5666   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5667   format %{ "XCHGL   $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
 5668   ins_encode(z_enc_SwapL(mem, dst, tmp));
 5669   ins_pipe(pipe_class_dummy);
 5670 %}
 5671 
 5672 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
 5673   match(Set dst (GetAndSetN mem dst));
 5674   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5675   format %{ "XCHGN   $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
 5676   ins_encode(z_enc_SwapI(mem, dst, tmp));
 5677   ins_pipe(pipe_class_dummy);
 5678 %}
 5679 
 5680 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
 5681   match(Set dst (GetAndSetP mem dst));
 5682   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5683   format %{ "XCHGP   $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
 5684   ins_encode(z_enc_SwapL(mem, dst, tmp));
 5685   ins_pipe(pipe_class_dummy);
 5686 %}
 5687 
 5688 
 5689 //----------Arithmetic Instructions--------------------------------------------
 5690 
 5691 // The rules are sorted by right operand type and operand length. Please keep
 5692 // it that way.
 5693 // Left operand type is always reg. Left operand len is I, L, P
 5694 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
 5695 // Special instruction formats, e.g. multi-operand, are inserted at the end.
 5696 
 5697 // ADD
 5698 
 5699 // REG = REG + REG
 5700 
 5701 // Register Addition
 5702 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
 5703   match(Set dst (AddI dst src));
 5704   effect(KILL cr);
 5705   // TODO: s390 port size(FIXED_SIZE);
 5706   format %{ "AR      $dst,$src\t # int  CISC ALU" %}
 5707   opcode(AR_ZOPC);
 5708   ins_encode(z_rrform(dst, src));
 5709   ins_pipe(pipe_class_dummy);
 5710 %}
 5711 
 5712 // Avoid use of LA(Y) for general ALU operation.
 5713 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 5714   match(Set dst (AddI src1 src2));
 5715   effect(KILL cr);
 5716   predicate(VM_Version::has_DistinctOpnds());
 5717   ins_cost(DEFAULT_COST);
 5718   size(4);
 5719   format %{ "ARK     $dst,$src1,$src2\t # int  RISC ALU" %}
 5720   opcode(ARK_ZOPC);
 5721   ins_encode(z_rrfform(dst, src1, src2));
 5722   ins_pipe(pipe_class_dummy);
 5723 %}
 5724 
 5725 // REG = REG + IMM
 5726 
 5727 // Avoid use of LA(Y) for general ALU operation.
 5728 // Immediate Addition
 5729 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
 5730   match(Set dst (AddI dst con));
 5731   effect(KILL cr);
 5732   ins_cost(DEFAULT_COST);
 5733   // TODO: s390 port size(FIXED_SIZE);
 5734   format %{ "AHI     $dst,$con\t # int  CISC ALU" %}
 5735   opcode(AHI_ZOPC);
 5736   ins_encode(z_riform_signed(dst, con));
 5737   ins_pipe(pipe_class_dummy);
 5738 %}
 5739 
 5740 // Avoid use of LA(Y) for general ALU operation.
 5741 // Immediate Addition
 5742 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
 5743   match(Set dst (AddI src con));
 5744   effect(KILL cr);
 5745   predicate( VM_Version::has_DistinctOpnds());
 5746   ins_cost(DEFAULT_COST);
 5747   // TODO: s390 port size(FIXED_SIZE);
 5748   format %{ "AHIK    $dst,$src,$con\t # int  RISC ALU" %}
 5749   opcode(AHIK_ZOPC);
 5750   ins_encode(z_rieform_d(dst, src, con));
 5751   ins_pipe(pipe_class_dummy);
 5752 %}
 5753 
 5754 // Immediate Addition
 5755 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
 5756   match(Set dst (AddI dst src));
 5757   effect(KILL cr);
 5758   ins_cost(DEFAULT_COST_HIGH);
 5759   size(6);
 5760   format %{ "AFI     $dst,$src" %}
 5761   opcode(AFI_ZOPC);
 5762   ins_encode(z_rilform_signed(dst, src));
 5763   ins_pipe(pipe_class_dummy);
 5764 %}
 5765 
 5766 // Immediate Addition
 5767 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
 5768   match(Set dst (AddI src con));
 5769   predicate(PreferLAoverADD);
 5770   ins_cost(DEFAULT_COST_LOW);
 5771   size(4);
 5772   format %{ "LA      $dst,$con(,$src)\t # int d12(,b)" %}
 5773   opcode(LA_ZOPC);
 5774   ins_encode(z_rxform_imm_reg(dst, con, src));
 5775   ins_pipe(pipe_class_dummy);
 5776 %}
 5777 
 5778 // Immediate Addition
 5779 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
 5780   match(Set dst (AddI src con));
 5781   predicate(PreferLAoverADD);
 5782   ins_cost(DEFAULT_COST);
 5783   size(6);
 5784   format %{ "LAY     $dst,$con(,$src)\t # int d20(,b)" %}
 5785   opcode(LAY_ZOPC);
 5786   ins_encode(z_rxyform_imm_reg(dst, con, src));
 5787   ins_pipe(pipe_class_dummy);
 5788 %}
 5789 
 5790 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
 5791   match(Set dst (AddI (AddI src1 src2) con));
 5792   predicate( PreferLAoverADD);
 5793   ins_cost(DEFAULT_COST_LOW);
 5794   size(4);
 5795   format %{ "LA      $dst,$con($src1,$src2)\t # int d12(x,b)" %}
 5796   opcode(LA_ZOPC);
 5797   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 5798   ins_pipe(pipe_class_dummy);
 5799 %}
 5800 
 5801 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
 5802   match(Set dst (AddI (AddI src1 src2) con));
 5803   predicate(PreferLAoverADD);
 5804   ins_cost(DEFAULT_COST);
 5805   size(6);
 5806   format %{ "LAY     $dst,$con($src1,$src2)\t # int d20(x,b)" %}
 5807   opcode(LAY_ZOPC);
 5808   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 5809   ins_pipe(pipe_class_dummy);
 5810 %}
 5811 
 5812 // REG = REG + MEM
 5813 
 5814 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 5815   match(Set dst (AddI dst (LoadI src)));
 5816   effect(KILL cr);
 5817   ins_cost(MEMORY_REF_COST);
 5818   // TODO: s390 port size(VARIABLE_SIZE);
 5819   format %{ "A(Y)    $dst, $src\t # int" %}
 5820   opcode(AY_ZOPC, A_ZOPC);
 5821   ins_encode(z_form_rt_mem_opt(dst, src));
 5822   ins_pipe(pipe_class_dummy);
 5823 %}
 5824 
 5825 // MEM = MEM + IMM
 5826 
 5827 // Add Immediate to 4-byte memory operand and result
 5828 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
 5829   match(Set mem (StoreI mem (AddI (LoadI mem) src)));
 5830   effect(KILL cr);
 5831   predicate(VM_Version::has_MemWithImmALUOps());
 5832   ins_cost(MEMORY_REF_COST);
 5833   size(6);
 5834   format %{ "ASI     $mem,$src\t # direct mem add 4" %}
 5835   opcode(ASI_ZOPC);
 5836   ins_encode(z_siyform(mem, src));
 5837   ins_pipe(pipe_class_dummy);
 5838 %}
 5839 
 5840 
 5841 //
 5842 
 5843 // REG = REG + REG
 5844 
 5845 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
 5846   match(Set dst (AddL dst (ConvI2L src)));
 5847   effect(KILL cr);
 5848   size(4);
 5849   format %{ "AGFR    $dst,$src\t # long<-int CISC ALU" %}
 5850   opcode(AGFR_ZOPC);
 5851   ins_encode(z_rreform(dst, src));
 5852   ins_pipe(pipe_class_dummy);
 5853 %}
 5854 
 5855 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
 5856   match(Set dst (AddL dst src));
 5857   effect(KILL cr);
 5858   // TODO: s390 port size(FIXED_SIZE);
 5859   format %{ "AGR     $dst, $src\t # long CISC ALU" %}
 5860   opcode(AGR_ZOPC);
 5861   ins_encode(z_rreform(dst, src));
 5862   ins_pipe(pipe_class_dummy);
 5863 %}
 5864 
 5865 // Avoid use of LA(Y) for general ALU operation.
 5866 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
 5867   match(Set dst (AddL src1 src2));
 5868   effect(KILL cr);
 5869   predicate(VM_Version::has_DistinctOpnds());
 5870   ins_cost(DEFAULT_COST);
 5871   size(4);
 5872   format %{ "AGRK    $dst,$src1,$src2\t # long RISC ALU" %}
 5873   opcode(AGRK_ZOPC);
 5874   ins_encode(z_rrfform(dst, src1, src2));
 5875   ins_pipe(pipe_class_dummy);
 5876 %}
 5877 
 5878 // REG = REG + IMM
 5879 
 5880 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
 5881   match(Set dst (AddL src con));
 5882   predicate( PreferLAoverADD);
 5883   ins_cost(DEFAULT_COST_LOW);
 5884   size(4);
 5885   format %{ "LA      $dst,$con(,$src)\t # long d12(,b)" %}
 5886   opcode(LA_ZOPC);
 5887   ins_encode(z_rxform_imm_reg(dst, con, src));
 5888   ins_pipe(pipe_class_dummy);
 5889 %}
 5890 
 5891 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
 5892   match(Set dst (AddL src con));
 5893   predicate(PreferLAoverADD);
 5894   ins_cost(DEFAULT_COST);
 5895   size(6);
 5896   format %{ "LAY     $dst,$con(,$src)\t # long d20(,b)" %}
 5897   opcode(LAY_ZOPC);
 5898   ins_encode(z_rxyform_imm_reg(dst, con, src));
 5899   ins_pipe(pipe_class_dummy);
 5900 %}
 5901 
 5902 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
 5903   match(Set dst (AddL dst con));
 5904   effect(KILL cr);
 5905   ins_cost(DEFAULT_COST_HIGH);
 5906   size(6);
 5907   format %{ "AGFI    $dst,$con\t # long CISC ALU" %}
 5908   opcode(AGFI_ZOPC);
 5909   ins_encode(z_rilform_signed(dst, con));
 5910   ins_pipe(pipe_class_dummy);
 5911 %}
 5912 
 5913 // Avoid use of LA(Y) for general ALU operation.
 5914 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
 5915   match(Set dst (AddL dst con));
 5916   effect(KILL cr);
 5917   ins_cost(DEFAULT_COST);
 5918   // TODO: s390 port size(FIXED_SIZE);
 5919   format %{ "AGHI    $dst,$con\t # long CISC ALU" %}
 5920   opcode(AGHI_ZOPC);
 5921   ins_encode(z_riform_signed(dst, con));
 5922   ins_pipe(pipe_class_dummy);
 5923 %}
 5924 
 5925 // Avoid use of LA(Y) for general ALU operation.
 5926 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
 5927   match(Set dst (AddL src con));
 5928   effect(KILL cr);
 5929   predicate( VM_Version::has_DistinctOpnds());
 5930   ins_cost(DEFAULT_COST);
 5931   size(6);
 5932   format %{ "AGHIK   $dst,$src,$con\t # long RISC ALU" %}
 5933   opcode(AGHIK_ZOPC);
 5934   ins_encode(z_rieform_d(dst, src, con));
 5935   ins_pipe(pipe_class_dummy);
 5936 %}
 5937 
 5938 // REG = REG + MEM
 5939 
 5940 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
 5941   match(Set dst (AddL dst (ConvI2L (LoadI src))));
 5942   effect(KILL cr);
 5943   ins_cost(MEMORY_REF_COST);
 5944   size(Z_DISP3_SIZE);
 5945   format %{ "AGF     $dst, $src\t # long/int" %}
 5946   opcode(AGF_ZOPC, AGF_ZOPC);
 5947   ins_encode(z_form_rt_mem_opt(dst, src));
 5948   ins_pipe(pipe_class_dummy);
 5949 %}
 5950 
 5951 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 5952   match(Set dst (AddL dst (LoadL src)));
 5953   effect(KILL cr);
 5954   ins_cost(MEMORY_REF_COST);
 5955   size(Z_DISP3_SIZE);
 5956   format %{ "AG      $dst, $src\t # long" %}
 5957   opcode(AG_ZOPC, AG_ZOPC);
 5958   ins_encode(z_form_rt_mem_opt(dst, src));
 5959   ins_pipe(pipe_class_dummy);
 5960 %}
 5961 
 5962 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
 5963   match(Set dst (AddL (AddL src1 src2) con));
 5964   predicate( PreferLAoverADD);
 5965   ins_cost(DEFAULT_COST_LOW);
 5966   size(4);
 5967   format %{ "LA     $dst,$con($src1,$src2)\t # long d12(x,b)" %}
 5968   opcode(LA_ZOPC);
 5969   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 5970   ins_pipe(pipe_class_dummy);
 5971 %}
 5972 
 5973 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
 5974   match(Set dst (AddL (AddL src1 src2) con));
 5975   predicate(PreferLAoverADD);
 5976   ins_cost(DEFAULT_COST);
 5977   size(6);
 5978   format %{ "LAY    $dst,$con($src1,$src2)\t # long d20(x,b)" %}
 5979   opcode(LAY_ZOPC);
 5980   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 5981   ins_pipe(pipe_class_dummy);
 5982 %}
 5983 
 5984 // MEM = MEM + IMM
 5985 
 5986 // Add Immediate to 8-byte memory operand and result.
 5987 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
 5988   match(Set mem (StoreL mem (AddL (LoadL mem) src)));
 5989   effect(KILL cr);
 5990   predicate(VM_Version::has_MemWithImmALUOps());
 5991   ins_cost(MEMORY_REF_COST);
 5992   size(6);
 5993   format %{ "AGSI    $mem,$src\t # direct mem add 8" %}
 5994   opcode(AGSI_ZOPC);
 5995   ins_encode(z_siyform(mem, src));
 5996   ins_pipe(pipe_class_dummy);
 5997 %}
 5998 
 5999 
 6000 // REG = REG + REG
 6001 
 6002 // Ptr Addition
 6003 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
 6004   match(Set dst (AddP src1 src2));
 6005   predicate( PreferLAoverADD);
 6006   ins_cost(DEFAULT_COST);
 6007   size(4);
 6008   format %{ "LA      $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
 6009   opcode(LA_ZOPC);
 6010   ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
 6011   ins_pipe(pipe_class_dummy);
 6012 %}
 6013 
 6014 // Ptr Addition
 6015 // Avoid use of LA(Y) for general ALU operation.
 6016 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
 6017   match(Set dst (AddP dst src));
 6018   effect(KILL cr);
 6019   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
 6020   ins_cost(DEFAULT_COST);
 6021   // TODO: s390 port size(FIXED_SIZE);
 6022   format %{ "ALGR    $dst,$src\t # ptr CICS ALU" %}
 6023   opcode(ALGR_ZOPC);
 6024   ins_encode(z_rreform(dst, src));
 6025   ins_pipe(pipe_class_dummy);
 6026 %}
 6027 
 6028 // Ptr Addition
 6029 // Avoid use of LA(Y) for general ALU operation.
 6030 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
 6031   match(Set dst (AddP src1 src2));
 6032   effect(KILL cr);
 6033   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
 6034   ins_cost(DEFAULT_COST);
 6035   // TODO: s390 port size(FIXED_SIZE);
 6036   format %{ "ALGRK   $dst,$src1,$src2\t # ptr RISC ALU" %}
 6037   opcode(ALGRK_ZOPC);
 6038   ins_encode(z_rrfform(dst, src1, src2));
 6039   ins_pipe(pipe_class_dummy);
 6040 %}
 6041 
 6042 // REG = REG + IMM
 6043 
 6044 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
 6045   match(Set dst (AddP src con));
 6046   predicate( PreferLAoverADD);
 6047   ins_cost(DEFAULT_COST_LOW);
 6048   size(4);
 6049   format %{ "LA      $dst,$con(,$src)\t # ptr d12(,b)" %}
 6050   opcode(LA_ZOPC);
 6051   ins_encode(z_rxform_imm_reg(dst, con, src));
 6052   ins_pipe(pipe_class_dummy);
 6053 %}
 6054 
 6055 // Avoid use of LA(Y) for general ALU operation.
 6056 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
 6057   match(Set dst (AddP dst src));
 6058   effect(KILL cr);
 6059   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
 6060   ins_cost(DEFAULT_COST);
 6061   // TODO: s390 port size(FIXED_SIZE);
 6062   format %{ "AGHI    $dst,$src\t # ptr CISC ALU" %}
 6063   opcode(AGHI_ZOPC);
 6064   ins_encode(z_riform_signed(dst, src));
 6065   ins_pipe(pipe_class_dummy);
 6066 %}
 6067 
 6068 // Avoid use of LA(Y) for general ALU operation.
 6069 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
 6070   match(Set dst (AddP src con));
 6071   effect(KILL cr);
 6072   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
 6073   ins_cost(DEFAULT_COST);
 6074   // TODO: s390 port size(FIXED_SIZE);
 6075   format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
 6076   opcode(ALGHSIK_ZOPC);
 6077   ins_encode(z_rieform_d(dst, src, con));
 6078   ins_pipe(pipe_class_dummy);
 6079 %}
 6080 
 6081 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
 6082   match(Set dst (AddP src con));
 6083   predicate(PreferLAoverADD);
 6084   ins_cost(DEFAULT_COST);
 6085   size(6);
 6086   format %{ "LAY     $dst,$con(,$src)\t # ptr d20(,b)" %}
 6087   opcode(LAY_ZOPC);
 6088   ins_encode(z_rxyform_imm_reg(dst, con, src));
 6089   ins_pipe(pipe_class_dummy);
 6090 %}
 6091 
 6092 // Pointer Immediate Addition
 6093 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
 6094   match(Set dst (AddP dst src));
 6095   effect(KILL cr);
 6096   ins_cost(DEFAULT_COST_HIGH);
 6097   // TODO: s390 port size(FIXED_SIZE);
 6098   format %{ "AGFI    $dst,$src\t # ptr" %}
 6099   opcode(AGFI_ZOPC);
 6100   ins_encode(z_rilform_signed(dst, src));
 6101   ins_pipe(pipe_class_dummy);
 6102 %}
 6103 
 6104 // REG = REG1 + REG2 + IMM
 6105 
 6106 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
 6107   match(Set dst (AddP (AddP src1 src2) con));
 6108   predicate( PreferLAoverADD);
 6109   ins_cost(DEFAULT_COST_LOW);
 6110   size(4);
 6111   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
 6112   opcode(LA_ZOPC);
 6113   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 6114   ins_pipe(pipe_class_dummy);
 6115 %}
 6116 
 6117 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
 6118   match(Set dst (AddP (AddP src1 src2) con));
 6119   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 6120   ins_cost(DEFAULT_COST_LOW);
 6121   size(4);
 6122   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
 6123   opcode(LA_ZOPC);
 6124   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 6125   ins_pipe(pipe_class_dummy);
 6126 %}
 6127 
 6128 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
 6129   match(Set dst (AddP (AddP src1 src2) con));
 6130   predicate(PreferLAoverADD);
 6131   ins_cost(DEFAULT_COST);
 6132   // TODO: s390 port size(FIXED_SIZE);
 6133   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
 6134   opcode(LAY_ZOPC);
 6135   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 6136   ins_pipe(pipe_class_dummy);
 6137 %}
 6138 
 6139 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
 6140   match(Set dst (AddP (AddP src1 src2) con));
 6141   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 6142   ins_cost(DEFAULT_COST);
 6143   // TODO: s390 port size(FIXED_SIZE);
 6144   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
 6145   opcode(LAY_ZOPC);
 6146   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 6147   ins_pipe(pipe_class_dummy);
 6148 %}
 6149 
 6150 // MEM = MEM + IMM
 6151 
 6152 // Add Immediate to 8-byte memory operand and result
 6153 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
 6154   match(Set mem (StoreP mem (AddP (LoadP mem) src)));
 6155   effect(KILL cr);
 6156   predicate(VM_Version::has_MemWithImmALUOps());
 6157   ins_cost(MEMORY_REF_COST);
 6158   size(6);
 6159   format %{ "AGSI    $mem,$src\t # direct mem add 8 (ptr)" %}
 6160   opcode(AGSI_ZOPC);
 6161   ins_encode(z_siyform(mem, src));
 6162   ins_pipe(pipe_class_dummy);
 6163 %}
 6164 
 6165 // SUB
 6166 
 6167 // Register Subtraction
 6168 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
 6169   match(Set dst (SubI dst src));
 6170   effect(KILL cr);
 6171   // TODO: s390 port size(FIXED_SIZE);
 6172   format %{ "SR      $dst,$src\t # int  CISC ALU" %}
 6173   opcode(SR_ZOPC);
 6174   ins_encode(z_rrform(dst, src));
 6175   ins_pipe(pipe_class_dummy);
 6176 %}
 6177 
 6178 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 6179   match(Set dst (SubI src1 src2));
 6180   effect(KILL cr);
 6181   predicate(VM_Version::has_DistinctOpnds());
 6182   ins_cost(DEFAULT_COST);
 6183   size(4);
 6184   format %{ "SRK     $dst,$src1,$src2\t # int  RISC ALU" %}
 6185   opcode(SRK_ZOPC);
 6186   ins_encode(z_rrfform(dst, src1, src2));
 6187   ins_pipe(pipe_class_dummy);
 6188 %}
 6189 
 6190 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 6191   match(Set dst (SubI dst (LoadI src)));
 6192   effect(KILL cr);
 6193   ins_cost(MEMORY_REF_COST);
 6194   // TODO: s390 port size(VARIABLE_SIZE);
 6195   format %{ "S(Y)    $dst, $src\t # int" %}
 6196   opcode(SY_ZOPC, S_ZOPC);
 6197   ins_encode(z_form_rt_mem_opt(dst, src));
 6198   ins_pipe(pipe_class_dummy);
 6199 %}
 6200 
 6201 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
 6202   match(Set dst (SubI zero src));
 6203   effect(KILL cr);
 6204   size(2);
 6205   format %{ "NEG     $dst, $src" %}
 6206   ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
 6207   ins_pipe(pipe_class_dummy);
 6208 %}
 6209 
 6210 //
 6211 
 6212 // Long subtraction
 6213 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
 6214   match(Set dst (SubL dst src));
 6215   effect(KILL cr);
 6216   // TODO: s390 port size(FIXED_SIZE);
 6217   format %{ "SGR     $dst,$src\t # int  CISC ALU" %}
 6218   opcode(SGR_ZOPC);
 6219   ins_encode(z_rreform(dst, src));
 6220   ins_pipe(pipe_class_dummy);
 6221 %}
 6222 
 6223 // Avoid use of LA(Y) for general ALU operation.
 6224 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
 6225   match(Set dst (SubL src1 src2));
 6226   effect(KILL cr);
 6227   predicate(VM_Version::has_DistinctOpnds());
 6228   ins_cost(DEFAULT_COST);
 6229   size(4);
 6230   format %{ "SGRK    $dst,$src1,$src2\t # int  RISC ALU" %}
 6231   opcode(SGRK_ZOPC);
 6232   ins_encode(z_rrfform(dst, src1, src2));
 6233   ins_pipe(pipe_class_dummy);
 6234 %}
 6235 
 6236 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
 6237   match(Set dst (SubL dst (ConvI2L src)));
 6238   effect(KILL cr);
 6239   size(4);
 6240   format %{ "SGFR    $dst, $src\t # int  CISC ALU" %}
 6241   opcode(SGFR_ZOPC);
 6242   ins_encode(z_rreform(dst, src));
 6243   ins_pipe(pipe_class_dummy);
 6244 %}
 6245 
 6246 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
 6247   match(Set dst (SubL dst (ConvI2L (LoadI src))));
 6248   effect(KILL cr);
 6249   ins_cost(MEMORY_REF_COST);
 6250   size(Z_DISP3_SIZE);
 6251   format %{ "SGF     $dst, $src\t # long/int" %}
 6252   opcode(SGF_ZOPC, SGF_ZOPC);
 6253   ins_encode(z_form_rt_mem_opt(dst, src));
 6254   ins_pipe(pipe_class_dummy);
 6255 %}
 6256 
 6257 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 6258   match(Set dst (SubL dst (LoadL src)));
 6259   effect(KILL cr);
 6260   ins_cost(MEMORY_REF_COST);
 6261   size(Z_DISP3_SIZE);
 6262   format %{ "SG      $dst, $src\t # long" %}
 6263   opcode(SG_ZOPC, SG_ZOPC);
 6264   ins_encode(z_form_rt_mem_opt(dst, src));
 6265   ins_pipe(pipe_class_dummy);
 6266 %}
 6267 
 6268 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
 6269 
 6270 //  MUL
 6271 
 6272 // Register Multiplication
 6273 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
 6274   match(Set dst (MulI dst src));
 6275   ins_cost(DEFAULT_COST);
 6276   size(4);
 6277   format %{ "MSR     $dst, $src" %}
 6278   opcode(MSR_ZOPC);
 6279   ins_encode(z_rreform(dst, src));
 6280   ins_pipe(pipe_class_dummy);
 6281 %}
 6282 
 6283 // Immediate Multiplication
 6284 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
 6285   match(Set dst (MulI dst con));
 6286   ins_cost(DEFAULT_COST);
 6287   // TODO: s390 port size(FIXED_SIZE);
 6288   format %{ "MHI     $dst,$con" %}
 6289   opcode(MHI_ZOPC);
 6290   ins_encode(z_riform_signed(dst,con));
 6291   ins_pipe(pipe_class_dummy);
 6292 %}
 6293 
 6294 // Immediate (32bit) Multiplication
 6295 instruct mulI_reg_imm32(iRegI dst, immI con) %{
 6296   match(Set dst (MulI dst con));
 6297   ins_cost(DEFAULT_COST);
 6298   size(6);
 6299   format %{ "MSFI    $dst,$con" %}
 6300   opcode(MSFI_ZOPC);
 6301   ins_encode(z_rilform_signed(dst,con));
 6302   ins_pipe(pipe_class_dummy);
 6303 %}
 6304 
 6305 instruct mulI_Reg_mem(iRegI dst, memory src)%{
 6306   match(Set dst (MulI dst (LoadI src)));
 6307   ins_cost(MEMORY_REF_COST);
 6308   // TODO: s390 port size(VARIABLE_SIZE);
 6309   format %{ "MS(Y)   $dst, $src\t # int" %}
 6310   opcode(MSY_ZOPC, MS_ZOPC);
 6311   ins_encode(z_form_rt_mem_opt(dst, src));
 6312   ins_pipe(pipe_class_dummy);
 6313 %}
 6314 
 6315 //
 6316 
 6317 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
 6318   match(Set dst (MulL dst (ConvI2L src)));
 6319   ins_cost(DEFAULT_COST);
 6320   // TODO: s390 port size(FIXED_SIZE);
 6321   format %{ "MSGFR   $dst $src\t # long/int" %}
 6322   opcode(MSGFR_ZOPC);
 6323   ins_encode(z_rreform(dst, src));
 6324   ins_pipe(pipe_class_dummy);
 6325 %}
 6326 
 6327 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
 6328   match(Set dst (MulL dst src));
 6329   ins_cost(DEFAULT_COST);
 6330   size(4);
 6331   format %{ "MSGR    $dst $src\t # long" %}
 6332   opcode(MSGR_ZOPC);
 6333   ins_encode(z_rreform(dst, src));
 6334   ins_pipe(pipe_class_dummy);
 6335 %}
 6336 
 6337 // Immediate Multiplication
 6338 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
 6339   match(Set dst (MulL dst src));
 6340   ins_cost(DEFAULT_COST);
 6341   // TODO: s390 port size(FIXED_SIZE);
 6342   format %{ "MGHI    $dst,$src\t # long" %}
 6343   opcode(MGHI_ZOPC);
 6344   ins_encode(z_riform_signed(dst, src));
 6345   ins_pipe(pipe_class_dummy);
 6346 %}
 6347 
 6348 // Immediate (32bit) Multiplication
 6349 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
 6350   match(Set dst (MulL dst con));
 6351   ins_cost(DEFAULT_COST);
 6352   size(6);
 6353   format %{ "MSGFI   $dst,$con" %}
 6354   opcode(MSGFI_ZOPC);
 6355   ins_encode(z_rilform_signed(dst,con));
 6356   ins_pipe(pipe_class_dummy);
 6357 %}
 6358 
 6359 instruct mulL_Reg_memI(iRegL dst, memory src)%{
 6360   match(Set dst (MulL dst (ConvI2L (LoadI src))));
 6361   ins_cost(MEMORY_REF_COST);
 6362   size(Z_DISP3_SIZE);
 6363   format %{ "MSGF    $dst, $src\t # long" %}
 6364   opcode(MSGF_ZOPC, MSGF_ZOPC);
 6365   ins_encode(z_form_rt_mem_opt(dst, src));
 6366   ins_pipe(pipe_class_dummy);
 6367 %}
 6368 
 6369 instruct mulL_Reg_mem(iRegL dst, memory src)%{
 6370   match(Set dst (MulL dst (LoadL src)));
 6371   ins_cost(MEMORY_REF_COST);
 6372   size(Z_DISP3_SIZE);
 6373   format %{ "MSG     $dst, $src\t # long" %}
 6374   opcode(MSG_ZOPC, MSG_ZOPC);
 6375   ins_encode(z_form_rt_mem_opt(dst, src));
 6376   ins_pipe(pipe_class_dummy);
 6377 %}
 6378 
 6379 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
 6380   match(Set Rdst (MulHiL Rsrc1 Rsrc2));
 6381   effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
 6382   ins_cost(7*DEFAULT_COST);
 6383   // TODO: s390 port size(VARIABLE_SIZE);
 6384   format %{ "MulHiL  $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
 6385   ins_encode%{
 6386     Register dst  = $Rdst$$Register;
 6387     Register src1 = $Rsrc1$$Register;
 6388     Register src2 = $Rsrc2$$Register;
 6389     Register tmp1 = $Rtmp1$$Register;
 6390     Register tmp2 = $Rdst$$Register;
 6391     // z/Architecture has only unsigned multiply (64 * 64 -> 128).
 6392     // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
 6393     __ z_srag(tmp2, src1, 63);  // a>>63
 6394     __ z_srag(tmp1, src2, 63);  // b>>63
 6395     __ z_ngr(tmp2, src2);       // b & (a>>63)
 6396     __ z_ngr(tmp1, src1);       // a & (b>>63)
 6397     __ z_agr(tmp1, tmp2);       // ((a & (b>>63)) + (b & (a>>63)))
 6398     __ z_mlgr(dst, src2);       // tricky: 128-bit product is written to even/odd pair (dst,src1),
 6399                                 //         multiplicand is taken from oddReg (src1), multiplier in src2.
 6400     __ z_sgr(dst, tmp1);
 6401   %}
 6402   ins_pipe(pipe_class_dummy);
 6403 %}
 6404 
 6405 //  DIV
 6406 
 6407 // Integer DIVMOD with Register, both quotient and mod results
 6408 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
 6409   match(DivModI dst1src1 src2);
 6410   effect(KILL cr);
 6411   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6412   size((VM_Version::has_CompareBranch() ? 24 : 26));
 6413   format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
 6414   ins_encode %{
 6415     Register d1s1 = $dst1src1$$Register;
 6416     Register d2   = $dst2$$Register;
 6417     Register s2   = $src2$$Register;
 6418 
 6419     assert_different_registers(d1s1, s2);
 6420 
 6421     Label do_div, done_div;
 6422     if (VM_Version::has_CompareBranch()) {
 6423       __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
 6424     } else {
 6425       __ z_chi(s2, -1);
 6426       __ z_brne(do_div);
 6427     }
 6428     __ z_lcr(d1s1, d1s1);
 6429     __ clear_reg(d2, false, false);
 6430     __ z_bru(done_div);
 6431     __ bind(do_div);
 6432     __ z_lgfr(d1s1, d1s1);
 6433     __ z_dsgfr(d2, s2);
 6434     __ bind(done_div);
 6435   %}
 6436   ins_pipe(pipe_class_dummy);
 6437 %}
 6438 
 6439 
 6440 // Register Division
 6441 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
 6442   match(Set dst (DivI src1 src2));
 6443   effect(KILL tmp, KILL cr);
 6444   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6445   size((VM_Version::has_CompareBranch() ? 20 : 22));
 6446   format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
 6447   ins_encode %{
 6448     Register a = $src1$$Register;
 6449     Register b = $src2$$Register;
 6450     Register t = $dst$$Register;
 6451 
 6452     assert_different_registers(t, b);
 6453 
 6454     Label do_div, done_div;
 6455     if (VM_Version::has_CompareBranch()) {
 6456       __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
 6457     } else {
 6458       __ z_chi(b, -1);
 6459       __ z_brne(do_div);
 6460     }
 6461     __ z_lcr(t, a);
 6462     __ z_bru(done_div);
 6463     __ bind(do_div);
 6464     __ z_lgfr(t, a);
 6465     __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
 6466     __ bind(done_div);
 6467   %}
 6468   ins_pipe(pipe_class_dummy);
 6469 %}
 6470 
 6471 // Immediate Division
 6472 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
 6473   match(Set dst (DivI src1 src2));
 6474   effect(KILL tmp, KILL cr);  // R0 is killed, too.
 6475   ins_cost(2 * DEFAULT_COST);
 6476   // TODO: s390 port size(VARIABLE_SIZE);
 6477   format %{ "DIV_const  $dst,$src1,$src2" %}
 6478   ins_encode %{
 6479     // No sign extension of Rdividend needed here.
 6480     if ($src2$$constant != -1) {
 6481       __ z_lghi(Z_R0_scratch, $src2$$constant);
 6482       __ z_lgfr($dst$$Register, $src1$$Register);
 6483       __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
 6484     } else {
 6485       __ z_lcr($dst$$Register, $src1$$Register);
 6486     }
 6487   %}
 6488   ins_pipe(pipe_class_dummy);
 6489 %}
 6490 
 6491 // Long DIVMOD with Register, both quotient and mod results
 6492 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
 6493   match(DivModL dst1src1 src2);
 6494   effect(KILL cr);
 6495   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6496   size((VM_Version::has_CompareBranch() ? 22 : 24));
 6497   format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
 6498   ins_encode %{
 6499     Register d1s1 = $dst1src1$$Register;
 6500     Register d2   = $dst2$$Register;
 6501     Register s2   = $src2$$Register;
 6502 
 6503     Label do_div, done_div;
 6504     if (VM_Version::has_CompareBranch()) {
 6505       __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
 6506     } else {
 6507       __ z_cghi(s2, -1);
 6508       __ z_brne(do_div);
 6509     }
 6510     __ z_lcgr(d1s1, d1s1);
 6511     // indicate unused result
 6512     (void) __ clear_reg(d2, true, false);
 6513     __ z_bru(done_div);
 6514     __ bind(do_div);
 6515     __ z_dsgr(d2, s2);
 6516     __ bind(done_div);
 6517   %}
 6518   ins_pipe(pipe_class_dummy);
 6519 %}
 6520 
 6521 // Register Long Division
 6522 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
 6523   match(Set dst (DivL dst src));
 6524   effect(KILL tmp, KILL cr);
 6525   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6526   size((VM_Version::has_CompareBranch() ? 18 : 20));
 6527   format %{ "DIVG_checked  $dst, $src\t # long, treats special case 0x80../-1" %}
 6528   ins_encode %{
 6529     Register b = $src$$Register;
 6530     Register t = $dst$$Register;
 6531 
 6532     Label done_div;
 6533     __ z_lcgr(t, t);    // Does no harm. divisor is in other register.
 6534     if (VM_Version::has_CompareBranch()) {
 6535       __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
 6536     } else {
 6537       __ z_cghi(b, -1);
 6538       __ z_bre(done_div);
 6539     }
 6540     __ z_lcgr(t, t);    // Restore sign.
 6541     __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
 6542     __ bind(done_div);
 6543   %}
 6544   ins_pipe(pipe_class_dummy);
 6545 %}
 6546 
 6547 // Immediate Long Division
 6548 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
 6549   match(Set dst (DivL src1 src2));
 6550   effect(KILL tmp, KILL cr);  // R0 is killed, too.
 6551   ins_cost(2 * DEFAULT_COST);
 6552   // TODO: s390 port size(VARIABLE_SIZE);
 6553   format %{ "DIVG_const  $dst,$src1,$src2\t # long" %}
 6554   ins_encode %{
 6555     if ($src2$$constant != -1) {
 6556       __ z_lghi(Z_R0_scratch, $src2$$constant);
 6557       __ lgr_if_needed($dst$$Register, $src1$$Register);
 6558       __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
 6559     } else {
 6560       __ z_lcgr($dst$$Register, $src1$$Register);
 6561     }
 6562   %}
 6563   ins_pipe(pipe_class_dummy);
 6564 %}
 6565 
 6566 // REM
 6567 
 6568 // Integer Remainder
 6569 // Register Remainder
 6570 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
 6571   match(Set dst (ModI src1 src2));
 6572   effect(KILL tmp, KILL cr);
 6573   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6574   // TODO: s390 port size(VARIABLE_SIZE);
 6575   format %{ "MOD_checked   $dst,$src1,$src2" %}
 6576   ins_encode %{
 6577     Register a = $src1$$Register;
 6578     Register b = $src2$$Register;
 6579     Register t = $dst$$Register;
 6580     assert_different_registers(t->successor(), b);
 6581 
 6582     Label do_div, done_div;
 6583 
 6584     if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
 6585       (void) __ clear_reg(t, true, false);  // Does no harm. Operands are in other regs.
 6586       if (VM_Version::has_CompareBranch()) {
 6587         __ z_cij(b, -1, Assembler::bcondEqual, done_div);
 6588       } else {
 6589         __ z_chi(b, -1);
 6590         __ z_bre(done_div);
 6591       }
 6592       __ z_lgfr(t->successor(), a);
 6593       __ z_dsgfr(t/* t is even part of a register pair. */, b);
 6594     } else {
 6595       if (VM_Version::has_CompareBranch()) {
 6596         __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
 6597       } else {
 6598         __ z_chi(b, -1);
 6599         __ z_brne(do_div);
 6600       }
 6601       __ clear_reg(t, true, false);
 6602       __ z_bru(done_div);
 6603       __ bind(do_div);
 6604       __ z_lgfr(t->successor(), a);
 6605       __ z_dsgfr(t/* t is even part of a register pair. */, b);
 6606     }
 6607     __ bind(done_div);
 6608   %}
 6609   ins_pipe(pipe_class_dummy);
 6610 %}
 6611 
 6612 // Immediate Remainder
 6613 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
 6614   match(Set dst (ModI src1 src2));
 6615   effect(KILL tmp, KILL cr); // R0 is killed, too.
 6616   ins_cost(3 * DEFAULT_COST);
 6617   // TODO: s390 port size(VARIABLE_SIZE);
 6618   format %{ "MOD_const  $dst,src1,$src2" %}
 6619   ins_encode %{
 6620     assert_different_registers($dst$$Register, $src1$$Register);
 6621     assert_different_registers($dst$$Register->successor(), $src1$$Register);
 6622     int divisor = $src2$$constant;
 6623 
 6624     if (divisor != -1) {
 6625       __ z_lghi(Z_R0_scratch, divisor);
 6626       __ z_lgfr($dst$$Register->successor(), $src1$$Register);
 6627       __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
 6628     } else {
 6629       __ clear_reg($dst$$Register, true, false);
 6630     }
 6631   %}
 6632   ins_pipe(pipe_class_dummy);
 6633 %}
 6634 
 6635 // Register Long Remainder
 6636 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
 6637   match(Set dst (ModL src1 src2));
 6638   effect(KILL src1, KILL cr); // R0 is killed, too.
 6639   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6640   // TODO: s390 port size(VARIABLE_SIZE);
 6641   format %{ "MODG_checked   $dst,$src1,$src2" %}
 6642   ins_encode %{
 6643     Register a = $src1$$Register;
 6644     Register b = $src2$$Register;
 6645     Register t = $dst$$Register;
 6646     assert(t->successor() == a, "(t,a) is an even-odd pair" );
 6647 
 6648     Label do_div, done_div;
 6649     if (t->encoding() != b->encoding()) {
 6650       (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
 6651       if (VM_Version::has_CompareBranch()) {
 6652         __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
 6653       } else {
 6654         __ z_cghi(b, -1);
 6655         __ z_bre(done_div);
 6656       }
 6657       __ z_dsgr(t, b);
 6658     } else {
 6659       if (VM_Version::has_CompareBranch()) {
 6660         __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
 6661       } else {
 6662         __ z_cghi(b, -1);
 6663         __ z_brne(do_div);
 6664       }
 6665       __ clear_reg(t, true, false);
 6666       __ z_bru(done_div);
 6667       __ bind(do_div);
 6668       __ z_dsgr(t, b);
 6669     }
 6670     __ bind(done_div);
 6671   %}
 6672   ins_pipe(pipe_class_dummy);
 6673 %}
 6674 
 6675 // Register Long Remainder
 6676 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
 6677   match(Set dst (ModL src1 src2));
 6678   effect(KILL tmp, KILL cr); // R0 is killed, too.
 6679   ins_cost(3 * DEFAULT_COST);
 6680   // TODO: s390 port size(VARIABLE_SIZE);
 6681   format %{ "MODG_const  $dst,src1,$src2\t # long" %}
 6682   ins_encode %{
 6683     int divisor = $src2$$constant;
 6684     if (divisor != -1) {
 6685       __ z_lghi(Z_R0_scratch, divisor);
 6686       __ z_lgr($dst$$Register->successor(), $src1$$Register);
 6687       __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch);  // Instruction kills tmp.
 6688     } else {
 6689       __ clear_reg($dst$$Register, true, false);
 6690     }
 6691   %}
 6692   ins_pipe(pipe_class_dummy);
 6693 %}
 6694 
 6695 // SHIFT
 6696 
 6697 // Shift left logical
 6698 
 6699 // Register Shift Left variable
 6700 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
 6701   match(Set dst (LShiftI src nbits));
 6702   effect(KILL cr); // R1 is killed, too.
 6703   ins_cost(3 * DEFAULT_COST);
 6704   size(14);
 6705   format %{ "SLL     $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
 6706   ins_encode %{
 6707     __ z_lgr(Z_R1_scratch, $nbits$$Register);
 6708     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6709     __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
 6710   %}
 6711   ins_pipe(pipe_class_dummy);
 6712 %}
 6713 
 6714 // Register Shift Left Immediate
 6715 // Constant shift count is masked in ideal graph already.
 6716 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
 6717   match(Set dst (LShiftI src nbits));
 6718   size(6);
 6719   format %{ "SLL     $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
 6720   ins_encode %{
 6721     int Nbit = $nbits$$constant;
 6722     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6723     __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6724   %}
 6725   ins_pipe(pipe_class_dummy);
 6726 %}
 6727 
 6728 // Register Shift Left Immediate by 1bit
 6729 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
 6730   match(Set dst (LShiftI src nbits));
 6731   predicate(PreferLAoverADD);
 6732   ins_cost(DEFAULT_COST_LOW);
 6733   size(4);
 6734   format %{ "LA      $dst,#0($src,$src)\t # SLL by 1 (int)" %}
 6735   ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
 6736   ins_pipe(pipe_class_dummy);
 6737 %}
 6738 
 6739 // Register Shift Left Long
 6740 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
 6741   match(Set dst (LShiftL src1 nbits));
 6742   size(6);
 6743   format %{ "SLLG    $dst,$src1,[$nbits]" %}
 6744   opcode(SLLG_ZOPC);
 6745   ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
 6746   ins_pipe(pipe_class_dummy);
 6747 %}
 6748 
 6749 // Register Shift Left Long Immediate
 6750 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
 6751   match(Set dst (LShiftL src1 nbits));
 6752   size(6);
 6753   format %{ "SLLG    $dst,$src1,$nbits" %}
 6754   opcode(SLLG_ZOPC);
 6755   ins_encode(z_rsyform_const(dst, src1, nbits));
 6756   ins_pipe(pipe_class_dummy);
 6757 %}
 6758 
 6759 // Register Shift Left Long Immediate by 1bit
 6760 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
 6761   match(Set dst (LShiftL src1 nbits));
 6762   predicate(PreferLAoverADD);
 6763   ins_cost(DEFAULT_COST_LOW);
 6764   size(4);
 6765   format %{ "LA      $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
 6766   ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
 6767   ins_pipe(pipe_class_dummy);
 6768 %}
 6769 
 6770 // Shift right arithmetic
 6771 
 6772 // Register Arithmetic Shift Right
 6773 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 6774   match(Set dst (RShiftI dst src));
 6775   effect(KILL cr); // R1 is killed, too.
 6776   ins_cost(3 * DEFAULT_COST);
 6777   size(12);
 6778   format %{ "SRA     $dst,[$src] & 31" %}
 6779   ins_encode %{
 6780     __ z_lgr(Z_R1_scratch, $src$$Register);
 6781     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6782     __ z_sra($dst$$Register, 0, Z_R1_scratch);
 6783   %}
 6784   ins_pipe(pipe_class_dummy);
 6785 %}
 6786 
 6787 // Register Arithmetic Shift Right Immediate
 6788 // Constant shift count is masked in ideal graph already.
 6789 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
 6790   match(Set dst (RShiftI dst src));
 6791   effect(KILL cr);
 6792   size(4);
 6793   format %{ "SRA     $dst,$src" %}
 6794   ins_encode %{
 6795     int Nbit = $src$$constant;
 6796     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6797     __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6798   %}
 6799   ins_pipe(pipe_class_dummy);
 6800 %}
 6801 
 6802 // Register Arithmetic Shift Right Long
 6803 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
 6804   match(Set dst (RShiftL src1 src2));
 6805   effect(KILL cr);
 6806   size(6);
 6807   format %{ "SRAG    $dst,$src1,[$src2]" %}
 6808   opcode(SRAG_ZOPC);
 6809   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
 6810   ins_pipe(pipe_class_dummy);
 6811 %}
 6812 
 6813 // Register Arithmetic Shift Right Long Immediate
 6814 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
 6815   match(Set dst (RShiftL src1 src2));
 6816   effect(KILL cr);
 6817   size(6);
 6818   format %{ "SRAG    $dst,$src1,$src2" %}
 6819   opcode(SRAG_ZOPC);
 6820   ins_encode(z_rsyform_const(dst, src1, src2));
 6821   ins_pipe(pipe_class_dummy);
 6822 %}
 6823 
 6824 //  Shift right logical
 6825 
 6826 // Register Shift Right
 6827 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 6828   match(Set dst (URShiftI dst src));
 6829   effect(KILL cr); // R1 is killed, too.
 6830   ins_cost(3 * DEFAULT_COST);
 6831   size(12);
 6832   format %{ "SRL     $dst,[$src] & 31" %}
 6833   ins_encode %{
 6834     __ z_lgr(Z_R1_scratch, $src$$Register);
 6835     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6836     __ z_srl($dst$$Register, 0, Z_R1_scratch);
 6837   %}
 6838   ins_pipe(pipe_class_dummy);
 6839 %}
 6840 
 6841 // Register Shift Right Immediate
 6842 // Constant shift count is masked in ideal graph already.
 6843 instruct srlI_reg_imm(iRegI dst, immI src) %{
 6844   match(Set dst (URShiftI dst src));
 6845   size(4);
 6846   format %{ "SRL     $dst,$src" %}
 6847   ins_encode %{
 6848     int Nbit = $src$$constant;
 6849     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6850     __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6851   %}
 6852   ins_pipe(pipe_class_dummy);
 6853 %}
 6854 
 6855 // Register Shift Right Long
 6856 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
 6857   match(Set dst (URShiftL src1 src2));
 6858   size(6);
 6859   format %{ "SRLG    $dst,$src1,[$src2]" %}
 6860   opcode(SRLG_ZOPC);
 6861   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
 6862   ins_pipe(pipe_class_dummy);
 6863 %}
 6864 
 6865 // Register Shift Right Long Immediate
 6866 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
 6867   match(Set dst (URShiftL src1 src2));
 6868   size(6);
 6869   format %{ "SRLG    $dst,$src1,$src2" %}
 6870   opcode(SRLG_ZOPC);
 6871   ins_encode(z_rsyform_const(dst, src1, src2));
 6872   ins_pipe(pipe_class_dummy);
 6873 %}
 6874 
 6875 // Register Shift Right Immediate with a CastP2X
 6876 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
 6877   match(Set dst (URShiftL (CastP2X src1) src2));
 6878   size(6);
 6879   format %{ "SRLG    $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
 6880   opcode(SRLG_ZOPC);
 6881   ins_encode(z_rsyform_const(dst, src1, src2));
 6882   ins_pipe(pipe_class_dummy);
 6883 %}
 6884 
 6885 //----------Rotate Instructions------------------------------------------------
 6886 
 6887 // Rotate left 32bit.
 6888 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
 6889   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
 6890   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
 6891   size(6);
 6892   format %{ "RLL     $dst,$src,$lshift\t # ROTL32" %}
 6893   opcode(RLL_ZOPC);
 6894   ins_encode(z_rsyform_const(dst, src, lshift));
 6895   ins_pipe(pipe_class_dummy);
 6896 %}
 6897 
 6898 // Rotate left 64bit.
 6899 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
 6900   match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
 6901   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
 6902   size(6);
 6903   format %{ "RLLG    $dst,$src,$lshift\t # ROTL64" %}
 6904   opcode(RLLG_ZOPC);
 6905   ins_encode(z_rsyform_const(dst, src, lshift));
 6906   ins_pipe(pipe_class_dummy);
 6907 %}
 6908 
 6909 // Rotate right 32bit.
 6910 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
 6911   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
 6912   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
 6913   // TODO: s390 port size(FIXED_SIZE);
 6914   format %{ "RLL     $dst,$src,$rshift\t # ROTR32" %}
 6915   opcode(RLL_ZOPC);
 6916   ins_encode(z_rsyform_const(dst, src, rshift));
 6917   ins_pipe(pipe_class_dummy);
 6918 %}
 6919 
 6920 // Rotate right 64bit.
 6921 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
 6922   match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
 6923   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
 6924   // TODO: s390 port size(FIXED_SIZE);
 6925   format %{ "RLLG    $dst,$src,$rshift\t # ROTR64" %}
 6926   opcode(RLLG_ZOPC);
 6927   ins_encode(z_rsyform_const(dst, src, rshift));
 6928   ins_pipe(pipe_class_dummy);
 6929 %}
 6930 
 6931 
 6932 //----------Overflow Math Instructions-----------------------------------------
 6933 
 6934 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 6935   match(Set cr (OverflowAddI op1 op2));
 6936   effect(DEF cr, USE op1, USE op2);
 6937   // TODO: s390 port size(FIXED_SIZE);
 6938   format %{ "AR      $op1,$op2\t # overflow check int" %}
 6939   ins_encode %{
 6940     __ z_lr(Z_R0_scratch, $op1$$Register);
 6941     __ z_ar(Z_R0_scratch, $op2$$Register);
 6942   %}
 6943   ins_pipe(pipe_class_dummy);
 6944 %}
 6945 
 6946 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 6947   match(Set cr (OverflowAddI op1 op2));
 6948   effect(DEF cr, USE op1, USE op2);
 6949   // TODO: s390 port size(VARIABLE_SIZE);
 6950   format %{ "AR      $op1,$op2\t # overflow check int" %}
 6951   ins_encode %{
 6952     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
 6953     __ z_ar(Z_R0_scratch, $op1$$Register);
 6954   %}
 6955   ins_pipe(pipe_class_dummy);
 6956 %}
 6957 
 6958 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 6959   match(Set cr (OverflowAddL op1 op2));
 6960   effect(DEF cr, USE op1, USE op2);
 6961   // TODO: s390 port size(FIXED_SIZE);
 6962   format %{ "AGR     $op1,$op2\t # overflow check long" %}
 6963   ins_encode %{
 6964     __ z_lgr(Z_R0_scratch, $op1$$Register);
 6965     __ z_agr(Z_R0_scratch, $op2$$Register);
 6966   %}
 6967   ins_pipe(pipe_class_dummy);
 6968 %}
 6969 
 6970 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
 6971   match(Set cr (OverflowAddL op1 op2));
 6972   effect(DEF cr, USE op1, USE op2);
 6973   // TODO: s390 port size(VARIABLE_SIZE);
 6974   format %{ "AGR     $op1,$op2\t # overflow check long" %}
 6975   ins_encode %{
 6976     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
 6977     __ z_agr(Z_R0_scratch, $op1$$Register);
 6978   %}
 6979   ins_pipe(pipe_class_dummy);
 6980 %}
 6981 
 6982 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 6983   match(Set cr (OverflowSubI op1 op2));
 6984   effect(DEF cr, USE op1, USE op2);
 6985   // TODO: s390 port size(FIXED_SIZE);
 6986   format %{ "SR      $op1,$op2\t # overflow check int" %}
 6987   ins_encode %{
 6988     __ z_lr(Z_R0_scratch, $op1$$Register);
 6989     __ z_sr(Z_R0_scratch, $op2$$Register);
 6990   %}
 6991   ins_pipe(pipe_class_dummy);
 6992 %}
 6993 
 6994 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 6995   match(Set cr (OverflowSubI op1 op2));
 6996   effect(DEF cr, USE op1, USE op2);
 6997   // TODO: s390 port size(VARIABLE_SIZE);
 6998   format %{ "SR      $op1,$op2\t # overflow check int" %}
 6999   ins_encode %{
 7000     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
 7001     __ z_lr(Z_R0_scratch, $op1$$Register);
 7002     __ z_sr(Z_R0_scratch, Z_R1_scratch);
 7003   %}
 7004   ins_pipe(pipe_class_dummy);
 7005 %}
 7006 
 7007 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 7008   match(Set cr (OverflowSubL op1 op2));
 7009   effect(DEF cr, USE op1, USE op2);
 7010   // TODO: s390 port size(FIXED_SIZE);
 7011   format %{ "SGR     $op1,$op2\t # overflow check long" %}
 7012   ins_encode %{
 7013     __ z_lgr(Z_R0_scratch, $op1$$Register);
 7014     __ z_sgr(Z_R0_scratch, $op2$$Register);
 7015   %}
 7016   ins_pipe(pipe_class_dummy);
 7017 %}
 7018 
 7019 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
 7020   match(Set cr (OverflowSubL op1 op2));
 7021   effect(DEF cr, USE op1, USE op2);
 7022   // TODO: s390 port size(VARIABLE_SIZE);
 7023   format %{ "SGR     $op1,$op2\t # overflow check long" %}
 7024   ins_encode %{
 7025     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
 7026     __ z_lgr(Z_R0_scratch, $op1$$Register);
 7027     __ z_sgr(Z_R0_scratch, Z_R1_scratch);
 7028   %}
 7029   ins_pipe(pipe_class_dummy);
 7030 %}
 7031 
 7032 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
 7033   match(Set cr (OverflowSubI zero op2));
 7034   effect(DEF cr, USE op2);
 7035   format %{ "NEG    $op2\t # overflow check int" %}
 7036   ins_encode %{
 7037     __ clear_reg(Z_R0_scratch, false, false);
 7038     __ z_sr(Z_R0_scratch, $op2$$Register);
 7039   %}
 7040   ins_pipe(pipe_class_dummy);
 7041 %}
 7042 
 7043 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
 7044   match(Set cr (OverflowSubL zero op2));
 7045   effect(DEF cr, USE op2);
 7046   format %{ "NEGG    $op2\t # overflow check long" %}
 7047   ins_encode %{
 7048     __ clear_reg(Z_R0_scratch, true, false);
 7049     __ z_sgr(Z_R0_scratch, $op2$$Register);
 7050   %}
 7051   ins_pipe(pipe_class_dummy);
 7052 %}
 7053 
 7054 // No intrinsics for multiplication, since there is no easy way
 7055 // to check for overflow.
 7056 
 7057 
 7058 //----------Floating Point Arithmetic Instructions-----------------------------
 7059 
 7060 //  ADD
 7061 
 7062 //  Add float single precision
 7063 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
 7064   match(Set dst (AddF dst src));
 7065   effect(KILL cr);
 7066   ins_cost(ALU_REG_COST);
 7067   size(4);
 7068   format %{ "AEBR     $dst,$src" %}
 7069   opcode(AEBR_ZOPC);
 7070   ins_encode(z_rreform(dst, src));
 7071   ins_pipe(pipe_class_dummy);
 7072 %}
 7073 
 7074 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
 7075   match(Set dst (AddF dst (LoadF src)));
 7076   effect(KILL cr);
 7077   ins_cost(ALU_MEMORY_COST);
 7078   size(6);
 7079   format %{ "AEB      $dst,$src\t # floatMemory" %}
 7080   opcode(AEB_ZOPC);
 7081   ins_encode(z_form_rt_memFP(dst, src));
 7082   ins_pipe(pipe_class_dummy);
 7083 %}
 7084 
 7085 // Add float double precision
 7086 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
 7087   match(Set dst (AddD dst src));
 7088   effect(KILL cr);
 7089   ins_cost(ALU_REG_COST);
 7090   size(4);
 7091   format %{ "ADBR     $dst,$src" %}
 7092   opcode(ADBR_ZOPC);
 7093   ins_encode(z_rreform(dst, src));
 7094   ins_pipe(pipe_class_dummy);
 7095 %}
 7096 
 7097 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
 7098   match(Set dst (AddD dst (LoadD src)));
 7099   effect(KILL cr);
 7100   ins_cost(ALU_MEMORY_COST);
 7101   size(6);
 7102   format %{ "ADB      $dst,$src\t # doubleMemory" %}
 7103   opcode(ADB_ZOPC);
 7104   ins_encode(z_form_rt_memFP(dst, src));
 7105   ins_pipe(pipe_class_dummy);
 7106 %}
 7107 
 7108 // SUB
 7109 
 7110 // Sub float single precision
 7111 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
 7112   match(Set dst (SubF dst src));
 7113   effect(KILL cr);
 7114   ins_cost(ALU_REG_COST);
 7115   size(4);
 7116   format %{ "SEBR     $dst,$src" %}
 7117   opcode(SEBR_ZOPC);
 7118   ins_encode(z_rreform(dst, src));
 7119   ins_pipe(pipe_class_dummy);
 7120 %}
 7121 
 7122 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
 7123   match(Set dst (SubF dst (LoadF src)));
 7124   effect(KILL cr);
 7125   ins_cost(ALU_MEMORY_COST);
 7126   size(6);
 7127   format %{ "SEB      $dst,$src\t # floatMemory" %}
 7128   opcode(SEB_ZOPC);
 7129   ins_encode(z_form_rt_memFP(dst, src));
 7130   ins_pipe(pipe_class_dummy);
 7131 %}
 7132 
 7133 //  Sub float double precision
 7134 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
 7135   match(Set dst (SubD dst src));
 7136   effect(KILL cr);
 7137   ins_cost(ALU_REG_COST);
 7138   size(4);
 7139   format %{ "SDBR     $dst,$src" %}
 7140   opcode(SDBR_ZOPC);
 7141   ins_encode(z_rreform(dst, src));
 7142   ins_pipe(pipe_class_dummy);
 7143 %}
 7144 
 7145 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
 7146   match(Set dst (SubD dst (LoadD src)));
 7147   effect(KILL cr);
 7148   ins_cost(ALU_MEMORY_COST);
 7149   size(6);
 7150   format %{ "SDB      $dst,$src\t # doubleMemory" %}
 7151   opcode(SDB_ZOPC);
 7152   ins_encode(z_form_rt_memFP(dst, src));
 7153   ins_pipe(pipe_class_dummy);
 7154 %}
 7155 
 7156 // MUL
 7157 
 7158 // Mul float single precision
 7159 instruct mulF_reg_reg(regF dst, regF src) %{
 7160   match(Set dst (MulF dst src));
 7161   // CC unchanged by MUL.
 7162   ins_cost(ALU_REG_COST);
 7163   size(4);
 7164   format %{ "MEEBR    $dst,$src" %}
 7165   opcode(MEEBR_ZOPC);
 7166   ins_encode(z_rreform(dst, src));
 7167   ins_pipe(pipe_class_dummy);
 7168 %}
 7169 
 7170 instruct mulF_reg_mem(regF dst, memoryRX src)%{
 7171   match(Set dst (MulF dst (LoadF src)));
 7172   // CC unchanged by MUL.
 7173   ins_cost(ALU_MEMORY_COST);
 7174   size(6);
 7175   format %{ "MEEB     $dst,$src\t # floatMemory" %}
 7176   opcode(MEEB_ZOPC);
 7177   ins_encode(z_form_rt_memFP(dst, src));
 7178   ins_pipe(pipe_class_dummy);
 7179 %}
 7180 
 7181 //  Mul float double precision
 7182 instruct mulD_reg_reg(regD dst, regD src) %{
 7183   match(Set dst (MulD dst src));
 7184   // CC unchanged by MUL.
 7185   ins_cost(ALU_REG_COST);
 7186   size(4);
 7187   format %{ "MDBR     $dst,$src" %}
 7188   opcode(MDBR_ZOPC);
 7189   ins_encode(z_rreform(dst, src));
 7190   ins_pipe(pipe_class_dummy);
 7191 %}
 7192 
 7193 instruct mulD_reg_mem(regD dst, memoryRX src)%{
 7194   match(Set dst (MulD dst (LoadD src)));
 7195   // CC unchanged by MUL.
 7196   ins_cost(ALU_MEMORY_COST);
 7197   size(6);
 7198   format %{ "MDB      $dst,$src\t # doubleMemory" %}
 7199   opcode(MDB_ZOPC);
 7200   ins_encode(z_form_rt_memFP(dst, src));
 7201   ins_pipe(pipe_class_dummy);
 7202 %}
 7203 
 7204 // Multiply-Accumulate
 7205 // src1 * src2 + dst
 7206 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
 7207   match(Set dst (FmaF dst (Binary src1 src2)));
 7208   // CC unchanged by MUL-ADD.
 7209   ins_cost(ALU_REG_COST);
 7210   size(4);
 7211   format %{ "MAEBR    $dst, $src1, $src2" %}
 7212   ins_encode %{
 7213     __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7214   %}
 7215   ins_pipe(pipe_class_dummy);
 7216 %}
 7217 
 7218 // src1 * src2 + dst
 7219 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
 7220   match(Set dst (FmaD dst (Binary src1 src2)));
 7221   // CC unchanged by MUL-ADD.
 7222   ins_cost(ALU_REG_COST);
 7223   size(4);
 7224   format %{ "MADBR    $dst, $src1, $src2" %}
 7225   ins_encode %{
 7226     __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7227   %}
 7228   ins_pipe(pipe_class_dummy);
 7229 %}
 7230 
 7231 // src1 * src2 - dst
 7232 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
 7233   match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
 7234   // CC unchanged by MUL-SUB.
 7235   ins_cost(ALU_REG_COST);
 7236   size(4);
 7237   format %{ "MSEBR    $dst, $src1, $src2" %}
 7238   ins_encode %{
 7239     __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7240   %}
 7241   ins_pipe(pipe_class_dummy);
 7242 %}
 7243 
 7244 // src1 * src2 - dst
 7245 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
 7246   match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
 7247   // CC unchanged by MUL-SUB.
 7248   ins_cost(ALU_REG_COST);
 7249   size(4);
 7250   format %{ "MSDBR    $dst, $src1, $src2" %}
 7251   ins_encode %{
 7252     __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7253   %}
 7254   ins_pipe(pipe_class_dummy);
 7255 %}
 7256 
 7257 // src1 * src2 + dst
 7258 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
 7259   match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
 7260   // CC unchanged by MUL-ADD.
 7261   ins_cost(ALU_MEMORY_COST);
 7262   size(6);
 7263   format %{ "MAEB     $dst, $src1, $src2" %}
 7264   ins_encode %{
 7265     __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
 7266               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7267   %}
 7268   ins_pipe(pipe_class_dummy);
 7269 %}
 7270 
 7271 // src1 * src2 + dst
 7272 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
 7273   match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
 7274   // CC unchanged by MUL-ADD.
 7275   ins_cost(ALU_MEMORY_COST);
 7276   size(6);
 7277   format %{ "MADB     $dst, $src1, $src2" %}
 7278   ins_encode %{
 7279     __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
 7280               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7281   %}
 7282   ins_pipe(pipe_class_dummy);
 7283 %}
 7284 
 7285 // src1 * src2 - dst
 7286 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
 7287   match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
 7288   // CC unchanged by MUL-SUB.
 7289   ins_cost(ALU_MEMORY_COST);
 7290   size(6);
 7291   format %{ "MSEB     $dst, $src1, $src2" %}
 7292   ins_encode %{
 7293     __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
 7294               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7295   %}
 7296   ins_pipe(pipe_class_dummy);
 7297 %}
 7298 
 7299 // src1 * src2 - dst
 7300 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
 7301   match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
 7302   // CC unchanged by MUL-SUB.
 7303   ins_cost(ALU_MEMORY_COST);
 7304   size(6);
 7305   format %{ "MSDB    $dst, $src1, $src2" %}
 7306   ins_encode %{
 7307     __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
 7308               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7309   %}
 7310   ins_pipe(pipe_class_dummy);
 7311 %}
 7312 
 7313 // src1 * src2 + dst
 7314 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
 7315   match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
 7316   // CC unchanged by MUL-ADD.
 7317   ins_cost(ALU_MEMORY_COST);
 7318   size(6);
 7319   format %{ "MAEB     $dst, $src1, $src2" %}
 7320   ins_encode %{
 7321     __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
 7322               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7323   %}
 7324   ins_pipe(pipe_class_dummy);
 7325 %}
 7326 
 7327 // src1 * src2 + dst
 7328 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
 7329   match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
 7330   // CC unchanged by MUL-ADD.
 7331   ins_cost(ALU_MEMORY_COST);
 7332   size(6);
 7333   format %{ "MADB     $dst, $src1, $src2" %}
 7334   ins_encode %{
 7335     __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
 7336               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7337   %}
 7338   ins_pipe(pipe_class_dummy);
 7339 %}
 7340 
 7341 // src1 * src2 - dst
 7342 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
 7343   match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
 7344   // CC unchanged by MUL-SUB.
 7345   ins_cost(ALU_MEMORY_COST);
 7346   size(6);
 7347   format %{ "MSEB     $dst, $src1, $src2" %}
 7348   ins_encode %{
 7349     __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
 7350               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7351   %}
 7352   ins_pipe(pipe_class_dummy);
 7353 %}
 7354 
 7355 // src1 * src2 - dst
 7356 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
 7357   match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
 7358   // CC unchanged by MUL-SUB.
 7359   ins_cost(ALU_MEMORY_COST);
 7360   size(6);
 7361   format %{ "MSDB    $dst, $src1, $src2" %}
 7362   ins_encode %{
 7363     __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
 7364               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7365   %}
 7366   ins_pipe(pipe_class_dummy);
 7367 %}
 7368 
 7369 //  DIV
 7370 
 7371 //  Div float single precision
 7372 instruct divF_reg_reg(regF dst, regF src) %{
 7373   match(Set dst (DivF dst src));
 7374   // CC unchanged by DIV.
 7375   ins_cost(ALU_REG_COST);
 7376   size(4);
 7377   format %{ "DEBR     $dst,$src" %}
 7378   opcode(DEBR_ZOPC);
 7379   ins_encode(z_rreform(dst, src));
 7380   ins_pipe(pipe_class_dummy);
 7381 %}
 7382 
 7383 instruct divF_reg_mem(regF dst, memoryRX src)%{
 7384   match(Set dst (DivF dst (LoadF src)));
 7385   // CC unchanged by DIV.
 7386   ins_cost(ALU_MEMORY_COST);
 7387   size(6);
 7388   format %{ "DEB      $dst,$src\t # floatMemory" %}
 7389   opcode(DEB_ZOPC);
 7390   ins_encode(z_form_rt_memFP(dst, src));
 7391   ins_pipe(pipe_class_dummy);
 7392 %}
 7393 
 7394 //  Div float double precision
 7395 instruct divD_reg_reg(regD dst, regD src) %{
 7396   match(Set dst (DivD dst src));
 7397   // CC unchanged by DIV.
 7398   ins_cost(ALU_REG_COST);
 7399   size(4);
 7400   format %{ "DDBR     $dst,$src" %}
 7401   opcode(DDBR_ZOPC);
 7402   ins_encode(z_rreform(dst, src));
 7403   ins_pipe(pipe_class_dummy);
 7404 %}
 7405 
 7406 instruct divD_reg_mem(regD dst, memoryRX src)%{
 7407   match(Set dst (DivD dst (LoadD src)));
 7408   // CC unchanged by DIV.
 7409   ins_cost(ALU_MEMORY_COST);
 7410   size(6);
 7411   format %{ "DDB      $dst,$src\t # doubleMemory" %}
 7412   opcode(DDB_ZOPC);
 7413   ins_encode(z_form_rt_memFP(dst, src));
 7414   ins_pipe(pipe_class_dummy);
 7415 %}
 7416 
 7417 // ABS
 7418 
 7419 // Absolute float single precision
 7420 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
 7421   match(Set dst (AbsF src));
 7422   effect(KILL cr);
 7423   size(4);
 7424   format %{ "LPEBR    $dst,$src\t float" %}
 7425   opcode(LPEBR_ZOPC);
 7426   ins_encode(z_rreform(dst, src));
 7427   ins_pipe(pipe_class_dummy);
 7428 %}
 7429 
 7430 // Absolute float double precision
 7431 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
 7432   match(Set dst (AbsD src));
 7433   effect(KILL cr);
 7434   size(4);
 7435   format %{ "LPDBR    $dst,$src\t double" %}
 7436   opcode(LPDBR_ZOPC);
 7437   ins_encode(z_rreform(dst, src));
 7438   ins_pipe(pipe_class_dummy);
 7439 %}
 7440 
 7441 //  NEG(ABS)
 7442 
 7443 // Negative absolute float single precision
 7444 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
 7445   match(Set dst (NegF (AbsF src)));
 7446   effect(KILL cr);
 7447   size(4);
 7448   format %{ "LNEBR    $dst,$src\t float" %}
 7449   opcode(LNEBR_ZOPC);
 7450   ins_encode(z_rreform(dst, src));
 7451   ins_pipe(pipe_class_dummy);
 7452 %}
 7453 
 7454 // Negative absolute float double precision
 7455 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
 7456   match(Set dst (NegD (AbsD src)));
 7457   effect(KILL cr);
 7458   size(4);
 7459   format %{ "LNDBR    $dst,$src\t double" %}
 7460   opcode(LNDBR_ZOPC);
 7461   ins_encode(z_rreform(dst, src));
 7462   ins_pipe(pipe_class_dummy);
 7463 %}
 7464 
 7465 // NEG
 7466 
 7467 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
 7468   match(Set dst (NegF src));
 7469   effect(KILL cr);
 7470   size(4);
 7471   format %{ "NegF     $dst,$src\t float" %}
 7472   ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
 7473   ins_pipe(pipe_class_dummy);
 7474 %}
 7475 
 7476 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
 7477   match(Set dst (NegD src));
 7478   effect(KILL cr);
 7479   size(4);
 7480   format %{ "NegD     $dst,$src\t double" %}
 7481   ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
 7482   ins_pipe(pipe_class_dummy);
 7483 %}
 7484 
 7485 // SQRT
 7486 
 7487 // Sqrt float precision
 7488 instruct sqrtF_reg(regF dst, regF src) %{
 7489   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7490   // CC remains unchanged.
 7491   ins_cost(ALU_REG_COST);
 7492   size(4);
 7493   format %{ "SQEBR    $dst,$src" %}
 7494   opcode(SQEBR_ZOPC);
 7495   ins_encode(z_rreform(dst, src));
 7496   ins_pipe(pipe_class_dummy);
 7497 %}
 7498 
 7499 // Sqrt double precision
 7500 instruct sqrtD_reg(regD dst, regD src) %{
 7501   match(Set dst (SqrtD src));
 7502   // CC remains unchanged.
 7503   ins_cost(ALU_REG_COST);
 7504   size(4);
 7505   format %{ "SQDBR    $dst,$src" %}
 7506   opcode(SQDBR_ZOPC);
 7507   ins_encode(z_rreform(dst, src));
 7508   ins_pipe(pipe_class_dummy);
 7509 %}
 7510 
 7511 instruct sqrtF_mem(regF dst, memoryRX src) %{
 7512   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7513   // CC remains unchanged.
 7514   ins_cost(ALU_MEMORY_COST);
 7515   size(6);
 7516   format %{ "SQEB     $dst,$src\t # floatMemory" %}
 7517   opcode(SQEB_ZOPC);
 7518   ins_encode(z_form_rt_memFP(dst, src));
 7519   ins_pipe(pipe_class_dummy);
 7520 %}
 7521 
 7522 instruct sqrtD_mem(regD dst, memoryRX src) %{
 7523   match(Set dst (SqrtD src));
 7524   // CC remains unchanged.
 7525   ins_cost(ALU_MEMORY_COST);
 7526   // TODO: s390 port size(FIXED_SIZE);
 7527   format %{ "SQDB     $dst,$src\t # doubleMemory" %}
 7528   opcode(SQDB_ZOPC);
 7529   ins_encode(z_form_rt_memFP(dst, src));
 7530   ins_pipe(pipe_class_dummy);
 7531 %}
 7532 
 7533 //----------Logical Instructions-----------------------------------------------
 7534 
 7535 // Register And
 7536 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7537   match(Set dst (AndI dst src));
 7538   effect(KILL cr);
 7539   ins_cost(DEFAULT_COST_LOW);
 7540   size(2);
 7541   format %{ "NR      $dst,$src\t # int" %}
 7542   opcode(NR_ZOPC);
 7543   ins_encode(z_rrform(dst, src));
 7544   ins_pipe(pipe_class_dummy);
 7545 %}
 7546 
 7547 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7548   match(Set dst (AndI dst (LoadI src)));
 7549   effect(KILL cr);
 7550   ins_cost(MEMORY_REF_COST);
 7551   // TODO: s390 port size(VARIABLE_SIZE);
 7552   format %{ "N(Y)    $dst, $src\t # int" %}
 7553   opcode(NY_ZOPC, N_ZOPC);
 7554   ins_encode(z_form_rt_mem_opt(dst, src));
 7555   ins_pipe(pipe_class_dummy);
 7556 %}
 7557 
 7558 // Immediate And
 7559 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
 7560   match(Set dst (AndI dst src));
 7561   effect(KILL cr);
 7562   ins_cost(DEFAULT_COST_HIGH);
 7563   size(6);
 7564   format %{ "NILF    $dst,$src" %}
 7565   opcode(NILF_ZOPC);
 7566   ins_encode(z_rilform_unsigned(dst, src));
 7567   ins_pipe(pipe_class_dummy);
 7568 %}
 7569 
 7570 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
 7571   match(Set dst (AndI dst src));
 7572   effect(KILL cr);
 7573   ins_cost(DEFAULT_COST);
 7574   size(4);
 7575   format %{ "NILH    $dst,$src" %}
 7576   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
 7577   ins_pipe(pipe_class_dummy);
 7578 %}
 7579 
 7580 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
 7581   match(Set dst (AndI dst src));
 7582   effect(KILL cr);
 7583   ins_cost(DEFAULT_COST);
 7584   size(4);
 7585   format %{ "NILL    $dst,$src" %}
 7586   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
 7587   ins_pipe(pipe_class_dummy);
 7588 %}
 7589 
 7590 // Register And Long
 7591 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7592   match(Set dst (AndL dst src));
 7593   effect(KILL cr);
 7594   ins_cost(DEFAULT_COST);
 7595   size(4);
 7596   format %{ "NGR     $dst,$src\t # long" %}
 7597   opcode(NGR_ZOPC);
 7598   ins_encode(z_rreform(dst, src));
 7599   ins_pipe(pipe_class_dummy);
 7600 %}
 7601 
 7602 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7603   match(Set dst (AndL dst (LoadL src)));
 7604   effect(KILL cr);
 7605   ins_cost(MEMORY_REF_COST);
 7606   size(Z_DISP3_SIZE);
 7607   format %{ "NG      $dst, $src\t # long" %}
 7608   opcode(NG_ZOPC, NG_ZOPC);
 7609   ins_encode(z_form_rt_mem_opt(dst, src));
 7610   ins_pipe(pipe_class_dummy);
 7611 %}
 7612 
 7613 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
 7614   match(Set dst (AndL dst src));
 7615   effect(KILL cr);
 7616   ins_cost(DEFAULT_COST);
 7617   size(4);
 7618   format %{ "NILL    $dst,$src\t # long" %}
 7619   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
 7620   ins_pipe(pipe_class_dummy);
 7621 %}
 7622 
 7623 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
 7624   match(Set dst (AndL dst src));
 7625   effect(KILL cr);
 7626   ins_cost(DEFAULT_COST);
 7627   size(4);
 7628   format %{ "NILH    $dst,$src\t # long" %}
 7629   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
 7630   ins_pipe(pipe_class_dummy);
 7631 %}
 7632 
 7633 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
 7634   match(Set dst (AndL dst src));
 7635   effect(KILL cr);
 7636   ins_cost(DEFAULT_COST);
 7637   size(4);
 7638   format %{ "NIHL    $dst,$src\t # long" %}
 7639   ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
 7640   ins_pipe(pipe_class_dummy);
 7641 %}
 7642 
 7643 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
 7644   match(Set dst (AndL dst src));
 7645   effect(KILL cr);
 7646   ins_cost(DEFAULT_COST);
 7647   size(4);
 7648   format %{ "NIHH    $dst,$src\t # long" %}
 7649   ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
 7650   ins_pipe(pipe_class_dummy);
 7651 %}
 7652 
 7653 //  OR
 7654 
 7655 // Or Instructions
 7656 // Register Or
 7657 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7658   match(Set dst (OrI dst src));
 7659   effect(KILL cr);
 7660   size(2);
 7661   format %{ "OR      $dst,$src" %}
 7662   opcode(OR_ZOPC);
 7663   ins_encode(z_rrform(dst, src));
 7664   ins_pipe(pipe_class_dummy);
 7665 %}
 7666 
 7667 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7668   match(Set dst (OrI dst (LoadI src)));
 7669   effect(KILL cr);
 7670   ins_cost(MEMORY_REF_COST);
 7671   // TODO: s390 port size(VARIABLE_SIZE);
 7672   format %{ "O(Y)    $dst, $src\t # int" %}
 7673   opcode(OY_ZOPC, O_ZOPC);
 7674   ins_encode(z_form_rt_mem_opt(dst, src));
 7675   ins_pipe(pipe_class_dummy);
 7676 %}
 7677 
 7678 // Immediate Or
 7679 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
 7680   match(Set dst (OrI dst con));
 7681   effect(KILL cr);
 7682   size(4);
 7683   format %{ "OILL    $dst,$con" %}
 7684   opcode(OILL_ZOPC);
 7685   ins_encode(z_riform_unsigned(dst,con));
 7686   ins_pipe(pipe_class_dummy);
 7687 %}
 7688 
 7689 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
 7690   match(Set dst (OrI dst con));
 7691   effect(KILL cr);
 7692   ins_cost(DEFAULT_COST_HIGH);
 7693   size(6);
 7694   format %{ "OILF    $dst,$con" %}
 7695   opcode(OILF_ZOPC);
 7696   ins_encode(z_rilform_unsigned(dst,con));
 7697   ins_pipe(pipe_class_dummy);
 7698 %}
 7699 
 7700 // Register Or Long
 7701 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7702   match(Set dst (OrL dst src));
 7703   effect(KILL cr);
 7704   ins_cost(DEFAULT_COST);
 7705   size(4);
 7706   format %{ "OGR      $dst,$src\t # long" %}
 7707   opcode(OGR_ZOPC);
 7708   ins_encode(z_rreform(dst, src));
 7709   ins_pipe(pipe_class_dummy);
 7710 %}
 7711 
 7712 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7713   match(Set dst (OrL dst (LoadL src)));
 7714   effect(KILL cr);
 7715   ins_cost(MEMORY_REF_COST);
 7716   size(Z_DISP3_SIZE);
 7717   format %{ "OG      $dst, $src\t # long" %}
 7718   opcode(OG_ZOPC, OG_ZOPC);
 7719   ins_encode(z_form_rt_mem_opt(dst, src));
 7720   ins_pipe(pipe_class_dummy);
 7721 %}
 7722 
 7723 // Immediate Or long
 7724 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
 7725   match(Set dst (OrL dst con));
 7726   effect(KILL cr);
 7727   ins_cost(DEFAULT_COST);
 7728   size(4);
 7729   format %{ "OILL    $dst,$con\t # long" %}
 7730   opcode(OILL_ZOPC);
 7731   ins_encode(z_riform_unsigned(dst,con));
 7732   ins_pipe(pipe_class_dummy);
 7733 %}
 7734 
 7735 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
 7736   match(Set dst (OrI dst con));
 7737   effect(KILL cr);
 7738   ins_cost(DEFAULT_COST_HIGH);
 7739   // TODO: s390 port size(FIXED_SIZE);
 7740   format %{ "OILF    $dst,$con\t # long" %}
 7741   opcode(OILF_ZOPC);
 7742   ins_encode(z_rilform_unsigned(dst,con));
 7743   ins_pipe(pipe_class_dummy);
 7744 %}
 7745 
 7746 // XOR
 7747 
 7748 // Register Xor
 7749 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7750   match(Set dst (XorI dst src));
 7751   effect(KILL cr);
 7752   size(2);
 7753   format %{ "XR      $dst,$src" %}
 7754   opcode(XR_ZOPC);
 7755   ins_encode(z_rrform(dst, src));
 7756   ins_pipe(pipe_class_dummy);
 7757 %}
 7758 
 7759 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7760   match(Set dst (XorI dst (LoadI src)));
 7761   effect(KILL cr);
 7762   ins_cost(MEMORY_REF_COST);
 7763   // TODO: s390 port size(VARIABLE_SIZE);
 7764   format %{ "X(Y)    $dst, $src\t # int" %}
 7765   opcode(XY_ZOPC, X_ZOPC);
 7766   ins_encode(z_form_rt_mem_opt(dst, src));
 7767   ins_pipe(pipe_class_dummy);
 7768 %}
 7769 
 7770 // Immediate Xor
 7771 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
 7772   match(Set dst (XorI dst src));
 7773   effect(KILL cr);
 7774   ins_cost(DEFAULT_COST_HIGH);
 7775   size(6);
 7776   format %{ "XILF    $dst,$src" %}
 7777   opcode(XILF_ZOPC);
 7778   ins_encode(z_rilform_unsigned(dst, src));
 7779   ins_pipe(pipe_class_dummy);
 7780 %}
 7781 
 7782 // Register Xor Long
 7783 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7784   match(Set dst (XorL dst src));
 7785   effect(KILL cr);
 7786   ins_cost(DEFAULT_COST);
 7787   size(4);
 7788   format %{ "XGR     $dst,$src\t # long" %}
 7789   opcode(XGR_ZOPC);
 7790   ins_encode(z_rreform(dst, src));
 7791   ins_pipe(pipe_class_dummy);
 7792 %}
 7793 
 7794 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7795   match(Set dst (XorL dst (LoadL src)));
 7796   effect(KILL cr);
 7797   ins_cost(MEMORY_REF_COST);
 7798   size(Z_DISP3_SIZE);
 7799   format %{ "XG      $dst, $src\t # long" %}
 7800   opcode(XG_ZOPC, XG_ZOPC);
 7801   ins_encode(z_form_rt_mem_opt(dst, src));
 7802   ins_pipe(pipe_class_dummy);
 7803 %}
 7804 
 7805 // Immediate Xor Long
 7806 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
 7807   match(Set dst (XorL dst con));
 7808   effect(KILL cr);
 7809   ins_cost(DEFAULT_COST_HIGH);
 7810   size(6);
 7811   format %{ "XILF    $dst,$con\t # long" %}
 7812   opcode(XILF_ZOPC);
 7813   ins_encode(z_rilform_unsigned(dst,con));
 7814   ins_pipe(pipe_class_dummy);
 7815 %}
 7816 
 7817 //----------Convert to Boolean-------------------------------------------------
 7818 
 7819 // Convert integer to boolean.
 7820 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
 7821   match(Set dst (Conv2B src));
 7822   effect(KILL cr);
 7823   ins_cost(3 * DEFAULT_COST);
 7824   size(6);
 7825   format %{ "convI2B $dst,$src" %}
 7826   ins_encode %{
 7827     __ z_lnr($dst$$Register, $src$$Register);  // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
 7828     __ z_srl($dst$$Register, 31);              // Rdst := sign(Rdest)
 7829   %}
 7830   ins_pipe(pipe_class_dummy);
 7831 %}
 7832 
 7833 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
 7834   match(Set dst (Conv2B src));
 7835   effect(KILL cr);
 7836   ins_cost(3 * DEFAULT_COST);
 7837   size(10);
 7838   format %{ "convP2B $dst,$src" %}
 7839   ins_encode %{
 7840     __ z_lngr($dst$$Register, $src$$Register);     // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
 7841     __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
 7842   %}
 7843   ins_pipe(pipe_class_dummy);
 7844 %}
 7845 
 7846 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7847   match(Set dst (CmpLTMask dst src));
 7848   effect(KILL cr);
 7849   ins_cost(2 * DEFAULT_COST);
 7850   size(18);
 7851   format %{ "Set $dst CmpLTMask $dst,$src" %}
 7852   ins_encode %{
 7853     // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
 7854     __ z_lgfr(Z_R0_scratch, $src$$Register);
 7855     __ z_lgfr($dst$$Register, $dst$$Register);
 7856     __ z_sgr($dst$$Register, Z_R0_scratch);
 7857     __ z_srag($dst$$Register, $dst$$Register, 63);
 7858   %}
 7859   ins_pipe(pipe_class_dummy);
 7860 %}
 7861 
 7862 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
 7863   match(Set dst (CmpLTMask dst zero));
 7864   effect(KILL cr);
 7865   ins_cost(DEFAULT_COST);
 7866   size(4);
 7867   format %{ "Set $dst CmpLTMask $dst,$zero" %}
 7868   ins_encode %{ __ z_sra($dst$$Register, 31); %}
 7869   ins_pipe(pipe_class_dummy);
 7870 %}
 7871 
 7872 
 7873 //----------Arithmetic Conversion Instructions---------------------------------
 7874 // The conversions operations are all Alpha sorted. Please keep it that way!
 7875 
 7876 instruct convD2F_reg(regF dst, regD src) %{
 7877   match(Set dst (ConvD2F src));
 7878   // CC remains unchanged.
 7879   size(4);
 7880   format %{ "LEDBR   $dst,$src" %}
 7881   opcode(LEDBR_ZOPC);
 7882   ins_encode(z_rreform(dst, src));
 7883   ins_pipe(pipe_class_dummy);
 7884 %}
 7885 
 7886 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
 7887   match(Set dst (ConvF2I src));
 7888   effect(KILL cr);
 7889   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7890   size(16);
 7891   format %{ "convF2I  $dst,$src" %}
 7892   ins_encode %{
 7893     Label done;
 7894     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
 7895     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7896     __ z_brno(done);                             // Result is zero if unordered argument.
 7897     __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7898     __ bind(done);
 7899   %}
 7900   ins_pipe(pipe_class_dummy);
 7901 %}
 7902 
 7903 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
 7904   match(Set dst (ConvD2I src));
 7905   effect(KILL cr);
 7906   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7907   size(16);
 7908   format %{ "convD2I  $dst,$src" %}
 7909   ins_encode %{
 7910     Label done;
 7911     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
 7912     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7913     __ z_brno(done);                             // Result is zero if unordered argument.
 7914     __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7915     __ bind(done);
 7916   %}
 7917   ins_pipe(pipe_class_dummy);
 7918 %}
 7919 
 7920 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
 7921   match(Set dst (ConvF2L src));
 7922   effect(KILL cr);
 7923   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7924   size(16);
 7925   format %{ "convF2L  $dst,$src" %}
 7926   ins_encode %{
 7927     Label done;
 7928     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
 7929     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7930     __ z_brno(done);                             // Result is zero if unordered argument.
 7931     __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7932     __ bind(done);
 7933   %}
 7934   ins_pipe(pipe_class_dummy);
 7935 %}
 7936 
 7937 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
 7938   match(Set dst (ConvD2L src));
 7939   effect(KILL cr);
 7940   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7941   size(16);
 7942   format %{ "convD2L  $dst,$src" %}
 7943   ins_encode %{
 7944     Label done;
 7945     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
 7946     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7947     __ z_brno(done);                             // Result is zero if unordered argument.
 7948     __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7949     __ bind(done);
 7950   %}
 7951   ins_pipe(pipe_class_dummy);
 7952 %}
 7953 
 7954 instruct convF2D_reg(regD dst, regF src) %{
 7955   match(Set dst (ConvF2D src));
 7956   // CC remains unchanged.
 7957   size(4);
 7958   format %{ "LDEBR   $dst,$src" %}
 7959   opcode(LDEBR_ZOPC);
 7960   ins_encode(z_rreform(dst, src));
 7961   ins_pipe(pipe_class_dummy);
 7962 %}
 7963 
 7964 instruct convF2D_mem(regD dst, memoryRX src) %{
 7965   match(Set dst (ConvF2D src));
 7966   // CC remains unchanged.
 7967   size(6);
 7968   format %{ "LDEB    $dst,$src" %}
 7969   opcode(LDEB_ZOPC);
 7970   ins_encode(z_form_rt_memFP(dst, src));
 7971   ins_pipe(pipe_class_dummy);
 7972 %}
 7973 
 7974 instruct convI2D_reg(regD dst, iRegI src) %{
 7975   match(Set dst (ConvI2D src));
 7976   // CC remains unchanged.
 7977   ins_cost(DEFAULT_COST);
 7978   size(4);
 7979   format %{ "CDFBR   $dst,$src" %}
 7980   opcode(CDFBR_ZOPC);
 7981   ins_encode(z_rreform(dst, src));
 7982   ins_pipe(pipe_class_dummy);
 7983 %}
 7984 
 7985 // Optimization that saves up to two memory operations for each conversion.
 7986 instruct convI2F_ireg(regF dst, iRegI src) %{
 7987   match(Set dst (ConvI2F src));
 7988   // CC remains unchanged.
 7989   ins_cost(DEFAULT_COST);
 7990   size(4);
 7991   format %{ "CEFBR   $dst,$src\t # convert int to float" %}
 7992   opcode(CEFBR_ZOPC);
 7993   ins_encode(z_rreform(dst, src));
 7994   ins_pipe(pipe_class_dummy);
 7995 %}
 7996 
 7997 instruct convI2L_reg(iRegL dst, iRegI src) %{
 7998   match(Set dst (ConvI2L src));
 7999   size(4);
 8000   format %{ "LGFR    $dst,$src\t # int->long" %}
 8001   opcode(LGFR_ZOPC);
 8002   ins_encode(z_rreform(dst, src));
 8003   ins_pipe(pipe_class_dummy);
 8004 %}
 8005 
 8006 // Zero-extend convert int to long.
 8007 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
 8008   match(Set dst (AndL (ConvI2L src) mask));
 8009   size(4);
 8010   format %{ "LLGFR   $dst, $src \t # zero-extend int to long" %}
 8011   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
 8012   ins_pipe(pipe_class_dummy);
 8013 %}
 8014 
 8015 // Zero-extend convert int to long.
 8016 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
 8017   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
 8018   // Uses load_const_optmized, so size can vary.
 8019   // TODO: s390 port size(VARIABLE_SIZE);
 8020   format %{ "LLGF    $dst, $src \t # zero-extend int to long" %}
 8021   opcode(LLGF_ZOPC, LLGF_ZOPC);
 8022   ins_encode(z_form_rt_mem_opt(dst, src));
 8023   ins_pipe(pipe_class_dummy);
 8024 %}
 8025 
 8026 // Zero-extend long
 8027 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
 8028   match(Set dst (AndL src mask));
 8029   size(4);
 8030   format %{ "LLGFR   $dst, $src \t # zero-extend long to long" %}
 8031   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
 8032   ins_pipe(pipe_class_dummy);
 8033 %}
 8034 
 8035 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
 8036   match(Set dst (RShiftI (LShiftI src amount) amount));
 8037   size(4);
 8038   format %{ "LHR     $dst,$src\t short->int" %}
 8039   opcode(LHR_ZOPC);
 8040   ins_encode(z_rreform(dst, src));
 8041   ins_pipe(pipe_class_dummy);
 8042 %}
 8043 
 8044 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
 8045   match(Set dst (RShiftI (LShiftI src amount) amount));
 8046   size(4);
 8047   format %{ "LBR     $dst,$src\t byte->int" %}
 8048   opcode(LBR_ZOPC);
 8049   ins_encode(z_rreform(dst, src));
 8050   ins_pipe(pipe_class_dummy);
 8051 %}
 8052 
 8053 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
 8054   match(Set dst (MoveF2I src));
 8055   ins_cost(MEMORY_REF_COST);
 8056   size(4);
 8057   format %{ "L       $dst,$src\t # MoveF2I" %}
 8058   opcode(L_ZOPC);
 8059   ins_encode(z_form_rt_mem(dst, src));
 8060   ins_pipe(pipe_class_dummy);
 8061 %}
 8062 
 8063 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
 8064 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
 8065   match(Set dst (MoveI2F src));
 8066   ins_cost(MEMORY_REF_COST);
 8067   // TODO: s390 port size(FIXED_SIZE);
 8068   format %{ "LE      $dst,$src\t # MoveI2F" %}
 8069   opcode(LE_ZOPC);
 8070   ins_encode(z_form_rt_mem(dst, src));
 8071   ins_pipe(pipe_class_dummy);
 8072 %}
 8073 
 8074 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
 8075   match(Set dst (MoveD2L src));
 8076   ins_cost(MEMORY_REF_COST);
 8077   size(6);
 8078   format %{ "LG      $src,$dst\t # MoveD2L" %}
 8079   opcode(LG_ZOPC);
 8080   ins_encode(z_form_rt_mem(dst, src));
 8081   ins_pipe(pipe_class_dummy);
 8082 %}
 8083 
 8084 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
 8085   match(Set dst (MoveL2D src));
 8086   ins_cost(MEMORY_REF_COST);
 8087   size(4);
 8088   format %{ "LD      $dst,$src\t # MoveL2D" %}
 8089   opcode(LD_ZOPC);
 8090   ins_encode(z_form_rt_mem(dst, src));
 8091   ins_pipe(pipe_class_dummy);
 8092 %}
 8093 
 8094 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8095   match(Set dst (MoveI2F src));
 8096   ins_cost(MEMORY_REF_COST);
 8097   size(4);
 8098   format %{ "ST      $src,$dst\t # MoveI2F" %}
 8099   opcode(ST_ZOPC);
 8100   ins_encode(z_form_rt_mem(src, dst));
 8101   ins_pipe(pipe_class_dummy);
 8102 %}
 8103 
 8104 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
 8105   match(Set dst (MoveD2L src));
 8106   effect(DEF dst, USE src);
 8107   ins_cost(MEMORY_REF_COST);
 8108   size(4);
 8109   format %{ "STD     $src,$dst\t # MoveD2L" %}
 8110   opcode(STD_ZOPC);
 8111   ins_encode(z_form_rt_mem(src,dst));
 8112   ins_pipe(pipe_class_dummy);
 8113 %}
 8114 
 8115 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8116   match(Set dst (MoveL2D src));
 8117   ins_cost(MEMORY_REF_COST);
 8118   size(6);
 8119   format %{ "STG     $src,$dst\t # MoveL2D" %}
 8120   opcode(STG_ZOPC);
 8121   ins_encode(z_form_rt_mem(src,dst));
 8122   ins_pipe(pipe_class_dummy);
 8123 %}
 8124 
 8125 instruct convL2F_reg(regF dst, iRegL src) %{
 8126   match(Set dst (ConvL2F src));
 8127   // CC remains unchanged.
 8128   ins_cost(DEFAULT_COST);
 8129   size(4);
 8130   format %{ "CEGBR   $dst,$src" %}
 8131   opcode(CEGBR_ZOPC);
 8132   ins_encode(z_rreform(dst, src));
 8133   ins_pipe(pipe_class_dummy);
 8134 %}
 8135 
 8136 instruct convL2D_reg(regD dst, iRegL src) %{
 8137   match(Set dst (ConvL2D src));
 8138   // CC remains unchanged.
 8139   ins_cost(DEFAULT_COST);
 8140   size(4);
 8141   format %{ "CDGBR   $dst,$src" %}
 8142   opcode(CDGBR_ZOPC);
 8143   ins_encode(z_rreform(dst, src));
 8144   ins_pipe(pipe_class_dummy);
 8145 %}
 8146 
 8147 instruct convL2I_reg(iRegI dst, iRegL src) %{
 8148   match(Set dst (ConvL2I src));
 8149   // TODO: s390 port size(VARIABLE_SIZE);
 8150   format %{ "LR      $dst,$src\t # long->int (if needed)" %}
 8151   ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
 8152   ins_pipe(pipe_class_dummy);
 8153 %}
 8154 
 8155 // Register Shift Right Immediate
 8156 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
 8157   match(Set dst (ConvL2I (RShiftL src cnt)));
 8158   effect(KILL cr);
 8159   size(6);
 8160   format %{ "SRAG    $dst,$src,$cnt" %}
 8161   opcode(SRAG_ZOPC);
 8162   ins_encode(z_rsyform_const(dst, src, cnt));
 8163   ins_pipe(pipe_class_dummy);
 8164 %}
 8165 
 8166 //----------TRAP based zero checks and range checks----------------------------
 8167 
 8168 // SIGTRAP based implicit range checks in compiled code.
 8169 // A range check in the ideal world has one of the following shapes:
 8170 //   - (If le (CmpU length index)), (IfTrue  throw exception)
 8171 //   - (If lt (CmpU index length)), (IfFalse throw exception)
 8172 //
 8173 // Match range check 'If le (CmpU length index)'
 8174 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
 8175   match(If cmp (CmpU length index));
 8176   effect(USE labl);
 8177   predicate(TrapBasedRangeChecks &&
 8178             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
 8179             PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
 8180             Matcher::branches_to_uncommon_trap(_leaf));
 8181   ins_cost(1);
 8182   // TODO: s390 port size(FIXED_SIZE);
 8183 
 8184   ins_is_TrapBasedCheckNode(true);
 8185 
 8186   format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
 8187   ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
 8188   ins_pipe(pipe_class_trap);
 8189 %}
 8190 
 8191 // Match range check 'If lt (CmpU index length)'
 8192 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
 8193   match(If cmp (CmpU index length));
 8194   effect(USE labl, KILL cr);
 8195   predicate(TrapBasedRangeChecks &&
 8196             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
 8197             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
 8198             Matcher::branches_to_uncommon_trap(_leaf));
 8199   ins_cost(1);
 8200   // TODO: s390 port size(FIXED_SIZE);
 8201 
 8202   ins_is_TrapBasedCheckNode(true);
 8203 
 8204   format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
 8205   ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
 8206   ins_pipe(pipe_class_trap);
 8207 %}
 8208 
 8209 // Match range check 'If lt (CmpU index length)'
 8210 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
 8211   match(If cmp (CmpU index length));
 8212   effect(USE labl);
 8213   predicate(TrapBasedRangeChecks &&
 8214             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
 8215             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
 8216             Matcher::branches_to_uncommon_trap(_leaf));
 8217   ins_cost(1);
 8218   // TODO: s390 port size(FIXED_SIZE);
 8219 
 8220   ins_is_TrapBasedCheckNode(true);
 8221 
 8222   format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
 8223   ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
 8224   ins_pipe(pipe_class_trap);
 8225 %}
 8226 
 8227 // Implicit zero checks (more implicit null checks).
 8228 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
 8229   match(If cmp (CmpP value zero));
 8230   effect(USE labl);
 8231   predicate(TrapBasedNullChecks &&
 8232             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
 8233             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
 8234             Matcher::branches_to_uncommon_trap(_leaf));
 8235   size(6);
 8236 
 8237   ins_is_TrapBasedCheckNode(true);
 8238 
 8239   format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
 8240   ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
 8241   ins_pipe(pipe_class_trap);
 8242 %}
 8243 
 8244 // Implicit zero checks (more implicit null checks).
 8245 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
 8246   match(If cmp (CmpN value zero));
 8247   effect(USE labl);
 8248   predicate(TrapBasedNullChecks &&
 8249             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
 8250             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
 8251             Matcher::branches_to_uncommon_trap(_leaf));
 8252   size(6);
 8253 
 8254   ins_is_TrapBasedCheckNode(true);
 8255 
 8256   format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
 8257   ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
 8258   ins_pipe(pipe_class_trap);
 8259 %}
 8260 
 8261 //----------Compare instructions-----------------------------------------------
 8262 
 8263 // INT signed
 8264 
 8265 // Compare Integers
 8266 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 8267   match(Set cr (CmpI op1 op2));
 8268   size(2);
 8269   format %{ "CR      $op1,$op2" %}
 8270   opcode(CR_ZOPC);
 8271   ins_encode(z_rrform(op1, op2));
 8272   ins_pipe(pipe_class_dummy);
 8273 %}
 8274 
 8275 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 8276   match(Set cr (CmpI op1 op2));
 8277   size(6);
 8278   format %{ "CFI     $op1,$op2" %}
 8279   opcode(CFI_ZOPC);
 8280   ins_encode(z_rilform_signed(op1, op2));
 8281   ins_pipe(pipe_class_dummy);
 8282 %}
 8283 
 8284 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
 8285   match(Set cr (CmpI op1 op2));
 8286   size(4);
 8287   format %{ "CHI     $op1,$op2" %}
 8288   opcode(CHI_ZOPC);
 8289   ins_encode(z_riform_signed(op1, op2));
 8290   ins_pipe(pipe_class_dummy);
 8291 %}
 8292 
 8293 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
 8294   match(Set cr (CmpI op1 zero));
 8295   ins_cost(DEFAULT_COST_LOW);
 8296   size(2);
 8297   format %{ "LTR     $op1,$op1" %}
 8298   opcode(LTR_ZOPC);
 8299   ins_encode(z_rrform(op1, op1));
 8300   ins_pipe(pipe_class_dummy);
 8301 %}
 8302 
 8303 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
 8304   match(Set cr (CmpI op1 (LoadI op2)));
 8305   ins_cost(MEMORY_REF_COST);
 8306   // TODO: s390 port size(VARIABLE_SIZE);
 8307   format %{ "C(Y)    $op1, $op2\t # int" %}
 8308   opcode(CY_ZOPC, C_ZOPC);
 8309   ins_encode(z_form_rt_mem_opt(op1, op2));
 8310   ins_pipe(pipe_class_dummy);
 8311 %}
 8312 
 8313 // INT unsigned
 8314 
 8315 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 8316   match(Set cr (CmpU op1 op2));
 8317   size(2);
 8318   format %{ "CLR     $op1,$op2\t # unsigned" %}
 8319   opcode(CLR_ZOPC);
 8320   ins_encode(z_rrform(op1, op2));
 8321   ins_pipe(pipe_class_dummy);
 8322 %}
 8323 
 8324 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
 8325   match(Set cr (CmpU op1 op2));
 8326   size(6);
 8327   format %{ "CLFI    $op1,$op2\t # unsigned" %}
 8328   opcode(CLFI_ZOPC);
 8329   ins_encode(z_rilform_unsigned(op1, op2));
 8330   ins_pipe(pipe_class_dummy);
 8331 %}
 8332 
 8333 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
 8334   match(Set cr (CmpU op1 (LoadI op2)));
 8335   ins_cost(MEMORY_REF_COST);
 8336   // TODO: s390 port size(VARIABLE_SIZE);
 8337   format %{ "CL(Y)   $op1, $op2\t # unsigned" %}
 8338   opcode(CLY_ZOPC, CL_ZOPC);
 8339   ins_encode(z_form_rt_mem_opt(op1, op2));
 8340   ins_pipe(pipe_class_dummy);
 8341 %}
 8342 
 8343 // LONG signed
 8344 
 8345 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 8346   match(Set cr (CmpL op1 op2));
 8347   size(4);
 8348   format %{ "CGR     $op1,$op2\t # long" %}
 8349   opcode(CGR_ZOPC);
 8350   ins_encode(z_rreform(op1, op2));
 8351   ins_pipe(pipe_class_dummy);
 8352 %}
 8353 
 8354 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
 8355   match(Set cr (CmpL op1 (ConvI2L op2)));
 8356   size(4);
 8357   format %{ "CGFR    $op1,$op2\t # long/int" %}
 8358   opcode(CGFR_ZOPC);
 8359   ins_encode(z_rreform(op1, op2));
 8360   ins_pipe(pipe_class_dummy);
 8361 %}
 8362 
 8363 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
 8364   match(Set cr (CmpL op1 con));
 8365   size(6);
 8366   format %{ "CGFI    $op1,$con" %}
 8367   opcode(CGFI_ZOPC);
 8368   ins_encode(z_rilform_signed(op1, con));
 8369   ins_pipe(pipe_class_dummy);
 8370 %}
 8371 
 8372 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
 8373   match(Set cr (CmpL op1 con));
 8374   size(4);
 8375   format %{ "CGHI    $op1,$con" %}
 8376   opcode(CGHI_ZOPC);
 8377   ins_encode(z_riform_signed(op1, con));
 8378   ins_pipe(pipe_class_dummy);
 8379 %}
 8380 
 8381 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
 8382   match(Set cr (CmpL op1 con));
 8383   ins_cost(DEFAULT_COST_LOW);
 8384   size(4);
 8385   format %{ "LTGR    $op1,$op1" %}
 8386   opcode(LTGR_ZOPC);
 8387   ins_encode(z_rreform(op1, op1));
 8388   ins_pipe(pipe_class_dummy);
 8389 %}
 8390 
 8391 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
 8392   match(Set cr (CmpL (ConvI2L op1) con));
 8393   ins_cost(DEFAULT_COST_LOW);
 8394   size(4);
 8395   format %{ "LTGFR    $op1,$op1" %}
 8396   opcode(LTGFR_ZOPC);
 8397   ins_encode(z_rreform(op1, op1));
 8398   ins_pipe(pipe_class_dummy);
 8399 %}
 8400 
 8401 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
 8402   match(Set cr (CmpL dst (LoadL src)));
 8403   ins_cost(MEMORY_REF_COST);
 8404   size(Z_DISP3_SIZE);
 8405   format %{ "CG      $dst, $src\t # long" %}
 8406   opcode(CG_ZOPC, CG_ZOPC);
 8407   ins_encode(z_form_rt_mem_opt(dst, src));
 8408   ins_pipe(pipe_class_dummy);
 8409 %}
 8410 
 8411 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
 8412   match(Set cr (CmpL dst (ConvI2L (LoadI src))));
 8413   ins_cost(MEMORY_REF_COST);
 8414   size(Z_DISP3_SIZE);
 8415   format %{ "CGF     $dst, $src\t # long/int" %}
 8416   opcode(CGF_ZOPC, CGF_ZOPC);
 8417   ins_encode(z_form_rt_mem_opt(dst, src));
 8418   ins_pipe(pipe_class_dummy);
 8419 %}
 8420 
 8421 //  LONG unsigned
 8422 // Added CmpUL for LoopPredicate.
 8423 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 8424   match(Set cr (CmpUL op1 op2));
 8425   size(4);
 8426   format %{ "CLGR    $op1,$op2\t # long" %}
 8427   opcode(CLGR_ZOPC);
 8428   ins_encode(z_rreform(op1, op2));
 8429   ins_pipe(pipe_class_dummy);
 8430 %}
 8431 
 8432 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
 8433   match(Set cr (CmpUL op1 con));
 8434   size(6);
 8435   format %{ "CLGFI   $op1,$con" %}
 8436   opcode(CLGFI_ZOPC);
 8437   ins_encode(z_rilform_unsigned(op1, con));
 8438   ins_pipe(pipe_class_dummy);
 8439 %}
 8440 
 8441 //  PTR unsigned
 8442 
 8443 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
 8444   match(Set cr (CmpP op1 op2));
 8445   size(4);
 8446   format %{ "CLGR    $op1,$op2\t # ptr" %}
 8447   opcode(CLGR_ZOPC);
 8448   ins_encode(z_rreform(op1, op2));
 8449   ins_pipe(pipe_class_dummy);
 8450 %}
 8451 
 8452 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
 8453   match(Set cr (CmpP op1 op2));
 8454   ins_cost(DEFAULT_COST_LOW);
 8455   size(4);
 8456   format %{ "LTGR    $op1, $op1\t # ptr" %}
 8457   opcode(LTGR_ZOPC);
 8458   ins_encode(z_rreform(op1, op1));
 8459   ins_pipe(pipe_class_dummy);
 8460 %}
 8461 
 8462 // Don't use LTGFR which performs sign extend.
 8463 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
 8464   match(Set cr (CmpP (DecodeN op1) op2));
 8465   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 8466   ins_cost(DEFAULT_COST_LOW);
 8467   size(2);
 8468   format %{ "LTR    $op1, $op1\t # ptr" %}
 8469   opcode(LTR_ZOPC);
 8470   ins_encode(z_rrform(op1, op1));
 8471   ins_pipe(pipe_class_dummy);
 8472 %}
 8473 
 8474 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
 8475   match(Set cr (CmpP dst (LoadP src)));
 8476   ins_cost(MEMORY_REF_COST);
 8477   size(Z_DISP3_SIZE);
 8478   format %{ "CLG     $dst, $src\t # ptr" %}
 8479   opcode(CLG_ZOPC, CLG_ZOPC);
 8480   ins_encode(z_form_rt_mem_opt(dst, src));
 8481   ins_pipe(pipe_class_dummy);
 8482 %}
 8483 
 8484 //----------Max and Min--------------------------------------------------------
 8485 
 8486 // Max Register with Register
 8487 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8488   match(Set dst (MinI src1 src2));
 8489   effect(KILL cr);
 8490   predicate(VM_Version::has_LoadStoreConditional());
 8491   ins_cost(3 * DEFAULT_COST);
 8492   // TODO: s390 port size(VARIABLE_SIZE);
 8493   format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
 8494   ins_encode %{
 8495     Register Rdst = $dst$$Register;
 8496     Register Rsrc1 = $src1$$Register;
 8497     Register Rsrc2 = $src2$$Register;
 8498 
 8499     if (Rsrc1 == Rsrc2) {
 8500       if (Rdst != Rsrc1) {
 8501         __ z_lgfr(Rdst, Rsrc1);
 8502       }
 8503     } else if (Rdst == Rsrc1) {   // Rdst preset with src1.
 8504       __ z_cr(Rsrc1, Rsrc2);      // Move src2 only if src1 is NotLow.
 8505       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
 8506     } else if (Rdst == Rsrc2) {   // Rdst preset with src2.
 8507       __ z_cr(Rsrc2, Rsrc1);      // Move src1 only if src2 is NotLow.
 8508       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
 8509     } else {
 8510       // Rdst is disjoint from operands, move in either case.
 8511       __ z_cr(Rsrc1, Rsrc2);
 8512       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
 8513       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8514     }
 8515   %}
 8516   ins_pipe(pipe_class_dummy);
 8517 %}
 8518 
 8519 // Min Register with Register.
 8520 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8521   match(Set dst (MinI src1 src2));
 8522   effect(KILL cr);
 8523   predicate(VM_Version::has_CompareBranch());
 8524   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8525   // TODO: s390 port size(VARIABLE_SIZE);
 8526   format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
 8527   ins_encode %{
 8528     Register Rdst = $dst$$Register;
 8529     Register Rsrc1 = $src1$$Register;
 8530     Register Rsrc2 = $src2$$Register;
 8531     Label done;
 8532 
 8533     if (Rsrc1 == Rsrc2) {
 8534       if (Rdst != Rsrc1) {
 8535         __ z_lgfr(Rdst, Rsrc1);
 8536       }
 8537     } else if (Rdst == Rsrc1) {
 8538       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
 8539       __ z_lgfr(Rdst, Rsrc2);
 8540     } else if (Rdst == Rsrc2) {
 8541       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
 8542       __ z_lgfr(Rdst, Rsrc1);
 8543     } else {
 8544       __ z_lgfr(Rdst, Rsrc1);
 8545       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
 8546       __ z_lgfr(Rdst, Rsrc2);
 8547     }
 8548     __ bind(done);
 8549   %}
 8550   ins_pipe(pipe_class_dummy);
 8551 %}
 8552 
 8553 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8554   match(Set dst (MinI src1 src2));
 8555   effect(KILL cr);
 8556   predicate(!VM_Version::has_CompareBranch());
 8557   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
 8558   // TODO: s390 port size(VARIABLE_SIZE);
 8559   format %{ "MinI $dst $src1,$src2\t MinI" %}
 8560   ins_encode %{
 8561     Register Rdst = $dst$$Register;
 8562     Register Rsrc1 = $src1$$Register;
 8563     Register Rsrc2 = $src2$$Register;
 8564     Label done;
 8565 
 8566     if (Rsrc1 == Rsrc2) {
 8567       if (Rdst != Rsrc1) {
 8568         __ z_lgfr(Rdst, Rsrc1);
 8569       }
 8570     } else if (Rdst == Rsrc1) {
 8571       __ z_cr(Rsrc1, Rsrc2);
 8572       __ z_brl(done);
 8573       __ z_lgfr(Rdst, Rsrc2);
 8574     } else if (Rdst == Rsrc2) {
 8575       __ z_cr(Rsrc2, Rsrc1);
 8576       __ z_brl(done);
 8577       __ z_lgfr(Rdst, Rsrc1);
 8578     } else {
 8579       __ z_lgfr(Rdst, Rsrc1);
 8580       __ z_cr(Rsrc1, Rsrc2);
 8581       __ z_brl(done);
 8582       __ z_lgfr(Rdst, Rsrc2);
 8583     }
 8584     __ bind(done);
 8585   %}
 8586   ins_pipe(pipe_class_dummy);
 8587 %}
 8588 
 8589 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8590   match(Set dst (MinI src1 src2));
 8591   effect(KILL cr);
 8592   predicate(VM_Version::has_LoadStoreConditional());
 8593   ins_cost(3 * DEFAULT_COST);
 8594   // TODO: s390 port size(VARIABLE_SIZE);
 8595   format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
 8596   ins_encode %{
 8597     Register Rdst = $dst$$Register;
 8598     Register Rsrc1 = $src1$$Register;
 8599     int      Isrc2 = $src2$$constant;
 8600 
 8601     if (Rdst == Rsrc1) {
 8602       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8603       __ z_cfi(Rsrc1, Isrc2);
 8604       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
 8605     } else {
 8606       __ load_const_optimized(Rdst, Isrc2);
 8607       __ z_cfi(Rsrc1, Isrc2);
 8608       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8609     }
 8610   %}
 8611   ins_pipe(pipe_class_dummy);
 8612 %}
 8613 
 8614 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8615   match(Set dst (MinI src1 src2));
 8616   effect(KILL cr);
 8617   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8618   // TODO: s390 port size(VARIABLE_SIZE);
 8619   format %{ "MinI $dst $src1,$src2\t MinI const32" %}
 8620   ins_encode %{
 8621     Label done;
 8622     if ($dst$$Register != $src1$$Register) {
 8623       __ z_lgfr($dst$$Register, $src1$$Register);
 8624     }
 8625     __ z_cfi($src1$$Register, $src2$$constant);
 8626     __ z_brl(done);
 8627     __ z_lgfi($dst$$Register, $src2$$constant);
 8628     __ bind(done);
 8629   %}
 8630   ins_pipe(pipe_class_dummy);
 8631 %}
 8632 
 8633 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8634   match(Set dst (MinI src1 src2));
 8635   effect(KILL cr);
 8636   predicate(VM_Version::has_LoadStoreConditional());
 8637   ins_cost(3 * DEFAULT_COST);
 8638   // TODO: s390 port size(VARIABLE_SIZE);
 8639   format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
 8640   ins_encode %{
 8641     Register Rdst = $dst$$Register;
 8642     Register Rsrc1 = $src1$$Register;
 8643     int      Isrc2 = $src2$$constant;
 8644 
 8645     if (Rdst == Rsrc1) {
 8646       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8647       __ z_chi(Rsrc1, Isrc2);
 8648       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
 8649     } else {
 8650       __ load_const_optimized(Rdst, Isrc2);
 8651       __ z_chi(Rsrc1, Isrc2);
 8652       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8653     }
 8654   %}
 8655   ins_pipe(pipe_class_dummy);
 8656 %}
 8657 
 8658 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8659   match(Set dst (MinI src1 src2));
 8660   effect(KILL cr);
 8661   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8662   // TODO: s390 port size(VARIABLE_SIZE);
 8663   format %{ "MinI $dst $src1,$src2\t MinI const16" %}
 8664   ins_encode %{
 8665     Label done;
 8666     if ($dst$$Register != $src1$$Register) {
 8667       __ z_lgfr($dst$$Register, $src1$$Register);
 8668     }
 8669     __ z_chi($src1$$Register, $src2$$constant);
 8670     __ z_brl(done);
 8671     __ z_lghi($dst$$Register, $src2$$constant);
 8672     __ bind(done);
 8673   %}
 8674   ins_pipe(pipe_class_dummy);
 8675 %}
 8676 
 8677 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
 8678   match(Set dst (MinI src1 src2));
 8679   effect(KILL cr);
 8680   predicate(VM_Version::has_CompareBranch());
 8681   ins_cost(DEFAULT_COST + BRANCH_COST);
 8682   // TODO: s390 port size(VARIABLE_SIZE);
 8683   format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
 8684   ins_encode %{
 8685     Label done;
 8686     if ($dst$$Register != $src1$$Register) {
 8687       __ z_lgfr($dst$$Register, $src1$$Register);
 8688     }
 8689     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
 8690     __ z_lghi($dst$$Register, $src2$$constant);
 8691     __ bind(done);
 8692   %}
 8693   ins_pipe(pipe_class_dummy);
 8694 %}
 8695 
 8696 // Max Register with Register
 8697 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8698   match(Set dst (MaxI src1 src2));
 8699   effect(KILL cr);
 8700   predicate(VM_Version::has_LoadStoreConditional());
 8701   ins_cost(3 * DEFAULT_COST);
 8702   // TODO: s390 port size(VARIABLE_SIZE);
 8703   format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
 8704   ins_encode %{
 8705     Register Rdst = $dst$$Register;
 8706     Register Rsrc1 = $src1$$Register;
 8707     Register Rsrc2 = $src2$$Register;
 8708 
 8709     if (Rsrc1 == Rsrc2) {
 8710       if (Rdst != Rsrc1) {
 8711         __ z_lgfr(Rdst, Rsrc1);
 8712       }
 8713     } else if (Rdst == Rsrc1) { // Rdst preset with src1.
 8714       __ z_cr(Rsrc1, Rsrc2);    // Move src2 only if src1 is NotHigh.
 8715       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
 8716     } else if (Rdst == Rsrc2) { // Rdst preset with src2.
 8717       __ z_cr(Rsrc2, Rsrc1);    // Move src1 only if src2 is NotHigh.
 8718       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
 8719     } else {                    // Rdst is disjoint from operands, move in either case.
 8720       __ z_cr(Rsrc1, Rsrc2);
 8721       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
 8722       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8723     }
 8724   %}
 8725   ins_pipe(pipe_class_dummy);
 8726 %}
 8727 
 8728 // Max Register with Register
 8729 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8730   match(Set dst (MaxI src1 src2));
 8731   effect(KILL cr);
 8732   predicate(VM_Version::has_CompareBranch());
 8733   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8734   // TODO: s390 port size(VARIABLE_SIZE);
 8735   format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
 8736   ins_encode %{
 8737     Register Rdst = $dst$$Register;
 8738     Register Rsrc1 = $src1$$Register;
 8739     Register Rsrc2 = $src2$$Register;
 8740     Label done;
 8741 
 8742     if (Rsrc1 == Rsrc2) {
 8743       if (Rdst != Rsrc1) {
 8744         __ z_lgfr(Rdst, Rsrc1);
 8745       }
 8746     } else if (Rdst == Rsrc1) {
 8747       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
 8748       __ z_lgfr(Rdst, Rsrc2);
 8749     } else if (Rdst == Rsrc2) {
 8750       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
 8751       __ z_lgfr(Rdst, Rsrc1);
 8752     } else {
 8753       __ z_lgfr(Rdst, Rsrc1);
 8754       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
 8755       __ z_lgfr(Rdst, Rsrc2);
 8756     }
 8757     __ bind(done);
 8758   %}
 8759   ins_pipe(pipe_class_dummy);
 8760 %}
 8761 
 8762 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8763   match(Set dst (MaxI src1 src2));
 8764   effect(KILL cr);
 8765   predicate(!VM_Version::has_CompareBranch());
 8766   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
 8767   // TODO: s390 port size(VARIABLE_SIZE);
 8768   format %{ "MaxI $dst $src1,$src2\t MaxI" %}
 8769   ins_encode %{
 8770     Register Rdst = $dst$$Register;
 8771     Register Rsrc1 = $src1$$Register;
 8772     Register Rsrc2 = $src2$$Register;
 8773     Label done;
 8774 
 8775     if (Rsrc1 == Rsrc2) {
 8776       if (Rdst != Rsrc1) {
 8777         __ z_lgfr(Rdst, Rsrc1);
 8778       }
 8779     } else if (Rdst == Rsrc1) {
 8780       __ z_cr(Rsrc1, Rsrc2);
 8781       __ z_brh(done);
 8782       __ z_lgfr(Rdst, Rsrc2);
 8783     } else if (Rdst == Rsrc2) {
 8784       __ z_cr(Rsrc2, Rsrc1);
 8785       __ z_brh(done);
 8786       __ z_lgfr(Rdst, Rsrc1);
 8787     } else {
 8788       __ z_lgfr(Rdst, Rsrc1);
 8789       __ z_cr(Rsrc1, Rsrc2);
 8790       __ z_brh(done);
 8791       __ z_lgfr(Rdst, Rsrc2);
 8792     }
 8793 
 8794     __ bind(done);
 8795   %}
 8796 
 8797   ins_pipe(pipe_class_dummy);
 8798 %}
 8799 
 8800 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8801   match(Set dst (MaxI src1 src2));
 8802   effect(KILL cr);
 8803   predicate(VM_Version::has_LoadStoreConditional());
 8804   ins_cost(3 * DEFAULT_COST);
 8805   // TODO: s390 port size(VARIABLE_SIZE);
 8806   format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
 8807   ins_encode %{
 8808     Register Rdst = $dst$$Register;
 8809     Register Rsrc1 = $src1$$Register;
 8810     int      Isrc2 = $src2$$constant;
 8811 
 8812     if (Rdst == Rsrc1) {
 8813       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8814       __ z_cfi(Rsrc1, Isrc2);
 8815       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
 8816     } else {
 8817       __ load_const_optimized(Rdst, Isrc2);
 8818       __ z_cfi(Rsrc1, Isrc2);
 8819       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8820     }
 8821   %}
 8822   ins_pipe(pipe_class_dummy);
 8823 %}
 8824 
 8825 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8826   match(Set dst (MaxI src1 src2));
 8827   effect(KILL cr);
 8828   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8829   // TODO: s390 port size(VARIABLE_SIZE);
 8830   format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
 8831   ins_encode %{
 8832     Label done;
 8833     if ($dst$$Register != $src1$$Register) {
 8834       __ z_lgfr($dst$$Register, $src1$$Register);
 8835     }
 8836     __ z_cfi($src1$$Register, $src2$$constant);
 8837     __ z_brh(done);
 8838     __ z_lgfi($dst$$Register, $src2$$constant);
 8839     __ bind(done);
 8840   %}
 8841   ins_pipe(pipe_class_dummy);
 8842 %}
 8843 
 8844 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8845   match(Set dst (MaxI src1 src2));
 8846   effect(KILL cr);
 8847   predicate(VM_Version::has_LoadStoreConditional());
 8848   ins_cost(3 * DEFAULT_COST);
 8849   // TODO: s390 port size(VARIABLE_SIZE);
 8850   format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
 8851   ins_encode %{
 8852     Register Rdst = $dst$$Register;
 8853     Register Rsrc1 = $src1$$Register;
 8854     int      Isrc2 = $src2$$constant;
 8855     if (Rdst == Rsrc1) {
 8856       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8857       __ z_chi(Rsrc1, Isrc2);
 8858       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
 8859     } else {
 8860       __ load_const_optimized(Rdst, Isrc2);
 8861       __ z_chi(Rsrc1, Isrc2);
 8862       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8863     }
 8864   %}
 8865   ins_pipe(pipe_class_dummy);
 8866 %}
 8867 
 8868 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8869   match(Set dst (MaxI src1 src2));
 8870   effect(KILL cr);
 8871   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8872   // TODO: s390 port size(VARIABLE_SIZE);
 8873   format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
 8874   ins_encode %{
 8875     Label done;
 8876     if ($dst$$Register != $src1$$Register) {
 8877       __ z_lgfr($dst$$Register, $src1$$Register);
 8878     }
 8879     __ z_chi($src1$$Register, $src2$$constant);
 8880     __ z_brh(done);
 8881     __ z_lghi($dst$$Register, $src2$$constant);
 8882     __ bind(done);
 8883   %}
 8884   ins_pipe(pipe_class_dummy);
 8885 %}
 8886 
 8887 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
 8888   match(Set dst (MaxI src1 src2));
 8889   effect(KILL cr);
 8890   predicate(VM_Version::has_CompareBranch());
 8891   ins_cost(DEFAULT_COST + BRANCH_COST);
 8892   // TODO: s390 port size(VARIABLE_SIZE);
 8893   format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
 8894   ins_encode %{
 8895     Label done;
 8896     if ($dst$$Register != $src1$$Register) {
 8897       __ z_lgfr($dst$$Register, $src1$$Register);
 8898     }
 8899     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
 8900     __ z_lghi($dst$$Register, $src2$$constant);
 8901     __ bind(done);
 8902   %}
 8903   ins_pipe(pipe_class_dummy);
 8904 %}
 8905 
 8906 //----------Abs---------------------------------------------------------------
 8907 
 8908 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
 8909   match(Set dst (AbsI src));
 8910   effect(KILL cr);
 8911   ins_cost(DEFAULT_COST_LOW);
 8912   // TODO: s390 port size(FIXED_SIZE);
 8913   format %{ "LPR     $dst, $src" %}
 8914   opcode(LPR_ZOPC);
 8915   ins_encode(z_rrform(dst, src));
 8916   ins_pipe(pipe_class_dummy);
 8917 %}
 8918 
 8919 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
 8920   match(Set dst (AbsL src));
 8921   effect(KILL cr);
 8922   ins_cost(DEFAULT_COST_LOW);
 8923   // TODO: s390 port size(FIXED_SIZE);
 8924   format %{ "LPGR     $dst, $src" %}
 8925   opcode(LPGR_ZOPC);
 8926   ins_encode(z_rreform(dst, src));
 8927   ins_pipe(pipe_class_dummy);
 8928 %}
 8929 
 8930 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
 8931   match(Set dst (SubI zero (AbsI src)));
 8932   effect(KILL cr);
 8933   ins_cost(DEFAULT_COST_LOW);
 8934   // TODO: s390 port size(FIXED_SIZE);
 8935   format %{ "LNR     $dst, $src" %}
 8936   opcode(LNR_ZOPC);
 8937   ins_encode(z_rrform(dst, src));
 8938   ins_pipe(pipe_class_dummy);
 8939 %}
 8940 
 8941 //----------Float Compares----------------------------------------------------
 8942 
 8943 // Compare floating, generate condition code.
 8944 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
 8945   match(Set cr (CmpF src1 src2));
 8946   ins_cost(ALU_REG_COST);
 8947   size(4);
 8948   format %{ "FCMPcc   $src1,$src2\t # float" %}
 8949   ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
 8950   ins_pipe(pipe_class_dummy);
 8951 %}
 8952 
 8953 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
 8954   match(Set cr (CmpD src1 src2));
 8955   ins_cost(ALU_REG_COST);
 8956   size(4);
 8957   format %{ "FCMPcc   $src1,$src2 \t # double" %}
 8958   ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
 8959   ins_pipe(pipe_class_dummy);
 8960 %}
 8961 
 8962 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
 8963   match(Set cr (CmpF src1 (LoadF src2)));
 8964   ins_cost(ALU_MEMORY_COST);
 8965   size(6);
 8966   format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
 8967   opcode(CEB_ZOPC);
 8968   ins_encode(z_form_rt_memFP(src1, src2));
 8969   ins_pipe(pipe_class_dummy);
 8970 %}
 8971 
 8972 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
 8973   match(Set cr (CmpD src1 (LoadD src2)));
 8974   ins_cost(ALU_MEMORY_COST);
 8975   size(6);
 8976   format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
 8977   opcode(CDB_ZOPC);
 8978   ins_encode(z_form_rt_memFP(src1, src2));
 8979   ins_pipe(pipe_class_dummy);
 8980 %}
 8981 
 8982 // Compare floating, generate condition code
 8983 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
 8984   match(Set cr (CmpF src1 src2));
 8985   ins_cost(DEFAULT_COST);
 8986   size(4);
 8987   format %{ "LTEBR    $src1,$src1\t # float" %}
 8988   opcode(LTEBR_ZOPC);
 8989   ins_encode(z_rreform(src1, src1));
 8990   ins_pipe(pipe_class_dummy);
 8991 %}
 8992 
 8993 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
 8994   match(Set cr (CmpD src1 src2));
 8995   ins_cost(DEFAULT_COST);
 8996   size(4);
 8997   format %{ "LTDBR    $src1,$src1 \t # double" %}
 8998   opcode(LTDBR_ZOPC);
 8999   ins_encode(z_rreform(src1, src1));
 9000   ins_pipe(pipe_class_dummy);
 9001 %}
 9002 
 9003 // Compare floating, generate -1,0,1
 9004 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
 9005   match(Set dst (CmpF3 src1 src2));
 9006   effect(KILL cr);
 9007   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9008   size(24);
 9009   format %{ "CmpF3    $dst,$src1,$src2" %}
 9010   ins_encode %{
 9011     // compare registers
 9012     __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
 9013     // Convert condition code into -1,0,1, where
 9014     // -1 means unordered or less
 9015     //  0 means equal
 9016     //  1 means greater.
 9017     if (VM_Version::has_LoadStoreConditional()) {
 9018       Register one       = Z_R0_scratch;
 9019       Register minus_one = Z_R1_scratch;
 9020       __ z_lghi(minus_one, -1);
 9021       __ z_lghi(one, 1);
 9022       __ z_lghi( $dst$$Register, 0);
 9023       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9024       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
 9025     } else {
 9026       Label done;
 9027       __ clear_reg($dst$$Register, true, false);
 9028       __ z_bre(done);
 9029       __ z_lhi($dst$$Register, 1);
 9030       __ z_brh(done);
 9031       __ z_lhi($dst$$Register, -1);
 9032       __ bind(done);
 9033     }
 9034   %}
 9035   ins_pipe(pipe_class_dummy);
 9036 %}
 9037 
 9038 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
 9039   match(Set dst (CmpD3 src1 src2));
 9040   effect(KILL cr);
 9041   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9042   size(24);
 9043   format %{ "CmpD3    $dst,$src1,$src2" %}
 9044   ins_encode %{
 9045     // compare registers
 9046     __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
 9047     // Convert condition code into -1,0,1, where
 9048     // -1 means unordered or less
 9049     //  0 means equal
 9050     //  1 means greater.
 9051     if (VM_Version::has_LoadStoreConditional()) {
 9052       Register one       = Z_R0_scratch;
 9053       Register minus_one = Z_R1_scratch;
 9054       __ z_lghi(minus_one, -1);
 9055       __ z_lghi(one, 1);
 9056       __ z_lghi( $dst$$Register, 0);
 9057       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9058       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
 9059     } else {
 9060       Label done;
 9061       // indicate unused result
 9062       (void) __ clear_reg($dst$$Register, true, false);
 9063       __ z_bre(done);
 9064       __ z_lhi($dst$$Register, 1);
 9065       __ z_brh(done);
 9066       __ z_lhi($dst$$Register, -1);
 9067       __ bind(done);
 9068     }
 9069   %}
 9070   ins_pipe(pipe_class_dummy);
 9071 %}
 9072 
 9073 //----------Branches---------------------------------------------------------
 9074 // Jump
 9075 
 9076 // Direct Branch.
 9077 instruct branch(label labl) %{
 9078   match(Goto);
 9079   effect(USE labl);
 9080   ins_cost(BRANCH_COST);
 9081   size(4);
 9082   format %{ "BRU     $labl" %}
 9083   ins_encode(z_enc_bru(labl));
 9084   ins_pipe(pipe_class_dummy);
 9085   // If set to 1 this indicates that the current instruction is a
 9086   // short variant of a long branch. This avoids using this
 9087   // instruction in first-pass matching. It will then only be used in
 9088   // the `Shorten_branches' pass.
 9089   ins_short_branch(1);
 9090 %}
 9091 
 9092 // Direct Branch.
 9093 instruct branchFar(label labl) %{
 9094   match(Goto);
 9095   effect(USE labl);
 9096   ins_cost(BRANCH_COST);
 9097   size(6);
 9098   format %{ "BRUL   $labl" %}
 9099   ins_encode(z_enc_brul(labl));
 9100   ins_pipe(pipe_class_dummy);
 9101   // This is not a short variant of a branch, but the long variant.
 9102   ins_short_branch(0);
 9103 %}
 9104 
 9105 // Conditional Near Branch
 9106 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
 9107   // Same match rule as `branchConFar'.
 9108   match(If cmp cr);
 9109   effect(USE lbl);
 9110   ins_cost(BRANCH_COST);
 9111   size(4);
 9112   format %{ "branch_con_short,$cmp   $lbl" %}
 9113   ins_encode(z_enc_branch_con_short(cmp, lbl));
 9114   ins_pipe(pipe_class_dummy);
 9115   // If set to 1 this indicates that the current instruction is a
 9116   // short variant of a long branch. This avoids using this
 9117   // instruction in first-pass matching. It will then only be used in
 9118   // the `Shorten_branches' pass.
 9119   ins_short_branch(1);
 9120 %}
 9121 
 9122 // This is for cases when the z/Architecture conditional branch instruction
 9123 // does not reach far enough. So we emit a far branch here, which is
 9124 // more expensive.
 9125 //
 9126 // Conditional Far Branch
 9127 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
 9128   // Same match rule as `branchCon'.
 9129   match(If cmp cr);
 9130   effect(USE cr, USE lbl);
 9131   // Make more expensive to prefer compare_and_branch over separate instructions.
 9132   ins_cost(2 * BRANCH_COST);
 9133   size(6);
 9134   format %{ "branch_con_far,$cmp   $lbl" %}
 9135   ins_encode(z_enc_branch_con_far(cmp, lbl));
 9136   ins_pipe(pipe_class_dummy);
 9137   // This is not a short variant of a branch, but the long variant..
 9138   ins_short_branch(0);
 9139 %}
 9140 
 9141 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
 9142   match(CountedLoopEnd cmp cr);
 9143   effect(USE labl);
 9144   ins_cost(BRANCH_COST);
 9145   size(4);
 9146   format %{ "branch_con_short,$cmp   $labl\t # counted loop end" %}
 9147   ins_encode(z_enc_branch_con_short(cmp, labl));
 9148   ins_pipe(pipe_class_dummy);
 9149   // If set to 1 this indicates that the current instruction is a
 9150   // short variant of a long branch. This avoids using this
 9151   // instruction in first-pass matching. It will then only be used in
 9152   // the `Shorten_branches' pass.
 9153   ins_short_branch(1);
 9154 %}
 9155 
 9156 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
 9157   match(CountedLoopEnd cmp cr);
 9158   effect(USE labl);
 9159   ins_cost(BRANCH_COST);
 9160   size(6);
 9161   format %{ "branch_con_far,$cmp   $labl\t # counted loop end" %}
 9162   ins_encode(z_enc_branch_con_far(cmp, labl));
 9163   ins_pipe(pipe_class_dummy);
 9164   // This is not a short variant of a branch, but the long variant.
 9165   ins_short_branch(0);
 9166 %}
 9167 
 9168 //----------Compare and Branch (short distance)------------------------------
 9169 
 9170 // INT REG operands for loop counter processing.
 9171 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9172   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9173   effect(USE labl, KILL cr);
 9174   predicate(VM_Version::has_CompareBranch());
 9175   ins_cost(BRANCH_COST);
 9176   // TODO: s390 port size(FIXED_SIZE);
 9177   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
 9178   opcode(CRJ_ZOPC);
 9179   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9180   ins_pipe(pipe_class_dummy);
 9181   ins_short_branch(1);
 9182 %}
 9183 
 9184 // INT REG operands.
 9185 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9186   match(If boolnode (CmpI src1 src2));
 9187   effect(USE labl, KILL cr);
 9188   predicate(VM_Version::has_CompareBranch());
 9189   ins_cost(BRANCH_COST);
 9190   // TODO: s390 port size(FIXED_SIZE);
 9191   format %{ "CRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9192   opcode(CRJ_ZOPC);
 9193   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9194   ins_pipe(pipe_class_dummy);
 9195   ins_short_branch(1);
 9196 %}
 9197 
 9198 // Unsigned INT REG operands
 9199 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9200   match(If boolnode (CmpU src1 src2));
 9201   effect(USE labl, KILL cr);
 9202   predicate(VM_Version::has_CompareBranch());
 9203   ins_cost(BRANCH_COST);
 9204   // TODO: s390 port size(FIXED_SIZE);
 9205   format %{ "CLRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9206   opcode(CLRJ_ZOPC);
 9207   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9208   ins_pipe(pipe_class_dummy);
 9209   ins_short_branch(1);
 9210 %}
 9211 
 9212 // LONG REG operands
 9213 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
 9214   match(If boolnode (CmpL src1 src2));
 9215   effect(USE labl, KILL cr);
 9216   predicate(VM_Version::has_CompareBranch());
 9217   ins_cost(BRANCH_COST);
 9218   // TODO: s390 port size(FIXED_SIZE);
 9219   format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9220   opcode(CGRJ_ZOPC);
 9221   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9222   ins_pipe(pipe_class_dummy);
 9223   ins_short_branch(1);
 9224 %}
 9225 
 9226 //  PTR REG operands
 9227 
 9228 // Separate rules for regular and narrow oops.  ADLC can't recognize
 9229 // rules with polymorphic operands to be sisters -> shorten_branches
 9230 // will not shorten.
 9231 
 9232 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
 9233   match(If boolnode (CmpP src1 src2));
 9234   effect(USE labl, KILL cr);
 9235   predicate(VM_Version::has_CompareBranch());
 9236   ins_cost(BRANCH_COST);
 9237   // TODO: s390 port size(FIXED_SIZE);
 9238   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9239   opcode(CLGRJ_ZOPC);
 9240   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9241   ins_pipe(pipe_class_dummy);
 9242   ins_short_branch(1);
 9243 %}
 9244 
 9245 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
 9246   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9247   effect(USE labl, KILL cr);
 9248   predicate(VM_Version::has_CompareBranch());
 9249   ins_cost(BRANCH_COST);
 9250   // TODO: s390 port size(FIXED_SIZE);
 9251   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9252   opcode(CLGRJ_ZOPC);
 9253   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9254   ins_pipe(pipe_class_dummy);
 9255   ins_short_branch(1);
 9256 %}
 9257 
 9258 // INT REG/IMM operands for loop counter processing
 9259 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9260   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9261   effect(USE labl, KILL cr);
 9262   predicate(VM_Version::has_CompareBranch());
 9263   ins_cost(BRANCH_COST);
 9264   // TODO: s390 port size(FIXED_SIZE);
 9265   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
 9266   opcode(CIJ_ZOPC);
 9267   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9268   ins_pipe(pipe_class_dummy);
 9269   ins_short_branch(1);
 9270 %}
 9271 
 9272 // INT REG/IMM operands
 9273 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9274   match(If boolnode (CmpI src1 src2));
 9275   effect(USE labl, KILL cr);
 9276   predicate(VM_Version::has_CompareBranch());
 9277   ins_cost(BRANCH_COST);
 9278   // TODO: s390 port size(FIXED_SIZE);
 9279   format %{ "CIJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9280   opcode(CIJ_ZOPC);
 9281   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9282   ins_pipe(pipe_class_dummy);
 9283   ins_short_branch(1);
 9284 %}
 9285 
 9286 // INT REG/IMM operands
 9287 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
 9288   match(If boolnode (CmpU src1 src2));
 9289   effect(USE labl, KILL cr);
 9290   predicate(VM_Version::has_CompareBranch());
 9291   ins_cost(BRANCH_COST);
 9292   // TODO: s390 port size(FIXED_SIZE);
 9293   format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9294   opcode(CLIJ_ZOPC);
 9295   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9296   ins_pipe(pipe_class_dummy);
 9297   ins_short_branch(1);
 9298 %}
 9299 
 9300 // LONG REG/IMM operands
 9301 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
 9302   match(If boolnode (CmpL src1 src2));
 9303   effect(USE labl, KILL cr);
 9304   predicate(VM_Version::has_CompareBranch());
 9305   ins_cost(BRANCH_COST);
 9306   // TODO: s390 port size(FIXED_SIZE);
 9307   format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9308   opcode(CGIJ_ZOPC);
 9309   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9310   ins_pipe(pipe_class_dummy);
 9311   ins_short_branch(1);
 9312 %}
 9313 
 9314 // PTR REG-imm operands
 9315 
 9316 // Separate rules for regular and narrow oops. ADLC can't recognize
 9317 // rules with polymorphic operands to be sisters -> shorten_branches
 9318 // will not shorten.
 9319 
 9320 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
 9321   match(If boolnode (CmpP src1 src2));
 9322   effect(USE labl, KILL cr);
 9323   predicate(VM_Version::has_CompareBranch());
 9324   ins_cost(BRANCH_COST);
 9325   // TODO: s390 port size(FIXED_SIZE);
 9326   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9327   opcode(CLGIJ_ZOPC);
 9328   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9329   ins_pipe(pipe_class_dummy);
 9330   ins_short_branch(1);
 9331 %}
 9332 
 9333 // Compare against zero only, do not mix N and P oops (encode/decode required).
 9334 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
 9335   match(If boolnode (CmpP (DecodeN src1) src2));
 9336   effect(USE labl, KILL cr);
 9337   predicate(VM_Version::has_CompareBranch());
 9338   ins_cost(BRANCH_COST);
 9339   // TODO: s390 port size(FIXED_SIZE);
 9340   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9341   opcode(CLGIJ_ZOPC);
 9342   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9343   ins_pipe(pipe_class_dummy);
 9344   ins_short_branch(1);
 9345 %}
 9346 
 9347 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
 9348   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9349   effect(USE labl, KILL cr);
 9350   predicate(VM_Version::has_CompareBranch());
 9351   ins_cost(BRANCH_COST);
 9352   // TODO: s390 port size(FIXED_SIZE);
 9353   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9354   opcode(CLGIJ_ZOPC);
 9355   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9356   ins_pipe(pipe_class_dummy);
 9357   ins_short_branch(1);
 9358 %}
 9359 
 9360 
 9361 //----------Compare and Branch (far distance)------------------------------
 9362 
 9363 // INT REG operands for loop counter processing
 9364 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9365   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9366   effect(USE labl, KILL cr);
 9367   predicate(VM_Version::has_CompareBranch());
 9368   ins_cost(BRANCH_COST+DEFAULT_COST);
 9369   // TODO: s390 port size(FIXED_SIZE);
 9370   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
 9371   opcode(CR_ZOPC, BRCL_ZOPC);
 9372   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9373   ins_pipe(pipe_class_dummy);
 9374   ins_short_branch(0);
 9375 %}
 9376 
 9377 // INT REG operands
 9378 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9379   match(If boolnode (CmpI src1 src2));
 9380   effect(USE labl, KILL cr);
 9381   predicate(VM_Version::has_CompareBranch());
 9382   ins_cost(BRANCH_COST+DEFAULT_COST);
 9383   // TODO: s390 port size(FIXED_SIZE);
 9384   format %{ "CRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9385   opcode(CR_ZOPC, BRCL_ZOPC);
 9386   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9387   ins_pipe(pipe_class_dummy);
 9388   ins_short_branch(0);
 9389 %}
 9390 
 9391 // INT REG operands
 9392 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9393   match(If boolnode (CmpU src1 src2));
 9394   effect(USE labl, KILL cr);
 9395   predicate(VM_Version::has_CompareBranch());
 9396   ins_cost(BRANCH_COST+DEFAULT_COST);
 9397   // TODO: s390 port size(FIXED_SIZE);
 9398   format %{ "CLRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9399   opcode(CLR_ZOPC, BRCL_ZOPC);
 9400   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9401   ins_pipe(pipe_class_dummy);
 9402   ins_short_branch(0);
 9403 %}
 9404 
 9405 // LONG REG operands
 9406 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
 9407   match(If boolnode (CmpL src1 src2));
 9408   effect(USE labl, KILL cr);
 9409   predicate(VM_Version::has_CompareBranch());
 9410   ins_cost(BRANCH_COST+DEFAULT_COST);
 9411   // TODO: s390 port size(FIXED_SIZE);
 9412   format %{ "CGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9413   opcode(CGR_ZOPC, BRCL_ZOPC);
 9414   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9415   ins_pipe(pipe_class_dummy);
 9416   ins_short_branch(0);
 9417 %}
 9418 
 9419 // PTR REG operands
 9420 
 9421 // Separate rules for regular and narrow oops. ADLC can't recognize
 9422 // rules with polymorphic operands to be sisters -> shorten_branches
 9423 // will not shorten.
 9424 
 9425 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
 9426   match(If boolnode (CmpP src1 src2));
 9427   effect(USE labl, KILL cr);
 9428   predicate(VM_Version::has_CompareBranch());
 9429   ins_cost(BRANCH_COST+DEFAULT_COST);
 9430   // TODO: s390 port size(FIXED_SIZE);
 9431   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9432   opcode(CLGR_ZOPC, BRCL_ZOPC);
 9433   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9434   ins_pipe(pipe_class_dummy);
 9435   ins_short_branch(0);
 9436 %}
 9437 
 9438 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
 9439   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9440   effect(USE labl, KILL cr);
 9441   predicate(VM_Version::has_CompareBranch());
 9442   ins_cost(BRANCH_COST+DEFAULT_COST);
 9443   // TODO: s390 port size(FIXED_SIZE);
 9444   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9445   opcode(CLGR_ZOPC, BRCL_ZOPC);
 9446   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9447   ins_pipe(pipe_class_dummy);
 9448   ins_short_branch(0);
 9449 %}
 9450 
 9451 // INT REG/IMM operands for loop counter processing
 9452 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9453   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9454   effect(USE labl, KILL cr);
 9455   predicate(VM_Version::has_CompareBranch());
 9456   ins_cost(BRANCH_COST+DEFAULT_COST);
 9457   // TODO: s390 port size(FIXED_SIZE);
 9458   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
 9459   opcode(CHI_ZOPC, BRCL_ZOPC);
 9460   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9461   ins_pipe(pipe_class_dummy);
 9462   ins_short_branch(0);
 9463 %}
 9464 
 9465 // INT REG/IMM operands
 9466 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9467   match(If boolnode (CmpI src1 src2));
 9468   effect(USE labl, KILL cr);
 9469   predicate(VM_Version::has_CompareBranch());
 9470   ins_cost(BRANCH_COST+DEFAULT_COST);
 9471   // TODO: s390 port size(FIXED_SIZE);
 9472   format %{ "CIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9473   opcode(CHI_ZOPC, BRCL_ZOPC);
 9474   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9475   ins_pipe(pipe_class_dummy);
 9476   ins_short_branch(0);
 9477 %}
 9478 
 9479 // INT REG/IMM operands
 9480 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
 9481   match(If boolnode (CmpU src1 src2));
 9482   effect(USE labl, KILL cr);
 9483   predicate(VM_Version::has_CompareBranch());
 9484   ins_cost(BRANCH_COST+DEFAULT_COST);
 9485   // TODO: s390 port size(FIXED_SIZE);
 9486   format %{ "CLIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9487   opcode(CLFI_ZOPC, BRCL_ZOPC);
 9488   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9489   ins_pipe(pipe_class_dummy);
 9490   ins_short_branch(0);
 9491 %}
 9492 
 9493 // LONG REG/IMM operands
 9494 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
 9495   match(If boolnode (CmpL src1 src2));
 9496   effect(USE labl, KILL cr);
 9497   predicate(VM_Version::has_CompareBranch());
 9498   ins_cost(BRANCH_COST+DEFAULT_COST);
 9499   // TODO: s390 port size(FIXED_SIZE);
 9500   format %{ "CGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9501   opcode(CGHI_ZOPC, BRCL_ZOPC);
 9502   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9503   ins_pipe(pipe_class_dummy);
 9504   ins_short_branch(0);
 9505 %}
 9506 
 9507 // PTR REG-imm operands
 9508 
 9509 // Separate rules for regular and narrow oops. ADLC can't recognize
 9510 // rules with polymorphic operands to be sisters -> shorten_branches
 9511 // will not shorten.
 9512 
 9513 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
 9514   match(If boolnode (CmpP src1 src2));
 9515   effect(USE labl, KILL cr);
 9516   predicate(VM_Version::has_CompareBranch());
 9517   ins_cost(BRANCH_COST+DEFAULT_COST);
 9518   // TODO: s390 port size(FIXED_SIZE);
 9519   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9520   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9521   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9522   ins_pipe(pipe_class_dummy);
 9523   ins_short_branch(0);
 9524 %}
 9525 
 9526 // Compare against zero only, do not mix N and P oops (encode/decode required).
 9527 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
 9528   match(If boolnode (CmpP (DecodeN src1) src2));
 9529   effect(USE labl, KILL cr);
 9530   predicate(VM_Version::has_CompareBranch());
 9531   ins_cost(BRANCH_COST+DEFAULT_COST);
 9532   // TODO: s390 port size(FIXED_SIZE);
 9533   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9534   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9535   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9536   ins_pipe(pipe_class_dummy);
 9537   ins_short_branch(0);
 9538 %}
 9539 
 9540 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
 9541   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9542   effect(USE labl, KILL cr);
 9543   predicate(VM_Version::has_CompareBranch());
 9544   ins_cost(BRANCH_COST+DEFAULT_COST);
 9545   // TODO: s390 port size(FIXED_SIZE);
 9546   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9547   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9548   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9549   ins_pipe(pipe_class_dummy);
 9550   ins_short_branch(0);
 9551 %}
 9552 
 9553 // ============================================================================
 9554 // Long Compare
 9555 
 9556 // Due to a shortcoming in the ADLC, it mixes up expressions like:
 9557 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
 9558 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
 9559 // are collapsed internally in the ADLC's dfa-gen code. The match for
 9560 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
 9561 // foo match ends up with the wrong leaf. One fix is to not match both
 9562 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
 9563 // both forms beat the trinary form of long-compare and both are very useful
 9564 // on platforms which have few registers.
 9565 
 9566 // Manifest a CmpL3 result in an integer register. Very painful.
 9567 // This is the test to avoid.
 9568 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
 9569   match(Set dst (CmpL3 src1 src2));
 9570   effect(KILL cr);
 9571   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9572   size(24);
 9573   format %{ "CmpL3 $dst,$src1,$src2" %}
 9574   ins_encode %{
 9575     Label done;
 9576     // compare registers
 9577     __ z_cgr($src1$$Register, $src2$$Register);
 9578     // Convert condition code into -1,0,1, where
 9579     // -1 means less
 9580     //  0 means equal
 9581     //  1 means greater.
 9582     if (VM_Version::has_LoadStoreConditional()) {
 9583       Register one       = Z_R0_scratch;
 9584       Register minus_one = Z_R1_scratch;
 9585       __ z_lghi(minus_one, -1);
 9586       __ z_lghi(one, 1);
 9587       __ z_lghi( $dst$$Register, 0);
 9588       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9589       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
 9590     } else {
 9591       __ clear_reg($dst$$Register, true, false);
 9592       __ z_bre(done);
 9593       __ z_lhi($dst$$Register, 1);
 9594       __ z_brh(done);
 9595       __ z_lhi($dst$$Register, -1);
 9596     }
 9597     __ bind(done);
 9598   %}
 9599   ins_pipe(pipe_class_dummy);
 9600 %}
 9601 
 9602 // ============================================================================
 9603 // Safepoint Instruction
 9604 
 9605 instruct safePoint() %{
 9606   match(SafePoint);
 9607   predicate(false);
 9608   // TODO: s390 port size(FIXED_SIZE);
 9609   format %{ "UNIMPLEMENTED Safepoint_ " %}
 9610   ins_encode(enc_unimplemented());
 9611   ins_pipe(pipe_class_dummy);
 9612 %}
 9613 
 9614 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
 9615   match(SafePoint poll);
 9616   effect(USE poll, KILL cr); // R0 is killed, too.
 9617   // TODO: s390 port size(FIXED_SIZE);
 9618   format %{ "TM      #0[,$poll],#111\t # Safepoint: poll for GC" %}
 9619   ins_encode %{
 9620     // Mark the code position where the load from the safepoint
 9621     // polling page was emitted as relocInfo::poll_type.
 9622     __ relocate(relocInfo::poll_type);
 9623     __ load_from_polling_page($poll$$Register);
 9624   %}
 9625   ins_pipe(pipe_class_dummy);
 9626 %}
 9627 
 9628 // ============================================================================
 9629 
 9630 // Call Instructions
 9631 
 9632 // Call Java Static Instruction
 9633 instruct CallStaticJavaDirect_dynTOC(method meth) %{
 9634   match(CallStaticJava);
 9635   effect(USE meth);
 9636   ins_cost(CALL_COST);
 9637   // TODO: s390 port size(VARIABLE_SIZE);
 9638   format %{ "CALL,static dynTOC $meth; ==> " %}
 9639   ins_encode( z_enc_java_static_call(meth) );
 9640   ins_pipe(pipe_class_dummy);
 9641   ins_alignment(2);
 9642 %}
 9643 
 9644 // Call Java Dynamic Instruction
 9645 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
 9646   match(CallDynamicJava);
 9647   effect(USE meth);
 9648   ins_cost(CALL_COST);
 9649   // TODO: s390 port size(VARIABLE_SIZE);
 9650   format %{ "CALL,dynamic dynTOC $meth; ==> " %}
 9651   ins_encode(z_enc_java_dynamic_call(meth));
 9652   ins_pipe(pipe_class_dummy);
 9653   ins_alignment(2);
 9654 %}
 9655 
 9656 // Call Runtime Instruction
 9657 instruct CallRuntimeDirect(method meth) %{
 9658   match(CallRuntime);
 9659   effect(USE meth);
 9660   ins_cost(CALL_COST);
 9661   // TODO: s390 port size(VARIABLE_SIZE);
 9662   ins_num_consts(1);
 9663   ins_alignment(2);
 9664   format %{ "CALL,runtime" %}
 9665   ins_encode( z_enc_java_to_runtime_call(meth) );
 9666   ins_pipe(pipe_class_dummy);
 9667 %}
 9668 
 9669 // Call runtime without safepoint - same as CallRuntime
 9670 instruct CallLeafDirect(method meth) %{
 9671   match(CallLeaf);
 9672   effect(USE meth);
 9673   ins_cost(CALL_COST);
 9674   // TODO: s390 port size(VARIABLE_SIZE);
 9675   ins_num_consts(1);
 9676   ins_alignment(2);
 9677   format %{ "CALL,runtime leaf $meth" %}
 9678   ins_encode( z_enc_java_to_runtime_call(meth) );
 9679   ins_pipe(pipe_class_dummy);
 9680 %}
 9681 
 9682 // Call runtime without safepoint - same as CallLeaf
 9683 instruct CallLeafNoFPDirect(method meth) %{
 9684   match(CallLeafNoFP);
 9685   effect(USE meth);
 9686   ins_cost(CALL_COST);
 9687   // TODO: s390 port size(VARIABLE_SIZE);
 9688   ins_num_consts(1);
 9689   format %{ "CALL,runtime leaf nofp $meth" %}
 9690   ins_encode( z_enc_java_to_runtime_call(meth) );
 9691   ins_pipe(pipe_class_dummy);
 9692   ins_alignment(2);
 9693 %}
 9694 
 9695 // Tail Call; Jump from runtime stub to Java code.
 9696 // Also known as an 'interprocedural jump'.
 9697 // Target of jump will eventually return to caller.
 9698 // TailJump below removes the return address.
 9699 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
 9700   match(TailCall jump_target method_ptr);
 9701   ins_cost(CALL_COST);
 9702   size(2);
 9703   format %{ "Jmp     $jump_target\t # $method_ptr holds method" %}
 9704   ins_encode %{ __ z_br($jump_target$$Register); %}
 9705   ins_pipe(pipe_class_dummy);
 9706 %}
 9707 
 9708 // Return Instruction
 9709 instruct Ret() %{
 9710   match(Return);
 9711   size(2);
 9712   format %{ "BR(Z_R14) // branch to link register" %}
 9713   ins_encode %{ __ z_br(Z_R14); %}
 9714   ins_pipe(pipe_class_dummy);
 9715 %}
 9716 
 9717 // Tail Jump; remove the return address; jump to target.
 9718 // TailCall above leaves the return address around.
 9719 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
 9720 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
 9721 // "restore" before this instruction (in Epilogue), we need to materialize it
 9722 // in %i0.
 9723 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
 9724   match(TailJump jump_target ex_oop);
 9725   ins_cost(CALL_COST);
 9726   size(8);
 9727   format %{ "TailJump $jump_target" %}
 9728   ins_encode %{
 9729     __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
 9730     __ z_br($jump_target$$Register);
 9731   %}
 9732   ins_pipe(pipe_class_dummy);
 9733 %}
 9734 
 9735 // Create exception oop: created by stack-crawling runtime code.
 9736 // Created exception is now available to this handler, and is setup
 9737 // just prior to jumping to this handler. No code emitted.
 9738 instruct CreateException(rarg1RegP ex_oop) %{
 9739   match(Set ex_oop (CreateEx));
 9740   ins_cost(0);
 9741   size(0);
 9742   format %{ "# exception oop; no code emitted" %}
 9743   ins_encode(/*empty*/);
 9744   ins_pipe(pipe_class_dummy);
 9745 %}
 9746 
 9747 // Rethrow exception: The exception oop will come in the first
 9748 // argument position. Then JUMP (not call) to the rethrow stub code.
 9749 instruct RethrowException() %{
 9750   match(Rethrow);
 9751   ins_cost(CALL_COST);
 9752   // TODO: s390 port size(VARIABLE_SIZE);
 9753   format %{ "Jmp    rethrow_stub" %}
 9754   ins_encode %{
 9755     cbuf.set_insts_mark();
 9756     __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
 9757     __ z_br(Z_R1_scratch);
 9758   %}
 9759   ins_pipe(pipe_class_dummy);
 9760 %}
 9761 
 9762 // Die now.
 9763 instruct ShouldNotReachHere() %{
 9764   match(Halt);
 9765   ins_cost(CALL_COST);
 9766   format %{ "ILLTRAP; ShouldNotReachHere" %}
 9767   ins_encode %{
 9768     if (is_reachable()) {
 9769       __ stop(_halt_reason);
 9770     }
 9771   %}
 9772   ins_pipe(pipe_class_dummy);
 9773 %}
 9774 
 9775 // ============================================================================
 9776 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
 9777 // array for an instance of the superklass. Set a hidden internal cache on a
 9778 // hit (cache is checked with exposed code in gen_subtype_check()). Return
 9779 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
 9780 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
 9781                              rarg4RegP scratch1, rarg5RegP scratch2) %{
 9782   match(Set index (PartialSubtypeCheck sub super));
 9783   effect(KILL pcc, KILL scratch1, KILL scratch2);
 9784   ins_cost(10 * DEFAULT_COST);
 9785   // TODO: s390 port size(FIXED_SIZE);
 9786   format %{ "  CALL   PartialSubtypeCheck\n" %}
 9787   ins_encode %{
 9788     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
 9789     __ load_const_optimized(Z_ARG4, stub_address);
 9790     __ z_basr(Z_R14, Z_ARG4);
 9791   %}
 9792   ins_pipe(pipe_class_dummy);
 9793 %}
 9794 
 9795 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
 9796                                      rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
 9797   match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
 9798   effect(KILL scratch1, KILL scratch2, KILL index);
 9799   ins_cost(10 * DEFAULT_COST);
 9800   // TODO: s390 port size(FIXED_SIZE);
 9801   format %{ "CALL   PartialSubtypeCheck_vs_zero\n" %}
 9802   ins_encode %{
 9803     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
 9804     __ load_const_optimized(Z_ARG4, stub_address);
 9805     __ z_basr(Z_R14, Z_ARG4);
 9806   %}
 9807   ins_pipe(pipe_class_dummy);
 9808 %}
 9809 
 9810 // ============================================================================
 9811 // inlined locking and unlocking
 9812 
 9813 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
 9814   match(Set pcc (FastLock oop box));
 9815   effect(TEMP tmp1, TEMP tmp2);
 9816   ins_cost(100);
 9817   // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
 9818   format %{ "FASTLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
 9819   ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register); %}
 9820   ins_pipe(pipe_class_dummy);
 9821 %}
 9822 
 9823 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
 9824   match(Set pcc (FastUnlock oop box));
 9825   effect(TEMP tmp1, TEMP tmp2);
 9826   ins_cost(100);
 9827   // TODO: s390 port size(FIXED_SIZE);
 9828   format %{ "FASTUNLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
 9829   ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register); %}
 9830   ins_pipe(pipe_class_dummy);
 9831 %}
 9832 
 9833 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
 9834   match(Set dummy (ClearArray cnt base));
 9835   effect(KILL cr);
 9836   ins_cost(100);
 9837   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to varying #instructions.
 9838   format %{ "ClearArrayConst $cnt,$base" %}
 9839   ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
 9840   ins_pipe(pipe_class_dummy);
 9841 %}
 9842 
 9843 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
 9844   match(Set dummy (ClearArray cnt base));
 9845   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
 9846   ins_cost(200);
 9847   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to optimized constant loader.
 9848   format %{ "ClearArrayConstBig $cnt,$base" %}
 9849   ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
 9850   ins_pipe(pipe_class_dummy);
 9851 %}
 9852 
 9853 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
 9854   match(Set dummy (ClearArray cnt base));
 9855   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
 9856   ins_cost(300);
 9857   // TODO: s390 port size(FIXED_SIZE);  // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
 9858   format %{ "ClearArrayVar $cnt,$base" %}
 9859   ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
 9860   ins_pipe(pipe_class_dummy);
 9861 %}
 9862 
 9863 // ============================================================================
 9864 // CompactStrings
 9865 
 9866 // String equals
 9867 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9868   match(Set result (StrEquals (Binary str1 str2) cnt));
 9869   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9870   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
 9871   ins_cost(300);
 9872   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
 9873   ins_encode %{
 9874     __ array_equals(false, $str1$$Register, $str2$$Register,
 9875                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
 9876                     $result$$Register, true /* byte */);
 9877   %}
 9878   ins_pipe(pipe_class_dummy);
 9879 %}
 9880 
 9881 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9882   match(Set result (StrEquals (Binary str1 str2) cnt));
 9883   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9884   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
 9885   ins_cost(300);
 9886   format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
 9887   ins_encode %{
 9888     __ array_equals(false, $str1$$Register, $str2$$Register,
 9889                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
 9890                     $result$$Register, false /* byte */);
 9891   %}
 9892   ins_pipe(pipe_class_dummy);
 9893 %}
 9894 
 9895 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
 9896   match(Set result (StrEquals (Binary str1 str2) cnt));
 9897   effect(KILL cr); // R0 is killed, too.
 9898   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
 9899   ins_cost(100);
 9900   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
 9901   ins_encode %{
 9902     const int cnt_imm = $cnt$$constant;
 9903     if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
 9904     __ z_lhi($result$$Register, 1);
 9905     if (cnt_imm) {
 9906       if (VM_Version::has_LoadStoreConditional()) {
 9907         __ z_lhi(Z_R0_scratch, 0);
 9908         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
 9909       } else {
 9910         Label Lskip;
 9911         __ z_bre(Lskip);
 9912         __ clear_reg($result$$Register);
 9913         __ bind(Lskip);
 9914       }
 9915     }
 9916   %}
 9917   ins_pipe(pipe_class_dummy);
 9918 %}
 9919 
 9920 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
 9921   match(Set result (StrEquals (Binary str1 str2) cnt));
 9922   effect(KILL cr); // R0 is killed, too.
 9923   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
 9924   ins_cost(100);
 9925   format %{ "String Equals $str1,$str2,$cnt -> $result" %}
 9926   ins_encode %{
 9927     const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
 9928     if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
 9929     __ z_lhi($result$$Register, 1);
 9930     if (cnt_imm) {
 9931       if (VM_Version::has_LoadStoreConditional()) {
 9932         __ z_lhi(Z_R0_scratch, 0);
 9933         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
 9934       } else {
 9935         Label Lskip;
 9936         __ z_bre(Lskip);
 9937         __ clear_reg($result$$Register);
 9938         __ bind(Lskip);
 9939       }
 9940     }
 9941   %}
 9942   ins_pipe(pipe_class_dummy);
 9943 %}
 9944 
 9945 // Array equals
 9946 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9947   match(Set result (AryEq ary1 ary2));
 9948   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9949   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
 9950   ins_cost(300);
 9951   format %{ "Array Equals $ary1,$ary2 -> $result" %}
 9952   ins_encode %{
 9953     __ array_equals(true, $ary1$$Register, $ary2$$Register,
 9954                     noreg, $oddReg$$Register, $evenReg$$Register,
 9955                     $result$$Register, true /* byte */);
 9956   %}
 9957   ins_pipe(pipe_class_dummy);
 9958 %}
 9959 
 9960 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9961   match(Set result (AryEq ary1 ary2));
 9962   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9963   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
 9964   ins_cost(300);
 9965   format %{ "Array Equals $ary1,$ary2 -> $result" %}
 9966   ins_encode %{
 9967     __ array_equals(true, $ary1$$Register, $ary2$$Register,
 9968                     noreg, $oddReg$$Register, $evenReg$$Register,
 9969                     $result$$Register, false /* byte */);
 9970   %}
 9971   ins_pipe(pipe_class_dummy);
 9972 %}
 9973 
 9974 // String CompareTo
 9975 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9976   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
 9977   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9978   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
 9979   ins_cost(300);
 9980   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
 9981   ins_encode %{
 9982     __ string_compare($str1$$Register, $str2$$Register,
 9983                       $cnt1$$Register, $cnt2$$Register,
 9984                       $oddReg$$Register, $evenReg$$Register,
 9985                       $result$$Register, StrIntrinsicNode::LL);
 9986   %}
 9987   ins_pipe(pipe_class_dummy);
 9988 %}
 9989 
 9990 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9991   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
 9992   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9993   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
 9994   ins_cost(300);
 9995   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
 9996   ins_encode %{
 9997     __ string_compare($str1$$Register, $str2$$Register,
 9998                       $cnt1$$Register, $cnt2$$Register,
 9999                       $oddReg$$Register, $evenReg$$Register,
10000                       $result$$Register, StrIntrinsicNode::UU);
10001   %}
10002   ins_pipe(pipe_class_dummy);
10003 %}
10004 
10005 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10006   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10007   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10008   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10009   ins_cost(300);
10010   format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10011   ins_encode %{
10012     __ string_compare($str1$$Register, $str2$$Register,
10013                       $cnt1$$Register, $cnt2$$Register,
10014                       $oddReg$$Register, $evenReg$$Register,
10015                       $result$$Register, StrIntrinsicNode::LU);
10016   %}
10017   ins_pipe(pipe_class_dummy);
10018 %}
10019 
10020 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10021   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10022   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10023   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10024   ins_cost(300);
10025   format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10026   ins_encode %{
10027     __ string_compare($str2$$Register, $str1$$Register,
10028                       $cnt2$$Register, $cnt1$$Register,
10029                       $oddReg$$Register, $evenReg$$Register,
10030                       $result$$Register, StrIntrinsicNode::UL);
10031   %}
10032   ins_pipe(pipe_class_dummy);
10033 %}
10034 
10035 // String IndexOfChar
10036 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10037   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10038   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10039   predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10040   ins_cost(200);
10041   format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10042   ins_encode %{
10043     __ string_indexof_char($result$$Register,
10044                            $haystack$$Register, $haycnt$$Register,
10045                            $ch$$Register, 0 /* unused, ch is in register */,
10046                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10047   %}
10048   ins_pipe(pipe_class_dummy);
10049 %}
10050 
10051 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10052   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10053   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10054   predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10055   ins_cost(200);
10056   format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10057   ins_encode %{
10058     __ string_indexof_char($result$$Register,
10059                            $haystack$$Register, $haycnt$$Register,
10060                            $ch$$Register, 0 /* unused, ch is in register */,
10061                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10062   %}
10063   ins_pipe(pipe_class_dummy);
10064 %}
10065 
10066 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10067   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10068   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10069   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10070   ins_cost(200);
10071   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10072   ins_encode %{
10073     immPOper *needleOper = (immPOper *)$needle;
10074     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10075     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10076     jchar chr;
10077 #ifdef VM_LITTLE_ENDIAN
10078     Unimplemented();
10079 #else
10080     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10081            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10082 #endif
10083     __ string_indexof_char($result$$Register,
10084                            $haystack$$Register, $haycnt$$Register,
10085                            noreg, chr,
10086                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10087   %}
10088   ins_pipe(pipe_class_dummy);
10089 %}
10090 
10091 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10092   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10093   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10094   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10095   ins_cost(200);
10096   format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10097   ins_encode %{
10098     immPOper *needleOper = (immPOper *)$needle;
10099     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10100     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10101     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10102     __ string_indexof_char($result$$Register,
10103                            $haystack$$Register, $haycnt$$Register,
10104                            noreg, chr,
10105                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10106   %}
10107   ins_pipe(pipe_class_dummy);
10108 %}
10109 
10110 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10111   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10112   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10113   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10114   ins_cost(200);
10115   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10116   ins_encode %{
10117     immPOper *needleOper = (immPOper *)$needle;
10118     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10119     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10120     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10121     __ string_indexof_char($result$$Register,
10122                            $haystack$$Register, $haycnt$$Register,
10123                            noreg, chr,
10124                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10125   %}
10126   ins_pipe(pipe_class_dummy);
10127 %}
10128 
10129 // String IndexOf
10130 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10131   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10132   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10133   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10134   ins_cost(250);
10135   format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10136   ins_encode %{
10137     __ string_indexof($result$$Register,
10138                       $haystack$$Register, $haycnt$$Register,
10139                       $needle$$Register, noreg, $needlecntImm$$constant,
10140                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10141   %}
10142   ins_pipe(pipe_class_dummy);
10143 %}
10144 
10145 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10146   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10147   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10148   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10149   ins_cost(250);
10150   format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10151   ins_encode %{
10152     __ string_indexof($result$$Register,
10153                       $haystack$$Register, $haycnt$$Register,
10154                       $needle$$Register, noreg, $needlecntImm$$constant,
10155                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10156   %}
10157   ins_pipe(pipe_class_dummy);
10158 %}
10159 
10160 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10161   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10162   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10163   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10164   ins_cost(250);
10165   format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10166   ins_encode %{
10167     __ string_indexof($result$$Register,
10168                       $haystack$$Register, $haycnt$$Register,
10169                       $needle$$Register, noreg, $needlecntImm$$constant,
10170                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10171   %}
10172   ins_pipe(pipe_class_dummy);
10173 %}
10174 
10175 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10176   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10177   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10178   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10179   ins_cost(300);
10180   format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10181   ins_encode %{
10182     __ string_indexof($result$$Register,
10183                       $haystack$$Register, $haycnt$$Register,
10184                       $needle$$Register, $needlecnt$$Register, 0,
10185                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10186   %}
10187   ins_pipe(pipe_class_dummy);
10188 %}
10189 
10190 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10191   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10192   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10193   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10194   ins_cost(300);
10195   format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10196   ins_encode %{
10197     __ string_indexof($result$$Register,
10198                       $haystack$$Register, $haycnt$$Register,
10199                       $needle$$Register, $needlecnt$$Register, 0,
10200                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10201   %}
10202   ins_pipe(pipe_class_dummy);
10203 %}
10204 
10205 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10206   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10207   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10208   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10209   ins_cost(300);
10210   format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10211   ins_encode %{
10212     __ string_indexof($result$$Register,
10213                       $haystack$$Register, $haycnt$$Register,
10214                       $needle$$Register, $needlecnt$$Register, 0,
10215                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10216   %}
10217   ins_pipe(pipe_class_dummy);
10218 %}
10219 
10220 // char[] to byte[] compression
10221 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10222   match(Set result (StrCompressedCopy src (Binary dst len)));
10223   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10224   ins_cost(300);
10225   format %{ "String Compress $src->$dst($len) -> $result" %}
10226   ins_encode %{
10227     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10228                        $tmp$$Register, false);
10229   %}
10230   ins_pipe(pipe_class_dummy);
10231 %}
10232 
10233 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10234 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10235 //  match(Set dummy (StrInflatedCopy src (Binary dst len)));
10236 //  effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10237 //  predicate(VM_Version::has_ETF2Enhancements());
10238 //  ins_cost(300);
10239 //  format %{ "String Inflate (trot) $dst,$src($len)" %}
10240 //  ins_encode %{
10241 //    __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10242 //  %}
10243 //  ins_pipe(pipe_class_dummy);
10244 //%}
10245 
10246 // byte[] to char[] inflation
10247 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
10248   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10249   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10250   ins_cost(300);
10251   format %{ "String Inflate $src->$dst($len)" %}
10252   ins_encode %{
10253     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10254   %}
10255   ins_pipe(pipe_class_dummy);
10256 %}
10257 
10258 // byte[] to char[] inflation
10259 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
10260   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10261   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10262   ins_cost(300);
10263   format %{ "String Inflate (constLen) $src->$dst($len)" %}
10264   ins_encode %{
10265     __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant);
10266   %}
10267   ins_pipe(pipe_class_dummy);
10268 %}
10269 
10270 // StringCoding.java intrinsics
10271 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10272   match(Set result (HasNegatives ary1 len));
10273   effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10274   ins_cost(300);
10275   format %{ "has negatives byte[] $ary1($len) -> $result" %}
10276   ins_encode %{
10277     __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10278                      $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10279   %}
10280   ins_pipe(pipe_class_dummy);
10281 %}
10282 
10283 // encode char[] to byte[] in ISO_8859_1
10284 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10285   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10286   match(Set result (EncodeISOArray src (Binary dst len)));
10287   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10288   ins_cost(300);
10289   format %{ "Encode array $src->$dst($len) -> $result" %}
10290   ins_encode %{
10291     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10292                        $tmp$$Register, true);
10293   %}
10294   ins_pipe(pipe_class_dummy);
10295 %}
10296 
10297 
10298 //----------PEEPHOLE RULES-----------------------------------------------------
10299 // These must follow all instruction definitions as they use the names
10300 // defined in the instructions definitions.
10301 //
10302 // peepmatch (root_instr_name [preceeding_instruction]*);
10303 //
10304 // peepconstraint %{
10305 // (instruction_number.operand_name relational_op instruction_number.operand_name
10306 //  [, ...]);
10307 // // instruction numbers are zero-based using left to right order in peepmatch
10308 //
10309 // peepreplace (instr_name([instruction_number.operand_name]*));
10310 // // provide an instruction_number.operand_name for each operand that appears
10311 // // in the replacement instruction's match rule
10312 //
10313 // ---------VM FLAGS---------------------------------------------------------
10314 //
10315 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10316 //
10317 // Each peephole rule is given an identifying number starting with zero and
10318 // increasing by one in the order seen by the parser. An individual peephole
10319 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10320 // on the command-line.
10321 //
10322 // ---------CURRENT LIMITATIONS----------------------------------------------
10323 //
10324 // Only match adjacent instructions in same basic block
10325 // Only equality constraints
10326 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10327 // Only one replacement instruction
10328 //
10329 // ---------EXAMPLE----------------------------------------------------------
10330 //
10331 // // pertinent parts of existing instructions in architecture description
10332 // instruct movI(eRegI dst, eRegI src) %{
10333 //   match(Set dst (CopyI src));
10334 // %}
10335 //
10336 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10337 //   match(Set dst (AddI dst src));
10338 //   effect(KILL cr);
10339 // %}
10340 //
10341 // // Change (inc mov) to lea
10342 // peephole %{
10343 //   // increment preceeded by register-register move
10344 //   peepmatch (incI_eReg movI);
10345 //   // require that the destination register of the increment
10346 //   // match the destination register of the move
10347 //   peepconstraint (0.dst == 1.dst);
10348 //   // construct a replacement instruction that sets
10349 //   // the destination to (move's source register + one)
10350 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10351 // %}
10352 //
10353 // Implementation no longer uses movX instructions since
10354 // machine-independent system no longer uses CopyX nodes.
10355 //
10356 // peephole %{
10357 //   peepmatch (incI_eReg movI);
10358 //   peepconstraint (0.dst == 1.dst);
10359 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10360 // %}
10361 //
10362 // peephole %{
10363 //   peepmatch (decI_eReg movI);
10364 //   peepconstraint (0.dst == 1.dst);
10365 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10366 // %}
10367 //
10368 // peephole %{
10369 //   peepmatch (addI_eReg_imm movI);
10370 //   peepconstraint (0.dst == 1.dst);
10371 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10372 // %}
10373 //
10374 // peephole %{
10375 //   peepmatch (addP_eReg_imm movP);
10376 //   peepconstraint (0.dst == 1.dst);
10377 //   peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10378 // %}
10379 
10380 
10381 //  This peephole rule does not work, probably because ADLC can't handle two effects:
10382 //  Effect 1 is defining 0.op1 and effect 2 is setting CC
10383 // condense a load from memory and subsequent test for zero
10384 // into a single, more efficient ICM instruction.
10385 // peephole %{
10386 //   peepmatch (compI_iReg_imm0 loadI);
10387 //   peepconstraint (1.dst == 0.op1);
10388 //   peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10389 // %}
10390 
10391 // // Change load of spilled value to only a spill
10392 // instruct storeI(memory mem, eRegI src) %{
10393 //   match(Set mem (StoreI mem src));
10394 // %}
10395 //
10396 // instruct loadI(eRegI dst, memory mem) %{
10397 //   match(Set dst (LoadI mem));
10398 // %}
10399 //
10400 peephole %{
10401   peepmatch (loadI storeI);
10402   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10403   peepreplace (storeI(1.mem 1.mem 1.src));
10404 %}
10405 
10406 peephole %{
10407   peepmatch (loadL storeL);
10408   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10409   peepreplace (storeL(1.mem 1.mem 1.src));
10410 %}
10411 
10412 peephole %{
10413   peepmatch (loadP storeP);
10414   peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10415   peepreplace (storeP(1.dst 1.dst 1.src));
10416 %}
10417 
10418 //----------SUPERWORD RULES---------------------------------------------------
10419 
10420 //  Expand rules for special cases
10421 
10422 instruct expand_storeF(stackSlotF mem, regF src) %{
10423   // No match rule, false predicate, for expand only.
10424   effect(DEF mem, USE src);
10425   predicate(false);
10426   ins_cost(MEMORY_REF_COST);
10427   // TODO: s390 port size(FIXED_SIZE);
10428   format %{ "STE      $src,$mem\t # replicate(float2stack)" %}
10429   opcode(STE_ZOPC, STE_ZOPC);
10430   ins_encode(z_form_rt_mem(src, mem));
10431   ins_pipe(pipe_class_dummy);
10432 %}
10433 
10434 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10435   // No match rule, false predicate, for expand only.
10436   effect(DEF dst, USE mem);
10437   predicate(false);
10438   ins_cost(MEMORY_REF_COST);
10439   // TODO: s390 port size(FIXED_SIZE);
10440   format %{ "LLGF     $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10441   opcode(LLGF_ZOPC, LLGF_ZOPC);
10442   ins_encode(z_form_rt_mem(dst, mem));
10443   ins_pipe(pipe_class_dummy);
10444 %}
10445 
10446 // Replicate scalar int to packed int values (8 Bytes)
10447 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10448   // Dummy match rule, false predicate, for expand only.
10449   match(Set dst (ConvI2L src));
10450   predicate(false);
10451   ins_cost(DEFAULT_COST);
10452   // TODO: s390 port size(FIXED_SIZE);
10453   format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10454   ins_encode %{
10455     if ($dst$$Register == $src$$Register) {
10456       __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10457       __ z_ogr($dst$$Register, Z_R0_scratch);
10458     }  else {
10459       __ z_sllg($dst$$Register, $src$$Register, 64-32);
10460       __ z_ogr( $dst$$Register, $src$$Register);
10461     }
10462   %}
10463   ins_pipe(pipe_class_dummy);
10464 %}
10465 
10466 // Replication
10467 
10468 // Exploit rotate_then_insert, if available
10469 // Replicate scalar byte to packed byte values (8 Bytes).
10470 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10471   match(Set dst (ReplicateB src));
10472   effect(KILL cr);
10473   predicate((n->as_Vector()->length() == 8));
10474   format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10475   ins_encode %{
10476     if ($dst$$Register != $src$$Register) {
10477       __ z_lgr($dst$$Register, $src$$Register);
10478     }
10479     __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55,  8, false);
10480     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10481     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10482   %}
10483   ins_pipe(pipe_class_dummy);
10484 %}
10485 
10486 // Replicate scalar byte to packed byte values (8 Bytes).
10487 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10488   match(Set dst (ReplicateB src));
10489   predicate(n->as_Vector()->length() == 8);
10490   ins_should_rematerialize(true);
10491   format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10492   ins_encode %{
10493     int64_t  Isrc8 = $src$$constant & 0x000000ff;
10494     int64_t Isrc16 =  Isrc8 <<  8 |  Isrc8;
10495     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10496     assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10497 
10498     __ z_llilf($dst$$Register, Isrc32);
10499     __ z_iihf($dst$$Register, Isrc32);
10500   %}
10501   ins_pipe(pipe_class_dummy);
10502 %}
10503 
10504 // Replicate scalar byte to packed byte values (8 Bytes).
10505 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10506   match(Set dst (ReplicateB src));
10507   predicate(n->as_Vector()->length() == 8);
10508   ins_should_rematerialize(true);
10509   format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10510   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10511   ins_pipe(pipe_class_dummy);
10512 %}
10513 
10514 // Replicate scalar byte to packed byte values (8 Bytes).
10515 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10516   match(Set dst (ReplicateB src));
10517   predicate(n->as_Vector()->length() == 8);
10518   ins_should_rematerialize(true);
10519   format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10520   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10521   ins_pipe(pipe_class_dummy);
10522 %}
10523 
10524 // Exploit rotate_then_insert, if available
10525 // Replicate scalar short to packed short values (8 Bytes).
10526 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10527   match(Set dst (ReplicateS src));
10528   effect(KILL cr);
10529   predicate((n->as_Vector()->length() == 4));
10530   format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10531   ins_encode %{
10532     if ($dst$$Register != $src$$Register) {
10533       __ z_lgr($dst$$Register, $src$$Register);
10534     }
10535     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10536     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10537   %}
10538   ins_pipe(pipe_class_dummy);
10539 %}
10540 
10541 // Replicate scalar short to packed short values (8 Bytes).
10542 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10543   match(Set dst (ReplicateS src));
10544   predicate(n->as_Vector()->length() == 4);
10545   ins_should_rematerialize(true);
10546   format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10547   ins_encode %{
10548     int64_t Isrc16 = $src$$constant & 0x0000ffff;
10549     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10550     assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10551            ") should be handled by other match rules.", $src$$constant);
10552 
10553     __ z_llilf($dst$$Register, Isrc32);
10554     __ z_iihf($dst$$Register, Isrc32);
10555   %}
10556   ins_pipe(pipe_class_dummy);
10557 %}
10558 
10559 // Replicate scalar short to packed short values (8 Bytes).
10560 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10561   match(Set dst (ReplicateS src));
10562   predicate(n->as_Vector()->length() == 4);
10563   ins_should_rematerialize(true);
10564   format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10565   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10566   ins_pipe(pipe_class_dummy);
10567 %}
10568 
10569 // Replicate scalar short to packed short values (8 Bytes).
10570 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10571   match(Set dst (ReplicateS src));
10572   predicate(n->as_Vector()->length() == 4);
10573   ins_should_rematerialize(true);
10574   format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10575   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10576   ins_pipe(pipe_class_dummy);
10577 %}
10578 
10579 // Exploit rotate_then_insert, if available.
10580 // Replicate scalar int to packed int values (8 Bytes).
10581 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10582   match(Set dst (ReplicateI src));
10583   effect(KILL cr);
10584   predicate((n->as_Vector()->length() == 2));
10585   format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10586   ins_encode %{
10587     if ($dst$$Register != $src$$Register) {
10588       __ z_lgr($dst$$Register, $src$$Register);
10589     }
10590     __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10591   %}
10592   ins_pipe(pipe_class_dummy);
10593 %}
10594 
10595 // Replicate scalar int to packed int values (8 Bytes).
10596 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10597   match(Set dst (ReplicateI src));
10598   predicate(n->as_Vector()->length() == 2);
10599   ins_should_rematerialize(true);
10600   format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10601   ins_encode %{
10602     int64_t Isrc32 = $src$$constant;
10603     assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10604 
10605     __ z_llilf($dst$$Register, Isrc32);
10606     __ z_iihf($dst$$Register, Isrc32);
10607   %}
10608   ins_pipe(pipe_class_dummy);
10609 %}
10610 
10611 // Replicate scalar int to packed int values (8 Bytes).
10612 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10613   match(Set dst (ReplicateI src));
10614   predicate(n->as_Vector()->length() == 2);
10615   ins_should_rematerialize(true);
10616   format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10617   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10618   ins_pipe(pipe_class_dummy);
10619 %}
10620 
10621 // Replicate scalar int to packed int values (8 Bytes).
10622 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10623   match(Set dst (ReplicateI src));
10624   predicate(n->as_Vector()->length() == 2);
10625   ins_should_rematerialize(true);
10626   format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10627   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10628   ins_pipe(pipe_class_dummy);
10629 %}
10630 
10631 //
10632 
10633 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10634   match(Set dst (ReplicateF src));
10635   effect(KILL cr);
10636   predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10637   format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10638   expand %{
10639     stackSlotF tmp;
10640     iRegL      tmp2;
10641     expand_storeF(tmp, src);
10642     expand_LoadLogical_I2L(tmp2, tmp);
10643     expand_Repl2I_reg(dst, tmp2);
10644   %}
10645 %}
10646 
10647 // Replicate scalar float to packed float values in GREG (8 Bytes).
10648 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10649   match(Set dst (ReplicateF src));
10650   effect(KILL cr);
10651   predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10652   format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10653   ins_encode %{
10654     assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10655     __ z_lgdr($dst$$Register, $src$$FloatRegister);
10656 
10657     __ z_srlg(Z_R0_scratch, $dst$$Register, 32);  // Floats are left-justified in 64bit reg.
10658     __ z_iilf($dst$$Register, 0);                 // Save a "result not ready" stall.
10659     __ z_ogr($dst$$Register, Z_R0_scratch);
10660   %}
10661   ins_pipe(pipe_class_dummy);
10662 %}
10663 
10664 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10665 instruct Repl2F_imm(iRegL dst, immF src) %{
10666   match(Set dst (ReplicateF src));
10667   predicate(n->as_Vector()->length() == 2);
10668   ins_should_rematerialize(true);
10669   format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10670   ins_encode %{
10671     union {
10672       int   Isrc32;
10673       float Fsrc32;
10674     };
10675     Fsrc32 = $src$$constant;
10676     __ z_llilf($dst$$Register, Isrc32);
10677     __ z_iihf($dst$$Register, Isrc32);
10678   %}
10679   ins_pipe(pipe_class_dummy);
10680 %}
10681 
10682 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10683 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10684 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10685   match(Set dst (ReplicateF src));
10686   predicate(n->as_Vector()->length() == 2);
10687   ins_should_rematerialize(true);
10688   format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10689   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10690   ins_pipe(pipe_class_dummy);
10691 %}
10692 
10693 // Load/Store vector
10694 
10695 // Store Aligned Packed Byte register to memory (8 Bytes).
10696 instruct storeA8B(memory mem, iRegL src) %{
10697   match(Set mem (StoreVector mem src));
10698   predicate(n->as_StoreVector()->memory_size() == 8);
10699   ins_cost(MEMORY_REF_COST);
10700   // TODO: s390 port size(VARIABLE_SIZE);
10701   format %{ "STG     $src,$mem\t # ST(packed8B)" %}
10702   opcode(STG_ZOPC, STG_ZOPC);
10703   ins_encode(z_form_rt_mem_opt(src, mem));
10704   ins_pipe(pipe_class_dummy);
10705 %}
10706 
10707 instruct loadV8(iRegL dst, memory mem) %{
10708   match(Set dst (LoadVector mem));
10709   predicate(n->as_LoadVector()->memory_size() == 8);
10710   ins_cost(MEMORY_REF_COST);
10711   // TODO: s390 port size(VARIABLE_SIZE);
10712   format %{ "LG      $dst,$mem\t # L(packed8B)" %}
10713   opcode(LG_ZOPC, LG_ZOPC);
10714   ins_encode(z_form_rt_mem_opt(dst, mem));
10715   ins_pipe(pipe_class_dummy);
10716 %}
10717 
10718 // Reinterpret: only one vector size used
10719 instruct reinterpret(iRegL dst) %{
10720   match(Set dst (VectorReinterpret dst));
10721   ins_cost(0);
10722   format %{ "reinterpret $dst" %}
10723   ins_encode( /*empty*/ );
10724   ins_pipe(pipe_class_dummy);
10725 %}
10726 
10727 //----------POPULATION COUNT RULES--------------------------------------------
10728 
10729 // Byte reverse
10730 
10731 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10732   match(Set dst (ReverseBytesI src));
10733   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10734   ins_cost(DEFAULT_COST);
10735   size(4);
10736   format %{ "LRVR    $dst,$src\t # byte reverse int" %}
10737   opcode(LRVR_ZOPC);
10738   ins_encode(z_rreform(dst, src));
10739   ins_pipe(pipe_class_dummy);
10740 %}
10741 
10742 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10743   match(Set dst (ReverseBytesL src));
10744   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10745   ins_cost(DEFAULT_COST);
10746   // TODO: s390 port size(FIXED_SIZE);
10747   format %{ "LRVGR   $dst,$src\t # byte reverse long" %}
10748   opcode(LRVGR_ZOPC);
10749   ins_encode(z_rreform(dst, src));
10750   ins_pipe(pipe_class_dummy);
10751 %}
10752 
10753 // Leading zeroes
10754 
10755 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10756 // returns the bit position of the leftmost 1 in the 64bit source register.
10757 // As the bits are numbered from left to right (0..63), the returned
10758 // position index is equivalent to the number of leading zeroes.
10759 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10760 // returns position 64. That's exactly what we need.
10761 
10762 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10763   match(Set dst (CountLeadingZerosI src));
10764   effect(KILL tmp, KILL cr);
10765   ins_cost(3 * DEFAULT_COST);
10766   size(14);
10767   format %{ "SLLG    $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
10768             "IILH    $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
10769             "FLOGR   $dst,$dst"
10770          %}
10771   ins_encode %{
10772     // Performance experiments indicate that "FLOGR" is using some kind of
10773     // iteration to find the leftmost "1" bit.
10774     //
10775     // The prior implementation zero-extended the 32-bit argument to 64 bit,
10776     // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10777     // We could gain measurable speedup in micro benchmark:
10778     //
10779     //               leading   trailing
10780     //   z10:   int     2.04       1.68
10781     //         long     1.00       1.02
10782     //   z196:  int     0.99       1.23
10783     //         long     1.00       1.11
10784     //
10785     // By shifting the argument into the high-word instead of zero-extending it.
10786     // The add'l branch on condition (taken for a zero argument, very infrequent,
10787     // good prediction) is well compensated for by the savings.
10788     //
10789     // We leave the previous implementation in for some time in the future when
10790     // the "FLOGR" instruction may become less iterative.
10791 
10792     // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10793     __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10794     __ z_iilh($dst$$Register, 0x8000);   // Insert "stop bit" to force result 32 for zero src.
10795     __ z_flogr($dst$$Register, $dst$$Register);
10796   %}
10797   ins_pipe(pipe_class_dummy);
10798 %}
10799 
10800 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10801   match(Set dst (CountLeadingZerosL src));
10802   effect(KILL tmp, KILL cr);
10803   ins_cost(DEFAULT_COST);
10804   size(4);
10805   format %{ "FLOGR   $dst,$src \t # count leading zeros (long)\n\t" %}
10806   ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10807   ins_pipe(pipe_class_dummy);
10808 %}
10809 
10810 // trailing zeroes
10811 
10812 // We transform the trailing zeroes problem to a leading zeroes problem
10813 // such that can use the FLOGR instruction to our advantage.
10814 
10815 // With
10816 //   tmp1 = src - 1
10817 // we flip all trailing zeroes to ones and the rightmost one to zero.
10818 // All other bits remain unchanged.
10819 // With the complement
10820 //   tmp2 = ~src
10821 // we get all ones in the trailing zeroes positions. Thus,
10822 //   tmp3 = tmp1 & tmp2
10823 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10824 // Now we can apply FLOGR and get 64-(trailing zeroes).
10825 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10826   match(Set dst (CountTrailingZerosI src));
10827   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10828   ins_cost(8 * DEFAULT_COST);
10829   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10830   format %{ "LLGFR   $dst,$src  \t # clear upper 32 bits (we are dealing with int)\n\t"
10831             "LCGFR   $tmp,$src  \t # load 2's complement (32->64 bit)\n\t"
10832             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10833             "AGHI    $tmp,-1    \t # tmp2 = -src-1 = ~src\n\t"
10834             "NGR     $dst,$tmp  \t # tmp3 = tmp1&tmp2\n\t"
10835             "FLOGR   $dst,$dst  \t # count trailing zeros (int)\n\t"
10836             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10837             "LCR     $dst,$dst  \t # res = -tmp4"
10838          %}
10839   ins_encode %{
10840     Register Rdst = $dst$$Register;
10841     Register Rsrc = $src$$Register;
10842     // Rtmp only needed for for zero-argument shortcut. With kill effect in
10843     // match rule Rsrc = roddReg would be possible, saving one register.
10844     Register Rtmp = $tmp$$Register;
10845 
10846     assert_different_registers(Rdst, Rsrc, Rtmp);
10847 
10848     // Algorithm:
10849     // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10850     //   All other bits in the result are zero.
10851     // - Find the "leftmost one" bit position in the single-bit result from previous step.
10852     // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10853 
10854     // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10855     Label done;
10856     __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10857     __ z_lcgfr(Rtmp, Rsrc);
10858     __ z_bre(done);                    // Taken very infrequently, good prediction, no BHT entry.
10859 
10860     __ z_nr(Rtmp, Rsrc);               // (src) & (-src) leaves nothing but least significant bit.
10861     __ z_ahi(Rtmp,  -1);               // Subtract one to fill all trailing zero positions with ones.
10862                                        // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10863                                        // into upper half of reg. Not relevant with sllg below.
10864     __ z_sllg(Rdst, Rtmp, 32);         // Shift interesting contents to upper half of register.
10865     __ z_bre(done);                    // Shortcut for argument = 1, result will be 0.
10866                                        // Depends on CC set by ahi above.
10867                                        // Taken very infrequently, good prediction, no BHT entry.
10868                                        // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10869                                        // after SLLG Rdst == 0(64bit)).
10870     __ z_flogr(Rdst, Rdst);            // Kills tmp which is the oddReg for dst.
10871     __ add2reg(Rdst,  -32);            // 32-pos(leftmost1) is #trailing zeros
10872     __ z_lcgfr(Rdst, Rdst);            // Provide 64bit result at no cost.
10873     __ bind(done);
10874   %}
10875   ins_pipe(pipe_class_dummy);
10876 %}
10877 
10878 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10879   match(Set dst (CountTrailingZerosL src));
10880   effect(TEMP_DEF dst, KILL tmp, KILL cr);
10881   ins_cost(8 * DEFAULT_COST);
10882   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10883   format %{ "LCGR    $dst,$src  \t # preserve src\n\t"
10884             "NGR     $dst,$src  \t #\n\t"
10885             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10886             "FLOGR   $dst,$dst  \t # count trailing zeros (long), kill $tmp\n\t"
10887             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10888             "LCR     $dst,$dst  \t #"
10889          %}
10890   ins_encode %{
10891     Register Rdst = $dst$$Register;
10892     Register Rsrc = $src$$Register;
10893     assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10894 
10895     // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10896     __ z_lcgr(Rdst, Rsrc);
10897     __ z_ngr(Rdst, Rsrc);
10898     __ add2reg(Rdst,   -1);
10899     __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10900     __ add2reg(Rdst,  -64);
10901     __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10902   %}
10903   ins_pipe(pipe_class_dummy);
10904 %}
10905 
10906 
10907 // bit count
10908 
10909 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10910   match(Set dst (PopCountI src));
10911   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10912   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10913   ins_cost(DEFAULT_COST);
10914   size(24);
10915   format %{ "POPCNT  $dst,$src\t # pop count int" %}
10916   ins_encode %{
10917     Register Rdst = $dst$$Register;
10918     Register Rsrc = $src$$Register;
10919     Register Rtmp = $tmp$$Register;
10920 
10921     // Prefer compile-time assertion over run-time SIGILL.
10922     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10923     assert_different_registers(Rdst, Rtmp);
10924 
10925     // Version 2: shows 10%(z196) improvement over original.
10926     __ z_popcnt(Rdst, Rsrc);
10927     __ z_srlg(Rtmp, Rdst, 16); // calc  byte4+byte6 and byte5+byte7
10928     __ z_alr(Rdst, Rtmp);      //   into byte6 and byte7
10929     __ z_srlg(Rtmp, Rdst,  8); // calc (byte4+byte6) + (byte5+byte7)
10930     __ z_alr(Rdst, Rtmp);      //   into byte7
10931     __ z_llgcr(Rdst, Rdst);    // zero-extend sum
10932   %}
10933   ins_pipe(pipe_class_dummy);
10934 %}
10935 
10936 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10937   match(Set dst (PopCountL src));
10938   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10939   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10940   ins_cost(DEFAULT_COST);
10941   // TODO: s390 port size(FIXED_SIZE);
10942   format %{ "POPCNT  $dst,$src\t # pop count long" %}
10943   ins_encode %{
10944     Register Rdst = $dst$$Register;
10945     Register Rsrc = $src$$Register;
10946     Register Rtmp = $tmp$$Register;
10947 
10948     // Prefer compile-time assertion over run-time SIGILL.
10949     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10950     assert_different_registers(Rdst, Rtmp);
10951 
10952     // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
10953     __ z_popcnt(Rdst, Rsrc);
10954     __ z_ahhlr(Rdst, Rdst, Rdst);
10955     __ z_sllg(Rtmp, Rdst, 16);
10956     __ z_algr(Rdst, Rtmp);
10957     __ z_sllg(Rtmp, Rdst,  8);
10958     __ z_algr(Rdst, Rtmp);
10959     __ z_srlg(Rdst, Rdst, 56);
10960   %}
10961   ins_pipe(pipe_class_dummy);
10962 %}
10963 
10964 //----------SMARTSPILL RULES---------------------------------------------------
10965 // These must follow all instruction definitions as they use the names
10966 // defined in the instructions definitions.
10967 
10968 // ============================================================================
10969 // TYPE PROFILING RULES