1 //
    2 // Copyright (c) 2017, 2021, Oracle and/or its affiliates. All rights reserved.
    3 // Copyright (c) 2017, 2020 SAP SE. All rights reserved.
    4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
    5 //
    6 // This code is free software; you can redistribute it and/or modify it
    7 // under the terms of the GNU General Public License version 2 only, as
    8 // published by the Free Software Foundation.
    9 //
   10 // This code is distributed in the hope that it will be useful, but WITHOUT
   11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
   12 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
   13 // version 2 for more details (a copy is included in the LICENSE file that
   14 // accompanied this code).
   15 //
   16 // You should have received a copy of the GNU General Public License version
   17 // 2 along with this work; if not, write to the Free Software Foundation,
   18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
   19 //
   20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
   21 // or visit www.oracle.com if you need additional information or have any
   22 // questions.
   23 //
   24 
   25 // z/Architecture Architecture Description File
   26 
   27 // Major contributions by AS, JL, LS.
   28 
   29 //
   30 // Following information is derived from private mail communication
   31 // (Oct. 2011).
   32 //
   33 // General branch target alignment considerations
   34 //
   35 // z/Architecture does not imply a general branch target alignment requirement.
   36 // There are side effects and side considerations, though, which may
   37 // provide some performance benefit. These are:
   38 //  - Align branch target on octoword (32-byte) boundary
   39 //    On more recent models (from z9 on), I-fetch is done on a Octoword
   40 //    (32 bytes at a time) basis. To avoid I-fetching unnecessary
   41 //    instructions, branch targets should be 32-byte aligend. If this
   42 //    exact alingment cannot be achieved, having the branch target in
   43 //    the first doubleword still provides some benefit.
   44 //  - Avoid branch targets at the end of cache lines (> 64 bytes distance).
   45 //    Sequential instruction prefetching after the branch target starts
   46 //    immediately after having fetched the octoword containing the
   47 //    branch target. When I-fetching crosses a cache line, there may be
   48 //    a small stall. The worst case: the branch target (at the end of
   49 //    a cache line) is a L1 I-cache miss and the next line as well.
   50 //    Then, the entire target line must be filled first (to contine at the
   51 //    branch target). Only then can the next sequential line be filled.
   52 //  - Avoid multiple poorly predicted branches in a row.
   53 //
   54 
   55 //----------REGISTER DEFINITION BLOCK------------------------------------------
   56 // This information is used by the matcher and the register allocator to
   57 // describe individual registers and classes of registers within the target
   58 // architecture.
   59 
   60 register %{
   61 
   62 //----------Architecture Description Register Definitions----------------------
   63 // General Registers
   64 // "reg_def" name (register save type, C convention save type,
   65 //                   ideal register type, encoding);
   66 //
   67 // Register Save Types:
   68 //
   69 //   NS  = No-Save:     The register allocator assumes that these registers
   70 //                      can be used without saving upon entry to the method, &
   71 //                      that they do not need to be saved at call sites.
   72 //
   73 //   SOC = Save-On-Call: The register allocator assumes that these registers
   74 //                      can be used without saving upon entry to the method,
   75 //                      but that they must be saved at call sites.
   76 //
   77 //   SOE = Save-On-Entry: The register allocator assumes that these registers
   78 //                      must be saved before using them upon entry to the
   79 //                      method, but they do not need to be saved at call sites.
   80 //
   81 //   AS  = Always-Save: The register allocator assumes that these registers
   82 //                      must be saved before using them upon entry to the
   83 //                      method, & that they must be saved at call sites.
   84 //
   85 // Ideal Register Type is used to determine how to save & restore a
   86 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
   87 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
   88 //
   89 // The encoding number is the actual bit-pattern placed into the opcodes.
   90 
   91 // z/Architecture register definitions, based on the z/Architecture Principles
   92 // of Operation, 5th Edition, September 2005, and z/Linux Elf ABI Supplement,
   93 // 5th Edition, March 2001.
   94 //
   95 // For each 64-bit register we must define two registers: the register
   96 // itself, e.g. Z_R3, and a corresponding virtual other (32-bit-)'half',
   97 // e.g. Z_R3_H, which is needed by the allocator, but is not used
   98 // for stores, loads, etc.
   99 
  100   // Integer/Long Registers
  101   // ----------------------------
  102 
  103   // z/Architecture has 16 64-bit integer registers.
  104 
  105   // types: v = volatile, nv = non-volatile, s = system
  106   reg_def Z_R0   (SOC, SOC, Op_RegI,  0, Z_R0->as_VMReg());   // v   scratch1
  107   reg_def Z_R0_H (SOC, SOC, Op_RegI, 99, Z_R0->as_VMReg()->next());
  108   reg_def Z_R1   (SOC, SOC, Op_RegI,  1, Z_R1->as_VMReg());   // v   scratch2
  109   reg_def Z_R1_H (SOC, SOC, Op_RegI, 99, Z_R1->as_VMReg()->next());
  110   reg_def Z_R2   (SOC, SOC, Op_RegI,  2, Z_R2->as_VMReg());   // v   iarg1 & iret
  111   reg_def Z_R2_H (SOC, SOC, Op_RegI, 99, Z_R2->as_VMReg()->next());
  112   reg_def Z_R3   (SOC, SOC, Op_RegI,  3, Z_R3->as_VMReg());   // v   iarg2
  113   reg_def Z_R3_H (SOC, SOC, Op_RegI, 99, Z_R3->as_VMReg()->next());
  114   reg_def Z_R4   (SOC, SOC, Op_RegI,  4, Z_R4->as_VMReg());   // v   iarg3
  115   reg_def Z_R4_H (SOC, SOC, Op_RegI, 99, Z_R4->as_VMReg()->next());
  116   reg_def Z_R5   (SOC, SOC, Op_RegI,  5, Z_R5->as_VMReg());   // v   iarg4
  117   reg_def Z_R5_H (SOC, SOC, Op_RegI, 99, Z_R5->as_VMReg()->next());
  118   reg_def Z_R6   (SOC, SOE, Op_RegI,  6, Z_R6->as_VMReg());   // v   iarg5
  119   reg_def Z_R6_H (SOC, SOE, Op_RegI, 99, Z_R6->as_VMReg()->next());
  120   reg_def Z_R7   (SOC, SOE, Op_RegI,  7, Z_R7->as_VMReg());
  121   reg_def Z_R7_H (SOC, SOE, Op_RegI, 99, Z_R7->as_VMReg()->next());
  122   reg_def Z_R8   (SOC, SOE, Op_RegI,  8, Z_R8->as_VMReg());
  123   reg_def Z_R8_H (SOC, SOE, Op_RegI, 99, Z_R8->as_VMReg()->next());
  124   reg_def Z_R9   (SOC, SOE, Op_RegI,  9, Z_R9->as_VMReg());
  125   reg_def Z_R9_H (SOC, SOE, Op_RegI, 99, Z_R9->as_VMReg()->next());
  126   reg_def Z_R10  (SOC, SOE, Op_RegI, 10, Z_R10->as_VMReg());
  127   reg_def Z_R10_H(SOC, SOE, Op_RegI, 99, Z_R10->as_VMReg()->next());
  128   reg_def Z_R11  (SOC, SOE, Op_RegI, 11, Z_R11->as_VMReg());
  129   reg_def Z_R11_H(SOC, SOE, Op_RegI, 99, Z_R11->as_VMReg()->next());
  130   reg_def Z_R12  (SOC, SOE, Op_RegI, 12, Z_R12->as_VMReg());
  131   reg_def Z_R12_H(SOC, SOE, Op_RegI, 99, Z_R12->as_VMReg()->next());
  132   reg_def Z_R13  (SOC, SOE, Op_RegI, 13, Z_R13->as_VMReg());
  133   reg_def Z_R13_H(SOC, SOE, Op_RegI, 99, Z_R13->as_VMReg()->next());
  134   reg_def Z_R14  (NS,  NS,  Op_RegI, 14, Z_R14->as_VMReg());   // s  return_pc
  135   reg_def Z_R14_H(NS,  NS,  Op_RegI, 99, Z_R14->as_VMReg()->next());
  136   reg_def Z_R15  (NS,  NS,  Op_RegI, 15, Z_R15->as_VMReg());   // s  SP
  137   reg_def Z_R15_H(NS,  NS,  Op_RegI, 99, Z_R15->as_VMReg()->next());
  138 
  139   // Float/Double Registers
  140 
  141   // The rules of ADL require that double registers be defined in pairs.
  142   // Each pair must be two 32-bit values, but not necessarily a pair of
  143   // single float registers. In each pair, ADLC-assigned register numbers
  144   // must be adjacent, with the lower number even. Finally, when the
  145   // CPU stores such a register pair to memory, the word associated with
  146   // the lower ADLC-assigned number must be stored to the lower address.
  147 
  148   // z/Architecture has 16 64-bit floating-point registers. Each can store a single
  149   // or double precision floating-point value.
  150 
  151   // types: v = volatile, nv = non-volatile, s = system
  152   reg_def Z_F0   (SOC, SOC, Op_RegF,  0, Z_F0->as_VMReg());   // v   farg1 & fret
  153   reg_def Z_F0_H (SOC, SOC, Op_RegF, 99, Z_F0->as_VMReg()->next());
  154   reg_def Z_F1   (SOC, SOC, Op_RegF,  1, Z_F1->as_VMReg());
  155   reg_def Z_F1_H (SOC, SOC, Op_RegF, 99, Z_F1->as_VMReg()->next());
  156   reg_def Z_F2   (SOC, SOC, Op_RegF,  2, Z_F2->as_VMReg());   // v   farg2
  157   reg_def Z_F2_H (SOC, SOC, Op_RegF, 99, Z_F2->as_VMReg()->next());
  158   reg_def Z_F3   (SOC, SOC, Op_RegF,  3, Z_F3->as_VMReg());
  159   reg_def Z_F3_H (SOC, SOC, Op_RegF, 99, Z_F3->as_VMReg()->next());
  160   reg_def Z_F4   (SOC, SOC, Op_RegF,  4, Z_F4->as_VMReg());   // v   farg3
  161   reg_def Z_F4_H (SOC, SOC, Op_RegF, 99, Z_F4->as_VMReg()->next());
  162   reg_def Z_F5   (SOC, SOC, Op_RegF,  5, Z_F5->as_VMReg());
  163   reg_def Z_F5_H (SOC, SOC, Op_RegF, 99, Z_F5->as_VMReg()->next());
  164   reg_def Z_F6   (SOC, SOC, Op_RegF,  6, Z_F6->as_VMReg());
  165   reg_def Z_F6_H (SOC, SOC, Op_RegF, 99, Z_F6->as_VMReg()->next());
  166   reg_def Z_F7   (SOC, SOC, Op_RegF,  7, Z_F7->as_VMReg());
  167   reg_def Z_F7_H (SOC, SOC, Op_RegF, 99, Z_F7->as_VMReg()->next());
  168   reg_def Z_F8   (SOC, SOE, Op_RegF,  8, Z_F8->as_VMReg());
  169   reg_def Z_F8_H (SOC, SOE, Op_RegF, 99, Z_F8->as_VMReg()->next());
  170   reg_def Z_F9   (SOC, SOE, Op_RegF,  9, Z_F9->as_VMReg());
  171   reg_def Z_F9_H (SOC, SOE, Op_RegF, 99, Z_F9->as_VMReg()->next());
  172   reg_def Z_F10  (SOC, SOE, Op_RegF, 10, Z_F10->as_VMReg());
  173   reg_def Z_F10_H(SOC, SOE, Op_RegF, 99, Z_F10->as_VMReg()->next());
  174   reg_def Z_F11  (SOC, SOE, Op_RegF, 11, Z_F11->as_VMReg());
  175   reg_def Z_F11_H(SOC, SOE, Op_RegF, 99, Z_F11->as_VMReg()->next());
  176   reg_def Z_F12  (SOC, SOE, Op_RegF, 12, Z_F12->as_VMReg());
  177   reg_def Z_F12_H(SOC, SOE, Op_RegF, 99, Z_F12->as_VMReg()->next());
  178   reg_def Z_F13  (SOC, SOE, Op_RegF, 13, Z_F13->as_VMReg());
  179   reg_def Z_F13_H(SOC, SOE, Op_RegF, 99, Z_F13->as_VMReg()->next());
  180   reg_def Z_F14  (SOC, SOE, Op_RegF, 14, Z_F14->as_VMReg());
  181   reg_def Z_F14_H(SOC, SOE, Op_RegF, 99, Z_F14->as_VMReg()->next());
  182   reg_def Z_F15  (SOC, SOE, Op_RegF, 15, Z_F15->as_VMReg());
  183   reg_def Z_F15_H(SOC, SOE, Op_RegF, 99, Z_F15->as_VMReg()->next());
  184 
  185 
  186   // Special Registers
  187 
  188   // Condition Codes Flag Registers
  189 
  190   // z/Architecture has the PSW (program status word) that contains
  191   // (among other information) the condition code. We treat this
  192   // part of the PSW as a condition register CR. It consists of 4
  193   // bits. Floating point instructions influence the same condition register CR.
  194 
  195   reg_def Z_CR(SOC, SOC, Op_RegFlags, 0, Z_CR->as_VMReg());   // volatile
  196 
  197 
  198 // Specify priority of register selection within phases of register
  199 // allocation. Highest priority is first. A useful heuristic is to
  200 // give registers a low priority when they are required by machine
  201 // instructions, and choose no-save registers before save-on-call, and
  202 // save-on-call before save-on-entry. Registers which participate in
  203 // fix calling sequences should come last. Registers which are used
  204 // as pairs must fall on an even boundary.
  205 
  206 // It's worth about 1% on SPEC geomean to get this right.
  207 
  208 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration
  209 // in adGlobals_s390.hpp which defines the <register>_num values, e.g.
  210 // Z_R3_num. Therefore, Z_R3_num may not be (and in reality is not)
  211 // the same as Z_R3->encoding()! Furthermore, we cannot make any
  212 // assumptions on ordering, e.g. Z_R3_num may be less than Z_R2_num.
  213 // Additionally, the function
  214 //   static enum RC rc_class(OptoReg::Name reg)
  215 // maps a given <register>_num value to its chunk type (except for flags)
  216 // and its current implementation relies on chunk0 and chunk1 having a
  217 // size of 64 each.
  218 
  219 alloc_class chunk0(
  220   // chunk0 contains *all* 32 integer registers halves.
  221 
  222   // potential SOE regs
  223   Z_R13,Z_R13_H,
  224   Z_R12,Z_R12_H,
  225   Z_R11,Z_R11_H,
  226   Z_R10,Z_R10_H,
  227 
  228   Z_R9,Z_R9_H,
  229   Z_R8,Z_R8_H,
  230   Z_R7,Z_R7_H,
  231 
  232   Z_R1,Z_R1_H,
  233   Z_R0,Z_R0_H,
  234 
  235   // argument registers
  236   Z_R6,Z_R6_H,
  237   Z_R5,Z_R5_H,
  238   Z_R4,Z_R4_H,
  239   Z_R3,Z_R3_H,
  240   Z_R2,Z_R2_H,
  241 
  242   // special registers
  243   Z_R14,Z_R14_H,
  244   Z_R15,Z_R15_H
  245 );
  246 
  247 alloc_class chunk1(
  248   // Chunk1 contains *all* 64 floating-point registers halves.
  249 
  250   Z_F15,Z_F15_H,
  251   Z_F14,Z_F14_H,
  252   Z_F13,Z_F13_H,
  253   Z_F12,Z_F12_H,
  254   Z_F11,Z_F11_H,
  255   Z_F10,Z_F10_H,
  256   Z_F9,Z_F9_H,
  257   Z_F8,Z_F8_H,
  258   // scratch register
  259   Z_F7,Z_F7_H,
  260   Z_F5,Z_F5_H,
  261   Z_F3,Z_F3_H,
  262   Z_F1,Z_F1_H,
  263   // argument registers
  264   Z_F6,Z_F6_H,
  265   Z_F4,Z_F4_H,
  266   Z_F2,Z_F2_H,
  267   Z_F0,Z_F0_H
  268 );
  269 
  270 alloc_class chunk2(
  271   Z_CR
  272 );
  273 
  274 
  275 //-------Architecture Description Register Classes-----------------------
  276 
  277 // Several register classes are automatically defined based upon
  278 // information in this architecture description.
  279 
  280 // 1) reg_class inline_cache_reg           (as defined in frame section)
  281 // 2) reg_class stack_slots(/* one chunk of stack-based "registers" */)
  282 
  283 // Integer Register Classes
  284 reg_class z_int_reg(
  285 /*Z_R0*/              // R0
  286 /*Z_R1*/
  287   Z_R2,
  288   Z_R3,
  289   Z_R4,
  290   Z_R5,
  291   Z_R6,
  292   Z_R7,
  293 /*Z_R8,*/             // Z_thread
  294   Z_R9,
  295   Z_R10,
  296   Z_R11,
  297   Z_R12,
  298   Z_R13
  299 /*Z_R14*/             // return_pc
  300 /*Z_R15*/             // SP
  301 );
  302 
  303 reg_class z_no_odd_int_reg(
  304 /*Z_R0*/              // R0
  305 /*Z_R1*/
  306   Z_R2,
  307   Z_R3,
  308   Z_R4,
  309 /*Z_R5,*/             // odd part of fix register pair
  310   Z_R6,
  311   Z_R7,
  312 /*Z_R8,*/             // Z_thread
  313   Z_R9,
  314   Z_R10,
  315   Z_R11,
  316   Z_R12,
  317   Z_R13
  318 /*Z_R14*/             // return_pc
  319 /*Z_R15*/             // SP
  320 );
  321 
  322 reg_class z_no_arg_int_reg(
  323 /*Z_R0*/              // R0
  324 /*Z_R1*/              // scratch
  325 /*Z_R2*/
  326 /*Z_R3*/
  327 /*Z_R4*/
  328 /*Z_R5*/
  329 /*Z_R6*/
  330   Z_R7,
  331 /*Z_R8*/              // Z_thread
  332   Z_R9,
  333   Z_R10,
  334   Z_R11,
  335   Z_R12,
  336   Z_R13
  337 /*Z_R14*/             // return_pc
  338 /*Z_R15*/             // SP
  339 );
  340 
  341 reg_class z_rarg1_int_reg(Z_R2);
  342 reg_class z_rarg2_int_reg(Z_R3);
  343 reg_class z_rarg3_int_reg(Z_R4);
  344 reg_class z_rarg4_int_reg(Z_R5);
  345 reg_class z_rarg5_int_reg(Z_R6);
  346 
  347 // Pointer Register Classes
  348 
  349 // 64-bit build means 64-bit pointers means hi/lo pairs.
  350 
  351 reg_class z_rarg5_ptrN_reg(Z_R6);
  352 
  353 reg_class z_rarg1_ptr_reg(Z_R2_H,Z_R2);
  354 reg_class z_rarg2_ptr_reg(Z_R3_H,Z_R3);
  355 reg_class z_rarg3_ptr_reg(Z_R4_H,Z_R4);
  356 reg_class z_rarg4_ptr_reg(Z_R5_H,Z_R5);
  357 reg_class z_rarg5_ptr_reg(Z_R6_H,Z_R6);
  358 reg_class z_thread_ptr_reg(Z_R8_H,Z_R8);
  359 
  360 reg_class z_ptr_reg(
  361 /*Z_R0_H,Z_R0*/     // R0
  362 /*Z_R1_H,Z_R1*/
  363   Z_R2_H,Z_R2,
  364   Z_R3_H,Z_R3,
  365   Z_R4_H,Z_R4,
  366   Z_R5_H,Z_R5,
  367   Z_R6_H,Z_R6,
  368   Z_R7_H,Z_R7,
  369 /*Z_R8_H,Z_R8,*/    // Z_thread
  370   Z_R9_H,Z_R9,
  371   Z_R10_H,Z_R10,
  372   Z_R11_H,Z_R11,
  373   Z_R12_H,Z_R12,
  374   Z_R13_H,Z_R13
  375 /*Z_R14_H,Z_R14*/   // return_pc
  376 /*Z_R15_H,Z_R15*/   // SP
  377 );
  378 
  379 reg_class z_lock_ptr_reg(
  380 /*Z_R0_H,Z_R0*/     // R0
  381 /*Z_R1_H,Z_R1*/
  382   Z_R2_H,Z_R2,
  383   Z_R3_H,Z_R3,
  384   Z_R4_H,Z_R4,
  385 /*Z_R5_H,Z_R5,*/
  386 /*Z_R6_H,Z_R6,*/
  387   Z_R7_H,Z_R7,
  388 /*Z_R8_H,Z_R8,*/    // Z_thread
  389   Z_R9_H,Z_R9,
  390   Z_R10_H,Z_R10,
  391   Z_R11_H,Z_R11,
  392   Z_R12_H,Z_R12,
  393   Z_R13_H,Z_R13
  394 /*Z_R14_H,Z_R14*/   // return_pc
  395 /*Z_R15_H,Z_R15*/   // SP
  396 );
  397 
  398 reg_class z_no_arg_ptr_reg(
  399 /*Z_R0_H,Z_R0*/        // R0
  400 /*Z_R1_H,Z_R1*/        // scratch
  401 /*Z_R2_H,Z_R2*/
  402 /*Z_R3_H,Z_R3*/
  403 /*Z_R4_H,Z_R4*/
  404 /*Z_R5_H,Z_R5*/
  405 /*Z_R6_H,Z_R6*/
  406   Z_R7_H, Z_R7,
  407 /*Z_R8_H,Z_R8*/        // Z_thread
  408   Z_R9_H,Z_R9,
  409   Z_R10_H,Z_R10,
  410   Z_R11_H,Z_R11,
  411   Z_R12_H,Z_R12,
  412   Z_R13_H,Z_R13
  413 /*Z_R14_H,Z_R14*/      // return_pc
  414 /*Z_R15_H,Z_R15*/      // SP
  415 );
  416 
  417 // Special class for storeP instructions, which can store SP or RPC to
  418 // TLS. (Note: Do not generalize this to "any_reg". If you add
  419 // another register, such as FP, to this mask, the allocator may try
  420 // to put a temp in it.)
  421 // Register class for memory access base registers,
  422 // This class is a superset of z_ptr_reg including Z_thread.
  423 reg_class z_memory_ptr_reg(
  424 /*Z_R0_H,Z_R0*/     // R0
  425 /*Z_R1_H,Z_R1*/
  426   Z_R2_H,Z_R2,
  427   Z_R3_H,Z_R3,
  428   Z_R4_H,Z_R4,
  429   Z_R5_H,Z_R5,
  430   Z_R6_H,Z_R6,
  431   Z_R7_H,Z_R7,
  432   Z_R8_H,Z_R8,      // Z_thread
  433   Z_R9_H,Z_R9,
  434   Z_R10_H,Z_R10,
  435   Z_R11_H,Z_R11,
  436   Z_R12_H,Z_R12,
  437   Z_R13_H,Z_R13
  438 /*Z_R14_H,Z_R14*/   // return_pc
  439 /*Z_R15_H,Z_R15*/   // SP
  440 );
  441 
  442 // Other special pointer regs.
  443 reg_class z_r1_regP(Z_R1_H,Z_R1);
  444 reg_class z_r9_regP(Z_R9_H,Z_R9);
  445 
  446 
  447 // Long Register Classes
  448 
  449 reg_class z_rarg1_long_reg(Z_R2_H,Z_R2);
  450 reg_class z_rarg2_long_reg(Z_R3_H,Z_R3);
  451 reg_class z_rarg3_long_reg(Z_R4_H,Z_R4);
  452 reg_class z_rarg4_long_reg(Z_R5_H,Z_R5);
  453 reg_class z_rarg5_long_reg(Z_R6_H,Z_R6);
  454 
  455 // Longs in 1 register. Aligned adjacent hi/lo pairs.
  456 reg_class z_long_reg(
  457 /*Z_R0_H,Z_R0*/     // R0
  458 /*Z_R1_H,Z_R1*/
  459   Z_R2_H,Z_R2,
  460   Z_R3_H,Z_R3,
  461   Z_R4_H,Z_R4,
  462   Z_R5_H,Z_R5,
  463   Z_R6_H,Z_R6,
  464   Z_R7_H,Z_R7,
  465 /*Z_R8_H,Z_R8,*/    // Z_thread
  466   Z_R9_H,Z_R9,
  467   Z_R10_H,Z_R10,
  468   Z_R11_H,Z_R11,
  469   Z_R12_H,Z_R12,
  470   Z_R13_H,Z_R13
  471 /*Z_R14_H,Z_R14,*/  // return_pc
  472 /*Z_R15_H,Z_R15*/   // SP
  473 );
  474 
  475 // z_long_reg without even registers
  476 reg_class z_long_odd_reg(
  477 /*Z_R0_H,Z_R0*/     // R0
  478 /*Z_R1_H,Z_R1*/
  479   Z_R3_H,Z_R3,
  480   Z_R5_H,Z_R5,
  481   Z_R7_H,Z_R7,
  482   Z_R9_H,Z_R9,
  483   Z_R11_H,Z_R11,
  484   Z_R13_H,Z_R13
  485 /*Z_R14_H,Z_R14,*/  // return_pc
  486 /*Z_R15_H,Z_R15*/   // SP
  487 );
  488 
  489 // Special Class for Condition Code Flags Register
  490 
  491 reg_class z_condition_reg(
  492   Z_CR
  493 );
  494 
  495 // Scratch register for late profiling. Callee saved.
  496 reg_class z_rscratch2_bits64_reg(Z_R2_H, Z_R2);
  497 
  498 
  499 // Float Register Classes
  500 
  501 reg_class z_flt_reg(
  502   Z_F0,
  503 /*Z_F1,*/ // scratch
  504   Z_F2,
  505   Z_F3,
  506   Z_F4,
  507   Z_F5,
  508   Z_F6,
  509   Z_F7,
  510   Z_F8,
  511   Z_F9,
  512   Z_F10,
  513   Z_F11,
  514   Z_F12,
  515   Z_F13,
  516   Z_F14,
  517   Z_F15
  518 );
  519 reg_class z_rscratch1_flt_reg(Z_F1);
  520 
  521 // Double precision float registers have virtual `high halves' that
  522 // are needed by the allocator.
  523 reg_class z_dbl_reg(
  524   Z_F0,Z_F0_H,
  525 /*Z_F1,Z_F1_H,*/ // scratch
  526   Z_F2,Z_F2_H,
  527   Z_F3,Z_F3_H,
  528   Z_F4,Z_F4_H,
  529   Z_F5,Z_F5_H,
  530   Z_F6,Z_F6_H,
  531   Z_F7,Z_F7_H,
  532   Z_F8,Z_F8_H,
  533   Z_F9,Z_F9_H,
  534   Z_F10,Z_F10_H,
  535   Z_F11,Z_F11_H,
  536   Z_F12,Z_F12_H,
  537   Z_F13,Z_F13_H,
  538   Z_F14,Z_F14_H,
  539   Z_F15,Z_F15_H
  540 );
  541 reg_class z_rscratch1_dbl_reg(Z_F1,Z_F1_H);
  542 
  543 %}
  544 
  545 //----------DEFINITION BLOCK---------------------------------------------------
  546 // Define 'name --> value' mappings to inform the ADLC of an integer valued name.
  547 // Current support includes integer values in the range [0, 0x7FFFFFFF].
  548 // Format:
  549 //        int_def  <name>         (<int_value>, <expression>);
  550 // Generated Code in ad_<arch>.hpp
  551 //        #define  <name>   (<expression>)
  552 //        // value == <int_value>
  553 // Generated code in ad_<arch>.cpp adlc_verification()
  554 //        assert(<name> == <int_value>, "Expect (<expression>) to equal <int_value>");
  555 //
  556 definitions %{
  557   // The default cost (of an ALU instruction).
  558   int_def DEFAULT_COST      (   100,     100);
  559   int_def DEFAULT_COST_LOW  (    80,      80);
  560   int_def DEFAULT_COST_HIGH (   120,     120);
  561   int_def HUGE_COST         (1000000, 1000000);
  562 
  563   // Put an advantage on REG_MEM vs. MEM+REG_REG operations.
  564   int_def ALU_REG_COST      (   100, DEFAULT_COST);
  565   int_def ALU_MEMORY_COST   (   150,          150);
  566 
  567   // Memory refs are twice as expensive as run-of-the-mill.
  568   int_def MEMORY_REF_COST_HI (   220, 2 * DEFAULT_COST+20);
  569   int_def MEMORY_REF_COST    (   200, 2 * DEFAULT_COST);
  570   int_def MEMORY_REF_COST_LO (   180, 2 * DEFAULT_COST-20);
  571 
  572   // Branches are even more expensive.
  573   int_def BRANCH_COST       (   300, DEFAULT_COST * 3);
  574   int_def CALL_COST         (   300, DEFAULT_COST * 3);
  575 %}
  576 
  577 source %{
  578 
  579 #ifdef PRODUCT
  580 #define BLOCK_COMMENT(str)
  581 #define BIND(label)        __ bind(label)
  582 #else
  583 #define BLOCK_COMMENT(str) __ block_comment(str)
  584 #define BIND(label)        __ bind(label); BLOCK_COMMENT(#label ":")
  585 #endif
  586 
  587 #define __ _masm.
  588 
  589 #define Z_DISP_SIZE Immediate::is_uimm12((long)opnd_array(1)->disp(ra_,this,2)) ?  4 : 6
  590 #define Z_DISP3_SIZE 6
  591 
  592 // Tertiary op of a LoadP or StoreP encoding.
  593 #define REGP_OP true
  594 
  595 // Given a register encoding, produce an Integer Register object.
  596 static Register reg_to_register_object(int register_encoding);
  597 
  598 // ****************************************************************************
  599 
  600 // REQUIRED FUNCTIONALITY
  601 
  602 // !!!!! Special hack to get all type of calls to specify the byte offset
  603 //       from the start of the call to the point where the return address
  604 //       will point.
  605 
  606 void PhaseOutput::pd_perform_mach_node_analysis() {
  607 }
  608 
  609 int MachNode::pd_alignment_required() const {
  610   return 1;
  611 }
  612 
  613 int MachNode::compute_padding(int current_offset) const {
  614   return 0;
  615 }
  616 
  617 int MachCallStaticJavaNode::ret_addr_offset() {
  618   if (_method) {
  619     return 8;
  620   } else {
  621     return MacroAssembler::call_far_patchable_ret_addr_offset();
  622   }
  623 }
  624 
  625 int MachCallDynamicJavaNode::ret_addr_offset() {
  626   // Consider size of receiver type profiling (C2 tiers).
  627   int profile_receiver_type_size = 0;
  628 
  629   int vtable_index = this->_vtable_index;
  630   if (vtable_index == -4) {
  631     return 14 + profile_receiver_type_size;
  632   } else {
  633     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
  634     return 36 + profile_receiver_type_size;
  635   }
  636 }
  637 
  638 int MachCallRuntimeNode::ret_addr_offset() {
  639   return 12 + MacroAssembler::call_far_patchable_ret_addr_offset();
  640 }
  641 
  642 int MachCallNativeNode::ret_addr_offset() {
  643   Unimplemented();
  644   return -1;
  645 }
  646 
  647 // Compute padding required for nodes which need alignment
  648 //
  649 // The addresses of the call instructions needs to be 4-byte aligned to
  650 // ensure that they don't span a cache line so that they are atomically patchable.
  651 // The actual calls get emitted at different offsets within the node emitters.
  652 // ins_alignment needs to be set to 2 which means that up to 1 nop may get inserted.
  653 
  654 int CallStaticJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
  655   return (0 - current_offset) & 2;
  656 }
  657 
  658 int CallDynamicJavaDirect_dynTOCNode::compute_padding(int current_offset) const {
  659   return (6 - current_offset) & 2;
  660 }
  661 
  662 int CallRuntimeDirectNode::compute_padding(int current_offset) const {
  663   return (12 - current_offset) & 2;
  664 }
  665 
  666 int CallLeafDirectNode::compute_padding(int current_offset) const {
  667   return (12 - current_offset) & 2;
  668 }
  669 
  670 int CallLeafNoFPDirectNode::compute_padding(int current_offset) const {
  671   return (12 - current_offset) & 2;
  672 }
  673 
  674 void emit_nop(CodeBuffer &cbuf) {
  675   C2_MacroAssembler _masm(&cbuf);
  676   __ z_nop();
  677 }
  678 
  679 // Emit an interrupt that is caught by the debugger (for debugging compiler).
  680 void emit_break(CodeBuffer &cbuf) {
  681   C2_MacroAssembler _masm(&cbuf);
  682   __ z_illtrap();
  683 }
  684 
  685 #if !defined(PRODUCT)
  686 void MachBreakpointNode::format(PhaseRegAlloc *, outputStream *os) const {
  687   os->print("TA");
  688 }
  689 #endif
  690 
  691 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  692   emit_break(cbuf);
  693 }
  694 
  695 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
  696   return MachNode::size(ra_);
  697 }
  698 
  699 static inline void z_emit16(CodeBuffer &cbuf, long value) {
  700   // 32bit instructions may become sign extended.
  701   assert(value >= 0, "unintended sign extension (int->long)");
  702   assert(value < (1L << 16), "instruction too large");
  703   *((unsigned short*)(cbuf.insts_end())) = (unsigned short)value;
  704   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned short));
  705 }
  706 
  707 static inline void z_emit32(CodeBuffer &cbuf, long value) {
  708   // 32bit instructions may become sign extended.
  709   assert(value < (1L << 32), "instruction too large");
  710   *((unsigned int*)(cbuf.insts_end())) = (unsigned int)value;
  711   cbuf.set_insts_end(cbuf.insts_end() + sizeof(unsigned int));
  712 }
  713 
  714 static inline void z_emit48(CodeBuffer &cbuf, long value) {
  715   // 32bit instructions may become sign extended.
  716   assert(value >= 0, "unintended sign extension (int->long)");
  717   assert(value < (1L << 48), "instruction too large");
  718   value = value<<16;
  719   memcpy(cbuf.insts_end(), (unsigned char*)&value, 6);
  720   cbuf.set_insts_end(cbuf.insts_end() + 6);
  721 }
  722 
  723 static inline unsigned int z_emit_inst(CodeBuffer &cbuf, long value) {
  724   if (value < 0) {
  725     // There obviously has been an unintended sign extension (int->long). Revert it.
  726     value = (long)((unsigned long)((unsigned int)value));
  727   }
  728 
  729   if (value < (1L << 16)) { // 2-byte instruction
  730     z_emit16(cbuf, value);
  731     return 2;
  732   }
  733 
  734   if (value < (1L << 32)) { // 4-byte instruction, might be unaligned store
  735     z_emit32(cbuf, value);
  736     return 4;
  737   }
  738 
  739   // 6-byte instruction, probably unaligned store.
  740   z_emit48(cbuf, value);
  741   return 6;
  742 }
  743 
  744 // Check effective address (at runtime) for required alignment.
  745 static inline void z_assert_aligned(CodeBuffer &cbuf, int disp, Register index, Register base, int alignment) {
  746   C2_MacroAssembler _masm(&cbuf);
  747 
  748   __ z_lay(Z_R0, disp, index, base);
  749   __ z_nill(Z_R0, alignment-1);
  750   __ z_brc(Assembler::bcondEqual, +3);
  751   __ z_illtrap();
  752 }
  753 
  754 int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, relocInfo::relocType rtype,
  755                     PhaseRegAlloc* ra_, bool is_native_call = false) {
  756   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
  757   address old_mark = __ inst_mark();
  758   unsigned int start_off = __ offset();
  759 
  760   if (is_native_call) {
  761     ShouldNotReachHere();
  762   }
  763 
  764   if (rtype == relocInfo::runtime_call_w_cp_type) {
  765     assert((__ offset() & 2) == 0, "misaligned emit_call_reloc");
  766     address call_addr = __ call_c_opt((address)entry_point);
  767     if (call_addr == NULL) {
  768       Compile::current()->env()->record_out_of_memory_failure();
  769       return -1;
  770     }
  771   } else {
  772     assert(rtype == relocInfo::none || rtype == relocInfo::opt_virtual_call_type ||
  773            rtype == relocInfo::static_call_type, "unexpected rtype");
  774     __ relocate(rtype);
  775     // BRASL must be prepended with a nop to identify it in the instruction stream.
  776     __ z_nop();
  777     __ z_brasl(Z_R14, (address)entry_point);
  778   }
  779 
  780   unsigned int ret_off = __ offset();
  781 
  782   return (ret_off - start_off);
  783 }
  784 
  785 static int emit_call_reloc(C2_MacroAssembler &_masm, intptr_t entry_point, RelocationHolder const& rspec) {
  786   __ set_inst_mark(); // Used in z_enc_java_static_call() and emit_java_to_interp().
  787   address old_mark = __ inst_mark();
  788   unsigned int start_off = __ offset();
  789 
  790   relocInfo::relocType rtype = rspec.type();
  791   assert(rtype == relocInfo::opt_virtual_call_type || rtype == relocInfo::static_call_type,
  792          "unexpected rtype");
  793 
  794   __ relocate(rspec);
  795   __ z_nop();
  796   __ z_brasl(Z_R14, (address)entry_point);
  797 
  798   unsigned int ret_off = __ offset();
  799 
  800   return (ret_off - start_off);
  801 }
  802 
  803 //=============================================================================
  804 
  805 const RegMask& MachConstantBaseNode::_out_RegMask = _Z_PTR_REG_mask;
  806 int ConstantTable::calculate_table_base_offset() const {
  807   return 0;  // absolute addressing, no offset
  808 }
  809 
  810 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
  811 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
  812   ShouldNotReachHere();
  813 }
  814 
  815 // Even with PC-relative TOC addressing, we still need this node.
  816 // Float loads/stores do not support PC-relative addresses.
  817 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
  818   C2_MacroAssembler _masm(&cbuf);
  819   Register Rtoc = as_Register(ra_->get_encode(this));
  820   __ load_toc(Rtoc);
  821 }
  822 
  823 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
  824   // PCrelative TOC access.
  825   return 6;   // sizeof(LARL)
  826 }
  827 
  828 #if !defined(PRODUCT)
  829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
  830   Register r = as_Register(ra_->get_encode(this));
  831   st->print("LARL    %s,&constant_pool # MachConstantBaseNode", r->name());
  832 }
  833 #endif
  834 
  835 //=============================================================================
  836 
  837 #if !defined(PRODUCT)
  838 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const {
  839   Compile* C = ra_->C;
  840   st->print_cr("--- MachPrologNode ---");
  841   st->print("\t");
  842   for (int i = 0; i < OptoPrologueNops; i++) {
  843     st->print_cr("NOP"); st->print("\t");
  844   }
  845 
  846   if (VerifyThread) {
  847     st->print_cr("Verify_Thread");
  848     st->print("\t");
  849   }
  850 
  851   long framesize = C->output()->frame_size_in_bytes();
  852   int bangsize   = C->output()->bang_size_in_bytes();
  853 
  854   // Calls to C2R adapters often do not accept exceptional returns.
  855   // We require that their callers must bang for them. But be
  856   // careful, because some VM calls (such as call site linkage) can
  857   // use several kilobytes of stack. But the stack safety zone should
  858   // account for that. See bugs 4446381, 4468289, 4497237.
  859   if (C->output()->need_stack_bang(bangsize)) {
  860     st->print_cr("# stack bang"); st->print("\t");
  861   }
  862   st->print_cr("push_frame %d", (int)-framesize);
  863   st->print("\t");
  864 }
  865 #endif
  866 
  867 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  868   Compile* C = ra_->C;
  869   C2_MacroAssembler _masm(&cbuf);
  870 
  871   __ verify_thread();
  872 
  873   size_t framesize = C->output()->frame_size_in_bytes();
  874   size_t bangsize  = C->output()->bang_size_in_bytes();
  875 
  876   assert(framesize % wordSize == 0, "must preserve wordSize alignment");
  877 
  878   if (C->clinit_barrier_on_entry()) {
  879     assert(!C->method()->holder()->is_not_initialized(), "initialization should have been started");
  880 
  881     Label L_skip_barrier;
  882     Register klass = Z_R1_scratch;
  883 
  884     // Notify OOP recorder (don't need the relocation)
  885     AddressLiteral md = __ constant_metadata_address(C->method()->holder()->constant_encoding());
  886     __ load_const_optimized(klass, md.value());
  887     __ clinit_barrier(klass, Z_thread, &L_skip_barrier /*L_fast_path*/);
  888 
  889     __ load_const_optimized(klass, SharedRuntime::get_handle_wrong_method_stub());
  890     __ z_br(klass);
  891 
  892     __ bind(L_skip_barrier);
  893   }
  894 
  895   // Calls to C2R adapters often do not accept exceptional returns.
  896   // We require that their callers must bang for them. But be
  897   // careful, because some VM calls (such as call site linkage) can
  898   // use several kilobytes of stack. But the stack safety zone should
  899   // account for that. See bugs 4446381, 4468289, 4497237.
  900   if (C->output()->need_stack_bang(bangsize)) {
  901     __ generate_stack_overflow_check(bangsize);
  902   }
  903 
  904   assert(Immediate::is_uimm32((long)framesize), "to do: choose suitable types!");
  905   __ save_return_pc();
  906 
  907   // The z/Architecture abi is already accounted for in `framesize' via the
  908   // 'out_preserve_stack_slots' declaration.
  909   __ push_frame((unsigned int)framesize/*includes JIT ABI*/);
  910 
  911   if (C->has_mach_constant_base_node()) {
  912     // NOTE: We set the table base offset here because users might be
  913     // emitted before MachConstantBaseNode.
  914     ConstantTable& constant_table = C->output()->constant_table();
  915     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
  916   }
  917 }
  918 
  919 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
  920   // Variable size. Determine dynamically.
  921   return MachNode::size(ra_);
  922 }
  923 
  924 int MachPrologNode::reloc() const {
  925   // Return number of relocatable values contained in this instruction.
  926   return 1; // One reloc entry for load_const(toc).
  927 }
  928 
  929 //=============================================================================
  930 
  931 #if !defined(PRODUCT)
  932 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
  933   os->print_cr("epilog");
  934   os->print("\t");
  935   if (do_polling() && ra_->C->is_method_compilation()) {
  936     os->print_cr("load_from_polling_page Z_R1_scratch");
  937     os->print("\t");
  938   }
  939 }
  940 #endif
  941 
  942 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
  943   C2_MacroAssembler _masm(&cbuf);
  944   Compile* C = ra_->C;
  945   __ verify_thread();
  946 
  947   // If this does safepoint polling, then do it here.
  948   bool need_polling = do_polling() && C->is_method_compilation();
  949 
  950   // Pop frame, restore return_pc, and all stuff needed by interpreter.
  951   int frame_size_in_bytes = Assembler::align((C->output()->frame_slots() << LogBytesPerInt), frame::alignment_in_bytes);
  952   __ pop_frame_restore_retPC(frame_size_in_bytes);
  953 
  954   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
  955     __ reserved_stack_check(Z_R14);
  956   }
  957 
  958   // Touch the polling page.
  959   if (need_polling) {
  960     __ z_lg(Z_R1_scratch, Address(Z_thread, JavaThread::polling_page_offset()));
  961     // We need to mark the code position where the load from the safepoint
  962     // polling page was emitted as relocInfo::poll_return_type here.
  963     __ relocate(relocInfo::poll_return_type);
  964     __ load_from_polling_page(Z_R1_scratch);
  965   }
  966 }
  967 
  968 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
  969   // Variable size. determine dynamically.
  970   return MachNode::size(ra_);
  971 }
  972 
  973 int MachEpilogNode::reloc() const {
  974   // Return number of relocatable values contained in this instruction.
  975   return 1; // One for load_from_polling_page.
  976 }
  977 
  978 const Pipeline * MachEpilogNode::pipeline() const {
  979   return MachNode::pipeline_class();
  980 }
  981 
  982 //=============================================================================
  983 
  984 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack.
  985 enum RC { rc_bad, rc_int, rc_float, rc_stack };
  986 
  987 static enum RC rc_class(OptoReg::Name reg) {
  988   // Return the register class for the given register. The given register
  989   // reg is a <register>_num value, which is an index into the MachRegisterNumbers
  990   // enumeration in adGlobals_s390.hpp.
  991 
  992   if (reg == OptoReg::Bad) {
  993     return rc_bad;
  994   }
  995 
  996   // We have 32 integer register halves, starting at index 0.
  997   if (reg < 32) {
  998     return rc_int;
  999   }
 1000 
 1001   // We have 32 floating-point register halves, starting at index 32.
 1002   if (reg < 32+32) {
 1003     return rc_float;
 1004   }
 1005 
 1006   // Between float regs & stack are the flags regs.
 1007   assert(reg >= OptoReg::stack0(), "blow up if spilling flags");
 1008   return rc_stack;
 1009 }
 1010 
 1011 // Returns size as obtained from z_emit_instr.
 1012 static unsigned int z_ld_st_helper(CodeBuffer *cbuf, const char *op_str, unsigned long opcode,
 1013                                    int reg, int offset, bool do_print, outputStream *os) {
 1014 
 1015   if (cbuf) {
 1016     if (opcode > (1L<<32)) {
 1017       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 48) |
 1018                          Assembler::simm20(offset) | Assembler::reg(Z_R0, 12, 48) | Assembler::regz(Z_SP, 16, 48));
 1019     } else {
 1020       return z_emit_inst(*cbuf, opcode | Assembler::reg(Matcher::_regEncode[reg], 8, 32) |
 1021                          Assembler::uimm12(offset, 20, 32) | Assembler::reg(Z_R0, 12, 32) | Assembler::regz(Z_SP, 16, 32));
 1022     }
 1023   }
 1024 
 1025 #if !defined(PRODUCT)
 1026   if (do_print) {
 1027     os->print("%s    %s,#%d[,SP]\t # MachCopy spill code",op_str, Matcher::regName[reg], offset);
 1028   }
 1029 #endif
 1030   return (opcode > (1L << 32)) ? 6 : 4;
 1031 }
 1032 
 1033 static unsigned int z_mvc_helper(CodeBuffer *cbuf, int len, int dst_off, int src_off, bool do_print, outputStream *os) {
 1034   if (cbuf) {
 1035     C2_MacroAssembler _masm(cbuf);
 1036     __ z_mvc(dst_off, len-1, Z_SP, src_off, Z_SP);
 1037   }
 1038 
 1039 #if !defined(PRODUCT)
 1040   else if (do_print) {
 1041     os->print("MVC     %d(%d,SP),%d(SP)\t # MachCopy spill code",dst_off, len, src_off);
 1042   }
 1043 #endif
 1044 
 1045   return 6;
 1046 }
 1047 
 1048 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *os) const {
 1049   // Get registers to move.
 1050   OptoReg::Name src_hi = ra_->get_reg_second(in(1));
 1051   OptoReg::Name src_lo = ra_->get_reg_first(in(1));
 1052   OptoReg::Name dst_hi = ra_->get_reg_second(this);
 1053   OptoReg::Name dst_lo = ra_->get_reg_first(this);
 1054 
 1055   enum RC src_hi_rc = rc_class(src_hi);
 1056   enum RC src_lo_rc = rc_class(src_lo);
 1057   enum RC dst_hi_rc = rc_class(dst_hi);
 1058   enum RC dst_lo_rc = rc_class(dst_lo);
 1059 
 1060   assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register");
 1061   bool is64 = (src_hi_rc != rc_bad);
 1062   assert(!is64 ||
 1063          ((src_lo&1) == 0 && src_lo+1 == src_hi && (dst_lo&1) == 0 && dst_lo+1 == dst_hi),
 1064          "expected aligned-adjacent pairs");
 1065 
 1066   // Generate spill code!
 1067 
 1068   if (src_lo == dst_lo && src_hi == dst_hi) {
 1069     return 0;            // Self copy, no move.
 1070   }
 1071 
 1072   int  src_offset = ra_->reg2offset(src_lo);
 1073   int  dst_offset = ra_->reg2offset(dst_lo);
 1074   bool print = !do_size;
 1075   bool src12 = Immediate::is_uimm12(src_offset);
 1076   bool dst12 = Immediate::is_uimm12(dst_offset);
 1077 
 1078   const char   *mnemo = NULL;
 1079   unsigned long opc = 0;
 1080 
 1081   // Memory->Memory Spill. Use Z_R0 to hold the value.
 1082   if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) {
 1083 
 1084     assert(!is64 || (src_hi_rc==rc_stack && dst_hi_rc==rc_stack),
 1085            "expected same type of move for high parts");
 1086 
 1087     if (src12 && dst12) {
 1088       return z_mvc_helper(cbuf, is64 ? 8 : 4, dst_offset, src_offset, print, os);
 1089     }
 1090 
 1091     int r0 = Z_R0_num;
 1092     if (is64) {
 1093       return z_ld_st_helper(cbuf, "LG  ", LG_ZOPC, r0, src_offset, print, os) +
 1094              z_ld_st_helper(cbuf, "STG ", STG_ZOPC, r0, dst_offset, print, os);
 1095     }
 1096 
 1097     return z_ld_st_helper(cbuf, "LY   ", LY_ZOPC, r0, src_offset, print, os) +
 1098            z_ld_st_helper(cbuf, "STY  ", STY_ZOPC, r0, dst_offset, print, os);
 1099   }
 1100 
 1101   // Check for float->int copy. Requires a trip through memory.
 1102   if (src_lo_rc == rc_float && dst_lo_rc == rc_int) {
 1103     Unimplemented();  // Unsafe, do not remove!
 1104   }
 1105 
 1106   // Check for integer reg-reg copy.
 1107   if (src_lo_rc == rc_int && dst_lo_rc == rc_int) {
 1108     if (cbuf) {
 1109       C2_MacroAssembler _masm(cbuf);
 1110       Register Rsrc = as_Register(Matcher::_regEncode[src_lo]);
 1111       Register Rdst = as_Register(Matcher::_regEncode[dst_lo]);
 1112       __ z_lgr(Rdst, Rsrc);
 1113       return 4;
 1114     }
 1115 #if !defined(PRODUCT)
 1116     // else
 1117     if (print) {
 1118       os->print("LGR     %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 1119     }
 1120 #endif
 1121     return 4;
 1122   }
 1123 
 1124   // Check for integer store.
 1125   if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) {
 1126     assert(!is64 || (src_hi_rc==rc_int && dst_hi_rc==rc_stack),
 1127            "expected same type of move for high parts");
 1128 
 1129     if (is64) {
 1130       return z_ld_st_helper(cbuf, "STG ", STG_ZOPC, src_lo, dst_offset, print, os);
 1131     }
 1132 
 1133     // else
 1134     mnemo = dst12 ? "ST  " : "STY ";
 1135     opc = dst12 ? ST_ZOPC : STY_ZOPC;
 1136 
 1137     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1138   }
 1139 
 1140   // Check for integer load
 1141   // Always load cOops zero-extended. That doesn't hurt int loads.
 1142   if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) {
 1143 
 1144     assert(!is64 || (dst_hi_rc==rc_int && src_hi_rc==rc_stack),
 1145            "expected same type of move for high parts");
 1146 
 1147     mnemo = is64 ? "LG  " : "LLGF";
 1148     opc = is64 ? LG_ZOPC : LLGF_ZOPC;
 1149 
 1150     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1151   }
 1152 
 1153   // Check for float reg-reg copy.
 1154   if (src_lo_rc == rc_float && dst_lo_rc == rc_float) {
 1155     if (cbuf) {
 1156       C2_MacroAssembler _masm(cbuf);
 1157       FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]);
 1158       FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]);
 1159       __ z_ldr(Rdst, Rsrc);
 1160       return 2;
 1161     }
 1162 #if !defined(PRODUCT)
 1163     // else
 1164     if (print) {
 1165       os->print("LDR      %s,%s\t # MachCopy spill code", Matcher::regName[dst_lo], Matcher::regName[src_lo]);
 1166     }
 1167 #endif
 1168     return 2;
 1169   }
 1170 
 1171   // Check for float store.
 1172   if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) {
 1173     assert(!is64 || (src_hi_rc==rc_float && dst_hi_rc==rc_stack),
 1174            "expected same type of move for high parts");
 1175 
 1176     if (is64) {
 1177       mnemo = dst12 ? "STD  " : "STDY ";
 1178       opc = dst12 ? STD_ZOPC : STDY_ZOPC;
 1179       return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1180     }
 1181     // else
 1182 
 1183     mnemo = dst12 ? "STE  " : "STEY ";
 1184     opc = dst12 ? STE_ZOPC : STEY_ZOPC;
 1185     return z_ld_st_helper(cbuf, mnemo, opc, src_lo, dst_offset, print, os);
 1186   }
 1187 
 1188   // Check for float load.
 1189   if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) {
 1190     assert(!is64 || (dst_hi_rc==rc_float && src_hi_rc==rc_stack),
 1191            "expected same type of move for high parts");
 1192 
 1193     if (is64) {
 1194       mnemo = src12 ? "LD   " : "LDY  ";
 1195       opc = src12 ? LD_ZOPC : LDY_ZOPC;
 1196       return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1197     }
 1198     // else
 1199 
 1200     mnemo = src12 ? "LE   " : "LEY  ";
 1201     opc = src12 ? LE_ZOPC : LEY_ZOPC;
 1202     return z_ld_st_helper(cbuf, mnemo, opc, dst_lo, src_offset, print, os);
 1203   }
 1204 
 1205   // --------------------------------------------------------------------
 1206   // Check for hi bits still needing moving. Only happens for misaligned
 1207   // arguments to native calls.
 1208   if (src_hi == dst_hi) {
 1209     return 0;               // Self copy, no move.
 1210   }
 1211 
 1212   assert(is64 && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad");
 1213   Unimplemented();  // Unsafe, do not remove!
 1214 
 1215   return 0; // never reached, but make the compiler shut up!
 1216 }
 1217 
 1218 #if !defined(PRODUCT)
 1219 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1220   if (ra_ && ra_->node_regs_max_index() > 0) {
 1221     implementation(NULL, ra_, false, os);
 1222   } else {
 1223     if (req() == 2 && in(1)) {
 1224       os->print("N%d = N%d\n", _idx, in(1)->_idx);
 1225     } else {
 1226       const char *c = "(";
 1227       os->print("N%d = ", _idx);
 1228       for (uint i = 1; i < req(); ++i) {
 1229         os->print("%sN%d", c, in(i)->_idx);
 1230         c = ", ";
 1231       }
 1232       os->print(")");
 1233     }
 1234   }
 1235 }
 1236 #endif
 1237 
 1238 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1239   implementation(&cbuf, ra_, false, NULL);
 1240 }
 1241 
 1242 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
 1243   return implementation(NULL, ra_, true, NULL);
 1244 }
 1245 
 1246 //=============================================================================
 1247 
 1248 #if !defined(PRODUCT)
 1249 void MachNopNode::format(PhaseRegAlloc *, outputStream *os) const {
 1250   os->print("NOP     # pad for alignment (%d nops, %d bytes)", _count, _count*MacroAssembler::nop_size());
 1251 }
 1252 #endif
 1253 
 1254 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ra_) const {
 1255   C2_MacroAssembler _masm(&cbuf);
 1256 
 1257   int rem_space = 0;
 1258   if (!(ra_->C->output()->in_scratch_emit_size())) {
 1259     rem_space = cbuf.insts()->remaining();
 1260     if (rem_space <= _count*2 + 8) {
 1261       tty->print("NopNode: _count = %3.3d, remaining space before = %d", _count, rem_space);
 1262     }
 1263   }
 1264 
 1265   for (int i = 0; i < _count; i++) {
 1266     __ z_nop();
 1267   }
 1268 
 1269   if (!(ra_->C->output()->in_scratch_emit_size())) {
 1270     if (rem_space <= _count*2 + 8) {
 1271       int rem_space2 = cbuf.insts()->remaining();
 1272       tty->print_cr(", after = %d", rem_space2);
 1273     }
 1274   }
 1275 }
 1276 
 1277 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
 1278    return 2 * _count;
 1279 }
 1280 
 1281 #if !defined(PRODUCT)
 1282 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1283   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1284   if (ra_ && ra_->node_regs_max_index() > 0) {
 1285     int reg = ra_->get_reg_first(this);
 1286     os->print("ADDHI  %s, SP, %d\t//box node", Matcher::regName[reg], offset);
 1287   } else {
 1288     os->print("ADDHI  N%d = SP + %d\t// box node", _idx, offset);
 1289   }
 1290 }
 1291 #endif
 1292 
 1293 // Take care of the size function, if you make changes here!
 1294 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1295   C2_MacroAssembler _masm(&cbuf);
 1296 
 1297   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
 1298   int reg = ra_->get_encode(this);
 1299   __ z_lay(as_Register(reg), offset, Z_SP);
 1300 }
 1301 
 1302 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
 1303   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
 1304   return 6;
 1305 }
 1306 
 1307  %} // end source section
 1308 
 1309 //----------SOURCE BLOCK-------------------------------------------------------
 1310 // This is a block of C++ code which provides values, functions, and
 1311 // definitions necessary in the rest of the architecture description
 1312 
 1313 source_hpp %{
 1314 
 1315 // Header information of the source block.
 1316 // Method declarations/definitions which are used outside
 1317 // the ad-scope can conveniently be defined here.
 1318 //
 1319 // To keep related declarations/definitions/uses close together,
 1320 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 1321 
 1322 #include "oops/klass.inline.hpp"
 1323 
 1324 //--------------------------------------------------------------
 1325 // Used for optimization in Compile::Shorten_branches
 1326 //--------------------------------------------------------------
 1327 
 1328 class CallStubImpl {
 1329  public:
 1330 
 1331   // call trampolines
 1332   // Size of call trampoline stub. For add'l comments, see size_java_to_interp().
 1333   static uint size_call_trampoline() {
 1334     return 0; // no call trampolines on this platform
 1335   }
 1336 
 1337   // call trampolines
 1338   // Number of relocations needed by a call trampoline stub.
 1339   static uint reloc_call_trampoline() {
 1340     return 0; // No call trampolines on this platform.
 1341   }
 1342 };
 1343 
 1344 %} // end source_hpp section
 1345 
 1346 source %{
 1347 
 1348 #if !defined(PRODUCT)
 1349 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *os) const {
 1350   os->print_cr("---- MachUEPNode ----");
 1351   os->print_cr("\tTA");
 1352   os->print_cr("\tload_const Z_R1, SharedRuntime::get_ic_miss_stub()");
 1353   os->print_cr("\tBR(Z_R1)");
 1354   os->print_cr("\tTA  # pad with illtraps");
 1355   os->print_cr("\t...");
 1356   os->print_cr("\tTA");
 1357   os->print_cr("\tLTGR    Z_R2, Z_R2");
 1358   os->print_cr("\tBRU     ic_miss");
 1359 }
 1360 #endif
 1361 
 1362 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 1363   C2_MacroAssembler _masm(&cbuf);
 1364   const int ic_miss_offset = 2;
 1365 
 1366   // Inline_cache contains a klass.
 1367   Register ic_klass = as_Register(Matcher::inline_cache_reg_encode());
 1368   // ARG1 is the receiver oop.
 1369   Register R2_receiver = Z_ARG1;
 1370   int      klass_offset = oopDesc::klass_offset_in_bytes();
 1371   AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
 1372   Register R1_ic_miss_stub_addr = Z_R1_scratch;
 1373 
 1374   // Null check of receiver.
 1375   // This is the null check of the receiver that actually should be
 1376   // done in the caller. It's here because in case of implicit null
 1377   // checks we get it for free.
 1378   assert(!MacroAssembler::needs_explicit_null_check(oopDesc::klass_offset_in_bytes()),
 1379          "second word in oop should not require explicit null check.");
 1380   if (!ImplicitNullChecks) {
 1381     Label valid;
 1382     if (VM_Version::has_CompareBranch()) {
 1383       __ z_cgij(R2_receiver, 0, Assembler::bcondNotEqual, valid);
 1384     } else {
 1385       __ z_ltgr(R2_receiver, R2_receiver);
 1386       __ z_bre(valid);
 1387     }
 1388     // The ic_miss_stub will handle the null pointer exception.
 1389     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
 1390     __ z_br(R1_ic_miss_stub_addr);
 1391     __ bind(valid);
 1392   }
 1393 
 1394   // Check whether this method is the proper implementation for the class of
 1395   // the receiver (ic miss check).
 1396   {
 1397     Label valid;
 1398     // Compare cached class against klass from receiver.
 1399     // This also does an implicit null check!
 1400     __ compare_klass_ptr(ic_klass, klass_offset, R2_receiver, false);
 1401     __ z_bre(valid);
 1402     // The inline cache points to the wrong method. Call the
 1403     // ic_miss_stub to find the proper method.
 1404     __ load_const_optimized(R1_ic_miss_stub_addr, icmiss);
 1405     __ z_br(R1_ic_miss_stub_addr);
 1406     __ bind(valid);
 1407   }
 1408 }
 1409 
 1410 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
 1411   // Determine size dynamically.
 1412   return MachNode::size(ra_);
 1413 }
 1414 
 1415 //=============================================================================
 1416 
 1417 %} // interrupt source section
 1418 
 1419 source_hpp %{ // Header information of the source block.
 1420 
 1421 class HandlerImpl {
 1422  public:
 1423 
 1424   static int emit_exception_handler(CodeBuffer &cbuf);
 1425   static int emit_deopt_handler(CodeBuffer& cbuf);
 1426 
 1427   static uint size_exception_handler() {
 1428     return NativeJump::max_instruction_size();
 1429   }
 1430 
 1431   static uint size_deopt_handler() {
 1432     return NativeCall::max_instruction_size();
 1433   }
 1434 };
 1435 
 1436 class Node::PD {
 1437 public:
 1438   enum NodeFlags {
 1439     _last_flag = Node::_last_flag
 1440   };
 1441 };
 1442 
 1443 %} // end source_hpp section
 1444 
 1445 source %{
 1446 
 1447 // This exception handler code snippet is placed after the method's
 1448 // code. It is the return point if an exception occurred. it jumps to
 1449 // the exception blob.
 1450 //
 1451 // If the method gets deoptimized, the method and this code snippet
 1452 // get patched.
 1453 //
 1454 // 1) Trampoline code gets patched into the end of this exception
 1455 //   handler. the trampoline code jumps to the deoptimization blob.
 1456 //
 1457 // 2) The return address in the method's code will get patched such
 1458 //   that it jumps to the trampoline.
 1459 //
 1460 // 3) The handler will get patched such that it does not jump to the
 1461 //   exception blob, but to an entry in the deoptimization blob being
 1462 //   aware of the exception.
 1463 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) {
 1464   Register temp_reg = Z_R1;
 1465   C2_MacroAssembler _masm(&cbuf);
 1466 
 1467   address base = __ start_a_stub(size_exception_handler());
 1468   if (base == NULL) {
 1469     return 0;          // CodeBuffer::expand failed
 1470   }
 1471 
 1472   int offset = __ offset();
 1473   // Use unconditional pc-relative jump with 32-bit range here.
 1474   __ load_const_optimized(temp_reg, (address)OptoRuntime::exception_blob()->content_begin());
 1475   __ z_br(temp_reg);
 1476 
 1477   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
 1478 
 1479   __ end_a_stub();
 1480 
 1481   return offset;
 1482 }
 1483 
 1484 // Emit deopt handler code.
 1485 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
 1486   C2_MacroAssembler _masm(&cbuf);
 1487   address        base = __ start_a_stub(size_deopt_handler());
 1488 
 1489   if (base == NULL) {
 1490     return 0;  // CodeBuffer::expand failed
 1491   }
 1492 
 1493   int offset = __ offset();
 1494 
 1495   // Size_deopt_handler() must be exact on zarch, so for simplicity
 1496   // we do not use load_const_opt here.
 1497   __ load_const(Z_R1, SharedRuntime::deopt_blob()->unpack());
 1498   __ call(Z_R1);
 1499   assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size");
 1500 
 1501   __ end_a_stub();
 1502   return offset;
 1503 }
 1504 
 1505 //=============================================================================
 1506 
 1507 
 1508 // Given a register encoding, produce an Integer Register object.
 1509 static Register reg_to_register_object(int register_encoding) {
 1510   assert(Z_R12->encoding() == Z_R12_enc, "wrong coding");
 1511   return as_Register(register_encoding);
 1512 }
 1513 
 1514 const bool Matcher::match_rule_supported(int opcode) {
 1515   if (!has_match_rule(opcode)) {
 1516     return false; // no match rule present
 1517   }
 1518 
 1519   switch (opcode) {
 1520     case Op_ReverseBytesI:
 1521     case Op_ReverseBytesL:
 1522       return UseByteReverseInstruction;
 1523     case Op_PopCountI:
 1524     case Op_PopCountL:
 1525       // PopCount supported by H/W from z/Architecture G5 (z196) on.
 1526       return (UsePopCountInstruction && VM_Version::has_PopCount());
 1527   }
 1528 
 1529   return true; // Per default match rules are supported.
 1530 }
 1531 
 1532 const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
 1533   if (!match_rule_supported(opcode) || !vector_size_supported(bt, vlen)) {
 1534     return false;
 1535   }
 1536   return true; // Per default match rules are supported.
 1537 }
 1538 
 1539 const bool Matcher::match_rule_supported_vector_masked(int opcode, int vlen, BasicType bt) {
 1540   return false;
 1541 }
 1542 
 1543 const RegMask* Matcher::predicate_reg_mask(void) {
 1544   return NULL;
 1545 }
 1546 
 1547 const TypeVect* Matcher::predicate_reg_type(const Type* elemTy, int length) {
 1548   return NULL;
 1549 }
 1550 
 1551 // Vector calling convention not yet implemented.
 1552 const bool Matcher::supports_vector_calling_convention(void) {
 1553   return false;
 1554 }
 1555 
 1556 OptoRegPair Matcher::vector_return_value(uint ideal_reg) {
 1557   Unimplemented();
 1558   return OptoRegPair(0, 0);
 1559 }
 1560 
 1561 //----------SUPERWORD HELPERS----------------------------------------
 1562 
 1563 // Vector width in bytes.
 1564 const int Matcher::vector_width_in_bytes(BasicType bt) {
 1565   assert(MaxVectorSize == 8, "");
 1566   return 8;
 1567 }
 1568 
 1569 // Vector ideal reg.
 1570 const uint Matcher::vector_ideal_reg(int size) {
 1571   assert(MaxVectorSize == 8 && size == 8, "");
 1572   return Op_RegL;
 1573 }
 1574 
 1575 // Limits on vector size (number of elements) loaded into vector.
 1576 const int Matcher::max_vector_size(const BasicType bt) {
 1577   assert(is_java_primitive(bt), "only primitive type vectors");
 1578   return vector_width_in_bytes(bt)/type2aelembytes(bt);
 1579 }
 1580 
 1581 const int Matcher::min_vector_size(const BasicType bt) {
 1582   return max_vector_size(bt); // Same as max.
 1583 }
 1584 
 1585 const int Matcher::scalable_vector_reg_size(const BasicType bt) {
 1586   return -1;
 1587 }
 1588 
 1589 // RETURNS: whether this branch offset is short enough that a short
 1590 // branch can be used.
 1591 //
 1592 // If the platform does not provide any short branch variants, then
 1593 // this method should return `false' for offset 0.
 1594 //
 1595 // `Compile::Fill_buffer' will decide on basis of this information
 1596 // whether to do the pass `Compile::Shorten_branches' at all.
 1597 //
 1598 // And `Compile::Shorten_branches' will decide on basis of this
 1599 // information whether to replace particular branch sites by short
 1600 // ones.
 1601 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
 1602   // On zarch short branches use a 16 bit signed immediate that
 1603   // is the pc-relative offset in halfword (= 2 bytes) units.
 1604   return Assembler::is_within_range_of_RelAddr16((address)((long)offset), (address)0);
 1605 }
 1606 
 1607 MachOper* Matcher::pd_specialize_generic_vector_operand(MachOper* original_opnd, uint ideal_reg, bool is_temp) {
 1608   ShouldNotReachHere(); // generic vector operands not supported
 1609   return NULL;
 1610 }
 1611 
 1612 bool Matcher::is_reg2reg_move(MachNode* m) {
 1613   ShouldNotReachHere();  // generic vector operands not supported
 1614   return false;
 1615 }
 1616 
 1617 bool Matcher::is_generic_vector(MachOper* opnd)  {
 1618   ShouldNotReachHere();  // generic vector operands not supported
 1619   return false;
 1620 }
 1621 
 1622 // Constants for c2c and c calling conventions.
 1623 
 1624 const MachRegisterNumbers z_iarg_reg[5] = {
 1625   Z_R2_num, Z_R3_num, Z_R4_num, Z_R5_num, Z_R6_num
 1626 };
 1627 
 1628 const MachRegisterNumbers z_farg_reg[4] = {
 1629   Z_F0_num, Z_F2_num, Z_F4_num, Z_F6_num
 1630 };
 1631 
 1632 const int z_num_iarg_registers = sizeof(z_iarg_reg) / sizeof(z_iarg_reg[0]);
 1633 
 1634 const int z_num_farg_registers = sizeof(z_farg_reg) / sizeof(z_farg_reg[0]);
 1635 
 1636 // Return whether or not this register is ever used as an argument. This
 1637 // function is used on startup to build the trampoline stubs in generateOptoStub.
 1638 // Registers not mentioned will be killed by the VM call in the trampoline, and
 1639 // arguments in those registers not be available to the callee.
 1640 bool Matcher::can_be_java_arg(int reg) {
 1641   // We return true for all registers contained in z_iarg_reg[] and
 1642   // z_farg_reg[] and their virtual halves.
 1643   // We must include the virtual halves in order to get STDs and LDs
 1644   // instead of STWs and LWs in the trampoline stubs.
 1645 
 1646   if (reg == Z_R2_num || reg == Z_R2_H_num ||
 1647       reg == Z_R3_num || reg == Z_R3_H_num ||
 1648       reg == Z_R4_num || reg == Z_R4_H_num ||
 1649       reg == Z_R5_num || reg == Z_R5_H_num ||
 1650       reg == Z_R6_num || reg == Z_R6_H_num) {
 1651     return true;
 1652   }
 1653 
 1654   if (reg == Z_F0_num || reg == Z_F0_H_num ||
 1655       reg == Z_F2_num || reg == Z_F2_H_num ||
 1656       reg == Z_F4_num || reg == Z_F4_H_num ||
 1657       reg == Z_F6_num || reg == Z_F6_H_num) {
 1658     return true;
 1659   }
 1660 
 1661   return false;
 1662 }
 1663 
 1664 bool Matcher::is_spillable_arg(int reg) {
 1665   return can_be_java_arg(reg);
 1666 }
 1667 
 1668 uint Matcher::int_pressure_limit()
 1669 {
 1670   // Medium size register set, 6 special purpose regs, 3 SOE regs.
 1671   return (INTPRESSURE == -1) ? 10 : INTPRESSURE;
 1672 }
 1673 
 1674 uint Matcher::float_pressure_limit()
 1675 {
 1676   return (FLOATPRESSURE == -1) ? 15 : FLOATPRESSURE;
 1677 }
 1678 
 1679 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) {
 1680   return false;
 1681 }
 1682 
 1683 // Register for DIVI projection of divmodI
 1684 RegMask Matcher::divI_proj_mask() {
 1685   return _Z_RARG4_INT_REG_mask;
 1686 }
 1687 
 1688 // Register for MODI projection of divmodI
 1689 RegMask Matcher::modI_proj_mask() {
 1690   return _Z_RARG3_INT_REG_mask;
 1691 }
 1692 
 1693 // Register for DIVL projection of divmodL
 1694 RegMask Matcher::divL_proj_mask() {
 1695   return _Z_RARG4_LONG_REG_mask;
 1696 }
 1697 
 1698 // Register for MODL projection of divmodL
 1699 RegMask Matcher::modL_proj_mask() {
 1700   return _Z_RARG3_LONG_REG_mask;
 1701 }
 1702 
 1703 // Copied from sparc.
 1704 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
 1705   return RegMask();
 1706 }
 1707 
 1708 // Should the matcher clone input 'm' of node 'n'?
 1709 bool Matcher::pd_clone_node(Node* n, Node* m, Matcher::MStack& mstack) {
 1710   return false;
 1711 }
 1712 
 1713 // Should the Matcher clone shifts on addressing modes, expecting them
 1714 // to be subsumed into complex addressing expressions or compute them
 1715 // into registers?
 1716 bool Matcher::pd_clone_address_expressions(AddPNode* m, Matcher::MStack& mstack, VectorSet& address_visited) {
 1717   return clone_base_plus_offset_address(m, mstack, address_visited);
 1718 }
 1719 
 1720 %} // source
 1721 
 1722 //----------ENCODING BLOCK-----------------------------------------------------
 1723 // This block specifies the encoding classes used by the compiler to output
 1724 // byte streams. Encoding classes are parameterized macros used by
 1725 // Machine Instruction Nodes in order to generate the bit encoding of the
 1726 // instruction. Operands specify their base encoding interface with the
 1727 // interface keyword. There are currently supported four interfaces,
 1728 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
 1729 // operand to generate a function which returns its register number when
 1730 // queried. CONST_INTER causes an operand to generate a function which
 1731 // returns the value of the constant when queried. MEMORY_INTER causes an
 1732 // operand to generate four functions which return the Base Register, the
 1733 // Index Register, the Scale Value, and the Offset Value of the operand when
 1734 // queried. COND_INTER causes an operand to generate six functions which
 1735 // return the encoding code (ie - encoding bits for the instruction)
 1736 // associated with each basic boolean condition for a conditional instruction.
 1737 //
 1738 // Instructions specify two basic values for encoding. Again, a function
 1739 // is available to check if the constant displacement is an oop. They use the
 1740 // ins_encode keyword to specify their encoding classes (which must be
 1741 // a sequence of enc_class names, and their parameters, specified in
 1742 // the encoding block), and they use the
 1743 // opcode keyword to specify, in order, their primary, secondary, and
 1744 // tertiary opcode. Only the opcode sections which a particular instruction
 1745 // needs for encoding need to be specified.
 1746 encode %{
 1747   enc_class enc_unimplemented %{
 1748     C2_MacroAssembler _masm(&cbuf);
 1749     __ unimplemented("Unimplemented mach node encoding in AD file.", 13);
 1750   %}
 1751 
 1752   enc_class enc_untested %{
 1753 #ifdef ASSERT
 1754     C2_MacroAssembler _masm(&cbuf);
 1755     __ untested("Untested mach node encoding in AD file.");
 1756 #endif
 1757   %}
 1758 
 1759   enc_class z_rrform(iRegI dst, iRegI src) %{
 1760     assert((($primary >> 14) & 0x03) == 0, "Instruction format error");
 1761     assert( ($primary >> 16)         == 0, "Instruction format error");
 1762     z_emit16(cbuf, $primary |
 1763              Assembler::reg($dst$$reg,8,16) |
 1764              Assembler::reg($src$$reg,12,16));
 1765   %}
 1766 
 1767   enc_class z_rreform(iRegI dst1, iRegI src2) %{
 1768     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
 1769     z_emit32(cbuf, $primary |
 1770              Assembler::reg($dst1$$reg,24,32) |
 1771              Assembler::reg($src2$$reg,28,32));
 1772   %}
 1773 
 1774   enc_class z_rrfform(iRegI dst1, iRegI src2, iRegI src3) %{
 1775     assert((($primary >> 30) & 0x03) == 2, "Instruction format error");
 1776     z_emit32(cbuf, $primary |
 1777              Assembler::reg($dst1$$reg,24,32) |
 1778              Assembler::reg($src2$$reg,28,32) |
 1779              Assembler::reg($src3$$reg,16,32));
 1780   %}
 1781 
 1782   enc_class z_riform_signed(iRegI dst, immI16 src) %{
 1783     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
 1784     z_emit32(cbuf, $primary |
 1785              Assembler::reg($dst$$reg,8,32) |
 1786              Assembler::simm16($src$$constant,16,32));
 1787   %}
 1788 
 1789   enc_class z_riform_unsigned(iRegI dst, uimmI16 src) %{
 1790     assert((($primary>>30) & 0x03) == 2, "Instruction format error");
 1791     z_emit32(cbuf, $primary |
 1792              Assembler::reg($dst$$reg,8,32) |
 1793              Assembler::uimm16($src$$constant,16,32));
 1794   %}
 1795 
 1796   enc_class z_rieform_d(iRegI dst1, iRegI src3, immI src2) %{
 1797     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1798     z_emit48(cbuf, $primary |
 1799              Assembler::reg($dst1$$reg,8,48) |
 1800              Assembler::reg($src3$$reg,12,48) |
 1801              Assembler::simm16($src2$$constant,16,48));
 1802   %}
 1803 
 1804   enc_class z_rilform_signed(iRegI dst, immL32 src) %{
 1805     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1806     z_emit48(cbuf, $primary |
 1807              Assembler::reg($dst$$reg,8,48) |
 1808              Assembler::simm32($src$$constant,16,48));
 1809   %}
 1810 
 1811   enc_class z_rilform_unsigned(iRegI dst, uimmL32 src) %{
 1812     assert((($primary>>46) & 0x03) == 3, "Instruction format error");
 1813     z_emit48(cbuf, $primary |
 1814              Assembler::reg($dst$$reg,8,48) |
 1815              Assembler::uimm32($src$$constant,16,48));
 1816   %}
 1817 
 1818   enc_class z_rsyform_const(iRegI dst, iRegI src1, immI src2) %{
 1819     z_emit48(cbuf, $primary |
 1820              Assembler::reg($dst$$reg,8,48) |
 1821              Assembler::reg($src1$$reg,12,48) |
 1822              Assembler::simm20($src2$$constant));
 1823   %}
 1824 
 1825   enc_class z_rsyform_reg_reg(iRegI dst, iRegI src, iRegI shft) %{
 1826     z_emit48(cbuf, $primary |
 1827              Assembler::reg($dst$$reg,8,48) |
 1828              Assembler::reg($src$$reg,12,48) |
 1829              Assembler::reg($shft$$reg,16,48) |
 1830              Assembler::simm20(0));
 1831   %}
 1832 
 1833   enc_class z_rxform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
 1834     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
 1835     z_emit32(cbuf, $primary |
 1836              Assembler::reg($dst$$reg,8,32) |
 1837              Assembler::reg($src1$$reg,12,32) |
 1838              Assembler::reg($src2$$reg,16,32) |
 1839              Assembler::uimm12($con$$constant,20,32));
 1840   %}
 1841 
 1842   enc_class z_rxform_imm_reg(iRegL dst, immL con, iRegL src) %{
 1843     assert((($primary>>30) & 0x03) == 1, "Instruction format error");
 1844     z_emit32(cbuf, $primary |
 1845              Assembler::reg($dst$$reg,8,32) |
 1846              Assembler::reg($src$$reg,16,32) |
 1847              Assembler::uimm12($con$$constant,20,32));
 1848   %}
 1849 
 1850   enc_class z_rxyform_imm_reg_reg(iRegL dst, immL con, iRegL src1, iRegL src2) %{
 1851     z_emit48(cbuf, $primary |
 1852              Assembler::reg($dst$$reg,8,48) |
 1853              Assembler::reg($src1$$reg,12,48) |
 1854              Assembler::reg($src2$$reg,16,48) |
 1855              Assembler::simm20($con$$constant));
 1856   %}
 1857 
 1858   enc_class z_rxyform_imm_reg(iRegL dst, immL con, iRegL src) %{
 1859     z_emit48(cbuf, $primary |
 1860              Assembler::reg($dst$$reg,8,48) |
 1861              Assembler::reg($src$$reg,16,48) |
 1862              Assembler::simm20($con$$constant));
 1863   %}
 1864 
 1865   // Direct memory arithmetic.
 1866   enc_class z_siyform(memoryRSY mem, immI8 src) %{
 1867     int      disp = $mem$$disp;
 1868     Register base = reg_to_register_object($mem$$base);
 1869     int      con  = $src$$constant;
 1870 
 1871     assert(VM_Version::has_MemWithImmALUOps(), "unsupported CPU");
 1872     z_emit_inst(cbuf, $primary |
 1873                 Assembler::regz(base,16,48) |
 1874                 Assembler::simm20(disp) |
 1875                 Assembler::simm8(con,8,48));
 1876   %}
 1877 
 1878   enc_class z_silform(memoryRS mem, immI16 src) %{
 1879     z_emit_inst(cbuf, $primary |
 1880                 Assembler::regz(reg_to_register_object($mem$$base),16,48) |
 1881                 Assembler::uimm12($mem$$disp,20,48) |
 1882                 Assembler::simm16($src$$constant,32,48));
 1883   %}
 1884 
 1885   // Encoder for FP ALU reg/mem instructions (support only short displacements).
 1886   enc_class z_form_rt_memFP(RegF dst, memoryRX mem) %{
 1887     Register Ridx = $mem$$index$$Register;
 1888     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1889     if ($primary > (1L << 32)) {
 1890       z_emit_inst(cbuf, $primary |
 1891                   Assembler::reg($dst$$reg, 8, 48) |
 1892                   Assembler::uimm12($mem$$disp, 20, 48) |
 1893                   Assembler::reg(Ridx, 12, 48) |
 1894                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1895     } else {
 1896       z_emit_inst(cbuf, $primary |
 1897                   Assembler::reg($dst$$reg, 8, 32) |
 1898                   Assembler::uimm12($mem$$disp, 20, 32) |
 1899                   Assembler::reg(Ridx, 12, 32) |
 1900                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
 1901     }
 1902   %}
 1903 
 1904   enc_class z_form_rt_mem(iRegI dst, memory mem) %{
 1905     Register Ridx = $mem$$index$$Register;
 1906     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1907     if ($primary > (1L<<32)) {
 1908       z_emit_inst(cbuf, $primary |
 1909                   Assembler::reg($dst$$reg, 8, 48) |
 1910                   Assembler::simm20($mem$$disp) |
 1911                   Assembler::reg(Ridx, 12, 48) |
 1912                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1913     } else {
 1914       z_emit_inst(cbuf, $primary |
 1915                   Assembler::reg($dst$$reg, 8, 32) |
 1916                   Assembler::uimm12($mem$$disp, 20, 32) |
 1917                   Assembler::reg(Ridx, 12, 32) |
 1918                   Assembler::regz(reg_to_register_object($mem$$base), 16, 32));
 1919     }
 1920   %}
 1921 
 1922   enc_class z_form_rt_mem_opt(iRegI dst, memory mem) %{
 1923     int isize = $secondary > 1L << 32 ? 48 : 32;
 1924     Register Ridx = $mem$$index$$Register;
 1925     if (Ridx == noreg) { Ridx = Z_R0; } // Index is 0.
 1926 
 1927     if (Displacement::is_shortDisp((long)$mem$$disp)) {
 1928       z_emit_inst(cbuf, $secondary |
 1929                   Assembler::reg($dst$$reg, 8, isize) |
 1930                   Assembler::uimm12($mem$$disp, 20, isize) |
 1931                   Assembler::reg(Ridx, 12, isize) |
 1932                   Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
 1933     } else if (Displacement::is_validDisp((long)$mem$$disp)) {
 1934       z_emit_inst(cbuf, $primary |
 1935                   Assembler::reg($dst$$reg, 8, 48) |
 1936                   Assembler::simm20($mem$$disp) |
 1937                   Assembler::reg(Ridx, 12, 48) |
 1938                   Assembler::regz(reg_to_register_object($mem$$base), 16, 48));
 1939     } else {
 1940         C2_MacroAssembler _masm(&cbuf);
 1941         __ load_const_optimized(Z_R1_scratch, $mem$$disp);
 1942         if (Ridx != Z_R0) { __ z_agr(Z_R1_scratch, Ridx); }
 1943         z_emit_inst(cbuf, $secondary |
 1944                     Assembler::reg($dst$$reg, 8, isize) |
 1945                     Assembler::uimm12(0, 20, isize) |
 1946                     Assembler::reg(Z_R1_scratch, 12, isize) |
 1947                     Assembler::regz(reg_to_register_object($mem$$base), 16, isize));
 1948     }
 1949   %}
 1950 
 1951   enc_class z_enc_brul(Label lbl) %{
 1952     C2_MacroAssembler _masm(&cbuf);
 1953     Label* p = $lbl$$label;
 1954 
 1955     // 'p' is `NULL' when this encoding class is used only to
 1956     // determine the size of the encoded instruction.
 1957     // Use a bound dummy label in that case.
 1958     Label d;
 1959     __ bind(d);
 1960     Label& l = (NULL == p) ? d : *(p);
 1961     __ z_brul(l);
 1962   %}
 1963 
 1964   enc_class z_enc_bru(Label lbl) %{
 1965     C2_MacroAssembler _masm(&cbuf);
 1966     Label* p = $lbl$$label;
 1967 
 1968     // 'p' is `NULL' when this encoding class is used only to
 1969     // determine the size of the encoded instruction.
 1970     // Use a bound dummy label in that case.
 1971     Label d;
 1972     __ bind(d);
 1973     Label& l = (NULL == p) ? d : *(p);
 1974     __ z_bru(l);
 1975   %}
 1976 
 1977   enc_class z_enc_branch_con_far(cmpOp cmp, Label lbl) %{
 1978     C2_MacroAssembler _masm(&cbuf);
 1979     Label* p = $lbl$$label;
 1980 
 1981     // 'p' is `NULL' when this encoding class is used only to
 1982     // determine the size of the encoded instruction.
 1983     // Use a bound dummy label in that case.
 1984     Label d;
 1985     __ bind(d);
 1986     Label& l = (NULL == p) ? d : *(p);
 1987     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 1988   %}
 1989 
 1990   enc_class z_enc_branch_con_short(cmpOp cmp, Label lbl) %{
 1991     C2_MacroAssembler _masm(&cbuf);
 1992     Label* p = $lbl$$label;
 1993 
 1994     // 'p' is `NULL' when this encoding class is used only to
 1995     // determine the size of the encoded instruction.
 1996     // Use a bound dummy label in that case.
 1997     Label d;
 1998     __ bind(d);
 1999     Label& l = (NULL == p) ? d : *(p);
 2000     __ z_brc((Assembler::branch_condition)$cmp$$cmpcode, l);
 2001   %}
 2002 
 2003   enc_class z_enc_cmpb_regreg(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
 2004     C2_MacroAssembler _masm(&cbuf);
 2005     Label* p = $lbl$$label;
 2006 
 2007     // 'p' is `NULL' when this encoding class is used only to
 2008     // determine the size of the encoded instruction.
 2009     // Use a bound dummy label in that case.
 2010     Label d;
 2011     __ bind(d);
 2012     Label& l = (NULL == p) ? d : *(p);
 2013     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2014     unsigned long instr = $primary;
 2015     if (instr == CRJ_ZOPC) {
 2016       __ z_crj($src1$$Register, $src2$$Register, cc, l);
 2017     } else if (instr == CLRJ_ZOPC) {
 2018       __ z_clrj($src1$$Register, $src2$$Register, cc, l);
 2019     } else if (instr == CGRJ_ZOPC) {
 2020       __ z_cgrj($src1$$Register, $src2$$Register, cc, l);
 2021     } else {
 2022       guarantee(instr == CLGRJ_ZOPC, "opcode not implemented");
 2023       __ z_clgrj($src1$$Register, $src2$$Register, cc, l);
 2024     }
 2025   %}
 2026 
 2027   enc_class z_enc_cmpb_regregFar(iRegI src1, iRegI src2, Label lbl, cmpOpT cmp) %{
 2028     C2_MacroAssembler _masm(&cbuf);
 2029     Label* p = $lbl$$label;
 2030 
 2031     // 'p' is `NULL' when this encoding class is used only to
 2032     // determine the size of the encoded instruction.
 2033     // Use a bound dummy label in that case.
 2034     Label d;
 2035     __ bind(d);
 2036     Label& l = (NULL == p) ? d : *(p);
 2037 
 2038     unsigned long instr = $primary;
 2039     if (instr == CR_ZOPC) {
 2040       __ z_cr($src1$$Register, $src2$$Register);
 2041     } else if (instr == CLR_ZOPC) {
 2042       __ z_clr($src1$$Register, $src2$$Register);
 2043     } else if (instr == CGR_ZOPC) {
 2044       __ z_cgr($src1$$Register, $src2$$Register);
 2045     } else {
 2046       guarantee(instr == CLGR_ZOPC, "opcode not implemented");
 2047       __ z_clgr($src1$$Register, $src2$$Register);
 2048     }
 2049 
 2050     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 2051   %}
 2052 
 2053   enc_class z_enc_cmpb_regimm(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
 2054     C2_MacroAssembler _masm(&cbuf);
 2055     Label* p = $lbl$$label;
 2056 
 2057     // 'p' is `NULL' when this encoding class is used only to
 2058     // determine the size of the encoded instruction.
 2059     // Use a bound dummy label in that case.
 2060     Label d;
 2061     __ bind(d);
 2062     Label& l = (NULL == p) ? d : *(p);
 2063 
 2064     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2065     unsigned long instr = $primary;
 2066     if (instr == CIJ_ZOPC) {
 2067       __ z_cij($src1$$Register, $src2$$constant, cc, l);
 2068     } else if (instr == CLIJ_ZOPC) {
 2069       __ z_clij($src1$$Register, $src2$$constant, cc, l);
 2070     } else if (instr == CGIJ_ZOPC) {
 2071       __ z_cgij($src1$$Register, $src2$$constant, cc, l);
 2072     } else {
 2073       guarantee(instr == CLGIJ_ZOPC, "opcode not implemented");
 2074       __ z_clgij($src1$$Register, $src2$$constant, cc, l);
 2075     }
 2076   %}
 2077 
 2078   enc_class z_enc_cmpb_regimmFar(iRegI src1, immI8 src2, Label lbl, cmpOpT cmp) %{
 2079     C2_MacroAssembler _masm(&cbuf);
 2080     Label* p = $lbl$$label;
 2081 
 2082     // 'p' is `NULL' when this encoding class is used only to
 2083     // determine the size of the encoded instruction.
 2084     // Use a bound dummy label in that case.
 2085     Label d;
 2086     __ bind(d);
 2087     Label& l = (NULL == p) ? d : *(p);
 2088 
 2089     unsigned long instr = $primary;
 2090     if (instr == CHI_ZOPC) {
 2091       __ z_chi($src1$$Register, $src2$$constant);
 2092     } else if (instr == CLFI_ZOPC) {
 2093       __ z_clfi($src1$$Register, $src2$$constant);
 2094     } else if (instr == CGHI_ZOPC) {
 2095       __ z_cghi($src1$$Register, $src2$$constant);
 2096     } else {
 2097       guarantee(instr == CLGFI_ZOPC, "opcode not implemented");
 2098       __ z_clgfi($src1$$Register, $src2$$constant);
 2099     }
 2100 
 2101     __ z_brcl((Assembler::branch_condition)$cmp$$cmpcode, l);
 2102   %}
 2103 
 2104   // Call from Java to runtime.
 2105   enc_class z_enc_java_to_runtime_call(method meth) %{
 2106     C2_MacroAssembler _masm(&cbuf);
 2107 
 2108     // Save return pc before call to the place where we need it, since
 2109     // callee doesn't.
 2110     unsigned int start_off = __ offset();
 2111     // Compute size of "larl + stg + call_c_opt".
 2112     const int size_of_code = 6 + 6 + MacroAssembler::call_far_patchable_size();
 2113     __ get_PC(Z_R14, size_of_code);
 2114     __ save_return_pc();
 2115     assert(__ offset() - start_off == 12, "bad prelude len: %d", __ offset() - start_off);
 2116 
 2117     assert((__ offset() & 2) == 0, "misaligned z_enc_java_to_runtime_call");
 2118     address call_addr = __ call_c_opt((address)$meth$$method);
 2119     if (call_addr == NULL) {
 2120       Compile::current()->env()->record_out_of_memory_failure();
 2121       return;
 2122     }
 2123 
 2124 #ifdef ASSERT
 2125     // Plausibility check for size_of_code assumptions.
 2126     unsigned int actual_ret_off = __ offset();
 2127     assert(start_off + size_of_code == actual_ret_off, "wrong return_pc");
 2128 #endif
 2129   %}
 2130 
 2131   enc_class z_enc_java_static_call(method meth) %{
 2132     // Call to fixup routine. Fixup routine uses ScopeDesc info to determine
 2133     // whom we intended to call.
 2134     C2_MacroAssembler _masm(&cbuf);
 2135     int ret_offset = 0;
 2136 
 2137     if (!_method) {
 2138       ret_offset = emit_call_reloc(_masm, $meth$$method,
 2139                                    relocInfo::runtime_call_w_cp_type, ra_);
 2140     } else {
 2141       int method_index = resolved_method_index(cbuf);
 2142       if (_optimized_virtual) {
 2143         ret_offset = emit_call_reloc(_masm, $meth$$method,
 2144                                      opt_virtual_call_Relocation::spec(method_index));
 2145       } else {
 2146         ret_offset = emit_call_reloc(_masm, $meth$$method,
 2147                                      static_call_Relocation::spec(method_index));
 2148       }
 2149     }
 2150     assert(__ inst_mark() != NULL, "emit_call_reloc must set_inst_mark()");
 2151 
 2152     if (_method) { // Emit stub for static call.
 2153       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
 2154       if (stub == NULL) {
 2155         ciEnv::current()->record_failure("CodeCache is full");
 2156         return;
 2157       }
 2158     }
 2159   %}
 2160 
 2161   // Java dynamic call
 2162   enc_class z_enc_java_dynamic_call(method meth) %{
 2163     C2_MacroAssembler _masm(&cbuf);
 2164     unsigned int start_off = __ offset();
 2165 
 2166     int vtable_index = this->_vtable_index;
 2167     if (vtable_index == -4) {
 2168       Register ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
 2169       address virtual_call_oop_addr = NULL;
 2170 
 2171       AddressLiteral empty_ic((address) Universe::non_oop_word());
 2172       virtual_call_oop_addr = __ pc();
 2173       bool success = __ load_const_from_toc(ic_reg, empty_ic);
 2174       if (!success) {
 2175         Compile::current()->env()->record_out_of_memory_failure();
 2176         return;
 2177       }
 2178 
 2179       // Call to fixup routine. Fixup routine uses ScopeDesc info
 2180       // to determine who we intended to call.
 2181       int method_index = resolved_method_index(cbuf);
 2182       __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index));
 2183       unsigned int ret_off = __ offset();
 2184       assert(__ offset() - start_off == 6, "bad prelude len: %d", __ offset() - start_off);
 2185       ret_off += emit_call_reloc(_masm, $meth$$method, relocInfo::none, ra_);
 2186       assert(_method, "lazy_constant may be wrong when _method==null");
 2187     } else {
 2188       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 2189       // Go through the vtable. Get receiver klass. Receiver already
 2190       // checked for non-null. If we'll go thru a C2I adapter, the
 2191       // interpreter expects method in Z_method.
 2192       // Use Z_method to temporarily hold the klass oop.
 2193       // Z_R1_scratch is destroyed.
 2194       __ load_klass(Z_method, Z_R2);
 2195 
 2196       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index * vtableEntry::size_in_bytes();
 2197       int v_off        = entry_offset + vtableEntry::method_offset_in_bytes();
 2198 
 2199       if (Displacement::is_validDisp(v_off) ) {
 2200         // Can use load instruction with large offset.
 2201         __ z_lg(Z_method, Address(Z_method /*class oop*/, v_off /*method offset*/));
 2202       } else {
 2203         // Worse case, must load offset into register.
 2204         __ load_const(Z_R1_scratch, v_off);
 2205         __ z_lg(Z_method, Address(Z_method /*class oop*/, Z_R1_scratch /*method offset*/));
 2206       }
 2207       // NOTE: for vtable dispatches, the vtable entry will never be
 2208       // null. However it may very well end up in handle_wrong_method
 2209       // if the method is abstract for the particular class.
 2210       __ z_lg(Z_R1_scratch, Address(Z_method, Method::from_compiled_offset()));
 2211       // Call target. Either compiled code or C2I adapter.
 2212       __ z_basr(Z_R14, Z_R1_scratch);
 2213       unsigned int ret_off = __ offset();
 2214     }
 2215   %}
 2216 
 2217   enc_class z_enc_cmov_reg(cmpOp cmp, iRegI dst, iRegI src) %{
 2218     C2_MacroAssembler _masm(&cbuf);
 2219     Register Rdst = reg_to_register_object($dst$$reg);
 2220     Register Rsrc = reg_to_register_object($src$$reg);
 2221 
 2222     // Don't emit code if operands are identical (same register).
 2223     if (Rsrc != Rdst) {
 2224       Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2225 
 2226       if (VM_Version::has_LoadStoreConditional()) {
 2227         __ z_locgr(Rdst, Rsrc, cc);
 2228       } else {
 2229         // Branch if not (cmp cr).
 2230         Label done;
 2231         __ z_brc(Assembler::inverse_condition(cc), done);
 2232         __ z_lgr(Rdst, Rsrc); // Used for int and long+ptr.
 2233         __ bind(done);
 2234       }
 2235     }
 2236   %}
 2237 
 2238   enc_class z_enc_cmov_imm(cmpOp cmp, iRegI dst, immI16 src) %{
 2239     C2_MacroAssembler _masm(&cbuf);
 2240     Register Rdst = reg_to_register_object($dst$$reg);
 2241     int      Csrc = $src$$constant;
 2242     Assembler::branch_condition cc = (Assembler::branch_condition)$cmp$$cmpcode;
 2243     Label done;
 2244     // Branch if not (cmp cr).
 2245     __ z_brc(Assembler::inverse_condition(cc), done);
 2246     if (Csrc == 0) {
 2247       // Don't set CC.
 2248       __ clear_reg(Rdst, true, false);  // Use for int, long & ptr.
 2249     } else {
 2250       __ z_lghi(Rdst, Csrc); // Use for int, long & ptr.
 2251     }
 2252     __ bind(done);
 2253   %}
 2254 
 2255   enc_class z_enc_cctobool(iRegI res) %{
 2256     C2_MacroAssembler _masm(&cbuf);
 2257     Register Rres = reg_to_register_object($res$$reg);
 2258 
 2259     if (VM_Version::has_LoadStoreConditional()) {
 2260       __ load_const_optimized(Z_R0_scratch, 0L); // false (failed)
 2261       __ load_const_optimized(Rres, 1L);         // true  (succeed)
 2262       __ z_locgr(Rres, Z_R0_scratch, Assembler::bcondNotEqual);
 2263     } else {
 2264       Label done;
 2265       __ load_const_optimized(Rres, 0L); // false (failed)
 2266       __ z_brne(done);                   // Assume true to be the common case.
 2267       __ load_const_optimized(Rres, 1L); // true  (succeed)
 2268       __ bind(done);
 2269     }
 2270   %}
 2271 
 2272   enc_class z_enc_casI(iRegI compare_value, iRegI exchange_value, iRegP addr_ptr) %{
 2273     C2_MacroAssembler _masm(&cbuf);
 2274     Register Rcomp = reg_to_register_object($compare_value$$reg);
 2275     Register Rnew  = reg_to_register_object($exchange_value$$reg);
 2276     Register Raddr = reg_to_register_object($addr_ptr$$reg);
 2277 
 2278     __ z_cs(Rcomp, Rnew, 0, Raddr);
 2279   %}
 2280 
 2281   enc_class z_enc_casL(iRegL compare_value, iRegL exchange_value, iRegP addr_ptr) %{
 2282     C2_MacroAssembler _masm(&cbuf);
 2283     Register Rcomp = reg_to_register_object($compare_value$$reg);
 2284     Register Rnew  = reg_to_register_object($exchange_value$$reg);
 2285     Register Raddr = reg_to_register_object($addr_ptr$$reg);
 2286 
 2287     __ z_csg(Rcomp, Rnew, 0, Raddr);
 2288   %}
 2289 
 2290   enc_class z_enc_SwapI(memoryRSY mem, iRegI dst, iRegI tmp) %{
 2291     C2_MacroAssembler _masm(&cbuf);
 2292     Register Rdst = reg_to_register_object($dst$$reg);
 2293     Register Rtmp = reg_to_register_object($tmp$$reg);
 2294     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
 2295     Label    retry;
 2296 
 2297     // Iterate until swap succeeds.
 2298     __ z_llgf(Rtmp, $mem$$Address);  // current contents
 2299     __ bind(retry);
 2300       // Calculate incremented value.
 2301       __ z_csy(Rtmp, Rdst, $mem$$Address); // Try to store new value.
 2302       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
 2303     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
 2304   %}
 2305 
 2306   enc_class z_enc_SwapL(memoryRSY mem, iRegL dst, iRegL tmp) %{
 2307     C2_MacroAssembler _masm(&cbuf);
 2308     Register Rdst = reg_to_register_object($dst$$reg);
 2309     Register Rtmp = reg_to_register_object($tmp$$reg);
 2310     guarantee(Rdst != Rtmp, "Fix match rule to use TEMP_DEF");
 2311     Label    retry;
 2312 
 2313     // Iterate until swap succeeds.
 2314     __ z_lg(Rtmp, $mem$$Address);  // current contents
 2315     __ bind(retry);
 2316       // Calculate incremented value.
 2317       __ z_csg(Rtmp, Rdst, $mem$$Address); // Try to store new value.
 2318       __ z_brne(retry);                    // Yikes, concurrent update, need to retry.
 2319     __ z_lgr(Rdst, Rtmp);                  // Exchanged value from memory is return value.
 2320   %}
 2321 
 2322 %} // encode
 2323 
 2324 source %{
 2325 
 2326   // Check whether outs are all Stores. If so, we can omit clearing the upper
 2327   // 32 bits after encoding.
 2328   static bool all_outs_are_Stores(const Node *n) {
 2329     for (DUIterator_Fast imax, k = n->fast_outs(imax); k < imax; k++) {
 2330       Node *out = n->fast_out(k);
 2331       if (!out->is_Mach() || out->as_Mach()->ideal_Opcode() != Op_StoreN) {
 2332         // Most other outs are SpillCopy, but there are various other.
 2333         // jvm98 has arond 9% Encodes where we return false.
 2334         return false;
 2335       }
 2336     }
 2337     return true;
 2338   }
 2339 
 2340 %} // source
 2341 
 2342 
 2343 //----------FRAME--------------------------------------------------------------
 2344 // Definition of frame structure and management information.
 2345 
 2346 frame %{
 2347   // These two registers define part of the calling convention between
 2348   // compiled code and the interpreter.
 2349 
 2350   // Inline Cache Register
 2351   inline_cache_reg(Z_R9); // Z_inline_cache
 2352 
 2353   // Argument pointer for I2C adapters
 2354   //
 2355   // Tos is loaded in run_compiled_code to Z_ARG5=Z_R6.
 2356   // interpreter_arg_ptr_reg(Z_R6);
 2357 
 2358   // Optional: name the operand used by cisc-spilling to access
 2359   // [stack_pointer + offset].
 2360   cisc_spilling_operand_name(indOffset12);
 2361 
 2362   // Number of stack slots consumed by a Monitor enter.
 2363   sync_stack_slots(frame::jit_monitor_size_in_4_byte_units);
 2364 
 2365   // Compiled code's Frame Pointer
 2366   //
 2367   // z/Architecture stack pointer
 2368   frame_pointer(Z_R15); // Z_SP
 2369 
 2370   // Interpreter stores its frame pointer in a register which is
 2371   // stored to the stack by I2CAdaptors. I2CAdaptors convert from
 2372   // interpreted java to compiled java.
 2373   //
 2374   // Z_state holds pointer to caller's cInterpreter.
 2375   interpreter_frame_pointer(Z_R7); // Z_state
 2376 
 2377   // Use alignment_in_bytes instead of log_2_of_alignment_in_bits.
 2378   stack_alignment(frame::alignment_in_bytes);
 2379 
 2380   // A `slot' is assumed 4 bytes here!
 2381   // out_preserve_stack_slots(frame::jit_out_preserve_size_in_4_byte_units);
 2382 
 2383   // Number of outgoing stack slots killed above the
 2384   // out_preserve_stack_slots for calls to C. Supports the var-args
 2385   // backing area for register parms.
 2386   varargs_C_out_slots_killed(((frame::z_abi_160_size - frame::z_jit_out_preserve_size) / VMRegImpl::stack_slot_size));
 2387 
 2388   // The after-PROLOG location of the return address. Location of
 2389   // return address specifies a type (REG or STACK) and a number
 2390   // representing the register number (i.e. - use a register name) or
 2391   // stack slot.
 2392   return_addr(REG Z_R14);
 2393 
 2394   // Location of native (C/C++) and interpreter return values. This
 2395   // is specified to be the same as Java. In the 32-bit VM, long
 2396   // values are actually returned from native calls in O0:O1 and
 2397   // returned to the interpreter in I0:I1. The copying to and from
 2398   // the register pairs is done by the appropriate call and epilog
 2399   // opcodes. This simplifies the register allocator.
 2400   //
 2401   // Use register pair for c return value.
 2402   c_return_value %{
 2403     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
 2404     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
 2405     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
 2406     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
 2407   %}
 2408 
 2409   // Use register pair for return value.
 2410   // Location of compiled Java return values. Same as C
 2411   return_value %{
 2412     assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values");
 2413     static int typeToRegLo[Op_RegL+1] = { 0, 0, Z_R2_num, Z_R2_num, Z_R2_num, Z_F0_num, Z_F0_num, Z_R2_num };
 2414     static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, OptoReg::Bad, Z_R2_H_num, OptoReg::Bad, Z_F0_H_num, Z_R2_H_num };
 2415     return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]);
 2416   %}
 2417 %}
 2418 
 2419 
 2420 //----------ATTRIBUTES---------------------------------------------------------
 2421 
 2422 //----------Operand Attributes-------------------------------------------------
 2423 op_attrib op_cost(1);          // Required cost attribute
 2424 
 2425 //----------Instruction Attributes---------------------------------------------
 2426 
 2427 // Cost attribute. required.
 2428 ins_attrib ins_cost(DEFAULT_COST);
 2429 
 2430 // Is this instruction a non-matching short branch variant of some
 2431 // long branch? Not required.
 2432 ins_attrib ins_short_branch(0);
 2433 
 2434 // Indicates this is a trap based check node and final control-flow fixup
 2435 // must generate a proper fall through.
 2436 ins_attrib ins_is_TrapBasedCheckNode(true);
 2437 
 2438 // Attribute of instruction to tell how many constants the instruction will generate.
 2439 // (optional attribute). Default: 0.
 2440 ins_attrib ins_num_consts(0);
 2441 
 2442 // Required alignment attribute (must be a power of 2)
 2443 // specifies the alignment that some part of the instruction (not
 2444 // necessarily the start) requires. If > 1, a compute_padding()
 2445 // function must be provided for the instruction.
 2446 //
 2447 // WARNING: Don't use size(FIXED_SIZE) or size(VARIABLE_SIZE) in
 2448 // instructions which depend on the proper alignment, because the
 2449 // desired alignment isn't guaranteed for the call to "emit()" during
 2450 // the size computation.
 2451 ins_attrib ins_alignment(1);
 2452 
 2453 // Enforce/prohibit rematerializations.
 2454 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)'
 2455 //   then rematerialization of that instruction is prohibited and the
 2456 //   instruction's value will be spilled if necessary.
 2457 // - If an instruction is attributed with 'ins_should_rematerialize(true)'
 2458 //   then rematerialization is enforced and the instruction's value will
 2459 //   never get spilled. a copy of the instruction will be inserted if
 2460 //   necessary.
 2461 //   Note: this may result in rematerializations in front of every use.
 2462 // (optional attribute)
 2463 ins_attrib ins_cannot_rematerialize(false);
 2464 ins_attrib ins_should_rematerialize(false);
 2465 
 2466 //----------OPERANDS-----------------------------------------------------------
 2467 // Operand definitions must precede instruction definitions for correct
 2468 // parsing in the ADLC because operands constitute user defined types
 2469 // which are used in instruction definitions.
 2470 
 2471 //----------Simple Operands----------------------------------------------------
 2472 // Immediate Operands
 2473 // Please note:
 2474 // Formats are generated automatically for constants and base registers.
 2475 
 2476 //----------------------------------------------
 2477 // SIGNED (shorter than INT) immediate operands
 2478 //----------------------------------------------
 2479 
 2480 // Byte Immediate: constant 'int -1'
 2481 operand immB_minus1() %{
 2482   //         sign-ext constant      zero-ext constant
 2483   predicate((n->get_int() == -1) || ((n->get_int()&0x000000ff) == 0x000000ff));
 2484   match(ConI);
 2485   op_cost(1);
 2486   format %{ %}
 2487   interface(CONST_INTER);
 2488 %}
 2489 
 2490 // Byte Immediate: constant, but not 'int 0' nor 'int -1'.
 2491 operand immB_n0m1() %{
 2492   //                             sign-ext constant     zero-ext constant
 2493   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x000000ff) != 0x000000ff);
 2494   match(ConI);
 2495   op_cost(1);
 2496   format %{ %}
 2497   interface(CONST_INTER);
 2498 %}
 2499 
 2500 // Short Immediate: constant 'int -1'
 2501 operand immS_minus1() %{
 2502   //         sign-ext constant      zero-ext constant
 2503   predicate((n->get_int() == -1) || ((n->get_int()&0x0000ffff) == 0x0000ffff));
 2504   match(ConI);
 2505   op_cost(1);
 2506   format %{ %}
 2507   interface(CONST_INTER);
 2508 %}
 2509 
 2510 // Short Immediate: constant, but not 'int 0' nor 'int -1'.
 2511 operand immS_n0m1() %{
 2512   //                             sign-ext constant     zero-ext constant
 2513   predicate(n->get_int() != 0 && n->get_int() != -1 && (n->get_int()&0x0000ffff) != 0x0000ffff);
 2514   match(ConI);
 2515   op_cost(1);
 2516   format %{ %}
 2517   interface(CONST_INTER);
 2518 %}
 2519 
 2520 //-----------------------------------------
 2521 //  SIGNED INT immediate operands
 2522 //-----------------------------------------
 2523 
 2524 // Integer Immediate: 32-bit
 2525 operand immI() %{
 2526   match(ConI);
 2527   op_cost(1);
 2528   format %{ %}
 2529   interface(CONST_INTER);
 2530 %}
 2531 
 2532 // Int Immediate: 20-bit
 2533 operand immI20() %{
 2534   predicate(Immediate::is_simm20(n->get_int()));
 2535   match(ConI);
 2536   op_cost(1);
 2537   format %{ %}
 2538   interface(CONST_INTER);
 2539 %}
 2540 
 2541 // Integer Immediate: 16-bit
 2542 operand immI16() %{
 2543   predicate(Immediate::is_simm16(n->get_int()));
 2544   match(ConI);
 2545   op_cost(1);
 2546   format %{ %}
 2547   interface(CONST_INTER);
 2548 %}
 2549 
 2550 // Integer Immediate: 8-bit
 2551 operand immI8() %{
 2552   predicate(Immediate::is_simm8(n->get_int()));
 2553   match(ConI);
 2554   op_cost(1);
 2555   format %{ %}
 2556   interface(CONST_INTER);
 2557 %}
 2558 
 2559 // Integer Immediate: constant 'int 0'
 2560 operand immI_0() %{
 2561   predicate(n->get_int() == 0);
 2562   match(ConI);
 2563   op_cost(1);
 2564   format %{ %}
 2565   interface(CONST_INTER);
 2566 %}
 2567 
 2568 // Integer Immediate: constant 'int -1'
 2569 operand immI_minus1() %{
 2570   predicate(n->get_int() == -1);
 2571   match(ConI);
 2572   op_cost(1);
 2573   format %{ %}
 2574   interface(CONST_INTER);
 2575 %}
 2576 
 2577 // Integer Immediate: constant, but not 'int 0' nor 'int -1'.
 2578 operand immI_n0m1() %{
 2579   predicate(n->get_int() != 0 && n->get_int() != -1);
 2580   match(ConI);
 2581   op_cost(1);
 2582   format %{ %}
 2583   interface(CONST_INTER);
 2584 %}
 2585 
 2586 //-------------------------------------------
 2587 // UNSIGNED INT immediate operands
 2588 //-------------------------------------------
 2589 
 2590 // Unsigned Integer Immediate: 32-bit
 2591 operand uimmI() %{
 2592   match(ConI);
 2593   op_cost(1);
 2594   format %{ %}
 2595   interface(CONST_INTER);
 2596 %}
 2597 
 2598 // Unsigned Integer Immediate: 16-bit
 2599 operand uimmI16() %{
 2600   predicate(Immediate::is_uimm16(n->get_int()));
 2601   match(ConI);
 2602   op_cost(1);
 2603   format %{ %}
 2604   interface(CONST_INTER);
 2605 %}
 2606 
 2607 // Unsigned Integer Immediate: 12-bit
 2608 operand uimmI12() %{
 2609   predicate(Immediate::is_uimm12(n->get_int()));
 2610   match(ConI);
 2611   op_cost(1);
 2612   format %{ %}
 2613   interface(CONST_INTER);
 2614 %}
 2615 
 2616 // Unsigned Integer Immediate: 12-bit
 2617 operand uimmI8() %{
 2618   predicate(Immediate::is_uimm8(n->get_int()));
 2619   match(ConI);
 2620   op_cost(1);
 2621   format %{ %}
 2622   interface(CONST_INTER);
 2623 %}
 2624 
 2625 // Integer Immediate: 6-bit
 2626 operand uimmI6() %{
 2627   predicate(Immediate::is_uimm(n->get_int(), 6));
 2628   match(ConI);
 2629   op_cost(1);
 2630   format %{ %}
 2631   interface(CONST_INTER);
 2632 %}
 2633 
 2634 // Integer Immediate: 5-bit
 2635 operand uimmI5() %{
 2636   predicate(Immediate::is_uimm(n->get_int(), 5));
 2637   match(ConI);
 2638   op_cost(1);
 2639   format %{ %}
 2640   interface(CONST_INTER);
 2641 %}
 2642 
 2643 // Length for SS instructions, given in DWs,
 2644 //   possible range [1..512], i.e. [8..4096] Bytes
 2645 //   used     range [1..256], i.e. [8..2048] Bytes
 2646 //   operand type int
 2647 // Unsigned Integer Immediate: 9-bit
 2648 operand SSlenDW() %{
 2649   predicate(Immediate::is_uimm8(n->get_long()-1));
 2650   match(ConL);
 2651   op_cost(1);
 2652   format %{ %}
 2653   interface(CONST_INTER);
 2654 %}
 2655 
 2656 //------------------------------------------
 2657 // (UN)SIGNED INT specific values
 2658 //------------------------------------------
 2659 
 2660 // Integer Immediate: the value 1
 2661 operand immI_1() %{
 2662   predicate(n->get_int() == 1);
 2663   match(ConI);
 2664   op_cost(1);
 2665   format %{ %}
 2666   interface(CONST_INTER);
 2667 %}
 2668 
 2669 // Integer Immediate: the value 16.
 2670 operand immI_16() %{
 2671   predicate(n->get_int() == 16);
 2672   match(ConI);
 2673   op_cost(1);
 2674   format %{ %}
 2675   interface(CONST_INTER);
 2676 %}
 2677 
 2678 // Integer Immediate: the value 24.
 2679 operand immI_24() %{
 2680   predicate(n->get_int() == 24);
 2681   match(ConI);
 2682   op_cost(1);
 2683   format %{ %}
 2684   interface(CONST_INTER);
 2685 %}
 2686 
 2687 // Integer Immediate: the value 255
 2688 operand immI_255() %{
 2689   predicate(n->get_int() == 255);
 2690   match(ConI);
 2691   op_cost(1);
 2692   format %{ %}
 2693   interface(CONST_INTER);
 2694 %}
 2695 
 2696 // Integer Immediate: the values 32-63
 2697 operand immI_32_63() %{
 2698   predicate(n->get_int() >= 32 && n->get_int() <= 63);
 2699   match(ConI);
 2700   op_cost(1);
 2701   format %{ %}
 2702   interface(CONST_INTER);
 2703 %}
 2704 
 2705 // Unsigned Integer Immediate: LL-part, extended by 1s.
 2706 operand uimmI_LL1() %{
 2707   predicate((n->get_int() & 0xFFFF0000) == 0xFFFF0000);
 2708   match(ConI);
 2709   op_cost(1);
 2710   format %{ %}
 2711   interface(CONST_INTER);
 2712 %}
 2713 
 2714 // Unsigned Integer Immediate: LH-part, extended by 1s.
 2715 operand uimmI_LH1() %{
 2716   predicate((n->get_int() & 0xFFFF) == 0xFFFF);
 2717   match(ConI);
 2718   op_cost(1);
 2719   format %{ %}
 2720   interface(CONST_INTER);
 2721 %}
 2722 
 2723 //------------------------------------------
 2724 // SIGNED LONG immediate operands
 2725 //------------------------------------------
 2726 
 2727 operand immL() %{
 2728   match(ConL);
 2729   op_cost(1);
 2730   format %{ %}
 2731   interface(CONST_INTER);
 2732 %}
 2733 
 2734 // Long Immediate: 32-bit
 2735 operand immL32() %{
 2736   predicate(Immediate::is_simm32(n->get_long()));
 2737   match(ConL);
 2738   op_cost(1);
 2739   format %{ %}
 2740   interface(CONST_INTER);
 2741 %}
 2742 
 2743 // Long Immediate: 20-bit
 2744 operand immL20() %{
 2745   predicate(Immediate::is_simm20(n->get_long()));
 2746   match(ConL);
 2747   op_cost(1);
 2748   format %{ %}
 2749   interface(CONST_INTER);
 2750 %}
 2751 
 2752 // Long Immediate: 16-bit
 2753 operand immL16() %{
 2754   predicate(Immediate::is_simm16(n->get_long()));
 2755   match(ConL);
 2756   op_cost(1);
 2757   format %{ %}
 2758   interface(CONST_INTER);
 2759 %}
 2760 
 2761 // Long Immediate: 8-bit
 2762 operand immL8() %{
 2763   predicate(Immediate::is_simm8(n->get_long()));
 2764   match(ConL);
 2765   op_cost(1);
 2766   format %{ %}
 2767   interface(CONST_INTER);
 2768 %}
 2769 
 2770 //--------------------------------------------
 2771 // UNSIGNED LONG immediate operands
 2772 //--------------------------------------------
 2773 
 2774 operand uimmL32() %{
 2775   predicate(Immediate::is_uimm32(n->get_long()));
 2776   match(ConL);
 2777   op_cost(1);
 2778   format %{ %}
 2779   interface(CONST_INTER);
 2780 %}
 2781 
 2782 // Unsigned Long Immediate: 16-bit
 2783 operand uimmL16() %{
 2784   predicate(Immediate::is_uimm16(n->get_long()));
 2785   match(ConL);
 2786   op_cost(1);
 2787   format %{ %}
 2788   interface(CONST_INTER);
 2789 %}
 2790 
 2791 // Unsigned Long Immediate: 12-bit
 2792 operand uimmL12() %{
 2793   predicate(Immediate::is_uimm12(n->get_long()));
 2794   match(ConL);
 2795   op_cost(1);
 2796   format %{ %}
 2797   interface(CONST_INTER);
 2798 %}
 2799 
 2800 // Unsigned Long Immediate: 8-bit
 2801 operand uimmL8() %{
 2802   predicate(Immediate::is_uimm8(n->get_long()));
 2803   match(ConL);
 2804   op_cost(1);
 2805   format %{ %}
 2806   interface(CONST_INTER);
 2807 %}
 2808 
 2809 //-------------------------------------------
 2810 // (UN)SIGNED LONG specific values
 2811 //-------------------------------------------
 2812 
 2813 // Long Immediate: the value FF
 2814 operand immL_FF() %{
 2815   predicate(n->get_long() == 0xFFL);
 2816   match(ConL);
 2817   op_cost(1);
 2818   format %{ %}
 2819   interface(CONST_INTER);
 2820 %}
 2821 
 2822 // Long Immediate: the value FFFF
 2823 operand immL_FFFF() %{
 2824   predicate(n->get_long() == 0xFFFFL);
 2825   match(ConL);
 2826   op_cost(1);
 2827   format %{ %}
 2828   interface(CONST_INTER);
 2829 %}
 2830 
 2831 // Long Immediate: the value FFFFFFFF
 2832 operand immL_FFFFFFFF() %{
 2833   predicate(n->get_long() == 0xFFFFFFFFL);
 2834   match(ConL);
 2835   op_cost(1);
 2836   format %{ %}
 2837   interface(CONST_INTER);
 2838 %}
 2839 
 2840 operand immL_0() %{
 2841   predicate(n->get_long() == 0L);
 2842   match(ConL);
 2843   op_cost(1);
 2844   format %{ %}
 2845   interface(CONST_INTER);
 2846 %}
 2847 
 2848 // Unsigned Long Immediate: LL-part, extended by 1s.
 2849 operand uimmL_LL1() %{
 2850   predicate((n->get_long() & 0xFFFFFFFFFFFF0000L) == 0xFFFFFFFFFFFF0000L);
 2851   match(ConL);
 2852   op_cost(1);
 2853   format %{ %}
 2854   interface(CONST_INTER);
 2855 %}
 2856 
 2857 // Unsigned Long Immediate: LH-part, extended by 1s.
 2858 operand uimmL_LH1() %{
 2859   predicate((n->get_long() & 0xFFFFFFFF0000FFFFL) == 0xFFFFFFFF0000FFFFL);
 2860   match(ConL);
 2861   op_cost(1);
 2862   format %{ %}
 2863   interface(CONST_INTER);
 2864 %}
 2865 
 2866 // Unsigned Long Immediate: HL-part, extended by 1s.
 2867 operand uimmL_HL1() %{
 2868   predicate((n->get_long() & 0xFFFF0000FFFFFFFFL) == 0xFFFF0000FFFFFFFFL);
 2869   match(ConL);
 2870   op_cost(1);
 2871   format %{ %}
 2872   interface(CONST_INTER);
 2873 %}
 2874 
 2875 // Unsigned Long Immediate: HH-part, extended by 1s.
 2876 operand uimmL_HH1() %{
 2877   predicate((n->get_long() & 0xFFFFFFFFFFFFL) == 0xFFFFFFFFFFFFL);
 2878   match(ConL);
 2879   op_cost(1);
 2880   format %{ %}
 2881   interface(CONST_INTER);
 2882 %}
 2883 
 2884 // Long Immediate: low 32-bit mask
 2885 operand immL_32bits() %{
 2886   predicate(n->get_long() == 0xFFFFFFFFL);
 2887   match(ConL);
 2888   op_cost(1);
 2889   format %{ %}
 2890   interface(CONST_INTER);
 2891 %}
 2892 
 2893 //--------------------------------------
 2894 //  POINTER immediate operands
 2895 //--------------------------------------
 2896 
 2897 // Pointer Immediate: 64-bit
 2898 operand immP() %{
 2899   match(ConP);
 2900   op_cost(1);
 2901   format %{ %}
 2902   interface(CONST_INTER);
 2903 %}
 2904 
 2905 // Pointer Immediate: 32-bit
 2906 operand immP32() %{
 2907   predicate(Immediate::is_uimm32(n->get_ptr()));
 2908   match(ConP);
 2909   op_cost(1);
 2910   format %{ %}
 2911   interface(CONST_INTER);
 2912 %}
 2913 
 2914 // Pointer Immediate: 16-bit
 2915 operand immP16() %{
 2916   predicate(Immediate::is_uimm16(n->get_ptr()));
 2917   match(ConP);
 2918   op_cost(1);
 2919   format %{ %}
 2920   interface(CONST_INTER);
 2921 %}
 2922 
 2923 // Pointer Immediate: 8-bit
 2924 operand immP8() %{
 2925   predicate(Immediate::is_uimm8(n->get_ptr()));
 2926   match(ConP);
 2927   op_cost(1);
 2928   format %{ %}
 2929   interface(CONST_INTER);
 2930 %}
 2931 
 2932 //-----------------------------------
 2933 // POINTER specific values
 2934 //-----------------------------------
 2935 
 2936 // Pointer Immediate: NULL
 2937 operand immP0() %{
 2938   predicate(n->get_ptr() == 0);
 2939   match(ConP);
 2940   op_cost(1);
 2941   format %{ %}
 2942   interface(CONST_INTER);
 2943 %}
 2944 
 2945 //---------------------------------------------
 2946 // NARROW POINTER immediate operands
 2947 //---------------------------------------------
 2948 
 2949 // Narrow Pointer Immediate
 2950 operand immN() %{
 2951   match(ConN);
 2952   op_cost(1);
 2953   format %{ %}
 2954   interface(CONST_INTER);
 2955 %}
 2956 
 2957 operand immNKlass() %{
 2958   match(ConNKlass);
 2959   op_cost(1);
 2960   format %{ %}
 2961   interface(CONST_INTER);
 2962 %}
 2963 
 2964 // Narrow Pointer Immediate
 2965 operand immN8() %{
 2966   predicate(Immediate::is_uimm8(n->get_narrowcon()));
 2967   match(ConN);
 2968   op_cost(1);
 2969   format %{ %}
 2970   interface(CONST_INTER);
 2971 %}
 2972 
 2973 // Narrow NULL Pointer Immediate
 2974 operand immN0() %{
 2975   predicate(n->get_narrowcon() == 0);
 2976   match(ConN);
 2977   op_cost(1);
 2978   format %{ %}
 2979   interface(CONST_INTER);
 2980 %}
 2981 
 2982 // FLOAT and DOUBLE immediate operands
 2983 
 2984 // Double Immediate
 2985 operand immD() %{
 2986   match(ConD);
 2987   op_cost(1);
 2988   format %{ %}
 2989   interface(CONST_INTER);
 2990 %}
 2991 
 2992 // Double Immediate: +-0
 2993 operand immDpm0() %{
 2994   predicate(n->getd() == 0);
 2995   match(ConD);
 2996   op_cost(1);
 2997   format %{ %}
 2998   interface(CONST_INTER);
 2999 %}
 3000 
 3001 // Double Immediate: +0
 3002 operand immDp0() %{
 3003   predicate(jlong_cast(n->getd()) == 0);
 3004   match(ConD);
 3005   op_cost(1);
 3006   format %{ %}
 3007   interface(CONST_INTER);
 3008 %}
 3009 
 3010 // Float Immediate
 3011 operand immF() %{
 3012   match(ConF);
 3013   op_cost(1);
 3014   format %{ %}
 3015   interface(CONST_INTER);
 3016 %}
 3017 
 3018 // Float Immediate: +-0
 3019 operand immFpm0() %{
 3020   predicate(n->getf() == 0);
 3021   match(ConF);
 3022   op_cost(1);
 3023   format %{ %}
 3024   interface(CONST_INTER);
 3025 %}
 3026 
 3027 // Float Immediate: +0
 3028 operand immFp0() %{
 3029   predicate(jint_cast(n->getf()) == 0);
 3030   match(ConF);
 3031   op_cost(1);
 3032   format %{ %}
 3033   interface(CONST_INTER);
 3034 %}
 3035 
 3036 // End of Immediate Operands
 3037 
 3038 // Integer Register Operands
 3039 // Integer Register
 3040 operand iRegI() %{
 3041   constraint(ALLOC_IN_RC(z_int_reg));
 3042   match(RegI);
 3043   match(noArg_iRegI);
 3044   match(rarg1RegI);
 3045   match(rarg2RegI);
 3046   match(rarg3RegI);
 3047   match(rarg4RegI);
 3048   match(rarg5RegI);
 3049   match(noOdd_iRegI);
 3050   match(revenRegI);
 3051   match(roddRegI);
 3052   format %{ %}
 3053   interface(REG_INTER);
 3054 %}
 3055 
 3056 operand noArg_iRegI() %{
 3057   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
 3058   match(RegI);
 3059   format %{ %}
 3060   interface(REG_INTER);
 3061 %}
 3062 
 3063 // revenRegI and roddRegI constitute and even-odd-pair.
 3064 operand revenRegI() %{
 3065   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3066   match(iRegI);
 3067   format %{ %}
 3068   interface(REG_INTER);
 3069 %}
 3070 
 3071 // revenRegI and roddRegI constitute and even-odd-pair.
 3072 operand roddRegI() %{
 3073   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3074   match(iRegI);
 3075   format %{ %}
 3076   interface(REG_INTER);
 3077 %}
 3078 
 3079 operand rarg1RegI() %{
 3080   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
 3081   match(iRegI);
 3082   format %{ %}
 3083   interface(REG_INTER);
 3084 %}
 3085 
 3086 operand rarg2RegI() %{
 3087   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
 3088   match(iRegI);
 3089   format %{ %}
 3090   interface(REG_INTER);
 3091 %}
 3092 
 3093 operand rarg3RegI() %{
 3094   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3095   match(iRegI);
 3096   format %{ %}
 3097   interface(REG_INTER);
 3098 %}
 3099 
 3100 operand rarg4RegI() %{
 3101   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3102   match(iRegI);
 3103   format %{ %}
 3104   interface(REG_INTER);
 3105 %}
 3106 
 3107 operand rarg5RegI() %{
 3108   constraint(ALLOC_IN_RC(z_rarg5_int_reg));
 3109   match(iRegI);
 3110   format %{ %}
 3111   interface(REG_INTER);
 3112 %}
 3113 
 3114 operand noOdd_iRegI() %{
 3115   constraint(ALLOC_IN_RC(z_no_odd_int_reg));
 3116   match(RegI);
 3117   match(revenRegI);
 3118   format %{ %}
 3119   interface(REG_INTER);
 3120 %}
 3121 
 3122 // Pointer Register
 3123 operand iRegP() %{
 3124   constraint(ALLOC_IN_RC(z_ptr_reg));
 3125   match(RegP);
 3126   match(noArg_iRegP);
 3127   match(rarg1RegP);
 3128   match(rarg2RegP);
 3129   match(rarg3RegP);
 3130   match(rarg4RegP);
 3131   match(rarg5RegP);
 3132   match(revenRegP);
 3133   match(roddRegP);
 3134   format %{ %}
 3135   interface(REG_INTER);
 3136 %}
 3137 
 3138 // thread operand
 3139 operand threadRegP() %{
 3140   constraint(ALLOC_IN_RC(z_thread_ptr_reg));
 3141   match(RegP);
 3142   format %{ "Z_THREAD" %}
 3143   interface(REG_INTER);
 3144 %}
 3145 
 3146 operand noArg_iRegP() %{
 3147   constraint(ALLOC_IN_RC(z_no_arg_ptr_reg));
 3148   match(iRegP);
 3149   format %{ %}
 3150   interface(REG_INTER);
 3151 %}
 3152 
 3153 operand rarg1RegP() %{
 3154   constraint(ALLOC_IN_RC(z_rarg1_ptr_reg));
 3155   match(iRegP);
 3156   format %{ %}
 3157   interface(REG_INTER);
 3158 %}
 3159 
 3160 operand rarg2RegP() %{
 3161   constraint(ALLOC_IN_RC(z_rarg2_ptr_reg));
 3162   match(iRegP);
 3163   format %{ %}
 3164   interface(REG_INTER);
 3165 %}
 3166 
 3167 operand rarg3RegP() %{
 3168   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
 3169   match(iRegP);
 3170   format %{ %}
 3171   interface(REG_INTER);
 3172 %}
 3173 
 3174 operand rarg4RegP() %{
 3175   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
 3176   match(iRegP);
 3177   format %{ %}
 3178   interface(REG_INTER);
 3179 %}
 3180 
 3181 operand rarg5RegP() %{
 3182   constraint(ALLOC_IN_RC(z_rarg5_ptr_reg));
 3183   match(iRegP);
 3184   format %{ %}
 3185   interface(REG_INTER);
 3186 %}
 3187 
 3188 operand memoryRegP() %{
 3189   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3190   match(RegP);
 3191   match(iRegP);
 3192   match(threadRegP);
 3193   format %{ %}
 3194   interface(REG_INTER);
 3195 %}
 3196 
 3197 // revenRegP and roddRegP constitute and even-odd-pair.
 3198 operand revenRegP() %{
 3199   constraint(ALLOC_IN_RC(z_rarg3_ptr_reg));
 3200   match(iRegP);
 3201   format %{ %}
 3202   interface(REG_INTER);
 3203 %}
 3204 
 3205 // revenRegP and roddRegP constitute and even-odd-pair.
 3206 operand roddRegP() %{
 3207   constraint(ALLOC_IN_RC(z_rarg4_ptr_reg));
 3208   match(iRegP);
 3209   format %{ %}
 3210   interface(REG_INTER);
 3211 %}
 3212 
 3213 operand lock_ptr_RegP() %{
 3214   constraint(ALLOC_IN_RC(z_lock_ptr_reg));
 3215   match(RegP);
 3216   format %{ %}
 3217   interface(REG_INTER);
 3218 %}
 3219 
 3220 operand rscratch2RegP() %{
 3221   constraint(ALLOC_IN_RC(z_rscratch2_bits64_reg));
 3222   match(RegP);
 3223   format %{ %}
 3224   interface(REG_INTER);
 3225 %}
 3226 
 3227 operand iRegN() %{
 3228   constraint(ALLOC_IN_RC(z_int_reg));
 3229   match(RegN);
 3230   match(noArg_iRegN);
 3231   match(rarg1RegN);
 3232   match(rarg2RegN);
 3233   match(rarg3RegN);
 3234   match(rarg4RegN);
 3235   match(rarg5RegN);
 3236   format %{ %}
 3237   interface(REG_INTER);
 3238 %}
 3239 
 3240 operand noArg_iRegN() %{
 3241   constraint(ALLOC_IN_RC(z_no_arg_int_reg));
 3242   match(iRegN);
 3243   format %{ %}
 3244   interface(REG_INTER);
 3245 %}
 3246 
 3247 operand rarg1RegN() %{
 3248   constraint(ALLOC_IN_RC(z_rarg1_int_reg));
 3249   match(iRegN);
 3250   format %{ %}
 3251   interface(REG_INTER);
 3252 %}
 3253 
 3254 operand rarg2RegN() %{
 3255   constraint(ALLOC_IN_RC(z_rarg2_int_reg));
 3256   match(iRegN);
 3257   format %{ %}
 3258   interface(REG_INTER);
 3259 %}
 3260 
 3261 operand rarg3RegN() %{
 3262   constraint(ALLOC_IN_RC(z_rarg3_int_reg));
 3263   match(iRegN);
 3264   format %{ %}
 3265   interface(REG_INTER);
 3266 %}
 3267 
 3268 operand rarg4RegN() %{
 3269   constraint(ALLOC_IN_RC(z_rarg4_int_reg));
 3270   match(iRegN);
 3271   format %{ %}
 3272   interface(REG_INTER);
 3273 %}
 3274 
 3275 operand rarg5RegN() %{
 3276   constraint(ALLOC_IN_RC(z_rarg5_ptrN_reg));
 3277   match(iRegN);
 3278   format %{ %}
 3279   interface(REG_INTER);
 3280 %}
 3281 
 3282 // Long Register
 3283 operand iRegL() %{
 3284   constraint(ALLOC_IN_RC(z_long_reg));
 3285   match(RegL);
 3286   match(revenRegL);
 3287   match(roddRegL);
 3288   match(allRoddRegL);
 3289   match(rarg1RegL);
 3290   match(rarg5RegL);
 3291   format %{ %}
 3292   interface(REG_INTER);
 3293 %}
 3294 
 3295 // revenRegL and roddRegL constitute and even-odd-pair.
 3296 operand revenRegL() %{
 3297   constraint(ALLOC_IN_RC(z_rarg3_long_reg));
 3298   match(iRegL);
 3299   format %{ %}
 3300   interface(REG_INTER);
 3301 %}
 3302 
 3303 // revenRegL and roddRegL constitute and even-odd-pair.
 3304 operand roddRegL() %{
 3305   constraint(ALLOC_IN_RC(z_rarg4_long_reg));
 3306   match(iRegL);
 3307   format %{ %}
 3308   interface(REG_INTER);
 3309 %}
 3310 
 3311 // available odd registers for iRegL
 3312 operand allRoddRegL() %{
 3313   constraint(ALLOC_IN_RC(z_long_odd_reg));
 3314   match(iRegL);
 3315   format %{ %}
 3316   interface(REG_INTER);
 3317 %}
 3318 
 3319 operand rarg1RegL() %{
 3320   constraint(ALLOC_IN_RC(z_rarg1_long_reg));
 3321   match(iRegL);
 3322   format %{ %}
 3323   interface(REG_INTER);
 3324 %}
 3325 
 3326 operand rarg5RegL() %{
 3327   constraint(ALLOC_IN_RC(z_rarg5_long_reg));
 3328   match(iRegL);
 3329   format %{ %}
 3330   interface(REG_INTER);
 3331 %}
 3332 
 3333 // Condition Code Flag Registers
 3334 operand flagsReg() %{
 3335   constraint(ALLOC_IN_RC(z_condition_reg));
 3336   match(RegFlags);
 3337   format %{ "CR" %}
 3338   interface(REG_INTER);
 3339 %}
 3340 
 3341 // Condition Code Flag Registers for rules with result tuples
 3342 operand TD_flagsReg() %{
 3343   constraint(ALLOC_IN_RC(z_condition_reg));
 3344   match(RegFlags);
 3345   format %{ "CR" %}
 3346   interface(REG_TUPLE_DEST_INTER);
 3347 %}
 3348 
 3349 operand regD() %{
 3350   constraint(ALLOC_IN_RC(z_dbl_reg));
 3351   match(RegD);
 3352   format %{ %}
 3353   interface(REG_INTER);
 3354 %}
 3355 
 3356 operand rscratchRegD() %{
 3357   constraint(ALLOC_IN_RC(z_rscratch1_dbl_reg));
 3358   match(RegD);
 3359   format %{ %}
 3360   interface(REG_INTER);
 3361 %}
 3362 
 3363 operand regF() %{
 3364   constraint(ALLOC_IN_RC(z_flt_reg));
 3365   match(RegF);
 3366   format %{ %}
 3367   interface(REG_INTER);
 3368 %}
 3369 
 3370 operand rscratchRegF() %{
 3371   constraint(ALLOC_IN_RC(z_rscratch1_flt_reg));
 3372   match(RegF);
 3373   format %{ %}
 3374   interface(REG_INTER);
 3375 %}
 3376 
 3377 // Special Registers
 3378 
 3379 // Method Register
 3380 operand inline_cache_regP(iRegP reg) %{
 3381   constraint(ALLOC_IN_RC(z_r9_regP)); // inline_cache_reg
 3382   match(reg);
 3383   format %{ %}
 3384   interface(REG_INTER);
 3385 %}
 3386 
 3387 // Operands to remove register moves in unscaled mode.
 3388 // Match read/write registers with an EncodeP node if neither shift nor add are required.
 3389 operand iRegP2N(iRegP reg) %{
 3390   predicate(CompressedOops::shift() == 0 && _leaf->as_EncodeP()->in(0) == NULL);
 3391   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3392   match(EncodeP reg);
 3393   format %{ "$reg" %}
 3394   interface(REG_INTER)
 3395 %}
 3396 
 3397 operand iRegN2P(iRegN reg) %{
 3398   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0 &&
 3399             _leaf->as_DecodeN()->in(0) == NULL);
 3400   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3401   match(DecodeN reg);
 3402   format %{ "$reg" %}
 3403   interface(REG_INTER)
 3404 %}
 3405 
 3406 
 3407 //----------Complex Operands---------------------------------------------------
 3408 
 3409 // Indirect Memory Reference
 3410 operand indirect(memoryRegP base) %{
 3411   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3412   match(base);
 3413   op_cost(1);
 3414   format %{ "#0[,$base]" %}
 3415   interface(MEMORY_INTER) %{
 3416     base($base);
 3417     index(0xffffFFFF); // noreg
 3418     scale(0x0);
 3419     disp(0x0);
 3420   %}
 3421 %}
 3422 
 3423 // Indirect with Offset (long)
 3424 operand indOffset20(memoryRegP base, immL20 offset) %{
 3425   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3426   match(AddP base offset);
 3427   op_cost(1);
 3428   format %{ "$offset[,$base]" %}
 3429   interface(MEMORY_INTER) %{
 3430     base($base);
 3431     index(0xffffFFFF); // noreg
 3432     scale(0x0);
 3433     disp($offset);
 3434   %}
 3435 %}
 3436 
 3437 operand indOffset20Narrow(iRegN base, immL20 offset) %{
 3438   predicate(Matcher::narrow_oop_use_complex_address());
 3439   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3440   match(AddP (DecodeN base) offset);
 3441   op_cost(1);
 3442   format %{ "$offset[,$base]" %}
 3443   interface(MEMORY_INTER) %{
 3444     base($base);
 3445     index(0xffffFFFF); // noreg
 3446     scale(0x0);
 3447     disp($offset);
 3448   %}
 3449 %}
 3450 
 3451 // Indirect with Offset (short)
 3452 operand indOffset12(memoryRegP base, uimmL12 offset) %{
 3453   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3454   match(AddP base offset);
 3455   op_cost(1);
 3456   format %{ "$offset[[,$base]]" %}
 3457   interface(MEMORY_INTER) %{
 3458     base($base);
 3459     index(0xffffFFFF); // noreg
 3460     scale(0x0);
 3461     disp($offset);
 3462   %}
 3463 %}
 3464 
 3465 operand indOffset12Narrow(iRegN base, uimmL12 offset) %{
 3466   predicate(Matcher::narrow_oop_use_complex_address());
 3467   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3468   match(AddP (DecodeN base) offset);
 3469   op_cost(1);
 3470   format %{ "$offset[[,$base]]" %}
 3471   interface(MEMORY_INTER) %{
 3472     base($base);
 3473     index(0xffffFFFF); // noreg
 3474     scale(0x0);
 3475     disp($offset);
 3476   %}
 3477 %}
 3478 
 3479 // Indirect with Register Index
 3480 operand indIndex(memoryRegP base, iRegL index) %{
 3481   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3482   match(AddP base index);
 3483   op_cost(1);
 3484   format %{ "#0[($index,$base)]" %}
 3485   interface(MEMORY_INTER) %{
 3486     base($base);
 3487     index($index);
 3488     scale(0x0);
 3489     disp(0x0);
 3490   %}
 3491 %}
 3492 
 3493 // Indirect with Offset (long) and index
 3494 operand indOffset20index(memoryRegP base, immL20 offset, iRegL index) %{
 3495   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3496   match(AddP (AddP base index) offset);
 3497   op_cost(1);
 3498   format %{ "$offset[($index,$base)]" %}
 3499   interface(MEMORY_INTER) %{
 3500     base($base);
 3501     index($index);
 3502     scale(0x0);
 3503     disp($offset);
 3504   %}
 3505 %}
 3506 
 3507 operand indOffset20indexNarrow(iRegN base, immL20 offset, iRegL index) %{
 3508   predicate(Matcher::narrow_oop_use_complex_address());
 3509   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3510   match(AddP (AddP (DecodeN base) index) offset);
 3511   op_cost(1);
 3512   format %{ "$offset[($index,$base)]" %}
 3513   interface(MEMORY_INTER) %{
 3514     base($base);
 3515     index($index);
 3516     scale(0x0);
 3517     disp($offset);
 3518   %}
 3519 %}
 3520 
 3521 // Indirect with Offset (short) and index
 3522 operand indOffset12index(memoryRegP base, uimmL12 offset, iRegL index) %{
 3523   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3524   match(AddP (AddP base index) offset);
 3525   op_cost(1);
 3526   format %{ "$offset[[($index,$base)]]" %}
 3527   interface(MEMORY_INTER) %{
 3528     base($base);
 3529     index($index);
 3530     scale(0x0);
 3531     disp($offset);
 3532   %}
 3533 %}
 3534 
 3535 operand indOffset12indexNarrow(iRegN base, uimmL12 offset, iRegL index) %{
 3536   predicate(Matcher::narrow_oop_use_complex_address());
 3537   constraint(ALLOC_IN_RC(z_memory_ptr_reg));
 3538   match(AddP (AddP (DecodeN base) index) offset);
 3539   op_cost(1);
 3540   format %{ "$offset[[($index,$base)]]" %}
 3541   interface(MEMORY_INTER) %{
 3542     base($base);
 3543     index($index);
 3544     scale(0x0);
 3545     disp($offset);
 3546   %}
 3547 %}
 3548 
 3549 //----------Special Memory Operands--------------------------------------------
 3550 
 3551 // Stack Slot Operand
 3552 // This operand is used for loading and storing temporary values on
 3553 // the stack where a match requires a value to flow through memory.
 3554 operand stackSlotI(sRegI reg) %{
 3555   constraint(ALLOC_IN_RC(stack_slots));
 3556   op_cost(1);
 3557   format %{ "[$reg(stackSlotI)]" %}
 3558   interface(MEMORY_INTER) %{
 3559     base(0xf);   // Z_SP
 3560     index(0xffffFFFF); // noreg
 3561     scale(0x0);
 3562     disp($reg);  // stack offset
 3563   %}
 3564 %}
 3565 
 3566 operand stackSlotP(sRegP reg) %{
 3567   constraint(ALLOC_IN_RC(stack_slots));
 3568   op_cost(1);
 3569   format %{ "[$reg(stackSlotP)]" %}
 3570   interface(MEMORY_INTER) %{
 3571     base(0xf);   // Z_SP
 3572     index(0xffffFFFF); // noreg
 3573     scale(0x0);
 3574     disp($reg);  // Stack Offset
 3575   %}
 3576 %}
 3577 
 3578 operand stackSlotF(sRegF reg) %{
 3579   constraint(ALLOC_IN_RC(stack_slots));
 3580   op_cost(1);
 3581   format %{ "[$reg(stackSlotF)]" %}
 3582   interface(MEMORY_INTER) %{
 3583     base(0xf);   // Z_SP
 3584     index(0xffffFFFF); // noreg
 3585     scale(0x0);
 3586     disp($reg);  // Stack Offset
 3587   %}
 3588 %}
 3589 
 3590 operand stackSlotD(sRegD reg) %{
 3591   constraint(ALLOC_IN_RC(stack_slots));
 3592   op_cost(1);
 3593   //match(RegD);
 3594   format %{ "[$reg(stackSlotD)]" %}
 3595   interface(MEMORY_INTER) %{
 3596     base(0xf);   // Z_SP
 3597     index(0xffffFFFF); // noreg
 3598     scale(0x0);
 3599     disp($reg);  // Stack Offset
 3600   %}
 3601 %}
 3602 
 3603 operand stackSlotL(sRegL reg) %{
 3604   constraint(ALLOC_IN_RC(stack_slots));
 3605   op_cost(1);  //match(RegL);
 3606   format %{ "[$reg(stackSlotL)]" %}
 3607   interface(MEMORY_INTER) %{
 3608     base(0xf);   // Z_SP
 3609     index(0xffffFFFF); // noreg
 3610     scale(0x0);
 3611     disp($reg);  // Stack Offset
 3612   %}
 3613 %}
 3614 
 3615 // Operands for expressing Control Flow
 3616 // NOTE: Label is a predefined operand which should not be redefined in
 3617 // the AD file. It is generically handled within the ADLC.
 3618 
 3619 //----------Conditional Branch Operands----------------------------------------
 3620 // Comparison Op  - This is the operation of the comparison, and is limited to
 3621 //                  the following set of codes:
 3622 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
 3623 //
 3624 // Other attributes of the comparison, such as unsignedness, are specified
 3625 // by the comparison instruction that sets a condition code flags register.
 3626 // That result is represented by a flags operand whose subtype is appropriate
 3627 // to the unsignedness (etc.) of the comparison.
 3628 //
 3629 // Later, the instruction which matches both the Comparison Op (a Bool) and
 3630 // the flags (produced by the Cmp) specifies the coding of the comparison op
 3631 // by matching a specific subtype of Bool operand below.
 3632 
 3633 // INT cmpOps for CompareAndBranch and CompareAndTrap instructions should not
 3634 // have mask bit #3 set.
 3635 operand cmpOpT() %{
 3636   match(Bool);
 3637   format %{ "" %}
 3638   interface(COND_INTER) %{
 3639     equal(0x8);         // Assembler::bcondEqual
 3640     not_equal(0x6);     // Assembler::bcondNotEqual
 3641     less(0x4);          // Assembler::bcondLow
 3642     greater_equal(0xa); // Assembler::bcondNotLow
 3643     less_equal(0xc);    // Assembler::bcondNotHigh
 3644     greater(0x2);       // Assembler::bcondHigh
 3645     overflow(0x1);      // Assembler::bcondOverflow
 3646     no_overflow(0xe);   // Assembler::bcondNotOverflow
 3647   %}
 3648 %}
 3649 
 3650 // When used for floating point comparisons: unordered is treated as less.
 3651 operand cmpOpF() %{
 3652   match(Bool);
 3653   format %{ "" %}
 3654   interface(COND_INTER) %{
 3655     equal(0x8);
 3656     not_equal(0x7);     // Includes 'unordered'.
 3657     less(0x5);          // Includes 'unordered'.
 3658     greater_equal(0xa);
 3659     less_equal(0xd);    // Includes 'unordered'.
 3660     greater(0x2);
 3661     overflow(0x0);      // Not meaningful on z/Architecture.
 3662     no_overflow(0x0);   // leave unchanged (zero) therefore
 3663   %}
 3664 %}
 3665 
 3666 // "Regular" cmpOp for int comparisons, includes bit #3 (overflow).
 3667 operand cmpOp() %{
 3668   match(Bool);
 3669   format %{ "" %}
 3670   interface(COND_INTER) %{
 3671     equal(0x8);
 3672     not_equal(0x7);     // Includes 'unordered'.
 3673     less(0x5);          // Includes 'unordered'.
 3674     greater_equal(0xa);
 3675     less_equal(0xd);    // Includes 'unordered'.
 3676     greater(0x2);
 3677     overflow(0x1);      // Assembler::bcondOverflow
 3678     no_overflow(0xe);   // Assembler::bcondNotOverflow
 3679   %}
 3680 %}
 3681 
 3682 //----------OPERAND CLASSES----------------------------------------------------
 3683 // Operand Classes are groups of operands that are used to simplify
 3684 // instruction definitions by not requiring the AD writer to specify
 3685 // seperate instructions for every form of operand when the
 3686 // instruction accepts multiple operand types with the same basic
 3687 // encoding and format.  The classic case of this is memory operands.
 3688 // Indirect is not included since its use is limited to Compare & Swap
 3689 
 3690 // Most general memory operand, allows base, index, and long displacement.
 3691 opclass memory(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
 3692 opclass memoryRXY(indirect, indIndex, indOffset20, indOffset20Narrow, indOffset20index, indOffset20indexNarrow);
 3693 
 3694 // General memory operand, allows base, index, and short displacement.
 3695 opclass memoryRX(indirect, indIndex, indOffset12, indOffset12Narrow, indOffset12index, indOffset12indexNarrow);
 3696 
 3697 // Memory operand, allows only base and long displacement.
 3698 opclass memoryRSY(indirect, indOffset20, indOffset20Narrow);
 3699 
 3700 // Memory operand, allows only base and short displacement.
 3701 opclass memoryRS(indirect, indOffset12, indOffset12Narrow);
 3702 
 3703 // Operand classes to match encode and decode.
 3704 opclass iRegN_P2N(iRegN);
 3705 opclass iRegP_N2P(iRegP);
 3706 
 3707 
 3708 //----------PIPELINE-----------------------------------------------------------
 3709 pipeline %{
 3710 
 3711 //----------ATTRIBUTES---------------------------------------------------------
 3712 attributes %{
 3713   // z/Architecture instructions are of length 2, 4, or 6 bytes.
 3714   variable_size_instructions;
 3715   instruction_unit_size = 2;
 3716 
 3717   // Meaningless on z/Architecture.
 3718   max_instructions_per_bundle = 1;
 3719 
 3720   // The z/Architecture processor fetches 64 bytes...
 3721   instruction_fetch_unit_size = 64;
 3722 
 3723   // ...in one line.
 3724   instruction_fetch_units = 1
 3725 %}
 3726 
 3727 //----------RESOURCES----------------------------------------------------------
 3728 // Resources are the functional units available to the machine.
 3729 resources(
 3730    Z_BR,     // branch unit
 3731    Z_CR,     // condition unit
 3732    Z_FX1,    // integer arithmetic unit 1
 3733    Z_FX2,    // integer arithmetic unit 2
 3734    Z_LDST1,  // load/store unit 1
 3735    Z_LDST2,  // load/store unit 2
 3736    Z_FP1,    // float arithmetic unit 1
 3737    Z_FP2,    // float arithmetic unit 2
 3738    Z_LDST = Z_LDST1 | Z_LDST2,
 3739    Z_FX   = Z_FX1 | Z_FX2,
 3740    Z_FP   = Z_FP1 | Z_FP2
 3741   );
 3742 
 3743 //----------PIPELINE DESCRIPTION-----------------------------------------------
 3744 // Pipeline Description specifies the stages in the machine's pipeline.
 3745 pipe_desc(
 3746    // TODO: adapt
 3747    Z_IF,  // instruction fetch
 3748    Z_IC,
 3749    Z_D0,  // decode
 3750    Z_D1,  // decode
 3751    Z_D2,  // decode
 3752    Z_D3,  // decode
 3753    Z_Xfer1,
 3754    Z_GD,  // group definition
 3755    Z_MP,  // map
 3756    Z_ISS, // issue
 3757    Z_RF,  // resource fetch
 3758    Z_EX1, // execute (all units)
 3759    Z_EX2, // execute (FP, LDST)
 3760    Z_EX3, // execute (FP, LDST)
 3761    Z_EX4, // execute (FP)
 3762    Z_EX5, // execute (FP)
 3763    Z_EX6, // execute (FP)
 3764    Z_WB,  // write back
 3765    Z_Xfer2,
 3766    Z_CP
 3767   );
 3768 
 3769 //----------PIPELINE CLASSES---------------------------------------------------
 3770 // Pipeline Classes describe the stages in which input and output are
 3771 // referenced by the hardware pipeline.
 3772 
 3773 // Providing the `ins_pipe' declarations in the instruction
 3774 // specifications seems to be of little use. So we use
 3775 // `pipe_class_dummy' for all our instructions at present.
 3776 pipe_class pipe_class_dummy() %{
 3777   single_instruction;
 3778   fixed_latency(4);
 3779 %}
 3780 
 3781 // SIGTRAP based implicit range checks in compiled code.
 3782 // Currently, no pipe classes are used on z/Architecture.
 3783 pipe_class pipe_class_trap() %{
 3784   single_instruction;
 3785 %}
 3786 
 3787 pipe_class pipe_class_fx_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
 3788   single_instruction;
 3789   dst  : Z_EX1(write);
 3790   src1 : Z_RF(read);
 3791   src2 : Z_RF(read);
 3792   Z_FX : Z_RF;
 3793 %}
 3794 
 3795 pipe_class pipe_class_ldst(iRegP dst, memory mem) %{
 3796   single_instruction;
 3797   mem : Z_RF(read);
 3798   dst : Z_WB(write);
 3799   Z_LDST : Z_RF;
 3800 %}
 3801 
 3802 define %{
 3803   MachNop = pipe_class_dummy;
 3804 %}
 3805 
 3806 %}
 3807 
 3808 //----------INSTRUCTIONS-------------------------------------------------------
 3809 
 3810 //---------- Chain stack slots between similar types --------
 3811 
 3812 // Load integer from stack slot.
 3813 instruct stkI_to_regI(iRegI dst, stackSlotI src) %{
 3814   match(Set dst src);
 3815   ins_cost(MEMORY_REF_COST);
 3816   // TODO: s390 port size(FIXED_SIZE);
 3817   format %{ "L       $dst,$src\t # stk reload int" %}
 3818   opcode(L_ZOPC);
 3819   ins_encode(z_form_rt_mem(dst, src));
 3820   ins_pipe(pipe_class_dummy);
 3821 %}
 3822 
 3823 // Store integer to stack slot.
 3824 instruct regI_to_stkI(stackSlotI dst, iRegI src) %{
 3825   match(Set dst src);
 3826   ins_cost(MEMORY_REF_COST);
 3827   // TODO: s390 port size(FIXED_SIZE);
 3828   format %{ "ST      $src,$dst\t # stk spill int" %}
 3829   opcode(ST_ZOPC);
 3830   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3831   ins_pipe(pipe_class_dummy);
 3832 %}
 3833 
 3834 // Load long from stack slot.
 3835 instruct stkL_to_regL(iRegL dst, stackSlotL src) %{
 3836   match(Set dst src);
 3837   ins_cost(MEMORY_REF_COST);
 3838   // TODO: s390 port size(FIXED_SIZE);
 3839   format %{ "LG      $dst,$src\t # stk reload long" %}
 3840   opcode(LG_ZOPC);
 3841   ins_encode(z_form_rt_mem(dst, src));
 3842   ins_pipe(pipe_class_dummy);
 3843 %}
 3844 
 3845 // Store long to stack slot.
 3846 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
 3847   match(Set dst src);
 3848   ins_cost(MEMORY_REF_COST);
 3849   size(6);
 3850   format %{ "STG     $src,$dst\t # stk spill long" %}
 3851   opcode(STG_ZOPC);
 3852   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3853   ins_pipe(pipe_class_dummy);
 3854 %}
 3855 
 3856 // Load pointer from stack slot, 64-bit encoding.
 3857 instruct stkP_to_regP(iRegP dst, stackSlotP src) %{
 3858   match(Set dst src);
 3859   ins_cost(MEMORY_REF_COST);
 3860   // TODO: s390 port size(FIXED_SIZE);
 3861   format %{ "LG      $dst,$src\t # stk reload ptr" %}
 3862   opcode(LG_ZOPC);
 3863   ins_encode(z_form_rt_mem(dst, src));
 3864   ins_pipe(pipe_class_dummy);
 3865 %}
 3866 
 3867 // Store pointer to stack slot.
 3868 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
 3869   match(Set dst src);
 3870   ins_cost(MEMORY_REF_COST);
 3871   // TODO: s390 port size(FIXED_SIZE);
 3872   format %{ "STG     $src,$dst\t # stk spill ptr" %}
 3873   opcode(STG_ZOPC);
 3874   ins_encode(z_form_rt_mem(src, dst)); // rs=rt
 3875   ins_pipe(pipe_class_dummy);
 3876 %}
 3877 
 3878 //  Float types
 3879 
 3880 // Load float value from stack slot.
 3881 instruct stkF_to_regF(regF dst, stackSlotF src) %{
 3882   match(Set dst src);
 3883   ins_cost(MEMORY_REF_COST);
 3884   size(4);
 3885   format %{ "LE(Y)   $dst,$src\t # stk reload float" %}
 3886   opcode(LE_ZOPC);
 3887   ins_encode(z_form_rt_mem(dst, src));
 3888   ins_pipe(pipe_class_dummy);
 3889 %}
 3890 
 3891 // Store float value to stack slot.
 3892 instruct regF_to_stkF(stackSlotF dst, regF src) %{
 3893   match(Set dst src);
 3894   ins_cost(MEMORY_REF_COST);
 3895   size(4);
 3896   format %{ "STE(Y)  $src,$dst\t # stk spill float" %}
 3897   opcode(STE_ZOPC);
 3898   ins_encode(z_form_rt_mem(src, dst));
 3899   ins_pipe(pipe_class_dummy);
 3900 %}
 3901 
 3902 // Load double value from stack slot.
 3903 instruct stkD_to_regD(regD dst, stackSlotD src) %{
 3904   match(Set dst src);
 3905   ins_cost(MEMORY_REF_COST);
 3906   // TODO: s390 port size(FIXED_SIZE);
 3907   format %{ "LD(Y)   $dst,$src\t # stk reload double" %}
 3908   opcode(LD_ZOPC);
 3909   ins_encode(z_form_rt_mem(dst, src));
 3910   ins_pipe(pipe_class_dummy);
 3911 %}
 3912 
 3913 // Store double value to stack slot.
 3914 instruct regD_to_stkD(stackSlotD dst, regD src) %{
 3915   match(Set dst src);
 3916   ins_cost(MEMORY_REF_COST);
 3917   size(4);
 3918   format %{ "STD(Y)  $src,$dst\t # stk spill double" %}
 3919   opcode(STD_ZOPC);
 3920   ins_encode(z_form_rt_mem(src, dst));
 3921   ins_pipe(pipe_class_dummy);
 3922 %}
 3923 
 3924 //----------Load/Store/Move Instructions---------------------------------------
 3925 
 3926 //----------Load Instructions--------------------------------------------------
 3927 
 3928 //------------------
 3929 //  MEMORY
 3930 //------------------
 3931 
 3932 //  BYTE
 3933 // Load Byte (8bit signed)
 3934 instruct loadB(iRegI dst, memory mem) %{
 3935   match(Set dst (LoadB mem));
 3936   ins_cost(MEMORY_REF_COST);
 3937   size(Z_DISP3_SIZE);
 3938   format %{ "LB      $dst, $mem\t # sign-extend byte to int" %}
 3939   opcode(LB_ZOPC, LB_ZOPC);
 3940   ins_encode(z_form_rt_mem_opt(dst, mem));
 3941   ins_pipe(pipe_class_dummy);
 3942 %}
 3943 
 3944 // Load Byte (8bit signed)
 3945 instruct loadB2L(iRegL dst, memory mem) %{
 3946   match(Set dst (ConvI2L (LoadB mem)));
 3947   ins_cost(MEMORY_REF_COST);
 3948   size(Z_DISP3_SIZE);
 3949   format %{ "LGB     $dst, $mem\t # sign-extend byte to long" %}
 3950   opcode(LGB_ZOPC, LGB_ZOPC);
 3951   ins_encode(z_form_rt_mem_opt(dst, mem));
 3952   ins_pipe(pipe_class_dummy);
 3953 %}
 3954 
 3955 // Load Unsigned Byte (8bit UNsigned) into an int reg.
 3956 instruct loadUB(iRegI dst, memory mem) %{
 3957   match(Set dst (LoadUB mem));
 3958   ins_cost(MEMORY_REF_COST);
 3959   size(Z_DISP3_SIZE);
 3960   format %{ "LLGC    $dst,$mem\t # zero-extend byte to int" %}
 3961   opcode(LLGC_ZOPC, LLGC_ZOPC);
 3962   ins_encode(z_form_rt_mem_opt(dst, mem));
 3963   ins_pipe(pipe_class_dummy);
 3964 %}
 3965 
 3966 // Load Unsigned Byte (8bit UNsigned) into a Long Register.
 3967 instruct loadUB2L(iRegL dst, memory mem) %{
 3968   match(Set dst (ConvI2L (LoadUB mem)));
 3969   ins_cost(MEMORY_REF_COST);
 3970   size(Z_DISP3_SIZE);
 3971   format %{ "LLGC    $dst,$mem\t # zero-extend byte to long" %}
 3972   opcode(LLGC_ZOPC, LLGC_ZOPC);
 3973   ins_encode(z_form_rt_mem_opt(dst, mem));
 3974   ins_pipe(pipe_class_dummy);
 3975 %}
 3976 
 3977 // CHAR/SHORT
 3978 
 3979 // Load Short (16bit signed)
 3980 instruct loadS(iRegI dst, memory mem) %{
 3981   match(Set dst (LoadS mem));
 3982   ins_cost(MEMORY_REF_COST);
 3983   size(Z_DISP_SIZE);
 3984   format %{ "LH(Y)   $dst,$mem\t # sign-extend short to int" %}
 3985   opcode(LHY_ZOPC, LH_ZOPC);
 3986   ins_encode(z_form_rt_mem_opt(dst, mem));
 3987   ins_pipe(pipe_class_dummy);
 3988 %}
 3989 
 3990 // Load Short (16bit signed)
 3991 instruct loadS2L(iRegL dst, memory mem) %{
 3992   match(Set dst (ConvI2L (LoadS mem)));
 3993   ins_cost(MEMORY_REF_COST);
 3994   size(Z_DISP3_SIZE);
 3995   format %{ "LGH     $dst,$mem\t # sign-extend short to long" %}
 3996   opcode(LGH_ZOPC, LGH_ZOPC);
 3997   ins_encode(z_form_rt_mem_opt(dst, mem));
 3998   ins_pipe(pipe_class_dummy);
 3999 %}
 4000 
 4001 // Load Char (16bit Unsigned)
 4002 instruct loadUS(iRegI dst, memory mem) %{
 4003   match(Set dst (LoadUS mem));
 4004   ins_cost(MEMORY_REF_COST);
 4005   size(Z_DISP3_SIZE);
 4006   format %{ "LLGH    $dst,$mem\t # zero-extend short to int" %}
 4007   opcode(LLGH_ZOPC, LLGH_ZOPC);
 4008   ins_encode(z_form_rt_mem_opt(dst, mem));
 4009   ins_pipe(pipe_class_dummy);
 4010 %}
 4011 
 4012 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register.
 4013 instruct loadUS2L(iRegL dst, memory mem) %{
 4014   match(Set dst (ConvI2L (LoadUS mem)));
 4015   ins_cost(MEMORY_REF_COST);
 4016   size(Z_DISP3_SIZE);
 4017   format %{ "LLGH    $dst,$mem\t # zero-extend short to long" %}
 4018   opcode(LLGH_ZOPC, LLGH_ZOPC);
 4019   ins_encode(z_form_rt_mem_opt(dst, mem));
 4020   ins_pipe(pipe_class_dummy);
 4021 %}
 4022 
 4023 // INT
 4024 
 4025 // Load Integer
 4026 instruct loadI(iRegI dst, memory mem) %{
 4027   match(Set dst (LoadI mem));
 4028   ins_cost(MEMORY_REF_COST);
 4029   size(Z_DISP_SIZE);
 4030   format %{ "L(Y)    $dst,$mem\t #" %}
 4031   opcode(LY_ZOPC, L_ZOPC);
 4032   ins_encode(z_form_rt_mem_opt(dst, mem));
 4033   ins_pipe(pipe_class_dummy);
 4034 %}
 4035 
 4036 // Load and convert to long.
 4037 instruct loadI2L(iRegL dst, memory mem) %{
 4038   match(Set dst (ConvI2L (LoadI mem)));
 4039   ins_cost(MEMORY_REF_COST);
 4040   size(Z_DISP3_SIZE);
 4041   format %{ "LGF     $dst,$mem\t #" %}
 4042   opcode(LGF_ZOPC, LGF_ZOPC);
 4043   ins_encode(z_form_rt_mem_opt(dst, mem));
 4044   ins_pipe(pipe_class_dummy);
 4045 %}
 4046 
 4047 // Load Unsigned Integer into a Long Register
 4048 instruct loadUI2L(iRegL dst, memory mem, immL_FFFFFFFF mask) %{
 4049   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
 4050   ins_cost(MEMORY_REF_COST);
 4051   size(Z_DISP3_SIZE);
 4052   format %{ "LLGF    $dst,$mem\t # zero-extend int to long" %}
 4053   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4054   ins_encode(z_form_rt_mem_opt(dst, mem));
 4055   ins_pipe(pipe_class_dummy);
 4056 %}
 4057 
 4058 // range = array length (=jint)
 4059 // Load Range
 4060 instruct loadRange(iRegI dst, memory mem) %{
 4061   match(Set dst (LoadRange mem));
 4062   ins_cost(MEMORY_REF_COST);
 4063   size(Z_DISP_SIZE);
 4064   format %{ "L(Y)    $dst,$mem\t # range" %}
 4065   opcode(LY_ZOPC, L_ZOPC);
 4066   ins_encode(z_form_rt_mem_opt(dst, mem));
 4067   ins_pipe(pipe_class_dummy);
 4068 %}
 4069 
 4070 // LONG
 4071 
 4072 // Load Long - aligned
 4073 instruct loadL(iRegL dst, memory mem) %{
 4074   match(Set dst (LoadL mem));
 4075   ins_cost(MEMORY_REF_COST);
 4076   size(Z_DISP3_SIZE);
 4077   format %{ "LG      $dst,$mem\t # long" %}
 4078   opcode(LG_ZOPC, LG_ZOPC);
 4079   ins_encode(z_form_rt_mem_opt(dst, mem));
 4080   ins_pipe(pipe_class_dummy);
 4081 %}
 4082 
 4083 // Load Long - UNaligned
 4084 instruct loadL_unaligned(iRegL dst, memory mem) %{
 4085   match(Set dst (LoadL_unaligned mem));
 4086   ins_cost(MEMORY_REF_COST);
 4087   size(Z_DISP3_SIZE);
 4088   format %{ "LG      $dst,$mem\t # unaligned long" %}
 4089   opcode(LG_ZOPC, LG_ZOPC);
 4090   ins_encode(z_form_rt_mem_opt(dst, mem));
 4091   ins_pipe(pipe_class_dummy);
 4092 %}
 4093 
 4094 
 4095 // PTR
 4096 
 4097 // Load Pointer
 4098 instruct loadP(iRegP dst, memory mem) %{
 4099   match(Set dst (LoadP mem));
 4100   ins_cost(MEMORY_REF_COST);
 4101   size(Z_DISP3_SIZE);
 4102   format %{ "LG      $dst,$mem\t # ptr" %}
 4103   opcode(LG_ZOPC, LG_ZOPC);
 4104   ins_encode(z_form_rt_mem_opt(dst, mem));
 4105   ins_pipe(pipe_class_dummy);
 4106 %}
 4107 
 4108 // LoadP + CastP2L
 4109 instruct castP2X_loadP(iRegL dst, memory mem) %{
 4110   match(Set dst (CastP2X (LoadP mem)));
 4111   ins_cost(MEMORY_REF_COST);
 4112   size(Z_DISP3_SIZE);
 4113   format %{ "LG      $dst,$mem\t # ptr + p2x" %}
 4114   opcode(LG_ZOPC, LG_ZOPC);
 4115   ins_encode(z_form_rt_mem_opt(dst, mem));
 4116   ins_pipe(pipe_class_dummy);
 4117 %}
 4118 
 4119 // Load Klass Pointer
 4120 instruct loadKlass(iRegP dst, memory mem) %{
 4121   match(Set dst (LoadKlass mem));
 4122   ins_cost(MEMORY_REF_COST);
 4123   size(Z_DISP3_SIZE);
 4124   format %{ "LG      $dst,$mem\t # klass ptr" %}
 4125   opcode(LG_ZOPC, LG_ZOPC);
 4126   ins_encode(z_form_rt_mem_opt(dst, mem));
 4127   ins_pipe(pipe_class_dummy);
 4128 %}
 4129 
 4130 instruct loadTOC(iRegL dst) %{
 4131   effect(DEF dst);
 4132   ins_cost(DEFAULT_COST);
 4133   // TODO: s390 port size(FIXED_SIZE);
 4134   // TODO: check why this attribute causes many unnecessary rematerializations.
 4135   //
 4136   // The graphs I saw just had high register pressure. Further the
 4137   // register TOC is loaded to is overwritten by the constant short
 4138   // after. Here something as round robin register allocation might
 4139   // help. But rematerializing seems not to hurt, jack even seems to
 4140   // improve slightly.
 4141   //
 4142   // Without this flag we get spill-split recycle sanity check
 4143   // failures in
 4144   // spec.benchmarks._228_jack.NfaState::GenerateCode. This happens in
 4145   // a block with three loadConP_dynTOC nodes and a tlsLoadP. The
 4146   // tlsLoadP has a huge amount of outs and forces the TOC down to the
 4147   // stack. Later tlsLoadP is rematerialized, leaving the register
 4148   // allocator with TOC on the stack and a badly placed reload.
 4149   ins_should_rematerialize(true);
 4150   format %{ "LARL    $dst, &constant_pool\t; load dynTOC" %}
 4151   ins_encode %{ __ load_toc($dst$$Register); %}
 4152   ins_pipe(pipe_class_dummy);
 4153 %}
 4154 
 4155 // FLOAT
 4156 
 4157 // Load Float
 4158 instruct loadF(regF dst, memory mem) %{
 4159   match(Set dst (LoadF mem));
 4160   ins_cost(MEMORY_REF_COST);
 4161   size(Z_DISP_SIZE);
 4162   format %{ "LE(Y)    $dst,$mem" %}
 4163   opcode(LEY_ZOPC, LE_ZOPC);
 4164   ins_encode(z_form_rt_mem_opt(dst, mem));
 4165   ins_pipe(pipe_class_dummy);
 4166 %}
 4167 
 4168 // DOUBLE
 4169 
 4170 // Load Double
 4171 instruct loadD(regD dst, memory mem) %{
 4172   match(Set dst (LoadD mem));
 4173   ins_cost(MEMORY_REF_COST);
 4174   size(Z_DISP_SIZE);
 4175   format %{ "LD(Y)    $dst,$mem" %}
 4176   opcode(LDY_ZOPC, LD_ZOPC);
 4177   ins_encode(z_form_rt_mem_opt(dst, mem));
 4178   ins_pipe(pipe_class_dummy);
 4179 %}
 4180 
 4181 // Load Double - UNaligned
 4182 instruct loadD_unaligned(regD dst, memory mem) %{
 4183   match(Set dst (LoadD_unaligned mem));
 4184   ins_cost(MEMORY_REF_COST);
 4185   size(Z_DISP_SIZE);
 4186   format %{ "LD(Y)    $dst,$mem" %}
 4187   opcode(LDY_ZOPC, LD_ZOPC);
 4188   ins_encode(z_form_rt_mem_opt(dst, mem));
 4189   ins_pipe(pipe_class_dummy);
 4190 %}
 4191 
 4192 
 4193 //----------------------
 4194 //  IMMEDIATES
 4195 //----------------------
 4196 
 4197 instruct loadConI(iRegI dst, immI src) %{
 4198   match(Set dst src);
 4199   ins_cost(DEFAULT_COST);
 4200   size(6);
 4201   format %{ "LGFI    $dst,$src\t # (int)" %}
 4202   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4203   ins_pipe(pipe_class_dummy);
 4204 %}
 4205 
 4206 instruct loadConI16(iRegI dst, immI16 src) %{
 4207   match(Set dst src);
 4208   ins_cost(DEFAULT_COST_LOW);
 4209   size(4);
 4210   format %{ "LGHI    $dst,$src\t # (int)" %}
 4211   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4212   ins_pipe(pipe_class_dummy);
 4213 %}
 4214 
 4215 instruct loadConI_0(iRegI dst, immI_0 src, flagsReg cr) %{
 4216   match(Set dst src);
 4217   effect(KILL cr);
 4218   ins_cost(DEFAULT_COST_LOW);
 4219   size(4);
 4220   format %{ "loadConI $dst,$src\t # (int) XGR because ZERO is loaded" %}
 4221   opcode(XGR_ZOPC);
 4222   ins_encode(z_rreform(dst, dst));
 4223   ins_pipe(pipe_class_dummy);
 4224 %}
 4225 
 4226 instruct loadConUI16(iRegI dst, uimmI16 src) %{
 4227   match(Set dst src);
 4228   // TODO: s390 port size(FIXED_SIZE);
 4229   format %{ "LLILL    $dst,$src" %}
 4230   opcode(LLILL_ZOPC);
 4231   ins_encode(z_riform_unsigned(dst, src) );
 4232   ins_pipe(pipe_class_dummy);
 4233 %}
 4234 
 4235 // Load long constant from TOC with pcrelative address.
 4236 instruct loadConL_pcrelTOC(iRegL dst, immL src) %{
 4237   match(Set dst src);
 4238   ins_cost(MEMORY_REF_COST_LO);
 4239   size(6);
 4240   format %{ "LGRL    $dst,[pcrelTOC]\t # load long $src from table" %}
 4241   ins_encode %{
 4242     address long_address = __ long_constant($src$$constant);
 4243     if (long_address == NULL) {
 4244       Compile::current()->env()->record_out_of_memory_failure();
 4245       return;
 4246     }
 4247     __ load_long_pcrelative($dst$$Register, long_address);
 4248   %}
 4249   ins_pipe(pipe_class_dummy);
 4250 %}
 4251 
 4252 instruct loadConL32(iRegL dst, immL32 src) %{
 4253   match(Set dst src);
 4254   ins_cost(DEFAULT_COST);
 4255   size(6);
 4256   format %{ "LGFI     $dst,$src\t # (long)" %}
 4257   ins_encode %{ __ z_lgfi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4258   ins_pipe(pipe_class_dummy);
 4259 %}
 4260 
 4261 instruct loadConL16(iRegL dst, immL16 src) %{
 4262   match(Set dst src);
 4263   ins_cost(DEFAULT_COST_LOW);
 4264   size(4);
 4265   format %{ "LGHI     $dst,$src\t # (long)" %}
 4266   ins_encode %{ __ z_lghi($dst$$Register, $src$$constant); %}  // Sign-extend to 64 bit, it's at no cost.
 4267   ins_pipe(pipe_class_dummy);
 4268 %}
 4269 
 4270 instruct loadConL_0(iRegL dst, immL_0 src, flagsReg cr) %{
 4271   match(Set dst src);
 4272   effect(KILL cr);
 4273   ins_cost(DEFAULT_COST_LOW);
 4274   format %{ "LoadConL    $dst,$src\t # (long) XGR because ZERO is loaded" %}
 4275   opcode(XGR_ZOPC);
 4276   ins_encode(z_rreform(dst, dst));
 4277   ins_pipe(pipe_class_dummy);
 4278 %}
 4279 
 4280 // Load ptr constant from TOC with pc relative address.
 4281 // Special handling for oop constants required.
 4282 instruct loadConP_pcrelTOC(iRegP dst, immP src) %{
 4283   match(Set dst src);
 4284   ins_cost(MEMORY_REF_COST_LO);
 4285   size(6);
 4286   format %{ "LGRL    $dst,[pcrelTOC]\t # load ptr $src from table" %}
 4287   ins_encode %{
 4288     relocInfo::relocType constant_reloc = $src->constant_reloc();
 4289     if (constant_reloc == relocInfo::oop_type) {
 4290       AddressLiteral a = __ allocate_oop_address((jobject)$src$$constant);
 4291       bool success = __ load_oop_from_toc($dst$$Register, a);
 4292       if (!success) {
 4293         Compile::current()->env()->record_out_of_memory_failure();
 4294         return;
 4295       }
 4296     } else if (constant_reloc == relocInfo::metadata_type) {
 4297       AddressLiteral a = __ constant_metadata_address((Metadata *)$src$$constant);
 4298       address const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none);
 4299       if (const_toc_addr == NULL) {
 4300         Compile::current()->env()->record_out_of_memory_failure();
 4301         return;
 4302       }
 4303       __ load_long_pcrelative($dst$$Register, const_toc_addr);
 4304     } else {          // Non-oop pointers, e.g. card mark base, heap top.
 4305       address long_address = __ long_constant((jlong)$src$$constant);
 4306       if (long_address == NULL) {
 4307         Compile::current()->env()->record_out_of_memory_failure();
 4308         return;
 4309       }
 4310       __ load_long_pcrelative($dst$$Register, long_address);
 4311     }
 4312   %}
 4313   ins_pipe(pipe_class_dummy);
 4314 %}
 4315 
 4316 // We don't use immP16 to avoid problems with oops.
 4317 instruct loadConP0(iRegP dst, immP0 src, flagsReg cr) %{
 4318   match(Set dst src);
 4319   effect(KILL cr);
 4320   size(4);
 4321   format %{ "XGR     $dst,$dst\t # NULL ptr" %}
 4322   opcode(XGR_ZOPC);
 4323   ins_encode(z_rreform(dst, dst));
 4324   ins_pipe(pipe_class_dummy);
 4325 %}
 4326 
 4327 //----------Load Float Constant Instructions-------------------------------------------------
 4328 
 4329 // We may not specify this instruction via an `expand' rule. If we do,
 4330 // code selection will forget that this instruction needs a floating
 4331 // point constant inserted into the code buffer. So `Shorten_branches'
 4332 // will fail.
 4333 instruct loadConF_dynTOC(regF dst, immF src, flagsReg cr) %{
 4334   match(Set dst src);
 4335   effect(KILL cr);
 4336   ins_cost(MEMORY_REF_COST);
 4337   size(6);
 4338   // If this instruction rematerializes, it prolongs the live range
 4339   // of the toc node, causing illegal graphs.
 4340   ins_cannot_rematerialize(true);
 4341   format %{ "LE(Y)    $dst,$constantoffset[,$constanttablebase]\t # load FLOAT $src from table" %}
 4342   ins_encode %{
 4343     __ load_float_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
 4344   %}
 4345   ins_pipe(pipe_class_dummy);
 4346 %}
 4347 
 4348 // E may not specify this instruction via an `expand' rule. If we do,
 4349 // code selection will forget that this instruction needs a floating
 4350 // point constant inserted into the code buffer. So `Shorten_branches'
 4351 // will fail.
 4352 instruct loadConD_dynTOC(regD dst, immD src, flagsReg cr) %{
 4353   match(Set dst src);
 4354   effect(KILL cr);
 4355   ins_cost(MEMORY_REF_COST);
 4356   size(6);
 4357   // If this instruction rematerializes, it prolongs the live range
 4358   // of the toc node, causing illegal graphs.
 4359   ins_cannot_rematerialize(true);
 4360   format %{ "LD(Y)    $dst,$constantoffset[,$constanttablebase]\t # load DOUBLE $src from table" %}
 4361   ins_encode %{
 4362     __ load_double_largeoffset($dst$$FloatRegister, $constantoffset($src), $constanttablebase, Z_R1_scratch);
 4363   %}
 4364   ins_pipe(pipe_class_dummy);
 4365 %}
 4366 
 4367 // Special case: Load Const 0.0F
 4368 
 4369 // There's a special instr to clear a FP register.
 4370 instruct loadConF0(regF dst, immFp0 src) %{
 4371   match(Set dst src);
 4372   ins_cost(DEFAULT_COST_LOW);
 4373   size(4);
 4374   format %{ "LZER     $dst,$src\t # clear to zero" %}
 4375   opcode(LZER_ZOPC);
 4376   ins_encode(z_rreform(dst, Z_F0));
 4377   ins_pipe(pipe_class_dummy);
 4378 %}
 4379 
 4380 // There's a special instr to clear a FP register.
 4381 instruct loadConD0(regD dst, immDp0 src) %{
 4382   match(Set dst src);
 4383   ins_cost(DEFAULT_COST_LOW);
 4384   size(4);
 4385   format %{ "LZDR     $dst,$src\t # clear to zero" %}
 4386   opcode(LZDR_ZOPC);
 4387   ins_encode(z_rreform(dst, Z_F0));
 4388   ins_pipe(pipe_class_dummy);
 4389 %}
 4390 
 4391 
 4392 //----------Store Instructions-------------------------------------------------
 4393 
 4394 // BYTE
 4395 
 4396 // Store Byte
 4397 instruct storeB(memory mem, iRegI src) %{
 4398   match(Set mem (StoreB mem src));
 4399   ins_cost(MEMORY_REF_COST);
 4400   size(Z_DISP_SIZE);
 4401   format %{ "STC(Y)  $src,$mem\t # byte" %}
 4402   opcode(STCY_ZOPC, STC_ZOPC);
 4403   ins_encode(z_form_rt_mem_opt(src, mem));
 4404   ins_pipe(pipe_class_dummy);
 4405 %}
 4406 
 4407 instruct storeCM(memory mem, immI_0 src) %{
 4408   match(Set mem (StoreCM mem src));
 4409   ins_cost(MEMORY_REF_COST);
 4410   // TODO: s390 port size(VARIABLE_SIZE);
 4411   format %{ "STC(Y)  $src,$mem\t # CMS card-mark byte (must be 0!)" %}
 4412   ins_encode %{
 4413     guarantee($mem$$index$$Register != Z_R0, "content will not be used.");
 4414     if ($mem$$index$$Register != noreg) {
 4415       // Can't use clear_mem --> load const zero and store character.
 4416       __ load_const_optimized(Z_R0_scratch, (long)0);
 4417       if (Immediate::is_uimm12($mem$$disp)) {
 4418         __ z_stc(Z_R0_scratch, $mem$$Address);
 4419       } else {
 4420         __ z_stcy(Z_R0_scratch, $mem$$Address);
 4421       }
 4422     } else {
 4423       __ clear_mem(Address($mem$$Address), 1);
 4424     }
 4425   %}
 4426   ins_pipe(pipe_class_dummy);
 4427 %}
 4428 
 4429 // CHAR/SHORT
 4430 
 4431 // Store Char/Short
 4432 instruct storeC(memory mem, iRegI src) %{
 4433   match(Set mem (StoreC mem src));
 4434   ins_cost(MEMORY_REF_COST);
 4435   size(Z_DISP_SIZE);
 4436   format %{ "STH(Y)  $src,$mem\t # short" %}
 4437   opcode(STHY_ZOPC, STH_ZOPC);
 4438   ins_encode(z_form_rt_mem_opt(src, mem));
 4439   ins_pipe(pipe_class_dummy);
 4440 %}
 4441 
 4442 // INT
 4443 
 4444 // Store Integer
 4445 instruct storeI(memory mem, iRegI src) %{
 4446   match(Set mem (StoreI mem src));
 4447   ins_cost(MEMORY_REF_COST);
 4448   size(Z_DISP_SIZE);
 4449   format %{ "ST(Y)   $src,$mem\t # int" %}
 4450   opcode(STY_ZOPC, ST_ZOPC);
 4451   ins_encode(z_form_rt_mem_opt(src, mem));
 4452   ins_pipe(pipe_class_dummy);
 4453 %}
 4454 
 4455 // LONG
 4456 
 4457 // Store Long
 4458 instruct storeL(memory mem, iRegL src) %{
 4459   match(Set mem (StoreL mem src));
 4460   ins_cost(MEMORY_REF_COST);
 4461   size(Z_DISP3_SIZE);
 4462   format %{ "STG     $src,$mem\t # long" %}
 4463   opcode(STG_ZOPC, STG_ZOPC);
 4464   ins_encode(z_form_rt_mem_opt(src, mem));
 4465   ins_pipe(pipe_class_dummy);
 4466 %}
 4467 
 4468 // PTR
 4469 
 4470 // Store Pointer
 4471 instruct storeP(memory dst, memoryRegP src) %{
 4472   match(Set dst (StoreP dst src));
 4473   ins_cost(MEMORY_REF_COST);
 4474   size(Z_DISP3_SIZE);
 4475   format %{ "STG     $src,$dst\t # ptr" %}
 4476   opcode(STG_ZOPC, STG_ZOPC);
 4477   ins_encode(z_form_rt_mem_opt(src, dst));
 4478   ins_pipe(pipe_class_dummy);
 4479 %}
 4480 
 4481 // FLOAT
 4482 
 4483 // Store Float
 4484 instruct storeF(memory mem, regF src) %{
 4485   match(Set mem (StoreF mem src));
 4486   ins_cost(MEMORY_REF_COST);
 4487   size(Z_DISP_SIZE);
 4488   format %{ "STE(Y)   $src,$mem\t # float" %}
 4489   opcode(STEY_ZOPC, STE_ZOPC);
 4490   ins_encode(z_form_rt_mem_opt(src, mem));
 4491   ins_pipe(pipe_class_dummy);
 4492 %}
 4493 
 4494 // DOUBLE
 4495 
 4496 // Store Double
 4497 instruct storeD(memory mem, regD src) %{
 4498   match(Set mem (StoreD mem src));
 4499   ins_cost(MEMORY_REF_COST);
 4500   size(Z_DISP_SIZE);
 4501   format %{ "STD(Y)   $src,$mem\t # double" %}
 4502   opcode(STDY_ZOPC, STD_ZOPC);
 4503   ins_encode(z_form_rt_mem_opt(src, mem));
 4504   ins_pipe(pipe_class_dummy);
 4505 %}
 4506 
 4507 // Prefetch instructions. Must be safe to execute with invalid address (cannot fault).
 4508 
 4509 // Should support match rule for PrefetchAllocation.
 4510 // Still needed after 8068977 for PrefetchAllocate.
 4511 instruct prefetchAlloc(memory mem) %{
 4512   match(PrefetchAllocation mem);
 4513   predicate(VM_Version::has_Prefetch());
 4514   ins_cost(DEFAULT_COST);
 4515   format %{ "PREFETCH 2, $mem\t # Prefetch allocation, z10 only" %}
 4516   ins_encode %{ __ z_pfd(0x02, $mem$$Address); %}
 4517   ins_pipe(pipe_class_dummy);
 4518 %}
 4519 
 4520 //----------Memory init instructions------------------------------------------
 4521 
 4522 // Move Immediate to 1-byte memory.
 4523 instruct memInitB(memoryRSY mem, immI8 src) %{
 4524   match(Set mem (StoreB mem src));
 4525   ins_cost(MEMORY_REF_COST);
 4526   // TODO: s390 port size(VARIABLE_SIZE);
 4527   format %{ "MVI     $mem,$src\t # direct mem init 1" %}
 4528   ins_encode %{
 4529     if (Immediate::is_uimm12((long)$mem$$disp)) {
 4530       __ z_mvi($mem$$Address, $src$$constant);
 4531     } else {
 4532       __ z_mviy($mem$$Address, $src$$constant);
 4533     }
 4534   %}
 4535   ins_pipe(pipe_class_dummy);
 4536 %}
 4537 
 4538 // Move Immediate to 2-byte memory.
 4539 instruct memInitC(memoryRS mem, immI16 src) %{
 4540   match(Set mem (StoreC mem src));
 4541   ins_cost(MEMORY_REF_COST);
 4542   size(6);
 4543   format %{ "MVHHI   $mem,$src\t # direct mem init 2" %}
 4544   opcode(MVHHI_ZOPC);
 4545   ins_encode(z_silform(mem, src));
 4546   ins_pipe(pipe_class_dummy);
 4547 %}
 4548 
 4549 // Move Immediate to 4-byte memory.
 4550 instruct memInitI(memoryRS mem, immI16 src) %{
 4551   match(Set mem (StoreI mem src));
 4552   ins_cost(MEMORY_REF_COST);
 4553   size(6);
 4554   format %{ "MVHI    $mem,$src\t # direct mem init 4" %}
 4555   opcode(MVHI_ZOPC);
 4556   ins_encode(z_silform(mem, src));
 4557   ins_pipe(pipe_class_dummy);
 4558 %}
 4559 
 4560 
 4561 // Move Immediate to 8-byte memory.
 4562 instruct memInitL(memoryRS mem, immL16 src) %{
 4563   match(Set mem (StoreL mem src));
 4564   ins_cost(MEMORY_REF_COST);
 4565   size(6);
 4566   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
 4567   opcode(MVGHI_ZOPC);
 4568   ins_encode(z_silform(mem, src));
 4569   ins_pipe(pipe_class_dummy);
 4570 %}
 4571 
 4572 // Move Immediate to 8-byte memory.
 4573 instruct memInitP(memoryRS mem, immP16 src) %{
 4574   match(Set mem (StoreP mem src));
 4575   ins_cost(MEMORY_REF_COST);
 4576   size(6);
 4577   format %{ "MVGHI   $mem,$src\t # direct mem init 8" %}
 4578   opcode(MVGHI_ZOPC);
 4579   ins_encode(z_silform(mem, src));
 4580   ins_pipe(pipe_class_dummy);
 4581 %}
 4582 
 4583 
 4584 //----------Instructions for compressed pointers (cOop and NKlass)-------------
 4585 
 4586 // See cOop encoding classes for elaborate comment.
 4587 
 4588 // Moved here because it is needed in expand rules for encode.
 4589 // Long negation.
 4590 instruct negL_reg_reg(iRegL dst, immL_0 zero, iRegL src, flagsReg cr) %{
 4591   match(Set dst (SubL zero src));
 4592   effect(KILL cr);
 4593   size(4);
 4594   format %{ "NEG     $dst, $src\t # long" %}
 4595   ins_encode %{ __ z_lcgr($dst$$Register, $src$$Register); %}
 4596   ins_pipe(pipe_class_dummy);
 4597 %}
 4598 
 4599 // Load Compressed Pointer
 4600 
 4601 // Load narrow oop
 4602 instruct loadN(iRegN dst, memory mem) %{
 4603   match(Set dst (LoadN mem));
 4604   ins_cost(MEMORY_REF_COST);
 4605   size(Z_DISP3_SIZE);
 4606   format %{ "LoadN   $dst,$mem\t # (cOop)" %}
 4607   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4608   ins_encode(z_form_rt_mem_opt(dst, mem));
 4609   ins_pipe(pipe_class_dummy);
 4610 %}
 4611 
 4612 // Load narrow Klass Pointer
 4613 instruct loadNKlass(iRegN dst, memory mem) %{
 4614   match(Set dst (LoadNKlass mem));
 4615   ins_cost(MEMORY_REF_COST);
 4616   size(Z_DISP3_SIZE);
 4617   format %{ "LoadNKlass $dst,$mem\t # (klass cOop)" %}
 4618   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4619   ins_encode(z_form_rt_mem_opt(dst, mem));
 4620   ins_pipe(pipe_class_dummy);
 4621 %}
 4622 
 4623 // Load constant Compressed Pointer
 4624 
 4625 instruct loadConN(iRegN dst, immN src) %{
 4626   match(Set dst src);
 4627   ins_cost(DEFAULT_COST);
 4628   size(6);
 4629   format %{ "loadConN    $dst,$src\t # (cOop)" %}
 4630   ins_encode %{
 4631     AddressLiteral cOop = __ constant_oop_address((jobject)$src$$constant);
 4632     __ relocate(cOop.rspec(), 1);
 4633     __ load_narrow_oop($dst$$Register, (narrowOop)cOop.value());
 4634   %}
 4635   ins_pipe(pipe_class_dummy);
 4636 %}
 4637 
 4638 instruct loadConN0(iRegN dst, immN0 src, flagsReg cr) %{
 4639   match(Set dst src);
 4640   effect(KILL cr);
 4641   ins_cost(DEFAULT_COST_LOW);
 4642   size(4);
 4643   format %{ "loadConN    $dst,$src\t # (cOop) XGR because ZERO is loaded" %}
 4644   opcode(XGR_ZOPC);
 4645   ins_encode(z_rreform(dst, dst));
 4646   ins_pipe(pipe_class_dummy);
 4647 %}
 4648 
 4649 instruct loadConNKlass(iRegN dst, immNKlass src) %{
 4650   match(Set dst src);
 4651   ins_cost(DEFAULT_COST);
 4652   size(6);
 4653   format %{ "loadConNKlass $dst,$src\t # (cKlass)" %}
 4654   ins_encode %{
 4655     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
 4656     __ relocate(NKlass.rspec(), 1);
 4657     __ load_narrow_klass($dst$$Register, (Klass*)NKlass.value());
 4658   %}
 4659   ins_pipe(pipe_class_dummy);
 4660 %}
 4661 
 4662 // Load and Decode Compressed Pointer
 4663 // optimized variants for Unscaled cOops
 4664 
 4665 instruct decodeLoadN(iRegP dst, memory mem) %{
 4666   match(Set dst (DecodeN (LoadN mem)));
 4667   predicate(false && (CompressedOops::base()==NULL)&&(CompressedOops::shift()==0));
 4668   ins_cost(MEMORY_REF_COST);
 4669   size(Z_DISP3_SIZE);
 4670   format %{ "DecodeLoadN  $dst,$mem\t # (cOop Load+Decode)" %}
 4671   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4672   ins_encode(z_form_rt_mem_opt(dst, mem));
 4673   ins_pipe(pipe_class_dummy);
 4674 %}
 4675 
 4676 instruct decodeLoadNKlass(iRegP dst, memory mem) %{
 4677   match(Set dst (DecodeNKlass (LoadNKlass mem)));
 4678   predicate(false && (CompressedKlassPointers::base()==NULL)&&(CompressedKlassPointers::shift()==0));
 4679   ins_cost(MEMORY_REF_COST);
 4680   size(Z_DISP3_SIZE);
 4681   format %{ "DecodeLoadNKlass  $dst,$mem\t # (load/decode NKlass)" %}
 4682   opcode(LLGF_ZOPC, LLGF_ZOPC);
 4683   ins_encode(z_form_rt_mem_opt(dst, mem));
 4684   ins_pipe(pipe_class_dummy);
 4685 %}
 4686 
 4687 instruct decodeLoadConNKlass(iRegP dst, immNKlass src) %{
 4688   match(Set dst (DecodeNKlass src));
 4689   ins_cost(3 * DEFAULT_COST);
 4690   size(12);
 4691   format %{ "DecodeLoadConNKlass  $dst,$src\t # decode(cKlass)" %}
 4692   ins_encode %{
 4693     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src$$constant);
 4694     __ relocate(NKlass.rspec(), 1);
 4695     __ load_const($dst$$Register, (Klass*)NKlass.value());
 4696   %}
 4697   ins_pipe(pipe_class_dummy);
 4698 %}
 4699 
 4700 // Decode Compressed Pointer
 4701 
 4702 // General decoder
 4703 instruct decodeN(iRegP dst, iRegN src, flagsReg cr) %{
 4704   match(Set dst (DecodeN src));
 4705   effect(KILL cr);
 4706   predicate(CompressedOops::base() == NULL || !ExpandLoadingBaseDecode);
 4707   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
 4708   // TODO: s390 port size(VARIABLE_SIZE);
 4709   format %{ "decodeN  $dst,$src\t # (decode cOop)" %}
 4710   ins_encode %{  __ oop_decoder($dst$$Register, $src$$Register, true); %}
 4711   ins_pipe(pipe_class_dummy);
 4712 %}
 4713 
 4714 // General Klass decoder
 4715 instruct decodeKlass(iRegP dst, iRegN src, flagsReg cr) %{
 4716   match(Set dst (DecodeNKlass src));
 4717   effect(KILL cr);
 4718   ins_cost(3 * DEFAULT_COST);
 4719   format %{ "decode_klass $dst,$src" %}
 4720   ins_encode %{ __ decode_klass_not_null($dst$$Register, $src$$Register); %}
 4721   ins_pipe(pipe_class_dummy);
 4722 %}
 4723 
 4724 // General decoder
 4725 instruct decodeN_NN(iRegP dst, iRegN src, flagsReg cr) %{
 4726   match(Set dst (DecodeN src));
 4727   effect(KILL cr);
 4728   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
 4729              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
 4730             (CompressedOops::base()== NULL || !ExpandLoadingBaseDecode_NN));
 4731   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4732   // TODO: s390 port size(VARIABLE_SIZE);
 4733   format %{ "decodeN  $dst,$src\t # (decode cOop NN)" %}
 4734   ins_encode %{ __ oop_decoder($dst$$Register, $src$$Register, false); %}
 4735   ins_pipe(pipe_class_dummy);
 4736 %}
 4737 
 4738   instruct loadBase(iRegL dst, immL baseImm) %{
 4739     effect(DEF dst, USE baseImm);
 4740     predicate(false);
 4741     format %{ "llihl    $dst=$baseImm \t// load heap base" %}
 4742     ins_encode %{ __ get_oop_base($dst$$Register, $baseImm$$constant); %}
 4743     ins_pipe(pipe_class_dummy);
 4744   %}
 4745 
 4746   // Decoder for heapbased mode peeling off loading the base.
 4747   instruct decodeN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
 4748     match(Set dst (DecodeN src base));
 4749     // Note: Effect TEMP dst was used with the intention to get
 4750     // different regs for dst and base, but this has caused ADLC to
 4751     // generate wrong code. Oop_decoder generates additional lgr when
 4752     // dst==base.
 4753     effect(KILL cr);
 4754     predicate(false);
 4755     // TODO: s390 port size(VARIABLE_SIZE);
 4756     format %{ "decodeN  $dst = ($src == 0) ? NULL : ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
 4757     ins_encode %{
 4758       __ oop_decoder($dst$$Register, $src$$Register, true, $base$$Register,
 4759                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
 4760     %}
 4761     ins_pipe(pipe_class_dummy);
 4762   %}
 4763 
 4764   // Decoder for heapbased mode peeling off loading the base.
 4765   instruct decodeN_NN_base(iRegP dst, iRegN src, iRegL base, flagsReg cr) %{
 4766     match(Set dst (DecodeN src base));
 4767     effect(KILL cr);
 4768     predicate(false);
 4769     // TODO: s390 port size(VARIABLE_SIZE);
 4770     format %{ "decodeN  $dst = ($src << 3) + $base + pow2_offset\t # (decode cOop)" %}
 4771     ins_encode %{
 4772       __ oop_decoder($dst$$Register, $src$$Register, false, $base$$Register,
 4773                      (jlong)MacroAssembler::get_oop_base_pow2_offset((uint64_t)(intptr_t)CompressedOops::base()));
 4774     %}
 4775     ins_pipe(pipe_class_dummy);
 4776   %}
 4777 
 4778 // Decoder for heapbased mode peeling off loading the base.
 4779 instruct decodeN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
 4780   match(Set dst (DecodeN src));
 4781   predicate(CompressedOops::base() != NULL && ExpandLoadingBaseDecode);
 4782   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST + BRANCH_COST);
 4783   // TODO: s390 port size(VARIABLE_SIZE);
 4784   expand %{
 4785     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4786     iRegL base;
 4787     loadBase(base, baseImm);
 4788     decodeN_base(dst, src, base, cr);
 4789   %}
 4790 %}
 4791 
 4792 // Decoder for heapbased mode peeling off loading the base.
 4793 instruct decodeN_NN_Ex(iRegP dst, iRegN src, flagsReg cr) %{
 4794   match(Set dst (DecodeN src));
 4795   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull ||
 4796              n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) &&
 4797             CompressedOops::base() != NULL && ExpandLoadingBaseDecode_NN);
 4798   ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4799   // TODO: s390 port size(VARIABLE_SIZE);
 4800   expand %{
 4801     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4802     iRegL base;
 4803     loadBase(base, baseImm);
 4804     decodeN_NN_base(dst, src, base, cr);
 4805   %}
 4806 %}
 4807 
 4808 //  Encode Compressed Pointer
 4809 
 4810 // General encoder
 4811 instruct encodeP(iRegN dst, iRegP src, flagsReg cr) %{
 4812   match(Set dst (EncodeP src));
 4813   effect(KILL cr);
 4814   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
 4815             (CompressedOops::base() == 0 ||
 4816              CompressedOops::base_disjoint() ||
 4817              !ExpandLoadingBaseEncode));
 4818   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4819   // TODO: s390 port size(VARIABLE_SIZE);
 4820   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
 4821   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, true, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
 4822   ins_pipe(pipe_class_dummy);
 4823 %}
 4824 
 4825 // General class encoder
 4826 instruct encodeKlass(iRegN dst, iRegP src, flagsReg cr) %{
 4827   match(Set dst (EncodePKlass src));
 4828   effect(KILL cr);
 4829   format %{ "encode_klass $dst,$src" %}
 4830   ins_encode %{ __ encode_klass_not_null($dst$$Register, $src$$Register); %}
 4831   ins_pipe(pipe_class_dummy);
 4832 %}
 4833 
 4834 instruct encodeP_NN(iRegN dst, iRegP src, flagsReg cr) %{
 4835   match(Set dst (EncodeP src));
 4836   effect(KILL cr);
 4837   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
 4838             (CompressedOops::base() == 0 ||
 4839              CompressedOops::base_disjoint() ||
 4840              !ExpandLoadingBaseEncode_NN));
 4841   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4842   // TODO: s390 port size(VARIABLE_SIZE);
 4843   format %{ "encodeP  $dst,$src\t # (encode cOop)" %}
 4844   ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, Z_R1_scratch, -1, all_outs_are_Stores(this)); %}
 4845   ins_pipe(pipe_class_dummy);
 4846 %}
 4847 
 4848   // Encoder for heapbased mode peeling off loading the base.
 4849   instruct encodeP_base(iRegN dst, iRegP src, iRegL base) %{
 4850     match(Set dst (EncodeP src (Binary base dst)));
 4851     effect(TEMP_DEF dst);
 4852     predicate(false);
 4853     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4854     // TODO: s390 port size(VARIABLE_SIZE);
 4855     format %{ "encodeP  $dst = ($src>>3) +$base + pow2_offset\t # (encode cOop)" %}
 4856     ins_encode %{
 4857       jlong offset = -(jlong)MacroAssembler::get_oop_base_pow2_offset
 4858         (((uint64_t)(intptr_t)CompressedOops::base()) >> CompressedOops::shift());
 4859       __ oop_encoder($dst$$Register, $src$$Register, true, $base$$Register, offset);
 4860     %}
 4861     ins_pipe(pipe_class_dummy);
 4862   %}
 4863 
 4864   // Encoder for heapbased mode peeling off loading the base.
 4865   instruct encodeP_NN_base(iRegN dst, iRegP src, iRegL base, immL pow2_offset) %{
 4866     match(Set dst (EncodeP src base));
 4867     effect(USE pow2_offset);
 4868     predicate(false);
 4869     ins_cost(MEMORY_REF_COST+2 * DEFAULT_COST);
 4870     // TODO: s390 port size(VARIABLE_SIZE);
 4871     format %{ "encodeP  $dst = ($src>>3) +$base + $pow2_offset\t # (encode cOop)" %}
 4872     ins_encode %{ __ oop_encoder($dst$$Register, $src$$Register, false, $base$$Register, $pow2_offset$$constant); %}
 4873     ins_pipe(pipe_class_dummy);
 4874   %}
 4875 
 4876 // Encoder for heapbased mode peeling off loading the base.
 4877 instruct encodeP_Ex(iRegN dst, iRegP src, flagsReg cr) %{
 4878   match(Set dst (EncodeP src));
 4879   effect(KILL cr);
 4880   predicate((n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull) &&
 4881             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode));
 4882   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4883   // TODO: s390 port size(VARIABLE_SIZE);
 4884   expand %{
 4885     immL baseImm %{ ((jlong)(intptr_t)CompressedOops::base()) >> CompressedOops::shift() %}
 4886     immL_0 zero %{ (0) %}
 4887     flagsReg ccr;
 4888     iRegL base;
 4889     iRegL negBase;
 4890     loadBase(base, baseImm);
 4891     negL_reg_reg(negBase, zero, base, ccr);
 4892     encodeP_base(dst, src, negBase);
 4893   %}
 4894 %}
 4895 
 4896 // Encoder for heapbased mode peeling off loading the base.
 4897 instruct encodeP_NN_Ex(iRegN dst, iRegP src, flagsReg cr) %{
 4898   match(Set dst (EncodeP src));
 4899   effect(KILL cr);
 4900   predicate((n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull) &&
 4901             (CompressedOops::base_overlaps() && ExpandLoadingBaseEncode_NN));
 4902   ins_cost(MEMORY_REF_COST+3 * DEFAULT_COST);
 4903   // TODO: s390 port size(VARIABLE_SIZE);
 4904   expand %{
 4905     immL baseImm %{ (jlong)(intptr_t)CompressedOops::base() %}
 4906     immL pow2_offset %{ -(jlong)MacroAssembler::get_oop_base_pow2_offset(((uint64_t)(intptr_t)CompressedOops::base())) %}
 4907     immL_0 zero %{ 0 %}
 4908     flagsReg ccr;
 4909     iRegL base;
 4910     iRegL negBase;
 4911     loadBase(base, baseImm);
 4912     negL_reg_reg(negBase, zero, base, ccr);
 4913     encodeP_NN_base(dst, src, negBase, pow2_offset);
 4914   %}
 4915 %}
 4916 
 4917 //  Store Compressed Pointer
 4918 
 4919 // Store Compressed Pointer
 4920 instruct storeN(memory mem, iRegN_P2N src) %{
 4921   match(Set mem (StoreN mem src));
 4922   ins_cost(MEMORY_REF_COST);
 4923   size(Z_DISP_SIZE);
 4924   format %{ "ST      $src,$mem\t # (cOop)" %}
 4925   opcode(STY_ZOPC, ST_ZOPC);
 4926   ins_encode(z_form_rt_mem_opt(src, mem));
 4927   ins_pipe(pipe_class_dummy);
 4928 %}
 4929 
 4930 // Store Compressed Klass pointer
 4931 instruct storeNKlass(memory mem, iRegN src) %{
 4932   match(Set mem (StoreNKlass mem src));
 4933   ins_cost(MEMORY_REF_COST);
 4934   size(Z_DISP_SIZE);
 4935   format %{ "ST      $src,$mem\t # (cKlass)" %}
 4936   opcode(STY_ZOPC, ST_ZOPC);
 4937   ins_encode(z_form_rt_mem_opt(src, mem));
 4938   ins_pipe(pipe_class_dummy);
 4939 %}
 4940 
 4941 // Compare Compressed Pointers
 4942 
 4943 instruct compN_iRegN(iRegN_P2N src1, iRegN_P2N src2, flagsReg cr) %{
 4944   match(Set cr (CmpN src1 src2));
 4945   ins_cost(DEFAULT_COST);
 4946   size(2);
 4947   format %{ "CLR     $src1,$src2\t # (cOop)" %}
 4948   opcode(CLR_ZOPC);
 4949   ins_encode(z_rrform(src1, src2));
 4950   ins_pipe(pipe_class_dummy);
 4951 %}
 4952 
 4953 instruct compN_iRegN_immN(iRegN_P2N src1, immN src2, flagsReg cr) %{
 4954   match(Set cr (CmpN src1 src2));
 4955   ins_cost(DEFAULT_COST);
 4956   size(6);
 4957   format %{ "CLFI    $src1,$src2\t # (cOop) compare immediate narrow" %}
 4958   ins_encode %{
 4959     AddressLiteral cOop = __ constant_oop_address((jobject)$src2$$constant);
 4960     __ relocate(cOop.rspec(), 1);
 4961     __ compare_immediate_narrow_oop($src1$$Register, (narrowOop)cOop.value());
 4962   %}
 4963   ins_pipe(pipe_class_dummy);
 4964 %}
 4965 
 4966 instruct compNKlass_iRegN_immN(iRegN src1, immNKlass src2, flagsReg cr) %{
 4967   match(Set cr (CmpN src1 src2));
 4968   ins_cost(DEFAULT_COST);
 4969   size(6);
 4970   format %{ "CLFI    $src1,$src2\t # (NKlass) compare immediate narrow" %}
 4971   ins_encode %{
 4972     AddressLiteral NKlass = __ constant_metadata_address((Metadata*)$src2$$constant);
 4973     __ relocate(NKlass.rspec(), 1);
 4974     __ compare_immediate_narrow_klass($src1$$Register, (Klass*)NKlass.value());
 4975   %}
 4976   ins_pipe(pipe_class_dummy);
 4977 %}
 4978 
 4979 instruct compN_iRegN_immN0(iRegN_P2N src1, immN0 src2, flagsReg cr) %{
 4980   match(Set cr (CmpN src1 src2));
 4981   ins_cost(DEFAULT_COST);
 4982   size(2);
 4983   format %{ "LTR     $src1,$src2\t # (cOop) LTR because comparing against zero" %}
 4984   opcode(LTR_ZOPC);
 4985   ins_encode(z_rrform(src1, src1));
 4986   ins_pipe(pipe_class_dummy);
 4987 %}
 4988 
 4989 
 4990 //----------MemBar Instructions-----------------------------------------------
 4991 
 4992 // Memory barrier flavors
 4993 
 4994 instruct membar_acquire() %{
 4995   match(MemBarAcquire);
 4996   match(LoadFence);
 4997   ins_cost(4*MEMORY_REF_COST);
 4998   size(0);
 4999   format %{ "MEMBAR-acquire" %}
 5000   ins_encode %{ __ z_acquire(); %}
 5001   ins_pipe(pipe_class_dummy);
 5002 %}
 5003 
 5004 instruct membar_acquire_lock() %{
 5005   match(MemBarAcquireLock);
 5006   ins_cost(0);
 5007   size(0);
 5008   format %{ "MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
 5009   ins_encode(/*empty*/);
 5010   ins_pipe(pipe_class_dummy);
 5011 %}
 5012 
 5013 instruct membar_release() %{
 5014   match(MemBarRelease);
 5015   match(StoreFence);
 5016   ins_cost(4 * MEMORY_REF_COST);
 5017   size(0);
 5018   format %{ "MEMBAR-release" %}
 5019   ins_encode %{ __ z_release(); %}
 5020   ins_pipe(pipe_class_dummy);
 5021 %}
 5022 
 5023 instruct membar_release_lock() %{
 5024   match(MemBarReleaseLock);
 5025   ins_cost(0);
 5026   size(0);
 5027   format %{ "MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
 5028   ins_encode(/*empty*/);
 5029   ins_pipe(pipe_class_dummy);
 5030 %}
 5031 
 5032 instruct membar_volatile() %{
 5033   match(MemBarVolatile);
 5034   ins_cost(4 * MEMORY_REF_COST);
 5035   size(2);
 5036   format %{ "MEMBAR-volatile" %}
 5037   ins_encode %{ __ z_fence(); %}
 5038   ins_pipe(pipe_class_dummy);
 5039 %}
 5040 
 5041 instruct unnecessary_membar_volatile() %{
 5042   match(MemBarVolatile);
 5043   predicate(Matcher::post_store_load_barrier(n));
 5044   ins_cost(0);
 5045   size(0);
 5046   format %{ "# MEMBAR-volatile (empty)" %}
 5047   ins_encode(/*empty*/);
 5048   ins_pipe(pipe_class_dummy);
 5049 %}
 5050 
 5051 instruct membar_CPUOrder() %{
 5052   match(MemBarCPUOrder);
 5053   ins_cost(0);
 5054   // TODO: s390 port size(FIXED_SIZE);
 5055   format %{ "MEMBAR-CPUOrder (empty)" %}
 5056   ins_encode(/*empty*/);
 5057   ins_pipe(pipe_class_dummy);
 5058 %}
 5059 
 5060 instruct membar_storestore() %{
 5061   match(MemBarStoreStore);
 5062   ins_cost(0);
 5063   size(0);
 5064   format %{ "MEMBAR-storestore (empty)" %}
 5065   ins_encode();
 5066   ins_pipe(pipe_class_dummy);
 5067 %}
 5068 
 5069 
 5070 //----------Register Move Instructions-----------------------------------------
 5071 instruct roundDouble_nop(regD dst) %{
 5072   match(Set dst (RoundDouble dst));
 5073   ins_cost(0);
 5074   // TODO: s390 port size(FIXED_SIZE);
 5075   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
 5076   ins_encode();
 5077   ins_pipe(pipe_class_dummy);
 5078 %}
 5079 
 5080 instruct roundFloat_nop(regF dst) %{
 5081   match(Set dst (RoundFloat dst));
 5082   ins_cost(0);
 5083   // TODO: s390 port size(FIXED_SIZE);
 5084   // z/Architecture results are already "rounded" (i.e., normal-format IEEE).
 5085   ins_encode();
 5086   ins_pipe(pipe_class_dummy);
 5087 %}
 5088 
 5089 // Cast Long to Pointer for unsafe natives.
 5090 instruct castX2P(iRegP dst, iRegL src) %{
 5091   match(Set dst (CastX2P src));
 5092   // TODO: s390 port size(VARIABLE_SIZE);
 5093   format %{ "LGR     $dst,$src\t # CastX2P" %}
 5094   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
 5095   ins_pipe(pipe_class_dummy);
 5096 %}
 5097 
 5098 // Cast Pointer to Long for unsafe natives.
 5099 instruct castP2X(iRegL dst, iRegP_N2P src) %{
 5100   match(Set dst (CastP2X src));
 5101   // TODO: s390 port size(VARIABLE_SIZE);
 5102   format %{ "LGR     $dst,$src\t # CastP2X" %}
 5103   ins_encode %{ __ lgr_if_needed($dst$$Register, $src$$Register); %}
 5104   ins_pipe(pipe_class_dummy);
 5105 %}
 5106 
 5107 instruct stfSSD(stackSlotD stkSlot, regD src) %{
 5108   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
 5109   match(Set stkSlot src);   // chain rule
 5110   ins_cost(MEMORY_REF_COST);
 5111   // TODO: s390 port size(FIXED_SIZE);
 5112   format %{ " STD   $src,$stkSlot\t # stk" %}
 5113   opcode(STD_ZOPC);
 5114   ins_encode(z_form_rt_mem(src, stkSlot));
 5115   ins_pipe(pipe_class_dummy);
 5116 %}
 5117 
 5118 instruct stfSSF(stackSlotF stkSlot, regF src) %{
 5119   // %%%% TODO: Tell the coalescer that this kind of node is a copy!
 5120   match(Set stkSlot src);   // chain rule
 5121   ins_cost(MEMORY_REF_COST);
 5122   // TODO: s390 port size(FIXED_SIZE);
 5123   format %{ "STE   $src,$stkSlot\t # stk" %}
 5124   opcode(STE_ZOPC);
 5125   ins_encode(z_form_rt_mem(src, stkSlot));
 5126   ins_pipe(pipe_class_dummy);
 5127 %}
 5128 
 5129 //----------Conditional Move---------------------------------------------------
 5130 
 5131 instruct cmovN_reg(cmpOp cmp, flagsReg cr, iRegN dst, iRegN_P2N src) %{
 5132   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
 5133   ins_cost(DEFAULT_COST + BRANCH_COST);
 5134   // TODO: s390 port size(VARIABLE_SIZE);
 5135   format %{ "CMoveN,$cmp   $dst,$src" %}
 5136   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5137   ins_pipe(pipe_class_dummy);
 5138 %}
 5139 
 5140 instruct cmovN_imm(cmpOp cmp, flagsReg cr, iRegN dst, immN0 src) %{
 5141   match(Set dst (CMoveN (Binary cmp cr) (Binary dst src)));
 5142   ins_cost(DEFAULT_COST + BRANCH_COST);
 5143   // TODO: s390 port size(VARIABLE_SIZE);
 5144   format %{ "CMoveN,$cmp   $dst,$src" %}
 5145   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5146   ins_pipe(pipe_class_dummy);
 5147 %}
 5148 
 5149 instruct cmovI_reg(cmpOp cmp, flagsReg cr, iRegI dst, iRegI src) %{
 5150   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
 5151   ins_cost(DEFAULT_COST + BRANCH_COST);
 5152   // TODO: s390 port size(VARIABLE_SIZE);
 5153   format %{ "CMoveI,$cmp   $dst,$src" %}
 5154   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5155   ins_pipe(pipe_class_dummy);
 5156 %}
 5157 
 5158 instruct cmovI_imm(cmpOp cmp, flagsReg cr, iRegI dst, immI16 src) %{
 5159   match(Set dst (CMoveI (Binary cmp cr) (Binary dst src)));
 5160   ins_cost(DEFAULT_COST + BRANCH_COST);
 5161   // TODO: s390 port size(VARIABLE_SIZE);
 5162   format %{ "CMoveI,$cmp   $dst,$src" %}
 5163   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5164   ins_pipe(pipe_class_dummy);
 5165 %}
 5166 
 5167 instruct cmovP_reg(cmpOp cmp, flagsReg cr, iRegP dst, iRegP_N2P src) %{
 5168   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
 5169   ins_cost(DEFAULT_COST + BRANCH_COST);
 5170   // TODO: s390 port size(VARIABLE_SIZE);
 5171   format %{ "CMoveP,$cmp    $dst,$src" %}
 5172   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5173   ins_pipe(pipe_class_dummy);
 5174 %}
 5175 
 5176 instruct cmovP_imm(cmpOp cmp, flagsReg cr, iRegP dst, immP0 src) %{
 5177   match(Set dst (CMoveP (Binary cmp cr) (Binary dst src)));
 5178   ins_cost(DEFAULT_COST + BRANCH_COST);
 5179   // TODO: s390 port size(VARIABLE_SIZE);
 5180   format %{ "CMoveP,$cmp  $dst,$src" %}
 5181   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5182   ins_pipe(pipe_class_dummy);
 5183 %}
 5184 
 5185 instruct cmovF_reg(cmpOpF cmp, flagsReg cr, regF dst, regF src) %{
 5186   match(Set dst (CMoveF (Binary cmp cr) (Binary dst src)));
 5187   ins_cost(DEFAULT_COST + BRANCH_COST);
 5188   // TODO: s390 port size(VARIABLE_SIZE);
 5189   format %{ "CMoveF,$cmp   $dst,$src" %}
 5190   ins_encode %{
 5191     // Don't emit code if operands are identical (same register).
 5192     if ($dst$$FloatRegister != $src$$FloatRegister) {
 5193       Label done;
 5194       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
 5195       __ z_ler($dst$$FloatRegister, $src$$FloatRegister);
 5196       __ bind(done);
 5197     }
 5198   %}
 5199   ins_pipe(pipe_class_dummy);
 5200 %}
 5201 
 5202 instruct cmovD_reg(cmpOpF cmp, flagsReg cr, regD dst, regD src) %{
 5203   match(Set dst (CMoveD (Binary cmp cr) (Binary dst src)));
 5204   ins_cost(DEFAULT_COST + BRANCH_COST);
 5205   // TODO: s390 port size(VARIABLE_SIZE);
 5206   format %{ "CMoveD,$cmp   $dst,$src" %}
 5207   ins_encode %{
 5208     // Don't emit code if operands are identical (same register).
 5209     if ($dst$$FloatRegister != $src$$FloatRegister) {
 5210       Label done;
 5211       __ z_brc(Assembler::inverse_float_condition((Assembler::branch_condition)$cmp$$cmpcode), done);
 5212       __ z_ldr($dst$$FloatRegister, $src$$FloatRegister);
 5213       __ bind(done);
 5214     }
 5215   %}
 5216   ins_pipe(pipe_class_dummy);
 5217 %}
 5218 
 5219 instruct cmovL_reg(cmpOp cmp, flagsReg cr, iRegL dst, iRegL src) %{
 5220   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
 5221   ins_cost(DEFAULT_COST + BRANCH_COST);
 5222   // TODO: s390 port size(VARIABLE_SIZE);
 5223   format %{ "CMoveL,$cmp  $dst,$src" %}
 5224   ins_encode(z_enc_cmov_reg(cmp,dst,src));
 5225   ins_pipe(pipe_class_dummy);
 5226 %}
 5227 
 5228 instruct cmovL_imm(cmpOp cmp, flagsReg cr, iRegL dst, immL16 src) %{
 5229   match(Set dst (CMoveL (Binary cmp cr) (Binary dst src)));
 5230   ins_cost(DEFAULT_COST + BRANCH_COST);
 5231   // TODO: s390 port size(VARIABLE_SIZE);
 5232   format %{ "CMoveL,$cmp  $dst,$src" %}
 5233   ins_encode(z_enc_cmov_imm(cmp,dst,src));
 5234   ins_pipe(pipe_class_dummy);
 5235 %}
 5236 
 5237 //----------OS and Locking Instructions----------------------------------------
 5238 
 5239 // This name is KNOWN by the ADLC and cannot be changed.
 5240 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
 5241 // for this guy.
 5242 instruct tlsLoadP(threadRegP dst) %{
 5243   match(Set dst (ThreadLocal));
 5244   ins_cost(0);
 5245   size(0);
 5246   ins_should_rematerialize(true);
 5247   format %{ "# $dst=ThreadLocal" %}
 5248   ins_encode(/* empty */);
 5249   ins_pipe(pipe_class_dummy);
 5250 %}
 5251 
 5252 instruct checkCastPP(iRegP dst) %{
 5253   match(Set dst (CheckCastPP dst));
 5254   size(0);
 5255   format %{ "# checkcastPP of $dst" %}
 5256   ins_encode(/*empty*/);
 5257   ins_pipe(pipe_class_dummy);
 5258 %}
 5259 
 5260 instruct castPP(iRegP dst) %{
 5261   match(Set dst (CastPP dst));
 5262   size(0);
 5263   format %{ "# castPP of $dst" %}
 5264   ins_encode(/*empty*/);
 5265   ins_pipe(pipe_class_dummy);
 5266 %}
 5267 
 5268 instruct castII(iRegI dst) %{
 5269   match(Set dst (CastII dst));
 5270   size(0);
 5271   format %{ "# castII of $dst" %}
 5272   ins_encode(/*empty*/);
 5273   ins_pipe(pipe_class_dummy);
 5274 %}
 5275 
 5276 instruct castLL(iRegL dst) %{
 5277   match(Set dst (CastLL dst));
 5278   size(0);
 5279   format %{ "# castLL of $dst" %}
 5280   ins_encode(/*empty*/);
 5281   ins_pipe(pipe_class_dummy);
 5282 %}
 5283 
 5284 instruct castFF(regF dst) %{
 5285   match(Set dst (CastFF dst));
 5286   size(0);
 5287   format %{ "# castFF of $dst" %}
 5288   ins_encode(/*empty*/);
 5289   ins_pipe(pipe_class_dummy);
 5290 %}
 5291 
 5292 instruct castDD(regD dst) %{
 5293   match(Set dst (CastDD dst));
 5294   size(0);
 5295   format %{ "# castDD of $dst" %}
 5296   ins_encode(/*empty*/);
 5297   ins_pipe(pipe_class_dummy);
 5298 %}
 5299 
 5300 instruct castVV(iRegL dst) %{
 5301   match(Set dst (CastVV dst));
 5302   size(0);
 5303   format %{ "# castVV of $dst" %}
 5304   ins_encode(/*empty*/);
 5305   ins_pipe(pipe_class_dummy);
 5306 %}
 5307 
 5308 //----------Conditional_store--------------------------------------------------
 5309 // Conditional-store of the updated heap-top.
 5310 // Used during allocation of the shared heap.
 5311 // Sets flags (EQ) on success.
 5312 
 5313 // Implement LoadPLocked. Must be ordered against changes of the memory location
 5314 // by storePConditional.
 5315 // Don't know whether this is ever used.
 5316 instruct loadPLocked(iRegP dst, memory mem) %{
 5317   match(Set dst (LoadPLocked mem));
 5318   ins_cost(MEMORY_REF_COST);
 5319   size(Z_DISP3_SIZE);
 5320   format %{ "LG      $dst,$mem\t # LoadPLocked" %}
 5321   opcode(LG_ZOPC, LG_ZOPC);
 5322   ins_encode(z_form_rt_mem_opt(dst, mem));
 5323   ins_pipe(pipe_class_dummy);
 5324 %}
 5325 
 5326 // As compareAndSwapP, but return flag register instead of boolean value in
 5327 // int register.
 5328 // This instruction is matched if UseTLAB is off. Needed to pass
 5329 // option tests.  Mem_ptr must be a memory operand, else this node
 5330 // does not get Flag_needs_anti_dependence_check set by adlc. If this
 5331 // is not set this node can be rematerialized which leads to errors.
 5332 instruct storePConditional(indirect mem_ptr, rarg5RegP oldval, iRegP_N2P newval, flagsReg cr) %{
 5333   match(Set cr (StorePConditional mem_ptr (Binary oldval newval)));
 5334   effect(KILL oldval);
 5335   // TODO: s390 port size(FIXED_SIZE);
 5336   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
 5337   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
 5338   ins_pipe(pipe_class_dummy);
 5339 %}
 5340 
 5341 // As compareAndSwapL, but return flag register instead of boolean value in
 5342 // int register.
 5343 // Used by sun/misc/AtomicLongCSImpl.java. Mem_ptr must be a memory
 5344 // operand, else this node does not get
 5345 // Flag_needs_anti_dependence_check set by adlc. If this is not set
 5346 // this node can be rematerialized which leads to errors.
 5347 instruct storeLConditional(indirect mem_ptr, rarg5RegL oldval, iRegL newval, flagsReg cr) %{
 5348   match(Set cr (StoreLConditional mem_ptr (Binary oldval newval)));
 5349   effect(KILL oldval);
 5350   // TODO: s390 port size(FIXED_SIZE);
 5351   format %{ "storePConditional $oldval,$newval,$mem_ptr" %}
 5352   ins_encode(z_enc_casL(oldval, newval, mem_ptr));
 5353   ins_pipe(pipe_class_dummy);
 5354 %}
 5355 
 5356 // No flag versions for CompareAndSwap{P,I,L,N} because matcher can't match them.
 5357 
 5358 instruct compareAndSwapI_bool(iRegP mem_ptr, rarg5RegI oldval, iRegI newval, iRegI res, flagsReg cr) %{
 5359   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
 5360   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5361   size(16);
 5362   format %{ "$res = CompareAndSwapI $oldval,$newval,$mem_ptr" %}
 5363   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
 5364              z_enc_cctobool(res));
 5365   ins_pipe(pipe_class_dummy);
 5366 %}
 5367 
 5368 instruct compareAndSwapL_bool(iRegP mem_ptr, rarg5RegL oldval, iRegL newval, iRegI res, flagsReg cr) %{
 5369   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
 5370   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5371   size(18);
 5372   format %{ "$res = CompareAndSwapL $oldval,$newval,$mem_ptr" %}
 5373   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
 5374              z_enc_cctobool(res));
 5375   ins_pipe(pipe_class_dummy);
 5376 %}
 5377 
 5378 instruct compareAndSwapP_bool(iRegP mem_ptr, rarg5RegP oldval, iRegP_N2P newval, iRegI res, flagsReg cr) %{
 5379   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
 5380   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5381   size(18);
 5382   format %{ "$res = CompareAndSwapP $oldval,$newval,$mem_ptr" %}
 5383   ins_encode(z_enc_casL(oldval, newval, mem_ptr),
 5384              z_enc_cctobool(res));
 5385   ins_pipe(pipe_class_dummy);
 5386 %}
 5387 
 5388 instruct compareAndSwapN_bool(iRegP mem_ptr, rarg5RegN oldval, iRegN_P2N newval, iRegI res, flagsReg cr) %{
 5389   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
 5390   effect(USE mem_ptr, USE_KILL oldval, KILL cr);
 5391   size(16);
 5392   format %{ "$res = CompareAndSwapN $oldval,$newval,$mem_ptr" %}
 5393   ins_encode(z_enc_casI(oldval, newval, mem_ptr),
 5394              z_enc_cctobool(res));
 5395   ins_pipe(pipe_class_dummy);
 5396 %}
 5397 
 5398 //----------Atomic operations on memory (GetAndSet*, GetAndAdd*)---------------
 5399 
 5400 // Exploit: direct memory arithmetic
 5401 // Prereqs: - instructions available
 5402 //          - instructions guarantee atomicity
 5403 //          - immediate operand to be added
 5404 //          - immediate operand is small enough (8-bit signed).
 5405 //          - result of instruction is not used
 5406 instruct addI_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immI8 src, flagsReg cr) %{
 5407   match(Set dummy (GetAndAddI mem src));
 5408   effect(KILL cr);
 5409   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
 5410   ins_cost(MEMORY_REF_COST);
 5411   size(6);
 5412   format %{ "ASI     [$mem],$src\t # GetAndAddI (atomic)" %}
 5413   opcode(ASI_ZOPC);
 5414   ins_encode(z_siyform(mem, src));
 5415   ins_pipe(pipe_class_dummy);
 5416 %}
 5417 
 5418 // Fallback: direct memory arithmetic not available
 5419 // Disadvantages: - CS-Loop required, very expensive.
 5420 //                - more code generated (26 to xx bytes vs. 6 bytes)
 5421 instruct addI_mem_imm16_atomic(memoryRSY mem, iRegI dst, immI16 src, iRegI tmp, flagsReg cr) %{
 5422   match(Set dst (GetAndAddI mem src));
 5423   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5424   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5425   format %{ "BEGIN ATOMIC {\n\t"
 5426             "  LGF     $dst,[$mem]\n\t"
 5427             "  AHIK    $tmp,$dst,$src\n\t"
 5428             "  CSY     $dst,$tmp,$mem\n\t"
 5429             "  retry if failed\n\t"
 5430             "} END ATOMIC"
 5431          %}
 5432   ins_encode %{
 5433     Register Rdst = $dst$$Register;
 5434     Register Rtmp = $tmp$$Register;
 5435     int      Isrc = $src$$constant;
 5436     Label    retry;
 5437 
 5438     // Iterate until update with incremented value succeeds.
 5439     __ z_lgf(Rdst, $mem$$Address);    // current contents
 5440     __ bind(retry);
 5441       // Calculate incremented value.
 5442       if (VM_Version::has_DistinctOpnds()) {
 5443         __ z_ahik(Rtmp, Rdst, Isrc);
 5444       } else {
 5445         __ z_lr(Rtmp, Rdst);
 5446         __ z_ahi(Rtmp, Isrc);
 5447       }
 5448       // Swap into memory location.
 5449       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5450     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5451   %}
 5452   ins_pipe(pipe_class_dummy);
 5453 %}
 5454 
 5455 instruct addI_mem_imm32_atomic(memoryRSY mem, iRegI dst, immI src, iRegI tmp, flagsReg cr) %{
 5456   match(Set dst (GetAndAddI mem src));
 5457   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5458   ins_cost(MEMORY_REF_COST+200*DEFAULT_COST);
 5459   format %{ "BEGIN ATOMIC {\n\t"
 5460             "  LGF     $dst,[$mem]\n\t"
 5461             "  LGR     $tmp,$dst\n\t"
 5462             "  AFI     $tmp,$src\n\t"
 5463             "  CSY     $dst,$tmp,$mem\n\t"
 5464             "  retry if failed\n\t"
 5465             "} END ATOMIC"
 5466          %}
 5467   ins_encode %{
 5468     Register Rdst = $dst$$Register;
 5469     Register Rtmp = $tmp$$Register;
 5470     int      Isrc = $src$$constant;
 5471     Label    retry;
 5472 
 5473     // Iterate until update with incremented value succeeds.
 5474     __ z_lgf(Rdst, $mem$$Address);    // current contents
 5475     __ bind(retry);
 5476       // Calculate incremented value.
 5477       __ z_lr(Rtmp, Rdst);
 5478       __ z_afi(Rtmp, Isrc);
 5479       // Swap into memory location.
 5480       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5481     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5482   %}
 5483   ins_pipe(pipe_class_dummy);
 5484 %}
 5485 
 5486 instruct addI_mem_reg_atomic(memoryRSY mem, iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
 5487   match(Set dst (GetAndAddI mem src));
 5488   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5489   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5490   format %{ "BEGIN ATOMIC {\n\t"
 5491             "  LGF     $dst,[$mem]\n\t"
 5492             "  ARK     $tmp,$dst,$src\n\t"
 5493             "  CSY     $dst,$tmp,$mem\n\t"
 5494             "  retry if failed\n\t"
 5495             "} END ATOMIC"
 5496          %}
 5497   ins_encode %{
 5498     Register Rsrc = $src$$Register;
 5499     Register Rdst = $dst$$Register;
 5500     Register Rtmp = $tmp$$Register;
 5501     Label    retry;
 5502 
 5503     // Iterate until update with incremented value succeeds.
 5504     __ z_lgf(Rdst, $mem$$Address);  // current contents
 5505     __ bind(retry);
 5506       // Calculate incremented value.
 5507       if (VM_Version::has_DistinctOpnds()) {
 5508         __ z_ark(Rtmp, Rdst, Rsrc);
 5509       } else {
 5510         __ z_lr(Rtmp, Rdst);
 5511         __ z_ar(Rtmp, Rsrc);
 5512       }
 5513       __ z_csy(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5514     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5515   %}
 5516   ins_pipe(pipe_class_dummy);
 5517 %}
 5518 
 5519 
 5520 // Exploit: direct memory arithmetic
 5521 // Prereqs: - instructions available
 5522 //          - instructions guarantee atomicity
 5523 //          - immediate operand to be added
 5524 //          - immediate operand is small enough (8-bit signed).
 5525 //          - result of instruction is not used
 5526 instruct addL_mem_imm8_atomic_no_res(memoryRSY mem, Universe dummy, immL8 src, flagsReg cr) %{
 5527   match(Set dummy (GetAndAddL mem src));
 5528   effect(KILL cr);
 5529   predicate(VM_Version::has_AtomicMemWithImmALUOps() && n->as_LoadStore()->result_not_used());
 5530   ins_cost(MEMORY_REF_COST);
 5531   size(6);
 5532   format %{ "AGSI    [$mem],$src\t # GetAndAddL (atomic)" %}
 5533   opcode(AGSI_ZOPC);
 5534   ins_encode(z_siyform(mem, src));
 5535   ins_pipe(pipe_class_dummy);
 5536 %}
 5537 
 5538 // Fallback: direct memory arithmetic not available
 5539 // Disadvantages: - CS-Loop required, very expensive.
 5540 //                - more code generated (26 to xx bytes vs. 6 bytes)
 5541 instruct addL_mem_imm16_atomic(memoryRSY mem, iRegL dst, immL16 src, iRegL tmp, flagsReg cr) %{
 5542   match(Set dst (GetAndAddL mem src));
 5543   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5544   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5545   format %{ "BEGIN ATOMIC {\n\t"
 5546             "  LG      $dst,[$mem]\n\t"
 5547             "  AGHIK   $tmp,$dst,$src\n\t"
 5548             "  CSG     $dst,$tmp,$mem\n\t"
 5549             "  retry if failed\n\t"
 5550             "} END ATOMIC"
 5551          %}
 5552   ins_encode %{
 5553     Register Rdst = $dst$$Register;
 5554     Register Rtmp = $tmp$$Register;
 5555     int      Isrc = $src$$constant;
 5556     Label    retry;
 5557 
 5558     // Iterate until update with incremented value succeeds.
 5559     __ z_lg(Rdst, $mem$$Address);  // current contents
 5560     __ bind(retry);
 5561       // Calculate incremented value.
 5562       if (VM_Version::has_DistinctOpnds()) {
 5563         __ z_aghik(Rtmp, Rdst, Isrc);
 5564       } else {
 5565         __ z_lgr(Rtmp, Rdst);
 5566         __ z_aghi(Rtmp, Isrc);
 5567       }
 5568       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5569     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5570   %}
 5571   ins_pipe(pipe_class_dummy);
 5572 %}
 5573 
 5574 instruct addL_mem_imm32_atomic(memoryRSY mem, iRegL dst, immL32 src, iRegL tmp, flagsReg cr) %{
 5575   match(Set dst (GetAndAddL mem src));
 5576   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5577   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5578   format %{ "BEGIN ATOMIC {\n\t"
 5579             "  LG      $dst,[$mem]\n\t"
 5580             "  LGR     $tmp,$dst\n\t"
 5581             "  AGFI    $tmp,$src\n\t"
 5582             "  CSG     $dst,$tmp,$mem\n\t"
 5583             "  retry if failed\n\t"
 5584             "} END ATOMIC"
 5585          %}
 5586   ins_encode %{
 5587     Register Rdst = $dst$$Register;
 5588     Register Rtmp = $tmp$$Register;
 5589     int      Isrc = $src$$constant;
 5590     Label    retry;
 5591 
 5592     // Iterate until update with incremented value succeeds.
 5593     __ z_lg(Rdst, $mem$$Address);  // current contents
 5594     __ bind(retry);
 5595       // Calculate incremented value.
 5596       __ z_lgr(Rtmp, Rdst);
 5597       __ z_agfi(Rtmp, Isrc);
 5598       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5599     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5600   %}
 5601   ins_pipe(pipe_class_dummy);
 5602 %}
 5603 
 5604 instruct addL_mem_reg_atomic(memoryRSY mem, iRegL dst, iRegL src, iRegL tmp, flagsReg cr) %{
 5605   match(Set dst (GetAndAddL mem src));
 5606   effect(KILL cr, TEMP_DEF dst, TEMP tmp);
 5607   ins_cost(MEMORY_REF_COST+100*DEFAULT_COST);
 5608   format %{ "BEGIN ATOMIC {\n\t"
 5609             "  LG      $dst,[$mem]\n\t"
 5610             "  AGRK    $tmp,$dst,$src\n\t"
 5611             "  CSG     $dst,$tmp,$mem\n\t"
 5612             "  retry if failed\n\t"
 5613             "} END ATOMIC"
 5614          %}
 5615   ins_encode %{
 5616     Register Rsrc = $src$$Register;
 5617     Register Rdst = $dst$$Register;
 5618     Register Rtmp = $tmp$$Register;
 5619     Label    retry;
 5620 
 5621     // Iterate until update with incremented value succeeds.
 5622     __ z_lg(Rdst, $mem$$Address);  // current contents
 5623     __ bind(retry);
 5624       // Calculate incremented value.
 5625       if (VM_Version::has_DistinctOpnds()) {
 5626         __ z_agrk(Rtmp, Rdst, Rsrc);
 5627       } else {
 5628         __ z_lgr(Rtmp, Rdst);
 5629         __ z_agr(Rtmp, Rsrc);
 5630       }
 5631       __ z_csg(Rdst, Rtmp, $mem$$Address); // Try to store new value.
 5632     __ z_brne(retry);                      // Yikes, concurrent update, need to retry.
 5633   %}
 5634   ins_pipe(pipe_class_dummy);
 5635 %}
 5636 
 5637 // Increment value in memory, save old value in dst.
 5638 instruct addI_mem_reg_atomic_z196(memoryRSY mem, iRegI dst, iRegI src) %{
 5639   match(Set dst (GetAndAddI mem src));
 5640   predicate(VM_Version::has_LoadAndALUAtomicV1());
 5641   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
 5642   size(6);
 5643   format %{ "LAA     $dst,$src,[$mem]" %}
 5644   ins_encode %{ __ z_laa($dst$$Register, $src$$Register, $mem$$Address); %}
 5645   ins_pipe(pipe_class_dummy);
 5646 %}
 5647 
 5648 // Increment value in memory, save old value in dst.
 5649 instruct addL_mem_reg_atomic_z196(memoryRSY mem, iRegL dst, iRegL src) %{
 5650   match(Set dst (GetAndAddL mem src));
 5651   predicate(VM_Version::has_LoadAndALUAtomicV1());
 5652   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
 5653   size(6);
 5654   format %{ "LAAG    $dst,$src,[$mem]" %}
 5655   ins_encode %{ __ z_laag($dst$$Register, $src$$Register, $mem$$Address); %}
 5656   ins_pipe(pipe_class_dummy);
 5657 %}
 5658 
 5659 
 5660 instruct xchgI_reg_mem(memoryRSY mem, iRegI dst, iRegI tmp, flagsReg cr) %{
 5661   match(Set dst (GetAndSetI mem dst));
 5662   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5663   format %{ "XCHGI   $dst,[$mem]\t # EXCHANGE (int, atomic), temp $tmp" %}
 5664   ins_encode(z_enc_SwapI(mem, dst, tmp));
 5665   ins_pipe(pipe_class_dummy);
 5666 %}
 5667 
 5668 instruct xchgL_reg_mem(memoryRSY mem, iRegL dst, iRegL tmp, flagsReg cr) %{
 5669   match(Set dst (GetAndSetL mem dst));
 5670   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5671   format %{ "XCHGL   $dst,[$mem]\t # EXCHANGE (long, atomic), temp $tmp" %}
 5672   ins_encode(z_enc_SwapL(mem, dst, tmp));
 5673   ins_pipe(pipe_class_dummy);
 5674 %}
 5675 
 5676 instruct xchgN_reg_mem(memoryRSY mem, iRegN dst, iRegI tmp, flagsReg cr) %{
 5677   match(Set dst (GetAndSetN mem dst));
 5678   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5679   format %{ "XCHGN   $dst,[$mem]\t # EXCHANGE (coop, atomic), temp $tmp" %}
 5680   ins_encode(z_enc_SwapI(mem, dst, tmp));
 5681   ins_pipe(pipe_class_dummy);
 5682 %}
 5683 
 5684 instruct xchgP_reg_mem(memoryRSY mem, iRegP dst, iRegL tmp, flagsReg cr) %{
 5685   match(Set dst (GetAndSetP mem dst));
 5686   effect(KILL cr, TEMP tmp); // USE_DEF dst by match rule.
 5687   format %{ "XCHGP   $dst,[$mem]\t # EXCHANGE (oop, atomic), temp $tmp" %}
 5688   ins_encode(z_enc_SwapL(mem, dst, tmp));
 5689   ins_pipe(pipe_class_dummy);
 5690 %}
 5691 
 5692 
 5693 //----------Arithmetic Instructions--------------------------------------------
 5694 
 5695 // The rules are sorted by right operand type and operand length. Please keep
 5696 // it that way.
 5697 // Left operand type is always reg. Left operand len is I, L, P
 5698 // Right operand type is reg, imm, mem. Right operand len is S, I, L, P
 5699 // Special instruction formats, e.g. multi-operand, are inserted at the end.
 5700 
 5701 // ADD
 5702 
 5703 // REG = REG + REG
 5704 
 5705 // Register Addition
 5706 instruct addI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
 5707   match(Set dst (AddI dst src));
 5708   effect(KILL cr);
 5709   // TODO: s390 port size(FIXED_SIZE);
 5710   format %{ "AR      $dst,$src\t # int  CISC ALU" %}
 5711   opcode(AR_ZOPC);
 5712   ins_encode(z_rrform(dst, src));
 5713   ins_pipe(pipe_class_dummy);
 5714 %}
 5715 
 5716 // Avoid use of LA(Y) for general ALU operation.
 5717 instruct addI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 5718   match(Set dst (AddI src1 src2));
 5719   effect(KILL cr);
 5720   predicate(VM_Version::has_DistinctOpnds());
 5721   ins_cost(DEFAULT_COST);
 5722   size(4);
 5723   format %{ "ARK     $dst,$src1,$src2\t # int  RISC ALU" %}
 5724   opcode(ARK_ZOPC);
 5725   ins_encode(z_rrfform(dst, src1, src2));
 5726   ins_pipe(pipe_class_dummy);
 5727 %}
 5728 
 5729 // REG = REG + IMM
 5730 
 5731 // Avoid use of LA(Y) for general ALU operation.
 5732 // Immediate Addition
 5733 instruct addI_reg_imm16_CISC(iRegI dst, immI16 con, flagsReg cr) %{
 5734   match(Set dst (AddI dst con));
 5735   effect(KILL cr);
 5736   ins_cost(DEFAULT_COST);
 5737   // TODO: s390 port size(FIXED_SIZE);
 5738   format %{ "AHI     $dst,$con\t # int  CISC ALU" %}
 5739   opcode(AHI_ZOPC);
 5740   ins_encode(z_riform_signed(dst, con));
 5741   ins_pipe(pipe_class_dummy);
 5742 %}
 5743 
 5744 // Avoid use of LA(Y) for general ALU operation.
 5745 // Immediate Addition
 5746 instruct addI_reg_imm16_RISC(iRegI dst, iRegI src, immI16 con, flagsReg cr) %{
 5747   match(Set dst (AddI src con));
 5748   effect(KILL cr);
 5749   predicate( VM_Version::has_DistinctOpnds());
 5750   ins_cost(DEFAULT_COST);
 5751   // TODO: s390 port size(FIXED_SIZE);
 5752   format %{ "AHIK    $dst,$src,$con\t # int  RISC ALU" %}
 5753   opcode(AHIK_ZOPC);
 5754   ins_encode(z_rieform_d(dst, src, con));
 5755   ins_pipe(pipe_class_dummy);
 5756 %}
 5757 
 5758 // Immediate Addition
 5759 instruct addI_reg_imm32(iRegI dst, immI src, flagsReg cr) %{
 5760   match(Set dst (AddI dst src));
 5761   effect(KILL cr);
 5762   ins_cost(DEFAULT_COST_HIGH);
 5763   size(6);
 5764   format %{ "AFI     $dst,$src" %}
 5765   opcode(AFI_ZOPC);
 5766   ins_encode(z_rilform_signed(dst, src));
 5767   ins_pipe(pipe_class_dummy);
 5768 %}
 5769 
 5770 // Immediate Addition
 5771 instruct addI_reg_imm12(iRegI dst, iRegI src, uimmI12 con) %{
 5772   match(Set dst (AddI src con));
 5773   predicate(PreferLAoverADD);
 5774   ins_cost(DEFAULT_COST_LOW);
 5775   size(4);
 5776   format %{ "LA      $dst,$con(,$src)\t # int d12(,b)" %}
 5777   opcode(LA_ZOPC);
 5778   ins_encode(z_rxform_imm_reg(dst, con, src));
 5779   ins_pipe(pipe_class_dummy);
 5780 %}
 5781 
 5782 // Immediate Addition
 5783 instruct addI_reg_imm20(iRegI dst, iRegI src, immI20 con) %{
 5784   match(Set dst (AddI src con));
 5785   predicate(PreferLAoverADD);
 5786   ins_cost(DEFAULT_COST);
 5787   size(6);
 5788   format %{ "LAY     $dst,$con(,$src)\t # int d20(,b)" %}
 5789   opcode(LAY_ZOPC);
 5790   ins_encode(z_rxyform_imm_reg(dst, con, src));
 5791   ins_pipe(pipe_class_dummy);
 5792 %}
 5793 
 5794 instruct addI_reg_reg_imm12(iRegI dst, iRegI src1, iRegI src2, uimmI12 con) %{
 5795   match(Set dst (AddI (AddI src1 src2) con));
 5796   predicate( PreferLAoverADD);
 5797   ins_cost(DEFAULT_COST_LOW);
 5798   size(4);
 5799   format %{ "LA      $dst,$con($src1,$src2)\t # int d12(x,b)" %}
 5800   opcode(LA_ZOPC);
 5801   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 5802   ins_pipe(pipe_class_dummy);
 5803 %}
 5804 
 5805 instruct addI_reg_reg_imm20(iRegI dst, iRegI src1, iRegI src2, immI20 con) %{
 5806   match(Set dst (AddI (AddI src1 src2) con));
 5807   predicate(PreferLAoverADD);
 5808   ins_cost(DEFAULT_COST);
 5809   size(6);
 5810   format %{ "LAY     $dst,$con($src1,$src2)\t # int d20(x,b)" %}
 5811   opcode(LAY_ZOPC);
 5812   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 5813   ins_pipe(pipe_class_dummy);
 5814 %}
 5815 
 5816 // REG = REG + MEM
 5817 
 5818 instruct addI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 5819   match(Set dst (AddI dst (LoadI src)));
 5820   effect(KILL cr);
 5821   ins_cost(MEMORY_REF_COST);
 5822   // TODO: s390 port size(VARIABLE_SIZE);
 5823   format %{ "A(Y)    $dst, $src\t # int" %}
 5824   opcode(AY_ZOPC, A_ZOPC);
 5825   ins_encode(z_form_rt_mem_opt(dst, src));
 5826   ins_pipe(pipe_class_dummy);
 5827 %}
 5828 
 5829 // MEM = MEM + IMM
 5830 
 5831 // Add Immediate to 4-byte memory operand and result
 5832 instruct addI_mem_imm(memoryRSY mem, immI8 src, flagsReg cr) %{
 5833   match(Set mem (StoreI mem (AddI (LoadI mem) src)));
 5834   effect(KILL cr);
 5835   predicate(VM_Version::has_MemWithImmALUOps());
 5836   ins_cost(MEMORY_REF_COST);
 5837   size(6);
 5838   format %{ "ASI     $mem,$src\t # direct mem add 4" %}
 5839   opcode(ASI_ZOPC);
 5840   ins_encode(z_siyform(mem, src));
 5841   ins_pipe(pipe_class_dummy);
 5842 %}
 5843 
 5844 
 5845 //
 5846 
 5847 // REG = REG + REG
 5848 
 5849 instruct addL_reg_regI(iRegL dst, iRegI src, flagsReg cr) %{
 5850   match(Set dst (AddL dst (ConvI2L src)));
 5851   effect(KILL cr);
 5852   size(4);
 5853   format %{ "AGFR    $dst,$src\t # long<-int CISC ALU" %}
 5854   opcode(AGFR_ZOPC);
 5855   ins_encode(z_rreform(dst, src));
 5856   ins_pipe(pipe_class_dummy);
 5857 %}
 5858 
 5859 instruct addL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
 5860   match(Set dst (AddL dst src));
 5861   effect(KILL cr);
 5862   // TODO: s390 port size(FIXED_SIZE);
 5863   format %{ "AGR     $dst, $src\t # long CISC ALU" %}
 5864   opcode(AGR_ZOPC);
 5865   ins_encode(z_rreform(dst, src));
 5866   ins_pipe(pipe_class_dummy);
 5867 %}
 5868 
 5869 // Avoid use of LA(Y) for general ALU operation.
 5870 instruct addL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
 5871   match(Set dst (AddL src1 src2));
 5872   effect(KILL cr);
 5873   predicate(VM_Version::has_DistinctOpnds());
 5874   ins_cost(DEFAULT_COST);
 5875   size(4);
 5876   format %{ "AGRK    $dst,$src1,$src2\t # long RISC ALU" %}
 5877   opcode(AGRK_ZOPC);
 5878   ins_encode(z_rrfform(dst, src1, src2));
 5879   ins_pipe(pipe_class_dummy);
 5880 %}
 5881 
 5882 // REG = REG + IMM
 5883 
 5884 instruct addL_reg_imm12(iRegL dst, iRegL src, uimmL12 con) %{
 5885   match(Set dst (AddL src con));
 5886   predicate( PreferLAoverADD);
 5887   ins_cost(DEFAULT_COST_LOW);
 5888   size(4);
 5889   format %{ "LA      $dst,$con(,$src)\t # long d12(,b)" %}
 5890   opcode(LA_ZOPC);
 5891   ins_encode(z_rxform_imm_reg(dst, con, src));
 5892   ins_pipe(pipe_class_dummy);
 5893 %}
 5894 
 5895 instruct addL_reg_imm20(iRegL dst, iRegL src, immL20 con) %{
 5896   match(Set dst (AddL src con));
 5897   predicate(PreferLAoverADD);
 5898   ins_cost(DEFAULT_COST);
 5899   size(6);
 5900   format %{ "LAY     $dst,$con(,$src)\t # long d20(,b)" %}
 5901   opcode(LAY_ZOPC);
 5902   ins_encode(z_rxyform_imm_reg(dst, con, src));
 5903   ins_pipe(pipe_class_dummy);
 5904 %}
 5905 
 5906 instruct addL_reg_imm32(iRegL dst, immL32 con, flagsReg cr) %{
 5907   match(Set dst (AddL dst con));
 5908   effect(KILL cr);
 5909   ins_cost(DEFAULT_COST_HIGH);
 5910   size(6);
 5911   format %{ "AGFI    $dst,$con\t # long CISC ALU" %}
 5912   opcode(AGFI_ZOPC);
 5913   ins_encode(z_rilform_signed(dst, con));
 5914   ins_pipe(pipe_class_dummy);
 5915 %}
 5916 
 5917 // Avoid use of LA(Y) for general ALU operation.
 5918 instruct addL_reg_imm16_CISC(iRegL dst, immL16 con, flagsReg cr) %{
 5919   match(Set dst (AddL dst con));
 5920   effect(KILL cr);
 5921   ins_cost(DEFAULT_COST);
 5922   // TODO: s390 port size(FIXED_SIZE);
 5923   format %{ "AGHI    $dst,$con\t # long CISC ALU" %}
 5924   opcode(AGHI_ZOPC);
 5925   ins_encode(z_riform_signed(dst, con));
 5926   ins_pipe(pipe_class_dummy);
 5927 %}
 5928 
 5929 // Avoid use of LA(Y) for general ALU operation.
 5930 instruct addL_reg_imm16_RISC(iRegL dst, iRegL src, immL16 con, flagsReg cr) %{
 5931   match(Set dst (AddL src con));
 5932   effect(KILL cr);
 5933   predicate( VM_Version::has_DistinctOpnds());
 5934   ins_cost(DEFAULT_COST);
 5935   size(6);
 5936   format %{ "AGHIK   $dst,$src,$con\t # long RISC ALU" %}
 5937   opcode(AGHIK_ZOPC);
 5938   ins_encode(z_rieform_d(dst, src, con));
 5939   ins_pipe(pipe_class_dummy);
 5940 %}
 5941 
 5942 // REG = REG + MEM
 5943 
 5944 instruct addL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
 5945   match(Set dst (AddL dst (ConvI2L (LoadI src))));
 5946   effect(KILL cr);
 5947   ins_cost(MEMORY_REF_COST);
 5948   size(Z_DISP3_SIZE);
 5949   format %{ "AGF     $dst, $src\t # long/int" %}
 5950   opcode(AGF_ZOPC, AGF_ZOPC);
 5951   ins_encode(z_form_rt_mem_opt(dst, src));
 5952   ins_pipe(pipe_class_dummy);
 5953 %}
 5954 
 5955 instruct addL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 5956   match(Set dst (AddL dst (LoadL src)));
 5957   effect(KILL cr);
 5958   ins_cost(MEMORY_REF_COST);
 5959   size(Z_DISP3_SIZE);
 5960   format %{ "AG      $dst, $src\t # long" %}
 5961   opcode(AG_ZOPC, AG_ZOPC);
 5962   ins_encode(z_form_rt_mem_opt(dst, src));
 5963   ins_pipe(pipe_class_dummy);
 5964 %}
 5965 
 5966 instruct addL_reg_reg_imm12(iRegL dst, iRegL src1, iRegL src2, uimmL12 con) %{
 5967   match(Set dst (AddL (AddL src1 src2) con));
 5968   predicate( PreferLAoverADD);
 5969   ins_cost(DEFAULT_COST_LOW);
 5970   size(4);
 5971   format %{ "LA     $dst,$con($src1,$src2)\t # long d12(x,b)" %}
 5972   opcode(LA_ZOPC);
 5973   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 5974   ins_pipe(pipe_class_dummy);
 5975 %}
 5976 
 5977 instruct addL_reg_reg_imm20(iRegL dst, iRegL src1, iRegL src2, immL20 con) %{
 5978   match(Set dst (AddL (AddL src1 src2) con));
 5979   predicate(PreferLAoverADD);
 5980   ins_cost(DEFAULT_COST);
 5981   size(6);
 5982   format %{ "LAY    $dst,$con($src1,$src2)\t # long d20(x,b)" %}
 5983   opcode(LAY_ZOPC);
 5984   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 5985   ins_pipe(pipe_class_dummy);
 5986 %}
 5987 
 5988 // MEM = MEM + IMM
 5989 
 5990 // Add Immediate to 8-byte memory operand and result.
 5991 instruct addL_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
 5992   match(Set mem (StoreL mem (AddL (LoadL mem) src)));
 5993   effect(KILL cr);
 5994   predicate(VM_Version::has_MemWithImmALUOps());
 5995   ins_cost(MEMORY_REF_COST);
 5996   size(6);
 5997   format %{ "AGSI    $mem,$src\t # direct mem add 8" %}
 5998   opcode(AGSI_ZOPC);
 5999   ins_encode(z_siyform(mem, src));
 6000   ins_pipe(pipe_class_dummy);
 6001 %}
 6002 
 6003 
 6004 // REG = REG + REG
 6005 
 6006 // Ptr Addition
 6007 instruct addP_reg_reg_LA(iRegP dst, iRegP_N2P src1, iRegL src2) %{
 6008   match(Set dst (AddP src1 src2));
 6009   predicate( PreferLAoverADD);
 6010   ins_cost(DEFAULT_COST);
 6011   size(4);
 6012   format %{ "LA      $dst,#0($src1,$src2)\t # ptr 0(x,b)" %}
 6013   opcode(LA_ZOPC);
 6014   ins_encode(z_rxform_imm_reg_reg(dst, 0x0, src1, src2));
 6015   ins_pipe(pipe_class_dummy);
 6016 %}
 6017 
 6018 // Ptr Addition
 6019 // Avoid use of LA(Y) for general ALU operation.
 6020 instruct addP_reg_reg_CISC(iRegP dst, iRegL src, flagsReg cr) %{
 6021   match(Set dst (AddP dst src));
 6022   effect(KILL cr);
 6023   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
 6024   ins_cost(DEFAULT_COST);
 6025   // TODO: s390 port size(FIXED_SIZE);
 6026   format %{ "ALGR    $dst,$src\t # ptr CICS ALU" %}
 6027   opcode(ALGR_ZOPC);
 6028   ins_encode(z_rreform(dst, src));
 6029   ins_pipe(pipe_class_dummy);
 6030 %}
 6031 
 6032 // Ptr Addition
 6033 // Avoid use of LA(Y) for general ALU operation.
 6034 instruct addP_reg_reg_RISC(iRegP dst, iRegP_N2P src1, iRegL src2, flagsReg cr) %{
 6035   match(Set dst (AddP src1 src2));
 6036   effect(KILL cr);
 6037   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
 6038   ins_cost(DEFAULT_COST);
 6039   // TODO: s390 port size(FIXED_SIZE);
 6040   format %{ "ALGRK   $dst,$src1,$src2\t # ptr RISC ALU" %}
 6041   opcode(ALGRK_ZOPC);
 6042   ins_encode(z_rrfform(dst, src1, src2));
 6043   ins_pipe(pipe_class_dummy);
 6044 %}
 6045 
 6046 // REG = REG + IMM
 6047 
 6048 instruct addP_reg_imm12(iRegP dst, iRegP_N2P src, uimmL12 con) %{
 6049   match(Set dst (AddP src con));
 6050   predicate( PreferLAoverADD);
 6051   ins_cost(DEFAULT_COST_LOW);
 6052   size(4);
 6053   format %{ "LA      $dst,$con(,$src)\t # ptr d12(,b)" %}
 6054   opcode(LA_ZOPC);
 6055   ins_encode(z_rxform_imm_reg(dst, con, src));
 6056   ins_pipe(pipe_class_dummy);
 6057 %}
 6058 
 6059 // Avoid use of LA(Y) for general ALU operation.
 6060 instruct addP_reg_imm16_CISC(iRegP dst, immL16 src, flagsReg cr) %{
 6061   match(Set dst (AddP dst src));
 6062   effect(KILL cr);
 6063   predicate(!PreferLAoverADD && !VM_Version::has_DistinctOpnds());
 6064   ins_cost(DEFAULT_COST);
 6065   // TODO: s390 port size(FIXED_SIZE);
 6066   format %{ "AGHI    $dst,$src\t # ptr CISC ALU" %}
 6067   opcode(AGHI_ZOPC);
 6068   ins_encode(z_riform_signed(dst, src));
 6069   ins_pipe(pipe_class_dummy);
 6070 %}
 6071 
 6072 // Avoid use of LA(Y) for general ALU operation.
 6073 instruct addP_reg_imm16_RISC(iRegP dst, iRegP_N2P src, immL16 con, flagsReg cr) %{
 6074   match(Set dst (AddP src con));
 6075   effect(KILL cr);
 6076   predicate(!PreferLAoverADD && VM_Version::has_DistinctOpnds());
 6077   ins_cost(DEFAULT_COST);
 6078   // TODO: s390 port size(FIXED_SIZE);
 6079   format %{ "ALGHSIK $dst,$src,$con\t # ptr RISC ALU" %}
 6080   opcode(ALGHSIK_ZOPC);
 6081   ins_encode(z_rieform_d(dst, src, con));
 6082   ins_pipe(pipe_class_dummy);
 6083 %}
 6084 
 6085 instruct addP_reg_imm20(iRegP dst, memoryRegP src, immL20 con) %{
 6086   match(Set dst (AddP src con));
 6087   predicate(PreferLAoverADD);
 6088   ins_cost(DEFAULT_COST);
 6089   size(6);
 6090   format %{ "LAY     $dst,$con(,$src)\t # ptr d20(,b)" %}
 6091   opcode(LAY_ZOPC);
 6092   ins_encode(z_rxyform_imm_reg(dst, con, src));
 6093   ins_pipe(pipe_class_dummy);
 6094 %}
 6095 
 6096 // Pointer Immediate Addition
 6097 instruct addP_reg_imm32(iRegP dst, immL32 src, flagsReg cr) %{
 6098   match(Set dst (AddP dst src));
 6099   effect(KILL cr);
 6100   ins_cost(DEFAULT_COST_HIGH);
 6101   // TODO: s390 port size(FIXED_SIZE);
 6102   format %{ "AGFI    $dst,$src\t # ptr" %}
 6103   opcode(AGFI_ZOPC);
 6104   ins_encode(z_rilform_signed(dst, src));
 6105   ins_pipe(pipe_class_dummy);
 6106 %}
 6107 
 6108 // REG = REG1 + REG2 + IMM
 6109 
 6110 instruct addP_reg_reg_imm12(iRegP dst, memoryRegP src1, iRegL src2, uimmL12 con) %{
 6111   match(Set dst (AddP (AddP src1 src2) con));
 6112   predicate( PreferLAoverADD);
 6113   ins_cost(DEFAULT_COST_LOW);
 6114   size(4);
 6115   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
 6116   opcode(LA_ZOPC);
 6117   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 6118   ins_pipe(pipe_class_dummy);
 6119 %}
 6120 
 6121 instruct addP_regN_reg_imm12(iRegP dst, iRegP_N2P src1, iRegL src2, uimmL12 con) %{
 6122   match(Set dst (AddP (AddP src1 src2) con));
 6123   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 6124   ins_cost(DEFAULT_COST_LOW);
 6125   size(4);
 6126   format %{ "LA      $dst,$con($src1,$src2)\t # ptr d12(x,b)" %}
 6127   opcode(LA_ZOPC);
 6128   ins_encode(z_rxform_imm_reg_reg(dst, con, src1, src2));
 6129   ins_pipe(pipe_class_dummy);
 6130 %}
 6131 
 6132 instruct addP_reg_reg_imm20(iRegP dst, memoryRegP src1, iRegL src2, immL20 con) %{
 6133   match(Set dst (AddP (AddP src1 src2) con));
 6134   predicate(PreferLAoverADD);
 6135   ins_cost(DEFAULT_COST);
 6136   // TODO: s390 port size(FIXED_SIZE);
 6137   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
 6138   opcode(LAY_ZOPC);
 6139   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 6140   ins_pipe(pipe_class_dummy);
 6141 %}
 6142 
 6143 instruct addP_regN_reg_imm20(iRegP dst, iRegP_N2P src1, iRegL src2, immL20 con) %{
 6144   match(Set dst (AddP (AddP src1 src2) con));
 6145   predicate( PreferLAoverADD && CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 6146   ins_cost(DEFAULT_COST);
 6147   // TODO: s390 port size(FIXED_SIZE);
 6148   format %{ "LAY     $dst,$con($src1,$src2)\t # ptr d20(x,b)" %}
 6149   opcode(LAY_ZOPC);
 6150   ins_encode(z_rxyform_imm_reg_reg(dst, con, src1, src2));
 6151   ins_pipe(pipe_class_dummy);
 6152 %}
 6153 
 6154 // MEM = MEM + IMM
 6155 
 6156 // Add Immediate to 8-byte memory operand and result
 6157 instruct addP_mem_imm(memoryRSY mem, immL8 src, flagsReg cr) %{
 6158   match(Set mem (StoreP mem (AddP (LoadP mem) src)));
 6159   effect(KILL cr);
 6160   predicate(VM_Version::has_MemWithImmALUOps());
 6161   ins_cost(MEMORY_REF_COST);
 6162   size(6);
 6163   format %{ "AGSI    $mem,$src\t # direct mem add 8 (ptr)" %}
 6164   opcode(AGSI_ZOPC);
 6165   ins_encode(z_siyform(mem, src));
 6166   ins_pipe(pipe_class_dummy);
 6167 %}
 6168 
 6169 // SUB
 6170 
 6171 // Register Subtraction
 6172 instruct subI_reg_reg_CISC(iRegI dst, iRegI src, flagsReg cr) %{
 6173   match(Set dst (SubI dst src));
 6174   effect(KILL cr);
 6175   // TODO: s390 port size(FIXED_SIZE);
 6176   format %{ "SR      $dst,$src\t # int  CISC ALU" %}
 6177   opcode(SR_ZOPC);
 6178   ins_encode(z_rrform(dst, src));
 6179   ins_pipe(pipe_class_dummy);
 6180 %}
 6181 
 6182 instruct subI_reg_reg_RISC(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 6183   match(Set dst (SubI src1 src2));
 6184   effect(KILL cr);
 6185   predicate(VM_Version::has_DistinctOpnds());
 6186   ins_cost(DEFAULT_COST);
 6187   size(4);
 6188   format %{ "SRK     $dst,$src1,$src2\t # int  RISC ALU" %}
 6189   opcode(SRK_ZOPC);
 6190   ins_encode(z_rrfform(dst, src1, src2));
 6191   ins_pipe(pipe_class_dummy);
 6192 %}
 6193 
 6194 instruct subI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 6195   match(Set dst (SubI dst (LoadI src)));
 6196   effect(KILL cr);
 6197   ins_cost(MEMORY_REF_COST);
 6198   // TODO: s390 port size(VARIABLE_SIZE);
 6199   format %{ "S(Y)    $dst, $src\t # int" %}
 6200   opcode(SY_ZOPC, S_ZOPC);
 6201   ins_encode(z_form_rt_mem_opt(dst, src));
 6202   ins_pipe(pipe_class_dummy);
 6203 %}
 6204 
 6205 instruct subI_zero_reg(iRegI dst, immI_0 zero, iRegI src, flagsReg cr) %{
 6206   match(Set dst (SubI zero src));
 6207   effect(KILL cr);
 6208   size(2);
 6209   format %{ "NEG     $dst, $src" %}
 6210   ins_encode %{ __ z_lcr($dst$$Register, $src$$Register); %}
 6211   ins_pipe(pipe_class_dummy);
 6212 %}
 6213 
 6214 //
 6215 
 6216 // Long subtraction
 6217 instruct subL_reg_reg_CISC(iRegL dst, iRegL src, flagsReg cr) %{
 6218   match(Set dst (SubL dst src));
 6219   effect(KILL cr);
 6220   // TODO: s390 port size(FIXED_SIZE);
 6221   format %{ "SGR     $dst,$src\t # int  CISC ALU" %}
 6222   opcode(SGR_ZOPC);
 6223   ins_encode(z_rreform(dst, src));
 6224   ins_pipe(pipe_class_dummy);
 6225 %}
 6226 
 6227 // Avoid use of LA(Y) for general ALU operation.
 6228 instruct subL_reg_reg_RISC(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
 6229   match(Set dst (SubL src1 src2));
 6230   effect(KILL cr);
 6231   predicate(VM_Version::has_DistinctOpnds());
 6232   ins_cost(DEFAULT_COST);
 6233   size(4);
 6234   format %{ "SGRK    $dst,$src1,$src2\t # int  RISC ALU" %}
 6235   opcode(SGRK_ZOPC);
 6236   ins_encode(z_rrfform(dst, src1, src2));
 6237   ins_pipe(pipe_class_dummy);
 6238 %}
 6239 
 6240 instruct subL_reg_regI_CISC(iRegL dst, iRegI src, flagsReg cr) %{
 6241   match(Set dst (SubL dst (ConvI2L src)));
 6242   effect(KILL cr);
 6243   size(4);
 6244   format %{ "SGFR    $dst, $src\t # int  CISC ALU" %}
 6245   opcode(SGFR_ZOPC);
 6246   ins_encode(z_rreform(dst, src));
 6247   ins_pipe(pipe_class_dummy);
 6248 %}
 6249 
 6250 instruct subL_Reg_memI(iRegL dst, memory src, flagsReg cr)%{
 6251   match(Set dst (SubL dst (ConvI2L (LoadI src))));
 6252   effect(KILL cr);
 6253   ins_cost(MEMORY_REF_COST);
 6254   size(Z_DISP3_SIZE);
 6255   format %{ "SGF     $dst, $src\t # long/int" %}
 6256   opcode(SGF_ZOPC, SGF_ZOPC);
 6257   ins_encode(z_form_rt_mem_opt(dst, src));
 6258   ins_pipe(pipe_class_dummy);
 6259 %}
 6260 
 6261 instruct subL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 6262   match(Set dst (SubL dst (LoadL src)));
 6263   effect(KILL cr);
 6264   ins_cost(MEMORY_REF_COST);
 6265   size(Z_DISP3_SIZE);
 6266   format %{ "SG      $dst, $src\t # long" %}
 6267   opcode(SG_ZOPC, SG_ZOPC);
 6268   ins_encode(z_form_rt_mem_opt(dst, src));
 6269   ins_pipe(pipe_class_dummy);
 6270 %}
 6271 
 6272 // Moved declaration of negL_reg_reg before encode nodes, where it is used.
 6273 
 6274 //  MUL
 6275 
 6276 // Register Multiplication
 6277 instruct mulI_reg_reg(iRegI dst, iRegI src) %{
 6278   match(Set dst (MulI dst src));
 6279   ins_cost(DEFAULT_COST);
 6280   size(4);
 6281   format %{ "MSR     $dst, $src" %}
 6282   opcode(MSR_ZOPC);
 6283   ins_encode(z_rreform(dst, src));
 6284   ins_pipe(pipe_class_dummy);
 6285 %}
 6286 
 6287 // Immediate Multiplication
 6288 instruct mulI_reg_imm16(iRegI dst, immI16 con) %{
 6289   match(Set dst (MulI dst con));
 6290   ins_cost(DEFAULT_COST);
 6291   // TODO: s390 port size(FIXED_SIZE);
 6292   format %{ "MHI     $dst,$con" %}
 6293   opcode(MHI_ZOPC);
 6294   ins_encode(z_riform_signed(dst,con));
 6295   ins_pipe(pipe_class_dummy);
 6296 %}
 6297 
 6298 // Immediate (32bit) Multiplication
 6299 instruct mulI_reg_imm32(iRegI dst, immI con) %{
 6300   match(Set dst (MulI dst con));
 6301   ins_cost(DEFAULT_COST);
 6302   size(6);
 6303   format %{ "MSFI    $dst,$con" %}
 6304   opcode(MSFI_ZOPC);
 6305   ins_encode(z_rilform_signed(dst,con));
 6306   ins_pipe(pipe_class_dummy);
 6307 %}
 6308 
 6309 instruct mulI_Reg_mem(iRegI dst, memory src)%{
 6310   match(Set dst (MulI dst (LoadI src)));
 6311   ins_cost(MEMORY_REF_COST);
 6312   // TODO: s390 port size(VARIABLE_SIZE);
 6313   format %{ "MS(Y)   $dst, $src\t # int" %}
 6314   opcode(MSY_ZOPC, MS_ZOPC);
 6315   ins_encode(z_form_rt_mem_opt(dst, src));
 6316   ins_pipe(pipe_class_dummy);
 6317 %}
 6318 
 6319 //
 6320 
 6321 instruct mulL_reg_regI(iRegL dst, iRegI src) %{
 6322   match(Set dst (MulL dst (ConvI2L src)));
 6323   ins_cost(DEFAULT_COST);
 6324   // TODO: s390 port size(FIXED_SIZE);
 6325   format %{ "MSGFR   $dst $src\t # long/int" %}
 6326   opcode(MSGFR_ZOPC);
 6327   ins_encode(z_rreform(dst, src));
 6328   ins_pipe(pipe_class_dummy);
 6329 %}
 6330 
 6331 instruct mulL_reg_reg(iRegL dst, iRegL src) %{
 6332   match(Set dst (MulL dst src));
 6333   ins_cost(DEFAULT_COST);
 6334   size(4);
 6335   format %{ "MSGR    $dst $src\t # long" %}
 6336   opcode(MSGR_ZOPC);
 6337   ins_encode(z_rreform(dst, src));
 6338   ins_pipe(pipe_class_dummy);
 6339 %}
 6340 
 6341 // Immediate Multiplication
 6342 instruct mulL_reg_imm16(iRegL dst, immL16 src) %{
 6343   match(Set dst (MulL dst src));
 6344   ins_cost(DEFAULT_COST);
 6345   // TODO: s390 port size(FIXED_SIZE);
 6346   format %{ "MGHI    $dst,$src\t # long" %}
 6347   opcode(MGHI_ZOPC);
 6348   ins_encode(z_riform_signed(dst, src));
 6349   ins_pipe(pipe_class_dummy);
 6350 %}
 6351 
 6352 // Immediate (32bit) Multiplication
 6353 instruct mulL_reg_imm32(iRegL dst, immL32 con) %{
 6354   match(Set dst (MulL dst con));
 6355   ins_cost(DEFAULT_COST);
 6356   size(6);
 6357   format %{ "MSGFI   $dst,$con" %}
 6358   opcode(MSGFI_ZOPC);
 6359   ins_encode(z_rilform_signed(dst,con));
 6360   ins_pipe(pipe_class_dummy);
 6361 %}
 6362 
 6363 instruct mulL_Reg_memI(iRegL dst, memory src)%{
 6364   match(Set dst (MulL dst (ConvI2L (LoadI src))));
 6365   ins_cost(MEMORY_REF_COST);
 6366   size(Z_DISP3_SIZE);
 6367   format %{ "MSGF    $dst, $src\t # long" %}
 6368   opcode(MSGF_ZOPC, MSGF_ZOPC);
 6369   ins_encode(z_form_rt_mem_opt(dst, src));
 6370   ins_pipe(pipe_class_dummy);
 6371 %}
 6372 
 6373 instruct mulL_Reg_mem(iRegL dst, memory src)%{
 6374   match(Set dst (MulL dst (LoadL src)));
 6375   ins_cost(MEMORY_REF_COST);
 6376   size(Z_DISP3_SIZE);
 6377   format %{ "MSG     $dst, $src\t # long" %}
 6378   opcode(MSG_ZOPC, MSG_ZOPC);
 6379   ins_encode(z_form_rt_mem_opt(dst, src));
 6380   ins_pipe(pipe_class_dummy);
 6381 %}
 6382 
 6383 instruct mulHiL_reg_reg(revenRegL Rdst, roddRegL Rsrc1, iRegL Rsrc2, iRegL Rtmp1, flagsReg cr)%{
 6384   match(Set Rdst (MulHiL Rsrc1 Rsrc2));
 6385   effect(TEMP_DEF Rdst, USE_KILL Rsrc1, TEMP Rtmp1, KILL cr);
 6386   ins_cost(7*DEFAULT_COST);
 6387   // TODO: s390 port size(VARIABLE_SIZE);
 6388   format %{ "MulHiL  $Rdst, $Rsrc1, $Rsrc2\t # Multiply High Long" %}
 6389   ins_encode%{
 6390     Register dst  = $Rdst$$Register;
 6391     Register src1 = $Rsrc1$$Register;
 6392     Register src2 = $Rsrc2$$Register;
 6393     Register tmp1 = $Rtmp1$$Register;
 6394     Register tmp2 = $Rdst$$Register;
 6395     // z/Architecture has only unsigned multiply (64 * 64 -> 128).
 6396     // implementing mulhs(a,b) = mulhu(a,b) – (a & (b>>63)) – (b & (a>>63))
 6397     __ z_srag(tmp2, src1, 63);  // a>>63
 6398     __ z_srag(tmp1, src2, 63);  // b>>63
 6399     __ z_ngr(tmp2, src2);       // b & (a>>63)
 6400     __ z_ngr(tmp1, src1);       // a & (b>>63)
 6401     __ z_agr(tmp1, tmp2);       // ((a & (b>>63)) + (b & (a>>63)))
 6402     __ z_mlgr(dst, src2);       // tricky: 128-bit product is written to even/odd pair (dst,src1),
 6403                                 //         multiplicand is taken from oddReg (src1), multiplier in src2.
 6404     __ z_sgr(dst, tmp1);
 6405   %}
 6406   ins_pipe(pipe_class_dummy);
 6407 %}
 6408 
 6409 //  DIV
 6410 
 6411 // Integer DIVMOD with Register, both quotient and mod results
 6412 instruct divModI_reg_divmod(roddRegI dst1src1, revenRegI dst2, noOdd_iRegI src2, flagsReg cr) %{
 6413   match(DivModI dst1src1 src2);
 6414   effect(KILL cr);
 6415   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6416   size((VM_Version::has_CompareBranch() ? 24 : 26));
 6417   format %{ "DIVMODI ($dst1src1, $dst2) $src2" %}
 6418   ins_encode %{
 6419     Register d1s1 = $dst1src1$$Register;
 6420     Register d2   = $dst2$$Register;
 6421     Register s2   = $src2$$Register;
 6422 
 6423     assert_different_registers(d1s1, s2);
 6424 
 6425     Label do_div, done_div;
 6426     if (VM_Version::has_CompareBranch()) {
 6427       __ z_cij(s2, -1, Assembler::bcondNotEqual, do_div);
 6428     } else {
 6429       __ z_chi(s2, -1);
 6430       __ z_brne(do_div);
 6431     }
 6432     __ z_lcr(d1s1, d1s1);
 6433     __ clear_reg(d2, false, false);
 6434     __ z_bru(done_div);
 6435     __ bind(do_div);
 6436     __ z_lgfr(d1s1, d1s1);
 6437     __ z_dsgfr(d2, s2);
 6438     __ bind(done_div);
 6439   %}
 6440   ins_pipe(pipe_class_dummy);
 6441 %}
 6442 
 6443 
 6444 // Register Division
 6445 instruct divI_reg_reg(roddRegI dst, iRegI src1, noOdd_iRegI src2, revenRegI tmp, flagsReg cr) %{
 6446   match(Set dst (DivI src1 src2));
 6447   effect(KILL tmp, KILL cr);
 6448   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6449   size((VM_Version::has_CompareBranch() ? 20 : 22));
 6450   format %{ "DIV_checked $dst, $src1,$src2\t # treats special case 0x80../-1" %}
 6451   ins_encode %{
 6452     Register a = $src1$$Register;
 6453     Register b = $src2$$Register;
 6454     Register t = $dst$$Register;
 6455 
 6456     assert_different_registers(t, b);
 6457 
 6458     Label do_div, done_div;
 6459     if (VM_Version::has_CompareBranch()) {
 6460       __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
 6461     } else {
 6462       __ z_chi(b, -1);
 6463       __ z_brne(do_div);
 6464     }
 6465     __ z_lcr(t, a);
 6466     __ z_bru(done_div);
 6467     __ bind(do_div);
 6468     __ z_lgfr(t, a);
 6469     __ z_dsgfr(t->predecessor()/* t is odd part of a register pair. */, b);
 6470     __ bind(done_div);
 6471   %}
 6472   ins_pipe(pipe_class_dummy);
 6473 %}
 6474 
 6475 // Immediate Division
 6476 instruct divI_reg_imm16(roddRegI dst, iRegI src1, immI16 src2, revenRegI tmp, flagsReg cr) %{
 6477   match(Set dst (DivI src1 src2));
 6478   effect(KILL tmp, KILL cr);  // R0 is killed, too.
 6479   ins_cost(2 * DEFAULT_COST);
 6480   // TODO: s390 port size(VARIABLE_SIZE);
 6481   format %{ "DIV_const  $dst,$src1,$src2" %}
 6482   ins_encode %{
 6483     // No sign extension of Rdividend needed here.
 6484     if ($src2$$constant != -1) {
 6485       __ z_lghi(Z_R0_scratch, $src2$$constant);
 6486       __ z_lgfr($dst$$Register, $src1$$Register);
 6487       __ z_dsgfr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
 6488     } else {
 6489       __ z_lcr($dst$$Register, $src1$$Register);
 6490     }
 6491   %}
 6492   ins_pipe(pipe_class_dummy);
 6493 %}
 6494 
 6495 // Long DIVMOD with Register, both quotient and mod results
 6496 instruct divModL_reg_divmod(roddRegL dst1src1, revenRegL dst2, iRegL src2, flagsReg cr) %{
 6497   match(DivModL dst1src1 src2);
 6498   effect(KILL cr);
 6499   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6500   size((VM_Version::has_CompareBranch() ? 22 : 24));
 6501   format %{ "DIVMODL ($dst1src1, $dst2) $src2" %}
 6502   ins_encode %{
 6503     Register d1s1 = $dst1src1$$Register;
 6504     Register d2   = $dst2$$Register;
 6505     Register s2   = $src2$$Register;
 6506 
 6507     Label do_div, done_div;
 6508     if (VM_Version::has_CompareBranch()) {
 6509       __ z_cgij(s2, -1, Assembler::bcondNotEqual, do_div);
 6510     } else {
 6511       __ z_cghi(s2, -1);
 6512       __ z_brne(do_div);
 6513     }
 6514     __ z_lcgr(d1s1, d1s1);
 6515     // indicate unused result
 6516     (void) __ clear_reg(d2, true, false);
 6517     __ z_bru(done_div);
 6518     __ bind(do_div);
 6519     __ z_dsgr(d2, s2);
 6520     __ bind(done_div);
 6521   %}
 6522   ins_pipe(pipe_class_dummy);
 6523 %}
 6524 
 6525 // Register Long Division
 6526 instruct divL_reg_reg(roddRegL dst, iRegL src, revenRegL tmp, flagsReg cr) %{
 6527   match(Set dst (DivL dst src));
 6528   effect(KILL tmp, KILL cr);
 6529   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6530   size((VM_Version::has_CompareBranch() ? 18 : 20));
 6531   format %{ "DIVG_checked  $dst, $src\t # long, treats special case 0x80../-1" %}
 6532   ins_encode %{
 6533     Register b = $src$$Register;
 6534     Register t = $dst$$Register;
 6535 
 6536     Label done_div;
 6537     __ z_lcgr(t, t);    // Does no harm. divisor is in other register.
 6538     if (VM_Version::has_CompareBranch()) {
 6539       __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
 6540     } else {
 6541       __ z_cghi(b, -1);
 6542       __ z_bre(done_div);
 6543     }
 6544     __ z_lcgr(t, t);    // Restore sign.
 6545     __ z_dsgr(t->predecessor()/* t is odd part of a register pair. */, b);
 6546     __ bind(done_div);
 6547   %}
 6548   ins_pipe(pipe_class_dummy);
 6549 %}
 6550 
 6551 // Immediate Long Division
 6552 instruct divL_reg_imm16(roddRegL dst, iRegL src1, immL16 src2, revenRegL tmp, flagsReg cr) %{
 6553   match(Set dst (DivL src1 src2));
 6554   effect(KILL tmp, KILL cr);  // R0 is killed, too.
 6555   ins_cost(2 * DEFAULT_COST);
 6556   // TODO: s390 port size(VARIABLE_SIZE);
 6557   format %{ "DIVG_const  $dst,$src1,$src2\t # long" %}
 6558   ins_encode %{
 6559     if ($src2$$constant != -1) {
 6560       __ z_lghi(Z_R0_scratch, $src2$$constant);
 6561       __ lgr_if_needed($dst$$Register, $src1$$Register);
 6562       __ z_dsgr($dst$$Register->predecessor()/* Dst is odd part of a register pair. */, Z_R0_scratch);
 6563     } else {
 6564       __ z_lcgr($dst$$Register, $src1$$Register);
 6565     }
 6566   %}
 6567   ins_pipe(pipe_class_dummy);
 6568 %}
 6569 
 6570 // REM
 6571 
 6572 // Integer Remainder
 6573 // Register Remainder
 6574 instruct modI_reg_reg(revenRegI dst, iRegI src1, noOdd_iRegI src2, roddRegI tmp, flagsReg cr) %{
 6575   match(Set dst (ModI src1 src2));
 6576   effect(KILL tmp, KILL cr);
 6577   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6578   // TODO: s390 port size(VARIABLE_SIZE);
 6579   format %{ "MOD_checked   $dst,$src1,$src2" %}
 6580   ins_encode %{
 6581     Register a = $src1$$Register;
 6582     Register b = $src2$$Register;
 6583     Register t = $dst$$Register;
 6584     assert_different_registers(t->successor(), b);
 6585 
 6586     Label do_div, done_div;
 6587 
 6588     if ((t->encoding() != b->encoding()) && (t->encoding() != a->encoding())) {
 6589       (void) __ clear_reg(t, true, false);  // Does no harm. Operands are in other regs.
 6590       if (VM_Version::has_CompareBranch()) {
 6591         __ z_cij(b, -1, Assembler::bcondEqual, done_div);
 6592       } else {
 6593         __ z_chi(b, -1);
 6594         __ z_bre(done_div);
 6595       }
 6596       __ z_lgfr(t->successor(), a);
 6597       __ z_dsgfr(t/* t is even part of a register pair. */, b);
 6598     } else {
 6599       if (VM_Version::has_CompareBranch()) {
 6600         __ z_cij(b, -1, Assembler::bcondNotEqual, do_div);
 6601       } else {
 6602         __ z_chi(b, -1);
 6603         __ z_brne(do_div);
 6604       }
 6605       __ clear_reg(t, true, false);
 6606       __ z_bru(done_div);
 6607       __ bind(do_div);
 6608       __ z_lgfr(t->successor(), a);
 6609       __ z_dsgfr(t/* t is even part of a register pair. */, b);
 6610     }
 6611     __ bind(done_div);
 6612   %}
 6613   ins_pipe(pipe_class_dummy);
 6614 %}
 6615 
 6616 // Immediate Remainder
 6617 instruct modI_reg_imm16(revenRegI dst, iRegI src1, immI16 src2, roddRegI tmp, flagsReg cr) %{
 6618   match(Set dst (ModI src1 src2));
 6619   effect(KILL tmp, KILL cr); // R0 is killed, too.
 6620   ins_cost(3 * DEFAULT_COST);
 6621   // TODO: s390 port size(VARIABLE_SIZE);
 6622   format %{ "MOD_const  $dst,src1,$src2" %}
 6623   ins_encode %{
 6624     assert_different_registers($dst$$Register, $src1$$Register);
 6625     assert_different_registers($dst$$Register->successor(), $src1$$Register);
 6626     int divisor = $src2$$constant;
 6627 
 6628     if (divisor != -1) {
 6629       __ z_lghi(Z_R0_scratch, divisor);
 6630       __ z_lgfr($dst$$Register->successor(), $src1$$Register);
 6631       __ z_dsgfr($dst$$Register/* Dst is even part of a register pair. */, Z_R0_scratch); // Instruction kills tmp.
 6632     } else {
 6633       __ clear_reg($dst$$Register, true, false);
 6634     }
 6635   %}
 6636   ins_pipe(pipe_class_dummy);
 6637 %}
 6638 
 6639 // Register Long Remainder
 6640 instruct modL_reg_reg(revenRegL dst, roddRegL src1, iRegL src2, flagsReg cr) %{
 6641   match(Set dst (ModL src1 src2));
 6642   effect(KILL src1, KILL cr); // R0 is killed, too.
 6643   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 6644   // TODO: s390 port size(VARIABLE_SIZE);
 6645   format %{ "MODG_checked   $dst,$src1,$src2" %}
 6646   ins_encode %{
 6647     Register a = $src1$$Register;
 6648     Register b = $src2$$Register;
 6649     Register t = $dst$$Register;
 6650     assert(t->successor() == a, "(t,a) is an even-odd pair" );
 6651 
 6652     Label do_div, done_div;
 6653     if (t->encoding() != b->encoding()) {
 6654       (void) __ clear_reg(t, true, false); // Does no harm. Dividend is in successor.
 6655       if (VM_Version::has_CompareBranch()) {
 6656         __ z_cgij(b, -1, Assembler::bcondEqual, done_div);
 6657       } else {
 6658         __ z_cghi(b, -1);
 6659         __ z_bre(done_div);
 6660       }
 6661       __ z_dsgr(t, b);
 6662     } else {
 6663       if (VM_Version::has_CompareBranch()) {
 6664         __ z_cgij(b, -1, Assembler::bcondNotEqual, do_div);
 6665       } else {
 6666         __ z_cghi(b, -1);
 6667         __ z_brne(do_div);
 6668       }
 6669       __ clear_reg(t, true, false);
 6670       __ z_bru(done_div);
 6671       __ bind(do_div);
 6672       __ z_dsgr(t, b);
 6673     }
 6674     __ bind(done_div);
 6675   %}
 6676   ins_pipe(pipe_class_dummy);
 6677 %}
 6678 
 6679 // Register Long Remainder
 6680 instruct modL_reg_imm16(revenRegL dst, iRegL src1, immL16 src2, roddRegL tmp, flagsReg cr) %{
 6681   match(Set dst (ModL src1 src2));
 6682   effect(KILL tmp, KILL cr); // R0 is killed, too.
 6683   ins_cost(3 * DEFAULT_COST);
 6684   // TODO: s390 port size(VARIABLE_SIZE);
 6685   format %{ "MODG_const  $dst,src1,$src2\t # long" %}
 6686   ins_encode %{
 6687     int divisor = $src2$$constant;
 6688     if (divisor != -1) {
 6689       __ z_lghi(Z_R0_scratch, divisor);
 6690       __ z_lgr($dst$$Register->successor(), $src1$$Register);
 6691       __ z_dsgr($dst$$Register /* Dst is even part of a register pair. */, Z_R0_scratch);  // Instruction kills tmp.
 6692     } else {
 6693       __ clear_reg($dst$$Register, true, false);
 6694     }
 6695   %}
 6696   ins_pipe(pipe_class_dummy);
 6697 %}
 6698 
 6699 // SHIFT
 6700 
 6701 // Shift left logical
 6702 
 6703 // Register Shift Left variable
 6704 instruct sllI_reg_reg(iRegI dst, iRegI src, iRegI nbits, flagsReg cr) %{
 6705   match(Set dst (LShiftI src nbits));
 6706   effect(KILL cr); // R1 is killed, too.
 6707   ins_cost(3 * DEFAULT_COST);
 6708   size(14);
 6709   format %{ "SLL     $dst,$src,[$nbits] & 31\t # use RISC-like SLLG also for int" %}
 6710   ins_encode %{
 6711     __ z_lgr(Z_R1_scratch, $nbits$$Register);
 6712     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6713     __ z_sllg($dst$$Register, $src$$Register, 0, Z_R1_scratch);
 6714   %}
 6715   ins_pipe(pipe_class_dummy);
 6716 %}
 6717 
 6718 // Register Shift Left Immediate
 6719 // Constant shift count is masked in ideal graph already.
 6720 instruct sllI_reg_imm(iRegI dst, iRegI src, immI nbits) %{
 6721   match(Set dst (LShiftI src nbits));
 6722   size(6);
 6723   format %{ "SLL     $dst,$src,$nbits\t # use RISC-like SLLG also for int" %}
 6724   ins_encode %{
 6725     int Nbit = $nbits$$constant;
 6726     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6727     __ z_sllg($dst$$Register, $src$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6728   %}
 6729   ins_pipe(pipe_class_dummy);
 6730 %}
 6731 
 6732 // Register Shift Left Immediate by 1bit
 6733 instruct sllI_reg_imm_1(iRegI dst, iRegI src, immI_1 nbits) %{
 6734   match(Set dst (LShiftI src nbits));
 6735   predicate(PreferLAoverADD);
 6736   ins_cost(DEFAULT_COST_LOW);
 6737   size(4);
 6738   format %{ "LA      $dst,#0($src,$src)\t # SLL by 1 (int)" %}
 6739   ins_encode %{ __ z_la($dst$$Register, 0, $src$$Register, $src$$Register); %}
 6740   ins_pipe(pipe_class_dummy);
 6741 %}
 6742 
 6743 // Register Shift Left Long
 6744 instruct sllL_reg_reg(iRegL dst, iRegL src1, iRegI nbits) %{
 6745   match(Set dst (LShiftL src1 nbits));
 6746   size(6);
 6747   format %{ "SLLG    $dst,$src1,[$nbits]" %}
 6748   opcode(SLLG_ZOPC);
 6749   ins_encode(z_rsyform_reg_reg(dst, src1, nbits));
 6750   ins_pipe(pipe_class_dummy);
 6751 %}
 6752 
 6753 // Register Shift Left Long Immediate
 6754 instruct sllL_reg_imm(iRegL dst, iRegL src1, immI nbits) %{
 6755   match(Set dst (LShiftL src1 nbits));
 6756   size(6);
 6757   format %{ "SLLG    $dst,$src1,$nbits" %}
 6758   opcode(SLLG_ZOPC);
 6759   ins_encode(z_rsyform_const(dst, src1, nbits));
 6760   ins_pipe(pipe_class_dummy);
 6761 %}
 6762 
 6763 // Register Shift Left Long Immediate by 1bit
 6764 instruct sllL_reg_imm_1(iRegL dst, iRegL src1, immI_1 nbits) %{
 6765   match(Set dst (LShiftL src1 nbits));
 6766   predicate(PreferLAoverADD);
 6767   ins_cost(DEFAULT_COST_LOW);
 6768   size(4);
 6769   format %{ "LA      $dst,#0($src1,$src1)\t # SLLG by 1 (long)" %}
 6770   ins_encode %{ __ z_la($dst$$Register, 0, $src1$$Register, $src1$$Register); %}
 6771   ins_pipe(pipe_class_dummy);
 6772 %}
 6773 
 6774 // Shift right arithmetic
 6775 
 6776 // Register Arithmetic Shift Right
 6777 instruct sraI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 6778   match(Set dst (RShiftI dst src));
 6779   effect(KILL cr); // R1 is killed, too.
 6780   ins_cost(3 * DEFAULT_COST);
 6781   size(12);
 6782   format %{ "SRA     $dst,[$src] & 31" %}
 6783   ins_encode %{
 6784     __ z_lgr(Z_R1_scratch, $src$$Register);
 6785     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6786     __ z_sra($dst$$Register, 0, Z_R1_scratch);
 6787   %}
 6788   ins_pipe(pipe_class_dummy);
 6789 %}
 6790 
 6791 // Register Arithmetic Shift Right Immediate
 6792 // Constant shift count is masked in ideal graph already.
 6793 instruct sraI_reg_imm(iRegI dst, immI src, flagsReg cr) %{
 6794   match(Set dst (RShiftI dst src));
 6795   effect(KILL cr);
 6796   size(4);
 6797   format %{ "SRA     $dst,$src" %}
 6798   ins_encode %{
 6799     int Nbit = $src$$constant;
 6800     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6801     __ z_sra($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6802   %}
 6803   ins_pipe(pipe_class_dummy);
 6804 %}
 6805 
 6806 // Register Arithmetic Shift Right Long
 6807 instruct sraL_reg_reg(iRegL dst, iRegL src1, iRegI src2, flagsReg cr) %{
 6808   match(Set dst (RShiftL src1 src2));
 6809   effect(KILL cr);
 6810   size(6);
 6811   format %{ "SRAG    $dst,$src1,[$src2]" %}
 6812   opcode(SRAG_ZOPC);
 6813   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
 6814   ins_pipe(pipe_class_dummy);
 6815 %}
 6816 
 6817 // Register Arithmetic Shift Right Long Immediate
 6818 instruct sraL_reg_imm(iRegL dst, iRegL src1, immI src2, flagsReg cr) %{
 6819   match(Set dst (RShiftL src1 src2));
 6820   effect(KILL cr);
 6821   size(6);
 6822   format %{ "SRAG    $dst,$src1,$src2" %}
 6823   opcode(SRAG_ZOPC);
 6824   ins_encode(z_rsyform_const(dst, src1, src2));
 6825   ins_pipe(pipe_class_dummy);
 6826 %}
 6827 
 6828 //  Shift right logical
 6829 
 6830 // Register Shift Right
 6831 instruct srlI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 6832   match(Set dst (URShiftI dst src));
 6833   effect(KILL cr); // R1 is killed, too.
 6834   ins_cost(3 * DEFAULT_COST);
 6835   size(12);
 6836   format %{ "SRL     $dst,[$src] & 31" %}
 6837   ins_encode %{
 6838     __ z_lgr(Z_R1_scratch, $src$$Register);
 6839     __ z_nill(Z_R1_scratch, BitsPerJavaInteger-1);
 6840     __ z_srl($dst$$Register, 0, Z_R1_scratch);
 6841   %}
 6842   ins_pipe(pipe_class_dummy);
 6843 %}
 6844 
 6845 // Register Shift Right Immediate
 6846 // Constant shift count is masked in ideal graph already.
 6847 instruct srlI_reg_imm(iRegI dst, immI src) %{
 6848   match(Set dst (URShiftI dst src));
 6849   size(4);
 6850   format %{ "SRL     $dst,$src" %}
 6851   ins_encode %{
 6852     int Nbit = $src$$constant;
 6853     assert((Nbit & (BitsPerJavaInteger - 1)) == Nbit, "Check shift mask in ideal graph");
 6854     __ z_srl($dst$$Register, Nbit & (BitsPerJavaInteger - 1), Z_R0);
 6855   %}
 6856   ins_pipe(pipe_class_dummy);
 6857 %}
 6858 
 6859 // Register Shift Right Long
 6860 instruct srlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
 6861   match(Set dst (URShiftL src1 src2));
 6862   size(6);
 6863   format %{ "SRLG    $dst,$src1,[$src2]" %}
 6864   opcode(SRLG_ZOPC);
 6865   ins_encode(z_rsyform_reg_reg(dst, src1, src2));
 6866   ins_pipe(pipe_class_dummy);
 6867 %}
 6868 
 6869 // Register Shift Right Long Immediate
 6870 instruct srlL_reg_imm(iRegL dst, iRegL src1, immI src2) %{
 6871   match(Set dst (URShiftL src1 src2));
 6872   size(6);
 6873   format %{ "SRLG    $dst,$src1,$src2" %}
 6874   opcode(SRLG_ZOPC);
 6875   ins_encode(z_rsyform_const(dst, src1, src2));
 6876   ins_pipe(pipe_class_dummy);
 6877 %}
 6878 
 6879 // Register Shift Right Immediate with a CastP2X
 6880 instruct srlP_reg_imm(iRegL dst, iRegP_N2P src1, immI src2) %{
 6881   match(Set dst (URShiftL (CastP2X src1) src2));
 6882   size(6);
 6883   format %{ "SRLG    $dst,$src1,$src2\t # Cast ptr $src1 to long and shift" %}
 6884   opcode(SRLG_ZOPC);
 6885   ins_encode(z_rsyform_const(dst, src1, src2));
 6886   ins_pipe(pipe_class_dummy);
 6887 %}
 6888 
 6889 //----------Rotate Instructions------------------------------------------------
 6890 
 6891 // Rotate left 32bit.
 6892 instruct rotlI_reg_immI8(iRegI dst, iRegI src, immI8 lshift, immI8 rshift) %{
 6893   match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift)));
 6894   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
 6895   size(6);
 6896   format %{ "RLL     $dst,$src,$lshift\t # ROTL32" %}
 6897   opcode(RLL_ZOPC);
 6898   ins_encode(z_rsyform_const(dst, src, lshift));
 6899   ins_pipe(pipe_class_dummy);
 6900 %}
 6901 
 6902 // Rotate left 64bit.
 6903 instruct rotlL_reg_immI8(iRegL dst, iRegL src, immI8 lshift, immI8 rshift) %{
 6904   match(Set dst (OrL (LShiftL src lshift) (URShiftL src rshift)));
 6905   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
 6906   size(6);
 6907   format %{ "RLLG    $dst,$src,$lshift\t # ROTL64" %}
 6908   opcode(RLLG_ZOPC);
 6909   ins_encode(z_rsyform_const(dst, src, lshift));
 6910   ins_pipe(pipe_class_dummy);
 6911 %}
 6912 
 6913 // Rotate right 32bit.
 6914 instruct rotrI_reg_immI8(iRegI dst, iRegI src, immI8 rshift, immI8 lshift) %{
 6915   match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift)));
 6916   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
 6917   // TODO: s390 port size(FIXED_SIZE);
 6918   format %{ "RLL     $dst,$src,$rshift\t # ROTR32" %}
 6919   opcode(RLL_ZOPC);
 6920   ins_encode(z_rsyform_const(dst, src, rshift));
 6921   ins_pipe(pipe_class_dummy);
 6922 %}
 6923 
 6924 // Rotate right 64bit.
 6925 instruct rotrL_reg_immI8(iRegL dst, iRegL src, immI8 rshift, immI8 lshift) %{
 6926   match(Set dst (OrL (URShiftL src rshift) (LShiftL src lshift)));
 6927   predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
 6928   // TODO: s390 port size(FIXED_SIZE);
 6929   format %{ "RLLG    $dst,$src,$rshift\t # ROTR64" %}
 6930   opcode(RLLG_ZOPC);
 6931   ins_encode(z_rsyform_const(dst, src, rshift));
 6932   ins_pipe(pipe_class_dummy);
 6933 %}
 6934 
 6935 
 6936 //----------Overflow Math Instructions-----------------------------------------
 6937 
 6938 instruct overflowAddI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 6939   match(Set cr (OverflowAddI op1 op2));
 6940   effect(DEF cr, USE op1, USE op2);
 6941   // TODO: s390 port size(FIXED_SIZE);
 6942   format %{ "AR      $op1,$op2\t # overflow check int" %}
 6943   ins_encode %{
 6944     __ z_lr(Z_R0_scratch, $op1$$Register);
 6945     __ z_ar(Z_R0_scratch, $op2$$Register);
 6946   %}
 6947   ins_pipe(pipe_class_dummy);
 6948 %}
 6949 
 6950 instruct overflowAddI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 6951   match(Set cr (OverflowAddI op1 op2));
 6952   effect(DEF cr, USE op1, USE op2);
 6953   // TODO: s390 port size(VARIABLE_SIZE);
 6954   format %{ "AR      $op1,$op2\t # overflow check int" %}
 6955   ins_encode %{
 6956     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
 6957     __ z_ar(Z_R0_scratch, $op1$$Register);
 6958   %}
 6959   ins_pipe(pipe_class_dummy);
 6960 %}
 6961 
 6962 instruct overflowAddL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 6963   match(Set cr (OverflowAddL op1 op2));
 6964   effect(DEF cr, USE op1, USE op2);
 6965   // TODO: s390 port size(FIXED_SIZE);
 6966   format %{ "AGR     $op1,$op2\t # overflow check long" %}
 6967   ins_encode %{
 6968     __ z_lgr(Z_R0_scratch, $op1$$Register);
 6969     __ z_agr(Z_R0_scratch, $op2$$Register);
 6970   %}
 6971   ins_pipe(pipe_class_dummy);
 6972 %}
 6973 
 6974 instruct overflowAddL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
 6975   match(Set cr (OverflowAddL op1 op2));
 6976   effect(DEF cr, USE op1, USE op2);
 6977   // TODO: s390 port size(VARIABLE_SIZE);
 6978   format %{ "AGR     $op1,$op2\t # overflow check long" %}
 6979   ins_encode %{
 6980     __ load_const_optimized(Z_R0_scratch, $op2$$constant);
 6981     __ z_agr(Z_R0_scratch, $op1$$Register);
 6982   %}
 6983   ins_pipe(pipe_class_dummy);
 6984 %}
 6985 
 6986 instruct overflowSubI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 6987   match(Set cr (OverflowSubI op1 op2));
 6988   effect(DEF cr, USE op1, USE op2);
 6989   // TODO: s390 port size(FIXED_SIZE);
 6990   format %{ "SR      $op1,$op2\t # overflow check int" %}
 6991   ins_encode %{
 6992     __ z_lr(Z_R0_scratch, $op1$$Register);
 6993     __ z_sr(Z_R0_scratch, $op2$$Register);
 6994   %}
 6995   ins_pipe(pipe_class_dummy);
 6996 %}
 6997 
 6998 instruct overflowSubI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 6999   match(Set cr (OverflowSubI op1 op2));
 7000   effect(DEF cr, USE op1, USE op2);
 7001   // TODO: s390 port size(VARIABLE_SIZE);
 7002   format %{ "SR      $op1,$op2\t # overflow check int" %}
 7003   ins_encode %{
 7004     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
 7005     __ z_lr(Z_R0_scratch, $op1$$Register);
 7006     __ z_sr(Z_R0_scratch, Z_R1_scratch);
 7007   %}
 7008   ins_pipe(pipe_class_dummy);
 7009 %}
 7010 
 7011 instruct overflowSubL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 7012   match(Set cr (OverflowSubL op1 op2));
 7013   effect(DEF cr, USE op1, USE op2);
 7014   // TODO: s390 port size(FIXED_SIZE);
 7015   format %{ "SGR     $op1,$op2\t # overflow check long" %}
 7016   ins_encode %{
 7017     __ z_lgr(Z_R0_scratch, $op1$$Register);
 7018     __ z_sgr(Z_R0_scratch, $op2$$Register);
 7019   %}
 7020   ins_pipe(pipe_class_dummy);
 7021 %}
 7022 
 7023 instruct overflowSubL_reg_imm(flagsReg cr, iRegL op1, immL op2) %{
 7024   match(Set cr (OverflowSubL op1 op2));
 7025   effect(DEF cr, USE op1, USE op2);
 7026   // TODO: s390 port size(VARIABLE_SIZE);
 7027   format %{ "SGR     $op1,$op2\t # overflow check long" %}
 7028   ins_encode %{
 7029     __ load_const_optimized(Z_R1_scratch, $op2$$constant);
 7030     __ z_lgr(Z_R0_scratch, $op1$$Register);
 7031     __ z_sgr(Z_R0_scratch, Z_R1_scratch);
 7032   %}
 7033   ins_pipe(pipe_class_dummy);
 7034 %}
 7035 
 7036 instruct overflowNegI_rReg(flagsReg cr, immI_0 zero, iRegI op2) %{
 7037   match(Set cr (OverflowSubI zero op2));
 7038   effect(DEF cr, USE op2);
 7039   format %{ "NEG    $op2\t # overflow check int" %}
 7040   ins_encode %{
 7041     __ clear_reg(Z_R0_scratch, false, false);
 7042     __ z_sr(Z_R0_scratch, $op2$$Register);
 7043   %}
 7044   ins_pipe(pipe_class_dummy);
 7045 %}
 7046 
 7047 instruct overflowNegL_rReg(flagsReg cr, immL_0 zero, iRegL op2) %{
 7048   match(Set cr (OverflowSubL zero op2));
 7049   effect(DEF cr, USE op2);
 7050   format %{ "NEGG    $op2\t # overflow check long" %}
 7051   ins_encode %{
 7052     __ clear_reg(Z_R0_scratch, true, false);
 7053     __ z_sgr(Z_R0_scratch, $op2$$Register);
 7054   %}
 7055   ins_pipe(pipe_class_dummy);
 7056 %}
 7057 
 7058 // No intrinsics for multiplication, since there is no easy way
 7059 // to check for overflow.
 7060 
 7061 
 7062 //----------Floating Point Arithmetic Instructions-----------------------------
 7063 
 7064 //  ADD
 7065 
 7066 //  Add float single precision
 7067 instruct addF_reg_reg(regF dst, regF src, flagsReg cr) %{
 7068   match(Set dst (AddF dst src));
 7069   effect(KILL cr);
 7070   ins_cost(ALU_REG_COST);
 7071   size(4);
 7072   format %{ "AEBR     $dst,$src" %}
 7073   opcode(AEBR_ZOPC);
 7074   ins_encode(z_rreform(dst, src));
 7075   ins_pipe(pipe_class_dummy);
 7076 %}
 7077 
 7078 instruct addF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
 7079   match(Set dst (AddF dst (LoadF src)));
 7080   effect(KILL cr);
 7081   ins_cost(ALU_MEMORY_COST);
 7082   size(6);
 7083   format %{ "AEB      $dst,$src\t # floatMemory" %}
 7084   opcode(AEB_ZOPC);
 7085   ins_encode(z_form_rt_memFP(dst, src));
 7086   ins_pipe(pipe_class_dummy);
 7087 %}
 7088 
 7089 // Add float double precision
 7090 instruct addD_reg_reg(regD dst, regD src, flagsReg cr) %{
 7091   match(Set dst (AddD dst src));
 7092   effect(KILL cr);
 7093   ins_cost(ALU_REG_COST);
 7094   size(4);
 7095   format %{ "ADBR     $dst,$src" %}
 7096   opcode(ADBR_ZOPC);
 7097   ins_encode(z_rreform(dst, src));
 7098   ins_pipe(pipe_class_dummy);
 7099 %}
 7100 
 7101 instruct addD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
 7102   match(Set dst (AddD dst (LoadD src)));
 7103   effect(KILL cr);
 7104   ins_cost(ALU_MEMORY_COST);
 7105   size(6);
 7106   format %{ "ADB      $dst,$src\t # doubleMemory" %}
 7107   opcode(ADB_ZOPC);
 7108   ins_encode(z_form_rt_memFP(dst, src));
 7109   ins_pipe(pipe_class_dummy);
 7110 %}
 7111 
 7112 // SUB
 7113 
 7114 // Sub float single precision
 7115 instruct subF_reg_reg(regF dst, regF src, flagsReg cr) %{
 7116   match(Set dst (SubF dst src));
 7117   effect(KILL cr);
 7118   ins_cost(ALU_REG_COST);
 7119   size(4);
 7120   format %{ "SEBR     $dst,$src" %}
 7121   opcode(SEBR_ZOPC);
 7122   ins_encode(z_rreform(dst, src));
 7123   ins_pipe(pipe_class_dummy);
 7124 %}
 7125 
 7126 instruct subF_reg_mem(regF dst, memoryRX src, flagsReg cr)%{
 7127   match(Set dst (SubF dst (LoadF src)));
 7128   effect(KILL cr);
 7129   ins_cost(ALU_MEMORY_COST);
 7130   size(6);
 7131   format %{ "SEB      $dst,$src\t # floatMemory" %}
 7132   opcode(SEB_ZOPC);
 7133   ins_encode(z_form_rt_memFP(dst, src));
 7134   ins_pipe(pipe_class_dummy);
 7135 %}
 7136 
 7137 //  Sub float double precision
 7138 instruct subD_reg_reg(regD dst, regD src, flagsReg cr) %{
 7139   match(Set dst (SubD dst src));
 7140   effect(KILL cr);
 7141   ins_cost(ALU_REG_COST);
 7142   size(4);
 7143   format %{ "SDBR     $dst,$src" %}
 7144   opcode(SDBR_ZOPC);
 7145   ins_encode(z_rreform(dst, src));
 7146   ins_pipe(pipe_class_dummy);
 7147 %}
 7148 
 7149 instruct subD_reg_mem(regD dst, memoryRX src, flagsReg cr)%{
 7150   match(Set dst (SubD dst (LoadD src)));
 7151   effect(KILL cr);
 7152   ins_cost(ALU_MEMORY_COST);
 7153   size(6);
 7154   format %{ "SDB      $dst,$src\t # doubleMemory" %}
 7155   opcode(SDB_ZOPC);
 7156   ins_encode(z_form_rt_memFP(dst, src));
 7157   ins_pipe(pipe_class_dummy);
 7158 %}
 7159 
 7160 // MUL
 7161 
 7162 // Mul float single precision
 7163 instruct mulF_reg_reg(regF dst, regF src) %{
 7164   match(Set dst (MulF dst src));
 7165   // CC unchanged by MUL.
 7166   ins_cost(ALU_REG_COST);
 7167   size(4);
 7168   format %{ "MEEBR    $dst,$src" %}
 7169   opcode(MEEBR_ZOPC);
 7170   ins_encode(z_rreform(dst, src));
 7171   ins_pipe(pipe_class_dummy);
 7172 %}
 7173 
 7174 instruct mulF_reg_mem(regF dst, memoryRX src)%{
 7175   match(Set dst (MulF dst (LoadF src)));
 7176   // CC unchanged by MUL.
 7177   ins_cost(ALU_MEMORY_COST);
 7178   size(6);
 7179   format %{ "MEEB     $dst,$src\t # floatMemory" %}
 7180   opcode(MEEB_ZOPC);
 7181   ins_encode(z_form_rt_memFP(dst, src));
 7182   ins_pipe(pipe_class_dummy);
 7183 %}
 7184 
 7185 //  Mul float double precision
 7186 instruct mulD_reg_reg(regD dst, regD src) %{
 7187   match(Set dst (MulD dst src));
 7188   // CC unchanged by MUL.
 7189   ins_cost(ALU_REG_COST);
 7190   size(4);
 7191   format %{ "MDBR     $dst,$src" %}
 7192   opcode(MDBR_ZOPC);
 7193   ins_encode(z_rreform(dst, src));
 7194   ins_pipe(pipe_class_dummy);
 7195 %}
 7196 
 7197 instruct mulD_reg_mem(regD dst, memoryRX src)%{
 7198   match(Set dst (MulD dst (LoadD src)));
 7199   // CC unchanged by MUL.
 7200   ins_cost(ALU_MEMORY_COST);
 7201   size(6);
 7202   format %{ "MDB      $dst,$src\t # doubleMemory" %}
 7203   opcode(MDB_ZOPC);
 7204   ins_encode(z_form_rt_memFP(dst, src));
 7205   ins_pipe(pipe_class_dummy);
 7206 %}
 7207 
 7208 // Multiply-Accumulate
 7209 // src1 * src2 + dst
 7210 instruct maddF_reg_reg(regF dst, regF src1, regF src2) %{
 7211   match(Set dst (FmaF dst (Binary src1 src2)));
 7212   // CC unchanged by MUL-ADD.
 7213   ins_cost(ALU_REG_COST);
 7214   size(4);
 7215   format %{ "MAEBR    $dst, $src1, $src2" %}
 7216   ins_encode %{
 7217     __ z_maebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7218   %}
 7219   ins_pipe(pipe_class_dummy);
 7220 %}
 7221 
 7222 // src1 * src2 + dst
 7223 instruct maddD_reg_reg(regD dst, regD src1, regD src2) %{
 7224   match(Set dst (FmaD dst (Binary src1 src2)));
 7225   // CC unchanged by MUL-ADD.
 7226   ins_cost(ALU_REG_COST);
 7227   size(4);
 7228   format %{ "MADBR    $dst, $src1, $src2" %}
 7229   ins_encode %{
 7230     __ z_madbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7231   %}
 7232   ins_pipe(pipe_class_dummy);
 7233 %}
 7234 
 7235 // src1 * src2 - dst
 7236 instruct msubF_reg_reg(regF dst, regF src1, regF src2) %{
 7237   match(Set dst (FmaF (NegF dst) (Binary src1 src2)));
 7238   // CC unchanged by MUL-SUB.
 7239   ins_cost(ALU_REG_COST);
 7240   size(4);
 7241   format %{ "MSEBR    $dst, $src1, $src2" %}
 7242   ins_encode %{
 7243     __ z_msebr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7244   %}
 7245   ins_pipe(pipe_class_dummy);
 7246 %}
 7247 
 7248 // src1 * src2 - dst
 7249 instruct msubD_reg_reg(regD dst, regD src1, regD src2) %{
 7250   match(Set dst (FmaD (NegD dst) (Binary src1 src2)));
 7251   // CC unchanged by MUL-SUB.
 7252   ins_cost(ALU_REG_COST);
 7253   size(4);
 7254   format %{ "MSDBR    $dst, $src1, $src2" %}
 7255   ins_encode %{
 7256     __ z_msdbr($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister);
 7257   %}
 7258   ins_pipe(pipe_class_dummy);
 7259 %}
 7260 
 7261 // src1 * src2 + dst
 7262 instruct maddF_reg_mem(regF dst, regF src1, memoryRX src2) %{
 7263   match(Set dst (FmaF dst (Binary src1 (LoadF src2))));
 7264   // CC unchanged by MUL-ADD.
 7265   ins_cost(ALU_MEMORY_COST);
 7266   size(6);
 7267   format %{ "MAEB     $dst, $src1, $src2" %}
 7268   ins_encode %{
 7269     __ z_maeb($dst$$FloatRegister, $src1$$FloatRegister,
 7270               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7271   %}
 7272   ins_pipe(pipe_class_dummy);
 7273 %}
 7274 
 7275 // src1 * src2 + dst
 7276 instruct maddD_reg_mem(regD dst, regD src1, memoryRX src2) %{
 7277   match(Set dst (FmaD dst (Binary src1 (LoadD src2))));
 7278   // CC unchanged by MUL-ADD.
 7279   ins_cost(ALU_MEMORY_COST);
 7280   size(6);
 7281   format %{ "MADB     $dst, $src1, $src2" %}
 7282   ins_encode %{
 7283     __ z_madb($dst$$FloatRegister, $src1$$FloatRegister,
 7284               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7285   %}
 7286   ins_pipe(pipe_class_dummy);
 7287 %}
 7288 
 7289 // src1 * src2 - dst
 7290 instruct msubF_reg_mem(regF dst, regF src1, memoryRX src2) %{
 7291   match(Set dst (FmaF (NegF dst) (Binary src1 (LoadF src2))));
 7292   // CC unchanged by MUL-SUB.
 7293   ins_cost(ALU_MEMORY_COST);
 7294   size(6);
 7295   format %{ "MSEB     $dst, $src1, $src2" %}
 7296   ins_encode %{
 7297     __ z_mseb($dst$$FloatRegister, $src1$$FloatRegister,
 7298               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7299   %}
 7300   ins_pipe(pipe_class_dummy);
 7301 %}
 7302 
 7303 // src1 * src2 - dst
 7304 instruct msubD_reg_mem(regD dst, regD src1, memoryRX src2) %{
 7305   match(Set dst (FmaD (NegD dst) (Binary src1 (LoadD src2))));
 7306   // CC unchanged by MUL-SUB.
 7307   ins_cost(ALU_MEMORY_COST);
 7308   size(6);
 7309   format %{ "MSDB    $dst, $src1, $src2" %}
 7310   ins_encode %{
 7311     __ z_msdb($dst$$FloatRegister, $src1$$FloatRegister,
 7312               Address(reg_to_register_object($src2$$base), $src2$$index$$Register, $src2$$disp));
 7313   %}
 7314   ins_pipe(pipe_class_dummy);
 7315 %}
 7316 
 7317 // src1 * src2 + dst
 7318 instruct maddF_mem_reg(regF dst, memoryRX src1, regF src2) %{
 7319   match(Set dst (FmaF dst (Binary (LoadF src1) src2)));
 7320   // CC unchanged by MUL-ADD.
 7321   ins_cost(ALU_MEMORY_COST);
 7322   size(6);
 7323   format %{ "MAEB     $dst, $src1, $src2" %}
 7324   ins_encode %{
 7325     __ z_maeb($dst$$FloatRegister, $src2$$FloatRegister,
 7326               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7327   %}
 7328   ins_pipe(pipe_class_dummy);
 7329 %}
 7330 
 7331 // src1 * src2 + dst
 7332 instruct maddD_mem_reg(regD dst, memoryRX src1, regD src2) %{
 7333   match(Set dst (FmaD dst (Binary (LoadD src1) src2)));
 7334   // CC unchanged by MUL-ADD.
 7335   ins_cost(ALU_MEMORY_COST);
 7336   size(6);
 7337   format %{ "MADB     $dst, $src1, $src2" %}
 7338   ins_encode %{
 7339     __ z_madb($dst$$FloatRegister, $src2$$FloatRegister,
 7340               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7341   %}
 7342   ins_pipe(pipe_class_dummy);
 7343 %}
 7344 
 7345 // src1 * src2 - dst
 7346 instruct msubF_mem_reg(regF dst, memoryRX src1, regF src2) %{
 7347   match(Set dst (FmaF (NegF dst) (Binary (LoadF src1) src2)));
 7348   // CC unchanged by MUL-SUB.
 7349   ins_cost(ALU_MEMORY_COST);
 7350   size(6);
 7351   format %{ "MSEB     $dst, $src1, $src2" %}
 7352   ins_encode %{
 7353     __ z_mseb($dst$$FloatRegister, $src2$$FloatRegister,
 7354               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7355   %}
 7356   ins_pipe(pipe_class_dummy);
 7357 %}
 7358 
 7359 // src1 * src2 - dst
 7360 instruct msubD_mem_reg(regD dst, memoryRX src1, regD src2) %{
 7361   match(Set dst (FmaD (NegD dst) (Binary (LoadD src1) src2)));
 7362   // CC unchanged by MUL-SUB.
 7363   ins_cost(ALU_MEMORY_COST);
 7364   size(6);
 7365   format %{ "MSDB    $dst, $src1, $src2" %}
 7366   ins_encode %{
 7367     __ z_msdb($dst$$FloatRegister, $src2$$FloatRegister,
 7368               Address(reg_to_register_object($src1$$base), $src1$$index$$Register, $src1$$disp));
 7369   %}
 7370   ins_pipe(pipe_class_dummy);
 7371 %}
 7372 
 7373 //  DIV
 7374 
 7375 //  Div float single precision
 7376 instruct divF_reg_reg(regF dst, regF src) %{
 7377   match(Set dst (DivF dst src));
 7378   // CC unchanged by DIV.
 7379   ins_cost(ALU_REG_COST);
 7380   size(4);
 7381   format %{ "DEBR     $dst,$src" %}
 7382   opcode(DEBR_ZOPC);
 7383   ins_encode(z_rreform(dst, src));
 7384   ins_pipe(pipe_class_dummy);
 7385 %}
 7386 
 7387 instruct divF_reg_mem(regF dst, memoryRX src)%{
 7388   match(Set dst (DivF dst (LoadF src)));
 7389   // CC unchanged by DIV.
 7390   ins_cost(ALU_MEMORY_COST);
 7391   size(6);
 7392   format %{ "DEB      $dst,$src\t # floatMemory" %}
 7393   opcode(DEB_ZOPC);
 7394   ins_encode(z_form_rt_memFP(dst, src));
 7395   ins_pipe(pipe_class_dummy);
 7396 %}
 7397 
 7398 //  Div float double precision
 7399 instruct divD_reg_reg(regD dst, regD src) %{
 7400   match(Set dst (DivD dst src));
 7401   // CC unchanged by DIV.
 7402   ins_cost(ALU_REG_COST);
 7403   size(4);
 7404   format %{ "DDBR     $dst,$src" %}
 7405   opcode(DDBR_ZOPC);
 7406   ins_encode(z_rreform(dst, src));
 7407   ins_pipe(pipe_class_dummy);
 7408 %}
 7409 
 7410 instruct divD_reg_mem(regD dst, memoryRX src)%{
 7411   match(Set dst (DivD dst (LoadD src)));
 7412   // CC unchanged by DIV.
 7413   ins_cost(ALU_MEMORY_COST);
 7414   size(6);
 7415   format %{ "DDB      $dst,$src\t # doubleMemory" %}
 7416   opcode(DDB_ZOPC);
 7417   ins_encode(z_form_rt_memFP(dst, src));
 7418   ins_pipe(pipe_class_dummy);
 7419 %}
 7420 
 7421 // ABS
 7422 
 7423 // Absolute float single precision
 7424 instruct absF_reg(regF dst, regF src, flagsReg cr) %{
 7425   match(Set dst (AbsF src));
 7426   effect(KILL cr);
 7427   size(4);
 7428   format %{ "LPEBR    $dst,$src\t float" %}
 7429   opcode(LPEBR_ZOPC);
 7430   ins_encode(z_rreform(dst, src));
 7431   ins_pipe(pipe_class_dummy);
 7432 %}
 7433 
 7434 // Absolute float double precision
 7435 instruct absD_reg(regD dst, regD src, flagsReg cr) %{
 7436   match(Set dst (AbsD src));
 7437   effect(KILL cr);
 7438   size(4);
 7439   format %{ "LPDBR    $dst,$src\t double" %}
 7440   opcode(LPDBR_ZOPC);
 7441   ins_encode(z_rreform(dst, src));
 7442   ins_pipe(pipe_class_dummy);
 7443 %}
 7444 
 7445 //  NEG(ABS)
 7446 
 7447 // Negative absolute float single precision
 7448 instruct nabsF_reg(regF dst, regF src, flagsReg cr) %{
 7449   match(Set dst (NegF (AbsF src)));
 7450   effect(KILL cr);
 7451   size(4);
 7452   format %{ "LNEBR    $dst,$src\t float" %}
 7453   opcode(LNEBR_ZOPC);
 7454   ins_encode(z_rreform(dst, src));
 7455   ins_pipe(pipe_class_dummy);
 7456 %}
 7457 
 7458 // Negative absolute float double precision
 7459 instruct nabsD_reg(regD dst, regD src, flagsReg cr) %{
 7460   match(Set dst (NegD (AbsD src)));
 7461   effect(KILL cr);
 7462   size(4);
 7463   format %{ "LNDBR    $dst,$src\t double" %}
 7464   opcode(LNDBR_ZOPC);
 7465   ins_encode(z_rreform(dst, src));
 7466   ins_pipe(pipe_class_dummy);
 7467 %}
 7468 
 7469 // NEG
 7470 
 7471 instruct negF_reg(regF dst, regF src, flagsReg cr) %{
 7472   match(Set dst (NegF src));
 7473   effect(KILL cr);
 7474   size(4);
 7475   format %{ "NegF     $dst,$src\t float" %}
 7476   ins_encode %{ __ z_lcebr($dst$$FloatRegister, $src$$FloatRegister); %}
 7477   ins_pipe(pipe_class_dummy);
 7478 %}
 7479 
 7480 instruct negD_reg(regD dst, regD src, flagsReg cr) %{
 7481   match(Set dst (NegD src));
 7482   effect(KILL cr);
 7483   size(4);
 7484   format %{ "NegD     $dst,$src\t double" %}
 7485   ins_encode %{ __ z_lcdbr($dst$$FloatRegister, $src$$FloatRegister); %}
 7486   ins_pipe(pipe_class_dummy);
 7487 %}
 7488 
 7489 // SQRT
 7490 
 7491 // Sqrt float precision
 7492 instruct sqrtF_reg(regF dst, regF src) %{
 7493   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7494   // CC remains unchanged.
 7495   ins_cost(ALU_REG_COST);
 7496   size(4);
 7497   format %{ "SQEBR    $dst,$src" %}
 7498   opcode(SQEBR_ZOPC);
 7499   ins_encode(z_rreform(dst, src));
 7500   ins_pipe(pipe_class_dummy);
 7501 %}
 7502 
 7503 // Sqrt double precision
 7504 instruct sqrtD_reg(regD dst, regD src) %{
 7505   match(Set dst (SqrtD src));
 7506   // CC remains unchanged.
 7507   ins_cost(ALU_REG_COST);
 7508   size(4);
 7509   format %{ "SQDBR    $dst,$src" %}
 7510   opcode(SQDBR_ZOPC);
 7511   ins_encode(z_rreform(dst, src));
 7512   ins_pipe(pipe_class_dummy);
 7513 %}
 7514 
 7515 instruct sqrtF_mem(regF dst, memoryRX src) %{
 7516   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
 7517   // CC remains unchanged.
 7518   ins_cost(ALU_MEMORY_COST);
 7519   size(6);
 7520   format %{ "SQEB     $dst,$src\t # floatMemory" %}
 7521   opcode(SQEB_ZOPC);
 7522   ins_encode(z_form_rt_memFP(dst, src));
 7523   ins_pipe(pipe_class_dummy);
 7524 %}
 7525 
 7526 instruct sqrtD_mem(regD dst, memoryRX src) %{
 7527   match(Set dst (SqrtD src));
 7528   // CC remains unchanged.
 7529   ins_cost(ALU_MEMORY_COST);
 7530   // TODO: s390 port size(FIXED_SIZE);
 7531   format %{ "SQDB     $dst,$src\t # doubleMemory" %}
 7532   opcode(SQDB_ZOPC);
 7533   ins_encode(z_form_rt_memFP(dst, src));
 7534   ins_pipe(pipe_class_dummy);
 7535 %}
 7536 
 7537 //----------Logical Instructions-----------------------------------------------
 7538 
 7539 // Register And
 7540 instruct andI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7541   match(Set dst (AndI dst src));
 7542   effect(KILL cr);
 7543   ins_cost(DEFAULT_COST_LOW);
 7544   size(2);
 7545   format %{ "NR      $dst,$src\t # int" %}
 7546   opcode(NR_ZOPC);
 7547   ins_encode(z_rrform(dst, src));
 7548   ins_pipe(pipe_class_dummy);
 7549 %}
 7550 
 7551 instruct andI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7552   match(Set dst (AndI dst (LoadI src)));
 7553   effect(KILL cr);
 7554   ins_cost(MEMORY_REF_COST);
 7555   // TODO: s390 port size(VARIABLE_SIZE);
 7556   format %{ "N(Y)    $dst, $src\t # int" %}
 7557   opcode(NY_ZOPC, N_ZOPC);
 7558   ins_encode(z_form_rt_mem_opt(dst, src));
 7559   ins_pipe(pipe_class_dummy);
 7560 %}
 7561 
 7562 // Immediate And
 7563 instruct andI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
 7564   match(Set dst (AndI dst src));
 7565   effect(KILL cr);
 7566   ins_cost(DEFAULT_COST_HIGH);
 7567   size(6);
 7568   format %{ "NILF    $dst,$src" %}
 7569   opcode(NILF_ZOPC);
 7570   ins_encode(z_rilform_unsigned(dst, src));
 7571   ins_pipe(pipe_class_dummy);
 7572 %}
 7573 
 7574 instruct andI_reg_uimmI_LH1(iRegI dst, uimmI_LH1 src, flagsReg cr) %{
 7575   match(Set dst (AndI dst src));
 7576   effect(KILL cr);
 7577   ins_cost(DEFAULT_COST);
 7578   size(4);
 7579   format %{ "NILH    $dst,$src" %}
 7580   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
 7581   ins_pipe(pipe_class_dummy);
 7582 %}
 7583 
 7584 instruct andI_reg_uimmI_LL1(iRegI dst, uimmI_LL1 src, flagsReg cr) %{
 7585   match(Set dst (AndI dst src));
 7586   effect(KILL cr);
 7587   ins_cost(DEFAULT_COST);
 7588   size(4);
 7589   format %{ "NILL    $dst,$src" %}
 7590   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
 7591   ins_pipe(pipe_class_dummy);
 7592 %}
 7593 
 7594 // Register And Long
 7595 instruct andL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7596   match(Set dst (AndL dst src));
 7597   effect(KILL cr);
 7598   ins_cost(DEFAULT_COST);
 7599   size(4);
 7600   format %{ "NGR     $dst,$src\t # long" %}
 7601   opcode(NGR_ZOPC);
 7602   ins_encode(z_rreform(dst, src));
 7603   ins_pipe(pipe_class_dummy);
 7604 %}
 7605 
 7606 instruct andL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7607   match(Set dst (AndL dst (LoadL src)));
 7608   effect(KILL cr);
 7609   ins_cost(MEMORY_REF_COST);
 7610   size(Z_DISP3_SIZE);
 7611   format %{ "NG      $dst, $src\t # long" %}
 7612   opcode(NG_ZOPC, NG_ZOPC);
 7613   ins_encode(z_form_rt_mem_opt(dst, src));
 7614   ins_pipe(pipe_class_dummy);
 7615 %}
 7616 
 7617 instruct andL_reg_uimmL_LL1(iRegL dst, uimmL_LL1 src, flagsReg cr) %{
 7618   match(Set dst (AndL dst src));
 7619   effect(KILL cr);
 7620   ins_cost(DEFAULT_COST);
 7621   size(4);
 7622   format %{ "NILL    $dst,$src\t # long" %}
 7623   ins_encode %{ __ z_nill($dst$$Register, $src$$constant & 0xFFFF); %}
 7624   ins_pipe(pipe_class_dummy);
 7625 %}
 7626 
 7627 instruct andL_reg_uimmL_LH1(iRegL dst, uimmL_LH1 src, flagsReg cr) %{
 7628   match(Set dst (AndL dst src));
 7629   effect(KILL cr);
 7630   ins_cost(DEFAULT_COST);
 7631   size(4);
 7632   format %{ "NILH    $dst,$src\t # long" %}
 7633   ins_encode %{ __ z_nilh($dst$$Register, ($src$$constant >> 16) & 0xFFFF); %}
 7634   ins_pipe(pipe_class_dummy);
 7635 %}
 7636 
 7637 instruct andL_reg_uimmL_HL1(iRegL dst, uimmL_HL1 src, flagsReg cr) %{
 7638   match(Set dst (AndL dst src));
 7639   effect(KILL cr);
 7640   ins_cost(DEFAULT_COST);
 7641   size(4);
 7642   format %{ "NIHL    $dst,$src\t # long" %}
 7643   ins_encode %{ __ z_nihl($dst$$Register, ($src$$constant >> 32) & 0xFFFF); %}
 7644   ins_pipe(pipe_class_dummy);
 7645 %}
 7646 
 7647 instruct andL_reg_uimmL_HH1(iRegL dst, uimmL_HH1 src, flagsReg cr) %{
 7648   match(Set dst (AndL dst src));
 7649   effect(KILL cr);
 7650   ins_cost(DEFAULT_COST);
 7651   size(4);
 7652   format %{ "NIHH    $dst,$src\t # long" %}
 7653   ins_encode %{ __ z_nihh($dst$$Register, ($src$$constant >> 48) & 0xFFFF); %}
 7654   ins_pipe(pipe_class_dummy);
 7655 %}
 7656 
 7657 //  OR
 7658 
 7659 // Or Instructions
 7660 // Register Or
 7661 instruct orI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7662   match(Set dst (OrI dst src));
 7663   effect(KILL cr);
 7664   size(2);
 7665   format %{ "OR      $dst,$src" %}
 7666   opcode(OR_ZOPC);
 7667   ins_encode(z_rrform(dst, src));
 7668   ins_pipe(pipe_class_dummy);
 7669 %}
 7670 
 7671 instruct orI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7672   match(Set dst (OrI dst (LoadI src)));
 7673   effect(KILL cr);
 7674   ins_cost(MEMORY_REF_COST);
 7675   // TODO: s390 port size(VARIABLE_SIZE);
 7676   format %{ "O(Y)    $dst, $src\t # int" %}
 7677   opcode(OY_ZOPC, O_ZOPC);
 7678   ins_encode(z_form_rt_mem_opt(dst, src));
 7679   ins_pipe(pipe_class_dummy);
 7680 %}
 7681 
 7682 // Immediate Or
 7683 instruct orI_reg_uimm16(iRegI dst, uimmI16 con, flagsReg cr) %{
 7684   match(Set dst (OrI dst con));
 7685   effect(KILL cr);
 7686   size(4);
 7687   format %{ "OILL    $dst,$con" %}
 7688   opcode(OILL_ZOPC);
 7689   ins_encode(z_riform_unsigned(dst,con));
 7690   ins_pipe(pipe_class_dummy);
 7691 %}
 7692 
 7693 instruct orI_reg_uimm32(iRegI dst, uimmI con, flagsReg cr) %{
 7694   match(Set dst (OrI dst con));
 7695   effect(KILL cr);
 7696   ins_cost(DEFAULT_COST_HIGH);
 7697   size(6);
 7698   format %{ "OILF    $dst,$con" %}
 7699   opcode(OILF_ZOPC);
 7700   ins_encode(z_rilform_unsigned(dst,con));
 7701   ins_pipe(pipe_class_dummy);
 7702 %}
 7703 
 7704 // Register Or Long
 7705 instruct orL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7706   match(Set dst (OrL dst src));
 7707   effect(KILL cr);
 7708   ins_cost(DEFAULT_COST);
 7709   size(4);
 7710   format %{ "OGR      $dst,$src\t # long" %}
 7711   opcode(OGR_ZOPC);
 7712   ins_encode(z_rreform(dst, src));
 7713   ins_pipe(pipe_class_dummy);
 7714 %}
 7715 
 7716 instruct orL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7717   match(Set dst (OrL dst (LoadL src)));
 7718   effect(KILL cr);
 7719   ins_cost(MEMORY_REF_COST);
 7720   size(Z_DISP3_SIZE);
 7721   format %{ "OG      $dst, $src\t # long" %}
 7722   opcode(OG_ZOPC, OG_ZOPC);
 7723   ins_encode(z_form_rt_mem_opt(dst, src));
 7724   ins_pipe(pipe_class_dummy);
 7725 %}
 7726 
 7727 // Immediate Or long
 7728 instruct orL_reg_uimm16(iRegL dst, uimmL16 con, flagsReg cr) %{
 7729   match(Set dst (OrL dst con));
 7730   effect(KILL cr);
 7731   ins_cost(DEFAULT_COST);
 7732   size(4);
 7733   format %{ "OILL    $dst,$con\t # long" %}
 7734   opcode(OILL_ZOPC);
 7735   ins_encode(z_riform_unsigned(dst,con));
 7736   ins_pipe(pipe_class_dummy);
 7737 %}
 7738 
 7739 instruct orL_reg_uimm32(iRegI dst, uimmL32 con, flagsReg cr) %{
 7740   match(Set dst (OrI dst con));
 7741   effect(KILL cr);
 7742   ins_cost(DEFAULT_COST_HIGH);
 7743   // TODO: s390 port size(FIXED_SIZE);
 7744   format %{ "OILF    $dst,$con\t # long" %}
 7745   opcode(OILF_ZOPC);
 7746   ins_encode(z_rilform_unsigned(dst,con));
 7747   ins_pipe(pipe_class_dummy);
 7748 %}
 7749 
 7750 // XOR
 7751 
 7752 // Register Xor
 7753 instruct xorI_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7754   match(Set dst (XorI dst src));
 7755   effect(KILL cr);
 7756   size(2);
 7757   format %{ "XR      $dst,$src" %}
 7758   opcode(XR_ZOPC);
 7759   ins_encode(z_rrform(dst, src));
 7760   ins_pipe(pipe_class_dummy);
 7761 %}
 7762 
 7763 instruct xorI_Reg_mem(iRegI dst, memory src, flagsReg cr)%{
 7764   match(Set dst (XorI dst (LoadI src)));
 7765   effect(KILL cr);
 7766   ins_cost(MEMORY_REF_COST);
 7767   // TODO: s390 port size(VARIABLE_SIZE);
 7768   format %{ "X(Y)    $dst, $src\t # int" %}
 7769   opcode(XY_ZOPC, X_ZOPC);
 7770   ins_encode(z_form_rt_mem_opt(dst, src));
 7771   ins_pipe(pipe_class_dummy);
 7772 %}
 7773 
 7774 // Immediate Xor
 7775 instruct xorI_reg_uimm32(iRegI dst, uimmI src, flagsReg cr) %{
 7776   match(Set dst (XorI dst src));
 7777   effect(KILL cr);
 7778   ins_cost(DEFAULT_COST_HIGH);
 7779   size(6);
 7780   format %{ "XILF    $dst,$src" %}
 7781   opcode(XILF_ZOPC);
 7782   ins_encode(z_rilform_unsigned(dst, src));
 7783   ins_pipe(pipe_class_dummy);
 7784 %}
 7785 
 7786 // Register Xor Long
 7787 instruct xorL_reg_reg(iRegL dst, iRegL src, flagsReg cr) %{
 7788   match(Set dst (XorL dst src));
 7789   effect(KILL cr);
 7790   ins_cost(DEFAULT_COST);
 7791   size(4);
 7792   format %{ "XGR     $dst,$src\t # long" %}
 7793   opcode(XGR_ZOPC);
 7794   ins_encode(z_rreform(dst, src));
 7795   ins_pipe(pipe_class_dummy);
 7796 %}
 7797 
 7798 instruct xorL_Reg_mem(iRegL dst, memory src, flagsReg cr)%{
 7799   match(Set dst (XorL dst (LoadL src)));
 7800   effect(KILL cr);
 7801   ins_cost(MEMORY_REF_COST);
 7802   size(Z_DISP3_SIZE);
 7803   format %{ "XG      $dst, $src\t # long" %}
 7804   opcode(XG_ZOPC, XG_ZOPC);
 7805   ins_encode(z_form_rt_mem_opt(dst, src));
 7806   ins_pipe(pipe_class_dummy);
 7807 %}
 7808 
 7809 // Immediate Xor Long
 7810 instruct xorL_reg_uimm32(iRegL dst, uimmL32 con, flagsReg cr) %{
 7811   match(Set dst (XorL dst con));
 7812   effect(KILL cr);
 7813   ins_cost(DEFAULT_COST_HIGH);
 7814   size(6);
 7815   format %{ "XILF    $dst,$con\t # long" %}
 7816   opcode(XILF_ZOPC);
 7817   ins_encode(z_rilform_unsigned(dst,con));
 7818   ins_pipe(pipe_class_dummy);
 7819 %}
 7820 
 7821 //----------Convert to Boolean-------------------------------------------------
 7822 
 7823 // Convert integer to boolean.
 7824 instruct convI2B(iRegI dst, iRegI src, flagsReg cr) %{
 7825   match(Set dst (Conv2B src));
 7826   effect(KILL cr);
 7827   ins_cost(3 * DEFAULT_COST);
 7828   size(6);
 7829   format %{ "convI2B $dst,$src" %}
 7830   ins_encode %{
 7831     __ z_lnr($dst$$Register, $src$$Register);  // Rdst := -|Rsrc|, i.e. Rdst == 0 <=> Rsrc == 0
 7832     __ z_srl($dst$$Register, 31);              // Rdst := sign(Rdest)
 7833   %}
 7834   ins_pipe(pipe_class_dummy);
 7835 %}
 7836 
 7837 instruct convP2B(iRegI dst, iRegP_N2P src, flagsReg cr) %{
 7838   match(Set dst (Conv2B src));
 7839   effect(KILL cr);
 7840   ins_cost(3 * DEFAULT_COST);
 7841   size(10);
 7842   format %{ "convP2B $dst,$src" %}
 7843   ins_encode %{
 7844     __ z_lngr($dst$$Register, $src$$Register);     // Rdst := -|Rsrc| i.e. Rdst == 0 <=> Rsrc == 0
 7845     __ z_srlg($dst$$Register, $dst$$Register, 63); // Rdst := sign(Rdest)
 7846   %}
 7847   ins_pipe(pipe_class_dummy);
 7848 %}
 7849 
 7850 instruct cmpLTMask_reg_reg(iRegI dst, iRegI src, flagsReg cr) %{
 7851   match(Set dst (CmpLTMask dst src));
 7852   effect(KILL cr);
 7853   ins_cost(2 * DEFAULT_COST);
 7854   size(18);
 7855   format %{ "Set $dst CmpLTMask $dst,$src" %}
 7856   ins_encode %{
 7857     // Avoid signed 32 bit overflow: Do sign extend and sub 64 bit.
 7858     __ z_lgfr(Z_R0_scratch, $src$$Register);
 7859     __ z_lgfr($dst$$Register, $dst$$Register);
 7860     __ z_sgr($dst$$Register, Z_R0_scratch);
 7861     __ z_srag($dst$$Register, $dst$$Register, 63);
 7862   %}
 7863   ins_pipe(pipe_class_dummy);
 7864 %}
 7865 
 7866 instruct cmpLTMask_reg_zero(iRegI dst, immI_0 zero, flagsReg cr) %{
 7867   match(Set dst (CmpLTMask dst zero));
 7868   effect(KILL cr);
 7869   ins_cost(DEFAULT_COST);
 7870   size(4);
 7871   format %{ "Set $dst CmpLTMask $dst,$zero" %}
 7872   ins_encode %{ __ z_sra($dst$$Register, 31); %}
 7873   ins_pipe(pipe_class_dummy);
 7874 %}
 7875 
 7876 
 7877 //----------Arithmetic Conversion Instructions---------------------------------
 7878 // The conversions operations are all Alpha sorted. Please keep it that way!
 7879 
 7880 instruct convD2F_reg(regF dst, regD src) %{
 7881   match(Set dst (ConvD2F src));
 7882   // CC remains unchanged.
 7883   size(4);
 7884   format %{ "LEDBR   $dst,$src" %}
 7885   opcode(LEDBR_ZOPC);
 7886   ins_encode(z_rreform(dst, src));
 7887   ins_pipe(pipe_class_dummy);
 7888 %}
 7889 
 7890 instruct convF2I_reg(iRegI dst, regF src, flagsReg cr) %{
 7891   match(Set dst (ConvF2I src));
 7892   effect(KILL cr);
 7893   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7894   size(16);
 7895   format %{ "convF2I  $dst,$src" %}
 7896   ins_encode %{
 7897     Label done;
 7898     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
 7899     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7900     __ z_brno(done);                             // Result is zero if unordered argument.
 7901     __ z_cfebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7902     __ bind(done);
 7903   %}
 7904   ins_pipe(pipe_class_dummy);
 7905 %}
 7906 
 7907 instruct convD2I_reg(iRegI dst, regD src, flagsReg cr) %{
 7908   match(Set dst (ConvD2I src));
 7909   effect(KILL cr);
 7910   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7911   size(16);
 7912   format %{ "convD2I  $dst,$src" %}
 7913   ins_encode %{
 7914     Label done;
 7915     __ clear_reg($dst$$Register, false, false);  // Initialize with result for unordered: 0.
 7916     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7917     __ z_brno(done);                             // Result is zero if unordered argument.
 7918     __ z_cfdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7919     __ bind(done);
 7920   %}
 7921   ins_pipe(pipe_class_dummy);
 7922 %}
 7923 
 7924 instruct convF2L_reg(iRegL dst, regF src, flagsReg cr) %{
 7925   match(Set dst (ConvF2L src));
 7926   effect(KILL cr);
 7927   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7928   size(16);
 7929   format %{ "convF2L  $dst,$src" %}
 7930   ins_encode %{
 7931     Label done;
 7932     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
 7933     __ z_cebr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7934     __ z_brno(done);                             // Result is zero if unordered argument.
 7935     __ z_cgebr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7936     __ bind(done);
 7937   %}
 7938   ins_pipe(pipe_class_dummy);
 7939 %}
 7940 
 7941 instruct convD2L_reg(iRegL dst, regD src, flagsReg cr) %{
 7942   match(Set dst (ConvD2L src));
 7943   effect(KILL cr);
 7944   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 7945   size(16);
 7946   format %{ "convD2L  $dst,$src" %}
 7947   ins_encode %{
 7948     Label done;
 7949     __ clear_reg($dst$$Register, true, false);  // Initialize with result for unordered: 0.
 7950     __ z_cdbr($src$$FloatRegister, $src$$FloatRegister);   // Round.
 7951     __ z_brno(done);                             // Result is zero if unordered argument.
 7952     __ z_cgdbr($dst$$Register, $src$$FloatRegister, Assembler::to_zero);
 7953     __ bind(done);
 7954   %}
 7955   ins_pipe(pipe_class_dummy);
 7956 %}
 7957 
 7958 instruct convF2D_reg(regD dst, regF src) %{
 7959   match(Set dst (ConvF2D src));
 7960   // CC remains unchanged.
 7961   size(4);
 7962   format %{ "LDEBR   $dst,$src" %}
 7963   opcode(LDEBR_ZOPC);
 7964   ins_encode(z_rreform(dst, src));
 7965   ins_pipe(pipe_class_dummy);
 7966 %}
 7967 
 7968 instruct convF2D_mem(regD dst, memoryRX src) %{
 7969   match(Set dst (ConvF2D src));
 7970   // CC remains unchanged.
 7971   size(6);
 7972   format %{ "LDEB    $dst,$src" %}
 7973   opcode(LDEB_ZOPC);
 7974   ins_encode(z_form_rt_memFP(dst, src));
 7975   ins_pipe(pipe_class_dummy);
 7976 %}
 7977 
 7978 instruct convI2D_reg(regD dst, iRegI src) %{
 7979   match(Set dst (ConvI2D src));
 7980   // CC remains unchanged.
 7981   ins_cost(DEFAULT_COST);
 7982   size(4);
 7983   format %{ "CDFBR   $dst,$src" %}
 7984   opcode(CDFBR_ZOPC);
 7985   ins_encode(z_rreform(dst, src));
 7986   ins_pipe(pipe_class_dummy);
 7987 %}
 7988 
 7989 // Optimization that saves up to two memory operations for each conversion.
 7990 instruct convI2F_ireg(regF dst, iRegI src) %{
 7991   match(Set dst (ConvI2F src));
 7992   // CC remains unchanged.
 7993   ins_cost(DEFAULT_COST);
 7994   size(4);
 7995   format %{ "CEFBR   $dst,$src\t # convert int to float" %}
 7996   opcode(CEFBR_ZOPC);
 7997   ins_encode(z_rreform(dst, src));
 7998   ins_pipe(pipe_class_dummy);
 7999 %}
 8000 
 8001 instruct convI2L_reg(iRegL dst, iRegI src) %{
 8002   match(Set dst (ConvI2L src));
 8003   size(4);
 8004   format %{ "LGFR    $dst,$src\t # int->long" %}
 8005   opcode(LGFR_ZOPC);
 8006   ins_encode(z_rreform(dst, src));
 8007   ins_pipe(pipe_class_dummy);
 8008 %}
 8009 
 8010 // Zero-extend convert int to long.
 8011 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask) %{
 8012   match(Set dst (AndL (ConvI2L src) mask));
 8013   size(4);
 8014   format %{ "LLGFR   $dst, $src \t # zero-extend int to long" %}
 8015   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
 8016   ins_pipe(pipe_class_dummy);
 8017 %}
 8018 
 8019 // Zero-extend convert int to long.
 8020 instruct convI2L_mem_zex(iRegL dst, memory src, immL_32bits mask) %{
 8021   match(Set dst (AndL (ConvI2L (LoadI src)) mask));
 8022   // Uses load_const_optmized, so size can vary.
 8023   // TODO: s390 port size(VARIABLE_SIZE);
 8024   format %{ "LLGF    $dst, $src \t # zero-extend int to long" %}
 8025   opcode(LLGF_ZOPC, LLGF_ZOPC);
 8026   ins_encode(z_form_rt_mem_opt(dst, src));
 8027   ins_pipe(pipe_class_dummy);
 8028 %}
 8029 
 8030 // Zero-extend long
 8031 instruct zeroExtend_long(iRegL dst, iRegL src, immL_32bits mask) %{
 8032   match(Set dst (AndL src mask));
 8033   size(4);
 8034   format %{ "LLGFR   $dst, $src \t # zero-extend long to long" %}
 8035   ins_encode %{ __ z_llgfr($dst$$Register, $src$$Register); %}
 8036   ins_pipe(pipe_class_dummy);
 8037 %}
 8038 
 8039 instruct rShiftI16_lShiftI16_reg(iRegI dst, iRegI src, immI_16 amount) %{
 8040   match(Set dst (RShiftI (LShiftI src amount) amount));
 8041   size(4);
 8042   format %{ "LHR     $dst,$src\t short->int" %}
 8043   opcode(LHR_ZOPC);
 8044   ins_encode(z_rreform(dst, src));
 8045   ins_pipe(pipe_class_dummy);
 8046 %}
 8047 
 8048 instruct rShiftI24_lShiftI24_reg(iRegI dst, iRegI src, immI_24 amount) %{
 8049   match(Set dst (RShiftI (LShiftI src amount) amount));
 8050   size(4);
 8051   format %{ "LBR     $dst,$src\t byte->int" %}
 8052   opcode(LBR_ZOPC);
 8053   ins_encode(z_rreform(dst, src));
 8054   ins_pipe(pipe_class_dummy);
 8055 %}
 8056 
 8057 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
 8058   match(Set dst (MoveF2I src));
 8059   ins_cost(MEMORY_REF_COST);
 8060   size(4);
 8061   format %{ "L       $dst,$src\t # MoveF2I" %}
 8062   opcode(L_ZOPC);
 8063   ins_encode(z_form_rt_mem(dst, src));
 8064   ins_pipe(pipe_class_dummy);
 8065 %}
 8066 
 8067 // javax.imageio.stream.ImageInputStreamImpl.toFloats([B[FII)
 8068 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
 8069   match(Set dst (MoveI2F src));
 8070   ins_cost(MEMORY_REF_COST);
 8071   // TODO: s390 port size(FIXED_SIZE);
 8072   format %{ "LE      $dst,$src\t # MoveI2F" %}
 8073   opcode(LE_ZOPC);
 8074   ins_encode(z_form_rt_mem(dst, src));
 8075   ins_pipe(pipe_class_dummy);
 8076 %}
 8077 
 8078 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
 8079   match(Set dst (MoveD2L src));
 8080   ins_cost(MEMORY_REF_COST);
 8081   size(6);
 8082   format %{ "LG      $src,$dst\t # MoveD2L" %}
 8083   opcode(LG_ZOPC);
 8084   ins_encode(z_form_rt_mem(dst, src));
 8085   ins_pipe(pipe_class_dummy);
 8086 %}
 8087 
 8088 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
 8089   match(Set dst (MoveL2D src));
 8090   ins_cost(MEMORY_REF_COST);
 8091   size(4);
 8092   format %{ "LD      $dst,$src\t # MoveL2D" %}
 8093   opcode(LD_ZOPC);
 8094   ins_encode(z_form_rt_mem(dst, src));
 8095   ins_pipe(pipe_class_dummy);
 8096 %}
 8097 
 8098 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
 8099   match(Set dst (MoveI2F src));
 8100   ins_cost(MEMORY_REF_COST);
 8101   size(4);
 8102   format %{ "ST      $src,$dst\t # MoveI2F" %}
 8103   opcode(ST_ZOPC);
 8104   ins_encode(z_form_rt_mem(src, dst));
 8105   ins_pipe(pipe_class_dummy);
 8106 %}
 8107 
 8108 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
 8109   match(Set dst (MoveD2L src));
 8110   effect(DEF dst, USE src);
 8111   ins_cost(MEMORY_REF_COST);
 8112   size(4);
 8113   format %{ "STD     $src,$dst\t # MoveD2L" %}
 8114   opcode(STD_ZOPC);
 8115   ins_encode(z_form_rt_mem(src,dst));
 8116   ins_pipe(pipe_class_dummy);
 8117 %}
 8118 
 8119 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
 8120   match(Set dst (MoveL2D src));
 8121   ins_cost(MEMORY_REF_COST);
 8122   size(6);
 8123   format %{ "STG     $src,$dst\t # MoveL2D" %}
 8124   opcode(STG_ZOPC);
 8125   ins_encode(z_form_rt_mem(src,dst));
 8126   ins_pipe(pipe_class_dummy);
 8127 %}
 8128 
 8129 instruct convL2F_reg(regF dst, iRegL src) %{
 8130   match(Set dst (ConvL2F src));
 8131   // CC remains unchanged.
 8132   ins_cost(DEFAULT_COST);
 8133   size(4);
 8134   format %{ "CEGBR   $dst,$src" %}
 8135   opcode(CEGBR_ZOPC);
 8136   ins_encode(z_rreform(dst, src));
 8137   ins_pipe(pipe_class_dummy);
 8138 %}
 8139 
 8140 instruct convL2D_reg(regD dst, iRegL src) %{
 8141   match(Set dst (ConvL2D src));
 8142   // CC remains unchanged.
 8143   ins_cost(DEFAULT_COST);
 8144   size(4);
 8145   format %{ "CDGBR   $dst,$src" %}
 8146   opcode(CDGBR_ZOPC);
 8147   ins_encode(z_rreform(dst, src));
 8148   ins_pipe(pipe_class_dummy);
 8149 %}
 8150 
 8151 instruct convL2I_reg(iRegI dst, iRegL src) %{
 8152   match(Set dst (ConvL2I src));
 8153   // TODO: s390 port size(VARIABLE_SIZE);
 8154   format %{ "LR      $dst,$src\t # long->int (if needed)" %}
 8155   ins_encode %{ __ lr_if_needed($dst$$Register, $src$$Register); %}
 8156   ins_pipe(pipe_class_dummy);
 8157 %}
 8158 
 8159 // Register Shift Right Immediate
 8160 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt, flagsReg cr) %{
 8161   match(Set dst (ConvL2I (RShiftL src cnt)));
 8162   effect(KILL cr);
 8163   size(6);
 8164   format %{ "SRAG    $dst,$src,$cnt" %}
 8165   opcode(SRAG_ZOPC);
 8166   ins_encode(z_rsyform_const(dst, src, cnt));
 8167   ins_pipe(pipe_class_dummy);
 8168 %}
 8169 
 8170 //----------TRAP based zero checks and range checks----------------------------
 8171 
 8172 // SIGTRAP based implicit range checks in compiled code.
 8173 // A range check in the ideal world has one of the following shapes:
 8174 //   - (If le (CmpU length index)), (IfTrue  throw exception)
 8175 //   - (If lt (CmpU index length)), (IfFalse throw exception)
 8176 //
 8177 // Match range check 'If le (CmpU length index)'
 8178 instruct rangeCheck_iReg_uimmI16(cmpOpT cmp, iRegI length, uimmI16 index, label labl) %{
 8179   match(If cmp (CmpU length index));
 8180   effect(USE labl);
 8181   predicate(TrapBasedRangeChecks &&
 8182             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le &&
 8183             PROB_UNLIKELY(_leaf->as_If ()->_prob) >= PROB_ALWAYS &&
 8184             Matcher::branches_to_uncommon_trap(_leaf));
 8185   ins_cost(1);
 8186   // TODO: s390 port size(FIXED_SIZE);
 8187 
 8188   ins_is_TrapBasedCheckNode(true);
 8189 
 8190   format %{ "RangeCheck len=$length cmp=$cmp idx=$index => trap $labl" %}
 8191   ins_encode %{ __ z_clfit($length$$Register, $index$$constant, $cmp$$cmpcode); %}
 8192   ins_pipe(pipe_class_trap);
 8193 %}
 8194 
 8195 // Match range check 'If lt (CmpU index length)'
 8196 instruct rangeCheck_iReg_iReg(cmpOpT cmp, iRegI index, iRegI length, label labl, flagsReg cr) %{
 8197   match(If cmp (CmpU index length));
 8198   effect(USE labl, KILL cr);
 8199   predicate(TrapBasedRangeChecks &&
 8200             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
 8201             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
 8202             Matcher::branches_to_uncommon_trap(_leaf));
 8203   ins_cost(1);
 8204   // TODO: s390 port size(FIXED_SIZE);
 8205 
 8206   ins_is_TrapBasedCheckNode(true);
 8207 
 8208   format %{ "RangeCheck idx=$index cmp=$cmp len=$length => trap $labl" %}
 8209   ins_encode %{ __ z_clrt($index$$Register, $length$$Register, $cmp$$cmpcode); %}
 8210   ins_pipe(pipe_class_trap);
 8211 %}
 8212 
 8213 // Match range check 'If lt (CmpU index length)'
 8214 instruct rangeCheck_uimmI16_iReg(cmpOpT cmp, iRegI index, uimmI16 length, label labl) %{
 8215   match(If cmp (CmpU index length));
 8216   effect(USE labl);
 8217   predicate(TrapBasedRangeChecks &&
 8218             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt &&
 8219             _leaf->as_If ()->_prob >= PROB_ALWAYS &&
 8220             Matcher::branches_to_uncommon_trap(_leaf));
 8221   ins_cost(1);
 8222   // TODO: s390 port size(FIXED_SIZE);
 8223 
 8224   ins_is_TrapBasedCheckNode(true);
 8225 
 8226   format %{ "RangeCheck idx=$index cmp=$cmp len= $length => trap $labl" %}
 8227   ins_encode %{ __ z_clfit($index$$Register, $length$$constant, $cmp$$cmpcode); %}
 8228   ins_pipe(pipe_class_trap);
 8229 %}
 8230 
 8231 // Implicit zero checks (more implicit null checks).
 8232 instruct zeroCheckP_iReg_imm0(cmpOpT cmp, iRegP_N2P value, immP0 zero, label labl) %{
 8233   match(If cmp (CmpP value zero));
 8234   effect(USE labl);
 8235   predicate(TrapBasedNullChecks &&
 8236             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
 8237             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
 8238             Matcher::branches_to_uncommon_trap(_leaf));
 8239   size(6);
 8240 
 8241   ins_is_TrapBasedCheckNode(true);
 8242 
 8243   format %{ "ZeroCheckP value=$value cmp=$cmp zero=$zero => trap $labl" %}
 8244   ins_encode %{ __ z_cgit($value$$Register, 0, $cmp$$cmpcode); %}
 8245   ins_pipe(pipe_class_trap);
 8246 %}
 8247 
 8248 // Implicit zero checks (more implicit null checks).
 8249 instruct zeroCheckN_iReg_imm0(cmpOpT cmp, iRegN_P2N value, immN0 zero, label labl) %{
 8250   match(If cmp (CmpN value zero));
 8251   effect(USE labl);
 8252   predicate(TrapBasedNullChecks &&
 8253             _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne &&
 8254             _leaf->as_If ()->_prob >= PROB_LIKELY_MAG(4) &&
 8255             Matcher::branches_to_uncommon_trap(_leaf));
 8256   size(6);
 8257 
 8258   ins_is_TrapBasedCheckNode(true);
 8259 
 8260   format %{ "ZeroCheckN value=$value cmp=$cmp zero=$zero => trap $labl" %}
 8261   ins_encode %{ __ z_cit($value$$Register, 0, $cmp$$cmpcode); %}
 8262   ins_pipe(pipe_class_trap);
 8263 %}
 8264 
 8265 //----------Compare instructions-----------------------------------------------
 8266 
 8267 // INT signed
 8268 
 8269 // Compare Integers
 8270 instruct compI_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 8271   match(Set cr (CmpI op1 op2));
 8272   size(2);
 8273   format %{ "CR      $op1,$op2" %}
 8274   opcode(CR_ZOPC);
 8275   ins_encode(z_rrform(op1, op2));
 8276   ins_pipe(pipe_class_dummy);
 8277 %}
 8278 
 8279 instruct compI_reg_imm(flagsReg cr, iRegI op1, immI op2) %{
 8280   match(Set cr (CmpI op1 op2));
 8281   size(6);
 8282   format %{ "CFI     $op1,$op2" %}
 8283   opcode(CFI_ZOPC);
 8284   ins_encode(z_rilform_signed(op1, op2));
 8285   ins_pipe(pipe_class_dummy);
 8286 %}
 8287 
 8288 instruct compI_reg_imm16(flagsReg cr, iRegI op1, immI16 op2) %{
 8289   match(Set cr (CmpI op1 op2));
 8290   size(4);
 8291   format %{ "CHI     $op1,$op2" %}
 8292   opcode(CHI_ZOPC);
 8293   ins_encode(z_riform_signed(op1, op2));
 8294   ins_pipe(pipe_class_dummy);
 8295 %}
 8296 
 8297 instruct compI_reg_imm0(flagsReg cr, iRegI op1, immI_0 zero) %{
 8298   match(Set cr (CmpI op1 zero));
 8299   ins_cost(DEFAULT_COST_LOW);
 8300   size(2);
 8301   format %{ "LTR     $op1,$op1" %}
 8302   opcode(LTR_ZOPC);
 8303   ins_encode(z_rrform(op1, op1));
 8304   ins_pipe(pipe_class_dummy);
 8305 %}
 8306 
 8307 instruct compI_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
 8308   match(Set cr (CmpI op1 (LoadI op2)));
 8309   ins_cost(MEMORY_REF_COST);
 8310   // TODO: s390 port size(VARIABLE_SIZE);
 8311   format %{ "C(Y)    $op1, $op2\t # int" %}
 8312   opcode(CY_ZOPC, C_ZOPC);
 8313   ins_encode(z_form_rt_mem_opt(op1, op2));
 8314   ins_pipe(pipe_class_dummy);
 8315 %}
 8316 
 8317 // INT unsigned
 8318 
 8319 instruct compU_reg_reg(flagsReg cr, iRegI op1, iRegI op2) %{
 8320   match(Set cr (CmpU op1 op2));
 8321   size(2);
 8322   format %{ "CLR     $op1,$op2\t # unsigned" %}
 8323   opcode(CLR_ZOPC);
 8324   ins_encode(z_rrform(op1, op2));
 8325   ins_pipe(pipe_class_dummy);
 8326 %}
 8327 
 8328 instruct compU_reg_uimm(flagsReg cr, iRegI op1, uimmI op2) %{
 8329   match(Set cr (CmpU op1 op2));
 8330   size(6);
 8331   format %{ "CLFI    $op1,$op2\t # unsigned" %}
 8332   opcode(CLFI_ZOPC);
 8333   ins_encode(z_rilform_unsigned(op1, op2));
 8334   ins_pipe(pipe_class_dummy);
 8335 %}
 8336 
 8337 instruct compU_reg_mem(flagsReg cr, iRegI op1, memory op2)%{
 8338   match(Set cr (CmpU op1 (LoadI op2)));
 8339   ins_cost(MEMORY_REF_COST);
 8340   // TODO: s390 port size(VARIABLE_SIZE);
 8341   format %{ "CL(Y)   $op1, $op2\t # unsigned" %}
 8342   opcode(CLY_ZOPC, CL_ZOPC);
 8343   ins_encode(z_form_rt_mem_opt(op1, op2));
 8344   ins_pipe(pipe_class_dummy);
 8345 %}
 8346 
 8347 // LONG signed
 8348 
 8349 instruct compL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 8350   match(Set cr (CmpL op1 op2));
 8351   size(4);
 8352   format %{ "CGR     $op1,$op2\t # long" %}
 8353   opcode(CGR_ZOPC);
 8354   ins_encode(z_rreform(op1, op2));
 8355   ins_pipe(pipe_class_dummy);
 8356 %}
 8357 
 8358 instruct compL_reg_regI(flagsReg cr, iRegL op1, iRegI op2) %{
 8359   match(Set cr (CmpL op1 (ConvI2L op2)));
 8360   size(4);
 8361   format %{ "CGFR    $op1,$op2\t # long/int" %}
 8362   opcode(CGFR_ZOPC);
 8363   ins_encode(z_rreform(op1, op2));
 8364   ins_pipe(pipe_class_dummy);
 8365 %}
 8366 
 8367 instruct compL_reg_imm32(flagsReg cr, iRegL op1, immL32 con) %{
 8368   match(Set cr (CmpL op1 con));
 8369   size(6);
 8370   format %{ "CGFI    $op1,$con" %}
 8371   opcode(CGFI_ZOPC);
 8372   ins_encode(z_rilform_signed(op1, con));
 8373   ins_pipe(pipe_class_dummy);
 8374 %}
 8375 
 8376 instruct compL_reg_imm16(flagsReg cr, iRegL op1, immL16 con) %{
 8377   match(Set cr (CmpL op1 con));
 8378   size(4);
 8379   format %{ "CGHI    $op1,$con" %}
 8380   opcode(CGHI_ZOPC);
 8381   ins_encode(z_riform_signed(op1, con));
 8382   ins_pipe(pipe_class_dummy);
 8383 %}
 8384 
 8385 instruct compL_reg_imm0(flagsReg cr, iRegL op1, immL_0 con) %{
 8386   match(Set cr (CmpL op1 con));
 8387   ins_cost(DEFAULT_COST_LOW);
 8388   size(4);
 8389   format %{ "LTGR    $op1,$op1" %}
 8390   opcode(LTGR_ZOPC);
 8391   ins_encode(z_rreform(op1, op1));
 8392   ins_pipe(pipe_class_dummy);
 8393 %}
 8394 
 8395 instruct compL_conv_reg_imm0(flagsReg cr, iRegI op1, immL_0 con) %{
 8396   match(Set cr (CmpL (ConvI2L op1) con));
 8397   ins_cost(DEFAULT_COST_LOW);
 8398   size(4);
 8399   format %{ "LTGFR    $op1,$op1" %}
 8400   opcode(LTGFR_ZOPC);
 8401   ins_encode(z_rreform(op1, op1));
 8402   ins_pipe(pipe_class_dummy);
 8403 %}
 8404 
 8405 instruct compL_reg_mem(iRegL dst, memory src, flagsReg cr)%{
 8406   match(Set cr (CmpL dst (LoadL src)));
 8407   ins_cost(MEMORY_REF_COST);
 8408   size(Z_DISP3_SIZE);
 8409   format %{ "CG      $dst, $src\t # long" %}
 8410   opcode(CG_ZOPC, CG_ZOPC);
 8411   ins_encode(z_form_rt_mem_opt(dst, src));
 8412   ins_pipe(pipe_class_dummy);
 8413 %}
 8414 
 8415 instruct compL_reg_memI(iRegL dst, memory src, flagsReg cr)%{
 8416   match(Set cr (CmpL dst (ConvI2L (LoadI src))));
 8417   ins_cost(MEMORY_REF_COST);
 8418   size(Z_DISP3_SIZE);
 8419   format %{ "CGF     $dst, $src\t # long/int" %}
 8420   opcode(CGF_ZOPC, CGF_ZOPC);
 8421   ins_encode(z_form_rt_mem_opt(dst, src));
 8422   ins_pipe(pipe_class_dummy);
 8423 %}
 8424 
 8425 //  LONG unsigned
 8426 // Added CmpUL for LoopPredicate.
 8427 instruct compUL_reg_reg(flagsReg cr, iRegL op1, iRegL op2) %{
 8428   match(Set cr (CmpUL op1 op2));
 8429   size(4);
 8430   format %{ "CLGR    $op1,$op2\t # long" %}
 8431   opcode(CLGR_ZOPC);
 8432   ins_encode(z_rreform(op1, op2));
 8433   ins_pipe(pipe_class_dummy);
 8434 %}
 8435 
 8436 instruct compUL_reg_imm32(flagsReg cr, iRegL op1, uimmL32 con) %{
 8437   match(Set cr (CmpUL op1 con));
 8438   size(6);
 8439   format %{ "CLGFI   $op1,$con" %}
 8440   opcode(CLGFI_ZOPC);
 8441   ins_encode(z_rilform_unsigned(op1, con));
 8442   ins_pipe(pipe_class_dummy);
 8443 %}
 8444 
 8445 //  PTR unsigned
 8446 
 8447 instruct compP_reg_reg(flagsReg cr, iRegP_N2P op1, iRegP_N2P op2) %{
 8448   match(Set cr (CmpP op1 op2));
 8449   size(4);
 8450   format %{ "CLGR    $op1,$op2\t # ptr" %}
 8451   opcode(CLGR_ZOPC);
 8452   ins_encode(z_rreform(op1, op2));
 8453   ins_pipe(pipe_class_dummy);
 8454 %}
 8455 
 8456 instruct compP_reg_imm0(flagsReg cr, iRegP_N2P op1, immP0 op2) %{
 8457   match(Set cr (CmpP op1 op2));
 8458   ins_cost(DEFAULT_COST_LOW);
 8459   size(4);
 8460   format %{ "LTGR    $op1, $op1\t # ptr" %}
 8461   opcode(LTGR_ZOPC);
 8462   ins_encode(z_rreform(op1, op1));
 8463   ins_pipe(pipe_class_dummy);
 8464 %}
 8465 
 8466 // Don't use LTGFR which performs sign extend.
 8467 instruct compP_decode_reg_imm0(flagsReg cr, iRegN op1, immP0 op2) %{
 8468   match(Set cr (CmpP (DecodeN op1) op2));
 8469   predicate(CompressedOops::base() == NULL && CompressedOops::shift() == 0);
 8470   ins_cost(DEFAULT_COST_LOW);
 8471   size(2);
 8472   format %{ "LTR    $op1, $op1\t # ptr" %}
 8473   opcode(LTR_ZOPC);
 8474   ins_encode(z_rrform(op1, op1));
 8475   ins_pipe(pipe_class_dummy);
 8476 %}
 8477 
 8478 instruct compP_reg_mem(iRegP dst, memory src, flagsReg cr)%{
 8479   match(Set cr (CmpP dst (LoadP src)));
 8480   ins_cost(MEMORY_REF_COST);
 8481   size(Z_DISP3_SIZE);
 8482   format %{ "CLG     $dst, $src\t # ptr" %}
 8483   opcode(CLG_ZOPC, CLG_ZOPC);
 8484   ins_encode(z_form_rt_mem_opt(dst, src));
 8485   ins_pipe(pipe_class_dummy);
 8486 %}
 8487 
 8488 //----------Max and Min--------------------------------------------------------
 8489 
 8490 // Max Register with Register
 8491 instruct z196_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8492   match(Set dst (MinI src1 src2));
 8493   effect(KILL cr);
 8494   predicate(VM_Version::has_LoadStoreConditional());
 8495   ins_cost(3 * DEFAULT_COST);
 8496   // TODO: s390 port size(VARIABLE_SIZE);
 8497   format %{ "MinI $dst $src1,$src2\t MinI (z196 only)" %}
 8498   ins_encode %{
 8499     Register Rdst = $dst$$Register;
 8500     Register Rsrc1 = $src1$$Register;
 8501     Register Rsrc2 = $src2$$Register;
 8502 
 8503     if (Rsrc1 == Rsrc2) {
 8504       if (Rdst != Rsrc1) {
 8505         __ z_lgfr(Rdst, Rsrc1);
 8506       }
 8507     } else if (Rdst == Rsrc1) {   // Rdst preset with src1.
 8508       __ z_cr(Rsrc1, Rsrc2);      // Move src2 only if src1 is NotLow.
 8509       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
 8510     } else if (Rdst == Rsrc2) {   // Rdst preset with src2.
 8511       __ z_cr(Rsrc2, Rsrc1);      // Move src1 only if src2 is NotLow.
 8512       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotLow);
 8513     } else {
 8514       // Rdst is disjoint from operands, move in either case.
 8515       __ z_cr(Rsrc1, Rsrc2);
 8516       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotLow);
 8517       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8518     }
 8519   %}
 8520   ins_pipe(pipe_class_dummy);
 8521 %}
 8522 
 8523 // Min Register with Register.
 8524 instruct z10_minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8525   match(Set dst (MinI src1 src2));
 8526   effect(KILL cr);
 8527   predicate(VM_Version::has_CompareBranch());
 8528   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8529   // TODO: s390 port size(VARIABLE_SIZE);
 8530   format %{ "MinI $dst $src1,$src2\t MinI (z10 only)" %}
 8531   ins_encode %{
 8532     Register Rdst = $dst$$Register;
 8533     Register Rsrc1 = $src1$$Register;
 8534     Register Rsrc2 = $src2$$Register;
 8535     Label done;
 8536 
 8537     if (Rsrc1 == Rsrc2) {
 8538       if (Rdst != Rsrc1) {
 8539         __ z_lgfr(Rdst, Rsrc1);
 8540       }
 8541     } else if (Rdst == Rsrc1) {
 8542       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
 8543       __ z_lgfr(Rdst, Rsrc2);
 8544     } else if (Rdst == Rsrc2) {
 8545       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondLow, done);
 8546       __ z_lgfr(Rdst, Rsrc1);
 8547     } else {
 8548       __ z_lgfr(Rdst, Rsrc1);
 8549       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondLow, done);
 8550       __ z_lgfr(Rdst, Rsrc2);
 8551     }
 8552     __ bind(done);
 8553   %}
 8554   ins_pipe(pipe_class_dummy);
 8555 %}
 8556 
 8557 instruct minI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8558   match(Set dst (MinI src1 src2));
 8559   effect(KILL cr);
 8560   predicate(!VM_Version::has_CompareBranch());
 8561   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
 8562   // TODO: s390 port size(VARIABLE_SIZE);
 8563   format %{ "MinI $dst $src1,$src2\t MinI" %}
 8564   ins_encode %{
 8565     Register Rdst = $dst$$Register;
 8566     Register Rsrc1 = $src1$$Register;
 8567     Register Rsrc2 = $src2$$Register;
 8568     Label done;
 8569 
 8570     if (Rsrc1 == Rsrc2) {
 8571       if (Rdst != Rsrc1) {
 8572         __ z_lgfr(Rdst, Rsrc1);
 8573       }
 8574     } else if (Rdst == Rsrc1) {
 8575       __ z_cr(Rsrc1, Rsrc2);
 8576       __ z_brl(done);
 8577       __ z_lgfr(Rdst, Rsrc2);
 8578     } else if (Rdst == Rsrc2) {
 8579       __ z_cr(Rsrc2, Rsrc1);
 8580       __ z_brl(done);
 8581       __ z_lgfr(Rdst, Rsrc1);
 8582     } else {
 8583       __ z_lgfr(Rdst, Rsrc1);
 8584       __ z_cr(Rsrc1, Rsrc2);
 8585       __ z_brl(done);
 8586       __ z_lgfr(Rdst, Rsrc2);
 8587     }
 8588     __ bind(done);
 8589   %}
 8590   ins_pipe(pipe_class_dummy);
 8591 %}
 8592 
 8593 instruct z196_minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8594   match(Set dst (MinI src1 src2));
 8595   effect(KILL cr);
 8596   predicate(VM_Version::has_LoadStoreConditional());
 8597   ins_cost(3 * DEFAULT_COST);
 8598   // TODO: s390 port size(VARIABLE_SIZE);
 8599   format %{ "MinI $dst $src1,$src2\t MinI const32 (z196 only)" %}
 8600   ins_encode %{
 8601     Register Rdst = $dst$$Register;
 8602     Register Rsrc1 = $src1$$Register;
 8603     int      Isrc2 = $src2$$constant;
 8604 
 8605     if (Rdst == Rsrc1) {
 8606       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8607       __ z_cfi(Rsrc1, Isrc2);
 8608       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
 8609     } else {
 8610       __ load_const_optimized(Rdst, Isrc2);
 8611       __ z_cfi(Rsrc1, Isrc2);
 8612       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8613     }
 8614   %}
 8615   ins_pipe(pipe_class_dummy);
 8616 %}
 8617 
 8618 instruct minI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8619   match(Set dst (MinI src1 src2));
 8620   effect(KILL cr);
 8621   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8622   // TODO: s390 port size(VARIABLE_SIZE);
 8623   format %{ "MinI $dst $src1,$src2\t MinI const32" %}
 8624   ins_encode %{
 8625     Label done;
 8626     if ($dst$$Register != $src1$$Register) {
 8627       __ z_lgfr($dst$$Register, $src1$$Register);
 8628     }
 8629     __ z_cfi($src1$$Register, $src2$$constant);
 8630     __ z_brl(done);
 8631     __ z_lgfi($dst$$Register, $src2$$constant);
 8632     __ bind(done);
 8633   %}
 8634   ins_pipe(pipe_class_dummy);
 8635 %}
 8636 
 8637 instruct z196_minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8638   match(Set dst (MinI src1 src2));
 8639   effect(KILL cr);
 8640   predicate(VM_Version::has_LoadStoreConditional());
 8641   ins_cost(3 * DEFAULT_COST);
 8642   // TODO: s390 port size(VARIABLE_SIZE);
 8643   format %{ "MinI $dst $src1,$src2\t MinI const16 (z196 only)" %}
 8644   ins_encode %{
 8645     Register Rdst = $dst$$Register;
 8646     Register Rsrc1 = $src1$$Register;
 8647     int      Isrc2 = $src2$$constant;
 8648 
 8649     if (Rdst == Rsrc1) {
 8650       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8651       __ z_chi(Rsrc1, Isrc2);
 8652       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotLow);
 8653     } else {
 8654       __ load_const_optimized(Rdst, Isrc2);
 8655       __ z_chi(Rsrc1, Isrc2);
 8656       __ z_locr(Rdst, Rsrc1, Assembler::bcondLow);
 8657     }
 8658   %}
 8659   ins_pipe(pipe_class_dummy);
 8660 %}
 8661 
 8662 instruct minI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8663   match(Set dst (MinI src1 src2));
 8664   effect(KILL cr);
 8665   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8666   // TODO: s390 port size(VARIABLE_SIZE);
 8667   format %{ "MinI $dst $src1,$src2\t MinI const16" %}
 8668   ins_encode %{
 8669     Label done;
 8670     if ($dst$$Register != $src1$$Register) {
 8671       __ z_lgfr($dst$$Register, $src1$$Register);
 8672     }
 8673     __ z_chi($src1$$Register, $src2$$constant);
 8674     __ z_brl(done);
 8675     __ z_lghi($dst$$Register, $src2$$constant);
 8676     __ bind(done);
 8677   %}
 8678   ins_pipe(pipe_class_dummy);
 8679 %}
 8680 
 8681 instruct z10_minI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
 8682   match(Set dst (MinI src1 src2));
 8683   effect(KILL cr);
 8684   predicate(VM_Version::has_CompareBranch());
 8685   ins_cost(DEFAULT_COST + BRANCH_COST);
 8686   // TODO: s390 port size(VARIABLE_SIZE);
 8687   format %{ "MinI $dst $src1,$src2\t MinI const8 (z10 only)" %}
 8688   ins_encode %{
 8689     Label done;
 8690     if ($dst$$Register != $src1$$Register) {
 8691       __ z_lgfr($dst$$Register, $src1$$Register);
 8692     }
 8693     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondLow, done);
 8694     __ z_lghi($dst$$Register, $src2$$constant);
 8695     __ bind(done);
 8696   %}
 8697   ins_pipe(pipe_class_dummy);
 8698 %}
 8699 
 8700 // Max Register with Register
 8701 instruct z196_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8702   match(Set dst (MaxI src1 src2));
 8703   effect(KILL cr);
 8704   predicate(VM_Version::has_LoadStoreConditional());
 8705   ins_cost(3 * DEFAULT_COST);
 8706   // TODO: s390 port size(VARIABLE_SIZE);
 8707   format %{ "MaxI $dst $src1,$src2\t MaxI (z196 only)" %}
 8708   ins_encode %{
 8709     Register Rdst = $dst$$Register;
 8710     Register Rsrc1 = $src1$$Register;
 8711     Register Rsrc2 = $src2$$Register;
 8712 
 8713     if (Rsrc1 == Rsrc2) {
 8714       if (Rdst != Rsrc1) {
 8715         __ z_lgfr(Rdst, Rsrc1);
 8716       }
 8717     } else if (Rdst == Rsrc1) { // Rdst preset with src1.
 8718       __ z_cr(Rsrc1, Rsrc2);    // Move src2 only if src1 is NotHigh.
 8719       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
 8720     } else if (Rdst == Rsrc2) { // Rdst preset with src2.
 8721       __ z_cr(Rsrc2, Rsrc1);    // Move src1 only if src2 is NotHigh.
 8722       __ z_locr(Rdst, Rsrc1, Assembler::bcondNotHigh);
 8723     } else {                    // Rdst is disjoint from operands, move in either case.
 8724       __ z_cr(Rsrc1, Rsrc2);
 8725       __ z_locr(Rdst, Rsrc2, Assembler::bcondNotHigh);
 8726       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8727     }
 8728   %}
 8729   ins_pipe(pipe_class_dummy);
 8730 %}
 8731 
 8732 // Max Register with Register
 8733 instruct z10_maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8734   match(Set dst (MaxI src1 src2));
 8735   effect(KILL cr);
 8736   predicate(VM_Version::has_CompareBranch());
 8737   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8738   // TODO: s390 port size(VARIABLE_SIZE);
 8739   format %{ "MaxI $dst $src1,$src2\t MaxI (z10 only)" %}
 8740   ins_encode %{
 8741     Register Rdst = $dst$$Register;
 8742     Register Rsrc1 = $src1$$Register;
 8743     Register Rsrc2 = $src2$$Register;
 8744     Label done;
 8745 
 8746     if (Rsrc1 == Rsrc2) {
 8747       if (Rdst != Rsrc1) {
 8748         __ z_lgfr(Rdst, Rsrc1);
 8749       }
 8750     } else if (Rdst == Rsrc1) {
 8751       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
 8752       __ z_lgfr(Rdst, Rsrc2);
 8753     } else if (Rdst == Rsrc2) {
 8754       __ z_crj(Rsrc2, Rsrc1, Assembler::bcondHigh, done);
 8755       __ z_lgfr(Rdst, Rsrc1);
 8756     } else {
 8757       __ z_lgfr(Rdst, Rsrc1);
 8758       __ z_crj(Rsrc1, Rsrc2, Assembler::bcondHigh, done);
 8759       __ z_lgfr(Rdst, Rsrc2);
 8760     }
 8761     __ bind(done);
 8762   %}
 8763   ins_pipe(pipe_class_dummy);
 8764 %}
 8765 
 8766 instruct maxI_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
 8767   match(Set dst (MaxI src1 src2));
 8768   effect(KILL cr);
 8769   predicate(!VM_Version::has_CompareBranch());
 8770   ins_cost(3 * DEFAULT_COST + BRANCH_COST);
 8771   // TODO: s390 port size(VARIABLE_SIZE);
 8772   format %{ "MaxI $dst $src1,$src2\t MaxI" %}
 8773   ins_encode %{
 8774     Register Rdst = $dst$$Register;
 8775     Register Rsrc1 = $src1$$Register;
 8776     Register Rsrc2 = $src2$$Register;
 8777     Label done;
 8778 
 8779     if (Rsrc1 == Rsrc2) {
 8780       if (Rdst != Rsrc1) {
 8781         __ z_lgfr(Rdst, Rsrc1);
 8782       }
 8783     } else if (Rdst == Rsrc1) {
 8784       __ z_cr(Rsrc1, Rsrc2);
 8785       __ z_brh(done);
 8786       __ z_lgfr(Rdst, Rsrc2);
 8787     } else if (Rdst == Rsrc2) {
 8788       __ z_cr(Rsrc2, Rsrc1);
 8789       __ z_brh(done);
 8790       __ z_lgfr(Rdst, Rsrc1);
 8791     } else {
 8792       __ z_lgfr(Rdst, Rsrc1);
 8793       __ z_cr(Rsrc1, Rsrc2);
 8794       __ z_brh(done);
 8795       __ z_lgfr(Rdst, Rsrc2);
 8796     }
 8797 
 8798     __ bind(done);
 8799   %}
 8800 
 8801   ins_pipe(pipe_class_dummy);
 8802 %}
 8803 
 8804 instruct z196_maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8805   match(Set dst (MaxI src1 src2));
 8806   effect(KILL cr);
 8807   predicate(VM_Version::has_LoadStoreConditional());
 8808   ins_cost(3 * DEFAULT_COST);
 8809   // TODO: s390 port size(VARIABLE_SIZE);
 8810   format %{ "MaxI $dst $src1,$src2\t MaxI const32 (z196 only)" %}
 8811   ins_encode %{
 8812     Register Rdst = $dst$$Register;
 8813     Register Rsrc1 = $src1$$Register;
 8814     int      Isrc2 = $src2$$constant;
 8815 
 8816     if (Rdst == Rsrc1) {
 8817       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8818       __ z_cfi(Rsrc1, Isrc2);
 8819       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
 8820     } else {
 8821       __ load_const_optimized(Rdst, Isrc2);
 8822       __ z_cfi(Rsrc1, Isrc2);
 8823       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8824     }
 8825   %}
 8826   ins_pipe(pipe_class_dummy);
 8827 %}
 8828 
 8829 instruct maxI_reg_imm32(iRegI dst, iRegI src1, immI src2, flagsReg cr) %{
 8830   match(Set dst (MaxI src1 src2));
 8831   effect(KILL cr);
 8832   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8833   // TODO: s390 port size(VARIABLE_SIZE);
 8834   format %{ "MaxI $dst $src1,$src2\t MaxI const32" %}
 8835   ins_encode %{
 8836     Label done;
 8837     if ($dst$$Register != $src1$$Register) {
 8838       __ z_lgfr($dst$$Register, $src1$$Register);
 8839     }
 8840     __ z_cfi($src1$$Register, $src2$$constant);
 8841     __ z_brh(done);
 8842     __ z_lgfi($dst$$Register, $src2$$constant);
 8843     __ bind(done);
 8844   %}
 8845   ins_pipe(pipe_class_dummy);
 8846 %}
 8847 
 8848 instruct z196_maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8849   match(Set dst (MaxI src1 src2));
 8850   effect(KILL cr);
 8851   predicate(VM_Version::has_LoadStoreConditional());
 8852   ins_cost(3 * DEFAULT_COST);
 8853   // TODO: s390 port size(VARIABLE_SIZE);
 8854   format %{ "MaxI $dst $src1,$src2\t MaxI const16 (z196 only)" %}
 8855   ins_encode %{
 8856     Register Rdst = $dst$$Register;
 8857     Register Rsrc1 = $src1$$Register;
 8858     int      Isrc2 = $src2$$constant;
 8859     if (Rdst == Rsrc1) {
 8860       __ load_const_optimized(Z_R0_scratch, Isrc2);
 8861       __ z_chi(Rsrc1, Isrc2);
 8862       __ z_locr(Rdst, Z_R0_scratch, Assembler::bcondNotHigh);
 8863     } else {
 8864       __ load_const_optimized(Rdst, Isrc2);
 8865       __ z_chi(Rsrc1, Isrc2);
 8866       __ z_locr(Rdst, Rsrc1, Assembler::bcondHigh);
 8867     }
 8868   %}
 8869   ins_pipe(pipe_class_dummy);
 8870 %}
 8871 
 8872 instruct maxI_reg_imm16(iRegI dst, iRegI src1, immI16 src2, flagsReg cr) %{
 8873   match(Set dst (MaxI src1 src2));
 8874   effect(KILL cr);
 8875   ins_cost(2 * DEFAULT_COST + BRANCH_COST);
 8876   // TODO: s390 port size(VARIABLE_SIZE);
 8877   format %{ "MaxI $dst $src1,$src2\t MaxI const16" %}
 8878   ins_encode %{
 8879     Label done;
 8880     if ($dst$$Register != $src1$$Register) {
 8881       __ z_lgfr($dst$$Register, $src1$$Register);
 8882     }
 8883     __ z_chi($src1$$Register, $src2$$constant);
 8884     __ z_brh(done);
 8885     __ z_lghi($dst$$Register, $src2$$constant);
 8886     __ bind(done);
 8887   %}
 8888   ins_pipe(pipe_class_dummy);
 8889 %}
 8890 
 8891 instruct z10_maxI_reg_imm8(iRegI dst, iRegI src1, immI8 src2, flagsReg cr) %{
 8892   match(Set dst (MaxI src1 src2));
 8893   effect(KILL cr);
 8894   predicate(VM_Version::has_CompareBranch());
 8895   ins_cost(DEFAULT_COST + BRANCH_COST);
 8896   // TODO: s390 port size(VARIABLE_SIZE);
 8897   format %{ "MaxI $dst $src1,$src2\t MaxI const8" %}
 8898   ins_encode %{
 8899     Label done;
 8900     if ($dst$$Register != $src1$$Register) {
 8901       __ z_lgfr($dst$$Register, $src1$$Register);
 8902     }
 8903     __ z_cij($src1$$Register, $src2$$constant, Assembler::bcondHigh, done);
 8904     __ z_lghi($dst$$Register, $src2$$constant);
 8905     __ bind(done);
 8906   %}
 8907   ins_pipe(pipe_class_dummy);
 8908 %}
 8909 
 8910 //----------Abs---------------------------------------------------------------
 8911 
 8912 instruct absI_reg(iRegI dst, iRegI src, flagsReg cr) %{
 8913   match(Set dst (AbsI src));
 8914   effect(KILL cr);
 8915   ins_cost(DEFAULT_COST_LOW);
 8916   // TODO: s390 port size(FIXED_SIZE);
 8917   format %{ "LPR     $dst, $src" %}
 8918   opcode(LPR_ZOPC);
 8919   ins_encode(z_rrform(dst, src));
 8920   ins_pipe(pipe_class_dummy);
 8921 %}
 8922 
 8923 instruct absL_reg(iRegL dst, iRegL src, flagsReg cr) %{
 8924   match(Set dst (AbsL src));
 8925   effect(KILL cr);
 8926   ins_cost(DEFAULT_COST_LOW);
 8927   // TODO: s390 port size(FIXED_SIZE);
 8928   format %{ "LPGR     $dst, $src" %}
 8929   opcode(LPGR_ZOPC);
 8930   ins_encode(z_rreform(dst, src));
 8931   ins_pipe(pipe_class_dummy);
 8932 %}
 8933 
 8934 instruct negabsI_reg(iRegI dst, iRegI src, immI_0 zero, flagsReg cr) %{
 8935   match(Set dst (SubI zero (AbsI src)));
 8936   effect(KILL cr);
 8937   ins_cost(DEFAULT_COST_LOW);
 8938   // TODO: s390 port size(FIXED_SIZE);
 8939   format %{ "LNR     $dst, $src" %}
 8940   opcode(LNR_ZOPC);
 8941   ins_encode(z_rrform(dst, src));
 8942   ins_pipe(pipe_class_dummy);
 8943 %}
 8944 
 8945 //----------Float Compares----------------------------------------------------
 8946 
 8947 // Compare floating, generate condition code.
 8948 instruct cmpF_cc(flagsReg cr, regF src1, regF src2) %{
 8949   match(Set cr (CmpF src1 src2));
 8950   ins_cost(ALU_REG_COST);
 8951   size(4);
 8952   format %{ "FCMPcc   $src1,$src2\t # float" %}
 8953   ins_encode %{ __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister); %}
 8954   ins_pipe(pipe_class_dummy);
 8955 %}
 8956 
 8957 instruct cmpD_cc(flagsReg cr, regD src1, regD src2) %{
 8958   match(Set cr (CmpD src1 src2));
 8959   ins_cost(ALU_REG_COST);
 8960   size(4);
 8961   format %{ "FCMPcc   $src1,$src2 \t # double" %}
 8962   ins_encode %{ __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister); %}
 8963   ins_pipe(pipe_class_dummy);
 8964 %}
 8965 
 8966 instruct cmpF_cc_mem(flagsReg cr, regF src1, memoryRX src2) %{
 8967   match(Set cr (CmpF src1 (LoadF src2)));
 8968   ins_cost(ALU_MEMORY_COST);
 8969   size(6);
 8970   format %{ "FCMPcc_mem $src1,$src2\t # floatMemory" %}
 8971   opcode(CEB_ZOPC);
 8972   ins_encode(z_form_rt_memFP(src1, src2));
 8973   ins_pipe(pipe_class_dummy);
 8974 %}
 8975 
 8976 instruct cmpD_cc_mem(flagsReg cr, regD src1, memoryRX src2) %{
 8977   match(Set cr (CmpD src1 (LoadD src2)));
 8978   ins_cost(ALU_MEMORY_COST);
 8979   size(6);
 8980   format %{ "DCMPcc_mem $src1,$src2\t # doubleMemory" %}
 8981   opcode(CDB_ZOPC);
 8982   ins_encode(z_form_rt_memFP(src1, src2));
 8983   ins_pipe(pipe_class_dummy);
 8984 %}
 8985 
 8986 // Compare floating, generate condition code
 8987 instruct cmpF0_cc(flagsReg cr, regF src1, immFpm0 src2) %{
 8988   match(Set cr (CmpF src1 src2));
 8989   ins_cost(DEFAULT_COST);
 8990   size(4);
 8991   format %{ "LTEBR    $src1,$src1\t # float" %}
 8992   opcode(LTEBR_ZOPC);
 8993   ins_encode(z_rreform(src1, src1));
 8994   ins_pipe(pipe_class_dummy);
 8995 %}
 8996 
 8997 instruct cmpD0_cc(flagsReg cr, regD src1, immDpm0 src2) %{
 8998   match(Set cr (CmpD src1 src2));
 8999   ins_cost(DEFAULT_COST);
 9000   size(4);
 9001   format %{ "LTDBR    $src1,$src1 \t # double" %}
 9002   opcode(LTDBR_ZOPC);
 9003   ins_encode(z_rreform(src1, src1));
 9004   ins_pipe(pipe_class_dummy);
 9005 %}
 9006 
 9007 // Compare floating, generate -1,0,1
 9008 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsReg cr) %{
 9009   match(Set dst (CmpF3 src1 src2));
 9010   effect(KILL cr);
 9011   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9012   size(24);
 9013   format %{ "CmpF3    $dst,$src1,$src2" %}
 9014   ins_encode %{
 9015     // compare registers
 9016     __ z_cebr($src1$$FloatRegister, $src2$$FloatRegister);
 9017     // Convert condition code into -1,0,1, where
 9018     // -1 means unordered or less
 9019     //  0 means equal
 9020     //  1 means greater.
 9021     if (VM_Version::has_LoadStoreConditional()) {
 9022       Register one       = Z_R0_scratch;
 9023       Register minus_one = Z_R1_scratch;
 9024       __ z_lghi(minus_one, -1);
 9025       __ z_lghi(one, 1);
 9026       __ z_lghi( $dst$$Register, 0);
 9027       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9028       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
 9029     } else {
 9030       Label done;
 9031       __ clear_reg($dst$$Register, true, false);
 9032       __ z_bre(done);
 9033       __ z_lhi($dst$$Register, 1);
 9034       __ z_brh(done);
 9035       __ z_lhi($dst$$Register, -1);
 9036       __ bind(done);
 9037     }
 9038   %}
 9039   ins_pipe(pipe_class_dummy);
 9040 %}
 9041 
 9042 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsReg cr) %{
 9043   match(Set dst (CmpD3 src1 src2));
 9044   effect(KILL cr);
 9045   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9046   size(24);
 9047   format %{ "CmpD3    $dst,$src1,$src2" %}
 9048   ins_encode %{
 9049     // compare registers
 9050     __ z_cdbr($src1$$FloatRegister, $src2$$FloatRegister);
 9051     // Convert condition code into -1,0,1, where
 9052     // -1 means unordered or less
 9053     //  0 means equal
 9054     //  1 means greater.
 9055     if (VM_Version::has_LoadStoreConditional()) {
 9056       Register one       = Z_R0_scratch;
 9057       Register minus_one = Z_R1_scratch;
 9058       __ z_lghi(minus_one, -1);
 9059       __ z_lghi(one, 1);
 9060       __ z_lghi( $dst$$Register, 0);
 9061       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9062       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLowOrNotOrdered);
 9063     } else {
 9064       Label done;
 9065       // indicate unused result
 9066       (void) __ clear_reg($dst$$Register, true, false);
 9067       __ z_bre(done);
 9068       __ z_lhi($dst$$Register, 1);
 9069       __ z_brh(done);
 9070       __ z_lhi($dst$$Register, -1);
 9071       __ bind(done);
 9072     }
 9073   %}
 9074   ins_pipe(pipe_class_dummy);
 9075 %}
 9076 
 9077 //----------Branches---------------------------------------------------------
 9078 // Jump
 9079 
 9080 // Direct Branch.
 9081 instruct branch(label labl) %{
 9082   match(Goto);
 9083   effect(USE labl);
 9084   ins_cost(BRANCH_COST);
 9085   size(4);
 9086   format %{ "BRU     $labl" %}
 9087   ins_encode(z_enc_bru(labl));
 9088   ins_pipe(pipe_class_dummy);
 9089   // If set to 1 this indicates that the current instruction is a
 9090   // short variant of a long branch. This avoids using this
 9091   // instruction in first-pass matching. It will then only be used in
 9092   // the `Shorten_branches' pass.
 9093   ins_short_branch(1);
 9094 %}
 9095 
 9096 // Direct Branch.
 9097 instruct branchFar(label labl) %{
 9098   match(Goto);
 9099   effect(USE labl);
 9100   ins_cost(BRANCH_COST);
 9101   size(6);
 9102   format %{ "BRUL   $labl" %}
 9103   ins_encode(z_enc_brul(labl));
 9104   ins_pipe(pipe_class_dummy);
 9105   // This is not a short variant of a branch, but the long variant.
 9106   ins_short_branch(0);
 9107 %}
 9108 
 9109 // Conditional Near Branch
 9110 instruct branchCon(cmpOp cmp, flagsReg cr, label lbl) %{
 9111   // Same match rule as `branchConFar'.
 9112   match(If cmp cr);
 9113   effect(USE lbl);
 9114   ins_cost(BRANCH_COST);
 9115   size(4);
 9116   format %{ "branch_con_short,$cmp   $lbl" %}
 9117   ins_encode(z_enc_branch_con_short(cmp, lbl));
 9118   ins_pipe(pipe_class_dummy);
 9119   // If set to 1 this indicates that the current instruction is a
 9120   // short variant of a long branch. This avoids using this
 9121   // instruction in first-pass matching. It will then only be used in
 9122   // the `Shorten_branches' pass.
 9123   ins_short_branch(1);
 9124 %}
 9125 
 9126 // This is for cases when the z/Architecture conditional branch instruction
 9127 // does not reach far enough. So we emit a far branch here, which is
 9128 // more expensive.
 9129 //
 9130 // Conditional Far Branch
 9131 instruct branchConFar(cmpOp cmp, flagsReg cr, label lbl) %{
 9132   // Same match rule as `branchCon'.
 9133   match(If cmp cr);
 9134   effect(USE cr, USE lbl);
 9135   // Make more expensive to prefer compare_and_branch over separate instructions.
 9136   ins_cost(2 * BRANCH_COST);
 9137   size(6);
 9138   format %{ "branch_con_far,$cmp   $lbl" %}
 9139   ins_encode(z_enc_branch_con_far(cmp, lbl));
 9140   ins_pipe(pipe_class_dummy);
 9141   // This is not a short variant of a branch, but the long variant..
 9142   ins_short_branch(0);
 9143 %}
 9144 
 9145 instruct branchLoopEnd(cmpOp cmp, flagsReg cr, label labl) %{
 9146   match(CountedLoopEnd cmp cr);
 9147   effect(USE labl);
 9148   ins_cost(BRANCH_COST);
 9149   size(4);
 9150   format %{ "branch_con_short,$cmp   $labl\t # counted loop end" %}
 9151   ins_encode(z_enc_branch_con_short(cmp, labl));
 9152   ins_pipe(pipe_class_dummy);
 9153   // If set to 1 this indicates that the current instruction is a
 9154   // short variant of a long branch. This avoids using this
 9155   // instruction in first-pass matching. It will then only be used in
 9156   // the `Shorten_branches' pass.
 9157   ins_short_branch(1);
 9158 %}
 9159 
 9160 instruct branchLoopEndFar(cmpOp cmp, flagsReg cr, label labl) %{
 9161   match(CountedLoopEnd cmp cr);
 9162   effect(USE labl);
 9163   ins_cost(BRANCH_COST);
 9164   size(6);
 9165   format %{ "branch_con_far,$cmp   $labl\t # counted loop end" %}
 9166   ins_encode(z_enc_branch_con_far(cmp, labl));
 9167   ins_pipe(pipe_class_dummy);
 9168   // This is not a short variant of a branch, but the long variant.
 9169   ins_short_branch(0);
 9170 %}
 9171 
 9172 //----------Compare and Branch (short distance)------------------------------
 9173 
 9174 // INT REG operands for loop counter processing.
 9175 instruct testAndBranchLoopEnd_Reg(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9176   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9177   effect(USE labl, KILL cr);
 9178   predicate(VM_Version::has_CompareBranch());
 9179   ins_cost(BRANCH_COST);
 9180   // TODO: s390 port size(FIXED_SIZE);
 9181   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
 9182   opcode(CRJ_ZOPC);
 9183   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9184   ins_pipe(pipe_class_dummy);
 9185   ins_short_branch(1);
 9186 %}
 9187 
 9188 // INT REG operands.
 9189 instruct cmpb_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9190   match(If boolnode (CmpI src1 src2));
 9191   effect(USE labl, KILL cr);
 9192   predicate(VM_Version::has_CompareBranch());
 9193   ins_cost(BRANCH_COST);
 9194   // TODO: s390 port size(FIXED_SIZE);
 9195   format %{ "CRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9196   opcode(CRJ_ZOPC);
 9197   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9198   ins_pipe(pipe_class_dummy);
 9199   ins_short_branch(1);
 9200 %}
 9201 
 9202 // Unsigned INT REG operands
 9203 instruct cmpbU_RegI(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9204   match(If boolnode (CmpU src1 src2));
 9205   effect(USE labl, KILL cr);
 9206   predicate(VM_Version::has_CompareBranch());
 9207   ins_cost(BRANCH_COST);
 9208   // TODO: s390 port size(FIXED_SIZE);
 9209   format %{ "CLRJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9210   opcode(CLRJ_ZOPC);
 9211   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9212   ins_pipe(pipe_class_dummy);
 9213   ins_short_branch(1);
 9214 %}
 9215 
 9216 // LONG REG operands
 9217 instruct cmpb_RegL(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
 9218   match(If boolnode (CmpL src1 src2));
 9219   effect(USE labl, KILL cr);
 9220   predicate(VM_Version::has_CompareBranch());
 9221   ins_cost(BRANCH_COST);
 9222   // TODO: s390 port size(FIXED_SIZE);
 9223   format %{ "CGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9224   opcode(CGRJ_ZOPC);
 9225   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9226   ins_pipe(pipe_class_dummy);
 9227   ins_short_branch(1);
 9228 %}
 9229 
 9230 //  PTR REG operands
 9231 
 9232 // Separate rules for regular and narrow oops.  ADLC can't recognize
 9233 // rules with polymorphic operands to be sisters -> shorten_branches
 9234 // will not shorten.
 9235 
 9236 instruct cmpb_RegPP(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
 9237   match(If boolnode (CmpP src1 src2));
 9238   effect(USE labl, KILL cr);
 9239   predicate(VM_Version::has_CompareBranch());
 9240   ins_cost(BRANCH_COST);
 9241   // TODO: s390 port size(FIXED_SIZE);
 9242   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9243   opcode(CLGRJ_ZOPC);
 9244   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9245   ins_pipe(pipe_class_dummy);
 9246   ins_short_branch(1);
 9247 %}
 9248 
 9249 instruct cmpb_RegNN(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
 9250   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9251   effect(USE labl, KILL cr);
 9252   predicate(VM_Version::has_CompareBranch());
 9253   ins_cost(BRANCH_COST);
 9254   // TODO: s390 port size(FIXED_SIZE);
 9255   format %{ "CLGRJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9256   opcode(CLGRJ_ZOPC);
 9257   ins_encode(z_enc_cmpb_regreg(src1, src2, labl, boolnode));
 9258   ins_pipe(pipe_class_dummy);
 9259   ins_short_branch(1);
 9260 %}
 9261 
 9262 // INT REG/IMM operands for loop counter processing
 9263 instruct testAndBranchLoopEnd_Imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9264   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9265   effect(USE labl, KILL cr);
 9266   predicate(VM_Version::has_CompareBranch());
 9267   ins_cost(BRANCH_COST);
 9268   // TODO: s390 port size(FIXED_SIZE);
 9269   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end SHORT" %}
 9270   opcode(CIJ_ZOPC);
 9271   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9272   ins_pipe(pipe_class_dummy);
 9273   ins_short_branch(1);
 9274 %}
 9275 
 9276 // INT REG/IMM operands
 9277 instruct cmpb_RegI_imm(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9278   match(If boolnode (CmpI src1 src2));
 9279   effect(USE labl, KILL cr);
 9280   predicate(VM_Version::has_CompareBranch());
 9281   ins_cost(BRANCH_COST);
 9282   // TODO: s390 port size(FIXED_SIZE);
 9283   format %{ "CIJ,$boolnode  $src1,$src2,$labl\t # SHORT" %}
 9284   opcode(CIJ_ZOPC);
 9285   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9286   ins_pipe(pipe_class_dummy);
 9287   ins_short_branch(1);
 9288 %}
 9289 
 9290 // INT REG/IMM operands
 9291 instruct cmpbU_RegI_imm(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
 9292   match(If boolnode (CmpU src1 src2));
 9293   effect(USE labl, KILL cr);
 9294   predicate(VM_Version::has_CompareBranch());
 9295   ins_cost(BRANCH_COST);
 9296   // TODO: s390 port size(FIXED_SIZE);
 9297   format %{ "CLIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9298   opcode(CLIJ_ZOPC);
 9299   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9300   ins_pipe(pipe_class_dummy);
 9301   ins_short_branch(1);
 9302 %}
 9303 
 9304 // LONG REG/IMM operands
 9305 instruct cmpb_RegL_imm(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
 9306   match(If boolnode (CmpL src1 src2));
 9307   effect(USE labl, KILL cr);
 9308   predicate(VM_Version::has_CompareBranch());
 9309   ins_cost(BRANCH_COST);
 9310   // TODO: s390 port size(FIXED_SIZE);
 9311   format %{ "CGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9312   opcode(CGIJ_ZOPC);
 9313   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9314   ins_pipe(pipe_class_dummy);
 9315   ins_short_branch(1);
 9316 %}
 9317 
 9318 // PTR REG-imm operands
 9319 
 9320 // Separate rules for regular and narrow oops. ADLC can't recognize
 9321 // rules with polymorphic operands to be sisters -> shorten_branches
 9322 // will not shorten.
 9323 
 9324 instruct cmpb_RegP_immP(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
 9325   match(If boolnode (CmpP src1 src2));
 9326   effect(USE labl, KILL cr);
 9327   predicate(VM_Version::has_CompareBranch());
 9328   ins_cost(BRANCH_COST);
 9329   // TODO: s390 port size(FIXED_SIZE);
 9330   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9331   opcode(CLGIJ_ZOPC);
 9332   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9333   ins_pipe(pipe_class_dummy);
 9334   ins_short_branch(1);
 9335 %}
 9336 
 9337 // Compare against zero only, do not mix N and P oops (encode/decode required).
 9338 instruct cmpb_RegN_immP0(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
 9339   match(If boolnode (CmpP (DecodeN src1) src2));
 9340   effect(USE labl, KILL cr);
 9341   predicate(VM_Version::has_CompareBranch());
 9342   ins_cost(BRANCH_COST);
 9343   // TODO: s390 port size(FIXED_SIZE);
 9344   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9345   opcode(CLGIJ_ZOPC);
 9346   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9347   ins_pipe(pipe_class_dummy);
 9348   ins_short_branch(1);
 9349 %}
 9350 
 9351 instruct cmpb_RegN_imm(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
 9352   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9353   effect(USE labl, KILL cr);
 9354   predicate(VM_Version::has_CompareBranch());
 9355   ins_cost(BRANCH_COST);
 9356   // TODO: s390 port size(FIXED_SIZE);
 9357   format %{ "CLGIJ,$boolnode $src1,$src2,$labl\t # SHORT" %}
 9358   opcode(CLGIJ_ZOPC);
 9359   ins_encode(z_enc_cmpb_regimm(src1, src2, labl, boolnode));
 9360   ins_pipe(pipe_class_dummy);
 9361   ins_short_branch(1);
 9362 %}
 9363 
 9364 
 9365 //----------Compare and Branch (far distance)------------------------------
 9366 
 9367 // INT REG operands for loop counter processing
 9368 instruct testAndBranchLoopEnd_RegFar(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9369   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9370   effect(USE labl, KILL cr);
 9371   predicate(VM_Version::has_CompareBranch());
 9372   ins_cost(BRANCH_COST+DEFAULT_COST);
 9373   // TODO: s390 port size(FIXED_SIZE);
 9374   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
 9375   opcode(CR_ZOPC, BRCL_ZOPC);
 9376   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9377   ins_pipe(pipe_class_dummy);
 9378   ins_short_branch(0);
 9379 %}
 9380 
 9381 // INT REG operands
 9382 instruct cmpb_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9383   match(If boolnode (CmpI src1 src2));
 9384   effect(USE labl, KILL cr);
 9385   predicate(VM_Version::has_CompareBranch());
 9386   ins_cost(BRANCH_COST+DEFAULT_COST);
 9387   // TODO: s390 port size(FIXED_SIZE);
 9388   format %{ "CRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9389   opcode(CR_ZOPC, BRCL_ZOPC);
 9390   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9391   ins_pipe(pipe_class_dummy);
 9392   ins_short_branch(0);
 9393 %}
 9394 
 9395 // INT REG operands
 9396 instruct cmpbU_RegI_Far(cmpOpT boolnode, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
 9397   match(If boolnode (CmpU src1 src2));
 9398   effect(USE labl, KILL cr);
 9399   predicate(VM_Version::has_CompareBranch());
 9400   ins_cost(BRANCH_COST+DEFAULT_COST);
 9401   // TODO: s390 port size(FIXED_SIZE);
 9402   format %{ "CLRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9403   opcode(CLR_ZOPC, BRCL_ZOPC);
 9404   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9405   ins_pipe(pipe_class_dummy);
 9406   ins_short_branch(0);
 9407 %}
 9408 
 9409 // LONG REG operands
 9410 instruct cmpb_RegL_Far(cmpOpT boolnode, iRegL src1, iRegL src2, label labl, flagsReg cr) %{
 9411   match(If boolnode (CmpL src1 src2));
 9412   effect(USE labl, KILL cr);
 9413   predicate(VM_Version::has_CompareBranch());
 9414   ins_cost(BRANCH_COST+DEFAULT_COST);
 9415   // TODO: s390 port size(FIXED_SIZE);
 9416   format %{ "CGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9417   opcode(CGR_ZOPC, BRCL_ZOPC);
 9418   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9419   ins_pipe(pipe_class_dummy);
 9420   ins_short_branch(0);
 9421 %}
 9422 
 9423 // PTR REG operands
 9424 
 9425 // Separate rules for regular and narrow oops. ADLC can't recognize
 9426 // rules with polymorphic operands to be sisters -> shorten_branches
 9427 // will not shorten.
 9428 
 9429 instruct cmpb_RegPP_Far(cmpOpT boolnode, iRegP src1, iRegP src2, label labl, flagsReg cr) %{
 9430   match(If boolnode (CmpP src1 src2));
 9431   effect(USE labl, KILL cr);
 9432   predicate(VM_Version::has_CompareBranch());
 9433   ins_cost(BRANCH_COST+DEFAULT_COST);
 9434   // TODO: s390 port size(FIXED_SIZE);
 9435   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9436   opcode(CLGR_ZOPC, BRCL_ZOPC);
 9437   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9438   ins_pipe(pipe_class_dummy);
 9439   ins_short_branch(0);
 9440 %}
 9441 
 9442 instruct cmpb_RegNN_Far(cmpOpT boolnode, iRegN src1, iRegN src2, label labl, flagsReg cr) %{
 9443   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9444   effect(USE labl, KILL cr);
 9445   predicate(VM_Version::has_CompareBranch());
 9446   ins_cost(BRANCH_COST+DEFAULT_COST);
 9447   // TODO: s390 port size(FIXED_SIZE);
 9448   format %{ "CLGRJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9449   opcode(CLGR_ZOPC, BRCL_ZOPC);
 9450   ins_encode(z_enc_cmpb_regregFar(src1, src2, labl, boolnode));
 9451   ins_pipe(pipe_class_dummy);
 9452   ins_short_branch(0);
 9453 %}
 9454 
 9455 // INT REG/IMM operands for loop counter processing
 9456 instruct testAndBranchLoopEnd_ImmFar(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9457   match(CountedLoopEnd boolnode (CmpI src1 src2));
 9458   effect(USE labl, KILL cr);
 9459   predicate(VM_Version::has_CompareBranch());
 9460   ins_cost(BRANCH_COST+DEFAULT_COST);
 9461   // TODO: s390 port size(FIXED_SIZE);
 9462   format %{ "test_and_branch_loop_end,$boolnode  $src1,$src2,$labl\t # counted loop end FAR" %}
 9463   opcode(CHI_ZOPC, BRCL_ZOPC);
 9464   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9465   ins_pipe(pipe_class_dummy);
 9466   ins_short_branch(0);
 9467 %}
 9468 
 9469 // INT REG/IMM operands
 9470 instruct cmpb_RegI_imm_Far(cmpOpT boolnode, iRegI src1, immI8 src2, label labl, flagsReg cr) %{
 9471   match(If boolnode (CmpI src1 src2));
 9472   effect(USE labl, KILL cr);
 9473   predicate(VM_Version::has_CompareBranch());
 9474   ins_cost(BRANCH_COST+DEFAULT_COST);
 9475   // TODO: s390 port size(FIXED_SIZE);
 9476   format %{ "CIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9477   opcode(CHI_ZOPC, BRCL_ZOPC);
 9478   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9479   ins_pipe(pipe_class_dummy);
 9480   ins_short_branch(0);
 9481 %}
 9482 
 9483 // INT REG/IMM operands
 9484 instruct cmpbU_RegI_imm_Far(cmpOpT boolnode, iRegI src1, uimmI8 src2, label labl, flagsReg cr) %{
 9485   match(If boolnode (CmpU src1 src2));
 9486   effect(USE labl, KILL cr);
 9487   predicate(VM_Version::has_CompareBranch());
 9488   ins_cost(BRANCH_COST+DEFAULT_COST);
 9489   // TODO: s390 port size(FIXED_SIZE);
 9490   format %{ "CLIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9491   opcode(CLFI_ZOPC, BRCL_ZOPC);
 9492   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9493   ins_pipe(pipe_class_dummy);
 9494   ins_short_branch(0);
 9495 %}
 9496 
 9497 // LONG REG/IMM operands
 9498 instruct cmpb_RegL_imm_Far(cmpOpT boolnode, iRegL src1, immL8 src2, label labl, flagsReg cr) %{
 9499   match(If boolnode (CmpL src1 src2));
 9500   effect(USE labl, KILL cr);
 9501   predicate(VM_Version::has_CompareBranch());
 9502   ins_cost(BRANCH_COST+DEFAULT_COST);
 9503   // TODO: s390 port size(FIXED_SIZE);
 9504   format %{ "CGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9505   opcode(CGHI_ZOPC, BRCL_ZOPC);
 9506   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9507   ins_pipe(pipe_class_dummy);
 9508   ins_short_branch(0);
 9509 %}
 9510 
 9511 // PTR REG-imm operands
 9512 
 9513 // Separate rules for regular and narrow oops. ADLC can't recognize
 9514 // rules with polymorphic operands to be sisters -> shorten_branches
 9515 // will not shorten.
 9516 
 9517 instruct cmpb_RegP_immP_Far(cmpOpT boolnode, iRegP src1, immP8 src2, label labl, flagsReg cr) %{
 9518   match(If boolnode (CmpP src1 src2));
 9519   effect(USE labl, KILL cr);
 9520   predicate(VM_Version::has_CompareBranch());
 9521   ins_cost(BRANCH_COST+DEFAULT_COST);
 9522   // TODO: s390 port size(FIXED_SIZE);
 9523   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9524   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9525   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9526   ins_pipe(pipe_class_dummy);
 9527   ins_short_branch(0);
 9528 %}
 9529 
 9530 // Compare against zero only, do not mix N and P oops (encode/decode required).
 9531 instruct cmpb_RegN_immP0_Far(cmpOpT boolnode, iRegN src1, immP0 src2, label labl, flagsReg cr) %{
 9532   match(If boolnode (CmpP (DecodeN src1) src2));
 9533   effect(USE labl, KILL cr);
 9534   predicate(VM_Version::has_CompareBranch());
 9535   ins_cost(BRANCH_COST+DEFAULT_COST);
 9536   // TODO: s390 port size(FIXED_SIZE);
 9537   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9538   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9539   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9540   ins_pipe(pipe_class_dummy);
 9541   ins_short_branch(0);
 9542 %}
 9543 
 9544 instruct cmpb_RegN_immN_Far(cmpOpT boolnode, iRegN src1, immN8 src2, label labl, flagsReg cr) %{
 9545   match(If boolnode (CmpP (DecodeN src1) (DecodeN src2)));
 9546   effect(USE labl, KILL cr);
 9547   predicate(VM_Version::has_CompareBranch());
 9548   ins_cost(BRANCH_COST+DEFAULT_COST);
 9549   // TODO: s390 port size(FIXED_SIZE);
 9550   format %{ "CLGIJ,$boolnode   $src1,$src2,$labl\t # FAR(substituted)" %}
 9551   opcode(CLGFI_ZOPC, BRCL_ZOPC);
 9552   ins_encode(z_enc_cmpb_regimmFar(src1, src2, labl, boolnode));
 9553   ins_pipe(pipe_class_dummy);
 9554   ins_short_branch(0);
 9555 %}
 9556 
 9557 // ============================================================================
 9558 // Long Compare
 9559 
 9560 // Due to a shortcoming in the ADLC, it mixes up expressions like:
 9561 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
 9562 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
 9563 // are collapsed internally in the ADLC's dfa-gen code. The match for
 9564 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
 9565 // foo match ends up with the wrong leaf. One fix is to not match both
 9566 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
 9567 // both forms beat the trinary form of long-compare and both are very useful
 9568 // on platforms which have few registers.
 9569 
 9570 // Manifest a CmpL3 result in an integer register. Very painful.
 9571 // This is the test to avoid.
 9572 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr) %{
 9573   match(Set dst (CmpL3 src1 src2));
 9574   effect(KILL cr);
 9575   ins_cost(DEFAULT_COST * 5 + BRANCH_COST);
 9576   size(24);
 9577   format %{ "CmpL3 $dst,$src1,$src2" %}
 9578   ins_encode %{
 9579     Label done;
 9580     // compare registers
 9581     __ z_cgr($src1$$Register, $src2$$Register);
 9582     // Convert condition code into -1,0,1, where
 9583     // -1 means less
 9584     //  0 means equal
 9585     //  1 means greater.
 9586     if (VM_Version::has_LoadStoreConditional()) {
 9587       Register one       = Z_R0_scratch;
 9588       Register minus_one = Z_R1_scratch;
 9589       __ z_lghi(minus_one, -1);
 9590       __ z_lghi(one, 1);
 9591       __ z_lghi( $dst$$Register, 0);
 9592       __ z_locgr($dst$$Register, one,       Assembler::bcondHigh);
 9593       __ z_locgr($dst$$Register, minus_one, Assembler::bcondLow);
 9594     } else {
 9595       __ clear_reg($dst$$Register, true, false);
 9596       __ z_bre(done);
 9597       __ z_lhi($dst$$Register, 1);
 9598       __ z_brh(done);
 9599       __ z_lhi($dst$$Register, -1);
 9600     }
 9601     __ bind(done);
 9602   %}
 9603   ins_pipe(pipe_class_dummy);
 9604 %}
 9605 
 9606 // ============================================================================
 9607 // Safepoint Instruction
 9608 
 9609 instruct safePoint() %{
 9610   match(SafePoint);
 9611   predicate(false);
 9612   // TODO: s390 port size(FIXED_SIZE);
 9613   format %{ "UNIMPLEMENTED Safepoint_ " %}
 9614   ins_encode(enc_unimplemented());
 9615   ins_pipe(pipe_class_dummy);
 9616 %}
 9617 
 9618 instruct safePoint_poll(iRegP poll, flagsReg cr) %{
 9619   match(SafePoint poll);
 9620   effect(USE poll, KILL cr); // R0 is killed, too.
 9621   // TODO: s390 port size(FIXED_SIZE);
 9622   format %{ "TM      #0[,$poll],#111\t # Safepoint: poll for GC" %}
 9623   ins_encode %{
 9624     // Mark the code position where the load from the safepoint
 9625     // polling page was emitted as relocInfo::poll_type.
 9626     __ relocate(relocInfo::poll_type);
 9627     __ load_from_polling_page($poll$$Register);
 9628   %}
 9629   ins_pipe(pipe_class_dummy);
 9630 %}
 9631 
 9632 // ============================================================================
 9633 
 9634 // Call Instructions
 9635 
 9636 // Call Java Static Instruction
 9637 instruct CallStaticJavaDirect_dynTOC(method meth) %{
 9638   match(CallStaticJava);
 9639   effect(USE meth);
 9640   ins_cost(CALL_COST);
 9641   // TODO: s390 port size(VARIABLE_SIZE);
 9642   format %{ "CALL,static dynTOC $meth; ==> " %}
 9643   ins_encode( z_enc_java_static_call(meth) );
 9644   ins_pipe(pipe_class_dummy);
 9645   ins_alignment(2);
 9646 %}
 9647 
 9648 // Call Java Dynamic Instruction
 9649 instruct CallDynamicJavaDirect_dynTOC(method meth) %{
 9650   match(CallDynamicJava);
 9651   effect(USE meth);
 9652   ins_cost(CALL_COST);
 9653   // TODO: s390 port size(VARIABLE_SIZE);
 9654   format %{ "CALL,dynamic dynTOC $meth; ==> " %}
 9655   ins_encode(z_enc_java_dynamic_call(meth));
 9656   ins_pipe(pipe_class_dummy);
 9657   ins_alignment(2);
 9658 %}
 9659 
 9660 // Call Runtime Instruction
 9661 instruct CallRuntimeDirect(method meth) %{
 9662   match(CallRuntime);
 9663   effect(USE meth);
 9664   ins_cost(CALL_COST);
 9665   // TODO: s390 port size(VARIABLE_SIZE);
 9666   ins_num_consts(1);
 9667   ins_alignment(2);
 9668   format %{ "CALL,runtime" %}
 9669   ins_encode( z_enc_java_to_runtime_call(meth) );
 9670   ins_pipe(pipe_class_dummy);
 9671 %}
 9672 
 9673 // Call runtime without safepoint - same as CallRuntime
 9674 instruct CallLeafDirect(method meth) %{
 9675   match(CallLeaf);
 9676   effect(USE meth);
 9677   ins_cost(CALL_COST);
 9678   // TODO: s390 port size(VARIABLE_SIZE);
 9679   ins_num_consts(1);
 9680   ins_alignment(2);
 9681   format %{ "CALL,runtime leaf $meth" %}
 9682   ins_encode( z_enc_java_to_runtime_call(meth) );
 9683   ins_pipe(pipe_class_dummy);
 9684 %}
 9685 
 9686 // Call runtime without safepoint - same as CallLeaf
 9687 instruct CallLeafNoFPDirect(method meth) %{
 9688   match(CallLeafNoFP);
 9689   effect(USE meth);
 9690   ins_cost(CALL_COST);
 9691   // TODO: s390 port size(VARIABLE_SIZE);
 9692   ins_num_consts(1);
 9693   format %{ "CALL,runtime leaf nofp $meth" %}
 9694   ins_encode( z_enc_java_to_runtime_call(meth) );
 9695   ins_pipe(pipe_class_dummy);
 9696   ins_alignment(2);
 9697 %}
 9698 
 9699 // Tail Call; Jump from runtime stub to Java code.
 9700 // Also known as an 'interprocedural jump'.
 9701 // Target of jump will eventually return to caller.
 9702 // TailJump below removes the return address.
 9703 instruct TailCalljmpInd(iRegP jump_target, inline_cache_regP method_ptr) %{
 9704   match(TailCall jump_target method_ptr);
 9705   ins_cost(CALL_COST);
 9706   size(2);
 9707   format %{ "Jmp     $jump_target\t # $method_ptr holds method" %}
 9708   ins_encode %{ __ z_br($jump_target$$Register); %}
 9709   ins_pipe(pipe_class_dummy);
 9710 %}
 9711 
 9712 // Return Instruction
 9713 instruct Ret() %{
 9714   match(Return);
 9715   size(2);
 9716   format %{ "BR(Z_R14) // branch to link register" %}
 9717   ins_encode %{ __ z_br(Z_R14); %}
 9718   ins_pipe(pipe_class_dummy);
 9719 %}
 9720 
 9721 // Tail Jump; remove the return address; jump to target.
 9722 // TailCall above leaves the return address around.
 9723 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
 9724 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
 9725 // "restore" before this instruction (in Epilogue), we need to materialize it
 9726 // in %i0.
 9727 instruct tailjmpInd(iRegP jump_target, rarg1RegP ex_oop) %{
 9728   match(TailJump jump_target ex_oop);
 9729   ins_cost(CALL_COST);
 9730   size(8);
 9731   format %{ "TailJump $jump_target" %}
 9732   ins_encode %{
 9733     __ z_lg(Z_ARG2/* issuing pc */, _z_abi(return_pc), Z_SP);
 9734     __ z_br($jump_target$$Register);
 9735   %}
 9736   ins_pipe(pipe_class_dummy);
 9737 %}
 9738 
 9739 // Create exception oop: created by stack-crawling runtime code.
 9740 // Created exception is now available to this handler, and is setup
 9741 // just prior to jumping to this handler. No code emitted.
 9742 instruct CreateException(rarg1RegP ex_oop) %{
 9743   match(Set ex_oop (CreateEx));
 9744   ins_cost(0);
 9745   size(0);
 9746   format %{ "# exception oop; no code emitted" %}
 9747   ins_encode(/*empty*/);
 9748   ins_pipe(pipe_class_dummy);
 9749 %}
 9750 
 9751 // Rethrow exception: The exception oop will come in the first
 9752 // argument position. Then JUMP (not call) to the rethrow stub code.
 9753 instruct RethrowException() %{
 9754   match(Rethrow);
 9755   ins_cost(CALL_COST);
 9756   // TODO: s390 port size(VARIABLE_SIZE);
 9757   format %{ "Jmp    rethrow_stub" %}
 9758   ins_encode %{
 9759     cbuf.set_insts_mark();
 9760     __ load_const_optimized(Z_R1_scratch, (address)OptoRuntime::rethrow_stub());
 9761     __ z_br(Z_R1_scratch);
 9762   %}
 9763   ins_pipe(pipe_class_dummy);
 9764 %}
 9765 
 9766 // Die now.
 9767 instruct ShouldNotReachHere() %{
 9768   match(Halt);
 9769   ins_cost(CALL_COST);
 9770   format %{ "ILLTRAP; ShouldNotReachHere" %}
 9771   ins_encode %{
 9772     if (is_reachable()) {
 9773       __ stop(_halt_reason);
 9774     }
 9775   %}
 9776   ins_pipe(pipe_class_dummy);
 9777 %}
 9778 
 9779 // ============================================================================
 9780 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
 9781 // array for an instance of the superklass. Set a hidden internal cache on a
 9782 // hit (cache is checked with exposed code in gen_subtype_check()). Return
 9783 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
 9784 instruct partialSubtypeCheck(rarg1RegP index, rarg2RegP sub, rarg3RegP super, flagsReg pcc,
 9785                              rarg4RegP scratch1, rarg5RegP scratch2) %{
 9786   match(Set index (PartialSubtypeCheck sub super));
 9787   effect(KILL pcc, KILL scratch1, KILL scratch2);
 9788   ins_cost(10 * DEFAULT_COST);
 9789   // TODO: s390 port size(FIXED_SIZE);
 9790   format %{ "  CALL   PartialSubtypeCheck\n" %}
 9791   ins_encode %{
 9792     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
 9793     __ load_const_optimized(Z_ARG4, stub_address);
 9794     __ z_basr(Z_R14, Z_ARG4);
 9795   %}
 9796   ins_pipe(pipe_class_dummy);
 9797 %}
 9798 
 9799 instruct partialSubtypeCheck_vs_zero(flagsReg pcc, rarg2RegP sub, rarg3RegP super, immP0 zero,
 9800                                      rarg1RegP index, rarg4RegP scratch1, rarg5RegP scratch2) %{
 9801   match(Set pcc (CmpI (PartialSubtypeCheck sub super) zero));
 9802   effect(KILL scratch1, KILL scratch2, KILL index);
 9803   ins_cost(10 * DEFAULT_COST);
 9804   // TODO: s390 port size(FIXED_SIZE);
 9805   format %{ "CALL   PartialSubtypeCheck_vs_zero\n" %}
 9806   ins_encode %{
 9807     AddressLiteral stub_address(StubRoutines::zarch::partial_subtype_check());
 9808     __ load_const_optimized(Z_ARG4, stub_address);
 9809     __ z_basr(Z_R14, Z_ARG4);
 9810   %}
 9811   ins_pipe(pipe_class_dummy);
 9812 %}
 9813 
 9814 // ============================================================================
 9815 // inlined locking and unlocking
 9816 
 9817 instruct cmpFastLock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
 9818   match(Set pcc (FastLock oop box));
 9819   effect(TEMP tmp1, TEMP tmp2);
 9820   ins_cost(100);
 9821   // TODO: s390 port size(VARIABLE_SIZE); // Uses load_const_optimized.
 9822   format %{ "FASTLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
 9823   ins_encode %{ __ compiler_fast_lock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register); %}
 9824   ins_pipe(pipe_class_dummy);
 9825 %}
 9826 
 9827 instruct cmpFastUnlock(flagsReg pcc, iRegP_N2P oop, iRegP_N2P box, iRegP tmp1, iRegP tmp2) %{
 9828   match(Set pcc (FastUnlock oop box));
 9829   effect(TEMP tmp1, TEMP tmp2);
 9830   ins_cost(100);
 9831   // TODO: s390 port size(FIXED_SIZE);
 9832   format %{ "FASTUNLOCK  $oop, $box; KILL Z_ARG4, Z_ARG5" %}
 9833   ins_encode %{ __ compiler_fast_unlock_object($oop$$Register, $box$$Register, $tmp1$$Register, $tmp2$$Register); %}
 9834   ins_pipe(pipe_class_dummy);
 9835 %}
 9836 
 9837 instruct inlineCallClearArrayConst(SSlenDW cnt, iRegP_N2P base, Universe dummy, flagsReg cr) %{
 9838   match(Set dummy (ClearArray cnt base));
 9839   effect(KILL cr);
 9840   ins_cost(100);
 9841   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to varying #instructions.
 9842   format %{ "ClearArrayConst $cnt,$base" %}
 9843   ins_encode %{ __ Clear_Array_Const($cnt$$constant, $base$$Register); %}
 9844   ins_pipe(pipe_class_dummy);
 9845 %}
 9846 
 9847 instruct inlineCallClearArrayConstBig(immL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
 9848   match(Set dummy (ClearArray cnt base));
 9849   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
 9850   ins_cost(200);
 9851   // TODO: s390 port size(VARIABLE_SIZE);       // Variable in size due to optimized constant loader.
 9852   format %{ "ClearArrayConstBig $cnt,$base" %}
 9853   ins_encode %{ __ Clear_Array_Const_Big($cnt$$constant, $base$$Register, $tmpL$$Register); %}
 9854   ins_pipe(pipe_class_dummy);
 9855 %}
 9856 
 9857 instruct inlineCallClearArray(iRegL cnt, iRegP_N2P base, Universe dummy, allRoddRegL tmpL, flagsReg cr) %{
 9858   match(Set dummy (ClearArray cnt base));
 9859   effect(TEMP tmpL, KILL cr); // R0, R1 are killed, too.
 9860   ins_cost(300);
 9861   // TODO: s390 port size(FIXED_SIZE);  // z/Architecture: emitted code depends on PreferLAoverADD being on/off.
 9862   format %{ "ClearArrayVar $cnt,$base" %}
 9863   ins_encode %{ __ Clear_Array($cnt$$Register, $base$$Register, $tmpL$$Register); %}
 9864   ins_pipe(pipe_class_dummy);
 9865 %}
 9866 
 9867 // ============================================================================
 9868 // CompactStrings
 9869 
 9870 // String equals
 9871 instruct string_equalsL(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9872   match(Set result (StrEquals (Binary str1 str2) cnt));
 9873   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9874   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
 9875   ins_cost(300);
 9876   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
 9877   ins_encode %{
 9878     __ array_equals(false, $str1$$Register, $str2$$Register,
 9879                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
 9880                     $result$$Register, true /* byte */);
 9881   %}
 9882   ins_pipe(pipe_class_dummy);
 9883 %}
 9884 
 9885 instruct string_equalsU(iRegP str1, iRegP str2, iRegI cnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9886   match(Set result (StrEquals (Binary str1 str2) cnt));
 9887   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9888   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
 9889   ins_cost(300);
 9890   format %{ "String Equals char[] $str1,$str2,$cnt -> $result" %}
 9891   ins_encode %{
 9892     __ array_equals(false, $str1$$Register, $str2$$Register,
 9893                     $cnt$$Register, $oddReg$$Register, $evenReg$$Register,
 9894                     $result$$Register, false /* byte */);
 9895   %}
 9896   ins_pipe(pipe_class_dummy);
 9897 %}
 9898 
 9899 instruct string_equals_imm(iRegP str1, iRegP str2, uimmI8 cnt, iRegI result, flagsReg cr) %{
 9900   match(Set result (StrEquals (Binary str1 str2) cnt));
 9901   effect(KILL cr); // R0 is killed, too.
 9902   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL || ((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
 9903   ins_cost(100);
 9904   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result" %}
 9905   ins_encode %{
 9906     const int cnt_imm = $cnt$$constant;
 9907     if (cnt_imm) { __ z_clc(0, cnt_imm - 1, $str1$$Register, 0, $str2$$Register); }
 9908     __ z_lhi($result$$Register, 1);
 9909     if (cnt_imm) {
 9910       if (VM_Version::has_LoadStoreConditional()) {
 9911         __ z_lhi(Z_R0_scratch, 0);
 9912         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
 9913       } else {
 9914         Label Lskip;
 9915         __ z_bre(Lskip);
 9916         __ clear_reg($result$$Register);
 9917         __ bind(Lskip);
 9918       }
 9919     }
 9920   %}
 9921   ins_pipe(pipe_class_dummy);
 9922 %}
 9923 
 9924 instruct string_equalsC_imm(iRegP str1, iRegP str2, immI8 cnt, iRegI result, flagsReg cr) %{
 9925   match(Set result (StrEquals (Binary str1 str2) cnt));
 9926   effect(KILL cr); // R0 is killed, too.
 9927   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::none);
 9928   ins_cost(100);
 9929   format %{ "String Equals $str1,$str2,$cnt -> $result" %}
 9930   ins_encode %{
 9931     const int cnt_imm = $cnt$$constant; // positive immI8 (7 bits used)
 9932     if (cnt_imm) { __ z_clc(0, (cnt_imm << 1) - 1, $str1$$Register, 0, $str2$$Register); }
 9933     __ z_lhi($result$$Register, 1);
 9934     if (cnt_imm) {
 9935       if (VM_Version::has_LoadStoreConditional()) {
 9936         __ z_lhi(Z_R0_scratch, 0);
 9937         __ z_locr($result$$Register, Z_R0_scratch, Assembler::bcondNotEqual);
 9938       } else {
 9939         Label Lskip;
 9940         __ z_bre(Lskip);
 9941         __ clear_reg($result$$Register);
 9942         __ bind(Lskip);
 9943       }
 9944     }
 9945   %}
 9946   ins_pipe(pipe_class_dummy);
 9947 %}
 9948 
 9949 // Array equals
 9950 instruct array_equalsB(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9951   match(Set result (AryEq ary1 ary2));
 9952   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9953   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
 9954   ins_cost(300);
 9955   format %{ "Array Equals $ary1,$ary2 -> $result" %}
 9956   ins_encode %{
 9957     __ array_equals(true, $ary1$$Register, $ary2$$Register,
 9958                     noreg, $oddReg$$Register, $evenReg$$Register,
 9959                     $result$$Register, true /* byte */);
 9960   %}
 9961   ins_pipe(pipe_class_dummy);
 9962 %}
 9963 
 9964 instruct array_equalsC(iRegP ary1, iRegP ary2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9965   match(Set result (AryEq ary1 ary2));
 9966   effect(TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9967   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
 9968   ins_cost(300);
 9969   format %{ "Array Equals $ary1,$ary2 -> $result" %}
 9970   ins_encode %{
 9971     __ array_equals(true, $ary1$$Register, $ary2$$Register,
 9972                     noreg, $oddReg$$Register, $evenReg$$Register,
 9973                     $result$$Register, false /* byte */);
 9974   %}
 9975   ins_pipe(pipe_class_dummy);
 9976 %}
 9977 
 9978 // String CompareTo
 9979 instruct string_compareL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9980   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
 9981   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9982   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
 9983   ins_cost(300);
 9984   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
 9985   ins_encode %{
 9986     __ string_compare($str1$$Register, $str2$$Register,
 9987                       $cnt1$$Register, $cnt2$$Register,
 9988                       $oddReg$$Register, $evenReg$$Register,
 9989                       $result$$Register, StrIntrinsicNode::LL);
 9990   %}
 9991   ins_pipe(pipe_class_dummy);
 9992 %}
 9993 
 9994 instruct string_compareU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
 9995   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
 9996   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
 9997   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrCompNode*)n)->encoding() == StrIntrinsicNode::none);
 9998   ins_cost(300);
 9999   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10000   ins_encode %{
10001     __ string_compare($str1$$Register, $str2$$Register,
10002                       $cnt1$$Register, $cnt2$$Register,
10003                       $oddReg$$Register, $evenReg$$Register,
10004                       $result$$Register, StrIntrinsicNode::UU);
10005   %}
10006   ins_pipe(pipe_class_dummy);
10007 %}
10008 
10009 instruct string_compareLU(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10010   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10011   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10012   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10013   ins_cost(300);
10014   format %{ "String Compare byte[],char[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10015   ins_encode %{
10016     __ string_compare($str1$$Register, $str2$$Register,
10017                       $cnt1$$Register, $cnt2$$Register,
10018                       $oddReg$$Register, $evenReg$$Register,
10019                       $result$$Register, StrIntrinsicNode::LU);
10020   %}
10021   ins_pipe(pipe_class_dummy);
10022 %}
10023 
10024 instruct string_compareUL(iRegP str1, iRegP str2, rarg2RegI cnt1, rarg5RegI cnt2, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10025   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10026   effect(TEMP_DEF result, USE_KILL cnt1, USE_KILL cnt2, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10027   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10028   ins_cost(300);
10029   format %{ "String Compare char[],byte[] $str1,$cnt1,$str2,$cnt2 -> $result" %}
10030   ins_encode %{
10031     __ string_compare($str2$$Register, $str1$$Register,
10032                       $cnt2$$Register, $cnt1$$Register,
10033                       $oddReg$$Register, $evenReg$$Register,
10034                       $result$$Register, StrIntrinsicNode::UL);
10035   %}
10036   ins_pipe(pipe_class_dummy);
10037 %}
10038 
10039 // String IndexOfChar
10040 instruct indexOfChar_U(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10041   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10042   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10043   predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::U);
10044   ins_cost(200);
10045   format %{ "StringUTF16 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10046   ins_encode %{
10047     __ string_indexof_char($result$$Register,
10048                            $haystack$$Register, $haycnt$$Register,
10049                            $ch$$Register, 0 /* unused, ch is in register */,
10050                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10051   %}
10052   ins_pipe(pipe_class_dummy);
10053 %}
10054 
10055 instruct indexOfChar_L(iRegP haystack, iRegI haycnt, iRegI ch, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10056   match(Set result (StrIndexOfChar (Binary haystack haycnt) ch));
10057   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10058   predicate(((StrIndexOfCharNode*)n)->encoding() == StrIntrinsicNode::L);
10059   ins_cost(200);
10060   format %{ "StringLatin1 IndexOfChar [0..$haycnt]($haystack), $ch -> $result" %}
10061   ins_encode %{
10062     __ string_indexof_char($result$$Register,
10063                            $haystack$$Register, $haycnt$$Register,
10064                            $ch$$Register, 0 /* unused, ch is in register */,
10065                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10066   %}
10067   ins_pipe(pipe_class_dummy);
10068 %}
10069 
10070 instruct indexOf_imm1_U(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10071   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10072   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10073   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10074   ins_cost(200);
10075   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10076   ins_encode %{
10077     immPOper *needleOper = (immPOper *)$needle;
10078     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10079     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10080     jchar chr;
10081 #ifdef VM_LITTLE_ENDIAN
10082     Unimplemented();
10083 #else
10084     chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) |
10085            ((jchar)(unsigned char)needle_values->element_value(1).as_byte());
10086 #endif
10087     __ string_indexof_char($result$$Register,
10088                            $haystack$$Register, $haycnt$$Register,
10089                            noreg, chr,
10090                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10091   %}
10092   ins_pipe(pipe_class_dummy);
10093 %}
10094 
10095 instruct indexOf_imm1_L(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10096   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10097   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10098   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10099   ins_cost(200);
10100   format %{ "String IndexOf L [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10101   ins_encode %{
10102     immPOper *needleOper = (immPOper *)$needle;
10103     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10104     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10105     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10106     __ string_indexof_char($result$$Register,
10107                            $haystack$$Register, $haycnt$$Register,
10108                            noreg, chr,
10109                            $oddReg$$Register, $evenReg$$Register, true /*is_byte*/);
10110   %}
10111   ins_pipe(pipe_class_dummy);
10112 %}
10113 
10114 instruct indexOf_imm1_UL(iRegP haystack, iRegI haycnt, immP needle, immI_1 needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10115   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10116   effect(TEMP_DEF result, TEMP evenReg, TEMP oddReg, KILL cr); // R0, R1 are killed, too.
10117   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10118   ins_cost(200);
10119   format %{ "String IndexOf UL [0..$haycnt]($haystack), [0]($needle) -> $result" %}
10120   ins_encode %{
10121     immPOper *needleOper = (immPOper *)$needle;
10122     const TypeOopPtr *t = needleOper->type()->isa_oopptr();
10123     ciTypeArray* needle_values = t->const_oop()->as_type_array();  // Pointer to live char *
10124     jchar chr = (jchar)needle_values->element_value(0).as_byte();
10125     __ string_indexof_char($result$$Register,
10126                            $haystack$$Register, $haycnt$$Register,
10127                            noreg, chr,
10128                            $oddReg$$Register, $evenReg$$Register, false /*is_byte*/);
10129   %}
10130   ins_pipe(pipe_class_dummy);
10131 %}
10132 
10133 // String IndexOf
10134 instruct indexOf_imm_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10135   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10136   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10137   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10138   ins_cost(250);
10139   format %{ "String IndexOf U [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10140   ins_encode %{
10141     __ string_indexof($result$$Register,
10142                       $haystack$$Register, $haycnt$$Register,
10143                       $needle$$Register, noreg, $needlecntImm$$constant,
10144                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10145   %}
10146   ins_pipe(pipe_class_dummy);
10147 %}
10148 
10149 instruct indexOf_imm_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10150   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10151   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10152   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10153   ins_cost(250);
10154   format %{ "String IndexOf L [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10155   ins_encode %{
10156     __ string_indexof($result$$Register,
10157                       $haystack$$Register, $haycnt$$Register,
10158                       $needle$$Register, noreg, $needlecntImm$$constant,
10159                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10160   %}
10161   ins_pipe(pipe_class_dummy);
10162 %}
10163 
10164 instruct indexOf_imm_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, immI16 needlecntImm, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10165   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm)));
10166   effect(TEMP_DEF result, USE_KILL haycnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10167   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10168   ins_cost(250);
10169   format %{ "String IndexOf UL [0..$needlecntImm]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10170   ins_encode %{
10171     __ string_indexof($result$$Register,
10172                       $haystack$$Register, $haycnt$$Register,
10173                       $needle$$Register, noreg, $needlecntImm$$constant,
10174                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10175   %}
10176   ins_pipe(pipe_class_dummy);
10177 %}
10178 
10179 instruct indexOf_U(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10180   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10181   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10182   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU || ((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::none);
10183   ins_cost(300);
10184   format %{ "String IndexOf U [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10185   ins_encode %{
10186     __ string_indexof($result$$Register,
10187                       $haystack$$Register, $haycnt$$Register,
10188                       $needle$$Register, $needlecnt$$Register, 0,
10189                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UU);
10190   %}
10191   ins_pipe(pipe_class_dummy);
10192 %}
10193 
10194 instruct indexOf_L(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10195   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10196   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10197   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL);
10198   ins_cost(300);
10199   format %{ "String IndexOf L [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10200   ins_encode %{
10201     __ string_indexof($result$$Register,
10202                       $haystack$$Register, $haycnt$$Register,
10203                       $needle$$Register, $needlecnt$$Register, 0,
10204                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::LL);
10205   %}
10206   ins_pipe(pipe_class_dummy);
10207 %}
10208 
10209 instruct indexOf_UL(iRegP haystack, rarg2RegI haycnt, iRegP needle, rarg5RegI needlecnt, iRegI result, roddRegL oddReg, revenRegL evenReg, flagsReg cr) %{
10210   match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt)));
10211   effect(TEMP_DEF result, USE_KILL haycnt, USE_KILL needlecnt, TEMP oddReg, TEMP evenReg, KILL cr); // R0, R1 are killed, too.
10212   predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL);
10213   ins_cost(300);
10214   format %{ "String IndexOf UL [0..$needlecnt]($needle) .in. [0..$haycnt]($haystack) -> $result" %}
10215   ins_encode %{
10216     __ string_indexof($result$$Register,
10217                       $haystack$$Register, $haycnt$$Register,
10218                       $needle$$Register, $needlecnt$$Register, 0,
10219                       $oddReg$$Register, $evenReg$$Register, StrIntrinsicNode::UL);
10220   %}
10221   ins_pipe(pipe_class_dummy);
10222 %}
10223 
10224 // char[] to byte[] compression
10225 instruct string_compress(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10226   match(Set result (StrCompressedCopy src (Binary dst len)));
10227   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10228   ins_cost(300);
10229   format %{ "String Compress $src->$dst($len) -> $result" %}
10230   ins_encode %{
10231     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10232                        $tmp$$Register, false);
10233   %}
10234   ins_pipe(pipe_class_dummy);
10235 %}
10236 
10237 // byte[] to char[] inflation. trot implementation is shorter, but slower than the unrolled icm(h) loop.
10238 //instruct string_inflate_trot(Universe dummy, iRegP src, revenRegP dst, roddRegI len, iRegI tmp, flagsReg cr) %{
10239 //  match(Set dummy (StrInflatedCopy src (Binary dst len)));
10240 //  effect(USE_KILL dst, USE_KILL len, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10241 //  predicate(VM_Version::has_ETF2Enhancements());
10242 //  ins_cost(300);
10243 //  format %{ "String Inflate (trot) $dst,$src($len)" %}
10244 //  ins_encode %{
10245 //    __ string_inflate_trot($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10246 //  %}
10247 //  ins_pipe(pipe_class_dummy);
10248 //%}
10249 
10250 // byte[] to char[] inflation
10251 instruct string_inflate(Universe dummy, iRegP src, iRegP dst, iRegI len, iRegI tmp, flagsReg cr) %{
10252   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10253   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10254   ins_cost(300);
10255   format %{ "String Inflate $src->$dst($len)" %}
10256   ins_encode %{
10257     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register);
10258   %}
10259   ins_pipe(pipe_class_dummy);
10260 %}
10261 
10262 // byte[] to char[] inflation
10263 instruct string_inflate_const(Universe dummy, iRegP src, iRegP dst, iRegI tmp, immI len, flagsReg cr) %{
10264   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10265   effect(TEMP tmp, KILL cr); // R0, R1 are killed, too.
10266   ins_cost(300);
10267   format %{ "String Inflate (constLen) $src->$dst($len)" %}
10268   ins_encode %{
10269     __ string_inflate_const($src$$Register, $dst$$Register, $tmp$$Register, $len$$constant);
10270   %}
10271   ins_pipe(pipe_class_dummy);
10272 %}
10273 
10274 // StringCoding.java intrinsics
10275 instruct has_negatives(rarg5RegP ary1, iRegI len, iRegI result, roddRegI oddReg, revenRegI evenReg, iRegI tmp, flagsReg cr) %{
10276   match(Set result (HasNegatives ary1 len));
10277   effect(TEMP_DEF result, USE_KILL ary1, TEMP oddReg, TEMP evenReg, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10278   ins_cost(300);
10279   format %{ "has negatives byte[] $ary1($len) -> $result" %}
10280   ins_encode %{
10281     __ has_negatives($result$$Register, $ary1$$Register, $len$$Register,
10282                      $oddReg$$Register, $evenReg$$Register, $tmp$$Register);
10283   %}
10284   ins_pipe(pipe_class_dummy);
10285 %}
10286 
10287 // encode char[] to byte[] in ISO_8859_1
10288 instruct encode_iso_array(iRegP src, iRegP dst, iRegI result, iRegI len, iRegI tmp, flagsReg cr) %{
10289   predicate(!((EncodeISOArrayNode*)n)->is_ascii());
10290   match(Set result (EncodeISOArray src (Binary dst len)));
10291   effect(TEMP_DEF result, TEMP tmp, KILL cr); // R0, R1 are killed, too.
10292   ins_cost(300);
10293   format %{ "Encode array $src->$dst($len) -> $result" %}
10294   ins_encode %{
10295     __ string_compress($result$$Register, $src$$Register, $dst$$Register, $len$$Register,
10296                        $tmp$$Register, true);
10297   %}
10298   ins_pipe(pipe_class_dummy);
10299 %}
10300 
10301 
10302 //----------PEEPHOLE RULES-----------------------------------------------------
10303 // These must follow all instruction definitions as they use the names
10304 // defined in the instructions definitions.
10305 //
10306 // peepmatch (root_instr_name [preceeding_instruction]*);
10307 //
10308 // peepconstraint %{
10309 // (instruction_number.operand_name relational_op instruction_number.operand_name
10310 //  [, ...]);
10311 // // instruction numbers are zero-based using left to right order in peepmatch
10312 //
10313 // peepreplace (instr_name([instruction_number.operand_name]*));
10314 // // provide an instruction_number.operand_name for each operand that appears
10315 // // in the replacement instruction's match rule
10316 //
10317 // ---------VM FLAGS---------------------------------------------------------
10318 //
10319 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10320 //
10321 // Each peephole rule is given an identifying number starting with zero and
10322 // increasing by one in the order seen by the parser. An individual peephole
10323 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10324 // on the command-line.
10325 //
10326 // ---------CURRENT LIMITATIONS----------------------------------------------
10327 //
10328 // Only match adjacent instructions in same basic block
10329 // Only equality constraints
10330 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10331 // Only one replacement instruction
10332 //
10333 // ---------EXAMPLE----------------------------------------------------------
10334 //
10335 // // pertinent parts of existing instructions in architecture description
10336 // instruct movI(eRegI dst, eRegI src) %{
10337 //   match(Set dst (CopyI src));
10338 // %}
10339 //
10340 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10341 //   match(Set dst (AddI dst src));
10342 //   effect(KILL cr);
10343 // %}
10344 //
10345 // // Change (inc mov) to lea
10346 // peephole %{
10347 //   // increment preceeded by register-register move
10348 //   peepmatch (incI_eReg movI);
10349 //   // require that the destination register of the increment
10350 //   // match the destination register of the move
10351 //   peepconstraint (0.dst == 1.dst);
10352 //   // construct a replacement instruction that sets
10353 //   // the destination to (move's source register + one)
10354 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10355 // %}
10356 //
10357 // Implementation no longer uses movX instructions since
10358 // machine-independent system no longer uses CopyX nodes.
10359 //
10360 // peephole %{
10361 //   peepmatch (incI_eReg movI);
10362 //   peepconstraint (0.dst == 1.dst);
10363 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10364 // %}
10365 //
10366 // peephole %{
10367 //   peepmatch (decI_eReg movI);
10368 //   peepconstraint (0.dst == 1.dst);
10369 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10370 // %}
10371 //
10372 // peephole %{
10373 //   peepmatch (addI_eReg_imm movI);
10374 //   peepconstraint (0.dst == 1.dst);
10375 //   peepreplace (leaI_eReg_immI(0.dst 1.src 0.src));
10376 // %}
10377 //
10378 // peephole %{
10379 //   peepmatch (addP_eReg_imm movP);
10380 //   peepconstraint (0.dst == 1.dst);
10381 //   peepreplace (leaP_eReg_immI(0.dst 1.src 0.src));
10382 // %}
10383 
10384 
10385 //  This peephole rule does not work, probably because ADLC can't handle two effects:
10386 //  Effect 1 is defining 0.op1 and effect 2 is setting CC
10387 // condense a load from memory and subsequent test for zero
10388 // into a single, more efficient ICM instruction.
10389 // peephole %{
10390 //   peepmatch (compI_iReg_imm0 loadI);
10391 //   peepconstraint (1.dst == 0.op1);
10392 //   peepreplace (loadtest15_iReg_mem(0.op1 0.op1 1.mem));
10393 // %}
10394 
10395 // // Change load of spilled value to only a spill
10396 // instruct storeI(memory mem, eRegI src) %{
10397 //   match(Set mem (StoreI mem src));
10398 // %}
10399 //
10400 // instruct loadI(eRegI dst, memory mem) %{
10401 //   match(Set dst (LoadI mem));
10402 // %}
10403 //
10404 peephole %{
10405   peepmatch (loadI storeI);
10406   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10407   peepreplace (storeI(1.mem 1.mem 1.src));
10408 %}
10409 
10410 peephole %{
10411   peepmatch (loadL storeL);
10412   peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
10413   peepreplace (storeL(1.mem 1.mem 1.src));
10414 %}
10415 
10416 peephole %{
10417   peepmatch (loadP storeP);
10418   peepconstraint (1.src == 0.dst, 1.dst == 0.mem);
10419   peepreplace (storeP(1.dst 1.dst 1.src));
10420 %}
10421 
10422 //----------SUPERWORD RULES---------------------------------------------------
10423 
10424 //  Expand rules for special cases
10425 
10426 instruct expand_storeF(stackSlotF mem, regF src) %{
10427   // No match rule, false predicate, for expand only.
10428   effect(DEF mem, USE src);
10429   predicate(false);
10430   ins_cost(MEMORY_REF_COST);
10431   // TODO: s390 port size(FIXED_SIZE);
10432   format %{ "STE      $src,$mem\t # replicate(float2stack)" %}
10433   opcode(STE_ZOPC, STE_ZOPC);
10434   ins_encode(z_form_rt_mem(src, mem));
10435   ins_pipe(pipe_class_dummy);
10436 %}
10437 
10438 instruct expand_LoadLogical_I2L(iRegL dst, stackSlotF mem) %{
10439   // No match rule, false predicate, for expand only.
10440   effect(DEF dst, USE mem);
10441   predicate(false);
10442   ins_cost(MEMORY_REF_COST);
10443   // TODO: s390 port size(FIXED_SIZE);
10444   format %{ "LLGF     $dst,$mem\t # replicate(stack2reg(unsigned))" %}
10445   opcode(LLGF_ZOPC, LLGF_ZOPC);
10446   ins_encode(z_form_rt_mem(dst, mem));
10447   ins_pipe(pipe_class_dummy);
10448 %}
10449 
10450 // Replicate scalar int to packed int values (8 Bytes)
10451 instruct expand_Repl2I_reg(iRegL dst, iRegL src) %{
10452   // Dummy match rule, false predicate, for expand only.
10453   match(Set dst (ConvI2L src));
10454   predicate(false);
10455   ins_cost(DEFAULT_COST);
10456   // TODO: s390 port size(FIXED_SIZE);
10457   format %{ "REPLIC2F $dst,$src\t # replicate(pack2F)" %}
10458   ins_encode %{
10459     if ($dst$$Register == $src$$Register) {
10460       __ z_sllg(Z_R0_scratch, $src$$Register, 64-32);
10461       __ z_ogr($dst$$Register, Z_R0_scratch);
10462     }  else {
10463       __ z_sllg($dst$$Register, $src$$Register, 64-32);
10464       __ z_ogr( $dst$$Register, $src$$Register);
10465     }
10466   %}
10467   ins_pipe(pipe_class_dummy);
10468 %}
10469 
10470 // Replication
10471 
10472 // Exploit rotate_then_insert, if available
10473 // Replicate scalar byte to packed byte values (8 Bytes).
10474 instruct Repl8B_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10475   match(Set dst (ReplicateB src));
10476   effect(KILL cr);
10477   predicate((n->as_Vector()->length() == 8));
10478   format %{ "REPLIC8B $dst,$src\t # pack8B" %}
10479   ins_encode %{
10480     if ($dst$$Register != $src$$Register) {
10481       __ z_lgr($dst$$Register, $src$$Register);
10482     }
10483     __ rotate_then_insert($dst$$Register, $dst$$Register, 48, 55,  8, false);
10484     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10485     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10486   %}
10487   ins_pipe(pipe_class_dummy);
10488 %}
10489 
10490 // Replicate scalar byte to packed byte values (8 Bytes).
10491 instruct Repl8B_imm(iRegL dst, immB_n0m1 src) %{
10492   match(Set dst (ReplicateB src));
10493   predicate(n->as_Vector()->length() == 8);
10494   ins_should_rematerialize(true);
10495   format %{ "REPLIC8B $dst,$src\t # pack8B imm" %}
10496   ins_encode %{
10497     int64_t  Isrc8 = $src$$constant & 0x000000ff;
10498     int64_t Isrc16 =  Isrc8 <<  8 |  Isrc8;
10499     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10500     assert(Isrc8 != 0x000000ff && Isrc8 != 0, "should be handled by other match rules.");
10501 
10502     __ z_llilf($dst$$Register, Isrc32);
10503     __ z_iihf($dst$$Register, Isrc32);
10504   %}
10505   ins_pipe(pipe_class_dummy);
10506 %}
10507 
10508 // Replicate scalar byte to packed byte values (8 Bytes).
10509 instruct Repl8B_imm0(iRegL dst, immI_0 src) %{
10510   match(Set dst (ReplicateB src));
10511   predicate(n->as_Vector()->length() == 8);
10512   ins_should_rematerialize(true);
10513   format %{ "REPLIC8B $dst,$src\t # pack8B imm0" %}
10514   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10515   ins_pipe(pipe_class_dummy);
10516 %}
10517 
10518 // Replicate scalar byte to packed byte values (8 Bytes).
10519 instruct Repl8B_immm1(iRegL dst, immB_minus1 src) %{
10520   match(Set dst (ReplicateB src));
10521   predicate(n->as_Vector()->length() == 8);
10522   ins_should_rematerialize(true);
10523   format %{ "REPLIC8B $dst,$src\t # pack8B immm1" %}
10524   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10525   ins_pipe(pipe_class_dummy);
10526 %}
10527 
10528 // Exploit rotate_then_insert, if available
10529 // Replicate scalar short to packed short values (8 Bytes).
10530 instruct Repl4S_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10531   match(Set dst (ReplicateS src));
10532   effect(KILL cr);
10533   predicate((n->as_Vector()->length() == 4));
10534   format %{ "REPLIC4S $dst,$src\t # pack4S" %}
10535   ins_encode %{
10536     if ($dst$$Register != $src$$Register) {
10537       __ z_lgr($dst$$Register, $src$$Register);
10538     }
10539     __ rotate_then_insert($dst$$Register, $dst$$Register, 32, 47, 16, false);
10540     __ rotate_then_insert($dst$$Register, $dst$$Register,  0, 31, 32, false);
10541   %}
10542   ins_pipe(pipe_class_dummy);
10543 %}
10544 
10545 // Replicate scalar short to packed short values (8 Bytes).
10546 instruct Repl4S_imm(iRegL dst, immS_n0m1 src) %{
10547   match(Set dst (ReplicateS src));
10548   predicate(n->as_Vector()->length() == 4);
10549   ins_should_rematerialize(true);
10550   format %{ "REPLIC4S $dst,$src\t # pack4S imm" %}
10551   ins_encode %{
10552     int64_t Isrc16 = $src$$constant & 0x0000ffff;
10553     int64_t Isrc32 = Isrc16 << 16 | Isrc16;
10554     assert(Isrc16 != 0x0000ffff && Isrc16 != 0, "Repl4S_imm: (src == " INT64_FORMAT
10555            ") should be handled by other match rules.", $src$$constant);
10556 
10557     __ z_llilf($dst$$Register, Isrc32);
10558     __ z_iihf($dst$$Register, Isrc32);
10559   %}
10560   ins_pipe(pipe_class_dummy);
10561 %}
10562 
10563 // Replicate scalar short to packed short values (8 Bytes).
10564 instruct Repl4S_imm0(iRegL dst, immI_0 src) %{
10565   match(Set dst (ReplicateS src));
10566   predicate(n->as_Vector()->length() == 4);
10567   ins_should_rematerialize(true);
10568   format %{ "REPLIC4S $dst,$src\t # pack4S imm0" %}
10569   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10570   ins_pipe(pipe_class_dummy);
10571 %}
10572 
10573 // Replicate scalar short to packed short values (8 Bytes).
10574 instruct Repl4S_immm1(iRegL dst, immS_minus1 src) %{
10575   match(Set dst (ReplicateS src));
10576   predicate(n->as_Vector()->length() == 4);
10577   ins_should_rematerialize(true);
10578   format %{ "REPLIC4S $dst,$src\t # pack4S immm1" %}
10579   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10580   ins_pipe(pipe_class_dummy);
10581 %}
10582 
10583 // Exploit rotate_then_insert, if available.
10584 // Replicate scalar int to packed int values (8 Bytes).
10585 instruct Repl2I_reg_risbg(iRegL dst, iRegI src, flagsReg cr) %{
10586   match(Set dst (ReplicateI src));
10587   effect(KILL cr);
10588   predicate((n->as_Vector()->length() == 2));
10589   format %{ "REPLIC2I $dst,$src\t # pack2I" %}
10590   ins_encode %{
10591     if ($dst$$Register != $src$$Register) {
10592       __ z_lgr($dst$$Register, $src$$Register);
10593     }
10594     __ rotate_then_insert($dst$$Register, $dst$$Register, 0, 31, 32, false);
10595   %}
10596   ins_pipe(pipe_class_dummy);
10597 %}
10598 
10599 // Replicate scalar int to packed int values (8 Bytes).
10600 instruct Repl2I_imm(iRegL dst, immI_n0m1 src) %{
10601   match(Set dst (ReplicateI src));
10602   predicate(n->as_Vector()->length() == 2);
10603   ins_should_rematerialize(true);
10604   format %{ "REPLIC2I $dst,$src\t # pack2I imm" %}
10605   ins_encode %{
10606     int64_t Isrc32 = $src$$constant;
10607     assert(Isrc32 != -1 && Isrc32 != 0, "should be handled by other match rules.");
10608 
10609     __ z_llilf($dst$$Register, Isrc32);
10610     __ z_iihf($dst$$Register, Isrc32);
10611   %}
10612   ins_pipe(pipe_class_dummy);
10613 %}
10614 
10615 // Replicate scalar int to packed int values (8 Bytes).
10616 instruct Repl2I_imm0(iRegL dst, immI_0 src) %{
10617   match(Set dst (ReplicateI src));
10618   predicate(n->as_Vector()->length() == 2);
10619   ins_should_rematerialize(true);
10620   format %{ "REPLIC2I $dst,$src\t # pack2I imm0" %}
10621   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10622   ins_pipe(pipe_class_dummy);
10623 %}
10624 
10625 // Replicate scalar int to packed int values (8 Bytes).
10626 instruct Repl2I_immm1(iRegL dst, immI_minus1 src) %{
10627   match(Set dst (ReplicateI src));
10628   predicate(n->as_Vector()->length() == 2);
10629   ins_should_rematerialize(true);
10630   format %{ "REPLIC2I $dst,$src\t # pack2I immm1" %}
10631   ins_encode %{ __ z_lghi($dst$$Register, -1); %}
10632   ins_pipe(pipe_class_dummy);
10633 %}
10634 
10635 //
10636 
10637 instruct Repl2F_reg_indirect(iRegL dst, regF src, flagsReg cr) %{
10638   match(Set dst (ReplicateF src));
10639   effect(KILL cr);
10640   predicate(!VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10641   format %{ "REPLIC2F $dst,$src\t # pack2F indirect" %}
10642   expand %{
10643     stackSlotF tmp;
10644     iRegL      tmp2;
10645     expand_storeF(tmp, src);
10646     expand_LoadLogical_I2L(tmp2, tmp);
10647     expand_Repl2I_reg(dst, tmp2);
10648   %}
10649 %}
10650 
10651 // Replicate scalar float to packed float values in GREG (8 Bytes).
10652 instruct Repl2F_reg_direct(iRegL dst, regF src, flagsReg cr) %{
10653   match(Set dst (ReplicateF src));
10654   effect(KILL cr);
10655   predicate(VM_Version::has_FPSupportEnhancements() && n->as_Vector()->length() == 2);
10656   format %{ "REPLIC2F $dst,$src\t # pack2F direct" %}
10657   ins_encode %{
10658     assert(VM_Version::has_FPSupportEnhancements(), "encoder should never be called on old H/W");
10659     __ z_lgdr($dst$$Register, $src$$FloatRegister);
10660 
10661     __ z_srlg(Z_R0_scratch, $dst$$Register, 32);  // Floats are left-justified in 64bit reg.
10662     __ z_iilf($dst$$Register, 0);                 // Save a "result not ready" stall.
10663     __ z_ogr($dst$$Register, Z_R0_scratch);
10664   %}
10665   ins_pipe(pipe_class_dummy);
10666 %}
10667 
10668 // Replicate scalar float immediate to packed float values in GREG (8 Bytes).
10669 instruct Repl2F_imm(iRegL dst, immF src) %{
10670   match(Set dst (ReplicateF src));
10671   predicate(n->as_Vector()->length() == 2);
10672   ins_should_rematerialize(true);
10673   format %{ "REPLIC2F $dst,$src\t # pack2F imm" %}
10674   ins_encode %{
10675     union {
10676       int   Isrc32;
10677       float Fsrc32;
10678     };
10679     Fsrc32 = $src$$constant;
10680     __ z_llilf($dst$$Register, Isrc32);
10681     __ z_iihf($dst$$Register, Isrc32);
10682   %}
10683   ins_pipe(pipe_class_dummy);
10684 %}
10685 
10686 // Replicate scalar float immediate zeroes to packed float values in GREG (8 Bytes).
10687 // Do this only for 'real' zeroes, especially don't loose sign of negative zeroes.
10688 instruct Repl2F_imm0(iRegL dst, immFp0 src) %{
10689   match(Set dst (ReplicateF src));
10690   predicate(n->as_Vector()->length() == 2);
10691   ins_should_rematerialize(true);
10692   format %{ "REPLIC2F $dst,$src\t # pack2F imm0" %}
10693   ins_encode %{ __ z_laz($dst$$Register, 0, Z_R0); %}
10694   ins_pipe(pipe_class_dummy);
10695 %}
10696 
10697 // Load/Store vector
10698 
10699 // Store Aligned Packed Byte register to memory (8 Bytes).
10700 instruct storeA8B(memory mem, iRegL src) %{
10701   match(Set mem (StoreVector mem src));
10702   predicate(n->as_StoreVector()->memory_size() == 8);
10703   ins_cost(MEMORY_REF_COST);
10704   // TODO: s390 port size(VARIABLE_SIZE);
10705   format %{ "STG     $src,$mem\t # ST(packed8B)" %}
10706   opcode(STG_ZOPC, STG_ZOPC);
10707   ins_encode(z_form_rt_mem_opt(src, mem));
10708   ins_pipe(pipe_class_dummy);
10709 %}
10710 
10711 instruct loadV8(iRegL dst, memory mem) %{
10712   match(Set dst (LoadVector mem));
10713   predicate(n->as_LoadVector()->memory_size() == 8);
10714   ins_cost(MEMORY_REF_COST);
10715   // TODO: s390 port size(VARIABLE_SIZE);
10716   format %{ "LG      $dst,$mem\t # L(packed8B)" %}
10717   opcode(LG_ZOPC, LG_ZOPC);
10718   ins_encode(z_form_rt_mem_opt(dst, mem));
10719   ins_pipe(pipe_class_dummy);
10720 %}
10721 
10722 // Reinterpret: only one vector size used
10723 instruct reinterpret(iRegL dst) %{
10724   match(Set dst (VectorReinterpret dst));
10725   ins_cost(0);
10726   format %{ "reinterpret $dst" %}
10727   ins_encode( /*empty*/ );
10728   ins_pipe(pipe_class_dummy);
10729 %}
10730 
10731 //----------POPULATION COUNT RULES--------------------------------------------
10732 
10733 // Byte reverse
10734 
10735 instruct bytes_reverse_int(iRegI dst, iRegI src) %{
10736   match(Set dst (ReverseBytesI src));
10737   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10738   ins_cost(DEFAULT_COST);
10739   size(4);
10740   format %{ "LRVR    $dst,$src\t # byte reverse int" %}
10741   opcode(LRVR_ZOPC);
10742   ins_encode(z_rreform(dst, src));
10743   ins_pipe(pipe_class_dummy);
10744 %}
10745 
10746 instruct bytes_reverse_long(iRegL dst, iRegL src) %{
10747   match(Set dst (ReverseBytesL src));
10748   predicate(UseByteReverseInstruction);  // See Matcher::match_rule_supported
10749   ins_cost(DEFAULT_COST);
10750   // TODO: s390 port size(FIXED_SIZE);
10751   format %{ "LRVGR   $dst,$src\t # byte reverse long" %}
10752   opcode(LRVGR_ZOPC);
10753   ins_encode(z_rreform(dst, src));
10754   ins_pipe(pipe_class_dummy);
10755 %}
10756 
10757 // Leading zeroes
10758 
10759 // The instruction FLOGR (Find Leftmost One in Grande (64bit) Register)
10760 // returns the bit position of the leftmost 1 in the 64bit source register.
10761 // As the bits are numbered from left to right (0..63), the returned
10762 // position index is equivalent to the number of leading zeroes.
10763 // If no 1-bit is found (i.e. the regsiter contains zero), the instruction
10764 // returns position 64. That's exactly what we need.
10765 
10766 instruct countLeadingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10767   match(Set dst (CountLeadingZerosI src));
10768   effect(KILL tmp, KILL cr);
10769   ins_cost(3 * DEFAULT_COST);
10770   size(14);
10771   format %{ "SLLG    $dst,$src,32\t # no need to always count 32 zeroes first\n\t"
10772             "IILH    $dst,0x8000 \t # insert \"stop bit\" to force result 32 for zero src.\n\t"
10773             "FLOGR   $dst,$dst"
10774          %}
10775   ins_encode %{
10776     // Performance experiments indicate that "FLOGR" is using some kind of
10777     // iteration to find the leftmost "1" bit.
10778     //
10779     // The prior implementation zero-extended the 32-bit argument to 64 bit,
10780     // thus forcing "FLOGR" to count 32 bits of which we know they are zero.
10781     // We could gain measurable speedup in micro benchmark:
10782     //
10783     //               leading   trailing
10784     //   z10:   int     2.04       1.68
10785     //         long     1.00       1.02
10786     //   z196:  int     0.99       1.23
10787     //         long     1.00       1.11
10788     //
10789     // By shifting the argument into the high-word instead of zero-extending it.
10790     // The add'l branch on condition (taken for a zero argument, very infrequent,
10791     // good prediction) is well compensated for by the savings.
10792     //
10793     // We leave the previous implementation in for some time in the future when
10794     // the "FLOGR" instruction may become less iterative.
10795 
10796     // Version 2: shows 62%(z9), 204%(z10), -1%(z196) improvement over original
10797     __ z_sllg($dst$$Register, $src$$Register, 32); // No need to always count 32 zeroes first.
10798     __ z_iilh($dst$$Register, 0x8000);   // Insert "stop bit" to force result 32 for zero src.
10799     __ z_flogr($dst$$Register, $dst$$Register);
10800   %}
10801   ins_pipe(pipe_class_dummy);
10802 %}
10803 
10804 instruct countLeadingZerosL(revenRegI dst, iRegL src, roddRegI tmp, flagsReg cr) %{
10805   match(Set dst (CountLeadingZerosL src));
10806   effect(KILL tmp, KILL cr);
10807   ins_cost(DEFAULT_COST);
10808   size(4);
10809   format %{ "FLOGR   $dst,$src \t # count leading zeros (long)\n\t" %}
10810   ins_encode %{ __ z_flogr($dst$$Register, $src$$Register); %}
10811   ins_pipe(pipe_class_dummy);
10812 %}
10813 
10814 // trailing zeroes
10815 
10816 // We transform the trailing zeroes problem to a leading zeroes problem
10817 // such that can use the FLOGR instruction to our advantage.
10818 
10819 // With
10820 //   tmp1 = src - 1
10821 // we flip all trailing zeroes to ones and the rightmost one to zero.
10822 // All other bits remain unchanged.
10823 // With the complement
10824 //   tmp2 = ~src
10825 // we get all ones in the trailing zeroes positions. Thus,
10826 //   tmp3 = tmp1 & tmp2
10827 // yields ones in the trailing zeroes positions and zeroes elsewhere.
10828 // Now we can apply FLOGR and get 64-(trailing zeroes).
10829 instruct countTrailingZerosI(revenRegI dst, iRegI src, roddRegI tmp, flagsReg cr) %{
10830   match(Set dst (CountTrailingZerosI src));
10831   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10832   ins_cost(8 * DEFAULT_COST);
10833   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10834   format %{ "LLGFR   $dst,$src  \t # clear upper 32 bits (we are dealing with int)\n\t"
10835             "LCGFR   $tmp,$src  \t # load 2's complement (32->64 bit)\n\t"
10836             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10837             "AGHI    $tmp,-1    \t # tmp2 = -src-1 = ~src\n\t"
10838             "NGR     $dst,$tmp  \t # tmp3 = tmp1&tmp2\n\t"
10839             "FLOGR   $dst,$dst  \t # count trailing zeros (int)\n\t"
10840             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10841             "LCR     $dst,$dst  \t # res = -tmp4"
10842          %}
10843   ins_encode %{
10844     Register Rdst = $dst$$Register;
10845     Register Rsrc = $src$$Register;
10846     // Rtmp only needed for for zero-argument shortcut. With kill effect in
10847     // match rule Rsrc = roddReg would be possible, saving one register.
10848     Register Rtmp = $tmp$$Register;
10849 
10850     assert_different_registers(Rdst, Rsrc, Rtmp);
10851 
10852     // Algorithm:
10853     // - Isolate the least significant (rightmost) set bit using (src & (-src)).
10854     //   All other bits in the result are zero.
10855     // - Find the "leftmost one" bit position in the single-bit result from previous step.
10856     // - 63-("leftmost one" bit position) gives the # of trailing zeros.
10857 
10858     // Version 2: shows 79%(z9), 68%(z10), 23%(z196) improvement over original.
10859     Label done;
10860     __ load_const_optimized(Rdst, 32); // Prepare for shortcut (zero argument), result will be 32.
10861     __ z_lcgfr(Rtmp, Rsrc);
10862     __ z_bre(done);                    // Taken very infrequently, good prediction, no BHT entry.
10863 
10864     __ z_nr(Rtmp, Rsrc);               // (src) & (-src) leaves nothing but least significant bit.
10865     __ z_ahi(Rtmp,  -1);               // Subtract one to fill all trailing zero positions with ones.
10866                                        // Use 32bit op to prevent borrow propagation (case Rdst = 0x80000000)
10867                                        // into upper half of reg. Not relevant with sllg below.
10868     __ z_sllg(Rdst, Rtmp, 32);         // Shift interesting contents to upper half of register.
10869     __ z_bre(done);                    // Shortcut for argument = 1, result will be 0.
10870                                        // Depends on CC set by ahi above.
10871                                        // Taken very infrequently, good prediction, no BHT entry.
10872                                        // Branch delayed to have Rdst set correctly (Rtmp == 0(32bit)
10873                                        // after SLLG Rdst == 0(64bit)).
10874     __ z_flogr(Rdst, Rdst);            // Kills tmp which is the oddReg for dst.
10875     __ add2reg(Rdst,  -32);            // 32-pos(leftmost1) is #trailing zeros
10876     __ z_lcgfr(Rdst, Rdst);            // Provide 64bit result at no cost.
10877     __ bind(done);
10878   %}
10879   ins_pipe(pipe_class_dummy);
10880 %}
10881 
10882 instruct countTrailingZerosL(revenRegI dst, iRegL src, roddRegL tmp, flagsReg cr) %{
10883   match(Set dst (CountTrailingZerosL src));
10884   effect(TEMP_DEF dst, KILL tmp, KILL cr);
10885   ins_cost(8 * DEFAULT_COST);
10886   // TODO: s390 port size(FIXED_SIZE);  // Emitted code depends on PreferLAoverADD being on/off.
10887   format %{ "LCGR    $dst,$src  \t # preserve src\n\t"
10888             "NGR     $dst,$src  \t #\n\t"
10889             "AGHI    $dst,-1    \t # tmp1 = src-1\n\t"
10890             "FLOGR   $dst,$dst  \t # count trailing zeros (long), kill $tmp\n\t"
10891             "AHI     $dst,-64   \t # tmp4 = 64-(trailing zeroes)-64\n\t"
10892             "LCR     $dst,$dst  \t #"
10893          %}
10894   ins_encode %{
10895     Register Rdst = $dst$$Register;
10896     Register Rsrc = $src$$Register;
10897     assert_different_registers(Rdst, Rsrc); // Rtmp == Rsrc allowed.
10898 
10899     // New version: shows 5%(z9), 2%(z10), 11%(z196) improvement over original.
10900     __ z_lcgr(Rdst, Rsrc);
10901     __ z_ngr(Rdst, Rsrc);
10902     __ add2reg(Rdst,   -1);
10903     __ z_flogr(Rdst, Rdst); // Kills tmp which is the oddReg for dst.
10904     __ add2reg(Rdst,  -64);
10905     __ z_lcgfr(Rdst, Rdst); // Provide 64bit result at no cost.
10906   %}
10907   ins_pipe(pipe_class_dummy);
10908 %}
10909 
10910 
10911 // bit count
10912 
10913 instruct popCountI(iRegI dst, iRegI src, iRegI tmp, flagsReg cr) %{
10914   match(Set dst (PopCountI src));
10915   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10916   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10917   ins_cost(DEFAULT_COST);
10918   size(24);
10919   format %{ "POPCNT  $dst,$src\t # pop count int" %}
10920   ins_encode %{
10921     Register Rdst = $dst$$Register;
10922     Register Rsrc = $src$$Register;
10923     Register Rtmp = $tmp$$Register;
10924 
10925     // Prefer compile-time assertion over run-time SIGILL.
10926     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10927     assert_different_registers(Rdst, Rtmp);
10928 
10929     // Version 2: shows 10%(z196) improvement over original.
10930     __ z_popcnt(Rdst, Rsrc);
10931     __ z_srlg(Rtmp, Rdst, 16); // calc  byte4+byte6 and byte5+byte7
10932     __ z_alr(Rdst, Rtmp);      //   into byte6 and byte7
10933     __ z_srlg(Rtmp, Rdst,  8); // calc (byte4+byte6) + (byte5+byte7)
10934     __ z_alr(Rdst, Rtmp);      //   into byte7
10935     __ z_llgcr(Rdst, Rdst);    // zero-extend sum
10936   %}
10937   ins_pipe(pipe_class_dummy);
10938 %}
10939 
10940 instruct popCountL(iRegI dst, iRegL src, iRegL tmp, flagsReg cr) %{
10941   match(Set dst (PopCountL src));
10942   effect(TEMP_DEF dst, TEMP tmp, KILL cr);
10943   predicate(UsePopCountInstruction && VM_Version::has_PopCount());
10944   ins_cost(DEFAULT_COST);
10945   // TODO: s390 port size(FIXED_SIZE);
10946   format %{ "POPCNT  $dst,$src\t # pop count long" %}
10947   ins_encode %{
10948     Register Rdst = $dst$$Register;
10949     Register Rsrc = $src$$Register;
10950     Register Rtmp = $tmp$$Register;
10951 
10952     // Prefer compile-time assertion over run-time SIGILL.
10953     assert(VM_Version::has_PopCount(), "bad predicate for countLeadingZerosI");
10954     assert_different_registers(Rdst, Rtmp);
10955 
10956     // Original version. Using LA instead of algr seems to be a really bad idea (-35%).
10957     __ z_popcnt(Rdst, Rsrc);
10958     __ z_ahhlr(Rdst, Rdst, Rdst);
10959     __ z_sllg(Rtmp, Rdst, 16);
10960     __ z_algr(Rdst, Rtmp);
10961     __ z_sllg(Rtmp, Rdst,  8);
10962     __ z_algr(Rdst, Rtmp);
10963     __ z_srlg(Rdst, Rdst, 56);
10964   %}
10965   ins_pipe(pipe_class_dummy);
10966 %}
10967 
10968 //----------SMARTSPILL RULES---------------------------------------------------
10969 // These must follow all instruction definitions as they use the names
10970 // defined in the instructions definitions.
10971 
10972 // ============================================================================
10973 // TYPE PROFILING RULES