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src/hotspot/cpu/x86/assembler_x86.cpp

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 4870   int encode = prefix_and_encode(dst->encoding());
 4871   emit_int8(0x58 | encode);
 4872 }
 4873 
 4874 void Assembler::popcntl(Register dst, Address src) {
 4875   assert(VM_Version::supports_popcnt(), "must support");
 4876   InstructionMark im(this);
 4877   emit_int8((unsigned char)0xF3);
 4878   prefix(src, dst);
 4879   emit_int16(0x0F, (unsigned char)0xB8);
 4880   emit_operand(dst, src);
 4881 }
 4882 
 4883 void Assembler::popcntl(Register dst, Register src) {
 4884   assert(VM_Version::supports_popcnt(), "must support");
 4885   emit_int8((unsigned char)0xF3);
 4886   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 4887   emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
 4888 }
 4889 
 4890 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {


























 4891   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4892   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);

 4893   attributes.set_is_evex_instruction();




 4894   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4895   emit_int16(0x55, (0xC0 | encode));
 4896 }
 4897 
 4898 void Assembler::vpopcntq(XMMRegister dst, XMMRegister src, int vector_len) {
 4899   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4900   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);

 4901   attributes.set_is_evex_instruction();




 4902   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4903   emit_int16(0x55, (0xC0 | encode));
 4904 }
 4905 
 4906 void Assembler::popf() {
 4907   emit_int8((unsigned char)0x9D);
 4908 }
 4909 
 4910 #ifndef _LP64 // no 32bit push/pop on amd64
 4911 void Assembler::popl(Address dst) {
 4912   // NOTE: this will adjust stack by 8byte on 64bits
 4913   InstructionMark im(this);
 4914   prefix(dst);
 4915   emit_int8((unsigned char)0x8F);
 4916   emit_operand(rax, dst);
 4917 }
 4918 #endif
 4919 
 4920 void Assembler::prefetchnta(Address src) {
 4921   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));

 7926 }
 7927 
 7928 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7929   assert(VM_Version::supports_evex(), "requires EVEX support");
 7930   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7931   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7932   attributes.set_is_evex_instruction();
 7933   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7934   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 7935 }
 7936 
 7937 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7938   assert(VM_Version::supports_evex(), "requires EVEX support");
 7939   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7940   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7941   attributes.set_is_evex_instruction();
 7942   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7943   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 7944 }
 7945 
























 7946 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 7947   assert(VM_Version::supports_evex(), "requires EVEX support");
 7948   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7949   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7950   attributes.set_is_evex_instruction();
 7951   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 7952   emit_int8(0x25);
 7953   emit_int8((unsigned char)(0xC0 | encode));
 7954   emit_int8(imm8);
 7955 }
 7956 
 7957 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
 7958   assert(VM_Version::supports_evex(), "requires EVEX support");
 7959   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7960   assert(dst != xnoreg, "sanity");
 7961   InstructionMark im(this);
 7962   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7963   attributes.set_is_evex_instruction();
 7964   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 7965   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 7966   emit_int8(0x25);
 7967   emit_operand(dst, src3);
 7968   emit_int8(imm8);
 7969 }
 7970 
 7971 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 7972   assert(VM_Version::supports_evex(), "requires EVEX support");
 7973   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7974   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7975   attributes.set_is_evex_instruction();
 7976   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 7977   emit_int8(0x25);
 7978   emit_int8((unsigned char)(0xC0 | encode));
 7979   emit_int8(imm8);
 7980 }
 7981 














































































 7982 // vinserti forms
 7983 
 7984 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 7985   assert(VM_Version::supports_avx2(), "");
 7986   assert(imm8 <= 0x01, "imm8: %u", imm8);
 7987   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7988   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 7989   // last byte:
 7990   // 0x00 - insert into lower 128 bits
 7991   // 0x01 - insert into upper 128 bits
 7992   emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
 7993 }
 7994 
 7995 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 7996   assert(VM_Version::supports_avx2(), "");
 7997   assert(dst != xnoreg, "sanity");
 7998   assert(imm8 <= 0x01, "imm8: %u", imm8);
 7999   InstructionMark im(this);
 8000   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8001   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);

 8005   // 0x00 - insert into lower 128 bits
 8006   // 0x01 - insert into upper 128 bits
 8007   emit_int8(imm8 & 0x01);
 8008 }
 8009 
 8010 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8011   assert(VM_Version::supports_evex(), "");
 8012   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8013   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8014   attributes.set_is_evex_instruction();
 8015   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8016   // imm8:
 8017   // 0x00 - insert into q0 128 bits (0..127)
 8018   // 0x01 - insert into q1 128 bits (128..255)
 8019   // 0x02 - insert into q2 128 bits (256..383)
 8020   // 0x03 - insert into q3 128 bits (384..511)
 8021   emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
 8022 }
 8023 
 8024 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8025   assert(VM_Version::supports_avx(), "");
 8026   assert(dst != xnoreg, "sanity");
 8027   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8028   InstructionMark im(this);
 8029   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8030   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8031   attributes.set_is_evex_instruction();
 8032   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8033   emit_int8(0x18);
 8034   emit_operand(dst, src);
 8035   // 0x00 - insert into q0 128 bits (0..127)
 8036   // 0x01 - insert into q1 128 bits (128..255)
 8037   // 0x02 - insert into q2 128 bits (256..383)
 8038   // 0x03 - insert into q3 128 bits (384..511)
 8039   emit_int8(imm8 & 0x03);
 8040 }
 8041 
 8042 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8043   assert(VM_Version::supports_evex(), "");
 8044   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8045   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);

 8064   // 0x01 - insert into upper 128 bits
 8065   emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
 8066 }
 8067 
 8068 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8069   assert(VM_Version::supports_avx(), "");
 8070   assert(dst != xnoreg, "sanity");
 8071   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8072   InstructionMark im(this);
 8073   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8074   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8075   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8076   emit_int8(0x18);
 8077   emit_operand(dst, src);
 8078   // 0x00 - insert into lower 128 bits
 8079   // 0x01 - insert into upper 128 bits
 8080   emit_int8(imm8 & 0x01);
 8081 }
 8082 
 8083 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8084   assert(VM_Version::supports_avx2(), "");
 8085   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8086   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8087   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8088   // imm8:
 8089   // 0x00 - insert into q0 128 bits (0..127)
 8090   // 0x01 - insert into q1 128 bits (128..255)
 8091   // 0x02 - insert into q0 128 bits (256..383)
 8092   // 0x03 - insert into q1 128 bits (384..512)
 8093   emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
 8094 }
 8095 
 8096 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8097   assert(VM_Version::supports_avx(), "");
 8098   assert(dst != xnoreg, "sanity");
 8099   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8100   InstructionMark im(this);
 8101   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8102   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8103   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8104   emit_int8(0x18);
 8105   emit_operand(dst, src);
 8106   // 0x00 - insert into q0 128 bits (0..127)
 8107   // 0x01 - insert into q1 128 bits (128..255)
 8108   // 0x02 - insert into q0 128 bits (256..383)
 8109   // 0x03 - insert into q1 128 bits (384..512)
 8110   emit_int8(imm8 & 0x03);
 8111 }
 8112 
 8113 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8114   assert(VM_Version::supports_evex(), "");
 8115   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8116   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8117   attributes.set_is_evex_instruction();

 8378 
 8379 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
 8380   assert(VM_Version::supports_avx2(), "");
 8381   assert(dst != xnoreg, "sanity");
 8382   InstructionMark im(this);
 8383   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8384   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 8385   // swap src<->dst for encoding
 8386   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8387   emit_int8(0x79);
 8388   emit_operand(dst, src);
 8389 }
 8390 
 8391 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8392   assert(UseAVX > 0, "requires some form of AVX");
 8393   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8394   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8395   emit_int16((unsigned char)0xF6, (0xC0 | encode));
 8396 }
 8397 














 8398 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8399   assert(UseAVX > 0, "requires some form of AVX");
 8400   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8401   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8402   emit_int16(0x6A, (0xC0 | encode));
 8403 }
 8404 
 8405 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8406   assert(UseAVX > 0, "requires some form of AVX");
 8407   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8408   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8409   emit_int16(0x62, (0xC0 | encode));
 8410 }
 8411 
 8412 // xmm/mem sourced byte/word/dword/qword replicate
 8413 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8414   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8415   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8416   attributes.set_is_evex_instruction();
 8417   attributes.set_embedded_opmask_register_specifier(mask);

 9894 }
 9895 
 9896 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
 9897   assert(VM_Version::supports_evex(), "requires EVEX support");
 9898   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 9899   assert(dst != xnoreg, "sanity");
 9900   InstructionMark im(this);
 9901   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 9902   attributes.set_is_evex_instruction();
 9903   attributes.set_embedded_opmask_register_specifier(mask);
 9904   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 9905   if (merge) {
 9906     attributes.reset_is_clear_context();
 9907   }
 9908   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 9909   emit_int8(0x25);
 9910   emit_operand(dst, src3);
 9911   emit_int8(imm8);
 9912 }
 9913 








 9914 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
 9915 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
 9916   assert(UseAVX >= 2, "");
 9917   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 9918   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9919   emit_int16(0x58, (0xC0 | encode));
 9920 }
 9921 
 9922 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
 9923   assert(VM_Version::supports_avx2(), "");
 9924   assert(dst != xnoreg, "sanity");
 9925   InstructionMark im(this);
 9926   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 9927   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
 9928   // swap src<->dst for encoding
 9929   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 9930   emit_int8(0x58);
 9931   emit_operand(dst, src);
 9932 }
 9933 

11587   attributes.set_is_evex_instruction();
11588   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11589   emit_int16(0x38, (0xC0 | encode));
11590 }
11591 
11592 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
11593   assert(VM_Version::supports_avx512vlbw(), "");
11594   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11595   attributes.set_is_evex_instruction();
11596   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11597   emit_int16(0x28, (0xC0 | encode));
11598 }
11599 
11600 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
11601   assert(VM_Version::supports_avx512vlbw(), "");
11602   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11603   attributes.set_is_evex_instruction();
11604   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11605   emit_int16(0x28, (0xC0 | encode));
11606 }









































































11607 #ifndef _LP64
11608 
11609 void Assembler::incl(Register dst) {
11610   // Don't use it directly. Use MacroAssembler::incrementl() instead.
11611   emit_int8(0x40 | dst->encoding());
11612 }
11613 
11614 void Assembler::lea(Register dst, Address src) {
11615   leal(dst, src);
11616 }
11617 
11618 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
11619   InstructionMark im(this);
11620   emit_int8((unsigned char)0xC7);
11621   emit_operand(rax, dst);
11622   emit_data((int)imm32, rspec, 0);
11623 }
11624 
11625 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
11626   InstructionMark im(this);

 4870   int encode = prefix_and_encode(dst->encoding());
 4871   emit_int8(0x58 | encode);
 4872 }
 4873 
 4874 void Assembler::popcntl(Register dst, Address src) {
 4875   assert(VM_Version::supports_popcnt(), "must support");
 4876   InstructionMark im(this);
 4877   emit_int8((unsigned char)0xF3);
 4878   prefix(src, dst);
 4879   emit_int16(0x0F, (unsigned char)0xB8);
 4880   emit_operand(dst, src);
 4881 }
 4882 
 4883 void Assembler::popcntl(Register dst, Register src) {
 4884   assert(VM_Version::supports_popcnt(), "must support");
 4885   emit_int8((unsigned char)0xF3);
 4886   int encode = prefix_and_encode(dst->encoding(), src->encoding());
 4887   emit_int24(0x0F, (unsigned char)0xB8, (0xC0 | encode));
 4888 }
 4889 
 4890 void Assembler::evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4891   assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
 4892   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4893   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4894   attributes.set_embedded_opmask_register_specifier(mask);
 4895   attributes.set_is_evex_instruction();
 4896   if (merge) {
 4897     attributes.reset_is_clear_context();
 4898   }
 4899   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4900   emit_int16(0x54, (0xC0 | encode));
 4901 }
 4902 
 4903 void Assembler::evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4904   assert(VM_Version::supports_avx512_bitalg(), "must support avx512bitalg feature");
 4905   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4906   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4907   attributes.set_is_evex_instruction();
 4908   attributes.set_embedded_opmask_register_specifier(mask);
 4909   if (merge) {
 4910     attributes.reset_is_clear_context();
 4911   }
 4912   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4913   emit_int16(0x54, (0xC0 | encode));
 4914 }
 4915 
 4916 void Assembler::evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4917   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4918   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4919   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4920   attributes.set_is_evex_instruction();
 4921   attributes.set_embedded_opmask_register_specifier(mask);
 4922   if (merge) {
 4923     attributes.reset_is_clear_context();
 4924   }
 4925   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4926   emit_int16(0x55, (0xC0 | encode));
 4927 }
 4928 
 4929 void Assembler::evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 4930   assert(VM_Version::supports_avx512_vpopcntdq(), "must support vpopcntdq feature");
 4931   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 4932   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
 4933   attributes.set_is_evex_instruction();
 4934   attributes.set_embedded_opmask_register_specifier(mask);
 4935   if (merge) {
 4936     attributes.reset_is_clear_context();
 4937   }
 4938   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 4939   emit_int16(0x55, (0xC0 | encode));
 4940 }
 4941 
 4942 void Assembler::popf() {
 4943   emit_int8((unsigned char)0x9D);
 4944 }
 4945 
 4946 #ifndef _LP64 // no 32bit push/pop on amd64
 4947 void Assembler::popl(Address dst) {
 4948   // NOTE: this will adjust stack by 8byte on 64bits
 4949   InstructionMark im(this);
 4950   prefix(dst);
 4951   emit_int8((unsigned char)0x8F);
 4952   emit_operand(rax, dst);
 4953 }
 4954 #endif
 4955 
 4956 void Assembler::prefetchnta(Address src) {
 4957   NOT_LP64(assert(VM_Version::supports_sse(), "must support"));

 7962 }
 7963 
 7964 void Assembler::evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7965   assert(VM_Version::supports_evex(), "requires EVEX support");
 7966   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7967   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7968   attributes.set_is_evex_instruction();
 7969   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7970   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 7971 }
 7972 
 7973 void Assembler::evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
 7974   assert(VM_Version::supports_evex(), "requires EVEX support");
 7975   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 7976   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 7977   attributes.set_is_evex_instruction();
 7978   int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7979   emit_int16(0x14, (unsigned char)(0xC0 | encode));
 7980 }
 7981 
 7982 void Assembler::evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 7983   assert(VM_Version::supports_avx512cd() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 7984   InstructionAttr attributes(vector_len, /* vex_w */ false,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7985   attributes.set_is_evex_instruction();
 7986   attributes.set_embedded_opmask_register_specifier(mask);
 7987   if (merge) {
 7988     attributes.reset_is_clear_context();
 7989   }
 7990   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 7991   emit_int16(0x44, (0xC0 | encode));
 7992 }
 7993 
 7994 void Assembler::evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 7995   assert(VM_Version::supports_avx512cd() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 7996   InstructionAttr attributes(vector_len, /* vex_w */ true,/* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 7997   attributes.set_is_evex_instruction();
 7998   attributes.set_embedded_opmask_register_specifier(mask);
 7999   if (merge) {
 8000     attributes.reset_is_clear_context();
 8001   }
 8002   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8003   emit_int16(0x44, (0xC0 | encode));
 8004 }
 8005 
 8006 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 8007   assert(VM_Version::supports_evex(), "requires EVEX support");
 8008   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8009   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8010   attributes.set_is_evex_instruction();
 8011   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8012   emit_int8(0x25);
 8013   emit_int8((unsigned char)(0xC0 | encode));
 8014   emit_int8(imm8);
 8015 }
 8016 
 8017 void Assembler::vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len) {
 8018   assert(VM_Version::supports_evex(), "requires EVEX support");
 8019   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8020   assert(dst != xnoreg, "sanity");
 8021   InstructionMark im(this);
 8022   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8023   attributes.set_is_evex_instruction();
 8024   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
 8025   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8026   emit_int8(0x25);
 8027   emit_operand(dst, src3);
 8028   emit_int8(imm8);
 8029 }
 8030 
 8031 void Assembler::vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len) {
 8032   assert(VM_Version::supports_evex(), "requires EVEX support");
 8033   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
 8034   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8035   attributes.set_is_evex_instruction();
 8036   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8037   emit_int8(0x25);
 8038   emit_int8((unsigned char)(0xC0 | encode));
 8039   emit_int8(imm8);
 8040 }
 8041 
 8042 void Assembler::evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8043   assert(VM_Version::supports_evex(), "");
 8044   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8045   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8046   attributes.set_is_evex_instruction();
 8047   attributes.set_embedded_opmask_register_specifier(mask);
 8048   if (merge) {
 8049     attributes.reset_is_clear_context();
 8050   }
 8051   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8052   emit_int16((unsigned char)0x88, (0xC0 | encode));
 8053 }
 8054 
 8055 void Assembler::evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8056   assert(VM_Version::supports_evex(), "");
 8057   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8058   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8059   attributes.set_is_evex_instruction();
 8060   attributes.set_embedded_opmask_register_specifier(mask);
 8061   if (merge) {
 8062     attributes.reset_is_clear_context();
 8063   }
 8064   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8065   emit_int16((unsigned char)0x88, (0xC0 | encode));
 8066 }
 8067 
 8068 void Assembler::evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8069   assert(VM_Version::supports_avx512_vbmi2(), "");
 8070   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8071   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8072   attributes.set_is_evex_instruction();
 8073   attributes.set_embedded_opmask_register_specifier(mask);
 8074   if (merge) {
 8075     attributes.reset_is_clear_context();
 8076   }
 8077   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8078   emit_int16(0x62, (0xC0 | encode));
 8079 }
 8080 
 8081 void Assembler::evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8082   assert(VM_Version::supports_avx512_vbmi2(), "");
 8083   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8084   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8085   attributes.set_is_evex_instruction();
 8086   attributes.set_embedded_opmask_register_specifier(mask);
 8087   if (merge) {
 8088     attributes.reset_is_clear_context();
 8089   }
 8090   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8091   emit_int16(0x62, (0xC0 | encode));
 8092 }
 8093 
 8094 void Assembler::evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8095   assert(VM_Version::supports_evex(), "");
 8096   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8097   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8098   attributes.set_is_evex_instruction();
 8099   attributes.set_embedded_opmask_register_specifier(mask);
 8100   if (merge) {
 8101     attributes.reset_is_clear_context();
 8102   }
 8103   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8104   emit_int16((unsigned char)0x89, (0xC0 | encode));
 8105 }
 8106 
 8107 void Assembler::evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
 8108   assert(VM_Version::supports_evex(), "");
 8109   assert(vector_len == AVX_512bit || VM_Version::supports_avx512vl(), "");
 8110   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8111   attributes.set_is_evex_instruction();
 8112   attributes.set_embedded_opmask_register_specifier(mask);
 8113   if (merge) {
 8114     attributes.reset_is_clear_context();
 8115   }
 8116   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8117   emit_int16((unsigned char)0x89, (0xC0 | encode));
 8118 }
 8119 
 8120 // vinserti forms
 8121 
 8122 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8123   assert(VM_Version::supports_avx2(), "");
 8124   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8125   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8126   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8127   // last byte:
 8128   // 0x00 - insert into lower 128 bits
 8129   // 0x01 - insert into upper 128 bits
 8130   emit_int24(0x38, (0xC0 | encode), imm8 & 0x01);
 8131 }
 8132 
 8133 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8134   assert(VM_Version::supports_avx2(), "");
 8135   assert(dst != xnoreg, "sanity");
 8136   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8137   InstructionMark im(this);
 8138   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8139   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);

 8143   // 0x00 - insert into lower 128 bits
 8144   // 0x01 - insert into upper 128 bits
 8145   emit_int8(imm8 & 0x01);
 8146 }
 8147 
 8148 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8149   assert(VM_Version::supports_evex(), "");
 8150   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8151   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8152   attributes.set_is_evex_instruction();
 8153   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8154   // imm8:
 8155   // 0x00 - insert into q0 128 bits (0..127)
 8156   // 0x01 - insert into q1 128 bits (128..255)
 8157   // 0x02 - insert into q2 128 bits (256..383)
 8158   // 0x03 - insert into q3 128 bits (384..511)
 8159   emit_int24(0x38, (0xC0 | encode), imm8 & 0x03);
 8160 }
 8161 
 8162 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8163   assert(VM_Version::supports_evex(), "");
 8164   assert(dst != xnoreg, "sanity");
 8165   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8166   InstructionMark im(this);
 8167   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8168   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8169   attributes.set_is_evex_instruction();
 8170   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8171   emit_int8(0x18);
 8172   emit_operand(dst, src);
 8173   // 0x00 - insert into q0 128 bits (0..127)
 8174   // 0x01 - insert into q1 128 bits (128..255)
 8175   // 0x02 - insert into q2 128 bits (256..383)
 8176   // 0x03 - insert into q3 128 bits (384..511)
 8177   emit_int8(imm8 & 0x03);
 8178 }
 8179 
 8180 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8181   assert(VM_Version::supports_evex(), "");
 8182   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8183   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);

 8202   // 0x01 - insert into upper 128 bits
 8203   emit_int24(0x18, (0xC0 | encode), imm8 & 0x01);
 8204 }
 8205 
 8206 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8207   assert(VM_Version::supports_avx(), "");
 8208   assert(dst != xnoreg, "sanity");
 8209   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8210   InstructionMark im(this);
 8211   InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8212   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8213   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8214   emit_int8(0x18);
 8215   emit_operand(dst, src);
 8216   // 0x00 - insert into lower 128 bits
 8217   // 0x01 - insert into upper 128 bits
 8218   emit_int8(imm8 & 0x01);
 8219 }
 8220 
 8221 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8222   assert(VM_Version::supports_evex(), "");
 8223   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8224   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8225   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8226   // imm8:
 8227   // 0x00 - insert into q0 128 bits (0..127)
 8228   // 0x01 - insert into q1 128 bits (128..255)
 8229   // 0x02 - insert into q0 128 bits (256..383)
 8230   // 0x03 - insert into q1 128 bits (384..512)
 8231   emit_int24(0x18, (0xC0 | encode), imm8 & 0x03);
 8232 }
 8233 
 8234 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
 8235   assert(VM_Version::supports_evex(), "");
 8236   assert(dst != xnoreg, "sanity");
 8237   assert(imm8 <= 0x03, "imm8: %u", imm8);
 8238   InstructionMark im(this);
 8239   InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8240   attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
 8241   vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
 8242   emit_int8(0x18);
 8243   emit_operand(dst, src);
 8244   // 0x00 - insert into q0 128 bits (0..127)
 8245   // 0x01 - insert into q1 128 bits (128..255)
 8246   // 0x02 - insert into q0 128 bits (256..383)
 8247   // 0x03 - insert into q1 128 bits (384..512)
 8248   emit_int8(imm8 & 0x03);
 8249 }
 8250 
 8251 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
 8252   assert(VM_Version::supports_evex(), "");
 8253   assert(imm8 <= 0x01, "imm8: %u", imm8);
 8254   InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8255   attributes.set_is_evex_instruction();

 8516 
 8517 void Assembler::vpbroadcastw(XMMRegister dst, Address src, int vector_len) {
 8518   assert(VM_Version::supports_avx2(), "");
 8519   assert(dst != xnoreg, "sanity");
 8520   InstructionMark im(this);
 8521   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8522   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
 8523   // swap src<->dst for encoding
 8524   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
 8525   emit_int8(0x79);
 8526   emit_operand(dst, src);
 8527 }
 8528 
 8529 void Assembler::vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8530   assert(UseAVX > 0, "requires some form of AVX");
 8531   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
 8532   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8533   emit_int16((unsigned char)0xF6, (0xC0 | encode));
 8534 }
 8535 
 8536 void Assembler::vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8537   assert(UseAVX > 0, "requires some form of AVX");
 8538   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8539   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8540   emit_int16(0x69, (0xC0 | encode));
 8541 }
 8542 
 8543 void Assembler::vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8544   assert(UseAVX > 0, "requires some form of AVX");
 8545   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8546   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8547   emit_int16(0x61, (0xC0 | encode));
 8548 }
 8549 
 8550 void Assembler::vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8551   assert(UseAVX > 0, "requires some form of AVX");
 8552   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8553   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8554   emit_int16(0x6A, (0xC0 | encode));
 8555 }
 8556 
 8557 void Assembler::vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
 8558   assert(UseAVX > 0, "requires some form of AVX");
 8559   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
 8560   int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
 8561   emit_int16(0x62, (0xC0 | encode));
 8562 }
 8563 
 8564 // xmm/mem sourced byte/word/dword/qword replicate
 8565 void Assembler::evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
 8566   assert(VM_Version::supports_avx512bw() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
 8567   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false,/* uses_vl */ true);
 8568   attributes.set_is_evex_instruction();
 8569   attributes.set_embedded_opmask_register_specifier(mask);

10046 }
10047 
10048 void Assembler::evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len) {
10049   assert(VM_Version::supports_evex(), "requires EVEX support");
10050   assert(vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl(), "requires VL support");
10051   assert(dst != xnoreg, "sanity");
10052   InstructionMark im(this);
10053   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
10054   attributes.set_is_evex_instruction();
10055   attributes.set_embedded_opmask_register_specifier(mask);
10056   attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
10057   if (merge) {
10058     attributes.reset_is_clear_context();
10059   }
10060   vex_prefix(src3, src2->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10061   emit_int8(0x25);
10062   emit_operand(dst, src3);
10063   emit_int8(imm8);
10064 }
10065 
10066 void Assembler::vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len) {
10067   assert(VM_Version::supports_gfni(), "requires GFNI support");
10068   assert(VM_Version::supports_sse(), "");
10069   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10070   int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src3->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
10071   emit_int24((unsigned char)0xCE, (unsigned char)(0xC0 | encode), imm8);
10072 }
10073 
10074 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
10075 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
10076   assert(UseAVX >= 2, "");
10077   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10078   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10079   emit_int16(0x58, (0xC0 | encode));
10080 }
10081 
10082 void Assembler::vpbroadcastd(XMMRegister dst, Address src, int vector_len) {
10083   assert(VM_Version::supports_avx2(), "");
10084   assert(dst != xnoreg, "sanity");
10085   InstructionMark im(this);
10086   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
10087   attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
10088   // swap src<->dst for encoding
10089   vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
10090   emit_int8(0x58);
10091   emit_operand(dst, src);
10092 }
10093 

11747   attributes.set_is_evex_instruction();
11748   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11749   emit_int16(0x38, (0xC0 | encode));
11750 }
11751 
11752 void Assembler::evpmovm2w(XMMRegister dst, KRegister src, int vector_len) {
11753   assert(VM_Version::supports_avx512vlbw(), "");
11754   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11755   attributes.set_is_evex_instruction();
11756   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11757   emit_int16(0x28, (0xC0 | encode));
11758 }
11759 
11760 void Assembler::evpmovm2b(XMMRegister dst, KRegister src, int vector_len) {
11761   assert(VM_Version::supports_avx512vlbw(), "");
11762   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
11763   attributes.set_is_evex_instruction();
11764   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
11765   emit_int16(0x28, (0xC0 | encode));
11766 }
11767 
11768 void Assembler::evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11769   assert(VM_Version::supports_avx512_vbmi2() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11770   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11771   attributes.set_embedded_opmask_register_specifier(mask);
11772   attributes.set_is_evex_instruction();
11773   if (merge) {
11774     attributes.reset_is_clear_context();
11775   }
11776   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11777   emit_int16((unsigned char)0x63, (0xC0 | encode));
11778 }
11779 
11780 void Assembler::evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11781   assert(VM_Version::supports_avx512_vbmi2() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11782   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11783   attributes.set_embedded_opmask_register_specifier(mask);
11784   attributes.set_is_evex_instruction();
11785   if (merge) {
11786     attributes.reset_is_clear_context();
11787   }
11788   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11789   emit_int16((unsigned char)0x63, (0xC0 | encode));
11790 }
11791 
11792 void Assembler::evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11793   assert(VM_Version::supports_evex() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11794   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11795   attributes.set_embedded_opmask_register_specifier(mask);
11796   attributes.set_is_evex_instruction();
11797   if (merge) {
11798     attributes.reset_is_clear_context();
11799   }
11800   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11801   emit_int16((unsigned char)0x8B, (0xC0 | encode));
11802 }
11803 
11804 void Assembler::evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11805   assert(VM_Version::supports_evex() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11806   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11807   attributes.set_embedded_opmask_register_specifier(mask);
11808   attributes.set_is_evex_instruction();
11809   if (merge) {
11810     attributes.reset_is_clear_context();
11811   }
11812   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11813   emit_int16((unsigned char)0x8B, (0xC0 | encode));
11814 }
11815 
11816 void Assembler::evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11817   assert(VM_Version::supports_evex() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11818   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11819   attributes.set_embedded_opmask_register_specifier(mask);
11820   attributes.set_is_evex_instruction();
11821   if (merge) {
11822     attributes.reset_is_clear_context();
11823   }
11824   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11825   emit_int16((unsigned char)0x8A, (0xC0 | encode));
11826 }
11827 
11828 void Assembler::evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
11829   assert(VM_Version::supports_evex() && (vector_len == AVX_512bit || VM_Version::supports_avx512vl()), "");
11830   InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
11831   attributes.set_embedded_opmask_register_specifier(mask);
11832   attributes.set_is_evex_instruction();
11833   if (merge) {
11834     attributes.reset_is_clear_context();
11835   }
11836   int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
11837   emit_int16((unsigned char)0x8A, (0xC0 | encode));
11838 }
11839 
11840 #ifndef _LP64
11841 
11842 void Assembler::incl(Register dst) {
11843   // Don't use it directly. Use MacroAssembler::incrementl() instead.
11844   emit_int8(0x40 | dst->encoding());
11845 }
11846 
11847 void Assembler::lea(Register dst, Address src) {
11848   leal(dst, src);
11849 }
11850 
11851 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
11852   InstructionMark im(this);
11853   emit_int8((unsigned char)0xC7);
11854   emit_operand(rax, dst);
11855   emit_data((int)imm32, rspec, 0);
11856 }
11857 
11858 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
11859   InstructionMark im(this);
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