1 /* 2 * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #ifndef CPU_X86_ASSEMBLER_X86_HPP 26 #define CPU_X86_ASSEMBLER_X86_HPP 27 28 #include "asm/register.hpp" 29 #include "utilities/powerOfTwo.hpp" 30 31 // Contains all the definitions needed for x86 assembly code generation. 32 33 // Calling convention 34 class Argument { 35 public: 36 enum { 37 #ifdef _LP64 38 #ifdef _WIN64 39 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...) 40 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... ) 41 n_int_register_returns_c = 1, // rax 42 n_float_register_returns_c = 1, // xmm0 43 #else 44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...) 45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... ) 46 n_int_register_returns_c = 2, // rax, rdx 47 n_float_register_returns_c = 2, // xmm0, xmm1 48 #endif // _WIN64 49 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ... 50 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ... 51 #else 52 n_register_parameters = 0 // 0 registers used to pass arguments 53 #endif // _LP64 54 }; 55 }; 56 57 58 #ifdef _LP64 59 // Symbolically name the register arguments used by the c calling convention. 60 // Windows is different from linux/solaris. So much for standards... 61 62 #ifdef _WIN64 63 64 REGISTER_DECLARATION(Register, c_rarg0, rcx); 65 REGISTER_DECLARATION(Register, c_rarg1, rdx); 66 REGISTER_DECLARATION(Register, c_rarg2, r8); 67 REGISTER_DECLARATION(Register, c_rarg3, r9); 68 69 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 70 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 71 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 72 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 73 74 #else 75 76 REGISTER_DECLARATION(Register, c_rarg0, rdi); 77 REGISTER_DECLARATION(Register, c_rarg1, rsi); 78 REGISTER_DECLARATION(Register, c_rarg2, rdx); 79 REGISTER_DECLARATION(Register, c_rarg3, rcx); 80 REGISTER_DECLARATION(Register, c_rarg4, r8); 81 REGISTER_DECLARATION(Register, c_rarg5, r9); 82 83 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0); 84 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1); 85 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2); 86 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3); 87 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4); 88 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5); 89 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6); 90 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7); 91 92 #endif // _WIN64 93 94 // Symbolically name the register arguments used by the Java calling convention. 95 // We have control over the convention for java so we can do what we please. 96 // What pleases us is to offset the java calling convention so that when 97 // we call a suitable jni method the arguments are lined up and we don't 98 // have to do little shuffling. A suitable jni method is non-static and a 99 // small number of arguments (two fewer args on windows) 100 // 101 // |-------------------------------------------------------| 102 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 | 103 // |-------------------------------------------------------| 104 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg) 105 // | rdi rsi rdx rcx r8 r9 | solaris/linux 106 // |-------------------------------------------------------| 107 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 | 108 // |-------------------------------------------------------| 109 110 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1); 111 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2); 112 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3); 113 // Windows runs out of register args here 114 #ifdef _WIN64 115 REGISTER_DECLARATION(Register, j_rarg3, rdi); 116 REGISTER_DECLARATION(Register, j_rarg4, rsi); 117 #else 118 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4); 119 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5); 120 #endif /* _WIN64 */ 121 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0); 122 123 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0); 124 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1); 125 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2); 126 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3); 127 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4); 128 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5); 129 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6); 130 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7); 131 132 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile 133 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile 134 135 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved 136 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved 137 138 #else 139 // rscratch1 will appear in 32bit code that is dead but of course must compile 140 // Using noreg ensures if the dead code is incorrectly live and executed it 141 // will cause an assertion failure 142 #define rscratch1 noreg 143 #define rscratch2 noreg 144 145 #endif // _LP64 146 147 // JSR 292 148 // On x86, the SP does not have to be saved when invoking method handle intrinsics 149 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg. 150 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg); 151 152 // Address is an abstraction used to represent a memory location 153 // using any of the amd64 addressing modes with one object. 154 // 155 // Note: A register location is represented via a Register, not 156 // via an address for efficiency & simplicity reasons. 157 158 class ArrayAddress; 159 160 class Address { 161 public: 162 enum ScaleFactor { 163 no_scale = -1, 164 times_1 = 0, 165 times_2 = 1, 166 times_4 = 2, 167 times_8 = 3, 168 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4) 169 }; 170 static ScaleFactor times(int size) { 171 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size"); 172 if (size == 8) return times_8; 173 if (size == 4) return times_4; 174 if (size == 2) return times_2; 175 return times_1; 176 } 177 static int scale_size(ScaleFactor scale) { 178 assert(scale != no_scale, ""); 179 assert(((1 << (int)times_1) == 1 && 180 (1 << (int)times_2) == 2 && 181 (1 << (int)times_4) == 4 && 182 (1 << (int)times_8) == 8), ""); 183 return (1 << (int)scale); 184 } 185 186 private: 187 Register _base; 188 Register _index; 189 XMMRegister _xmmindex; 190 ScaleFactor _scale; 191 int _disp; 192 bool _isxmmindex; 193 RelocationHolder _rspec; 194 195 // Easily misused constructors make them private 196 // %%% can we make these go away? 197 NOT_LP64(Address(address loc, RelocationHolder spec);) 198 Address(int disp, address loc, relocInfo::relocType rtype); 199 Address(int disp, address loc, RelocationHolder spec); 200 201 public: 202 203 int disp() { return _disp; } 204 // creation 205 Address() 206 : _base(noreg), 207 _index(noreg), 208 _xmmindex(xnoreg), 209 _scale(no_scale), 210 _disp(0), 211 _isxmmindex(false){ 212 } 213 214 // No default displacement otherwise Register can be implicitly 215 // converted to 0(Register) which is quite a different animal. 216 217 Address(Register base, int disp) 218 : _base(base), 219 _index(noreg), 220 _xmmindex(xnoreg), 221 _scale(no_scale), 222 _disp(disp), 223 _isxmmindex(false){ 224 } 225 226 Address(Register base, Register index, ScaleFactor scale, int disp = 0) 227 : _base (base), 228 _index(index), 229 _xmmindex(xnoreg), 230 _scale(scale), 231 _disp (disp), 232 _isxmmindex(false) { 233 assert(!index->is_valid() == (scale == Address::no_scale), 234 "inconsistent address"); 235 } 236 237 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0) 238 : _base (base), 239 _index(index.register_or_noreg()), 240 _xmmindex(xnoreg), 241 _scale(scale), 242 _disp (disp + (index.constant_or_zero() * scale_size(scale))), 243 _isxmmindex(false){ 244 if (!index.is_register()) scale = Address::no_scale; 245 assert(!_index->is_valid() == (scale == Address::no_scale), 246 "inconsistent address"); 247 } 248 249 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0) 250 : _base (base), 251 _index(noreg), 252 _xmmindex(index), 253 _scale(scale), 254 _disp(disp), 255 _isxmmindex(true) { 256 assert(!index->is_valid() == (scale == Address::no_scale), 257 "inconsistent address"); 258 } 259 260 // The following overloads are used in connection with the 261 // ByteSize type (see sizes.hpp). They simplify the use of 262 // ByteSize'd arguments in assembly code. 263 264 Address(Register base, ByteSize disp) 265 : Address(base, in_bytes(disp)) {} 266 267 Address(Register base, Register index, ScaleFactor scale, ByteSize disp) 268 : Address(base, index, scale, in_bytes(disp)) {} 269 270 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp) 271 : Address(base, index, scale, in_bytes(disp)) {} 272 273 Address plus_disp(int disp) const { 274 Address a = (*this); 275 a._disp += disp; 276 return a; 277 } 278 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const { 279 Address a = (*this); 280 a._disp += disp.constant_or_zero() * scale_size(scale); 281 if (disp.is_register()) { 282 assert(!a.index()->is_valid(), "competing indexes"); 283 a._index = disp.as_register(); 284 a._scale = scale; 285 } 286 return a; 287 } 288 bool is_same_address(Address a) const { 289 // disregard _rspec 290 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale; 291 } 292 293 // accessors 294 bool uses(Register reg) const { return _base == reg || _index == reg; } 295 Register base() const { return _base; } 296 Register index() const { return _index; } 297 XMMRegister xmmindex() const { return _xmmindex; } 298 ScaleFactor scale() const { return _scale; } 299 int disp() const { return _disp; } 300 bool isxmmindex() const { return _isxmmindex; } 301 302 // Convert the raw encoding form into the form expected by the constructor for 303 // Address. An index of 4 (rsp) corresponds to having no index, so convert 304 // that to noreg for the Address constructor. 305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc); 306 307 static Address make_array(ArrayAddress); 308 309 private: 310 bool base_needs_rex() const { 311 return _base->is_valid() && _base->encoding() >= 8; 312 } 313 314 bool index_needs_rex() const { 315 return _index->is_valid() &&_index->encoding() >= 8; 316 } 317 318 bool xmmindex_needs_rex() const { 319 return _xmmindex->is_valid() && _xmmindex->encoding() >= 8; 320 } 321 322 relocInfo::relocType reloc() const { return _rspec.type(); } 323 324 friend class Assembler; 325 friend class MacroAssembler; 326 friend class LIR_Assembler; // base/index/scale/disp 327 }; 328 329 // 330 // AddressLiteral has been split out from Address because operands of this type 331 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out 332 // the few instructions that need to deal with address literals are unique and the 333 // MacroAssembler does not have to implement every instruction in the Assembler 334 // in order to search for address literals that may need special handling depending 335 // on the instruction and the platform. As small step on the way to merging i486/amd64 336 // directories. 337 // 338 class AddressLiteral { 339 friend class ArrayAddress; 340 RelocationHolder _rspec; 341 // Typically we use AddressLiterals we want to use their rval 342 // However in some situations we want the lval (effect address) of the item. 343 // We provide a special factory for making those lvals. 344 bool _is_lval; 345 346 // If the target is far we'll need to load the ea of this to 347 // a register to reach it. Otherwise if near we can do rip 348 // relative addressing. 349 350 address _target; 351 352 protected: 353 // creation 354 AddressLiteral() 355 : _is_lval(false), 356 _target(NULL) 357 {} 358 359 public: 360 361 362 AddressLiteral(address target, relocInfo::relocType rtype); 363 364 AddressLiteral(address target, RelocationHolder const& rspec) 365 : _rspec(rspec), 366 _is_lval(false), 367 _target(target) 368 {} 369 370 AddressLiteral addr() { 371 AddressLiteral ret = *this; 372 ret._is_lval = true; 373 return ret; 374 } 375 376 377 private: 378 379 address target() { return _target; } 380 bool is_lval() const { return _is_lval; } 381 382 relocInfo::relocType reloc() const { return _rspec.type(); } 383 const RelocationHolder& rspec() const { return _rspec; } 384 385 friend class Assembler; 386 friend class MacroAssembler; 387 friend class Address; 388 friend class LIR_Assembler; 389 }; 390 391 // Convenience classes 392 class RuntimeAddress: public AddressLiteral { 393 394 public: 395 396 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {} 397 398 }; 399 400 class ExternalAddress: public AddressLiteral { 401 private: 402 static relocInfo::relocType reloc_for_target(address target) { 403 // Sometimes ExternalAddress is used for values which aren't 404 // exactly addresses, like the card table base. 405 // external_word_type can't be used for values in the first page 406 // so just skip the reloc in that case. 407 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none; 408 } 409 410 public: 411 412 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {} 413 414 }; 415 416 class InternalAddress: public AddressLiteral { 417 418 public: 419 420 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {} 421 422 }; 423 424 // x86 can do array addressing as a single operation since disp can be an absolute 425 // address amd64 can't. We create a class that expresses the concept but does extra 426 // magic on amd64 to get the final result 427 428 class ArrayAddress { 429 private: 430 431 AddressLiteral _base; 432 Address _index; 433 434 public: 435 436 ArrayAddress() {}; 437 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {}; 438 AddressLiteral base() { return _base; } 439 Address index() { return _index; } 440 441 }; 442 443 class InstructionAttr; 444 445 // 64-bit reflect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes 446 // See fxsave and xsave(EVEX enabled) documentation for layout 447 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize); 448 449 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction 450 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write 451 // is what you get. The Assembler is generating code into a CodeBuffer. 452 453 class Assembler : public AbstractAssembler { 454 friend class AbstractAssembler; // for the non-virtual hack 455 friend class LIR_Assembler; // as_Address() 456 friend class StubGenerator; 457 458 public: 459 enum Condition { // The x86 condition codes used for conditional jumps/moves. 460 zero = 0x4, 461 notZero = 0x5, 462 equal = 0x4, 463 notEqual = 0x5, 464 less = 0xc, 465 lessEqual = 0xe, 466 greater = 0xf, 467 greaterEqual = 0xd, 468 below = 0x2, 469 belowEqual = 0x6, 470 above = 0x7, 471 aboveEqual = 0x3, 472 overflow = 0x0, 473 noOverflow = 0x1, 474 carrySet = 0x2, 475 carryClear = 0x3, 476 negative = 0x8, 477 positive = 0x9, 478 parity = 0xa, 479 noParity = 0xb 480 }; 481 482 enum Prefix { 483 // segment overrides 484 CS_segment = 0x2e, 485 SS_segment = 0x36, 486 DS_segment = 0x3e, 487 ES_segment = 0x26, 488 FS_segment = 0x64, 489 GS_segment = 0x65, 490 491 REX = 0x40, 492 493 REX_B = 0x41, 494 REX_X = 0x42, 495 REX_XB = 0x43, 496 REX_R = 0x44, 497 REX_RB = 0x45, 498 REX_RX = 0x46, 499 REX_RXB = 0x47, 500 501 REX_W = 0x48, 502 503 REX_WB = 0x49, 504 REX_WX = 0x4A, 505 REX_WXB = 0x4B, 506 REX_WR = 0x4C, 507 REX_WRB = 0x4D, 508 REX_WRX = 0x4E, 509 REX_WRXB = 0x4F, 510 511 VEX_3bytes = 0xC4, 512 VEX_2bytes = 0xC5, 513 EVEX_4bytes = 0x62, 514 Prefix_EMPTY = 0x0 515 }; 516 517 enum VexPrefix { 518 VEX_B = 0x20, 519 VEX_X = 0x40, 520 VEX_R = 0x80, 521 VEX_W = 0x80 522 }; 523 524 enum ExexPrefix { 525 EVEX_F = 0x04, 526 EVEX_V = 0x08, 527 EVEX_Rb = 0x10, 528 EVEX_X = 0x40, 529 EVEX_Z = 0x80 530 }; 531 532 enum VexSimdPrefix { 533 VEX_SIMD_NONE = 0x0, 534 VEX_SIMD_66 = 0x1, 535 VEX_SIMD_F3 = 0x2, 536 VEX_SIMD_F2 = 0x3 537 }; 538 539 enum VexOpcode { 540 VEX_OPCODE_NONE = 0x0, 541 VEX_OPCODE_0F = 0x1, 542 VEX_OPCODE_0F_38 = 0x2, 543 VEX_OPCODE_0F_3A = 0x3, 544 VEX_OPCODE_MASK = 0x1F 545 }; 546 547 enum AvxVectorLen { 548 AVX_128bit = 0x0, 549 AVX_256bit = 0x1, 550 AVX_512bit = 0x2, 551 AVX_NoVec = 0x4 552 }; 553 554 enum EvexTupleType { 555 EVEX_FV = 0, 556 EVEX_HV = 4, 557 EVEX_FVM = 6, 558 EVEX_T1S = 7, 559 EVEX_T1F = 11, 560 EVEX_T2 = 13, 561 EVEX_T4 = 15, 562 EVEX_T8 = 17, 563 EVEX_HVM = 18, 564 EVEX_QVM = 19, 565 EVEX_OVM = 20, 566 EVEX_M128 = 21, 567 EVEX_DUP = 22, 568 EVEX_ETUP = 23 569 }; 570 571 enum EvexInputSizeInBits { 572 EVEX_8bit = 0, 573 EVEX_16bit = 1, 574 EVEX_32bit = 2, 575 EVEX_64bit = 3, 576 EVEX_NObit = 4 577 }; 578 579 enum WhichOperand { 580 // input to locate_operand, and format code for relocations 581 imm_operand = 0, // embedded 32-bit|64-bit immediate operand 582 disp32_operand = 1, // embedded 32-bit displacement or address 583 call32_operand = 2, // embedded 32-bit self-relative displacement 584 #ifndef _LP64 585 _WhichOperand_limit = 3 586 #else 587 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop 588 _WhichOperand_limit = 4 589 #endif 590 }; 591 592 // Comparison predicates for integral types & FP types when using SSE 593 enum ComparisonPredicate { 594 eq = 0, 595 lt = 1, 596 le = 2, 597 _false = 3, 598 neq = 4, 599 nlt = 5, 600 nle = 6, 601 _true = 7 602 }; 603 604 // Comparison predicates for FP types when using AVX 605 // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true. 606 // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN. 607 enum ComparisonPredicateFP { 608 EQ_OQ = 0, 609 LT_OS = 1, 610 LE_OS = 2, 611 UNORD_Q = 3, 612 NEQ_UQ = 4, 613 NLT_US = 5, 614 NLE_US = 6, 615 ORD_Q = 7, 616 EQ_UQ = 8, 617 NGE_US = 9, 618 NGT_US = 0xA, 619 FALSE_OQ = 0XB, 620 NEQ_OQ = 0xC, 621 GE_OS = 0xD, 622 GT_OS = 0xE, 623 TRUE_UQ = 0xF, 624 EQ_OS = 0x10, 625 LT_OQ = 0x11, 626 LE_OQ = 0x12, 627 UNORD_S = 0x13, 628 NEQ_US = 0x14, 629 NLT_UQ = 0x15, 630 NLE_UQ = 0x16, 631 ORD_S = 0x17, 632 EQ_US = 0x18, 633 NGE_UQ = 0x19, 634 NGT_UQ = 0x1A, 635 FALSE_OS = 0x1B, 636 NEQ_OS = 0x1C, 637 GE_OQ = 0x1D, 638 GT_OQ = 0x1E, 639 TRUE_US =0x1F 640 }; 641 642 enum Width { 643 B = 0, 644 W = 1, 645 D = 2, 646 Q = 3 647 }; 648 649 //---< calculate length of instruction >--- 650 // As instruction size can't be found out easily on x86/x64, 651 // we just use '4' for len and maxlen. 652 // instruction must start at passed address 653 static unsigned int instr_len(unsigned char *instr) { return 4; } 654 655 //---< longest instructions >--- 656 // Max instruction length is not specified in architecture documentation. 657 // We could use a "safe enough" estimate (15), but just default to 658 // instruction length guess from above. 659 static unsigned int instr_maxlen() { return 4; } 660 661 // NOTE: The general philopsophy of the declarations here is that 64bit versions 662 // of instructions are freely declared without the need for wrapping them an ifdef. 663 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.) 664 // In the .cpp file the implementations are wrapped so that they are dropped out 665 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL 666 // to the size it was prior to merging up the 32bit and 64bit assemblers. 667 // 668 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction 669 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down. 670 671 private: 672 673 bool _legacy_mode_bw; 674 bool _legacy_mode_dq; 675 bool _legacy_mode_vl; 676 bool _legacy_mode_vlbw; 677 NOT_LP64(bool _is_managed;) 678 679 class InstructionAttr *_attributes; 680 681 // 64bit prefixes 682 void prefix(Register reg); 683 void prefix(Register dst, Register src, Prefix p); 684 void prefix(Register dst, Address adr, Prefix p); 685 686 void prefix(Address adr); 687 void prefix(Address adr, Register reg, bool byteinst = false); 688 void prefix(Address adr, XMMRegister reg); 689 690 int prefix_and_encode(int reg_enc, bool byteinst = false); 691 int prefix_and_encode(int dst_enc, int src_enc) { 692 return prefix_and_encode(dst_enc, false, src_enc, false); 693 } 694 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte); 695 696 // Some prefixq variants always emit exactly one prefix byte, so besides a 697 // prefix-emitting method we provide a method to get the prefix byte to emit, 698 // which can then be folded into a byte stream. 699 int8_t get_prefixq(Address adr); 700 int8_t get_prefixq(Address adr, Register reg); 701 702 void prefixq(Address adr); 703 void prefixq(Address adr, Register reg); 704 void prefixq(Address adr, XMMRegister reg); 705 706 int prefixq_and_encode(int reg_enc); 707 int prefixq_and_encode(int dst_enc, int src_enc); 708 709 void rex_prefix(Address adr, XMMRegister xreg, 710 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 711 int rex_prefix_and_encode(int dst_enc, int src_enc, 712 VexSimdPrefix pre, VexOpcode opc, bool rex_w); 713 714 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc); 715 716 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, 717 int nds_enc, VexSimdPrefix pre, VexOpcode opc); 718 719 void vex_prefix(Address adr, int nds_enc, int xreg_enc, 720 VexSimdPrefix pre, VexOpcode opc, 721 InstructionAttr *attributes); 722 723 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, 724 VexSimdPrefix pre, VexOpcode opc, 725 InstructionAttr *attributes); 726 727 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre, 728 VexOpcode opc, InstructionAttr *attributes); 729 730 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre, 731 VexOpcode opc, InstructionAttr *attributes); 732 733 // Helper functions for groups of instructions 734 void emit_arith_b(int op1, int op2, Register dst, int imm8); 735 736 void emit_arith(int op1, int op2, Register dst, int32_t imm32); 737 // Force generation of a 4 byte immediate value even if it fits into 8bit 738 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32); 739 void emit_arith(int op1, int op2, Register dst, Register src); 740 741 bool emit_compressed_disp_byte(int &disp); 742 743 void emit_modrm(int mod, int dst_enc, int src_enc); 744 void emit_modrm_disp8(int mod, int dst_enc, int src_enc, 745 int disp); 746 void emit_modrm_sib(int mod, int dst_enc, int src_enc, 747 Address::ScaleFactor scale, int index_enc, int base_enc); 748 void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc, 749 Address::ScaleFactor scale, int index_enc, int base_enc, 750 int disp); 751 752 void emit_operand_helper(int reg_enc, 753 int base_enc, int index_enc, Address::ScaleFactor scale, 754 int disp, 755 RelocationHolder const& rspec, 756 int rip_relative_correction = 0); 757 758 void emit_operand(Register reg, 759 Register base, Register index, Address::ScaleFactor scale, 760 int disp, 761 RelocationHolder const& rspec, 762 int rip_relative_correction = 0); 763 764 void emit_operand(Register reg, 765 Register base, XMMRegister index, Address::ScaleFactor scale, 766 int disp, 767 RelocationHolder const& rspec); 768 769 void emit_operand(XMMRegister xreg, 770 Register base, XMMRegister xindex, Address::ScaleFactor scale, 771 int disp, 772 RelocationHolder const& rspec); 773 774 void emit_operand(Register reg, Address adr, 775 int rip_relative_correction = 0); 776 777 void emit_operand(XMMRegister reg, 778 Register base, Register index, Address::ScaleFactor scale, 779 int disp, 780 RelocationHolder const& rspec); 781 782 void emit_operand(XMMRegister reg, Address adr); 783 784 // Immediate-to-memory forms 785 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32); 786 787 protected: 788 #ifdef ASSERT 789 void check_relocation(RelocationHolder const& rspec, int format); 790 #endif 791 792 void emit_data(jint data, relocInfo::relocType rtype, int format); 793 void emit_data(jint data, RelocationHolder const& rspec, int format); 794 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0); 795 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0); 796 797 bool reachable(AddressLiteral adr) NOT_LP64({ return true;}); 798 799 // These are all easily abused and hence protected 800 801 // 32BIT ONLY SECTION 802 #ifndef _LP64 803 // Make these disappear in 64bit mode since they would never be correct 804 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 805 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 806 807 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 808 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 809 810 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY 811 #else 812 // 64BIT ONLY SECTION 813 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY 814 815 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec); 816 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec); 817 818 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec); 819 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec); 820 #endif // _LP64 821 822 // These are unique in that we are ensured by the caller that the 32bit 823 // relative in these instructions will always be able to reach the potentially 824 // 64bit address described by entry. Since they can take a 64bit address they 825 // don't have the 32 suffix like the other instructions in this class. 826 827 void call_literal(address entry, RelocationHolder const& rspec); 828 void jmp_literal(address entry, RelocationHolder const& rspec); 829 830 // Avoid using directly section 831 // Instructions in this section are actually usable by anyone without danger 832 // of failure but have performance issues that are addressed my enhanced 833 // instructions which will do the proper thing base on the particular cpu. 834 // We protect them because we don't trust you... 835 836 // Don't use next inc() and dec() methods directly. INC & DEC instructions 837 // could cause a partial flag stall since they don't set CF flag. 838 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods 839 // which call inc() & dec() or add() & sub() in accordance with 840 // the product flag UseIncDec value. 841 842 void decl(Register dst); 843 void decl(Address dst); 844 void decq(Address dst); 845 846 void incl(Register dst); 847 void incl(Address dst); 848 void incq(Register dst); 849 void incq(Address dst); 850 851 // New cpus require use of movsd and movss to avoid partial register stall 852 // when loading from memory. But for old Opteron use movlpd instead of movsd. 853 // The selection is done in MacroAssembler::movdbl() and movflt(). 854 855 // Move Scalar Single-Precision Floating-Point Values 856 void movss(XMMRegister dst, Address src); 857 void movss(XMMRegister dst, XMMRegister src); 858 void movss(Address dst, XMMRegister src); 859 860 // Move Scalar Double-Precision Floating-Point Values 861 void movsd(XMMRegister dst, Address src); 862 void movsd(XMMRegister dst, XMMRegister src); 863 void movsd(Address dst, XMMRegister src); 864 void movlpd(XMMRegister dst, Address src); 865 866 // New cpus require use of movaps and movapd to avoid partial register stall 867 // when moving between registers. 868 void movaps(XMMRegister dst, XMMRegister src); 869 void movapd(XMMRegister dst, XMMRegister src); 870 871 // End avoid using directly 872 873 874 // Instruction prefixes 875 void prefix(Prefix p); 876 877 public: 878 879 // Creation 880 Assembler(CodeBuffer* code) : AbstractAssembler(code) { 881 init_attributes(); 882 } 883 884 // Decoding 885 static address locate_operand(address inst, WhichOperand which); 886 static address locate_next_instruction(address inst); 887 888 // Utilities 889 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len, 890 int cur_tuple_type, int in_size_in_bits, int cur_encoding); 891 892 // Generic instructions 893 // Does 32bit or 64bit as needed for the platform. In some sense these 894 // belong in macro assembler but there is no need for both varieties to exist 895 896 void init_attributes(void); 897 898 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; } 899 void clear_attributes(void) { _attributes = NULL; } 900 901 void set_managed(void) { NOT_LP64(_is_managed = true;) } 902 void clear_managed(void) { NOT_LP64(_is_managed = false;) } 903 bool is_managed(void) { 904 NOT_LP64(return _is_managed;) 905 LP64_ONLY(return false;) } 906 907 void lea(Register dst, Address src); 908 909 void mov(Register dst, Register src); 910 911 #ifdef _LP64 912 // support caching the result of some routines 913 914 // must be called before pusha(), popa(), vzeroupper() - checked with asserts 915 static void precompute_instructions(); 916 917 void pusha_uncached(); 918 void popa_uncached(); 919 #endif 920 void vzeroupper_uncached(); 921 void decq(Register dst); 922 923 void pusha(); 924 void popa(); 925 926 void pushf(); 927 void popf(); 928 929 void push(int32_t imm32); 930 931 void push(Register src); 932 933 void pop(Register dst); 934 935 // These are dummies to prevent surprise implicit conversions to Register 936 void push(void* v); 937 void pop(void* v); 938 939 // These do register sized moves/scans 940 void rep_mov(); 941 void rep_stos(); 942 void rep_stosb(); 943 void repne_scan(); 944 #ifdef _LP64 945 void repne_scanl(); 946 #endif 947 948 // Vanilla instructions in lexical order 949 950 void adcl(Address dst, int32_t imm32); 951 void adcl(Address dst, Register src); 952 void adcl(Register dst, int32_t imm32); 953 void adcl(Register dst, Address src); 954 void adcl(Register dst, Register src); 955 956 void adcq(Register dst, int32_t imm32); 957 void adcq(Register dst, Address src); 958 void adcq(Register dst, Register src); 959 960 void addb(Address dst, int imm8); 961 void addw(Register dst, Register src); 962 void addw(Address dst, int imm16); 963 964 void addl(Address dst, int32_t imm32); 965 void addl(Address dst, Register src); 966 void addl(Register dst, int32_t imm32); 967 void addl(Register dst, Address src); 968 void addl(Register dst, Register src); 969 970 void addq(Address dst, int32_t imm32); 971 void addq(Address dst, Register src); 972 void addq(Register dst, int32_t imm32); 973 void addq(Register dst, Address src); 974 void addq(Register dst, Register src); 975 976 #ifdef _LP64 977 //Add Unsigned Integers with Carry Flag 978 void adcxq(Register dst, Register src); 979 980 //Add Unsigned Integers with Overflow Flag 981 void adoxq(Register dst, Register src); 982 #endif 983 984 void addr_nop_4(); 985 void addr_nop_5(); 986 void addr_nop_7(); 987 void addr_nop_8(); 988 989 // Add Scalar Double-Precision Floating-Point Values 990 void addsd(XMMRegister dst, Address src); 991 void addsd(XMMRegister dst, XMMRegister src); 992 993 // Add Scalar Single-Precision Floating-Point Values 994 void addss(XMMRegister dst, Address src); 995 void addss(XMMRegister dst, XMMRegister src); 996 997 // AES instructions 998 void aesdec(XMMRegister dst, Address src); 999 void aesdec(XMMRegister dst, XMMRegister src); 1000 void aesdeclast(XMMRegister dst, Address src); 1001 void aesdeclast(XMMRegister dst, XMMRegister src); 1002 void aesenc(XMMRegister dst, Address src); 1003 void aesenc(XMMRegister dst, XMMRegister src); 1004 void aesenclast(XMMRegister dst, Address src); 1005 void aesenclast(XMMRegister dst, XMMRegister src); 1006 // Vector AES instructions 1007 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1008 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1009 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1010 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1011 1012 void andw(Register dst, Register src); 1013 void andb(Address dst, Register src); 1014 1015 void andl(Address dst, int32_t imm32); 1016 void andl(Register dst, int32_t imm32); 1017 void andl(Register dst, Address src); 1018 void andl(Register dst, Register src); 1019 void andl(Address dst, Register src); 1020 1021 void andq(Address dst, int32_t imm32); 1022 void andq(Register dst, int32_t imm32); 1023 void andq(Register dst, Address src); 1024 void andq(Register dst, Register src); 1025 void andq(Address dst, Register src); 1026 1027 // BMI instructions 1028 void andnl(Register dst, Register src1, Register src2); 1029 void andnl(Register dst, Register src1, Address src2); 1030 void andnq(Register dst, Register src1, Register src2); 1031 void andnq(Register dst, Register src1, Address src2); 1032 1033 void blsil(Register dst, Register src); 1034 void blsil(Register dst, Address src); 1035 void blsiq(Register dst, Register src); 1036 void blsiq(Register dst, Address src); 1037 1038 void blsmskl(Register dst, Register src); 1039 void blsmskl(Register dst, Address src); 1040 void blsmskq(Register dst, Register src); 1041 void blsmskq(Register dst, Address src); 1042 1043 void blsrl(Register dst, Register src); 1044 void blsrl(Register dst, Address src); 1045 void blsrq(Register dst, Register src); 1046 void blsrq(Register dst, Address src); 1047 1048 void bsfl(Register dst, Register src); 1049 void bsrl(Register dst, Register src); 1050 1051 #ifdef _LP64 1052 void bsfq(Register dst, Register src); 1053 void bsrq(Register dst, Register src); 1054 #endif 1055 1056 void bswapl(Register reg); 1057 1058 void bswapq(Register reg); 1059 1060 void call(Label& L, relocInfo::relocType rtype); 1061 void call(Register reg); // push pc; pc <- reg 1062 void call(Address adr); // push pc; pc <- adr 1063 1064 void cdql(); 1065 1066 void cdqq(); 1067 1068 void cld(); 1069 1070 void clflush(Address adr); 1071 void clflushopt(Address adr); 1072 void clwb(Address adr); 1073 1074 void cmovl(Condition cc, Register dst, Register src); 1075 void cmovl(Condition cc, Register dst, Address src); 1076 1077 void cmovq(Condition cc, Register dst, Register src); 1078 void cmovq(Condition cc, Register dst, Address src); 1079 1080 1081 void cmpb(Address dst, int imm8); 1082 1083 void cmpl(Address dst, int32_t imm32); 1084 void cmpl(Register dst, int32_t imm32); 1085 void cmpl(Register dst, Register src); 1086 void cmpl(Register dst, Address src); 1087 1088 void cmpq(Address dst, int32_t imm32); 1089 void cmpq(Address dst, Register src); 1090 void cmpq(Register dst, int32_t imm32); 1091 void cmpq(Register dst, Register src); 1092 void cmpq(Register dst, Address src); 1093 1094 // these are dummies used to catch attempting to convert NULL to Register 1095 void cmpl(Register dst, void* junk); // dummy 1096 void cmpq(Register dst, void* junk); // dummy 1097 1098 void cmpw(Address dst, int imm16); 1099 1100 void cmpxchg8 (Address adr); 1101 1102 void cmpxchgb(Register reg, Address adr); 1103 void cmpxchgl(Register reg, Address adr); 1104 1105 void cmpxchgq(Register reg, Address adr); 1106 void cmpxchgw(Register reg, Address adr); 1107 1108 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 1109 void comisd(XMMRegister dst, Address src); 1110 void comisd(XMMRegister dst, XMMRegister src); 1111 1112 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 1113 void comiss(XMMRegister dst, Address src); 1114 void comiss(XMMRegister dst, XMMRegister src); 1115 1116 // Identify processor type and features 1117 void cpuid(); 1118 1119 // CRC32C 1120 void crc32(Register crc, Register v, int8_t sizeInBytes); 1121 void crc32(Register crc, Address adr, int8_t sizeInBytes); 1122 1123 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value 1124 void cvtsd2ss(XMMRegister dst, XMMRegister src); 1125 void cvtsd2ss(XMMRegister dst, Address src); 1126 1127 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value 1128 void cvtsi2sdl(XMMRegister dst, Register src); 1129 void cvtsi2sdl(XMMRegister dst, Address src); 1130 void cvtsi2sdq(XMMRegister dst, Register src); 1131 void cvtsi2sdq(XMMRegister dst, Address src); 1132 1133 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value 1134 void cvtsi2ssl(XMMRegister dst, Register src); 1135 void cvtsi2ssl(XMMRegister dst, Address src); 1136 void cvtsi2ssq(XMMRegister dst, Register src); 1137 void cvtsi2ssq(XMMRegister dst, Address src); 1138 1139 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value 1140 void cvtdq2pd(XMMRegister dst, XMMRegister src); 1141 void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len); 1142 1143 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value 1144 void cvtdq2ps(XMMRegister dst, XMMRegister src); 1145 void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len); 1146 1147 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value 1148 void cvtss2sd(XMMRegister dst, XMMRegister src); 1149 void cvtss2sd(XMMRegister dst, Address src); 1150 1151 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer 1152 void cvtsd2siq(Register dst, XMMRegister src); 1153 void cvttsd2sil(Register dst, Address src); 1154 void cvttsd2sil(Register dst, XMMRegister src); 1155 void cvttsd2siq(Register dst, Address src); 1156 void cvttsd2siq(Register dst, XMMRegister src); 1157 1158 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer 1159 void cvttss2sil(Register dst, XMMRegister src); 1160 void cvttss2siq(Register dst, XMMRegister src); 1161 void cvtss2sil(Register dst, XMMRegister src); 1162 1163 // Convert vector double to int 1164 void cvttpd2dq(XMMRegister dst, XMMRegister src); 1165 1166 // Convert vector float and double 1167 void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len); 1168 void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len); 1169 1170 // Convert vector float and int 1171 void vcvtps2dq(XMMRegister dst, XMMRegister src, int vector_len); 1172 void vcvttps2dq(XMMRegister dst, XMMRegister src, int vector_len); 1173 1174 // Convert vector long to vector FP 1175 void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len); 1176 void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len); 1177 1178 // Convert vector double to long 1179 void evcvtpd2qq(XMMRegister dst, XMMRegister src, int vector_len); 1180 void evcvttpd2qq(XMMRegister dst, XMMRegister src, int vector_len); 1181 1182 // Evex casts with truncation 1183 void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len); 1184 void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len); 1185 void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len); 1186 void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len); 1187 void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len); 1188 void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len); 1189 1190 //Abs of packed Integer values 1191 void pabsb(XMMRegister dst, XMMRegister src); 1192 void pabsw(XMMRegister dst, XMMRegister src); 1193 void pabsd(XMMRegister dst, XMMRegister src); 1194 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len); 1195 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len); 1196 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len); 1197 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len); 1198 1199 void divl(Register src); 1200 void divq(Register src); 1201 1202 // Divide Scalar Double-Precision Floating-Point Values 1203 void divsd(XMMRegister dst, Address src); 1204 void divsd(XMMRegister dst, XMMRegister src); 1205 1206 // Divide Scalar Single-Precision Floating-Point Values 1207 void divss(XMMRegister dst, Address src); 1208 void divss(XMMRegister dst, XMMRegister src); 1209 1210 1211 #ifndef _LP64 1212 private: 1213 1214 void emit_farith(int b1, int b2, int i); 1215 1216 public: 1217 void emms(); 1218 1219 void fabs(); 1220 1221 void fadd(int i); 1222 1223 void fadd_d(Address src); 1224 void fadd_s(Address src); 1225 1226 // "Alternate" versions of x87 instructions place result down in FPU 1227 // stack instead of on TOS 1228 1229 void fadda(int i); // "alternate" fadd 1230 void faddp(int i = 1); 1231 1232 void fchs(); 1233 1234 void fcom(int i); 1235 1236 void fcomp(int i = 1); 1237 void fcomp_d(Address src); 1238 void fcomp_s(Address src); 1239 1240 void fcompp(); 1241 1242 void fcos(); 1243 1244 void fdecstp(); 1245 1246 void fdiv(int i); 1247 void fdiv_d(Address src); 1248 void fdivr_s(Address src); 1249 void fdiva(int i); // "alternate" fdiv 1250 void fdivp(int i = 1); 1251 1252 void fdivr(int i); 1253 void fdivr_d(Address src); 1254 void fdiv_s(Address src); 1255 1256 void fdivra(int i); // "alternate" reversed fdiv 1257 1258 void fdivrp(int i = 1); 1259 1260 void ffree(int i = 0); 1261 1262 void fild_d(Address adr); 1263 void fild_s(Address adr); 1264 1265 void fincstp(); 1266 1267 void finit(); 1268 1269 void fist_s (Address adr); 1270 void fistp_d(Address adr); 1271 void fistp_s(Address adr); 1272 1273 void fld1(); 1274 1275 void fld_d(Address adr); 1276 void fld_s(Address adr); 1277 void fld_s(int index); 1278 1279 void fldcw(Address src); 1280 1281 void fldenv(Address src); 1282 1283 void fldlg2(); 1284 1285 void fldln2(); 1286 1287 void fldz(); 1288 1289 void flog(); 1290 void flog10(); 1291 1292 void fmul(int i); 1293 1294 void fmul_d(Address src); 1295 void fmul_s(Address src); 1296 1297 void fmula(int i); // "alternate" fmul 1298 1299 void fmulp(int i = 1); 1300 1301 void fnsave(Address dst); 1302 1303 void fnstcw(Address src); 1304 1305 void fnstsw_ax(); 1306 1307 void fprem(); 1308 void fprem1(); 1309 1310 void frstor(Address src); 1311 1312 void fsin(); 1313 1314 void fsqrt(); 1315 1316 void fst_d(Address adr); 1317 void fst_s(Address adr); 1318 1319 void fstp_d(Address adr); 1320 void fstp_d(int index); 1321 void fstp_s(Address adr); 1322 1323 void fsub(int i); 1324 void fsub_d(Address src); 1325 void fsub_s(Address src); 1326 1327 void fsuba(int i); // "alternate" fsub 1328 1329 void fsubp(int i = 1); 1330 1331 void fsubr(int i); 1332 void fsubr_d(Address src); 1333 void fsubr_s(Address src); 1334 1335 void fsubra(int i); // "alternate" reversed fsub 1336 1337 void fsubrp(int i = 1); 1338 1339 void ftan(); 1340 1341 void ftst(); 1342 1343 void fucomi(int i = 1); 1344 void fucomip(int i = 1); 1345 1346 void fwait(); 1347 1348 void fxch(int i = 1); 1349 1350 void fyl2x(); 1351 void frndint(); 1352 void f2xm1(); 1353 void fldl2e(); 1354 #endif // !_LP64 1355 1356 // operands that only take the original 32bit registers 1357 void emit_operand32(Register reg, Address adr); 1358 1359 void fld_x(Address adr); // extended-precision (80-bit) format 1360 void fstp_x(Address adr); // extended-precision (80-bit) format 1361 void fxrstor(Address src); 1362 void xrstor(Address src); 1363 1364 void fxsave(Address dst); 1365 void xsave(Address dst); 1366 1367 void hlt(); 1368 1369 void idivl(Register src); 1370 void idivl(Address src); 1371 void idivq(Register src); 1372 void idivq(Address src); 1373 1374 void imull(Register src); 1375 void imull(Register dst, Register src); 1376 void imull(Register dst, Register src, int value); 1377 void imull(Register dst, Address src, int value); 1378 void imull(Register dst, Address src); 1379 1380 #ifdef _LP64 1381 void imulq(Register dst, Register src); 1382 void imulq(Register dst, Register src, int value); 1383 void imulq(Register dst, Address src, int value); 1384 void imulq(Register dst, Address src); 1385 void imulq(Register dst); 1386 #endif 1387 1388 // jcc is the generic conditional branch generator to run- 1389 // time routines, jcc is used for branches to labels. jcc 1390 // takes a branch opcode (cc) and a label (L) and generates 1391 // either a backward branch or a forward branch and links it 1392 // to the label fixup chain. Usage: 1393 // 1394 // Label L; // unbound label 1395 // jcc(cc, L); // forward branch to unbound label 1396 // bind(L); // bind label to the current pc 1397 // jcc(cc, L); // backward branch to bound label 1398 // bind(L); // illegal: a label may be bound only once 1399 // 1400 // Note: The same Label can be used for forward and backward branches 1401 // but it may be bound only once. 1402 1403 void jcc(Condition cc, Label& L, bool maybe_short = true); 1404 1405 // Conditional jump to a 8-bit offset to L. 1406 // WARNING: be very careful using this for forward jumps. If the label is 1407 // not bound within an 8-bit offset of this instruction, a run-time error 1408 // will occur. 1409 1410 // Use macro to record file and line number. 1411 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__) 1412 1413 void jccb_0(Condition cc, Label& L, const char* file, int line); 1414 1415 void jmp(Address entry); // pc <- entry 1416 1417 // Label operations & relative jumps (PPUM Appendix D) 1418 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L 1419 1420 void jmp(Register entry); // pc <- entry 1421 1422 // Unconditional 8-bit offset jump to L. 1423 // WARNING: be very careful using this for forward jumps. If the label is 1424 // not bound within an 8-bit offset of this instruction, a run-time error 1425 // will occur. 1426 1427 // Use macro to record file and line number. 1428 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__) 1429 1430 void jmpb_0(Label& L, const char* file, int line); 1431 1432 void ldmxcsr( Address src ); 1433 1434 void leal(Register dst, Address src); 1435 1436 void leaq(Register dst, Address src); 1437 1438 void lfence(); 1439 1440 void lock(); 1441 void size_prefix(); 1442 1443 void lzcntl(Register dst, Register src); 1444 1445 #ifdef _LP64 1446 void lzcntq(Register dst, Register src); 1447 #endif 1448 1449 enum Membar_mask_bits { 1450 StoreStore = 1 << 3, 1451 LoadStore = 1 << 2, 1452 StoreLoad = 1 << 1, 1453 LoadLoad = 1 << 0 1454 }; 1455 1456 // Serializes memory and blows flags 1457 void membar(Membar_mask_bits order_constraint); 1458 1459 void mfence(); 1460 void sfence(); 1461 1462 // Moves 1463 1464 void mov64(Register dst, int64_t imm64); 1465 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format); 1466 1467 void movb(Address dst, Register src); 1468 void movb(Address dst, int imm8); 1469 void movb(Register dst, Address src); 1470 1471 void movddup(XMMRegister dst, XMMRegister src); 1472 void vmovddup(XMMRegister dst, Address src, int vector_len); 1473 1474 void kandbl(KRegister dst, KRegister src1, KRegister src2); 1475 void kandwl(KRegister dst, KRegister src1, KRegister src2); 1476 void kanddl(KRegister dst, KRegister src1, KRegister src2); 1477 void kandql(KRegister dst, KRegister src1, KRegister src2); 1478 1479 void korbl(KRegister dst, KRegister src1, KRegister src2); 1480 void korwl(KRegister dst, KRegister src1, KRegister src2); 1481 void kordl(KRegister dst, KRegister src1, KRegister src2); 1482 void korql(KRegister dst, KRegister src1, KRegister src2); 1483 1484 void kxorbl(KRegister dst, KRegister src1, KRegister src2); 1485 void kxorwl(KRegister dst, KRegister src1, KRegister src2); 1486 void kxordl(KRegister dst, KRegister src1, KRegister src2); 1487 void kxorql(KRegister dst, KRegister src1, KRegister src2); 1488 void kmovbl(KRegister dst, Register src); 1489 void kmovbl(Register dst, KRegister src); 1490 void kmovbl(KRegister dst, KRegister src); 1491 void kmovwl(KRegister dst, Register src); 1492 void kmovwl(KRegister dst, Address src); 1493 void kmovwl(Register dst, KRegister src); 1494 void kmovwl(Address dst, KRegister src); 1495 void kmovwl(KRegister dst, KRegister src); 1496 void kmovdl(KRegister dst, Register src); 1497 void kmovdl(Register dst, KRegister src); 1498 void kmovql(KRegister dst, KRegister src); 1499 void kmovql(Address dst, KRegister src); 1500 void kmovql(KRegister dst, Address src); 1501 void kmovql(KRegister dst, Register src); 1502 void kmovql(Register dst, KRegister src); 1503 1504 void knotbl(KRegister dst, KRegister src); 1505 void knotwl(KRegister dst, KRegister src); 1506 void knotdl(KRegister dst, KRegister src); 1507 void knotql(KRegister dst, KRegister src); 1508 1509 void kortestbl(KRegister dst, KRegister src); 1510 void kortestwl(KRegister dst, KRegister src); 1511 void kortestdl(KRegister dst, KRegister src); 1512 void kortestql(KRegister dst, KRegister src); 1513 1514 void kxnorbl(KRegister dst, KRegister src1, KRegister src2); 1515 void kshiftlbl(KRegister dst, KRegister src, int imm8); 1516 void kshiftlql(KRegister dst, KRegister src, int imm8); 1517 void kshiftrbl(KRegister dst, KRegister src, int imm8); 1518 void kshiftrwl(KRegister dst, KRegister src, int imm8); 1519 void kshiftrdl(KRegister dst, KRegister src, int imm8); 1520 void kshiftrql(KRegister dst, KRegister src, int imm8); 1521 void ktestq(KRegister src1, KRegister src2); 1522 void ktestd(KRegister src1, KRegister src2); 1523 void kunpckdql(KRegister dst, KRegister src1, KRegister src2); 1524 1525 1526 void ktestql(KRegister dst, KRegister src); 1527 void ktestdl(KRegister dst, KRegister src); 1528 void ktestwl(KRegister dst, KRegister src); 1529 void ktestbl(KRegister dst, KRegister src); 1530 1531 void movdl(XMMRegister dst, Register src); 1532 void movdl(Register dst, XMMRegister src); 1533 void movdl(XMMRegister dst, Address src); 1534 void movdl(Address dst, XMMRegister src); 1535 1536 // Move Double Quadword 1537 void movdq(XMMRegister dst, Register src); 1538 void movdq(Register dst, XMMRegister src); 1539 1540 // Move Aligned Double Quadword 1541 void movdqa(XMMRegister dst, XMMRegister src); 1542 void movdqa(XMMRegister dst, Address src); 1543 1544 // Move Unaligned Double Quadword 1545 void movdqu(Address dst, XMMRegister src); 1546 void movdqu(XMMRegister dst, Address src); 1547 void movdqu(XMMRegister dst, XMMRegister src); 1548 1549 // Move Unaligned 256bit Vector 1550 void vmovdqu(Address dst, XMMRegister src); 1551 void vmovdqu(XMMRegister dst, Address src); 1552 void vmovdqu(XMMRegister dst, XMMRegister src); 1553 1554 // Move Unaligned 512bit Vector 1555 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len); 1556 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len); 1557 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len); 1558 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1559 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1560 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len); 1561 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1562 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len); 1563 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1564 void evmovdqul(Address dst, XMMRegister src, int vector_len); 1565 void evmovdqul(XMMRegister dst, Address src, int vector_len); 1566 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len); 1567 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1568 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1569 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1570 void evmovdquq(Address dst, XMMRegister src, int vector_len); 1571 void evmovdquq(XMMRegister dst, Address src, int vector_len); 1572 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len); 1573 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1574 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 1575 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1576 1577 // Move lower 64bit to high 64bit in 128bit register 1578 void movlhps(XMMRegister dst, XMMRegister src); 1579 1580 void movl(Register dst, int32_t imm32); 1581 void movl(Address dst, int32_t imm32); 1582 void movl(Register dst, Register src); 1583 void movl(Register dst, Address src); 1584 void movl(Address dst, Register src); 1585 1586 // These dummies prevent using movl from converting a zero (like NULL) into Register 1587 // by giving the compiler two choices it can't resolve 1588 1589 void movl(Address dst, void* junk); 1590 void movl(Register dst, void* junk); 1591 1592 #ifdef _LP64 1593 void movq(Register dst, Register src); 1594 void movq(Register dst, Address src); 1595 void movq(Address dst, Register src); 1596 void movq(Address dst, int32_t imm32); 1597 void movq(Register dst, int32_t imm32); 1598 1599 // These dummies prevent using movq from converting a zero (like NULL) into Register 1600 // by giving the compiler two choices it can't resolve 1601 1602 void movq(Address dst, void* dummy); 1603 void movq(Register dst, void* dummy); 1604 #endif 1605 1606 // Move Quadword 1607 void movq(Address dst, XMMRegister src); 1608 void movq(XMMRegister dst, Address src); 1609 void movq(XMMRegister dst, XMMRegister src); 1610 void movq(Register dst, XMMRegister src); 1611 void movq(XMMRegister dst, Register src); 1612 1613 void movsbl(Register dst, Address src); 1614 void movsbl(Register dst, Register src); 1615 1616 #ifdef _LP64 1617 void movsbq(Register dst, Address src); 1618 void movsbq(Register dst, Register src); 1619 1620 // Move signed 32bit immediate to 64bit extending sign 1621 void movslq(Address dst, int32_t imm64); 1622 void movslq(Register dst, int32_t imm64); 1623 1624 void movslq(Register dst, Address src); 1625 void movslq(Register dst, Register src); 1626 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous 1627 #endif 1628 1629 void movswl(Register dst, Address src); 1630 void movswl(Register dst, Register src); 1631 1632 #ifdef _LP64 1633 void movswq(Register dst, Address src); 1634 void movswq(Register dst, Register src); 1635 #endif 1636 1637 void movw(Address dst, int imm16); 1638 void movw(Register dst, Address src); 1639 void movw(Address dst, Register src); 1640 1641 void movzbl(Register dst, Address src); 1642 void movzbl(Register dst, Register src); 1643 1644 #ifdef _LP64 1645 void movzbq(Register dst, Address src); 1646 void movzbq(Register dst, Register src); 1647 #endif 1648 1649 void movzwl(Register dst, Address src); 1650 void movzwl(Register dst, Register src); 1651 1652 #ifdef _LP64 1653 void movzwq(Register dst, Address src); 1654 void movzwq(Register dst, Register src); 1655 #endif 1656 1657 // Unsigned multiply with RAX destination register 1658 void mull(Address src); 1659 void mull(Register src); 1660 1661 #ifdef _LP64 1662 void mulq(Address src); 1663 void mulq(Register src); 1664 void mulxq(Register dst1, Register dst2, Register src); 1665 #endif 1666 1667 // Multiply Scalar Double-Precision Floating-Point Values 1668 void mulsd(XMMRegister dst, Address src); 1669 void mulsd(XMMRegister dst, XMMRegister src); 1670 1671 // Multiply Scalar Single-Precision Floating-Point Values 1672 void mulss(XMMRegister dst, Address src); 1673 void mulss(XMMRegister dst, XMMRegister src); 1674 1675 void negl(Register dst); 1676 void negl(Address dst); 1677 1678 #ifdef _LP64 1679 void negq(Register dst); 1680 void negq(Address dst); 1681 #endif 1682 1683 void nop(int i = 1); 1684 1685 void notl(Register dst); 1686 1687 #ifdef _LP64 1688 void notq(Register dst); 1689 1690 void btsq(Address dst, int imm8); 1691 void btrq(Address dst, int imm8); 1692 #endif 1693 1694 void orw(Register dst, Register src); 1695 1696 void orl(Address dst, int32_t imm32); 1697 void orl(Register dst, int32_t imm32); 1698 void orl(Register dst, Address src); 1699 void orl(Register dst, Register src); 1700 void orl(Address dst, Register src); 1701 1702 void orb(Address dst, int imm8); 1703 void orb(Address dst, Register src); 1704 1705 void orq(Address dst, int32_t imm32); 1706 void orq(Address dst, Register src); 1707 void orq(Register dst, int32_t imm32); 1708 void orq(Register dst, Address src); 1709 void orq(Register dst, Register src); 1710 1711 // Pack with signed saturation 1712 void packsswb(XMMRegister dst, XMMRegister src); 1713 void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1714 void packssdw(XMMRegister dst, XMMRegister src); 1715 void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1716 1717 // Pack with unsigned saturation 1718 void packuswb(XMMRegister dst, XMMRegister src); 1719 void packuswb(XMMRegister dst, Address src); 1720 void packusdw(XMMRegister dst, XMMRegister src); 1721 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1722 void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1723 1724 // Permutations 1725 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1726 void vpermq(XMMRegister dst, XMMRegister src, int imm8); 1727 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1728 void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1729 void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1730 void vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1731 void vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1732 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1733 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1734 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1735 void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1736 void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1737 void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len); 1738 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1739 void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1740 void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len); 1741 1742 void pause(); 1743 1744 // Undefined Instruction 1745 void ud2(); 1746 1747 // SSE4.2 string instructions 1748 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8); 1749 void pcmpestri(XMMRegister xmm1, Address src, int imm8); 1750 1751 void pcmpeqb(XMMRegister dst, XMMRegister src); 1752 void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len); 1753 1754 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1755 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1756 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1757 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1758 1759 void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1760 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1761 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1762 1763 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len); 1764 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len); 1765 1766 void pcmpeqw(XMMRegister dst, XMMRegister src); 1767 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1768 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1769 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1770 1771 void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1772 1773 void pcmpeqd(XMMRegister dst, XMMRegister src); 1774 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1775 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len); 1776 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len); 1777 1778 void pcmpeqq(XMMRegister dst, XMMRegister src); 1779 void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len); 1780 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1781 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len); 1782 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len); 1783 1784 void pcmpgtq(XMMRegister dst, XMMRegister src); 1785 void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1786 1787 void pmovmskb(Register dst, XMMRegister src); 1788 void vpmovmskb(Register dst, XMMRegister src, int vec_enc); 1789 void vmovmskps(Register dst, XMMRegister src, int vec_enc); 1790 void vmovmskpd(Register dst, XMMRegister src, int vec_enc); 1791 void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 1792 1793 // SSE 4.1 extract 1794 void pextrd(Register dst, XMMRegister src, int imm8); 1795 void pextrq(Register dst, XMMRegister src, int imm8); 1796 void pextrd(Address dst, XMMRegister src, int imm8); 1797 void pextrq(Address dst, XMMRegister src, int imm8); 1798 void pextrb(Register dst, XMMRegister src, int imm8); 1799 void pextrb(Address dst, XMMRegister src, int imm8); 1800 // SSE 2 extract 1801 void pextrw(Register dst, XMMRegister src, int imm8); 1802 void pextrw(Address dst, XMMRegister src, int imm8); 1803 1804 // SSE 4.1 insert 1805 void pinsrd(XMMRegister dst, Register src, int imm8); 1806 void pinsrq(XMMRegister dst, Register src, int imm8); 1807 void pinsrb(XMMRegister dst, Register src, int imm8); 1808 void pinsrd(XMMRegister dst, Address src, int imm8); 1809 void pinsrq(XMMRegister dst, Address src, int imm8); 1810 void pinsrb(XMMRegister dst, Address src, int imm8); 1811 void insertps(XMMRegister dst, XMMRegister src, int imm8); 1812 // SSE 2 insert 1813 void pinsrw(XMMRegister dst, Register src, int imm8); 1814 void pinsrw(XMMRegister dst, Address src, int imm8); 1815 1816 // AVX insert 1817 void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1818 void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1819 void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1820 void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8); 1821 void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8); 1822 1823 // Zero extend moves 1824 void pmovzxbw(XMMRegister dst, XMMRegister src); 1825 void pmovzxbw(XMMRegister dst, Address src); 1826 void pmovzxbd(XMMRegister dst, XMMRegister src); 1827 void vpmovzxbw(XMMRegister dst, Address src, int vector_len); 1828 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len); 1829 void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len); 1830 void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len); 1831 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len); 1832 void vpmovzxwq(XMMRegister dst, XMMRegister src, int vector_len); 1833 void pmovzxdq(XMMRegister dst, XMMRegister src); 1834 void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len); 1835 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len); 1836 1837 // Sign extend moves 1838 void pmovsxbd(XMMRegister dst, XMMRegister src); 1839 void pmovsxbq(XMMRegister dst, XMMRegister src); 1840 void pmovsxbw(XMMRegister dst, XMMRegister src); 1841 void pmovsxwd(XMMRegister dst, XMMRegister src); 1842 void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len); 1843 void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len); 1844 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len); 1845 void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len); 1846 void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len); 1847 void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len); 1848 1849 void evpmovwb(Address dst, XMMRegister src, int vector_len); 1850 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len); 1851 void evpmovdb(Address dst, XMMRegister src, int vector_len); 1852 1853 // Multiply add 1854 void pmaddwd(XMMRegister dst, XMMRegister src); 1855 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1856 void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 1857 1858 // Multiply add accumulate 1859 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1860 1861 #ifndef _LP64 // no 32bit push/pop on amd64 1862 void popl(Address dst); 1863 #endif 1864 1865 #ifdef _LP64 1866 void popq(Address dst); 1867 void popq(Register dst); 1868 #endif 1869 1870 void popcntl(Register dst, Address src); 1871 void popcntl(Register dst, Register src); 1872 1873 void evpopcntb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1874 void evpopcntw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1875 void evpopcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1876 void evpopcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 1877 1878 #ifdef _LP64 1879 void popcntq(Register dst, Address src); 1880 void popcntq(Register dst, Register src); 1881 #endif 1882 1883 // Prefetches (SSE, SSE2, 3DNOW only) 1884 1885 void prefetchnta(Address src); 1886 void prefetchr(Address src); 1887 void prefetcht0(Address src); 1888 void prefetcht1(Address src); 1889 void prefetcht2(Address src); 1890 void prefetchw(Address src); 1891 1892 // Shuffle Bytes 1893 void pshufb(XMMRegister dst, XMMRegister src); 1894 void pshufb(XMMRegister dst, Address src); 1895 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1896 1897 // Shuffle Packed Doublewords 1898 void pshufd(XMMRegister dst, XMMRegister src, int mode); 1899 void pshufd(XMMRegister dst, Address src, int mode); 1900 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len); 1901 1902 // Shuffle Packed High/Low Words 1903 void pshufhw(XMMRegister dst, XMMRegister src, int mode); 1904 void pshuflw(XMMRegister dst, XMMRegister src, int mode); 1905 void pshuflw(XMMRegister dst, Address src, int mode); 1906 1907 //shuffle floats and doubles 1908 void pshufps(XMMRegister, XMMRegister, int); 1909 void pshufpd(XMMRegister, XMMRegister, int); 1910 void vpshufps(XMMRegister, XMMRegister, XMMRegister, int, int); 1911 void vpshufpd(XMMRegister, XMMRegister, XMMRegister, int, int); 1912 1913 // Shuffle packed values at 128 bit granularity 1914 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); 1915 1916 // Shift Right by bytes Logical DoubleQuadword Immediate 1917 void psrldq(XMMRegister dst, int shift); 1918 // Shift Left by bytes Logical DoubleQuadword Immediate 1919 void pslldq(XMMRegister dst, int shift); 1920 1921 // Logical Compare 128bit 1922 void ptest(XMMRegister dst, XMMRegister src); 1923 void ptest(XMMRegister dst, Address src); 1924 // Logical Compare 256bit 1925 void vptest(XMMRegister dst, XMMRegister src); 1926 void vptest(XMMRegister dst, Address src); 1927 1928 void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1929 1930 // Vector compare 1931 void vptest(XMMRegister dst, XMMRegister src, int vector_len); 1932 1933 // Interleave Low Bytes 1934 void punpcklbw(XMMRegister dst, XMMRegister src); 1935 void punpcklbw(XMMRegister dst, Address src); 1936 1937 // Interleave Low Doublewords 1938 void punpckldq(XMMRegister dst, XMMRegister src); 1939 void punpckldq(XMMRegister dst, Address src); 1940 void vpunpckldq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1941 1942 // Interleave High Word 1943 void vpunpckhwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1944 1945 // Interleave Low Word 1946 void vpunpcklwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1947 1948 // Interleave High Doublewords 1949 void vpunpckhdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1950 1951 // Interleave Low Quadwords 1952 void punpcklqdq(XMMRegister dst, XMMRegister src); 1953 1954 // Vector sum of absolute difference. 1955 void vpsadbw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 1956 1957 #ifndef _LP64 // no 32bit push/pop on amd64 1958 void pushl(Address src); 1959 #endif 1960 1961 void pushq(Address src); 1962 1963 void rcll(Register dst, int imm8); 1964 1965 void rclq(Register dst, int imm8); 1966 1967 void rcrq(Register dst, int imm8); 1968 1969 void rcpps(XMMRegister dst, XMMRegister src); 1970 1971 void rcpss(XMMRegister dst, XMMRegister src); 1972 1973 void rdtsc(); 1974 1975 void ret(int imm16); 1976 1977 void roll(Register dst); 1978 1979 void roll(Register dst, int imm8); 1980 1981 void rorl(Register dst); 1982 1983 void rorl(Register dst, int imm8); 1984 1985 #ifdef _LP64 1986 void rolq(Register dst); 1987 void rolq(Register dst, int imm8); 1988 void rorq(Register dst); 1989 void rorq(Register dst, int imm8); 1990 void rorxq(Register dst, Register src, int imm8); 1991 void rorxd(Register dst, Register src, int imm8); 1992 #endif 1993 1994 void sahf(); 1995 1996 void sall(Register dst, int imm8); 1997 void sall(Register dst); 1998 void sall(Address dst, int imm8); 1999 void sall(Address dst); 2000 2001 void sarl(Address dst, int imm8); 2002 void sarl(Address dst); 2003 void sarl(Register dst, int imm8); 2004 void sarl(Register dst); 2005 2006 #ifdef _LP64 2007 void salq(Register dst, int imm8); 2008 void salq(Register dst); 2009 void salq(Address dst, int imm8); 2010 void salq(Address dst); 2011 2012 void sarq(Address dst, int imm8); 2013 void sarq(Address dst); 2014 void sarq(Register dst, int imm8); 2015 void sarq(Register dst); 2016 #endif 2017 2018 void sbbl(Address dst, int32_t imm32); 2019 void sbbl(Register dst, int32_t imm32); 2020 void sbbl(Register dst, Address src); 2021 void sbbl(Register dst, Register src); 2022 2023 void sbbq(Address dst, int32_t imm32); 2024 void sbbq(Register dst, int32_t imm32); 2025 void sbbq(Register dst, Address src); 2026 void sbbq(Register dst, Register src); 2027 2028 void setb(Condition cc, Register dst); 2029 2030 void sete(Register dst); 2031 void setl(Register dst); 2032 void setne(Register dst); 2033 2034 void palignr(XMMRegister dst, XMMRegister src, int imm8); 2035 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len); 2036 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2037 2038 void pblendw(XMMRegister dst, XMMRegister src, int imm8); 2039 void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len); 2040 2041 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8); 2042 void sha1nexte(XMMRegister dst, XMMRegister src); 2043 void sha1msg1(XMMRegister dst, XMMRegister src); 2044 void sha1msg2(XMMRegister dst, XMMRegister src); 2045 // xmm0 is implicit additional source to the following instruction. 2046 void sha256rnds2(XMMRegister dst, XMMRegister src); 2047 void sha256msg1(XMMRegister dst, XMMRegister src); 2048 void sha256msg2(XMMRegister dst, XMMRegister src); 2049 2050 void shldl(Register dst, Register src); 2051 void shldl(Register dst, Register src, int8_t imm8); 2052 void shrdl(Register dst, Register src); 2053 void shrdl(Register dst, Register src, int8_t imm8); 2054 2055 void shll(Register dst, int imm8); 2056 void shll(Register dst); 2057 2058 void shlq(Register dst, int imm8); 2059 void shlq(Register dst); 2060 2061 void shrl(Register dst, int imm8); 2062 void shrl(Register dst); 2063 void shrl(Address dst); 2064 void shrl(Address dst, int imm8); 2065 2066 void shrq(Register dst, int imm8); 2067 void shrq(Register dst); 2068 void shrq(Address dst); 2069 void shrq(Address dst, int imm8); 2070 2071 void smovl(); // QQQ generic? 2072 2073 // Compute Square Root of Scalar Double-Precision Floating-Point Value 2074 void sqrtsd(XMMRegister dst, Address src); 2075 void sqrtsd(XMMRegister dst, XMMRegister src); 2076 2077 void roundsd(XMMRegister dst, Address src, int32_t rmode); 2078 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode); 2079 2080 // Compute Square Root of Scalar Single-Precision Floating-Point Value 2081 void sqrtss(XMMRegister dst, Address src); 2082 void sqrtss(XMMRegister dst, XMMRegister src); 2083 2084 void std(); 2085 2086 void stmxcsr( Address dst ); 2087 2088 void subl(Address dst, int32_t imm32); 2089 void subl(Address dst, Register src); 2090 void subl(Register dst, int32_t imm32); 2091 void subl(Register dst, Address src); 2092 void subl(Register dst, Register src); 2093 2094 void subq(Address dst, int32_t imm32); 2095 void subq(Address dst, Register src); 2096 void subq(Register dst, int32_t imm32); 2097 void subq(Register dst, Address src); 2098 void subq(Register dst, Register src); 2099 2100 // Force generation of a 4 byte immediate value even if it fits into 8bit 2101 void subl_imm32(Register dst, int32_t imm32); 2102 void subq_imm32(Register dst, int32_t imm32); 2103 2104 // Subtract Scalar Double-Precision Floating-Point Values 2105 void subsd(XMMRegister dst, Address src); 2106 void subsd(XMMRegister dst, XMMRegister src); 2107 2108 // Subtract Scalar Single-Precision Floating-Point Values 2109 void subss(XMMRegister dst, Address src); 2110 void subss(XMMRegister dst, XMMRegister src); 2111 2112 void testb(Address dst, int imm8); 2113 void testb(Register dst, int imm8); 2114 2115 void testl(Address dst, int32_t imm32); 2116 void testl(Register dst, int32_t imm32); 2117 void testl(Register dst, Register src); 2118 void testl(Register dst, Address src); 2119 2120 void testq(Address dst, int32_t imm32); 2121 void testq(Register dst, int32_t imm32); 2122 void testq(Register dst, Register src); 2123 void testq(Register dst, Address src); 2124 2125 // BMI - count trailing zeros 2126 void tzcntl(Register dst, Register src); 2127 void tzcntq(Register dst, Register src); 2128 2129 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS 2130 void ucomisd(XMMRegister dst, Address src); 2131 void ucomisd(XMMRegister dst, XMMRegister src); 2132 2133 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS 2134 void ucomiss(XMMRegister dst, Address src); 2135 void ucomiss(XMMRegister dst, XMMRegister src); 2136 2137 void xabort(int8_t imm8); 2138 2139 void xaddb(Address dst, Register src); 2140 void xaddw(Address dst, Register src); 2141 void xaddl(Address dst, Register src); 2142 void xaddq(Address dst, Register src); 2143 2144 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none); 2145 2146 void xchgb(Register reg, Address adr); 2147 void xchgw(Register reg, Address adr); 2148 void xchgl(Register reg, Address adr); 2149 void xchgl(Register dst, Register src); 2150 2151 void xchgq(Register reg, Address adr); 2152 void xchgq(Register dst, Register src); 2153 2154 void xend(); 2155 2156 // Get Value of Extended Control Register 2157 void xgetbv(); 2158 2159 void xorl(Register dst, int32_t imm32); 2160 void xorl(Address dst, int32_t imm32); 2161 void xorl(Register dst, Address src); 2162 void xorl(Register dst, Register src); 2163 void xorl(Address dst, Register src); 2164 2165 void xorb(Address dst, Register src); 2166 void xorb(Register dst, Address src); 2167 void xorw(Register dst, Register src); 2168 2169 void xorq(Register dst, Address src); 2170 void xorq(Address dst, int32_t imm32); 2171 void xorq(Register dst, Register src); 2172 void xorq(Register dst, int32_t imm32); 2173 void xorq(Address dst, Register src); 2174 2175 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0 2176 2177 // AVX 3-operands scalar instructions (encoded with VEX prefix) 2178 2179 void vaddsd(XMMRegister dst, XMMRegister nds, Address src); 2180 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2181 void vaddss(XMMRegister dst, XMMRegister nds, Address src); 2182 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2183 void vdivsd(XMMRegister dst, XMMRegister nds, Address src); 2184 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2185 void vdivss(XMMRegister dst, XMMRegister nds, Address src); 2186 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2187 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2188 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2189 void vmulsd(XMMRegister dst, XMMRegister nds, Address src); 2190 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2191 void vmulss(XMMRegister dst, XMMRegister nds, Address src); 2192 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2193 void vsubsd(XMMRegister dst, XMMRegister nds, Address src); 2194 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2195 void vsubss(XMMRegister dst, XMMRegister nds, Address src); 2196 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2197 2198 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2199 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2200 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src); 2201 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src); 2202 2203 void shlxl(Register dst, Register src1, Register src2); 2204 void shlxq(Register dst, Register src1, Register src2); 2205 void shrxl(Register dst, Register src1, Register src2); 2206 void shrxq(Register dst, Register src1, Register src2); 2207 2208 void bzhiq(Register dst, Register src1, Register src2); 2209 void pext(Register dst, Register src1, Register src2); 2210 void pdep(Register dst, Register src1, Register src2); 2211 2212 //====================VECTOR ARITHMETIC===================================== 2213 // Add Packed Floating-Point Values 2214 void addpd(XMMRegister dst, XMMRegister src); 2215 void addpd(XMMRegister dst, Address src); 2216 void addps(XMMRegister dst, XMMRegister src); 2217 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2218 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2219 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2220 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2221 2222 // Subtract Packed Floating-Point Values 2223 void subpd(XMMRegister dst, XMMRegister src); 2224 void subps(XMMRegister dst, XMMRegister src); 2225 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2226 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2227 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2228 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2229 2230 // Multiply Packed Floating-Point Values 2231 void mulpd(XMMRegister dst, XMMRegister src); 2232 void mulpd(XMMRegister dst, Address src); 2233 void mulps(XMMRegister dst, XMMRegister src); 2234 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2235 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2236 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2237 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2238 2239 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2240 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2241 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2242 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2243 2244 // Divide Packed Floating-Point Values 2245 void divpd(XMMRegister dst, XMMRegister src); 2246 void divps(XMMRegister dst, XMMRegister src); 2247 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2248 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2249 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2250 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2251 2252 // Sqrt Packed Floating-Point Values 2253 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len); 2254 void vsqrtpd(XMMRegister dst, Address src, int vector_len); 2255 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len); 2256 void vsqrtps(XMMRegister dst, Address src, int vector_len); 2257 2258 // Round Packed Double precision value. 2259 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); 2260 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len); 2261 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len); 2262 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len); 2263 2264 // Bitwise Logical AND of Packed Floating-Point Values 2265 void andpd(XMMRegister dst, XMMRegister src); 2266 void andps(XMMRegister dst, XMMRegister src); 2267 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2268 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2269 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2270 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2271 2272 void unpckhpd(XMMRegister dst, XMMRegister src); 2273 void unpcklpd(XMMRegister dst, XMMRegister src); 2274 2275 // Bitwise Logical XOR of Packed Floating-Point Values 2276 void xorpd(XMMRegister dst, XMMRegister src); 2277 void xorps(XMMRegister dst, XMMRegister src); 2278 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2279 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2280 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2281 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2282 2283 // Add horizontal packed integers 2284 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2285 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2286 void phaddw(XMMRegister dst, XMMRegister src); 2287 void phaddd(XMMRegister dst, XMMRegister src); 2288 2289 // Add packed integers 2290 void paddb(XMMRegister dst, XMMRegister src); 2291 void paddw(XMMRegister dst, XMMRegister src); 2292 void paddd(XMMRegister dst, XMMRegister src); 2293 void paddd(XMMRegister dst, Address src); 2294 void paddq(XMMRegister dst, XMMRegister src); 2295 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2296 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2297 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2298 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2299 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2300 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2301 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2302 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2303 2304 // Leaf level assembler routines for masked operations. 2305 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2306 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2307 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2308 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2309 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2310 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2311 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2312 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2313 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2314 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2315 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2316 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2317 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2318 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2319 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2320 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2321 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2322 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2323 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2324 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2325 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2326 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2327 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2328 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2329 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2330 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2331 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2332 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2333 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2334 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2335 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2336 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2337 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2338 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2339 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2340 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2341 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2342 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2343 void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2344 void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 2345 void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2346 void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 2347 void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2348 void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 2349 void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2350 void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len); 2351 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2352 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2353 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2354 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2355 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2356 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2357 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2358 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2359 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2360 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2361 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2362 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2363 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2364 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2365 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2366 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2367 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2368 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2369 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2370 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2371 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2372 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2373 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2374 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2375 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2376 2377 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2378 void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2379 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2380 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2381 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2382 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2383 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2384 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2385 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2386 2387 void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2388 void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2389 void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2390 void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2391 void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2392 void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2393 void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2394 void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2395 void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2396 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2397 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2398 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2399 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2400 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2401 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2402 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2403 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2404 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2405 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2406 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2407 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2408 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2409 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2410 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2411 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2412 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2413 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2414 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2415 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2416 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2417 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2418 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2419 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2420 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2421 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2422 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2423 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len); 2424 2425 void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2426 void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2427 void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2428 void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2429 void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2430 void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len); 2431 void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2432 void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2433 2434 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len); 2435 void evpternlogd(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len); 2436 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, XMMRegister src3, bool merge, int vector_len); 2437 void evpternlogq(XMMRegister dst, int imm8, KRegister mask, XMMRegister src2, Address src3, bool merge, int vector_len); 2438 2439 void evplzcntd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2440 void evplzcntq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2441 2442 // Sub packed integers 2443 void psubb(XMMRegister dst, XMMRegister src); 2444 void psubw(XMMRegister dst, XMMRegister src); 2445 void psubd(XMMRegister dst, XMMRegister src); 2446 void psubq(XMMRegister dst, XMMRegister src); 2447 void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2448 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2449 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2450 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2451 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2452 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2453 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2454 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2455 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2456 2457 // Multiply packed integers (only shorts and ints) 2458 void pmullw(XMMRegister dst, XMMRegister src); 2459 void pmulld(XMMRegister dst, XMMRegister src); 2460 void pmuludq(XMMRegister dst, XMMRegister src); 2461 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2462 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2463 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2464 void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2465 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2466 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2467 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2468 void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2469 2470 // Minimum of packed integers 2471 void pminsb(XMMRegister dst, XMMRegister src); 2472 void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2473 void pminsw(XMMRegister dst, XMMRegister src); 2474 void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2475 void pminsd(XMMRegister dst, XMMRegister src); 2476 void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2477 void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2478 void minps(XMMRegister dst, XMMRegister src); 2479 void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2480 void minpd(XMMRegister dst, XMMRegister src); 2481 void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2482 2483 // Maximum of packed integers 2484 void pmaxsb(XMMRegister dst, XMMRegister src); 2485 void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2486 void pmaxsw(XMMRegister dst, XMMRegister src); 2487 void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2488 void pmaxsd(XMMRegister dst, XMMRegister src); 2489 void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2490 void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2491 void maxps(XMMRegister dst, XMMRegister src); 2492 void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2493 void maxpd(XMMRegister dst, XMMRegister src); 2494 void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len); 2495 2496 // Shift left packed integers 2497 void psllw(XMMRegister dst, int shift); 2498 void pslld(XMMRegister dst, int shift); 2499 void psllq(XMMRegister dst, int shift); 2500 void psllw(XMMRegister dst, XMMRegister shift); 2501 void pslld(XMMRegister dst, XMMRegister shift); 2502 void psllq(XMMRegister dst, XMMRegister shift); 2503 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2504 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2505 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2506 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2507 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2508 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2509 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2510 2511 // Logical shift right packed integers 2512 void psrlw(XMMRegister dst, int shift); 2513 void psrld(XMMRegister dst, int shift); 2514 void psrlq(XMMRegister dst, int shift); 2515 void psrlw(XMMRegister dst, XMMRegister shift); 2516 void psrld(XMMRegister dst, XMMRegister shift); 2517 void psrlq(XMMRegister dst, XMMRegister shift); 2518 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2519 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2520 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2521 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2522 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2523 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2524 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2525 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2526 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2527 2528 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs) 2529 void psraw(XMMRegister dst, int shift); 2530 void psrad(XMMRegister dst, int shift); 2531 void psraw(XMMRegister dst, XMMRegister shift); 2532 void psrad(XMMRegister dst, XMMRegister shift); 2533 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2534 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2535 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2536 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2537 void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2538 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2539 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2540 2541 // Variable shift left packed integers 2542 void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2543 void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2544 2545 // Variable shift right packed integers 2546 void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2547 void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2548 2549 // Variable shift right arithmetic packed integers 2550 void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2551 void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2552 2553 void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2554 void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2555 2556 // And packed integers 2557 void pand(XMMRegister dst, XMMRegister src); 2558 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2559 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2560 void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2561 2562 // Andn packed integers 2563 void pandn(XMMRegister dst, XMMRegister src); 2564 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2565 2566 // Or packed integers 2567 void por(XMMRegister dst, XMMRegister src); 2568 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2569 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2570 void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2571 2572 // Xor packed integers 2573 void pxor(XMMRegister dst, XMMRegister src); 2574 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2575 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2576 void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2577 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2578 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len); 2579 2580 // Ternary logic instruction. 2581 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len); 2582 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len); 2583 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len); 2584 2585 // Vector compress/expand instructions. 2586 void evpcompressb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2587 void evpcompressw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2588 void evpcompressd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2589 void evpcompressq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2590 void evcompressps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2591 void evcompresspd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2592 2593 void evpexpandb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2594 void evpexpandw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2595 void evpexpandd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2596 void evpexpandq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2597 void evexpandps(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2598 void evexpandpd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len); 2599 2600 // Vector Rotate Left/Right instruction. 2601 void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2602 void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2603 void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2604 void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len); 2605 void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2606 void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2607 void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2608 void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len); 2609 2610 // vinserti forms 2611 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2612 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2613 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2614 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2615 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2616 2617 // vinsertf forms 2618 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2619 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2620 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2621 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2622 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8); 2623 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8); 2624 2625 // vextracti forms 2626 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8); 2627 void vextracti128(Address dst, XMMRegister src, uint8_t imm8); 2628 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2629 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8); 2630 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); 2631 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2632 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8); 2633 2634 // vextractf forms 2635 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8); 2636 void vextractf128(Address dst, XMMRegister src, uint8_t imm8); 2637 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2638 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8); 2639 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8); 2640 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8); 2641 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8); 2642 2643 // xmm/mem sourced byte/word/dword/qword replicate 2644 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len); 2645 void vpbroadcastb(XMMRegister dst, Address src, int vector_len); 2646 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len); 2647 void vpbroadcastw(XMMRegister dst, Address src, int vector_len); 2648 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len); 2649 void vpbroadcastd(XMMRegister dst, Address src, int vector_len); 2650 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len); 2651 void vpbroadcastq(XMMRegister dst, Address src, int vector_len); 2652 2653 void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len); 2654 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len); 2655 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len); 2656 2657 // scalar single/double/128bit precision replicate 2658 void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len); 2659 void vbroadcastss(XMMRegister dst, Address src, int vector_len); 2660 void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len); 2661 void vbroadcastsd(XMMRegister dst, Address src, int vector_len); 2662 void vbroadcastf128(XMMRegister dst, Address src, int vector_len); 2663 2664 // gpr sourced byte/word/dword/qword replicate 2665 void evpbroadcastb(XMMRegister dst, Register src, int vector_len); 2666 void evpbroadcastw(XMMRegister dst, Register src, int vector_len); 2667 void evpbroadcastd(XMMRegister dst, Register src, int vector_len); 2668 void evpbroadcastq(XMMRegister dst, Register src, int vector_len); 2669 2670 // Gather AVX2 and AVX3 2671 void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2672 void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2673 void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2674 void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len); 2675 void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len); 2676 void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len); 2677 void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len); 2678 void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len); 2679 2680 //Scatter AVX3 only 2681 void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len); 2682 void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len); 2683 void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len); 2684 void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len); 2685 2686 // Carry-Less Multiplication Quadword 2687 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask); 2688 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask); 2689 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len); 2690 // AVX instruction which is used to clear upper 128 bits of YMM registers and 2691 // to avoid transaction penalty between AVX and SSE states. There is no 2692 // penalty if legacy SSE instructions are encoded using VEX prefix because 2693 // they always clear upper 128 bits. It should be used before calling 2694 // runtime code and native libraries. 2695 void vzeroupper(); 2696 2697 // Vector double compares 2698 void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len); 2699 void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2700 ComparisonPredicateFP comparison, int vector_len); 2701 2702 // Vector float compares 2703 void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len); 2704 void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2705 ComparisonPredicateFP comparison, int vector_len); 2706 2707 // Vector integer compares 2708 void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len); 2709 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2710 int comparison, bool is_signed, int vector_len); 2711 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2712 int comparison, bool is_signed, int vector_len); 2713 2714 // Vector long compares 2715 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2716 int comparison, bool is_signed, int vector_len); 2717 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2718 int comparison, bool is_signed, int vector_len); 2719 2720 // Vector byte compares 2721 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2722 int comparison, bool is_signed, int vector_len); 2723 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2724 int comparison, bool is_signed, int vector_len); 2725 2726 // Vector short compares 2727 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, 2728 int comparison, bool is_signed, int vector_len); 2729 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src, 2730 int comparison, bool is_signed, int vector_len); 2731 2732 void evpmovb2m(KRegister dst, XMMRegister src, int vector_len); 2733 void evpmovw2m(KRegister dst, XMMRegister src, int vector_len); 2734 void evpmovd2m(KRegister dst, XMMRegister src, int vector_len); 2735 void evpmovq2m(KRegister dst, XMMRegister src, int vector_len); 2736 void evpmovm2b(XMMRegister dst, KRegister src, int vector_len); 2737 void evpmovm2w(XMMRegister dst, KRegister src, int vector_len); 2738 void evpmovm2d(XMMRegister dst, KRegister src, int vector_len); 2739 void evpmovm2q(XMMRegister dst, KRegister src, int vector_len); 2740 2741 // Vector blends 2742 void blendvps(XMMRegister dst, XMMRegister src); 2743 void blendvpd(XMMRegister dst, XMMRegister src); 2744 void pblendvb(XMMRegister dst, XMMRegister src); 2745 void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); 2746 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len); 2747 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len); 2748 void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len); 2749 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len); 2750 void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2751 void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2752 void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2753 void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2754 void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2755 void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len); 2756 2757 // Galois field affine transformation instructions. 2758 void vgf2p8affineqb(XMMRegister dst, XMMRegister src2, XMMRegister src3, int imm8, int vector_len); 2759 2760 protected: 2761 // Next instructions require address alignment 16 bytes SSE mode. 2762 // They should be called only from corresponding MacroAssembler instructions. 2763 void andpd(XMMRegister dst, Address src); 2764 void andps(XMMRegister dst, Address src); 2765 void xorpd(XMMRegister dst, Address src); 2766 void xorps(XMMRegister dst, Address src); 2767 2768 }; 2769 2770 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions. 2771 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction 2772 // are applied. 2773 class InstructionAttr { 2774 public: 2775 InstructionAttr( 2776 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX 2777 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true 2778 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX 2779 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used 2780 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX 2781 : 2782 _rex_vex_w(rex_vex_w), 2783 _legacy_mode(legacy_mode || UseAVX < 3), 2784 _no_reg_mask(no_reg_mask), 2785 _uses_vl(uses_vl), 2786 _rex_vex_w_reverted(false), 2787 _is_evex_instruction(false), 2788 _is_clear_context(true), 2789 _is_extended_context(false), 2790 _avx_vector_len(vector_len), 2791 _tuple_type(Assembler::EVEX_ETUP), 2792 _input_size_in_bits(Assembler::EVEX_NObit), 2793 _evex_encoding(0), 2794 _embedded_opmask_register_specifier(0), // hard code k0 2795 _current_assembler(NULL) { } 2796 2797 ~InstructionAttr() { 2798 if (_current_assembler != NULL) { 2799 _current_assembler->clear_attributes(); 2800 } 2801 _current_assembler = NULL; 2802 } 2803 2804 private: 2805 bool _rex_vex_w; 2806 bool _legacy_mode; 2807 bool _no_reg_mask; 2808 bool _uses_vl; 2809 bool _rex_vex_w_reverted; 2810 bool _is_evex_instruction; 2811 bool _is_clear_context; 2812 bool _is_extended_context; 2813 int _avx_vector_len; 2814 int _tuple_type; 2815 int _input_size_in_bits; 2816 int _evex_encoding; 2817 int _embedded_opmask_register_specifier; 2818 2819 Assembler *_current_assembler; 2820 2821 public: 2822 // query functions for field accessors 2823 bool is_rex_vex_w(void) const { return _rex_vex_w; } 2824 bool is_legacy_mode(void) const { return _legacy_mode; } 2825 bool is_no_reg_mask(void) const { return _no_reg_mask; } 2826 bool uses_vl(void) const { return _uses_vl; } 2827 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; } 2828 bool is_evex_instruction(void) const { return _is_evex_instruction; } 2829 bool is_clear_context(void) const { return _is_clear_context; } 2830 bool is_extended_context(void) const { return _is_extended_context; } 2831 int get_vector_len(void) const { return _avx_vector_len; } 2832 int get_tuple_type(void) const { return _tuple_type; } 2833 int get_input_size(void) const { return _input_size_in_bits; } 2834 int get_evex_encoding(void) const { return _evex_encoding; } 2835 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; } 2836 2837 // Set the vector len manually 2838 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; } 2839 2840 // Set revert rex_vex_w for avx encoding 2841 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; } 2842 2843 // Set rex_vex_w based on state 2844 void set_rex_vex_w(bool state) { _rex_vex_w = state; } 2845 2846 // Set the instruction to be encoded in AVX mode 2847 void set_is_legacy_mode(void) { _legacy_mode = true; } 2848 2849 // Set the current instruction to be encoded as an EVEX instruction 2850 void set_is_evex_instruction(void) { _is_evex_instruction = true; } 2851 2852 // Internal encoding data used in compressed immediate offset programming 2853 void set_evex_encoding(int value) { _evex_encoding = value; } 2854 2855 // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components. 2856 // This method unsets it so that merge semantics are used instead. 2857 void reset_is_clear_context(void) { _is_clear_context = false; } 2858 2859 // Map back to current assembler so that we can manage object level association 2860 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; } 2861 2862 // Address modifiers used for compressed displacement calculation 2863 void set_address_attributes(int tuple_type, int input_size_in_bits); 2864 2865 // Set embedded opmask register specifier. 2866 void set_embedded_opmask_register_specifier(KRegister mask) { 2867 _embedded_opmask_register_specifier = (*mask).encoding() & 0x7; 2868 } 2869 2870 }; 2871 2872 #endif // CPU_X86_ASSEMBLER_X86_HPP