1 /*
2 * Copyright (c) 1997, 2021, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_X86_ASSEMBLER_X86_HPP
26 #define CPU_X86_ASSEMBLER_X86_HPP
27
28 #include "asm/register.hpp"
29 #include "utilities/powerOfTwo.hpp"
30
31 // Contains all the definitions needed for x86 assembly code generation.
32
33 // Calling convention
34 class Argument {
35 public:
36 enum {
37 #ifdef _LP64
38 #ifdef _WIN64
39 n_int_register_parameters_c = 4, // rcx, rdx, r8, r9 (c_rarg0, c_rarg1, ...)
40 n_float_register_parameters_c = 4, // xmm0 - xmm3 (c_farg0, c_farg1, ... )
41 n_int_register_returns_c = 1, // rax
42 n_float_register_returns_c = 1, // xmm0
43 #else
44 n_int_register_parameters_c = 6, // rdi, rsi, rdx, rcx, r8, r9 (c_rarg0, c_rarg1, ...)
45 n_float_register_parameters_c = 8, // xmm0 - xmm7 (c_farg0, c_farg1, ... )
46 n_int_register_returns_c = 2, // rax, rdx
47 n_float_register_returns_c = 2, // xmm0, xmm1
48 #endif // _WIN64
49 n_int_register_parameters_j = 6, // j_rarg0, j_rarg1, ...
50 n_float_register_parameters_j = 8 // j_farg0, j_farg1, ...
51 #else
52 n_register_parameters = 0 // 0 registers used to pass arguments
53 #endif // _LP64
54 };
55 };
56
57
58 #ifdef _LP64
59 // Symbolically name the register arguments used by the c calling convention.
60 // Windows is different from linux/solaris. So much for standards...
61
62 #ifdef _WIN64
63
64 REGISTER_DECLARATION(Register, c_rarg0, rcx);
65 REGISTER_DECLARATION(Register, c_rarg1, rdx);
66 REGISTER_DECLARATION(Register, c_rarg2, r8);
67 REGISTER_DECLARATION(Register, c_rarg3, r9);
68
69 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
70 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
71 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
72 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
73
74 #else
75
76 REGISTER_DECLARATION(Register, c_rarg0, rdi);
77 REGISTER_DECLARATION(Register, c_rarg1, rsi);
78 REGISTER_DECLARATION(Register, c_rarg2, rdx);
79 REGISTER_DECLARATION(Register, c_rarg3, rcx);
80 REGISTER_DECLARATION(Register, c_rarg4, r8);
81 REGISTER_DECLARATION(Register, c_rarg5, r9);
82
83 REGISTER_DECLARATION(XMMRegister, c_farg0, xmm0);
84 REGISTER_DECLARATION(XMMRegister, c_farg1, xmm1);
85 REGISTER_DECLARATION(XMMRegister, c_farg2, xmm2);
86 REGISTER_DECLARATION(XMMRegister, c_farg3, xmm3);
87 REGISTER_DECLARATION(XMMRegister, c_farg4, xmm4);
88 REGISTER_DECLARATION(XMMRegister, c_farg5, xmm5);
89 REGISTER_DECLARATION(XMMRegister, c_farg6, xmm6);
90 REGISTER_DECLARATION(XMMRegister, c_farg7, xmm7);
91
92 #endif // _WIN64
93
94 // Symbolically name the register arguments used by the Java calling convention.
95 // We have control over the convention for java so we can do what we please.
96 // What pleases us is to offset the java calling convention so that when
97 // we call a suitable jni method the arguments are lined up and we don't
98 // have to do little shuffling. A suitable jni method is non-static and a
99 // small number of arguments (two fewer args on windows)
100 //
101 // |-------------------------------------------------------|
102 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 |
103 // |-------------------------------------------------------|
104 // | rcx rdx r8 r9 rdi* rsi* | windows (* not a c_rarg)
105 // | rdi rsi rdx rcx r8 r9 | solaris/linux
106 // |-------------------------------------------------------|
107 // | j_rarg5 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 |
108 // |-------------------------------------------------------|
109
110 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
111 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
112 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
113 // Windows runs out of register args here
114 #ifdef _WIN64
115 REGISTER_DECLARATION(Register, j_rarg3, rdi);
116 REGISTER_DECLARATION(Register, j_rarg4, rsi);
117 #else
118 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
119 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
120 #endif /* _WIN64 */
121 REGISTER_DECLARATION(Register, j_rarg5, c_rarg0);
122
123 REGISTER_DECLARATION(XMMRegister, j_farg0, xmm0);
124 REGISTER_DECLARATION(XMMRegister, j_farg1, xmm1);
125 REGISTER_DECLARATION(XMMRegister, j_farg2, xmm2);
126 REGISTER_DECLARATION(XMMRegister, j_farg3, xmm3);
127 REGISTER_DECLARATION(XMMRegister, j_farg4, xmm4);
128 REGISTER_DECLARATION(XMMRegister, j_farg5, xmm5);
129 REGISTER_DECLARATION(XMMRegister, j_farg6, xmm6);
130 REGISTER_DECLARATION(XMMRegister, j_farg7, xmm7);
131
132 REGISTER_DECLARATION(Register, rscratch1, r10); // volatile
133 REGISTER_DECLARATION(Register, rscratch2, r11); // volatile
134
135 REGISTER_DECLARATION(Register, r12_heapbase, r12); // callee-saved
136 REGISTER_DECLARATION(Register, r15_thread, r15); // callee-saved
137
138 #else
139 // rscratch1 will apear in 32bit code that is dead but of course must compile
140 // Using noreg ensures if the dead code is incorrectly live and executed it
141 // will cause an assertion failure
142 #define rscratch1 noreg
143 #define rscratch2 noreg
144
145 #endif // _LP64
146
147 // JSR 292
148 // On x86, the SP does not have to be saved when invoking method handle intrinsics
149 // or compiled lambda forms. We indicate that by setting rbp_mh_SP_save to noreg.
150 REGISTER_DECLARATION(Register, rbp_mh_SP_save, noreg);
151
152 // Address is an abstraction used to represent a memory location
153 // using any of the amd64 addressing modes with one object.
154 //
155 // Note: A register location is represented via a Register, not
156 // via an address for efficiency & simplicity reasons.
157
158 class ArrayAddress;
159
160 class Address {
161 public:
162 enum ScaleFactor {
163 no_scale = -1,
164 times_1 = 0,
165 times_2 = 1,
166 times_4 = 2,
167 times_8 = 3,
168 times_ptr = LP64_ONLY(times_8) NOT_LP64(times_4)
169 };
170 static ScaleFactor times(int size) {
171 assert(size >= 1 && size <= 8 && is_power_of_2(size), "bad scale size");
172 if (size == 8) return times_8;
173 if (size == 4) return times_4;
174 if (size == 2) return times_2;
175 return times_1;
176 }
177 static int scale_size(ScaleFactor scale) {
178 assert(scale != no_scale, "");
179 assert(((1 << (int)times_1) == 1 &&
180 (1 << (int)times_2) == 2 &&
181 (1 << (int)times_4) == 4 &&
182 (1 << (int)times_8) == 8), "");
183 return (1 << (int)scale);
184 }
185
186 private:
187 Register _base;
188 Register _index;
189 XMMRegister _xmmindex;
190 ScaleFactor _scale;
191 int _disp;
192 bool _isxmmindex;
193 RelocationHolder _rspec;
194
195 // Easily misused constructors make them private
196 // %%% can we make these go away?
197 NOT_LP64(Address(address loc, RelocationHolder spec);)
198 Address(int disp, address loc, relocInfo::relocType rtype);
199 Address(int disp, address loc, RelocationHolder spec);
200
201 public:
202
203 int disp() { return _disp; }
204 // creation
205 Address()
206 : _base(noreg),
207 _index(noreg),
208 _xmmindex(xnoreg),
209 _scale(no_scale),
210 _disp(0),
211 _isxmmindex(false){
212 }
213
214 // No default displacement otherwise Register can be implicitly
215 // converted to 0(Register) which is quite a different animal.
216
217 Address(Register base, int disp)
218 : _base(base),
219 _index(noreg),
220 _xmmindex(xnoreg),
221 _scale(no_scale),
222 _disp(disp),
223 _isxmmindex(false){
224 }
225
226 Address(Register base, Register index, ScaleFactor scale, int disp = 0)
227 : _base (base),
228 _index(index),
229 _xmmindex(xnoreg),
230 _scale(scale),
231 _disp (disp),
232 _isxmmindex(false) {
233 assert(!index->is_valid() == (scale == Address::no_scale),
234 "inconsistent address");
235 }
236
237 Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
238 : _base (base),
239 _index(index.register_or_noreg()),
240 _xmmindex(xnoreg),
241 _scale(scale),
242 _disp (disp + (index.constant_or_zero() * scale_size(scale))),
243 _isxmmindex(false){
244 if (!index.is_register()) scale = Address::no_scale;
245 assert(!_index->is_valid() == (scale == Address::no_scale),
246 "inconsistent address");
247 }
248
249 Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
250 : _base (base),
251 _index(noreg),
252 _xmmindex(index),
253 _scale(scale),
254 _disp(disp),
255 _isxmmindex(true) {
256 assert(!index->is_valid() == (scale == Address::no_scale),
257 "inconsistent address");
258 }
259
260 // The following overloads are used in connection with the
261 // ByteSize type (see sizes.hpp). They simplify the use of
262 // ByteSize'd arguments in assembly code.
263
264 Address(Register base, ByteSize disp)
265 : Address(base, in_bytes(disp)) {}
266
267 Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
268 : Address(base, index, scale, in_bytes(disp)) {}
269
270 Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
271 : Address(base, index, scale, in_bytes(disp)) {}
272
273 Address plus_disp(int disp) const {
274 Address a = (*this);
275 a._disp += disp;
276 return a;
277 }
278 Address plus_disp(RegisterOrConstant disp, ScaleFactor scale = times_1) const {
279 Address a = (*this);
280 a._disp += disp.constant_or_zero() * scale_size(scale);
281 if (disp.is_register()) {
282 assert(!a.index()->is_valid(), "competing indexes");
283 a._index = disp.as_register();
284 a._scale = scale;
285 }
286 return a;
287 }
288 bool is_same_address(Address a) const {
289 // disregard _rspec
290 return _base == a._base && _disp == a._disp && _index == a._index && _scale == a._scale;
291 }
292
293 // accessors
294 bool uses(Register reg) const { return _base == reg || _index == reg; }
295 Register base() const { return _base; }
296 Register index() const { return _index; }
297 XMMRegister xmmindex() const { return _xmmindex; }
298 ScaleFactor scale() const { return _scale; }
299 int disp() const { return _disp; }
300 bool isxmmindex() const { return _isxmmindex; }
301
302 // Convert the raw encoding form into the form expected by the constructor for
303 // Address. An index of 4 (rsp) corresponds to having no index, so convert
304 // that to noreg for the Address constructor.
305 static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
306
307 static Address make_array(ArrayAddress);
308
309 private:
310 bool base_needs_rex() const {
311 return _base->is_valid() && _base->encoding() >= 8;
312 }
313
314 bool index_needs_rex() const {
315 return _index->is_valid() &&_index->encoding() >= 8;
316 }
317
318 bool xmmindex_needs_rex() const {
319 return _xmmindex->is_valid() && _xmmindex->encoding() >= 8;
320 }
321
322 relocInfo::relocType reloc() const { return _rspec.type(); }
323
324 friend class Assembler;
325 friend class MacroAssembler;
326 friend class LIR_Assembler; // base/index/scale/disp
327 };
328
329 //
330 // AddressLiteral has been split out from Address because operands of this type
331 // need to be treated specially on 32bit vs. 64bit platforms. By splitting it out
332 // the few instructions that need to deal with address literals are unique and the
333 // MacroAssembler does not have to implement every instruction in the Assembler
334 // in order to search for address literals that may need special handling depending
335 // on the instruction and the platform. As small step on the way to merging i486/amd64
336 // directories.
337 //
338 class AddressLiteral {
339 friend class ArrayAddress;
340 RelocationHolder _rspec;
341 // Typically we use AddressLiterals we want to use their rval
342 // However in some situations we want the lval (effect address) of the item.
343 // We provide a special factory for making those lvals.
344 bool _is_lval;
345
346 // If the target is far we'll need to load the ea of this to
347 // a register to reach it. Otherwise if near we can do rip
348 // relative addressing.
349
350 address _target;
351
352 protected:
353 // creation
354 AddressLiteral()
355 : _is_lval(false),
356 _target(NULL)
357 {}
358
359 public:
360
361
362 AddressLiteral(address target, relocInfo::relocType rtype);
363
364 AddressLiteral(address target, RelocationHolder const& rspec)
365 : _rspec(rspec),
366 _is_lval(false),
367 _target(target)
368 {}
369
370 AddressLiteral addr() {
371 AddressLiteral ret = *this;
372 ret._is_lval = true;
373 return ret;
374 }
375
376
377 private:
378
379 address target() { return _target; }
380 bool is_lval() { return _is_lval; }
381
382 relocInfo::relocType reloc() const { return _rspec.type(); }
383 const RelocationHolder& rspec() const { return _rspec; }
384
385 friend class Assembler;
386 friend class MacroAssembler;
387 friend class Address;
388 friend class LIR_Assembler;
389 };
390
391 // Convience classes
392 class RuntimeAddress: public AddressLiteral {
393
394 public:
395
396 RuntimeAddress(address target) : AddressLiteral(target, relocInfo::runtime_call_type) {}
397
398 };
399
400 class ExternalAddress: public AddressLiteral {
401 private:
402 static relocInfo::relocType reloc_for_target(address target) {
403 // Sometimes ExternalAddress is used for values which aren't
404 // exactly addresses, like the card table base.
405 // external_word_type can't be used for values in the first page
406 // so just skip the reloc in that case.
407 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
408 }
409
410 public:
411
412 ExternalAddress(address target) : AddressLiteral(target, reloc_for_target(target)) {}
413
414 };
415
416 class InternalAddress: public AddressLiteral {
417
418 public:
419
420 InternalAddress(address target) : AddressLiteral(target, relocInfo::internal_word_type) {}
421
422 };
423
424 // x86 can do array addressing as a single operation since disp can be an absolute
425 // address amd64 can't. We create a class that expresses the concept but does extra
426 // magic on amd64 to get the final result
427
428 class ArrayAddress {
429 private:
430
431 AddressLiteral _base;
432 Address _index;
433
434 public:
435
436 ArrayAddress() {};
437 ArrayAddress(AddressLiteral base, Address index): _base(base), _index(index) {};
438 AddressLiteral base() { return _base; }
439 Address index() { return _index; }
440
441 };
442
443 class InstructionAttr;
444
445 // 64-bit refect the fxsave size which is 512 bytes and the new xsave area on EVEX which is another 2176 bytes
446 // See fxsave and xsave(EVEX enabled) documentation for layout
447 const int FPUStateSizeInWords = NOT_LP64(27) LP64_ONLY(2688 / wordSize);
448
449 // The Intel x86/Amd64 Assembler: Pure assembler doing NO optimizations on the instruction
450 // level (e.g. mov rax, 0 is not translated into xor rax, rax!); i.e., what you write
451 // is what you get. The Assembler is generating code into a CodeBuffer.
452
453 class Assembler : public AbstractAssembler {
454 friend class AbstractAssembler; // for the non-virtual hack
455 friend class LIR_Assembler; // as_Address()
456 friend class StubGenerator;
457
458 public:
459 enum Condition { // The x86 condition codes used for conditional jumps/moves.
460 zero = 0x4,
461 notZero = 0x5,
462 equal = 0x4,
463 notEqual = 0x5,
464 less = 0xc,
465 lessEqual = 0xe,
466 greater = 0xf,
467 greaterEqual = 0xd,
468 below = 0x2,
469 belowEqual = 0x6,
470 above = 0x7,
471 aboveEqual = 0x3,
472 overflow = 0x0,
473 noOverflow = 0x1,
474 carrySet = 0x2,
475 carryClear = 0x3,
476 negative = 0x8,
477 positive = 0x9,
478 parity = 0xa,
479 noParity = 0xb
480 };
481
482 enum Prefix {
483 // segment overrides
484 CS_segment = 0x2e,
485 SS_segment = 0x36,
486 DS_segment = 0x3e,
487 ES_segment = 0x26,
488 FS_segment = 0x64,
489 GS_segment = 0x65,
490
491 REX = 0x40,
492
493 REX_B = 0x41,
494 REX_X = 0x42,
495 REX_XB = 0x43,
496 REX_R = 0x44,
497 REX_RB = 0x45,
498 REX_RX = 0x46,
499 REX_RXB = 0x47,
500
501 REX_W = 0x48,
502
503 REX_WB = 0x49,
504 REX_WX = 0x4A,
505 REX_WXB = 0x4B,
506 REX_WR = 0x4C,
507 REX_WRB = 0x4D,
508 REX_WRX = 0x4E,
509 REX_WRXB = 0x4F,
510
511 VEX_3bytes = 0xC4,
512 VEX_2bytes = 0xC5,
513 EVEX_4bytes = 0x62,
514 Prefix_EMPTY = 0x0
515 };
516
517 enum VexPrefix {
518 VEX_B = 0x20,
519 VEX_X = 0x40,
520 VEX_R = 0x80,
521 VEX_W = 0x80
522 };
523
524 enum ExexPrefix {
525 EVEX_F = 0x04,
526 EVEX_V = 0x08,
527 EVEX_Rb = 0x10,
528 EVEX_X = 0x40,
529 EVEX_Z = 0x80
530 };
531
532 enum VexSimdPrefix {
533 VEX_SIMD_NONE = 0x0,
534 VEX_SIMD_66 = 0x1,
535 VEX_SIMD_F3 = 0x2,
536 VEX_SIMD_F2 = 0x3
537 };
538
539 enum VexOpcode {
540 VEX_OPCODE_NONE = 0x0,
541 VEX_OPCODE_0F = 0x1,
542 VEX_OPCODE_0F_38 = 0x2,
543 VEX_OPCODE_0F_3A = 0x3,
544 VEX_OPCODE_MASK = 0x1F
545 };
546
547 enum AvxVectorLen {
548 AVX_128bit = 0x0,
549 AVX_256bit = 0x1,
550 AVX_512bit = 0x2,
551 AVX_NoVec = 0x4
552 };
553
554 enum EvexTupleType {
555 EVEX_FV = 0,
556 EVEX_HV = 4,
557 EVEX_FVM = 6,
558 EVEX_T1S = 7,
559 EVEX_T1F = 11,
560 EVEX_T2 = 13,
561 EVEX_T4 = 15,
562 EVEX_T8 = 17,
563 EVEX_HVM = 18,
564 EVEX_QVM = 19,
565 EVEX_OVM = 20,
566 EVEX_M128 = 21,
567 EVEX_DUP = 22,
568 EVEX_ETUP = 23
569 };
570
571 enum EvexInputSizeInBits {
572 EVEX_8bit = 0,
573 EVEX_16bit = 1,
574 EVEX_32bit = 2,
575 EVEX_64bit = 3,
576 EVEX_NObit = 4
577 };
578
579 enum WhichOperand {
580 // input to locate_operand, and format code for relocations
581 imm_operand = 0, // embedded 32-bit|64-bit immediate operand
582 disp32_operand = 1, // embedded 32-bit displacement or address
583 call32_operand = 2, // embedded 32-bit self-relative displacement
584 #ifndef _LP64
585 _WhichOperand_limit = 3
586 #else
587 narrow_oop_operand = 3, // embedded 32-bit immediate narrow oop
588 _WhichOperand_limit = 4
589 #endif
590 };
591
592 // Comparison predicates for integral types & FP types when using SSE
593 enum ComparisonPredicate {
594 eq = 0,
595 lt = 1,
596 le = 2,
597 _false = 3,
598 neq = 4,
599 nlt = 5,
600 nle = 6,
601 _true = 7
602 };
603
604 // Comparison predicates for FP types when using AVX
605 // O means ordered. U is unordered. When using ordered, any NaN comparison is false. Otherwise, it is true.
606 // S means signaling. Q means non-signaling. When signaling is true, instruction signals #IA on NaN.
607 enum ComparisonPredicateFP {
608 EQ_OQ = 0,
609 LT_OS = 1,
610 LE_OS = 2,
611 UNORD_Q = 3,
612 NEQ_UQ = 4,
613 NLT_US = 5,
614 NLE_US = 6,
615 ORD_Q = 7,
616 EQ_UQ = 8,
617 NGE_US = 9,
618 NGT_US = 0xA,
619 FALSE_OQ = 0XB,
620 NEQ_OQ = 0xC,
621 GE_OS = 0xD,
622 GT_OS = 0xE,
623 TRUE_UQ = 0xF,
624 EQ_OS = 0x10,
625 LT_OQ = 0x11,
626 LE_OQ = 0x12,
627 UNORD_S = 0x13,
628 NEQ_US = 0x14,
629 NLT_UQ = 0x15,
630 NLE_UQ = 0x16,
631 ORD_S = 0x17,
632 EQ_US = 0x18,
633 NGE_UQ = 0x19,
634 NGT_UQ = 0x1A,
635 FALSE_OS = 0x1B,
636 NEQ_OS = 0x1C,
637 GE_OQ = 0x1D,
638 GT_OQ = 0x1E,
639 TRUE_US =0x1F
640 };
641
642 enum Width {
643 B = 0,
644 W = 1,
645 D = 2,
646 Q = 3
647 };
648
649 //---< calculate length of instruction >---
650 // As instruction size can't be found out easily on x86/x64,
651 // we just use '4' for len and maxlen.
652 // instruction must start at passed address
653 static unsigned int instr_len(unsigned char *instr) { return 4; }
654
655 //---< longest instructions >---
656 // Max instruction length is not specified in architecture documentation.
657 // We could use a "safe enough" estimate (15), but just default to
658 // instruction length guess from above.
659 static unsigned int instr_maxlen() { return 4; }
660
661 // NOTE: The general philopsophy of the declarations here is that 64bit versions
662 // of instructions are freely declared without the need for wrapping them an ifdef.
663 // (Some dangerous instructions are ifdef's out of inappropriate jvm's.)
664 // In the .cpp file the implementations are wrapped so that they are dropped out
665 // of the resulting jvm. This is done mostly to keep the footprint of MINIMAL
666 // to the size it was prior to merging up the 32bit and 64bit assemblers.
667 //
668 // This does mean you'll get a linker/runtime error if you use a 64bit only instruction
669 // in a 32bit vm. This is somewhat unfortunate but keeps the ifdef noise down.
670
671 private:
672
673 bool _legacy_mode_bw;
674 bool _legacy_mode_dq;
675 bool _legacy_mode_vl;
676 bool _legacy_mode_vlbw;
677 NOT_LP64(bool _is_managed;)
678
679 class InstructionAttr *_attributes;
680
681 // 64bit prefixes
682 void prefix(Register reg);
683 void prefix(Register dst, Register src, Prefix p);
684 void prefix(Register dst, Address adr, Prefix p);
685
686 void prefix(Address adr);
687 void prefix(Address adr, Register reg, bool byteinst = false);
688 void prefix(Address adr, XMMRegister reg);
689
690 int prefix_and_encode(int reg_enc, bool byteinst = false);
691 int prefix_and_encode(int dst_enc, int src_enc) {
692 return prefix_and_encode(dst_enc, false, src_enc, false);
693 }
694 int prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte);
695
696 // Some prefixq variants always emit exactly one prefix byte, so besides a
697 // prefix-emitting method we provide a method to get the prefix byte to emit,
698 // which can then be folded into a byte stream.
699 int8_t get_prefixq(Address adr);
700 int8_t get_prefixq(Address adr, Register reg);
701
702 void prefixq(Address adr);
703 void prefixq(Address adr, Register reg);
704 void prefixq(Address adr, XMMRegister reg);
705
706 int prefixq_and_encode(int reg_enc);
707 int prefixq_and_encode(int dst_enc, int src_enc);
708
709 void rex_prefix(Address adr, XMMRegister xreg,
710 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
711 int rex_prefix_and_encode(int dst_enc, int src_enc,
712 VexSimdPrefix pre, VexOpcode opc, bool rex_w);
713
714 void vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc);
715
716 void evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v,
717 int nds_enc, VexSimdPrefix pre, VexOpcode opc);
718
719 void vex_prefix(Address adr, int nds_enc, int xreg_enc,
720 VexSimdPrefix pre, VexOpcode opc,
721 InstructionAttr *attributes);
722
723 int vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc,
724 VexSimdPrefix pre, VexOpcode opc,
725 InstructionAttr *attributes);
726
727 void simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
728 VexOpcode opc, InstructionAttr *attributes);
729
730 int simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
731 VexOpcode opc, InstructionAttr *attributes);
732
733 // Helper functions for groups of instructions
734 void emit_arith_b(int op1, int op2, Register dst, int imm8);
735
736 void emit_arith(int op1, int op2, Register dst, int32_t imm32);
737 // Force generation of a 4 byte immediate value even if it fits into 8bit
738 void emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32);
739 void emit_arith(int op1, int op2, Register dst, Register src);
740
741 bool emit_compressed_disp_byte(int &disp);
742
743 void emit_modrm(int mod, int dst_enc, int src_enc);
744 void emit_modrm_disp8(int mod, int dst_enc, int src_enc,
745 int disp);
746 void emit_modrm_sib(int mod, int dst_enc, int src_enc,
747 Address::ScaleFactor scale, int index_enc, int base_enc);
748 void emit_modrm_sib_disp8(int mod, int dst_enc, int src_enc,
749 Address::ScaleFactor scale, int index_enc, int base_enc,
750 int disp);
751
752 void emit_operand_helper(int reg_enc,
753 int base_enc, int index_enc, Address::ScaleFactor scale,
754 int disp,
755 RelocationHolder const& rspec,
756 int rip_relative_correction = 0);
757
758 void emit_operand(Register reg,
759 Register base, Register index, Address::ScaleFactor scale,
760 int disp,
761 RelocationHolder const& rspec,
762 int rip_relative_correction = 0);
763
764 void emit_operand(Register reg,
765 Register base, XMMRegister index, Address::ScaleFactor scale,
766 int disp,
767 RelocationHolder const& rspec);
768
769 void emit_operand(XMMRegister xreg,
770 Register base, XMMRegister xindex, Address::ScaleFactor scale,
771 int disp,
772 RelocationHolder const& rspec);
773
774 void emit_operand(Register reg, Address adr,
775 int rip_relative_correction = 0);
776
777 void emit_operand(XMMRegister reg,
778 Register base, Register index, Address::ScaleFactor scale,
779 int disp,
780 RelocationHolder const& rspec);
781
782 void emit_operand(XMMRegister reg, Address adr);
783
784 // Immediate-to-memory forms
785 void emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32);
786
787 protected:
788 #ifdef ASSERT
789 void check_relocation(RelocationHolder const& rspec, int format);
790 #endif
791
792 void emit_data(jint data, relocInfo::relocType rtype, int format);
793 void emit_data(jint data, RelocationHolder const& rspec, int format);
794 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
795 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
796
797 bool reachable(AddressLiteral adr) NOT_LP64({ return true;});
798
799 // These are all easily abused and hence protected
800
801 // 32BIT ONLY SECTION
802 #ifndef _LP64
803 // Make these disappear in 64bit mode since they would never be correct
804 void cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
805 void cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
806
807 void mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
808 void mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
809
810 void push_literal32(int32_t imm32, RelocationHolder const& rspec); // 32BIT ONLY
811 #else
812 // 64BIT ONLY SECTION
813 void mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec); // 64BIT ONLY
814
815 void cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec);
816 void cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec);
817
818 void mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec);
819 void mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec);
820 #endif // _LP64
821
822 // These are unique in that we are ensured by the caller that the 32bit
823 // relative in these instructions will always be able to reach the potentially
824 // 64bit address described by entry. Since they can take a 64bit address they
825 // don't have the 32 suffix like the other instructions in this class.
826
827 void call_literal(address entry, RelocationHolder const& rspec);
828 void jmp_literal(address entry, RelocationHolder const& rspec);
829
830 // Avoid using directly section
831 // Instructions in this section are actually usable by anyone without danger
832 // of failure but have performance issues that are addressed my enhanced
833 // instructions which will do the proper thing base on the particular cpu.
834 // We protect them because we don't trust you...
835
836 // Don't use next inc() and dec() methods directly. INC & DEC instructions
837 // could cause a partial flag stall since they don't set CF flag.
838 // Use MacroAssembler::decrement() & MacroAssembler::increment() methods
839 // which call inc() & dec() or add() & sub() in accordance with
840 // the product flag UseIncDec value.
841
842 void decl(Register dst);
843 void decl(Address dst);
844 void decq(Address dst);
845
846 void incl(Register dst);
847 void incl(Address dst);
848 void incq(Register dst);
849 void incq(Address dst);
850
851 // New cpus require use of movsd and movss to avoid partial register stall
852 // when loading from memory. But for old Opteron use movlpd instead of movsd.
853 // The selection is done in MacroAssembler::movdbl() and movflt().
854
855 // Move Scalar Single-Precision Floating-Point Values
856 void movss(XMMRegister dst, Address src);
857 void movss(XMMRegister dst, XMMRegister src);
858 void movss(Address dst, XMMRegister src);
859
860 // Move Scalar Double-Precision Floating-Point Values
861 void movsd(XMMRegister dst, Address src);
862 void movsd(XMMRegister dst, XMMRegister src);
863 void movsd(Address dst, XMMRegister src);
864 void movlpd(XMMRegister dst, Address src);
865
866 // New cpus require use of movaps and movapd to avoid partial register stall
867 // when moving between registers.
868 void movaps(XMMRegister dst, XMMRegister src);
869 void movapd(XMMRegister dst, XMMRegister src);
870
871 // End avoid using directly
872
873
874 // Instruction prefixes
875 void prefix(Prefix p);
876
877 public:
878
879 // Creation
880 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
881 init_attributes();
882 }
883
884 // Decoding
885 static address locate_operand(address inst, WhichOperand which);
886 static address locate_next_instruction(address inst);
887
888 // Utilities
889 static bool query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
890 int cur_tuple_type, int in_size_in_bits, int cur_encoding);
891
892 // Generic instructions
893 // Does 32bit or 64bit as needed for the platform. In some sense these
894 // belong in macro assembler but there is no need for both varieties to exist
895
896 void init_attributes(void);
897
898 void set_attributes(InstructionAttr *attributes) { _attributes = attributes; }
899 void clear_attributes(void) { _attributes = NULL; }
900
901 void set_managed(void) { NOT_LP64(_is_managed = true;) }
902 void clear_managed(void) { NOT_LP64(_is_managed = false;) }
903 bool is_managed(void) {
904 NOT_LP64(return _is_managed;)
905 LP64_ONLY(return false;) }
906
907 void lea(Register dst, Address src);
908
909 void mov(Register dst, Register src);
910
911 #ifdef _LP64
912 // support caching the result of some routines
913
914 // must be called before pusha(), popa(), vzeroupper() - checked with asserts
915 static void precompute_instructions();
916
917 void pusha_uncached();
918 void popa_uncached();
919 #endif
920 void vzeroupper_uncached();
921 void decq(Register dst);
922
923 void pusha();
924 void popa();
925
926 void pushf();
927 void popf();
928
929 void push(int32_t imm32);
930
931 void push(Register src);
932
933 void pop(Register dst);
934
935 // These are dummies to prevent surprise implicit conversions to Register
936 void push(void* v);
937 void pop(void* v);
938
939 // These do register sized moves/scans
940 void rep_mov();
941 void rep_stos();
942 void rep_stosb();
943 void repne_scan();
944 #ifdef _LP64
945 void repne_scanl();
946 #endif
947
948 // Vanilla instructions in lexical order
949
950 void adcl(Address dst, int32_t imm32);
951 void adcl(Address dst, Register src);
952 void adcl(Register dst, int32_t imm32);
953 void adcl(Register dst, Address src);
954 void adcl(Register dst, Register src);
955
956 void adcq(Register dst, int32_t imm32);
957 void adcq(Register dst, Address src);
958 void adcq(Register dst, Register src);
959
960 void addb(Address dst, int imm8);
961 void addw(Register dst, Register src);
962 void addw(Address dst, int imm16);
963
964 void addl(Address dst, int32_t imm32);
965 void addl(Address dst, Register src);
966 void addl(Register dst, int32_t imm32);
967 void addl(Register dst, Address src);
968 void addl(Register dst, Register src);
969
970 void addq(Address dst, int32_t imm32);
971 void addq(Address dst, Register src);
972 void addq(Register dst, int32_t imm32);
973 void addq(Register dst, Address src);
974 void addq(Register dst, Register src);
975
976 #ifdef _LP64
977 //Add Unsigned Integers with Carry Flag
978 void adcxq(Register dst, Register src);
979
980 //Add Unsigned Integers with Overflow Flag
981 void adoxq(Register dst, Register src);
982 #endif
983
984 void addr_nop_4();
985 void addr_nop_5();
986 void addr_nop_7();
987 void addr_nop_8();
988
989 // Add Scalar Double-Precision Floating-Point Values
990 void addsd(XMMRegister dst, Address src);
991 void addsd(XMMRegister dst, XMMRegister src);
992
993 // Add Scalar Single-Precision Floating-Point Values
994 void addss(XMMRegister dst, Address src);
995 void addss(XMMRegister dst, XMMRegister src);
996
997 // AES instructions
998 void aesdec(XMMRegister dst, Address src);
999 void aesdec(XMMRegister dst, XMMRegister src);
1000 void aesdeclast(XMMRegister dst, Address src);
1001 void aesdeclast(XMMRegister dst, XMMRegister src);
1002 void aesenc(XMMRegister dst, Address src);
1003 void aesenc(XMMRegister dst, XMMRegister src);
1004 void aesenclast(XMMRegister dst, Address src);
1005 void aesenclast(XMMRegister dst, XMMRegister src);
1006 // Vector AES instructions
1007 void vaesenc(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1008 void vaesenclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1009 void vaesdec(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1010 void vaesdeclast(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1011
1012 void andw(Register dst, Register src);
1013 void andb(Address dst, Register src);
1014
1015 void andl(Address dst, int32_t imm32);
1016 void andl(Register dst, int32_t imm32);
1017 void andl(Register dst, Address src);
1018 void andl(Register dst, Register src);
1019 void andl(Address dst, Register src);
1020
1021 void andq(Address dst, int32_t imm32);
1022 void andq(Register dst, int32_t imm32);
1023 void andq(Register dst, Address src);
1024 void andq(Register dst, Register src);
1025 void andq(Address dst, Register src);
1026
1027 // BMI instructions
1028 void andnl(Register dst, Register src1, Register src2);
1029 void andnl(Register dst, Register src1, Address src2);
1030 void andnq(Register dst, Register src1, Register src2);
1031 void andnq(Register dst, Register src1, Address src2);
1032
1033 void blsil(Register dst, Register src);
1034 void blsil(Register dst, Address src);
1035 void blsiq(Register dst, Register src);
1036 void blsiq(Register dst, Address src);
1037
1038 void blsmskl(Register dst, Register src);
1039 void blsmskl(Register dst, Address src);
1040 void blsmskq(Register dst, Register src);
1041 void blsmskq(Register dst, Address src);
1042
1043 void blsrl(Register dst, Register src);
1044 void blsrl(Register dst, Address src);
1045 void blsrq(Register dst, Register src);
1046 void blsrq(Register dst, Address src);
1047
1048 void bsfl(Register dst, Register src);
1049 void bsrl(Register dst, Register src);
1050
1051 #ifdef _LP64
1052 void bsfq(Register dst, Register src);
1053 void bsrq(Register dst, Register src);
1054 #endif
1055
1056 void bswapl(Register reg);
1057
1058 void bswapq(Register reg);
1059
1060 void call(Label& L, relocInfo::relocType rtype);
1061 void call(Register reg); // push pc; pc <- reg
1062 void call(Address adr); // push pc; pc <- adr
1063
1064 void cdql();
1065
1066 void cdqq();
1067
1068 void cld();
1069
1070 void clflush(Address adr);
1071 void clflushopt(Address adr);
1072 void clwb(Address adr);
1073
1074 void cmovl(Condition cc, Register dst, Register src);
1075 void cmovl(Condition cc, Register dst, Address src);
1076
1077 void cmovq(Condition cc, Register dst, Register src);
1078 void cmovq(Condition cc, Register dst, Address src);
1079
1080
1081 void cmpb(Address dst, int imm8);
1082
1083 void cmpl(Address dst, int32_t imm32);
1084
1085 void cmp(Register dst, int32_t imm32);
1086 void cmpl(Register dst, int32_t imm32);
1087 void cmpl(Register dst, Register src);
1088 void cmpl(Register dst, Address src);
1089
1090 void cmpq(Address dst, int32_t imm32);
1091 void cmpq(Address dst, Register src);
1092
1093 void cmpq(Register dst, int32_t imm32);
1094 void cmpq(Register dst, Register src);
1095 void cmpq(Register dst, Address src);
1096
1097 // these are dummies used to catch attempting to convert NULL to Register
1098 void cmpl(Register dst, void* junk); // dummy
1099 void cmpq(Register dst, void* junk); // dummy
1100
1101 void cmpw(Address dst, int imm16);
1102
1103 void cmpxchg8 (Address adr);
1104
1105 void cmpxchgb(Register reg, Address adr);
1106 void cmpxchgl(Register reg, Address adr);
1107
1108 void cmpxchgq(Register reg, Address adr);
1109 void cmpxchgw(Register reg, Address adr);
1110
1111 // Ordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
1112 void comisd(XMMRegister dst, Address src);
1113 void comisd(XMMRegister dst, XMMRegister src);
1114
1115 // Ordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
1116 void comiss(XMMRegister dst, Address src);
1117 void comiss(XMMRegister dst, XMMRegister src);
1118
1119 // Identify processor type and features
1120 void cpuid();
1121
1122 // CRC32C
1123 void crc32(Register crc, Register v, int8_t sizeInBytes);
1124 void crc32(Register crc, Address adr, int8_t sizeInBytes);
1125
1126 // Convert Scalar Double-Precision Floating-Point Value to Scalar Single-Precision Floating-Point Value
1127 void cvtsd2ss(XMMRegister dst, XMMRegister src);
1128 void cvtsd2ss(XMMRegister dst, Address src);
1129
1130 // Convert Doubleword Integer to Scalar Double-Precision Floating-Point Value
1131 void cvtsi2sdl(XMMRegister dst, Register src);
1132 void cvtsi2sdl(XMMRegister dst, Address src);
1133 void cvtsi2sdq(XMMRegister dst, Register src);
1134 void cvtsi2sdq(XMMRegister dst, Address src);
1135
1136 // Convert Doubleword Integer to Scalar Single-Precision Floating-Point Value
1137 void cvtsi2ssl(XMMRegister dst, Register src);
1138 void cvtsi2ssl(XMMRegister dst, Address src);
1139 void cvtsi2ssq(XMMRegister dst, Register src);
1140 void cvtsi2ssq(XMMRegister dst, Address src);
1141
1142 // Convert Packed Signed Doubleword Integers to Packed Double-Precision Floating-Point Value
1143 void cvtdq2pd(XMMRegister dst, XMMRegister src);
1144 void vcvtdq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1145
1146 // Convert Packed Signed Doubleword Integers to Packed Single-Precision Floating-Point Value
1147 void cvtdq2ps(XMMRegister dst, XMMRegister src);
1148 void vcvtdq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1149
1150 // Convert Scalar Single-Precision Floating-Point Value to Scalar Double-Precision Floating-Point Value
1151 void cvtss2sd(XMMRegister dst, XMMRegister src);
1152 void cvtss2sd(XMMRegister dst, Address src);
1153
1154 // Convert with Truncation Scalar Double-Precision Floating-Point Value to Doubleword Integer
1155 void cvttsd2sil(Register dst, Address src);
1156 void cvttsd2sil(Register dst, XMMRegister src);
1157 void cvttsd2siq(Register dst, Address src);
1158 void cvttsd2siq(Register dst, XMMRegister src);
1159
1160 // Convert with Truncation Scalar Single-Precision Floating-Point Value to Doubleword Integer
1161 void cvttss2sil(Register dst, XMMRegister src);
1162 void cvttss2siq(Register dst, XMMRegister src);
1163
1164 // Convert vector double to int
1165 void cvttpd2dq(XMMRegister dst, XMMRegister src);
1166
1167 // Convert vector float and double
1168 void vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len);
1169 void vcvtpd2ps(XMMRegister dst, XMMRegister src, int vector_len);
1170
1171 // Convert vector long to vector FP
1172 void evcvtqq2ps(XMMRegister dst, XMMRegister src, int vector_len);
1173 void evcvtqq2pd(XMMRegister dst, XMMRegister src, int vector_len);
1174
1175 // Evex casts with truncation
1176 void evpmovwb(XMMRegister dst, XMMRegister src, int vector_len);
1177 void evpmovdw(XMMRegister dst, XMMRegister src, int vector_len);
1178 void evpmovdb(XMMRegister dst, XMMRegister src, int vector_len);
1179 void evpmovqd(XMMRegister dst, XMMRegister src, int vector_len);
1180 void evpmovqb(XMMRegister dst, XMMRegister src, int vector_len);
1181 void evpmovqw(XMMRegister dst, XMMRegister src, int vector_len);
1182
1183 //Abs of packed Integer values
1184 void pabsb(XMMRegister dst, XMMRegister src);
1185 void pabsw(XMMRegister dst, XMMRegister src);
1186 void pabsd(XMMRegister dst, XMMRegister src);
1187 void vpabsb(XMMRegister dst, XMMRegister src, int vector_len);
1188 void vpabsw(XMMRegister dst, XMMRegister src, int vector_len);
1189 void vpabsd(XMMRegister dst, XMMRegister src, int vector_len);
1190 void evpabsq(XMMRegister dst, XMMRegister src, int vector_len);
1191
1192 // Divide Scalar Double-Precision Floating-Point Values
1193 void divsd(XMMRegister dst, Address src);
1194 void divsd(XMMRegister dst, XMMRegister src);
1195
1196 // Divide Scalar Single-Precision Floating-Point Values
1197 void divss(XMMRegister dst, Address src);
1198 void divss(XMMRegister dst, XMMRegister src);
1199
1200
1201 #ifndef _LP64
1202 private:
1203
1204 void emit_farith(int b1, int b2, int i);
1205
1206 public:
1207 void emms();
1208
1209 void fabs();
1210
1211 void fadd(int i);
1212
1213 void fadd_d(Address src);
1214 void fadd_s(Address src);
1215
1216 // "Alternate" versions of x87 instructions place result down in FPU
1217 // stack instead of on TOS
1218
1219 void fadda(int i); // "alternate" fadd
1220 void faddp(int i = 1);
1221
1222 void fchs();
1223
1224 void fcom(int i);
1225
1226 void fcomp(int i = 1);
1227 void fcomp_d(Address src);
1228 void fcomp_s(Address src);
1229
1230 void fcompp();
1231
1232 void fcos();
1233
1234 void fdecstp();
1235
1236 void fdiv(int i);
1237 void fdiv_d(Address src);
1238 void fdivr_s(Address src);
1239 void fdiva(int i); // "alternate" fdiv
1240 void fdivp(int i = 1);
1241
1242 void fdivr(int i);
1243 void fdivr_d(Address src);
1244 void fdiv_s(Address src);
1245
1246 void fdivra(int i); // "alternate" reversed fdiv
1247
1248 void fdivrp(int i = 1);
1249
1250 void ffree(int i = 0);
1251
1252 void fild_d(Address adr);
1253 void fild_s(Address adr);
1254
1255 void fincstp();
1256
1257 void finit();
1258
1259 void fist_s (Address adr);
1260 void fistp_d(Address adr);
1261 void fistp_s(Address adr);
1262
1263 void fld1();
1264
1265 void fld_d(Address adr);
1266 void fld_s(Address adr);
1267 void fld_s(int index);
1268
1269 void fldcw(Address src);
1270
1271 void fldenv(Address src);
1272
1273 void fldlg2();
1274
1275 void fldln2();
1276
1277 void fldz();
1278
1279 void flog();
1280 void flog10();
1281
1282 void fmul(int i);
1283
1284 void fmul_d(Address src);
1285 void fmul_s(Address src);
1286
1287 void fmula(int i); // "alternate" fmul
1288
1289 void fmulp(int i = 1);
1290
1291 void fnsave(Address dst);
1292
1293 void fnstcw(Address src);
1294
1295 void fnstsw_ax();
1296
1297 void fprem();
1298 void fprem1();
1299
1300 void frstor(Address src);
1301
1302 void fsin();
1303
1304 void fsqrt();
1305
1306 void fst_d(Address adr);
1307 void fst_s(Address adr);
1308
1309 void fstp_d(Address adr);
1310 void fstp_d(int index);
1311 void fstp_s(Address adr);
1312
1313 void fsub(int i);
1314 void fsub_d(Address src);
1315 void fsub_s(Address src);
1316
1317 void fsuba(int i); // "alternate" fsub
1318
1319 void fsubp(int i = 1);
1320
1321 void fsubr(int i);
1322 void fsubr_d(Address src);
1323 void fsubr_s(Address src);
1324
1325 void fsubra(int i); // "alternate" reversed fsub
1326
1327 void fsubrp(int i = 1);
1328
1329 void ftan();
1330
1331 void ftst();
1332
1333 void fucomi(int i = 1);
1334 void fucomip(int i = 1);
1335
1336 void fwait();
1337
1338 void fxch(int i = 1);
1339
1340 void fyl2x();
1341 void frndint();
1342 void f2xm1();
1343 void fldl2e();
1344 #endif // !_LP64
1345
1346 // operands that only take the original 32bit registers
1347 void emit_operand32(Register reg, Address adr);
1348
1349 void fld_x(Address adr); // extended-precision (80-bit) format
1350 void fstp_x(Address adr); // extended-precision (80-bit) format
1351 void fxrstor(Address src);
1352 void xrstor(Address src);
1353
1354 void fxsave(Address dst);
1355 void xsave(Address dst);
1356
1357 void hlt();
1358
1359 void idivl(Register src);
1360 void divl(Register src); // Unsigned division
1361
1362 #ifdef _LP64
1363 void idivq(Register src);
1364 #endif
1365
1366 void imull(Register src);
1367 void imull(Register dst, Register src);
1368 void imull(Register dst, Register src, int value);
1369 void imull(Register dst, Address src, int value);
1370 void imull(Register dst, Address src);
1371
1372 #ifdef _LP64
1373 void imulq(Register dst, Register src);
1374 void imulq(Register dst, Register src, int value);
1375 void imulq(Register dst, Address src, int value);
1376 void imulq(Register dst, Address src);
1377 void imulq(Register dst);
1378 #endif
1379
1380 // jcc is the generic conditional branch generator to run-
1381 // time routines, jcc is used for branches to labels. jcc
1382 // takes a branch opcode (cc) and a label (L) and generates
1383 // either a backward branch or a forward branch and links it
1384 // to the label fixup chain. Usage:
1385 //
1386 // Label L; // unbound label
1387 // jcc(cc, L); // forward branch to unbound label
1388 // bind(L); // bind label to the current pc
1389 // jcc(cc, L); // backward branch to bound label
1390 // bind(L); // illegal: a label may be bound only once
1391 //
1392 // Note: The same Label can be used for forward and backward branches
1393 // but it may be bound only once.
1394
1395 void jcc(Condition cc, Label& L, bool maybe_short = true);
1396
1397 // Conditional jump to a 8-bit offset to L.
1398 // WARNING: be very careful using this for forward jumps. If the label is
1399 // not bound within an 8-bit offset of this instruction, a run-time error
1400 // will occur.
1401
1402 // Use macro to record file and line number.
1403 #define jccb(cc, L) jccb_0(cc, L, __FILE__, __LINE__)
1404
1405 void jccb_0(Condition cc, Label& L, const char* file, int line);
1406
1407 void jmp(Address entry); // pc <- entry
1408
1409 // Label operations & relative jumps (PPUM Appendix D)
1410 void jmp(Label& L, bool maybe_short = true); // unconditional jump to L
1411
1412 void jmp(Register entry); // pc <- entry
1413
1414 // Unconditional 8-bit offset jump to L.
1415 // WARNING: be very careful using this for forward jumps. If the label is
1416 // not bound within an 8-bit offset of this instruction, a run-time error
1417 // will occur.
1418
1419 // Use macro to record file and line number.
1420 #define jmpb(L) jmpb_0(L, __FILE__, __LINE__)
1421
1422 void jmpb_0(Label& L, const char* file, int line);
1423
1424 void ldmxcsr( Address src );
1425
1426 void leal(Register dst, Address src);
1427
1428 void leaq(Register dst, Address src);
1429
1430 void lfence();
1431
1432 void lock();
1433 void size_prefix();
1434
1435 void lzcntl(Register dst, Register src);
1436
1437 #ifdef _LP64
1438 void lzcntq(Register dst, Register src);
1439 #endif
1440
1441 enum Membar_mask_bits {
1442 StoreStore = 1 << 3,
1443 LoadStore = 1 << 2,
1444 StoreLoad = 1 << 1,
1445 LoadLoad = 1 << 0
1446 };
1447
1448 // Serializes memory and blows flags
1449 void membar(Membar_mask_bits order_constraint);
1450
1451 void mfence();
1452 void sfence();
1453
1454 // Moves
1455
1456 void mov64(Register dst, int64_t imm64);
1457 void mov64(Register dst, int64_t imm64, relocInfo::relocType rtype, int format);
1458
1459 void movb(Address dst, Register src);
1460 void movb(Address dst, int imm8);
1461 void movb(Register dst, Address src);
1462
1463 void movddup(XMMRegister dst, XMMRegister src);
1464
1465 void kandbl(KRegister dst, KRegister src1, KRegister src2);
1466 void kandwl(KRegister dst, KRegister src1, KRegister src2);
1467 void kanddl(KRegister dst, KRegister src1, KRegister src2);
1468 void kandql(KRegister dst, KRegister src1, KRegister src2);
1469
1470 void korbl(KRegister dst, KRegister src1, KRegister src2);
1471 void korwl(KRegister dst, KRegister src1, KRegister src2);
1472 void kordl(KRegister dst, KRegister src1, KRegister src2);
1473 void korql(KRegister dst, KRegister src1, KRegister src2);
1474
1475 void kxorbl(KRegister dst, KRegister src1, KRegister src2);
1476 void kxorwl(KRegister dst, KRegister src1, KRegister src2);
1477 void kxordl(KRegister dst, KRegister src1, KRegister src2);
1478 void kxorql(KRegister dst, KRegister src1, KRegister src2);
1479 void kmovbl(KRegister dst, Register src);
1480 void kmovbl(Register dst, KRegister src);
1481 void kmovbl(KRegister dst, KRegister src);
1482 void kmovwl(KRegister dst, Register src);
1483 void kmovwl(KRegister dst, Address src);
1484 void kmovwl(Register dst, KRegister src);
1485 void kmovwl(Address dst, KRegister src);
1486 void kmovwl(KRegister dst, KRegister src);
1487 void kmovdl(KRegister dst, Register src);
1488 void kmovdl(Register dst, KRegister src);
1489 void kmovql(KRegister dst, KRegister src);
1490 void kmovql(Address dst, KRegister src);
1491 void kmovql(KRegister dst, Address src);
1492 void kmovql(KRegister dst, Register src);
1493 void kmovql(Register dst, KRegister src);
1494
1495 void knotbl(KRegister dst, KRegister src);
1496 void knotwl(KRegister dst, KRegister src);
1497 void knotdl(KRegister dst, KRegister src);
1498 void knotql(KRegister dst, KRegister src);
1499
1500 void kortestbl(KRegister dst, KRegister src);
1501 void kortestwl(KRegister dst, KRegister src);
1502 void kortestdl(KRegister dst, KRegister src);
1503 void kortestql(KRegister dst, KRegister src);
1504
1505 void kxnorbl(KRegister dst, KRegister src1, KRegister src2);
1506 void kshiftlbl(KRegister dst, KRegister src, int imm8);
1507 void kshiftrbl(KRegister dst, KRegister src, int imm8);
1508 void kshiftrwl(KRegister dst, KRegister src, int imm8);
1509 void kshiftrdl(KRegister dst, KRegister src, int imm8);
1510 void kshiftrql(KRegister dst, KRegister src, int imm8);
1511 void ktestq(KRegister src1, KRegister src2);
1512 void ktestd(KRegister src1, KRegister src2);
1513
1514 void ktestql(KRegister dst, KRegister src);
1515 void ktestdl(KRegister dst, KRegister src);
1516 void ktestwl(KRegister dst, KRegister src);
1517 void ktestbl(KRegister dst, KRegister src);
1518
1519 void movdl(XMMRegister dst, Register src);
1520 void movdl(Register dst, XMMRegister src);
1521 void movdl(XMMRegister dst, Address src);
1522 void movdl(Address dst, XMMRegister src);
1523
1524 // Move Double Quadword
1525 void movdq(XMMRegister dst, Register src);
1526 void movdq(Register dst, XMMRegister src);
1527
1528 // Move Aligned Double Quadword
1529 void movdqa(XMMRegister dst, XMMRegister src);
1530 void movdqa(XMMRegister dst, Address src);
1531
1532 // Move Unaligned Double Quadword
1533 void movdqu(Address dst, XMMRegister src);
1534 void movdqu(XMMRegister dst, Address src);
1535 void movdqu(XMMRegister dst, XMMRegister src);
1536
1537 // Move Unaligned 256bit Vector
1538 void vmovdqu(Address dst, XMMRegister src);
1539 void vmovdqu(XMMRegister dst, Address src);
1540 void vmovdqu(XMMRegister dst, XMMRegister src);
1541
1542 // Move Unaligned 512bit Vector
1543 void evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len);
1544 void evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len);
1545 void evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len);
1546 void evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1547 void evmovdqub(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1548 void evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len);
1549 void evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1550 void evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len);
1551 void evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1552 void evmovdqul(Address dst, XMMRegister src, int vector_len);
1553 void evmovdqul(XMMRegister dst, Address src, int vector_len);
1554 void evmovdqul(XMMRegister dst, XMMRegister src, int vector_len);
1555 void evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1556 void evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1557 void evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1558 void evmovdquq(Address dst, XMMRegister src, int vector_len);
1559 void evmovdquq(XMMRegister dst, Address src, int vector_len);
1560 void evmovdquq(XMMRegister dst, XMMRegister src, int vector_len);
1561 void evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1562 void evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
1563 void evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
1564
1565 // Move lower 64bit to high 64bit in 128bit register
1566 void movlhps(XMMRegister dst, XMMRegister src);
1567
1568 void movl(Register dst, int32_t imm32);
1569 void movl(Address dst, int32_t imm32);
1570 void movl(Register dst, Register src);
1571 void movl(Register dst, Address src);
1572 void movl(Address dst, Register src);
1573
1574 // These dummies prevent using movl from converting a zero (like NULL) into Register
1575 // by giving the compiler two choices it can't resolve
1576
1577 void movl(Address dst, void* junk);
1578 void movl(Register dst, void* junk);
1579
1580 #ifdef _LP64
1581 void movq(Register dst, Register src);
1582 void movq(Register dst, Address src);
1583 void movq(Address dst, Register src);
1584 void movq(Address dst, int32_t imm32);
1585 void movq(Register dst, int32_t imm32);
1586
1587 // These dummies prevent using movq from converting a zero (like NULL) into Register
1588 // by giving the compiler two choices it can't resolve
1589
1590 void movq(Address dst, void* dummy);
1591 void movq(Register dst, void* dummy);
1592 #endif
1593
1594 // Move Quadword
1595 void movq(Address dst, XMMRegister src);
1596 void movq(XMMRegister dst, Address src);
1597 void movq(XMMRegister dst, XMMRegister src);
1598 void movq(Register dst, XMMRegister src);
1599 void movq(XMMRegister dst, Register src);
1600
1601 void movsbl(Register dst, Address src);
1602 void movsbl(Register dst, Register src);
1603
1604 #ifdef _LP64
1605 void movsbq(Register dst, Address src);
1606 void movsbq(Register dst, Register src);
1607
1608 // Move signed 32bit immediate to 64bit extending sign
1609 void movslq(Address dst, int32_t imm64);
1610 void movslq(Register dst, int32_t imm64);
1611
1612 void movslq(Register dst, Address src);
1613 void movslq(Register dst, Register src);
1614 void movslq(Register dst, void* src); // Dummy declaration to cause NULL to be ambiguous
1615 #endif
1616
1617 void movswl(Register dst, Address src);
1618 void movswl(Register dst, Register src);
1619
1620 #ifdef _LP64
1621 void movswq(Register dst, Address src);
1622 void movswq(Register dst, Register src);
1623 #endif
1624
1625 void movw(Address dst, int imm16);
1626 void movw(Register dst, Address src);
1627 void movw(Address dst, Register src);
1628
1629 void movzbl(Register dst, Address src);
1630 void movzbl(Register dst, Register src);
1631
1632 #ifdef _LP64
1633 void movzbq(Register dst, Address src);
1634 void movzbq(Register dst, Register src);
1635 #endif
1636
1637 void movzwl(Register dst, Address src);
1638 void movzwl(Register dst, Register src);
1639
1640 #ifdef _LP64
1641 void movzwq(Register dst, Address src);
1642 void movzwq(Register dst, Register src);
1643 #endif
1644
1645 // Unsigned multiply with RAX destination register
1646 void mull(Address src);
1647 void mull(Register src);
1648
1649 #ifdef _LP64
1650 void mulq(Address src);
1651 void mulq(Register src);
1652 void mulxq(Register dst1, Register dst2, Register src);
1653 #endif
1654
1655 // Multiply Scalar Double-Precision Floating-Point Values
1656 void mulsd(XMMRegister dst, Address src);
1657 void mulsd(XMMRegister dst, XMMRegister src);
1658
1659 // Multiply Scalar Single-Precision Floating-Point Values
1660 void mulss(XMMRegister dst, Address src);
1661 void mulss(XMMRegister dst, XMMRegister src);
1662
1663 void negl(Register dst);
1664 void negl(Address dst);
1665
1666 #ifdef _LP64
1667 void negq(Register dst);
1668 void negq(Address dst);
1669 #endif
1670
1671 void nop(int i = 1);
1672
1673 void notl(Register dst);
1674
1675 #ifdef _LP64
1676 void notq(Register dst);
1677
1678 void btsq(Address dst, int imm8);
1679 void btrq(Address dst, int imm8);
1680 #endif
1681
1682 void orw(Register dst, Register src);
1683
1684 void orl(Address dst, int32_t imm32);
1685 void orl(Register dst, int32_t imm32);
1686 void orl(Register dst, Address src);
1687 void orl(Register dst, Register src);
1688 void orl(Address dst, Register src);
1689
1690 void orb(Address dst, int imm8);
1691 void orb(Address dst, Register src);
1692
1693 void orq(Address dst, int32_t imm32);
1694 void orq(Address dst, Register src);
1695 void orq(Register dst, int32_t imm32);
1696 void orq(Register dst, Address src);
1697 void orq(Register dst, Register src);
1698
1699 // Pack with signed saturation
1700 void packsswb(XMMRegister dst, XMMRegister src);
1701 void vpacksswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1702 void packssdw(XMMRegister dst, XMMRegister src);
1703 void vpackssdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1704
1705 // Pack with unsigned saturation
1706 void packuswb(XMMRegister dst, XMMRegister src);
1707 void packuswb(XMMRegister dst, Address src);
1708 void packusdw(XMMRegister dst, XMMRegister src);
1709 void vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1710 void vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1711
1712 // Permutations
1713 void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1714 void vpermq(XMMRegister dst, XMMRegister src, int imm8);
1715 void vpermq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1716 void vpermb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1717 void vpermb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1718 void vpermw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1719 void vpermd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1720 void vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1721 void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1722 void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1723 void vpermilps(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1724 void vpermilpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1725 void vpermpd(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
1726 void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1727 void evpermt2b(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1728 void evpmultishiftqb(XMMRegister dst, XMMRegister ctl, XMMRegister src, int vector_len);
1729
1730 void pause();
1731
1732 // Undefined Instruction
1733 void ud2();
1734
1735 // SSE4.2 string instructions
1736 void pcmpestri(XMMRegister xmm1, XMMRegister xmm2, int imm8);
1737 void pcmpestri(XMMRegister xmm1, Address src, int imm8);
1738
1739 void pcmpeqb(XMMRegister dst, XMMRegister src);
1740 void vpcmpCCbwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1741
1742 void vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1743 void evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1744 void evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1745 void evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1746
1747 void vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1748 void evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1749 void evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1750
1751 void evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len);
1752 void evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len);
1753
1754 void pcmpeqw(XMMRegister dst, XMMRegister src);
1755 void vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1756 void evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1757 void evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1758
1759 void vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1760
1761 void pcmpeqd(XMMRegister dst, XMMRegister src);
1762 void vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1763 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len);
1764 void evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len);
1765
1766 void pcmpeqq(XMMRegister dst, XMMRegister src);
1767 void vpcmpCCq(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, int vector_len);
1768 void vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1769 void evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len);
1770 void evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len);
1771
1772 void pcmpgtq(XMMRegister dst, XMMRegister src);
1773 void vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1774
1775 void pmovmskb(Register dst, XMMRegister src);
1776 void vpmovmskb(Register dst, XMMRegister src, int vec_enc);
1777 void vpmaskmovd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
1778
1779 // SSE 4.1 extract
1780 void pextrd(Register dst, XMMRegister src, int imm8);
1781 void pextrq(Register dst, XMMRegister src, int imm8);
1782 void pextrd(Address dst, XMMRegister src, int imm8);
1783 void pextrq(Address dst, XMMRegister src, int imm8);
1784 void pextrb(Register dst, XMMRegister src, int imm8);
1785 void pextrb(Address dst, XMMRegister src, int imm8);
1786 // SSE 2 extract
1787 void pextrw(Register dst, XMMRegister src, int imm8);
1788 void pextrw(Address dst, XMMRegister src, int imm8);
1789
1790 // SSE 4.1 insert
1791 void pinsrd(XMMRegister dst, Register src, int imm8);
1792 void pinsrq(XMMRegister dst, Register src, int imm8);
1793 void pinsrb(XMMRegister dst, Register src, int imm8);
1794 void pinsrd(XMMRegister dst, Address src, int imm8);
1795 void pinsrq(XMMRegister dst, Address src, int imm8);
1796 void pinsrb(XMMRegister dst, Address src, int imm8);
1797 void insertps(XMMRegister dst, XMMRegister src, int imm8);
1798 // SSE 2 insert
1799 void pinsrw(XMMRegister dst, Register src, int imm8);
1800 void pinsrw(XMMRegister dst, Address src, int imm8);
1801
1802 // AVX insert
1803 void vpinsrd(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1804 void vpinsrb(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1805 void vpinsrq(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1806 void vpinsrw(XMMRegister dst, XMMRegister nds, Register src, int imm8);
1807 void vinsertps(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
1808
1809 // Zero extend moves
1810 void pmovzxbw(XMMRegister dst, XMMRegister src);
1811 void pmovzxbw(XMMRegister dst, Address src);
1812 void pmovzxbd(XMMRegister dst, XMMRegister src);
1813 void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
1814 void pmovzxdq(XMMRegister dst, XMMRegister src);
1815 void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
1816 void vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len);
1817 void vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len);
1818 void vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len);
1819 void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
1820
1821 // Sign extend moves
1822 void pmovsxbd(XMMRegister dst, XMMRegister src);
1823 void pmovsxbq(XMMRegister dst, XMMRegister src);
1824 void pmovsxbw(XMMRegister dst, XMMRegister src);
1825 void pmovsxwd(XMMRegister dst, XMMRegister src);
1826 void vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len);
1827 void vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len);
1828 void vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len);
1829 void vpmovsxwd(XMMRegister dst, XMMRegister src, int vector_len);
1830 void vpmovsxwq(XMMRegister dst, XMMRegister src, int vector_len);
1831 void vpmovsxdq(XMMRegister dst, XMMRegister src, int vector_len);
1832
1833 void evpmovwb(Address dst, XMMRegister src, int vector_len);
1834 void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
1835
1836 void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
1837
1838 void evpmovdb(Address dst, XMMRegister src, int vector_len);
1839
1840 // Multiply add
1841 void pmaddwd(XMMRegister dst, XMMRegister src);
1842 void vpmaddwd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1843 void vpmaddubsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
1844
1845 // Multiply add accumulate
1846 void evpdpwssd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1847
1848 #ifndef _LP64 // no 32bit push/pop on amd64
1849 void popl(Address dst);
1850 #endif
1851
1852 #ifdef _LP64
1853 void popq(Address dst);
1854 void popq(Register dst);
1855 #endif
1856
1857 void popcntl(Register dst, Address src);
1858 void popcntl(Register dst, Register src);
1859
1860 void vpopcntd(XMMRegister dst, XMMRegister src, int vector_len);
1861
1862 #ifdef _LP64
1863 void popcntq(Register dst, Address src);
1864 void popcntq(Register dst, Register src);
1865 #endif
1866
1867 // Prefetches (SSE, SSE2, 3DNOW only)
1868
1869 void prefetchnta(Address src);
1870 void prefetchr(Address src);
1871 void prefetcht0(Address src);
1872 void prefetcht1(Address src);
1873 void prefetcht2(Address src);
1874 void prefetchw(Address src);
1875
1876 // Shuffle Bytes
1877 void pshufb(XMMRegister dst, XMMRegister src);
1878 void pshufb(XMMRegister dst, Address src);
1879 void vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1880
1881 // Shuffle Packed Doublewords
1882 void pshufd(XMMRegister dst, XMMRegister src, int mode);
1883 void pshufd(XMMRegister dst, Address src, int mode);
1884 void vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len);
1885
1886 // Shuffle Packed High/Low Words
1887 void pshufhw(XMMRegister dst, XMMRegister src, int mode);
1888 void pshuflw(XMMRegister dst, XMMRegister src, int mode);
1889 void pshuflw(XMMRegister dst, Address src, int mode);
1890
1891 //shuffle floats and doubles
1892 void pshufps(XMMRegister, XMMRegister, int);
1893 void pshufpd(XMMRegister, XMMRegister, int);
1894 void vpshufps(XMMRegister, XMMRegister, XMMRegister, int, int);
1895 void vpshufpd(XMMRegister, XMMRegister, XMMRegister, int, int);
1896
1897 // Shuffle packed values at 128 bit granularity
1898 void evshufi64x2(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
1899
1900 // Shift Right by bytes Logical DoubleQuadword Immediate
1901 void psrldq(XMMRegister dst, int shift);
1902 // Shift Left by bytes Logical DoubleQuadword Immediate
1903 void pslldq(XMMRegister dst, int shift);
1904
1905 // Logical Compare 128bit
1906 void ptest(XMMRegister dst, XMMRegister src);
1907 void ptest(XMMRegister dst, Address src);
1908 // Logical Compare 256bit
1909 void vptest(XMMRegister dst, XMMRegister src);
1910 void vptest(XMMRegister dst, Address src);
1911
1912 void evptestmb(KRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
1913
1914 // Vector compare
1915 void vptest(XMMRegister dst, XMMRegister src, int vector_len);
1916
1917 // Interleave Low Bytes
1918 void punpcklbw(XMMRegister dst, XMMRegister src);
1919 void punpcklbw(XMMRegister dst, Address src);
1920
1921 // Interleave Low Doublewords
1922 void punpckldq(XMMRegister dst, XMMRegister src);
1923 void punpckldq(XMMRegister dst, Address src);
1924
1925 // Interleave Low Quadwords
1926 void punpcklqdq(XMMRegister dst, XMMRegister src);
1927
1928 #ifndef _LP64 // no 32bit push/pop on amd64
1929 void pushl(Address src);
1930 #endif
1931
1932 void pushq(Address src);
1933
1934 void rcll(Register dst, int imm8);
1935
1936 void rclq(Register dst, int imm8);
1937
1938 void rcrq(Register dst, int imm8);
1939
1940 void rcpps(XMMRegister dst, XMMRegister src);
1941
1942 void rcpss(XMMRegister dst, XMMRegister src);
1943
1944 void rdtsc();
1945
1946 void ret(int imm16);
1947
1948 void roll(Register dst);
1949
1950 void roll(Register dst, int imm8);
1951
1952 void rorl(Register dst);
1953
1954 void rorl(Register dst, int imm8);
1955
1956 #ifdef _LP64
1957 void rolq(Register dst);
1958 void rolq(Register dst, int imm8);
1959 void rorq(Register dst);
1960 void rorq(Register dst, int imm8);
1961 void rorxq(Register dst, Register src, int imm8);
1962 void rorxd(Register dst, Register src, int imm8);
1963 #endif
1964
1965 void sahf();
1966
1967 void sall(Register dst, int imm8);
1968 void sall(Register dst);
1969 void sall(Address dst, int imm8);
1970 void sall(Address dst);
1971
1972 void sarl(Address dst, int imm8);
1973 void sarl(Address dst);
1974 void sarl(Register dst, int imm8);
1975 void sarl(Register dst);
1976
1977 #ifdef _LP64
1978 void salq(Register dst, int imm8);
1979 void salq(Register dst);
1980 void salq(Address dst, int imm8);
1981 void salq(Address dst);
1982
1983 void sarq(Address dst, int imm8);
1984 void sarq(Address dst);
1985 void sarq(Register dst, int imm8);
1986 void sarq(Register dst);
1987 #endif
1988
1989 void sbbl(Address dst, int32_t imm32);
1990 void sbbl(Register dst, int32_t imm32);
1991 void sbbl(Register dst, Address src);
1992 void sbbl(Register dst, Register src);
1993
1994 void sbbq(Address dst, int32_t imm32);
1995 void sbbq(Register dst, int32_t imm32);
1996 void sbbq(Register dst, Address src);
1997 void sbbq(Register dst, Register src);
1998
1999 void setb(Condition cc, Register dst);
2000
2001 void sete(Register dst);
2002 void setl(Register dst);
2003 void setne(Register dst);
2004
2005 void palignr(XMMRegister dst, XMMRegister src, int imm8);
2006 void vpalignr(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2007 void evalignq(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2008
2009 void pblendw(XMMRegister dst, XMMRegister src, int imm8);
2010 void vblendps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int imm8, int vector_len);
2011
2012 void sha1rnds4(XMMRegister dst, XMMRegister src, int imm8);
2013 void sha1nexte(XMMRegister dst, XMMRegister src);
2014 void sha1msg1(XMMRegister dst, XMMRegister src);
2015 void sha1msg2(XMMRegister dst, XMMRegister src);
2016 // xmm0 is implicit additional source to the following instruction.
2017 void sha256rnds2(XMMRegister dst, XMMRegister src);
2018 void sha256msg1(XMMRegister dst, XMMRegister src);
2019 void sha256msg2(XMMRegister dst, XMMRegister src);
2020
2021 void shldl(Register dst, Register src);
2022 void shldl(Register dst, Register src, int8_t imm8);
2023 void shrdl(Register dst, Register src);
2024 void shrdl(Register dst, Register src, int8_t imm8);
2025
2026 void shll(Register dst, int imm8);
2027 void shll(Register dst);
2028
2029 void shlq(Register dst, int imm8);
2030 void shlq(Register dst);
2031
2032 void shrl(Register dst, int imm8);
2033 void shrl(Register dst);
2034 void shrl(Address dst);
2035 void shrl(Address dst, int imm8);
2036
2037 void shrq(Register dst, int imm8);
2038 void shrq(Register dst);
2039 void shrq(Address dst);
2040 void shrq(Address dst, int imm8);
2041
2042 void smovl(); // QQQ generic?
2043
2044 // Compute Square Root of Scalar Double-Precision Floating-Point Value
2045 void sqrtsd(XMMRegister dst, Address src);
2046 void sqrtsd(XMMRegister dst, XMMRegister src);
2047
2048 void roundsd(XMMRegister dst, Address src, int32_t rmode);
2049 void roundsd(XMMRegister dst, XMMRegister src, int32_t rmode);
2050
2051 // Compute Square Root of Scalar Single-Precision Floating-Point Value
2052 void sqrtss(XMMRegister dst, Address src);
2053 void sqrtss(XMMRegister dst, XMMRegister src);
2054
2055 void std();
2056
2057 void stmxcsr( Address dst );
2058
2059 void subl(Address dst, int32_t imm32);
2060 void subl(Address dst, Register src);
2061 void subl(Register dst, int32_t imm32);
2062 void subl(Register dst, Address src);
2063 void subl(Register dst, Register src);
2064
2065 void subq(Address dst, int32_t imm32);
2066 void subq(Address dst, Register src);
2067 void subq(Register dst, int32_t imm32);
2068 void subq(Register dst, Address src);
2069 void subq(Register dst, Register src);
2070
2071 // Force generation of a 4 byte immediate value even if it fits into 8bit
2072 void subl_imm32(Register dst, int32_t imm32);
2073 void subq_imm32(Register dst, int32_t imm32);
2074
2075 // Subtract Scalar Double-Precision Floating-Point Values
2076 void subsd(XMMRegister dst, Address src);
2077 void subsd(XMMRegister dst, XMMRegister src);
2078
2079 // Subtract Scalar Single-Precision Floating-Point Values
2080 void subss(XMMRegister dst, Address src);
2081 void subss(XMMRegister dst, XMMRegister src);
2082
2083 void testb(Register dst, int imm8);
2084 void testb(Address dst, int imm8);
2085
2086 void testl(Register dst, int32_t imm32);
2087 void testl(Register dst, Register src);
2088 void testl(Register dst, Address src);
2089
2090 void testq(Address dst, int32_t imm32);
2091 void testq(Register dst, int32_t imm32);
2092 void testq(Register dst, Register src);
2093 void testq(Register dst, Address src);
2094
2095 // BMI - count trailing zeros
2096 void tzcntl(Register dst, Register src);
2097 void tzcntq(Register dst, Register src);
2098
2099 // Unordered Compare Scalar Double-Precision Floating-Point Values and set EFLAGS
2100 void ucomisd(XMMRegister dst, Address src);
2101 void ucomisd(XMMRegister dst, XMMRegister src);
2102
2103 // Unordered Compare Scalar Single-Precision Floating-Point Values and set EFLAGS
2104 void ucomiss(XMMRegister dst, Address src);
2105 void ucomiss(XMMRegister dst, XMMRegister src);
2106
2107 void xabort(int8_t imm8);
2108
2109 void xaddb(Address dst, Register src);
2110 void xaddw(Address dst, Register src);
2111 void xaddl(Address dst, Register src);
2112 void xaddq(Address dst, Register src);
2113
2114 void xbegin(Label& abort, relocInfo::relocType rtype = relocInfo::none);
2115
2116 void xchgb(Register reg, Address adr);
2117 void xchgw(Register reg, Address adr);
2118 void xchgl(Register reg, Address adr);
2119 void xchgl(Register dst, Register src);
2120
2121 void xchgq(Register reg, Address adr);
2122 void xchgq(Register dst, Register src);
2123
2124 void xend();
2125
2126 // Get Value of Extended Control Register
2127 void xgetbv();
2128
2129 void xorl(Register dst, int32_t imm32);
2130 void xorl(Address dst, int32_t imm32);
2131 void xorl(Register dst, Address src);
2132 void xorl(Register dst, Register src);
2133 void xorl(Address dst, Register src);
2134
2135 void xorb(Address dst, Register src);
2136 void xorb(Register dst, Address src);
2137 void xorw(Register dst, Register src);
2138
2139 void xorq(Register dst, Address src);
2140 void xorq(Address dst, int32_t imm32);
2141 void xorq(Register dst, Register src);
2142 void xorq(Register dst, int32_t imm32);
2143 void xorq(Address dst, Register src);
2144
2145 void set_byte_if_not_zero(Register dst); // sets reg to 1 if not zero, otherwise 0
2146
2147 // AVX 3-operands scalar instructions (encoded with VEX prefix)
2148
2149 void vaddsd(XMMRegister dst, XMMRegister nds, Address src);
2150 void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2151 void vaddss(XMMRegister dst, XMMRegister nds, Address src);
2152 void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2153 void vdivsd(XMMRegister dst, XMMRegister nds, Address src);
2154 void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2155 void vdivss(XMMRegister dst, XMMRegister nds, Address src);
2156 void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2157 void vfmadd231sd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2158 void vfmadd231ss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2159 void vmulsd(XMMRegister dst, XMMRegister nds, Address src);
2160 void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2161 void vmulss(XMMRegister dst, XMMRegister nds, Address src);
2162 void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2163 void vsubsd(XMMRegister dst, XMMRegister nds, Address src);
2164 void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2165 void vsubss(XMMRegister dst, XMMRegister nds, Address src);
2166 void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2167
2168 void vmaxss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2169 void vmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2170 void vminss(XMMRegister dst, XMMRegister nds, XMMRegister src);
2171 void vminsd(XMMRegister dst, XMMRegister nds, XMMRegister src);
2172
2173 void shlxl(Register dst, Register src1, Register src2);
2174 void shlxq(Register dst, Register src1, Register src2);
2175 void shrxl(Register dst, Register src1, Register src2);
2176 void shrxq(Register dst, Register src1, Register src2);
2177
2178 void bzhiq(Register dst, Register src1, Register src2);
2179
2180 //====================VECTOR ARITHMETIC=====================================
2181 // Add Packed Floating-Point Values
2182 void addpd(XMMRegister dst, XMMRegister src);
2183 void addpd(XMMRegister dst, Address src);
2184 void addps(XMMRegister dst, XMMRegister src);
2185 void vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2186 void vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2187 void vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2188 void vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2189
2190 // Subtract Packed Floating-Point Values
2191 void subpd(XMMRegister dst, XMMRegister src);
2192 void subps(XMMRegister dst, XMMRegister src);
2193 void vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2194 void vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2195 void vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2196 void vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2197
2198 // Multiply Packed Floating-Point Values
2199 void mulpd(XMMRegister dst, XMMRegister src);
2200 void mulpd(XMMRegister dst, Address src);
2201 void mulps(XMMRegister dst, XMMRegister src);
2202 void vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2203 void vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2204 void vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2205 void vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2206
2207 void vfmadd231pd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2208 void vfmadd231ps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2209 void vfmadd231pd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2210 void vfmadd231ps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2211
2212 // Divide Packed Floating-Point Values
2213 void divpd(XMMRegister dst, XMMRegister src);
2214 void divps(XMMRegister dst, XMMRegister src);
2215 void vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2216 void vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2217 void vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2218 void vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2219
2220 // Sqrt Packed Floating-Point Values
2221 void vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len);
2222 void vsqrtpd(XMMRegister dst, Address src, int vector_len);
2223 void vsqrtps(XMMRegister dst, XMMRegister src, int vector_len);
2224 void vsqrtps(XMMRegister dst, Address src, int vector_len);
2225
2226 // Round Packed Double precision value.
2227 void vroundpd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2228 void vroundpd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2229 void vrndscalepd(XMMRegister dst, XMMRegister src, int32_t rmode, int vector_len);
2230 void vrndscalepd(XMMRegister dst, Address src, int32_t rmode, int vector_len);
2231
2232 // Bitwise Logical AND of Packed Floating-Point Values
2233 void andpd(XMMRegister dst, XMMRegister src);
2234 void andps(XMMRegister dst, XMMRegister src);
2235 void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2236 void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2237 void vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2238 void vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2239
2240 void unpckhpd(XMMRegister dst, XMMRegister src);
2241 void unpcklpd(XMMRegister dst, XMMRegister src);
2242
2243 // Bitwise Logical XOR of Packed Floating-Point Values
2244 void xorpd(XMMRegister dst, XMMRegister src);
2245 void xorps(XMMRegister dst, XMMRegister src);
2246 void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2247 void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2248 void vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2249 void vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2250
2251 // Add horizontal packed integers
2252 void vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2253 void vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2254 void phaddw(XMMRegister dst, XMMRegister src);
2255 void phaddd(XMMRegister dst, XMMRegister src);
2256
2257 // Add packed integers
2258 void paddb(XMMRegister dst, XMMRegister src);
2259 void paddw(XMMRegister dst, XMMRegister src);
2260 void paddd(XMMRegister dst, XMMRegister src);
2261 void paddd(XMMRegister dst, Address src);
2262 void paddq(XMMRegister dst, XMMRegister src);
2263 void vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2264 void vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2265 void vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2266 void vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2267 void vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2268 void vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2269 void vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2270 void vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2271
2272 // Leaf level assembler routines for masked operations.
2273 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2274 void evpaddb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2275 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2276 void evpaddw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2277 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2278 void evpaddd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2279 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2280 void evpaddq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2281 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2282 void evaddps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2283 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2284 void evaddpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2285 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2286 void evpsubb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2287 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2288 void evpsubw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2289 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2290 void evpsubd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2291 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2292 void evpsubq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2293 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2294 void evsubps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2295 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2296 void evsubpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2297 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2298 void evpmullw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2299 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2300 void evpmulld(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2301 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2302 void evpmullq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2303 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2304 void evmulps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2305 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2306 void evmulpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2307 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2308 void evdivps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2309 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2310 void evdivpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2311 void evpabsb(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2312 void evpabsb(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2313 void evpabsw(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2314 void evpabsw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2315 void evpabsd(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2316 void evpabsd(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2317 void evpabsq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len);
2318 void evpabsq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len);
2319 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2320 void evpfma213ps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2321 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2322 void evpfma213pd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2323 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2324 void evpermb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2325 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2326 void evpermw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2327 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2328 void evpermd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2329 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2330 void evpermq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2331 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2332 void evpslld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2333 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2334 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2335 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2336 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2337 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2338 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2339 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2340 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2341 void evsqrtps(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2342 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2343 void evsqrtpd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2344
2345 void evpsllw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2346 void evpslld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2347 void evpsllq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2348 void evpsrlw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2349 void evpsrld(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2350 void evpsrlq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2351 void evpsraw(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2352 void evpsrad(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2353 void evpsraq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2354
2355 void evpsllvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2356 void evpsllvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2357 void evpsllvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2358 void evpsrlvw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2359 void evpsrlvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2360 void evpsrlvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2361 void evpsravw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2362 void evpsravd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2363 void evpsravq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2364 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2365 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2366 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2367 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2368 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2369 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2370 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2371 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2372 void evpmaxsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2373 void evpmaxsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2374 void evpmaxsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2375 void evpmaxsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2376 void evpminsb(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2377 void evpminsw(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2378 void evpminsd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2379 void evpminsq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2380 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2381 void evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2382 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2383 void evporq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2384 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2385 void evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2386 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2387 void evpandq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2388 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2389 void evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2390 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2391 void evpxorq(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len);
2392
2393 void evprold(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2394 void evprolq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2395 void evprolvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2396 void evprolvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2397 void evprord(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2398 void evprorq(XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vector_len);
2399 void evprorvd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2400 void evprorvq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2401
2402 // Sub packed integers
2403 void psubb(XMMRegister dst, XMMRegister src);
2404 void psubw(XMMRegister dst, XMMRegister src);
2405 void psubd(XMMRegister dst, XMMRegister src);
2406 void psubq(XMMRegister dst, XMMRegister src);
2407 void vpsubusb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2408 void vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2409 void vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2410 void vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2411 void vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2412 void vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2413 void vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2414 void vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2415 void vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2416
2417 // Multiply packed integers (only shorts and ints)
2418 void pmullw(XMMRegister dst, XMMRegister src);
2419 void pmulld(XMMRegister dst, XMMRegister src);
2420 void pmuludq(XMMRegister dst, XMMRegister src);
2421 void vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2422 void vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2423 void vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2424 void vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2425 void vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2426 void vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2427 void vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2428 void vpmulhuw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2429
2430 // Minimum of packed integers
2431 void pminsb(XMMRegister dst, XMMRegister src);
2432 void vpminsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2433 void pminsw(XMMRegister dst, XMMRegister src);
2434 void vpminsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2435 void pminsd(XMMRegister dst, XMMRegister src);
2436 void vpminsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2437 void vpminsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2438 void minps(XMMRegister dst, XMMRegister src);
2439 void vminps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2440 void minpd(XMMRegister dst, XMMRegister src);
2441 void vminpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2442
2443 // Maximum of packed integers
2444 void pmaxsb(XMMRegister dst, XMMRegister src);
2445 void vpmaxsb(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2446 void pmaxsw(XMMRegister dst, XMMRegister src);
2447 void vpmaxsw(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2448 void pmaxsd(XMMRegister dst, XMMRegister src);
2449 void vpmaxsd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2450 void vpmaxsq(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2451 void maxps(XMMRegister dst, XMMRegister src);
2452 void vmaxps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2453 void maxpd(XMMRegister dst, XMMRegister src);
2454 void vmaxpd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len);
2455
2456 // Shift left packed integers
2457 void psllw(XMMRegister dst, int shift);
2458 void pslld(XMMRegister dst, int shift);
2459 void psllq(XMMRegister dst, int shift);
2460 void psllw(XMMRegister dst, XMMRegister shift);
2461 void pslld(XMMRegister dst, XMMRegister shift);
2462 void psllq(XMMRegister dst, XMMRegister shift);
2463 void vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2464 void vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2465 void vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2466 void vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2467 void vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2468 void vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2469 void vpslldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2470
2471 // Logical shift right packed integers
2472 void psrlw(XMMRegister dst, int shift);
2473 void psrld(XMMRegister dst, int shift);
2474 void psrlq(XMMRegister dst, int shift);
2475 void psrlw(XMMRegister dst, XMMRegister shift);
2476 void psrld(XMMRegister dst, XMMRegister shift);
2477 void psrlq(XMMRegister dst, XMMRegister shift);
2478 void vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2479 void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2480 void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2481 void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2482 void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2483 void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2484 void vpsrldq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2485 void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2486 void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2487
2488 // Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
2489 void psraw(XMMRegister dst, int shift);
2490 void psrad(XMMRegister dst, int shift);
2491 void psraw(XMMRegister dst, XMMRegister shift);
2492 void psrad(XMMRegister dst, XMMRegister shift);
2493 void vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2494 void vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2495 void vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2496 void vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2497 void evpsravw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2498 void evpsraq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2499 void evpsraq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2500
2501 // Variable shift left packed integers
2502 void vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2503 void vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2504
2505 // Variable shift right packed integers
2506 void vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2507 void vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2508
2509 // Variable shift right arithmetic packed integers
2510 void vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2511 void evpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2512
2513 void vpshldvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2514 void vpshrdvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2515
2516 // And packed integers
2517 void pand(XMMRegister dst, XMMRegister src);
2518 void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2519 void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2520 void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2521
2522 // Andn packed integers
2523 void pandn(XMMRegister dst, XMMRegister src);
2524 void vpandn(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2525
2526 // Or packed integers
2527 void por(XMMRegister dst, XMMRegister src);
2528 void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2529 void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2530 void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2531
2532 // Xor packed integers
2533 void pxor(XMMRegister dst, XMMRegister src);
2534 void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2535 void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2536 void vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2537 void evpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2538 void evpxorq(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
2539
2540 // Ternary logic instruction.
2541 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2542 void vpternlogd(XMMRegister dst, int imm8, XMMRegister src2, Address src3, int vector_len);
2543 void vpternlogq(XMMRegister dst, int imm8, XMMRegister src2, XMMRegister src3, int vector_len);
2544
2545 // Vector Rotate Left/Right instruction.
2546 void evprolvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2547 void evprolvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2548 void evprorvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2549 void evprorvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
2550 void evprold(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2551 void evprolq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2552 void evprord(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2553 void evprorq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
2554
2555 // vinserti forms
2556 void vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2557 void vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2558 void vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2559 void vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2560 void vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2561
2562 // vinsertf forms
2563 void vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2564 void vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2565 void vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2566 void vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2567 void vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8);
2568 void vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8);
2569
2570 // vextracti forms
2571 void vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2572 void vextracti128(Address dst, XMMRegister src, uint8_t imm8);
2573 void vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2574 void vextracti32x4(Address dst, XMMRegister src, uint8_t imm8);
2575 void vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2576 void vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2577 void vextracti64x4(Address dst, XMMRegister src, uint8_t imm8);
2578
2579 // vextractf forms
2580 void vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8);
2581 void vextractf128(Address dst, XMMRegister src, uint8_t imm8);
2582 void vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2583 void vextractf32x4(Address dst, XMMRegister src, uint8_t imm8);
2584 void vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8);
2585 void vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8);
2586 void vextractf64x4(Address dst, XMMRegister src, uint8_t imm8);
2587
2588 // xmm/mem sourced byte/word/dword/qword replicate
2589 void vpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len);
2590 void vpbroadcastb(XMMRegister dst, Address src, int vector_len);
2591 void vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len);
2592 void vpbroadcastw(XMMRegister dst, Address src, int vector_len);
2593 void vpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len);
2594 void vpbroadcastd(XMMRegister dst, Address src, int vector_len);
2595 void vpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len);
2596 void vpbroadcastq(XMMRegister dst, Address src, int vector_len);
2597
2598 void evbroadcasti32x4(XMMRegister dst, Address src, int vector_len);
2599 void evbroadcasti64x2(XMMRegister dst, XMMRegister src, int vector_len);
2600 void evbroadcasti64x2(XMMRegister dst, Address src, int vector_len);
2601
2602 // scalar single/double/128bit precision replicate
2603 void vbroadcastss(XMMRegister dst, XMMRegister src, int vector_len);
2604 void vbroadcastss(XMMRegister dst, Address src, int vector_len);
2605 void vbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len);
2606 void vbroadcastsd(XMMRegister dst, Address src, int vector_len);
2607 void vbroadcastf128(XMMRegister dst, Address src, int vector_len);
2608
2609 // gpr sourced byte/word/dword/qword replicate
2610 void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
2611 void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
2612 void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
2613 void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
2614
2615 // Gather AVX2 and AVX3
2616 void vpgatherdd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2617 void vpgatherdq(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2618 void vgatherdpd(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2619 void vgatherdps(XMMRegister dst, Address src, XMMRegister mask, int vector_len);
2620 void evpgatherdd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2621 void evpgatherdq(XMMRegister dst, KRegister mask, Address src, int vector_len);
2622 void evgatherdpd(XMMRegister dst, KRegister mask, Address src, int vector_len);
2623 void evgatherdps(XMMRegister dst, KRegister mask, Address src, int vector_len);
2624
2625 //Scatter AVX3 only
2626 void evpscatterdd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2627 void evpscatterdq(Address dst, KRegister mask, XMMRegister src, int vector_len);
2628 void evscatterdps(Address dst, KRegister mask, XMMRegister src, int vector_len);
2629 void evscatterdpd(Address dst, KRegister mask, XMMRegister src, int vector_len);
2630
2631 // Carry-Less Multiplication Quadword
2632 void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
2633 void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
2634 void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
2635 // AVX instruction which is used to clear upper 128 bits of YMM registers and
2636 // to avoid transaction penalty between AVX and SSE states. There is no
2637 // penalty if legacy SSE instructions are encoded using VEX prefix because
2638 // they always clear upper 128 bits. It should be used before calling
2639 // runtime code and native libraries.
2640 void vzeroupper();
2641
2642 // Vector double compares
2643 void vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len);
2644 void evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2645 ComparisonPredicateFP comparison, int vector_len);
2646
2647 // Vector float compares
2648 void vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len);
2649 void evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2650 ComparisonPredicateFP comparison, int vector_len);
2651
2652 // Vector integer compares
2653 void vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
2654 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2655 int comparison, bool is_signed, int vector_len);
2656 void evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2657 int comparison, bool is_signed, int vector_len);
2658
2659 // Vector long compares
2660 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2661 int comparison, bool is_signed, int vector_len);
2662 void evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2663 int comparison, bool is_signed, int vector_len);
2664
2665 // Vector byte compares
2666 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2667 int comparison, bool is_signed, int vector_len);
2668 void evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2669 int comparison, bool is_signed, int vector_len);
2670
2671 // Vector short compares
2672 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
2673 int comparison, bool is_signed, int vector_len);
2674 void evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
2675 int comparison, bool is_signed, int vector_len);
2676
2677 void evpmovb2m(KRegister dst, XMMRegister src, int vector_len);
2678 void evpmovw2m(KRegister dst, XMMRegister src, int vector_len);
2679 void evpmovd2m(KRegister dst, XMMRegister src, int vector_len);
2680 void evpmovq2m(KRegister dst, XMMRegister src, int vector_len);
2681 void evpmovm2b(XMMRegister dst, KRegister src, int vector_len);
2682 void evpmovm2w(XMMRegister dst, KRegister src, int vector_len);
2683 void evpmovm2d(XMMRegister dst, KRegister src, int vector_len);
2684 void evpmovm2q(XMMRegister dst, KRegister src, int vector_len);
2685
2686 // Vector blends
2687 void blendvps(XMMRegister dst, XMMRegister src);
2688 void blendvpd(XMMRegister dst, XMMRegister src);
2689 void pblendvb(XMMRegister dst, XMMRegister src);
2690 void blendvpb(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2691 void vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2692 void vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len);
2693 void vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len);
2694 void vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len);
2695 void evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2696 void evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2697 void evpblendmb(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2698 void evpblendmw(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2699 void evpblendmd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2700 void evpblendmq(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len);
2701 protected:
2702 // Next instructions require address alignment 16 bytes SSE mode.
2703 // They should be called only from corresponding MacroAssembler instructions.
2704 void andpd(XMMRegister dst, Address src);
2705 void andps(XMMRegister dst, Address src);
2706 void xorpd(XMMRegister dst, Address src);
2707 void xorps(XMMRegister dst, Address src);
2708
2709 };
2710
2711 // The Intel x86/Amd64 Assembler attributes: All fields enclosed here are to guide encoding level decisions.
2712 // Specific set functions are for specialized use, else defaults or whatever was supplied to object construction
2713 // are applied.
2714 class InstructionAttr {
2715 public:
2716 InstructionAttr(
2717 int vector_len, // The length of vector to be applied in encoding - for both AVX and EVEX
2718 bool rex_vex_w, // Width of data: if 32-bits or less, false, else if 64-bit or specially defined, true
2719 bool legacy_mode, // Details if either this instruction is conditionally encoded to AVX or earlier if true else possibly EVEX
2720 bool no_reg_mask, // when true, k0 is used when EVEX encoding is chosen, else embedded_opmask_register_specifier is used
2721 bool uses_vl) // This instruction may have legacy constraints based on vector length for EVEX
2722 :
2723 _rex_vex_w(rex_vex_w),
2724 _legacy_mode(legacy_mode || UseAVX < 3),
2725 _no_reg_mask(no_reg_mask),
2726 _uses_vl(uses_vl),
2727 _rex_vex_w_reverted(false),
2728 _is_evex_instruction(false),
2729 _is_clear_context(true),
2730 _is_extended_context(false),
2731 _avx_vector_len(vector_len),
2732 _tuple_type(Assembler::EVEX_ETUP),
2733 _input_size_in_bits(Assembler::EVEX_NObit),
2734 _evex_encoding(0),
2735 _embedded_opmask_register_specifier(0), // hard code k0
2736 _current_assembler(NULL) { }
2737
2738 ~InstructionAttr() {
2739 if (_current_assembler != NULL) {
2740 _current_assembler->clear_attributes();
2741 }
2742 _current_assembler = NULL;
2743 }
2744
2745 private:
2746 bool _rex_vex_w;
2747 bool _legacy_mode;
2748 bool _no_reg_mask;
2749 bool _uses_vl;
2750 bool _rex_vex_w_reverted;
2751 bool _is_evex_instruction;
2752 bool _is_clear_context;
2753 bool _is_extended_context;
2754 int _avx_vector_len;
2755 int _tuple_type;
2756 int _input_size_in_bits;
2757 int _evex_encoding;
2758 int _embedded_opmask_register_specifier;
2759
2760 Assembler *_current_assembler;
2761
2762 public:
2763 // query functions for field accessors
2764 bool is_rex_vex_w(void) const { return _rex_vex_w; }
2765 bool is_legacy_mode(void) const { return _legacy_mode; }
2766 bool is_no_reg_mask(void) const { return _no_reg_mask; }
2767 bool uses_vl(void) const { return _uses_vl; }
2768 bool is_rex_vex_w_reverted(void) { return _rex_vex_w_reverted; }
2769 bool is_evex_instruction(void) const { return _is_evex_instruction; }
2770 bool is_clear_context(void) const { return _is_clear_context; }
2771 bool is_extended_context(void) const { return _is_extended_context; }
2772 int get_vector_len(void) const { return _avx_vector_len; }
2773 int get_tuple_type(void) const { return _tuple_type; }
2774 int get_input_size(void) const { return _input_size_in_bits; }
2775 int get_evex_encoding(void) const { return _evex_encoding; }
2776 int get_embedded_opmask_register_specifier(void) const { return _embedded_opmask_register_specifier; }
2777
2778 // Set the vector len manually
2779 void set_vector_len(int vector_len) { _avx_vector_len = vector_len; }
2780
2781 // Set revert rex_vex_w for avx encoding
2782 void set_rex_vex_w_reverted(void) { _rex_vex_w_reverted = true; }
2783
2784 // Set rex_vex_w based on state
2785 void set_rex_vex_w(bool state) { _rex_vex_w = state; }
2786
2787 // Set the instruction to be encoded in AVX mode
2788 void set_is_legacy_mode(void) { _legacy_mode = true; }
2789
2790 // Set the current instuction to be encoded as an EVEX instuction
2791 void set_is_evex_instruction(void) { _is_evex_instruction = true; }
2792
2793 // Internal encoding data used in compressed immediate offset programming
2794 void set_evex_encoding(int value) { _evex_encoding = value; }
2795
2796 // When the Evex.Z field is set (true), it is used to clear all non directed XMM/YMM/ZMM components.
2797 // This method unsets it so that merge semantics are used instead.
2798 void reset_is_clear_context(void) { _is_clear_context = false; }
2799
2800 // Map back to current asembler so that we can manage object level assocation
2801 void set_current_assembler(Assembler *current_assembler) { _current_assembler = current_assembler; }
2802
2803 // Address modifiers used for compressed displacement calculation
2804 void set_address_attributes(int tuple_type, int input_size_in_bits);
2805
2806 // Set embedded opmask register specifier.
2807 void set_embedded_opmask_register_specifier(KRegister mask) {
2808 _embedded_opmask_register_specifier = (*mask).encoding() & 0x7;
2809 }
2810
2811 };
2812
2813 #endif // CPU_X86_ASSEMBLER_X86_HPP