1 /*
   2  * Copyright (c) 1997, 2022, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #include "precompiled.hpp"
  26 #include "jvm.h"
  27 #include "asm/assembler.hpp"
  28 #include "asm/assembler.inline.hpp"
  29 #include "compiler/compiler_globals.hpp"
  30 #include "compiler/disassembler.hpp"
  31 #include "gc/shared/barrierSet.hpp"
  32 #include "gc/shared/barrierSetAssembler.hpp"
  33 #include "gc/shared/collectedHeap.inline.hpp"
  34 #include "gc/shared/tlab_globals.hpp"
  35 #include "interpreter/bytecodeHistogram.hpp"
  36 #include "interpreter/interpreter.hpp"
  37 #include "memory/resourceArea.hpp"
  38 #include "memory/universe.hpp"
  39 #include "oops/accessDecorators.hpp"
  40 #include "oops/compressedOops.inline.hpp"
  41 #include "oops/klass.inline.hpp"
  42 #include "prims/methodHandles.hpp"
  43 #include "runtime/flags/flagSetting.hpp"
  44 #include "runtime/interfaceSupport.inline.hpp"
  45 #include "runtime/jniHandles.hpp"
  46 #include "runtime/objectMonitor.hpp"
  47 #include "runtime/os.hpp"
  48 #include "runtime/safepoint.hpp"
  49 #include "runtime/safepointMechanism.hpp"
  50 #include "runtime/sharedRuntime.hpp"
  51 #include "runtime/stubRoutines.hpp"
  52 #include "runtime/thread.hpp"
  53 #include "utilities/macros.hpp"
  54 #include "crc32c.h"
  55 
  56 #ifdef PRODUCT
  57 #define BLOCK_COMMENT(str) /* nothing */
  58 #define STOP(error) stop(error)
  59 #else
  60 #define BLOCK_COMMENT(str) block_comment(str)
  61 #define STOP(error) block_comment(error); stop(error)
  62 #endif
  63 
  64 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
  65 
  66 #ifdef ASSERT
  67 bool AbstractAssembler::pd_check_instruction_mark() { return true; }
  68 #endif
  69 
  70 static Assembler::Condition reverse[] = {
  71     Assembler::noOverflow     /* overflow      = 0x0 */ ,
  72     Assembler::overflow       /* noOverflow    = 0x1 */ ,
  73     Assembler::aboveEqual     /* carrySet      = 0x2, below         = 0x2 */ ,
  74     Assembler::below          /* aboveEqual    = 0x3, carryClear    = 0x3 */ ,
  75     Assembler::notZero        /* zero          = 0x4, equal         = 0x4 */ ,
  76     Assembler::zero           /* notZero       = 0x5, notEqual      = 0x5 */ ,
  77     Assembler::above          /* belowEqual    = 0x6 */ ,
  78     Assembler::belowEqual     /* above         = 0x7 */ ,
  79     Assembler::positive       /* negative      = 0x8 */ ,
  80     Assembler::negative       /* positive      = 0x9 */ ,
  81     Assembler::noParity       /* parity        = 0xa */ ,
  82     Assembler::parity         /* noParity      = 0xb */ ,
  83     Assembler::greaterEqual   /* less          = 0xc */ ,
  84     Assembler::less           /* greaterEqual  = 0xd */ ,
  85     Assembler::greater        /* lessEqual     = 0xe */ ,
  86     Assembler::lessEqual      /* greater       = 0xf, */
  87 
  88 };
  89 
  90 
  91 // Implementation of MacroAssembler
  92 
  93 // First all the versions that have distinct versions depending on 32/64 bit
  94 // Unless the difference is trivial (1 line or so).
  95 
  96 #ifndef _LP64
  97 
  98 // 32bit versions
  99 
 100 Address MacroAssembler::as_Address(AddressLiteral adr) {
 101   return Address(adr.target(), adr.rspec());
 102 }
 103 
 104 Address MacroAssembler::as_Address(ArrayAddress adr) {
 105   return Address::make_array(adr);
 106 }
 107 
 108 void MacroAssembler::call_VM_leaf_base(address entry_point,
 109                                        int number_of_arguments) {
 110   call(RuntimeAddress(entry_point));
 111   increment(rsp, number_of_arguments * wordSize);
 112 }
 113 
 114 void MacroAssembler::cmpklass(Address src1, Metadata* obj) {
 115   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 116 }
 117 
 118 
 119 void MacroAssembler::cmpklass(Register src1, Metadata* obj) {
 120   cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 121 }
 122 
 123 void MacroAssembler::cmpoop(Address src1, jobject obj) {
 124   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 125 }
 126 
 127 void MacroAssembler::cmpoop(Register src1, jobject obj) {
 128   cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate());
 129 }
 130 
 131 void MacroAssembler::extend_sign(Register hi, Register lo) {
 132   // According to Intel Doc. AP-526, "Integer Divide", p.18.
 133   if (VM_Version::is_P6() && hi == rdx && lo == rax) {
 134     cdql();
 135   } else {
 136     movl(hi, lo);
 137     sarl(hi, 31);
 138   }
 139 }
 140 
 141 void MacroAssembler::jC2(Register tmp, Label& L) {
 142   // set parity bit if FPU flag C2 is set (via rax)
 143   save_rax(tmp);
 144   fwait(); fnstsw_ax();
 145   sahf();
 146   restore_rax(tmp);
 147   // branch
 148   jcc(Assembler::parity, L);
 149 }
 150 
 151 void MacroAssembler::jnC2(Register tmp, Label& L) {
 152   // set parity bit if FPU flag C2 is set (via rax)
 153   save_rax(tmp);
 154   fwait(); fnstsw_ax();
 155   sahf();
 156   restore_rax(tmp);
 157   // branch
 158   jcc(Assembler::noParity, L);
 159 }
 160 
 161 // 32bit can do a case table jump in one instruction but we no longer allow the base
 162 // to be installed in the Address class
 163 void MacroAssembler::jump(ArrayAddress entry) {
 164   jmp(as_Address(entry));
 165 }
 166 
 167 // Note: y_lo will be destroyed
 168 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 169   // Long compare for Java (semantics as described in JVM spec.)
 170   Label high, low, done;
 171 
 172   cmpl(x_hi, y_hi);
 173   jcc(Assembler::less, low);
 174   jcc(Assembler::greater, high);
 175   // x_hi is the return register
 176   xorl(x_hi, x_hi);
 177   cmpl(x_lo, y_lo);
 178   jcc(Assembler::below, low);
 179   jcc(Assembler::equal, done);
 180 
 181   bind(high);
 182   xorl(x_hi, x_hi);
 183   increment(x_hi);
 184   jmp(done);
 185 
 186   bind(low);
 187   xorl(x_hi, x_hi);
 188   decrementl(x_hi);
 189 
 190   bind(done);
 191 }
 192 
 193 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 194     mov_literal32(dst, (int32_t)src.target(), src.rspec());
 195 }
 196 
 197 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 198   // leal(dst, as_Address(adr));
 199   // see note in movl as to why we must use a move
 200   mov_literal32(dst, (int32_t) adr.target(), adr.rspec());
 201 }
 202 
 203 void MacroAssembler::leave() {
 204   mov(rsp, rbp);
 205   pop(rbp);
 206 }
 207 
 208 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) {
 209   // Multiplication of two Java long values stored on the stack
 210   // as illustrated below. Result is in rdx:rax.
 211   //
 212   // rsp ---> [  ??  ] \               \
 213   //            ....    | y_rsp_offset  |
 214   //          [ y_lo ] /  (in bytes)    | x_rsp_offset
 215   //          [ y_hi ]                  | (in bytes)
 216   //            ....                    |
 217   //          [ x_lo ]                 /
 218   //          [ x_hi ]
 219   //            ....
 220   //
 221   // Basic idea: lo(result) = lo(x_lo * y_lo)
 222   //             hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi)
 223   Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset);
 224   Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset);
 225   Label quick;
 226   // load x_hi, y_hi and check if quick
 227   // multiplication is possible
 228   movl(rbx, x_hi);
 229   movl(rcx, y_hi);
 230   movl(rax, rbx);
 231   orl(rbx, rcx);                                 // rbx, = 0 <=> x_hi = 0 and y_hi = 0
 232   jcc(Assembler::zero, quick);                   // if rbx, = 0 do quick multiply
 233   // do full multiplication
 234   // 1st step
 235   mull(y_lo);                                    // x_hi * y_lo
 236   movl(rbx, rax);                                // save lo(x_hi * y_lo) in rbx,
 237   // 2nd step
 238   movl(rax, x_lo);
 239   mull(rcx);                                     // x_lo * y_hi
 240   addl(rbx, rax);                                // add lo(x_lo * y_hi) to rbx,
 241   // 3rd step
 242   bind(quick);                                   // note: rbx, = 0 if quick multiply!
 243   movl(rax, x_lo);
 244   mull(y_lo);                                    // x_lo * y_lo
 245   addl(rdx, rbx);                                // correct hi(x_lo * y_lo)
 246 }
 247 
 248 void MacroAssembler::lneg(Register hi, Register lo) {
 249   negl(lo);
 250   adcl(hi, 0);
 251   negl(hi);
 252 }
 253 
 254 void MacroAssembler::lshl(Register hi, Register lo) {
 255   // Java shift left long support (semantics as described in JVM spec., p.305)
 256   // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n))
 257   // shift value is in rcx !
 258   assert(hi != rcx, "must not use rcx");
 259   assert(lo != rcx, "must not use rcx");
 260   const Register s = rcx;                        // shift count
 261   const int      n = BitsPerWord;
 262   Label L;
 263   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 264   cmpl(s, n);                                    // if (s < n)
 265   jcc(Assembler::less, L);                       // else (s >= n)
 266   movl(hi, lo);                                  // x := x << n
 267   xorl(lo, lo);
 268   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 269   bind(L);                                       // s (mod n) < n
 270   shldl(hi, lo);                                 // x := x << s
 271   shll(lo);
 272 }
 273 
 274 
 275 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) {
 276   // Java shift right long support (semantics as described in JVM spec., p.306 & p.310)
 277   // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n))
 278   assert(hi != rcx, "must not use rcx");
 279   assert(lo != rcx, "must not use rcx");
 280   const Register s = rcx;                        // shift count
 281   const int      n = BitsPerWord;
 282   Label L;
 283   andl(s, 0x3f);                                 // s := s & 0x3f (s < 0x40)
 284   cmpl(s, n);                                    // if (s < n)
 285   jcc(Assembler::less, L);                       // else (s >= n)
 286   movl(lo, hi);                                  // x := x >> n
 287   if (sign_extension) sarl(hi, 31);
 288   else                xorl(hi, hi);
 289   // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n!
 290   bind(L);                                       // s (mod n) < n
 291   shrdl(lo, hi);                                 // x := x >> s
 292   if (sign_extension) sarl(hi);
 293   else                shrl(hi);
 294 }
 295 
 296 void MacroAssembler::movoop(Register dst, jobject obj) {
 297   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 298 }
 299 
 300 void MacroAssembler::movoop(Address dst, jobject obj) {
 301   mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate());
 302 }
 303 
 304 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 305   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 306 }
 307 
 308 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 309   mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate());
 310 }
 311 
 312 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 313   // scratch register is not used,
 314   // it is defined to match parameters of 64-bit version of this method.
 315   if (src.is_lval()) {
 316     mov_literal32(dst, (intptr_t)src.target(), src.rspec());
 317   } else {
 318     movl(dst, as_Address(src));
 319   }
 320 }
 321 
 322 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 323   movl(as_Address(dst), src);
 324 }
 325 
 326 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 327   movl(dst, as_Address(src));
 328 }
 329 
 330 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 331 void MacroAssembler::movptr(Address dst, intptr_t src) {
 332   movl(dst, src);
 333 }
 334 
 335 void MacroAssembler::pushoop(jobject obj) {
 336   push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate());
 337 }
 338 
 339 void MacroAssembler::pushklass(Metadata* obj) {
 340   push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate());
 341 }
 342 
 343 void MacroAssembler::pushptr(AddressLiteral src) {
 344   if (src.is_lval()) {
 345     push_literal32((int32_t)src.target(), src.rspec());
 346   } else {
 347     pushl(as_Address(src));
 348   }
 349 }
 350 
 351 static void pass_arg0(MacroAssembler* masm, Register arg) {
 352   masm->push(arg);
 353 }
 354 
 355 static void pass_arg1(MacroAssembler* masm, Register arg) {
 356   masm->push(arg);
 357 }
 358 
 359 static void pass_arg2(MacroAssembler* masm, Register arg) {
 360   masm->push(arg);
 361 }
 362 
 363 static void pass_arg3(MacroAssembler* masm, Register arg) {
 364   masm->push(arg);
 365 }
 366 
 367 #ifndef PRODUCT
 368 extern "C" void findpc(intptr_t x);
 369 #endif
 370 
 371 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) {
 372   // In order to get locks to work, we need to fake a in_VM state
 373   JavaThread* thread = JavaThread::current();
 374   JavaThreadState saved_state = thread->thread_state();
 375   thread->set_thread_state(_thread_in_vm);
 376   if (ShowMessageBoxOnError) {
 377     JavaThread* thread = JavaThread::current();
 378     JavaThreadState saved_state = thread->thread_state();
 379     thread->set_thread_state(_thread_in_vm);
 380     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 381       ttyLocker ttyl;
 382       BytecodeCounter::print();
 383     }
 384     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 385     // This is the value of eip which points to where verify_oop will return.
 386     if (os::message_box(msg, "Execution stopped, print registers?")) {
 387       print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip);
 388       BREAKPOINT;
 389     }
 390   }
 391   fatal("DEBUG MESSAGE: %s", msg);
 392 }
 393 
 394 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) {
 395   ttyLocker ttyl;
 396   FlagSetting fs(Debugging, true);
 397   tty->print_cr("eip = 0x%08x", eip);
 398 #ifndef PRODUCT
 399   if ((WizardMode || Verbose) && PrintMiscellaneous) {
 400     tty->cr();
 401     findpc(eip);
 402     tty->cr();
 403   }
 404 #endif
 405 #define PRINT_REG(rax) \
 406   { tty->print("%s = ", #rax); os::print_location(tty, rax); }
 407   PRINT_REG(rax);
 408   PRINT_REG(rbx);
 409   PRINT_REG(rcx);
 410   PRINT_REG(rdx);
 411   PRINT_REG(rdi);
 412   PRINT_REG(rsi);
 413   PRINT_REG(rbp);
 414   PRINT_REG(rsp);
 415 #undef PRINT_REG
 416   // Print some words near top of staack.
 417   int* dump_sp = (int*) rsp;
 418   for (int col1 = 0; col1 < 8; col1++) {
 419     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 420     os::print_location(tty, *dump_sp++);
 421   }
 422   for (int row = 0; row < 16; row++) {
 423     tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 424     for (int col = 0; col < 8; col++) {
 425       tty->print(" 0x%08x", *dump_sp++);
 426     }
 427     tty->cr();
 428   }
 429   // Print some instructions around pc:
 430   Disassembler::decode((address)eip-64, (address)eip);
 431   tty->print_cr("--------");
 432   Disassembler::decode((address)eip, (address)eip+32);
 433 }
 434 
 435 void MacroAssembler::stop(const char* msg) {
 436   ExternalAddress message((address)msg);
 437   // push address of message
 438   pushptr(message.addr());
 439   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 440   pusha();                                            // push registers
 441   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32)));
 442   hlt();
 443 }
 444 
 445 void MacroAssembler::warn(const char* msg) {
 446   push_CPU_state();
 447 
 448   ExternalAddress message((address) msg);
 449   // push address of message
 450   pushptr(message.addr());
 451 
 452   call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning)));
 453   addl(rsp, wordSize);       // discard argument
 454   pop_CPU_state();
 455 }
 456 
 457 void MacroAssembler::print_state() {
 458   { Label L; call(L, relocInfo::none); bind(L); }     // push eip
 459   pusha();                                            // push registers
 460 
 461   push_CPU_state();
 462   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32)));
 463   pop_CPU_state();
 464 
 465   popa();
 466   addl(rsp, wordSize);
 467 }
 468 
 469 #else // _LP64
 470 
 471 // 64 bit versions
 472 
 473 Address MacroAssembler::as_Address(AddressLiteral adr) {
 474   // amd64 always does this as a pc-rel
 475   // we can be absolute or disp based on the instruction type
 476   // jmp/call are displacements others are absolute
 477   assert(!adr.is_lval(), "must be rval");
 478   assert(reachable(adr), "must be");
 479   return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc());
 480 
 481 }
 482 
 483 Address MacroAssembler::as_Address(ArrayAddress adr) {
 484   AddressLiteral base = adr.base();
 485   lea(rscratch1, base);
 486   Address index = adr.index();
 487   assert(index._disp == 0, "must not have disp"); // maybe it can?
 488   Address array(rscratch1, index._index, index._scale, index._disp);
 489   return array;
 490 }
 491 
 492 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) {
 493   Label L, E;
 494 
 495 #ifdef _WIN64
 496   // Windows always allocates space for it's register args
 497   assert(num_args <= 4, "only register arguments supported");
 498   subq(rsp,  frame::arg_reg_save_area_bytes);
 499 #endif
 500 
 501   // Align stack if necessary
 502   testl(rsp, 15);
 503   jcc(Assembler::zero, L);
 504 
 505   subq(rsp, 8);
 506   {
 507     call(RuntimeAddress(entry_point));
 508   }
 509   addq(rsp, 8);
 510   jmp(E);
 511 
 512   bind(L);
 513   {
 514     call(RuntimeAddress(entry_point));
 515   }
 516 
 517   bind(E);
 518 
 519 #ifdef _WIN64
 520   // restore stack pointer
 521   addq(rsp, frame::arg_reg_save_area_bytes);
 522 #endif
 523 
 524 }
 525 
 526 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) {
 527   assert(!src2.is_lval(), "should use cmpptr");
 528 
 529   if (reachable(src2)) {
 530     cmpq(src1, as_Address(src2));
 531   } else {
 532     lea(rscratch1, src2);
 533     Assembler::cmpq(src1, Address(rscratch1, 0));
 534   }
 535 }
 536 
 537 int MacroAssembler::corrected_idivq(Register reg) {
 538   // Full implementation of Java ldiv and lrem; checks for special
 539   // case as described in JVM spec., p.243 & p.271.  The function
 540   // returns the (pc) offset of the idivl instruction - may be needed
 541   // for implicit exceptions.
 542   //
 543   //         normal case                           special case
 544   //
 545   // input : rax: dividend                         min_long
 546   //         reg: divisor   (may not be eax/edx)   -1
 547   //
 548   // output: rax: quotient  (= rax idiv reg)       min_long
 549   //         rdx: remainder (= rax irem reg)       0
 550   assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register");
 551   static const int64_t min_long = 0x8000000000000000;
 552   Label normal_case, special_case;
 553 
 554   // check for special case
 555   cmp64(rax, ExternalAddress((address) &min_long));
 556   jcc(Assembler::notEqual, normal_case);
 557   xorl(rdx, rdx); // prepare rdx for possible special case (where
 558                   // remainder = 0)
 559   cmpq(reg, -1);
 560   jcc(Assembler::equal, special_case);
 561 
 562   // handle normal case
 563   bind(normal_case);
 564   cdqq();
 565   int idivq_offset = offset();
 566   idivq(reg);
 567 
 568   // normal and special case exit
 569   bind(special_case);
 570 
 571   return idivq_offset;
 572 }
 573 
 574 void MacroAssembler::decrementq(Register reg, int value) {
 575   if (value == min_jint) { subq(reg, value); return; }
 576   if (value <  0) { incrementq(reg, -value); return; }
 577   if (value == 0) {                        ; return; }
 578   if (value == 1 && UseIncDec) { decq(reg) ; return; }
 579   /* else */      { subq(reg, value)       ; return; }
 580 }
 581 
 582 void MacroAssembler::decrementq(Address dst, int value) {
 583   if (value == min_jint) { subq(dst, value); return; }
 584   if (value <  0) { incrementq(dst, -value); return; }
 585   if (value == 0) {                        ; return; }
 586   if (value == 1 && UseIncDec) { decq(dst) ; return; }
 587   /* else */      { subq(dst, value)       ; return; }
 588 }
 589 
 590 void MacroAssembler::incrementq(AddressLiteral dst) {
 591   if (reachable(dst)) {
 592     incrementq(as_Address(dst));
 593   } else {
 594     lea(rscratch1, dst);
 595     incrementq(Address(rscratch1, 0));
 596   }
 597 }
 598 
 599 void MacroAssembler::incrementq(Register reg, int value) {
 600   if (value == min_jint) { addq(reg, value); return; }
 601   if (value <  0) { decrementq(reg, -value); return; }
 602   if (value == 0) {                        ; return; }
 603   if (value == 1 && UseIncDec) { incq(reg) ; return; }
 604   /* else */      { addq(reg, value)       ; return; }
 605 }
 606 
 607 void MacroAssembler::incrementq(Address dst, int value) {
 608   if (value == min_jint) { addq(dst, value); return; }
 609   if (value <  0) { decrementq(dst, -value); return; }
 610   if (value == 0) {                        ; return; }
 611   if (value == 1 && UseIncDec) { incq(dst) ; return; }
 612   /* else */      { addq(dst, value)       ; return; }
 613 }
 614 
 615 // 32bit can do a case table jump in one instruction but we no longer allow the base
 616 // to be installed in the Address class
 617 void MacroAssembler::jump(ArrayAddress entry) {
 618   lea(rscratch1, entry.base());
 619   Address dispatch = entry.index();
 620   assert(dispatch._base == noreg, "must be");
 621   dispatch._base = rscratch1;
 622   jmp(dispatch);
 623 }
 624 
 625 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) {
 626   ShouldNotReachHere(); // 64bit doesn't use two regs
 627   cmpq(x_lo, y_lo);
 628 }
 629 
 630 void MacroAssembler::lea(Register dst, AddressLiteral src) {
 631     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 632 }
 633 
 634 void MacroAssembler::lea(Address dst, AddressLiteral adr) {
 635   mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec());
 636   movptr(dst, rscratch1);
 637 }
 638 
 639 void MacroAssembler::leave() {
 640   // %%% is this really better? Why not on 32bit too?
 641   emit_int8((unsigned char)0xC9); // LEAVE
 642 }
 643 
 644 void MacroAssembler::lneg(Register hi, Register lo) {
 645   ShouldNotReachHere(); // 64bit doesn't use two regs
 646   negq(lo);
 647 }
 648 
 649 void MacroAssembler::movoop(Register dst, jobject obj) {
 650   mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 651 }
 652 
 653 void MacroAssembler::movoop(Address dst, jobject obj) {
 654   mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate());
 655   movq(dst, rscratch1);
 656 }
 657 
 658 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) {
 659   mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 660 }
 661 
 662 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) {
 663   mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate());
 664   movq(dst, rscratch1);
 665 }
 666 
 667 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) {
 668   if (src.is_lval()) {
 669     mov_literal64(dst, (intptr_t)src.target(), src.rspec());
 670   } else {
 671     if (reachable(src)) {
 672       movq(dst, as_Address(src));
 673     } else {
 674       lea(scratch, src);
 675       movq(dst, Address(scratch, 0));
 676     }
 677   }
 678 }
 679 
 680 void MacroAssembler::movptr(ArrayAddress dst, Register src) {
 681   movq(as_Address(dst), src);
 682 }
 683 
 684 void MacroAssembler::movptr(Register dst, ArrayAddress src) {
 685   movq(dst, as_Address(src));
 686 }
 687 
 688 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
 689 void MacroAssembler::movptr(Address dst, intptr_t src) {
 690   if (is_simm32(src)) {
 691     movptr(dst, checked_cast<int32_t>(src));
 692   } else {
 693     mov64(rscratch1, src);
 694     movq(dst, rscratch1);
 695   }
 696 }
 697 
 698 // These are mostly for initializing NULL
 699 void MacroAssembler::movptr(Address dst, int32_t src) {
 700   movslq(dst, src);
 701 }
 702 
 703 void MacroAssembler::movptr(Register dst, int32_t src) {
 704   mov64(dst, (intptr_t)src);
 705 }
 706 
 707 void MacroAssembler::pushoop(jobject obj) {
 708   movoop(rscratch1, obj);
 709   push(rscratch1);
 710 }
 711 
 712 void MacroAssembler::pushklass(Metadata* obj) {
 713   mov_metadata(rscratch1, obj);
 714   push(rscratch1);
 715 }
 716 
 717 void MacroAssembler::pushptr(AddressLiteral src) {
 718   lea(rscratch1, src);
 719   if (src.is_lval()) {
 720     push(rscratch1);
 721   } else {
 722     pushq(Address(rscratch1, 0));
 723   }
 724 }
 725 
 726 void MacroAssembler::reset_last_Java_frame(bool clear_fp) {
 727   reset_last_Java_frame(r15_thread, clear_fp);
 728 }
 729 
 730 void MacroAssembler::set_last_Java_frame(Register last_java_sp,
 731                                          Register last_java_fp,
 732                                          address  last_java_pc) {
 733   vzeroupper();
 734   // determine last_java_sp register
 735   if (!last_java_sp->is_valid()) {
 736     last_java_sp = rsp;
 737   }
 738 
 739   // last_java_fp is optional
 740   if (last_java_fp->is_valid()) {
 741     movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()),
 742            last_java_fp);
 743   }
 744 
 745   // last_java_pc is optional
 746   if (last_java_pc != NULL) {
 747     Address java_pc(r15_thread,
 748                     JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset());
 749     lea(rscratch1, InternalAddress(last_java_pc));
 750     movptr(java_pc, rscratch1);
 751   }
 752 
 753   movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
 754 }
 755 
 756 static void pass_arg0(MacroAssembler* masm, Register arg) {
 757   if (c_rarg0 != arg ) {
 758     masm->mov(c_rarg0, arg);
 759   }
 760 }
 761 
 762 static void pass_arg1(MacroAssembler* masm, Register arg) {
 763   if (c_rarg1 != arg ) {
 764     masm->mov(c_rarg1, arg);
 765   }
 766 }
 767 
 768 static void pass_arg2(MacroAssembler* masm, Register arg) {
 769   if (c_rarg2 != arg ) {
 770     masm->mov(c_rarg2, arg);
 771   }
 772 }
 773 
 774 static void pass_arg3(MacroAssembler* masm, Register arg) {
 775   if (c_rarg3 != arg ) {
 776     masm->mov(c_rarg3, arg);
 777   }
 778 }
 779 
 780 void MacroAssembler::stop(const char* msg) {
 781   if (ShowMessageBoxOnError) {
 782     address rip = pc();
 783     pusha(); // get regs on stack
 784     lea(c_rarg1, InternalAddress(rip));
 785     movq(c_rarg2, rsp); // pass pointer to regs array
 786   }
 787   lea(c_rarg0, ExternalAddress((address) msg));
 788   andq(rsp, -16); // align stack as required by ABI
 789   call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64)));
 790   hlt();
 791 }
 792 
 793 void MacroAssembler::warn(const char* msg) {
 794   push(rbp);
 795   movq(rbp, rsp);
 796   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 797   push_CPU_state();   // keeps alignment at 16 bytes
 798   lea(c_rarg0, ExternalAddress((address) msg));
 799   lea(rax, ExternalAddress(CAST_FROM_FN_PTR(address, warning)));
 800   call(rax);
 801   pop_CPU_state();
 802   mov(rsp, rbp);
 803   pop(rbp);
 804 }
 805 
 806 void MacroAssembler::print_state() {
 807   address rip = pc();
 808   pusha();            // get regs on stack
 809   push(rbp);
 810   movq(rbp, rsp);
 811   andq(rsp, -16);     // align stack as required by push_CPU_state and call
 812   push_CPU_state();   // keeps alignment at 16 bytes
 813 
 814   lea(c_rarg0, InternalAddress(rip));
 815   lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array
 816   call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1);
 817 
 818   pop_CPU_state();
 819   mov(rsp, rbp);
 820   pop(rbp);
 821   popa();
 822 }
 823 
 824 #ifndef PRODUCT
 825 extern "C" void findpc(intptr_t x);
 826 #endif
 827 
 828 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) {
 829   // In order to get locks to work, we need to fake a in_VM state
 830   if (ShowMessageBoxOnError) {
 831     JavaThread* thread = JavaThread::current();
 832     JavaThreadState saved_state = thread->thread_state();
 833     thread->set_thread_state(_thread_in_vm);
 834 #ifndef PRODUCT
 835     if (CountBytecodes || TraceBytecodes || StopInterpreterAt) {
 836       ttyLocker ttyl;
 837       BytecodeCounter::print();
 838     }
 839 #endif
 840     // To see where a verify_oop failed, get $ebx+40/X for this frame.
 841     // XXX correct this offset for amd64
 842     // This is the value of eip which points to where verify_oop will return.
 843     if (os::message_box(msg, "Execution stopped, print registers?")) {
 844       print_state64(pc, regs);
 845       BREAKPOINT;
 846     }
 847   }
 848   fatal("DEBUG MESSAGE: %s", msg);
 849 }
 850 
 851 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) {
 852   ttyLocker ttyl;
 853   FlagSetting fs(Debugging, true);
 854   tty->print_cr("rip = 0x%016lx", (intptr_t)pc);
 855 #ifndef PRODUCT
 856   tty->cr();
 857   findpc(pc);
 858   tty->cr();
 859 #endif
 860 #define PRINT_REG(rax, value) \
 861   { tty->print("%s = ", #rax); os::print_location(tty, value); }
 862   PRINT_REG(rax, regs[15]);
 863   PRINT_REG(rbx, regs[12]);
 864   PRINT_REG(rcx, regs[14]);
 865   PRINT_REG(rdx, regs[13]);
 866   PRINT_REG(rdi, regs[8]);
 867   PRINT_REG(rsi, regs[9]);
 868   PRINT_REG(rbp, regs[10]);
 869   // rsp is actually not stored by pusha(), compute the old rsp from regs (rsp after pusha): regs + 16 = old rsp
 870   PRINT_REG(rsp, (intptr_t)(&regs[16]));
 871   PRINT_REG(r8 , regs[7]);
 872   PRINT_REG(r9 , regs[6]);
 873   PRINT_REG(r10, regs[5]);
 874   PRINT_REG(r11, regs[4]);
 875   PRINT_REG(r12, regs[3]);
 876   PRINT_REG(r13, regs[2]);
 877   PRINT_REG(r14, regs[1]);
 878   PRINT_REG(r15, regs[0]);
 879 #undef PRINT_REG
 880   // Print some words near the top of the stack.
 881   int64_t* rsp = &regs[16];
 882   int64_t* dump_sp = rsp;
 883   for (int col1 = 0; col1 < 8; col1++) {
 884     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 885     os::print_location(tty, *dump_sp++);
 886   }
 887   for (int row = 0; row < 25; row++) {
 888     tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp);
 889     for (int col = 0; col < 4; col++) {
 890       tty->print(" 0x%016lx", (intptr_t)*dump_sp++);
 891     }
 892     tty->cr();
 893   }
 894   // Print some instructions around pc:
 895   Disassembler::decode((address)pc-64, (address)pc);
 896   tty->print_cr("--------");
 897   Disassembler::decode((address)pc, (address)pc+32);
 898 }
 899 
 900 // The java_calling_convention describes stack locations as ideal slots on
 901 // a frame with no abi restrictions. Since we must observe abi restrictions
 902 // (like the placement of the register window) the slots must be biased by
 903 // the following value.
 904 static int reg2offset_in(VMReg r) {
 905   // Account for saved rbp and return address
 906   // This should really be in_preserve_stack_slots
 907   return (r->reg2stack() + 4) * VMRegImpl::stack_slot_size;
 908 }
 909 
 910 static int reg2offset_out(VMReg r) {
 911   return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
 912 }
 913 
 914 // A long move
 915 void MacroAssembler::long_move(VMRegPair src, VMRegPair dst) {
 916 
 917   // The calling conventions assures us that each VMregpair is either
 918   // all really one physical register or adjacent stack slots.
 919 
 920   if (src.is_single_phys_reg() ) {
 921     if (dst.is_single_phys_reg()) {
 922       if (dst.first() != src.first()) {
 923         mov(dst.first()->as_Register(), src.first()->as_Register());
 924       }
 925     } else {
 926       assert(dst.is_single_reg(), "not a stack pair");
 927       movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
 928     }
 929   } else if (dst.is_single_phys_reg()) {
 930     assert(src.is_single_reg(),  "not a stack pair");
 931     movq(dst.first()->as_Register(), Address(rbp, reg2offset_out(src.first())));
 932   } else {
 933     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 934     movq(rax, Address(rbp, reg2offset_in(src.first())));
 935     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 936   }
 937 }
 938 
 939 // A double move
 940 void MacroAssembler::double_move(VMRegPair src, VMRegPair dst) {
 941 
 942   // The calling conventions assures us that each VMregpair is either
 943   // all really one physical register or adjacent stack slots.
 944 
 945   if (src.is_single_phys_reg() ) {
 946     if (dst.is_single_phys_reg()) {
 947       // In theory these overlap but the ordering is such that this is likely a nop
 948       if ( src.first() != dst.first()) {
 949         movdbl(dst.first()->as_XMMRegister(), src.first()->as_XMMRegister());
 950       }
 951     } else {
 952       assert(dst.is_single_reg(), "not a stack pair");
 953       movdbl(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 954     }
 955   } else if (dst.is_single_phys_reg()) {
 956     assert(src.is_single_reg(),  "not a stack pair");
 957     movdbl(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_out(src.first())));
 958   } else {
 959     assert(src.is_single_reg() && dst.is_single_reg(), "not stack pairs");
 960     movq(rax, Address(rbp, reg2offset_in(src.first())));
 961     movq(Address(rsp, reg2offset_out(dst.first())), rax);
 962   }
 963 }
 964 
 965 
 966 // A float arg may have to do float reg int reg conversion
 967 void MacroAssembler::float_move(VMRegPair src, VMRegPair dst) {
 968   assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
 969 
 970   // The calling conventions assures us that each VMregpair is either
 971   // all really one physical register or adjacent stack slots.
 972 
 973   if (src.first()->is_stack()) {
 974     if (dst.first()->is_stack()) {
 975       movl(rax, Address(rbp, reg2offset_in(src.first())));
 976       movptr(Address(rsp, reg2offset_out(dst.first())), rax);
 977     } else {
 978       // stack to reg
 979       assert(dst.first()->is_XMMRegister(), "only expect xmm registers as parameters");
 980       movflt(dst.first()->as_XMMRegister(), Address(rbp, reg2offset_in(src.first())));
 981     }
 982   } else if (dst.first()->is_stack()) {
 983     // reg to stack
 984     assert(src.first()->is_XMMRegister(), "only expect xmm registers as parameters");
 985     movflt(Address(rsp, reg2offset_out(dst.first())), src.first()->as_XMMRegister());
 986   } else {
 987     // reg to reg
 988     // In theory these overlap but the ordering is such that this is likely a nop
 989     if ( src.first() != dst.first()) {
 990       movdbl(dst.first()->as_XMMRegister(),  src.first()->as_XMMRegister());
 991     }
 992   }
 993 }
 994 
 995 // On 64 bit we will store integer like items to the stack as
 996 // 64 bits items (x86_32/64 abi) even though java would only store
 997 // 32bits for a parameter. On 32bit it will simply be 32 bits
 998 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
 999 void MacroAssembler::move32_64(VMRegPair src, VMRegPair dst) {
1000   if (src.first()->is_stack()) {
1001     if (dst.first()->is_stack()) {
1002       // stack to stack
1003       movslq(rax, Address(rbp, reg2offset_in(src.first())));
1004       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1005     } else {
1006       // stack to reg
1007       movslq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1008     }
1009   } else if (dst.first()->is_stack()) {
1010     // reg to stack
1011     // Do we really have to sign extend???
1012     // __ movslq(src.first()->as_Register(), src.first()->as_Register());
1013     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1014   } else {
1015     // Do we really have to sign extend???
1016     // __ movslq(dst.first()->as_Register(), src.first()->as_Register());
1017     if (dst.first() != src.first()) {
1018       movq(dst.first()->as_Register(), src.first()->as_Register());
1019     }
1020   }
1021 }
1022 
1023 void MacroAssembler::move_ptr(VMRegPair src, VMRegPair dst) {
1024   if (src.first()->is_stack()) {
1025     if (dst.first()->is_stack()) {
1026       // stack to stack
1027       movq(rax, Address(rbp, reg2offset_in(src.first())));
1028       movq(Address(rsp, reg2offset_out(dst.first())), rax);
1029     } else {
1030       // stack to reg
1031       movq(dst.first()->as_Register(), Address(rbp, reg2offset_in(src.first())));
1032     }
1033   } else if (dst.first()->is_stack()) {
1034     // reg to stack
1035     movq(Address(rsp, reg2offset_out(dst.first())), src.first()->as_Register());
1036   } else {
1037     if (dst.first() != src.first()) {
1038       movq(dst.first()->as_Register(), src.first()->as_Register());
1039     }
1040   }
1041 }
1042 
1043 // An oop arg. Must pass a handle not the oop itself
1044 void MacroAssembler::object_move(OopMap* map,
1045                         int oop_handle_offset,
1046                         int framesize_in_slots,
1047                         VMRegPair src,
1048                         VMRegPair dst,
1049                         bool is_receiver,
1050                         int* receiver_offset) {
1051 
1052   // must pass a handle. First figure out the location we use as a handle
1053 
1054   Register rHandle = dst.first()->is_stack() ? rax : dst.first()->as_Register();
1055 
1056   // See if oop is NULL if it is we need no handle
1057 
1058   if (src.first()->is_stack()) {
1059 
1060     // Oop is already on the stack as an argument
1061     int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1062     map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1063     if (is_receiver) {
1064       *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1065     }
1066 
1067     cmpptr(Address(rbp, reg2offset_in(src.first())), (int32_t)NULL_WORD);
1068     lea(rHandle, Address(rbp, reg2offset_in(src.first())));
1069     // conditionally move a NULL
1070     cmovptr(Assembler::equal, rHandle, Address(rbp, reg2offset_in(src.first())));
1071   } else {
1072 
1073     // Oop is in an a register we must store it to the space we reserve
1074     // on the stack for oop_handles and pass a handle if oop is non-NULL
1075 
1076     const Register rOop = src.first()->as_Register();
1077     int oop_slot;
1078     if (rOop == j_rarg0)
1079       oop_slot = 0;
1080     else if (rOop == j_rarg1)
1081       oop_slot = 1;
1082     else if (rOop == j_rarg2)
1083       oop_slot = 2;
1084     else if (rOop == j_rarg3)
1085       oop_slot = 3;
1086     else if (rOop == j_rarg4)
1087       oop_slot = 4;
1088     else {
1089       assert(rOop == j_rarg5, "wrong register");
1090       oop_slot = 5;
1091     }
1092 
1093     oop_slot = oop_slot * VMRegImpl::slots_per_word + oop_handle_offset;
1094     int offset = oop_slot*VMRegImpl::stack_slot_size;
1095 
1096     map->set_oop(VMRegImpl::stack2reg(oop_slot));
1097     // Store oop in handle area, may be NULL
1098     movptr(Address(rsp, offset), rOop);
1099     if (is_receiver) {
1100       *receiver_offset = offset;
1101     }
1102 
1103     cmpptr(rOop, (int32_t)NULL_WORD);
1104     lea(rHandle, Address(rsp, offset));
1105     // conditionally move a NULL from the handle area where it was just stored
1106     cmovptr(Assembler::equal, rHandle, Address(rsp, offset));
1107   }
1108 
1109   // If arg is on the stack then place it otherwise it is already in correct reg.
1110   if (dst.first()->is_stack()) {
1111     movptr(Address(rsp, reg2offset_out(dst.first())), rHandle);
1112   }
1113 }
1114 
1115 #endif // _LP64
1116 
1117 // Now versions that are common to 32/64 bit
1118 
1119 void MacroAssembler::addptr(Register dst, int32_t imm32) {
1120   LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32));
1121 }
1122 
1123 void MacroAssembler::addptr(Register dst, Register src) {
1124   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1125 }
1126 
1127 void MacroAssembler::addptr(Address dst, Register src) {
1128   LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src));
1129 }
1130 
1131 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) {
1132   if (reachable(src)) {
1133     Assembler::addsd(dst, as_Address(src));
1134   } else {
1135     lea(rscratch1, src);
1136     Assembler::addsd(dst, Address(rscratch1, 0));
1137   }
1138 }
1139 
1140 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) {
1141   if (reachable(src)) {
1142     addss(dst, as_Address(src));
1143   } else {
1144     lea(rscratch1, src);
1145     addss(dst, Address(rscratch1, 0));
1146   }
1147 }
1148 
1149 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) {
1150   if (reachable(src)) {
1151     Assembler::addpd(dst, as_Address(src));
1152   } else {
1153     lea(rscratch1, src);
1154     Assembler::addpd(dst, Address(rscratch1, 0));
1155   }
1156 }
1157 
1158 // See 8273459.  Function for ensuring 64-byte alignment, intended for stubs only.
1159 // Stub code is generated once and never copied.
1160 // NMethods can't use this because they get copied and we can't force alignment > 32 bytes.
1161 void MacroAssembler::align64() {
1162   align(64, (unsigned long long) pc());
1163 }
1164 
1165 void MacroAssembler::align32() {
1166   align(32, (unsigned long long) pc());
1167 }
1168 
1169 void MacroAssembler::align(int modulus) {
1170   // 8273459: Ensure alignment is possible with current segment alignment
1171   assert(modulus <= CodeEntryAlignment, "Alignment must be <= CodeEntryAlignment");
1172   align(modulus, offset());
1173 }
1174 
1175 void MacroAssembler::align(int modulus, int target) {
1176   if (target % modulus != 0) {
1177     nop(modulus - (target % modulus));
1178   }
1179 }
1180 
1181 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1182   // Used in sign-masking with aligned address.
1183   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1184   if (reachable(src)) {
1185     Assembler::andpd(dst, as_Address(src));
1186   } else {
1187     lea(scratch_reg, src);
1188     Assembler::andpd(dst, Address(scratch_reg, 0));
1189   }
1190 }
1191 
1192 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
1193   // Used in sign-masking with aligned address.
1194   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
1195   if (reachable(src)) {
1196     Assembler::andps(dst, as_Address(src));
1197   } else {
1198     lea(scratch_reg, src);
1199     Assembler::andps(dst, Address(scratch_reg, 0));
1200   }
1201 }
1202 
1203 void MacroAssembler::andptr(Register dst, int32_t imm32) {
1204   LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32));
1205 }
1206 
1207 void MacroAssembler::atomic_incl(Address counter_addr) {
1208   lock();
1209   incrementl(counter_addr);
1210 }
1211 
1212 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) {
1213   if (reachable(counter_addr)) {
1214     atomic_incl(as_Address(counter_addr));
1215   } else {
1216     lea(scr, counter_addr);
1217     atomic_incl(Address(scr, 0));
1218   }
1219 }
1220 
1221 #ifdef _LP64
1222 void MacroAssembler::atomic_incq(Address counter_addr) {
1223   lock();
1224   incrementq(counter_addr);
1225 }
1226 
1227 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) {
1228   if (reachable(counter_addr)) {
1229     atomic_incq(as_Address(counter_addr));
1230   } else {
1231     lea(scr, counter_addr);
1232     atomic_incq(Address(scr, 0));
1233   }
1234 }
1235 #endif
1236 
1237 // Writes to stack successive pages until offset reached to check for
1238 // stack overflow + shadow pages.  This clobbers tmp.
1239 void MacroAssembler::bang_stack_size(Register size, Register tmp) {
1240   movptr(tmp, rsp);
1241   // Bang stack for total size given plus shadow page size.
1242   // Bang one page at a time because large size can bang beyond yellow and
1243   // red zones.
1244   Label loop;
1245   bind(loop);
1246   movl(Address(tmp, (-os::vm_page_size())), size );
1247   subptr(tmp, os::vm_page_size());
1248   subl(size, os::vm_page_size());
1249   jcc(Assembler::greater, loop);
1250 
1251   // Bang down shadow pages too.
1252   // At this point, (tmp-0) is the last address touched, so don't
1253   // touch it again.  (It was touched as (tmp-pagesize) but then tmp
1254   // was post-decremented.)  Skip this address by starting at i=1, and
1255   // touch a few more pages below.  N.B.  It is important to touch all
1256   // the way down including all pages in the shadow zone.
1257   for (int i = 1; i < ((int)StackOverflow::stack_shadow_zone_size() / os::vm_page_size()); i++) {
1258     // this could be any sized move but this is can be a debugging crumb
1259     // so the bigger the better.
1260     movptr(Address(tmp, (-i*os::vm_page_size())), size );
1261   }
1262 }
1263 
1264 void MacroAssembler::reserved_stack_check() {
1265     // testing if reserved zone needs to be enabled
1266     Label no_reserved_zone_enabling;
1267     Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread);
1268     NOT_LP64(get_thread(rsi);)
1269 
1270     cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset()));
1271     jcc(Assembler::below, no_reserved_zone_enabling);
1272 
1273     call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread);
1274     jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry()));
1275     should_not_reach_here();
1276 
1277     bind(no_reserved_zone_enabling);
1278 }
1279 
1280 void MacroAssembler::c2bool(Register x) {
1281   // implements x == 0 ? 0 : 1
1282   // note: must only look at least-significant byte of x
1283   //       since C-style booleans are stored in one byte
1284   //       only! (was bug)
1285   andl(x, 0xFF);
1286   setb(Assembler::notZero, x);
1287 }
1288 
1289 // Wouldn't need if AddressLiteral version had new name
1290 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) {
1291   Assembler::call(L, rtype);
1292 }
1293 
1294 void MacroAssembler::call(Register entry) {
1295   Assembler::call(entry);
1296 }
1297 
1298 void MacroAssembler::call(AddressLiteral entry) {
1299   if (reachable(entry)) {
1300     Assembler::call_literal(entry.target(), entry.rspec());
1301   } else {
1302     lea(rscratch1, entry);
1303     Assembler::call(rscratch1);
1304   }
1305 }
1306 
1307 void MacroAssembler::ic_call(address entry, jint method_index) {
1308   RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index);
1309   movptr(rax, (intptr_t)Universe::non_oop_word());
1310   call(AddressLiteral(entry, rh));
1311 }
1312 
1313 // Implementation of call_VM versions
1314 
1315 void MacroAssembler::call_VM(Register oop_result,
1316                              address entry_point,
1317                              bool check_exceptions) {
1318   Label C, E;
1319   call(C, relocInfo::none);
1320   jmp(E);
1321 
1322   bind(C);
1323   call_VM_helper(oop_result, entry_point, 0, check_exceptions);
1324   ret(0);
1325 
1326   bind(E);
1327 }
1328 
1329 void MacroAssembler::call_VM(Register oop_result,
1330                              address entry_point,
1331                              Register arg_1,
1332                              bool check_exceptions) {
1333   Label C, E;
1334   call(C, relocInfo::none);
1335   jmp(E);
1336 
1337   bind(C);
1338   pass_arg1(this, arg_1);
1339   call_VM_helper(oop_result, entry_point, 1, check_exceptions);
1340   ret(0);
1341 
1342   bind(E);
1343 }
1344 
1345 void MacroAssembler::call_VM(Register oop_result,
1346                              address entry_point,
1347                              Register arg_1,
1348                              Register arg_2,
1349                              bool check_exceptions) {
1350   Label C, E;
1351   call(C, relocInfo::none);
1352   jmp(E);
1353 
1354   bind(C);
1355 
1356   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1357 
1358   pass_arg2(this, arg_2);
1359   pass_arg1(this, arg_1);
1360   call_VM_helper(oop_result, entry_point, 2, check_exceptions);
1361   ret(0);
1362 
1363   bind(E);
1364 }
1365 
1366 void MacroAssembler::call_VM(Register oop_result,
1367                              address entry_point,
1368                              Register arg_1,
1369                              Register arg_2,
1370                              Register arg_3,
1371                              bool check_exceptions) {
1372   Label C, E;
1373   call(C, relocInfo::none);
1374   jmp(E);
1375 
1376   bind(C);
1377 
1378   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1379   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1380   pass_arg3(this, arg_3);
1381 
1382   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1383   pass_arg2(this, arg_2);
1384 
1385   pass_arg1(this, arg_1);
1386   call_VM_helper(oop_result, entry_point, 3, check_exceptions);
1387   ret(0);
1388 
1389   bind(E);
1390 }
1391 
1392 void MacroAssembler::call_VM(Register oop_result,
1393                              Register last_java_sp,
1394                              address entry_point,
1395                              int number_of_arguments,
1396                              bool check_exceptions) {
1397   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1398   call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1399 }
1400 
1401 void MacroAssembler::call_VM(Register oop_result,
1402                              Register last_java_sp,
1403                              address entry_point,
1404                              Register arg_1,
1405                              bool check_exceptions) {
1406   pass_arg1(this, arg_1);
1407   call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1408 }
1409 
1410 void MacroAssembler::call_VM(Register oop_result,
1411                              Register last_java_sp,
1412                              address entry_point,
1413                              Register arg_1,
1414                              Register arg_2,
1415                              bool check_exceptions) {
1416 
1417   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1418   pass_arg2(this, arg_2);
1419   pass_arg1(this, arg_1);
1420   call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1421 }
1422 
1423 void MacroAssembler::call_VM(Register oop_result,
1424                              Register last_java_sp,
1425                              address entry_point,
1426                              Register arg_1,
1427                              Register arg_2,
1428                              Register arg_3,
1429                              bool check_exceptions) {
1430   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1431   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1432   pass_arg3(this, arg_3);
1433   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1434   pass_arg2(this, arg_2);
1435   pass_arg1(this, arg_1);
1436   call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1437 }
1438 
1439 void MacroAssembler::super_call_VM(Register oop_result,
1440                                    Register last_java_sp,
1441                                    address entry_point,
1442                                    int number_of_arguments,
1443                                    bool check_exceptions) {
1444   Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg);
1445   MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions);
1446 }
1447 
1448 void MacroAssembler::super_call_VM(Register oop_result,
1449                                    Register last_java_sp,
1450                                    address entry_point,
1451                                    Register arg_1,
1452                                    bool check_exceptions) {
1453   pass_arg1(this, arg_1);
1454   super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions);
1455 }
1456 
1457 void MacroAssembler::super_call_VM(Register oop_result,
1458                                    Register last_java_sp,
1459                                    address entry_point,
1460                                    Register arg_1,
1461                                    Register arg_2,
1462                                    bool check_exceptions) {
1463 
1464   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1465   pass_arg2(this, arg_2);
1466   pass_arg1(this, arg_1);
1467   super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions);
1468 }
1469 
1470 void MacroAssembler::super_call_VM(Register oop_result,
1471                                    Register last_java_sp,
1472                                    address entry_point,
1473                                    Register arg_1,
1474                                    Register arg_2,
1475                                    Register arg_3,
1476                                    bool check_exceptions) {
1477   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1478   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1479   pass_arg3(this, arg_3);
1480   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1481   pass_arg2(this, arg_2);
1482   pass_arg1(this, arg_1);
1483   super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions);
1484 }
1485 
1486 void MacroAssembler::call_VM_base(Register oop_result,
1487                                   Register java_thread,
1488                                   Register last_java_sp,
1489                                   address  entry_point,
1490                                   int      number_of_arguments,
1491                                   bool     check_exceptions) {
1492   // determine java_thread register
1493   if (!java_thread->is_valid()) {
1494 #ifdef _LP64
1495     java_thread = r15_thread;
1496 #else
1497     java_thread = rdi;
1498     get_thread(java_thread);
1499 #endif // LP64
1500   }
1501   // determine last_java_sp register
1502   if (!last_java_sp->is_valid()) {
1503     last_java_sp = rsp;
1504   }
1505   // debugging support
1506   assert(number_of_arguments >= 0   , "cannot have negative number of arguments");
1507   LP64_ONLY(assert(java_thread == r15_thread, "unexpected register"));
1508 #ifdef ASSERT
1509   // TraceBytecodes does not use r12 but saves it over the call, so don't verify
1510   // r12 is the heapbase.
1511   LP64_ONLY(if (UseCompressedOops && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");)
1512 #endif // ASSERT
1513 
1514   assert(java_thread != oop_result  , "cannot use the same register for java_thread & oop_result");
1515   assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp");
1516 
1517   // push java thread (becomes first argument of C function)
1518 
1519   NOT_LP64(push(java_thread); number_of_arguments++);
1520   LP64_ONLY(mov(c_rarg0, r15_thread));
1521 
1522   // set last Java frame before call
1523   assert(last_java_sp != rbp, "can't use ebp/rbp");
1524 
1525   // Only interpreter should have to set fp
1526   set_last_Java_frame(java_thread, last_java_sp, rbp, NULL);
1527 
1528   // do the call, remove parameters
1529   MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments);
1530 
1531   // restore the thread (cannot use the pushed argument since arguments
1532   // may be overwritten by C code generated by an optimizing compiler);
1533   // however can use the register value directly if it is callee saved.
1534   if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) {
1535     // rdi & rsi (also r15) are callee saved -> nothing to do
1536 #ifdef ASSERT
1537     guarantee(java_thread != rax, "change this code");
1538     push(rax);
1539     { Label L;
1540       get_thread(rax);
1541       cmpptr(java_thread, rax);
1542       jcc(Assembler::equal, L);
1543       STOP("MacroAssembler::call_VM_base: rdi not callee saved?");
1544       bind(L);
1545     }
1546     pop(rax);
1547 #endif
1548   } else {
1549     get_thread(java_thread);
1550   }
1551   // reset last Java frame
1552   // Only interpreter should have to clear fp
1553   reset_last_Java_frame(java_thread, true);
1554 
1555    // C++ interp handles this in the interpreter
1556   check_and_handle_popframe(java_thread);
1557   check_and_handle_earlyret(java_thread);
1558 
1559   if (check_exceptions) {
1560     // check for pending exceptions (java_thread is set upon return)
1561     cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD);
1562 #ifndef _LP64
1563     jump_cc(Assembler::notEqual,
1564             RuntimeAddress(StubRoutines::forward_exception_entry()));
1565 #else
1566     // This used to conditionally jump to forward_exception however it is
1567     // possible if we relocate that the branch will not reach. So we must jump
1568     // around so we can always reach
1569 
1570     Label ok;
1571     jcc(Assembler::equal, ok);
1572     jump(RuntimeAddress(StubRoutines::forward_exception_entry()));
1573     bind(ok);
1574 #endif // LP64
1575   }
1576 
1577   // get oop result if there is one and reset the value in the thread
1578   if (oop_result->is_valid()) {
1579     get_vm_result(oop_result, java_thread);
1580   }
1581 }
1582 
1583 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) {
1584 
1585   // Calculate the value for last_Java_sp
1586   // somewhat subtle. call_VM does an intermediate call
1587   // which places a return address on the stack just under the
1588   // stack pointer as the user finished with it. This allows
1589   // use to retrieve last_Java_pc from last_Java_sp[-1].
1590   // On 32bit we then have to push additional args on the stack to accomplish
1591   // the actual requested call. On 64bit call_VM only can use register args
1592   // so the only extra space is the return address that call_VM created.
1593   // This hopefully explains the calculations here.
1594 
1595 #ifdef _LP64
1596   // We've pushed one address, correct last_Java_sp
1597   lea(rax, Address(rsp, wordSize));
1598 #else
1599   lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize));
1600 #endif // LP64
1601 
1602   call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions);
1603 
1604 }
1605 
1606 // Use this method when MacroAssembler version of call_VM_leaf_base() should be called from Interpreter.
1607 void MacroAssembler::call_VM_leaf0(address entry_point) {
1608   MacroAssembler::call_VM_leaf_base(entry_point, 0);
1609 }
1610 
1611 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) {
1612   call_VM_leaf_base(entry_point, number_of_arguments);
1613 }
1614 
1615 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) {
1616   pass_arg0(this, arg_0);
1617   call_VM_leaf(entry_point, 1);
1618 }
1619 
1620 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1621 
1622   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1623   pass_arg1(this, arg_1);
1624   pass_arg0(this, arg_0);
1625   call_VM_leaf(entry_point, 2);
1626 }
1627 
1628 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1629   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1630   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1631   pass_arg2(this, arg_2);
1632   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1633   pass_arg1(this, arg_1);
1634   pass_arg0(this, arg_0);
1635   call_VM_leaf(entry_point, 3);
1636 }
1637 
1638 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) {
1639   pass_arg0(this, arg_0);
1640   MacroAssembler::call_VM_leaf_base(entry_point, 1);
1641 }
1642 
1643 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) {
1644 
1645   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1646   pass_arg1(this, arg_1);
1647   pass_arg0(this, arg_0);
1648   MacroAssembler::call_VM_leaf_base(entry_point, 2);
1649 }
1650 
1651 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) {
1652   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1653   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1654   pass_arg2(this, arg_2);
1655   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1656   pass_arg1(this, arg_1);
1657   pass_arg0(this, arg_0);
1658   MacroAssembler::call_VM_leaf_base(entry_point, 3);
1659 }
1660 
1661 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) {
1662   LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg"));
1663   LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg"));
1664   LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg"));
1665   pass_arg3(this, arg_3);
1666   LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg"));
1667   LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg"));
1668   pass_arg2(this, arg_2);
1669   LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg"));
1670   pass_arg1(this, arg_1);
1671   pass_arg0(this, arg_0);
1672   MacroAssembler::call_VM_leaf_base(entry_point, 4);
1673 }
1674 
1675 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) {
1676   movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset()));
1677   movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD);
1678   verify_oop_msg(oop_result, "broken oop in call_VM_base");
1679 }
1680 
1681 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) {
1682   movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset()));
1683   movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD);
1684 }
1685 
1686 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
1687 }
1688 
1689 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
1690 }
1691 
1692 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) {
1693   if (reachable(src1)) {
1694     cmpl(as_Address(src1), imm);
1695   } else {
1696     lea(rscratch1, src1);
1697     cmpl(Address(rscratch1, 0), imm);
1698   }
1699 }
1700 
1701 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) {
1702   assert(!src2.is_lval(), "use cmpptr");
1703   if (reachable(src2)) {
1704     cmpl(src1, as_Address(src2));
1705   } else {
1706     lea(rscratch1, src2);
1707     cmpl(src1, Address(rscratch1, 0));
1708   }
1709 }
1710 
1711 void MacroAssembler::cmp32(Register src1, int32_t imm) {
1712   Assembler::cmpl(src1, imm);
1713 }
1714 
1715 void MacroAssembler::cmp32(Register src1, Address src2) {
1716   Assembler::cmpl(src1, src2);
1717 }
1718 
1719 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1720   ucomisd(opr1, opr2);
1721 
1722   Label L;
1723   if (unordered_is_less) {
1724     movl(dst, -1);
1725     jcc(Assembler::parity, L);
1726     jcc(Assembler::below , L);
1727     movl(dst, 0);
1728     jcc(Assembler::equal , L);
1729     increment(dst);
1730   } else { // unordered is greater
1731     movl(dst, 1);
1732     jcc(Assembler::parity, L);
1733     jcc(Assembler::above , L);
1734     movl(dst, 0);
1735     jcc(Assembler::equal , L);
1736     decrementl(dst);
1737   }
1738   bind(L);
1739 }
1740 
1741 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) {
1742   ucomiss(opr1, opr2);
1743 
1744   Label L;
1745   if (unordered_is_less) {
1746     movl(dst, -1);
1747     jcc(Assembler::parity, L);
1748     jcc(Assembler::below , L);
1749     movl(dst, 0);
1750     jcc(Assembler::equal , L);
1751     increment(dst);
1752   } else { // unordered is greater
1753     movl(dst, 1);
1754     jcc(Assembler::parity, L);
1755     jcc(Assembler::above , L);
1756     movl(dst, 0);
1757     jcc(Assembler::equal , L);
1758     decrementl(dst);
1759   }
1760   bind(L);
1761 }
1762 
1763 
1764 void MacroAssembler::cmp8(AddressLiteral src1, int imm) {
1765   if (reachable(src1)) {
1766     cmpb(as_Address(src1), imm);
1767   } else {
1768     lea(rscratch1, src1);
1769     cmpb(Address(rscratch1, 0), imm);
1770   }
1771 }
1772 
1773 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) {
1774 #ifdef _LP64
1775   if (src2.is_lval()) {
1776     movptr(rscratch1, src2);
1777     Assembler::cmpq(src1, rscratch1);
1778   } else if (reachable(src2)) {
1779     cmpq(src1, as_Address(src2));
1780   } else {
1781     lea(rscratch1, src2);
1782     Assembler::cmpq(src1, Address(rscratch1, 0));
1783   }
1784 #else
1785   if (src2.is_lval()) {
1786     cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1787   } else {
1788     cmpl(src1, as_Address(src2));
1789   }
1790 #endif // _LP64
1791 }
1792 
1793 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) {
1794   assert(src2.is_lval(), "not a mem-mem compare");
1795 #ifdef _LP64
1796   // moves src2's literal address
1797   movptr(rscratch1, src2);
1798   Assembler::cmpq(src1, rscratch1);
1799 #else
1800   cmp_literal32(src1, (int32_t) src2.target(), src2.rspec());
1801 #endif // _LP64
1802 }
1803 
1804 void MacroAssembler::cmpoop(Register src1, Register src2) {
1805   cmpptr(src1, src2);
1806 }
1807 
1808 void MacroAssembler::cmpoop(Register src1, Address src2) {
1809   cmpptr(src1, src2);
1810 }
1811 
1812 #ifdef _LP64
1813 void MacroAssembler::cmpoop(Register src1, jobject src2) {
1814   movoop(rscratch1, src2);
1815   cmpptr(src1, rscratch1);
1816 }
1817 #endif
1818 
1819 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) {
1820   if (reachable(adr)) {
1821     lock();
1822     cmpxchgptr(reg, as_Address(adr));
1823   } else {
1824     lea(rscratch1, adr);
1825     lock();
1826     cmpxchgptr(reg, Address(rscratch1, 0));
1827   }
1828 }
1829 
1830 void MacroAssembler::cmpxchgptr(Register reg, Address adr) {
1831   LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr));
1832 }
1833 
1834 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) {
1835   if (reachable(src)) {
1836     Assembler::comisd(dst, as_Address(src));
1837   } else {
1838     lea(rscratch1, src);
1839     Assembler::comisd(dst, Address(rscratch1, 0));
1840   }
1841 }
1842 
1843 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) {
1844   if (reachable(src)) {
1845     Assembler::comiss(dst, as_Address(src));
1846   } else {
1847     lea(rscratch1, src);
1848     Assembler::comiss(dst, Address(rscratch1, 0));
1849   }
1850 }
1851 
1852 
1853 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) {
1854   Condition negated_cond = negate_condition(cond);
1855   Label L;
1856   jcc(negated_cond, L);
1857   pushf(); // Preserve flags
1858   atomic_incl(counter_addr);
1859   popf();
1860   bind(L);
1861 }
1862 
1863 int MacroAssembler::corrected_idivl(Register reg) {
1864   // Full implementation of Java idiv and irem; checks for
1865   // special case as described in JVM spec., p.243 & p.271.
1866   // The function returns the (pc) offset of the idivl
1867   // instruction - may be needed for implicit exceptions.
1868   //
1869   //         normal case                           special case
1870   //
1871   // input : rax,: dividend                         min_int
1872   //         reg: divisor   (may not be rax,/rdx)   -1
1873   //
1874   // output: rax,: quotient  (= rax, idiv reg)       min_int
1875   //         rdx: remainder (= rax, irem reg)       0
1876   assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register");
1877   const int min_int = 0x80000000;
1878   Label normal_case, special_case;
1879 
1880   // check for special case
1881   cmpl(rax, min_int);
1882   jcc(Assembler::notEqual, normal_case);
1883   xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0)
1884   cmpl(reg, -1);
1885   jcc(Assembler::equal, special_case);
1886 
1887   // handle normal case
1888   bind(normal_case);
1889   cdql();
1890   int idivl_offset = offset();
1891   idivl(reg);
1892 
1893   // normal and special case exit
1894   bind(special_case);
1895 
1896   return idivl_offset;
1897 }
1898 
1899 
1900 
1901 void MacroAssembler::decrementl(Register reg, int value) {
1902   if (value == min_jint) {subl(reg, value) ; return; }
1903   if (value <  0) { incrementl(reg, -value); return; }
1904   if (value == 0) {                        ; return; }
1905   if (value == 1 && UseIncDec) { decl(reg) ; return; }
1906   /* else */      { subl(reg, value)       ; return; }
1907 }
1908 
1909 void MacroAssembler::decrementl(Address dst, int value) {
1910   if (value == min_jint) {subl(dst, value) ; return; }
1911   if (value <  0) { incrementl(dst, -value); return; }
1912   if (value == 0) {                        ; return; }
1913   if (value == 1 && UseIncDec) { decl(dst) ; return; }
1914   /* else */      { subl(dst, value)       ; return; }
1915 }
1916 
1917 void MacroAssembler::division_with_shift (Register reg, int shift_value) {
1918   assert (shift_value > 0, "illegal shift value");
1919   Label _is_positive;
1920   testl (reg, reg);
1921   jcc (Assembler::positive, _is_positive);
1922   int offset = (1 << shift_value) - 1 ;
1923 
1924   if (offset == 1) {
1925     incrementl(reg);
1926   } else {
1927     addl(reg, offset);
1928   }
1929 
1930   bind (_is_positive);
1931   sarl(reg, shift_value);
1932 }
1933 
1934 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) {
1935   if (reachable(src)) {
1936     Assembler::divsd(dst, as_Address(src));
1937   } else {
1938     lea(rscratch1, src);
1939     Assembler::divsd(dst, Address(rscratch1, 0));
1940   }
1941 }
1942 
1943 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) {
1944   if (reachable(src)) {
1945     Assembler::divss(dst, as_Address(src));
1946   } else {
1947     lea(rscratch1, src);
1948     Assembler::divss(dst, Address(rscratch1, 0));
1949   }
1950 }
1951 
1952 void MacroAssembler::enter() {
1953   push(rbp);
1954   mov(rbp, rsp);
1955 }
1956 
1957 // A 5 byte nop that is safe for patching (see patch_verified_entry)
1958 void MacroAssembler::fat_nop() {
1959   if (UseAddressNop) {
1960     addr_nop_5();
1961   } else {
1962     emit_int8(0x26); // es:
1963     emit_int8(0x2e); // cs:
1964     emit_int8(0x64); // fs:
1965     emit_int8(0x65); // gs:
1966     emit_int8((unsigned char)0x90);
1967   }
1968 }
1969 
1970 #ifndef _LP64
1971 void MacroAssembler::fcmp(Register tmp) {
1972   fcmp(tmp, 1, true, true);
1973 }
1974 
1975 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) {
1976   assert(!pop_right || pop_left, "usage error");
1977   if (VM_Version::supports_cmov()) {
1978     assert(tmp == noreg, "unneeded temp");
1979     if (pop_left) {
1980       fucomip(index);
1981     } else {
1982       fucomi(index);
1983     }
1984     if (pop_right) {
1985       fpop();
1986     }
1987   } else {
1988     assert(tmp != noreg, "need temp");
1989     if (pop_left) {
1990       if (pop_right) {
1991         fcompp();
1992       } else {
1993         fcomp(index);
1994       }
1995     } else {
1996       fcom(index);
1997     }
1998     // convert FPU condition into eflags condition via rax,
1999     save_rax(tmp);
2000     fwait(); fnstsw_ax();
2001     sahf();
2002     restore_rax(tmp);
2003   }
2004   // condition codes set as follows:
2005   //
2006   // CF (corresponds to C0) if x < y
2007   // PF (corresponds to C2) if unordered
2008   // ZF (corresponds to C3) if x = y
2009 }
2010 
2011 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) {
2012   fcmp2int(dst, unordered_is_less, 1, true, true);
2013 }
2014 
2015 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) {
2016   fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right);
2017   Label L;
2018   if (unordered_is_less) {
2019     movl(dst, -1);
2020     jcc(Assembler::parity, L);
2021     jcc(Assembler::below , L);
2022     movl(dst, 0);
2023     jcc(Assembler::equal , L);
2024     increment(dst);
2025   } else { // unordered is greater
2026     movl(dst, 1);
2027     jcc(Assembler::parity, L);
2028     jcc(Assembler::above , L);
2029     movl(dst, 0);
2030     jcc(Assembler::equal , L);
2031     decrementl(dst);
2032   }
2033   bind(L);
2034 }
2035 
2036 void MacroAssembler::fld_d(AddressLiteral src) {
2037   fld_d(as_Address(src));
2038 }
2039 
2040 void MacroAssembler::fld_s(AddressLiteral src) {
2041   fld_s(as_Address(src));
2042 }
2043 
2044 void MacroAssembler::fldcw(AddressLiteral src) {
2045   Assembler::fldcw(as_Address(src));
2046 }
2047 
2048 void MacroAssembler::fpop() {
2049   ffree();
2050   fincstp();
2051 }
2052 
2053 void MacroAssembler::fremr(Register tmp) {
2054   save_rax(tmp);
2055   { Label L;
2056     bind(L);
2057     fprem();
2058     fwait(); fnstsw_ax();
2059     sahf();
2060     jcc(Assembler::parity, L);
2061   }
2062   restore_rax(tmp);
2063   // Result is in ST0.
2064   // Note: fxch & fpop to get rid of ST1
2065   // (otherwise FPU stack could overflow eventually)
2066   fxch(1);
2067   fpop();
2068 }
2069 
2070 void MacroAssembler::empty_FPU_stack() {
2071   if (VM_Version::supports_mmx()) {
2072     emms();
2073   } else {
2074     for (int i = 8; i-- > 0; ) ffree(i);
2075   }
2076 }
2077 #endif // !LP64
2078 
2079 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) {
2080   if (reachable(src)) {
2081     Assembler::mulpd(dst, as_Address(src));
2082   } else {
2083     lea(rscratch1, src);
2084     Assembler::mulpd(dst, Address(rscratch1, 0));
2085   }
2086 }
2087 
2088 void MacroAssembler::load_float(Address src) {
2089 #ifdef _LP64
2090   movflt(xmm0, src);
2091 #else
2092   if (UseSSE >= 1) {
2093     movflt(xmm0, src);
2094   } else {
2095     fld_s(src);
2096   }
2097 #endif // LP64
2098 }
2099 
2100 void MacroAssembler::store_float(Address dst) {
2101 #ifdef _LP64
2102   movflt(dst, xmm0);
2103 #else
2104   if (UseSSE >= 1) {
2105     movflt(dst, xmm0);
2106   } else {
2107     fstp_s(dst);
2108   }
2109 #endif // LP64
2110 }
2111 
2112 void MacroAssembler::load_double(Address src) {
2113 #ifdef _LP64
2114   movdbl(xmm0, src);
2115 #else
2116   if (UseSSE >= 2) {
2117     movdbl(xmm0, src);
2118   } else {
2119     fld_d(src);
2120   }
2121 #endif // LP64
2122 }
2123 
2124 void MacroAssembler::store_double(Address dst) {
2125 #ifdef _LP64
2126   movdbl(dst, xmm0);
2127 #else
2128   if (UseSSE >= 2) {
2129     movdbl(dst, xmm0);
2130   } else {
2131     fstp_d(dst);
2132   }
2133 #endif // LP64
2134 }
2135 
2136 // dst = c = a * b + c
2137 void MacroAssembler::fmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2138   Assembler::vfmadd231sd(c, a, b);
2139   if (dst != c) {
2140     movdbl(dst, c);
2141   }
2142 }
2143 
2144 // dst = c = a * b + c
2145 void MacroAssembler::fmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c) {
2146   Assembler::vfmadd231ss(c, a, b);
2147   if (dst != c) {
2148     movflt(dst, c);
2149   }
2150 }
2151 
2152 // dst = c = a * b + c
2153 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2154   Assembler::vfmadd231pd(c, a, b, vector_len);
2155   if (dst != c) {
2156     vmovdqu(dst, c);
2157   }
2158 }
2159 
2160 // dst = c = a * b + c
2161 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, XMMRegister b, XMMRegister c, int vector_len) {
2162   Assembler::vfmadd231ps(c, a, b, vector_len);
2163   if (dst != c) {
2164     vmovdqu(dst, c);
2165   }
2166 }
2167 
2168 // dst = c = a * b + c
2169 void MacroAssembler::vfmad(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2170   Assembler::vfmadd231pd(c, a, b, vector_len);
2171   if (dst != c) {
2172     vmovdqu(dst, c);
2173   }
2174 }
2175 
2176 // dst = c = a * b + c
2177 void MacroAssembler::vfmaf(XMMRegister dst, XMMRegister a, Address b, XMMRegister c, int vector_len) {
2178   Assembler::vfmadd231ps(c, a, b, vector_len);
2179   if (dst != c) {
2180     vmovdqu(dst, c);
2181   }
2182 }
2183 
2184 void MacroAssembler::incrementl(AddressLiteral dst) {
2185   if (reachable(dst)) {
2186     incrementl(as_Address(dst));
2187   } else {
2188     lea(rscratch1, dst);
2189     incrementl(Address(rscratch1, 0));
2190   }
2191 }
2192 
2193 void MacroAssembler::incrementl(ArrayAddress dst) {
2194   incrementl(as_Address(dst));
2195 }
2196 
2197 void MacroAssembler::incrementl(Register reg, int value) {
2198   if (value == min_jint) {addl(reg, value) ; return; }
2199   if (value <  0) { decrementl(reg, -value); return; }
2200   if (value == 0) {                        ; return; }
2201   if (value == 1 && UseIncDec) { incl(reg) ; return; }
2202   /* else */      { addl(reg, value)       ; return; }
2203 }
2204 
2205 void MacroAssembler::incrementl(Address dst, int value) {
2206   if (value == min_jint) {addl(dst, value) ; return; }
2207   if (value <  0) { decrementl(dst, -value); return; }
2208   if (value == 0) {                        ; return; }
2209   if (value == 1 && UseIncDec) { incl(dst) ; return; }
2210   /* else */      { addl(dst, value)       ; return; }
2211 }
2212 
2213 void MacroAssembler::jump(AddressLiteral dst) {
2214   if (reachable(dst)) {
2215     jmp_literal(dst.target(), dst.rspec());
2216   } else {
2217     lea(rscratch1, dst);
2218     jmp(rscratch1);
2219   }
2220 }
2221 
2222 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) {
2223   if (reachable(dst)) {
2224     InstructionMark im(this);
2225     relocate(dst.reloc());
2226     const int short_size = 2;
2227     const int long_size = 6;
2228     int offs = (intptr_t)dst.target() - ((intptr_t)pc());
2229     if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) {
2230       // 0111 tttn #8-bit disp
2231       emit_int8(0x70 | cc);
2232       emit_int8((offs - short_size) & 0xFF);
2233     } else {
2234       // 0000 1111 1000 tttn #32-bit disp
2235       emit_int8(0x0F);
2236       emit_int8((unsigned char)(0x80 | cc));
2237       emit_int32(offs - long_size);
2238     }
2239   } else {
2240 #ifdef ASSERT
2241     warning("reversing conditional branch");
2242 #endif /* ASSERT */
2243     Label skip;
2244     jccb(reverse[cc], skip);
2245     lea(rscratch1, dst);
2246     Assembler::jmp(rscratch1);
2247     bind(skip);
2248   }
2249 }
2250 
2251 void MacroAssembler::fld_x(AddressLiteral src) {
2252   Assembler::fld_x(as_Address(src));
2253 }
2254 
2255 void MacroAssembler::ldmxcsr(AddressLiteral src, Register scratchReg) {
2256   if (reachable(src)) {
2257     Assembler::ldmxcsr(as_Address(src));
2258   } else {
2259     lea(scratchReg, src);
2260     Assembler::ldmxcsr(Address(scratchReg, 0));
2261   }
2262 }
2263 
2264 int MacroAssembler::load_signed_byte(Register dst, Address src) {
2265   int off;
2266   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2267     off = offset();
2268     movsbl(dst, src); // movsxb
2269   } else {
2270     off = load_unsigned_byte(dst, src);
2271     shll(dst, 24);
2272     sarl(dst, 24);
2273   }
2274   return off;
2275 }
2276 
2277 // Note: load_signed_short used to be called load_signed_word.
2278 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler
2279 // manual, which means 16 bits, that usage is found nowhere in HotSpot code.
2280 // The term "word" in HotSpot means a 32- or 64-bit machine word.
2281 int MacroAssembler::load_signed_short(Register dst, Address src) {
2282   int off;
2283   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2284     // This is dubious to me since it seems safe to do a signed 16 => 64 bit
2285     // version but this is what 64bit has always done. This seems to imply
2286     // that users are only using 32bits worth.
2287     off = offset();
2288     movswl(dst, src); // movsxw
2289   } else {
2290     off = load_unsigned_short(dst, src);
2291     shll(dst, 16);
2292     sarl(dst, 16);
2293   }
2294   return off;
2295 }
2296 
2297 int MacroAssembler::load_unsigned_byte(Register dst, Address src) {
2298   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2299   // and "3.9 Partial Register Penalties", p. 22).
2300   int off;
2301   if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) {
2302     off = offset();
2303     movzbl(dst, src); // movzxb
2304   } else {
2305     xorl(dst, dst);
2306     off = offset();
2307     movb(dst, src);
2308   }
2309   return off;
2310 }
2311 
2312 // Note: load_unsigned_short used to be called load_unsigned_word.
2313 int MacroAssembler::load_unsigned_short(Register dst, Address src) {
2314   // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16,
2315   // and "3.9 Partial Register Penalties", p. 22).
2316   int off;
2317   if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) {
2318     off = offset();
2319     movzwl(dst, src); // movzxw
2320   } else {
2321     xorl(dst, dst);
2322     off = offset();
2323     movw(dst, src);
2324   }
2325   return off;
2326 }
2327 
2328 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) {
2329   switch (size_in_bytes) {
2330 #ifndef _LP64
2331   case  8:
2332     assert(dst2 != noreg, "second dest register required");
2333     movl(dst,  src);
2334     movl(dst2, src.plus_disp(BytesPerInt));
2335     break;
2336 #else
2337   case  8:  movq(dst, src); break;
2338 #endif
2339   case  4:  movl(dst, src); break;
2340   case  2:  is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break;
2341   case  1:  is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break;
2342   default:  ShouldNotReachHere();
2343   }
2344 }
2345 
2346 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) {
2347   switch (size_in_bytes) {
2348 #ifndef _LP64
2349   case  8:
2350     assert(src2 != noreg, "second source register required");
2351     movl(dst,                        src);
2352     movl(dst.plus_disp(BytesPerInt), src2);
2353     break;
2354 #else
2355   case  8:  movq(dst, src); break;
2356 #endif
2357   case  4:  movl(dst, src); break;
2358   case  2:  movw(dst, src); break;
2359   case  1:  movb(dst, src); break;
2360   default:  ShouldNotReachHere();
2361   }
2362 }
2363 
2364 void MacroAssembler::mov32(AddressLiteral dst, Register src) {
2365   if (reachable(dst)) {
2366     movl(as_Address(dst), src);
2367   } else {
2368     lea(rscratch1, dst);
2369     movl(Address(rscratch1, 0), src);
2370   }
2371 }
2372 
2373 void MacroAssembler::mov32(Register dst, AddressLiteral src) {
2374   if (reachable(src)) {
2375     movl(dst, as_Address(src));
2376   } else {
2377     lea(rscratch1, src);
2378     movl(dst, Address(rscratch1, 0));
2379   }
2380 }
2381 
2382 // C++ bool manipulation
2383 
2384 void MacroAssembler::movbool(Register dst, Address src) {
2385   if(sizeof(bool) == 1)
2386     movb(dst, src);
2387   else if(sizeof(bool) == 2)
2388     movw(dst, src);
2389   else if(sizeof(bool) == 4)
2390     movl(dst, src);
2391   else
2392     // unsupported
2393     ShouldNotReachHere();
2394 }
2395 
2396 void MacroAssembler::movbool(Address dst, bool boolconst) {
2397   if(sizeof(bool) == 1)
2398     movb(dst, (int) boolconst);
2399   else if(sizeof(bool) == 2)
2400     movw(dst, (int) boolconst);
2401   else if(sizeof(bool) == 4)
2402     movl(dst, (int) boolconst);
2403   else
2404     // unsupported
2405     ShouldNotReachHere();
2406 }
2407 
2408 void MacroAssembler::movbool(Address dst, Register src) {
2409   if(sizeof(bool) == 1)
2410     movb(dst, src);
2411   else if(sizeof(bool) == 2)
2412     movw(dst, src);
2413   else if(sizeof(bool) == 4)
2414     movl(dst, src);
2415   else
2416     // unsupported
2417     ShouldNotReachHere();
2418 }
2419 
2420 void MacroAssembler::movbyte(ArrayAddress dst, int src) {
2421   movb(as_Address(dst), src);
2422 }
2423 
2424 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) {
2425   if (reachable(src)) {
2426     movdl(dst, as_Address(src));
2427   } else {
2428     lea(rscratch1, src);
2429     movdl(dst, Address(rscratch1, 0));
2430   }
2431 }
2432 
2433 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) {
2434   if (reachable(src)) {
2435     movq(dst, as_Address(src));
2436   } else {
2437     lea(rscratch1, src);
2438     movq(dst, Address(rscratch1, 0));
2439   }
2440 }
2441 
2442 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) {
2443   if (reachable(src)) {
2444     if (UseXmmLoadAndClearUpper) {
2445       movsd (dst, as_Address(src));
2446     } else {
2447       movlpd(dst, as_Address(src));
2448     }
2449   } else {
2450     lea(rscratch1, src);
2451     if (UseXmmLoadAndClearUpper) {
2452       movsd (dst, Address(rscratch1, 0));
2453     } else {
2454       movlpd(dst, Address(rscratch1, 0));
2455     }
2456   }
2457 }
2458 
2459 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) {
2460   if (reachable(src)) {
2461     movss(dst, as_Address(src));
2462   } else {
2463     lea(rscratch1, src);
2464     movss(dst, Address(rscratch1, 0));
2465   }
2466 }
2467 
2468 void MacroAssembler::movptr(Register dst, Register src) {
2469   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2470 }
2471 
2472 void MacroAssembler::movptr(Register dst, Address src) {
2473   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2474 }
2475 
2476 // src should NEVER be a real pointer. Use AddressLiteral for true pointers
2477 void MacroAssembler::movptr(Register dst, intptr_t src) {
2478   LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src));
2479 }
2480 
2481 void MacroAssembler::movptr(Address dst, Register src) {
2482   LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2483 }
2484 
2485 void MacroAssembler::movdqu(Address dst, XMMRegister src) {
2486     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2487     Assembler::movdqu(dst, src);
2488 }
2489 
2490 void MacroAssembler::movdqu(XMMRegister dst, Address src) {
2491     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2492     Assembler::movdqu(dst, src);
2493 }
2494 
2495 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) {
2496     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2497     Assembler::movdqu(dst, src);
2498 }
2499 
2500 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src, Register scratchReg) {
2501   if (reachable(src)) {
2502     movdqu(dst, as_Address(src));
2503   } else {
2504     lea(scratchReg, src);
2505     movdqu(dst, Address(scratchReg, 0));
2506   }
2507 }
2508 
2509 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) {
2510     assert(((src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2511     Assembler::vmovdqu(dst, src);
2512 }
2513 
2514 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) {
2515     assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2516     Assembler::vmovdqu(dst, src);
2517 }
2518 
2519 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2520     assert(((dst->encoding() < 16  && src->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
2521     Assembler::vmovdqu(dst, src);
2522 }
2523 
2524 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
2525   if (reachable(src)) {
2526     vmovdqu(dst, as_Address(src));
2527   }
2528   else {
2529     lea(scratch_reg, src);
2530     vmovdqu(dst, Address(scratch_reg, 0));
2531   }
2532 }
2533 
2534 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src, Register scratch_reg, int vector_len) {
2535   assert(vector_len <= AVX_256bit, "AVX2 vector length");
2536   if (vector_len == AVX_256bit) {
2537     vmovdqu(dst, src, scratch_reg);
2538   } else {
2539     movdqu(dst, src, scratch_reg);
2540   }
2541 }
2542 
2543 void MacroAssembler::kmov(KRegister dst, Address src) {
2544   if (VM_Version::supports_avx512bw()) {
2545     kmovql(dst, src);
2546   } else {
2547     assert(VM_Version::supports_evex(), "");
2548     kmovwl(dst, src);
2549   }
2550 }
2551 
2552 void MacroAssembler::kmov(Address dst, KRegister src) {
2553   if (VM_Version::supports_avx512bw()) {
2554     kmovql(dst, src);
2555   } else {
2556     assert(VM_Version::supports_evex(), "");
2557     kmovwl(dst, src);
2558   }
2559 }
2560 
2561 void MacroAssembler::kmov(KRegister dst, KRegister src) {
2562   if (VM_Version::supports_avx512bw()) {
2563     kmovql(dst, src);
2564   } else {
2565     assert(VM_Version::supports_evex(), "");
2566     kmovwl(dst, src);
2567   }
2568 }
2569 
2570 void MacroAssembler::kmov(Register dst, KRegister src) {
2571   if (VM_Version::supports_avx512bw()) {
2572     kmovql(dst, src);
2573   } else {
2574     assert(VM_Version::supports_evex(), "");
2575     kmovwl(dst, src);
2576   }
2577 }
2578 
2579 void MacroAssembler::kmov(KRegister dst, Register src) {
2580   if (VM_Version::supports_avx512bw()) {
2581     kmovql(dst, src);
2582   } else {
2583     assert(VM_Version::supports_evex(), "");
2584     kmovwl(dst, src);
2585   }
2586 }
2587 
2588 void MacroAssembler::kmovql(KRegister dst, AddressLiteral src, Register scratch_reg) {
2589   if (reachable(src)) {
2590     kmovql(dst, as_Address(src));
2591   } else {
2592     lea(scratch_reg, src);
2593     kmovql(dst, Address(scratch_reg, 0));
2594   }
2595 }
2596 
2597 void MacroAssembler::kmovwl(KRegister dst, AddressLiteral src, Register scratch_reg) {
2598   if (reachable(src)) {
2599     kmovwl(dst, as_Address(src));
2600   } else {
2601     lea(scratch_reg, src);
2602     kmovwl(dst, Address(scratch_reg, 0));
2603   }
2604 }
2605 
2606 void MacroAssembler::evmovdqub(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2607                                int vector_len, Register scratch_reg) {
2608   if (reachable(src)) {
2609     if (mask == k0) {
2610       Assembler::evmovdqub(dst, as_Address(src), merge, vector_len);
2611     } else {
2612       Assembler::evmovdqub(dst, mask, as_Address(src), merge, vector_len);
2613     }
2614   } else {
2615     lea(scratch_reg, src);
2616     if (mask == k0) {
2617       Assembler::evmovdqub(dst, Address(scratch_reg, 0), merge, vector_len);
2618     } else {
2619       Assembler::evmovdqub(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2620     }
2621   }
2622 }
2623 
2624 void MacroAssembler::evmovdquw(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2625                                int vector_len, Register scratch_reg) {
2626   if (reachable(src)) {
2627     Assembler::evmovdquw(dst, mask, as_Address(src), merge, vector_len);
2628   } else {
2629     lea(scratch_reg, src);
2630     Assembler::evmovdquw(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2631   }
2632 }
2633 
2634 void MacroAssembler::evmovdqul(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2635                                int vector_len, Register scratch_reg) {
2636   if (reachable(src)) {
2637     Assembler::evmovdqul(dst, mask, as_Address(src), merge, vector_len);
2638   } else {
2639     lea(scratch_reg, src);
2640     Assembler::evmovdqul(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2641   }
2642 }
2643 
2644 void MacroAssembler::evmovdquq(XMMRegister dst, KRegister mask, AddressLiteral src, bool merge,
2645                                int vector_len, Register scratch_reg) {
2646   if (reachable(src)) {
2647     Assembler::evmovdquq(dst, mask, as_Address(src), merge, vector_len);
2648   } else {
2649     lea(scratch_reg, src);
2650     Assembler::evmovdquq(dst, mask, Address(scratch_reg, 0), merge, vector_len);
2651   }
2652 }
2653 
2654 void MacroAssembler::evmovdquq(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2655   if (reachable(src)) {
2656     Assembler::evmovdquq(dst, as_Address(src), vector_len);
2657   } else {
2658     lea(rscratch, src);
2659     Assembler::evmovdquq(dst, Address(rscratch, 0), vector_len);
2660   }
2661 }
2662 
2663 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) {
2664   if (reachable(src)) {
2665     Assembler::movdqa(dst, as_Address(src));
2666   } else {
2667     lea(rscratch1, src);
2668     Assembler::movdqa(dst, Address(rscratch1, 0));
2669   }
2670 }
2671 
2672 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) {
2673   if (reachable(src)) {
2674     Assembler::movsd(dst, as_Address(src));
2675   } else {
2676     lea(rscratch1, src);
2677     Assembler::movsd(dst, Address(rscratch1, 0));
2678   }
2679 }
2680 
2681 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) {
2682   if (reachable(src)) {
2683     Assembler::movss(dst, as_Address(src));
2684   } else {
2685     lea(rscratch1, src);
2686     Assembler::movss(dst, Address(rscratch1, 0));
2687   }
2688 }
2689 
2690 void MacroAssembler::vmovddup(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
2691   if (reachable(src)) {
2692     Assembler::vmovddup(dst, as_Address(src), vector_len);
2693   } else {
2694     lea(rscratch, src);
2695     Assembler::vmovddup(dst, Address(rscratch, 0), vector_len);
2696   }
2697 }
2698 
2699 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) {
2700   if (reachable(src)) {
2701     Assembler::mulsd(dst, as_Address(src));
2702   } else {
2703     lea(rscratch1, src);
2704     Assembler::mulsd(dst, Address(rscratch1, 0));
2705   }
2706 }
2707 
2708 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) {
2709   if (reachable(src)) {
2710     Assembler::mulss(dst, as_Address(src));
2711   } else {
2712     lea(rscratch1, src);
2713     Assembler::mulss(dst, Address(rscratch1, 0));
2714   }
2715 }
2716 
2717 void MacroAssembler::null_check(Register reg, int offset) {
2718   if (needs_explicit_null_check(offset)) {
2719     // provoke OS NULL exception if reg = NULL by
2720     // accessing M[reg] w/o changing any (non-CC) registers
2721     // NOTE: cmpl is plenty here to provoke a segv
2722     cmpptr(rax, Address(reg, 0));
2723     // Note: should probably use testl(rax, Address(reg, 0));
2724     //       may be shorter code (however, this version of
2725     //       testl needs to be implemented first)
2726   } else {
2727     // nothing to do, (later) access of M[reg + offset]
2728     // will provoke OS NULL exception if reg = NULL
2729   }
2730 }
2731 
2732 void MacroAssembler::os_breakpoint() {
2733   // instead of directly emitting a breakpoint, call os:breakpoint for better debugability
2734   // (e.g., MSVC can't call ps() otherwise)
2735   call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint)));
2736 }
2737 
2738 void MacroAssembler::unimplemented(const char* what) {
2739   const char* buf = NULL;
2740   {
2741     ResourceMark rm;
2742     stringStream ss;
2743     ss.print("unimplemented: %s", what);
2744     buf = code_string(ss.as_string());
2745   }
2746   stop(buf);
2747 }
2748 
2749 #ifdef _LP64
2750 #define XSTATE_BV 0x200
2751 #endif
2752 
2753 void MacroAssembler::pop_CPU_state() {
2754   pop_FPU_state();
2755   pop_IU_state();
2756 }
2757 
2758 void MacroAssembler::pop_FPU_state() {
2759 #ifndef _LP64
2760   frstor(Address(rsp, 0));
2761 #else
2762   fxrstor(Address(rsp, 0));
2763 #endif
2764   addptr(rsp, FPUStateSizeInWords * wordSize);
2765 }
2766 
2767 void MacroAssembler::pop_IU_state() {
2768   popa();
2769   LP64_ONLY(addq(rsp, 8));
2770   popf();
2771 }
2772 
2773 // Save Integer and Float state
2774 // Warning: Stack must be 16 byte aligned (64bit)
2775 void MacroAssembler::push_CPU_state() {
2776   push_IU_state();
2777   push_FPU_state();
2778 }
2779 
2780 void MacroAssembler::push_FPU_state() {
2781   subptr(rsp, FPUStateSizeInWords * wordSize);
2782 #ifndef _LP64
2783   fnsave(Address(rsp, 0));
2784   fwait();
2785 #else
2786   fxsave(Address(rsp, 0));
2787 #endif // LP64
2788 }
2789 
2790 void MacroAssembler::push_IU_state() {
2791   // Push flags first because pusha kills them
2792   pushf();
2793   // Make sure rsp stays 16-byte aligned
2794   LP64_ONLY(subq(rsp, 8));
2795   pusha();
2796 }
2797 
2798 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp) { // determine java_thread register
2799   if (!java_thread->is_valid()) {
2800     java_thread = rdi;
2801     get_thread(java_thread);
2802   }
2803   // we must set sp to zero to clear frame
2804   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD);
2805   // must clear fp, so that compiled frames are not confused; it is
2806   // possible that we need it only for debugging
2807   if (clear_fp) {
2808     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD);
2809   }
2810   // Always clear the pc because it could have been set by make_walkable()
2811   movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD);
2812   vzeroupper();
2813 }
2814 
2815 void MacroAssembler::restore_rax(Register tmp) {
2816   if (tmp == noreg) pop(rax);
2817   else if (tmp != rax) mov(rax, tmp);
2818 }
2819 
2820 void MacroAssembler::round_to(Register reg, int modulus) {
2821   addptr(reg, modulus - 1);
2822   andptr(reg, -modulus);
2823 }
2824 
2825 void MacroAssembler::save_rax(Register tmp) {
2826   if (tmp == noreg) push(rax);
2827   else if (tmp != rax) mov(tmp, rax);
2828 }
2829 
2830 void MacroAssembler::safepoint_poll(Label& slow_path, Register thread_reg, bool at_return, bool in_nmethod) {
2831   if (at_return) {
2832     // Note that when in_nmethod is set, the stack pointer is incremented before the poll. Therefore,
2833     // we may safely use rsp instead to perform the stack watermark check.
2834     cmpptr(in_nmethod ? rsp : rbp, Address(thread_reg, JavaThread::polling_word_offset()));
2835     jcc(Assembler::above, slow_path);
2836     return;
2837   }
2838   testb(Address(thread_reg, JavaThread::polling_word_offset()), SafepointMechanism::poll_bit());
2839   jcc(Assembler::notZero, slow_path); // handshake bit set implies poll
2840 }
2841 
2842 // Calls to C land
2843 //
2844 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded
2845 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp
2846 // has to be reset to 0. This is required to allow proper stack traversal.
2847 void MacroAssembler::set_last_Java_frame(Register java_thread,
2848                                          Register last_java_sp,
2849                                          Register last_java_fp,
2850                                          address  last_java_pc) {
2851   vzeroupper();
2852   // determine java_thread register
2853   if (!java_thread->is_valid()) {
2854     java_thread = rdi;
2855     get_thread(java_thread);
2856   }
2857   // determine last_java_sp register
2858   if (!last_java_sp->is_valid()) {
2859     last_java_sp = rsp;
2860   }
2861 
2862   // last_java_fp is optional
2863 
2864   if (last_java_fp->is_valid()) {
2865     movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp);
2866   }
2867 
2868   // last_java_pc is optional
2869 
2870   if (last_java_pc != NULL) {
2871     lea(Address(java_thread,
2872                  JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()),
2873         InternalAddress(last_java_pc));
2874 
2875   }
2876   movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp);
2877 }
2878 
2879 void MacroAssembler::shlptr(Register dst, int imm8) {
2880   LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8));
2881 }
2882 
2883 void MacroAssembler::shrptr(Register dst, int imm8) {
2884   LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8));
2885 }
2886 
2887 void MacroAssembler::sign_extend_byte(Register reg) {
2888   if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) {
2889     movsbl(reg, reg); // movsxb
2890   } else {
2891     shll(reg, 24);
2892     sarl(reg, 24);
2893   }
2894 }
2895 
2896 void MacroAssembler::sign_extend_short(Register reg) {
2897   if (LP64_ONLY(true ||) VM_Version::is_P6()) {
2898     movswl(reg, reg); // movsxw
2899   } else {
2900     shll(reg, 16);
2901     sarl(reg, 16);
2902   }
2903 }
2904 
2905 void MacroAssembler::testl(Register dst, AddressLiteral src) {
2906   assert(reachable(src), "Address should be reachable");
2907   testl(dst, as_Address(src));
2908 }
2909 
2910 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
2911   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2912   Assembler::pcmpeqb(dst, src);
2913 }
2914 
2915 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
2916   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2917   Assembler::pcmpeqw(dst, src);
2918 }
2919 
2920 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
2921   assert((dst->encoding() < 16),"XMM register should be 0-15");
2922   Assembler::pcmpestri(dst, src, imm8);
2923 }
2924 
2925 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
2926   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2927   Assembler::pcmpestri(dst, src, imm8);
2928 }
2929 
2930 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
2931   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2932   Assembler::pmovzxbw(dst, src);
2933 }
2934 
2935 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) {
2936   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
2937   Assembler::pmovzxbw(dst, src);
2938 }
2939 
2940 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) {
2941   assert((src->encoding() < 16),"XMM register should be 0-15");
2942   Assembler::pmovmskb(dst, src);
2943 }
2944 
2945 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) {
2946   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
2947   Assembler::ptest(dst, src);
2948 }
2949 
2950 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) {
2951   if (reachable(src)) {
2952     Assembler::sqrtsd(dst, as_Address(src));
2953   } else {
2954     lea(rscratch1, src);
2955     Assembler::sqrtsd(dst, Address(rscratch1, 0));
2956   }
2957 }
2958 
2959 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) {
2960   if (reachable(src)) {
2961     Assembler::sqrtss(dst, as_Address(src));
2962   } else {
2963     lea(rscratch1, src);
2964     Assembler::sqrtss(dst, Address(rscratch1, 0));
2965   }
2966 }
2967 
2968 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) {
2969   if (reachable(src)) {
2970     Assembler::subsd(dst, as_Address(src));
2971   } else {
2972     lea(rscratch1, src);
2973     Assembler::subsd(dst, Address(rscratch1, 0));
2974   }
2975 }
2976 
2977 void MacroAssembler::roundsd(XMMRegister dst, AddressLiteral src, int32_t rmode, Register scratch_reg) {
2978   if (reachable(src)) {
2979     Assembler::roundsd(dst, as_Address(src), rmode);
2980   } else {
2981     lea(scratch_reg, src);
2982     Assembler::roundsd(dst, Address(scratch_reg, 0), rmode);
2983   }
2984 }
2985 
2986 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) {
2987   if (reachable(src)) {
2988     Assembler::subss(dst, as_Address(src));
2989   } else {
2990     lea(rscratch1, src);
2991     Assembler::subss(dst, Address(rscratch1, 0));
2992   }
2993 }
2994 
2995 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) {
2996   if (reachable(src)) {
2997     Assembler::ucomisd(dst, as_Address(src));
2998   } else {
2999     lea(rscratch1, src);
3000     Assembler::ucomisd(dst, Address(rscratch1, 0));
3001   }
3002 }
3003 
3004 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) {
3005   if (reachable(src)) {
3006     Assembler::ucomiss(dst, as_Address(src));
3007   } else {
3008     lea(rscratch1, src);
3009     Assembler::ucomiss(dst, Address(rscratch1, 0));
3010   }
3011 }
3012 
3013 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3014   // Used in sign-bit flipping with aligned address.
3015   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3016   if (reachable(src)) {
3017     Assembler::xorpd(dst, as_Address(src));
3018   } else {
3019     lea(scratch_reg, src);
3020     Assembler::xorpd(dst, Address(scratch_reg, 0));
3021   }
3022 }
3023 
3024 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) {
3025   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3026     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3027   }
3028   else {
3029     Assembler::xorpd(dst, src);
3030   }
3031 }
3032 
3033 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) {
3034   if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) {
3035     Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit);
3036   } else {
3037     Assembler::xorps(dst, src);
3038   }
3039 }
3040 
3041 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src, Register scratch_reg) {
3042   // Used in sign-bit flipping with aligned address.
3043   assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes");
3044   if (reachable(src)) {
3045     Assembler::xorps(dst, as_Address(src));
3046   } else {
3047     lea(scratch_reg, src);
3048     Assembler::xorps(dst, Address(scratch_reg, 0));
3049   }
3050 }
3051 
3052 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) {
3053   // Used in sign-bit flipping with aligned address.
3054   bool aligned_adr = (((intptr_t)src.target() & 15) == 0);
3055   assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes");
3056   if (reachable(src)) {
3057     Assembler::pshufb(dst, as_Address(src));
3058   } else {
3059     lea(rscratch1, src);
3060     Assembler::pshufb(dst, Address(rscratch1, 0));
3061   }
3062 }
3063 
3064 // AVX 3-operands instructions
3065 
3066 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3067   if (reachable(src)) {
3068     vaddsd(dst, nds, as_Address(src));
3069   } else {
3070     lea(rscratch1, src);
3071     vaddsd(dst, nds, Address(rscratch1, 0));
3072   }
3073 }
3074 
3075 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3076   if (reachable(src)) {
3077     vaddss(dst, nds, as_Address(src));
3078   } else {
3079     lea(rscratch1, src);
3080     vaddss(dst, nds, Address(rscratch1, 0));
3081   }
3082 }
3083 
3084 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3085   assert(UseAVX > 0, "requires some form of AVX");
3086   if (reachable(src)) {
3087     Assembler::vpaddb(dst, nds, as_Address(src), vector_len);
3088   } else {
3089     lea(rscratch, src);
3090     Assembler::vpaddb(dst, nds, Address(rscratch, 0), vector_len);
3091   }
3092 }
3093 
3094 void MacroAssembler::vpaddd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register rscratch) {
3095   assert(UseAVX > 0, "requires some form of AVX");
3096   if (reachable(src)) {
3097     Assembler::vpaddd(dst, nds, as_Address(src), vector_len);
3098   } else {
3099     lea(rscratch, src);
3100     Assembler::vpaddd(dst, nds, Address(rscratch, 0), vector_len);
3101   }
3102 }
3103 
3104 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3105   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3106   vandps(dst, nds, negate_field, vector_len);
3107 }
3108 
3109 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) {
3110   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3111   vandpd(dst, nds, negate_field, vector_len);
3112 }
3113 
3114 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3115   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3116   Assembler::vpaddb(dst, nds, src, vector_len);
3117 }
3118 
3119 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3120   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3121   Assembler::vpaddb(dst, nds, src, vector_len);
3122 }
3123 
3124 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3125   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3126   Assembler::vpaddw(dst, nds, src, vector_len);
3127 }
3128 
3129 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3130   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3131   Assembler::vpaddw(dst, nds, src, vector_len);
3132 }
3133 
3134 void MacroAssembler::vpand(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3135   if (reachable(src)) {
3136     Assembler::vpand(dst, nds, as_Address(src), vector_len);
3137   } else {
3138     lea(scratch_reg, src);
3139     Assembler::vpand(dst, nds, Address(scratch_reg, 0), vector_len);
3140   }
3141 }
3142 
3143 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
3144   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3145   Assembler::vpbroadcastw(dst, src, vector_len);
3146 }
3147 
3148 void MacroAssembler::vbroadcastsd(XMMRegister dst, AddressLiteral src, int vector_len, Register rscratch) {
3149   if (reachable(src)) {
3150     Assembler::vbroadcastsd(dst, as_Address(src), vector_len);
3151   } else {
3152     lea(rscratch, src);
3153     Assembler::vbroadcastsd(dst, Address(rscratch, 0), vector_len);
3154   }
3155 }
3156 
3157 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3158   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3159   Assembler::vpcmpeqb(dst, nds, src, vector_len);
3160 }
3161 
3162 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3163   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3164   Assembler::vpcmpeqw(dst, nds, src, vector_len);
3165 }
3166 
3167 void MacroAssembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds,
3168                                AddressLiteral src, int vector_len, Register scratch_reg) {
3169   if (reachable(src)) {
3170     Assembler::evpcmpeqd(kdst, mask, nds, as_Address(src), vector_len);
3171   } else {
3172     lea(scratch_reg, src);
3173     Assembler::evpcmpeqd(kdst, mask, nds, Address(scratch_reg, 0), vector_len);
3174   }
3175 }
3176 
3177 void MacroAssembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3178                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3179   if (reachable(src)) {
3180     Assembler::evpcmpd(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3181   } else {
3182     lea(scratch_reg, src);
3183     Assembler::evpcmpd(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3184   }
3185 }
3186 
3187 void MacroAssembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3188                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3189   if (reachable(src)) {
3190     Assembler::evpcmpq(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3191   } else {
3192     lea(scratch_reg, src);
3193     Assembler::evpcmpq(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3194   }
3195 }
3196 
3197 void MacroAssembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3198                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3199   if (reachable(src)) {
3200     Assembler::evpcmpb(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3201   } else {
3202     lea(scratch_reg, src);
3203     Assembler::evpcmpb(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3204   }
3205 }
3206 
3207 void MacroAssembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, AddressLiteral src,
3208                              int comparison, bool is_signed, int vector_len, Register scratch_reg) {
3209   if (reachable(src)) {
3210     Assembler::evpcmpw(kdst, mask, nds, as_Address(src), comparison, is_signed, vector_len);
3211   } else {
3212     lea(scratch_reg, src);
3213     Assembler::evpcmpw(kdst, mask, nds, Address(scratch_reg, 0), comparison, is_signed, vector_len);
3214   }
3215 }
3216 
3217 void MacroAssembler::vpcmpCC(XMMRegister dst, XMMRegister nds, XMMRegister src, int cond_encoding, Width width, int vector_len) {
3218   if (width == Assembler::Q) {
3219     Assembler::vpcmpCCq(dst, nds, src, cond_encoding, vector_len);
3220   } else {
3221     Assembler::vpcmpCCbwd(dst, nds, src, cond_encoding, vector_len);
3222   }
3223 }
3224 
3225 void MacroAssembler::vpcmpCCW(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister xtmp, ComparisonPredicate cond, Width width, int vector_len) {
3226   int eq_cond_enc = 0x29;
3227   int gt_cond_enc = 0x37;
3228   if (width != Assembler::Q) {
3229     eq_cond_enc = 0x74 + width;
3230     gt_cond_enc = 0x64 + width;
3231   }
3232   switch (cond) {
3233   case eq:
3234     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3235     break;
3236   case neq:
3237     vpcmpCC(dst, nds, src, eq_cond_enc, width, vector_len);
3238     vallones(xtmp, vector_len);
3239     vpxor(dst, xtmp, dst, vector_len);
3240     break;
3241   case le:
3242     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3243     vallones(xtmp, vector_len);
3244     vpxor(dst, xtmp, dst, vector_len);
3245     break;
3246   case nlt:
3247     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3248     vallones(xtmp, vector_len);
3249     vpxor(dst, xtmp, dst, vector_len);
3250     break;
3251   case lt:
3252     vpcmpCC(dst, src, nds, gt_cond_enc, width, vector_len);
3253     break;
3254   case nle:
3255     vpcmpCC(dst, nds, src, gt_cond_enc, width, vector_len);
3256     break;
3257   default:
3258     assert(false, "Should not reach here");
3259   }
3260 }
3261 
3262 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
3263   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3264   Assembler::vpmovzxbw(dst, src, vector_len);
3265 }
3266 
3267 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src, int vector_len) {
3268   assert((src->encoding() < 16),"XMM register should be 0-15");
3269   Assembler::vpmovmskb(dst, src, vector_len);
3270 }
3271 
3272 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3273   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3274   Assembler::vpmullw(dst, nds, src, vector_len);
3275 }
3276 
3277 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3278   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3279   Assembler::vpmullw(dst, nds, src, vector_len);
3280 }
3281 
3282 void MacroAssembler::vpmulld(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3283   assert((UseAVX > 0), "AVX support is needed");
3284   if (reachable(src)) {
3285     Assembler::vpmulld(dst, nds, as_Address(src), vector_len);
3286   } else {
3287     lea(scratch_reg, src);
3288     Assembler::vpmulld(dst, nds, Address(scratch_reg, 0), vector_len);
3289   }
3290 }
3291 
3292 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3293   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3294   Assembler::vpsubb(dst, nds, src, vector_len);
3295 }
3296 
3297 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3298   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3299   Assembler::vpsubb(dst, nds, src, vector_len);
3300 }
3301 
3302 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3303   assert(((dst->encoding() < 16 && src->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3304   Assembler::vpsubw(dst, nds, src, vector_len);
3305 }
3306 
3307 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
3308   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3309   Assembler::vpsubw(dst, nds, src, vector_len);
3310 }
3311 
3312 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3313   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3314   Assembler::vpsraw(dst, nds, shift, vector_len);
3315 }
3316 
3317 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3318   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3319   Assembler::vpsraw(dst, nds, shift, vector_len);
3320 }
3321 
3322 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3323   assert(UseAVX > 2,"");
3324   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3325      vector_len = 2;
3326   }
3327   Assembler::evpsraq(dst, nds, shift, vector_len);
3328 }
3329 
3330 void MacroAssembler::evpsraq(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3331   assert(UseAVX > 2,"");
3332   if (!VM_Version::supports_avx512vl() && vector_len < 2) {
3333      vector_len = 2;
3334   }
3335   Assembler::evpsraq(dst, nds, shift, vector_len);
3336 }
3337 
3338 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3339   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3340   Assembler::vpsrlw(dst, nds, shift, vector_len);
3341 }
3342 
3343 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3344   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3345   Assembler::vpsrlw(dst, nds, shift, vector_len);
3346 }
3347 
3348 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) {
3349   assert(((dst->encoding() < 16 && shift->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3350   Assembler::vpsllw(dst, nds, shift, vector_len);
3351 }
3352 
3353 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) {
3354   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3355   Assembler::vpsllw(dst, nds, shift, vector_len);
3356 }
3357 
3358 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) {
3359   assert((dst->encoding() < 16 && src->encoding() < 16),"XMM register should be 0-15");
3360   Assembler::vptest(dst, src);
3361 }
3362 
3363 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) {
3364   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3365   Assembler::punpcklbw(dst, src);
3366 }
3367 
3368 void MacroAssembler::pshufd(XMMRegister dst, Address src, int mode) {
3369   assert(((dst->encoding() < 16) || VM_Version::supports_avx512vl()),"XMM register should be 0-15");
3370   Assembler::pshufd(dst, src, mode);
3371 }
3372 
3373 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
3374   assert(((dst->encoding() < 16 && src->encoding() < 16) || VM_Version::supports_avx512vlbw()),"XMM register should be 0-15");
3375   Assembler::pshuflw(dst, src, mode);
3376 }
3377 
3378 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3379   if (reachable(src)) {
3380     vandpd(dst, nds, as_Address(src), vector_len);
3381   } else {
3382     lea(scratch_reg, src);
3383     vandpd(dst, nds, Address(scratch_reg, 0), vector_len);
3384   }
3385 }
3386 
3387 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3388   if (reachable(src)) {
3389     vandps(dst, nds, as_Address(src), vector_len);
3390   } else {
3391     lea(scratch_reg, src);
3392     vandps(dst, nds, Address(scratch_reg, 0), vector_len);
3393   }
3394 }
3395 
3396 void MacroAssembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, AddressLiteral src,
3397                             bool merge, int vector_len, Register scratch_reg) {
3398   if (reachable(src)) {
3399     Assembler::evpord(dst, mask, nds, as_Address(src), merge, vector_len);
3400   } else {
3401     lea(scratch_reg, src);
3402     Assembler::evpord(dst, mask, nds, Address(scratch_reg, 0), merge, vector_len);
3403   }
3404 }
3405 
3406 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3407   if (reachable(src)) {
3408     vdivsd(dst, nds, as_Address(src));
3409   } else {
3410     lea(rscratch1, src);
3411     vdivsd(dst, nds, Address(rscratch1, 0));
3412   }
3413 }
3414 
3415 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3416   if (reachable(src)) {
3417     vdivss(dst, nds, as_Address(src));
3418   } else {
3419     lea(rscratch1, src);
3420     vdivss(dst, nds, Address(rscratch1, 0));
3421   }
3422 }
3423 
3424 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3425   if (reachable(src)) {
3426     vmulsd(dst, nds, as_Address(src));
3427   } else {
3428     lea(rscratch1, src);
3429     vmulsd(dst, nds, Address(rscratch1, 0));
3430   }
3431 }
3432 
3433 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3434   if (reachable(src)) {
3435     vmulss(dst, nds, as_Address(src));
3436   } else {
3437     lea(rscratch1, src);
3438     vmulss(dst, nds, Address(rscratch1, 0));
3439   }
3440 }
3441 
3442 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3443   if (reachable(src)) {
3444     vsubsd(dst, nds, as_Address(src));
3445   } else {
3446     lea(rscratch1, src);
3447     vsubsd(dst, nds, Address(rscratch1, 0));
3448   }
3449 }
3450 
3451 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3452   if (reachable(src)) {
3453     vsubss(dst, nds, as_Address(src));
3454   } else {
3455     lea(rscratch1, src);
3456     vsubss(dst, nds, Address(rscratch1, 0));
3457   }
3458 }
3459 
3460 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3461   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3462   vxorps(dst, nds, src, Assembler::AVX_128bit);
3463 }
3464 
3465 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) {
3466   assert(((dst->encoding() < 16 && nds->encoding() < 16) || VM_Version::supports_avx512vldq()),"XMM register should be 0-15");
3467   vxorpd(dst, nds, src, Assembler::AVX_128bit);
3468 }
3469 
3470 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3471   if (reachable(src)) {
3472     vxorpd(dst, nds, as_Address(src), vector_len);
3473   } else {
3474     lea(scratch_reg, src);
3475     vxorpd(dst, nds, Address(scratch_reg, 0), vector_len);
3476   }
3477 }
3478 
3479 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3480   if (reachable(src)) {
3481     vxorps(dst, nds, as_Address(src), vector_len);
3482   } else {
3483     lea(scratch_reg, src);
3484     vxorps(dst, nds, Address(scratch_reg, 0), vector_len);
3485   }
3486 }
3487 
3488 void MacroAssembler::vpxor(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3489   if (UseAVX > 1 || (vector_len < 1)) {
3490     if (reachable(src)) {
3491       Assembler::vpxor(dst, nds, as_Address(src), vector_len);
3492     } else {
3493       lea(scratch_reg, src);
3494       Assembler::vpxor(dst, nds, Address(scratch_reg, 0), vector_len);
3495     }
3496   }
3497   else {
3498     MacroAssembler::vxorpd(dst, nds, src, vector_len, scratch_reg);
3499   }
3500 }
3501 
3502 void MacroAssembler::vpermd(XMMRegister dst,  XMMRegister nds, AddressLiteral src, int vector_len, Register scratch_reg) {
3503   if (reachable(src)) {
3504     Assembler::vpermd(dst, nds, as_Address(src), vector_len);
3505   } else {
3506     lea(scratch_reg, src);
3507     Assembler::vpermd(dst, nds, Address(scratch_reg, 0), vector_len);
3508   }
3509 }
3510 
3511 void MacroAssembler::clear_jweak_tag(Register possibly_jweak) {
3512   const int32_t inverted_jweak_mask = ~static_cast<int32_t>(JNIHandles::weak_tag_mask);
3513   STATIC_ASSERT(inverted_jweak_mask == -2); // otherwise check this code
3514   // The inverted mask is sign-extended
3515   andptr(possibly_jweak, inverted_jweak_mask);
3516 }
3517 
3518 void MacroAssembler::resolve_jobject(Register value,
3519                                      Register thread,
3520                                      Register tmp) {
3521   assert_different_registers(value, thread, tmp);
3522   Label done, not_weak;
3523   testptr(value, value);
3524   jcc(Assembler::zero, done);                // Use NULL as-is.
3525   testptr(value, JNIHandles::weak_tag_mask); // Test for jweak tag.
3526   jcc(Assembler::zero, not_weak);
3527   // Resolve jweak.
3528   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
3529                  value, Address(value, -JNIHandles::weak_tag_value), tmp, thread);
3530   verify_oop(value);
3531   jmp(done);
3532   bind(not_weak);
3533   // Resolve (untagged) jobject.
3534   access_load_at(T_OBJECT, IN_NATIVE, value, Address(value, 0), tmp, thread);
3535   verify_oop(value);
3536   bind(done);
3537 }
3538 
3539 void MacroAssembler::subptr(Register dst, int32_t imm32) {
3540   LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32));
3541 }
3542 
3543 // Force generation of a 4 byte immediate value even if it fits into 8bit
3544 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) {
3545   LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32));
3546 }
3547 
3548 void MacroAssembler::subptr(Register dst, Register src) {
3549   LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src));
3550 }
3551 
3552 // C++ bool manipulation
3553 void MacroAssembler::testbool(Register dst) {
3554   if(sizeof(bool) == 1)
3555     testb(dst, 0xff);
3556   else if(sizeof(bool) == 2) {
3557     // testw implementation needed for two byte bools
3558     ShouldNotReachHere();
3559   } else if(sizeof(bool) == 4)
3560     testl(dst, dst);
3561   else
3562     // unsupported
3563     ShouldNotReachHere();
3564 }
3565 
3566 void MacroAssembler::testptr(Register dst, Register src) {
3567   LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src));
3568 }
3569 
3570 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
3571 void MacroAssembler::tlab_allocate(Register thread, Register obj,
3572                                    Register var_size_in_bytes,
3573                                    int con_size_in_bytes,
3574                                    Register t1,
3575                                    Register t2,
3576                                    Label& slow_case) {
3577   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3578   bs->tlab_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, t2, slow_case);
3579 }
3580 
3581 RegSet MacroAssembler::call_clobbered_gp_registers() {
3582   RegSet regs;
3583 #ifdef _LP64
3584   regs += RegSet::of(rax, rcx, rdx);
3585 #ifndef WINDOWS
3586   regs += RegSet::of(rsi, rdi);
3587 #endif
3588   regs += RegSet::range(r8, r11);
3589 #else
3590   regs += RegSet::of(rax, rcx, rdx);
3591 #endif
3592   return regs;
3593 }
3594 
3595 XMMRegSet MacroAssembler::call_clobbered_xmm_registers() {
3596   int num_xmm_registers = XMMRegisterImpl::available_xmm_registers();
3597 #if defined(WINDOWS) && defined(_LP64)
3598   XMMRegSet result = XMMRegSet::range(xmm0, xmm5);
3599   if (num_xmm_registers > 16) {
3600      result += XMMRegSet::range(xmm16, as_XMMRegister(num_xmm_registers - 1));
3601   }
3602   return result;
3603 #else
3604   return XMMRegSet::range(xmm0, as_XMMRegister(num_xmm_registers - 1));
3605 #endif
3606 }
3607 
3608 static int FPUSaveAreaSize = align_up(108, StackAlignmentInBytes); // 108 bytes needed for FPU state by fsave/frstor
3609 
3610 #ifndef _LP64
3611 static bool use_x87_registers() { return UseSSE < 2; }
3612 #endif
3613 static bool use_xmm_registers() { return UseSSE >= 1; }
3614 
3615 // C1 only ever uses the first double/float of the XMM register.
3616 static int xmm_save_size() { return UseSSE >= 2 ? sizeof(double) : sizeof(float); }
3617 
3618 static void save_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3619   if (UseSSE == 1) {
3620     masm->movflt(Address(rsp, offset), reg);
3621   } else {
3622     masm->movdbl(Address(rsp, offset), reg);
3623   }
3624 }
3625 
3626 static void restore_xmm_register(MacroAssembler* masm, int offset, XMMRegister reg) {
3627   if (UseSSE == 1) {
3628     masm->movflt(reg, Address(rsp, offset));
3629   } else {
3630     masm->movdbl(reg, Address(rsp, offset));
3631   }
3632 }
3633 
3634 int register_section_sizes(RegSet gp_registers, XMMRegSet xmm_registers, bool save_fpu,
3635                            int& gp_area_size, int& fp_area_size, int& xmm_area_size) {
3636 
3637   gp_area_size = align_up(gp_registers.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size,
3638                          StackAlignmentInBytes);
3639 #ifdef _LP64
3640   fp_area_size = 0;
3641 #else
3642   fp_area_size = (save_fpu && use_x87_registers()) ? FPUSaveAreaSize : 0;
3643 #endif
3644   xmm_area_size = (save_fpu && use_xmm_registers()) ? xmm_registers.size() * xmm_save_size() : 0;
3645 
3646   return gp_area_size + fp_area_size + xmm_area_size;
3647 }
3648 
3649 void MacroAssembler::push_call_clobbered_registers_except(RegSet exclude, bool save_fpu) {
3650   block_comment("push_call_clobbered_registers start");
3651   // Regular registers
3652   RegSet gp_registers_to_push = call_clobbered_gp_registers() - exclude;
3653 
3654   int gp_area_size;
3655   int fp_area_size;
3656   int xmm_area_size;
3657   int total_save_size = register_section_sizes(gp_registers_to_push, call_clobbered_xmm_registers(), save_fpu,
3658                                                gp_area_size, fp_area_size, xmm_area_size);
3659   subptr(rsp, total_save_size);
3660 
3661   push_set(gp_registers_to_push, 0);
3662 
3663 #ifndef _LP64
3664   if (save_fpu && use_x87_registers()) {
3665     fnsave(Address(rsp, gp_area_size));
3666     fwait();
3667   }
3668 #endif
3669   if (save_fpu && use_xmm_registers()) {
3670     push_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
3671   }
3672 
3673   block_comment("push_call_clobbered_registers end");
3674 }
3675 
3676 void MacroAssembler::pop_call_clobbered_registers_except(RegSet exclude, bool restore_fpu) {
3677   block_comment("pop_call_clobbered_registers start");
3678 
3679   RegSet gp_registers_to_pop = call_clobbered_gp_registers() - exclude;
3680 
3681   int gp_area_size;
3682   int fp_area_size;
3683   int xmm_area_size;
3684   int total_save_size = register_section_sizes(gp_registers_to_pop, call_clobbered_xmm_registers(), restore_fpu,
3685                                                gp_area_size, fp_area_size, xmm_area_size);
3686 
3687   if (restore_fpu && use_xmm_registers()) {
3688     pop_set(call_clobbered_xmm_registers(), gp_area_size + fp_area_size);
3689   }
3690 #ifndef _LP64
3691   if (restore_fpu && use_x87_registers()) {
3692     frstor(Address(rsp, gp_area_size));
3693   }
3694 #endif
3695 
3696   pop_set(gp_registers_to_pop, 0);
3697 
3698   addptr(rsp, total_save_size);
3699 
3700   vzeroupper();
3701 
3702   block_comment("pop_call_clobbered_registers end");
3703 }
3704 
3705 void MacroAssembler::push_set(XMMRegSet set, int offset) {
3706   assert(is_aligned(set.size() * xmm_save_size(), StackAlignmentInBytes), "must be");
3707   int spill_offset = offset;
3708 
3709   for (RegSetIterator<XMMRegister> it = set.begin(); *it != xnoreg; ++it) {
3710     save_xmm_register(this, spill_offset, *it);
3711     spill_offset += xmm_save_size();
3712   }
3713 }
3714 
3715 void MacroAssembler::pop_set(XMMRegSet set, int offset) {
3716   int restore_size = set.size() * xmm_save_size();
3717   assert(is_aligned(restore_size, StackAlignmentInBytes), "must be");
3718 
3719   int restore_offset = offset + restore_size - xmm_save_size();
3720 
3721   for (ReverseRegSetIterator<XMMRegister> it = set.rbegin(); *it != xnoreg; ++it) {
3722     restore_xmm_register(this, restore_offset, *it);
3723     restore_offset -= xmm_save_size();
3724   }
3725 }
3726 
3727 void MacroAssembler::push_set(RegSet set, int offset) {
3728   int spill_offset;
3729   if (offset == -1) {
3730     int register_push_size = set.size() * RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3731     int aligned_size = align_up(register_push_size, StackAlignmentInBytes);
3732     subptr(rsp, aligned_size);
3733     spill_offset = 0;
3734   } else {
3735     spill_offset = offset;
3736   }
3737 
3738   for (RegSetIterator<Register> it = set.begin(); *it != noreg; ++it) {
3739     movptr(Address(rsp, spill_offset), *it);
3740     spill_offset += RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3741   }
3742 }
3743 
3744 void MacroAssembler::pop_set(RegSet set, int offset) {
3745 
3746   int gp_reg_size = RegisterImpl::max_slots_per_register * VMRegImpl::stack_slot_size;
3747   int restore_size = set.size() * gp_reg_size;
3748   int aligned_size = align_up(restore_size, StackAlignmentInBytes);
3749 
3750   int restore_offset;
3751   if (offset == -1) {
3752     restore_offset = restore_size - gp_reg_size;
3753   } else {
3754     restore_offset = offset + restore_size - gp_reg_size;
3755   }
3756   for (ReverseRegSetIterator<Register> it = set.rbegin(); *it != noreg; ++it) {
3757     movptr(*it, Address(rsp, restore_offset));
3758     restore_offset -= gp_reg_size;
3759   }
3760 
3761   if (offset == -1) {
3762     addptr(rsp, aligned_size);
3763   }
3764 }
3765 
3766 // Defines obj, preserves var_size_in_bytes
3767 void MacroAssembler::eden_allocate(Register thread, Register obj,
3768                                    Register var_size_in_bytes,
3769                                    int con_size_in_bytes,
3770                                    Register t1,
3771                                    Label& slow_case) {
3772   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
3773   bs->eden_allocate(this, thread, obj, var_size_in_bytes, con_size_in_bytes, t1, slow_case);
3774 }
3775 
3776 // Preserves the contents of address, destroys the contents length_in_bytes and temp.
3777 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) {
3778   assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different");
3779   assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord");
3780   Label done;
3781 
3782   testptr(length_in_bytes, length_in_bytes);
3783   jcc(Assembler::zero, done);
3784 
3785   // initialize topmost word, divide index by 2, check if odd and test if zero
3786   // note: for the remaining code to work, index must be a multiple of BytesPerWord
3787 #ifdef ASSERT
3788   {
3789     Label L;
3790     testptr(length_in_bytes, BytesPerWord - 1);
3791     jcc(Assembler::zero, L);
3792     stop("length must be a multiple of BytesPerWord");
3793     bind(L);
3794   }
3795 #endif
3796   Register index = length_in_bytes;
3797   xorptr(temp, temp);    // use _zero reg to clear memory (shorter code)
3798   if (UseIncDec) {
3799     shrptr(index, 3);  // divide by 8/16 and set carry flag if bit 2 was set
3800   } else {
3801     shrptr(index, 2);  // use 2 instructions to avoid partial flag stall
3802     shrptr(index, 1);
3803   }
3804 #ifndef _LP64
3805   // index could have not been a multiple of 8 (i.e., bit 2 was set)
3806   {
3807     Label even;
3808     // note: if index was a multiple of 8, then it cannot
3809     //       be 0 now otherwise it must have been 0 before
3810     //       => if it is even, we don't need to check for 0 again
3811     jcc(Assembler::carryClear, even);
3812     // clear topmost word (no jump would be needed if conditional assignment worked here)
3813     movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp);
3814     // index could be 0 now, must check again
3815     jcc(Assembler::zero, done);
3816     bind(even);
3817   }
3818 #endif // !_LP64
3819   // initialize remaining object fields: index is a multiple of 2 now
3820   {
3821     Label loop;
3822     bind(loop);
3823     movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp);
3824     NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);)
3825     decrement(index);
3826     jcc(Assembler::notZero, loop);
3827   }
3828 
3829   bind(done);
3830 }
3831 
3832 // Look up the method for a megamorphic invokeinterface call.
3833 // The target method is determined by <intf_klass, itable_index>.
3834 // The receiver klass is in recv_klass.
3835 // On success, the result will be in method_result, and execution falls through.
3836 // On failure, execution transfers to the given label.
3837 void MacroAssembler::lookup_interface_method(Register recv_klass,
3838                                              Register intf_klass,
3839                                              RegisterOrConstant itable_index,
3840                                              Register method_result,
3841                                              Register scan_temp,
3842                                              Label& L_no_such_interface,
3843                                              bool return_method) {
3844   assert_different_registers(recv_klass, intf_klass, scan_temp);
3845   assert_different_registers(method_result, intf_klass, scan_temp);
3846   assert(recv_klass != method_result || !return_method,
3847          "recv_klass can be destroyed when method isn't needed");
3848 
3849   assert(itable_index.is_constant() || itable_index.as_register() == method_result,
3850          "caller must use same register for non-constant itable index as for method");
3851 
3852   // Compute start of first itableOffsetEntry (which is at the end of the vtable)
3853   int vtable_base = in_bytes(Klass::vtable_start_offset());
3854   int itentry_off = itableMethodEntry::method_offset_in_bytes();
3855   int scan_step   = itableOffsetEntry::size() * wordSize;
3856   int vte_size    = vtableEntry::size_in_bytes();
3857   Address::ScaleFactor times_vte_scale = Address::times_ptr;
3858   assert(vte_size == wordSize, "else adjust times_vte_scale");
3859 
3860   movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset()));
3861 
3862   // %%% Could store the aligned, prescaled offset in the klassoop.
3863   lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base));
3864 
3865   if (return_method) {
3866     // Adjust recv_klass by scaled itable_index, so we can free itable_index.
3867     assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below");
3868     lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off));
3869   }
3870 
3871   // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) {
3872   //   if (scan->interface() == intf) {
3873   //     result = (klass + scan->offset() + itable_index);
3874   //   }
3875   // }
3876   Label search, found_method;
3877 
3878   for (int peel = 1; peel >= 0; peel--) {
3879     movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes()));
3880     cmpptr(intf_klass, method_result);
3881 
3882     if (peel) {
3883       jccb(Assembler::equal, found_method);
3884     } else {
3885       jccb(Assembler::notEqual, search);
3886       // (invert the test to fall through to found_method...)
3887     }
3888 
3889     if (!peel)  break;
3890 
3891     bind(search);
3892 
3893     // Check that the previous entry is non-null.  A null entry means that
3894     // the receiver class doesn't implement the interface, and wasn't the
3895     // same as when the caller was compiled.
3896     testptr(method_result, method_result);
3897     jcc(Assembler::zero, L_no_such_interface);
3898     addptr(scan_temp, scan_step);
3899   }
3900 
3901   bind(found_method);
3902 
3903   if (return_method) {
3904     // Got a hit.
3905     movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes()));
3906     movptr(method_result, Address(recv_klass, scan_temp, Address::times_1));
3907   }
3908 }
3909 
3910 
3911 // virtual method calling
3912 void MacroAssembler::lookup_virtual_method(Register recv_klass,
3913                                            RegisterOrConstant vtable_index,
3914                                            Register method_result) {
3915   const int base = in_bytes(Klass::vtable_start_offset());
3916   assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below");
3917   Address vtable_entry_addr(recv_klass,
3918                             vtable_index, Address::times_ptr,
3919                             base + vtableEntry::method_offset_in_bytes());
3920   movptr(method_result, vtable_entry_addr);
3921 }
3922 
3923 
3924 void MacroAssembler::check_klass_subtype(Register sub_klass,
3925                            Register super_klass,
3926                            Register temp_reg,
3927                            Label& L_success) {
3928   Label L_failure;
3929   check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg,        &L_success, &L_failure, NULL);
3930   check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL);
3931   bind(L_failure);
3932 }
3933 
3934 
3935 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass,
3936                                                    Register super_klass,
3937                                                    Register temp_reg,
3938                                                    Label* L_success,
3939                                                    Label* L_failure,
3940                                                    Label* L_slow_path,
3941                                         RegisterOrConstant super_check_offset) {
3942   assert_different_registers(sub_klass, super_klass, temp_reg);
3943   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
3944   if (super_check_offset.is_register()) {
3945     assert_different_registers(sub_klass, super_klass,
3946                                super_check_offset.as_register());
3947   } else if (must_load_sco) {
3948     assert(temp_reg != noreg, "supply either a temp or a register offset");
3949   }
3950 
3951   Label L_fallthrough;
3952   int label_nulls = 0;
3953   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
3954   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
3955   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
3956   assert(label_nulls <= 1, "at most one NULL in the batch");
3957 
3958   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3959   int sco_offset = in_bytes(Klass::super_check_offset_offset());
3960   Address super_check_offset_addr(super_klass, sco_offset);
3961 
3962   // Hacked jcc, which "knows" that L_fallthrough, at least, is in
3963   // range of a jccb.  If this routine grows larger, reconsider at
3964   // least some of these.
3965 #define local_jcc(assembler_cond, label)                                \
3966   if (&(label) == &L_fallthrough)  jccb(assembler_cond, label);         \
3967   else                             jcc( assembler_cond, label) /*omit semi*/
3968 
3969   // Hacked jmp, which may only be used just before L_fallthrough.
3970 #define final_jmp(label)                                                \
3971   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3972   else                            jmp(label)                /*omit semi*/
3973 
3974   // If the pointers are equal, we are done (e.g., String[] elements).
3975   // This self-check enables sharing of secondary supertype arrays among
3976   // non-primary types such as array-of-interface.  Otherwise, each such
3977   // type would need its own customized SSA.
3978   // We move this check to the front of the fast path because many
3979   // type checks are in fact trivially successful in this manner,
3980   // so we get a nicely predicted branch right at the start of the check.
3981   cmpptr(sub_klass, super_klass);
3982   local_jcc(Assembler::equal, *L_success);
3983 
3984   // Check the supertype display:
3985   if (must_load_sco) {
3986     // Positive movl does right thing on LP64.
3987     movl(temp_reg, super_check_offset_addr);
3988     super_check_offset = RegisterOrConstant(temp_reg);
3989   }
3990   Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0);
3991   cmpptr(super_klass, super_check_addr); // load displayed supertype
3992 
3993   // This check has worked decisively for primary supers.
3994   // Secondary supers are sought in the super_cache ('super_cache_addr').
3995   // (Secondary supers are interfaces and very deeply nested subtypes.)
3996   // This works in the same check above because of a tricky aliasing
3997   // between the super_cache and the primary super display elements.
3998   // (The 'super_check_addr' can address either, as the case requires.)
3999   // Note that the cache is updated below if it does not help us find
4000   // what we need immediately.
4001   // So if it was a primary super, we can just fail immediately.
4002   // Otherwise, it's the slow path for us (no success at this point).
4003 
4004   if (super_check_offset.is_register()) {
4005     local_jcc(Assembler::equal, *L_success);
4006     cmpl(super_check_offset.as_register(), sc_offset);
4007     if (L_failure == &L_fallthrough) {
4008       local_jcc(Assembler::equal, *L_slow_path);
4009     } else {
4010       local_jcc(Assembler::notEqual, *L_failure);
4011       final_jmp(*L_slow_path);
4012     }
4013   } else if (super_check_offset.as_constant() == sc_offset) {
4014     // Need a slow path; fast failure is impossible.
4015     if (L_slow_path == &L_fallthrough) {
4016       local_jcc(Assembler::equal, *L_success);
4017     } else {
4018       local_jcc(Assembler::notEqual, *L_slow_path);
4019       final_jmp(*L_success);
4020     }
4021   } else {
4022     // No slow path; it's a fast decision.
4023     if (L_failure == &L_fallthrough) {
4024       local_jcc(Assembler::equal, *L_success);
4025     } else {
4026       local_jcc(Assembler::notEqual, *L_failure);
4027       final_jmp(*L_success);
4028     }
4029   }
4030 
4031   bind(L_fallthrough);
4032 
4033 #undef local_jcc
4034 #undef final_jmp
4035 }
4036 
4037 
4038 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass,
4039                                                    Register super_klass,
4040                                                    Register temp_reg,
4041                                                    Register temp2_reg,
4042                                                    Label* L_success,
4043                                                    Label* L_failure,
4044                                                    bool set_cond_codes) {
4045   assert_different_registers(sub_klass, super_klass, temp_reg);
4046   if (temp2_reg != noreg)
4047     assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg);
4048 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg)
4049 
4050   Label L_fallthrough;
4051   int label_nulls = 0;
4052   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
4053   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
4054   assert(label_nulls <= 1, "at most one NULL in the batch");
4055 
4056   // a couple of useful fields in sub_klass:
4057   int ss_offset = in_bytes(Klass::secondary_supers_offset());
4058   int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
4059   Address secondary_supers_addr(sub_klass, ss_offset);
4060   Address super_cache_addr(     sub_klass, sc_offset);
4061 
4062   // Do a linear scan of the secondary super-klass chain.
4063   // This code is rarely used, so simplicity is a virtue here.
4064   // The repne_scan instruction uses fixed registers, which we must spill.
4065   // Don't worry too much about pre-existing connections with the input regs.
4066 
4067   assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super)
4068   assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter)
4069 
4070   // Get super_klass value into rax (even if it was in rdi or rcx).
4071   bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false;
4072   if (super_klass != rax || UseCompressedOops) {
4073     if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; }
4074     mov(rax, super_klass);
4075   }
4076   if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; }
4077   if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; }
4078 
4079 #ifndef PRODUCT
4080   int* pst_counter = &SharedRuntime::_partial_subtype_ctr;
4081   ExternalAddress pst_counter_addr((address) pst_counter);
4082   NOT_LP64(  incrementl(pst_counter_addr) );
4083   LP64_ONLY( lea(rcx, pst_counter_addr) );
4084   LP64_ONLY( incrementl(Address(rcx, 0)) );
4085 #endif //PRODUCT
4086 
4087   // We will consult the secondary-super array.
4088   movptr(rdi, secondary_supers_addr);
4089   // Load the array length.  (Positive movl does right thing on LP64.)
4090   movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes()));
4091   // Skip to start of data.
4092   addptr(rdi, Array<Klass*>::base_offset_in_bytes());
4093 
4094   // Scan RCX words at [RDI] for an occurrence of RAX.
4095   // Set NZ/Z based on last compare.
4096   // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does
4097   // not change flags (only scas instruction which is repeated sets flags).
4098   // Set Z = 0 (not equal) before 'repne' to indicate that class was not found.
4099 
4100     testptr(rax,rax); // Set Z = 0
4101     repne_scan();
4102 
4103   // Unspill the temp. registers:
4104   if (pushed_rdi)  pop(rdi);
4105   if (pushed_rcx)  pop(rcx);
4106   if (pushed_rax)  pop(rax);
4107 
4108   if (set_cond_codes) {
4109     // Special hack for the AD files:  rdi is guaranteed non-zero.
4110     assert(!pushed_rdi, "rdi must be left non-NULL");
4111     // Also, the condition codes are properly set Z/NZ on succeed/failure.
4112   }
4113 
4114   if (L_failure == &L_fallthrough)
4115         jccb(Assembler::notEqual, *L_failure);
4116   else  jcc(Assembler::notEqual, *L_failure);
4117 
4118   // Success.  Cache the super we found and proceed in triumph.
4119   movptr(super_cache_addr, super_klass);
4120 
4121   if (L_success != &L_fallthrough) {
4122     jmp(*L_success);
4123   }
4124 
4125 #undef IS_A_TEMP
4126 
4127   bind(L_fallthrough);
4128 }
4129 
4130 void MacroAssembler::clinit_barrier(Register klass, Register thread, Label* L_fast_path, Label* L_slow_path) {
4131   assert(L_fast_path != NULL || L_slow_path != NULL, "at least one is required");
4132 
4133   Label L_fallthrough;
4134   if (L_fast_path == NULL) {
4135     L_fast_path = &L_fallthrough;
4136   } else if (L_slow_path == NULL) {
4137     L_slow_path = &L_fallthrough;
4138   }
4139 
4140   // Fast path check: class is fully initialized
4141   cmpb(Address(klass, InstanceKlass::init_state_offset()), InstanceKlass::fully_initialized);
4142   jcc(Assembler::equal, *L_fast_path);
4143 
4144   // Fast path check: current thread is initializer thread
4145   cmpptr(thread, Address(klass, InstanceKlass::init_thread_offset()));
4146   if (L_slow_path == &L_fallthrough) {
4147     jcc(Assembler::equal, *L_fast_path);
4148     bind(*L_slow_path);
4149   } else if (L_fast_path == &L_fallthrough) {
4150     jcc(Assembler::notEqual, *L_slow_path);
4151     bind(*L_fast_path);
4152   } else {
4153     Unimplemented();
4154   }
4155 }
4156 
4157 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) {
4158   if (VM_Version::supports_cmov()) {
4159     cmovl(cc, dst, src);
4160   } else {
4161     Label L;
4162     jccb(negate_condition(cc), L);
4163     movl(dst, src);
4164     bind(L);
4165   }
4166 }
4167 
4168 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) {
4169   if (VM_Version::supports_cmov()) {
4170     cmovl(cc, dst, src);
4171   } else {
4172     Label L;
4173     jccb(negate_condition(cc), L);
4174     movl(dst, src);
4175     bind(L);
4176   }
4177 }
4178 
4179 void MacroAssembler::_verify_oop(Register reg, const char* s, const char* file, int line) {
4180   if (!VerifyOops) return;
4181 
4182   // Pass register number to verify_oop_subroutine
4183   const char* b = NULL;
4184   {
4185     ResourceMark rm;
4186     stringStream ss;
4187     ss.print("verify_oop: %s: %s (%s:%d)", reg->name(), s, file, line);
4188     b = code_string(ss.as_string());
4189   }
4190   BLOCK_COMMENT("verify_oop {");
4191 #ifdef _LP64
4192   push(rscratch1);                    // save r10, trashed by movptr()
4193 #endif
4194   push(rax);                          // save rax,
4195   push(reg);                          // pass register argument
4196   ExternalAddress buffer((address) b);
4197   // avoid using pushptr, as it modifies scratch registers
4198   // and our contract is not to modify anything
4199   movptr(rax, buffer.addr());
4200   push(rax);
4201   // call indirectly to solve generation ordering problem
4202   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4203   call(rax);
4204   // Caller pops the arguments (oop, message) and restores rax, r10
4205   BLOCK_COMMENT("} verify_oop");
4206 }
4207 
4208 void MacroAssembler::vallones(XMMRegister dst, int vector_len) {
4209   if (UseAVX > 2 && (vector_len == Assembler::AVX_512bit || VM_Version::supports_avx512vl())) {
4210     vpternlogd(dst, 0xFF, dst, dst, vector_len);
4211   } else {
4212     assert(UseAVX > 0, "");
4213     vpcmpeqb(dst, dst, dst, vector_len);
4214   }
4215 }
4216 
4217 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
4218                                          int extra_slot_offset) {
4219   // cf. TemplateTable::prepare_invoke(), if (load_receiver).
4220   int stackElementSize = Interpreter::stackElementSize;
4221   int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0);
4222 #ifdef ASSERT
4223   int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1);
4224   assert(offset1 - offset == stackElementSize, "correct arithmetic");
4225 #endif
4226   Register             scale_reg    = noreg;
4227   Address::ScaleFactor scale_factor = Address::no_scale;
4228   if (arg_slot.is_constant()) {
4229     offset += arg_slot.as_constant() * stackElementSize;
4230   } else {
4231     scale_reg    = arg_slot.as_register();
4232     scale_factor = Address::times(stackElementSize);
4233   }
4234   offset += wordSize;           // return PC is on stack
4235   return Address(rsp, scale_reg, scale_factor, offset);
4236 }
4237 
4238 void MacroAssembler::_verify_oop_addr(Address addr, const char* s, const char* file, int line) {
4239   if (!VerifyOops) return;
4240 
4241   // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord);
4242   // Pass register number to verify_oop_subroutine
4243   const char* b = NULL;
4244   {
4245     ResourceMark rm;
4246     stringStream ss;
4247     ss.print("verify_oop_addr: %s (%s:%d)", s, file, line);
4248     b = code_string(ss.as_string());
4249   }
4250 #ifdef _LP64
4251   push(rscratch1);                    // save r10, trashed by movptr()
4252 #endif
4253   push(rax);                          // save rax,
4254   // addr may contain rsp so we will have to adjust it based on the push
4255   // we just did (and on 64 bit we do two pushes)
4256   // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which
4257   // stores rax into addr which is backwards of what was intended.
4258   if (addr.uses(rsp)) {
4259     lea(rax, addr);
4260     pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord));
4261   } else {
4262     pushptr(addr);
4263   }
4264 
4265   ExternalAddress buffer((address) b);
4266   // pass msg argument
4267   // avoid using pushptr, as it modifies scratch registers
4268   // and our contract is not to modify anything
4269   movptr(rax, buffer.addr());
4270   push(rax);
4271 
4272   // call indirectly to solve generation ordering problem
4273   movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address()));
4274   call(rax);
4275   // Caller pops the arguments (addr, message) and restores rax, r10.
4276 }
4277 
4278 void MacroAssembler::verify_tlab() {
4279 #ifdef ASSERT
4280   if (UseTLAB && VerifyOops) {
4281     Label next, ok;
4282     Register t1 = rsi;
4283     Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread);
4284 
4285     push(t1);
4286     NOT_LP64(push(thread_reg));
4287     NOT_LP64(get_thread(thread_reg));
4288 
4289     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4290     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())));
4291     jcc(Assembler::aboveEqual, next);
4292     STOP("assert(top >= start)");
4293     should_not_reach_here();
4294 
4295     bind(next);
4296     movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())));
4297     cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())));
4298     jcc(Assembler::aboveEqual, ok);
4299     STOP("assert(top <= end)");
4300     should_not_reach_here();
4301 
4302     bind(ok);
4303     NOT_LP64(pop(thread_reg));
4304     pop(t1);
4305   }
4306 #endif
4307 }
4308 
4309 class ControlWord {
4310  public:
4311   int32_t _value;
4312 
4313   int  rounding_control() const        { return  (_value >> 10) & 3      ; }
4314   int  precision_control() const       { return  (_value >>  8) & 3      ; }
4315   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4316   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4317   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4318   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4319   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4320   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4321 
4322   void print() const {
4323     // rounding control
4324     const char* rc;
4325     switch (rounding_control()) {
4326       case 0: rc = "round near"; break;
4327       case 1: rc = "round down"; break;
4328       case 2: rc = "round up  "; break;
4329       case 3: rc = "chop      "; break;
4330       default:
4331         rc = NULL; // silence compiler warnings
4332         fatal("Unknown rounding control: %d", rounding_control());
4333     };
4334     // precision control
4335     const char* pc;
4336     switch (precision_control()) {
4337       case 0: pc = "24 bits "; break;
4338       case 1: pc = "reserved"; break;
4339       case 2: pc = "53 bits "; break;
4340       case 3: pc = "64 bits "; break;
4341       default:
4342         pc = NULL; // silence compiler warnings
4343         fatal("Unknown precision control: %d", precision_control());
4344     };
4345     // flags
4346     char f[9];
4347     f[0] = ' ';
4348     f[1] = ' ';
4349     f[2] = (precision   ()) ? 'P' : 'p';
4350     f[3] = (underflow   ()) ? 'U' : 'u';
4351     f[4] = (overflow    ()) ? 'O' : 'o';
4352     f[5] = (zero_divide ()) ? 'Z' : 'z';
4353     f[6] = (denormalized()) ? 'D' : 'd';
4354     f[7] = (invalid     ()) ? 'I' : 'i';
4355     f[8] = '\x0';
4356     // output
4357     printf("%04x  masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc);
4358   }
4359 
4360 };
4361 
4362 class StatusWord {
4363  public:
4364   int32_t _value;
4365 
4366   bool busy() const                    { return ((_value >> 15) & 1) != 0; }
4367   bool C3() const                      { return ((_value >> 14) & 1) != 0; }
4368   bool C2() const                      { return ((_value >> 10) & 1) != 0; }
4369   bool C1() const                      { return ((_value >>  9) & 1) != 0; }
4370   bool C0() const                      { return ((_value >>  8) & 1) != 0; }
4371   int  top() const                     { return  (_value >> 11) & 7      ; }
4372   bool error_status() const            { return ((_value >>  7) & 1) != 0; }
4373   bool stack_fault() const             { return ((_value >>  6) & 1) != 0; }
4374   bool precision() const               { return ((_value >>  5) & 1) != 0; }
4375   bool underflow() const               { return ((_value >>  4) & 1) != 0; }
4376   bool overflow() const                { return ((_value >>  3) & 1) != 0; }
4377   bool zero_divide() const             { return ((_value >>  2) & 1) != 0; }
4378   bool denormalized() const            { return ((_value >>  1) & 1) != 0; }
4379   bool invalid() const                 { return ((_value >>  0) & 1) != 0; }
4380 
4381   void print() const {
4382     // condition codes
4383     char c[5];
4384     c[0] = (C3()) ? '3' : '-';
4385     c[1] = (C2()) ? '2' : '-';
4386     c[2] = (C1()) ? '1' : '-';
4387     c[3] = (C0()) ? '0' : '-';
4388     c[4] = '\x0';
4389     // flags
4390     char f[9];
4391     f[0] = (error_status()) ? 'E' : '-';
4392     f[1] = (stack_fault ()) ? 'S' : '-';
4393     f[2] = (precision   ()) ? 'P' : '-';
4394     f[3] = (underflow   ()) ? 'U' : '-';
4395     f[4] = (overflow    ()) ? 'O' : '-';
4396     f[5] = (zero_divide ()) ? 'Z' : '-';
4397     f[6] = (denormalized()) ? 'D' : '-';
4398     f[7] = (invalid     ()) ? 'I' : '-';
4399     f[8] = '\x0';
4400     // output
4401     printf("%04x  flags = %s, cc =  %s, top = %d", _value & 0xFFFF, f, c, top());
4402   }
4403 
4404 };
4405 
4406 class TagWord {
4407  public:
4408   int32_t _value;
4409 
4410   int tag_at(int i) const              { return (_value >> (i*2)) & 3; }
4411 
4412   void print() const {
4413     printf("%04x", _value & 0xFFFF);
4414   }
4415 
4416 };
4417 
4418 class FPU_Register {
4419  public:
4420   int32_t _m0;
4421   int32_t _m1;
4422   int16_t _ex;
4423 
4424   bool is_indefinite() const           {
4425     return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0;
4426   }
4427 
4428   void print() const {
4429     char  sign = (_ex < 0) ? '-' : '+';
4430     const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : "   ";
4431     printf("%c%04hx.%08x%08x  %s", sign, _ex, _m1, _m0, kind);
4432   };
4433 
4434 };
4435 
4436 class FPU_State {
4437  public:
4438   enum {
4439     register_size       = 10,
4440     number_of_registers =  8,
4441     register_mask       =  7
4442   };
4443 
4444   ControlWord  _control_word;
4445   StatusWord   _status_word;
4446   TagWord      _tag_word;
4447   int32_t      _error_offset;
4448   int32_t      _error_selector;
4449   int32_t      _data_offset;
4450   int32_t      _data_selector;
4451   int8_t       _register[register_size * number_of_registers];
4452 
4453   int tag_for_st(int i) const          { return _tag_word.tag_at((_status_word.top() + i) & register_mask); }
4454   FPU_Register* st(int i) const        { return (FPU_Register*)&_register[register_size * i]; }
4455 
4456   const char* tag_as_string(int tag) const {
4457     switch (tag) {
4458       case 0: return "valid";
4459       case 1: return "zero";
4460       case 2: return "special";
4461       case 3: return "empty";
4462     }
4463     ShouldNotReachHere();
4464     return NULL;
4465   }
4466 
4467   void print() const {
4468     // print computation registers
4469     { int t = _status_word.top();
4470       for (int i = 0; i < number_of_registers; i++) {
4471         int j = (i - t) & register_mask;
4472         printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j);
4473         st(j)->print();
4474         printf(" %s\n", tag_as_string(_tag_word.tag_at(i)));
4475       }
4476     }
4477     printf("\n");
4478     // print control registers
4479     printf("ctrl = "); _control_word.print(); printf("\n");
4480     printf("stat = "); _status_word .print(); printf("\n");
4481     printf("tags = "); _tag_word    .print(); printf("\n");
4482   }
4483 
4484 };
4485 
4486 class Flag_Register {
4487  public:
4488   int32_t _value;
4489 
4490   bool overflow() const                { return ((_value >> 11) & 1) != 0; }
4491   bool direction() const               { return ((_value >> 10) & 1) != 0; }
4492   bool sign() const                    { return ((_value >>  7) & 1) != 0; }
4493   bool zero() const                    { return ((_value >>  6) & 1) != 0; }
4494   bool auxiliary_carry() const         { return ((_value >>  4) & 1) != 0; }
4495   bool parity() const                  { return ((_value >>  2) & 1) != 0; }
4496   bool carry() const                   { return ((_value >>  0) & 1) != 0; }
4497 
4498   void print() const {
4499     // flags
4500     char f[8];
4501     f[0] = (overflow       ()) ? 'O' : '-';
4502     f[1] = (direction      ()) ? 'D' : '-';
4503     f[2] = (sign           ()) ? 'S' : '-';
4504     f[3] = (zero           ()) ? 'Z' : '-';
4505     f[4] = (auxiliary_carry()) ? 'A' : '-';
4506     f[5] = (parity         ()) ? 'P' : '-';
4507     f[6] = (carry          ()) ? 'C' : '-';
4508     f[7] = '\x0';
4509     // output
4510     printf("%08x  flags = %s", _value, f);
4511   }
4512 
4513 };
4514 
4515 class IU_Register {
4516  public:
4517   int32_t _value;
4518 
4519   void print() const {
4520     printf("%08x  %11d", _value, _value);
4521   }
4522 
4523 };
4524 
4525 class IU_State {
4526  public:
4527   Flag_Register _eflags;
4528   IU_Register   _rdi;
4529   IU_Register   _rsi;
4530   IU_Register   _rbp;
4531   IU_Register   _rsp;
4532   IU_Register   _rbx;
4533   IU_Register   _rdx;
4534   IU_Register   _rcx;
4535   IU_Register   _rax;
4536 
4537   void print() const {
4538     // computation registers
4539     printf("rax,  = "); _rax.print(); printf("\n");
4540     printf("rbx,  = "); _rbx.print(); printf("\n");
4541     printf("rcx  = "); _rcx.print(); printf("\n");
4542     printf("rdx  = "); _rdx.print(); printf("\n");
4543     printf("rdi  = "); _rdi.print(); printf("\n");
4544     printf("rsi  = "); _rsi.print(); printf("\n");
4545     printf("rbp,  = "); _rbp.print(); printf("\n");
4546     printf("rsp  = "); _rsp.print(); printf("\n");
4547     printf("\n");
4548     // control registers
4549     printf("flgs = "); _eflags.print(); printf("\n");
4550   }
4551 };
4552 
4553 
4554 class CPU_State {
4555  public:
4556   FPU_State _fpu_state;
4557   IU_State  _iu_state;
4558 
4559   void print() const {
4560     printf("--------------------------------------------------\n");
4561     _iu_state .print();
4562     printf("\n");
4563     _fpu_state.print();
4564     printf("--------------------------------------------------\n");
4565   }
4566 
4567 };
4568 
4569 
4570 static void _print_CPU_state(CPU_State* state) {
4571   state->print();
4572 };
4573 
4574 
4575 void MacroAssembler::print_CPU_state() {
4576   push_CPU_state();
4577   push(rsp);                // pass CPU state
4578   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state)));
4579   addptr(rsp, wordSize);       // discard argument
4580   pop_CPU_state();
4581 }
4582 
4583 
4584 #ifndef _LP64
4585 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) {
4586   static int counter = 0;
4587   FPU_State* fs = &state->_fpu_state;
4588   counter++;
4589   // For leaf calls, only verify that the top few elements remain empty.
4590   // We only need 1 empty at the top for C2 code.
4591   if( stack_depth < 0 ) {
4592     if( fs->tag_for_st(7) != 3 ) {
4593       printf("FPR7 not empty\n");
4594       state->print();
4595       assert(false, "error");
4596       return false;
4597     }
4598     return true;                // All other stack states do not matter
4599   }
4600 
4601   assert((fs->_control_word._value & 0xffff) == StubRoutines::x86::fpu_cntrl_wrd_std(),
4602          "bad FPU control word");
4603 
4604   // compute stack depth
4605   int i = 0;
4606   while (i < FPU_State::number_of_registers && fs->tag_for_st(i)  < 3) i++;
4607   int d = i;
4608   while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++;
4609   // verify findings
4610   if (i != FPU_State::number_of_registers) {
4611     // stack not contiguous
4612     printf("%s: stack not contiguous at ST%d\n", s, i);
4613     state->print();
4614     assert(false, "error");
4615     return false;
4616   }
4617   // check if computed stack depth corresponds to expected stack depth
4618   if (stack_depth < 0) {
4619     // expected stack depth is -stack_depth or less
4620     if (d > -stack_depth) {
4621       // too many elements on the stack
4622       printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d);
4623       state->print();
4624       assert(false, "error");
4625       return false;
4626     }
4627   } else {
4628     // expected stack depth is stack_depth
4629     if (d != stack_depth) {
4630       // wrong stack depth
4631       printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d);
4632       state->print();
4633       assert(false, "error");
4634       return false;
4635     }
4636   }
4637   // everything is cool
4638   return true;
4639 }
4640 
4641 void MacroAssembler::verify_FPU(int stack_depth, const char* s) {
4642   if (!VerifyFPU) return;
4643   push_CPU_state();
4644   push(rsp);                // pass CPU state
4645   ExternalAddress msg((address) s);
4646   // pass message string s
4647   pushptr(msg.addr());
4648   push(stack_depth);        // pass stack depth
4649   call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU)));
4650   addptr(rsp, 3 * wordSize);   // discard arguments
4651   // check for error
4652   { Label L;
4653     testl(rax, rax);
4654     jcc(Assembler::notZero, L);
4655     int3();                  // break if error condition
4656     bind(L);
4657   }
4658   pop_CPU_state();
4659 }
4660 #endif // _LP64
4661 
4662 void MacroAssembler::restore_cpu_control_state_after_jni() {
4663   // Either restore the MXCSR register after returning from the JNI Call
4664   // or verify that it wasn't changed (with -Xcheck:jni flag).
4665   if (VM_Version::supports_sse()) {
4666     if (RestoreMXCSROnJNICalls) {
4667       ldmxcsr(ExternalAddress(StubRoutines::x86::addr_mxcsr_std()));
4668     } else if (CheckJNICalls) {
4669       call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry()));
4670     }
4671   }
4672   // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty.
4673   vzeroupper();
4674 
4675 #ifndef _LP64
4676   // Either restore the x87 floating pointer control word after returning
4677   // from the JNI call or verify that it wasn't changed.
4678   if (CheckJNICalls) {
4679     call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry()));
4680   }
4681 #endif // _LP64
4682 }
4683 
4684 // ((OopHandle)result).resolve();
4685 void MacroAssembler::resolve_oop_handle(Register result, Register tmp) {
4686   assert_different_registers(result, tmp);
4687 
4688   // Only 64 bit platforms support GCs that require a tmp register
4689   // Only IN_HEAP loads require a thread_tmp register
4690   // OopHandle::resolve is an indirection like jobject.
4691   access_load_at(T_OBJECT, IN_NATIVE,
4692                  result, Address(result, 0), tmp, /*tmp_thread*/noreg);
4693 }
4694 
4695 // ((WeakHandle)result).resolve();
4696 void MacroAssembler::resolve_weak_handle(Register rresult, Register rtmp) {
4697   assert_different_registers(rresult, rtmp);
4698   Label resolved;
4699 
4700   // A null weak handle resolves to null.
4701   cmpptr(rresult, 0);
4702   jcc(Assembler::equal, resolved);
4703 
4704   // Only 64 bit platforms support GCs that require a tmp register
4705   // Only IN_HEAP loads require a thread_tmp register
4706   // WeakHandle::resolve is an indirection like jweak.
4707   access_load_at(T_OBJECT, IN_NATIVE | ON_PHANTOM_OOP_REF,
4708                  rresult, Address(rresult, 0), rtmp, /*tmp_thread*/noreg);
4709   bind(resolved);
4710 }
4711 
4712 void MacroAssembler::load_mirror(Register mirror, Register method, Register tmp) {
4713   // get mirror
4714   const int mirror_offset = in_bytes(Klass::java_mirror_offset());
4715   load_method_holder(mirror, method);
4716   movptr(mirror, Address(mirror, mirror_offset));
4717   resolve_oop_handle(mirror, tmp);
4718 }
4719 
4720 void MacroAssembler::load_method_holder_cld(Register rresult, Register rmethod) {
4721   load_method_holder(rresult, rmethod);
4722   movptr(rresult, Address(rresult, InstanceKlass::class_loader_data_offset()));
4723 }
4724 
4725 void MacroAssembler::load_method_holder(Register holder, Register method) {
4726   movptr(holder, Address(method, Method::const_offset()));                      // ConstMethod*
4727   movptr(holder, Address(holder, ConstMethod::constants_offset()));             // ConstantPool*
4728   movptr(holder, Address(holder, ConstantPool::pool_holder_offset_in_bytes())); // InstanceKlass*
4729 }
4730 
4731 void MacroAssembler::load_klass(Register dst, Register src, Register tmp) {
4732   assert_different_registers(src, tmp);
4733   assert_different_registers(dst, tmp);
4734 #ifdef _LP64
4735   if (UseCompressedClassPointers) {
4736     movl(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4737     decode_klass_not_null(dst, tmp);
4738   } else
4739 #endif
4740     movptr(dst, Address(src, oopDesc::klass_offset_in_bytes()));
4741 }
4742 
4743 void MacroAssembler::store_klass(Register dst, Register src, Register tmp) {
4744   assert_different_registers(src, tmp);
4745   assert_different_registers(dst, tmp);
4746 #ifdef _LP64
4747   if (UseCompressedClassPointers) {
4748     encode_klass_not_null(src, tmp);
4749     movl(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4750   } else
4751 #endif
4752     movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src);
4753 }
4754 
4755 void MacroAssembler::access_load_at(BasicType type, DecoratorSet decorators, Register dst, Address src,
4756                                     Register tmp1, Register thread_tmp) {
4757   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4758   decorators = AccessInternal::decorator_fixup(decorators);
4759   bool as_raw = (decorators & AS_RAW) != 0;
4760   if (as_raw) {
4761     bs->BarrierSetAssembler::load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4762   } else {
4763     bs->load_at(this, decorators, type, dst, src, tmp1, thread_tmp);
4764   }
4765 }
4766 
4767 void MacroAssembler::access_store_at(BasicType type, DecoratorSet decorators, Address dst, Register src,
4768                                      Register tmp1, Register tmp2, Register tmp3) {
4769   BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
4770   decorators = AccessInternal::decorator_fixup(decorators);
4771   bool as_raw = (decorators & AS_RAW) != 0;
4772   if (as_raw) {
4773     bs->BarrierSetAssembler::store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4774   } else {
4775     bs->store_at(this, decorators, type, dst, src, tmp1, tmp2, tmp3);
4776   }
4777 }
4778 
4779 void MacroAssembler::load_heap_oop(Register dst, Address src, Register tmp1,
4780                                    Register thread_tmp, DecoratorSet decorators) {
4781   access_load_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, thread_tmp);
4782 }
4783 
4784 // Doesn't do verification, generates fixed size code
4785 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src, Register tmp1,
4786                                             Register thread_tmp, DecoratorSet decorators) {
4787   access_load_at(T_OBJECT, IN_HEAP | IS_NOT_NULL | decorators, dst, src, tmp1, thread_tmp);
4788 }
4789 
4790 void MacroAssembler::store_heap_oop(Address dst, Register src, Register tmp1,
4791                                     Register tmp2, Register tmp3, DecoratorSet decorators) {
4792   access_store_at(T_OBJECT, IN_HEAP | decorators, dst, src, tmp1, tmp2, tmp3);
4793 }
4794 
4795 // Used for storing NULLs.
4796 void MacroAssembler::store_heap_oop_null(Address dst) {
4797   access_store_at(T_OBJECT, IN_HEAP, dst, noreg, noreg, noreg, noreg);
4798 }
4799 
4800 #ifdef _LP64
4801 void MacroAssembler::store_klass_gap(Register dst, Register src) {
4802   if (UseCompressedClassPointers) {
4803     // Store to klass gap in destination
4804     movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src);
4805   }
4806 }
4807 
4808 #ifdef ASSERT
4809 void MacroAssembler::verify_heapbase(const char* msg) {
4810   assert (UseCompressedOops, "should be compressed");
4811   assert (Universe::heap() != NULL, "java heap should be initialized");
4812   if (CheckCompressedOops) {
4813     Label ok;
4814     const auto src2 = ExternalAddress((address)CompressedOops::ptrs_base_addr());
4815     assert(!src2.is_lval(), "should not be lval");
4816     const bool is_src2_reachable = reachable(src2);
4817     if (!is_src2_reachable) {
4818       push(rscratch1);  // cmpptr trashes rscratch1
4819     }
4820     cmpptr(r12_heapbase, src2);
4821     jcc(Assembler::equal, ok);
4822     STOP(msg);
4823     bind(ok);
4824     if (!is_src2_reachable) {
4825       pop(rscratch1);
4826     }
4827   }
4828 }
4829 #endif
4830 
4831 // Algorithm must match oop.inline.hpp encode_heap_oop.
4832 void MacroAssembler::encode_heap_oop(Register r) {
4833 #ifdef ASSERT
4834   verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?");
4835 #endif
4836   verify_oop_msg(r, "broken oop in encode_heap_oop");
4837   if (CompressedOops::base() == NULL) {
4838     if (CompressedOops::shift() != 0) {
4839       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4840       shrq(r, LogMinObjAlignmentInBytes);
4841     }
4842     return;
4843   }
4844   testq(r, r);
4845   cmovq(Assembler::equal, r, r12_heapbase);
4846   subq(r, r12_heapbase);
4847   shrq(r, LogMinObjAlignmentInBytes);
4848 }
4849 
4850 void MacroAssembler::encode_heap_oop_not_null(Register r) {
4851 #ifdef ASSERT
4852   verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?");
4853   if (CheckCompressedOops) {
4854     Label ok;
4855     testq(r, r);
4856     jcc(Assembler::notEqual, ok);
4857     STOP("null oop passed to encode_heap_oop_not_null");
4858     bind(ok);
4859   }
4860 #endif
4861   verify_oop_msg(r, "broken oop in encode_heap_oop_not_null");
4862   if (CompressedOops::base() != NULL) {
4863     subq(r, r12_heapbase);
4864   }
4865   if (CompressedOops::shift() != 0) {
4866     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4867     shrq(r, LogMinObjAlignmentInBytes);
4868   }
4869 }
4870 
4871 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) {
4872 #ifdef ASSERT
4873   verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?");
4874   if (CheckCompressedOops) {
4875     Label ok;
4876     testq(src, src);
4877     jcc(Assembler::notEqual, ok);
4878     STOP("null oop passed to encode_heap_oop_not_null2");
4879     bind(ok);
4880   }
4881 #endif
4882   verify_oop_msg(src, "broken oop in encode_heap_oop_not_null2");
4883   if (dst != src) {
4884     movq(dst, src);
4885   }
4886   if (CompressedOops::base() != NULL) {
4887     subq(dst, r12_heapbase);
4888   }
4889   if (CompressedOops::shift() != 0) {
4890     assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4891     shrq(dst, LogMinObjAlignmentInBytes);
4892   }
4893 }
4894 
4895 void  MacroAssembler::decode_heap_oop(Register r) {
4896 #ifdef ASSERT
4897   verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?");
4898 #endif
4899   if (CompressedOops::base() == NULL) {
4900     if (CompressedOops::shift() != 0) {
4901       assert (LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4902       shlq(r, LogMinObjAlignmentInBytes);
4903     }
4904   } else {
4905     Label done;
4906     shlq(r, LogMinObjAlignmentInBytes);
4907     jccb(Assembler::equal, done);
4908     addq(r, r12_heapbase);
4909     bind(done);
4910   }
4911   verify_oop_msg(r, "broken oop in decode_heap_oop");
4912 }
4913 
4914 void  MacroAssembler::decode_heap_oop_not_null(Register r) {
4915   // Note: it will change flags
4916   assert (UseCompressedOops, "should only be used for compressed headers");
4917   assert (Universe::heap() != NULL, "java heap should be initialized");
4918   // Cannot assert, unverified entry point counts instructions (see .ad file)
4919   // vtableStubs also counts instructions in pd_code_size_limit.
4920   // Also do not verify_oop as this is called by verify_oop.
4921   if (CompressedOops::shift() != 0) {
4922     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4923     shlq(r, LogMinObjAlignmentInBytes);
4924     if (CompressedOops::base() != NULL) {
4925       addq(r, r12_heapbase);
4926     }
4927   } else {
4928     assert (CompressedOops::base() == NULL, "sanity");
4929   }
4930 }
4931 
4932 void  MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) {
4933   // Note: it will change flags
4934   assert (UseCompressedOops, "should only be used for compressed headers");
4935   assert (Universe::heap() != NULL, "java heap should be initialized");
4936   // Cannot assert, unverified entry point counts instructions (see .ad file)
4937   // vtableStubs also counts instructions in pd_code_size_limit.
4938   // Also do not verify_oop as this is called by verify_oop.
4939   if (CompressedOops::shift() != 0) {
4940     assert(LogMinObjAlignmentInBytes == CompressedOops::shift(), "decode alg wrong");
4941     if (LogMinObjAlignmentInBytes == Address::times_8) {
4942       leaq(dst, Address(r12_heapbase, src, Address::times_8, 0));
4943     } else {
4944       if (dst != src) {
4945         movq(dst, src);
4946       }
4947       shlq(dst, LogMinObjAlignmentInBytes);
4948       if (CompressedOops::base() != NULL) {
4949         addq(dst, r12_heapbase);
4950       }
4951     }
4952   } else {
4953     assert (CompressedOops::base() == NULL, "sanity");
4954     if (dst != src) {
4955       movq(dst, src);
4956     }
4957   }
4958 }
4959 
4960 void MacroAssembler::encode_klass_not_null(Register r, Register tmp) {
4961   assert_different_registers(r, tmp);
4962   if (CompressedKlassPointers::base() != NULL) {
4963     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4964     subq(r, tmp);
4965   }
4966   if (CompressedKlassPointers::shift() != 0) {
4967     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4968     shrq(r, LogKlassAlignmentInBytes);
4969   }
4970 }
4971 
4972 void MacroAssembler::encode_and_move_klass_not_null(Register dst, Register src) {
4973   assert_different_registers(src, dst);
4974   if (CompressedKlassPointers::base() != NULL) {
4975     mov64(dst, -(int64_t)CompressedKlassPointers::base());
4976     addq(dst, src);
4977   } else {
4978     movptr(dst, src);
4979   }
4980   if (CompressedKlassPointers::shift() != 0) {
4981     assert (LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4982     shrq(dst, LogKlassAlignmentInBytes);
4983   }
4984 }
4985 
4986 void  MacroAssembler::decode_klass_not_null(Register r, Register tmp) {
4987   assert_different_registers(r, tmp);
4988   // Note: it will change flags
4989   assert(UseCompressedClassPointers, "should only be used for compressed headers");
4990   // Cannot assert, unverified entry point counts instructions (see .ad file)
4991   // vtableStubs also counts instructions in pd_code_size_limit.
4992   // Also do not verify_oop as this is called by verify_oop.
4993   if (CompressedKlassPointers::shift() != 0) {
4994     assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
4995     shlq(r, LogKlassAlignmentInBytes);
4996   }
4997   if (CompressedKlassPointers::base() != NULL) {
4998     mov64(tmp, (int64_t)CompressedKlassPointers::base());
4999     addq(r, tmp);
5000   }
5001 }
5002 
5003 void  MacroAssembler::decode_and_move_klass_not_null(Register dst, Register src) {
5004   assert_different_registers(src, dst);
5005   // Note: it will change flags
5006   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5007   // Cannot assert, unverified entry point counts instructions (see .ad file)
5008   // vtableStubs also counts instructions in pd_code_size_limit.
5009   // Also do not verify_oop as this is called by verify_oop.
5010 
5011   if (CompressedKlassPointers::base() == NULL &&
5012       CompressedKlassPointers::shift() == 0) {
5013     // The best case scenario is that there is no base or shift. Then it is already
5014     // a pointer that needs nothing but a register rename.
5015     movl(dst, src);
5016   } else {
5017     if (CompressedKlassPointers::base() != NULL) {
5018       mov64(dst, (int64_t)CompressedKlassPointers::base());
5019     } else {
5020       xorq(dst, dst);
5021     }
5022     if (CompressedKlassPointers::shift() != 0) {
5023       assert(LogKlassAlignmentInBytes == CompressedKlassPointers::shift(), "decode alg wrong");
5024       assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?");
5025       leaq(dst, Address(dst, src, Address::times_8, 0));
5026     } else {
5027       addq(dst, src);
5028     }
5029   }
5030 }
5031 
5032 void  MacroAssembler::set_narrow_oop(Register dst, jobject obj) {
5033   assert (UseCompressedOops, "should only be used for compressed headers");
5034   assert (Universe::heap() != NULL, "java heap should be initialized");
5035   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5036   int oop_index = oop_recorder()->find_index(obj);
5037   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5038   mov_narrow_oop(dst, oop_index, rspec);
5039 }
5040 
5041 void  MacroAssembler::set_narrow_oop(Address dst, jobject obj) {
5042   assert (UseCompressedOops, "should only be used for compressed headers");
5043   assert (Universe::heap() != NULL, "java heap should be initialized");
5044   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5045   int oop_index = oop_recorder()->find_index(obj);
5046   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5047   mov_narrow_oop(dst, oop_index, rspec);
5048 }
5049 
5050 void  MacroAssembler::set_narrow_klass(Register dst, Klass* k) {
5051   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5052   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5053   int klass_index = oop_recorder()->find_index(k);
5054   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5055   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5056 }
5057 
5058 void  MacroAssembler::set_narrow_klass(Address dst, Klass* k) {
5059   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5060   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5061   int klass_index = oop_recorder()->find_index(k);
5062   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5063   mov_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5064 }
5065 
5066 void  MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) {
5067   assert (UseCompressedOops, "should only be used for compressed headers");
5068   assert (Universe::heap() != NULL, "java heap should be initialized");
5069   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5070   int oop_index = oop_recorder()->find_index(obj);
5071   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5072   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5073 }
5074 
5075 void  MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) {
5076   assert (UseCompressedOops, "should only be used for compressed headers");
5077   assert (Universe::heap() != NULL, "java heap should be initialized");
5078   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5079   int oop_index = oop_recorder()->find_index(obj);
5080   RelocationHolder rspec = oop_Relocation::spec(oop_index);
5081   Assembler::cmp_narrow_oop(dst, oop_index, rspec);
5082 }
5083 
5084 void  MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) {
5085   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5086   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5087   int klass_index = oop_recorder()->find_index(k);
5088   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5089   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5090 }
5091 
5092 void  MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) {
5093   assert (UseCompressedClassPointers, "should only be used for compressed headers");
5094   assert (oop_recorder() != NULL, "this assembler needs an OopRecorder");
5095   int klass_index = oop_recorder()->find_index(k);
5096   RelocationHolder rspec = metadata_Relocation::spec(klass_index);
5097   Assembler::cmp_narrow_oop(dst, CompressedKlassPointers::encode(k), rspec);
5098 }
5099 
5100 void MacroAssembler::reinit_heapbase() {
5101   if (UseCompressedOops) {
5102     if (Universe::heap() != NULL) {
5103       if (CompressedOops::base() == NULL) {
5104         MacroAssembler::xorptr(r12_heapbase, r12_heapbase);
5105       } else {
5106         mov64(r12_heapbase, (int64_t)CompressedOops::ptrs_base());
5107       }
5108     } else {
5109       movptr(r12_heapbase, ExternalAddress((address)CompressedOops::ptrs_base_addr()));
5110     }
5111   }
5112 }
5113 
5114 #endif // _LP64
5115 
5116 // C2 compiled method's prolog code.
5117 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b, bool is_stub) {
5118 
5119   // WARNING: Initial instruction MUST be 5 bytes or longer so that
5120   // NativeJump::patch_verified_entry will be able to patch out the entry
5121   // code safely. The push to verify stack depth is ok at 5 bytes,
5122   // the frame allocation can be either 3 or 6 bytes. So if we don't do
5123   // stack bang then we must use the 6 byte frame allocation even if
5124   // we have no frame. :-(
5125   assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect");
5126 
5127   assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
5128   // Remove word for return addr
5129   framesize -= wordSize;
5130   stack_bang_size -= wordSize;
5131 
5132   // Calls to C2R adapters often do not accept exceptional returns.
5133   // We require that their callers must bang for them.  But be careful, because
5134   // some VM calls (such as call site linkage) can use several kilobytes of
5135   // stack.  But the stack safety zone should account for that.
5136   // See bugs 4446381, 4468289, 4497237.
5137   if (stack_bang_size > 0) {
5138     generate_stack_overflow_check(stack_bang_size);
5139 
5140     // We always push rbp, so that on return to interpreter rbp, will be
5141     // restored correctly and we can correct the stack.
5142     push(rbp);
5143     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5144     if (PreserveFramePointer) {
5145       mov(rbp, rsp);
5146     }
5147     // Remove word for ebp
5148     framesize -= wordSize;
5149 
5150     // Create frame
5151     if (framesize) {
5152       subptr(rsp, framesize);
5153     }
5154   } else {
5155     // Create frame (force generation of a 4 byte immediate value)
5156     subptr_imm32(rsp, framesize);
5157 
5158     // Save RBP register now.
5159     framesize -= wordSize;
5160     movptr(Address(rsp, framesize), rbp);
5161     // Save caller's stack pointer into RBP if the frame pointer is preserved.
5162     if (PreserveFramePointer) {
5163       movptr(rbp, rsp);
5164       if (framesize > 0) {
5165         addptr(rbp, framesize);
5166       }
5167     }
5168   }
5169 
5170   if (VerifyStackAtCalls) { // Majik cookie to verify stack depth
5171     framesize -= wordSize;
5172     movptr(Address(rsp, framesize), (int32_t)0xbadb100d);
5173   }
5174 
5175 #ifndef _LP64
5176   // If method sets FPU control word do it now
5177   if (fp_mode_24b) {
5178     fldcw(ExternalAddress(StubRoutines::x86::addr_fpu_cntrl_wrd_24()));
5179   }
5180   if (UseSSE >= 2 && VerifyFPU) {
5181     verify_FPU(0, "FPU stack must be clean on entry");
5182   }
5183 #endif
5184 
5185 #ifdef ASSERT
5186   if (VerifyStackAtCalls) {
5187     Label L;
5188     push(rax);
5189     mov(rax, rsp);
5190     andptr(rax, StackAlignmentInBytes-1);
5191     cmpptr(rax, StackAlignmentInBytes-wordSize);
5192     pop(rax);
5193     jcc(Assembler::equal, L);
5194     STOP("Stack is not properly aligned!");
5195     bind(L);
5196   }
5197 #endif
5198 
5199   if (!is_stub) {
5200     BarrierSetAssembler* bs = BarrierSet::barrier_set()->barrier_set_assembler();
5201     bs->nmethod_entry_barrier(this);
5202   }
5203 }
5204 
5205 #if COMPILER2_OR_JVMCI
5206 
5207 // clear memory of size 'cnt' qwords, starting at 'base' using XMM/YMM/ZMM registers
5208 void MacroAssembler::xmm_clear_mem(Register base, Register cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5209   // cnt - number of qwords (8-byte words).
5210   // base - start address, qword aligned.
5211   Label L_zero_64_bytes, L_loop, L_sloop, L_tail, L_end;
5212   bool use64byteVector = (MaxVectorSize == 64) && (VM_Version::avx3_threshold() == 0);
5213   if (use64byteVector) {
5214     vpxor(xtmp, xtmp, xtmp, AVX_512bit);
5215   } else if (MaxVectorSize >= 32) {
5216     vpxor(xtmp, xtmp, xtmp, AVX_256bit);
5217   } else {
5218     pxor(xtmp, xtmp);
5219   }
5220   jmp(L_zero_64_bytes);
5221 
5222   BIND(L_loop);
5223   if (MaxVectorSize >= 32) {
5224     fill64(base, 0, xtmp, use64byteVector);
5225   } else {
5226     movdqu(Address(base,  0), xtmp);
5227     movdqu(Address(base, 16), xtmp);
5228     movdqu(Address(base, 32), xtmp);
5229     movdqu(Address(base, 48), xtmp);
5230   }
5231   addptr(base, 64);
5232 
5233   BIND(L_zero_64_bytes);
5234   subptr(cnt, 8);
5235   jccb(Assembler::greaterEqual, L_loop);
5236 
5237   // Copy trailing 64 bytes
5238   if (use64byteVector) {
5239     addptr(cnt, 8);
5240     jccb(Assembler::equal, L_end);
5241     fill64_masked(3, base, 0, xtmp, mask, cnt, rtmp, true);
5242     jmp(L_end);
5243   } else {
5244     addptr(cnt, 4);
5245     jccb(Assembler::less, L_tail);
5246     if (MaxVectorSize >= 32) {
5247       vmovdqu(Address(base, 0), xtmp);
5248     } else {
5249       movdqu(Address(base,  0), xtmp);
5250       movdqu(Address(base, 16), xtmp);
5251     }
5252   }
5253   addptr(base, 32);
5254   subptr(cnt, 4);
5255 
5256   BIND(L_tail);
5257   addptr(cnt, 4);
5258   jccb(Assembler::lessEqual, L_end);
5259   if (UseAVX > 2 && MaxVectorSize >= 32 && VM_Version::supports_avx512vl()) {
5260     fill32_masked(3, base, 0, xtmp, mask, cnt, rtmp);
5261   } else {
5262     decrement(cnt);
5263 
5264     BIND(L_sloop);
5265     movq(Address(base, 0), xtmp);
5266     addptr(base, 8);
5267     decrement(cnt);
5268     jccb(Assembler::greaterEqual, L_sloop);
5269   }
5270   BIND(L_end);
5271 }
5272 
5273 // Clearing constant sized memory using YMM/ZMM registers.
5274 void MacroAssembler::clear_mem(Register base, int cnt, Register rtmp, XMMRegister xtmp, KRegister mask) {
5275   assert(UseAVX > 2 && VM_Version::supports_avx512vlbw(), "");
5276   bool use64byteVector = (MaxVectorSize > 32) && (VM_Version::avx3_threshold() == 0);
5277 
5278   int vector64_count = (cnt & (~0x7)) >> 3;
5279   cnt = cnt & 0x7;
5280 
5281   // 64 byte initialization loop.
5282   vpxor(xtmp, xtmp, xtmp, use64byteVector ? AVX_512bit : AVX_256bit);
5283   for (int i = 0; i < vector64_count; i++) {
5284     fill64(base, i * 64, xtmp, use64byteVector);
5285   }
5286 
5287   // Clear remaining 64 byte tail.
5288   int disp = vector64_count * 64;
5289   if (cnt) {
5290     switch (cnt) {
5291       case 1:
5292         movq(Address(base, disp), xtmp);
5293         break;
5294       case 2:
5295         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_128bit);
5296         break;
5297       case 3:
5298         movl(rtmp, 0x7);
5299         kmovwl(mask, rtmp);
5300         evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_256bit);
5301         break;
5302       case 4:
5303         evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5304         break;
5305       case 5:
5306         if (use64byteVector) {
5307           movl(rtmp, 0x1F);
5308           kmovwl(mask, rtmp);
5309           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5310         } else {
5311           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5312           movq(Address(base, disp + 32), xtmp);
5313         }
5314         break;
5315       case 6:
5316         if (use64byteVector) {
5317           movl(rtmp, 0x3F);
5318           kmovwl(mask, rtmp);
5319           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5320         } else {
5321           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5322           evmovdqu(T_LONG, k0, Address(base, disp + 32), xtmp, Assembler::AVX_128bit);
5323         }
5324         break;
5325       case 7:
5326         if (use64byteVector) {
5327           movl(rtmp, 0x7F);
5328           kmovwl(mask, rtmp);
5329           evmovdqu(T_LONG, mask, Address(base, disp), xtmp, Assembler::AVX_512bit);
5330         } else {
5331           evmovdqu(T_LONG, k0, Address(base, disp), xtmp, Assembler::AVX_256bit);
5332           movl(rtmp, 0x7);
5333           kmovwl(mask, rtmp);
5334           evmovdqu(T_LONG, mask, Address(base, disp + 32), xtmp, Assembler::AVX_256bit);
5335         }
5336         break;
5337       default:
5338         fatal("Unexpected length : %d\n",cnt);
5339         break;
5340     }
5341   }
5342 }
5343 
5344 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, XMMRegister xtmp,
5345                                bool is_large, KRegister mask) {
5346   // cnt      - number of qwords (8-byte words).
5347   // base     - start address, qword aligned.
5348   // is_large - if optimizers know cnt is larger than InitArrayShortSize
5349   assert(base==rdi, "base register must be edi for rep stos");
5350   assert(tmp==rax,   "tmp register must be eax for rep stos");
5351   assert(cnt==rcx,   "cnt register must be ecx for rep stos");
5352   assert(InitArrayShortSize % BytesPerLong == 0,
5353     "InitArrayShortSize should be the multiple of BytesPerLong");
5354 
5355   Label DONE;
5356   if (!is_large || !UseXMMForObjInit) {
5357     xorptr(tmp, tmp);
5358   }
5359 
5360   if (!is_large) {
5361     Label LOOP, LONG;
5362     cmpptr(cnt, InitArrayShortSize/BytesPerLong);
5363     jccb(Assembler::greater, LONG);
5364 
5365     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5366 
5367     decrement(cnt);
5368     jccb(Assembler::negative, DONE); // Zero length
5369 
5370     // Use individual pointer-sized stores for small counts:
5371     BIND(LOOP);
5372     movptr(Address(base, cnt, Address::times_ptr), tmp);
5373     decrement(cnt);
5374     jccb(Assembler::greaterEqual, LOOP);
5375     jmpb(DONE);
5376 
5377     BIND(LONG);
5378   }
5379 
5380   // Use longer rep-prefixed ops for non-small counts:
5381   if (UseFastStosb) {
5382     shlptr(cnt, 3); // convert to number of bytes
5383     rep_stosb();
5384   } else if (UseXMMForObjInit) {
5385     xmm_clear_mem(base, cnt, tmp, xtmp, mask);
5386   } else {
5387     NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM
5388     rep_stos();
5389   }
5390 
5391   BIND(DONE);
5392 }
5393 
5394 #endif //COMPILER2_OR_JVMCI
5395 
5396 
5397 void MacroAssembler::generate_fill(BasicType t, bool aligned,
5398                                    Register to, Register value, Register count,
5399                                    Register rtmp, XMMRegister xtmp) {
5400   ShortBranchVerifier sbv(this);
5401   assert_different_registers(to, value, count, rtmp);
5402   Label L_exit;
5403   Label L_fill_2_bytes, L_fill_4_bytes;
5404 
5405 #if defined(COMPILER2) && defined(_LP64)
5406   if(MaxVectorSize >=32 &&
5407      VM_Version::supports_avx512vlbw() &&
5408      VM_Version::supports_bmi2()) {
5409     generate_fill_avx3(t, to, value, count, rtmp, xtmp);
5410     return;
5411   }
5412 #endif
5413 
5414   int shift = -1;
5415   switch (t) {
5416     case T_BYTE:
5417       shift = 2;
5418       break;
5419     case T_SHORT:
5420       shift = 1;
5421       break;
5422     case T_INT:
5423       shift = 0;
5424       break;
5425     default: ShouldNotReachHere();
5426   }
5427 
5428   if (t == T_BYTE) {
5429     andl(value, 0xff);
5430     movl(rtmp, value);
5431     shll(rtmp, 8);
5432     orl(value, rtmp);
5433   }
5434   if (t == T_SHORT) {
5435     andl(value, 0xffff);
5436   }
5437   if (t == T_BYTE || t == T_SHORT) {
5438     movl(rtmp, value);
5439     shll(rtmp, 16);
5440     orl(value, rtmp);
5441   }
5442 
5443   cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element
5444   jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp
5445   if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) {
5446     Label L_skip_align2;
5447     // align source address at 4 bytes address boundary
5448     if (t == T_BYTE) {
5449       Label L_skip_align1;
5450       // One byte misalignment happens only for byte arrays
5451       testptr(to, 1);
5452       jccb(Assembler::zero, L_skip_align1);
5453       movb(Address(to, 0), value);
5454       increment(to);
5455       decrement(count);
5456       BIND(L_skip_align1);
5457     }
5458     // Two bytes misalignment happens only for byte and short (char) arrays
5459     testptr(to, 2);
5460     jccb(Assembler::zero, L_skip_align2);
5461     movw(Address(to, 0), value);
5462     addptr(to, 2);
5463     subl(count, 1<<(shift-1));
5464     BIND(L_skip_align2);
5465   }
5466   if (UseSSE < 2) {
5467     Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5468     // Fill 32-byte chunks
5469     subl(count, 8 << shift);
5470     jcc(Assembler::less, L_check_fill_8_bytes);
5471     align(16);
5472 
5473     BIND(L_fill_32_bytes_loop);
5474 
5475     for (int i = 0; i < 32; i += 4) {
5476       movl(Address(to, i), value);
5477     }
5478 
5479     addptr(to, 32);
5480     subl(count, 8 << shift);
5481     jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5482     BIND(L_check_fill_8_bytes);
5483     addl(count, 8 << shift);
5484     jccb(Assembler::zero, L_exit);
5485     jmpb(L_fill_8_bytes);
5486 
5487     //
5488     // length is too short, just fill qwords
5489     //
5490     BIND(L_fill_8_bytes_loop);
5491     movl(Address(to, 0), value);
5492     movl(Address(to, 4), value);
5493     addptr(to, 8);
5494     BIND(L_fill_8_bytes);
5495     subl(count, 1 << (shift + 1));
5496     jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5497     // fall through to fill 4 bytes
5498   } else {
5499     Label L_fill_32_bytes;
5500     if (!UseUnalignedLoadStores) {
5501       // align to 8 bytes, we know we are 4 byte aligned to start
5502       testptr(to, 4);
5503       jccb(Assembler::zero, L_fill_32_bytes);
5504       movl(Address(to, 0), value);
5505       addptr(to, 4);
5506       subl(count, 1<<shift);
5507     }
5508     BIND(L_fill_32_bytes);
5509     {
5510       assert( UseSSE >= 2, "supported cpu only" );
5511       Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes;
5512       movdl(xtmp, value);
5513       if (UseAVX >= 2 && UseUnalignedLoadStores) {
5514         Label L_check_fill_32_bytes;
5515         if (UseAVX > 2) {
5516           // Fill 64-byte chunks
5517           Label L_fill_64_bytes_loop_avx3, L_check_fill_64_bytes_avx2;
5518 
5519           // If number of bytes to fill < VM_Version::avx3_threshold(), perform fill using AVX2
5520           cmpl(count, VM_Version::avx3_threshold());
5521           jccb(Assembler::below, L_check_fill_64_bytes_avx2);
5522 
5523           vpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit);
5524 
5525           subl(count, 16 << shift);
5526           jccb(Assembler::less, L_check_fill_32_bytes);
5527           align(16);
5528 
5529           BIND(L_fill_64_bytes_loop_avx3);
5530           evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit);
5531           addptr(to, 64);
5532           subl(count, 16 << shift);
5533           jcc(Assembler::greaterEqual, L_fill_64_bytes_loop_avx3);
5534           jmpb(L_check_fill_32_bytes);
5535 
5536           BIND(L_check_fill_64_bytes_avx2);
5537         }
5538         // Fill 64-byte chunks
5539         Label L_fill_64_bytes_loop;
5540         vpbroadcastd(xtmp, xtmp, Assembler::AVX_256bit);
5541 
5542         subl(count, 16 << shift);
5543         jcc(Assembler::less, L_check_fill_32_bytes);
5544         align(16);
5545 
5546         BIND(L_fill_64_bytes_loop);
5547         vmovdqu(Address(to, 0), xtmp);
5548         vmovdqu(Address(to, 32), xtmp);
5549         addptr(to, 64);
5550         subl(count, 16 << shift);
5551         jcc(Assembler::greaterEqual, L_fill_64_bytes_loop);
5552 
5553         BIND(L_check_fill_32_bytes);
5554         addl(count, 8 << shift);
5555         jccb(Assembler::less, L_check_fill_8_bytes);
5556         vmovdqu(Address(to, 0), xtmp);
5557         addptr(to, 32);
5558         subl(count, 8 << shift);
5559 
5560         BIND(L_check_fill_8_bytes);
5561         // clean upper bits of YMM registers
5562         movdl(xtmp, value);
5563         pshufd(xtmp, xtmp, 0);
5564       } else {
5565         // Fill 32-byte chunks
5566         pshufd(xtmp, xtmp, 0);
5567 
5568         subl(count, 8 << shift);
5569         jcc(Assembler::less, L_check_fill_8_bytes);
5570         align(16);
5571 
5572         BIND(L_fill_32_bytes_loop);
5573 
5574         if (UseUnalignedLoadStores) {
5575           movdqu(Address(to, 0), xtmp);
5576           movdqu(Address(to, 16), xtmp);
5577         } else {
5578           movq(Address(to, 0), xtmp);
5579           movq(Address(to, 8), xtmp);
5580           movq(Address(to, 16), xtmp);
5581           movq(Address(to, 24), xtmp);
5582         }
5583 
5584         addptr(to, 32);
5585         subl(count, 8 << shift);
5586         jcc(Assembler::greaterEqual, L_fill_32_bytes_loop);
5587 
5588         BIND(L_check_fill_8_bytes);
5589       }
5590       addl(count, 8 << shift);
5591       jccb(Assembler::zero, L_exit);
5592       jmpb(L_fill_8_bytes);
5593 
5594       //
5595       // length is too short, just fill qwords
5596       //
5597       BIND(L_fill_8_bytes_loop);
5598       movq(Address(to, 0), xtmp);
5599       addptr(to, 8);
5600       BIND(L_fill_8_bytes);
5601       subl(count, 1 << (shift + 1));
5602       jcc(Assembler::greaterEqual, L_fill_8_bytes_loop);
5603     }
5604   }
5605   // fill trailing 4 bytes
5606   BIND(L_fill_4_bytes);
5607   testl(count, 1<<shift);
5608   jccb(Assembler::zero, L_fill_2_bytes);
5609   movl(Address(to, 0), value);
5610   if (t == T_BYTE || t == T_SHORT) {
5611     Label L_fill_byte;
5612     addptr(to, 4);
5613     BIND(L_fill_2_bytes);
5614     // fill trailing 2 bytes
5615     testl(count, 1<<(shift-1));
5616     jccb(Assembler::zero, L_fill_byte);
5617     movw(Address(to, 0), value);
5618     if (t == T_BYTE) {
5619       addptr(to, 2);
5620       BIND(L_fill_byte);
5621       // fill trailing byte
5622       testl(count, 1);
5623       jccb(Assembler::zero, L_exit);
5624       movb(Address(to, 0), value);
5625     } else {
5626       BIND(L_fill_byte);
5627     }
5628   } else {
5629     BIND(L_fill_2_bytes);
5630   }
5631   BIND(L_exit);
5632 }
5633 
5634 void MacroAssembler::evpbroadcast(BasicType type, XMMRegister dst, Register src, int vector_len) {
5635   switch(type) {
5636     case T_BYTE:
5637     case T_BOOLEAN:
5638       evpbroadcastb(dst, src, vector_len);
5639       break;
5640     case T_SHORT:
5641     case T_CHAR:
5642       evpbroadcastw(dst, src, vector_len);
5643       break;
5644     case T_INT:
5645     case T_FLOAT:
5646       evpbroadcastd(dst, src, vector_len);
5647       break;
5648     case T_LONG:
5649     case T_DOUBLE:
5650       evpbroadcastq(dst, src, vector_len);
5651       break;
5652     default:
5653       fatal("Unhandled type : %s", type2name(type));
5654       break;
5655   }
5656 }
5657 
5658 // encode char[] to byte[] in ISO_8859_1 or ASCII
5659    //@IntrinsicCandidate
5660    //private static int implEncodeISOArray(byte[] sa, int sp,
5661    //byte[] da, int dp, int len) {
5662    //  int i = 0;
5663    //  for (; i < len; i++) {
5664    //    char c = StringUTF16.getChar(sa, sp++);
5665    //    if (c > '\u00FF')
5666    //      break;
5667    //    da[dp++] = (byte)c;
5668    //  }
5669    //  return i;
5670    //}
5671    //
5672    //@IntrinsicCandidate
5673    //private static int implEncodeAsciiArray(char[] sa, int sp,
5674    //    byte[] da, int dp, int len) {
5675    //  int i = 0;
5676    //  for (; i < len; i++) {
5677    //    char c = sa[sp++];
5678    //    if (c >= '\u0080')
5679    //      break;
5680    //    da[dp++] = (byte)c;
5681    //  }
5682    //  return i;
5683    //}
5684 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len,
5685   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
5686   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
5687   Register tmp5, Register result, bool ascii) {
5688 
5689   // rsi: src
5690   // rdi: dst
5691   // rdx: len
5692   // rcx: tmp5
5693   // rax: result
5694   ShortBranchVerifier sbv(this);
5695   assert_different_registers(src, dst, len, tmp5, result);
5696   Label L_done, L_copy_1_char, L_copy_1_char_exit;
5697 
5698   int mask = ascii ? 0xff80ff80 : 0xff00ff00;
5699   int short_mask = ascii ? 0xff80 : 0xff00;
5700 
5701   // set result
5702   xorl(result, result);
5703   // check for zero length
5704   testl(len, len);
5705   jcc(Assembler::zero, L_done);
5706 
5707   movl(result, len);
5708 
5709   // Setup pointers
5710   lea(src, Address(src, len, Address::times_2)); // char[]
5711   lea(dst, Address(dst, len, Address::times_1)); // byte[]
5712   negptr(len);
5713 
5714   if (UseSSE42Intrinsics || UseAVX >= 2) {
5715     Label L_copy_8_chars, L_copy_8_chars_exit;
5716     Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit;
5717 
5718     if (UseAVX >= 2) {
5719       Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit;
5720       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5721       movdl(tmp1Reg, tmp5);
5722       vpbroadcastd(tmp1Reg, tmp1Reg, Assembler::AVX_256bit);
5723       jmp(L_chars_32_check);
5724 
5725       bind(L_copy_32_chars);
5726       vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64));
5727       vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32));
5728       vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5729       vptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5730       jccb(Assembler::notZero, L_copy_32_chars_exit);
5731       vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1);
5732       vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1);
5733       vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg);
5734 
5735       bind(L_chars_32_check);
5736       addptr(len, 32);
5737       jcc(Assembler::lessEqual, L_copy_32_chars);
5738 
5739       bind(L_copy_32_chars_exit);
5740       subptr(len, 16);
5741       jccb(Assembler::greater, L_copy_16_chars_exit);
5742 
5743     } else if (UseSSE42Intrinsics) {
5744       movl(tmp5, mask);   // create mask to test for Unicode or non-ASCII chars in vector
5745       movdl(tmp1Reg, tmp5);
5746       pshufd(tmp1Reg, tmp1Reg, 0);
5747       jmpb(L_chars_16_check);
5748     }
5749 
5750     bind(L_copy_16_chars);
5751     if (UseAVX >= 2) {
5752       vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32));
5753       vptest(tmp2Reg, tmp1Reg);
5754       jcc(Assembler::notZero, L_copy_16_chars_exit);
5755       vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1);
5756       vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1);
5757     } else {
5758       if (UseAVX > 0) {
5759         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5760         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5761         vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0);
5762       } else {
5763         movdqu(tmp3Reg, Address(src, len, Address::times_2, -32));
5764         por(tmp2Reg, tmp3Reg);
5765         movdqu(tmp4Reg, Address(src, len, Address::times_2, -16));
5766         por(tmp2Reg, tmp4Reg);
5767       }
5768       ptest(tmp2Reg, tmp1Reg);       // check for Unicode or non-ASCII chars in vector
5769       jccb(Assembler::notZero, L_copy_16_chars_exit);
5770       packuswb(tmp3Reg, tmp4Reg);
5771     }
5772     movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg);
5773 
5774     bind(L_chars_16_check);
5775     addptr(len, 16);
5776     jcc(Assembler::lessEqual, L_copy_16_chars);
5777 
5778     bind(L_copy_16_chars_exit);
5779     if (UseAVX >= 2) {
5780       // clean upper bits of YMM registers
5781       vpxor(tmp2Reg, tmp2Reg);
5782       vpxor(tmp3Reg, tmp3Reg);
5783       vpxor(tmp4Reg, tmp4Reg);
5784       movdl(tmp1Reg, tmp5);
5785       pshufd(tmp1Reg, tmp1Reg, 0);
5786     }
5787     subptr(len, 8);
5788     jccb(Assembler::greater, L_copy_8_chars_exit);
5789 
5790     bind(L_copy_8_chars);
5791     movdqu(tmp3Reg, Address(src, len, Address::times_2, -16));
5792     ptest(tmp3Reg, tmp1Reg);
5793     jccb(Assembler::notZero, L_copy_8_chars_exit);
5794     packuswb(tmp3Reg, tmp1Reg);
5795     movq(Address(dst, len, Address::times_1, -8), tmp3Reg);
5796     addptr(len, 8);
5797     jccb(Assembler::lessEqual, L_copy_8_chars);
5798 
5799     bind(L_copy_8_chars_exit);
5800     subptr(len, 8);
5801     jccb(Assembler::zero, L_done);
5802   }
5803 
5804   bind(L_copy_1_char);
5805   load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0));
5806   testl(tmp5, short_mask);      // check if Unicode or non-ASCII char
5807   jccb(Assembler::notZero, L_copy_1_char_exit);
5808   movb(Address(dst, len, Address::times_1, 0), tmp5);
5809   addptr(len, 1);
5810   jccb(Assembler::less, L_copy_1_char);
5811 
5812   bind(L_copy_1_char_exit);
5813   addptr(result, len); // len is negative count of not processed elements
5814 
5815   bind(L_done);
5816 }
5817 
5818 #ifdef _LP64
5819 /**
5820  * Helper for multiply_to_len().
5821  */
5822 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
5823   addq(dest_lo, src1);
5824   adcq(dest_hi, 0);
5825   addq(dest_lo, src2);
5826   adcq(dest_hi, 0);
5827 }
5828 
5829 /**
5830  * Multiply 64 bit by 64 bit first loop.
5831  */
5832 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
5833                                            Register y, Register y_idx, Register z,
5834                                            Register carry, Register product,
5835                                            Register idx, Register kdx) {
5836   //
5837   //  jlong carry, x[], y[], z[];
5838   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
5839   //    huge_128 product = y[idx] * x[xstart] + carry;
5840   //    z[kdx] = (jlong)product;
5841   //    carry  = (jlong)(product >>> 64);
5842   //  }
5843   //  z[xstart] = carry;
5844   //
5845 
5846   Label L_first_loop, L_first_loop_exit;
5847   Label L_one_x, L_one_y, L_multiply;
5848 
5849   decrementl(xstart);
5850   jcc(Assembler::negative, L_one_x);
5851 
5852   movq(x_xstart, Address(x, xstart, Address::times_4,  0));
5853   rorq(x_xstart, 32); // convert big-endian to little-endian
5854 
5855   bind(L_first_loop);
5856   decrementl(idx);
5857   jcc(Assembler::negative, L_first_loop_exit);
5858   decrementl(idx);
5859   jcc(Assembler::negative, L_one_y);
5860   movq(y_idx, Address(y, idx, Address::times_4,  0));
5861   rorq(y_idx, 32); // convert big-endian to little-endian
5862   bind(L_multiply);
5863   movq(product, x_xstart);
5864   mulq(y_idx); // product(rax) * y_idx -> rdx:rax
5865   addq(product, carry);
5866   adcq(rdx, 0);
5867   subl(kdx, 2);
5868   movl(Address(z, kdx, Address::times_4,  4), product);
5869   shrq(product, 32);
5870   movl(Address(z, kdx, Address::times_4,  0), product);
5871   movq(carry, rdx);
5872   jmp(L_first_loop);
5873 
5874   bind(L_one_y);
5875   movl(y_idx, Address(y,  0));
5876   jmp(L_multiply);
5877 
5878   bind(L_one_x);
5879   movl(x_xstart, Address(x,  0));
5880   jmp(L_first_loop);
5881 
5882   bind(L_first_loop_exit);
5883 }
5884 
5885 /**
5886  * Multiply 64 bit by 64 bit and add 128 bit.
5887  */
5888 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z,
5889                                             Register yz_idx, Register idx,
5890                                             Register carry, Register product, int offset) {
5891   //     huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
5892   //     z[kdx] = (jlong)product;
5893 
5894   movq(yz_idx, Address(y, idx, Address::times_4,  offset));
5895   rorq(yz_idx, 32); // convert big-endian to little-endian
5896   movq(product, x_xstart);
5897   mulq(yz_idx);     // product(rax) * yz_idx -> rdx:product(rax)
5898   movq(yz_idx, Address(z, idx, Address::times_4,  offset));
5899   rorq(yz_idx, 32); // convert big-endian to little-endian
5900 
5901   add2_with_carry(rdx, product, carry, yz_idx);
5902 
5903   movl(Address(z, idx, Address::times_4,  offset+4), product);
5904   shrq(product, 32);
5905   movl(Address(z, idx, Address::times_4,  offset), product);
5906 
5907 }
5908 
5909 /**
5910  * Multiply 128 bit by 128 bit. Unrolled inner loop.
5911  */
5912 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
5913                                              Register yz_idx, Register idx, Register jdx,
5914                                              Register carry, Register product,
5915                                              Register carry2) {
5916   //   jlong carry, x[], y[], z[];
5917   //   int kdx = ystart+1;
5918   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
5919   //     huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
5920   //     z[kdx+idx+1] = (jlong)product;
5921   //     jlong carry2  = (jlong)(product >>> 64);
5922   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
5923   //     z[kdx+idx] = (jlong)product;
5924   //     carry  = (jlong)(product >>> 64);
5925   //   }
5926   //   idx += 2;
5927   //   if (idx > 0) {
5928   //     product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
5929   //     z[kdx+idx] = (jlong)product;
5930   //     carry  = (jlong)(product >>> 64);
5931   //   }
5932   //
5933 
5934   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
5935 
5936   movl(jdx, idx);
5937   andl(jdx, 0xFFFFFFFC);
5938   shrl(jdx, 2);
5939 
5940   bind(L_third_loop);
5941   subl(jdx, 1);
5942   jcc(Assembler::negative, L_third_loop_exit);
5943   subl(idx, 4);
5944 
5945   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
5946   movq(carry2, rdx);
5947 
5948   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
5949   movq(carry, rdx);
5950   jmp(L_third_loop);
5951 
5952   bind (L_third_loop_exit);
5953 
5954   andl (idx, 0x3);
5955   jcc(Assembler::zero, L_post_third_loop_done);
5956 
5957   Label L_check_1;
5958   subl(idx, 2);
5959   jcc(Assembler::negative, L_check_1);
5960 
5961   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
5962   movq(carry, rdx);
5963 
5964   bind (L_check_1);
5965   addl (idx, 0x2);
5966   andl (idx, 0x1);
5967   subl(idx, 1);
5968   jcc(Assembler::negative, L_post_third_loop_done);
5969 
5970   movl(yz_idx, Address(y, idx, Address::times_4,  0));
5971   movq(product, x_xstart);
5972   mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax)
5973   movl(yz_idx, Address(z, idx, Address::times_4,  0));
5974 
5975   add2_with_carry(rdx, product, yz_idx, carry);
5976 
5977   movl(Address(z, idx, Address::times_4,  0), product);
5978   shrq(product, 32);
5979 
5980   shlq(rdx, 32);
5981   orq(product, rdx);
5982   movq(carry, product);
5983 
5984   bind(L_post_third_loop_done);
5985 }
5986 
5987 /**
5988  * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop.
5989  *
5990  */
5991 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z,
5992                                                   Register carry, Register carry2,
5993                                                   Register idx, Register jdx,
5994                                                   Register yz_idx1, Register yz_idx2,
5995                                                   Register tmp, Register tmp3, Register tmp4) {
5996   assert(UseBMI2Instructions, "should be used only when BMI2 is available");
5997 
5998   //   jlong carry, x[], y[], z[];
5999   //   int kdx = ystart+1;
6000   //   for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6001   //     huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry;
6002   //     jlong carry2  = (jlong)(tmp3 >>> 64);
6003   //     huge_128 tmp4 = (y[idx]   * rdx) + z[kdx+idx] + carry2;
6004   //     carry  = (jlong)(tmp4 >>> 64);
6005   //     z[kdx+idx+1] = (jlong)tmp3;
6006   //     z[kdx+idx] = (jlong)tmp4;
6007   //   }
6008   //   idx += 2;
6009   //   if (idx > 0) {
6010   //     yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry;
6011   //     z[kdx+idx] = (jlong)yz_idx1;
6012   //     carry  = (jlong)(yz_idx1 >>> 64);
6013   //   }
6014   //
6015 
6016   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6017 
6018   movl(jdx, idx);
6019   andl(jdx, 0xFFFFFFFC);
6020   shrl(jdx, 2);
6021 
6022   bind(L_third_loop);
6023   subl(jdx, 1);
6024   jcc(Assembler::negative, L_third_loop_exit);
6025   subl(idx, 4);
6026 
6027   movq(yz_idx1,  Address(y, idx, Address::times_4,  8));
6028   rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian
6029   movq(yz_idx2, Address(y, idx, Address::times_4,  0));
6030   rorxq(yz_idx2, yz_idx2, 32);
6031 
6032   mulxq(tmp4, tmp3, yz_idx1);  //  yz_idx1 * rdx -> tmp4:tmp3
6033   mulxq(carry2, tmp, yz_idx2); //  yz_idx2 * rdx -> carry2:tmp
6034 
6035   movq(yz_idx1,  Address(z, idx, Address::times_4,  8));
6036   rorxq(yz_idx1, yz_idx1, 32);
6037   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6038   rorxq(yz_idx2, yz_idx2, 32);
6039 
6040   if (VM_Version::supports_adx()) {
6041     adcxq(tmp3, carry);
6042     adoxq(tmp3, yz_idx1);
6043 
6044     adcxq(tmp4, tmp);
6045     adoxq(tmp4, yz_idx2);
6046 
6047     movl(carry, 0); // does not affect flags
6048     adcxq(carry2, carry);
6049     adoxq(carry2, carry);
6050   } else {
6051     add2_with_carry(tmp4, tmp3, carry, yz_idx1);
6052     add2_with_carry(carry2, tmp4, tmp, yz_idx2);
6053   }
6054   movq(carry, carry2);
6055 
6056   movl(Address(z, idx, Address::times_4, 12), tmp3);
6057   shrq(tmp3, 32);
6058   movl(Address(z, idx, Address::times_4,  8), tmp3);
6059 
6060   movl(Address(z, idx, Address::times_4,  4), tmp4);
6061   shrq(tmp4, 32);
6062   movl(Address(z, idx, Address::times_4,  0), tmp4);
6063 
6064   jmp(L_third_loop);
6065 
6066   bind (L_third_loop_exit);
6067 
6068   andl (idx, 0x3);
6069   jcc(Assembler::zero, L_post_third_loop_done);
6070 
6071   Label L_check_1;
6072   subl(idx, 2);
6073   jcc(Assembler::negative, L_check_1);
6074 
6075   movq(yz_idx1, Address(y, idx, Address::times_4,  0));
6076   rorxq(yz_idx1, yz_idx1, 32);
6077   mulxq(tmp4, tmp3, yz_idx1); //  yz_idx1 * rdx -> tmp4:tmp3
6078   movq(yz_idx2, Address(z, idx, Address::times_4,  0));
6079   rorxq(yz_idx2, yz_idx2, 32);
6080 
6081   add2_with_carry(tmp4, tmp3, carry, yz_idx2);
6082 
6083   movl(Address(z, idx, Address::times_4,  4), tmp3);
6084   shrq(tmp3, 32);
6085   movl(Address(z, idx, Address::times_4,  0), tmp3);
6086   movq(carry, tmp4);
6087 
6088   bind (L_check_1);
6089   addl (idx, 0x2);
6090   andl (idx, 0x1);
6091   subl(idx, 1);
6092   jcc(Assembler::negative, L_post_third_loop_done);
6093   movl(tmp4, Address(y, idx, Address::times_4,  0));
6094   mulxq(carry2, tmp3, tmp4);  //  tmp4 * rdx -> carry2:tmp3
6095   movl(tmp4, Address(z, idx, Address::times_4,  0));
6096 
6097   add2_with_carry(carry2, tmp3, tmp4, carry);
6098 
6099   movl(Address(z, idx, Address::times_4,  0), tmp3);
6100   shrq(tmp3, 32);
6101 
6102   shlq(carry2, 32);
6103   orq(tmp3, carry2);
6104   movq(carry, tmp3);
6105 
6106   bind(L_post_third_loop_done);
6107 }
6108 
6109 /**
6110  * Code for BigInteger::multiplyToLen() intrinsic.
6111  *
6112  * rdi: x
6113  * rax: xlen
6114  * rsi: y
6115  * rcx: ylen
6116  * r8:  z
6117  * r11: zlen
6118  * r12: tmp1
6119  * r13: tmp2
6120  * r14: tmp3
6121  * r15: tmp4
6122  * rbx: tmp5
6123  *
6124  */
6125 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
6126                                      Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) {
6127   ShortBranchVerifier sbv(this);
6128   assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx);
6129 
6130   push(tmp1);
6131   push(tmp2);
6132   push(tmp3);
6133   push(tmp4);
6134   push(tmp5);
6135 
6136   push(xlen);
6137   push(zlen);
6138 
6139   const Register idx = tmp1;
6140   const Register kdx = tmp2;
6141   const Register xstart = tmp3;
6142 
6143   const Register y_idx = tmp4;
6144   const Register carry = tmp5;
6145   const Register product  = xlen;
6146   const Register x_xstart = zlen;  // reuse register
6147 
6148   // First Loop.
6149   //
6150   //  final static long LONG_MASK = 0xffffffffL;
6151   //  int xstart = xlen - 1;
6152   //  int ystart = ylen - 1;
6153   //  long carry = 0;
6154   //  for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6155   //    long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6156   //    z[kdx] = (int)product;
6157   //    carry = product >>> 32;
6158   //  }
6159   //  z[xstart] = (int)carry;
6160   //
6161 
6162   movl(idx, ylen);      // idx = ylen;
6163   movl(kdx, zlen);      // kdx = xlen+ylen;
6164   xorq(carry, carry);   // carry = 0;
6165 
6166   Label L_done;
6167 
6168   movl(xstart, xlen);
6169   decrementl(xstart);
6170   jcc(Assembler::negative, L_done);
6171 
6172   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6173 
6174   Label L_second_loop;
6175   testl(kdx, kdx);
6176   jcc(Assembler::zero, L_second_loop);
6177 
6178   Label L_carry;
6179   subl(kdx, 1);
6180   jcc(Assembler::zero, L_carry);
6181 
6182   movl(Address(z, kdx, Address::times_4,  0), carry);
6183   shrq(carry, 32);
6184   subl(kdx, 1);
6185 
6186   bind(L_carry);
6187   movl(Address(z, kdx, Address::times_4,  0), carry);
6188 
6189   // Second and third (nested) loops.
6190   //
6191   // for (int i = xstart-1; i >= 0; i--) { // Second loop
6192   //   carry = 0;
6193   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6194   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6195   //                    (z[k] & LONG_MASK) + carry;
6196   //     z[k] = (int)product;
6197   //     carry = product >>> 32;
6198   //   }
6199   //   z[i] = (int)carry;
6200   // }
6201   //
6202   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6203 
6204   const Register jdx = tmp1;
6205 
6206   bind(L_second_loop);
6207   xorl(carry, carry);    // carry = 0;
6208   movl(jdx, ylen);       // j = ystart+1
6209 
6210   subl(xstart, 1);       // i = xstart-1;
6211   jcc(Assembler::negative, L_done);
6212 
6213   push (z);
6214 
6215   Label L_last_x;
6216   lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j
6217   subl(xstart, 1);       // i = xstart-1;
6218   jcc(Assembler::negative, L_last_x);
6219 
6220   if (UseBMI2Instructions) {
6221     movq(rdx,  Address(x, xstart, Address::times_4,  0));
6222     rorxq(rdx, rdx, 32); // convert big-endian to little-endian
6223   } else {
6224     movq(x_xstart, Address(x, xstart, Address::times_4,  0));
6225     rorq(x_xstart, 32);  // convert big-endian to little-endian
6226   }
6227 
6228   Label L_third_loop_prologue;
6229   bind(L_third_loop_prologue);
6230 
6231   push (x);
6232   push (xstart);
6233   push (ylen);
6234 
6235 
6236   if (UseBMI2Instructions) {
6237     multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4);
6238   } else { // !UseBMI2Instructions
6239     multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6240   }
6241 
6242   pop(ylen);
6243   pop(xlen);
6244   pop(x);
6245   pop(z);
6246 
6247   movl(tmp3, xlen);
6248   addl(tmp3, 1);
6249   movl(Address(z, tmp3, Address::times_4,  0), carry);
6250   subl(tmp3, 1);
6251   jccb(Assembler::negative, L_done);
6252 
6253   shrq(carry, 32);
6254   movl(Address(z, tmp3, Address::times_4,  0), carry);
6255   jmp(L_second_loop);
6256 
6257   // Next infrequent code is moved outside loops.
6258   bind(L_last_x);
6259   if (UseBMI2Instructions) {
6260     movl(rdx, Address(x,  0));
6261   } else {
6262     movl(x_xstart, Address(x,  0));
6263   }
6264   jmp(L_third_loop_prologue);
6265 
6266   bind(L_done);
6267 
6268   pop(zlen);
6269   pop(xlen);
6270 
6271   pop(tmp5);
6272   pop(tmp4);
6273   pop(tmp3);
6274   pop(tmp2);
6275   pop(tmp1);
6276 }
6277 
6278 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale,
6279   Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){
6280   assert(UseSSE42Intrinsics, "SSE4.2 must be enabled.");
6281   Label VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP;
6282   Label VECTOR8_TAIL, VECTOR4_TAIL;
6283   Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL;
6284   Label SAME_TILL_END, DONE;
6285   Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL;
6286 
6287   //scale is in rcx in both Win64 and Unix
6288   ShortBranchVerifier sbv(this);
6289 
6290   shlq(length);
6291   xorq(result, result);
6292 
6293   if ((AVX3Threshold == 0) && (UseAVX > 2) &&
6294       VM_Version::supports_avx512vlbw()) {
6295     Label VECTOR64_LOOP, VECTOR64_NOT_EQUAL, VECTOR32_TAIL;
6296 
6297     cmpq(length, 64);
6298     jcc(Assembler::less, VECTOR32_TAIL);
6299 
6300     movq(tmp1, length);
6301     andq(tmp1, 0x3F);      // tail count
6302     andq(length, ~(0x3F)); //vector count
6303 
6304     bind(VECTOR64_LOOP);
6305     // AVX512 code to compare 64 byte vectors.
6306     evmovdqub(rymm0, Address(obja, result), false, Assembler::AVX_512bit);
6307     evpcmpeqb(k7, rymm0, Address(objb, result), Assembler::AVX_512bit);
6308     kortestql(k7, k7);
6309     jcc(Assembler::aboveEqual, VECTOR64_NOT_EQUAL);     // mismatch
6310     addq(result, 64);
6311     subq(length, 64);
6312     jccb(Assembler::notZero, VECTOR64_LOOP);
6313 
6314     //bind(VECTOR64_TAIL);
6315     testq(tmp1, tmp1);
6316     jcc(Assembler::zero, SAME_TILL_END);
6317 
6318     //bind(VECTOR64_TAIL);
6319     // AVX512 code to compare up to 63 byte vectors.
6320     mov64(tmp2, 0xFFFFFFFFFFFFFFFF);
6321     shlxq(tmp2, tmp2, tmp1);
6322     notq(tmp2);
6323     kmovql(k3, tmp2);
6324 
6325     evmovdqub(rymm0, k3, Address(obja, result), false, Assembler::AVX_512bit);
6326     evpcmpeqb(k7, k3, rymm0, Address(objb, result), Assembler::AVX_512bit);
6327 
6328     ktestql(k7, k3);
6329     jcc(Assembler::below, SAME_TILL_END);     // not mismatch
6330 
6331     bind(VECTOR64_NOT_EQUAL);
6332     kmovql(tmp1, k7);
6333     notq(tmp1);
6334     tzcntq(tmp1, tmp1);
6335     addq(result, tmp1);
6336     shrq(result);
6337     jmp(DONE);
6338     bind(VECTOR32_TAIL);
6339   }
6340 
6341   cmpq(length, 8);
6342   jcc(Assembler::equal, VECTOR8_LOOP);
6343   jcc(Assembler::less, VECTOR4_TAIL);
6344 
6345   if (UseAVX >= 2) {
6346     Label VECTOR16_TAIL, VECTOR32_LOOP;
6347 
6348     cmpq(length, 16);
6349     jcc(Assembler::equal, VECTOR16_LOOP);
6350     jcc(Assembler::less, VECTOR8_LOOP);
6351 
6352     cmpq(length, 32);
6353     jccb(Assembler::less, VECTOR16_TAIL);
6354 
6355     subq(length, 32);
6356     bind(VECTOR32_LOOP);
6357     vmovdqu(rymm0, Address(obja, result));
6358     vmovdqu(rymm1, Address(objb, result));
6359     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit);
6360     vptest(rymm2, rymm2);
6361     jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found
6362     addq(result, 32);
6363     subq(length, 32);
6364     jcc(Assembler::greaterEqual, VECTOR32_LOOP);
6365     addq(length, 32);
6366     jcc(Assembler::equal, SAME_TILL_END);
6367     //falling through if less than 32 bytes left //close the branch here.
6368 
6369     bind(VECTOR16_TAIL);
6370     cmpq(length, 16);
6371     jccb(Assembler::less, VECTOR8_TAIL);
6372     bind(VECTOR16_LOOP);
6373     movdqu(rymm0, Address(obja, result));
6374     movdqu(rymm1, Address(objb, result));
6375     vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit);
6376     ptest(rymm2, rymm2);
6377     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6378     addq(result, 16);
6379     subq(length, 16);
6380     jcc(Assembler::equal, SAME_TILL_END);
6381     //falling through if less than 16 bytes left
6382   } else {//regular intrinsics
6383 
6384     cmpq(length, 16);
6385     jccb(Assembler::less, VECTOR8_TAIL);
6386 
6387     subq(length, 16);
6388     bind(VECTOR16_LOOP);
6389     movdqu(rymm0, Address(obja, result));
6390     movdqu(rymm1, Address(objb, result));
6391     pxor(rymm0, rymm1);
6392     ptest(rymm0, rymm0);
6393     jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found
6394     addq(result, 16);
6395     subq(length, 16);
6396     jccb(Assembler::greaterEqual, VECTOR16_LOOP);
6397     addq(length, 16);
6398     jcc(Assembler::equal, SAME_TILL_END);
6399     //falling through if less than 16 bytes left
6400   }
6401 
6402   bind(VECTOR8_TAIL);
6403   cmpq(length, 8);
6404   jccb(Assembler::less, VECTOR4_TAIL);
6405   bind(VECTOR8_LOOP);
6406   movq(tmp1, Address(obja, result));
6407   movq(tmp2, Address(objb, result));
6408   xorq(tmp1, tmp2);
6409   testq(tmp1, tmp1);
6410   jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found
6411   addq(result, 8);
6412   subq(length, 8);
6413   jcc(Assembler::equal, SAME_TILL_END);
6414   //falling through if less than 8 bytes left
6415 
6416   bind(VECTOR4_TAIL);
6417   cmpq(length, 4);
6418   jccb(Assembler::less, BYTES_TAIL);
6419   bind(VECTOR4_LOOP);
6420   movl(tmp1, Address(obja, result));
6421   xorl(tmp1, Address(objb, result));
6422   testl(tmp1, tmp1);
6423   jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found
6424   addq(result, 4);
6425   subq(length, 4);
6426   jcc(Assembler::equal, SAME_TILL_END);
6427   //falling through if less than 4 bytes left
6428 
6429   bind(BYTES_TAIL);
6430   bind(BYTES_LOOP);
6431   load_unsigned_byte(tmp1, Address(obja, result));
6432   load_unsigned_byte(tmp2, Address(objb, result));
6433   xorl(tmp1, tmp2);
6434   testl(tmp1, tmp1);
6435   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6436   decq(length);
6437   jcc(Assembler::zero, SAME_TILL_END);
6438   incq(result);
6439   load_unsigned_byte(tmp1, Address(obja, result));
6440   load_unsigned_byte(tmp2, Address(objb, result));
6441   xorl(tmp1, tmp2);
6442   testl(tmp1, tmp1);
6443   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6444   decq(length);
6445   jcc(Assembler::zero, SAME_TILL_END);
6446   incq(result);
6447   load_unsigned_byte(tmp1, Address(obja, result));
6448   load_unsigned_byte(tmp2, Address(objb, result));
6449   xorl(tmp1, tmp2);
6450   testl(tmp1, tmp1);
6451   jcc(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found
6452   jmp(SAME_TILL_END);
6453 
6454   if (UseAVX >= 2) {
6455     bind(VECTOR32_NOT_EQUAL);
6456     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit);
6457     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit);
6458     vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit);
6459     vpmovmskb(tmp1, rymm0);
6460     bsfq(tmp1, tmp1);
6461     addq(result, tmp1);
6462     shrq(result);
6463     jmp(DONE);
6464   }
6465 
6466   bind(VECTOR16_NOT_EQUAL);
6467   if (UseAVX >= 2) {
6468     vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit);
6469     vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit);
6470     pxor(rymm0, rymm2);
6471   } else {
6472     pcmpeqb(rymm2, rymm2);
6473     pxor(rymm0, rymm1);
6474     pcmpeqb(rymm0, rymm1);
6475     pxor(rymm0, rymm2);
6476   }
6477   pmovmskb(tmp1, rymm0);
6478   bsfq(tmp1, tmp1);
6479   addq(result, tmp1);
6480   shrq(result);
6481   jmpb(DONE);
6482 
6483   bind(VECTOR8_NOT_EQUAL);
6484   bind(VECTOR4_NOT_EQUAL);
6485   bsfq(tmp1, tmp1);
6486   shrq(tmp1, 3);
6487   addq(result, tmp1);
6488   bind(BYTES_NOT_EQUAL);
6489   shrq(result);
6490   jmpb(DONE);
6491 
6492   bind(SAME_TILL_END);
6493   mov64(result, -1);
6494 
6495   bind(DONE);
6496 }
6497 
6498 //Helper functions for square_to_len()
6499 
6500 /**
6501  * Store the squares of x[], right shifted one bit (divided by 2) into z[]
6502  * Preserves x and z and modifies rest of the registers.
6503  */
6504 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6505   // Perform square and right shift by 1
6506   // Handle odd xlen case first, then for even xlen do the following
6507   // jlong carry = 0;
6508   // for (int j=0, i=0; j < xlen; j+=2, i+=4) {
6509   //     huge_128 product = x[j:j+1] * x[j:j+1];
6510   //     z[i:i+1] = (carry << 63) | (jlong)(product >>> 65);
6511   //     z[i+2:i+3] = (jlong)(product >>> 1);
6512   //     carry = (jlong)product;
6513   // }
6514 
6515   xorq(tmp5, tmp5);     // carry
6516   xorq(rdxReg, rdxReg);
6517   xorl(tmp1, tmp1);     // index for x
6518   xorl(tmp4, tmp4);     // index for z
6519 
6520   Label L_first_loop, L_first_loop_exit;
6521 
6522   testl(xlen, 1);
6523   jccb(Assembler::zero, L_first_loop); //jump if xlen is even
6524 
6525   // Square and right shift by 1 the odd element using 32 bit multiply
6526   movl(raxReg, Address(x, tmp1, Address::times_4, 0));
6527   imulq(raxReg, raxReg);
6528   shrq(raxReg, 1);
6529   adcq(tmp5, 0);
6530   movq(Address(z, tmp4, Address::times_4, 0), raxReg);
6531   incrementl(tmp1);
6532   addl(tmp4, 2);
6533 
6534   // Square and  right shift by 1 the rest using 64 bit multiply
6535   bind(L_first_loop);
6536   cmpptr(tmp1, xlen);
6537   jccb(Assembler::equal, L_first_loop_exit);
6538 
6539   // Square
6540   movq(raxReg, Address(x, tmp1, Address::times_4,  0));
6541   rorq(raxReg, 32);    // convert big-endian to little-endian
6542   mulq(raxReg);        // 64-bit multiply rax * rax -> rdx:rax
6543 
6544   // Right shift by 1 and save carry
6545   shrq(tmp5, 1);       // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1
6546   rcrq(rdxReg, 1);
6547   rcrq(raxReg, 1);
6548   adcq(tmp5, 0);
6549 
6550   // Store result in z
6551   movq(Address(z, tmp4, Address::times_4, 0), rdxReg);
6552   movq(Address(z, tmp4, Address::times_4, 8), raxReg);
6553 
6554   // Update indices for x and z
6555   addl(tmp1, 2);
6556   addl(tmp4, 4);
6557   jmp(L_first_loop);
6558 
6559   bind(L_first_loop_exit);
6560 }
6561 
6562 
6563 /**
6564  * Perform the following multiply add operation using BMI2 instructions
6565  * carry:sum = sum + op1*op2 + carry
6566  * op2 should be in rdx
6567  * op2 is preserved, all other registers are modified
6568  */
6569 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) {
6570   // assert op2 is rdx
6571   mulxq(tmp2, op1, op1);  //  op1 * op2 -> tmp2:op1
6572   addq(sum, carry);
6573   adcq(tmp2, 0);
6574   addq(sum, op1);
6575   adcq(tmp2, 0);
6576   movq(carry, tmp2);
6577 }
6578 
6579 /**
6580  * Perform the following multiply add operation:
6581  * carry:sum = sum + op1*op2 + carry
6582  * Preserves op1, op2 and modifies rest of registers
6583  */
6584 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) {
6585   // rdx:rax = op1 * op2
6586   movq(raxReg, op2);
6587   mulq(op1);
6588 
6589   //  rdx:rax = sum + carry + rdx:rax
6590   addq(sum, carry);
6591   adcq(rdxReg, 0);
6592   addq(sum, raxReg);
6593   adcq(rdxReg, 0);
6594 
6595   // carry:sum = rdx:sum
6596   movq(carry, rdxReg);
6597 }
6598 
6599 /**
6600  * Add 64 bit long carry into z[] with carry propagation.
6601  * Preserves z and carry register values and modifies rest of registers.
6602  *
6603  */
6604 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) {
6605   Label L_fourth_loop, L_fourth_loop_exit;
6606 
6607   movl(tmp1, 1);
6608   subl(zlen, 2);
6609   addq(Address(z, zlen, Address::times_4, 0), carry);
6610 
6611   bind(L_fourth_loop);
6612   jccb(Assembler::carryClear, L_fourth_loop_exit);
6613   subl(zlen, 2);
6614   jccb(Assembler::negative, L_fourth_loop_exit);
6615   addq(Address(z, zlen, Address::times_4, 0), tmp1);
6616   jmp(L_fourth_loop);
6617   bind(L_fourth_loop_exit);
6618 }
6619 
6620 /**
6621  * Shift z[] left by 1 bit.
6622  * Preserves x, len, z and zlen registers and modifies rest of the registers.
6623  *
6624  */
6625 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) {
6626 
6627   Label L_fifth_loop, L_fifth_loop_exit;
6628 
6629   // Fifth loop
6630   // Perform primitiveLeftShift(z, zlen, 1)
6631 
6632   const Register prev_carry = tmp1;
6633   const Register new_carry = tmp4;
6634   const Register value = tmp2;
6635   const Register zidx = tmp3;
6636 
6637   // int zidx, carry;
6638   // long value;
6639   // carry = 0;
6640   // for (zidx = zlen-2; zidx >=0; zidx -= 2) {
6641   //    (carry:value)  = (z[i] << 1) | carry ;
6642   //    z[i] = value;
6643   // }
6644 
6645   movl(zidx, zlen);
6646   xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register
6647 
6648   bind(L_fifth_loop);
6649   decl(zidx);  // Use decl to preserve carry flag
6650   decl(zidx);
6651   jccb(Assembler::negative, L_fifth_loop_exit);
6652 
6653   if (UseBMI2Instructions) {
6654      movq(value, Address(z, zidx, Address::times_4, 0));
6655      rclq(value, 1);
6656      rorxq(value, value, 32);
6657      movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6658   }
6659   else {
6660     // clear new_carry
6661     xorl(new_carry, new_carry);
6662 
6663     // Shift z[i] by 1, or in previous carry and save new carry
6664     movq(value, Address(z, zidx, Address::times_4, 0));
6665     shlq(value, 1);
6666     adcl(new_carry, 0);
6667 
6668     orq(value, prev_carry);
6669     rorq(value, 0x20);
6670     movq(Address(z, zidx, Address::times_4,  0), value);  // Store back in big endian form
6671 
6672     // Set previous carry = new carry
6673     movl(prev_carry, new_carry);
6674   }
6675   jmp(L_fifth_loop);
6676 
6677   bind(L_fifth_loop_exit);
6678 }
6679 
6680 
6681 /**
6682  * Code for BigInteger::squareToLen() intrinsic
6683  *
6684  * rdi: x
6685  * rsi: len
6686  * r8:  z
6687  * rcx: zlen
6688  * r12: tmp1
6689  * r13: tmp2
6690  * r14: tmp3
6691  * r15: tmp4
6692  * rbx: tmp5
6693  *
6694  */
6695 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6696 
6697   Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, L_last_x, L_multiply;
6698   push(tmp1);
6699   push(tmp2);
6700   push(tmp3);
6701   push(tmp4);
6702   push(tmp5);
6703 
6704   // First loop
6705   // Store the squares, right shifted one bit (i.e., divided by 2).
6706   square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg);
6707 
6708   // Add in off-diagonal sums.
6709   //
6710   // Second, third (nested) and fourth loops.
6711   // zlen +=2;
6712   // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) {
6713   //    carry = 0;
6714   //    long op2 = x[xidx:xidx+1];
6715   //    for (int j=xidx-2,k=zidx; j >= 0; j-=2) {
6716   //       k -= 2;
6717   //       long op1 = x[j:j+1];
6718   //       long sum = z[k:k+1];
6719   //       carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs);
6720   //       z[k:k+1] = sum;
6721   //    }
6722   //    add_one_64(z, k, carry, tmp_regs);
6723   // }
6724 
6725   const Register carry = tmp5;
6726   const Register sum = tmp3;
6727   const Register op1 = tmp4;
6728   Register op2 = tmp2;
6729 
6730   push(zlen);
6731   push(len);
6732   addl(zlen,2);
6733   bind(L_second_loop);
6734   xorq(carry, carry);
6735   subl(zlen, 4);
6736   subl(len, 2);
6737   push(zlen);
6738   push(len);
6739   cmpl(len, 0);
6740   jccb(Assembler::lessEqual, L_second_loop_exit);
6741 
6742   // Multiply an array by one 64 bit long.
6743   if (UseBMI2Instructions) {
6744     op2 = rdxReg;
6745     movq(op2, Address(x, len, Address::times_4,  0));
6746     rorxq(op2, op2, 32);
6747   }
6748   else {
6749     movq(op2, Address(x, len, Address::times_4,  0));
6750     rorq(op2, 32);
6751   }
6752 
6753   bind(L_third_loop);
6754   decrementl(len);
6755   jccb(Assembler::negative, L_third_loop_exit);
6756   decrementl(len);
6757   jccb(Assembler::negative, L_last_x);
6758 
6759   movq(op1, Address(x, len, Address::times_4,  0));
6760   rorq(op1, 32);
6761 
6762   bind(L_multiply);
6763   subl(zlen, 2);
6764   movq(sum, Address(z, zlen, Address::times_4,  0));
6765 
6766   // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry.
6767   if (UseBMI2Instructions) {
6768     multiply_add_64_bmi2(sum, op1, op2, carry, tmp2);
6769   }
6770   else {
6771     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6772   }
6773 
6774   movq(Address(z, zlen, Address::times_4, 0), sum);
6775 
6776   jmp(L_third_loop);
6777   bind(L_third_loop_exit);
6778 
6779   // Fourth loop
6780   // Add 64 bit long carry into z with carry propagation.
6781   // Uses offsetted zlen.
6782   add_one_64(z, zlen, carry, tmp1);
6783 
6784   pop(len);
6785   pop(zlen);
6786   jmp(L_second_loop);
6787 
6788   // Next infrequent code is moved outside loops.
6789   bind(L_last_x);
6790   movl(op1, Address(x, 0));
6791   jmp(L_multiply);
6792 
6793   bind(L_second_loop_exit);
6794   pop(len);
6795   pop(zlen);
6796   pop(len);
6797   pop(zlen);
6798 
6799   // Fifth loop
6800   // Shift z left 1 bit.
6801   lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4);
6802 
6803   // z[zlen-1] |= x[len-1] & 1;
6804   movl(tmp3, Address(x, len, Address::times_4, -4));
6805   andl(tmp3, 1);
6806   orl(Address(z, zlen, Address::times_4,  -4), tmp3);
6807 
6808   pop(tmp5);
6809   pop(tmp4);
6810   pop(tmp3);
6811   pop(tmp2);
6812   pop(tmp1);
6813 }
6814 
6815 /**
6816  * Helper function for mul_add()
6817  * Multiply the in[] by int k and add to out[] starting at offset offs using
6818  * 128 bit by 32 bit multiply and return the carry in tmp5.
6819  * Only quad int aligned length of in[] is operated on in this function.
6820  * k is in rdxReg for BMI2Instructions, for others it is in tmp2.
6821  * This function preserves out, in and k registers.
6822  * len and offset point to the appropriate index in "in" & "out" correspondingly
6823  * tmp5 has the carry.
6824  * other registers are temporary and are modified.
6825  *
6826  */
6827 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in,
6828   Register offset, Register len, Register tmp1, Register tmp2, Register tmp3,
6829   Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6830 
6831   Label L_first_loop, L_first_loop_exit;
6832 
6833   movl(tmp1, len);
6834   shrl(tmp1, 2);
6835 
6836   bind(L_first_loop);
6837   subl(tmp1, 1);
6838   jccb(Assembler::negative, L_first_loop_exit);
6839 
6840   subl(len, 4);
6841   subl(offset, 4);
6842 
6843   Register op2 = tmp2;
6844   const Register sum = tmp3;
6845   const Register op1 = tmp4;
6846   const Register carry = tmp5;
6847 
6848   if (UseBMI2Instructions) {
6849     op2 = rdxReg;
6850   }
6851 
6852   movq(op1, Address(in, len, Address::times_4,  8));
6853   rorq(op1, 32);
6854   movq(sum, Address(out, offset, Address::times_4,  8));
6855   rorq(sum, 32);
6856   if (UseBMI2Instructions) {
6857     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6858   }
6859   else {
6860     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6861   }
6862   // Store back in big endian from little endian
6863   rorq(sum, 0x20);
6864   movq(Address(out, offset, Address::times_4,  8), sum);
6865 
6866   movq(op1, Address(in, len, Address::times_4,  0));
6867   rorq(op1, 32);
6868   movq(sum, Address(out, offset, Address::times_4,  0));
6869   rorq(sum, 32);
6870   if (UseBMI2Instructions) {
6871     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6872   }
6873   else {
6874     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6875   }
6876   // Store back in big endian from little endian
6877   rorq(sum, 0x20);
6878   movq(Address(out, offset, Address::times_4,  0), sum);
6879 
6880   jmp(L_first_loop);
6881   bind(L_first_loop_exit);
6882 }
6883 
6884 /**
6885  * Code for BigInteger::mulAdd() intrinsic
6886  *
6887  * rdi: out
6888  * rsi: in
6889  * r11: offs (out.length - offset)
6890  * rcx: len
6891  * r8:  k
6892  * r12: tmp1
6893  * r13: tmp2
6894  * r14: tmp3
6895  * r15: tmp4
6896  * rbx: tmp5
6897  * Multiply the in[] by word k and add to out[], return the carry in rax
6898  */
6899 void MacroAssembler::mul_add(Register out, Register in, Register offs,
6900    Register len, Register k, Register tmp1, Register tmp2, Register tmp3,
6901    Register tmp4, Register tmp5, Register rdxReg, Register raxReg) {
6902 
6903   Label L_carry, L_last_in, L_done;
6904 
6905 // carry = 0;
6906 // for (int j=len-1; j >= 0; j--) {
6907 //    long product = (in[j] & LONG_MASK) * kLong +
6908 //                   (out[offs] & LONG_MASK) + carry;
6909 //    out[offs--] = (int)product;
6910 //    carry = product >>> 32;
6911 // }
6912 //
6913   push(tmp1);
6914   push(tmp2);
6915   push(tmp3);
6916   push(tmp4);
6917   push(tmp5);
6918 
6919   Register op2 = tmp2;
6920   const Register sum = tmp3;
6921   const Register op1 = tmp4;
6922   const Register carry =  tmp5;
6923 
6924   if (UseBMI2Instructions) {
6925     op2 = rdxReg;
6926     movl(op2, k);
6927   }
6928   else {
6929     movl(op2, k);
6930   }
6931 
6932   xorq(carry, carry);
6933 
6934   //First loop
6935 
6936   //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply
6937   //The carry is in tmp5
6938   mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg);
6939 
6940   //Multiply the trailing in[] entry using 64 bit by 32 bit, if any
6941   decrementl(len);
6942   jccb(Assembler::negative, L_carry);
6943   decrementl(len);
6944   jccb(Assembler::negative, L_last_in);
6945 
6946   movq(op1, Address(in, len, Address::times_4,  0));
6947   rorq(op1, 32);
6948 
6949   subl(offs, 2);
6950   movq(sum, Address(out, offs, Address::times_4,  0));
6951   rorq(sum, 32);
6952 
6953   if (UseBMI2Instructions) {
6954     multiply_add_64_bmi2(sum, op1, op2, carry, raxReg);
6955   }
6956   else {
6957     multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg);
6958   }
6959 
6960   // Store back in big endian from little endian
6961   rorq(sum, 0x20);
6962   movq(Address(out, offs, Address::times_4,  0), sum);
6963 
6964   testl(len, len);
6965   jccb(Assembler::zero, L_carry);
6966 
6967   //Multiply the last in[] entry, if any
6968   bind(L_last_in);
6969   movl(op1, Address(in, 0));
6970   movl(sum, Address(out, offs, Address::times_4,  -4));
6971 
6972   movl(raxReg, k);
6973   mull(op1); //tmp4 * eax -> edx:eax
6974   addl(sum, carry);
6975   adcl(rdxReg, 0);
6976   addl(sum, raxReg);
6977   adcl(rdxReg, 0);
6978   movl(carry, rdxReg);
6979 
6980   movl(Address(out, offs, Address::times_4,  -4), sum);
6981 
6982   bind(L_carry);
6983   //return tmp5/carry as carry in rax
6984   movl(rax, carry);
6985 
6986   bind(L_done);
6987   pop(tmp5);
6988   pop(tmp4);
6989   pop(tmp3);
6990   pop(tmp2);
6991   pop(tmp1);
6992 }
6993 #endif
6994 
6995 /**
6996  * Emits code to update CRC-32 with a byte value according to constants in table
6997  *
6998  * @param [in,out]crc   Register containing the crc.
6999  * @param [in]val       Register containing the byte to fold into the CRC.
7000  * @param [in]table     Register containing the table of crc constants.
7001  *
7002  * uint32_t crc;
7003  * val = crc_table[(val ^ crc) & 0xFF];
7004  * crc = val ^ (crc >> 8);
7005  *
7006  */
7007 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
7008   xorl(val, crc);
7009   andl(val, 0xFF);
7010   shrl(crc, 8); // unsigned shift
7011   xorl(crc, Address(table, val, Address::times_4, 0));
7012 }
7013 
7014 /**
7015  * Fold 128-bit data chunk
7016  */
7017 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) {
7018   if (UseAVX > 0) {
7019     vpclmulhdq(xtmp, xK, xcrc); // [123:64]
7020     vpclmulldq(xcrc, xK, xcrc); // [63:0]
7021     vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */);
7022     pxor(xcrc, xtmp);
7023   } else {
7024     movdqa(xtmp, xcrc);
7025     pclmulhdq(xtmp, xK);   // [123:64]
7026     pclmulldq(xcrc, xK);   // [63:0]
7027     pxor(xcrc, xtmp);
7028     movdqu(xtmp, Address(buf, offset));
7029     pxor(xcrc, xtmp);
7030   }
7031 }
7032 
7033 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) {
7034   if (UseAVX > 0) {
7035     vpclmulhdq(xtmp, xK, xcrc);
7036     vpclmulldq(xcrc, xK, xcrc);
7037     pxor(xcrc, xbuf);
7038     pxor(xcrc, xtmp);
7039   } else {
7040     movdqa(xtmp, xcrc);
7041     pclmulhdq(xtmp, xK);
7042     pclmulldq(xcrc, xK);
7043     pxor(xcrc, xbuf);
7044     pxor(xcrc, xtmp);
7045   }
7046 }
7047 
7048 /**
7049  * 8-bit folds to compute 32-bit CRC
7050  *
7051  * uint64_t xcrc;
7052  * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8);
7053  */
7054 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) {
7055   movdl(tmp, xcrc);
7056   andl(tmp, 0xFF);
7057   movdl(xtmp, Address(table, tmp, Address::times_4, 0));
7058   psrldq(xcrc, 1); // unsigned shift one byte
7059   pxor(xcrc, xtmp);
7060 }
7061 
7062 /**
7063  * uint32_t crc;
7064  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
7065  */
7066 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
7067   movl(tmp, crc);
7068   andl(tmp, 0xFF);
7069   shrl(crc, 8);
7070   xorl(crc, Address(table, tmp, Address::times_4, 0));
7071 }
7072 
7073 /**
7074  * @param crc   register containing existing CRC (32-bit)
7075  * @param buf   register pointing to input byte buffer (byte*)
7076  * @param len   register containing number of bytes
7077  * @param table register that will contain address of CRC table
7078  * @param tmp   scratch register
7079  */
7080 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) {
7081   assert_different_registers(crc, buf, len, table, tmp, rax);
7082 
7083   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7084   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7085 
7086   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7087   // context for the registers used, where all instructions below are using 128-bit mode
7088   // On EVEX without VL and BW, these instructions will all be AVX.
7089   lea(table, ExternalAddress(StubRoutines::crc_table_addr()));
7090   notl(crc); // ~crc
7091   cmpl(len, 16);
7092   jcc(Assembler::less, L_tail);
7093 
7094   // Align buffer to 16 bytes
7095   movl(tmp, buf);
7096   andl(tmp, 0xF);
7097   jccb(Assembler::zero, L_aligned);
7098   subl(tmp,  16);
7099   addl(len, tmp);
7100 
7101   align(4);
7102   BIND(L_align_loop);
7103   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7104   update_byte_crc32(crc, rax, table);
7105   increment(buf);
7106   incrementl(tmp);
7107   jccb(Assembler::less, L_align_loop);
7108 
7109   BIND(L_aligned);
7110   movl(tmp, len); // save
7111   shrl(len, 4);
7112   jcc(Assembler::zero, L_tail_restore);
7113 
7114   // Fold crc into first bytes of vector
7115   movdqa(xmm1, Address(buf, 0));
7116   movdl(rax, xmm1);
7117   xorl(crc, rax);
7118   if (VM_Version::supports_sse4_1()) {
7119     pinsrd(xmm1, crc, 0);
7120   } else {
7121     pinsrw(xmm1, crc, 0);
7122     shrl(crc, 16);
7123     pinsrw(xmm1, crc, 1);
7124   }
7125   addptr(buf, 16);
7126   subl(len, 4); // len > 0
7127   jcc(Assembler::less, L_fold_tail);
7128 
7129   movdqa(xmm2, Address(buf,  0));
7130   movdqa(xmm3, Address(buf, 16));
7131   movdqa(xmm4, Address(buf, 32));
7132   addptr(buf, 48);
7133   subl(len, 3);
7134   jcc(Assembler::lessEqual, L_fold_512b);
7135 
7136   // Fold total 512 bits of polynomial on each iteration,
7137   // 128 bits per each of 4 parallel streams.
7138   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32));
7139 
7140   align32();
7141   BIND(L_fold_512b_loop);
7142   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7143   fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16);
7144   fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32);
7145   fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48);
7146   addptr(buf, 64);
7147   subl(len, 4);
7148   jcc(Assembler::greater, L_fold_512b_loop);
7149 
7150   // Fold 512 bits to 128 bits.
7151   BIND(L_fold_512b);
7152   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7153   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2);
7154   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3);
7155   fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4);
7156 
7157   // Fold the rest of 128 bits data chunks
7158   BIND(L_fold_tail);
7159   addl(len, 3);
7160   jccb(Assembler::lessEqual, L_fold_128b);
7161   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16));
7162 
7163   BIND(L_fold_tail_loop);
7164   fold_128bit_crc32(xmm1, xmm0, xmm5, buf,  0);
7165   addptr(buf, 16);
7166   decrementl(len);
7167   jccb(Assembler::greater, L_fold_tail_loop);
7168 
7169   // Fold 128 bits in xmm1 down into 32 bits in crc register.
7170   BIND(L_fold_128b);
7171   movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr()));
7172   if (UseAVX > 0) {
7173     vpclmulqdq(xmm2, xmm0, xmm1, 0x1);
7174     vpand(xmm3, xmm0, xmm2, 0 /* vector_len */);
7175     vpclmulqdq(xmm0, xmm0, xmm3, 0x1);
7176   } else {
7177     movdqa(xmm2, xmm0);
7178     pclmulqdq(xmm2, xmm1, 0x1);
7179     movdqa(xmm3, xmm0);
7180     pand(xmm3, xmm2);
7181     pclmulqdq(xmm0, xmm3, 0x1);
7182   }
7183   psrldq(xmm1, 8);
7184   psrldq(xmm2, 4);
7185   pxor(xmm0, xmm1);
7186   pxor(xmm0, xmm2);
7187 
7188   // 8 8-bit folds to compute 32-bit CRC.
7189   for (int j = 0; j < 4; j++) {
7190     fold_8bit_crc32(xmm0, table, xmm1, rax);
7191   }
7192   movdl(crc, xmm0); // mov 32 bits to general register
7193   for (int j = 0; j < 4; j++) {
7194     fold_8bit_crc32(crc, table, rax);
7195   }
7196 
7197   BIND(L_tail_restore);
7198   movl(len, tmp); // restore
7199   BIND(L_tail);
7200   andl(len, 0xf);
7201   jccb(Assembler::zero, L_exit);
7202 
7203   // Fold the rest of bytes
7204   align(4);
7205   BIND(L_tail_loop);
7206   movsbl(rax, Address(buf, 0)); // load byte with sign extension
7207   update_byte_crc32(crc, rax, table);
7208   increment(buf);
7209   decrementl(len);
7210   jccb(Assembler::greater, L_tail_loop);
7211 
7212   BIND(L_exit);
7213   notl(crc); // ~c
7214 }
7215 
7216 #ifdef _LP64
7217 // Helper function for AVX 512 CRC32
7218 // Fold 512-bit data chunks
7219 void MacroAssembler::fold512bit_crc32_avx512(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf,
7220                                              Register pos, int offset) {
7221   evmovdquq(xmm3, Address(buf, pos, Address::times_1, offset), Assembler::AVX_512bit);
7222   evpclmulqdq(xtmp, xcrc, xK, 0x10, Assembler::AVX_512bit); // [123:64]
7223   evpclmulqdq(xmm2, xcrc, xK, 0x01, Assembler::AVX_512bit); // [63:0]
7224   evpxorq(xcrc, xtmp, xmm2, Assembler::AVX_512bit /* vector_len */);
7225   evpxorq(xcrc, xcrc, xmm3, Assembler::AVX_512bit /* vector_len */);
7226 }
7227 
7228 // Helper function for AVX 512 CRC32
7229 // Compute CRC32 for < 256B buffers
7230 void MacroAssembler::kernel_crc32_avx512_256B(Register crc, Register buf, Register len, Register table, Register pos,
7231                                               Register tmp1, Register tmp2, Label& L_barrett, Label& L_16B_reduction_loop,
7232                                               Label& L_get_last_two_xmms, Label& L_128_done, Label& L_cleanup) {
7233 
7234   Label L_less_than_32, L_exact_16_left, L_less_than_16_left;
7235   Label L_less_than_8_left, L_less_than_4_left, L_less_than_2_left, L_zero_left;
7236   Label L_only_less_than_4, L_only_less_than_3, L_only_less_than_2;
7237 
7238   // check if there is enough buffer to be able to fold 16B at a time
7239   cmpl(len, 32);
7240   jcc(Assembler::less, L_less_than_32);
7241 
7242   // if there is, load the constants
7243   movdqu(xmm10, Address(table, 1 * 16));    //rk1 and rk2 in xmm10
7244   movdl(xmm0, crc);                        // get the initial crc value
7245   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7246   pxor(xmm7, xmm0);
7247 
7248   // update the buffer pointer
7249   addl(pos, 16);
7250   //update the counter.subtract 32 instead of 16 to save one instruction from the loop
7251   subl(len, 32);
7252   jmp(L_16B_reduction_loop);
7253 
7254   bind(L_less_than_32);
7255   //mov initial crc to the return value. this is necessary for zero - length buffers.
7256   movl(rax, crc);
7257   testl(len, len);
7258   jcc(Assembler::equal, L_cleanup);
7259 
7260   movdl(xmm0, crc);                        //get the initial crc value
7261 
7262   cmpl(len, 16);
7263   jcc(Assembler::equal, L_exact_16_left);
7264   jcc(Assembler::less, L_less_than_16_left);
7265 
7266   movdqu(xmm7, Address(buf, pos, Address::times_1, 0 * 16)); //load the plaintext
7267   pxor(xmm7, xmm0);                       //xor the initial crc value
7268   addl(pos, 16);
7269   subl(len, 16);
7270   movdqu(xmm10, Address(table, 1 * 16));    // rk1 and rk2 in xmm10
7271   jmp(L_get_last_two_xmms);
7272 
7273   bind(L_less_than_16_left);
7274   //use stack space to load data less than 16 bytes, zero - out the 16B in memory first.
7275   pxor(xmm1, xmm1);
7276   movptr(tmp1, rsp);
7277   movdqu(Address(tmp1, 0 * 16), xmm1);
7278 
7279   cmpl(len, 4);
7280   jcc(Assembler::less, L_only_less_than_4);
7281 
7282   //backup the counter value
7283   movl(tmp2, len);
7284   cmpl(len, 8);
7285   jcc(Assembler::less, L_less_than_8_left);
7286 
7287   //load 8 Bytes
7288   movq(rax, Address(buf, pos, Address::times_1, 0 * 16));
7289   movq(Address(tmp1, 0 * 16), rax);
7290   addptr(tmp1, 8);
7291   subl(len, 8);
7292   addl(pos, 8);
7293 
7294   bind(L_less_than_8_left);
7295   cmpl(len, 4);
7296   jcc(Assembler::less, L_less_than_4_left);
7297 
7298   //load 4 Bytes
7299   movl(rax, Address(buf, pos, Address::times_1, 0));
7300   movl(Address(tmp1, 0 * 16), rax);
7301   addptr(tmp1, 4);
7302   subl(len, 4);
7303   addl(pos, 4);
7304 
7305   bind(L_less_than_4_left);
7306   cmpl(len, 2);
7307   jcc(Assembler::less, L_less_than_2_left);
7308 
7309   // load 2 Bytes
7310   movw(rax, Address(buf, pos, Address::times_1, 0));
7311   movl(Address(tmp1, 0 * 16), rax);
7312   addptr(tmp1, 2);
7313   subl(len, 2);
7314   addl(pos, 2);
7315 
7316   bind(L_less_than_2_left);
7317   cmpl(len, 1);
7318   jcc(Assembler::less, L_zero_left);
7319 
7320   // load 1 Byte
7321   movb(rax, Address(buf, pos, Address::times_1, 0));
7322   movb(Address(tmp1, 0 * 16), rax);
7323 
7324   bind(L_zero_left);
7325   movdqu(xmm7, Address(rsp, 0));
7326   pxor(xmm7, xmm0);                       //xor the initial crc value
7327 
7328   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7329   movdqu(xmm0, Address(rax, tmp2));
7330   pshufb(xmm7, xmm0);
7331   jmp(L_128_done);
7332 
7333   bind(L_exact_16_left);
7334   movdqu(xmm7, Address(buf, pos, Address::times_1, 0));
7335   pxor(xmm7, xmm0);                       //xor the initial crc value
7336   jmp(L_128_done);
7337 
7338   bind(L_only_less_than_4);
7339   cmpl(len, 3);
7340   jcc(Assembler::less, L_only_less_than_3);
7341 
7342   // load 3 Bytes
7343   movb(rax, Address(buf, pos, Address::times_1, 0));
7344   movb(Address(tmp1, 0), rax);
7345 
7346   movb(rax, Address(buf, pos, Address::times_1, 1));
7347   movb(Address(tmp1, 1), rax);
7348 
7349   movb(rax, Address(buf, pos, Address::times_1, 2));
7350   movb(Address(tmp1, 2), rax);
7351 
7352   movdqu(xmm7, Address(rsp, 0));
7353   pxor(xmm7, xmm0);                     //xor the initial crc value
7354 
7355   pslldq(xmm7, 0x5);
7356   jmp(L_barrett);
7357   bind(L_only_less_than_3);
7358   cmpl(len, 2);
7359   jcc(Assembler::less, L_only_less_than_2);
7360 
7361   // load 2 Bytes
7362   movb(rax, Address(buf, pos, Address::times_1, 0));
7363   movb(Address(tmp1, 0), rax);
7364 
7365   movb(rax, Address(buf, pos, Address::times_1, 1));
7366   movb(Address(tmp1, 1), rax);
7367 
7368   movdqu(xmm7, Address(rsp, 0));
7369   pxor(xmm7, xmm0);                     //xor the initial crc value
7370 
7371   pslldq(xmm7, 0x6);
7372   jmp(L_barrett);
7373 
7374   bind(L_only_less_than_2);
7375   //load 1 Byte
7376   movb(rax, Address(buf, pos, Address::times_1, 0));
7377   movb(Address(tmp1, 0), rax);
7378 
7379   movdqu(xmm7, Address(rsp, 0));
7380   pxor(xmm7, xmm0);                     //xor the initial crc value
7381 
7382   pslldq(xmm7, 0x7);
7383 }
7384 
7385 /**
7386 * Compute CRC32 using AVX512 instructions
7387 * param crc   register containing existing CRC (32-bit)
7388 * param buf   register pointing to input byte buffer (byte*)
7389 * param len   register containing number of bytes
7390 * param table address of crc or crc32c table
7391 * param tmp1  scratch register
7392 * param tmp2  scratch register
7393 * return rax  result register
7394 *
7395 * This routine is identical for crc32c with the exception of the precomputed constant
7396 * table which will be passed as the table argument.  The calculation steps are
7397 * the same for both variants.
7398 */
7399 void MacroAssembler::kernel_crc32_avx512(Register crc, Register buf, Register len, Register table, Register tmp1, Register tmp2) {
7400   assert_different_registers(crc, buf, len, table, tmp1, tmp2, rax, r12);
7401 
7402   Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned;
7403   Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop;
7404   Label L_less_than_256, L_fold_128_B_loop, L_fold_256_B_loop;
7405   Label L_fold_128_B_register, L_final_reduction_for_128, L_16B_reduction_loop;
7406   Label L_128_done, L_get_last_two_xmms, L_barrett, L_cleanup;
7407 
7408   const Register pos = r12;
7409   push(r12);
7410   subptr(rsp, 16 * 2 + 8);
7411 
7412   // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge
7413   // context for the registers used, where all instructions below are using 128-bit mode
7414   // On EVEX without VL and BW, these instructions will all be AVX.
7415   movl(pos, 0);
7416 
7417   // check if smaller than 256B
7418   cmpl(len, 256);
7419   jcc(Assembler::less, L_less_than_256);
7420 
7421   // load the initial crc value
7422   movdl(xmm10, crc);
7423 
7424   // receive the initial 64B data, xor the initial crc value
7425   evmovdquq(xmm0, Address(buf, pos, Address::times_1, 0 * 64), Assembler::AVX_512bit);
7426   evmovdquq(xmm4, Address(buf, pos, Address::times_1, 1 * 64), Assembler::AVX_512bit);
7427   evpxorq(xmm0, xmm0, xmm10, Assembler::AVX_512bit);
7428   evbroadcasti32x4(xmm10, Address(table, 2 * 16), Assembler::AVX_512bit); //zmm10 has rk3 and rk4
7429 
7430   subl(len, 256);
7431   cmpl(len, 256);
7432   jcc(Assembler::less, L_fold_128_B_loop);
7433 
7434   evmovdquq(xmm7, Address(buf, pos, Address::times_1, 2 * 64), Assembler::AVX_512bit);
7435   evmovdquq(xmm8, Address(buf, pos, Address::times_1, 3 * 64), Assembler::AVX_512bit);
7436   evbroadcasti32x4(xmm16, Address(table, 0 * 16), Assembler::AVX_512bit); //zmm16 has rk-1 and rk-2
7437   subl(len, 256);
7438 
7439   bind(L_fold_256_B_loop);
7440   addl(pos, 256);
7441   fold512bit_crc32_avx512(xmm0, xmm16, xmm1, buf, pos, 0 * 64);
7442   fold512bit_crc32_avx512(xmm4, xmm16, xmm1, buf, pos, 1 * 64);
7443   fold512bit_crc32_avx512(xmm7, xmm16, xmm1, buf, pos, 2 * 64);
7444   fold512bit_crc32_avx512(xmm8, xmm16, xmm1, buf, pos, 3 * 64);
7445 
7446   subl(len, 256);
7447   jcc(Assembler::greaterEqual, L_fold_256_B_loop);
7448 
7449   // Fold 256 into 128
7450   addl(pos, 256);
7451   evpclmulqdq(xmm1, xmm0, xmm10, 0x01, Assembler::AVX_512bit);
7452   evpclmulqdq(xmm2, xmm0, xmm10, 0x10, Assembler::AVX_512bit);
7453   vpternlogq(xmm7, 0x96, xmm1, xmm2, Assembler::AVX_512bit); // xor ABC
7454 
7455   evpclmulqdq(xmm5, xmm4, xmm10, 0x01, Assembler::AVX_512bit);
7456   evpclmulqdq(xmm6, xmm4, xmm10, 0x10, Assembler::AVX_512bit);
7457   vpternlogq(xmm8, 0x96, xmm5, xmm6, Assembler::AVX_512bit); // xor ABC
7458 
7459   evmovdquq(xmm0, xmm7, Assembler::AVX_512bit);
7460   evmovdquq(xmm4, xmm8, Assembler::AVX_512bit);
7461 
7462   addl(len, 128);
7463   jmp(L_fold_128_B_register);
7464 
7465   // at this section of the code, there is 128 * x + y(0 <= y<128) bytes of buffer.The fold_128_B_loop
7466   // loop will fold 128B at a time until we have 128 + y Bytes of buffer
7467 
7468   // fold 128B at a time.This section of the code folds 8 xmm registers in parallel
7469   bind(L_fold_128_B_loop);
7470   addl(pos, 128);
7471   fold512bit_crc32_avx512(xmm0, xmm10, xmm1, buf, pos, 0 * 64);
7472   fold512bit_crc32_avx512(xmm4, xmm10, xmm1, buf, pos, 1 * 64);
7473 
7474   subl(len, 128);
7475   jcc(Assembler::greaterEqual, L_fold_128_B_loop);
7476 
7477   addl(pos, 128);
7478 
7479   // at this point, the buffer pointer is pointing at the last y Bytes of the buffer, where 0 <= y < 128
7480   // the 128B of folded data is in 8 of the xmm registers : xmm0, xmm1, xmm2, xmm3, xmm4, xmm5, xmm6, xmm7
7481   bind(L_fold_128_B_register);
7482   evmovdquq(xmm16, Address(table, 5 * 16), Assembler::AVX_512bit); // multiply by rk9-rk16
7483   evmovdquq(xmm11, Address(table, 9 * 16), Assembler::AVX_512bit); // multiply by rk17-rk20, rk1,rk2, 0,0
7484   evpclmulqdq(xmm1, xmm0, xmm16, 0x01, Assembler::AVX_512bit);
7485   evpclmulqdq(xmm2, xmm0, xmm16, 0x10, Assembler::AVX_512bit);
7486   // save last that has no multiplicand
7487   vextracti64x2(xmm7, xmm4, 3);
7488 
7489   evpclmulqdq(xmm5, xmm4, xmm11, 0x01, Assembler::AVX_512bit);
7490   evpclmulqdq(xmm6, xmm4, xmm11, 0x10, Assembler::AVX_512bit);
7491   // Needed later in reduction loop
7492   movdqu(xmm10, Address(table, 1 * 16));
7493   vpternlogq(xmm1, 0x96, xmm2, xmm5, Assembler::AVX_512bit); // xor ABC
7494   vpternlogq(xmm1, 0x96, xmm6, xmm7, Assembler::AVX_512bit); // xor ABC
7495 
7496   // Swap 1,0,3,2 - 01 00 11 10
7497   evshufi64x2(xmm8, xmm1, xmm1, 0x4e, Assembler::AVX_512bit);
7498   evpxorq(xmm8, xmm8, xmm1, Assembler::AVX_256bit);
7499   vextracti128(xmm5, xmm8, 1);
7500   evpxorq(xmm7, xmm5, xmm8, Assembler::AVX_128bit);
7501 
7502   // instead of 128, we add 128 - 16 to the loop counter to save 1 instruction from the loop
7503   // instead of a cmp instruction, we use the negative flag with the jl instruction
7504   addl(len, 128 - 16);
7505   jcc(Assembler::less, L_final_reduction_for_128);
7506 
7507   bind(L_16B_reduction_loop);
7508   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
7509   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7510   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7511   movdqu(xmm0, Address(buf, pos, Address::times_1, 0 * 16));
7512   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7513   addl(pos, 16);
7514   subl(len, 16);
7515   jcc(Assembler::greaterEqual, L_16B_reduction_loop);
7516 
7517   bind(L_final_reduction_for_128);
7518   addl(len, 16);
7519   jcc(Assembler::equal, L_128_done);
7520 
7521   bind(L_get_last_two_xmms);
7522   movdqu(xmm2, xmm7);
7523   addl(pos, len);
7524   movdqu(xmm1, Address(buf, pos, Address::times_1, -16));
7525   subl(pos, len);
7526 
7527   // get rid of the extra data that was loaded before
7528   // load the shift constant
7529   lea(rax, ExternalAddress(StubRoutines::x86::shuf_table_crc32_avx512_addr()));
7530   movdqu(xmm0, Address(rax, len));
7531   addl(rax, len);
7532 
7533   vpshufb(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7534   //Change mask to 512
7535   vpxor(xmm0, xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 2 * 16), Assembler::AVX_128bit, tmp2);
7536   vpshufb(xmm2, xmm2, xmm0, Assembler::AVX_128bit);
7537 
7538   blendvpb(xmm2, xmm2, xmm1, xmm0, Assembler::AVX_128bit);
7539   vpclmulqdq(xmm8, xmm7, xmm10, 0x01);
7540   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7541   vpxor(xmm7, xmm7, xmm8, Assembler::AVX_128bit);
7542   vpxor(xmm7, xmm7, xmm2, Assembler::AVX_128bit);
7543 
7544   bind(L_128_done);
7545   // compute crc of a 128-bit value
7546   movdqu(xmm10, Address(table, 3 * 16));
7547   movdqu(xmm0, xmm7);
7548 
7549   // 64b fold
7550   vpclmulqdq(xmm7, xmm7, xmm10, 0x0);
7551   vpsrldq(xmm0, xmm0, 0x8, Assembler::AVX_128bit);
7552   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7553 
7554   // 32b fold
7555   movdqu(xmm0, xmm7);
7556   vpslldq(xmm7, xmm7, 0x4, Assembler::AVX_128bit);
7557   vpclmulqdq(xmm7, xmm7, xmm10, 0x10);
7558   vpxor(xmm7, xmm7, xmm0, Assembler::AVX_128bit);
7559   jmp(L_barrett);
7560 
7561   bind(L_less_than_256);
7562   kernel_crc32_avx512_256B(crc, buf, len, table, pos, tmp1, tmp2, L_barrett, L_16B_reduction_loop, L_get_last_two_xmms, L_128_done, L_cleanup);
7563 
7564   //barrett reduction
7565   bind(L_barrett);
7566   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr() + 1 * 16), Assembler::AVX_128bit, tmp2);
7567   movdqu(xmm1, xmm7);
7568   movdqu(xmm2, xmm7);
7569   movdqu(xmm10, Address(table, 4 * 16));
7570 
7571   pclmulqdq(xmm7, xmm10, 0x0);
7572   pxor(xmm7, xmm2);
7573   vpand(xmm7, xmm7, ExternalAddress(StubRoutines::x86::crc_by128_masks_avx512_addr()), Assembler::AVX_128bit, tmp2);
7574   movdqu(xmm2, xmm7);
7575   pclmulqdq(xmm7, xmm10, 0x10);
7576   pxor(xmm7, xmm2);
7577   pxor(xmm7, xmm1);
7578   pextrd(crc, xmm7, 2);
7579 
7580   bind(L_cleanup);
7581   addptr(rsp, 16 * 2 + 8);
7582   pop(r12);
7583 }
7584 
7585 // S. Gueron / Information Processing Letters 112 (2012) 184
7586 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table.
7587 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0].
7588 // Output: the 64-bit carry-less product of B * CONST
7589 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n,
7590                                      Register tmp1, Register tmp2, Register tmp3) {
7591   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7592   if (n > 0) {
7593     addq(tmp3, n * 256 * 8);
7594   }
7595   //    Q1 = TABLEExt[n][B & 0xFF];
7596   movl(tmp1, in);
7597   andl(tmp1, 0x000000FF);
7598   shll(tmp1, 3);
7599   addq(tmp1, tmp3);
7600   movq(tmp1, Address(tmp1, 0));
7601 
7602   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7603   movl(tmp2, in);
7604   shrl(tmp2, 8);
7605   andl(tmp2, 0x000000FF);
7606   shll(tmp2, 3);
7607   addq(tmp2, tmp3);
7608   movq(tmp2, Address(tmp2, 0));
7609 
7610   shlq(tmp2, 8);
7611   xorq(tmp1, tmp2);
7612 
7613   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7614   movl(tmp2, in);
7615   shrl(tmp2, 16);
7616   andl(tmp2, 0x000000FF);
7617   shll(tmp2, 3);
7618   addq(tmp2, tmp3);
7619   movq(tmp2, Address(tmp2, 0));
7620 
7621   shlq(tmp2, 16);
7622   xorq(tmp1, tmp2);
7623 
7624   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7625   shrl(in, 24);
7626   andl(in, 0x000000FF);
7627   shll(in, 3);
7628   addq(in, tmp3);
7629   movq(in, Address(in, 0));
7630 
7631   shlq(in, 24);
7632   xorq(in, tmp1);
7633   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7634 }
7635 
7636 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7637                                       Register in_out,
7638                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7639                                       XMMRegister w_xtmp2,
7640                                       Register tmp1,
7641                                       Register n_tmp2, Register n_tmp3) {
7642   if (is_pclmulqdq_supported) {
7643     movdl(w_xtmp1, in_out); // modified blindly
7644 
7645     movl(tmp1, const_or_pre_comp_const_index);
7646     movdl(w_xtmp2, tmp1);
7647     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7648 
7649     movdq(in_out, w_xtmp1);
7650   } else {
7651     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3);
7652   }
7653 }
7654 
7655 // Recombination Alternative 2: No bit-reflections
7656 // T1 = (CRC_A * U1) << 1
7657 // T2 = (CRC_B * U2) << 1
7658 // C1 = T1 >> 32
7659 // C2 = T2 >> 32
7660 // T1 = T1 & 0xFFFFFFFF
7661 // T2 = T2 & 0xFFFFFFFF
7662 // T1 = CRC32(0, T1)
7663 // T2 = CRC32(0, T2)
7664 // C1 = C1 ^ T1
7665 // C2 = C2 ^ T2
7666 // CRC = C1 ^ C2 ^ CRC_C
7667 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7668                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7669                                      Register tmp1, Register tmp2,
7670                                      Register n_tmp3) {
7671   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7672   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7673   shlq(in_out, 1);
7674   movl(tmp1, in_out);
7675   shrq(in_out, 32);
7676   xorl(tmp2, tmp2);
7677   crc32(tmp2, tmp1, 4);
7678   xorl(in_out, tmp2); // we don't care about upper 32 bit contents here
7679   shlq(in1, 1);
7680   movl(tmp1, in1);
7681   shrq(in1, 32);
7682   xorl(tmp2, tmp2);
7683   crc32(tmp2, tmp1, 4);
7684   xorl(in1, tmp2);
7685   xorl(in_out, in1);
7686   xorl(in_out, in2);
7687 }
7688 
7689 // Set N to predefined value
7690 // Subtract from a length of a buffer
7691 // execute in a loop:
7692 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0
7693 // for i = 1 to N do
7694 //  CRC_A = CRC32(CRC_A, A[i])
7695 //  CRC_B = CRC32(CRC_B, B[i])
7696 //  CRC_C = CRC32(CRC_C, C[i])
7697 // end for
7698 // Recombine
7699 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7700                                        Register in_out1, Register in_out2, Register in_out3,
7701                                        Register tmp1, Register tmp2, Register tmp3,
7702                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7703                                        Register tmp4, Register tmp5,
7704                                        Register n_tmp6) {
7705   Label L_processPartitions;
7706   Label L_processPartition;
7707   Label L_exit;
7708 
7709   bind(L_processPartitions);
7710   cmpl(in_out1, 3 * size);
7711   jcc(Assembler::less, L_exit);
7712     xorl(tmp1, tmp1);
7713     xorl(tmp2, tmp2);
7714     movq(tmp3, in_out2);
7715     addq(tmp3, size);
7716 
7717     bind(L_processPartition);
7718       crc32(in_out3, Address(in_out2, 0), 8);
7719       crc32(tmp1, Address(in_out2, size), 8);
7720       crc32(tmp2, Address(in_out2, size * 2), 8);
7721       addq(in_out2, 8);
7722       cmpq(in_out2, tmp3);
7723       jcc(Assembler::less, L_processPartition);
7724     crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7725             w_xtmp1, w_xtmp2, w_xtmp3,
7726             tmp4, tmp5,
7727             n_tmp6);
7728     addq(in_out2, 2 * size);
7729     subl(in_out1, 3 * size);
7730     jmp(L_processPartitions);
7731 
7732   bind(L_exit);
7733 }
7734 #else
7735 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n,
7736                                      Register tmp1, Register tmp2, Register tmp3,
7737                                      XMMRegister xtmp1, XMMRegister xtmp2) {
7738   lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr()));
7739   if (n > 0) {
7740     addl(tmp3, n * 256 * 8);
7741   }
7742   //    Q1 = TABLEExt[n][B & 0xFF];
7743   movl(tmp1, in_out);
7744   andl(tmp1, 0x000000FF);
7745   shll(tmp1, 3);
7746   addl(tmp1, tmp3);
7747   movq(xtmp1, Address(tmp1, 0));
7748 
7749   //    Q2 = TABLEExt[n][B >> 8 & 0xFF];
7750   movl(tmp2, in_out);
7751   shrl(tmp2, 8);
7752   andl(tmp2, 0x000000FF);
7753   shll(tmp2, 3);
7754   addl(tmp2, tmp3);
7755   movq(xtmp2, Address(tmp2, 0));
7756 
7757   psllq(xtmp2, 8);
7758   pxor(xtmp1, xtmp2);
7759 
7760   //    Q3 = TABLEExt[n][B >> 16 & 0xFF];
7761   movl(tmp2, in_out);
7762   shrl(tmp2, 16);
7763   andl(tmp2, 0x000000FF);
7764   shll(tmp2, 3);
7765   addl(tmp2, tmp3);
7766   movq(xtmp2, Address(tmp2, 0));
7767 
7768   psllq(xtmp2, 16);
7769   pxor(xtmp1, xtmp2);
7770 
7771   //    Q4 = TABLEExt[n][B >> 24 & 0xFF];
7772   shrl(in_out, 24);
7773   andl(in_out, 0x000000FF);
7774   shll(in_out, 3);
7775   addl(in_out, tmp3);
7776   movq(xtmp2, Address(in_out, 0));
7777 
7778   psllq(xtmp2, 24);
7779   pxor(xtmp1, xtmp2); // Result in CXMM
7780   //    return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24;
7781 }
7782 
7783 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1,
7784                                       Register in_out,
7785                                       uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported,
7786                                       XMMRegister w_xtmp2,
7787                                       Register tmp1,
7788                                       Register n_tmp2, Register n_tmp3) {
7789   if (is_pclmulqdq_supported) {
7790     movdl(w_xtmp1, in_out);
7791 
7792     movl(tmp1, const_or_pre_comp_const_index);
7793     movdl(w_xtmp2, tmp1);
7794     pclmulqdq(w_xtmp1, w_xtmp2, 0);
7795     // Keep result in XMM since GPR is 32 bit in length
7796   } else {
7797     crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2);
7798   }
7799 }
7800 
7801 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2,
7802                                      XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7803                                      Register tmp1, Register tmp2,
7804                                      Register n_tmp3) {
7805   crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7806   crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3);
7807 
7808   psllq(w_xtmp1, 1);
7809   movdl(tmp1, w_xtmp1);
7810   psrlq(w_xtmp1, 32);
7811   movdl(in_out, w_xtmp1);
7812 
7813   xorl(tmp2, tmp2);
7814   crc32(tmp2, tmp1, 4);
7815   xorl(in_out, tmp2);
7816 
7817   psllq(w_xtmp2, 1);
7818   movdl(tmp1, w_xtmp2);
7819   psrlq(w_xtmp2, 32);
7820   movdl(in1, w_xtmp2);
7821 
7822   xorl(tmp2, tmp2);
7823   crc32(tmp2, tmp1, 4);
7824   xorl(in1, tmp2);
7825   xorl(in_out, in1);
7826   xorl(in_out, in2);
7827 }
7828 
7829 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported,
7830                                        Register in_out1, Register in_out2, Register in_out3,
7831                                        Register tmp1, Register tmp2, Register tmp3,
7832                                        XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7833                                        Register tmp4, Register tmp5,
7834                                        Register n_tmp6) {
7835   Label L_processPartitions;
7836   Label L_processPartition;
7837   Label L_exit;
7838 
7839   bind(L_processPartitions);
7840   cmpl(in_out1, 3 * size);
7841   jcc(Assembler::less, L_exit);
7842     xorl(tmp1, tmp1);
7843     xorl(tmp2, tmp2);
7844     movl(tmp3, in_out2);
7845     addl(tmp3, size);
7846 
7847     bind(L_processPartition);
7848       crc32(in_out3, Address(in_out2, 0), 4);
7849       crc32(tmp1, Address(in_out2, size), 4);
7850       crc32(tmp2, Address(in_out2, size*2), 4);
7851       crc32(in_out3, Address(in_out2, 0+4), 4);
7852       crc32(tmp1, Address(in_out2, size+4), 4);
7853       crc32(tmp2, Address(in_out2, size*2+4), 4);
7854       addl(in_out2, 8);
7855       cmpl(in_out2, tmp3);
7856       jcc(Assembler::less, L_processPartition);
7857 
7858         push(tmp3);
7859         push(in_out1);
7860         push(in_out2);
7861         tmp4 = tmp3;
7862         tmp5 = in_out1;
7863         n_tmp6 = in_out2;
7864 
7865       crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2,
7866             w_xtmp1, w_xtmp2, w_xtmp3,
7867             tmp4, tmp5,
7868             n_tmp6);
7869 
7870         pop(in_out2);
7871         pop(in_out1);
7872         pop(tmp3);
7873 
7874     addl(in_out2, 2 * size);
7875     subl(in_out1, 3 * size);
7876     jmp(L_processPartitions);
7877 
7878   bind(L_exit);
7879 }
7880 #endif //LP64
7881 
7882 #ifdef _LP64
7883 // Algorithm 2: Pipelined usage of the CRC32 instruction.
7884 // Input: A buffer I of L bytes.
7885 // Output: the CRC32C value of the buffer.
7886 // Notations:
7887 // Write L = 24N + r, with N = floor (L/24).
7888 // r = L mod 24 (0 <= r < 24).
7889 // Consider I as the concatenation of A|B|C|R, where A, B, C, each,
7890 // N quadwords, and R consists of r bytes.
7891 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1
7892 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1
7893 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1
7894 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1
7895 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7896                                           Register tmp1, Register tmp2, Register tmp3,
7897                                           Register tmp4, Register tmp5, Register tmp6,
7898                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7899                                           bool is_pclmulqdq_supported) {
7900   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7901   Label L_wordByWord;
7902   Label L_byteByByteProlog;
7903   Label L_byteByByte;
7904   Label L_exit;
7905 
7906   if (is_pclmulqdq_supported ) {
7907     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7908     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1);
7909 
7910     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7911     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7912 
7913     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7914     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7915     assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\"");
7916   } else {
7917     const_or_pre_comp_const_index[0] = 1;
7918     const_or_pre_comp_const_index[1] = 0;
7919 
7920     const_or_pre_comp_const_index[2] = 3;
7921     const_or_pre_comp_const_index[3] = 2;
7922 
7923     const_or_pre_comp_const_index[4] = 5;
7924     const_or_pre_comp_const_index[5] = 4;
7925    }
7926   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
7927                     in2, in1, in_out,
7928                     tmp1, tmp2, tmp3,
7929                     w_xtmp1, w_xtmp2, w_xtmp3,
7930                     tmp4, tmp5,
7931                     tmp6);
7932   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
7933                     in2, in1, in_out,
7934                     tmp1, tmp2, tmp3,
7935                     w_xtmp1, w_xtmp2, w_xtmp3,
7936                     tmp4, tmp5,
7937                     tmp6);
7938   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
7939                     in2, in1, in_out,
7940                     tmp1, tmp2, tmp3,
7941                     w_xtmp1, w_xtmp2, w_xtmp3,
7942                     tmp4, tmp5,
7943                     tmp6);
7944   movl(tmp1, in2);
7945   andl(tmp1, 0x00000007);
7946   negl(tmp1);
7947   addl(tmp1, in2);
7948   addq(tmp1, in1);
7949 
7950   BIND(L_wordByWord);
7951   cmpq(in1, tmp1);
7952   jcc(Assembler::greaterEqual, L_byteByByteProlog);
7953     crc32(in_out, Address(in1, 0), 4);
7954     addq(in1, 4);
7955     jmp(L_wordByWord);
7956 
7957   BIND(L_byteByByteProlog);
7958   andl(in2, 0x00000007);
7959   movl(tmp2, 1);
7960 
7961   BIND(L_byteByByte);
7962   cmpl(tmp2, in2);
7963   jccb(Assembler::greater, L_exit);
7964     crc32(in_out, Address(in1, 0), 1);
7965     incq(in1);
7966     incl(tmp2);
7967     jmp(L_byteByByte);
7968 
7969   BIND(L_exit);
7970 }
7971 #else
7972 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2,
7973                                           Register tmp1, Register  tmp2, Register tmp3,
7974                                           Register tmp4, Register  tmp5, Register tmp6,
7975                                           XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3,
7976                                           bool is_pclmulqdq_supported) {
7977   uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS];
7978   Label L_wordByWord;
7979   Label L_byteByByteProlog;
7980   Label L_byteByByte;
7981   Label L_exit;
7982 
7983   if (is_pclmulqdq_supported) {
7984     const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr;
7985     const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1);
7986 
7987     const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2);
7988     const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3);
7989 
7990     const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4);
7991     const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5);
7992   } else {
7993     const_or_pre_comp_const_index[0] = 1;
7994     const_or_pre_comp_const_index[1] = 0;
7995 
7996     const_or_pre_comp_const_index[2] = 3;
7997     const_or_pre_comp_const_index[3] = 2;
7998 
7999     const_or_pre_comp_const_index[4] = 5;
8000     const_or_pre_comp_const_index[5] = 4;
8001   }
8002   crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported,
8003                     in2, in1, in_out,
8004                     tmp1, tmp2, tmp3,
8005                     w_xtmp1, w_xtmp2, w_xtmp3,
8006                     tmp4, tmp5,
8007                     tmp6);
8008   crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported,
8009                     in2, in1, in_out,
8010                     tmp1, tmp2, tmp3,
8011                     w_xtmp1, w_xtmp2, w_xtmp3,
8012                     tmp4, tmp5,
8013                     tmp6);
8014   crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported,
8015                     in2, in1, in_out,
8016                     tmp1, tmp2, tmp3,
8017                     w_xtmp1, w_xtmp2, w_xtmp3,
8018                     tmp4, tmp5,
8019                     tmp6);
8020   movl(tmp1, in2);
8021   andl(tmp1, 0x00000007);
8022   negl(tmp1);
8023   addl(tmp1, in2);
8024   addl(tmp1, in1);
8025 
8026   BIND(L_wordByWord);
8027   cmpl(in1, tmp1);
8028   jcc(Assembler::greaterEqual, L_byteByByteProlog);
8029     crc32(in_out, Address(in1,0), 4);
8030     addl(in1, 4);
8031     jmp(L_wordByWord);
8032 
8033   BIND(L_byteByByteProlog);
8034   andl(in2, 0x00000007);
8035   movl(tmp2, 1);
8036 
8037   BIND(L_byteByByte);
8038   cmpl(tmp2, in2);
8039   jccb(Assembler::greater, L_exit);
8040     movb(tmp1, Address(in1, 0));
8041     crc32(in_out, tmp1, 1);
8042     incl(in1);
8043     incl(tmp2);
8044     jmp(L_byteByByte);
8045 
8046   BIND(L_exit);
8047 }
8048 #endif // LP64
8049 #undef BIND
8050 #undef BLOCK_COMMENT
8051 
8052 // Compress char[] array to byte[].
8053 //   ..\jdk\src\java.base\share\classes\java\lang\StringUTF16.java
8054 //   @IntrinsicCandidate
8055 //   private static int compress(char[] src, int srcOff, byte[] dst, int dstOff, int len) {
8056 //     for (int i = 0; i < len; i++) {
8057 //       int c = src[srcOff++];
8058 //       if (c >>> 8 != 0) {
8059 //         return 0;
8060 //       }
8061 //       dst[dstOff++] = (byte)c;
8062 //     }
8063 //     return len;
8064 //   }
8065 void MacroAssembler::char_array_compress(Register src, Register dst, Register len,
8066   XMMRegister tmp1Reg, XMMRegister tmp2Reg,
8067   XMMRegister tmp3Reg, XMMRegister tmp4Reg,
8068   Register tmp5, Register result, KRegister mask1, KRegister mask2) {
8069   Label copy_chars_loop, return_length, return_zero, done;
8070 
8071   // rsi: src
8072   // rdi: dst
8073   // rdx: len
8074   // rcx: tmp5
8075   // rax: result
8076 
8077   // rsi holds start addr of source char[] to be compressed
8078   // rdi holds start addr of destination byte[]
8079   // rdx holds length
8080 
8081   assert(len != result, "");
8082 
8083   // save length for return
8084   push(len);
8085 
8086   if ((AVX3Threshold == 0) && (UseAVX > 2) && // AVX512
8087     VM_Version::supports_avx512vlbw() &&
8088     VM_Version::supports_bmi2()) {
8089 
8090     Label copy_32_loop, copy_loop_tail, below_threshold;
8091 
8092     // alignment
8093     Label post_alignment;
8094 
8095     // if length of the string is less than 16, handle it in an old fashioned way
8096     testl(len, -32);
8097     jcc(Assembler::zero, below_threshold);
8098 
8099     // First check whether a character is compressible ( <= 0xFF).
8100     // Create mask to test for Unicode chars inside zmm vector
8101     movl(result, 0x00FF);
8102     evpbroadcastw(tmp2Reg, result, Assembler::AVX_512bit);
8103 
8104     testl(len, -64);
8105     jcc(Assembler::zero, post_alignment);
8106 
8107     movl(tmp5, dst);
8108     andl(tmp5, (32 - 1));
8109     negl(tmp5);
8110     andl(tmp5, (32 - 1));
8111 
8112     // bail out when there is nothing to be done
8113     testl(tmp5, 0xFFFFFFFF);
8114     jcc(Assembler::zero, post_alignment);
8115 
8116     // ~(~0 << len), where len is the # of remaining elements to process
8117     movl(result, 0xFFFFFFFF);
8118     shlxl(result, result, tmp5);
8119     notl(result);
8120     kmovdl(mask2, result);
8121 
8122     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8123     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8124     ktestd(mask1, mask2);
8125     jcc(Assembler::carryClear, return_zero);
8126 
8127     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8128 
8129     addptr(src, tmp5);
8130     addptr(src, tmp5);
8131     addptr(dst, tmp5);
8132     subl(len, tmp5);
8133 
8134     bind(post_alignment);
8135     // end of alignment
8136 
8137     movl(tmp5, len);
8138     andl(tmp5, (32 - 1));    // tail count (in chars)
8139     andl(len, ~(32 - 1));    // vector count (in chars)
8140     jcc(Assembler::zero, copy_loop_tail);
8141 
8142     lea(src, Address(src, len, Address::times_2));
8143     lea(dst, Address(dst, len, Address::times_1));
8144     negptr(len);
8145 
8146     bind(copy_32_loop);
8147     evmovdquw(tmp1Reg, Address(src, len, Address::times_2), /*merge*/ false, Assembler::AVX_512bit);
8148     evpcmpuw(mask1, tmp1Reg, tmp2Reg, Assembler::le, Assembler::AVX_512bit);
8149     kortestdl(mask1, mask1);
8150     jcc(Assembler::carryClear, return_zero);
8151 
8152     // All elements in current processed chunk are valid candidates for
8153     // compression. Write a truncated byte elements to the memory.
8154     evpmovwb(Address(dst, len, Address::times_1), tmp1Reg, Assembler::AVX_512bit);
8155     addptr(len, 32);
8156     jcc(Assembler::notZero, copy_32_loop);
8157 
8158     bind(copy_loop_tail);
8159     // bail out when there is nothing to be done
8160     testl(tmp5, 0xFFFFFFFF);
8161     jcc(Assembler::zero, return_length);
8162 
8163     movl(len, tmp5);
8164 
8165     // ~(~0 << len), where len is the # of remaining elements to process
8166     movl(result, 0xFFFFFFFF);
8167     shlxl(result, result, len);
8168     notl(result);
8169 
8170     kmovdl(mask2, result);
8171 
8172     evmovdquw(tmp1Reg, mask2, Address(src, 0), /*merge*/ false, Assembler::AVX_512bit);
8173     evpcmpw(mask1, mask2, tmp1Reg, tmp2Reg, Assembler::le, /*signed*/ false, Assembler::AVX_512bit);
8174     ktestd(mask1, mask2);
8175     jcc(Assembler::carryClear, return_zero);
8176 
8177     evpmovwb(Address(dst, 0), mask2, tmp1Reg, Assembler::AVX_512bit);
8178     jmp(return_length);
8179 
8180     bind(below_threshold);
8181   }
8182 
8183   if (UseSSE42Intrinsics) {
8184     Label copy_32_loop, copy_16, copy_tail;
8185 
8186     movl(result, len);
8187 
8188     movl(tmp5, 0xff00ff00);   // create mask to test for Unicode chars in vectors
8189 
8190     // vectored compression
8191     andl(len, 0xfffffff0);    // vector count (in chars)
8192     andl(result, 0x0000000f);    // tail count (in chars)
8193     testl(len, len);
8194     jcc(Assembler::zero, copy_16);
8195 
8196     // compress 16 chars per iter
8197     movdl(tmp1Reg, tmp5);
8198     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8199     pxor(tmp4Reg, tmp4Reg);
8200 
8201     lea(src, Address(src, len, Address::times_2));
8202     lea(dst, Address(dst, len, Address::times_1));
8203     negptr(len);
8204 
8205     bind(copy_32_loop);
8206     movdqu(tmp2Reg, Address(src, len, Address::times_2));     // load 1st 8 characters
8207     por(tmp4Reg, tmp2Reg);
8208     movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters
8209     por(tmp4Reg, tmp3Reg);
8210     ptest(tmp4Reg, tmp1Reg);       // check for Unicode chars in next vector
8211     jcc(Assembler::notZero, return_zero);
8212     packuswb(tmp2Reg, tmp3Reg);    // only ASCII chars; compress each to 1 byte
8213     movdqu(Address(dst, len, Address::times_1), tmp2Reg);
8214     addptr(len, 16);
8215     jcc(Assembler::notZero, copy_32_loop);
8216 
8217     // compress next vector of 8 chars (if any)
8218     bind(copy_16);
8219     movl(len, result);
8220     andl(len, 0xfffffff8);    // vector count (in chars)
8221     andl(result, 0x00000007);    // tail count (in chars)
8222     testl(len, len);
8223     jccb(Assembler::zero, copy_tail);
8224 
8225     movdl(tmp1Reg, tmp5);
8226     pshufd(tmp1Reg, tmp1Reg, 0);   // store Unicode mask in tmp1Reg
8227     pxor(tmp3Reg, tmp3Reg);
8228 
8229     movdqu(tmp2Reg, Address(src, 0));
8230     ptest(tmp2Reg, tmp1Reg);       // check for Unicode chars in vector
8231     jccb(Assembler::notZero, return_zero);
8232     packuswb(tmp2Reg, tmp3Reg);    // only LATIN1 chars; compress each to 1 byte
8233     movq(Address(dst, 0), tmp2Reg);
8234     addptr(src, 16);
8235     addptr(dst, 8);
8236 
8237     bind(copy_tail);
8238     movl(len, result);
8239   }
8240   // compress 1 char per iter
8241   testl(len, len);
8242   jccb(Assembler::zero, return_length);
8243   lea(src, Address(src, len, Address::times_2));
8244   lea(dst, Address(dst, len, Address::times_1));
8245   negptr(len);
8246 
8247   bind(copy_chars_loop);
8248   load_unsigned_short(result, Address(src, len, Address::times_2));
8249   testl(result, 0xff00);      // check if Unicode char
8250   jccb(Assembler::notZero, return_zero);
8251   movb(Address(dst, len, Address::times_1), result);  // ASCII char; compress to 1 byte
8252   increment(len);
8253   jcc(Assembler::notZero, copy_chars_loop);
8254 
8255   // if compression succeeded, return length
8256   bind(return_length);
8257   pop(result);
8258   jmpb(done);
8259 
8260   // if compression failed, return 0
8261   bind(return_zero);
8262   xorl(result, result);
8263   addptr(rsp, wordSize);
8264 
8265   bind(done);
8266 }
8267 
8268 // Inflate byte[] array to char[].
8269 //   ..\jdk\src\java.base\share\classes\java\lang\StringLatin1.java
8270 //   @IntrinsicCandidate
8271 //   private static void inflate(byte[] src, int srcOff, char[] dst, int dstOff, int len) {
8272 //     for (int i = 0; i < len; i++) {
8273 //       dst[dstOff++] = (char)(src[srcOff++] & 0xff);
8274 //     }
8275 //   }
8276 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len,
8277   XMMRegister tmp1, Register tmp2, KRegister mask) {
8278   Label copy_chars_loop, done, below_threshold, avx3_threshold;
8279   // rsi: src
8280   // rdi: dst
8281   // rdx: len
8282   // rcx: tmp2
8283 
8284   // rsi holds start addr of source byte[] to be inflated
8285   // rdi holds start addr of destination char[]
8286   // rdx holds length
8287   assert_different_registers(src, dst, len, tmp2);
8288   movl(tmp2, len);
8289   if ((UseAVX > 2) && // AVX512
8290     VM_Version::supports_avx512vlbw() &&
8291     VM_Version::supports_bmi2()) {
8292 
8293     Label copy_32_loop, copy_tail;
8294     Register tmp3_aliased = len;
8295 
8296     // if length of the string is less than 16, handle it in an old fashioned way
8297     testl(len, -16);
8298     jcc(Assembler::zero, below_threshold);
8299 
8300     testl(len, -1 * AVX3Threshold);
8301     jcc(Assembler::zero, avx3_threshold);
8302 
8303     // In order to use only one arithmetic operation for the main loop we use
8304     // this pre-calculation
8305     andl(tmp2, (32 - 1)); // tail count (in chars), 32 element wide loop
8306     andl(len, -32);     // vector count
8307     jccb(Assembler::zero, copy_tail);
8308 
8309     lea(src, Address(src, len, Address::times_1));
8310     lea(dst, Address(dst, len, Address::times_2));
8311     negptr(len);
8312 
8313 
8314     // inflate 32 chars per iter
8315     bind(copy_32_loop);
8316     vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_512bit);
8317     evmovdquw(Address(dst, len, Address::times_2), tmp1, /*merge*/ false, Assembler::AVX_512bit);
8318     addptr(len, 32);
8319     jcc(Assembler::notZero, copy_32_loop);
8320 
8321     bind(copy_tail);
8322     // bail out when there is nothing to be done
8323     testl(tmp2, -1); // we don't destroy the contents of tmp2 here
8324     jcc(Assembler::zero, done);
8325 
8326     // ~(~0 << length), where length is the # of remaining elements to process
8327     movl(tmp3_aliased, -1);
8328     shlxl(tmp3_aliased, tmp3_aliased, tmp2);
8329     notl(tmp3_aliased);
8330     kmovdl(mask, tmp3_aliased);
8331     evpmovzxbw(tmp1, mask, Address(src, 0), Assembler::AVX_512bit);
8332     evmovdquw(Address(dst, 0), mask, tmp1, /*merge*/ true, Assembler::AVX_512bit);
8333 
8334     jmp(done);
8335     bind(avx3_threshold);
8336   }
8337   if (UseSSE42Intrinsics) {
8338     Label copy_16_loop, copy_8_loop, copy_bytes, copy_new_tail, copy_tail;
8339 
8340     if (UseAVX > 1) {
8341       andl(tmp2, (16 - 1));
8342       andl(len, -16);
8343       jccb(Assembler::zero, copy_new_tail);
8344     } else {
8345       andl(tmp2, 0x00000007);   // tail count (in chars)
8346       andl(len, 0xfffffff8);    // vector count (in chars)
8347       jccb(Assembler::zero, copy_tail);
8348     }
8349 
8350     // vectored inflation
8351     lea(src, Address(src, len, Address::times_1));
8352     lea(dst, Address(dst, len, Address::times_2));
8353     negptr(len);
8354 
8355     if (UseAVX > 1) {
8356       bind(copy_16_loop);
8357       vpmovzxbw(tmp1, Address(src, len, Address::times_1), Assembler::AVX_256bit);
8358       vmovdqu(Address(dst, len, Address::times_2), tmp1);
8359       addptr(len, 16);
8360       jcc(Assembler::notZero, copy_16_loop);
8361 
8362       bind(below_threshold);
8363       bind(copy_new_tail);
8364       movl(len, tmp2);
8365       andl(tmp2, 0x00000007);
8366       andl(len, 0xFFFFFFF8);
8367       jccb(Assembler::zero, copy_tail);
8368 
8369       pmovzxbw(tmp1, Address(src, 0));
8370       movdqu(Address(dst, 0), tmp1);
8371       addptr(src, 8);
8372       addptr(dst, 2 * 8);
8373 
8374       jmp(copy_tail, true);
8375     }
8376 
8377     // inflate 8 chars per iter
8378     bind(copy_8_loop);
8379     pmovzxbw(tmp1, Address(src, len, Address::times_1));  // unpack to 8 words
8380     movdqu(Address(dst, len, Address::times_2), tmp1);
8381     addptr(len, 8);
8382     jcc(Assembler::notZero, copy_8_loop);
8383 
8384     bind(copy_tail);
8385     movl(len, tmp2);
8386 
8387     cmpl(len, 4);
8388     jccb(Assembler::less, copy_bytes);
8389 
8390     movdl(tmp1, Address(src, 0));  // load 4 byte chars
8391     pmovzxbw(tmp1, tmp1);
8392     movq(Address(dst, 0), tmp1);
8393     subptr(len, 4);
8394     addptr(src, 4);
8395     addptr(dst, 8);
8396 
8397     bind(copy_bytes);
8398   } else {
8399     bind(below_threshold);
8400   }
8401 
8402   testl(len, len);
8403   jccb(Assembler::zero, done);
8404   lea(src, Address(src, len, Address::times_1));
8405   lea(dst, Address(dst, len, Address::times_2));
8406   negptr(len);
8407 
8408   // inflate 1 char per iter
8409   bind(copy_chars_loop);
8410   load_unsigned_byte(tmp2, Address(src, len, Address::times_1));  // load byte char
8411   movw(Address(dst, len, Address::times_2), tmp2);  // inflate byte char to word
8412   increment(len);
8413   jcc(Assembler::notZero, copy_chars_loop);
8414 
8415   bind(done);
8416 }
8417 
8418 
8419 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, XMMRegister dst, Address src, int vector_len) {
8420   switch(type) {
8421     case T_BYTE:
8422     case T_BOOLEAN:
8423       evmovdqub(dst, kmask, src, false, vector_len);
8424       break;
8425     case T_CHAR:
8426     case T_SHORT:
8427       evmovdquw(dst, kmask, src, false, vector_len);
8428       break;
8429     case T_INT:
8430     case T_FLOAT:
8431       evmovdqul(dst, kmask, src, false, vector_len);
8432       break;
8433     case T_LONG:
8434     case T_DOUBLE:
8435       evmovdquq(dst, kmask, src, false, vector_len);
8436       break;
8437     default:
8438       fatal("Unexpected type argument %s", type2name(type));
8439       break;
8440   }
8441 }
8442 
8443 void MacroAssembler::evmovdqu(BasicType type, KRegister kmask, Address dst, XMMRegister src, int vector_len) {
8444   switch(type) {
8445     case T_BYTE:
8446     case T_BOOLEAN:
8447       evmovdqub(dst, kmask, src, true, vector_len);
8448       break;
8449     case T_CHAR:
8450     case T_SHORT:
8451       evmovdquw(dst, kmask, src, true, vector_len);
8452       break;
8453     case T_INT:
8454     case T_FLOAT:
8455       evmovdqul(dst, kmask, src, true, vector_len);
8456       break;
8457     case T_LONG:
8458     case T_DOUBLE:
8459       evmovdquq(dst, kmask, src, true, vector_len);
8460       break;
8461     default:
8462       fatal("Unexpected type argument %s", type2name(type));
8463       break;
8464   }
8465 }
8466 
8467 void MacroAssembler::knot(uint masklen, KRegister dst, KRegister src, KRegister ktmp, Register rtmp) {
8468   switch(masklen) {
8469     case 2:
8470        knotbl(dst, src);
8471        movl(rtmp, 3);
8472        kmovbl(ktmp, rtmp);
8473        kandbl(dst, ktmp, dst);
8474        break;
8475     case 4:
8476        knotbl(dst, src);
8477        movl(rtmp, 15);
8478        kmovbl(ktmp, rtmp);
8479        kandbl(dst, ktmp, dst);
8480        break;
8481     case 8:
8482        knotbl(dst, src);
8483        break;
8484     case 16:
8485        knotwl(dst, src);
8486        break;
8487     case 32:
8488        knotdl(dst, src);
8489        break;
8490     case 64:
8491        knotql(dst, src);
8492        break;
8493     default:
8494       fatal("Unexpected vector length %d", masklen);
8495       break;
8496   }
8497 }
8498 
8499 void MacroAssembler::kand(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8500   switch(type) {
8501     case T_BOOLEAN:
8502     case T_BYTE:
8503        kandbl(dst, src1, src2);
8504        break;
8505     case T_CHAR:
8506     case T_SHORT:
8507        kandwl(dst, src1, src2);
8508        break;
8509     case T_INT:
8510     case T_FLOAT:
8511        kanddl(dst, src1, src2);
8512        break;
8513     case T_LONG:
8514     case T_DOUBLE:
8515        kandql(dst, src1, src2);
8516        break;
8517     default:
8518       fatal("Unexpected type argument %s", type2name(type));
8519       break;
8520   }
8521 }
8522 
8523 void MacroAssembler::kor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8524   switch(type) {
8525     case T_BOOLEAN:
8526     case T_BYTE:
8527        korbl(dst, src1, src2);
8528        break;
8529     case T_CHAR:
8530     case T_SHORT:
8531        korwl(dst, src1, src2);
8532        break;
8533     case T_INT:
8534     case T_FLOAT:
8535        kordl(dst, src1, src2);
8536        break;
8537     case T_LONG:
8538     case T_DOUBLE:
8539        korql(dst, src1, src2);
8540        break;
8541     default:
8542       fatal("Unexpected type argument %s", type2name(type));
8543       break;
8544   }
8545 }
8546 
8547 void MacroAssembler::kxor(BasicType type, KRegister dst, KRegister src1, KRegister src2) {
8548   switch(type) {
8549     case T_BOOLEAN:
8550     case T_BYTE:
8551        kxorbl(dst, src1, src2);
8552        break;
8553     case T_CHAR:
8554     case T_SHORT:
8555        kxorwl(dst, src1, src2);
8556        break;
8557     case T_INT:
8558     case T_FLOAT:
8559        kxordl(dst, src1, src2);
8560        break;
8561     case T_LONG:
8562     case T_DOUBLE:
8563        kxorql(dst, src1, src2);
8564        break;
8565     default:
8566       fatal("Unexpected type argument %s", type2name(type));
8567       break;
8568   }
8569 }
8570 
8571 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8572   switch(type) {
8573     case T_BOOLEAN:
8574     case T_BYTE:
8575       evpermb(dst, mask, nds, src, merge, vector_len); break;
8576     case T_CHAR:
8577     case T_SHORT:
8578       evpermw(dst, mask, nds, src, merge, vector_len); break;
8579     case T_INT:
8580     case T_FLOAT:
8581       evpermd(dst, mask, nds, src, merge, vector_len); break;
8582     case T_LONG:
8583     case T_DOUBLE:
8584       evpermq(dst, mask, nds, src, merge, vector_len); break;
8585     default:
8586       fatal("Unexpected type argument %s", type2name(type)); break;
8587   }
8588 }
8589 
8590 void MacroAssembler::evperm(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8591   switch(type) {
8592     case T_BOOLEAN:
8593     case T_BYTE:
8594       evpermb(dst, mask, nds, src, merge, vector_len); break;
8595     case T_CHAR:
8596     case T_SHORT:
8597       evpermw(dst, mask, nds, src, merge, vector_len); break;
8598     case T_INT:
8599     case T_FLOAT:
8600       evpermd(dst, mask, nds, src, merge, vector_len); break;
8601     case T_LONG:
8602     case T_DOUBLE:
8603       evpermq(dst, mask, nds, src, merge, vector_len); break;
8604     default:
8605       fatal("Unexpected type argument %s", type2name(type)); break;
8606   }
8607 }
8608 
8609 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8610   switch(type) {
8611     case T_BYTE:
8612       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8613     case T_SHORT:
8614       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8615     case T_INT:
8616       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8617     case T_LONG:
8618       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8619     default:
8620       fatal("Unexpected type argument %s", type2name(type)); break;
8621   }
8622 }
8623 
8624 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8625   switch(type) {
8626     case T_BYTE:
8627       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8628     case T_SHORT:
8629       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8630     case T_INT:
8631       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8632     case T_LONG:
8633       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8634     default:
8635       fatal("Unexpected type argument %s", type2name(type)); break;
8636   }
8637 }
8638 
8639 void MacroAssembler::evpmins(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8640   switch(type) {
8641     case T_BYTE:
8642       evpminsb(dst, mask, nds, src, merge, vector_len); break;
8643     case T_SHORT:
8644       evpminsw(dst, mask, nds, src, merge, vector_len); break;
8645     case T_INT:
8646       evpminsd(dst, mask, nds, src, merge, vector_len); break;
8647     case T_LONG:
8648       evpminsq(dst, mask, nds, src, merge, vector_len); break;
8649     default:
8650       fatal("Unexpected type argument %s", type2name(type)); break;
8651   }
8652 }
8653 
8654 void MacroAssembler::evpmaxs(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8655   switch(type) {
8656     case T_BYTE:
8657       evpmaxsb(dst, mask, nds, src, merge, vector_len); break;
8658     case T_SHORT:
8659       evpmaxsw(dst, mask, nds, src, merge, vector_len); break;
8660     case T_INT:
8661       evpmaxsd(dst, mask, nds, src, merge, vector_len); break;
8662     case T_LONG:
8663       evpmaxsq(dst, mask, nds, src, merge, vector_len); break;
8664     default:
8665       fatal("Unexpected type argument %s", type2name(type)); break;
8666   }
8667 }
8668 
8669 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8670   switch(type) {
8671     case T_INT:
8672       evpxord(dst, mask, nds, src, merge, vector_len); break;
8673     case T_LONG:
8674       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8675     default:
8676       fatal("Unexpected type argument %s", type2name(type)); break;
8677   }
8678 }
8679 
8680 void MacroAssembler::evxor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8681   switch(type) {
8682     case T_INT:
8683       evpxord(dst, mask, nds, src, merge, vector_len); break;
8684     case T_LONG:
8685       evpxorq(dst, mask, nds, src, merge, vector_len); break;
8686     default:
8687       fatal("Unexpected type argument %s", type2name(type)); break;
8688   }
8689 }
8690 
8691 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8692   switch(type) {
8693     case T_INT:
8694       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8695     case T_LONG:
8696       evporq(dst, mask, nds, src, merge, vector_len); break;
8697     default:
8698       fatal("Unexpected type argument %s", type2name(type)); break;
8699   }
8700 }
8701 
8702 void MacroAssembler::evor(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8703   switch(type) {
8704     case T_INT:
8705       Assembler::evpord(dst, mask, nds, src, merge, vector_len); break;
8706     case T_LONG:
8707       evporq(dst, mask, nds, src, merge, vector_len); break;
8708     default:
8709       fatal("Unexpected type argument %s", type2name(type)); break;
8710   }
8711 }
8712 
8713 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8714   switch(type) {
8715     case T_INT:
8716       evpandd(dst, mask, nds, src, merge, vector_len); break;
8717     case T_LONG:
8718       evpandq(dst, mask, nds, src, merge, vector_len); break;
8719     default:
8720       fatal("Unexpected type argument %s", type2name(type)); break;
8721   }
8722 }
8723 
8724 void MacroAssembler::evand(BasicType type, XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
8725   switch(type) {
8726     case T_INT:
8727       evpandd(dst, mask, nds, src, merge, vector_len); break;
8728     case T_LONG:
8729       evpandq(dst, mask, nds, src, merge, vector_len); break;
8730     default:
8731       fatal("Unexpected type argument %s", type2name(type)); break;
8732   }
8733 }
8734 
8735 void MacroAssembler::anytrue(Register dst, uint masklen, KRegister src1, KRegister src2) {
8736    masklen = masklen < 8 ? 8 : masklen;
8737    ktest(masklen, src1, src2);
8738    setb(Assembler::notZero, dst);
8739    movzbl(dst, dst);
8740 }
8741 
8742 void MacroAssembler::alltrue(Register dst, uint masklen, KRegister src1, KRegister src2, KRegister kscratch) {
8743   if (masklen < 8) {
8744     knotbl(kscratch, src2);
8745     kortestbl(src1, kscratch);
8746     setb(Assembler::carrySet, dst);
8747     movzbl(dst, dst);
8748   } else {
8749     ktest(masklen, src1, src2);
8750     setb(Assembler::carrySet, dst);
8751     movzbl(dst, dst);
8752   }
8753 }
8754 
8755 void MacroAssembler::kortest(uint masklen, KRegister src1, KRegister src2) {
8756   switch(masklen) {
8757     case 8:
8758        kortestbl(src1, src2);
8759        break;
8760     case 16:
8761        kortestwl(src1, src2);
8762        break;
8763     case 32:
8764        kortestdl(src1, src2);
8765        break;
8766     case 64:
8767        kortestql(src1, src2);
8768        break;
8769     default:
8770       fatal("Unexpected mask length %d", masklen);
8771       break;
8772   }
8773 }
8774 
8775 
8776 void MacroAssembler::ktest(uint masklen, KRegister src1, KRegister src2) {
8777   switch(masklen)  {
8778     case 8:
8779        ktestbl(src1, src2);
8780        break;
8781     case 16:
8782        ktestwl(src1, src2);
8783        break;
8784     case 32:
8785        ktestdl(src1, src2);
8786        break;
8787     case 64:
8788        ktestql(src1, src2);
8789        break;
8790     default:
8791       fatal("Unexpected mask length %d", masklen);
8792       break;
8793   }
8794 }
8795 
8796 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8797   switch(type) {
8798     case T_INT:
8799       evprold(dst, mask, src, shift, merge, vlen_enc); break;
8800     case T_LONG:
8801       evprolq(dst, mask, src, shift, merge, vlen_enc); break;
8802     default:
8803       fatal("Unexpected type argument %s", type2name(type)); break;
8804       break;
8805   }
8806 }
8807 
8808 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src, int shift, bool merge, int vlen_enc) {
8809   switch(type) {
8810     case T_INT:
8811       evprord(dst, mask, src, shift, merge, vlen_enc); break;
8812     case T_LONG:
8813       evprorq(dst, mask, src, shift, merge, vlen_enc); break;
8814     default:
8815       fatal("Unexpected type argument %s", type2name(type)); break;
8816   }
8817 }
8818 
8819 void MacroAssembler::evrold(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8820   switch(type) {
8821     case T_INT:
8822       evprolvd(dst, mask, src1, src2, merge, vlen_enc); break;
8823     case T_LONG:
8824       evprolvq(dst, mask, src1, src2, merge, vlen_enc); break;
8825     default:
8826       fatal("Unexpected type argument %s", type2name(type)); break;
8827   }
8828 }
8829 
8830 void MacroAssembler::evrord(BasicType type, XMMRegister dst, KRegister mask, XMMRegister src1, XMMRegister src2, bool merge, int vlen_enc) {
8831   switch(type) {
8832     case T_INT:
8833       evprorvd(dst, mask, src1, src2, merge, vlen_enc); break;
8834     case T_LONG:
8835       evprorvq(dst, mask, src1, src2, merge, vlen_enc); break;
8836     default:
8837       fatal("Unexpected type argument %s", type2name(type)); break;
8838   }
8839 }
8840 #if COMPILER2_OR_JVMCI
8841 
8842 void MacroAssembler::fill_masked(BasicType bt, Address dst, XMMRegister xmm, KRegister mask,
8843                                  Register length, Register temp, int vec_enc) {
8844   // Computing mask for predicated vector store.
8845   movptr(temp, -1);
8846   bzhiq(temp, temp, length);
8847   kmov(mask, temp);
8848   evmovdqu(bt, mask, dst, xmm, vec_enc);
8849 }
8850 
8851 // Set memory operation for length "less than" 64 bytes.
8852 void MacroAssembler::fill64_masked(uint shift, Register dst, int disp,
8853                                        XMMRegister xmm, KRegister mask, Register length,
8854                                        Register temp, bool use64byteVector) {
8855   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8856   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8857   if (!use64byteVector) {
8858     fill32(dst, disp, xmm);
8859     subptr(length, 32 >> shift);
8860     fill32_masked(shift, dst, disp + 32, xmm, mask, length, temp);
8861   } else {
8862     assert(MaxVectorSize == 64, "vector length != 64");
8863     fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_512bit);
8864   }
8865 }
8866 
8867 
8868 void MacroAssembler::fill32_masked(uint shift, Register dst, int disp,
8869                                        XMMRegister xmm, KRegister mask, Register length,
8870                                        Register temp) {
8871   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8872   BasicType type[] = { T_BYTE, T_SHORT, T_INT, T_LONG};
8873   fill_masked(type[shift], Address(dst, disp), xmm, mask, length, temp, Assembler::AVX_256bit);
8874 }
8875 
8876 
8877 void MacroAssembler::fill32(Register dst, int disp, XMMRegister xmm) {
8878   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8879   vmovdqu(Address(dst, disp), xmm);
8880 }
8881 
8882 void MacroAssembler::fill64(Register dst, int disp, XMMRegister xmm, bool use64byteVector) {
8883   assert(MaxVectorSize >= 32, "vector length should be >= 32");
8884   BasicType type[] = {T_BYTE,  T_SHORT,  T_INT,   T_LONG};
8885   if (!use64byteVector) {
8886     fill32(dst, disp, xmm);
8887     fill32(dst, disp + 32, xmm);
8888   } else {
8889     evmovdquq(Address(dst, disp), xmm, Assembler::AVX_512bit);
8890   }
8891 }
8892 
8893 #ifdef _LP64
8894 void MacroAssembler::generate_fill_avx3(BasicType type, Register to, Register value,
8895                                         Register count, Register rtmp, XMMRegister xtmp) {
8896   Label L_exit;
8897   Label L_fill_start;
8898   Label L_fill_64_bytes;
8899   Label L_fill_96_bytes;
8900   Label L_fill_128_bytes;
8901   Label L_fill_128_bytes_loop;
8902   Label L_fill_128_loop_header;
8903   Label L_fill_128_bytes_loop_header;
8904   Label L_fill_128_bytes_loop_pre_header;
8905   Label L_fill_zmm_sequence;
8906 
8907   int shift = -1;
8908   int avx3threshold = VM_Version::avx3_threshold();
8909   switch(type) {
8910     case T_BYTE:  shift = 0;
8911       break;
8912     case T_SHORT: shift = 1;
8913       break;
8914     case T_INT:   shift = 2;
8915       break;
8916     /* Uncomment when LONG fill stubs are supported.
8917     case T_LONG:  shift = 3;
8918       break;
8919     */
8920     default:
8921       fatal("Unhandled type: %s\n", type2name(type));
8922   }
8923 
8924   if ((avx3threshold != 0)  || (MaxVectorSize == 32)) {
8925 
8926     if (MaxVectorSize == 64) {
8927       cmpq(count, avx3threshold >> shift);
8928       jcc(Assembler::greater, L_fill_zmm_sequence);
8929     }
8930 
8931     evpbroadcast(type, xtmp, value, Assembler::AVX_256bit);
8932 
8933     bind(L_fill_start);
8934 
8935     cmpq(count, 32 >> shift);
8936     jccb(Assembler::greater, L_fill_64_bytes);
8937     fill32_masked(shift, to, 0, xtmp, k2, count, rtmp);
8938     jmp(L_exit);
8939 
8940     bind(L_fill_64_bytes);
8941     cmpq(count, 64 >> shift);
8942     jccb(Assembler::greater, L_fill_96_bytes);
8943     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp);
8944     jmp(L_exit);
8945 
8946     bind(L_fill_96_bytes);
8947     cmpq(count, 96 >> shift);
8948     jccb(Assembler::greater, L_fill_128_bytes);
8949     fill64(to, 0, xtmp);
8950     subq(count, 64 >> shift);
8951     fill32_masked(shift, to, 64, xtmp, k2, count, rtmp);
8952     jmp(L_exit);
8953 
8954     bind(L_fill_128_bytes);
8955     cmpq(count, 128 >> shift);
8956     jccb(Assembler::greater, L_fill_128_bytes_loop_pre_header);
8957     fill64(to, 0, xtmp);
8958     fill32(to, 64, xtmp);
8959     subq(count, 96 >> shift);
8960     fill32_masked(shift, to, 96, xtmp, k2, count, rtmp);
8961     jmp(L_exit);
8962 
8963     bind(L_fill_128_bytes_loop_pre_header);
8964     {
8965       mov(rtmp, to);
8966       andq(rtmp, 31);
8967       jccb(Assembler::zero, L_fill_128_bytes_loop_header);
8968       negq(rtmp);
8969       addq(rtmp, 32);
8970       mov64(r8, -1L);
8971       bzhiq(r8, r8, rtmp);
8972       kmovql(k2, r8);
8973       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_256bit);
8974       addq(to, rtmp);
8975       shrq(rtmp, shift);
8976       subq(count, rtmp);
8977     }
8978 
8979     cmpq(count, 128 >> shift);
8980     jcc(Assembler::less, L_fill_start);
8981 
8982     bind(L_fill_128_bytes_loop_header);
8983     subq(count, 128 >> shift);
8984 
8985     align32();
8986     bind(L_fill_128_bytes_loop);
8987       fill64(to, 0, xtmp);
8988       fill64(to, 64, xtmp);
8989       addq(to, 128);
8990       subq(count, 128 >> shift);
8991       jccb(Assembler::greaterEqual, L_fill_128_bytes_loop);
8992 
8993     addq(count, 128 >> shift);
8994     jcc(Assembler::zero, L_exit);
8995     jmp(L_fill_start);
8996   }
8997 
8998   if (MaxVectorSize == 64) {
8999     // Sequence using 64 byte ZMM register.
9000     Label L_fill_128_bytes_zmm;
9001     Label L_fill_192_bytes_zmm;
9002     Label L_fill_192_bytes_loop_zmm;
9003     Label L_fill_192_bytes_loop_header_zmm;
9004     Label L_fill_192_bytes_loop_pre_header_zmm;
9005     Label L_fill_start_zmm_sequence;
9006 
9007     bind(L_fill_zmm_sequence);
9008     evpbroadcast(type, xtmp, value, Assembler::AVX_512bit);
9009 
9010     bind(L_fill_start_zmm_sequence);
9011     cmpq(count, 64 >> shift);
9012     jccb(Assembler::greater, L_fill_128_bytes_zmm);
9013     fill64_masked(shift, to, 0, xtmp, k2, count, rtmp, true);
9014     jmp(L_exit);
9015 
9016     bind(L_fill_128_bytes_zmm);
9017     cmpq(count, 128 >> shift);
9018     jccb(Assembler::greater, L_fill_192_bytes_zmm);
9019     fill64(to, 0, xtmp, true);
9020     subq(count, 64 >> shift);
9021     fill64_masked(shift, to, 64, xtmp, k2, count, rtmp, true);
9022     jmp(L_exit);
9023 
9024     bind(L_fill_192_bytes_zmm);
9025     cmpq(count, 192 >> shift);
9026     jccb(Assembler::greater, L_fill_192_bytes_loop_pre_header_zmm);
9027     fill64(to, 0, xtmp, true);
9028     fill64(to, 64, xtmp, true);
9029     subq(count, 128 >> shift);
9030     fill64_masked(shift, to, 128, xtmp, k2, count, rtmp, true);
9031     jmp(L_exit);
9032 
9033     bind(L_fill_192_bytes_loop_pre_header_zmm);
9034     {
9035       movq(rtmp, to);
9036       andq(rtmp, 63);
9037       jccb(Assembler::zero, L_fill_192_bytes_loop_header_zmm);
9038       negq(rtmp);
9039       addq(rtmp, 64);
9040       mov64(r8, -1L);
9041       bzhiq(r8, r8, rtmp);
9042       kmovql(k2, r8);
9043       evmovdqu(T_BYTE, k2, Address(to, 0), xtmp, Assembler::AVX_512bit);
9044       addq(to, rtmp);
9045       shrq(rtmp, shift);
9046       subq(count, rtmp);
9047     }
9048 
9049     cmpq(count, 192 >> shift);
9050     jcc(Assembler::less, L_fill_start_zmm_sequence);
9051 
9052     bind(L_fill_192_bytes_loop_header_zmm);
9053     subq(count, 192 >> shift);
9054 
9055     align32();
9056     bind(L_fill_192_bytes_loop_zmm);
9057       fill64(to, 0, xtmp, true);
9058       fill64(to, 64, xtmp, true);
9059       fill64(to, 128, xtmp, true);
9060       addq(to, 192);
9061       subq(count, 192 >> shift);
9062       jccb(Assembler::greaterEqual, L_fill_192_bytes_loop_zmm);
9063 
9064     addq(count, 192 >> shift);
9065     jcc(Assembler::zero, L_exit);
9066     jmp(L_fill_start_zmm_sequence);
9067   }
9068   bind(L_exit);
9069 }
9070 #endif
9071 #endif //COMPILER2_OR_JVMCI
9072 
9073 
9074 #ifdef _LP64
9075 void MacroAssembler::convert_f2i(Register dst, XMMRegister src) {
9076   Label done;
9077   cvttss2sil(dst, src);
9078   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9079   cmpl(dst, 0x80000000); // float_sign_flip
9080   jccb(Assembler::notEqual, done);
9081   subptr(rsp, 8);
9082   movflt(Address(rsp, 0), src);
9083   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
9084   pop(dst);
9085   bind(done);
9086 }
9087 
9088 void MacroAssembler::convert_d2i(Register dst, XMMRegister src) {
9089   Label done;
9090   cvttsd2sil(dst, src);
9091   // Conversion instructions do not match JLS for overflow, underflow and NaN -> fixup in stub
9092   cmpl(dst, 0x80000000); // float_sign_flip
9093   jccb(Assembler::notEqual, done);
9094   subptr(rsp, 8);
9095   movdbl(Address(rsp, 0), src);
9096   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
9097   pop(dst);
9098   bind(done);
9099 }
9100 
9101 void MacroAssembler::convert_f2l(Register dst, XMMRegister src) {
9102   Label done;
9103   cvttss2siq(dst, src);
9104   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9105   jccb(Assembler::notEqual, done);
9106   subptr(rsp, 8);
9107   movflt(Address(rsp, 0), src);
9108   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
9109   pop(dst);
9110   bind(done);
9111 }
9112 
9113 void MacroAssembler::round_float(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9114   // Following code is line by line assembly translation rounding algorithm.
9115   // Please refer to java.lang.Math.round(float) algorithm for details.
9116   const int32_t FloatConsts_EXP_BIT_MASK = 0x7F800000;
9117   const int32_t FloatConsts_SIGNIFICAND_WIDTH = 24;
9118   const int32_t FloatConsts_EXP_BIAS = 127;
9119   const int32_t FloatConsts_SIGNIF_BIT_MASK = 0x007FFFFF;
9120   const int32_t MINUS_32 = 0xFFFFFFE0;
9121   Label L_special_case, L_block1, L_exit;
9122   movl(rtmp, FloatConsts_EXP_BIT_MASK);
9123   movdl(dst, src);
9124   andl(dst, rtmp);
9125   sarl(dst, FloatConsts_SIGNIFICAND_WIDTH - 1);
9126   movl(rtmp, FloatConsts_SIGNIFICAND_WIDTH - 2 + FloatConsts_EXP_BIAS);
9127   subl(rtmp, dst);
9128   movl(rcx, rtmp);
9129   movl(dst, MINUS_32);
9130   testl(rtmp, dst);
9131   jccb(Assembler::notEqual, L_special_case);
9132   movdl(dst, src);
9133   andl(dst, FloatConsts_SIGNIF_BIT_MASK);
9134   orl(dst, FloatConsts_SIGNIF_BIT_MASK + 1);
9135   movdl(rtmp, src);
9136   testl(rtmp, rtmp);
9137   jccb(Assembler::greaterEqual, L_block1);
9138   negl(dst);
9139   bind(L_block1);
9140   sarl(dst);
9141   addl(dst, 0x1);
9142   sarl(dst, 0x1);
9143   jmp(L_exit);
9144   bind(L_special_case);
9145   convert_f2i(dst, src);
9146   bind(L_exit);
9147 }
9148 
9149 void MacroAssembler::round_double(Register dst, XMMRegister src, Register rtmp, Register rcx) {
9150   // Following code is line by line assembly translation rounding algorithm.
9151   // Please refer to java.lang.Math.round(double) algorithm for details.
9152   const int64_t DoubleConsts_EXP_BIT_MASK = 0x7FF0000000000000L;
9153   const int64_t DoubleConsts_SIGNIFICAND_WIDTH = 53;
9154   const int64_t DoubleConsts_EXP_BIAS = 1023;
9155   const int64_t DoubleConsts_SIGNIF_BIT_MASK = 0x000FFFFFFFFFFFFFL;
9156   const int64_t MINUS_64 = 0xFFFFFFFFFFFFFFC0L;
9157   Label L_special_case, L_block1, L_exit;
9158   mov64(rtmp, DoubleConsts_EXP_BIT_MASK);
9159   movq(dst, src);
9160   andq(dst, rtmp);
9161   sarq(dst, DoubleConsts_SIGNIFICAND_WIDTH - 1);
9162   mov64(rtmp, DoubleConsts_SIGNIFICAND_WIDTH - 2 + DoubleConsts_EXP_BIAS);
9163   subq(rtmp, dst);
9164   movq(rcx, rtmp);
9165   mov64(dst, MINUS_64);
9166   testq(rtmp, dst);
9167   jccb(Assembler::notEqual, L_special_case);
9168   movq(dst, src);
9169   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK);
9170   andq(dst, rtmp);
9171   mov64(rtmp, DoubleConsts_SIGNIF_BIT_MASK + 1);
9172   orq(dst, rtmp);
9173   movq(rtmp, src);
9174   testq(rtmp, rtmp);
9175   jccb(Assembler::greaterEqual, L_block1);
9176   negq(dst);
9177   bind(L_block1);
9178   sarq(dst);
9179   addq(dst, 0x1);
9180   sarq(dst, 0x1);
9181   jmp(L_exit);
9182   bind(L_special_case);
9183   convert_d2l(dst, src);
9184   bind(L_exit);
9185 }
9186 
9187 void MacroAssembler::convert_d2l(Register dst, XMMRegister src) {
9188   Label done;
9189   cvttsd2siq(dst, src);
9190   cmp64(dst, ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
9191   jccb(Assembler::notEqual, done);
9192   subptr(rsp, 8);
9193   movdbl(Address(rsp, 0), src);
9194   call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
9195   pop(dst);
9196   bind(done);
9197 }
9198 
9199 void MacroAssembler::cache_wb(Address line)
9200 {
9201   // 64 bit cpus always support clflush
9202   assert(VM_Version::supports_clflush(), "clflush should be available");
9203   bool optimized = VM_Version::supports_clflushopt();
9204   bool no_evict = VM_Version::supports_clwb();
9205 
9206   // prefer clwb (writeback without evict) otherwise
9207   // prefer clflushopt (potentially parallel writeback with evict)
9208   // otherwise fallback on clflush (serial writeback with evict)
9209 
9210   if (optimized) {
9211     if (no_evict) {
9212       clwb(line);
9213     } else {
9214       clflushopt(line);
9215     }
9216   } else {
9217     // no need for fence when using CLFLUSH
9218     clflush(line);
9219   }
9220 }
9221 
9222 void MacroAssembler::cache_wbsync(bool is_pre)
9223 {
9224   assert(VM_Version::supports_clflush(), "clflush should be available");
9225   bool optimized = VM_Version::supports_clflushopt();
9226   bool no_evict = VM_Version::supports_clwb();
9227 
9228   // pick the correct implementation
9229 
9230   if (!is_pre && (optimized || no_evict)) {
9231     // need an sfence for post flush when using clflushopt or clwb
9232     // otherwise no no need for any synchroniaztion
9233 
9234     sfence();
9235   }
9236 }
9237 
9238 #endif // _LP64
9239 
9240 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) {
9241   switch (cond) {
9242     // Note some conditions are synonyms for others
9243     case Assembler::zero:         return Assembler::notZero;
9244     case Assembler::notZero:      return Assembler::zero;
9245     case Assembler::less:         return Assembler::greaterEqual;
9246     case Assembler::lessEqual:    return Assembler::greater;
9247     case Assembler::greater:      return Assembler::lessEqual;
9248     case Assembler::greaterEqual: return Assembler::less;
9249     case Assembler::below:        return Assembler::aboveEqual;
9250     case Assembler::belowEqual:   return Assembler::above;
9251     case Assembler::above:        return Assembler::belowEqual;
9252     case Assembler::aboveEqual:   return Assembler::below;
9253     case Assembler::overflow:     return Assembler::noOverflow;
9254     case Assembler::noOverflow:   return Assembler::overflow;
9255     case Assembler::negative:     return Assembler::positive;
9256     case Assembler::positive:     return Assembler::negative;
9257     case Assembler::parity:       return Assembler::noParity;
9258     case Assembler::noParity:     return Assembler::parity;
9259   }
9260   ShouldNotReachHere(); return Assembler::overflow;
9261 }
9262 
9263 SkipIfEqual::SkipIfEqual(
9264     MacroAssembler* masm, const bool* flag_addr, bool value) {
9265   _masm = masm;
9266   _masm->cmp8(ExternalAddress((address)flag_addr), value);
9267   _masm->jcc(Assembler::equal, _label);
9268 }
9269 
9270 SkipIfEqual::~SkipIfEqual() {
9271   _masm->bind(_label);
9272 }
9273 
9274 // 32-bit Windows has its own fast-path implementation
9275 // of get_thread
9276 #if !defined(WIN32) || defined(_LP64)
9277 
9278 // This is simply a call to Thread::current()
9279 void MacroAssembler::get_thread(Register thread) {
9280   if (thread != rax) {
9281     push(rax);
9282   }
9283   LP64_ONLY(push(rdi);)
9284   LP64_ONLY(push(rsi);)
9285   push(rdx);
9286   push(rcx);
9287 #ifdef _LP64
9288   push(r8);
9289   push(r9);
9290   push(r10);
9291   push(r11);
9292 #endif
9293 
9294   MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0);
9295 
9296 #ifdef _LP64
9297   pop(r11);
9298   pop(r10);
9299   pop(r9);
9300   pop(r8);
9301 #endif
9302   pop(rcx);
9303   pop(rdx);
9304   LP64_ONLY(pop(rsi);)
9305   LP64_ONLY(pop(rdi);)
9306   if (thread != rax) {
9307     mov(thread, rax);
9308     pop(rax);
9309   }
9310 }
9311 
9312 
9313 #endif // !WIN32 || _LP64